Re: identcpu for 1-GByte pages

[Doug Hogan]

On Wed, Jul 02, 2014 at 10:36:25PM -0700, Matthew Dempsky wrote:
 According to the Intel 64 and IA-32 Architectures Software
 Developer's Manual, CPUID.8001H:EDX.Page1GB [bit 26] indicates
 whether 1-GByte pages are supported with IA-32e paging.
 
 I think the diff below adds support for identifying this feature in
 dmesg, but my X201s is seemingly to old to support it.

Works for me with the last snapshot:

OpenBSD 5.5-current (GENERIC.MP) #272: Sun Jul 13 20:46:20 MDT 2014
t...@amd64.openbsd.org:/usr/src/sys/arch/amd64/compile/GENERIC.MP
real mem = 17042100224 (16252MB)
avail mem = 16579661824 (15811MB)
mpath0 at root
scsibus0 at mpath0: 256 targets
mainbus0 at root
bios0 at mainbus0: SMBIOS rev. 2.7 @ 0xec120 (82 entries)
bios0: vendor American Megatrends Inc. version 1.1a date 01/03/2014
bios0: Supermicro X10SAE
acpi0 at bios0: rev 2
acpi0: sleep states S0 S1 S3 S4 S5
acpi0: tables DSDT FACP APIC FPDT LPIT SSDT SSDT SSDT SSDT MCFG HPET SSDT SSDT 
ASF! DMAR EINJ ERST HEST BERT
acpi0: wakeup devices PS2K(S3) PS2M(S3) PXSX(S4) RP01(S4) PXSX(S4) RP02(S4) 
PXSX(S4) RP03(S4) PXSX(S4) RP04(S4) PXSX(S4) RP05(S4) PXSX(S4) BR30(S4) 
RP06(S4) PXSX(S4) [...]
acpitimer0 at acpi0: 3579545 Hz, 24 bits
acpimadt0 at acpi0 addr 0xfee0: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: Intel(R) Xeon(R) CPU E3-1246 v3 @ 3.50GHz, 3500.44 MHz
cpu0: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,LONG,LAHF,ABM,PERF,ITSC,FSGSBASE,BMI1,HLE,AVX2,SMEP,BMI2,ERMS,INVPCID,RTM
cpu0: 256KB 64b/line 8-way L2 cache
cpu0: smt 0, core 0, package 0
mtrr: Pentium Pro MTRR support, 10 var ranges, 88 fixed ranges
cpu0: apic clock running at 100MHz
cpu0: mwait min=64, max=64, C-substates=0.2.1.2.4, IBE

identcpu for 1-GByte pages

[Matthew Dempsky]

According to the Intel 64 and IA-32 Architectures Software
Developer's Manual, CPUID.8001H:EDX.Page1GB [bit 26] indicates
whether 1-GByte pages are supported with IA-32e paging.

I think the diff below adds support for identifying this feature in
dmesg, but my X201s is seemingly to old to support it.

ok?

Index: amd64/include/specialreg.h
===
RCS file: /home/matthew/anoncvs/cvs/src/sys/arch/amd64/include/specialreg.h,v
retrieving revision 1.27
diff -w -u -p -r1.27 specialreg.h
--- amd64/include/specialreg.h  24 Aug 2013 04:26:16 -  1.27
+++ amd64/include/specialreg.h  3 Jul 2014 05:17:18 -
@@ -207,6 +207,7 @@
 #defineCPUID_NXE   0x0010  /* No-Execute Extension */
 #defineCPUID_MMXX  0x0040  /* AMD MMX Extensions */
 #defineCPUID_FFXSR 0x0200  /* fast FP/MMX save/restore */
+#defineCPUID_PAGE1GB   0x0400  /* 1-GByte pages */
 #defineCPUID_LONG  0x2000  /* long mode */
 #defineCPUID_3DNOW20x4000  /* 3DNow! Instruction Extension 
*/
 #defineCPUID_3DNOW 0x8000  /* 3DNow! Instructions */
Index: amd64/amd64/identcpu.c
===
RCS file: /home/matthew/anoncvs/cvs/src/sys/arch/amd64/amd64/identcpu.c,v
retrieving revision 1.52
diff -w -u -p -r1.52 identcpu.c
--- amd64/amd64/identcpu.c  19 Nov 2013 04:12:17 -  1.52
+++ amd64/amd64/identcpu.c  3 Jul 2014 05:19:54 -
@@ -96,6 +96,7 @@ const struct {
{ CPUID_NXE,NXE },
{ CPUID_MMXX,   MMXX },
{ CPUID_FFXSR,  FFXSR },
+   { CPUID_PAGE1GB,PAGE1GB },
{ CPUID_LONG,   LONG },
{ CPUID_3DNOW2, 3DNOW2 },
{ CPUID_3DNOW,  3DNOW }
Index: i386/include/specialreg.h
===
RCS file: /home/matthew/anoncvs/cvs/src/sys/arch/i386/include/specialreg.h,v
retrieving revision 1.46
diff -w -u -p -r1.46 specialreg.h
--- i386/include/specialreg.h   24 Aug 2013 04:26:16 -  1.46
+++ i386/include/specialreg.h   3 Jul 2014 05:20:23 -
@@ -206,6 +206,7 @@
 #defineCPUID_NXE   0x0010  /* No-Execute Extension */
 #defineCPUID_MMXX  0x0040  /* AMD MMX Extensions */
 #defineCPUID_FFXSR 0x0200  /* fast FP/MMX save/restore */
+#defineCPUID_PAGE1GB   0x0400  /* 1-GByte pages */
 #defineCPUID_LONG  0x2000  /* long mode */
 #defineCPUID_3DNOW20x4000  /* 3DNow! Instruction Extension 
*/
 #defineCPUID_3DNOW 0x8000  /* 3DNow! Instructions */
Index: i386/i386/machdep.c
===
RCS file: /home/matthew/anoncvs/cvs/src/sys/arch/i386/i386/machdep.c,v
retrieving revision 1.539
diff -w -u -p -r1.539 machdep.c
--- i386/i386/machdep.c 15 Jun 2014 11:43:24 -  1.539
+++ i386/i386/machdep.c 3 Jul 2014 05:20:56 -
@@ -1001,6 +1001,7 @@ const struct cpu_cpuid_feature i386_ecpu
{ CPUID_NXE,NXE },
{ CPUID_MMXX,   MMXX },
{ CPUID_FFXSR,  FFXSR },
+   { CPUID_PAGE1GB,PAGE1GB },
{ CPUID_LONG,   LONG },
{ CPUID_3DNOW2, 3DNOW2 },
{ CPUID_3DNOW,  3DNOW }