Re: initial Intel Elkhart Lake Ethernet support / dwqe(4) at pci
On Wed, Oct 11, 2023 at 10:27:24AM +0200, Stefan Sperling wrote: > On Tue, Oct 10, 2023 at 09:06:59PM +0200, Mark Kettenis wrote: > > > OK for your diff. Please put it in and I'll rebase on top. > > > > done > > Thanks. Here is a rebased version. Re-tested with the same results. not all the includes are needed Index: if_dwqe_pci.c === RCS file: /cvs/src/sys/dev/pci/if_dwqe_pci.c,v retrieving revision 1.1 diff -u -p -r1.1 if_dwqe_pci.c --- if_dwqe_pci.c 11 Oct 2023 12:52:01 - 1.1 +++ if_dwqe_pci.c 12 Oct 2023 04:34:57 - @@ -21,33 +21,19 @@ */ #include -#include #include #include -#include -#include -#include -#include -#include -#include -#include -#include #include #include #include -#if NBPFILTER > 0 -#include -#endif #include -#include #include #include #include -#include #include #include
Re: initial Intel Elkhart Lake Ethernet support / dwqe(4) at pci
On Wed, Oct 11, 2023 at 02:05:52PM +0200, Stefan Sperling wrote:
> Anyway, here is an eephy(4) diff to enable/disable delays on the 88E1512.
That diff wasn't quite right. The register offset should be 0x21,
and Linux configures delays every time after link auto-negotiation.
I am still unsure if this change really makes sense, and I cannot
easily verify it as it makes no apparent difference to dwqe(4).
Maybe this change should wait until we really need it?
---
add support for Tx/Rx delay settings on 881E512 to eephy(4)
diff 0292379527460b61efdf8c49732814a6faa13cc0
1b3f658f3c2db79931a12fb835f5c11f8e7b170c
commit - 0292379527460b61efdf8c49732814a6faa13cc0
commit + 1b3f658f3c2db79931a12fb835f5c11f8e7b170c
blob - e33abe384313e9301fb6c3292c05ce577ffc890e
blob + c4e39265405869cc631da7120e6c8b501c59aa15
--- sys/dev/mii/eephy.c
+++ sys/dev/mii/eephy.c
@@ -303,6 +303,11 @@ eephy_service(struct mii_softc *sc, struct mii_data *m
{
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
int bmcr;
+ /*
+* If autonegotiation is not enabled, we need a
+* software reset for the settings to take effect.
+*/
+ int sw_reset = (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO);
if ((sc->mii_dev.dv_flags & DVF_ACTIVE) == 0)
return (ENXIO);
@@ -335,11 +340,24 @@ eephy_service(struct mii_softc *sc, struct mii_data *m
mii_phy_setmedia(sc);
- /*
-* If autonegotiation is not enabled, we need a
-* software reset for the settings to take effect.
-*/
- if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
+ if (sc->mii_model == MII_MODEL_MARVELL_E1512 &&
+ (sc->mii_flags & MIIF_SETDELAY)) {
+ int page, reg;
+ printf("%s: configuring Rx/Tx delay\n", __func__);
+ page = PHY_READ(sc, E1000_EADR);
+ PHY_WRITE(sc, E1000_EADR, 2);
+ reg = PHY_READ(sc, E1000_MSCR2);
+ reg &= ~E1000_MSCR2_DELAY_MASK;
+ if (sc->mii_flags & MIIF_RXID)
+ reg |= E1000_MSCR2_RXDELAY;
+ if (sc->mii_flags & MIIF_TXID)
+ reg |= E1000_MSCR2_TXDELAY;
+ PHY_WRITE(sc, E1000_MSCR2, reg);
+ PHY_WRITE(sc, E1000_EADR, page);
+ sw_reset = 1;
+ }
+
+ if (sw_reset) {
bmcr = PHY_READ(sc, E1000_CR);
PHY_WRITE(sc, E1000_CR, bmcr | E1000_CR_RESET);
}
blob - 59c6c5678987cecde898f44c77b6046a9b7b672f
blob + 41ec501cca74c9a719213c9db1c1bc23ffc31047
--- sys/dev/mii/eephyreg.h
+++ sys/dev/mii/eephyreg.h
@@ -331,3 +331,10 @@
#define E1000_GCR1_RESET 0x8000
#define E1000_GCR1_MODE_MASK 0x0007
#define E1000_GCR1_MODE_SGMII 0x0001
+
+/* The following register is found only on the 88E151x Alaska PHY */
+/* Page 2 */
+#define E1000_MSCR20x21/* MAC-Specific Control Register 2 */
+#define E1000_MSCR2_RXDELAY0x20
+#define E1000_MSCR2_TXDELAY0x10
+#define E1000_MSCR2_DELAY_MASK 0x30
Re: initial Intel Elkhart Lake Ethernet support / dwqe(4) at pci
> Date: Wed, 11 Oct 2023 10:27:24 +0200
> From: Stefan Sperling
>
> On Tue, Oct 10, 2023 at 09:06:59PM +0200, Mark Kettenis wrote:
> > > OK for your diff. Please put it in and I'll rebase on top.
> >
> > done
>
> Thanks. Here is a rebased version. Re-tested with the same results.
ok kettenis@
> diff refs/heads/master refs/heads/dwqe
> commit - 8af2f04850cda85ea291bfaddc0e4d58c40f2935
> commit + 539534a1060039a11b4c3faca5385beb016c34de
> blob - c6094ca5a57d964784f56124b8d923393b1abb66
> blob + cf64e8ff2018fb0ee1e7e59b29b2bc2dd281aa99
> --- sys/arch/amd64/conf/GENERIC
> +++ sys/arch/amd64/conf/GENERIC
> @@ -556,6 +556,7 @@ lii* at pci? # Attansic L2
> Ethernet
> jme* at pci? # JMicron JMC250/JMC260 Ethernet
> bnxt*at pci? # Broadcom BCM573xx, BCM574xx
> ixl* at pci? # Intel Ethernet 700 Series
> +dwqe*at pci? # Intel Elkhart Lake Ethernet
> mcx* at pci? # Mellanox ConnectX-4
> iavf*at pci? # Intel Ethernet Adaptive VF
> aq* at pci? # Aquantia aQtion Ethernet
> blob - 7d260ef46054d6566ef2f81f6cf96dc8de5a5893
> blob + 3d01c4f2665c86b8fe4cbb18379afaccf8ca65ac
> --- sys/dev/ic/dwqe.c
> +++ sys/dev/ic/dwqe.c
> @@ -705,7 +705,7 @@ dwqe_up(struct dwqe_softc *sc)
> {
> struct ifnet *ifp = >sc_ac.ac_if;
> struct dwqe_buf *txb, *rxb;
> - uint32_t mode, reg, tqs, rqs;
> + uint32_t mode, reg, fifosz, tqs, rqs;
> int i;
>
> /* Allocate Tx descriptor ring. */
> @@ -793,9 +793,21 @@ dwqe_up(struct dwqe_softc *sc)
> mode |= GMAC_MTL_CHAN_RX_OP_MODE_RSF;
> }
> mode &= ~GMAC_MTL_CHAN_RX_OP_MODE_RQS_MASK;
> - rqs = (128 << GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(sc->sc_hw_feature[1]) /
> - 256) - 1;
> - mode |= rqs << GMAC_MTL_CHAN_RX_OP_MODE_RQS_SHIFT;
> + if (sc->sc_rxfifo_size)
> + fifosz = sc->sc_rxfifo_size;
> + else
> + fifosz = (128 <<
> + GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(sc->sc_hw_feature[1]));
> + rqs = fifosz / 256 - 1;
> + mode |= (rqs << GMAC_MTL_CHAN_RX_OP_MODE_RQS_SHIFT) &
> +GMAC_MTL_CHAN_RX_OP_MODE_RQS_MASK;
> + if (fifosz >= 4096) {
> + mode |= GMAC_MTL_CHAN_RX_OP_MODE_EHFC;
> + mode &= ~GMAC_MTL_CHAN_RX_OP_MODE_RFD_MASK;
> + mode |= 0x3 << GMAC_MTL_CHAN_RX_OP_MODE_RFD_SHIFT;
> + mode &= ~GMAC_MTL_CHAN_RX_OP_MODE_RFA_MASK;
> + mode |= 0x1 << GMAC_MTL_CHAN_RX_OP_MODE_RFA_SHIFT;
> + }
> dwqe_write(sc, GMAC_MTL_CHAN_RX_OP_MODE(0), mode);
>
> mode = dwqe_read(sc, GMAC_MTL_CHAN_TX_OP_MODE(0));
> @@ -809,9 +821,14 @@ dwqe_up(struct dwqe_softc *sc)
> mode &= ~GMAC_MTL_CHAN_TX_OP_MODE_TXQEN_MASK;
> mode |= GMAC_MTL_CHAN_TX_OP_MODE_TXQEN;
> mode &= ~GMAC_MTL_CHAN_TX_OP_MODE_TQS_MASK;
> - tqs = (128 << GMAC_MAC_HW_FEATURE1_TXFIFOSIZE(sc->sc_hw_feature[1]) /
> - 256) - 1;
> - mode |= tqs << GMAC_MTL_CHAN_TX_OP_MODE_TQS_SHIFT;
> + if (sc->sc_txfifo_size)
> + fifosz = sc->sc_txfifo_size;
> + else
> + fifosz = (128 <<
> + GMAC_MAC_HW_FEATURE1_TXFIFOSIZE(sc->sc_hw_feature[1]));
> + tqs = (fifosz / 256) - 1;
> + mode |= (tqs << GMAC_MTL_CHAN_TX_OP_MODE_TQS_SHIFT) &
> + GMAC_MTL_CHAN_TX_OP_MODE_TQS_MASK;
> dwqe_write(sc, GMAC_MTL_CHAN_TX_OP_MODE(0), mode);
>
> reg = dwqe_read(sc, GMAC_QX_TX_FLOW_CTRL(0));
> blob - 68d698a50beef00f002d986d7d24f8984c3efe0c
> blob + d5ba09b005c469eec48b17dcbda6c76f277380e7
> --- sys/dev/ic/dwqevar.h
> +++ sys/dev/ic/dwqevar.h
> @@ -97,6 +97,8 @@ struct dwqe_softc {
> int sc_pbl;
> int sc_txpbl;
> int sc_rxpbl;
> + int sc_txfifo_size;
> + int sc_rxfifo_size;
> int sc_axi_config;
> int sc_lpi_en;
> int sc_xit_frm;
> blob - 101ed502e76987c27878712b4921cc49f7eb7f59
> blob + 6868eb3591995804dbc332308c9d9629f73c269f
> --- sys/dev/pci/files.pci
> +++ sys/dev/pci/files.pci
> @@ -363,6 +363,10 @@ device ixl: ether, ifnet, ifmedia, intrmap, stoeplitz
> attach ixl at pci
> file dev/pci/if_ixl.cixl
>
> +# Intel Elkhart Lake Ethernet
> +attach dwqe at pci with dwqe_pci
> +file dev/pci/if_dwqe_pci.c dwqe_pci
> +
> # Neterion Xframe 10 Gigabit ethernet
> device xge: ether, ifnet, ifmedia
> attach xge at pci
> blob - /dev/null
> blob + d157f116c025d882f1ec8df84b4c3deca3ca340f (mode 644)
> --- /dev/null
> +++ sys/dev/pci/if_dwqe_pci.c
> @@ -0,0 +1,154 @@
> +/* $OpenBSD$ */
> +
> +/*
> + * Copyright (c) 2023 Stefan Sperling
> + *
> + * Permission to use, copy, modify, and distribute this software for
Re: initial Intel Elkhart Lake Ethernet support / dwqe(4) at pci
On Wed, Oct 11, 2023 at 10:27:24AM +0200, Stefan Sperling wrote:
> On Tue, Oct 10, 2023 at 09:06:59PM +0200, Mark Kettenis wrote:
> > > OK for your diff. Please put it in and I'll rebase on top.
> >
> > done
>
> Thanks. Here is a rebased version. Re-tested with the same results.
Turns out I made a mistake when setting up the PHY type because I
misunderstood the Linux driver code.
The phy mode needs to be: sc->sc_phy_mode = DWQE_PHY_MODE_RGMII_ID;
Which means Tx/Rx delays must be enabled (which they are by default).
Anyway, here is an eephy(4) diff to enable/disable delays on the 88E1512.
We might need this eventually in any case.
See Table 110 in the Alaska 88E1510/88E1518/88E1512/88E1514 datasheet
from January 6 2022, page 106/107.
diff /usr/src
commit - 08f2ab0930d2d7a77214a2b9b2623266a5f343ac
path + /usr/src
blob - e33abe384313e9301fb6c3292c05ce577ffc890e
file + sys/dev/mii/eephy.c
--- sys/dev/mii/eephy.c
+++ sys/dev/mii/eephy.c
@@ -200,6 +200,20 @@ eephy_attach(struct device *parent, struct device *sel
PHY_WRITE(sc, E1000_GCR1, reg);
PHY_WRITE(sc, E1000_EADR, page);
}
+
+ if (sc->mii_model == MII_MODEL_MARVELL_E1512 &&
+ (sc->mii_flags & MIIF_SETDELAY)) {
+ page = PHY_READ(sc, E1000_EADR);
+ PHY_WRITE(sc, E1000_EADR, 2);
+ reg = PHY_READ(sc, E1000_MSCR2);
+ reg &= ~E1000_MSCR2_DELAY_MASK;
+ if (sc->mii_flags & MIIF_RXID)
+ reg |= E1000_MSCR2_RXDELAY;
+ if (sc->mii_flags & MIIF_TXID)
+ reg |= E1000_MSCR2_TXDELAY;
+ PHY_WRITE(sc, E1000_MSCR2, reg);
+ PHY_WRITE(sc, E1000_EADR, page);
+ }
PHY_RESET(sc);
blob - 59c6c5678987cecde898f44c77b6046a9b7b672f
file + sys/dev/mii/eephyreg.h
--- sys/dev/mii/eephyreg.h
+++ sys/dev/mii/eephyreg.h
@@ -331,3 +331,10 @@
#define E1000_GCR1_RESET 0x8000
#define E1000_GCR1_MODE_MASK 0x0007
#define E1000_GCR1_MODE_SGMII 0x0001
+
+/* The following register is found only on the 88E151x Alaska PHY */
+/* Page 2 */
+#define E1000_MSCR20x15/* MAC-Specific Control Register 2 */
+#define E1000_MSCR2_RXDELAY0x20
+#define E1000_MSCR2_TXDELAY0x10
+#define E1000_MSCR2_DELAY_MASK 0x30
Re: initial Intel Elkhart Lake Ethernet support / dwqe(4) at pci
On Tue, Oct 10, 2023 at 09:06:59PM +0200, Mark Kettenis wrote:
> > OK for your diff. Please put it in and I'll rebase on top.
>
> done
Thanks. Here is a rebased version. Re-tested with the same results.
diff refs/heads/master refs/heads/dwqe
commit - 8af2f04850cda85ea291bfaddc0e4d58c40f2935
commit + 539534a1060039a11b4c3faca5385beb016c34de
blob - c6094ca5a57d964784f56124b8d923393b1abb66
blob + cf64e8ff2018fb0ee1e7e59b29b2bc2dd281aa99
--- sys/arch/amd64/conf/GENERIC
+++ sys/arch/amd64/conf/GENERIC
@@ -556,6 +556,7 @@ lii*at pci? # Attansic L2
Ethernet
jme* at pci? # JMicron JMC250/JMC260 Ethernet
bnxt* at pci? # Broadcom BCM573xx, BCM574xx
ixl* at pci? # Intel Ethernet 700 Series
+dwqe* at pci? # Intel Elkhart Lake Ethernet
mcx* at pci? # Mellanox ConnectX-4
iavf* at pci? # Intel Ethernet Adaptive VF
aq*at pci? # Aquantia aQtion Ethernet
blob - 7d260ef46054d6566ef2f81f6cf96dc8de5a5893
blob + 3d01c4f2665c86b8fe4cbb18379afaccf8ca65ac
--- sys/dev/ic/dwqe.c
+++ sys/dev/ic/dwqe.c
@@ -705,7 +705,7 @@ dwqe_up(struct dwqe_softc *sc)
{
struct ifnet *ifp = >sc_ac.ac_if;
struct dwqe_buf *txb, *rxb;
- uint32_t mode, reg, tqs, rqs;
+ uint32_t mode, reg, fifosz, tqs, rqs;
int i;
/* Allocate Tx descriptor ring. */
@@ -793,9 +793,21 @@ dwqe_up(struct dwqe_softc *sc)
mode |= GMAC_MTL_CHAN_RX_OP_MODE_RSF;
}
mode &= ~GMAC_MTL_CHAN_RX_OP_MODE_RQS_MASK;
- rqs = (128 << GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(sc->sc_hw_feature[1]) /
- 256) - 1;
- mode |= rqs << GMAC_MTL_CHAN_RX_OP_MODE_RQS_SHIFT;
+ if (sc->sc_rxfifo_size)
+ fifosz = sc->sc_rxfifo_size;
+ else
+ fifosz = (128 <<
+ GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(sc->sc_hw_feature[1]));
+ rqs = fifosz / 256 - 1;
+ mode |= (rqs << GMAC_MTL_CHAN_RX_OP_MODE_RQS_SHIFT) &
+ GMAC_MTL_CHAN_RX_OP_MODE_RQS_MASK;
+ if (fifosz >= 4096) {
+ mode |= GMAC_MTL_CHAN_RX_OP_MODE_EHFC;
+ mode &= ~GMAC_MTL_CHAN_RX_OP_MODE_RFD_MASK;
+ mode |= 0x3 << GMAC_MTL_CHAN_RX_OP_MODE_RFD_SHIFT;
+ mode &= ~GMAC_MTL_CHAN_RX_OP_MODE_RFA_MASK;
+ mode |= 0x1 << GMAC_MTL_CHAN_RX_OP_MODE_RFA_SHIFT;
+ }
dwqe_write(sc, GMAC_MTL_CHAN_RX_OP_MODE(0), mode);
mode = dwqe_read(sc, GMAC_MTL_CHAN_TX_OP_MODE(0));
@@ -809,9 +821,14 @@ dwqe_up(struct dwqe_softc *sc)
mode &= ~GMAC_MTL_CHAN_TX_OP_MODE_TXQEN_MASK;
mode |= GMAC_MTL_CHAN_TX_OP_MODE_TXQEN;
mode &= ~GMAC_MTL_CHAN_TX_OP_MODE_TQS_MASK;
- tqs = (128 << GMAC_MAC_HW_FEATURE1_TXFIFOSIZE(sc->sc_hw_feature[1]) /
- 256) - 1;
- mode |= tqs << GMAC_MTL_CHAN_TX_OP_MODE_TQS_SHIFT;
+ if (sc->sc_txfifo_size)
+ fifosz = sc->sc_txfifo_size;
+ else
+ fifosz = (128 <<
+ GMAC_MAC_HW_FEATURE1_TXFIFOSIZE(sc->sc_hw_feature[1]));
+ tqs = (fifosz / 256) - 1;
+ mode |= (tqs << GMAC_MTL_CHAN_TX_OP_MODE_TQS_SHIFT) &
+ GMAC_MTL_CHAN_TX_OP_MODE_TQS_MASK;
dwqe_write(sc, GMAC_MTL_CHAN_TX_OP_MODE(0), mode);
reg = dwqe_read(sc, GMAC_QX_TX_FLOW_CTRL(0));
blob - 68d698a50beef00f002d986d7d24f8984c3efe0c
blob + d5ba09b005c469eec48b17dcbda6c76f277380e7
--- sys/dev/ic/dwqevar.h
+++ sys/dev/ic/dwqevar.h
@@ -97,6 +97,8 @@ struct dwqe_softc {
int sc_pbl;
int sc_txpbl;
int sc_rxpbl;
+ int sc_txfifo_size;
+ int sc_rxfifo_size;
int sc_axi_config;
int sc_lpi_en;
int sc_xit_frm;
blob - 101ed502e76987c27878712b4921cc49f7eb7f59
blob + 6868eb3591995804dbc332308c9d9629f73c269f
--- sys/dev/pci/files.pci
+++ sys/dev/pci/files.pci
@@ -363,6 +363,10 @@ device ixl: ether, ifnet, ifmedia, intrmap, stoeplitz
attach ixl at pci
file dev/pci/if_ixl.cixl
+# Intel Elkhart Lake Ethernet
+attach dwqe at pci with dwqe_pci
+file dev/pci/if_dwqe_pci.c dwqe_pci
+
# Neterion Xframe 10 Gigabit ethernet
device xge: ether, ifnet, ifmedia
attach xge at pci
blob - /dev/null
blob + d157f116c025d882f1ec8df84b4c3deca3ca340f (mode 644)
--- /dev/null
+++ sys/dev/pci/if_dwqe_pci.c
@@ -0,0 +1,154 @@
+/* $OpenBSD$ */
+
+/*
+ * Copyright (c) 2023 Stefan Sperling
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *
Re: initial Intel Elkhart Lake Ethernet support / dwqe(4) at pci
> Date: Tue, 10 Oct 2023 20:49:46 +0200
> From: Stefan Sperling
>
> On Tue, Oct 10, 2023 at 08:41:37PM +0200, Mark Kettenis wrote:
> > So the GMAC_VERSION #define is simply wrong. We should commit the
> > diff attached and drop the sc_core stuff you added below.
>
> That means all our supported chips are GMAC4 and later? Good to know.
Yes, earlier generations are handled by dwge(4).
> > > + switch (PCI_PRODUCT(pa->pa_id)) {
> > > + case PCI_PRODUCT_INTEL_EHL_PSE0_RGMII_1G:
> > > + sc->sc_phy_mode = DWQE_PHY_MODE_RGMII;
> >
> > This suggests that the PHY must be programmed to disable its internal
> > delays. Our eephy(4) driver doesn't do this. That may explain the
> > poor performance. See how MIIF_SETDELAY, MIIF_RXID and MIIF_TXID are
> > used in rgephy(4).
> >
> > Anyway, that is a different driver, so a separate diff that can go in
> > after this one.
>
> Thanks for the hint. I will take a look.
>
> > > + sc->sc_txfifo_size = 4096 * 8;
> > > + sc->sc_rxfifo_size = 4096 * 8;
> >
> > Makes more sense to simply use 32768 here. Intel's data sheet says 32KB.
>
> I will fix this and send a follow-up version soon.
>
> OK for your diff. Please put it in and I'll rebase on top.
done
> > Index: dev/ic/dwqereg.h
> > ===
> > RCS file: /cvs/src/sys/dev/ic/dwqereg.h,v
> > retrieving revision 1.2
> > diff -u -p -r1.2 dwqereg.h
> > --- dev/ic/dwqereg.h16 Feb 2023 14:43:53 - 1.2
> > +++ dev/ic/dwqereg.h10 Oct 2023 18:40:19 -
> > @@ -39,8 +39,6 @@
> > #define GMAC_MAC_PACKET_FILTER_PR (1 << 0)
> > #define GMAC_MAC_HASH_TAB_REG0 0x0010
> > #define GMAC_MAC_HASH_TAB_REG1 0x0014
> > -#define GMAC_VERSION 0x0020
> > -#define GMAC_VERSION_SNPS_MASK0xff
> > #define GMAC_INT_MASK 0x003c
> > #define GMAC_INT_MASK_LPIIM (1 << 10)
> > #define GMAC_INT_MASK_PIM (1 << 3)
> > @@ -60,6 +58,8 @@
> > #define GMAC_INT_STATUS0x00b0
> > #define GMAC_INT_EN0x00b4
> > #define GMAC_MAC_1US_TIC_CTR 0x00dc
> > +#define GMAC_VERSION 0x0110
> > +#define GMAC_VERSION_SNPS_MASK0xff
> > #define GMAC_MAC_HW_FEATURE(x) (0x011c + (x) * 0x4)
> > #define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE(x) (((x) >> 6) & 0x1f)
> > #define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(x) (((x) >> 0) & 0x3f)
> >
> >
>
Re: initial Intel Elkhart Lake Ethernet support / dwqe(4) at pci
On Tue, Oct 10, 2023 at 08:41:37PM +0200, Mark Kettenis wrote:
> So the GMAC_VERSION #define is simply wrong. We should commit the
> diff attached and drop the sc_core stuff you added below.
That means all our supported chips are GMAC4 and later? Good to know.
> > + switch (PCI_PRODUCT(pa->pa_id)) {
> > + case PCI_PRODUCT_INTEL_EHL_PSE0_RGMII_1G:
> > + sc->sc_phy_mode = DWQE_PHY_MODE_RGMII;
>
> This suggests that the PHY must be programmed to disable its internal
> delays. Our eephy(4) driver doesn't do this. That may explain the
> poor performance. See how MIIF_SETDELAY, MIIF_RXID and MIIF_TXID are
> used in rgephy(4).
>
> Anyway, that is a different driver, so a separate diff that can go in
> after this one.
Thanks for the hint. I will take a look.
> > + sc->sc_txfifo_size = 4096 * 8;
> > + sc->sc_rxfifo_size = 4096 * 8;
>
> Makes more sense to simply use 32768 here. Intel's data sheet says 32KB.
I will fix this and send a follow-up version soon.
OK for your diff. Please put it in and I'll rebase on top.
> Index: dev/ic/dwqereg.h
> ===
> RCS file: /cvs/src/sys/dev/ic/dwqereg.h,v
> retrieving revision 1.2
> diff -u -p -r1.2 dwqereg.h
> --- dev/ic/dwqereg.h 16 Feb 2023 14:43:53 - 1.2
> +++ dev/ic/dwqereg.h 10 Oct 2023 18:40:19 -
> @@ -39,8 +39,6 @@
> #define GMAC_MAC_PACKET_FILTER_PR (1 << 0)
> #define GMAC_MAC_HASH_TAB_REG0 0x0010
> #define GMAC_MAC_HASH_TAB_REG1 0x0014
> -#define GMAC_VERSION 0x0020
> -#define GMAC_VERSION_SNPS_MASK 0xff
> #define GMAC_INT_MASK0x003c
> #define GMAC_INT_MASK_LPIIM (1 << 10)
> #define GMAC_INT_MASK_PIM (1 << 3)
> @@ -60,6 +58,8 @@
> #define GMAC_INT_STATUS 0x00b0
> #define GMAC_INT_EN 0x00b4
> #define GMAC_MAC_1US_TIC_CTR 0x00dc
> +#define GMAC_VERSION 0x0110
> +#define GMAC_VERSION_SNPS_MASK 0xff
> #define GMAC_MAC_HW_FEATURE(x) (0x011c + (x) * 0x4)
> #define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE(x) (((x) >> 6) & 0x1f)
> #define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(x) (((x) >> 0) & 0x3f)
>
>
Re: initial Intel Elkhart Lake Ethernet support / dwqe(4) at pci
> Date: Tue, 10 Oct 2023 19:40:31 +0200
> From: Stefan Sperling
>
> This patch adds enough code to get Elkart Lake devices with PCI
> Vendor ID 8086 and Product ID 4ba0 to attach and pass traffic.
>
> dwqe0 at pci0 dev 29 function 1 "Intel Elkhart Lake Ethernet" rev 0x11: rev
> 0x52, address xx:xx:xx:xx:xx:xx
> eephy0 at dwqe0 phy 1: 88E1512 10/100/1000 PHY, rev. 1
>
> # ifconfig dwqe0 media
> dwqe0: flags=8843 mtu 1500
> lladdr xx:xx:xx:xx:xx:xx
> index 5 priority 0 llprio 3
> media: Ethernet autoselect (1000baseT full-duplex,master)
> status: active
> supported media:
> media none
> media 10baseT
> media 10baseT mediaopt full-duplex
> media 100baseTX
> media 100baseTX mediaopt full-duplex
> media 1000baseT
> media 1000baseT mediaopt full-duplex
> media autoselect
>
> There is one issue though: Tx speed is currently capped to 64 Mbps in my
> testing, while Rx works at 300 Mbps. I will keep investigating this problem.
> But since 64 is better than 0 and the device seems to be working reliably
> in my testing I think it's worth getting this in and fixing remaining the
> issues in the tree.
>
> Various other PCI IDs could attach to this but would require more code.
> I don't have access to such hardware. So they remain commented for now.
> There is a second Elkhart Lake Ethernet device in the same box, with
> PCI id 4bb0. However, this interface has no physical Ethernet port
> exposed, and according to Linux there is no PHY attached to the MAC.
> Linux detects this device but fails to atach a PHY.
>
> ok?
So the GMAC_VERSION #define is simply wrong. We should commit the
diff attached and drop the sc_core stuff you added below.
A few more nits below...
> diff refs/heads/master refs/heads/dwqe
> commit - ef065493fb463fe122ab7b535932b871830b6de3
> commit + a82b4a31a1787b55291d125b3adfb40fe58779e4
> blob - c6094ca5a57d964784f56124b8d923393b1abb66
> blob + cf64e8ff2018fb0ee1e7e59b29b2bc2dd281aa99
> --- sys/arch/amd64/conf/GENERIC
> +++ sys/arch/amd64/conf/GENERIC
> @@ -556,6 +556,7 @@ lii* at pci? # Attansic L2
> Ethernet
> jme* at pci? # JMicron JMC250/JMC260 Ethernet
> bnxt*at pci? # Broadcom BCM573xx, BCM574xx
> ixl* at pci? # Intel Ethernet 700 Series
> +dwqe*at pci? # Intel Elkhart Lake Ethernet
> mcx* at pci? # Mellanox ConnectX-4
> iavf*at pci? # Intel Ethernet Adaptive VF
> aq* at pci? # Aquantia aQtion Ethernet
> blob - 7e6afaba34dd35e3bd180055a68741ee3b773486
> blob + 6a4cc88f048d63430ea9eb6080cd98741f7e1612
> --- sys/dev/fdt/if_dwqe_fdt.c
> +++ sys/dev/fdt/if_dwqe_fdt.c
> @@ -111,6 +111,8 @@ dwqe_fdt_attach(struct device *parent, struct device *
> }
> sc->sc_dmat = faa->fa_dmat;
>
> + sc->sc_core = DWQE_CORE_GMAC;
> +
> /* Decide GMAC id through address */
> switch (faa->fa_reg[0].addr) {
> case 0xfe2a:/* RK3568 */
> blob - 7d260ef46054d6566ef2f81f6cf96dc8de5a5893
> blob + 7ae36ee6e804b7456c296a248d2b058ffe65f722
> --- sys/dev/ic/dwqe.c
> +++ sys/dev/ic/dwqe.c
> @@ -100,7 +100,14 @@ dwqe_attach(struct dwqe_softc *sc)
> uint32_t version, mode;
> int i;
>
> - version = dwqe_read(sc, GMAC_VERSION);
> + switch (sc->sc_core) {
> + case DWQE_CORE_GMAC:
> + version = dwqe_read(sc, GMAC_VERSION);
> + break;
> + case DWQE_CORE_GMAC4:
> + version = dwqe_read(sc, GMAC4_VERSION);
> + break;
> + }
> printf(": rev 0x%02x, address %s\n", version & GMAC_VERSION_SNPS_MASK,
> ether_sprintf(sc->sc_lladdr));
>
> @@ -705,7 +712,7 @@ dwqe_up(struct dwqe_softc *sc)
> {
> struct ifnet *ifp = >sc_ac.ac_if;
> struct dwqe_buf *txb, *rxb;
> - uint32_t mode, reg, tqs, rqs;
> + uint32_t mode, reg, fifosz, tqs, rqs;
> int i;
>
> /* Allocate Tx descriptor ring. */
> @@ -793,9 +800,21 @@ dwqe_up(struct dwqe_softc *sc)
> mode |= GMAC_MTL_CHAN_RX_OP_MODE_RSF;
> }
> mode &= ~GMAC_MTL_CHAN_RX_OP_MODE_RQS_MASK;
> - rqs = (128 << GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(sc->sc_hw_feature[1]) /
> - 256) - 1;
> - mode |= rqs << GMAC_MTL_CHAN_RX_OP_MODE_RQS_SHIFT;
> + if (sc->sc_rxfifo_size)
> + fifosz = sc->sc_rxfifo_size;
> + else
> + fifosz = (128 <<
> + GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(sc->sc_hw_feature[1]));
> + rqs = fifosz / 256 - 1;
> + mode |= (rqs << GMAC_MTL_CHAN_RX_OP_MODE_RQS_SHIFT) &
> +GMAC_MTL_CHAN_RX_OP_MODE_RQS_MASK;
> + if (fifosz >= 4096) {
> + mode |= GMAC_MTL_CHAN_RX_OP_MODE_EHFC;
> + mode &=
initial Intel Elkhart Lake Ethernet support / dwqe(4) at pci
This patch adds enough code to get Elkart Lake devices with PCI
Vendor ID 8086 and Product ID 4ba0 to attach and pass traffic.
dwqe0 at pci0 dev 29 function 1 "Intel Elkhart Lake Ethernet" rev 0x11: rev
0x52, address xx:xx:xx:xx:xx:xx
eephy0 at dwqe0 phy 1: 88E1512 10/100/1000 PHY, rev. 1
# ifconfig dwqe0 media
dwqe0: flags=8843 mtu 1500
lladdr xx:xx:xx:xx:xx:xx
index 5 priority 0 llprio 3
media: Ethernet autoselect (1000baseT full-duplex,master)
status: active
supported media:
media none
media 10baseT
media 10baseT mediaopt full-duplex
media 100baseTX
media 100baseTX mediaopt full-duplex
media 1000baseT
media 1000baseT mediaopt full-duplex
media autoselect
There is one issue though: Tx speed is currently capped to 64 Mbps in my
testing, while Rx works at 300 Mbps. I will keep investigating this problem.
But since 64 is better than 0 and the device seems to be working reliably
in my testing I think it's worth getting this in and fixing remaining the
issues in the tree.
Various other PCI IDs could attach to this but would require more code.
I don't have access to such hardware. So they remain commented for now.
There is a second Elkhart Lake Ethernet device in the same box, with
PCI id 4bb0. However, this interface has no physical Ethernet port
exposed, and according to Linux there is no PHY attached to the MAC.
Linux detects this device but fails to atach a PHY.
ok?
diff refs/heads/master refs/heads/dwqe
commit - ef065493fb463fe122ab7b535932b871830b6de3
commit + a82b4a31a1787b55291d125b3adfb40fe58779e4
blob - c6094ca5a57d964784f56124b8d923393b1abb66
blob + cf64e8ff2018fb0ee1e7e59b29b2bc2dd281aa99
--- sys/arch/amd64/conf/GENERIC
+++ sys/arch/amd64/conf/GENERIC
@@ -556,6 +556,7 @@ lii*at pci? # Attansic L2
Ethernet
jme* at pci? # JMicron JMC250/JMC260 Ethernet
bnxt* at pci? # Broadcom BCM573xx, BCM574xx
ixl* at pci? # Intel Ethernet 700 Series
+dwqe* at pci? # Intel Elkhart Lake Ethernet
mcx* at pci? # Mellanox ConnectX-4
iavf* at pci? # Intel Ethernet Adaptive VF
aq*at pci? # Aquantia aQtion Ethernet
blob - 7e6afaba34dd35e3bd180055a68741ee3b773486
blob + 6a4cc88f048d63430ea9eb6080cd98741f7e1612
--- sys/dev/fdt/if_dwqe_fdt.c
+++ sys/dev/fdt/if_dwqe_fdt.c
@@ -111,6 +111,8 @@ dwqe_fdt_attach(struct device *parent, struct device *
}
sc->sc_dmat = faa->fa_dmat;
+ sc->sc_core = DWQE_CORE_GMAC;
+
/* Decide GMAC id through address */
switch (faa->fa_reg[0].addr) {
case 0xfe2a:/* RK3568 */
blob - 7d260ef46054d6566ef2f81f6cf96dc8de5a5893
blob + 7ae36ee6e804b7456c296a248d2b058ffe65f722
--- sys/dev/ic/dwqe.c
+++ sys/dev/ic/dwqe.c
@@ -100,7 +100,14 @@ dwqe_attach(struct dwqe_softc *sc)
uint32_t version, mode;
int i;
- version = dwqe_read(sc, GMAC_VERSION);
+ switch (sc->sc_core) {
+ case DWQE_CORE_GMAC:
+ version = dwqe_read(sc, GMAC_VERSION);
+ break;
+ case DWQE_CORE_GMAC4:
+ version = dwqe_read(sc, GMAC4_VERSION);
+ break;
+ }
printf(": rev 0x%02x, address %s\n", version & GMAC_VERSION_SNPS_MASK,
ether_sprintf(sc->sc_lladdr));
@@ -705,7 +712,7 @@ dwqe_up(struct dwqe_softc *sc)
{
struct ifnet *ifp = >sc_ac.ac_if;
struct dwqe_buf *txb, *rxb;
- uint32_t mode, reg, tqs, rqs;
+ uint32_t mode, reg, fifosz, tqs, rqs;
int i;
/* Allocate Tx descriptor ring. */
@@ -793,9 +800,21 @@ dwqe_up(struct dwqe_softc *sc)
mode |= GMAC_MTL_CHAN_RX_OP_MODE_RSF;
}
mode &= ~GMAC_MTL_CHAN_RX_OP_MODE_RQS_MASK;
- rqs = (128 << GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(sc->sc_hw_feature[1]) /
- 256) - 1;
- mode |= rqs << GMAC_MTL_CHAN_RX_OP_MODE_RQS_SHIFT;
+ if (sc->sc_rxfifo_size)
+ fifosz = sc->sc_rxfifo_size;
+ else
+ fifosz = (128 <<
+ GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(sc->sc_hw_feature[1]));
+ rqs = fifosz / 256 - 1;
+ mode |= (rqs << GMAC_MTL_CHAN_RX_OP_MODE_RQS_SHIFT) &
+ GMAC_MTL_CHAN_RX_OP_MODE_RQS_MASK;
+ if (fifosz >= 4096) {
+ mode |= GMAC_MTL_CHAN_RX_OP_MODE_EHFC;
+ mode &= ~GMAC_MTL_CHAN_RX_OP_MODE_RFD_MASK;
+ mode |= 0x3 << GMAC_MTL_CHAN_RX_OP_MODE_RFD_SHIFT;
+ mode &= ~GMAC_MTL_CHAN_RX_OP_MODE_RFA_MASK;
+ mode |= 0x1 << GMAC_MTL_CHAN_RX_OP_MODE_RFA_SHIFT;
+ }
dwqe_write(sc, GMAC_MTL_CHAN_RX_OP_MODE(0), mode);
mode = dwqe_read(sc, GMAC_MTL_CHAN_TX_OP_MODE(0));
@@ -809,9 +828,14 @@
