Re: remove support for Cyrix 486DLC & Cyrix 6x86
On Fri, Aug 19, 2022 at 10:31:30PM -0400, Daniel Dickman wrote:
> The below diff removes detection code for the Cyrix 486DLC and Cyrix 6x86
> CPUs from OpenBSD/i386.
>
> The Cyrix 486DLC is a 486-class CPU which we no longer support.
>
> The 6x86, also known as the M1, does not support CPUID by default. But it
> can be made to support this instruction if bit 7 in CCR4 is enabled. We
> don't do this in the tree today.
>
> The reason to remove support for the 6x86 is because it doesn't support
> the RDTSC instruction which we we use unconditionally. Therefore I don't
> believe Cyrix CPUs older than the 6x86MX (aka the M2) can run
> OpenBSD/i386.
>
> We keep the "cyrix6x86_cpu_setup" function in machdep because those quirks
> would still be needed on the M2.
>
> After this diff, the CPU detection code on i386 would assume that if the
> ID bit is missing from EFLAGS, we're running on an intel 486, while if we
> have the ID bit then we use the CPUID instruction for the detection logic.
>
> We also make the same change to amd64/include/specialreg.h to remove the
> defines for the Cyrix 486DLC. No Cyrix CPU supports amd64, so these
> defines have never made sense there.
>
ok jsg@
>
> Index: i386/i386/locore0.S
> ===
> RCS file: /cvs/src/sys/arch/i386/i386/locore0.S,v
> retrieving revision 1.7
> diff -u -p -u -r1.7 locore0.S
> --- i386/i386/locore0.S 15 Aug 2022 04:17:50 - 1.7
> +++ i386/i386/locore0.S 20 Aug 2022 02:07:30 -
> @@ -133,56 +133,6 @@ start: movw$0x1234,0x472 # warm
> boot
> jnz .Ltry586
> .Lis486: movl$CPU_486,RELOC(_C_LABEL(cpu))
>
> - /*
> - * Check Cyrix CPU
> - * Cyrix CPUs do not change the undefined flags following
> - * execution of the divide instruction which divides 5 by 2.
> - *
> - * Note: CPUID is enabled on M2, so it passes another way.
> - */
> - pushfl
> - movl$0x, %eax
> - xorl%edx, %edx
> - movl$2, %ecx
> - clc
> - divl%ecx
> - jnc .Ltrycyrix486
> - popfl
> - jmp 2f
> -.Ltrycyrix486:
> - movl$CPU_6x86,RELOC(_C_LABEL(cpu)) # set CPU type
> - /*
> - * Check for Cyrix 486 CPU by seeing if the flags change during a
> - * divide. This is documented in the Cx486SLC/e SMM Programmer's
> - * Guide.
> - */
> - xorl%edx,%edx
> - cmpl%edx,%edx # set flags to known state
> - pushfl
> - popl%ecx# store flags in ecx
> - movl$-1,%eax
> - movl$4,%ebx
> - divl%ebx# do a long division
> - pushfl
> - popl%eax
> - xorl%ecx,%eax # are the flags different?
> - testl $0x8d5,%eax # only check C|PF|AF|Z|N|V
> - jne 2f # yes; must not be Cyrix CPU
> - movl$CPU_486DLC,RELOC(_C_LABEL(cpu))# set CPU type
> -
> - /* Disable caching of the ISA hole only. */
> - invd
> - movb$CCR0,%al # Configuration Register index (CCR0)
> - outb%al,$0x22
> - inb $0x23,%al
> - orb $(CCR0_NC1|CCR0_BARB),%al
> - movb%al,%ah
> - movb$CCR0,%al
> - outb%al,$0x22
> - movb%ah,%al
> - outb%al,$0x23
> - invd
> -
> jmp 2f
>
> .Ltry586:/* Use the `cpuid' instruction. */
> Index: i386/i386/machdep.c
> ===
> RCS file: /cvs/src/sys/arch/i386/i386/machdep.c,v
> retrieving revision 1.653
> diff -u -p -u -r1.653 machdep.c
> --- i386/i386/machdep.c 18 Aug 2022 13:05:43 - 1.653
> +++ i386/i386/machdep.c 20 Aug 2022 02:07:30 -
> @@ -498,14 +498,8 @@ char cpu_model[120];
> * We deal with the rest in a different way.
> */
> const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = {
> - { CPUVENDOR_INTEL, "Intel", "486SX",CPUCLASS_486,
> - NULL}, /* CPU_486SX */
> { CPUVENDOR_INTEL, "Intel", "486DX",CPUCLASS_486,
> NULL}, /* CPU_486 */
> - { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486,
> - NULL}, /* CPU_486DLC */
> - { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486,
> - cyrix6x86_cpu_setup}, /* CPU_6x86 */
> };
>
> const char *classnames[] = {
> @@ -2075,9 +2069,6 @@ identifycpu(struct cpu_info *ci)
> cpu_class = class;
>
> ci->cpu_class = class;
> -
> - if (cpu == CPU_486DLC)
> - printf("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n");
>
> /*
>* Enable ring 0 write protection.
> Index: i386/include/cputypes.h
> ===
> RCS file: /cvs/src/sys/arch/i386/include/cputypes.h,v
> retrieving
Re: remove support for Cyrix 486DLC & Cyrix 6x86
On Fri, Aug 19, 2022 at 10:31:30PM -0400, Daniel Dickman wrote:
> The below diff removes detection code for the Cyrix 486DLC and Cyrix 6x86
> CPUs from OpenBSD/i386.
>
> The Cyrix 486DLC is a 486-class CPU which we no longer support.
>
> The 6x86, also known as the M1, does not support CPUID by default. But it
> can be made to support this instruction if bit 7 in CCR4 is enabled. We
> don't do this in the tree today.
>
> The reason to remove support for the 6x86 is because it doesn't support
> the RDTSC instruction which we we use unconditionally. Therefore I don't
> believe Cyrix CPUs older than the 6x86MX (aka the M2) can run
> OpenBSD/i386.
>
> We keep the "cyrix6x86_cpu_setup" function in machdep because those quirks
> would still be needed on the M2.
>
> After this diff, the CPU detection code on i386 would assume that if the
> ID bit is missing from EFLAGS, we're running on an intel 486, while if we
> have the ID bit then we use the CPUID instruction for the detection logic.
>
> We also make the same change to amd64/include/specialreg.h to remove the
> defines for the Cyrix 486DLC. No Cyrix CPU supports amd64, so these
> defines have never made sense there.
>
ok mlarkin
>
> Index: i386/i386/locore0.S
> ===
> RCS file: /cvs/src/sys/arch/i386/i386/locore0.S,v
> retrieving revision 1.7
> diff -u -p -u -r1.7 locore0.S
> --- i386/i386/locore0.S 15 Aug 2022 04:17:50 - 1.7
> +++ i386/i386/locore0.S 20 Aug 2022 02:07:30 -
> @@ -133,56 +133,6 @@ start: movw$0x1234,0x472 # warm
> boot
> jnz .Ltry586
> .Lis486: movl$CPU_486,RELOC(_C_LABEL(cpu))
>
> - /*
> - * Check Cyrix CPU
> - * Cyrix CPUs do not change the undefined flags following
> - * execution of the divide instruction which divides 5 by 2.
> - *
> - * Note: CPUID is enabled on M2, so it passes another way.
> - */
> - pushfl
> - movl$0x, %eax
> - xorl%edx, %edx
> - movl$2, %ecx
> - clc
> - divl%ecx
> - jnc .Ltrycyrix486
> - popfl
> - jmp 2f
> -.Ltrycyrix486:
> - movl$CPU_6x86,RELOC(_C_LABEL(cpu)) # set CPU type
> - /*
> - * Check for Cyrix 486 CPU by seeing if the flags change during a
> - * divide. This is documented in the Cx486SLC/e SMM Programmer's
> - * Guide.
> - */
> - xorl%edx,%edx
> - cmpl%edx,%edx # set flags to known state
> - pushfl
> - popl%ecx# store flags in ecx
> - movl$-1,%eax
> - movl$4,%ebx
> - divl%ebx# do a long division
> - pushfl
> - popl%eax
> - xorl%ecx,%eax # are the flags different?
> - testl $0x8d5,%eax # only check C|PF|AF|Z|N|V
> - jne 2f # yes; must not be Cyrix CPU
> - movl$CPU_486DLC,RELOC(_C_LABEL(cpu))# set CPU type
> -
> - /* Disable caching of the ISA hole only. */
> - invd
> - movb$CCR0,%al # Configuration Register index (CCR0)
> - outb%al,$0x22
> - inb $0x23,%al
> - orb $(CCR0_NC1|CCR0_BARB),%al
> - movb%al,%ah
> - movb$CCR0,%al
> - outb%al,$0x22
> - movb%ah,%al
> - outb%al,$0x23
> - invd
> -
> jmp 2f
>
> .Ltry586:/* Use the `cpuid' instruction. */
> Index: i386/i386/machdep.c
> ===
> RCS file: /cvs/src/sys/arch/i386/i386/machdep.c,v
> retrieving revision 1.653
> diff -u -p -u -r1.653 machdep.c
> --- i386/i386/machdep.c 18 Aug 2022 13:05:43 - 1.653
> +++ i386/i386/machdep.c 20 Aug 2022 02:07:30 -
> @@ -498,14 +498,8 @@ char cpu_model[120];
> * We deal with the rest in a different way.
> */
> const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = {
> - { CPUVENDOR_INTEL, "Intel", "486SX",CPUCLASS_486,
> - NULL}, /* CPU_486SX */
> { CPUVENDOR_INTEL, "Intel", "486DX",CPUCLASS_486,
> NULL}, /* CPU_486 */
> - { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486,
> - NULL}, /* CPU_486DLC */
> - { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486,
> - cyrix6x86_cpu_setup}, /* CPU_6x86 */
> };
>
> const char *classnames[] = {
> @@ -2075,9 +2069,6 @@ identifycpu(struct cpu_info *ci)
> cpu_class = class;
>
> ci->cpu_class = class;
> -
> - if (cpu == CPU_486DLC)
> - printf("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n");
>
> /*
>* Enable ring 0 write protection.
> Index: i386/include/cputypes.h
> ===
> RCS file: /cvs/src/sys/arch/i386/include/cputypes.h,v
> retrieving revision 1.13
> diff -u
remove support for Cyrix 486DLC & Cyrix 6x86
The below diff removes detection code for the Cyrix 486DLC and Cyrix 6x86
CPUs from OpenBSD/i386.
The Cyrix 486DLC is a 486-class CPU which we no longer support.
The 6x86, also known as the M1, does not support CPUID by default. But it
can be made to support this instruction if bit 7 in CCR4 is enabled. We
don't do this in the tree today.
The reason to remove support for the 6x86 is because it doesn't support
the RDTSC instruction which we we use unconditionally. Therefore I don't
believe Cyrix CPUs older than the 6x86MX (aka the M2) can run
OpenBSD/i386.
We keep the "cyrix6x86_cpu_setup" function in machdep because those quirks
would still be needed on the M2.
After this diff, the CPU detection code on i386 would assume that if the
ID bit is missing from EFLAGS, we're running on an intel 486, while if we
have the ID bit then we use the CPUID instruction for the detection logic.
We also make the same change to amd64/include/specialreg.h to remove the
defines for the Cyrix 486DLC. No Cyrix CPU supports amd64, so these
defines have never made sense there.
Index: i386/i386/locore0.S
===
RCS file: /cvs/src/sys/arch/i386/i386/locore0.S,v
retrieving revision 1.7
diff -u -p -u -r1.7 locore0.S
--- i386/i386/locore0.S 15 Aug 2022 04:17:50 - 1.7
+++ i386/i386/locore0.S 20 Aug 2022 02:07:30 -
@@ -133,56 +133,6 @@ start: movw$0x1234,0x472 # warm
boot
jnz .Ltry586
.Lis486: movl$CPU_486,RELOC(_C_LABEL(cpu))
- /*
-* Check Cyrix CPU
-* Cyrix CPUs do not change the undefined flags following
-* execution of the divide instruction which divides 5 by 2.
-*
-* Note: CPUID is enabled on M2, so it passes another way.
-*/
- pushfl
- movl$0x, %eax
- xorl%edx, %edx
- movl$2, %ecx
- clc
- divl%ecx
- jnc .Ltrycyrix486
- popfl
- jmp 2f
-.Ltrycyrix486:
- movl$CPU_6x86,RELOC(_C_LABEL(cpu)) # set CPU type
- /*
-* Check for Cyrix 486 CPU by seeing if the flags change during a
-* divide. This is documented in the Cx486SLC/e SMM Programmer's
-* Guide.
-*/
- xorl%edx,%edx
- cmpl%edx,%edx # set flags to known state
- pushfl
- popl%ecx# store flags in ecx
- movl$-1,%eax
- movl$4,%ebx
- divl%ebx# do a long division
- pushfl
- popl%eax
- xorl%ecx,%eax # are the flags different?
- testl $0x8d5,%eax # only check C|PF|AF|Z|N|V
- jne 2f # yes; must not be Cyrix CPU
- movl$CPU_486DLC,RELOC(_C_LABEL(cpu))# set CPU type
-
- /* Disable caching of the ISA hole only. */
- invd
- movb$CCR0,%al # Configuration Register index (CCR0)
- outb%al,$0x22
- inb $0x23,%al
- orb $(CCR0_NC1|CCR0_BARB),%al
- movb%al,%ah
- movb$CCR0,%al
- outb%al,$0x22
- movb%ah,%al
- outb%al,$0x23
- invd
-
jmp 2f
.Ltry586: /* Use the `cpuid' instruction. */
Index: i386/i386/machdep.c
===
RCS file: /cvs/src/sys/arch/i386/i386/machdep.c,v
retrieving revision 1.653
diff -u -p -u -r1.653 machdep.c
--- i386/i386/machdep.c 18 Aug 2022 13:05:43 - 1.653
+++ i386/i386/machdep.c 20 Aug 2022 02:07:30 -
@@ -498,14 +498,8 @@ char cpu_model[120];
* We deal with the rest in a different way.
*/
const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = {
- { CPUVENDOR_INTEL, "Intel", "486SX",CPUCLASS_486,
- NULL}, /* CPU_486SX */
{ CPUVENDOR_INTEL, "Intel", "486DX",CPUCLASS_486,
NULL}, /* CPU_486 */
- { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486,
- NULL}, /* CPU_486DLC */
- { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486,
- cyrix6x86_cpu_setup}, /* CPU_6x86 */
};
const char *classnames[] = {
@@ -2075,9 +2069,6 @@ identifycpu(struct cpu_info *ci)
cpu_class = class;
ci->cpu_class = class;
-
- if (cpu == CPU_486DLC)
- printf("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n");
/*
* Enable ring 0 write protection.
Index: i386/include/cputypes.h
===
RCS file: /cvs/src/sys/arch/i386/include/cputypes.h,v
retrieving revision 1.13
diff -u -p -u -r1.13 cputypes.h
--- i386/include/cputypes.h 15 Aug 2022 04:17:51 - 1.13
+++ i386/include/cputypes.h 20 Aug 2022 02:07:30 -
@@ -37,19 +37,10 @@
#define
