Re: [time-nuts] What is a Time-Nut grade Zero Crossing Circuit?

[Richard (Rick) Karlquist]

John Miles wrote:
>>> Modern ECL parts aren't necessarily that bad compared to the old MECL
>>> stuff.
>> My experience goes all the way back to the MECL 1000 series that was
>> discontinued 30 years ago.  I designed many synthesizers around them
>> for Zeta Labs.  Every newer family of ECL line receivers has been faster
>> and had worse phase noise, in my experience.
> 
> Which is odd because the jitter specs have gotten better -- at least, going
> by the promises and hype in the data sheets.  It sounds like the newer ECL
> parts' wider bandwidth is folding more noise into the output signal.

The older parts had no jitter specs.  Jitter specs assume a logic
waveform input, not a sine wave input.  Many jitter specs refer to
pattern jitter of data, which does not apply to clocks.  Also, jitter 
increases at low frequencies in practice, even though in theory it 
should not.  Like I said, this topic is very tricky.

Rick Karlquist N6RK



> 
>> This is a very tricky topic.  When measuring the phase noise of a non
>> sine wave, there are dependencies on how the measurement is done.
>> What is the measurement bandwidth?  Etc.
>>
>> In some cases, the noise is mostly common mode, and therefore will
>> depend on the common mode rejection ratio (if any) of your measurement
>> circuit.
> 
> I'm measuring it with a 3048A, feeding the DBM directly from one of the
> MC100EL16P's output pins via a 0.1 uF cap.  Both output pins are tied to
> ground with 200 ohms, per Q12 at
> http://www.pulseresearchlab.com/faqs/ecl_ques/ecl_Q9-Q12.htm .
> 
> Input-wise, I just tried a T1-1 balun instead of the single-ended
> termination I was using before, and got exactly the same results (floor at
> circa -148 to -150 dBc/Hz at 100 MHz, but only -140 dBc/Hz at 10 MHz.)
> That, I thought was interesting.  -148 dBc/Hz was always the 'rule of thumb'
> for the older ECL families from what I've read, and since it's not sensitive
> to input configuration or power-supply bypassing, it must be the process
> floor.

I measured phase noise on an MC100E131 drop from -145 to -165 by taking 
the output differentially.  This was done in 1992.  Others have
been unable to repeat this result, even using some old 1992 parts I
kept.  So who knows?  Todd Pearson of Motorola said that they have
seen this drop with differential outputs.


> 
> There was no LC or other bandpass filtering at the input, but the sources
> are decent-quality OCXOs in both cases so I don't think I'm feeding it too
> much broadband noise to begin with.
> 
> Maybe another T1-1 at the output would help, but I don't see any reason to
> think so.
> 
> -- john, KE5FX
> 
> 
> 
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Re: [time-nuts] What is a Time-Nut grade Zero Crossing Circuit?

[John Miles]

> > Modern ECL parts aren't necessarily that bad compared to the old MECL
> > stuff.
>
> My experience goes all the way back to the MECL 1000 series that was
> discontinued 30 years ago.  I designed many synthesizers around them
> for Zeta Labs.  Every newer family of ECL line receivers has been faster
> and had worse phase noise, in my experience.

Which is odd because the jitter specs have gotten better -- at least, going
by the promises and hype in the data sheets.  It sounds like the newer ECL
parts' wider bandwidth is folding more noise into the output signal.

> This is a very tricky topic.  When measuring the phase noise of a non
> sine wave, there are dependencies on how the measurement is done.
> What is the measurement bandwidth?  Etc.
>
> In some cases, the noise is mostly common mode, and therefore will
> depend on the common mode rejection ratio (if any) of your measurement
> circuit.

I'm measuring it with a 3048A, feeding the DBM directly from one of the
MC100EL16P's output pins via a 0.1 uF cap.  Both output pins are tied to
ground with 200 ohms, per Q12 at
http://www.pulseresearchlab.com/faqs/ecl_ques/ecl_Q9-Q12.htm .

Input-wise, I just tried a T1-1 balun instead of the single-ended
termination I was using before, and got exactly the same results (floor at
circa -148 to -150 dBc/Hz at 100 MHz, but only -140 dBc/Hz at 10 MHz.)
That, I thought was interesting.  -148 dBc/Hz was always the 'rule of thumb'
for the older ECL families from what I've read, and since it's not sensitive
to input configuration or power-supply bypassing, it must be the process
floor.

There was no LC or other bandpass filtering at the input, but the sources
are decent-quality OCXOs in both cases so I don't think I'm feeding it too
much broadband noise to begin with.

Maybe another T1-1 at the output would help, but I don't see any reason to
think so.

-- john, KE5FX



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Re: [time-nuts] What is a Time-Nut grade Zero Crossing Circuit?

[Rick Karlquist]

John Miles wrote:
> Modern ECL parts aren't necessarily that bad compared to the old MECL
> stuff.

My experience goes all the way back to the MECL 1000 series that was
discontinued 30 years ago.  I designed many synthesizers around them
for Zeta Labs.  Every newer family of ECL line receivers has been faster
and had worse phase noise, in my experience.


> For some reason, though, the one circuit I measured (MC100EL16 line
> receiver, driven single-ended) was much quieter at 100 MHz (-150 dBc/Hz
> floor) than at 10 MHz (-140 dBc/Hz floor).  I  need to look into that a
> bit
> further.

This is a very tricky topic.  When measuring the phase noise of a non
sine wave, there are dependencies on how the measurement is done.
What is the measurement bandwidth?  Etc.

In some cases, the noise is mostly common mode, and therefore will
depend on the common mode rejection ratio (if any) of your measurement
circuit.

Rick Karlquist N6RK

Rick Karlquist N6RK


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Re: [time-nuts] What is a Time-Nut grade Zero Crossing Circuit?

[Bruce Griffiths]

Pete wrote:
> The JPL paper is here:  http://tycho.usno.navy.mil/ptti/1990/Vol%2022_20.pdf
>
> Pete Rawson
>   

Pete

You can usually do much better than that.
The Collins paper indicates how.

http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?isnumber=10665&arnumber=494304&type=ref
 

(I know you have to purchase it or perhaps photocopy it. - but its well 
worth the effort)

I have extended the theory to include the case where the input noise 
spectral density is not the same for all finite gain limiter stages.
I also have a few spreadsheets which can be used to calculte the optimum 
gain distribution and corresponding filter bandwidths etc both for the 
restricted case that Collins analyses and the more general case.
The Collin's paper indicates how much better one can do with an 
optimised cascade of finite gain filtered limiter stages as opposed to 
the relatively conventional design in the Dick paper.

With high frequency signals one can use a bandpass filter at least for 
the first couple of low gain limiter stages.

Bruce

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Re: [time-nuts] What is a Time-Nut grade Zero Crossing Circuit?

[John Miles]

>
> I do agree with Richard, comparators are quite bad...
>
> Having played with interfacing signals to FPGA 'ad nausea'
> I found that the only simple scheme that works
> better than biased (or feedback) cmos gates and of
> course much better than ECL line receivers or comparators
> (even cmos gates biased sometimes exhibit some strange issues
> specially when no signal is present)...

Modern ECL parts aren't necessarily that bad compared to the old MECL stuff.
For some reason, though, the one circuit I measured (MC100EL16 line
receiver, driven single-ended) was much quieter at 100 MHz (-150 dBc/Hz
floor) than at 10 MHz (-140 dBc/Hz floor).  I  need to look into that a bit
further.

Point being, benchmarks taken at the usual 10 MHz may not be helpful if you
are actually going to work at higher frequencies.  If the additive jitter
remains constant, the additive phase noise should get worse at higher
carrier frequencies, not better... but that doesn't always seem to be what
happens.

-- john, KE5FX



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Re: [time-nuts] What is a Time-Nut grade Zero Crossing Circuit?

[John Miles]

> In any event, if you actually test real comparators, you will
> find them to be universally lousy.  I will be happy to be proven
> wrong if someone is aware of a good comparator.  It's just that
> I have never met I comparator I liked :-)

I think you're right about that.  About the best thing you can say for using
a comparator is that it can still be better than feeding a CMOS input that
has insufficient gain by itself.  You definitely get better inband phase
noise from the output of an Analog Devices ADF-series or NatSemi LMX-series
synthesizer if you feed its reference input through an external comparator
such as an LT1016.  Is that the best part for the job?  No, but it still
offers an improvement.

Something I've wanted to do for a long time now, but haven't had enough
spare time to, is to document the additive noise of a large list of
sine->square converters.  There is an extensive table in the manual for the
Lucent rubidium oscillator that was just mentioned on eBay (
http://www.symmetricom.com/media/pdf/manuals/man-lpro.pdf ), but it has
several limitations.  It doesn't cover single-ended versus differential
variations, it only considers 10 MHz inputs, it's not clear how they
controlled for amplitude levels and source impedance, and their LT1016 test
circuit is just embarassing.

It's an interesting topic, especially when you're not trying to go for
absolute optimal performance but just want to choose a quick/simple hack
that won't degrade whatever you're driving.  The literature is biased (no
pun intended) toward more complex circuits that are quieter than most signal
sources and destinations are likely to need.  That's what would be nice
about the Lucent app note, if only it were better realized.

-- john, KE5FX


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Re: [time-nuts] What is a Time-Nut grade Zero Crossing Circuit?

[Pete]

The JPL paper is here:  http://tycho.usno.navy.mil/ptti/1990/Vol%2022_20.pdf

Pete Rawson


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Re: [time-nuts] What is a Time-Nut grade Zero Crossing Circuit?

[Luis Cupido]

I do agree with Richard, comparators are quite bad...

Having played with interfacing signals to FPGA 'ad nausea'
I found that the only simple scheme that works
better than biased (or feedback) cmos gates and of
course much better than ECL line receivers or comparators
(even cmos gates biased sometimes exhibit some strange issues
specially when no signal is present)...

As I was saying the best I could find was a differential pair
of fets set to not too high gain. Signal is not step-square
to the ps but the outcome on jitter viewed from inside the FPGA
is the best of all many combinations I've tried, imediately followed
by a differential pair of microwave bipolar transistors which
preform excellent also... (note gains about 5 only, resistors set
to naturally clip the signal to 0 - 2.5V (FPGA friendly) by the
nature of the differential pair behaviour).
(PFET or PNP)

All the rest is crap compared to this...
At least in my experiments.

discrete but simple...
sometimes super-duper ic's are not the best option.

Luis Cupido.
ct1dmk.

p.s. my interest was wide band so filtering amplifying and clipping
(by far the best solution) was not an option for me.


Rick Karlquist wrote:
> Comparators have very wideband, high gain inputs with typically
> high noise figures.  The effective input noise is determined by
> the noise figure and the comparator bandwidth and the fact
> the the comparator only utilizes a few mV of the input signal.  If you are
> trying to square up a 10 MHz signal, and noise from DC-1000 MHz
> is affecting the comparator switching time, you have unnecessarily
> added a bunch of noise above 10 MHz.  You can't filter this noise
> back out after the comparator output.  That's the theory of it.
> 
> 1/f noise is not the issue.  CMOS gates have lower input noise
> IN RELATION TO THE SIGNAL LEVEL involved.  Comparators only use
> a few mV of your signal.  That's why the high gain is bad.
> 
> The ideal circuit is a bandpass linear amplifier that makes a
> large filtered 10 MHz sine wave, which is then passively clipped with
> diodes at the logic levels you need.  This is based on the paradigm
> described by John Dick (of JPL) in his 1990 PTTI paper on zero
> crossing detectors (someone posted that paper I think; anyone know
> the URL?).  It is clear IMHO that a comparator is just about exactly
> the opposite of what Dr. Dick prescribed.
> 
> In any event, if you actually test real comparators, you will
> find them to be universally lousy.  I will be happy to be proven
> wrong if someone is aware of a good comparator.  It's just that
> I have never met I comparator I liked :-)
> 
> Rick Karlquist N6RK
> 
> 
> Didier Juges wrote:
>> Rick,
>>
>> Can you explain #2?
>>
>> I understand ECL has more jitter, so I understand excluding ECL based
>> comparators, but why excluding ALL comparators? It seems to me the
>> comparators allow tighter control of the threshold, so it sounds as if it
>> would help at very low frequencies, unless the higher 1/f noise of the
>> compartor dominates other factors.
>>
>> How does the 1/f noise of a CMOS gate compare to an analog comparator?
>>
>> Didier KO4BB
>>
>>> -Original Message-
>>> From: [EMAIL PROTECTED]
>>> [mailto:[EMAIL PROTECTED] On Behalf Of Rick Karlquist
>>> Sent: Thursday, July 31, 2008 3:14 PM
>>> To: Discussion of precise time and frequency measurement
>>> Subject: Re: [time-nuts] What is a Time-Nut grade Zero
>>> Crossing Circuit?
>>>
>>> Two things NOT to do:
>>>
>>> 1.  Do NOT use ECL.  CMOS is much lower jitter.
>>>
>>> 2.  Do NOT use a comparator to square up the sine wave.
>>> Especially don't use a ultrafast ECL based comparator.
>>>
>>
> 
> 
> 
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Re: [time-nuts] What is a Time-Nut grade Zero Crossing Circuit?

[Rick Karlquist]

Comparators have very wideband, high gain inputs with typically
high noise figures.  The effective input noise is determined by
the noise figure and the comparator bandwidth and the fact
the the comparator only utilizes a few mV of the input signal.  If you are
trying to square up a 10 MHz signal, and noise from DC-1000 MHz
is affecting the comparator switching time, you have unnecessarily
added a bunch of noise above 10 MHz.  You can't filter this noise
back out after the comparator output.  That's the theory of it.

1/f noise is not the issue.  CMOS gates have lower input noise
IN RELATION TO THE SIGNAL LEVEL involved.  Comparators only use
a few mV of your signal.  That's why the high gain is bad.

The ideal circuit is a bandpass linear amplifier that makes a
large filtered 10 MHz sine wave, which is then passively clipped with
diodes at the logic levels you need.  This is based on the paradigm
described by John Dick (of JPL) in his 1990 PTTI paper on zero
crossing detectors (someone posted that paper I think; anyone know
the URL?).  It is clear IMHO that a comparator is just about exactly
the opposite of what Dr. Dick prescribed.

In any event, if you actually test real comparators, you will
find them to be universally lousy.  I will be happy to be proven
wrong if someone is aware of a good comparator.  It's just that
I have never met I comparator I liked :-)

Rick Karlquist N6RK


Didier Juges wrote:
> Rick,
>
> Can you explain #2?
>
> I understand ECL has more jitter, so I understand excluding ECL based
> comparators, but why excluding ALL comparators? It seems to me the
> comparators allow tighter control of the threshold, so it sounds as if it
> would help at very low frequencies, unless the higher 1/f noise of the
> compartor dominates other factors.
>
> How does the 1/f noise of a CMOS gate compare to an analog comparator?
>
> Didier KO4BB
>
>> -Original Message-
>> From: [EMAIL PROTECTED]
>> [mailto:[EMAIL PROTECTED] On Behalf Of Rick Karlquist
>> Sent: Thursday, July 31, 2008 3:14 PM
>> To: Discussion of precise time and frequency measurement
>> Subject: Re: [time-nuts] What is a Time-Nut grade Zero
>> Crossing Circuit?
>>
>> Two things NOT to do:
>>
>> 1.  Do NOT use ECL.  CMOS is much lower jitter.
>>
>> 2.  Do NOT use a comparator to square up the sine wave.
>> Especially don't use a ultrafast ECL based comparator.
>>
>
>



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Re: [time-nuts] What is a Time-Nut grade Zero Crossing Circuit?

[Didier Juges]

Rick,

Can you explain #2?

I understand ECL has more jitter, so I understand excluding ECL based
comparators, but why excluding ALL comparators? It seems to me the
comparators allow tighter control of the threshold, so it sounds as if it
would help at very low frequencies, unless the higher 1/f noise of the
compartor dominates other factors.

How does the 1/f noise of a CMOS gate compare to an analog comparator?

Didier KO4BB 

> -Original Message-
> From: [EMAIL PROTECTED] 
> [mailto:[EMAIL PROTECTED] On Behalf Of Rick Karlquist
> Sent: Thursday, July 31, 2008 3:14 PM
> To: Discussion of precise time and frequency measurement
> Subject: Re: [time-nuts] What is a Time-Nut grade Zero 
> Crossing Circuit?
> 
> Two things NOT to do:
> 
> 1.  Do NOT use ECL.  CMOS is much lower jitter.
> 
> 2.  Do NOT use a comparator to square up the sine wave.
> Especially don't use a ultrafast ECL based comparator.
> 


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Re: [time-nuts] What is a Time-Nut grade Zero Crossing Circuit?

[Rick Karlquist]

Two things NOT to do:

1.  Do NOT use ECL.  CMOS is much lower jitter.

2.  Do NOT use a comparator to square up the sine wave.
Especially don't use a ultrafast ECL based comparator.

---

Some things that you should do:

Make all circuitry differential if possible.  Make your 10 MHz
source differential by putting a transformer on the output.

Band pass filter your 10 MHz source with an LC filter.
I recommend Coilcraft Unicoils or Maxicoils.

Rick Karlquist N6RK


Bob Paddock wrote:
>
> Can you point me to a Time-Nut grade Zero Crossing
> circuit that I can feed a Actel Igloo FPGA (It doesn't
> like sine waves)?
>
> For the sake of discussion the source signal
> is a ThunderBolt at 10 MHz.
>
> The FPGA is rated to 350 MHz, so no need to have
> a 5. GHz Zero Crossing circuit. ;-)
>
> The FPGA has several interface styles,
> so we are not limited to just TTL or CMOS.
>
> Suggestions?
>
>
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Re: [time-nuts] What is a Time-Nut grade Zero Crossing Circuit?

[SAIDJACK]

Hello Bruce,
 
I believe a driver for an FPGA running at 350MHz was the initial query,  6GHz 
BW and crystal filters are probably overkill.
 
bye,
Said
 
 
In a message dated 7/31/2008 01:59:34 Pacific Daylight Time,  
[EMAIL PROTECTED] writes:

Yes,  however it is quieter and adding duty cycle stabilisation feedback 
fixes  that problem.

For even lower noise, bandpass filter the OCXO output (a  crystal filter 
is particularly effective).
Its not too difficult to  drop the noise floor to a few tens of femtosec.
The drawbacks being the  cost, and the need to regulate the bandpass 
filter temperature to minimise  phase shift variations with ambient 
temperature.
You would also need to  use a quieter clock driver.
It may even be necessary to use a well designed  bandpass limiter to 
increase the signal zero crossing slew rate before  using a 6GHz 
bandwidth clock driver.

However the cost and  complexity probably isnt justified when driving an 
FPGA which may have  tens of picoseconds of  jitter.

Bruce





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Re: [time-nuts] What is a Time-Nut grade Zero Crossing Circuit?

[Bruce Griffiths]

[EMAIL PROTECTED] wrote:
> Hi Bruce,
>  
> that would work too. We get <330fs jitter rms with this circuit using  the 
> Fairchild UHS LVC family, that's pretty much the noise floor of the  OCXO :)
>  
> If you use a bias network, you won't get 50% symmetry since it will never  
> perfectly match the inverter's inflection point (which changes with temp 
> etc),  
> and you may insert noise from the power supply. With the feedback resistor it 
>  
> will operation at the inversion point without adding power  supply noise.
>  
> bye,
> Said
>  
>  
>   
Yes, however it is quieter and adding duty cycle stabilisation feedback 
fixes that problem.

For even lower noise, bandpass filter the OCXO output (a crystal filter 
is particularly effective).
Its not too difficult to drop the noise floor to a few tens of femtosec.
The drawbacks being the cost, and the need to regulate the bandpass 
filter temperature to minimise phase shift variations with ambient 
temperature.
You would also need to use a quieter clock driver.
It may even be necessary to use a well designed bandpass limiter to 
increase the signal zero crossing slew rate before using a 6GHz 
bandwidth clock driver.

However the cost and complexity probably isnt justified when driving an 
FPGA which may have tens of picoseconds of jitter.

Bruce


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Re: [time-nuts] What is a Time-Nut grade Zero Crossing Circuit?

[SAIDJACK]

Hi Bruce,
 
that would work too. We get <330fs jitter rms with this circuit using  the 
Fairchild UHS LVC family, that's pretty much the noise floor of the  OCXO :)
 
If you use a bias network, you won't get 50% symmetry since it will never  
perfectly match the inverter's inflection point (which changes with temp etc),  
and you may insert noise from the power supply. With the feedback resistor it  
will operation at the inversion point without adding power  supply noise.
 
bye,
Said
 
 
In a message dated 7/30/2008 20:06:12 Pacific Daylight Time,  
[EMAIL PROTECTED] writes:

>   
Said

Noise is lower if you use a pair of  resistor to bias the inverter input 
at the threshold rather than the  feedback resistor.
A feedback circuit can be added to stabilise the output  duty cycle.

If you want subpicosecond jitter you need to use a  different 
device/logic  family.

Bruce




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