[time-nuts] Need help for measuring MTIE and TDEV of the oscillator

2013-12-02 Thread Varaprasad Rayudu
Hello All,

Can anybody help me by give the procedure to measure MTIE  TDEV parameters of 
the crystal oscillator by using DF6JB's Plotter software tool for the attached 
raw frequecny data.

Thanks in advance.

Regards,
Varaprasad.R996.5520
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Re: [time-nuts] Using a UBlox NEO-6 GPS module for calibrating a PIC microprocessor based timer.

2013-12-02 Thread Brian Inglis

On 2013-12-01 15:52, Attila Kinali wrote:

On Sun, 1 Dec 2013 13:57:56 -0500
Dale J. Robertson d...@nap-us.com wrote:


A unidirectional error of 1/100th of a second would accumulate around a
minute and a half per day. It's been a long time since I laid eyes on a
mechanical pendulum clock. I remember the clock in my childhood home kept
better time than that. ( I became odd very early. I compulsively compared
the clock time to WWV time at least once a day. I had been using the time
service from the phone company. I felt defrauded when I discovered (via WWV)
that the time from the local telco's dialup time service was just a rough
(very rough) approximation of the time.


IIRC 10^-6 was easily acheivable with mechanical clocks, with the
best going to 10^-8 or so (timescale IIRC 1 day).


Hi,
Many clocks and watches were tuned for years before being submitted for rating.

Astronomical regulators (accurate pendulum clocks) kept time within .01s/day, 
and
were improved down to about 1s/year, with the help of electromagnets, before 
being
replaced by quartz oscillators in the 1930s; regulators in other areas were
replaced by electric clocks timed from the grid during that same period.

The best of these had Q ~110,000, with variations in the hundreds of us/day,
better than network synced NTP servers which vary in the low ms.

Mechanical marine chronometer movements are expected to vary only about 
0.1s/day.
Quartz wristwatch COSC certified chronometer movements are rated within .2s/day.
Railroad chronometer movements were expected to stay within 30s/week or ~4s/day.
Mechanical wristwatch COSC certified chronometer movements are rated within 
+6/-4s/day.
The Geneva Standard certifies movements stay within 60s/week or ~8s/day.

The certifications and standards (including ISO 3159) also require drift in 
multiple
orientations and across a range of temperatures ~0-~40C should remain constant.

So with 1 PPM ~ 1 s/11.5 day about 1-10 PPM or 10^-5 to 10^-6 range is expected.

Most modern quartz wristwatches will be in this range and be more accurate than 
all
but the best, custom mechanical timepieces.

--
Take care. Thanks, Brian Inglis
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Re: [time-nuts] Using a UBlox NEO-6 GPS module for calibrating a PIC microprocessor based timer.

2013-12-02 Thread quartz55
I've got a German grandfather clock, with the heavy weights for the clock and 
gong that I played with for a long time, the pendulum had a screw at the 
bottom, probably most do, so it could be adjusted.  Took me a while, but I 
think I got it to within a minute or so every month.  That's not too bad for a 
mechanical device.  But who wants to wait a month to adjust things these days?  
I bet it could be adjusted that good in a day or less with the sound card and 
recording the ticks.

Dave
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[time-nuts] DARPA SBIR - Portable Microwave Cold Atomic Clock

2013-12-02 Thread Mark Kahrs
SB141-004   TITLE: *Portable Microwave Cold Atomic
Clock*



TECHNOLOGY AREAS: Materials/Processes, Sensors, Electronics



This topic is eligible for the DARPA Direct to Phase II Pilot Program.
Please see section 4.0 of the DARPA instructions for additional
information.  To be eligible, offerors are required to provide information
demonstrating the scientific and technical merit and feasibility of a Phase
I project. DARPA will not evaluate the offeror's related Phase II proposal
where it determines that the offeror has failed to demonstrate the
scientific and technical merit and feasibility of the Phase I project.
Offerors must choose between submitting a Phase I proposal OR a Direct to
Phase II proposal, and may not submit both for the same topic.



OBJECTIVE: Develop a laser-cooled microwave atomic clock with small volume
( 1 L) and weight ( 1 kg), low power consumption ( 5 W), and the
stability (10^-12 at 1 s) of a primary atomic frequency standard.



DESCRIPTION: Frequency and timing devices are essential components in
modern military systems. The stability and accuracy of these devices impact
the performance of communication, navigation, surveillance, and missile
guidance systems. Atomic clocks are at the cores of many of these systems,
either directly or via time-transfer from a master clock.



By employing techniques used in current laboratory atomic clocks, military
clocks can be improved by orders-of-magnitude. Such clocks will enable
secure data routing, communication systems that are insensitive to jamming,
higher resolution coherent radar, and more reliable and robust global
positioning.



Laser-cooled optical lattice atomic clocks are currently the world's most
stable clocks, with stability below 10^-18 at 6 hours of averaging [1].
DARPA's QuASAR program aims to miniaturize and ruggedize such
high-performance optical atomic clocks for deployment in the field [2].
While this work could enable widespread adoption of optical clock
technology, many applications cannot tolerate the size, weight, and power
(SWaP) of these first generation portable optical clocks (S  50 L, W  50
kg, P  150 W). DARPA's Chip Scale Atomic Clock (CSAC) program has
developed miniature microwave atomic clocks with extremely low SWaP values
(S ~ 16 cm^3, W ~ 35 g, P ~ 125 mW) and good short-term stability (10^-10
at 1 sec) [3]. However these clocks drift over long timescales making them
unsuitable for many applications.


The goal of this SBIR is to bridge the gap between these extremes by
developing an atomic frequency standard with long term stability (
5x10^-15 at 1 day), approaching that of laboratory frequency standards such
as the NIST F1 microwave Cs fountain clock [4] but with reasonable SWaP
values (S  1 L, W  1 kg, P  5 W).



To achieve these goals, this SBIR will combine aspects of the two extreme
clock architectures mentioned above: laser cooling (as used in QuASAR
optical clocks) and microwave hyperfine transitions (as used in CSAC).
Alternative strategies will also be considered if sufficiently justified.
Special attention will need to be focused on reducing the power
requirements of the requisite lasers, microwave sources, and local
oscillators. Furthermore, the final device should be robust to
environmental fluctuations (e.g. temperature, magnetic field, vibration) in
a relevant operating environment.



PHASE I: Develop an initial design and model key elements of the proposed
clock. The chosen work must be compatible with a fractional frequency
stability of  10^-12 at 1 second averaging and  5x10^-15 for 1 day of
averaging. It should have a size  1 L, weight  1 kg, and power
consumption  5 W. Develop a detailed analysis of the predicted performance
in a relevant environment accounting for expected environmental
fluctuations such as temperature, magnetic field, and vibration
fluctuations. Exhibit the feasibility of the approach through a laboratory
demonstration of critical components. Phase I deliverables will include a
design review including expected device performance and a report presenting
the plans for Phase II.



DIRECT TO PHASE II - Offerors interested in submitting a Direct to Phase II
proposal in response to this topic must provide documentation to
substantiate that the scientific and technical merit and feasibility
described in the Phase I section of this topic has been met and describes
the potential commercial applications. Documentation should include all
relevant information including, but not limited to: technical reports, test
data, prototype designs/models, and performance goals/results. Read and
follow Section 4.0 of the DARPA Instructions



PHASE II: Construct and demonstrate a prototype device validating the
device performance outlined in Phase I. The Transition Readiness Level to
be reached is 5: Component and/or bread-board validation in relevant
environment.



PHASE III: The low SWaP of the clock developed in this program should
enable widespread