Re: [time-nuts] Any reason not to use one power amplifier and splitter for distribution amplifier?
Hi, I was doing some phase noise measurements today at a friends place. The Rapco 1804M was about -110 dBc/Hz at 10 kHz. It was 30 dB higher up from the HP5065A, which was some 10 dB higher than the BVA. On the other hand, when viewing the ADEV and TDEV, it became apparent that the Rapco has around 1 ps RMS noise at 1 s, and few counters will be affected by that noise. Just to put it in context. So, one should at least ponder about where the noise contributions is and what value it brings to go for a quieter distribution amp, and for what in (additional) cost. Cheers, Magnus On 01/06/2015 01:59 AM, Bob Camp wrote: Hi Any time you run into terms like “low noise” it pays to think about what that means to you and your system. A quick scan of the posts here over the years will show that different definitions of low noise do exist. The same is true of system requirements. An offset that matters to one may have no impact at all on another system. In some cases -155 dbc/Hz at 10KHz or 100 KHz is “low noise”. In other cases “low noise” is -180 dbc/Hz. In either case, *delivering* a clean signal without spurs and crud is far from simple. In many long cable run cases, the cost of fancy cables, high performance magnetics, and all the other “stuff” is more than the cost of simply locking up a quiet oscillator on the end of a “dirty” cable. I don’t think I’ve ever seen a setup that tries / needs to “distribute” -170 dbc/Hz signals over anything bigger than a rack. I’ve seen *lots* of systems that regenerate those sort of signals many times over (= in many different boxes) to get around distributing them. Bob On Jan 5, 2015, at 2:15 PM, Tom Knox act...@hotmail.com wrote: Happy New Years All! I have seen a number of discussions on various approaches to distribution amps discussed on Time-Nuts ranging from DYI to products intended for Video. I thought I my weigh in with one point of interest; It seems like long term performance is pretty easy, but a low phase noise solution is quite a different story. Looking at the number of application specific products from MicroSemi/Symmetricom and other manufactures claimed and even more so real world specs vary a great deal so apparently it s not easy to just throw something together with great or even good close in phase noise. So depending on your labs direction in the future it may be worth researching and investing in an application specific distribution amp. I like the MicroSemi 4036B but there are a number of very good products out there on the surplus market selling for a small fraction of their original cost. Cheers; Thomas Knox From: bill.ric...@verizon.net To: time-nuts@febo.com Date: Sun, 4 Jan 2015 08:29:34 -0500 Subject: Re: [time-nuts] Any reason not to use one power amplifier and splitter for distribution amplifier? A cheap and dirty equivalent of a pass thru terminator that I use is a BNC t connector with a 52 ohm bnc terminator. I guess you could use a CATV 75 ohm F type with an adapter. Maybe that combination would produce too much garbage. 73, Bill, WA2DVU Cape May --- This email has been checked for viruses by Avast antivirus software. http://www.avast.com ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Any reason not to use one power amplifier and splitter for distribution amplifier?
Good point Bob, in my humble opinion Low Noise is about -115 @ 1 Hz dropping to about -165 @ 10KHz for 5 MHz about 3dB higher for 10MHz. Which from my testing will tax the noise floors of a fair number of application specific products. It is true that most of these distribution amps sold today were designed at least a decade ago, so there may be chips today that can meet or exceed those products on paper for DIY projects but it will still be a challenge for most of us. Thanks for your input Thomas Knox From: kb...@n1k.org Date: Mon, 5 Jan 2015 19:59:39 -0500 To: time-nuts@febo.com Subject: Re: [time-nuts] Any reason not to use one power amplifier and splitter for distribution amplifier? Hi Any time you run into terms like “low noise” it pays to think about what that means to you and your system. A quick scan of the posts here over the years will show that different definitions of low noise do exist. The same is true of system requirements. An offset that matters to one may have no impact at all on another system. In some cases -155 dbc/Hz at 10KHz or 100 KHz is “low noise”. In other cases “low noise” is -180 dbc/Hz. In either case, *delivering* a clean signal without spurs and crud is far from simple. In many long cable run cases, the cost of fancy cables, high performance magnetics, and all the other “stuff” is more than the cost of simply locking up a quiet oscillator on the end of a “dirty” cable. I don’t think I’ve ever seen a setup that tries / needs to “distribute” -170 dbc/Hz signals over anything bigger than a rack. I’ve seen *lots* of systems that regenerate those sort of signals many times over (= in many different boxes) to get around distributing them. Bob On Jan 5, 2015, at 2:15 PM, Tom Knox act...@hotmail.com wrote: Happy New Years All! I have seen a number of discussions on various approaches to distribution amps discussed on Time-Nuts ranging from DYI to products intended for Video. I thought I my weigh in with one point of interest; It seems like long term performance is pretty easy, but a low phase noise solution is quite a different story. Looking at the number of application specific products from MicroSemi/Symmetricom and other manufactures claimed and even more so real world specs vary a great deal so apparently it s not easy to just throw something together with great or even good close in phase noise. So depending on your labs direction in the future it may be worth researching and investing in an application specific distribution amp. I like the MicroSemi 4036B but there are a number of very good products out there on the surplus market selling for a small fraction of their original cost. Cheers; Thomas Knox From: bill.ric...@verizon.net To: time-nuts@febo.com Date: Sun, 4 Jan 2015 08:29:34 -0500 Subject: Re: [time-nuts] Any reason not to use one power amplifier and splitter for distribution amplifier? A cheap and dirty equivalent of a pass thru terminator that I use is a BNC t connector with a 52 ohm bnc terminator. I guess you could use a CATV 75 ohm F type with an adapter. Maybe that combination would produce too much garbage. 73, Bill, WA2DVU Cape May --- This email has been checked for viruses by Avast antivirus software. http://www.avast.com ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] schematics of frequency counter
Hi
On Jan 5, 2015, at 6:33 PM, Li Ang lll...@gmail.com wrote:
Hi Bob,
There are 2 oscillator on board, one 8MHz for MCU one 125MHz for FPGA.
I've took it down from the board, and changed MCU to use internal RC
oscillator for MCU and PLL to mutilply refclk to 200MHz for FPGA.
I will try do the same test tonight thanks.
Most counters use 10 MHz as a reference. A sneaky trick is to use that exact
same signal as the MCU clock and as the ref clock input to the FPGA’s PLL. It
keeps the spurs all “in step” with each other and helps to line up the timing
between the MCU and FPGA data. Because of delays, it’s not a perfect solution
to the lineup stuff, unless you play with the timing file. It certainly can
help with spurs.
Bob
2014-12-29 4:35 GMT+08:00 Bob Camp kb...@n1k.org:
Hi
On Dec 28, 2014, at 9:19 AM, Li Ang lll...@gmail.com wrote:
Hi Bob,
I did some test according to your suggestions. DUT is a symmetricom x72
rb oscillator. Also, I've tried signal generator as the DUT. RS SMY01 is
not as good as HP8662A but that the best I've got. The signal geneator is
also using FE5650 as ref clock.
According to my test with the TDC today, this unit is not producing
very
stable data.
I don't have accurate pulse generator, so this is how I test the TDC:
0) power the board with battery.
1) use FPGA to generate time pulse:
reg [15:0] shift;
always @(posedge refclk10M) begin
shift = {shift[14:0], sw_gate};
end
assign tdc_start = shift[3];
assign tdc_stop1 = shift[5];
2) use MCU to pull down sw_gate, the FPGA sync it to refclk10M domain and
generate input signal for TDC.
3) use TDC to test the time betwen tdc_start and tdc_stop1
The result is in tdc_test.zip. number * 100ns = time between tdc_start
and
tdc_stop1. (TDC highspeed clock is refclk10M/2).
There 2 issues from the test:
1) As we can see from the data, the number is around 1.98x not 2.00x. So
there is about 2ns delay between tdc_start and tdc_stop1 for this simple
test code. If it is from the PCB trace and something inside FPGA, this
part
should be a constant value at certain temperature.
So far all correct. If you are using Quartus, you can fire up the timing
analyzer and take a look at what it guesses for timing / delay on the
pulse. It is not a perfect number, but I’d bet it will confirm that the 2
ns does come from the FPGA.
I can calculate it by
measuring 2 cycles and 3 cylces. My current code has not implement this
part, it should provide some improvement. 2ns time error for 1s gate,
that
is something.
The delay probably is from the input / output fabric on the FPGA ( =
output driver). The test you propose should demonstrate this.
2) For a 90ps TDC, I think the result should be something like +-0.001
cycle. But I get something like +-0.003 cycle. I do not know the reason
for
now.
Two reasonable *guesses* would be crosstalk and noise.
1) If there are any other clocks running around during this test, I’d see
if they can be shut down. Things like an free running OCXO are good for
this - they are easy to isolate.
2) Noise could be internal to the TDC. If it’s 90 ns at one sigma, then
you will indeed see +’/- 3 X that (or more) depending on how long you watch
it. At least by my math the one sigma on the data is 149 ps. That’s a bit
over 90 ps, but not terribly far.
Delaying the signals relative to each other (clock and output) as Magnus
suggests in another post is probably a real good idea for sorting some of
this out.
Bob
2014-12-27 22:58 GMT+08:00 Bob Camp kb...@n1k.org:
Hi
(In reply to several posts. It’s easier for me this way)
Ok, that’s good news !!! (and useful data)
Your counter performance degraded a bit when you put in 5 db and not
much
when you put in 8 db.
It’s also maybe *too* good news. I suspect that cross talk between the
channels may be impacting your results.
Next step is to try it with two independent sources and a bit more
attenuation. When you try it with two sources, you need to attenuate
first
one source and then switch the attenuators to the other source. That
will
help you see if crosstalk from one channel is more of a problem than
from
the other channel.
One parts hint:
Cable TV attenuators are much cheaper than their fancy 50 ohm
MIniCircuits
cousins. They are also something you can pick up down at the corner
electronics store. For this sort of testing they are perfectly fine to
use.
At this point in the testing the mismatch between 75 ohms and 50 ohms is
not a big deal. You will need to adapt connectors, but you probably
still
will save money.
===
Op-amps that have enough bandwidth and performance for a high input
impedance counter input are rare items. They also are not cheap. Often
they
come as some sort of current feedback part with low(er) input
impedance. If
you want your counter to work to 300 MHz, it should accept a 300 MHz
square
wave. That
Re: [time-nuts] schematics of frequency counter
Hi,
If you have a stable delay of 198 ns, and we can't figure out why it is
bad, bad, bad, then just calibrate it and compensate for it.
I would be curious to figure out where it is. I don't have the full
system insight right now. It sounds like you need two coarse count
cycles (I think you said it was 100 ns) and then remaining difference
would be start-to-stop difference of about 2 ns.
Cheers,
Magnus
On 01/06/2015 12:26 AM, Li Ang wrote:
Hi
I've confirmed that it's 198ns between start and stop with my racal dana
1992. I've spent days to learn how to compensate this 2ns in Quartus.
However, it's not something easy for me to do. I will ask some
hardware colleague for help.
Two days ago, I assembled my 2 mv89a to PCB ,put them into 2 metal
boxes. The test time is longer than before since it's in the holiday. These
data confused me more. I got bigger frequency difference if sig=ref.
Things are getting more and more compilcated. :(
raw data: http://www.qsl.net/bi7lnq/freqcntv4/test/20150105/0105.zip
Thanks
2014-12-29 4:35 GMT+08:00 Bob Camp kb...@n1k.org:
Hi
On Dec 28, 2014, at 9:19 AM, Li Ang lll...@gmail.com wrote:
Hi Bob,
I did some test according to your suggestions. DUT is a symmetricom x72
rb oscillator. Also, I've tried signal generator as the DUT. RS SMY01 is
not as good as HP8662A but that the best I've got. The signal geneator is
also using FE5650 as ref clock.
According to my test with the TDC today, this unit is not producing
very
stable data.
I don't have accurate pulse generator, so this is how I test the TDC:
0) power the board with battery.
1) use FPGA to generate time pulse:
reg [15:0] shift;
always @(posedge refclk10M) begin
shift = {shift[14:0], sw_gate};
end
assign tdc_start = shift[3];
assign tdc_stop1 = shift[5];
2) use MCU to pull down sw_gate, the FPGA sync it to refclk10M domain and
generate input signal for TDC.
3) use TDC to test the time betwen tdc_start and tdc_stop1
The result is in tdc_test.zip. number * 100ns = time between tdc_start
and
tdc_stop1. (TDC highspeed clock is refclk10M/2).
There 2 issues from the test:
1) As we can see from the data, the number is around 1.98x not 2.00x. So
there is about 2ns delay between tdc_start and tdc_stop1 for this simple
test code. If it is from the PCB trace and something inside FPGA, this
part
should be a constant value at certain temperature.
So far all correct. If you are using Quartus, you can fire up the timing
analyzer and take a look at what it guesses for timing / delay on the
pulse. It is not a perfect number, but I’d bet it will confirm that the 2
ns does come from the FPGA.
I can calculate it by
measuring 2 cycles and 3 cylces. My current code has not implement this
part, it should provide some improvement. 2ns time error for 1s gate,
that
is something.
The delay probably is from the input / output fabric on the FPGA ( =
output driver). The test you propose should demonstrate this.
2) For a 90ps TDC, I think the result should be something like +-0.001
cycle. But I get something like +-0.003 cycle. I do not know the reason
for
now.
Two reasonable *guesses* would be crosstalk and noise.
1) If there are any other clocks running around during this test, I’d see
if they can be shut down. Things like an free running OCXO are good for
this - they are easy to isolate.
2) Noise could be internal to the TDC. If it’s 90 ns at one sigma, then
you will indeed see +’/- 3 X that (or more) depending on how long you watch
it. At least by my math the one sigma on the data is 149 ps. That’s a bit
over 90 ps, but not terribly far.
Delaying the signals relative to each other (clock and output) as Magnus
suggests in another post is probably a real good idea for sorting some of
this out.
Bob
2014-12-27 22:58 GMT+08:00 Bob Camp kb...@n1k.org:
Hi
(In reply to several posts. It’s easier for me this way)
Ok, that’s good news !!! (and useful data)
Your counter performance degraded a bit when you put in 5 db and not
much
when you put in 8 db.
It’s also maybe *too* good news. I suspect that cross talk between the
channels may be impacting your results.
Next step is to try it with two independent sources and a bit more
attenuation. When you try it with two sources, you need to attenuate
first
one source and then switch the attenuators to the other source. That
will
help you see if crosstalk from one channel is more of a problem than
from
the other channel.
One parts hint:
Cable TV attenuators are much cheaper than their fancy 50 ohm
MIniCircuits
cousins. They are also something you can pick up down at the corner
electronics store. For this sort of testing they are perfectly fine to
use.
At this point in the testing the mismatch between 75 ohms and 50 ohms is
not a big deal. You will need to adapt connectors, but you probably
still
will save money.
===
Op-amps that have enough bandwidth and performance for a high input
impedance counter input are rare
Re: [time-nuts] schematics of frequency counter
Hi On Jan 5, 2015, at 6:26 PM, Li Ang lll...@gmail.com wrote: Hi I've confirmed that it's 198ns between start and stop with my racal dana 1992. I've spent days to learn how to compensate this 2ns in Quartus. However, it's not something easy for me to do. It’s not something that anybody I know finds easy to do. The constraints in the sdc file are not as easy to work with as they could be. The Altera people are using a language that was defined by others. I find that many of the definitions are backwards from the way one would expect them to be. Their older timing approach was easier to understand, but it was not “industry standard”. I will ask some hardware colleague for help. Expect to buy them lunch. Hardware people are always hungry when asked for favors :) I’d bet the timing stuff is not something they enjoy doing either. Two days ago, I assembled my 2 mv89a to PCB ,put them into 2 metal boxes. Each box with it’s own power supply or both on one supply? Because of the high current draw of the OCXO, two supplies (even wall wart ones) are better than a single common supply. The test time is longer than before since it's in the holiday. These data confused me more. I got bigger frequency difference if sig=ref. That is a bit weird. Things are getting more and more compilcated. :( I would check the splitter and cables first. It may be something fairly simple (like a loose ground). Bob raw data: http://www.qsl.net/bi7lnq/freqcntv4/test/20150105/0105.zip Thanks 2014-12-29 4:35 GMT+08:00 Bob Camp kb...@n1k.org: Hi On Dec 28, 2014, at 9:19 AM, Li Ang lll...@gmail.com wrote: Hi Bob, I did some test according to your suggestions. DUT is a symmetricom x72 rb oscillator. Also, I've tried signal generator as the DUT. RS SMY01 is not as good as HP8662A but that the best I've got. The signal geneator is also using FE5650 as ref clock. According to my test with the TDC today, this unit is not producing very stable data. I don't have accurate pulse generator, so this is how I test the TDC: 0) power the board with battery. 1) use FPGA to generate time pulse: ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] schematics of frequency counter
Actually, I dont want to ask my colledge for help. Everytime ,for each guy I ask for help, I need expain the entire system and principle of a frequency counter to him. They just keep asking questions instead of answering mine. In defense of the hardware guys, there are a lot of questions that NEED to be asked (and answered) before a design that fulfills your requirements can even be attempted. I don't mean to be unkind, but you skipped all of those questions, designed the software, and now you want someone to hand you a hardware design that solves the problems you are having. From what I can tell, you still don't even have a good concept of what the hardware needs to do, much less how to specify these needs as coherent project requirements -- and even less how to actually design the circuitry you need. Furthermore, when someone suggests something that might fix a glaring error in your design, you say you can't do that because (for example) PNP transistors are too expensive. Ask any competent engineering manager and you will learn that good analog design engineers are the rarest and hardest to find development team members, and that getting the hardware right is very often the hardest part of any design (note that I did not say, most time-consuming -- rather, hardest). So, now you need the analog hardware for your counter, and you have the mistaken impression that it shouldn't be any effort at all. Hopefully, you are now beginning to understand that at least as much good thinking needs to go into the hardware as into the software. And hopefully, you have reviewed the analog circuitry of some good commercial designs to see what sorts of things good analog designers have done in the past to solve the same problems you are facing. You said yourself that you don't really know anything about analog design, and your existing circuit and your comments here on the list show that to be an honest and true assessment. But you also have resisted advice you have gotten from experienced analog designers, and now you say you can't even be bothered to answer the questions of people who would try to help you! At this point, I'm afraid that whatever is posted on this thread isn't really going to help you improve on what you have -- it is just so much wasted internet bandwidth. You need to learn at least enough about analog design to ask and answer intelligent questions about your needs, and you need to be willing to consider the advice you receive, before any of this can help you. Best regards, Charles ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] VC-OCXO EFC stability.
Hi, With a multiturn pot and a 78L05 I can get a 0 to 5V EFC to tune an OCXO on desired freq. But... maybe other voltage regulators or other scheme have better temp stability than the old 78L05. Before I crawl lost in new'ish fancy regulator land does anybody know the killer solution/IC for this job ? Luis Cupido ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] June 30 2015 leap second
Hello,
As I am in the process of creation of my own Nixie clocks. And it
probably good time frame to clarify one thing about leap seconds. In my
project I am using GPS module as an option to have current UTC time and
also to have 1PPS signal to do auto-adjustment for external RTC module.
The question is how usually GPS modules handle leap seconds ? Is it
satelates who send UTC time to GPS module or GPS module has firmware
with leap second information hard-coded ?
The same question is for UNIX epoch time. How computers knows if it is
necessary to add leap seconds ? Lets say I am using very simple script
to calculate UNIX time for specified date:
#!/usr/bin/perl
use Time::Local;
my ($d, $m, $y);
my $time;
@myYears = ('01/06/2000', '01/06/2015', '01/06/2038', '01/06/3000');
foreach (@myYears) {
($d, $m, $y) = split '/', $_;
$time = timelocal(0,0,0,$d,$m-1,$y);
printf %ld\n\r, $time;
}
==
It will produce the following output:
959832000
1433131200
2158977600
32516740800
I am not sure if its take leap second consideration. Most likely not.
And that means its only accurate for the present and pas time. Right ?
For my clock I already implement the function for the leap second and I
am able to add/remove number of seconds from the time I receiving from
GPS or any other source. But it will be more inetersting if clock could
do it automagically and shows me that famous 60 number without human
interaction. Any advise for this ? Thanks !
Regards,
V.P.
On , Tom Van Baak wrote:
Just announced: there will be a positive leap second at the end of
June 30 2015 UTC (that's Wednesday July 1st for most of the world).
As usual we time nuts will have a leap second party -- where we
capture and share the magic hh:59:60 display on as many different
clocks and instruments as possible.
/tvb
More info:
ftp://hpiers.obspm.fr/iers/bul/bulc/bulletinc.dat
http://hpiers.obspm.fr/eop-pc/
And for those of you who want to know how long each day really is:
ftp://hpiers.obspm.fr/iers/bul/bulb_new/bulletinb.dat
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and follow the instructions there.
--
WBW,
V.P.
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Re: [time-nuts] Any reason not to use one power amplifier and splitter for distribution amplifier?
On 4 January 2015 at 02:37, Bob Camp kb...@n1k.org wrote: Hi On Jan 3, 2015, at 6:09 PM, Dr. David Kirkby (Kirkby Microwave Ltd) drkir...@kirkbymicrowave.co.uk wrote: I was looking to make a 10 MHz distribution amp to feed test equipment with the output of a GPSDO. I see this http://m.ebay.com/itm/201244302355 16-way Minicircuits splitter on eBay which I got for $40. I guess the loss is around 12 dB. I actually bought another for $35 which was similar but one of them, the isolation data made no sense, so given their low cost I just bought both. I suspect internally these 16 way units might have a pair of 8 way dividers as there are two isolation figures, depending on what ports one is measuring between Is there any reason not to just drive that with 22 dBm or so of power to get 10 dBm at each of 16 ports? the reason for that hassle is to better isolate the outputs. The splitter has good isolation only when all the ports are properly matched. In the case of a “40 db isolation splitter” that can mean the terminations all have 40 db return loss. I bought two of these splitters. One covers 1-30 MHz, the other one 5-200 I think. Anyway, the 1-30 MHz one arrived today, the Minicircuits ZFSC-16-3. I had my VNA on, which unfortunately does not drop down to 10 MHz, or even 30 MHz, as its lower limit is 50 MHz. So I admit these results are a bit shaky, as I'm using the splitter outside its range. But that said, There seems to a reasonable amount of isolation at 50 MHz, even when all other ports are open. At 50 MHz, the loss from the common port is 12.8 dB, and the isolation between two ports sets of ports is either 38 or 48 dB, depending on what ports are chosen. BUT it appears to be improving as one goes lower in frequency. The Minicircuits data sheet makes it clear there are two sets of isolation figures. I'm pretty sure internally this is likely to be a pair of 8-way splitters. When the other splitter is here, I will use another VNA that covers 300 kHz to 9 GHz, and so make some measurements at 10 MHz on both of them. But I just happened to have this VNA calibrated in N, and so done a few quick and dirty measurements. I've made no allowances for losses of cables. So although I admit these measurements are not well done, but I'm not so convinced now that the terminations on the unused ports matters a huge amount. I looks to me that this unit might well exceed 40 dB isolation on all ports at 10 MHz, as all the graphs are sloping in the right direction. Dave common-to-port-7-others-open-S21-magnitude.pdf Description: Adobe PDF document port1-to-port-7-Common=50Ohm-others=open-S21-magnitude.pdf Description: Adobe PDF document port7-to-port-8-Common=50Ohm-others=open-S21-magnitude.pdf Description: Adobe PDF document ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Any reason not to use one power amplifier and splitter for distribution amplifier?
Dave wrote: At 50 MHz, the loss from the common port is 12.8 dB, and the isolation between two ports sets of ports is either 38 or 48 dB To get the worst-case output-to-output isolation, you need to test two output ports that are electrically adjacent (i.e., that share the same last 2:1 splitter, assuming that the 1:16 is a hierarchy of 1:2 splitters -- which is the case with the multi-output splitters I'm familiar with). You may already have found an electrically-adjacent pair (ports 7 and 8), but to be absolutely sure, you would need to repeat the test from one output to each of the 15 others (or find a full internal connection diagram, which does not seem to be on the datasheet). If it is a hierarchy of 1:2 splitters, you are correct that it is effectively two, 1:8 splitters. In that case, each output port on one of the 1:8 splitters is electrically equidistant from all of the output ports on the other 1:8 splitter. But the same is not true of the output ports of just one of the 1:8 splitters. In that case, there is one adjacent output port, two output ports at one remove, and four output ports twice removed. The isolation is generally worst between adjacent outputs, and better at each remove. It is logical to think that the adjacent output ports are 1-2, 3-4, ... 7-8, ... and 15-16 -- but this may not be the case. I wouldn't bother retesting with out-of-band signals, but when you test at 10MHz it is something to think about. Best regards, Charles ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] VC-OCXO EFC stability.
Hi Bob, That is the issue, it doesn't. (the 2,3 different types I would like to use none of them have it, so I will be making a small pcb with the trimpot and the regulator and some capacitors etc). Luis Cupido. ct1dmk On 1/7/2015 1:09 AM, Bob Stewart wrote: Does your oscillator have a VRef output? If so, use that instead of a regulator. It's cleaner and usually temperature compensated. Bob From: ct1dmkct1...@gmail.com To: Discussion of precise time and frequency measurementtime-nuts@febo.com Sent: Tuesday, January 6, 2015 6:40 PM Subject: [time-nuts] VC-OCXO EFC stability. Hi, With a multiturn pot and a 78L05 I can get a 0 to 5V EFC to tune an OCXO on desired freq. But... maybe other voltage regulators or other scheme have better temp stability than the old 78L05. Before I crawl lost in new'ish fancy regulator land does anybody know the killer solution/IC for this job ? Luis Cupido ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] VC-OCXO EFC stability.
Does your oscillator have a VRef output? If so, use that instead of a regulator. It's cleaner and usually temperature compensated. Bob From: ct1dmk ct1...@gmail.com To: Discussion of precise time and frequency measurement time-nuts@febo.com Sent: Tuesday, January 6, 2015 6:40 PM Subject: [time-nuts] VC-OCXO EFC stability. Hi, With a multiturn pot and a 78L05 I can get a 0 to 5V EFC to tune an OCXO on desired freq. But... maybe other voltage regulators or other scheme have better temp stability than the old 78L05. Before I crawl lost in new'ish fancy regulator land does anybody know the killer solution/IC for this job ? Luis Cupido ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] June 30 2015 leap second
Here's a nixie clock using javascript. It includes a leap second count down
which is now active:
http://leapsecond.com/java/nixie.htm
For your project, any GPS module with 1PPS output is a start. Those with NMEA
output are problematic. First, there is no advanced notice that a leap second
is pending in standard NMEA sentences. Second, some GPS receivers cheat and
output a double 23:59:59 or a double 00:00:00 instead of a true 23:59:60 for a
positive leap second. Third, the NMEA timestamp follows the 1PPS instead of
leads so you only find out too late that there was a leap second.
To get it right, you'll need two external switches that the user can flip to
indicate that a leap second should be applied at the end of the current
calendar month and what sign the leap second is (insert or delete). The state
should be reset after the leap second to avoid an accidental leap second the
next day or next month. This is what modern atomic clocks like the hp 5071A or
FTS 4065B do.
Better GPS receivers, like Oncore, M12, TBolt, and ublox provide a binary
interface and from this you get the leap second warning bits without resorting
to switches. This is the preferred automagic solution.
Note also that leap seconds are applied at UTC midnight, so if your Nixie clock
displays local time, including daylight saving time, you have to take this into
account. For me the local leap second is 15:59:60 PST or 16:59:60 PDT.
The UNIX epoch time and leap seconds is a can of worms. It's best to think of
time_t as a vintage, convenient, compact, binary integer encoding to/from a
readable, portable, ascii string -mm-dd hh:mm:ss that works most of the
time except when it doesn't. Your perl script will work, except for leap
seconds.
All the external RTC modules I've seen are incompatible with leap seconds. The
same is true for any analog clock display (wrist watches, wall clocks).
Big Ben handles leap seconds by adjusting the pendulum rate by an equivalent of
12 ppm a day before the leap. Google handles leap seconds in a similar way:
http://news.bbc.co.uk/2/hi/science/nature/7792436.stm
http://googleblog.blogspot.com/2011/09/time-technology-and-leaping-seconds.html
Most computers don't know if there will be a leap second (and don't care). If
you run NTP you get some low level support for leap seconds, but even still
most UNIX and Windows software is incapable of displaying or parsing the
23:59:60 leap second correctly.
/tvb
- Original Message -
From: d0ct0r t...@patoka.org
To: Discussion of precise time and frequency measurement time-nuts@febo.com
Sent: Tuesday, January 06, 2015 1:01 PM
Subject: Re: [time-nuts] June 30 2015 leap second
Hello,
As I am in the process of creation of my own Nixie clocks. And it
probably good time frame to clarify one thing about leap seconds. In my
project I am using GPS module as an option to have current UTC time and
also to have 1PPS signal to do auto-adjustment for external RTC module.
The question is how usually GPS modules handle leap seconds ? Is it
satelates who send UTC time to GPS module or GPS module has firmware
with leap second information hard-coded ?
The same question is for UNIX epoch time. How computers knows if it is
necessary to add leap seconds ? Lets say I am using very simple script
to calculate UNIX time for specified date:
#!/usr/bin/perl
use Time::Local;
my ($d, $m, $y);
my $time;
@myYears = ('01/06/2000', '01/06/2015', '01/06/2038', '01/06/3000');
foreach (@myYears) {
($d, $m, $y) = split '/', $_;
$time = timelocal(0,0,0,$d,$m-1,$y);
printf %ld\n\r, $time;
}
==
It will produce the following output:
959832000
1433131200
2158977600
32516740800
I am not sure if its take leap second consideration. Most likely not.
And that means its only accurate for the present and pas time. Right ?
For my clock I already implement the function for the leap second and I
am able to add/remove number of seconds from the time I receiving from
GPS or any other source. But it will be more inetersting if clock could
do it automagically and shows me that famous 60 number without human
interaction. Any advise for this ? Thanks !
Regards,
V.P.
On , Tom Van Baak wrote:
Just announced: there will be a positive leap second at the end of
June 30 2015 UTC (that's Wednesday July 1st for most of the world).
As usual we time nuts will have a leap second party -- where we
capture and share the magic hh:59:60 display on as many different
clocks and instruments as possible.
/tvb
More info:
ftp://hpiers.obspm.fr/iers/bul/bulc/bulletinc.dat
http://hpiers.obspm.fr/eop-pc/
And for those of you who want to know how long each day really is:
ftp://hpiers.obspm.fr/iers/bul/bulb_new/bulletinb.dat
Re: [time-nuts] Any reason not to use one power amplifier and splitter for distribution amplifier?
Just to say, the comment on the graphs that the VNA covers 50 MHz to 20 MHz, is obviously wrong. My 8720D covers 50 MHz to 20 GHz. I do have another couple of VNAs here that cover 10 MHz. I will do some more measurements, with a more suitable VNA when I have both splitters here and some time for something that's not a high priority. I am not yet writing off the possibility of using the power amp and one of these 16-way splitters, as I probably have enough bits in my junk box to do it; and my initial observations are that the isolation doesn't depend too much on the terminations on unused ports. Bob questioned the need for 16 ports. I counted up and I have 9 bits of test kit which take an external reference. So having 16 ports, while nearly double I need now, is not so grossly over the top. Dave ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] June 30 2015 leap second
On 7 Jan 2015 00:23, d0ct0r t...@patoka.org wrote: Hello, The same question is for UNIX epoch time. How computers knows if it is necessary to add leap seconds ? During the event, the kernel raw time (assuming UTC) will go from 23:59:58.9 straight to 00:00:00.0 when removing a leap second, and when inserting one, Linux for example will go 23:59:59.9 to 23:59:59.0 again. The time formatting library functions (aware of leap and time zones) will turn the latter into xx:59:60. As to how the computer knows - some time sync software (NTPd, PTPd etc.), which is made aware of the event from upstream, needs to tell the kernel about this - on systems with the kernel NTP API like Linux, BSDs and others, this is done by setting a respective STA_INS or STA_DEL status flag with ntp_adjtime() or adjtimex(). This can be done in kernel up to 24 hours in advance. When either of the two flags is set, the kernel will trigger the leap event in the last seconds of the current day. GPS should announce the pending leap second not long after the IERS announcement. I haven't checked my clocks yet but it may already be out there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] schematics of frequency counter
Hi Magnus You are right, I could compensate it in the software. I've tried that. The software sets sig=ref=10MHz and measures start-to-stop time t1. Then, it sets sig=ref=5MHz and measures time t2. With t1 t2, I could get the time difference between the start path and the stop path. Repeat it 1000 times every second and get the RMS value of it. I use the RMS value to compensate the result of the following second, but get much worse ADEV chart. I've uploaded the verilog code and schematic to http://www.qsl.net/bi7lnq/freqcntv4/code/freqcnt_v4.zip and http://www.qsl.net/bi7lnq/freqcntv4/freqcnt_bi7lnq_v4.pdf. The idea is from http://n1.taur.dk/permanent/*frequency*measurement.pdf ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] schematics of frequency counter
Hi Bob, Actually, I dont want to ask my colledge for help. Everytime ,for each guy I ask for help, I need expain the entire system and principle of a frequency counter to him. They just keep asking questions instead of answering mine. :( The 2 MV89As are powered by the same power supply right now. Next time I will use dedicated power supply for them. The linear power supply is just too noisy in the night. Using 10MHz as MCU clock is a good idea. Next time I modify the schematic I will make the change. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
