Re: [time-nuts] Fwd: Harmonics suppression in ring oscillators
On Tue, 17 Mar 2015 07:52:07 -0700 Alex Pummer a...@pcscons.com wrote: Hi Attila, just think how all ring/delay line oscillators working: a status change is traveling trough a delay, and after its arrival at the next active component it will release a new status change, which will travel and arrive at the next active component, and after once it will get back to the begin of the loop. Basically time which required to travel between the active devices will determine the frequiency, and --as it now obvious -- the status change can not release new status change at the following active component before arriving to that next active component , therefore self the oscillator can not run at higher frequency that as it determinated by the delays. Of course depending on the wave form at the output of the system you could see many other spectral components Actually, no. If you argue digitally, then you can prove that any odd number of transitions is a valid state of the ring oscillator. There is nothing that a status change will latch on until it comes around again. E.g. consider a ring of 9 inverters. The output state of each inverter could be: 0-1-1-1-0-0-1-1-0- I.e. we have 3 transitions in here, and oscillate at 2 times the fundamental frequency. You can even show that something like 0-1-0-1-0-1-0-1-0- is valid, where the oscillator would oscillate at 4 times the fundamental frequency. If you argue analog (the circuit is better described in the analog domain than in the digital), then you can have even higher modes, as long as the Barkhausen Criterion is fullfiled, which are infintely many, if you disregard the unity gain frequency. Even if you take the limited gain bandwidth product into account, the number of possible harmonics is quite high, especially for longer ring oscillator chains. As i wrote, for delay line oscillators, they usually use frequency dependent components (aka filters) to select one harmonic mode and suppress all others. But for ring oscillators, i have not seen any description where any frequency dependent component was used. All they talk about is a chain of inverters. Attila Kinali -- _av500_ phd is easy _av500_ getting dsl is hard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Harmonics suppression in ring oscillators
Hi, funnily I stumbled across that very question just a few weeks ago while doing my very first ring oscillator designs myself. The explanation I have come to is essentially the following: In principle, you're right, a ring oscillator CAN oscillate at a number of frequencies. Given the way the ring oscillator works, the list of possible fundamental frequencies (not considering the spectrum due to the rectangular waveform with some duty cycle) is essentially given by (1+2k)/(2*n*td), with n being the number of stages (odd integer), td being the time delay of one stage (assuming all stages are identical), and k being any integer between 0 and (n-1)/2. So, an 11 stage ring oscillator could in principle support fundamental frequencies of 1/(22*td), 3/(22*td), 5/(22*td), 7/(22*td), 9/(22*td) and finally 11/(22*td). Which mode actually is triggered depends mainly on circumstances that are pretty hard to tell a priori: How is power applied, what is the mismatch between stages. In the end it boils down to noise triggering one mode or another upon powerup, with some modes being more likely than others due to minute imperfections in manufacturing. The trick here is to have one element in the chain that can be used to create a steady internal state from which oscillation can be started predictably. In the 11 stage ring oscillator mentioned above, that might be a NAND or NOR gate together with 10 inverters. With one input of that NAND or NOR being tied to the output of the chain and the other one being tied to a reset input, which can be used to enable or disable oscillation. A steady state would be reached within 11 gate delays in the sample oscillator mentioned above after DISABLING oscillation. One oscillation is reenabled, it will ONLY oscillate at 1/(22*td). So, as said, the trick is to have the ring oscillator start oscillation from a predetermined state. Does that answer your question? Most likely it answered one and turned up three more ;-) Best regards, Florian Am Tue, 17 Mar 2015 11:28:59 +0100 schrieb Attila Kinali att...@kinali.ch: Hi, I stumbled over something that does not seem to be properly documented anywhere. A ring oscillator (like any delay line oscillator) has an infinte number of poles (on the complex plane), which are on a straight line (disregarding the effect that the transistor acts like a first order low pass filter, as f_t is usually a lot higher than the oscillation frequency). This means that a ring oscillator will always excite more than just one mode and oscillate on multiple frequencies. While for (optical/electrical) delay line oscillators, the way to go is to add a frequency selective element, this is not done for ring oscillators. So, how do people keep ring oscillators from oscillating at higher modes? So far, my google skills have failed me to turn up any answer. Attila Kinali ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Lady Heather
hi i wanted to give a status update on the wining of the lady... from an installation perspective, it has been a study in back to basics: chown vs editing /etc/group and cd Program Files (x86) to get past the (. from the app view, i see that my rooftop antenna leaves a LOT to be desired (the OR coast is very vertical to the east) and large trees close in are bad. i think there is another problem: watching the 10MHz on two counters i see the Hz digit 10,000,00n varying about ten (down for quite a while then back up. perhaps this a caused by the lousy view from the antenna... having only a single sat most of the time leads to a holdover every 15-20 minutes. both counters vary the same way, and only differ be about 2 Hz... so it probably is real. my late-lamented Rb unit was much more stable. the antenna is fixable... it has to be moved from the current location to the highest i can get it off the shop roof. that will take me a while. many thanks to all who helped. dave On Fri, Mar 13, 2015 at 6:19 PM, Adrian Godwin artgod...@gmail.com wrote: The ttyS* devices should be owned by root and be in the dialout group, eg crw-rw---T 1 root dialout 4, 64 Feb 28 08:31 /dev/ttyS0 crw-rw---T 1 root dialout 4, 65 Feb 28 08:31 /dev/ttyS1 crw-rw---T 1 root dialout 4, 66 Feb 28 08:31 /dev/ttyS2 crw-rw---T 1 root dialout 4, 67 Feb 28 08:31 /dev/ttyS3 Rather than chowning them to your username, put your user in the dialout group. On Fri, Mar 13, 2015 at 8:47 PM, Dave Mallery dave.mall...@gmail.com wrote: Lady Heather lives on linux (ubuntu 14-10, amd64)! as usual, the serial line connection to COM1 lived up to its reputation for stubbornness. i have to change the ownership of /dev/ttyS0 back to my username after every boot. previously, i had one of those lil 2-line displays from china. now i am drowning in numbers. did anyone ever document the screen? many thanks dave k5en On Wed, Mar 11, 2015 at 9:07 PM, Dave Mallery dave.mall...@gmail.com wrote: thanks Chuck! i will continue the installation process (new machine with quirks). On Wed, Mar 11, 2015 at 7:11 PM, Chuck Harris cfhar...@erols.com wrote: I Do. She works with wine on linux, and likes it! -Chuck Harris Dave Mallery wrote: hi does anyone have the lady running on WINE under Linux?? On Wed, Mar 11, 2015 at 6:13 PM, Paul Berger phb@gmail.com wrote: I have also used LH with a Thunderbolt 'E' and did not have any issues, however I have not turned on the E for some time now. Paul ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/ mailman/listinfo/time-nuts and follow the instructions there. -- Dave Mallery, K5EN (ubuntu linux 14.10) PO Box 15 Ophir, OR 97464 no gates... no windows! free at last! linux counter #64628 (since 1997) People aren't as dumb as Microsoft needs them to be. --PJ, May 2007 -- Dave Mallery, K5EN (ubuntu linux 14.10) PO Box 15 Ophir, OR 97464 no gates... no windows! free at last! linux counter #64628 (since 1997) People aren't as dumb as Microsoft needs them to be. --PJ, May 2007 ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. -- Dave Mallery, K5EN (ubuntu linux 14.10) PO Box 15 Ophir, OR 97464 no gates... no windows! free at last! linux counter #64628 (since 1997) People aren't as dumb as Microsoft needs them to be. --PJ, May 2007 ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] ADEV noise floor vs counter gate time
How is the counter configured? Are you reading period or frequency? Are you in E? (Every Result) mode, or C? (Continuous Result) mode? The former should give you continuous but independent measurements, while the latter gives heavily overlapped measurements. (For example, with a 100 second gate time, you get one E output every 100 seconds, which covers a different 100-second period than the previous measurement. In C mode, you get one output every 2 seconds, each of which is an estimate from 100 seconds of measurement, but 98 seconds of that data was also part of the previous output and only 2 seconds of new data is included). What does the data returned by the counter actually look like? The manual implies that you always get 10 digits worth of result (not including the exponent) regardless of gate time, but are the values rounded for display in 7, 8, or 9 digits at the shorter gate times, or are they a full 10 digits always? Given any particular value of frequency or period you get, you should be able to reverse-calculate the number of whole cycles of the input signal that the counter used as a gate time, and the number of cycles of 50 MHz timebase that were counted in that period. Since the counter doesn't have interpolators, both of these values should be integers, and so the possible output values are a small subset of all possible 10-digit values for the shorter gate times. For example, if the difference frequency is exactly 90 Hz, the period between two 1 second measurements will be exactly 1 second, and the counter will record 90 cycles of input and 5e7 cycles of timebase, exactly. In frequency mode, the output should be 90.0 Hz exactly, and in period mode the output should be 11. ms. Now suppose that the difference frequency is just a hair slow, enough that 90 cycles of input spans 50,000,001 counts of the timebase. The reported frequency should be 89.9820 Hz and the reported period should be 11.1133 ms. With a 1 s gate time, no values between those are possible unless the values are being rounded (or there is an error in the calculation, which is always possible). Looked at another way, the smallest possible change in the reported period is one timebase clock (20 ns) divided by the number of input cycles in one gate time (90 for 1 s). If the counter is rounding, you may be able to unambiguously figure out what the actual inputs (cycles of input and cycles of timebase) to the calculation were, and use that instead of the rounded value in your calculations. Rounding may round up or down, but if the two oscillators are stable enough the direction can be predominantly up or down for long periods of time, adding a bias to the actual frequency or period you're measuring. (I don't know what effect this bias would have on ADEV). - Dave On Mon, Mar 16, 2015 at 10:15 AM, James via time-nuts time-nuts@febo.com wrote: Hi All, I'm in the process of getting a better counter, but at present I'm using my TTi TF930 counter. For those who don't know it, it is a reciprocal counter which should be continuous, it counts periods in terms of its internal 50MHz clock which I've locked to an external 10MHz reference. There are 4 gate times available, 0.3 secs, 1 sec, 10 secs and 100 secs. These correspond to 7, 8, 9 and 10 digits. I've been experimenting with using a single mixer (mini circuits ZAD+) along with a 1MHz low pass filter and appropriate attenuators to measure Alan Deviation (using my own software). My set up is a 10MHz reference source (MV89A which I've approximately set using a 10kHz GPS signal). The reference is used as the external reference for an Agilent 33522A arbitrary waveform generator. The 33522A generates an 9.10 MHz (10MHz - 90Hz) sine wave at 300mVpp to the mixer and the mixer is also fed by the 10MHz reference output of the 33522A via an attenuator to get it to roughly the same level. The second output of the 33522A generates a 10MHz square wave as a reference for the counter (the counter requires quite a high reference signal and the reference out of the 33522A is too low a voltage to be used directly). I initially ran this with a gate of 1 second and the LOG10(ADEV) curve drops linearly vs LOG10(tau) but then curves back up again. (I tried many variants such as using period rather than frequency and so on.) But when I set the gate time to 10 seconds or 100 seconds then I get both lower curves and ones that no longer curve upwards. The attached pdf shows the three curves on the same graph. What puzzles me is that the counter at longer gates is only averaging to get more digits so the difference must come down to quantization in terms of the number of digits that are passed to the computer over the USB/RS232 link. I find it rather puzzling. James ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to
Re: [time-nuts] ADEV noise floor vs counter gate time
Hi Dave, Thank you for your detailed response. I use the E? command because it returns results at the gate time intervals rather than at the LCD update rate (as you point out). I think that this is working correctly because I get very different file sizes. The numbers are returned as strings of 10 digits - here are some for 1 second gate: 90.6359e+0Hz 90.7591e+0Hz 89.9640e+0Hz 89.8740e+0Hz 90.6007e+0Hz 89.6040e+0Hz 90.8648e+0Hz 90.8472e+0Hz 90.00011465e+0Hz 90.00014459e+0Hz I generally use the frequency mode but I also tried time period and found I got the same curve in essence, which was comforting in a way but showed it wasn't rounding in converting to frequency. The numbers above, on my calculator at least don't exactly match counts of 20 nanosecs. Here are some time period results: 11.11107736e-3s 11.0130e-3s 11.0769e-3s 11.0435e-3s 11.0593e-3s 11.0022e-3s 11.4000e-3s 11.e-3s 11.0370e-3s Again they don't seem to be integer values of 20 nanosec exactly, though quite close. For example 11.11107736E-3/20E-9 = 555,553.868 555,554 x 20E-9 = 11.11108E-3 But I guess what it returns is the ratio of counts within the gate. So 11.11107736E-3 period will occur 90 times in a second (as it is slightly short) and so I should take the ratio: 90 x 11.11107736E-3/20e-9 = 49,999,848.12 so still not quite an integer but if I assume the count (of 50MHz periods) was 49,999,848 and calculate one 90 th of it I get: 49,999,848 x 20E-9/90 = 1.07733 Still not exact agreement. I note that .12 is very close to .125 or 1/8 but I don't know if that is significant. It is probable that it rounds the ratio in binary and then converts to decimal to print out. I've tried assuming 89 periods and 91 periods but still don't get exact integer ratios. Anyway, as I get good agreement between period and frequency measurements at 1 sec, I don't think that it is a rounding issue. I do think it is a quantization issue down to the +/- 20 nanosecs/gate time but I can't quite work it out. I'm currently doing a run at 0.3 secs gate time and I'll see what sort of curve that produces. Tomorrow I should receive my new Tek counter (I went for the fca3100 in the end as I got a very good discount on an ex demo unit) and that should give something to compare (once I've worked out how to program it). James -Original Message- From: Dave Martindale dave.martind...@gmail.com To: jpbridge jpbri...@aol.com; Discussion of precise time and frequency measurement time-nuts@febo.com Sent: Tue, 17 Mar 2015 0:27 Subject: Re: [time-nuts] ADEV noise floor vs counter gate time How is the counter configured? Are you reading period or frequency? Are you in E? (Every Result) mode, or C? (Continuous Result) mode? The former should give you continuous but independent measurements, while the latter gives heavily overlapped measurements. (For example, with a 100 second gate time, you get one E output every 100 seconds, which covers a different 100-second period than the previous measurement. In C mode, you get one output every 2 seconds, each of which is an estimate from 100 seconds of measurement, but 98 seconds of that data was also part of the previous output and only 2 seconds of new data is included). What does the data returned by the counter actually look like? The manual implies that you always get 10 digits worth of result (not including the exponent) regardless of gate time, but are the values rounded for display in 7, 8, or 9 digits at the shorter gate times, or are they a full 10 digits always? Given any particular value of frequency or period you get, you should be able to reverse-calculate the number of whole cycles of the input signal that the counter used as a gate time, and the number of cycles of 50 MHz timebase that were counted in that period. Since the counter doesn't have interpolators, both of these values should be integers, and so the possible output values are a small subset of all possible 10-digit values for the shorter gate times. For example, if the difference frequency is exactly 90 Hz, the period between two 1 second measurements will be exactly 1 second, and the counter will record 90 cycles of input and 5e7 cycles of timebase, exactly. In frequency mode, the output should be 90.0 Hz exactly, and in period mode the output should be 11. ms. Now suppose that the difference frequency is just a hair slow, enough that 90 cycles of input spans 50,000,001 counts of the timebase. The reported frequency should be 89.9820 Hz and the reported period should be 11.1133 ms. With a 1 s gate time, no values between those are possible unless the values are being rounded (or there is an error in the calculation, which is always possible). Looked at another way, the smallest possible change in the reported period is one
[time-nuts] Fwd: PRS10 question - revisiting an old one with an accent on small signal detection
Hi guys, A year ago I posted a question concerning the 1PPS output from my PRS10. I had thought it an anomaly, but other users indicated that the signal profile was common to other units. I have since added 2 PRS10s (actually TDS12s) to my bench and they also show the same profile. Jarl Risum was very helpful in my investigations, and proposed using inverters to get a better shaped signal. I tried this out, but am not satisfied with the induced delay. In the end I settled on an AND gate for the project. In the forwarded mail below (hope the pic passes the censors) you can see the object of my irritattion is that although I have a nicely conditioned output, there is too much delay between the initital 1PPS input rise and the gate response for even mildly afflicted timenut . I couldn’t figure out what the source of this was until I reviewed it the other day with an object of distributing 1PPS over the bench. From looking at 74HC device data sheets I think the issue is that the start of the 1PPS pulse input, (the bit I am interested in) does not reach the trigger level needed for CMOS gates. Does that seem a reasonable assumption?, and if so is there a solution? I am wondering whether I could use a comparator? The trigger level of a LT1719 is better than 6mv but I fear that I might get false triggering as my scope indicates that the 0V level has =2mv noise. I don’t have one to test so I would appreciate your input. I also can’t see how I might implement it if it is worth testing. Regards,Mike Début du message réexpédié : De: mike cook cook.mich...@orange.fr Objet: Rép : PRS10 question Date: 1 mars 2014 16:50:12 UTC+1 À: Jarl Risum jarl.ri...@gmail.com Hi Jarl, Sorry about the late update but I was waiting for parts. I tried using a 74HC04 (I didn't have an HC14 but I only think the they differ in performance) in your suggested config on a separately powered breadboard but that doesn't give me what I want . It just gives a slightly attenuated copy of the original, which is to say I still have the slow rise to vcc after the initial 10ns of good rise. What I was looking for is something that triggers on the first 10ns and then forgets everything else after that, putting vcc on the output, until the input drops to 0, when the output should also go to zero. That is a simple AND operation. How about an AND gate? So I tried a 74HC7001. Now I get 10ns rise to 2V and 20ns to Vcc. There is a bit of overshoot but none of the ringing in the original plus a shorter settling time that I can probably smooth out if I needed. There is as you can see quite a bit of delay which I would need to characterize. However it looks much more usable. Regards, Mike Le 14 févr. 2014 à 16:08, Jarl Risum a écrit : Mike, Thanks for the feedback. OK - the coax cable explains your result so far. You may try an ordinary 10:1 probe directly on the BNC connector on the breakout board, but be careful to check - and if necessary correct - the probe response before use. The probe needs to have at least 100 MHz bandwidth. Your idea to use a buffer attached directly to the BNC connector on the breakout board is of course fine, but you should avoid loading pin 8 with anything except what it is intended for: as a supply to a lab. quality 10 kohm 10 turn potentiometer as an external means to correct the C-field in the Rb Physics Package. Pin 8 is a precision 5V reference also used by the internal 10 turn C-field potentiometer and you are almost sure to disturb the calibration if you load pin 8 with anything else. Please take a look at diagram RB_H1 (10MHz Ovenized Oscillator). The 5V reference circuit is at the top of the page, U100 and U102B. If you do not wish to add a 7805 5V regulator IC to your circuit yourself you might be able to get a few mA's from the 5V regulator on the breakout board. As a final remark I would like to draw your attention to the possibilty of using the 10 MHz output instead to feed a divider chain or a PIC divider which could output the 1 PPS where you need it. This solution would be somewhat more flexible with respect to interface problems since the 10 MHz could be distributed in coax cable over 10's of meters without any problem. Cheers Jarl 2014-02-14 14:57 GMT+01:00 mike cook cook.mich...@orange.fr mailto:cook.mich...@orange.fr: Jarl, Thanks for your tech comments. As far as electronics goes, I don't rise much above the level of a script-kiddie. I have in fact got a 2 meter 50Ohm coax into my scope. I will try to probe the output of the 74H140 to see what that looks like. Rather than use coax to connect in a buffer circuit, I was thinking of a breadboard dongle with BNC male and female connectors soldered to it, maybe slid into a metal tube once tested. I wouldn't be surprised to find it has already been invented. I might be able to steal some
[time-nuts] Harmonics suppression in ring oscillators
Hi, I stumbled over something that does not seem to be properly documented anywhere. A ring oscillator (like any delay line oscillator) has an infinte number of poles (on the complex plane), which are on a straight line (disregarding the effect that the transistor acts like a first order low pass filter, as f_t is usually a lot higher than the oscillation frequency). This means that a ring oscillator will always excite more than just one mode and oscillate on multiple frequencies. While for (optical/electrical) delay line oscillators, the way to go is to add a frequency selective element, this is not done for ring oscillators. So, how do people keep ring oscillators from oscillating at higher modes? So far, my google skills have failed me to turn up any answer. Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Fwd: Harmonics suppression in ring oscillators
Hi Attila, just think how all ring/delay line oscillators working: a status change is traveling trough a delay, and after its arrival at the next active component it will release a new status change, which will travel and arrive at the next active component, and after once it will get back to the begin of the loop. Basically time which required to travel between the active devices will determine the frequiency, and --as it now obvious -- the status change can not release new status change at the following active component before arriving to that next active component , therefore self the oscillator can not run at higher frequency that as it determinated by the delays. Of course depending on the wave form at the output of the system you could see many other spectral components Alexander, Pummer Original Message Subject:[time-nuts] Harmonics suppression in ring oscillators Date: Tue, 17 Mar 2015 11:28:59 +0100 From: Attila Kinali att...@kinali.ch Reply-To: Discussion of precise time and frequency measurement time-nuts@febo.com Organization: Geist To: Discussion of precise time and frequency measurement time-nuts@febo.com Hi, I stumbled over something that does not seem to be properly documented anywhere. A ring oscillator (like any delay line oscillator) has an infinte number of poles (on the complex plane), which are on a straight line (disregarding the effect that the transistor acts like a first order low pass filter, as f_t is usually a lot higher than the oscillation frequency). This means that a ring oscillator will always excite more than just one mode and oscillate on multiple frequencies. While for (optical/electrical) delay line oscillators, the way to go is to add a frequency selective element, this is not done for ring oscillators. So, how do people keep ring oscillators from oscillating at higher modes? So far, my google skills have failed me to turn up any answer. Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
