Re: [time-nuts] GPSDO Question - Clarification Please

2007-09-02 Thread Thomas Linbeck 
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I am confused by the PLL vs. FFL lock discussion.  Does this concern the
Schera board vs. the VE2ZAZ methods of time base discipline?  Can someone
share their thoughts on the subject?
Thanks!
73 de K4TEU (Tom(

-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On
Behalf Of Bruce Griffiths
Sent: Saturday, September 01, 2007 10:19 PM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] GPSDO Question

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JOS Earthlink wrote:
 73 de  K1JOS (Jerry)
 CCA #11906
 CRA #1777





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 Hi Group,

 I just recently completed a GPSDO inside a HP5328A.  I was going to use
the
 Schera board but opted for the VE2ZAZ.  At first I tried to cannibalize
the
 HP5328A's internal power supply for either the +/-15VDC or +5/-5.2VDC
supply
 but I discovered the hard way that they would not supply enough current
 (burnt out CR1 and Q7) or the supplies would not be well regulated.  I
opted
 therefore to include inside the case a +/-12VDC swtiching supply powered
 externally by a 24VDC wall wart.  From the +/-12VDC dual supply I cleaned
up
 the rails with an L7805 and L7905.  I was able to bring out to the the
rear
 panel the 10Mhz and 5Mhz references plus the SMA GPS antenna connector.
On
 the side panel I put in a momentary pushbutton switch to reset the GPS if
 needed plus a DB9 RS232 for serial communicatiosn with either the GPS
using
 software like VisualGPS) or to monitor the VE2ZAZ board status.  A simple
 DPDT switch next to the DB9 connector controls the serial selection.  I
have
 complete pictures if anyone is interested and it works very nicely.

 Jerry
 K1JOS


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Jerry

It is amusing/distressing to see that the myth that using an FLL to lock
an oscillator to the PPS output of a GPS receiver is a good approach
still persists.
The optimum solution is a phase lock loop.
Whilst building an FLL is instructive/educational, if you want the best
GPSDO performance you should really use a PLL.

Bruce

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Re: [time-nuts] GPSDO Question - Clarification Please

2007-09-02 Thread Bruce Griffiths 
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Thomas Linbeck wrote:
 I am confused by the PLL vs. FFL lock discussion.  Does this concern the
 Schera board vs. the VE2ZAZ methods of time base discipline?  Can someone
 share their thoughts on the subject?
 Thanks!
 73 de K4TEU (Tom(

   
Thomas

The discussion is somewhat more general than the Schera (PLL) board
versus the VE2ZAZ (FLL) board.

The Schera board is not the only way to implement an inexpensive PLL.
However don't fall into the trap of locking with a short loop time
constant to the 10KHz output of a Conexant/Navman Jupiter GPS receiver,
it has no better stability than the receivers PPS output.
The Schera board is certainly not (at least with a good modern GPS
timing receiver) the optimum technique for implementing a low cost high
performance GPSDO.
That said, its performance should be considerably better than that of an
FLL implementation using the same OCXO.
It is of course possible, with modern components to implement a
technique somewhat akin to the Schera method with far fewer ICs.

When one is trying to lock an oscillator to a passive atomic standard
(Rubidium absorption cell, Caesium beam tube, mecury ion trap, etc) then
a frequency lock loop is optimum.
In this case a phase lock loop will not work as there is no signal for
the PLL to lock onto. An FLL (using the Pound or similar technique) can
also be used with a passive standard like a  Sapphire whispering gallery
resonator or a quartz passive quartz crystal.

When one has an active frequency standard (hydrogen maser, GPS,
Rubidium, Caesium standard) a PLL is usually the optimum technique.

Bruce

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