Re: [time-nuts] Logging SPAD pulses on synced devices (was: Linux PPS clues?)

2016-11-22 Thread Ilia Platone 

Hi,
Do a SPI bus do this job correctly? I'd have the clock on one line and 
the pulses logged on a second line. Like CLK for clock pulses and 
MOSI/MISO for serial logging of pulses. I'd avoid I2C because of 
addressing packets.


Best Regards,
Ilia


On 11/05/16 04:48, Casey L. Jones wrote:
Yes, you might need a separate dedicated chip to take in the serial 
input steadily. Although you may not. Many serial ports have a small 
buffer to prevent missed serial input when the operating system gets 
distracted with something other than processing serial data.

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Ilia Platone
via Ferrara 54
47841
Cattolica (RN), Italy
Cell +39 349 1075999

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Re: [time-nuts] Logging SPAD pulses on synced devices

2016-11-05 Thread Ilia Platone 
Attached to this mail there are three files: the APD.asc LTSpice4 
simulation schematics, a model for the AD8561 comparator, a model for 
the VN2210 mosfet transistor, and a model for the BF959 bipolar transistor.


Please note that the APD model included into the schematics may have 
errors: I took it from an LTSpice demo and adapted on the APDs I have, 
some Marktech MTAPD, and observations made with them.


Unfortunately the boards have been ordered, but components shortening or 
value editing can be done. (the real value of the capacitor of the psu 
is 47uF, for faster rendering I dropped it to a lower value.


Best Regards,
Ilia.

On 11/05/16 06:10, Bruce Griffiths wrote:

Ilia
Circuit diagrams are  posted here from time to time, so it should be OK.
Bruce

 On Saturday, 5 November 2016 7:02 PM, Ilia Platone  
wrote:
  


  Hi, and thank you for these suggestions.

Currently this project becomes reality (slowly): this kind of
synchronization/grabbing is very interesting, but I need something fast
(I expect the SPAD with active quenching circuitry could output 30ns
pulses, and the quantization frequency I hope to run at is 350/450MHz
range).
Anyway, I found some FPGA code for so fast UART, not difficult to
implement, and using these kind of devices this system you propose can
be built from scratch, including a small buffer.

Can I post an LTSpice drawing for review here describing the active
quenching circuitry?

Best Regards,
Ilia

On 11/05/16 04:48, Casey L. Jones wrote:

Yes, you might need a separate dedicated chip to take in the serial
input steadily. Although you may not. Many serial ports have a small
buffer to prevent missed serial input when the operating system gets
distracted with something other than processing serial data.
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--
Ilia Platone
via Ferrara 54
47841
Cattolica (RN), Italy
Cell +39 349 1075999

.MODEL VN2210 NMOS (LEVEL=3 RS=0.02 NSUB=3.0E15 DELTA=1.0 KAPPA=1.20 TPG=1 
CGDO=1.61E-10 RD=0.03 VTO=1.650 VMAX=5.0E6 ETA=0.053089 NFS=6.6E10 TOX=725E-10 
LD=1.698E-9 UO=862.425 XJ=6.4666E-7 THETA=1.0E-5 CGSO=4.850E-9 L=4.0E-6 W=85E-3)

.MODEL BF959 NPN(IS=10.2e-15 BF=78.00 NF=1.000 VAF=80.50 IKF=60.00m ISE=16.80p 
NE=2.000 BR=4.000 NR=1.000 VAR=12.00 IKR=90.00m ISC=0.000 NC=2.000 RB=2.060 
IRB=0.000 RBM=0.000 RE=515.0m RC=206.0m CJE=1.740p VJE=1.100 MJE=500.0m 
TF=227.0p XTF=0.000 VTF=0.000 ITF=0.000 PTF=0.000 CJC=2.250p VJC=300.0m 
MJC=300.0m XCJC=1.000 TR=158.0n CJS=0.000 VJS=750.0m MJS=0.000 XTB=1.500 
EG=1.110 XTI=3.000 KF=0.000 AF=1.000 FC=500.0m TNOM=27.00)

* AD8561 SPICE Macro-Model Typical Values
* 4/98, Ver. 1.0
* TAM / ADSC
*
* Node assignments
*   non-inverting input
*   |   inverting input
*   |   |   positive supply
*   |   |   |   negative supply
*   |   |   |   |   Latch
*   |   |   |   |   |   DGND
*   |   |   |   |   |   |   Q
*   |   |   |   |   |   |   |   QNOT
*   |   |   |   |   |   |   |   |
.SUBCKT AD8561  1   2   99  50  80  51  45  65
*
* INPUT STAGE
*
*
Q1 4  3 5 PIX
Q2 6  2 5 PIX
IBIAS 99  5 800E-6
RC14 50 1E3
RC26 50 1E3
CL14  6 1E-12
CIN1  2 3E-12
VCM1  99  7 1
D1 5  7 DX
EOS3  1 POLY(1) (31,98) 1E-3 1
*
* Reference Voltage
*
EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5
RREF 98 0 100E3
*
* CMRR=80dB, ZERO AT 1kHz
*
ECM1 30 98 POLY(2) (1,98) (2,98) 0 0.5 0.5
RCM1 30 31 10E3
RCM2 31 98 1
CCM1 30 31 15.9E-9
*
* Latch Section
*
RX 80 51 100E3
E1 10 98 (4,6) 1
S1 10 11 (80,51) SLATCH1
R2 11 12 1
C3 12 98 10E-12
E2 13 98 (12,98) 1
R3 12 13 500
*
* Power Supply Section
*
GSY1 99 52 POLY(1) (99,50) 4E-3 -2.6E-4
GSY2 52 50 POLY(1) (99,50) 3.7E-3 -.6E-3
RSY  52 51 10
*
* Gain Stage Av=250 fp=100MHz
*
G2 98 20 (12,98) 0.25
R1 20 98 1000
C1 20 98 10E-13
D2 20 21 DX
D3 22 20 DX
V1 99 21 DC 0.8
V2 22 50 DC 0.8
*
* Q Output
*
Q3  99 41 46 NOX
Q4  47 42 50 NOX
RB1 43 41 200
RB2 40 42 5E3
CB1 99 41 10E-12
CB2 42 50 5E-12
RO1 46 45 2E3
RO2 47 45 500
EO1 98 43 POLY(1) (20,98) 0 1
EO2 40 98 POLY(1) (20,98) 0 1
*
* Q NOT Output
*
Q5  99 61 66 NOX
Q6  67 62 50 NOX
RB3 63 61 200
RB4 60 62 5E3
CB3 99 61 10E-12
CB4 62 50 5E-12
RO3 66 65 2E3
RO4 67 65 500
EO3 63 98 POLY(1) (20,98) 0 1
EO4 98 60 POLY(1) (20,98) 0 1
*
* MODELS
*
.MODEL PIX PNP(BF=100,IS=1E-16)
.MODEL NOX NPN(BF=100,VAF=130,IS=1E-14)
.MODEL DX D(IS=1E-16)
.MODEL SLATCH1 VSWITCH(ROFF=1E6,RON=500,VOFF=2.1,VON=1.4)
.ENDS AD8561
Version 4
SHEET 1 2888 1012
WIRE 208 0 -592 0
WIRE 1456 0 224 0
WIRE 1936 0 1472 0
WIRE 16 144 -64 144
WIRE 112 144 80 144
WIRE 128 144 112 144
WIRE 1216 144 1072 144

Re: [time-nuts] Logging SPAD pulses on synced devices (was: Linux PPS clues?)

2016-11-05 Thread Bruce Griffiths 
Ilia
Circuit diagrams are  posted here from time to time, so it should be OK.
Bruce 

On Saturday, 5 November 2016 7:02 PM, Ilia Platone  
wrote:
 

 Hi, and thank you for these suggestions.

Currently this project becomes reality (slowly): this kind of 
synchronization/grabbing is very interesting, but I need something fast 
(I expect the SPAD with active quenching circuitry could output 30ns 
pulses, and the quantization frequency I hope to run at is 350/450MHz 
range).
Anyway, I found some FPGA code for so fast UART, not difficult to 
implement, and using these kind of devices this system you propose can 
be built from scratch, including a small buffer.

Can I post an LTSpice drawing for review here describing the active 
quenching circuitry?

Best Regards,
Ilia

On 11/05/16 04:48, Casey L. Jones wrote:
> Yes, you might need a separate dedicated chip to take in the serial 
> input steadily. Although you may not. Many serial ports have a small 
> buffer to prevent missed serial input when the operating system gets 
> distracted with something other than processing serial data.
> ___
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to 
> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
>

-- 
Ilia Platone
via Ferrara 54
47841
Cattolica (RN), Italy
Cell +39 349 1075999

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Re: [time-nuts] Logging SPAD pulses on synced devices (was: Linux PPS clues?)

2016-11-05 Thread Ilia Platone 

Hi, and thank you for these suggestions.

Currently this project becomes reality (slowly): this kind of 
synchronization/grabbing is very interesting, but I need something fast 
(I expect the SPAD with active quenching circuitry could output 30ns 
pulses, and the quantization frequency I hope to run at is 350/450MHz 
range).
Anyway, I found some FPGA code for so fast UART, not difficult to 
implement, and using these kind of devices this system you propose can 
be built from scratch, including a small buffer.


Can I post an LTSpice drawing for review here describing the active 
quenching circuitry?


Best Regards,
Ilia

On 11/05/16 04:48, Casey L. Jones wrote:
Yes, you might need a separate dedicated chip to take in the serial 
input steadily. Although you may not. Many serial ports have a small 
buffer to prevent missed serial input when the operating system gets 
distracted with something other than processing serial data.

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To unsubscribe, go to 
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts

and follow the instructions there.



--
Ilia Platone
via Ferrara 54
47841
Cattolica (RN), Italy
Cell +39 349 1075999

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and follow the instructions there.