Hi, I have successfully set up the development environment. Here’s the link: https://pasteboard.co/HboNPNB.png
I am currently reading about issue #39 <https://github.com/timvideos/getting-started/issues/39>, to create a generic debug interface for soft-CPU cores and connect to GDB. Progress so far 1. I read about advanced debug system from openCores <https://opencores.org/usercontent,doc,1270062172>. The document elaborates the debugging system for OpenRisc-1000 Based systems. The document provides information to support debugging both during simulation as well as directly on the hardware. 2. I also read about JTAG and wishbone specifications. The doc illustrates the following diagram to build hardware level debugging system. Queries: 1. Is it acceptable to re-use the above approach implemented by OpenCores given in the attached document? 2. Do we need support for multiple softCPU cores at the same time? Can we use a MUX to switch between different softCPU cores? 3. After looking at the schematic of Numato Opsis board, I think standard JTAG TAP implementation is used. Is that correct? 4. Do I need to implement the project in Migen? 5. I also looked at the documentation of OpenOCD but couldn’t understand how it will be used for the project. Any help on that part? Things to do: 1. To look into the internal working of each module. How each module will interact with one another? 2. How to build an efficient system to support multiple soft-CPU cores? Please provide your valuable suggestions for the project. Thanks Shivam Aggarwal Potential GSOC Student -- You received this message because you are subscribed to the Google Groups "Tim Videos - timvideos.us" group. To unsubscribe from this group and stop receiving emails from it, send an email to timvideos+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
