[U-Boot] [PATCH 0/8 V2] EXYNOS5: Enable I2C support
This patch set enables I2C support for EXYNOS5. This patchset modifies the s3c24x0 I2C driver to use same for EXYNOS5. Multichannel support has been added to the s3c24x0 I2C driver. s3c24x0_i2c struct has been moved to a common place as it can used by different SOC's. Changes in V2: - Incorporated review comments from Simon Glass. - Aligned the pinmux functionality as per latest comments. This patchset depends on the following patch: [U-Boot] [PATCH 1/2 V6] EXYNOS5: PINMUX: Added default pinumx settings Rajeshwari Shinde (8): EXYNOS: CLK: Add i2c clock EXYNOS: Add I2C base address. EXYNOS: PINMUX: Add pinmux support for I2C I2C: Move struct s3c24x0_i2c to a common place. I2C: S3C24X0: Add offset to calculate next i2c channel base address I2C: Modify the I2C driver for EXYNOS5 I2C: Add support for Multi channel CONFIG: SMDK5250: I2C: Enable I2C arch/arm/cpu/armv7/exynos/clock.c | 33 +++ arch/arm/cpu/armv7/exynos/pinmux.c | 52 + arch/arm/include/asm/arch-exynos/clk.h |1 + arch/arm/include/asm/arch-exynos/cpu.h |3 + arch/arm/include/asm/arch-exynos/periph.h |8 + arch/arm/include/asm/arch-s3c24x0/s3c24x0.h | 10 - drivers/i2c/s3c24x0_i2c.c | 281 --- drivers/i2c/s3c24x0_i2c.h | 39 include/configs/smdk5250.h |8 + 9 files changed, 352 insertions(+), 83 deletions(-) create mode 100644 drivers/i2c/s3c24x0_i2c.h -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/8 V2] EXYNOS: CLK: Add i2c clock
This adds i2c clock information for EXYNOS5.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
changes in V2:
- Incorporated comments from Simon Glass which are removed extra
braces around (readl(clk-div_top1)) 24 and gave a tab space for
return statement.
arch/arm/cpu/armv7/exynos/clock.c | 33
arch/arm/include/asm/arch-exynos/clk.h |1 +
2 files changed, 34 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 330bd75..a80928b 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -578,6 +578,29 @@ void exynos4_set_mipi_clk(void)
writel(cfg, clk-div_lcd0);
}
+/*
+ * I2C
+ *
+ * exynos5: obtaining the I2C clock
+ */
+static unsigned long exynos5_get_i2c_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned long aclk_66, aclk_66_pre, sclk;
+ unsigned int ratio;
+
+ sclk = get_pll_clk(MPLL);
+
+ ratio = (readl(clk-div_top1)) 24;
+ ratio = (0x7);
+ aclk_66_pre = sclk/(ratio+1);
+ ratio = readl(clk-div_top0);
+ ratio = (0x7);
+ aclk_66 = aclk_66_pre/(ratio+1);
+ return aclk_66;
+}
+
unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5())
@@ -594,6 +617,16 @@ unsigned long get_arm_clk(void)
return exynos4_get_arm_clk();
}
+unsigned long get_i2c_clk(void)
+{
+ if (cpu_is_exynos5()) {
+ return exynos5_get_i2c_clk();
+ } else {
+ debug(I2C clock is not set for this CPU\n);
+ return 0;
+ }
+}
+
unsigned long get_pwm_clk(void)
{
if (cpu_is_exynos5())
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index 637fb4b..72dc655 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -30,6 +30,7 @@
unsigned long get_pll_clk(int pllreg);
unsigned long get_arm_clk(void);
+unsigned long get_i2c_clk(void);
unsigned long get_pwm_clk(void);
unsigned long get_uart_clk(int dev_index);
void set_mmc_clk(int dev_index, unsigned int div);
--
1.7.4.4
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[U-Boot] [PATCH 2/8 V2] EXYNOS: Add I2C base address.
This patch adds the base address for I2C. Signed-off-by: Alim Akhtar alim.akh...@samsung.com Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com Acked-by: Simon Glass s...@chromium.org --- arch/arm/include/asm/arch-exynos/cpu.h |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index b1e22f2..093bcc1 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -48,6 +48,7 @@ #define EXYNOS4_SROMC_BASE 0x1257 #define EXYNOS4_USBPHY_BASE0x125B #define EXYNOS4_UART_BASE 0x1380 +#define EXYNOS4_I2C_BASE 0x1386 #define EXYNOS4_ADC_BASE 0x1391 #define EXYNOS4_PWMTIMER_BASE 0x139D #define EXYNOS4_MODEM_BASE 0x13A0 @@ -74,6 +75,7 @@ #define EXYNOS5_USBOTG_BASE0x1248 #define EXYNOS5_USBPHY_BASE0x1248 #define EXYNOS5_UART_BASE 0x12C0 +#define EXYNOS5_I2C_BASE 0x12C6 #define EXYNOS5_PWMTIMER_BASE 0x12DD #define EXYNOS5_GPIO_PART2_BASE0x1340 #define EXYNOS5_FIMD_BASE 0x1440 @@ -146,6 +148,7 @@ SAMSUNG_BASE(adc, ADC_BASE) SAMSUNG_BASE(clock, CLOCK_BASE) SAMSUNG_BASE(sysreg, SYSREG_BASE) SAMSUNG_BASE(fimd, FIMD_BASE) +SAMSUNG_BASE(i2c, I2C_BASE) SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE) SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE) SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE) -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/8 V2] EXYNOS: PINMUX: Add pinmux support for I2C
This patch adds pinmux code for I2C.
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in V2:
- Aligned the pinmux functionality as per the latest comments.
This patch depends on the following patch:
[U-Boot] [PATCH 1/2 V6] EXYNOS5: PINMUX: Added default pinumx settings
arch/arm/cpu/armv7/exynos/pinmux.c| 52 +
arch/arm/include/asm/arch-exynos/periph.h |8
2 files changed, 60 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
b/arch/arm/cpu/armv7/exynos/pinmux.c
index 597e487..d3314a1 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -182,6 +182,48 @@ static void exynos5_sromc_config(int flags)
}
}
+static void exynos5_i2c_config(int peripheral, int flags)
+{
+
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+
+ switch (peripheral) {
+ case PERIPH_ID_I2C0:
+ s5p_gpio_cfg_pin(gpio1-b3, 0, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(gpio1-b3, 1, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C1:
+ s5p_gpio_cfg_pin(gpio1-b3, 2, GPIO_FUNC(0x2));
+ s5p_gpio_cfg_pin(gpio1-b3, 3, GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C2:
+ s5p_gpio_cfg_pin(gpio1-a0, 6, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(gpio1-a0, 7, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C3:
+ s5p_gpio_cfg_pin(gpio1-a1, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(gpio1-a1, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C4:
+ s5p_gpio_cfg_pin(gpio1-a2, 0, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(gpio1-a2, 1, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C5:
+ s5p_gpio_cfg_pin(gpio1-a2, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(gpio1-a2, 3, GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C6:
+ s5p_gpio_cfg_pin(gpio1-b1, 3, GPIO_FUNC(0x4));
+ s5p_gpio_cfg_pin(gpio1-b1, 4, GPIO_FUNC(0x4));
+ break;
+ case PERIPH_ID_I2C7:
+ s5p_gpio_cfg_pin(gpio1-b2, 2, GPIO_FUNC(0x3));
+ s5p_gpio_cfg_pin(gpio1-b2, 3, GPIO_FUNC(0x3));
+ break;
+ }
+}
+
static int exynos5_pinmux_config(int peripheral, int flags)
{
switch (peripheral) {
@@ -200,6 +242,16 @@ static int exynos5_pinmux_config(int peripheral, int flags)
case PERIPH_ID_SROMC:
exynos5_sromc_config(flags);
break;
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
+ exynos5_i2c_config(peripheral, flags);
+ break;
default:
debug(%s: invalid peripheral %d, __func__, peripheral);
return -1;
diff --git a/arch/arm/include/asm/arch-exynos/periph.h
b/arch/arm/include/asm/arch-exynos/periph.h
index 5db25aa..b861d7d 100644
--- a/arch/arm/include/asm/arch-exynos/periph.h
+++ b/arch/arm/include/asm/arch-exynos/periph.h
@@ -30,6 +30,14 @@
*
*/
enum periph_id {
+ PERIPH_ID_I2C0,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_I2C4,
+ PERIPH_ID_I2C5,
+ PERIPH_ID_I2C6,
+ PERIPH_ID_I2C7,
PERIPH_ID_SDMMC0,
PERIPH_ID_SDMMC1,
PERIPH_ID_SDMMC2,
--
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[U-Boot] [PATCH 7/8 V2] I2C: Add support for Multi channel
This adds multiple i2c channel support for I2C.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
drivers/i2c/s3c24x0_i2c.c | 27 +++
1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index a71f147..7521cb8 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -191,6 +191,33 @@ static void i2c_bus_init(struct s3c24x0_i2c *i2c, unsigned
int bus)
i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
}
+/*
+ * MULTI BUS I2C support
+ */
+
+#ifdef CONFIG_I2C_MULTI_BUS
+int i2c_set_bus_num(unsigned int bus)
+{
+ struct s3c24x0_i2c *i2c;
+
+ if ((bus 0) || (bus = CONFIG_MAX_I2C_NUM)) {
+ debug(Bad bus: %d\n, bus);
+ return -1;
+ }
+
+ g_current_bus = bus;
+ i2c = get_base_i2c(g_current_bus);
+ i2c_bus_init(i2c, g_current_bus);
+
+ return 0;
+}
+
+unsigned int i2c_get_bus_num(void)
+{
+ return g_current_bus;
+}
+#endif
+
#ifdef CONFIG_EXYNOS5
void i2c_init(int speed, int slaveadd)
{
--
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[U-Boot] [PATCH 6/8 V2] I2C: Modify the I2C driver for EXYNOS5
This patch modifies the S3C I2C driver to suppport EXYNOS5.
The cahnges made to driver are as follows:
- I2C base address is passed as a parameter to many
functions to avoid multiple #ifdef
- I2C init for Exynos5 is made as different function.
- Channel initialisation is moved to a commom funation
as it is required by both the i2c_init.
- Separate functions written to get I2C base address,
peripheral id for pinmux support.
- Hardcoding for I2CCON_ACKGEN removed.
- Replaced printf with debug.
- Checkpatch issues resolved.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in V2:
- Removed #define for I2C cahnnels from hearder file except for I2C0.
- Incorporated review comments from Simon Glass.
drivers/i2c/s3c24x0_i2c.c | 254 -
drivers/i2c/s3c24x0_i2c.h |3 +
2 files changed, 184 insertions(+), 73 deletions(-)
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index ba6f39b..a71f147 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -27,10 +27,17 @@
*/
#include common.h
+#ifdef CONFIG_EXYNOS5
+#include asm/arch/clk.h
+#include asm/arch/cpu.h
+#include asm/arch/gpio.h
+#include asm/arch/pinmux.h
+#else
#include asm/arch/s3c24x0_cpu.h
-
+#endif
#include asm/io.h
#include i2c.h
+#include s3c24x0_i2c.h
#ifdef CONFIG_HARD_I2C
@@ -45,6 +52,7 @@
#define I2CSTAT_BSY0x20/* Busy bit */
#define I2CSTAT_NACK 0x01/* Nack bit */
+#define I2CCON_ACKGEN 0x80/* Acknowledge generation */
#define I2CCON_IRPND 0x10/* Interrupt pending bit */
#define I2C_MODE_MT0xC0/* Master Transmit Mode */
#define I2C_MODE_MR0x80/* Master Receive Mode */
@@ -53,6 +61,44 @@
#define I2C_TIMEOUT 1 /* 1 second */
+#ifdef CONFIG_EXYNOS5
+static unsigned int g_current_bus; /* Stores Current I2C Bus */
+
+/* We should not rely on any particular ordering of these IDs */
+static enum periph_id periph_for_dev[] = {
+ PERIPH_ID_I2C0,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_I2C4,
+ PERIPH_ID_I2C5,
+ PERIPH_ID_I2C6,
+ PERIPH_ID_I2C7,
+};
+
+static enum periph_id i2c_get_periph_id(unsigned dev_index)
+{
+ if (dev_index ARRAY_SIZE(periph_for_dev))
+ return periph_for_dev[dev_index];
+
+ debug(%s: invalid bus %d, __func__, dev_index);
+
+ return PERIPH_ID_NONE;
+}
+
+static struct s3c24x0_i2c *get_base_i2c(int bus_idx)
+{
+ struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)samsung_get_base_i2c();
+
+ return i2c[bus_idx];
+}
+
+static inline struct exynos5_gpio_part1 *exynos_get_base_gpio1(void)
+{
+ return (struct exynos5_gpio_part1 *)(EXYNOS5_GPIO_PART1_BASE);
+}
+
+#else
static int GetI2CSDA(void)
{
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
@@ -77,16 +123,17 @@ static void SetI2CSCL(int x)
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
#ifdef CONFIG_S3C2410
- writel((readl(gpio-gpedat) ~0x4000) | (x 1) 14, gpio-gpedat);
+ writel((readl(gpio-gpedat) ~0x4000) |
+ (x 1) 14, gpio-gpedat);
#endif
#ifdef CONFIG_S3C2400
writel((readl(gpio-pgdat) ~0x0040) | (x 1) 6, gpio-pgdat);
#endif
}
+#endif
-static int WaitForXfer(void)
+static int WaitForXfer(struct s3c24x0_i2c *i2c)
{
- struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
int i;
i = I2C_TIMEOUT * 1;
@@ -98,25 +145,84 @@ static int WaitForXfer(void)
return (readl(i2c-iiccon) I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
}
-static int IsACK(void)
+static int IsACK(struct s3c24x0_i2c *i2c)
{
- struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
-
return !(readl(i2c-iicstat) I2CSTAT_NACK);
}
-static void ReadWriteByte(void)
+static void ReadWriteByte(struct s3c24x0_i2c *i2c)
{
- struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
-
writel(readl(i2c-iiccon) ~I2CCON_IRPND, i2c-iiccon);
}
+static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
+{
+ ulong freq, pres = 16, div;
+#ifdef CONFIG_EXYNOS5
+ freq = get_i2c_clk();
+#else
+ freq = get_PCLK();
+#endif
+ /* calculate prescaler and divisor values */
+ if ((freq / pres / (16 + 1)) speed)
+ /* set prescaler to 512 */
+ pres = 512;
+
+ div = 0;
+ while ((freq / pres / (div + 1)) speed)
+ div++;
+
+ /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
+ writel((div 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), i2c-iiccon);
+
+ /* init to SLAVE REVEIVE and set slaveaddr */
+ writel(0, i2c-iicstat);
+
[U-Boot] [PATCH 8/8 V2] CONFIG: SMDK5250: I2C: Enable I2C
This enables I2C support on smdk5250. Signed-off-by: Alim Akhtar alim.akh...@samsung.com Signed-off-by: Doug Anderson diand...@chromium.org Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com Acked-by: Simon Glass s...@chromium.org --- include/configs/smdk5250.h |8 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 9659f9e..1fca652 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -190,6 +190,14 @@ #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_LOAD_ADDR - 0x100) +/* I2C */ +#define CONFIG_HARD_I2C +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_SPEED 10 /* 100 Kbps */ +#define CONFIG_DRIVER_S3C24X0_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_MAX_I2C_NUM 8 + /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET #define CONFIG_SMC911X -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/8 V2] I2C: Move struct s3c24x0_i2c to a common place.
struct s3c24x0_i2c is being moved to common local header file so that
the same can be used by s3c series and exynos series SoCs.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
arch/arm/include/asm/arch-s3c24x0/s3c24x0.h | 10
drivers/i2c/s3c24x0_i2c.h | 33 +++
2 files changed, 33 insertions(+), 10 deletions(-)
create mode 100644 drivers/i2c/s3c24x0_i2c.h
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
index ca978c9..0f75c31 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
@@ -343,16 +343,6 @@ struct s3c24x0_watchdog {
u32 wtcnt;
};
-
-/* IIC (see manual chapter 20) */
-struct s3c24x0_i2c {
- u32 iiccon;
- u32 iicstat;
- u32 iicadd;
- u32 iicds;
-};
-
-
/* IIS (see manual chapter 21) */
struct s3c24x0_i2s {
#ifdef __BIG_ENDIAN
diff --git a/drivers/i2c/s3c24x0_i2c.h b/drivers/i2c/s3c24x0_i2c.h
new file mode 100644
index 000..2dd4b06
--- /dev/null
+++ b/drivers/i2c/s3c24x0_i2c.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_I2C_H
+#define _S3C24X0_I2C_H
+
+struct s3c24x0_i2c {
+ u32 iiccon;
+ u32 iicstat;
+ u32 iicadd;
+ u32 iicds;
+ u32 iiclc;
+};
+#endif /* _S3C24X0_I2C_H */
--
1.7.4.4
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[U-Boot] [PATCH 5/8 V2] I2C: S3C24X0: Add offset to calculate next i2c channel base address
As exynos has more than one i2c channels. This patch adds offset padding
for struct s3c24x0_i2c, in order to get the new base address of next i2c
channel.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
drivers/i2c/s3c24x0_i2c.h |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/s3c24x0_i2c.h b/drivers/i2c/s3c24x0_i2c.h
index 2dd4b06..d357a0a 100644
--- a/drivers/i2c/s3c24x0_i2c.h
+++ b/drivers/i2c/s3c24x0_i2c.h
@@ -29,5 +29,8 @@ struct s3c24x0_i2c {
u32 iicadd;
u32 iicds;
u32 iiclc;
+#ifdef CONFIG_EXYNOS5
+ uchar res1[0xffec];
+#endif
};
#endif /* _S3C24X0_I2C_H */
--
1.7.4.4
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[U-Boot] [PATCH 3/6] powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro
When compile the slave image for boot from SRIO, no longer need to
specify which SRIO port it will boot from. The code will get this
information from RCW and then finishes corresponding configurations.
This has the following advantages:
1. No longer need to rebuild an image when change the SRIO port for
boot from SRIO, just rewrite the new RCW with selected port,
then the code will get the port information by reading new RCW.
2. It will be easier to support other boot location options, for
example, boot from PCIE.
Signed-off-by: Liu Gang gang@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h |1 +
board/freescale/common/p_corenet/law.c | 13 -
drivers/misc/fsl_law.c | 27 +++
include/configs/corenet_ds.h |3 ---
4 files changed, 28 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 632e3c1..48a00b9 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1758,6 +1758,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR5_DDR_SYNC0x0080
#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
#define FSL_CORENET_RCWSR5_SRDS_EN 0x2000
+#define FSL_CORENET_RCWSR6_BOOT_LOC0x0f80
#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c00 /* bits 162..165 */
#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c /* bits 170..173 */
#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x0040
diff --git a/board/freescale/common/p_corenet/law.c
b/board/freescale/common/p_corenet/law.c
index c4566dd..09ef561 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -48,19 +48,6 @@ struct law_entry law_table[] = {
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
-#ifdef CONFIG_SRIOBOOT_SLAVE
-#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
- SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
- SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
-#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
- SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
- SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
- LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
-#endif
-#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index a7d04b7..a71a0ce 100644
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -275,5 +275,32 @@ void init_laws(void)
law_table[i].size, law_table[i].trgt_id);
}
+#ifdef CONFIG_SRIOBOOT_SLAVE
+ /* check RCW to get which port is used for boot */
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ u32 bootloc = in_be32(gur-rcwsr[6]);
+ /* in SRIO boot we need to set specail LAWs for SRIO interfaces */
+ switch ((bootloc FSL_CORENET_RCWSR6_BOOT_LOC) 23) {
+ case 0x8: /* boot from SRIO1 */
+ set_next_law(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_RIO_1);
+ set_next_law(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_RIO_1);
+ break;
+ case 0x9: /* boot from SRIO2 */
+ set_next_law(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_RIO_2);
+ set_next_law(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_RIO_2);
+ break;
+ default:
+ break;
+ }
+#endif
+
return ;
}
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 1f9fdfd..f2e48f5 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -413,9 +413,6 @@
* SRIOBOOT - SLAVE
*/
#ifdef CONFIG_SRIOBOOT_SLAVE
-/* slave port for srioboot */
-#define CONFIG_SRIOBOOT_SLAVE_PORT0
-/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */
#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE0
#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \
(0x3ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR)
--
1.7.1
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[U-Boot] [PATCH 2/6] powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build target
Get rid of the SRIOBOOT_MASTER build target, and to support for serving as
a SRIO boot master via environment variable. Set the environment variable
bootmaster to SRIO1 or SRIO2 using the following command:
setenv bootmaster SRIO1
saveenv
The bootmaster will enable the function of the SRIO boot master, and
this has the following advantages compared with SRIOBOOT_MASTER build
configuration:
1. Reduce a build configuration item in boards.cfg file.
No longer need to build a special image for master, just use a
normal target image and set the bootmaster variable.
2. No longer need to rebuild an image when change the SRIO port for
boot from SRIO, just set the corresponding value to bootmaster
based on the using SRIO port.
Signed-off-by: Liu Gang gang@freescale.com
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 17 +++--
arch/powerpc/cpu/mpc8xxx/srio.c | 137 ---
arch/powerpc/include/asm/fsl_srio.h |8 +--
boards.cfg |3 -
include/configs/corenet_ds.h| 32 ++--
5 files changed, 68 insertions(+), 129 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 2cd5db7..4c8b005 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -442,12 +442,17 @@ skip_l2:
#ifdef CONFIG_SYS_SRIO
srio_init();
-#ifdef CONFIG_SRIOBOOT_MASTER
- srio_boot_master();
-#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
- srio_boot_master_release_slave();
-#endif
-#endif
+ char *s = getenv(bootmaster);
+ if (s) {
+ if (!strcmp(s, SRIO1)) {
+ srio_boot_master(1);
+ srio_boot_master_release_slave(1);
+ }
+ if (!strcmp(s, SRIO2)) {
+ srio_boot_master(2);
+ srio_boot_master_release_slave(2);
+ }
+ }
#endif
#if defined(CONFIG_MP)
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index c7f3949..0ba7e2a 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -95,126 +95,91 @@ void srio_init(void)
}
}
-#ifdef CONFIG_SRIOBOOT_MASTER
-void srio_boot_master(void)
+void srio_boot_master(int port)
{
struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
/* set port accept-all */
- out_be32((void *)srio-impl.port[CONFIG_SRIOBOOT_MASTER_PORT].ptaacr,
+ out_be32((void *)srio-impl.port[port - 1].ptaacr,
SRIO_PORT_ACCEPT_ALL);
- debug(SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n,
- CONFIG_SRIOBOOT_MASTER_PORT);
+ debug(SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n, port);
/* configure inbound window for slave's u-boot image */
debug(SRIOBOOT - MASTER: Inbound window for slave's image;
Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
- (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1,
- (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1,
CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
- out_be32((void *)srio-atmu
- .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwtar,
- CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 12);
- out_be32((void *)srio-atmu
- .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwbar,
- CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 12);
- out_be32((void *)srio-atmu
- .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwar,
+ out_be32((void *)srio-atmu.port[port - 1].inbw[0].riwtar,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS 12);
+ out_be32((void *)srio-atmu.port[port - 1].inbw[0].riwbar,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1 12);
+ out_be32((void *)srio-atmu.port[port - 1].inbw[0].riwar,
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
/* configure inbound window for slave's u-boot image */
debug(SRIOBOOT - MASTER: Inbound window for slave's image;
Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n,
- (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2,
- (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS2,
CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
- out_be32((void *)srio-atmu
- .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwtar,
-
[U-Boot] [PATCH 1/6] powerpc/corenet_ds: Update README.srio-boot-corenet
Update some descriptions due to the implementation changes: For master: Get rid of the SRIOBOOT_MASTER build target, and to support for serving as a SRIO boot master via environment variable. For slave: 1. When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. 2. All slave's cores should be in hold off. Signed-off-by: Liu Gang gang@freescale.com --- doc/README.srio-boot-corenet | 70 -- 1 files changed, 33 insertions(+), 37 deletions(-) diff --git a/doc/README.srio-boot-corenet b/doc/README.srio-boot-corenet index 56b094c..6a13e9c 100644 --- a/doc/README.srio-boot-corenet +++ b/doc/README.srio-boot-corenet @@ -18,7 +18,7 @@ Environment of the SRIO boot: U-Boot images, UCodes will be stored in this flash. d) Slave has its own EEPROM for RCW and PBI. e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot - location to SRIO, and holdoff all the cores if needed. + location to SRIO, and holdoff all the cores. ----- --- | | | | | | @@ -30,63 +30,55 @@ Environment of the SRIO boot: The example based on P4080DS platform: Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO - ports 0 will be connected directly and will be used for the boot from SRIO. + ports 1 will be connected directly and will be used for the boot from SRIO. - 1. Slave's RCW example for boot from SRIO port 0 and core 0 not in holdoff. - : aa55 aa55 010e 0100 0c58 - 0010: 1818 1818 7440 4000 2000 - 0020: f400 0100 - 0030: 0083 - 0040: 0813 8040 698b 93fe - - 2. Slave's RCW example for boot from SRIO port 0 and all cores in holdoff. + 1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff. : aa55 aa55 010e 0100 0c58 0010: 1818 1818 7440 4000 2000 0020: f440 0100 0030: 0083 0040: 0813 8040 063c 778f - 3. Sequence in Step by Step. - a) Update RCW for slave with boot from SRIO port 0 configuration. + 2. Sequence in Step by Step. + a) Update RCW for slave with boot from SRIO port 1 configuration. b) Program slave's U-Boot image, UCode, and ENV parameters into master's NorFlash. - c) Start up master and it will boot up normally from its NorFlash. + c) Set environment variable bootmaster to SRIO1 and save environment + for master. + setenv bootmaster SRIO1 + saveenv + d) Restart up master and it will boot up normally from its NorFlash. Then, it will finish necessary configurations for slave's boot from - SRIO port 0. - d) Master will set inbound SRIO windows covered slave's U-Boot image stored + SRIO port 1. + e) Master will set inbound SRIO windows covered slave's U-Boot image stored in master's NorFlash. - e) Master will set an inbound SRIO window covered slave's UCode stored in - master's NorFlash. - f) Master will set an inbound SRIO window covered slave's ENV stored in - master's NorFlash. - g) If need to release slave's core, master will set outbound SRIO windows - in order to configure slave's registers for the core's releasing. - h) If all cores of slave in holdoff, slave should be powered on before all - the above master's steps, and wait to be released by master. If not all - cores in holdoff, that means core 0 will start up normally, slave should - be powered on after all the above master's steps. In the startup phase - of the slave from SRIO, it will finish some necessary configurations. + f) Master will set an inbound SRIO window covered slave's UCode and ENV + stored in master's NorFlash. + g) Master will set outbound SRIO windows in order to configure slave's + registers for the core's releasing. + h) Since all cores of slave in holdoff, slave should be powered on before all + the above master's steps, and wait to be
[U-Boot] [PATCH 4/6] powerpc/corenet_ds: Update README and README.srio-pcie-boot-corenet
Added descriptions about boot from PCIE in the files README and doc/README.srio-pcie-boot-corenet, and changed the name of the doc/README.srio-boot-corenet to doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang gang@freescale.com --- README| 12 ++-- doc/README.srio-boot-corenet | 99 doc/README.srio-pcie-boot-corenet | 112 + 3 files changed, 118 insertions(+), 105 deletions(-) delete mode 100644 doc/README.srio-boot-corenet create mode 100644 doc/README.srio-pcie-boot-corenet diff --git a/README b/README index 6919392..fda7ddc 100644 --- a/README +++ b/README @@ -3045,12 +3045,12 @@ to save the current settings. These two #defines specify the address and size of the environment area within the remote memory space. The local device can get the environment from remote memory - space by SRIO or other links. + space by SRIO or PCIE links. BE CAREFUL! For some special cases, the local device can not use saveenv command. For example, the local device will get the -environment stored in a remote NOR flash by SRIO link, but it can -not erase, write this NOR flash by SRIO interface. +environment stored in a remote NOR flash by SRIO or PCIE link, +but it can not erase, write this NOR flash by SRIO or PCIE interface. - CONFIG_ENV_IS_IN_NAND: @@ -3491,9 +3491,9 @@ within that device. - CONFIG_SYS_QE_FMAN_FW_IN_REMOTE Specifies that QE/FMAN firmware is located in the remote (master) memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which - can be mapped from slave TLB-slave LAW-slave SRIO outbound window - -master inbound window-master LAW-the ucode address in master's - NOR flash. + can be mapped from slave TLB-slave LAW-slave SRIO or PCIE outbound + window-master inbound window-master LAW-the ucode address in + master's memory space. Building the Software: == diff --git a/doc/README.srio-boot-corenet b/doc/README.srio-boot-corenet deleted file mode 100644 index 6a13e9c..000 --- a/doc/README.srio-boot-corenet +++ /dev/null @@ -1,99 +0,0 @@ --- -SRIO Boot on Corenet Platforms --- - -For some PowerPC processors with SRIO interface, boot location can be configured -to SRIO by RCW. The processor booting from SRIO can do without flash for u-boot -image, ucode and ENV. All the images can be fetched from another processor's -memory space by SRIO link connected between them. - -This document describes the processes based on an example implemented on P4080DS -platforms and a RCW example with boot from SRIO configuration. - -Environment of the SRIO boot: - a) Master and slave can be SOCs in one board or SOCs in separate boards. - b) They are connected with SRIO links, whether 1x or 4x, and directly or - through switch system. - c) Only Master has NorFlash for booting, and all the Master's and Slave's - U-Boot images, UCodes will be stored in this flash. - d) Slave has its own EEPROM for RCW and PBI. - e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot - location to SRIO, and holdoff all the cores. - - ----- --- - | | | | | | - | | | | | | - | NorFlash|-| Master |SRIO | Slave |[EEPROM] - | | | |===| | - | | | | | | - ----- --- - -The example based on P4080DS platform: - Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO - ports 1 will be connected directly and will be used for the boot from SRIO. - - 1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff. - : aa55 aa55 010e 0100 0c58 - 0010: 1818 1818 7440 4000 2000 - 0020: f440 0100 - 0030: 0083 - 0040: 0813 8040 063c 778f - - 2. Sequence in Step by Step. - a) Update RCW for slave with boot from SRIO port 1 configuration. - b) Program slave's U-Boot image, UCode, and ENV parameters into master's - NorFlash. - c) Set environment variable bootmaster to SRIO1 and save environment - for master. - setenv bootmaster SRIO1 - saveenv - d) Restart up master and it will boot up normally from its
[U-Boot] [PATCH 6/6] powerpc/corenet_ds: Slave module for boot from PCIE
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.
NOTE: Because the slave can not erase, write master's NOR flash by
PCIE interface, so it can not modify the ENV parameters stored
in master's NOR flash using saveenv or other commands.
environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Put the slave's ucode and ENV into it's own memory space.
4. Normally boot from local NOR flash.
5. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the slave module, need to finish these processes:
1. Set the boot location to one PCIE interface by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID of one PCIE for the boot.
4. Set a specific TLB entry in order to fetch ucode and ENV from
master.
5. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
6. Slave's u-boot image should be generated specifically by
make _SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF8 and other configurations.
In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
1. Updated the README.srio-boot-corenet to add descriptions about
boot from PCIE, and change the name to
README.srio-pcie-boot-corenet.
2. Changed the compile config _SRIOBOOT_SLAVE to
_SRIO_PCIE_BOOT, and the image builded with
_SRIO_PCIE_BOOT can support both the boot from SRIO and
from PCIE.
3. Updated other macros and documents if needed to add information
about boot from PCIE.
Signed-off-by: Liu Gang gang@freescale.com
---
board/freescale/common/p_corenet/tlb.c | 18 +++---
boards.cfg |6 ++--
common/env_remote.c|4 +-
drivers/misc/fsl_law.c | 39 +++-
include/configs/corenet_ds.h | 28 +++---
5 files changed, 61 insertions(+), 34 deletions(-)
diff --git a/board/freescale/common/p_corenet/tlb.c
b/board/freescale/common/p_corenet/tlb.c
index da21627..e5cf208 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -66,13 +66,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
-#elif defined(CONFIG_SRIOBOOT_SLAVE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
-* SRIOBOOT-SLAVE. When slave boot, the address of the
+* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
* space is at 0xfff0, it covered the 0xf000.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR,
- CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#else
@@ -147,13 +147,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_1M, 1),
#endif
-#ifdef CONFIG_SRIOBOOT_SLAVE
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/*
-* SRIOBOOT-SLAVE. 1M space from 0xffe0 for fetching ucode
-* and ENV from master
+* SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe0 for
+* fetching ucode and ENV from master
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR,
- CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 17, BOOKE_PAGESZ_1M, 1),
#endif
diff --git a/boards.cfg
[U-Boot] [PATCH 5/6] powerpc/corenet_ds: Master module for boot from PCIE
For the powerpc processors with PCIE interface, boot location can be configured from one PCIE interface by RCW. The processor booting from PCIE can do without flash for u-boot image. The image can be fetched from another processor's memory space by PCIE link connected between them. The processor booting from PCIE is slave, the processor booting from normal flash memory space is master, and it can help slave to boot from master's memory space. When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the master module, need to finish these processes: 1. Initialize the PCIE port and address space. 2. Set inbound PCIE windows covered slave's u-boot image stored in master's NOR flash. 3. Set outbound windows in order to configure slave's registers for the core's releasing. 4. Should set the environment variable bootmaster to PCIE1, PCIE2 or PCIE3 using the following command: setenv bootmaster PCIE1 saveenv Signed-off-by: Liu Gang gang@freescale.com --- arch/powerpc/cpu/mpc8xxx/srio.c | 44 drivers/pci/fsl_pci_init.c | 111 ++- include/configs/corenet_ds.h| 18 +++--- 3 files changed, 140 insertions(+), 33 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index 0ba7e2a..02b830d 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -107,44 +107,44 @@ void srio_boot_master(int port) /* configure inbound window for slave's u-boot image */ debug(SRIOBOOT - MASTER: Inbound window for slave's image; Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n, - (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS, - (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1, - CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); + (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, + (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, + CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); out_be32((void *)srio-atmu.port[port - 1].inbw[0].riwtar, - CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS 12); + CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 12); out_be32((void *)srio-atmu.port[port - 1].inbw[0].riwbar, - CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS1 12); + CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 12); out_be32((void *)srio-atmu.port[port - 1].inbw[0].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); + | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); /* configure inbound window for slave's u-boot image */ debug(SRIOBOOT - MASTER: Inbound window for slave's image; Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n, - (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS, - (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS2, - CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); + (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, + (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, + CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); out_be32((void *)srio-atmu.port[port - 1].inbw[1].riwtar, - CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_PHYS 12); + CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 12); out_be32((void *)srio-atmu.port[port - 1].inbw[1].riwbar, - CONFIG_SRIOBOOT_SLAVE_IMAGE_MEM_BUS2 12); + CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 12); out_be32((void *)srio-atmu.port[port - 1].inbw[1].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); + | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); /* configure inbound window for slave's ucode and ENV */ debug(SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n, -
Re: [U-Boot] [PATCH v2 07/10] tegra20: add SPL config options for seaboard
On Wed Jun 06, 2012 at 10:44:59AM -0600, Stephen Warren wrote: On 06/05/2012 03:20 PM, Allen Martin wrote: snip diff --git a/include/configs/tegra2-spl.h b/include/configs/tegra2-spl.h + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. Being a new file, this should be GPLv2 not GPLv2+. u-boot uses GPLv2+. http://www.denx.de/wiki/view/U-Boot/Patches#Attributing_Code_Copyrights_Sign http://www.mail-archive.com/u-boot@lists.denx.de/msg26569.html -sughosh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] 85xx platforms build broken due to flush dcache functions missing
Dear Zang Roy-R61911, The patch [PATCH V2] MPC8xxx: Define cache ops for USB wasn't applied yet for some reason. It fixes the issue. Hi, Marek When I build P5020DS_config with the current u-boot head, I got: /home/roy/CVS/upstream/u-boot/drivers/usb/host/ehci-hcd.c:346: undefined reference to `flush_dcache_range' /home/roy/CVS/upstream/u-boot/drivers/usb/host/ehci-hcd.c:348: undefined reference to `flush_dcache_range' /home/roy/CVS/upstream/u-boot/drivers/usb/host/ehci-hcd.c:349: undefined reference to `flush_dcache_range' /home/roy/CVS/upstream/u-boot/drivers/usb/host/ehci-hcd.c:372: undefined reference to `invalidate_dcache_range' /home/roy/CVS/upstream/u-boot/drivers/usb/host/ehci-hcd.c:374: undefined reference to `invalidate_dcache_range' /home/roy/CVS/upstream/u-boot/drivers/usb/host/ehci-hcd.c:376: undefined reference to `invalidate_dcache_range' /home/roy/CVS/upstream/u-boot/drivers/usb/host/ehci-hcd.c:386: undefined reference to `invalidate_dcache_range' make: *** [u-boot] Error 1 I found it was caused by your commit : commit b8adb12095814260d2b5edb23663ddf0ab97b877 Author: Marek Vasut ma...@denx.de Date: Mon Apr 9 04:07:46 2012 +0200 USB: Drop cache flush bloat in EHCI-HCD Discard the creepy cache flushing mechanisms in ehci-hcd.c and replace them more straightforward flushing. In the new approach, the flushing takes place directly in ehci_submit_async() call instead of going through the QH list an flushing all members and buffers. This discards a lot of weird bit operation on the members of QH and qTD structures. NOTE: Certainly, this flushes even qTDs which are possibly unused in some transactions, though the overhead of the previous code was much higher than the overhead of flushing two more cache lines (which most probably aren't ev cached). Signed-off-by: Marek Vasut marek.va...@gmail.com Do you have any comment? Your commit will break all 85xx platforms with USB controller. Thanks Roy Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 5/5] wispy: add weak functions board_spi_claim/release_bus
Hi Prafulla, On 06/05/2012 04:21 PM, Prafulla Wadaskar wrote: -Original Message- From: Valentin Longchamp [mailto:valentin.longch...@keymile.com] Sent: 01 June 2012 17:01 To: Prafulla Wadaskar Cc: u-boot@lists.denx.de; Valentin Longchamp; Holger Brunck Subject: [PATCH v4 5/5] kw_spi: add weak functions board_spi_claim/release_bus This allows a final, board specific, step in the claim/relase_bus function for the SPI controller, which may be needed for some hardware designs. Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com cc: Holger Brunck holger.bru...@keymile.com cc: Prafulla Wadaskar prafu...@marvell.com --- Applied this entire patch series to u-boot-marvell.git master branch Thank you for applying this patch series. I will now send you the third series as you discussed it with Holger (http://lists.denx.de/pipermail/u-boot/2012-May/125208.html), which contains the patches for the support of new boards and new features for Keymile boards. Valentin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 0/7] feature additions and fixes for da850/omap-l138
From: Lad, Prabhakar prabhakar@ti.com This series adds MMC/SD, NAND and NOR SPL support for Logic PD's DA850/OMAP-L138 EVM. This series also fixes some issues found on the EVM during testing. The patches are sent in a series as these patches need to be applied in the order they are sent. Changes for v2: 1: Fixed comments from Tom to remove unused macro and add comment. 2: Fixed comments from Christian to move GPIO pins to board file and add a check to perform initializations only when CONFIG_SPL_LIBCOMMON_SUPPORT is defined. Lad, Prabhakar (5): da850/omap-l138: Add MMC support for DA850/OMAP-L138 da850/omap-l138: Add support to read u-boot image from MMC/SD da850/omap-l138: Fix NAND flash timings da850/omap-l138: Add support for NAND SPL da850/omap-l138: add support for direct NOR boot mode Rajashekhara, Sudhakar (2): da850/omap-l138: modifications for Logic PD Rev.3 AM18xx EVM da850/omap-l138: Make MMC and NOR support mutually exclusive arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c | 11 +++ arch/arm/cpu/arm926ejs/davinci/spl.c| 27 +-- arch/arm/include/asm/arch-davinci/hardware.h|1 + arch/arm/include/asm/arch-davinci/pinmux_defs.h |3 + board/davinci/da8xxevm/da850evm.c | 54 +-- boards.cfg |1 + drivers/mmc/Makefile|4 + drivers/mmc/spl_mmc_load.c | 62 include/configs/da850evm.h | 86 +-- include/mmc.h |2 + 10 files changed, 233 insertions(+), 18 deletions(-) create mode 100644 drivers/mmc/spl_mmc_load.c -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/7] da850/omap-l138: Add MMC support for DA850/OMAP-L138
From: Lad, Prabhakar prabhakar@ti.com
This patch adds support for MMC/SD on DA850/OMAP-L138.
Signed-off-by: Lad, Prabhakar prabhakar@ti.com
Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com
Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com
---
Changes for v2:
1:Removed CONFIG_MMC_MBLOCK config which was never used.
2:Added comment while enabling MMC commands.
3:Moved GP0[11] to the board file da850evm.c
arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c | 11
arch/arm/include/asm/arch-davinci/hardware.h|1 +
arch/arm/include/asm/arch-davinci/pinmux_defs.h |3 ++
board/davinci/da8xxevm/da850evm.c | 32 +++
include/configs/da850evm.h | 17
5 files changed, 64 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
index fa07fb5..ad600b2 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
@@ -169,3 +169,14 @@ const struct pinmux_config emifa_pins_nor[] = {
{ pinmux(12), 1, 6 }, /* EMA_A[1] */
{ pinmux(12), 1, 7 }, /* EMA_A[0] */
};
+
+/* MMC0 pin muxer settings */
+const struct pinmux_config mmc0_pins[] = {
+ { pinmux(10), 2, 0 }, /* MMCSD0_CLK */
+ { pinmux(10), 2, 1 }, /* MMCSD0_CMD */
+ { pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */
+ { pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */
+ { pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */
+ { pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */
+ /* DA850 supports only 4-bit mode, remaining pins are not configured */
+};
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index b145c6e..f6b7a2c 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -446,6 +446,7 @@ struct davinci_pllc_regs {
#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3)
/* Clock IDs */
enum davinci_clk_ids {
+ DAVINCI_MMCSD_CLKID = 2,
DAVINCI_SPI0_CLKID = 2,
DAVINCI_UART2_CLKID = 2,
DAVINCI_MMC_CLKID = 2,
diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h
b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
index 07aceaa..0db1e40 100644
--- a/arch/arm/include/asm/arch-davinci/pinmux_defs.h
+++ b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
@@ -48,4 +48,7 @@ extern const struct pinmux_config emifa_pins_cs4[1];
extern const struct pinmux_config emifa_pins_nand[12];
extern const struct pinmux_config emifa_pins_nor[43];
+/* MMC pin muxer settings */
+extern const struct pinmux_config mmc0_pins[6];
+
#endif
diff --git a/board/davinci/da8xxevm/da850evm.c
b/board/davinci/da8xxevm/da850evm.c
index 004d5ad..88337ff 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -36,6 +36,11 @@
#include asm/errno.h
#include hwconfig.h
+#ifdef CONFIG_DAVINCI_MMC
+#include mmc.h
+#include asm/arch/sdmmc_defs.h
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_DRIVER_TI_EMAC
@@ -204,11 +209,32 @@ int misc_init_r(void)
return 0;
}
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+ .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_2,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
+
+ /* Add slot-0 to mmc subsystem */
+ return davinci_mmc_init(bis, mmc_sd0);
+}
+#endif
+
static const struct pinmux_config gpio_pins[] = {
#ifdef CONFIG_USE_NOR
/* GP0[11] is required for NOR to work on Rev 3 EVMs */
{ pinmux(0), 8, 4 },/* GP0[11] */
#endif
+#ifdef CONFIG_DAVINCI_MMC
+ /* GP0[11] is required for SD to work on Rev 3 EVMs */
+ { pinmux(0), 8, 4 }, /* GP0[11] */
+#endif
};
const struct pinmux_resource pinmuxes[] = {
@@ -236,6 +262,9 @@ const struct pinmux_resource pinmuxes[] = {
PINMUX_ITEM(emifa_pins_nor),
#endif
PINMUX_ITEM(gpio_pins),
+#ifdef CONFIG_DAVINCI_MMC
+ PINMUX_ITEM(mmc0_pins),
+#endif
};
const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
@@ -246,6 +275,9 @@ const struct lpsc_resource lpsc[] = {
{ DAVINCI_LPSC_EMAC }, /* image download */
{ DAVINCI_LPSC_UART2 }, /* console */
{ DAVINCI_LPSC_GPIO },
+#ifdef CONFIG_DAVINCI_MMC
+ { DAVINCI_LPSC_MMC_SD },
+#endif
};
const int lpsc_size = ARRAY_SIZE(lpsc);
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 989472b..8b4fea1 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -313,6 +313,23 @@
#undef CONFIG_CMD_ENV
#endif
+/* SD/MMC configuration */
+#define CONFIG_MMC
+#define CONFIG_DAVINCI_MMC_SD1
+#define CONFIG_GENERIC_MMC
+#define
[U-Boot] [PATCH v2 2/7] da850/omap-l138: modifications for Logic PD Rev.3 AM18xx EVM
From: Rajashekhara, Sudhakar sudhakar@ti.com
AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for
MMC and NOR to work on DA850/OMAP-L138 Rev.3 EVM. When
GP0[11] is low, the SD0 interface will not work, but NOR
flash will. When GP0[11] is high, SD0 will work but NOR
flash will not.
Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com
Signed-off-by: Lad, Prabhakar prabhakar@ti.com
Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com
---
board/davinci/da8xxevm/da850evm.c | 12 +++-
1 files changed, 11 insertions(+), 1 deletions(-)
diff --git a/board/davinci/da8xxevm/da850evm.c
b/board/davinci/da8xxevm/da850evm.c
index 88337ff..0d75b84 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -335,7 +335,7 @@ int board_early_init_f(void)
int board_init(void)
{
-#ifdef CONFIG_USE_NOR
+#if defined(CONFIG_USE_NOR) || defined(CONFIG_DAVINCI_MMC)
u32 val;
#endif
@@ -386,6 +386,16 @@ int board_init(void)
writel(val, GPIO_BANK0_REG_CLR_ADDR);
#endif
+#ifdef CONFIG_DAVINCI_MMC
+ /* Set the GPIO direction as output */
+ clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 11));
+
+ /* Set the output as high */
+ val = readl(GPIO_BANK0_REG_SET_ADDR);
+ val |= (0x01 11);
+ writel(val, GPIO_BANK0_REG_SET_ADDR);
+#endif
+
#ifdef CONFIG_DRIVER_TI_EMAC
davinci_emac_mii_mode_sel(HAS_RMII);
#endif /* CONFIG_DRIVER_TI_EMAC */
--
1.7.4.1
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[U-Boot] [PATCH v2 3/7] da850/omap-l138: Add support to read u-boot image from MMC/SD
From: Lad, Prabhakar prabhakar@ti.com
DA850/OMAP-L138 does not support strict MMC/SD boot mode. SPL will
be in SPI flash and U-Boot image will be in MMC/SD card. SPL will
do the low level initialization and then loads the u-boot image
from MMC/SD card.
Define the CONFIG_SPL_MMC_LOAD macro in the DA850/OMAP-L138
configuration file to enable this feature.
Signed-off-by: Lad, Prabhakar prabhakar@ti.com
Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com
Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com
---
arch/arm/cpu/arm926ejs/davinci/spl.c | 12 ++-
drivers/mmc/Makefile |4 ++
drivers/mmc/spl_mmc_load.c | 62 ++
include/configs/da850evm.h |8
include/mmc.h|2 +
5 files changed, 87 insertions(+), 1 deletions(-)
create mode 100644 drivers/mmc/spl_mmc_load.c
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c
b/arch/arm/cpu/arm926ejs/davinci/spl.c
index 74632e5..be397ce 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
@@ -28,6 +28,11 @@
#include ns16550.h
#include malloc.h
#include spi_flash.h
+#include mmc.h
+#include fat.h
+#include version.h
+#include asm/arch/davinci_misc.h
+#include asm/arch/pinmux_defs.h
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
@@ -91,6 +96,11 @@ void board_init_r(gd_t *id, ulong dummy)
gd-have_console = 1;
puts(SPI boot...\n);
+#ifdef CONFIG_SPL_MMC_LOAD
+ spl_mmc_load();
+#else
spi_boot();
-#endif
+#endif /* CONFIG_SPL_MMC_LOAD */
+
+#endif /* CONFIG_SPL_SPI_LOAD */
}
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index c245352..bf4b7d5 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -25,6 +25,10 @@ include $(TOPDIR)/config.mk
LIB:= $(obj)libmmc.o
+ifdef CONFIG_SPL_MMC_LOAD
+COBJS-$(CONFIG_SPL_SPI_LOAD) += spl_mmc_load.o
+endif
+
COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
diff --git a/drivers/mmc/spl_mmc_load.c b/drivers/mmc/spl_mmc_load.c
new file mode 100644
index 000..347dcfe
--- /dev/null
+++ b/drivers/mmc/spl_mmc_load.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include common.h
+#include mmc.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void mmc_load_image(struct mmc *mmc)
+{
+ s32 err;
+ void (*uboot)(void) __noreturn;
+
+ err = mmc-block_dev.block_read(0, CONFIG_SYS_MMC_U_BOOT_OFFS,
+ CONFIG_SYS_SPI_U_BOOT_SIZE/512,
+ (u32 *)CONFIG_SYS_TEXT_BASE);
+
+ if (err = 0) {
+ printf(spl: error reading image %s, err - %d\n,
+ u-boot.img, err);
+ hang();
+ }
+ uboot = (void *) CONFIG_SYS_TEXT_BASE;
+ (*uboot)();
+}
+
+void spl_mmc_load(void)
+{
+ struct mmc *mmc;
+ int err;
+ void (mmc_load_image)(struct mmc *mmc) __noreturn;
+
+ mmc_initialize(gd-bd);
+ mmc = find_mmc_device(0);
+ if (!mmc) {
+ puts(spl: mmc device not found!!\n);
+ hang();
+ } else {
+ puts(spl: mmc device found\n);
+ }
+ err = mmc_init(mmc);
+ if (err) {
+ printf(spl: mmc init failed: err - %d\n, err);
+ hang();
+ }
+ mmc_load_image(mmc);
+}
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 8b4fea1..3bc83d3 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -319,6 +319,14 @@
#define CONFIG_GENERIC_MMC
#define CONFIG_DAVINCI_MMC
+/* Load U-Boot Image From MMC */
+#ifdef CONFIG_SPL_MMC_LOAD
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SYS_MMC_U_BOOT_OFFS 0x75
+#endif
+
/*
* Enable MMC commands only when
* MMC support is present
diff --git a/include/mmc.h b/include/mmc.h
index f52df70..282b54d 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -27,6 +27,7 @@
#define _MMC_H_
#include linux/list.h
+#include linux/compiler.h
#define SD_VERSION_SD 0x2
#define SD_VERSION_2 (SD_VERSION_SD | 0x20)
@@ -320,6
[U-Boot] [PATCH v2 4/7] da850/omap-l138: Make MMC and NOR support mutually exclusive
From: Rajashekhara, Sudhakar sudhakar@ti.com On Logic PD Rev.3 DA850/OMAP-L138 EVM, NOR and MMC/SD cannot work together. This patch enables the MMC/SD support only when NOR support is disabled. NOR Flash identification works even without this patch, but erase and write will have issues. Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com Signed-off-by: Lad, Prabhakar prabhakar@ti.com Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com --- include/configs/da850evm.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 3bc83d3..8236c90 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -314,10 +314,12 @@ #endif /* SD/MMC configuration */ +#ifndef CONFIG_USE_NOR #define CONFIG_MMC #define CONFIG_DAVINCI_MMC_SD1 #define CONFIG_GENERIC_MMC #define CONFIG_DAVINCI_MMC +#endif /* Load U-Boot Image From MMC */ #ifdef CONFIG_SPL_MMC_LOAD -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 5/7] da850/omap-l138: Fix NAND flash timings
From: Lad, Prabhakar prabhakar@ti.com Though Commit id a3f88293ddd13facd734769c1664d35ab4ed681f (da850evm: setup the NAND flash timings) has configured the AEMIF timings, they are not exactly in sync with the timings used in Linux. Linux is configuring the timing register as 0x0804, where as currently it configured to 0x00100084 in U-Boot. This issue was found out when support for NAND SPL is added in U-Boot. Without this patch U-Boot does not come up with SPL. Signed-off-by: Lad, Prabhakar prabhakar@ti.com Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com --- board/davinci/da8xxevm/da850evm.c | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 0d75b84..1c0f75d 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -348,11 +348,11 @@ int board_init(void) * NAND CS setup - cycle counts based on da850evm NAND timings in the * Linux kernel @ 25MHz EMIFA */ - writel((DAVINCI_ABCR_WSETUP(0) | - DAVINCI_ABCR_WSTROBE(1) | - DAVINCI_ABCR_WHOLD(0) | - DAVINCI_ABCR_RSETUP(0) | - DAVINCI_ABCR_RSTROBE(1) | + writel((DAVINCI_ABCR_WSETUP(2) | + DAVINCI_ABCR_WSTROBE(2) | + DAVINCI_ABCR_WHOLD(1) | + DAVINCI_ABCR_RSETUP(1) | + DAVINCI_ABCR_RSTROBE(4) | DAVINCI_ABCR_RHOLD(0) | DAVINCI_ABCR_TA(1) | DAVINCI_ABCR_ASIZE_8BIT), -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 6/7] da850/omap-l138: Add support for NAND SPL
From: Lad, Prabhakar prabhakar@ti.com
This patch adds support for NAND SPL on DA850/OMAP-L138.
Signed-off-by: Lad, Prabhakar prabhakar@ti.com
Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com
Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com
---
Changes for v2:
1:Added a check to perform initializations of serial
console only if CONFIG_SPL_LIBCOMMON_SUPPORT is defined.
arch/arm/cpu/arm926ejs/davinci/spl.c | 15 +++-
include/configs/da850evm.h | 39 +
2 files changed, 43 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c
b/arch/arm/cpu/arm926ejs/davinci/spl.c
index be397ce..c7f2bfa 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
@@ -79,12 +79,7 @@ void board_init_f(ulong dummy)
void board_init_r(gd_t *id, ulong dummy)
{
-#ifdef CONFIG_SPL_NAND_LOAD
- nand_init();
- puts(Nand boot...\n);
- nand_boot();
-#endif
-#ifdef CONFIG_SPL_SPI_LOAD
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN,
CONFIG_SYS_MALLOC_LEN);
@@ -94,7 +89,15 @@ void board_init_r(gd_t *id, ulong dummy)
gd-baudrate = CONFIG_BAUDRATE;
serial_init(); /* serial communications setup */
gd-have_console = 1;
+#endif
+#ifdef CONFIG_SPL_NAND_LOAD
+ puts(Nand boot...\n);
+ nand_init();
+ puts(Nand Initalized...\n);
+ nand_boot();
+#endif
+#ifdef CONFIG_SPL_SPI_LOAD
puts(SPI boot...\n);
#ifdef CONFIG_SPL_MMC_LOAD
spl_mmc_load();
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 8236c90..c0b9077 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -183,6 +183,32 @@
#define CONFIG_SYS_ALE_MASK0x8
#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE (2 10)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 10)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS0x28000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE0x6
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xc108
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP(CONFIG_SYS_NAND_U_BOOT_DST - \
+ CONFIG_SYS_NAND_U_BOOT_SIZE - \
+ CONFIG_SYS_MALLOC_LEN - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_NAND_ECCPOS { \
+ 24, 25, 26, 27, 28, \
+ 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
+ 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
+ 59, 60, 61, 62, 63 }
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+#define CONFIG_SYS_NAND_ECCSIZE512
+#define CONFIG_SYS_NAND_ECCBYTES 10
+#define CONFIG_SYS_NAND_OOBSIZE64
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_LOAD
#endif
/*
@@ -340,13 +366,18 @@
#define CONFIG_CMD_MMC
#endif
-/* defines for SPL */
-#define CONFIG_SPL
+#ifdef CONFIG_USE_SPIFLASH
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_BUS 0
#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
+#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x3
+#endif
+
+/* defines for SPL */
+#define CONFIG_SPL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
@@ -354,11 +385,9 @@
#define CONFIG_SPL_STACK 0x8001ff00
#define CONFIG_SPL_TEXT_BASE 0x8000
#define CONFIG_SPL_MAX_SIZE32768
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
-#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x3
-
/* additions for new relocation code, must added to all boards */
#define CONFIG_SYS_SDRAM_BASE 0xc000
#define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_SDRAM_BASE + 0x1000
- /* Fix this */ \
GENERATED_GBL_DATA_SIZE)
+
#endif /* __CONFIG_H */
--
1.7.4.1
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[U-Boot] [PATCH v2 7/7] da850/omap-l138: add support for direct NOR boot mode
From: Lad, Prabhakar prabhakar@ti.com This patch adds support for direct NOR boot mode on da850/omap-l138. added da850evm_direct_nor entry in boards.cfg to allow to build targets. Signed-off-by: Lad, Prabhakar prabhakar@ti.com Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com --- Changes for v2: 1: Added entry in boards.cfg to build target for direct NOR boot mode. boards.cfg |1 + include/configs/da850evm.h | 22 +- 2 files changed, 22 insertions(+), 1 deletions(-) diff --git a/boards.cfg b/boards.cfg index 0dee43f..2685b73 100644 --- a/boards.cfg +++ b/boards.cfg @@ -122,6 +122,7 @@ cam_enc_4xx arm arm926ejs cam_enc_4xx ait da830evm arm arm926ejs da8xxevm davincidavinci da850_am18xxevm arm arm926ejs da8xxevm davincidavinci da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50 da850evm arm arm926ejs da8xxevm davincidavinci da850evm:MAC_ADDR_IN_SPIFLASH +da850evm_direct_nor arm arm926ejs da8xxevm davincidavinci da850evm:MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT davinci_dm355evm arm arm926ejs dm355evm davincidavinci davinci_dm355leopard arm arm926ejs dm355leopard davincidavinci davinci_dm365evm arm arm926ejs dm365evm davincidavinci diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index c0b9077..ff631d5 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -27,7 +27,10 @@ * Board */ #define CONFIG_DRIVER_TI_EMAC +/* check if direct NOR boot config is used */ +#ifndef CONFIG_DIRECT_NOR_BOOT #define CONFIG_USE_SPIFLASH +#endif /* @@ -43,10 +46,19 @@ #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCKclk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_TEXT_BASE 0xc108 #define CONFIG_SYS_DA850_PLL_INIT #define CONFIG_SYS_DA850_DDR_INIT +#ifdef CONFIG_DIRECT_NOR_BOOT +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DA8XX_GPIO +#define CONFIG_SYS_TEXT_BASE 0x6000 +#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) +#define CONFIG_DA850_LOWLEVEL +#else +#define CONFIG_SYS_TEXT_BASE 0xc108 +#endif + /* * Memory Info */ @@ -376,6 +388,7 @@ #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x3 #endif +#ifndef CONFIG_DIRECT_NOR_BOOT /* defines for SPL */ #define CONFIG_SPL #define CONFIG_SPL_SERIAL_SUPPORT @@ -385,9 +398,16 @@ #define CONFIG_SPL_STACK 0x8001ff00 #define CONFIG_SPL_TEXT_BASE 0x8000 #define CONFIG_SPL_MAX_SIZE32768 +#endif + /* additions for new relocation code, must added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0xc000 + +#ifdef CONFIG_DIRECT_NOR_BOOT +#define CONFIG_SYS_INIT_SP_ADDR0x8001ff00 +#else #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ GENERATED_GBL_DATA_SIZE) +#endif /* CONFIG_DIRECT_NOR_BOOT */ #endif /* __CONFIG_H */ -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 00/20] updates for Keymile Marvell boards
This series adds support for 2 new Kirkwood boards at Keymile: kmnusa and kmcoge5un. All the previously supported boards that had a proper config file now are all supported by the generic km_kirkwood.h config file. This series also adds support for the environment variables in the SPI NOR Flash, for a skippable FPGA download through the BOCO2 CPLD, and for the configuration of a managed Marvell switch that is used on kmnusa. This series also corrects a bug caused by accessing global static tables in board_early_init_f that is called before relocation which must be avoided. Holger Brunck (6): arm/km: add kmnusa board support arm/km: add kmcoge5un board support arm/km: convert mgcoge3un target to km_kirkwood arm/km: remove portl2.h and use km_kirkwood instead arm/km: cleanup km_kirkwood boards arm/km: remove spi toggle command Thomas Herzmann (2): arm/km: add implementation for read_dip_switch arm/km: fix testpin detection for kmcoge5un Valentin Longchamp (12): arm/km: enable spi claim bus arm/km: use correct kw_gpio function for NAND/SPI switching arm/kirkwood: protect the ENV_SPI #defines arm/km: correct init of 88e6352 switch in the reset_phy function arm/km: enable BOCO2 FPGA download support arm/km: redefine piggy 4 reg names to avoid conflicts arm/km: add support for external switch configuration arm/km: enable external switch configuration for kmnusa arm/km: skip FPGA config when already configured arm/km: support the 2 PCIe fpga resets arm/km: implement weak function board_spi_clam_bus/release arm/km: remove calls to kw_gpio_* in board_early_init_f MAINTAINERS |2 + arch/arm/include/asm/arch-kirkwood/config.h | 12 +- board/keymile/common/common.h |5 + board/keymile/km_arm/128M16-1.cfg | 294 + board/keymile/km_arm/256M8-1.cfg| 296 + board/keymile/km_arm/Makefile |8 + board/keymile/km_arm/fpga_config.c | 256 ++ board/keymile/km_arm/km_arm.c | 169 +-- board/keymile/km_arm/managed_switch.c | 316 +++ board/keymile/km_arm/managed_switch.h | 106 + boards.cfg | 10 +- include/configs/km/km_arm.h | 57 - include/configs/km_kirkwood.h | 154 - include/configs/mgcoge3un.h | 87 include/configs/portl2.h| 85 --- 15 files changed, 1583 insertions(+), 274 deletions(-) create mode 100644 board/keymile/km_arm/128M16-1.cfg create mode 100644 board/keymile/km_arm/256M8-1.cfg create mode 100644 board/keymile/km_arm/fpga_config.c create mode 100644 board/keymile/km_arm/managed_switch.c create mode 100644 board/keymile/km_arm/managed_switch.h delete mode 100644 include/configs/mgcoge3un.h delete mode 100644 include/configs/portl2.h ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching
This used to be done with registers direct access, which is not clear
and optimal.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
Signed-off-by: Holger Brunck holger.bru...@keymile.com
cc: Gerlando Falauto gerlando.fala...@keymile.com
cc: Prafulla Wadaskar prafu...@marvell.com
---
board/keymile/km_arm/km_arm.c | 53 +---
include/configs/km/km_arm.h |1 +
2 files changed, 29 insertions(+), 25 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index ed12b5c..e4ae1fb 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -247,15 +247,12 @@ int board_early_init_f(void)
kirkwood_mpp_conf(kwmpp_config, NULL);
/*
-* The FLASH_GPIO_PIN switches between using a
+* The KM_FLASH_GPIO_PIN switches between using a
* NAND or a SPI FLASH. Set this pin on start
* to NAND mode.
*/
- tmp = readl(KW_GPIO0_BASE);
- writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
- tmp = readl(KW_GPIO0_BASE + 4);
- writel(tmp (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
-
+ kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
+ kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
#if defined(CONFIG_SOFT_I2C)
/* init the GPIO for I2C Bitbang driver */
kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
@@ -284,35 +281,41 @@ int board_init(void)
return 0;
}
+int km_hw_spi_bus_claim(int on)
+{
+ int gpio_value = !on;
+
+ if (on) {
+ kwmpp_config[0] = MPP0_SPI_SCn;
+ kwmpp_config[1] = MPP1_SPI_MOSI;
+ kwmpp_config[2] = MPP2_SPI_SCK;
+ kwmpp_config[3] = MPP3_SPI_MISO;
+ } else {
+ kwmpp_config[0] = MPP0_NF_IO2;
+ kwmpp_config[1] = MPP1_NF_IO3;
+ kwmpp_config[2] = MPP2_NF_IO4;
+ kwmpp_config[3] = MPP3_NF_IO5;
+ }
+
+ /* Multi-Purpose Pins Functionality configuration */
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ kw_gpio_set_value(KM_FLASH_GPIO_PIN, gpio_value);
+
+ return 0;
+}
+
#if defined(CONFIG_CMD_SF)
int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- u32 tmp;
if (argc 2)
return cmd_usage(cmdtp);
if ((strcmp(argv[1], off) == 0)) {
printf(SPI FLASH disabled, NAND enabled\n);
- /* Multi-Purpose Pins Functionality configuration */
- kwmpp_config[0] = MPP0_NF_IO2;
- kwmpp_config[1] = MPP1_NF_IO3;
- kwmpp_config[2] = MPP2_NF_IO4;
- kwmpp_config[3] = MPP3_NF_IO5;
-
- kirkwood_mpp_conf(kwmpp_config, NULL);
- tmp = readl(KW_GPIO0_BASE);
- writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
+ km_hw_spi_bus_claim(0);
} else if ((strcmp(argv[1], on) == 0)) {
printf(SPI FLASH enabled, NAND disabled\n);
- /* Multi-Purpose Pins Functionality configuration */
- kwmpp_config[0] = MPP0_SPI_SCn;
- kwmpp_config[1] = MPP1_SPI_MOSI;
- kwmpp_config[2] = MPP2_SPI_SCK;
- kwmpp_config[3] = MPP3_SPI_MISO;
-
- kirkwood_mpp_conf(kwmpp_config, NULL);
- tmp = readl(KW_GPIO0_BASE);
- writel(tmp (~FLASH_GPIO_PIN) , KW_GPIO0_BASE);
+ km_hw_spi_bus_claim(1);
} else {
return cmd_usage(cmdtp);
}
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 056bf53..28b5021 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -231,6 +231,7 @@ int get_scl(void);
#define CONFIG_SYS_KW_SPI_MPP 0x0
#define FLASH_GPIO_PIN 0x0001
+#define KM_FLASH_GPIO_PIN 16
#define MTDIDS_DEFAULT nand0=orion_nand
/* test-only: partitioning needs some tuning, this is just for tests */
--
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[U-Boot] [PATCH 01/20] arm/km: enable spi claim bus
This is required for all our keymile ARM boards. The selected MPPs are the default one for the SPI controller, thus the 0x0 definition. Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com cc: Holger Brunck holger.bru...@keymile.com cc: Prafulla Wadaskar prafu...@marvell.com --- include/configs/km/km_arm.h |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index eb60d29..056bf53 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -227,6 +227,9 @@ int get_scl(void); #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO +/* SPI bus claim MPP configuration */ +#define CONFIG_SYS_KW_SPI_MPP 0x0 + #define FLASH_GPIO_PIN 0x0001 #define MTDIDS_DEFAULT nand0=orion_nand -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 03/20] arm/kirkwood: protect the ENV_SPI #defines
So that they can be redefined by some boards specific values. Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com Signed-off-by: Holger Brunck holger.bru...@keymile.com cc: Gerlando Falauto gerlando.fala...@keymile.com cc: Prafulla Wadaskar prafu...@marvell.com --- arch/arm/include/asm/arch-kirkwood/config.h | 12 +--- 1 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h index 91164eb..a9499b7 100644 --- a/arch/arm/include/asm/arch-kirkwood/config.h +++ b/arch/arm/include/asm/arch-kirkwood/config.h @@ -82,9 +82,15 @@ #ifdef CONFIG_CMD_SF #define CONFIG_HARD_SPI1 #define CONFIG_KIRKWOOD_SPI1 -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 5000/*50Mhz */ +#ifndef CONFIG_ENV_SPI_BUS +# define CONFIG_ENV_SPI_BUS0 +#endif +#ifndef CONFIG_ENV_SPI_CS +# define CONFIG_ENV_SPI_CS 0 +#endif +#ifndef CONFIG_ENV_SPI_MAX_HZ +# define CONFIG_ENV_SPI_MAX_HZ 5000 +#endif #endif /* -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 08/20] arm/km: correct init of 88e6352 switch in the reset_phy function
This is achieved thanks to the support read/write regs for the external
88e6352 switch. The functions for this are added into an own file
managed_switch.c. This is compiled if the define CONFIG_KM_MANAGED_SW_ADDR
was set in the board setup. This define specifies the phy address.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
Signed-off-by: Holger Brunck holger.bru...@keymile.com
cc: Gerlando Falauto gerlando.fala...@keymile.com
cc: Prafulla Wadaskar prafu...@marvell.com
---
board/keymile/common/common.h |6 +
board/keymile/km_arm/Makefile |4 +
board/keymile/km_arm/km_arm.c | 26 +-
board/keymile/km_arm/managed_switch.c | 166 +
include/configs/km_kirkwood.h | 13 +++
5 files changed, 214 insertions(+), 1 deletions(-)
create mode 100644 board/keymile/km_arm/managed_switch.c
diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h
index 6c1f640..49225b8 100644
--- a/board/keymile/common/common.h
+++ b/board/keymile/common/common.h
@@ -125,6 +125,12 @@ struct bfticu_iomap {
int ethernet_present(void);
int ivm_read_eeprom(void);
+
+int ext_switch_reg_write(const char *devname, u8 phy_addr, u8 port,
+ u8 reg, u16 data);
+int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 port,
+ u8 reg, u16 *data);
+
int set_km_env(void);
int fdt_set_node_and_value(void *blob,
char *nodename,
diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile
index aa51255..06079e9 100644
--- a/board/keymile/km_arm/Makefile
+++ b/board/keymile/km_arm/Makefile
@@ -31,6 +31,10 @@ LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o ../common/common.o ../common/ivm.o
+ifdef CONFIG_KM_MANAGED_SW_ADDR
+COBJS += managed_switch.o
+endif
+
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index f59ebfc..8f0a7c3 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -9,6 +9,9 @@
* (C) Copyright 2010
* Heiko Schocher, DENX Software Engineering, h...@denx.de.
*
+ * (C) Copyright 2011, 2012
+ * Valentin Lontgchamp, Keymile AG, valentin.longch...@keymile.com
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -35,6 +38,7 @@
#include miiphy.h
#include asm/io.h
#include asm/arch/cpu.h
+#include asm/errno.h
#include asm/arch/kirkwood.h
#include asm/arch/mpp.h
@@ -384,7 +388,27 @@ void reset_phy(void)
/* reset the phy */
miiphy_reset(name, CONFIG_PHY_BASE_ADR);
}
-#elif !defined(CONFIG_KM_PIGGY4_88E6352)
+#elif defined(CONFIG_KM_PIGGY4_88E6352)
+
+#if defined(CONFIG_KM_MANAGED_SW_ADDR)
+void reset_phy(void)
+{
+ char *name = egiga0;
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* enable autoneg on port 0 phy */
+ ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 0, 0, 0x3300);
+
+ /* egress broadcast franes on all macs, with forwarding */
+ ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 16, 4, 0x000f);
+ ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 20, 4, 0x000f);
+ ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 21, 4, 0x000f);
+}
+#endif
+
+#else
/* Configure and enable MV88E1118 PHY on the piggy*/
void reset_phy(void)
{
diff --git a/board/keymile/km_arm/managed_switch.c
b/board/keymile/km_arm/managed_switch.c
new file mode 100644
index 000..482c18d
--- /dev/null
+++ b/board/keymile/km_arm/managed_switch.c
@@ -0,0 +1,166 @@
+/*
+ * (C) Copyright 2012
+ * Valentin Lontgchamp, Keymile AG, valentin.longch...@keymile.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include common.h
+#include miiphy.h
+#include asm/errno.h
+
+#define SMI_HDR((0x8 | 0x1) 12)
+#define SMI_BUSY_MASK (0x8000)
+#define SMIRD_OP (0x2 10)
+#define SMIWR_OP (0x1 10)
+#define SMI_MASK 0x1f
+#define PORT_SHIFT 5
+
+#define COMMAND_REG0
+#define DATA_REG 1
+
+static int ext_switch_wait_rdy(const char *devname, u8 phy_addr)
+{
+
[U-Boot] [PATCH 18/20] arm/km: implement weak function board_spi_clam_bus/release
They are needed on all km_arm boards where we have the environement
variables in the NOR Flash. First boards using this feature are
kmcoge5un and kmnusa.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
Signed-off-by: Holger Brunck holger.bru...@keymile.com
cc: Gerlando Falauto gerlando.fala...@keymile.com
cc: Prafulla Wadaskar prafu...@marvell.com
---
board/keymile/km_arm/km_arm.c | 26 --
1 files changed, 8 insertions(+), 18 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 8e4c382..a71bd2f 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -36,6 +36,7 @@
#include nand.h
#include netdev.h
#include miiphy.h
+#include spi.h
#include asm/io.h
#include asm/arch/cpu.h
#include asm/errno.h
@@ -307,29 +308,18 @@ int board_late_init(void)
return 0;
}
-int km_hw_spi_bus_claim(int on)
+int board_spi_claim_bus(struct spi_slave *slave)
{
- int gpio_value = !on;
-
- if (on) {
- kwmpp_config[0] = MPP0_SPI_SCn;
- kwmpp_config[1] = MPP1_SPI_MOSI;
- kwmpp_config[2] = MPP2_SPI_SCK;
- kwmpp_config[3] = MPP3_SPI_MISO;
- } else {
- kwmpp_config[0] = MPP0_NF_IO2;
- kwmpp_config[1] = MPP1_NF_IO3;
- kwmpp_config[2] = MPP2_NF_IO4;
- kwmpp_config[3] = MPP3_NF_IO5;
- }
-
- /* Multi-Purpose Pins Functionality configuration */
- kirkwood_mpp_conf(kwmpp_config, NULL);
- kw_gpio_set_value(KM_FLASH_GPIO_PIN, gpio_value);
+ kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
return 0;
}
+void board_spi_release_bus(struct spi_slave *slave)
+{
+ kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
+}
+
#if defined(CONFIG_CMD_SF)
int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 04/20] arm/km: add kmnusa board support
From: Holger Brunck holger.bru...@keymile.com This board is similar to portl2, but it has the u-boot environment in a SPI NOR flash and not in an i2c eeprom like portl2 have. Some other details: - IVM EEPROM is at adress: pca9547:70:9 - PCI is enabled - PIGGY4 is connected via MV88E6352 simple switch. There is no phy between the simple switch and the kirkwood. Signed-off-by: Holger Brunck holger.bru...@keymile.com Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com cc: Gerlando Falauto gerlando.fala...@keymile.com cc: Prafulla Wadaskar prafu...@marvell.com --- MAINTAINERS |1 + board/keymile/km_arm/128M16-1.cfg | 294 + board/keymile/km_arm/km_arm.c |9 +- boards.cfg|1 + include/configs/km/km_arm.h | 44 +- include/configs/km_kirkwood.h | 67 +++-- 6 files changed, 392 insertions(+), 24 deletions(-) create mode 100644 board/keymile/km_arm/128M16-1.cfg diff --git a/MAINTAINERS b/MAINTAINERS index 0445539..aa11268 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -738,6 +738,7 @@ Sergey Lapin sla...@ossfans.org Valentin Longchamp valentin.longch...@keymile.com km_kirkwood ARM926EJS (Kirkwood SoC) + kmnusa ARM926EJS (Kirkwood SoC) mgcoge3un ARM926EJS (Kirkwood SoC) portl2 ARM926EJS (Kirkwood SoC) diff --git a/board/keymile/km_arm/128M16-1.cfg b/board/keymile/km_arm/128M16-1.cfg new file mode 100644 index 000..bcce907 --- /dev/null +++ b/board/keymile/km_arm/128M16-1.cfg @@ -0,0 +1,294 @@ +# +# (C) Copyright 2010 +# Heiko Schocher, DENX Software Engineering, h...@denx.de. +# +# (C) Copyright 2012 +# Valentin Longchamp, Keymile AG, valentin.longch...@keymile.com +# Stefan Bigler, Keymile AG, stefan.big...@keymile.com +# +# (C) Copyright 2012 +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +DATA 0xFFD1 0x0111 # MPP Control 0 Register +# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) +# bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3]) +# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) +# bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5]) +# bit 19-16: 1, MPPSel4 NF_IO[6] +# bit 23-20: 1, MPPSel5 NF_IO[7] +# bit 27-24: 1, MPPSel6 SYSRST_O +# bit 31-28: 0, MPPSel7 GPO[7] + +DATA 0xFFD10004 0x03303300 # MPP Control 1 Register +# bit 3-0: 0, MPPSel8 GPIO[8] +# bit 7-4: 0, MPPSel9 GPIO[9] +# bit 12-8: 3, MPPSel10 UA0_TXD +# bit 15-12: 3, MPPSel11 UA0_RXD +# bit 19-16: 0, MPPSel12 not connected +# bit 23-20: 3, MPPSel13 UA1_TXD +# bit 27-24: 3, MPPSel14 UA1_RXD +# bit 31-28: 0, MPPSel15 GPIO[15] + +DATA 0xFFD10008 0x1100 # MPP Control 2 Register +# bit 3-0: 0, MPPSel16 GPIO[16] +# bit 7-4: 0, MPPSel17 not connected +# bit 12-8: 1, MPPSel18 NF_IO[0] +# bit 15-12: 1, MPPSel19 NF_IO[1] +# bit 19-16: 0, MPPSel20 GPIO[20] +# bit 23-20: 0, MPPSel21 GPIO[21] +# bit 27-24: 0, MPPSel22 GPIO[22] +# bit 31-28: 0, MPPSel23 GPIO[23] + +# MPP Control 3-6 Register untouched (MPP24-49) + +DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register +# bit 2-0: 3, Reserved +# bit 5-3: 3, Reserved +# bit 6: 0, Reserved +# bit 7: 0, RGMII-pads voltage = 3.3V +# bit 10-8: 3, Reserved +# bit 13-11: 3, Reserved +# bit 14:0, Reserved +# bit 15:0, MPP RGMII-pads voltage = 3.3V +# bit 31-16 0x1B1B, Reserved + +DATA 0xFFD20134 0x # L2 RAM Timing 0 Register +# bit 0-1: 2, Tag RAM RTC RAM0 +# bit 3-2: 1, Tag RAM WTC RAM0 +# bit 7-4: 6, Reserve +# bit 9-8: 2, Valid RAM RTC RAM +# bit 11-10: 1, Valid RAM WTC RAM +# bit 13-12: 2, Dirty RAM RTC RAM +# bit 15-14: 1, Dirty RAM WTC RAM +# bit 17-16: 2, Data RAM RTC RAM0 +# bit 19-18: 1, Data RAM WTC RAM0 +# bit 21-20: 2, Data RAM RTC RAM1 +# bit 23-22: 1, Data RAM WTC RAM1 +# bit 25-24: 2, Data RAM RTC RAM2 +# bit 27-26: 1, Data RAM WTC RAM2 +# bit 29-28: 2, Data RAM RTC RAM3 +# bit 31-30: 1, Data RAM WTC RAM4 + +DATA 0xFFD20138 0x # L2 RAM Timing 1 Register +# bit 15-0: ???, Reserve +# bit
[U-Boot] [PATCH 10/20] arm/km: cleanup km_kirkwood boards
From: Holger Brunck holger.bru...@keymile.com Remove config options from boards.cfg and simply add one switch per board and differ afterwards in km_kirkwood.h between the features. More boards are upcoming and therefore it's easier to have this at one place. Signed-off-by: Holger Brunck holger.bru...@keymile.com Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com cc: Gerlando Falauto gerlando.fala...@keymile.com cc: Prafulla Wadaskar prafu...@marvell.com --- boards.cfg|4 ++-- include/configs/km_kirkwood.h |7 ++- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/boards.cfg b/boards.cfg index 0fb8811..9569d1a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -138,8 +138,8 @@ enbw_cmc arm arm926ejs enbw_cmcenbw calimain arm arm926ejs calimain omicrondavinci pogo_e02 arm arm926ejs - cloudengines kirkwood dns325 arm arm926ejs - d-link kirkwood -km_kirkwood arm arm926ejs km_arm keymilekirkwoodkm_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI -km_kirkwood_pci arm arm926ejs km_arm keymilekirkwoodkm_kirkwood:KM_KIRKWOOD_PCI,KM_FPGA_CONFIG +km_kirkwood arm arm926ejs km_arm keymilekirkwoodkm_kirkwood:KM_KIRKWOOD +km_kirkwood_pci arm arm926ejs km_arm keymilekirkwoodkm_kirkwood:KM_KIRKWOOD_PCI kmnusa arm arm926ejs km_arm keymilekirkwoodkm_kirkwood:KM_NUSA mgcoge3unarm arm926ejs km_arm keymilekirkwoodkm_kirkwood:KM_MGCOGE3UN kmcoge5unarm arm926ejs km_arm keymilekirkwoodkm_kirkwood:KMCOGE5UN diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 7d38413..549122b 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -37,15 +37,20 @@ #ifndef _CONFIG_KM_KIRKWOOD_H #define _CONFIG_KM_KIRKWOOD_H +/* KM_KIRKWOOD */ #if defined(CONFIG_KM_KIRKWOOD) #define CONFIG_IDENT_STRING\nKeymile Kirkwood #define CONFIG_HOSTNAMEkm_kirkwood -#undef CONFIG_KIRKWOOD_PCIE_INIT +#define CONFIG_KM_DISABLE_PCIE #define KM_IVM_BUS pca9544a:70:9 /* I2C2 (Mux-Port 1)*/ + +/* KM_KIRKWOOD_PCI */ #elif defined(CONFIG_KM_KIRKWOOD_PCI) #define CONFIG_IDENT_STRING\nKeymile Kirkwood PCI #define CONFIG_HOSTNAMEkm_kirkwood_pci #define KM_IVM_BUS pca9544a:70:9 /* I2C2 (Mux-Port 1)*/ +#define CONFIG_KM_FPGA_CONFIG + /* KM_NUSA */ #elif defined(CONFIG_KM_NUSA) #define KM_IVM_BUS pca9547:70:9 /* I2C2 (Mux-Port 1)*/ -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 12/20] arm/km: add support for external switch configuration
This can be used if we do not want to use an EEPROM for the
configuration.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
---
board/keymile/common/common.h |7 --
board/keymile/km_arm/managed_switch.c | 169 +++--
board/keymile/km_arm/managed_switch.h | 99 +++
3 files changed, 258 insertions(+), 17 deletions(-)
create mode 100644 board/keymile/km_arm/managed_switch.h
diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h
index c58e565..e9abfcd 100644
--- a/board/keymile/common/common.h
+++ b/board/keymile/common/common.h
@@ -125,13 +125,6 @@ struct bfticu_iomap {
int ethernet_present(void);
int ivm_read_eeprom(void);
-
-int ext_switch_reg_write(const char *devname, u8 phy_addr, u8 port,
- u8 reg, u16 data);
-int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 port,
- u8 reg, u16 *data);
-
-
int trigger_fpga_config(void);
int wait_for_fpga_config(void);
int fpga_reset(void);
diff --git a/board/keymile/km_arm/managed_switch.c
b/board/keymile/km_arm/managed_switch.c
index 482c18d..3b022cd 100644
--- a/board/keymile/km_arm/managed_switch.c
+++ b/board/keymile/km_arm/managed_switch.c
@@ -25,15 +25,43 @@
#include miiphy.h
#include asm/errno.h
-#define SMI_HDR((0x8 | 0x1) 12)
-#define SMI_BUSY_MASK (0x8000)
-#define SMIRD_OP (0x2 10)
-#define SMIWR_OP (0x1 10)
-#define SMI_MASK 0x1f
-#define PORT_SHIFT 5
+#include managed_switch.h
-#define COMMAND_REG0
-#define DATA_REG 1
+#if defined(CONFIG_KM_NUSA)
+struct switch_reg sw_conf[] = {
+ /* port 0, PIGY4, autoneg */
+ { PORT(0), PORT_PHY, NO_SPEED_FOR },
+ { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
+ FULL_DUPLEX },
+ { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
+ /* port 1, unused */
+ { PORT(1), PORT_CTRL, PORT_DIS },
+ { PHY(1), PHY_CTRL, PHY_PWR_DOWN },
+ { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+ /* port 2, unused */
+ { PORT(2), PORT_CTRL, PORT_DIS },
+ { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
+ { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+ /* port 3, unused */
+ { PORT(3), PORT_CTRL, PORT_DIS },
+ { PHY(3), PHY_CTRL, PHY_PWR_DOWN },
+ { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+ /* port 4, ICNEV, SerDes, SGMII */
+ { PORT(4), PORT_STATUS, NO_PHY_DETECT },
+ { PORT(4), PORT_PHY, SPEED_1000_FOR },
+ { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ { PHY(4), PHY_CTRL, PHY_PWR_DOWN },
+ { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+ /* port 5, CPU_RGMII */
+ { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
+ FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
+ FULL_DPX_FOR | SPEED_1000_FOR },
+ { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ /* port 6, unused, this port has no phy */
+ { PORT(6), PORT_CTRL, PORT_DIS },
+};
+#endif
static int ext_switch_wait_rdy(const char *devname, u8 phy_addr)
{
@@ -59,7 +87,7 @@ static int ext_switch_wait_rdy(const char *devname, u8
phy_addr)
return 0;
}
-int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 port,
+static int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 port,
u8 reg, u16 *data)
{
int ret;
@@ -85,7 +113,7 @@ int ext_switch_reg_read(const char *devname, u8 phy_addr, u8
port,
return ret;
}
-int ext_switch_reg_write(const char *devname, u8 phy_addr, u8 port,
+static int ext_switch_reg_write(const char *devname, u8 phy_addr, u8 port,
u8 reg, u16 data)
{
int ret;
@@ -114,6 +142,127 @@ int ext_switch_reg_write(const char *devname, u8
phy_addr, u8 port,
return 0;
}
+static int ppu_enable(const char *devname, u8 phy_addr)
+{
+ int i, ret = 0;
+ u16 reg;
+
+ ret = ext_switch_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg);
+ if (ret) {
+ printf(%s: Error reading global ctrl reg\n, __func__);
+ return ret;
+ }
+
+ reg |= PPU_ENABLE;
+
+ ret = ext_switch_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg);
+ if (ret) {
+ printf(%s: Error writing global ctrl reg\n, __func__);
+ return ret;
+ }
+
+ for (i = 0; i 1000; i++) {
+ ext_switch_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS,
+ reg);
+ if ((reg 0xc000) == 0xc000)
+ return 0;
+ udelay(1000);
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int ppu_disable(const char *devname, u8 phy_addr)
+{
+ int i, ret = 0;
+ u16 reg;
+
+ ret = ext_switch_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg);
+ if (ret) {
+ printf(%s: Error reading global ctrl reg\n,
[U-Boot] [PATCH 09/20] arm/km: enable BOCO2 FPGA download support
This adds a first support of the FPGA download for a PCIe FPGA based
on the BOCO2 CPLD.
This takes place in 3 steps, all done accessing the SPICTRL reg of the
BOCO2:
1) start the FPGA config with an access to the FPGA_PROG bit
2) later in the boot sequence, wait for the FPGA_DONE bit to toggle to 1
for the end of the FPGA configuration (with a timeout)
3) reset the FPGA
4) finally remove the access to its config EEPROM from the FPGA so that
the CPU can update the FPGA configuration when the kernel is running
The boards with a PCIe FPGA but without BOCO2 still are supported.
The config option name is CONFIG_KM_FPGA_CONFIG
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
Signed-off-by: Holger Brunck holger.bru...@keymile.com
cc: Gerlando Falauto gerlando.fala...@keymile.com
cc: Prafulla Wadaskar prafu...@marvell.com
---
board/keymile/common/common.h |6 +
board/keymile/km_arm/Makefile |4 +
board/keymile/km_arm/fpga_config.c | 212
board/keymile/km_arm/km_arm.c | 21 +++-
boards.cfg |2 +-
include/configs/km/km_arm.h|3 +
include/configs/km_kirkwood.h |8 +-
7 files changed, 246 insertions(+), 10 deletions(-)
create mode 100644 board/keymile/km_arm/fpga_config.c
diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h
index 49225b8..c58e565 100644
--- a/board/keymile/common/common.h
+++ b/board/keymile/common/common.h
@@ -131,6 +131,12 @@ int ext_switch_reg_write(const char *devname, u8 phy_addr,
u8 port,
int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 port,
u8 reg, u16 *data);
+
+int trigger_fpga_config(void);
+int wait_for_fpga_config(void);
+int fpga_reset(void);
+int toggle_eeprom_spi_bus(void);
+
int set_km_env(void);
int fdt_set_node_and_value(void *blob,
char *nodename,
diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile
index 06079e9..bd824e2 100644
--- a/board/keymile/km_arm/Makefile
+++ b/board/keymile/km_arm/Makefile
@@ -31,6 +31,10 @@ LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o ../common/common.o ../common/ivm.o
+ifdef CONFIG_KM_FPGA_CONFIG
+COBJS += fpga_config.o
+endif
+
ifdef CONFIG_KM_MANAGED_SW_ADDR
COBJS += managed_switch.o
endif
diff --git a/board/keymile/km_arm/fpga_config.c
b/board/keymile/km_arm/fpga_config.c
new file mode 100644
index 000..4356b9a
--- /dev/null
+++ b/board/keymile/km_arm/fpga_config.c
@@ -0,0 +1,212 @@
+/*
+ * (C) Copyright 2012
+ * Valentin Lontgchamp, Keymile AG, valentin.longch...@keymile.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include common.h
+#include i2c.h
+#include asm/errno.h
+
+/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
+#define KM_XLX_PROGRAM_B_PIN39
+
+#define BOCO_ADDR 0x10
+
+#define ID_REG 0x00
+#define BOCO2_ID 0x5b
+
+static int check_boco2(void)
+{
+ int ret;
+ u8 id;
+
+ ret = i2c_read(BOCO_ADDR, ID_REG, 1, id, 1);
+ if (ret) {
+ printf(%s: error reading the BOCO id !!\n, __func__);
+ return ret;
+ }
+
+ return (id == BOCO2_ID);
+}
+
+static int boco_clear_bits(u8 reg, u8 flags)
+{
+ int ret;
+ u8 regval;
+
+ /* give access to the EEPROM from FPGA */
+ ret = i2c_read(BOCO_ADDR, reg, 1, regval, 1);
+ if (ret) {
+ printf(%s: error reading the BOCO @%#x !!\n,
+ __func__, reg);
+ return ret;
+ }
+ regval = ~flags;
+ ret = i2c_write(BOCO_ADDR, reg, 1, regval, 1);
+ if (ret) {
+ printf(%s: error writing the BOCO @%#x !!\n,
+ __func__, reg);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int boco_set_bits(u8 reg, u8 flags)
+{
+ int ret;
+ u8 regval;
+
+ /* give access to the EEPROM from FPGA */
+ ret = i2c_read(BOCO_ADDR, reg, 1, regval, 1);
+ if (ret) {
+ printf(%s: error reading the BOCO @%#x !!\n,
+ __func__, reg);
+ return ret;
+ }
+ regval |= flags;
+
[U-Boot] [PATCH 19/20] arm/km: remove spi toggle command
From: Holger Brunck holger.bru...@keymile.com
Now we toggle between SPI and NAND flash automatically if
we claim the SPI bus. So we can get rid of this command.
Signed-off-by: Holger Brunck holger.bru...@keymile.com
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
cc: Prafulla Wadaskar prafu...@marvell.com
---
board/keymile/km_arm/km_arm.c | 26 --
include/configs/km/km_arm.h |5 ++---
2 files changed, 2 insertions(+), 29 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index a71bd2f..2581d61 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -320,32 +320,6 @@ void board_spi_release_bus(struct spi_slave *slave)
kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
}
-#if defined(CONFIG_CMD_SF)
-int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if (argc 2)
- return cmd_usage(cmdtp);
-
- if ((strcmp(argv[1], off) == 0)) {
- printf(SPI FLASH disabled, NAND enabled\n);
- km_hw_spi_bus_claim(0);
- } else if ((strcmp(argv[1], on) == 0)) {
- printf(SPI FLASH enabled, NAND disabled\n);
- km_hw_spi_bus_claim(1);
- } else {
- return cmd_usage(cmdtp);
- }
-
- return 0;
-}
-
-U_BOOT_CMD(
- spitoggle, 2, 0, do_spi_toggle,
- En-/disable SPI FLASH access,
- on|off - Enable (on) or disable (off) SPI FLASH access\n
- );
-#endif
-
int dram_init(void)
{
/* dram_init must store complete ramsize in gd-ram_size */
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 66f382b..5fbb590 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -257,9 +257,8 @@ int get_scl(void);
#defineCONFIG_KM_UPDATE_UBOOT
\
update= \
- spi on;sf probe 0;sf erase 0 +${filesize};\
- sf write ${load_addr_r} 0 ${filesize};\
- spi off\0
+ sf probe 0;sf erase 0 +${filesize}; \
+ sf write ${load_addr_r} 0 ${filesize};\0
#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
#define CONFIG_KM_NEW_ENV \
--
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[U-Boot] [PATCH 14/20] arm/km: skip FPGA config when already configured
In order to be able to perform board resets without interrupting the
traffic, the configuration of an already properly configured FPGA is
skipped.
This is because some PCIe FPGAs embed some other function that must
continue to work over reset.
It is then the responsibility of the application to trigger a
reconfiguration when needed. This is done by lowering the FPGA_INIT_B
pin for delaying the configuration to u-boot @ next reboot, and then
lower the FPGA_PROGRAM_B signal.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
---
board/keymile/km_arm/fpga_config.c | 41 +++-
1 files changed, 40 insertions(+), 1 deletions(-)
diff --git a/board/keymile/km_arm/fpga_config.c
b/board/keymile/km_arm/fpga_config.c
index 4356b9a..8ac6393 100644
--- a/board/keymile/km_arm/fpga_config.c
+++ b/board/keymile/km_arm/fpga_config.c
@@ -96,12 +96,43 @@ static int boco_set_bits(u8 reg, u8 flags)
#define SPI_REG0x06
#define CFG_EEPROM 0x02
#define FPGA_PROG 0x04
+#define FPGA_INIT_B0x10
#define FPGA_DONE 0x20
+static int fpga_done()
+{
+ int ret = 0;
+ u8 regval;
+
+ /* this is only supported with the boco2 design */
+ if (!check_boco2())
+ return 0;
+
+ ret = i2c_read(BOCO_ADDR, SPI_REG, 1, regval, 1);
+ if (ret) {
+ printf(%s: error reading the BOCO @%#x !!\n,
+ __func__, SPI_REG);
+ return 0;
+ }
+
+ return regval FPGA_DONE ? 1 : 0;
+}
+
+int skip;
+
int trigger_fpga_config(void)
{
int ret = 0;
+ /* if the FPGA is already configured, we do not want to
+* reconfigure it */
+ skip = 0;
+ if (fpga_done()) {
+ printf(PCIe FPGA config: skipped\n);
+ skip = 1;
+ return 0;
+ }
+
if (check_boco2()) {
/* we have a BOCO2, this has to be triggered here */
@@ -111,7 +142,7 @@ int trigger_fpga_config(void)
return ret;
/* trigger the config start */
- ret = boco_clear_bits(SPI_REG, FPGA_PROG);
+ ret = boco_clear_bits(SPI_REG, FPGA_PROG | FPGA_INIT_B);
if (ret)
return ret;
@@ -123,6 +154,11 @@ int trigger_fpga_config(void)
if (ret)
return ret;
+ /* finally, raise INIT_B to remove the config delay */
+ ret = boco_set_bits(SPI_REG, FPGA_INIT_B);
+ if (ret)
+ return ret;
+
} else {
/* we do it the old way, with the gpio pin */
kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
@@ -141,6 +177,9 @@ int wait_for_fpga_config(void)
u8 spictrl;
u32 timeout = 2;
+ if (skip)
+ return 0;
+
if (!check_boco2()) {
/* we do not have BOCO2, this is not really used */
return 0;
--
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[U-Boot] [PATCH 11/20] arm/km: redefine piggy 4 reg names to avoid conflicts
Some very similar #defines for reg addresses are used in a later patch (managed_switch support for km_arm). Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com cc: Holger Brunck holger.bru...@keymile.com cc: Prafulla Wadaskar prafu...@marvell.com --- board/keymile/km_arm/km_arm.c | 22 +++--- 1 files changed, 11 insertions(+), 11 deletions(-) diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index a062333..4a6bff1 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -365,13 +365,13 @@ void dram_init_banksize(void) #if (defined(CONFIG_KM_PIGGY4_88E6061)) -#definePHY_LED_SEL 0x18 -#define PHY_LED0_LINK (0x5) -#define PHY_LED1_ACT (0x84) -#define PHY_LED2_INT (0xe8) -#definePHY_SPEC_CTRL 0x1c +#definePHY_LED_SEL_REG 0x18 +#define PHY_LED0_LINK (0x5) +#define PHY_LED1_ACT (0x84) +#define PHY_LED2_INT (0xe8) +#definePHY_SPEC_CTRL_REG 0x1c #define PHY_RGMII_CLK_STABLE (0x110) -#define PHY_CLSA (0x11) +#define PHY_CLSA (0x11) /* Configure and enable MV88E3018 PHY */ void reset_phy(void) @@ -383,15 +383,15 @@ void reset_phy(void) return; /* RGMII clk transition on data stable */ - if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, reg) != 0) + if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, reg)) printf(Error reading PHY spec ctrl reg\n); - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, - reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0) + if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, + reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) printf(Error writing PHY spec ctrl reg\n); /* leds setup */ - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL, - PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0) + if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, + PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) printf(Error writing PHY LED reg\n); /* reset the phy */ -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 15/20] arm/km: support the 2 PCIe fpga resets
The PCIe FPGAs now have to support 2 resets: one for the non traffic
affecting part (PCIe) and one for the traffic affecting part.
When the FPGA is not reconfigured, we only reset the PCIe part.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
---
board/keymile/km_arm/fpga_config.c | 13 +
1 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/board/keymile/km_arm/fpga_config.c
b/board/keymile/km_arm/fpga_config.c
index 8ac6393..fcc5fe6 100644
--- a/board/keymile/km_arm/fpga_config.c
+++ b/board/keymile/km_arm/fpga_config.c
@@ -99,7 +99,7 @@ static int boco_set_bits(u8 reg, u8 flags)
#define FPGA_INIT_B0x10
#define FPGA_DONE 0x20
-static int fpga_done()
+static int fpga_done(void)
{
int ret = 0;
u8 regval;
@@ -206,25 +206,30 @@ int wait_for_fpga_config(void)
}
#define PRST1 0x4
-#define BRIDGE_RST 0x4
+#define PCIE_RST 0x10
+#define TRAFFIC_RST0x04
int fpga_reset(void)
{
int ret = 0;
+ u8 resets;
if (!check_boco2()) {
/* we do not have BOCO2, this is not really used */
return 0;
}
- ret = boco_clear_bits(PRST1, BRIDGE_RST);
+ /* if we have skipped, we only want to reset the PCIe part */
+ resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST;
+
+ ret = boco_clear_bits(PRST1, resets);
if (ret)
return ret;
/* small delay for the pulse */
udelay(10);
- ret = boco_set_bits(PRST1, BRIDGE_RST);
+ ret = boco_set_bits(PRST1, resets);
if (ret)
return ret;
--
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[U-Boot] [PATCH 05/20] arm/km: add kmcoge5un board support
From: Holger Brunck holger.bru...@keymile.com For u-boot this board is similar to mgcoge3un. But some differences are present. We have a different SDRAM on it and therefore a new SDRAM config file. Additionaly this board has a direct MAC/MAC connection from the kirkwood to a marvell simple switch without a phy inbetween, this needs a new configuration for the mvgbe driver. Signed-off-by: Holger Brunck holger.bru...@keymile.com Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com cc: Gerlando Falauto gerlando.fala...@keymile.com cc: Prafulla Wadaskar prafu...@marvell.com --- MAINTAINERS |1 + board/keymile/km_arm/256M8-1.cfg | 296 ++ boards.cfg |1 + include/configs/km_kirkwood.h| 16 ++- 4 files changed, 312 insertions(+), 2 deletions(-) create mode 100644 board/keymile/km_arm/256M8-1.cfg diff --git a/MAINTAINERS b/MAINTAINERS index aa11268..ef57cd6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -740,6 +740,7 @@ Valentin Longchamp valentin.longch...@keymile.com km_kirkwood ARM926EJS (Kirkwood SoC) kmnusa ARM926EJS (Kirkwood SoC) mgcoge3un ARM926EJS (Kirkwood SoC) + kmcoge5un ARM926EJS (Kirkwood SoC) portl2 ARM926EJS (Kirkwood SoC) Nishanth Menon n...@ti.com diff --git a/board/keymile/km_arm/256M8-1.cfg b/board/keymile/km_arm/256M8-1.cfg new file mode 100644 index 000..3e1237b --- /dev/null +++ b/board/keymile/km_arm/256M8-1.cfg @@ -0,0 +1,296 @@ +# +# (C) Copyright 2012 +# Stefan Bigler, Keymile AG, stefan.big...@keymile.com +# Norbert Mayer, Keymile AG, norbert.ma...@keymile.com +# Deepak Patel, XENTECH Limited, deepak.pa...@xentech.co.uk +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# +# This configuration applies to COGE5 design (ARM-part) +# Two 8-Bit devices are connected on the 16-Bit bus on the same +# chip-select. The supported devices are +# MT47H256M8EB-3IT:C +# MT47H256M8EB-25EIT:C + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +DATA 0xFFD1 0x0111 # MPP Control 0 Register +# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) +# bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3]) +# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) +# bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5]) +# bit 19-16: 1, MPPSel4 NF_IO[6] +# bit 23-20: 1, MPPSel5 NF_IO[7] +# bit 27-24: 1, MPPSel6 SYSRST_O +# bit 31-28: 0, MPPSel7 GPO[7] + +DATA 0xFFD10004 0x03303300 # MPP Control 1 Register +# bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged +# bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged +# bit 12-8: 3, MPPSel10 UA0_TXD +# bit 15-12: 3, MPPSel11 UA0_RXD +# bit 19-16: 0, MPPSel12 not connected +# bit 23-20: 3, MPPSel13 GPIO[14] +# bit 27-24: 3, MPPSel14 GPIO[15] +# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal) + +DATA 0xFFD10008 0x1100 # MPP Control 2 Register +# bit 3-0: 0, MPPSel16 GPIO[16] +# bit 7-4: 0, MPPSel17 not connected +# bit 11-8: 1, MPPSel18 NF_IO[0] +# bit 15-12: 1, MPPSel19 NF_IO[1] +# bit 19-16: 0, MPPSel20 GPIO[20] +# bit 23-20: 0, MPPSel21 GPIO[21] +# bit 27-24: 0, MPPSel22 GPIO[22] +# bit 31-28: 0, MPPSel23 GPIO[23] + +# MPP Control 3-6 Register untouched (MPP24-49) + +DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register +# bit 2-0: 3, Reserved +# bit 5-3: 3, Reserved +# bit 6: 0, Reserved +# bit 7: 0, RGMII-pads voltage = 3.3V +# bit 10-8: 3, Reserved +# bit 13-11: 3, Reserved +# bit 14:0, Reserved +# bit 15:0, MPP RGMII-pads voltage = 3.3V +# bit 31-16 0x1B1B, Reserved + +DATA 0xFFD20134 0x # L2 RAM Timing 0 Register +# bit 0-1: 2, Tag RAM RTC RAM0 +# bit 3-2: 1, Tag RAM WTC RAM0 +# bit 7-4: 6, Reserved +# bit 9-8: 2, Valid RAM RTC RAM +# bit 11-10: 1, Valid RAM WTC RAM +# bit 13-12: 2, Dirty RAM RTC RAM +# bit 15-14: 1, Dirty RAM WTC RAM +# bit 17-16: 2, Data RAM RTC RAM0 +# bit 19-18: 1, Data RAM WTC RAM0 +# bit 21-20: 2, Data RAM RTC RAM1 +# bit 23-22: 1, Data RAM WTC RAM1 +# bit 25-24: 2, Data RAM RTC RAM2 +# bit 27-26: 1, Data RAM WTC RAM2
[U-Boot] [PATCH 13/20] arm/km: enable external switch configuration for kmnusa
The configuration EEPROM should be removed for P1B.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
---
board/keymile/km_arm/km_arm.c | 11 +--
board/keymile/km_arm/managed_switch.c |3 ++-
board/keymile/km_arm/managed_switch.h |7 +++
3 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 4a6bff1..edaadb9 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -43,6 +43,7 @@
#include asm/arch/mpp.h
#include ../common/common.h
+#include managed_switch.h
DECLARE_GLOBAL_DATA_PTR;
@@ -407,13 +408,11 @@ void reset_phy(void)
if (miiphy_set_current_dev(name))
return;
- /* enable autoneg on port 0 phy */
- ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 0, 0, 0x3300);
+#if defined(CONFIG_KM_NUSA)
+ ext_switch_program(name, CONFIG_KM_MANAGED_SW_ADDR);
+#endif
- /* egress broadcast franes on all macs, with forwarding */
- ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 16, 4, 0x000f);
- ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 20, 4, 0x000f);
- ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 21, 4, 0x000f);
+ ext_switch_reset(name, CONFIG_KM_MANAGED_SW_ADDR);
}
#endif
diff --git a/board/keymile/km_arm/managed_switch.c
b/board/keymile/km_arm/managed_switch.c
index 3b022cd..a776f1d 100644
--- a/board/keymile/km_arm/managed_switch.c
+++ b/board/keymile/km_arm/managed_switch.c
@@ -32,9 +32,10 @@ struct switch_reg sw_conf[] = {
/* port 0, PIGY4, autoneg */
{ PORT(0), PORT_PHY, NO_SPEED_FOR },
{ PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ { PHY(0), PHY_1000_CTRL, NO_ADV },
+ { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
{ PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
FULL_DUPLEX },
- { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
/* port 1, unused */
{ PORT(1), PORT_CTRL, PORT_DIS },
{ PHY(1), PHY_CTRL, PHY_PWR_DOWN },
diff --git a/board/keymile/km_arm/managed_switch.h
b/board/keymile/km_arm/managed_switch.h
index c0dcf82..d5b938a 100644
--- a/board/keymile/km_arm/managed_switch.h
+++ b/board/keymile/km_arm/managed_switch.h
@@ -51,6 +51,7 @@
#define PHY_CTRL 0x00
#define PHY_100_MBPS 0x2000
+#define PHY_1_GBPS 0x0040
#define AUTONEG_EN 0x1000
#define AUTONEG_RST0x0200
#define FULL_DUPLEX0x0100
@@ -62,6 +63,12 @@
#define SPEC_PWR_DOWN 0x0004
#define AUTO_MDIX_EN 0x0060
+#define PHY_1000_CTRL 0x9
+
+#define NO_ADV 0x
+#define ADV_1000_FDPX 0x0200
+#define ADV_1000_HDPX 0x0100
+
/* PORT or MAC registers */
#define PORT(itf) (itf+0x10)
--
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[U-Boot] [PATCH 16/20] arm/km: add implementation for read_dip_switch
From: Thomas Herzmann thomas.herzm...@keymile.com
Add a function to read the dip_switch on kmcoge5un. If the
switch is set the actual_bank is set to 0 and this SW is
booted.
Signed-off-by: Thomas Herzmann thomas.herzm...@keymile.com
Signed-off-by: Holger Brunck holger.bru...@keymile.com
---
board/keymile/km_arm/km_arm.c | 14 +-
include/configs/km_kirkwood.h |3 ---
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index edaadb9..d6da632 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -286,12 +286,24 @@ int board_init(void)
int board_late_init(void)
{
+#if defined(CONFIG_KMCOGE5UN)
+/* I/O pin to erase flash RGPP09 = MPP43 */
+#define KM_FLASH_ERASE_ENABLE 43
+ u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
+
+ /* if pin 1 do full erase */
+ if (dip_switch != 0) {
+ /* start bootloader */
+ puts(DIP: Enabled\n);
+ setenv(actual_bank, 0);
+ }
+#endif
+
#if defined(CONFIG_KM_FPGA_CONFIG)
wait_for_fpga_config();
fpga_reset();
toggle_eeprom_spi_bus();
#endif
-
return 0;
}
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index 549122b..9ecfcf4 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -184,8 +184,5 @@
#undef CONFIG_KIRKWOOD_PCIE_INIT
#endif
-#ifndef CONFIG_KM_FPGA_CONFIG
-#undef BOARD_LATE_INIT
-#endif
#endif /* _CONFIG_KM_KIRKWOOD */
--
1.7.1
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[U-Boot] [PATCH 06/20] arm/km: convert mgcoge3un target to km_kirkwood
From: Holger Brunck holger.bru...@keymile.com
Use the generic header km_kirkwood.h and get rid of the
board specific header.
Signed-off-by: Holger Brunck holger.bru...@keymile.com
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
cc: Gerlando Falauto gerlando.fala...@keymile.com
cc: Prafulla Wadaskar prafu...@marvell.com
---
board/keymile/km_arm/km_arm.c |9 ++--
boards.cfg|2 +-
include/configs/km_kirkwood.h | 46 +
include/configs/mgcoge3un.h | 87 -
4 files changed, 51 insertions(+), 93 deletions(-)
delete mode 100644 include/configs/mgcoge3un.h
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index ffe13cd..5133446 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -113,7 +113,7 @@ u32 kwmpp_config[] = {
0
};
-#if defined(CONFIG_MGCOGE3UN)
+#if defined(CONFIG_KM_MGCOGE3UN)
/*
* Wait for startup OK from mgcoge3ne
*/
@@ -133,8 +133,7 @@ int startup_allowed(void)
}
#endif
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \
- defined(CONFIG_KM_PIGGY4_88E6352))
+#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
/*
* All boards with PIGGY4 connected via a simple switch have ethernet always
* present.
@@ -202,7 +201,7 @@ int misc_init_r(void)
printf(Overwriting MACH_TYPE with %d!!!\n, mach_type);
gd-bd-bi_arch_number = mach_type;
}
-#if defined(CONFIG_MGCOGE3UN)
+#if defined(CONFIG_KM_MGCOGE3UN)
char *wait_for_ne;
wait_for_ne = getenv(waitforne);
if (wait_for_ne != NULL) {
@@ -351,7 +350,7 @@ void dram_init_banksize(void)
}
}
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
+#if (defined(CONFIG_KM_MGCOGE3UN)|defined(CONFIG_PORTL2))
#definePHY_LED_SEL 0x18
#define PHY_LED0_LINK (0x5)
diff --git a/boards.cfg b/boards.cfg
index d174371..9e4de8e 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -141,7 +141,7 @@ dns325 arm arm926ejs -
d-link
km_kirkwood arm arm926ejs km_arm
keymilekirkwoodkm_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
km_kirkwood_pci arm arm926ejs km_arm
keymilekirkwoodkm_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX
kmnusa arm arm926ejs km_arm
keymilekirkwoodkm_kirkwood:KM_NUSA
-mgcoge3unarm arm926ejs km_arm
keymilekirkwood
+mgcoge3unarm arm926ejs km_arm
keymilekirkwoodkm_kirkwood:KM_MGCOGE3UN
kmcoge5unarm arm926ejs km_arm
keymilekirkwoodkm_kirkwood:KMCOGE5UN
portl2 arm arm926ejs km_arm
keymilekirkwood
inetspace_v2 arm arm926ejs netspace_v2 LaCie
kirkwood lacie_kw:INETSPACE_V2
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index e6f0e36..d1f3351 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -58,6 +58,20 @@
#define CONFIG_KM_FPGA_CONFIG
#define CONFIG_KM_PIGGY4_88E6352
+/* KM_MGCOGE3UN */
+#elif defined(CONFIG_KM_MGCOGE3UN)
+#define CONFIG_IDENT_STRING\nKeymile COGE3UN
+#define CONFIG_HOSTNAMEmgcoge3un
+#define KM_IVM_BUS pca9547:70:9 /* I2C2 (Mux-Port 1)*/
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG \
+ $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
+#define CONFIG_KM_BOARD_EXTRA_ENV waitforne=true\0
+#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3
+#define CONFIG_KM_DISABLE_PCIE
+#define CONFIG_KM_PIGGY4_88E6061
+
+/* KMCOGE5UN */
#elif defined(CONFIG_KMCOGE5UN)
#define CONFIG_IDENT_STRING\nKeymile COGE5UN
#define KM_IVM_BUS pca9547:70:9 /* I2C2 (Mux-Port 1)*/
@@ -111,7 +125,39 @@
#endif
+#ifdef CONFIG_KM_PIGGY4_88E6061
+/*
+ * Some keymile boards like mgcoge3un have their PIGGY4 connected via
+ * an Marvell 88E6061 simple switch.
+ * In this case we have to change the default settings for the
+ * ethernet phy connected to the kirkwood.
+ * In this case 100MB full duplex and autoneg off
+ */
+#define PORT_SERIAL_CONTROL_VALUE ( \
+ MVGBE_FORCE_LINK_PASS | \
+ MVGBE_DIS_AUTO_NEG_FOR_DUPLX| \
+ MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL| \
+ MVGBE_ADV_NO_FLOW_CTRL | \
+ MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
+ MVGBE_FORCE_BP_MODE_NO_JAM | \
+ (1 9) /* Reserved bit has to be 1 */ | \
+ MVGBE_DO_NOT_FORCE_LINK_FAIL| \
+ MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
+
[U-Boot] [PATCH 20/20] arm/km: remove calls to kw_gpio_* in board_early_init_f
These functions tried to access two static tables before relocation
(board_early_init_f is executed before relocation). But these static
tables lie in the bss section which is not valid before relocation.
These accesses then overwrote some parts of u-boot binary before it was
relocated. For the kmnusa build, this results in a corrupted important
env variable (bootcmd) but it may be that some other parts of the u-boot
binary are corrupted.
This patch solves this problem by moving all the kw_gpio_* calls to
board_init, which should be early enough in the boot sequence. The only
calls that could not be moved is the one for the SOFT (bitbang) I2C, and
they have been replaced by a direct access to the GPIO dataout Control
register to set the two GPIOs as output.
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
cc: Holger Brunck holger.bru...@keymile.com
cc: Prafulla Wadaskar prafu...@marvell.com
---
board/keymile/km_arm/km_arm.c | 34 --
include/configs/km/km_arm.h |1 +
2 files changed, 25 insertions(+), 10 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 2581d61..c13be71 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -248,9 +248,27 @@ int misc_init_r(void)
int board_early_init_f(void)
{
+#if defined(CONFIG_SOFT_I2C)
u32 tmp;
+ /* set the 2 bitbang i2c pins as output gpios */
+ tmp = readl(KW_GPIO0_BASE + 4);
+ writel(tmp (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
+#endif
+
kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /*
+* arch number of board
+*/
+ gd-bd-bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
+
+ /* address of boot parameters */
+ gd-bd-bi_boot_params = kw_sdram_bar(0) + 0x100;
/*
* The KM_FLASH_GPIO_PIN switches between using a
@@ -259,24 +277,20 @@ int board_early_init_f(void)
*/
kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
+
#if defined(CONFIG_SOFT_I2C)
- /* init the GPIO for I2C Bitbang driver */
+ /* reinit the GPIO for I2C Bitbang driver so that the now
+* available gpio framework is consistent. The calls to
+* direction output in are not necessary, they are already done in
+* board_early_init_f */
kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
- kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0);
- kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0);
#endif
+
#if defined(CONFIG_SYS_EEPROM_WREN)
kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
#endif
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd-bd-bi_boot_params = kw_sdram_bar(0) + 0x100;
#if defined(CONFIG_KM_FPGA_CONFIG)
trigger_fpga_config();
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 5fbb590..8a6b345 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -192,6 +192,7 @@ int get_sda(void);
int get_scl(void);
#define KM_KIRKWOOD_SDA_PIN8
#define KM_KIRKWOOD_SCL_PIN9
+#define KM_KIRKWOOD_SOFT_I2C_GPIOS 0x0300
#define KM_KIRKWOOD_ENV_WP 38
#define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0)
--
1.7.1
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[U-Boot] [PATCH 07/20] arm/km: remove portl2.h and use km_kirkwood instead
From: Holger Brunck holger.bru...@keymile.com The additional headerfile is unneeded here, we can use the generic km_kirkwood.h instead. And we can use the better config option KM_PIGGY4_88E6061 for the specific features for boards with this design in km_arm.c. Signed-off-by: Holger Brunck holger.bru...@keymile.com Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com cc: Gerlando Falauto gerlando.fala...@keymile.com cc: Prafulla Wadaskar prafu...@marvell.com --- board/keymile/km_arm/km_arm.c |2 +- boards.cfg|2 +- include/configs/km_kirkwood.h |8 include/configs/portl2.h | 85 - 4 files changed, 10 insertions(+), 87 deletions(-) delete mode 100644 include/configs/portl2.h diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 5133446..f59ebfc 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -350,7 +350,7 @@ void dram_init_banksize(void) } } -#if (defined(CONFIG_KM_MGCOGE3UN)|defined(CONFIG_PORTL2)) +#if (defined(CONFIG_KM_PIGGY4_88E6061)) #definePHY_LED_SEL 0x18 #define PHY_LED0_LINK (0x5) diff --git a/boards.cfg b/boards.cfg index 9e4de8e..4ca611a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -143,7 +143,7 @@ km_kirkwood_pci arm arm926ejs km_arm keymile kmnusa arm arm926ejs km_arm keymilekirkwoodkm_kirkwood:KM_NUSA mgcoge3unarm arm926ejs km_arm keymilekirkwoodkm_kirkwood:KM_MGCOGE3UN kmcoge5unarm arm926ejs km_arm keymilekirkwoodkm_kirkwood:KMCOGE5UN -portl2 arm arm926ejs km_arm keymilekirkwood +portl2 arm arm926ejs km_arm keymilekirkwoodkm_kirkwood:KM_PORTL2 inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:NET2BIG_V2 netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MAX_V2 diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index d1f3351..fbe714b 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -83,6 +83,14 @@ #define CONFIG_HOSTNAMEkmcoge5un #define CONFIG_KM_DISABLE_PCIE #define CONFIG_KM_PIGGY4_88E6352 + +/* KM_PORTL2 */ +#elif defined(CONFIG_KM_PORTL2) +#define CONFIG_IDENT_STRING\nKeymile Port-L2 +#define CONFIG_HOSTNAMEportl2 +#define KM_IVM_BUS pca9544a:70:9 /* I2C2 (Mux-Port 1)*/ +#define CONFIG_KM_PIGGY4_88E6061 + #else #error (Board unsupported) #endif diff --git a/include/configs/portl2.h b/include/configs/portl2.h deleted file mode 100644 index e436cfe..000 --- a/include/configs/portl2.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor www.marvell.com - * Prafulla Wadaskar prafu...@marvell.com - * - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, s...@denx.de. - * - * (C) Copyright 2010-2011 - * Holger Brunck, Keymile GmbH Hannover, holger.bru...@keymile.com. - * Valentin Longchamp, Keymile AG Bern, valentin.longch...@keymile.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* for linking errors see - * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ - -#ifndef _CONFIG_PORTL2_H -#define _CONFIG_PORTL2_H - -/* include common defines/options for all arm based Keymile boards */ -#include km/km_arm.h - -/* - * Version number information - */ -#define CONFIG_IDENT_STRING\nKeymile Port-L2 -#define CONFIG_HOSTNAMEportl2 -#define CONFIG_PORTL2 - -#define KM_IVM_BUS pca9544a:70:9 /* I2C2 (Mux-Port 1)*/ -/* - * Note: This is only valid for HW P1A if you got an outdated P1A - * use KM_ENV_BUS pca9544a:70:a - */ -#define
[U-Boot] [PATCH 17/20] arm/km: fix testpin detection for kmcoge5un
From: Thomas Herzmann thomas.herzm...@keymile.com
On kmcoge5un unfortunately the HW wiring is differently to
other km arm boards.
Signed-off-by: Thomas Herzmann thomas.herzm...@keymile.com
Signed-off-by: Holger Brunck holger.bru...@keymile.com
---
board/keymile/km_arm/km_arm.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index d6da632..8e4c382 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -533,7 +533,11 @@ int get_scl(void)
int post_hotkeys_pressed(void)
{
+#if defined(CONFIG_KMCOGE5UN)
+ return kw_gpio_get_value(KM_POST_EN_L);
+#else
return !kw_gpio_get_value(KM_POST_EN_L);
+#endif
}
ulong post_word_load(void)
--
1.7.1
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[U-Boot] [PATCH v2] da850/omap-l138: Enable auto negotiation in RMII mode
From: Rajashekhara, Sudhakar sudhakar@ti.com
On DA850/OMAP-L138 it was observed that in RMII mode,
auto negotiation was not performed. This patch enables
auto negotiation in RMII mode. Without this patch, EMAC
initialization takes more time and sometimes tftp fails
in RMII mode.
Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com
Signed-off-by: Lad, Prabhakar prabhakar@ti.com
Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com
---
Changes for V2:
1: Fix build warning and enable auto negotiation for
phy's which are connected.
drivers/net/davinci_emac.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index fbd0f1b..26cc1f0 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -895,5 +895,13 @@ int davinci_emac_initialize(void)
miiphy_register(phy[i].name, davinci_mii_phy_read,
davinci_mii_phy_write);
}
+
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) \
+ defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+ for (i = 0; i num_phy; i++) {
+ if (phy[i].is_phy_connected(i))
+ phy[i].auto_negotiate(i);
+ }
+#endif
return(1);
}
--
1.7.4.1
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Re: [U-Boot] [PATCH] da850/omap-l138: Enable auto negotiation in RMII mode
Hi Eric, On Wed, Jun 06, 2012 at 22:47:46, Eric Bénard wrote: Hi Prabhakar, Le Fri, 1 Jun 2012 19:04:37 +0530, Prabhakar Lad prabhakar@ti.com a écrit : From: Rajashekhara, Sudhakar sudhakar@ti.com On DA850/OMAP-L138 it was observed that in RMII mode, auto negotiation was not performed. This patch enables auto negotiation in RMII mode. Without this patch, EMAC initialization takes more time and sometimes tftp fails in RMII mode. Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com Signed-off-by: Lad, Prabhakar prabhakar@ti.com Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com Tested-by: Eric Bénard e...@eukrea.com on an AM1808 with a RMII PHY where tftp was nearly always failing. This patch had some build warnings which has been fixed in v2 version (http://www.mail-archive.com/u-boot@lists.denx.de/msg85270.html) can you test this patch and Ack it. Thx, --Prabhakar Lad Eric ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] [resend] kwboot: boot kirkwood SoCs over a serial link
Hi all, On Sun, May 27, 2012 at 11:44:51PM +0200, Luka Perkov wrote: The kwboot program boots boards based on Marvell's Kirkwood platform via Xmodem over their integrated UART. Signed-off-by: Daniel Stodden daniel.stod...@googlemail.com Acked-by: Luka Perkov ub...@lukaperkov.net Tested-By: Holger Brunck holger.bru...@keymile.com Tested-By: David Purdy david.c.pu...@gmail.com Tested-by: Simon Guinot simon.gui...@sequanux.org --- Changes from version 2: * fix timeouts in kwboot_tty_recv * revert indentation on manpage * on manpage note that TTY isn't optional * add David and Luka into the manpage Changes from version v1: * fix man page * minor cosmetic fixes in tools/kwboot.c I'm resending this patch because original version 3 was not following patch submission guidlines. doc/kwboot.1 | 84 +++ tools/Makefile |6 + tools/kwboot.c | 742 3 files changed, 832 insertions(+) If no one has objections to the code I would love to see it merged. Any NACK's or ACK's? Regards, Luka ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fix IDE_BUS(dev) macro
Hi Albert, On Tue, May 15, 2012 at 09:42:59PM +0200, Albert ARIBAUD wrote: On Sun, Apr 29, 2012 at 10:19:41PM +0200, Luka Perkov wrote: On Thu, Apr 19, 2012 at 08:38:19AM +0200, Albert ARIBAUD wrote: Not my main area of expertise here, but I am not sure how this plays on Marvell non-kirkwood platforms (e.g., orion5x). ISTR it is not the first time we deal with the whole IDE number of bus / number of ports [ / useable ports ] issue, and we may be running in circles here, fixing one platform and breaking another. I'll try this on EDMiniV2 in the coming days, and let people know the results in this thread. I was just wondering did you have the time to test this patch on your board? Albert, did you maybe have time to test this patch. I have included it bellow so you dont have to search for it... Signed-off-by: Simon Baatzgmbno...@gmail.com Tested-by: Luka Perkovub...@lukaperkov.net --- Simon discovered this while adding support for new board IB NAS6210. More info can be found here: http://lists.denx.de/pipermail/u-boot/2012-April/122525.html include/ide.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/ide.h b/include/ide.h index 8ecc9dd..385e909 100644 --- a/include/ide.h +++ b/include/ide.h @@ -24,7 +24,7 @@ #ifndef_IDE_H #define _IDE_H -#define IDE_BUS(dev)(dev 1) +#define IDE_BUS(dev)(dev / (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS)) #defineATA_CURR_BASE(dev) (CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)]) Sorry, been busier than usual. I'll try and test this tomorrow night; if not, that'll be next week I'm afraid. It's me beeing boring again, sorry... Can we get your feedback on this one? Regards, Luka ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] pull request for u-boot-tegra/master
Albert,
On Thu, May 31, 2012 at 9:47 AM, Tom Warren twarren.nvi...@gmail.com wrote:
Albert,
Please pull u-boot-tegra/master into ARM master. Thanks!
Haven't seen a reply, so repinging you.
Thanks,
Tom
The following changes since commit 2ca4a209a5b961ad1be8782c68dabe326d77dfaf:
SRICHARAN R (1):
OMAP4/5: Change omap4_sdp, omap4_panda, omap5_evm maintainer
are available in the git repository at:
git://git.denx.de/u-boot-tegra master
Lucas Stach (2):
tegra: sync SDIO1 pingroup enum name with TRM
tegra: add SDIO1 funcmux entry for UARTA
Simon Glass (1):
tegra: Correct PLL access in ap20.c and clock.c
Stephen Warren (22):
tegra: paz00: fix typo in SD slot CD detect GPIO
tegra: add alternate UART1 funcmux entry
tegra: Whistler board support
tegra: remove some cruft from CONFIG_EXTRA_ENV_SETTINGS
tegra: flesh out bootcmd
tegra: whistler: reduce and comment network cfg options
tegra: seaboard: add support for USB networking
tegra: add UART1 on GPU funcmux entry
tegra: add SDMMC1 on SDIO1 funcmux entry
tegra: Compulab TrimSlice board support
tegra: harmony: add device tree support
tegra: paz00: add device tree support
tegra: remove CONFIG_USB_ETHER_SMSC95XX from boards without it
tegra: ventana: add own device tree, enable USB
env_mmc: align buffers using ALLOC_CACHE_ALIGN_BUFFER
sf: winbond: Add support for the Winbond W25Q80BL
tegra: ventana: store environment in eMMC
tegra: whistler: store environment in eMMC
tegra: trimslice: store environment in SPI flash
tegra: paz00: store environment in eMMC
tegra: seaboard: disable SPI, move environment to eMMC
tegra: trimslice: fix a couple typos
Tom Warren (6):
spi: Tegra2: Seaboard: fix UART corruption during SPI transactions
spi: Tegra2: Seaboard: enable SPI/UART corruption fix
spi: tegra2: rename tegra2_spi.* to tegra_spi.*
mmc: tegra2: rename tegra2_mmc.* to tegra_mmc.*
gpio: tegra2: rename tegra2_gpio.* to tegra_gpio.*
arm: Tegra: Use ODMDATA from BCT in IRAM
amar...@nvidia.com (1):
tegra: override compiler flags for low level init code
MAINTAINERS | 2 +
arch/arm/cpu/armv7/tegra2/ap20.c | 28 -
arch/arm/cpu/armv7/tegra2/board.c | 18 +++-
arch/arm/cpu/armv7/tegra2/clock.c | 4 +-
arch/arm/cpu/armv7/tegra2/config.mk | 7 +-
arch/arm/cpu/armv7/tegra2/funcmux.c | 30 +-
arch/arm/include/asm/arch-tegra2/clock.h | 5 +-
arch/arm/include/asm/arch-tegra2/funcmux.h | 4 +
arch/arm/include/asm/arch-tegra2/gpio.h | 7 +-
arch/arm/include/asm/arch-tegra2/pinmux.h | 2 +-
arch/arm/include/asm/arch-tegra2/tegra2.h | 4 +
.../asm/arch-tegra2/{tegra2_spi.h = tegra_spi.h} | 9 +-
arch/arm/include/asm/arch-tegra2/uart-spi-switch.h | 4 +-
board/compal/dts/tegra2-paz00.dts | 57 ++
board/compal/paz00/paz00.c | 12 +-
board/compulab/dts/tegra2-trimslice.dts | 57 ++
board/compulab/trimslice/Makefile | 49
board/compulab/trimslice/trimslice.c | 73
board/nvidia/common/uart-spi-switch.c | 29 ++
board/nvidia/dts/tegra2-harmony.dts | 57 ++
board/nvidia/dts/tegra2-ventana.dts | 57 ++
board/nvidia/dts/tegra2-whistler.dts | 67 +++
board/nvidia/harmony/harmony.c | 4 +-
board/nvidia/seaboard/seaboard.c | 4 +-
board/nvidia/whistler/Makefile | 48
board/nvidia/whistler/whistler.c | 116 +++
boards.cfg | 2 +
common/env_mmc.c | 10 +-
drivers/gpio/Makefile | 2 +-
drivers/gpio/{tegra2_gpio.c = tegra_gpio.c} | 2 +-
drivers/mmc/Makefile | 2 +-
drivers/mmc/{tegra2_mmc.c = tegra_mmc.c} | 4 +-
drivers/mmc/{tegra2_mmc.h = tegra_mmc.h} | 8 +-
drivers/mtd/spi/winbond.c | 8 ++
drivers/spi/Makefile | 2 +-
drivers/spi/{tegra2_spi.c = tegra_spi.c} | 17 +++-
include/configs/harmony.h | 29 -
include/configs/medcom.h | 6 +-
include/configs/paz00.h | 34 +-
include/configs/plutux.h | 6 +-
include/configs/seaboard.h | 35 +++---
include/configs/tegra2-common-post.h | 117
Re: [U-Boot] [PATCH v2 07/10] tegra20: add SPL config options for seaboard
On 06/07/2012 01:15 AM, Sughosh Ganu wrote: On Wed Jun 06, 2012 at 10:44:59AM -0600, Stephen Warren wrote: On 06/05/2012 03:20 PM, Allen Martin wrote: snip diff --git a/include/configs/tegra2-spl.h b/include/configs/tegra2-spl.h + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. Being a new file, this should be GPLv2 not GPLv2+. u-boot uses GPLv2+. http://www.denx.de/wiki/view/U-Boot/Patches#Attributing_Code_Copyrights_Sign http://www.mail-archive.com/u-boot@lists.denx.de/msg26569.html Sughosh, I guess I'm a little confused here. COPYING in the U-Boot source tree states the following: U-Boot is Free Software. It is copyrighted by Wolfgang Denk and many others who contributed code (see the actual source code for details). You can redistribute U-Boot and/or modify it under the terms of version 2 of the GNU General Public License as published by the Free Software Foundation. Most of it can also be distributed, at your option, under any later version of the GNU General Public License -- see individual files for exceptions. ... which explicitly allows for either GPLv2 or GPLv2+ code. There is certainly GPLv2-only code already in U-Boot. Why do you say that GPLv2-only code isn't allowed? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/CoreNet: add tool to support pbl image build.
On 06/06/2012 10:16 PM, Xie Shaohui-B21989 wrote: -Original Message- From: Wood Scott-B07421 Sent: Thursday, June 07, 2012 2:19 AM To: Xie Shaohui-B21989 Cc: Wood Scott-B07421; u-boot@lists.denx.de; Tabi Timur-B04825 Subject: Re: [U-Boot] [PATCH] powerpc/CoreNet: add tool to support pbl image build. On 06/05/2012 09:45 PM, Xie Shaohui-B21989 wrote: Can Timur's tool do it automatically, or by some arguments provided? And even though, there will be two files for configuration, one is RCW output from Timur's tool, and another is PBI commands. This is too much for the tool; it has only one entry for configuration file. Too much for which tool, and why can't that be changed? [Xie Shaohui] The mkimage structure provides one entry to indicate the configuration file, is it OK to add a more entry just for PBL? I don't see why not. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 08/10] tegra20: add u-boot.t2 target
On Wed, Jun 06, 2012 at 07:02:45PM -0700, Stephen Warren wrote: On 06/06/2012 04:00 PM, Allen Martin wrote: Yes, that's the intention. Although I do have plans down the road for adding memory initialization to the SPL so I can use it for boot/flashing when in recovery mode and there's no BCT. In the normal case they have to be used together. How would that work; in the regular boot process, SPL would be linked to e.g. 00108000 since the boot ROM will put it into SDRAM. However, in recovery mode, code will be downloaded to the IRAM, so would have to be linked to a different address, and hence the same SPL binary couldn't be used. At that point, aren't we looking at: * Regular boot SPL, which just sets up a few PLLs and jump-starts the A9s. * Regular boot full-blown U-Boot to run on the A9s. * Some third build t run from IRAM. Or am I missing something? No, that's spot on, it's just that #3 and #1 above are very similar, only a few build/config tweaks should separate them. I've already hacked up an SPL to boot from IRAM as proof of concept and loaded it in recovery mode. But you're right, it has to be a separate build. -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 07/10] tegra20: add SPL config options for seaboard
On Thu Jun 07, 2012 at 10:36:53AM -0600, Stephen Warren wrote: On 06/07/2012 01:15 AM, Sughosh Ganu wrote: On Wed Jun 06, 2012 at 10:44:59AM -0600, Stephen Warren wrote: On 06/05/2012 03:20 PM, Allen Martin wrote: snip diff --git a/include/configs/tegra2-spl.h b/include/configs/tegra2-spl.h + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. Being a new file, this should be GPLv2 not GPLv2+. u-boot uses GPLv2+. http://www.denx.de/wiki/view/U-Boot/Patches#Attributing_Code_Copyrights_Sign http://www.mail-archive.com/u-boot@lists.denx.de/msg26569.html Sughosh, I guess I'm a little confused here. COPYING in the U-Boot source tree states the following: U-Boot is Free Software. It is copyrighted by Wolfgang Denk and many others who contributed code (see the actual source code for details). You can redistribute U-Boot and/or modify it under the terms of version 2 of the GNU General Public License as published by the Free Software Foundation. Most of it can also be distributed, at your option, under any later version of the GNU General Public License -- see individual files for exceptions. ... which explicitly allows for either GPLv2 or GPLv2+ code. There is certainly GPLv2-only code already in U-Boot. Why do you say that GPLv2-only code isn't allowed? I guess that could be because some of the existing files in u-boot are released under GPLv2 only license -- hence a separate mention that most of the files can be distributed under any later version too . Both Wolfgang and Detlev have stated many a times on the mailing list earlier that all new files need to be released under GPLv2+, and not GPLv2 only. -sughosh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] cmd_nand: fix crashing bug in nand read/write
Commit 418396e212b59bf907dbccad997ff50f7eb61b16 introduced a
bug that causes nand read and nand write to crash in strcmp
due to a null pointer.
Root cause is that strchr(cmd, '.') returns a null pointer when
the input string does not contain a '.'
The strcmp function does not check for null pointers, resulting
in a crash.
Signed-off-by: Steve Sakoman st...@sakoman.com
---
common/cmd_nand.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index fa44295..a91ccf4 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -617,7 +617,7 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *
const argv[])
s = strchr(cmd, '.');
- if (!strcmp(s, .raw)) {
+ if (s !strcmp(s, .raw)) {
raw = 1;
if (arg_off(argv[3], dev, off, size))
--
1.7.1
___
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Re: [U-Boot] [PATCH] cmd_nand: fix crashing bug in nand read/write
On 06/07/2012 12:19 PM, Steve Sakoman wrote: Commit 418396e212b59bf907dbccad997ff50f7eb61b16 introduced a bug that causes nand read and nand write to crash in strcmp due to a null pointer. Root cause is that strchr(cmd, '.') returns a null pointer when the input string does not contain a '.' The strcmp function does not check for null pointers, resulting in a crash. Signed-off-by: Steve Sakoman st...@sakoman.com Applied to u-boot-nand-flash, thanks! This was missed in testing because U-Boot on PowerPC unfortunately has a valid mapping at NULL. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] mx53ard: Remove unused CONFIG_MII_GASKET
From: Fabio Estevam fabio.este...@freescale.com CONFIG_MII_GASKET is not defined anywhere, so remove it. Signed-off-by: Fabio Estevam fabio.este...@freescale.com --- include/configs/mx53ard.h |1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index f48a41e..f59960e 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -68,7 +68,6 @@ /* Eth Configs */ #define CONFIG_HAS_ETH1 #define CONFIG_MII -#define CONFIG_MII_GASKET #define CONFIG_DISCOVER_PHY #define CONFIG_CMD_PING -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 07/10] tegra20: add SPL config options for seaboard
On 06/07/2012 11:04 AM, Sughosh Ganu wrote: On Thu Jun 07, 2012 at 10:36:53AM -0600, Stephen Warren wrote: On 06/07/2012 01:15 AM, Sughosh Ganu wrote: On Wed Jun 06, 2012 at 10:44:59AM -0600, Stephen Warren wrote: On 06/05/2012 03:20 PM, Allen Martin wrote: snip diff --git a/include/configs/tegra2-spl.h b/include/configs/tegra2-spl.h + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. Being a new file, this should be GPLv2 not GPLv2+. u-boot uses GPLv2+. http://www.denx.de/wiki/view/U-Boot/Patches#Attributing_Code_Copyrights_Sign http://www.mail-archive.com/u-boot@lists.denx.de/msg26569.html Sughosh, I guess I'm a little confused here. COPYING in the U-Boot source tree states the following: U-Boot is Free Software. It is copyrighted by Wolfgang Denk and many others who contributed code (see the actual source code for details). You can redistribute U-Boot and/or modify it under the terms of version 2 of the GNU General Public License as published by the Free Software Foundation. Most of it can also be distributed, at your option, under any later version of the GNU General Public License -- see individual files for exceptions. ... which explicitly allows for either GPLv2 or GPLv2+ code. There is certainly GPLv2-only code already in U-Boot. Why do you say that GPLv2-only code isn't allowed? I guess that could be because some of the existing files in u-boot are released under GPLv2 only license -- hence a separate mention that most of the files can be distributed under any later version too . Both Wolfgang and Detlev have stated many a times on the mailing list earlier that all new files need to be released under GPLv2+, and not GPLv2 only. Hmmm. It seems like a good idea for COPYING to be updated to be explicit re: why that exemption is there, to avoid future confusion. I assume the requirement for GPLv2+ only applies to new code written for U-Boot, not existing code that's being taken from or derived from some other GPLv2-only project? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH][v2] powerpc/CoreNet: add tool to support pbl image build.
Dear Xie Shaohui-B21989, In message ed492cceaf882048bc2237de806547c907968...@039-sn2mpn1-012.039d.mgd.msft.net you wrote: I want to get rid if config.mk files to the extend possible - and here I see no need for a new one. [Xie Shaohui] Actually, I was hesitate to use the config.mk file, I found other person define the CONFIG_XXX_CONFIG in header files, but when I tried the same way, the checkpatch.pl complained that $(SRCTREE)/$(CONFIG_BOARDDIR)/pblimage.cfg should be wrapped by Parentheses, but the Parentheses will make the cfg file cannot be found because the Parentheses was included in path of the cfg file. Should I ignore the complain of the checkpatch.pl? Yes. And please - restrict your line length so some 70 characters or so. Thanks. You don;t expect us to edit this fiule just when building for another target? Please find a solution that works without editing source files. [Xie Shaohui] Maybe I should have another file for RCW... Just building does not need to edit this file; this is only needed for real board. This is what I mean - it is mandatory that you can build U-Boot for any real board without modifying any source files, and with only including files that are checked in into the git repository. Also, such a command should never be necessary - the make system should catch any such situations automatically. If it doesn't, then please fix this. [Xie Shaohui] It *is* not necessary, for ex I've built a boot Image, but I want to try another configuration file, I only need to run this command with new configuration file, I do not need to rebuild everything. Yes, but this should be covered by the Makefile - the user should never need to know any such internal details. [Xie Shaohui] I just followed what people done. A bad day for me... Not really. Don't be frustrated. These were actually very few remarks on pretty long and complex code. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de In my experience the best way to get something done is to give it to someone who is busy. - Terry Pratchett, _Going_Postal_ ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] 85xx platforms build broken due to flush dcache functions missing
Dear Zang Roy-R61911, In message 201206071134.02455.ma...@denx.de Marek Vasut wrote: The patch [PATCH V2] MPC8xxx: Define cache ops for USB wasn't applied yet for some reason. It fixes the issue. Hi, Marek When I build P5020DS_config with the current u-boot head, I got: ... Do you have any comment? Your commit will break all 85xx platforms with USB controller. Thanks I have to commit that I find your comment a bit out of place. Mareks patch that fixes this issue was posted a long, long time ago. But nobody complained about all the broken boards, and those who actually would be in a position to test the patch, to comment on it, and especially to apply it to the MPC8xxx repository have all been in Deep Sleep ever since. Instead of contacting Marek in private (I cannot see any trace of your original message on the ML), you could try kicking your friends at FSL... Thanks. Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de If you're not part of the solution, you're part of the problem. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2] MPC8xxx: Define cache ops for USB
Dear Marek Vasut, In message 1337955286-22345-1-git-send-email-ma...@denx.de you wrote: This patch conditionally defines flush_dcache_range() and invalidate_dcache_range() on MPC8xxx, to avoid EHCI complaining, resulting in the following output: $ ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- ./MAKEALL MPC8572DS Configuring for MPC8572DS board... make: *** [u-boot] Error 1 powerpc-linux-gnu-size: './u-boot': No such file e1000.c: In function ‘e1000_initialize’: e1000.c:5264:13: warning: assignment from incompatible pointer type [enabled by default] tsec.c: In function ‘tsec_initialize’: tsec.c:638:12: warning: assignment from incompatible pointer type [enabled by default] drivers/usb/host/libusb_host.o: In function `ehci_td_buffer': /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:186: undefined reference to `flush_dcache_range' drivers/usb/host/libusb_host.o: In function `ehci_submit_async': /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:346: undefined reference to `flush_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:348: undefined reference to `flush_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:349: undefined reference to `flush_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:372: undefined reference to `invalidate_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:374: undefined reference to `invalidate_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:376: undefined reference to `invalidate_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:386: undefined reference to `invalidate_dcache_range' make: *** [u-boot] Error 1 - SUMMARY Boards compiled: 1 Boards with errors: 1 ( MPC8572DS ) -- Signed-off-by: Marek Vasut ma...@denx.de Cc: Wolfgang Denk w...@denx.de Cc: Anatolij Gustschin ag...@denx.de --- arch/powerpc/cpu/mpc512x/Makefile |3 +++ arch/powerpc/cpu/mpc512x/cache.c | 33 + arch/powerpc/cpu/mpc83xx/Makefile |3 +++ arch/powerpc/cpu/mpc83xx/cache.c | 33 + arch/powerpc/cpu/mpc85xx/Makefile |3 +++ arch/powerpc/cpu/mpc85xx/cache.c | 33 + 6 files changed, 108 insertions(+) create mode 100644 arch/powerpc/cpu/mpc512x/cache.c create mode 100644 arch/powerpc/cpu/mpc83xx/cache.c create mode 100644 arch/powerpc/cpu/mpc85xx/cache.c V2: Fix MPC512x too Applied, thanks. Andy, I hope it is OK with you that I apply this directly. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Bus error -- please leave by the rear door. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-sh
Dear Nobuhiro Iwamatsu, In message cabmqnvj7_tzmnk6gv+wz9yebrugn2cc_oj8enr2byhpve3k...@mail.gmail.com you wrote: Dear Wolfgang Denk. Please pull from git://git.denx.de/u-boot-sh master. Best regards, Nobuhiro The following changes since commit 4398d55991eb3c2484a2a8e991d701e5d7a64874: net: sh-eth: Add support Gigabit of SH7734 (2012-05-23 17:53:09 -0500) are available in the git repository at: git://git.denx.de/u-boot-sh.git master for you to fetch changes up to 99fc4fd168f2eff3237f05c6ec4e2bbffe9c06e5: sh/ap_sh4a_4a: Fix typo of operator in ET0_ETXD4 (2012-05-28 09:12:54 +09= 00) Nobuhiro Iwamatsu (8): sh: Add support Renesas SH7734 sh: Add support for r0p7734 board sh: Add bit control functions sh: r0p7734: Add support I2C controller sh: Add register definition of PFC for SH7734 sh: Add support for AP-SH4A-4A board sh: Set CONFIG_SH_ETHER_PHY_MODE and CONFIG_SH_ETHER_SH7734_MII to boards with sh_eth sh/ap_sh4a_4a: Fix typo of operator in ET0_ETXD4 Phil Edworthy (1): sh: Add SH7269 device and RSK2+SH7269 board MAINTAINERS |2 + arch/sh/include/asm/cpu_sh2.h |2 + arch/sh/include/asm/cpu_sh4.h |2 + arch/sh/include/asm/cpu_sh7269.h | 26 +++ arch/sh/include/asm/cpu_sh7734.h | 70 ++ arch/sh/include/asm/io.h | 43 ++- board/alphaproject/ap_sh4a_4a/Makefile| 40 ++ board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c| 195 + board/alphaproject/ap_sh4a_4a/lowlevel_init.S | 459 +++= board/renesas/r0p7734/Makefile| 40 ++ board/renesas/r0p7734/lowlevel_init.S | 606 +++= +++= ++ board/renesas/r0p7734/r0p7734.c | 96 += +++ board/renesas/rsk7269/Makefile| 27 +++ board/renesas/rsk7269/lowlevel_init.S | 182 ++ board/renesas/rsk7269/rsk7269.c | 73 +++ boards.cfg|3 + drivers/serial/serial_sh.c|4 + drivers/serial/serial_sh.h| 20 + include/configs/ap_sh4a_4a.h | 176 include/configs/ecovec.h |1 + include/configs/espt.h|1 + include/configs/r0p7734.h | 186 +++ include/configs/rsk7269.h | 76 +++ include/configs/sh7757lcr.h |1 + include/configs/sh7763rdp.h |1 + 25 files changed, 2329 insertions(+), 3 deletions(-) create mode 100644 arch/sh/include/asm/cpu_sh7269.h create mode 100644 arch/sh/include/asm/cpu_sh7734.h create mode 100644 board/alphaproject/ap_sh4a_4a/Makefile create mode 100644 board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c create mode 100644 board/alphaproject/ap_sh4a_4a/lowlevel_init.S create mode 100644 board/renesas/r0p7734/Makefile create mode 100644 board/renesas/r0p7734/lowlevel_init.S create mode 100644 board/renesas/r0p7734/r0p7734.c create mode 100644 board/renesas/rsk7269/Makefile create mode 100644 board/renesas/rsk7269/lowlevel_init.S create mode 100644 board/renesas/rsk7269/rsk7269.c create mode 100644 include/configs/ap_sh4a_4a.h create mode 100644 include/configs/r0p7734.h create mode 100644 include/configs/rsk7269.h Applied, thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de It all seemed, he thought, to be rather a lot of trouble to go to just sharpen a razor blade. - Terry Pratchett, _The Light Fantastic_ ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [GIT PULL] u-boot-mips/master
Dear Daniel Schwierzeck, In message 1338761093-27598-1-git-send-email-daniel.schwierz...@googlemail.com you wrote: Dear Wolfgang, please pull some checkpatch.pl cleanups for MIPS. The following changes since commit 4398d55991eb3c2484a2a8e991d701e5d7a64874: net: sh-eth: Add support Gigabit of SH7734 (2012-05-23 17:53:09 -0500) are available in the git repository at: git://git.denx.de/u-boot-mips.git master for you to fetch changes up to e034ea3b77baf90ab8dde2c1beeb22704b01fb2d: MIPS: board.c: move extern declarations to u-boot-mips.h (2012-06-03 23:46:04 +0200) Daniel Schwierzeck (3): MIPS: bootm.c: make checkpatch.pl clean MIPS: bootm_qemu_mips.c: make checkpatch.pl clean MIPS: board.c: move extern declarations to u-boot-mips.h arch/mips/include/asm/u-boot-mips.h | 11 arch/mips/lib/board.c |7 --- arch/mips/lib/bootm.c | 102 +-- arch/mips/lib/bootm_qemu_mips.c | 26 - include/common.h|3 ++ 5 files changed, 79 insertions(+), 70 deletions(-) create mode 100644 arch/mips/include/asm/u-boot-mips.h Applied, thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de What kind of love is that? Not to be loved; never to have shown love. -- Commissioner Nancy Hedford, Metamorphosis, stardate 3219.8 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-avr32
Dear Andreas =?iso-8859-1?Q?Bie=DFmann?=, In message 20120604104547.ga29...@azuregos.er.corscience.de you wrote: The following changes since commit 4398d55991eb3c2484a2a8e991d701e5d7a64874: net: sh-eth: Add support Gigabit of SH7734 (2012-05-23 17:53:09 -0500) are available in the git repository at: git://git.denx.de/u-boot-avr32.git master for you to fetch changes up to d3a105a26f89ba9f43800f9452907e01b8211da5: avr32:board.c: fix compile warning (2012-06-04 09:21:34 +0200) Andreas Bie�mann (2): avr32:grasshopper: fix PHY initialisation avr32:board.c: fix compile warning arch/avr32/lib/board.c |1 - board/in-circuit/grasshopper/grasshopper.c |7 +++ 2 files changed, 7 insertions(+), 1 deletion(-) Applied, thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de I distrust all systematisers, and avoid them. The will to a system shows a lack of honesty. - Friedrich Wilhelm Nietzsche _G�tzen-D�mmerung [The Twilight of the Idols]_ ``Maxims and Missiles'' no. 26 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Which version of u-boot contains support for twrmpc5125
Dear Rudy, In message 7a6a685f2ad2c242812385088f128c121c5a332...@ausp01vmbx02.collaborationhost.net you wrote: The latest version does not appear to contain support for the the twrmpc5125 processor because the following command issued in the u-boot installation directory yields nothing. $grep 5125 Makefile. Your result is correct (there is no support for MPC5125 in mainline U-Boot), even though your test is actually wrong - you should have looked inboards.cfg instead of Makefile. My question is, how do you know which version of u-boot contains the most current source code with Freescale MPC5121e support that may be obtained from the DENX website. This source code would contain the most recent bug-fixes and feature updates. There is no such code in mainline. Nobody ever bothered to submit patches. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Virtue is a relative term. -- Spock, Friday's Child, stardate 3499.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-video/master
Dear Anatolij Gustschin, In message 20120605095753.0b080872@wker you wrote: Hello Wolfgang, The following changes since commit 4398d55991eb3c2484a2a8e991d701e5d7a64874: net: sh-eth: Add support Gigabit of SH7734 (2012-05-23 17:53:09 -0500) are available in the git repository at: git://git.denx.de/u-boot-video.git master Anatolij Gustschin (6): include/video.h: drop unused video_printf() cmd_bmp.c: make bmp_display() usable by drivers or board code common/lcd.c: use ARRAY_SIZE common/lcd.c: reduce some CONFIG_LCD_*_LOGO ifdefs common/lcd.c: reduce one CONFIG_LCD_LOGO ifdef video: cfb_console: flush dcache for frame buffer in DRAM Bo Shen (1): video: atmel/lcd: add LCD driver for new Atmel SoC Donghwa Lee (5): LCD: change s6e8ax0 panel gamma value LCD: support another s6e8ax0 panel type LCD: display 32bpp decompressed bitmap image create lib/tizen directory EXYNOS: display 32bpp bitmap TIZEN logo Fabio Estevam (4): mx51evk: Add LCD support mx53: Allow IPUv3 driver to also work on mx53 mx5: Rename mx51_fb_init() mx53loco: Add LCD support Jeroen Hofstee (2): omap3_dss: add optional framebuffer omap3_dss: cosmetic changes Pali Roh=E1r (3): cfb_console: Fix function console_back cfb_console: Add console_clear_line function cfb_console: Ignore bell character Makefile |3 + arch/arm/include/asm/arch-exynos/mipi_dsim.h |1 + arch/arm/include/asm/arch-mx5/imx-regs.h |8 +- arch/arm/include/asm/arch-omap3/dss.h| 61 +- board/freescale/mx51evk/mx51evk.c| 59 + board/freescale/mx53loco/mx53loco.c | 72 + board/samsung/trats/trats.c | 16 + board/ttcontrol/vision2/vision2.c|2 +- common/cmd_bmp.c |3 +- common/lcd.c | 45 +- drivers/video/Makefile |3 +- drivers/video/atmel_hlcdfb.c | 211 ++ drivers/video/cfb_console.c | 89 +- drivers/video/exynos_fb.c| 19 + drivers/video/exynos_fb.h|7 - drivers/video/exynos_fimd.c |2 +- drivers/video/ipu_regs.h | 42 +- drivers/video/mxc_ipuv3_fb.c |2 +- drivers/video/omap3_dss.c| 77 +- drivers/video/s6e8ax0.c | 25 +- include/atmel_hlcdc.h| 231 ++ include/configs/mx51evk.h| 13 +- include/configs/mx53loco.h | 13 +- include/configs/trats.h |6 +- include/ipu_pixfmt.h |2 +- include/lcd.h| 17 +- include/libtizen.h | 29 + include/video.h |1 - lib/tizen/Makefile | 46 + lib/tizen/tizen.c| 40 + lib/tizen/tizen_hd_logo.h| 5071 ++= lib/tizen/tizen_hd_logo_data.h | 29 + 32 files changed, 6123 insertions(+), 122 deletions(-) create mode 100644 drivers/video/atmel_hlcdfb.c create mode 100644 include/atmel_hlcdc.h create mode 100644 include/libtizen.h create mode 100644 lib/tizen/Makefile create mode 100644 lib/tizen/tizen.c create mode 100644 lib/tizen/tizen_hd_logo.h create mode 100644 lib/tizen/tizen_hd_logo_data.h Applied, thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de He was so narrow minded he could see through a keyhole with both eyes ... ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] net/designware: Add-on: Consecutive writes must have delay
This commit is an add-on to f6c4191f. There are a few other registers where consecutive writes must have a delay. Signed-off-by: Dinh Nguyen dingu...@altera.com --- drivers/net/designware.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index e8e669b..34952c0 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -163,8 +163,8 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) writel(FIXEDBURST | PRIORXTX_41 | BURST_16, dma_p-busmode); - writel(FLUSHTXFIFO | readl(dma_p-opmode), dma_p-opmode); - writel(STOREFORWARD | TXSECONDFRAME, dma_p-opmode); + writel(readl(dma_p-opmode) | FLUSHTXFIFO | STOREFORWARD | \ + TXSECONDFRAME, dma_p-opmode); conf = FRAMEBURSTENABLE | DISABLERXOWN; -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] [resend] kwboot: boot kirkwood SoCs over a serial link
On Thu, 2012-06-07 at 15:27 +0200, Luka Perkov wrote: Hi all, On Sun, May 27, 2012 at 11:44:51PM +0200, Luka Perkov wrote: The kwboot program boots boards based on Marvell's Kirkwood platform via Xmodem over their integrated UART. Signed-off-by: Daniel Stodden daniel.stod...@googlemail.com Acked-by: Luka Perkov ub...@lukaperkov.net Tested-By: Holger Brunck holger.bru...@keymile.com Tested-By: David Purdy david.c.pu...@gmail.com Tested-by: Simon Guinot simon.gui...@sequanux.org --- Changes from version 2: * fix timeouts in kwboot_tty_recv * revert indentation on manpage * on manpage note that TTY isn't optional * add David and Luka into the manpage Changes from version v1: * fix man page * minor cosmetic fixes in tools/kwboot.c I'm resending this patch because original version 3 was not following patch submission guidlines. doc/kwboot.1 | 84 +++ tools/Makefile |6 + tools/kwboot.c | 742 3 files changed, 832 insertions(+) If no one has objections to the code I would love to see it merged. Any NACK's or ACK's? Certainly a thanks from me :) Daniel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] net/designware: Add-on: Consecutive writes must have delay
Dear Dinh, In message 1339104480-6191-1-git-send-email-dingu...@altera.com you wrote: This commit is an add-on to f6c4191f. There are a few other registers where consecutive writes must have a delay. Sorry, but this commit message is misleading - I was expecting to see something like udelay() in the code, but there wasn't any... Signed-off-by: Dinh Nguyen dingu...@altera.com --- drivers/net/designware.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index e8e669b..34952c0 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -163,8 +163,8 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) writel(FIXEDBURST | PRIORXTX_41 | BURST_16, dma_p-busmode); - writel(FLUSHTXFIFO | readl(dma_p-opmode), dma_p-opmode); - writel(STOREFORWARD | TXSECONDFRAME, dma_p-opmode); + writel(readl(dma_p-opmode) | FLUSHTXFIFO | STOREFORWARD | \ + TXSECONDFRAME, dma_p-opmode); There is no need for the continuation line here; please drop the backslash. Hm... Should we not rather use something like setbits_le32() here? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de You said you didn't want to use CGI.pm, but methinks you are needlessly reinventing the wheel, one spoke at a time. Either you are masochistic, or you just haven't seen enough of what CGI.pm can do for you. -- Randal L. Schwartz in 8cyb81rg81@gadget.cscaper.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] net/designware: Add-on: Consecutive writes must have delay
Dear Dinh, In message 71b37e0559ac6849a68c5ba94c509fb458298d3...@sj-itmsg02.altera.priv.altera.com you wrote: Sorry, but this commit message is misleading - I was expecting to see something like udelay() in the code, but there wasn't any... Combining the 2 individual writes into a single write will also work. I'm just keeping in sync with commit # f6c4191f. I understand this - but the commit message should match the code. Again, just keeping the code in sync with the previous commit that address this issue. If you like, I can change it to setbits_le32(). I think it would be cleaner, but if the rest of the code looks like that, I will not insist. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de ...one of the main causes of the fall of the Roman Empire was that, lacking zero, they had no way to indicate successful termination of their C programs. - Robert Firth ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] mmc: sh_mmcif: enable MMC_MODE_HC
The controller can control high capacity cards. So, the patch adds the flag. If the flag is not set, mmcinfo will fail when a high capacity card is used. Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda...@renesas.com --- drivers/mmc/sh_mmcif.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c index 2835e24..4588568 100644 --- a/drivers/mmc/sh_mmcif.c +++ b/drivers/mmc/sh_mmcif.c @@ -593,7 +593,7 @@ int mmcif_mmc_init(void) mmc-f_max = CLKDEV_EMMC_DATA; mmc-voltages = MMC_VDD_32_33 | MMC_VDD_33_34; mmc-host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT | -MMC_MODE_8BIT; +MMC_MODE_8BIT | MMC_MODE_HC; memcpy(mmc-name, DRIVER_NAME, sizeof(DRIVER_NAME)); mmc-send_cmd = sh_mmcif_request; mmc-set_ios = sh_mmcif_set_ios; -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/CoreNet: add tool to support pbl image build.
On 06/06/2012 10:16 PM, Xie Shaohui-B21989 wrote: -Original Message- From: Wood Scott-B07421 Sent: Thursday, June 07, 2012 2:19 AM To: Xie Shaohui-B21989 Cc: Wood Scott-B07421; u-boot@lists.denx.de; Tabi Timur-B04825 Subject: Re: [U-Boot] [PATCH] powerpc/CoreNet: add tool to support pbl image build. On 06/05/2012 09:45 PM, Xie Shaohui-B21989 wrote: Can Timur's tool do it automatically, or by some arguments provided? And even though, there will be two files for configuration, one is RCW output from Timur's tool, and another is PBI commands. This is too much for the tool; it has only one entry for configuration file. Too much for which tool, and why can't that be changed? [Xie Shaohui] The mkimage structure provides one entry to indicate the configuration file, is it OK to add a more entry just for PBL? I don't see why not. [Xie Shaohui] OK. Then I'll split the current configuration file in two, one is for RCW, another is for PBI commands. Also, add one more entry for the second configuration file. But as you know, Timur's tool is not in open source now, I can only use a default RCW file for now. I have two questions: 1. Is there a plan that we submit Timur' tool to open source? 2. If yes, should I combine Timur's tool with my tool or I just tell user They should use Timur's tool to produce the RCW and then use it in my tool? Best Regards, Shaohui Xie ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] mmc: fix capacity calculation when EXT_CSD_SEC_CNT is used
Since the type of ext_csd was array of char, the following
calculation might fail when the value of ext_csd[EXT_CSD_SEC_CNT]
was minus.
capacity = ext_csd[EXT_CSD_SEC_CNT] 0
| ext_csd[EXT_CSD_SEC_CNT + 1] 8
| ext_csd[EXT_CSD_SEC_CNT + 2] 16
| ext_csd[EXT_CSD_SEC_CNT + 3] 24;
So, this patch changes the type of ext_csd to array of u8.
Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda...@renesas.com
---
drivers/mmc/mmc.c | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 596732e..b781201 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -668,7 +668,7 @@ int mmc_send_op_cond(struct mmc *mmc)
}
-int mmc_send_ext_csd(struct mmc *mmc, char *ext_csd)
+int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
{
struct mmc_cmd cmd;
struct mmc_data data;
@@ -680,7 +680,7 @@ int mmc_send_ext_csd(struct mmc *mmc, char *ext_csd)
cmd.cmdarg = 0;
cmd.flags = 0;
- data.dest = ext_csd;
+ data.dest = (char *)ext_csd;
data.blocks = 1;
data.blocksize = 512;
data.flags = MMC_DATA_READ;
@@ -716,7 +716,7 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
int mmc_change_freq(struct mmc *mmc)
{
- ALLOC_CACHE_ALIGN_BUFFER(char, ext_csd, 512);
+ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, 512);
char cardtype;
int err;
@@ -978,8 +978,8 @@ int mmc_startup(struct mmc *mmc)
uint mult, freq;
u64 cmult, csize, capacity;
struct mmc_cmd cmd;
- ALLOC_CACHE_ALIGN_BUFFER(char, ext_csd, 512);
- ALLOC_CACHE_ALIGN_BUFFER(char, test_csd, 512);
+ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, 512);
+ ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, 512);
int timeout = 1000;
#ifdef CONFIG_MMC_SPI_CRC_ON
--
1.7.1
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