Re: [U-Boot] [PATCH] dlmalloc: remove manual reloc alias warning
Dear Simon Glass,
On 15.08.12 02:15, Simon Glass wrote:
Hi,
On Tue, Aug 14, 2012 at 1:50 AM, Andreas Bießmann
andreas.de...@googlemail.com wrote:
Dear all,
On 13.08.2012 11:02, Andreas Bießmann wrote:
From: Andreas Bießmann biessm...@corscience.de
The avr32 architecture (and some others) require manual relocation. Due to
the
previous error all avr32 boards gave warnings in MAKEALL wich makes it hard
to
find new warnings.
This patch fixes following warning:
---8---
dlmalloc.c: In function 'malloc_bin_reloc':
dlmalloc.c:1493: warning: dereferencing pointer 'p' does break
strict-aliasing rules
dlmalloc.c:1493: warning: dereferencing pointer 'p' does break
strict-aliasing rules
dlmalloc.c:1490: note: initialized from here
dlmalloc.c:1493: note: initialized from here
---8---
Signed-off-by: Andreas Bießmann biessm...@corscience.de
---
A question to all the other related arches, namely m68k, mips, nds32 and
sparc: Do you encounter the same warnings or is this warning due to my
outdated compiler (4.4.3 currently, unfortunately atmel do not bother to
send
their patches mainline)?
common/dlmalloc.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index c645d73..78b1885 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -1485,9 +1485,10 @@ static mbinptr av_[NAV * 2 + 2] = {
};
#ifdef CONFIG_NEEDS_MANUAL_RELOC
+typedef unsigned long __attribute__((__may_alias__)) ulong_aliased;
void malloc_bin_reloc (void)
{
- unsigned long *p = (unsigned long *)(av_[2]);
+ ulong_aliased *p = (ulong_aliased *)(av_[2]);
int i;
for (i=2; i(sizeof(av_)/sizeof(mbinptr)); ++i) {
*p++ += gd-reloc_off;
this seems to be related to
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/121848/focus=121849
can you Wolfgang and/or Simon please comment.
My only comment is that I created that patch due to errors I saw at
the time, and still see with the toolchain I use for avr32.
So you also want to remove this annoying warning. Sorry that I didn't
test your patch from January earlier, but it is broken at runtime.
I would really like to remove the alias warning in 2012.10. My patch is
straight forward, maybe there are better solutions.
However I would like to see tested by from other affected arches (m68k,
mips, nds32 and sparc).
Best regards
Andreas Bießmann
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Re: [U-Boot] [PATCH] ARM : at91sam9x5 : Remove CONFIG_ARCH_CPU_INIT
Dear Bo Shen, On 15.08.12 04:48, Bo Shen wrote: Remove CONFIG_ARCH_CPU_INIT, no need it anymore Signed-off-by: Bo Shen voice.s...@atmel.com --- applied to u-boot-atmel/master, thanks! Best regards Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] mx53_smd: add spi nor support
Add spi nor support to mx53 smd, including iomux, configs, etc.
To test spi nor on mx53 smd:
MX53SMD U-Boot sf probe 0:21249
JEDEC ID: 0x202016
m25p32 (4096 Kbytes)
SF: Detected m25p32 with page size 0 Bytes, total 4 MiB
Here, 21249 is integer of hex 0x5301. 0x01 is cs and 0x53 is active gpio
number.
Signed-off-by: Terry Lv r65...@freescale.com
---
board/freescale/mx53smd/mx53smd.c | 63 +
include/configs/mx53smd.h | 17 ++
2 files changed, 80 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mx53smd/mx53smd.c
b/board/freescale/mx53smd/mx53smd.c
index 87fa7fa..abb1e9b 100644
--- a/board/freescale/mx53smd/mx53smd.c
+++ b/board/freescale/mx53smd/mx53smd.c
@@ -127,6 +127,65 @@ static void setup_iomux_fec(void)
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
}
+#ifdef CONFIG_MXC_SPI
+static void setup_iomux_spi(u8 bus, u8 ss)
+{
+ switch (bus) {
+ case 0:
+ /* SCLK */
+ mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX53_PIN_EIM_D16,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+ mxc_iomux_set_input(MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
+ 0x3);
+
+ /* MISO */
+ mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX53_PIN_EIM_D17,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+ mxc_iomux_set_input(MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
+ 0x3);
+
+ /* MOSI */
+ mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX53_PIN_EIM_D18,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+ mxc_iomux_set_input(MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
+ 0x3);
+
+ if (0 == ss) {
+ mxc_request_iomux(MX53_PIN_EIM_EB2,
+ IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX53_PIN_EIM_EB2,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+ mxc_iomux_set_input(
+ MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
+ 0x3);
+
+ mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX53_PIN_EIM_EB2,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+ } else if (1 == ss){
+ mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX53_PIN_EIM_D19,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+ mxc_iomux_set_input(
+ MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
+ 0x2);
+
+ mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX53_PIN_EIM_D19,
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH);
+ }
+ break;
+ case 1:
+ case 2:
+ default:
+ break;
+ }
+}
+#endif
+
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{MMC_SDHC1_BASE_ADDR, 1},
@@ -203,6 +262,10 @@ int board_early_init_f(void)
{
setup_iomux_uart();
setup_iomux_fec();
+#if defined(CONFIG_MXC_SPI) defined(CONFIG_SPI_FLASH) \
+defined(CONFIG_SPI_FLASH_BUS) defined(CONFIG_SPI_FLASH_CS)
+ setup_iomux_spi(CONFIG_SPI_FLASH_BUS, CONFIG_SPI_FLASH_CS);
+#endif
return 0;
}
diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
index 48b32dd..e830c1b 100644
--- a/include/configs/mx53smd.h
+++ b/include/configs/mx53smd.h
@@ -65,6 +65,23 @@
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
+/* SPI Configs*/
+#define CONFIG_CMD_SPI
+#define CONFIG_MXC_SPI
+#define CONFIG_SPI_VER_2_3 1
+#define CONFIG_CSPI1_BASE_ADDR CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR CSPI2_BASE_ADDR
+#define CONFIG_CSPI3_BASE_ADDR CSPI3_BASE_ADDR
+
+/* SPI Flash Configs */
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO 1
+#define CONFIG_SF_DEFAULT_SPEED 2500
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+#define CONFIG_SPI_FLASH_BUS 0
+#define CONFIG_SPI_FLASH_CS1
+
/* Eth Configs */
#define CONFIG_HAS_ETH1
#define CONFIG_MII
--
1.7.0.4
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[U-Boot] [PATCH 3/3] mxc_spi: apply new mxc_spi version configs to other soc configs
Apply new mxc_spi version configs to other soc configs. Signed-off-by: Terry Lv r65...@freescale.com --- arch/arm/include/asm/arch-mx31/imx-regs.h |4 include/configs/efikamx.h |4 include/configs/flea3.h |3 +++ include/configs/imx31_litekit.h |5 + include/configs/imx31_phycore.h |4 include/configs/mx31ads.h |4 include/configs/mx31pdk.h |4 include/configs/mx35pdk.h |8 +++- include/configs/mx51evk.h |4 include/configs/qong.h|4 include/configs/tt01.h|5 + 11 files changed, 48 insertions(+), 1 deletions(-) diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 0147920..4f9c78c 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -24,6 +24,10 @@ #ifndef __ASM_ARCH_MX31_IMX_REGS_H #define __ASM_ARCH_MX31_IMX_REGS_H +#define CSPI1_BASE_ADDR0x43fa4000 +#define CSPI2_BASE_ADDR0x5001 +#define CSPI3_BASE_ADDR0x53f84000 + #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include asm/types.h diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h index a07c8b5..1fe558d 100644 --- a/include/configs/efikamx.h +++ b/include/configs/efikamx.h @@ -99,6 +99,10 @@ #define CONFIG_HARD_SPI #define CONFIG_MXC_SPI +#define CONFIG_SPI_VER_2_3 1 +#define CONFIG_CSPI1_BASE_ADDR CSPI1_BASE_ADDR +#define CONFIG_CSPI2_BASE_ADDR CSPI2_BASE_ADDR +#define CONFIG_CSPI3_BASE_ADDR CSPI3_BASE_ADDR #define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_MODE(SPI_MODE_0 | SPI_CS_HIGH) diff --git a/include/configs/flea3.h b/include/configs/flea3.h index d88c578..0d85ed5 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -71,6 +71,9 @@ #define CONFIG_SYS_I2C_SPEED 10 #define CONFIG_SYS_I2C_SLAVE 0xfe #define CONFIG_MXC_SPI +#define CONFIG_SPI_VER_0_7 1 +#define CONFIG_CSPI1_BASE_ADDR CSPI1_BASE_ADDR +#define CONFIG_CSPI2_BASE_ADDR CSPI2_BASE_ADDR #define CONFIG_MXC_GPIO /* diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 1455ea2..d213ed0 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -69,6 +69,11 @@ #define CONFIG_HARD_SPI1 #define CONFIG_MXC_SPI 1 +#define CONFIG_SPI_VER_0_5 1 +#define CONFIG_CSPI1_BASE_ADDR CSPI1_BASE_ADDR +#define CONFIG_CSPI2_BASE_ADDR CSPI2_BASE_ADDR +#define CONFIG_CSPI3_BASE_ADDR CSPI3_BASE_ADDR + #define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_MODE(SPI_MODE_0 | SPI_CS_HIGH) diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 1b75197..f7c2e2d 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -213,6 +213,10 @@ #define CONFIG_HARD_SPI #define CONFIG_MXC_SPI +#define CONFIG_SPI_VER_0_5 1 +#define CONFIG_CSPI1_BASE_ADDR CSPI1_BASE_ADDR +#define CONFIG_CSPI2_BASE_ADDR CSPI2_BASE_ADDR +#define CONFIG_CSPI3_BASE_ADDR CSPI3_BASE_ADDR #define CONFIG_CMD_SPI #define CONFIG_S6E63D6 diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index 7e011ae..eff70de 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -65,6 +65,10 @@ #define CONFIG_HARD_SPI1 #define CONFIG_MXC_SPI 1 +#define CONFIG_SPI_VER_0_5 1 +#define CONFIG_CSPI1_BASE_ADDR CSPI1_BASE_ADDR +#define CONFIG_CSPI2_BASE_ADDR CSPI2_BASE_ADDR +#define CONFIG_CSPI3_BASE_ADDR CSPI3_BASE_ADDR #define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_MODE(SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_MXC_GPIO diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 4253c3e..8210f97 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -67,6 +67,10 @@ #define CONFIG_HARD_SPI #define CONFIG_MXC_SPI +#define CONFIG_SPI_VER_0_5 1 +#define CONFIG_CSPI1_BASE_ADDR CSPI1_BASE_ADDR +#define CONFIG_CSPI2_BASE_ADDR CSPI2_BASE_ADDR +#define CONFIG_CSPI3_BASE_ADDR CSPI3_BASE_ADDR #define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_MODE(SPI_MODE_0 | SPI_CS_HIGH) diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 32ed609..26eb1d5 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -62,9 +62,15 @@ #define CONFIG_SYS_I2C_MX35_PORT1 #define CONFIG_SYS_I2C_SPEED 10 #define CONFIG_SYS_I2C_SLAVE 0xfe -#define CONFIG_MXC_SPI #define CONFIG_MXC_GPIO +/* + * SPI Configs + */ +#define CONFIG_MXC_SPI +#define CONFIG_SPI_VER_0_7 1 +#define CONFIG_CSPI1_BASE_ADDR CSPI1_BASE_ADDR +#define CONFIG_CSPI2_BASE_ADDR CSPI2_BASE_ADDR /* * PMIC Configs diff --git
Re: [U-Boot] [PATCH 1/4] spi_nor: add m25p32 spi nor driver
Sorry for that I don't know m25p32 spi nor supported in stmicro. I've thought that this might be a new driver for new chips. That's ok. Then I'll summit mx53smd spi nor patches with stmicro. -Original Message- From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Mike Frysinger Sent: 2012?8?14? 23:53 To: u-boot@lists.denx.de; r65...@shlinux3.net Subject: Re: [U-Boot] [PATCH 1/4] spi_nor: add m25p32 spi nor driver On Tuesday 14 August 2012 06:58:31 Terry Lv wrote: This driver is ported from kernel and can handle a series of spi nor flash including m25pxx, m45pxx, w25xxx, cat25xxx, sst25vf0xxx, sst25wfxxx, s25xxx, mx25xxx, at25xxx, at26xxx, en25xxx, xxxs33b. it doesn't make much sense to add a driver which duplicates all the existing ones. long term, we should look at migrating to the linux driver i think (if we can make it work), but i don't think this port is exactly the way. -mike ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/3] at91: atmel_nand: add PMECC(Programmable Multibit ECC controller) support
Hi, Andreas Sorry, in these patches of current version, it still has a bug, which will fail to write with PMECC, I will send out the v2 patch soon which include this bug fix. Best Regards, Josh Wu On 8/9/2012 6:21 PM, Josh Wu wrote: This patch series will add PMECC support for atmel nand driver in u-boot. The driver patch is ported from kernel patch. The main different from kernel patch is the modification about registers access part. in this version it via a register structure to access. It is tested in atmel 9x5 series board. Josh Wu (3): at91: atmel_nand: extract HWECC initialization code into one function: atmel_hw_nand_init_param(). at91: atmel_nand: remove unused variables. at91: atmel_nand: Update driver to support Programmable Multibit ECC controller drivers/mtd/nand/atmel_nand.c | 759 ++--- drivers/mtd/nand/atmel_nand_ecc.h | 107 ++ 2 files changed, 813 insertions(+), 53 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] mxc_spi: change to use version config instead of soc config in mxc_spi
In mxc_spi, we used to use soc config, e.g. CONFIG_MX35, CONFIG_MX51.
In this way, we can't exlain the difference of spi in each soc and we
need to modify the driver for each new soc.
Thus, now it use spi version config which can be found in reference
manual to diff. And new soc just need to add spi version config in
config files to enable it. it would be eaiser than before.
Signed-off-by: Terry Lv r65...@freescale.com
---
README|4 ++-
drivers/spi/mxc_spi.c | 59 -
2 files changed, 32 insertions(+), 31 deletions(-)
mode change 100644 = 100755 drivers/spi/mxc_spi.c
diff --git a/README b/README
index 07f1d11..19268d9 100644
--- a/README
+++ b/README
@@ -1910,7 +1910,9 @@ The following options need to be configured:
CONFIG_MXC_SPI
Enables the driver for the SPI controllers on i.MX and MXC
- SoCs. Currently i.MX31/35/51 are supported.
+ SoCs. The board must also define the version of SPI controller
+ and SPI base addresses that will be used.
+ Currently i.MX31/35/51/53 are supported.
- FPGA Support: CONFIG_FPGA
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
old mode 100644
new mode 100755
index 2fa7486..2f48483
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -27,14 +27,12 @@
#include asm/arch/imx-regs.h
#include asm/arch/clock.h
-#ifdef CONFIG_MX27
-/* i.MX27 has a completely wrong register layout and register definitions in
the
- * datasheet, the correct one is in the Freescale's Linux driver */
+#if defined(CONFIG_SPI_VER_0_4) || defined(CONFIG_SPI_VER_0_0)
-#error i.MX27 CSPI not supported due to drastic differences in register
definitions \
+#error CSPI version not supported due to drastic differences in register
definitions \
See linux mxc_spi driver from Freescale for details.
-#elif defined(CONFIG_MX31)
+#elif defined(CONFIG_SPI_VER_0_5)
#define MXC_CSPICTRL_EN(1 0)
#define MXC_CSPICTRL_MODE (1 1)
@@ -54,13 +52,7 @@
#define MXC_CSPIPERIOD_32KHZ (1 15)
#define MAX_SPI_BYTES 4
-static unsigned long spi_bases[] = {
- 0x43fa4000,
- 0x5001,
- 0x53f84000,
-};
-
-#elif defined(CONFIG_MX51)
+#elif defined(CONFIG_SPI_VER_2_3)
#define MXC_CSPICTRL_EN(1 0)
#define MXC_CSPICTRL_MODE (1 1)
@@ -85,13 +77,7 @@ static unsigned long spi_bases[] = {
#define MXC_CSPICON_PHA0
#define MXC_CSPICON_SSPOL 12
-static unsigned long spi_bases[] = {
- CSPI1_BASE_ADDR,
- CSPI2_BASE_ADDR,
- CSPI3_BASE_ADDR,
-};
-
-#elif defined(CONFIG_MX35)
+#elif defined(CONFIG_SPI_VER_0_7)
#define MXC_CSPICTRL_EN(1 0)
#define MXC_CSPICTRL_MODE (1 1)
@@ -111,15 +97,28 @@ static unsigned long spi_bases[] = {
#define MXC_CSPIPERIOD_32KHZ (1 15)
#define MAX_SPI_BYTES 4
-static unsigned long spi_bases[] = {
- 0x43fa4000,
- 0x5001,
-};
-
#else
-#error Unsupported architecture
+#error Unsupported cspi version
#endif
+static unsigned long spi_bases[] = {
+#ifdef CONFIG_CSPI1_BASE_ADDR
+ CONFIG_CSPI1_BASE_ADDR,
+#endif
+#ifdef CONFIG_CSPI2_BASE_ADDR
+ CONFIG_CSPI2_BASE_ADDR,
+#endif
+#ifdef CONFIG_CSPI3_BASE_ADDR
+ CONFIG_CSPI3_BASE_ADDR,
+#endif
+#ifdef CONFIG_CSPI4_BASE_ADDR
+ CONFIG_CSPI4_BASE_ADDR,
+#endif
+#ifdef CONFIG_CSPI5_BASE_ADDR
+ CONFIG_CSPI5_BASE_ADDR,
+#endif
+};
+
#define OUTMXC_GPIO_DIRECTION_OUT
#define reg_read readl
@@ -129,7 +128,7 @@ struct mxc_spi_slave {
struct spi_slave slave;
unsigned long base;
u32 ctrl_reg;
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SPI_VER_2_3)
u32 cfg_reg;
#endif
int gpio;
@@ -167,7 +166,7 @@ u32 get_cspi_div(u32 div)
return i;
}
-#if defined(CONFIG_MX31) || defined(CONFIG_MX35)
+#if defined(CONFIG_SPI_VER_0_5) || defined(CONFIG_SPI_VER_0_7)
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
@@ -187,7 +186,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned
int cs,
MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
MXC_CSPICTRL_DATARATE(div) |
MXC_CSPICTRL_EN |
-#ifdef CONFIG_MX35
+#ifdef CONFIG_SPI_VER_0_7
MXC_CSPICTRL_SSCTL |
#endif
MXC_CSPICTRL_MODE;
@@ -204,7 +203,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned
int cs,
}
#endif
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SPI_VER_2_3)
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
@@ -316,7 +315,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int
bitlen,
MXC_CSPICTRL_BITCOUNT(bitlen - 1);
reg_write(regs-ctrl, mxcs-ctrl_reg | MXC_CSPICTRL_EN);
Re: [U-Boot] [PATCH 2/2] apx4devkit: Turn on caches
On 05/08/2012 18:18, Fabio Estevam wrote: From: Fabio Estevam fabio.este...@freescale.com Turn on data and instruction caches. Signed-off-by: Fabio Estevam fabio.este...@freescale.com include/configs/apx4devkit.h |2 -- 1 files changed, 0 insertions(+), 2 deletions(-) Applied to u-boot-imx, thanks. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] m28evk: Turn on caches
On 05/08/2012 18:17, Fabio Estevam wrote: From: Fabio Estevam fabio.este...@freescale.com Turn on data and instruction caches. Signed-off-by: Fabio Estevam fabio.este...@freescale.com --- Applied to u-boot-imx, thanks. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2 1/2] mpc85xx: Initial SP alignment is wrong.
Scott Wood scottw...@freescale.com wrote on 2012/08/14 23:01:47: On 08/14/2012 03:55 PM, Joakim Tjernlund wrote: Ping? PowerPC mandates SP to be 16 bytes aligned. Furthermore, a stack frame is added, pointing to the reset vector which may in the way when gdb is walking the stack because the reset vector may not accessible depending on emulator settings. Also use a temp register so gdb doesn't pick up intermediate values. Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se --- v2 - Address Scott Wood's comments arch/powerpc/cpu/mpc85xx/start.S | 16 +--- 1 files changed, 5 insertions(+), 11 deletions(-) Andy Fleming is the 85xx custodian, but you didn't CC him. Oh, didn't notice that Andy was the custodian, there isn't an entry in MAINTAINERS. Andy, you think you can pick up [PATCHv2 1/2] mpc85xx: Initial SP alignment is wrong. Jocke ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/4] mxs: Remove not required explicit iomux-mx28.h include
On 13/08/2012 21:53, Otavio Salvador wrote: The iomux header is included on sys_proto.h so to avoid SoC specific header inclusion. Signed-off-by: Otavio Salvador ota...@ossystems.com.br --- Changes in v2: - no changes arch/arm/cpu/arm926ejs/mxs/spl_boot.c |1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 46f6770..84d4a17 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -26,7 +26,6 @@ #include common.h #include config.h #include asm/io.h -#include asm/arch/iomux-mx28.h #include asm/arch/imx-regs.h #include asm/arch/sys_proto.h #include asm/gpio.h Applied to u-boot-imx (the whole series), thanks. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2 1/2] mpc85xx: Initial SP alignment is wrong.
Kumar Gala ga...@kernel.crashing.org wrote on 2012/08/14 23:28:45: On Jul 23, 2012, at 3:58 PM, Joakim Tjernlund wrote: PowerPC mandates SP to be 16 bytes aligned. Furthermore, a stack frame is added, pointing to the reset vector which may in the way when gdb is walking the stack because the reset vector may not accessible depending on emulator settings. Also use a temp register so gdb doesn't pick up intermediate values. Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se --- v2 - Address Scott Wood's comments arch/powerpc/cpu/mpc85xx/start.S | 16 +--- 1 files changed, 5 insertions(+), 11 deletions(-) Acked-by: Kumar Gala ga...@kernel.crashing.org Thanks Kumar Will you pick up? [PATCHv2 2/2] powerpc: Stack Pointer not properly aligned It is not 85xx specific but for all PowerPC Jocke ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/3] at91: atmel_nand: add PMECC(Programmable Multibit ECC controller) support
Dear Josh Wu, On 15.08.2012 08:50, Josh Wu wrote: Hi, Andreas Sorry, in these patches of current version, it still has a bug, which will fail to write with PMECC, I will send out the v2 patch soon which include this bug fix. Oups, sorry I had this patch series not on my list. Will review this or v2 these days. On first sight the first two in series are ok, the third one has style problems: ---8--- abiessmann@azuregos % ./tools/checkpatch.pl U-Boot-3-3-at91-atmel_nand-Update-driver-to-support-Programmable-Multibit-ECC-controller.patch WARNING: line over 80 characters ... total: 1 errors, 27 warnings, 787 lines checked NOTE: Ignored message types: COMPLEX_MACRO CONSIDER_KSTRTO MINMAX MULTISTATEMENT_MACRO_USE_DO_WHILE U-Boot-3-3-at91-atmel_nand-Update-driver-to-support-Programmable-Multibit-ECC-controller.patch has style problems, please review. If any of these errors are false positives, please report them to the maintainer, see CHECKPATCH in MAINTAINERS. ---8--- I personally do not really care about the 80 char warning but please remove these for the sake of peace ;) and please have a look for the reported error. And the last, you should add at least one user of this feature. Isn't the lately applied at91sam9x5ek (is in u-boot-atmel/master and u-boot-arm/master) a perfect user for that? On 8/9/2012 6:21 PM, Josh Wu wrote: This patch series will add PMECC support for atmel nand driver in u-boot. The driver patch is ported from kernel patch. The main different from kernel patch is the modification about registers access part. in this version it via a register structure to access. A question regarding linux driver. You say it is derived from the kernel driver, but I can not see PMECC stuff in kernel: ---8--- abiessmann@azuregos % git describe v3.6-rc1-355-gddf343f abiessmann@azuregos % diff -Nrupa drivers/mtd/nand/atmel_nand.c ../u-boot/drivers/mtd/nand/atmel_nand.c | diffstat atmel_nand.c | 1231 ++- 1 file changed, 720 insertions(+), 511 deletions(-) abiessmann@azuregos % grep -in pmecc drivers/mtd/nand/atmel_nand* abiessmann@azuregos % ---8--- Which driver/patch do you mean? It is tested in atmel 9x5 series board. Unfortunately I can not test this driver cause I do only have older sam926x devices around. Best regards Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/3] at91: atmel_nand: add PMECC(Programmable Multibit ECC controller) support
Hi, Andreas Thank you for the quick reply. On 8/15/2012 3:50 PM, Andreas Bießmann wrote: Dear Josh Wu, On 15.08.2012 08:50, Josh Wu wrote: Hi, Andreas Sorry, in these patches of current version, it still has a bug, which will fail to write with PMECC, I will send out the v2 patch soon which include this bug fix. Oups, sorry I had this patch series not on my list. Will review this or v2 these days. On first sight the first two in series are ok, the third one has style problems: ---8--- abiessmann@azuregos % ./tools/checkpatch.pl U-Boot-3-3-at91-atmel_nand-Update-driver-to-support-Programmable-Multibit-ECC-controller.patch WARNING: line over 80 characters ... total: 1 errors, 27 warnings, 787 lines checked NOTE: Ignored message types: COMPLEX_MACRO CONSIDER_KSTRTO MINMAX MULTISTATEMENT_MACRO_USE_DO_WHILE U-Boot-3-3-at91-atmel_nand-Update-driver-to-support-Programmable-Multibit-ECC-controller.patch has style problems, please review. If any of these errors are false positives, please report them to the maintainer, see CHECKPATCH in MAINTAINERS. ---8--- I personally do not really care about the 80 char warning but please remove these for the sake of peace ;) and please have a look for the reported error. sure, I will fix that. :) And the last, you should add at least one user of this feature. Isn't the lately applied at91sam9x5ek (is in u-boot-atmel/master and u-boot-arm/master) a perfect user for that? you are right, The PMECC usage is for 9x5ek board. I planed to push the PMECC support patches in 9x5 board in two part: one is this series, which only include nand flash driver changes. I thought those patches should be merged by u-boot mtd maintainer. Another part is some patches for 9x5 board file and config file which enable PMECC in 9x5ek board. Those patches are not sent out yet. Now I think if you can merge all above patches to u-boot mainline, then maybe I can sent those patches together. What do you think about this? On 8/9/2012 6:21 PM, Josh Wu wrote: This patch series will add PMECC support for atmel nand driver in u-boot. The driver patch is ported from kernel patch. The main different from kernel patch is the modification about registers access part. in this version it via a register structure to access. A question regarding linux driver. You say it is derived from the kernel driver, but I can not see PMECC stuff in kernel: Sorry, I am not make it clear about this. Actually, The PMECC stuff is not in v3.6-rc1 now, it is queued in kernel MTD maintainer's git tree: http://git.infradead.org/linux-mtd.git/commit/1c7b874d33b463f7150b1ab4617f000af9b327fd Seems the maintainer missed the merge window of v3.6-rc1. I am not sure that can go into v3.6 or not. But I think it is not a bad idea to push those code into u-boot. :) ---8--- abiessmann@azuregos % git describe v3.6-rc1-355-gddf343f abiessmann@azuregos % diff -Nrupa drivers/mtd/nand/atmel_nand.c ../u-boot/drivers/mtd/nand/atmel_nand.c | diffstat atmel_nand.c | 1231 ++- 1 file changed, 720 insertions(+), 511 deletions(-) abiessmann@azuregos % grep -in pmecc drivers/mtd/nand/atmel_nand* abiessmann@azuregos % ---8--- Which driver/patch do you mean? It is tested in atmel 9x5 series board. Unfortunately I can not test this driver cause I do only have older sam926x devices around. If I send 9x5 board enable patches with nand PMECC patches together, I think maybe other people can test it in 9x5ed board. Best regards Andreas Bießmann Best Regards, Josh Wu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/3] at91: atmel_nand: add PMECC(Programmable Multibit ECC controller) support
Dear Josh Wu, On 15.08.2012 10:19, Josh Wu wrote: Hi, Andreas Thank you for the quick reply. On 8/15/2012 3:50 PM, Andreas Bießmann wrote: Dear Josh Wu, On 15.08.2012 08:50, Josh Wu wrote: Hi, Andreas snip And the last, you should add at least one user of this feature. Isn't the lately applied at91sam9x5ek (is in u-boot-atmel/master and u-boot-arm/master) a perfect user for that? you are right, The PMECC usage is for 9x5ek board. I planed to push the PMECC support patches in 9x5 board in two part: one is this series, which only include nand flash driver changes. I thought those patches should be merged by u-boot mtd maintainer. I don't care whether Scott Wood or I take the patch (Scott, can you please comment?). If Scott takes it I should ack or the other way round. Another part is some patches for 9x5 board file and config file which enable PMECC in 9x5ek board. Those patches are not sent out yet. For me it is a must to have at least one user of the added feature. Now I think if you can merge all above patches to u-boot mainline, then maybe I can sent those patches together. What do you think about this? I think there should be one patch in the series enabling the usage of the feature. Who takes this patch is another question but I favor to enable the series in a single step. On 8/9/2012 6:21 PM, Josh Wu wrote: This patch series will add PMECC support for atmel nand driver in u-boot. The driver patch is ported from kernel patch. The main different from kernel patch is the modification about registers access part. in this version it via a register structure to access. A question regarding linux driver. You say it is derived from the kernel driver, but I can not see PMECC stuff in kernel: Sorry, I am not make it clear about this. Actually, The PMECC stuff is not in v3.6-rc1 now, it is queued in kernel MTD maintainer's git tree: http://git.infradead.org/linux-mtd.git/commit/1c7b874d33b463f7150b1ab4617f000af9b327fd Ah, I see, just found your mail on the mtd list a couple of minutes ago. I asked just to have something to compare with, I do not want to dive into the specs just to get a clue whats going on. Seems the maintainer missed the merge window of v3.6-rc1. I am not sure that can go into v3.6 or not. But I think it is not a bad idea to push those code into u-boot. :) Me too. snip It is tested in atmel 9x5 series board. Unfortunately I can not test this driver cause I do only have older sam926x devices around. If I send 9x5 board enable patches with nand PMECC patches together, I think maybe other people can test it in 9x5ed board. Would be great to get some tested by for the patches. Best regards Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4 v2] xilinx: Add new Zynq board
Hi Joe,
sorry missed this one.
On 08/14/2012 05:48 PM, Joe Hershberger wrote:
Hi Michal,
On Tue, Aug 14, 2012 at 7:15 AM, Michal Simek mon...@monstr.eu wrote:
Add support for Xilinx Zynq board.
Signed-off-by: Michal Simek mon...@monstr.eu
---
v2: Forget to also add config file
---
board/xilinx/zynq/Makefile| 57 +
board/xilinx/zynq/board.c | 64 +++
board/xilinx/zynq/lowlevel_init.S | 27
This lowlevel_init.S should be in arch/arm/cpu/armv7/zynq/
It will be in the next version.
boards.cfg|1 +
include/configs/zynq.h| 124 +
5 files changed, 273 insertions(+), 0 deletions(-)
create mode 100644 board/xilinx/zynq/Makefile
create mode 100644 board/xilinx/zynq/board.c
create mode 100644 board/xilinx/zynq/lowlevel_init.S
create mode 100644 include/configs/zynq.h
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
new file mode 100644
index 000..373a8a7
--- /dev/null
+++ b/board/xilinx/zynq/Makefile
@@ -0,0 +1,57 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS-y:= board.o
+
+COBJS := $(sort $(COBJS-y))
+
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
new file mode 100644
index 000..716fcfe
--- /dev/null
+++ b/board/xilinx/zynq/board.c
Are you thinking that this will be the one and only Zynq board?
Perhaps a layout like what Xilinx has in their branch is more
appropriate.
http://git.xilinx.com/?p=u-boot-xarm.git;a=history;f=board/xilinx/zynq_common;hb=refs/heads/master
My intention is to have one zynq generic board as I have it for microblaze.
The main reason is that every board design could be different and supporting
all variants is impossible.
When DM is ready to use with OF then DTS will handle the board differences.
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2012 Michal Simek mon...@monstr.eu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include netdev.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ icache_enable();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+#if defined(CONFIG_XILINX_GEM) defined(CONFIG_XPSS_GEM_BASEADDR0)
+ ret |= xilinx_gem_initialize(bis, CONFIG_XPSS_GEM_BASEADDR0);
+#endif
+
+ return ret;
+}
+#endif
+
+int dram_init(void)
+{
+ gd-ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ while (1)
+ ;
+}
diff
Re: [U-Boot] [Patch 0/17] New 'qemu-mips64' test architecture for U-Boot
On Tue, Aug 14, 2012 at 11:51 PM, Mike Frysinger vap...@gentoo.org wrote: On Tuesday 14 August 2012 11:49:49 Mike Frysinger wrote: On Tuesday 14 August 2012 11:06:51 Zhi-zhou Zhang wrote: As so far, U-Boot has already supports mips32. But there are some differences between mips64 and mips32. Such as different ABI, different output format. so this patch adds mips64 support. many of your patches are line wrapped. please use `git send-email` rather than whatever client you're using (looks like gmail?) as it won't screw things up. hmm, actually it's worse than that -- the leading whitespace is all mangled too. i'm assuming your code isn't that screwed up, so please resend with git- sendemail. -mike ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot OK, I will retry. actually I sent it by copy-and-paste. I wasn't aware of that. thanks. -- Regards, Zhizhou Zhang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Strange / Unreadable console output
Dear Markus Hubig,
On 14.08.2012 17:11, Markus Hubig wrote:
On Tue, Aug 14, 2012 at 02:03:55PM +0200, Andreas Bießmann wrote:
On 14.08.2012 11:08, Markus Hubig wrote:
On Tue, Aug 14, 2012 at 08:22:11AM +0200, Andreas Bießmann wrote:
On 27.07.12 11:16, Markus Hubig wrote:
snipp
Has anyone an ideea how to fix this? Or what's the cause of it? Is it even
related to u-boot or is it something at91bootstrap is doing wrong?
can you please check http://patchwork.ozlabs.org/patch/107896/
It seems this patch was set to 'Accepted' but never applied to the
master repository. Unfortunately this got lost in nirvana end of last
year. I will apply it in any case but can you please check if it fixes
your problem?
Unfortunately not ... but it dosen't do any harm.
How sad!
I wonder if this has something to do with the ominous PC9. It is
possible that this PC9 switches some vital element e.g. power supply,
'output enable' of UART level shifter or something else which needs some
settling. Have you tried adding some delay in between setting this pin
and activating the serial port output pins?
Hmm no, good idea. I tryed this in board_early_init_f(), but again with no
console output at all ...
| int board_early_init_f(void)
| {
| struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
| /* Enable clocks for all PIOs */
| writel((1 ATMEL_ID_PIOA) | (1 ATMEL_ID_PIOB) |
| (1 ATMEL_ID_PIOC), pmc-pcer);
|
| /* Enable the serial interface */
| at91_set_gpio_output(AT91_PIN_PC9, 1);
| mdelay(1000);
| at91_seriald_hw_init();
|
| return 0;
| }
Can you just test the delay in board_init()? I think it should remove
the wired characters.
Did you investigate the PCB? Which device is directly behind the DB9
connector? Can you find a datasheet for that device and check if it has
some power saving features? Can you check if these power saving features
switched with the PC9? Did taskit respond to your request for detailed
information?
Problem is, I don't have the circuit diagrams and taskit didn't respond
yet ...
Another possible reason can be the fact that you enable the output pins
after serial port is enabled (serial_init runs way before board_init).
This is what I think too! But board_early_init_f() is called befor
serial_init() so this would be the place to put this, but I don't
unterstand why the
| at91_set_gpio_output(AT91_PIN_PC9, 1);
command is not working in board_early_init_f() ...
This works for me:
---8---
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -254,6 +254,14 @@ int board_early_init_f(void)
(1 ATMEL_ID_PIOCDE),
pmc-pcer);
+ at91_set_gpio_output(AT91_PIN_PB28, 0);
+ mdelay(10);
+ at91_set_gpio_output(AT91_PIN_PB28, 1);
+ mdelay(10);
+ at91_set_gpio_output(AT91_PIN_PB28, 0);
+ mdelay(10);
+ at91_set_gpio_output(AT91_PIN_PB28, 1);
+
at91_seriald_hw_init();
return 0;
}
---8---
I can see pin toggling, unfortunately not the correct timing (~38 us
instead of 10 ms; have to have a look for that). However the PB28 stays
high after leaving board_early_init_f().
Another possibility: Your switching of PC9 in board_early_init_f works
correctly but needs some settling. Due to the defective mdelay() in
board_early_init_f() you will just see nothing cause it was toggled out
after your level shifter was ready. Have you tried pressing Return
after boot in your terminal when you tested the at91_seriald_hw_init()
in board_early_init_f()?
I even put this into serial_init() but again with no luck ...
Therefore your output is put into the TX register but I don't know what
happens then. Eventually the output is delayed until the output pins are
enabled in conjunction with the 'SYS' clock. Maybe the TX logic is
happily shifting the bits into nirvana until you switch on the output
pins. In conjunction with the PC9 thing this could be your problem.
I'll wait what taskit says, maybe this will shine some light on this issue.
BTW: have you seen this patch http://patchwork.ozlabs.org/patch/71772/
before?
Best regards
Andreas Bießmann
PS: mdelay relies on __udelay() which needs the timer running, but the
timer is started after board_early_init_f!
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Re: [U-Boot] [PATCH] YAFFS2: Fix compiler errors preventing successful build
Dear Charles Manning, On Wednesday 15 August 2012 08:16:22 Marek Vasut wrote: Signed-off-by: Marek Vasut ma...@denx.de Cc: Charles Manning cdhmann...@gmail.com Cc: Wolfgang Denk w...@denx.de While I appreciate this, I would prefer the use the patch I submitted today which also gets rid of the yaffs hweight code too. Thanks Charles ... I'll review it in a bit. -- CHarles Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Early malloc() summary
On Tue, Aug 14, 2012 at 3:54 PM, Graeme Russ graeme.r...@gmail.com wrote: dm_malloc you mean? I'm not happy about it, maybe Graeme can pour in some crazy juice in our direction again? I don't like the idea of dm_malloc() either, but it may be the only way to get this past Wolfgang in the initial pass... I agree, I am going to do it like that. Yes, this is the main question: Should I hack malloc() function or does it make sense to have both early_malloc() and malloc() exposed to DM cores/drivers? This is indeed the main question -- ideas ? The first is better from the point of view of drivers - when you ask for memory, you get it. But you have to check yourself whether you need to relocate your pointers or not, though we can provide relocation chain you can register your relocation routine into to facilitate it. The later makes sense because this makes it explicit that whenever you use early_malloc() you are responsible for relocating your data on your own (again, we can provide some facility for ir). And there is the crux of it. Two failure scenarios: 1) Write a driver which uses malloc() and fail to implement a relocation helper - Driver blows up after relocation 2) Write a driver using malloc() which you never thought to use prior to relocation and it blows up because someone used it pre-relocation or in SPL and didn't convert it to use early_malloc() Neither can be picked up by at build time... There is a third path possible: We can provide early_malloc() and say wrapped_malloc() which can be the third function give me memory, I do not care whether it is early or not. So drivers and/or DM can choose to use malloc routines working in early-only, late-only or both. Third path is dm_malloc() - Although ugly, it has a few nicities... 1) It wraps malloc() and early_malloc() around a gd-flags GD_FLG_RELOC test 2) We can pass a pointer to a driver_core struct (or whatever struct it is that holds the 'reloc' helper function pointer). We can't pick up misuse at compile time, but dm_malloc() can print a meaningful message if it is called pre-relocation with no relocation function. (We should add a flag to indicate that no relocation helper is required which may be the case for very simple drivers) Yes, but it would prevent using dm_malloc(size_t size, driver *drv) for one-time buffers inside helper functions - strdup() for instance, inside drivers in early stage. In that case we need dm_malloc_nocheck(size_t size) or we need to pass a pointer to the driver structure to each and every function call in driver which might want to call dm_malloc. Both seems impractical to me. 3) We can see right away when driver developers forget to use it Yes. And I could add a debug check into malloc() to verify we have the flag GD_FLG_RELOC set and yell when it is not. Let's leave it at that for the time being - my other thought of registering early_malloc relocation helpers can wait until someone other than DM needs to use early_malloc(). Until then, DM can deal with managing the calls to the relocation functions. I think so. We can connect the DM function into the relocation chain when it is needed. Thanks, Tomas -- Tomáš Hlaváček tmshl...@gmail.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mx25: Clean up lowlevel_init
Dear Matthias, Dear Benoît Am 14.08.2012 23:25, schrieb Benoît Thébaudeau: Clean up mx25 lowlevel_init: - Add comments. - Do not use write32 repeatedly with the same value in order no to increase code size. - Make register values configurable. - Use defined values instead of literal constants. - Use defined macros instead of duplicating code. Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com Cc: Stefano Babic sba...@denx.de --- .../arch/arm/include/asm/arch-mx25/macro.h | 57 +--- .../board/karo/tx25/lowlevel_init.S| 37 +++-- .../board/syteco/zmx25/lowlevel_init.S |6 +++ 3 files changed, 51 insertions(+), 49 deletions(-) diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx25/macro.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx25/macro.h index 3b694da..9550ade 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx25/macro.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx25/macro.h @@ -32,32 +32,49 @@ #include asm/arch/imx-regs.h #include generated/asm-offsets.h +#include asm/macro.h +/* + * AIPS setup - Only setup MPROTx registers. + * The PACR default values are good. + */ .macro init_aips - write32 IMX_AIPS1_BASE + AIPS_MPR_0_7, 0x - write32 IMX_AIPS1_BASE + AIPS_MPR_8_15, 0x - write32 IMX_AIPS2_BASE + AIPS_MPR_0_7, 0x - write32 IMX_AIPS2_BASE + AIPS_MPR_8_15, 0x + ldr r0, =IMX_AIPS1_BASE + ldr r1, =AIPS_MPR_CONFIG + str r1, [r0, #AIPS_MPR_0_7] + str r1, [r0, #AIPS_MPR_8_15] + ldr r2, =IMX_AIPS2_BASE + str r1, [r2, #AIPS_MPR_0_7] + str r1, [r2, #AIPS_MPR_8_15] .endm +/* MAX (Multi-Layer AHB Crossbar Switch) setup */ .macro init_max - write32 IMX_MAX_BASE + MAX_MPR0, 0x43210 - write32 IMX_MAX_BASE + MAX_MPR1, 0x43210 - write32 IMX_MAX_BASE + MAX_MPR2, 0x43210 - write32 IMX_MAX_BASE + MAX_MPR3, 0x43210 - write32 IMX_MAX_BASE + MAX_MPR4, 0x43210 - - write32 IMX_MAX_BASE + MAX_SGPCR0, 0x10 - write32 IMX_MAX_BASE + MAX_SGPCR1, 0x10 - write32 IMX_MAX_BASE + MAX_SGPCR2, 0x10 - write32 IMX_MAX_BASE + MAX_SGPCR3, 0x10 - write32 IMX_MAX_BASE + MAX_SGPCR4, 0x10 + ldr r0, =IMX_MAX_BASE + ldr r1, =MAX_MPR_CONFIG + str r1, [r0, #MAX_MPR0] /* for S0 */ + str r1, [r0, #MAX_MPR1] /* for S1 */ + str r1, [r0, #MAX_MPR2] /* for S2 */ + str r1, [r0, #MAX_MPR3] /* for S3 */ + str r1, [r0, #MAX_MPR4] /* for S4 */ + ldr r1, =MAX_SGPCR_CONFIG + str r1, [r0, #MAX_SGPCR0] /* for S0 */ + str r1, [r0, #MAX_SGPCR1] /* for S1 */ + str r1, [r0, #MAX_SGPCR2] /* for S2 */ + str r1, [r0, #MAX_SGPCR3] /* for S3 */ + str r1, [r0, #MAX_SGPCR4] /* for S4 */ + ldr r1, =MAX_MGPCR_CONFIG + str r1, [r0, #MAX_MGPCR0] /* for M0 */ + str r1, [r0, #MAX_MGPCR1] /* for M1 */ + str r1, [r0, #MAX_MGPCR2] /* for M2 */ + str r1, [r0, #MAX_MGPCR3] /* for M3 */ + str r1, [r0, #MAX_MGPCR4] /* for M4 */ +.endm - write32 IMX_MAX_BASE + MAX_MGPCR0, 0x0 - write32 IMX_MAX_BASE + MAX_MGPCR1, 0x0 - write32 IMX_MAX_BASE + MAX_MGPCR2, 0x0 - write32 IMX_MAX_BASE + MAX_MGPCR3, 0x0 - write32 IMX_MAX_BASE + MAX_MGPCR4, 0x0 +/* M3IF setup */ +.macro init_m3if + /* M3IF Control Register (M3IFCTL) */ + write32 IMX_M3IF_CTRL_BASE, M3IFCTL_CONFIG .endm #endif /* __ASSEMBLY__ */ diff --git u-boot-4d3c95f.orig/board/karo/tx25/lowlevel_init.S u-boot-4d3c95f/board/karo/tx25/lowlevel_init.S index 823df10..cdd9bda 100644 --- u-boot-4d3c95f.orig/board/karo/tx25/lowlevel_init.S +++ u-boot-4d3c95f/board/karo/tx25/lowlevel_init.S @@ -23,36 +23,13 @@ #include asm/macro.h -.macro init_aips - write32 0x43f0, 0x - write32 0x43f4, 0x - write32 0x43f0, 0x - write32 0x53f4, 0x -.endm +#define AIPS_MPR_CONFIG0x +#define MAX_MPR_CONFIG 0x43210 +#define MAX_SGPCR_CONFIG 0x10 +#define MAX_MGPCR_CONFIG 0x0 +#define M3IFCTL_CONFIG 0x1 I think it would be nicer if the init_max macro can get these values as parameters and not as define which has to be there before including the header file. You could even use default arguments so that the macro can be used without any argument in the default case. What do you think? The solution that I applied here comes from the i.MX35 lowlevel_init code. I like your suggestion. I think I will do that in my i.MX35 ll series too. -.macro init_max - write32 0x43f04000, 0x43210 - write32 0x43f04100, 0x43210 - write32 0x43f04200, 0x43210 - write32 0x43f04300, 0x43210 - write32 0x43f04400, 0x43210 - -
[U-Boot] V4 S3C64XX: Switch all I/O to use readl/writel functio and Clear SMDK64XX
V4: 1. Adjust SPL patch order 2. seperate the patch of arm1176: Fixed No relocation., It is a common issue for arm platform. I sent it for other thread. V3: 1. Replace ELFIN with S3C64XX for all the variable of cpu.h. 2. Change __S3C6400_H__ into __CPU__H__. 3. Use C language to implement memory initialization. 4. Use C language to re-write reset function. 5. Delete u-boot-nand.lds. V2: 1. Modify the type of return for s3c64xx_get_base_nand 2. Add patch 0014 to support s3c6410 board 3. Adjust patch for mix content. V1: This serial patch intent to: 1. Switch all I/O to use readl/writel function 2. Change nand_spl to use SPL framework 3. S3C64XX serial includes s3c6400 and s3c6410, Here seprate cpu and board file to support to board's of s3c6410. I test this patch on my s3c6410 development board. the log as following: U-Boot 2012.07-rc3-00016-g351ea73 (Jul 28 2012 - 16:55:32) for DMATEK6410 CPU: S3C64XX@532MHz Fclk = 532MHz, Hclk = 133MHz, Pclk = 66MHz (ASYNC Mode) Board: DMATEK6410 DRAM: 128 MiB WARNING: Caches not enabled NAND: 128 MiB *** Warning - bad CRC, using default environment In:serial Out: serial Err: serial Net: dm9000 Zhong Hongbo (14): smdk6400: Move smdk6400 board from Makefile to boards.cfg S3C64XX: Switch to use readl/writel to operate nand flash S3C64XX: Use readl/writel to operate uart S3C64XX: add pwm for s3c64xx support S3C64XX: reference s5p cpu time system for s3c64xx timer S3C64xx: mov cpu_init.S to the board directory S3C6400: Adopt SPL framwork to support spl for nand flash S3C6400: Delete nand_spl for S3C6400 S3C64XX: Change SROM init to use read/write operation S3C64XX: Switch to use read/writel to operation clock system S3c64xx: clear GPIO, Interrupt, Watchdog variable. S3C6400: clear memory init variable S3C64XX: Move s3c6400.h to cpu.h to support s3c6410 board S3C6400: Remove the unused variable for S3C6400 Makefile| 20 - arch/arm/cpu/arm1176/s3c64xx/Makefile |7 +- arch/arm/cpu/arm1176/s3c64xx/cpu_init.S | 135 arch/arm/cpu/arm1176/s3c64xx/pwm.c | 188 + arch/arm/cpu/arm1176/s3c64xx/reset.S| 34 - arch/arm/cpu/arm1176/s3c64xx/reset.c| 39 + arch/arm/cpu/arm1176/s3c64xx/speed.c| 52 +- arch/arm/cpu/arm1176/s3c64xx/srom.c | 51 ++ arch/arm/cpu/arm1176/s3c64xx/timer.c| 195 +++--- arch/arm/cpu/arm1176/start.S| 16 +- arch/arm/include/asm/arch-s3c64xx/clock.h | 163 arch/arm/include/asm/arch-s3c64xx/cpu.h | 89 +++ arch/arm/include/asm/arch-s3c64xx/dmc.h | 62 ++ arch/arm/include/asm/arch-s3c64xx/gpio.h| 38 + arch/arm/include/asm/arch-s3c64xx/interrupt.h | 31 + arch/arm/include/asm/arch-s3c64xx/nand.h| 72 ++ arch/arm/include/asm/arch-s3c64xx/pwm.h | 70 ++ arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 895 --- arch/arm/include/asm/arch-s3c64xx/s3c64x0.h | 90 --- arch/arm/include/asm/arch-s3c64xx/sromc.h | 49 ++ arch/arm/include/asm/arch-s3c64xx/uart.h| 54 ++ board/samsung/smdk6400/Makefile | 30 +- board/samsung/smdk6400/config.mk| 30 - board/samsung/smdk6400/dmc_init.c | 110 +++ board/samsung/smdk6400/lowlevel_init.S | 76 +- board/samsung/smdk6400/setup.h | 137 board/samsung/smdk6400/smdk6400.c | 40 +- board/samsung/smdk6400/smdk6400_nand_spl.c | 61 ++- board/samsung/smdk6400/tools/mksmdk6400_image.c | 117 +++ board/samsung/smdk6400/u-boot-nand.lds | 84 --- boards.cfg |2 + drivers/mtd/nand/s3c64xx.c | 64 +- drivers/serial/s3c64xx.c| 52 +- drivers/usb/host/s3c64xx-hcd.c | 32 +- include/configs/smdk6400.h | 40 +- nand_spl/board/samsung/smdk6400/Makefile| 117 --- nand_spl/board/samsung/smdk6400/config.mk | 40 - nand_spl/board/samsung/smdk6400/u-boot.lds | 78 -- 38 files changed, 1667 insertions(+), 1793 deletions(-) delete mode 100644 arch/arm/cpu/arm1176/s3c64xx/cpu_init.S create mode 100644 arch/arm/cpu/arm1176/s3c64xx/pwm.c delete mode 100644 arch/arm/cpu/arm1176/s3c64xx/reset.S create mode 100644 arch/arm/cpu/arm1176/s3c64xx/reset.c create mode 100644 arch/arm/cpu/arm1176/s3c64xx/srom.c create mode 100644 arch/arm/include/asm/arch-s3c64xx/clock.h create mode 100644 arch/arm/include/asm/arch-s3c64xx/cpu.h create mode 100644 arch/arm/include/asm/arch-s3c64xx/dmc.h create mode 100644 arch/arm/include/asm/arch-s3c64xx/gpio.h create mode 100644 arch/arm/include/asm/arch-s3c64xx/interrupt.h create mode 100644 arch/arm/include/asm/arch-s3c64xx/nand.h create mode 100644 arch/arm/include/asm/arch-s3c64xx/pwm.h delete mode
[U-Boot] [PATCH 01/14] smdk6400: Move smdk6400 board from Makefile to boards.cfg
From: Zhong Hongbo bocui...@gmail.com Signed-off-by: Zhong Hongbo bocui...@gmail.com --- Change for V4: - None. Change for V3: - None. Change for V2: - None. --- Makefile | 20 board/samsung/smdk6400/config.mk |4 +--- boards.cfg |2 ++ include/configs/smdk6400.h |2 +- 4 files changed, 4 insertions(+), 24 deletions(-) diff --git a/Makefile b/Makefile index d57c15e..8af1d5d 100644 --- a/Makefile +++ b/Makefile @@ -711,26 +711,6 @@ SX1_config:unconfig fi; @$(MKCONFIG) -n $@ SX1 arm arm925t sx1 -# -## ARM1176 Systems -# -smdk6400_noUSB_config \ -smdk6400_config: unconfig - @mkdir -p $(obj)include $(obj)board/samsung/smdk6400 - @mkdir -p $(obj)nand_spl/board/samsung/smdk6400 - @echo #define CONFIG_NAND_U_BOOT $(obj)include/config.h - @echo CONFIG_NAND_U_BOOT = y $(obj)include/config.mk - @if [ -z $(findstring smdk6400_noUSB_config,$@) ]; then \ - echo RAM_TEXT = 0x57e0 $(obj)board/samsung/smdk6400/config.tmp;\ - else \ - echo RAM_TEXT = 0xc7e0 $(obj)board/samsung/smdk6400/config.tmp;\ - fi - @$(MKCONFIG) smdk6400 arm arm1176 smdk6400 samsung s3c64xx - @echo CONFIG_NAND_U_BOOT = y $(obj)include/config.mk - -# -# - clean: @rm -f $(obj)examples/standalone/82559_eeprom \ $(obj)examples/standalone/atmel_df_pow2\ diff --git a/board/samsung/smdk6400/config.mk b/board/samsung/smdk6400/config.mk index 6f04c2f..93a1a0d 100644 --- a/board/samsung/smdk6400/config.mk +++ b/board/samsung/smdk6400/config.mk @@ -21,10 +21,8 @@ # # download area is 0x5000c000 -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - ifndef CONFIG_NAND_SPL -CONFIG_SYS_TEXT_BASE = $(RAM_TEXT) +CONFIG_SYS_TEXT_BASE = $(CONFIG_RAM_TEXT) else CONFIG_SYS_TEXT_BASE = 0 endif diff --git a/boards.cfg b/boards.cfg index 2d36d83..0363b41 100644 --- a/boards.cfg +++ b/boards.cfg @@ -47,6 +47,8 @@ flea3arm arm1136 - CarMedi mx35pdk arm arm1136 - freescale mx35 apollon arm arm1136 apollon - omap24xx omap2420h4 arm arm1136 - ti omap24xx +smdk6400 arm arm1176 smdk6400 samsungs3c64xx smdk6400:NAND_U_BOOT,RAM_TEXT=0xc7e0 +smdk6400_nousb arm arm1176 smdk6400 samsungs3c64xx smdk6400:NAND_U_BOOT,RAM_TEXT=0x57e0 tnetv107x_evmarm arm1176 tnetv107xevmti tnetv107x integratorap_cm720t arm arm720t integrator armltd - integratorap:CM720T integratorap_cm920t arm arm920t integrator armltd - integratorap:CM920T diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index 04caeef..47326d6 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -54,7 +54,7 @@ /* input clock of PLL: SMDK6400 has 12MHz input clock */ #define CONFIG_SYS_CLK_FREQ1200 -#if !defined(CONFIG_NAND_SPL) (CONFIG_SYS_TEXT_BASE = 0xc000) +#if !defined(CONFIG_NAND_U_BOOT) (CONFIG_SYS_TEXT_BASE = 0xc000) #define CONFIG_ENABLE_MMU #endif -- 1.7.5.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 02/14] S3C64XX: Switch to use readl/writel to operate nand flash
From: Zhong Hongbo bocui...@gmail.com
Signed-off-by: Zhong Hongbo bocui...@gmail.com
---
Change for V4:
- None.
Change for V3:
- Replace the magic numbers with variable name.
Change for V2:
- Change the type of the return value from unsinged int
to unsinged long for s3c64xx_get_base_uart function.
- Delete const for the local variable.
---
arch/arm/include/asm/arch-s3c64xx/nand.h| 72
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 79 ++-
board/samsung/smdk6400/lowlevel_init.S |1 +
drivers/mtd/nand/s3c64xx.c | 58 +---
4 files changed, 116 insertions(+), 94 deletions(-)
create mode 100644 arch/arm/include/asm/arch-s3c64xx/nand.h
diff --git a/arch/arm/include/asm/arch-s3c64xx/nand.h
b/arch/arm/include/asm/arch-s3c64xx/nand.h
new file mode 100644
index 000..a1bf3ab
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c64xx/nand.h
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2012
+ * Zhong Hongbo bocui...@gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_NAND_H__
+#define __ASM_ARCH_NAND_H__
+
+#define NFCONF_OFFSET 0x00
+#define NFCONT_OFFSET 0x04
+
+#define NFCONF_ECC_4BIT(124)
+
+#define NFCONT_ECC_ENC (118)
+#define NFCONT_WP (116)
+#define NFCONT_MECCLOCK(17)
+#define NFCONT_SECCLOCK(16)
+#define NFCONT_INITMECC(15)
+#define NFCONT_INITSECC(14)
+#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC)
+#define NFCONT_CS_ALT (12)
+#define NFCONT_CS (11)
+#define NFCONT_ENABLE (10)
+
+#define NFSTAT_ECCENCDONE (17)
+#define NFSTAT_ECCDECDONE (16)
+#define NFSTAT_RnB (10)
+
+#define NFESTAT0_ECCBUSY (131)
+
+#ifndef __ASSEMBLY__
+/* NAND FLASH */
+struct s3c64xx_nand {
+ u32 nfconf;
+ u32 nfcont;
+ u32 nfcmmd;
+ u32 nfaddr;
+ u32 nfdata;
+ u32 nfmeccdata0;
+ u32 nfmeccdata1;
+ u32 nfseccdata0;
+ u32 nfsblk;
+ u32 nfeblk;
+ u32 nfstat;
+ u32 nfestat0;
+ u32 nfestat1;
+ u32 nfmecc0;
+ u32 nfmecc1;
+ u32 nfsecc;
+ u32 nfmlcbitpt;
+};
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index 10b3324..d6c5dd9 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -556,80 +556,6 @@
*/
#define ELFIN_NAND_BASE0x7020
-#define NFCONF_OFFSET 0x00
-#define NFCONT_OFFSET 0x04
-#define NFCMMD_OFFSET 0x08
-#define NFADDR_OFFSET 0x0c
-#define NFDATA_OFFSET 0x10
-#define NFMECCDATA0_OFFSET 0x14
-#define NFMECCDATA1_OFFSET 0x18
-#define NFSECCDATA0_OFFSET 0x1c
-#define NFSBLK_OFFSET 0x20
-#define NFEBLK_OFFSET 0x24
-#define NFSTAT_OFFSET 0x28
-#define NFESTAT0_OFFSET0x2c
-#define NFESTAT1_OFFSET0x30
-#define NFMECC0_OFFSET 0x34
-#define NFMECC1_OFFSET 0x38
-#define NFSECC_OFFSET 0x3c
-#define NFMLCBITPT_OFFSET 0x40
-
-#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET)
-#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET)
-#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET)
-#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET)
-#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFMECCDATA0(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
-#define NFMECCDATA1(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
-#define NFSECCDATA0(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
-#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET)
-#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET)
-#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET)
-#define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET)
-#define NFESTAT1 (ELFIN_NAND_BASE +
[U-Boot] [PATCH 03/14] S3C64XX: Use readl/writel to operate uart
From: Zhong Hongbo bocui...@gmail.com
Signed-off-by: Zhong Hongbo bocui...@gmail.com
---
Change for V4:
- None.
Change for v3:
- None.
Change for V2:
- Change the type of the return value from unsinged int
to unsinged long for s3c64xx_get_base_uart function.
- Delete const for the local variable.
---
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 65 +--
arch/arm/include/asm/arch-s3c64xx/s3c64x0.h | 31 -
arch/arm/include/asm/arch-s3c64xx/uart.h| 54 ++
board/samsung/smdk6400/lowlevel_init.S |8 ---
drivers/serial/s3c64xx.c| 50 +
5 files changed, 87 insertions(+), 121 deletions(-)
create mode 100644 arch/arm/include/asm/arch-s3c64xx/uart.h
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index d6c5dd9..77b9509 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -582,62 +582,6 @@
*/
#define ELFIN_UART_BASE0x7F005000
-#define ELFIN_UART0_OFFSET 0x
-#define ELFIN_UART1_OFFSET 0x0400
-#define ELFIN_UART2_OFFSET 0x0800
-
-#define ULCON_OFFSET 0x00
-#define UCON_OFFSET0x04
-#define UFCON_OFFSET 0x08
-#define UMCON_OFFSET 0x0C
-#define UTRSTAT_OFFSET 0x10
-#define UERSTAT_OFFSET 0x14
-#define UFSTAT_OFFSET 0x18
-#define UMSTAT_OFFSET 0x1C
-#define UTXH_OFFSET0x20
-#define URXH_OFFSET0x24
-#define UBRDIV_OFFSET 0x28
-#define UDIVSLOT_OFFSET0x2C
-#define UINTP_OFFSET 0x30
-#define UINTSP_OFFSET 0x34
-#define UINTM_OFFSET 0x38
-
-#define ULCON0_REG __REG(0x7F005000)
-#define UCON0_REG __REG(0x7F005004)
-#define UFCON0_REG __REG(0x7F005008)
-#define UMCON0_REG __REG(0x7F00500C)
-#define UTRSTAT0_REG __REG(0x7F005010)
-#define UERSTAT0_REG __REG(0x7F005014)
-#define UFSTAT0_REG__REG(0x7F005018)
-#define UMSTAT0_REG__REG(0x7F00501c)
-#define UTXH0_REG __REG(0x7F005020)
-#define URXH0_REG __REG(0x7F005024)
-#define UBRDIV0_REG__REG(0x7F005028)
-#define UDIVSLOT0_REG __REG(0x7F00502c)
-#define UINTP0_REG __REG(0x7F005030)
-#define UINTSP0_REG__REG(0x7F005034)
-#define UINTM0_REG __REG(0x7F005038)
-
-#define ULCON1_REG __REG(0x7F005400)
-#define UCON1_REG __REG(0x7F005404)
-#define UFCON1_REG __REG(0x7F005408)
-#define UMCON1_REG __REG(0x7F00540C)
-#define UTRSTAT1_REG __REG(0x7F005410)
-#define UERSTAT1_REG __REG(0x7F005414)
-#define UFSTAT1_REG__REG(0x7F005418)
-#define UMSTAT1_REG__REG(0x7F00541c)
-#define UTXH1_REG __REG(0x7F005420)
-#define URXH1_REG __REG(0x7F005424)
-#define UBRDIV1_REG__REG(0x7F005428)
-#define UDIVSLOT1_REG __REG(0x7F00542c)
-#define UINTP1_REG __REG(0x7F005430)
-#define UINTSP1_REG__REG(0x7F005434)
-#define UINTM1_REG __REG(0x7F005438)
-
-#define UTRSTAT_TX_EMPTY (1 2)
-#define UTRSTAT_RX_READY (1 0)
-#define UART_ERR_MASK 0xF
-
/*
* PWM timer
*/
@@ -804,17 +748,12 @@
#define DMC_DDR_USER_CONFIG1
#ifndef __ASSEMBLY__
-enum s3c64xx_uarts_nr {
- S3C64XX_UART0,
- S3C64XX_UART1,
- S3C64XX_UART2,
-};
#include s3c64x0.h
-static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr)
+static inline unsigned long s3c64xx_get_base_uart(void)
{
- return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400));
+ return ELFIN_UART_BASE;
}
static inline unsigned long s3c64xx_get_base_nand(void)
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
b/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
index 0bbf1d0..7add68c 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
@@ -40,37 +40,6 @@
#include asm/types.h
-/* UART (see manual chapter 11) */
-typedef struct {
- volatile u32ULCON;
- volatile u32UCON;
- volatile u32UFCON;
- volatile u32UMCON;
- volatile u32UTRSTAT;
- volatile u32UERSTAT;
- volatile u32UFSTAT;
- volatile u32UMSTAT;
-#ifdef __BIG_ENDIAN
- volatile u8 res1[3];
- volatile u8 UTXH;
- volatile u8 res2[3];
- volatile u8 URXH;
-#else /* Little Endian */
- volatile u8 UTXH;
- volatile u8 res1[3];
- volatile u8 URXH;
- volatile u8 res2[3];
-#endif
- volatile u32UBRDIV;
-#ifdef __BIG_ENDIAN
- volatile u8 res3[2];
- volatile u16UDIVSLOT;
-#else
- volatile u16
[U-Boot] [PATCH 04/14] S3C64XX: add pwm for s3c64xx support
From: Zhong Hongbo bocui...@gmail.com
Signed-off-by: Zhong Hongbo bocui...@gmail.com
---
Change for V4:
- None.
Change for V3:
- None.
Change for V2:
- Change the type of the return value from unsinged int
to unsinged long for s3c64xx_get_base_nand function.
---
arch/arm/cpu/arm1176/s3c64xx/Makefile |1 +
arch/arm/cpu/arm1176/s3c64xx/pwm.c | 188 +++
arch/arm/include/asm/arch-s3c64xx/pwm.h | 70 ++
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 56 ++---
arch/arm/include/asm/arch-s3c64xx/s3c64x0.h | 59 -
include/configs/smdk6400.h |3 +
6 files changed, 271 insertions(+), 106 deletions(-)
create mode 100644 arch/arm/cpu/arm1176/s3c64xx/pwm.c
create mode 100644 arch/arm/include/asm/arch-s3c64xx/pwm.h
delete mode 100644 arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile
b/arch/arm/cpu/arm1176/s3c64xx/Makefile
index 0785b19..93f 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/Makefile
+++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile
@@ -32,6 +32,7 @@ SOBJS = reset.o
COBJS-$(CONFIG_S3C6400)+= cpu_init.o speed.o
COBJS-y+= timer.o
+COBJS-$(CONFIG_PWM) += pwm.o
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
diff --git a/arch/arm/cpu/arm1176/s3c64xx/pwm.c
b/arch/arm/cpu/arm1176/s3c64xx/pwm.c
new file mode 100644
index 000..fff2c68
--- /dev/null
+++ b/arch/arm/cpu/arm1176/s3c64xx/pwm.c
@@ -0,0 +1,188 @@
+/*
+ * Copyright (C) 2012
+ * Zhong Hongbo bocui...@gmail.com
+ *
+ * based on arch/arm/cpu/armv7/s5p-common/pwm.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include errno.h
+#include pwm.h
+#include asm/io.h
+#include asm/arch/s3c6400.h
+#include asm/arch/pwm.h
+
+int pwm_enable(int pwm_id)
+{
+ const struct s3c_timer *pwm =
+ (struct s3c_timer *)s3c64xx_get_base_timer();
+ unsigned long tcon;
+
+ tcon = readl(pwm-tcon);
+ tcon |= TCON_START(pwm_id);
+
+ writel(tcon, pwm-tcon);
+
+ return 0;
+}
+
+void pwm_disable(int pwm_id)
+{
+ const struct s3c_timer *pwm =
+ (struct s3c_timer *)s3c64xx_get_base_timer();
+ unsigned long tcon;
+
+ tcon = readl(pwm-tcon);
+ tcon = ~TCON_START(pwm_id);
+
+ writel(tcon, pwm-tcon);
+}
+
+static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq)
+{
+ unsigned long tin_parent_rate;
+ unsigned int div;
+
+ tin_parent_rate = get_PCLK();
+
+ for (div = 2; div = 16; div *= 2) {
+ if ((tin_parent_rate / (div 16)) freq)
+ return tin_parent_rate / div;
+ }
+
+ return tin_parent_rate / 16;
+}
+
+#define NS_IN_HZ (10UL)
+
+int pwm_config(int pwm_id, int duty_ns, int period_ns)
+{
+ const struct s3c_timer *pwm =
+ (struct s3c_timer *)s3c64xx_get_base_timer();
+ unsigned int offset;
+ unsigned long tin_rate;
+ unsigned long tin_ns;
+ unsigned long period;
+ unsigned long tcon;
+ unsigned long tcnt;
+ unsigned long tcmp;
+
+ /*
+* We currently avoid using 64bit arithmetic by using the
+* fact that anything faster than 1GHz is easily representable
+* by 32bits.
+*/
+ if (period_ns NS_IN_HZ || duty_ns NS_IN_HZ)
+ return -ERANGE;
+
+ if (duty_ns period_ns)
+ return -EINVAL;
+
+ period = NS_IN_HZ / period_ns;
+
+ /* Check to see if we are changing the clock rate of the PWM */
+ tin_rate = pwm_calc_tin(pwm_id, period);
+
+ tin_ns = NS_IN_HZ / tin_rate;
+ tcnt = period_ns / tin_ns;
+
+ /* Note, counters count down */
+ tcmp = duty_ns / tin_ns;
+ tcmp = tcnt - tcmp;
+
+ /*
+* the pwm hw only checks the compare register after a decrement,
+* so the pin never toggles if tcmp = tcnt
+*/
+ if (tcmp == tcnt)
+ tcmp--;
+
+ if (tcmp 0)
+ tcmp = 0;
+
+ /* Update the PWM register block. */
+ offset = pwm_id * 3;
+ if (pwm_id 4) {
+
[U-Boot] [PATCH 05/14] S3C64XX: reference s5p cpu time system for s3c64xx timer
From: Zhong Hongbo bocui...@gmail.com
The old s3c64xx timer is not work normal, Adopt s5p time design,
It work perfect.
Signed-off-by: Zhong Hongbo bocui...@gmail.com
---
Change for V4:
- None.
Change for V3:
- None.
Change for V2:
- Delete const key word for the variable of struct s3c_timer
---
arch/arm/cpu/arm1176/s3c64xx/timer.c | 193 --
1 files changed, 93 insertions(+), 100 deletions(-)
diff --git a/arch/arm/cpu/arm1176/s3c64xx/timer.c
b/arch/arm/cpu/arm1176/s3c64xx/timer.c
index f16a37b..47d7731 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/timer.c
+++ b/arch/arm/cpu/arm1176/s3c64xx/timer.c
@@ -1,23 +1,8 @@
/*
- * (C) Copyright 2003
- * Texas Instruments www.ti.com
+ * Copyright (C) 2012
+ * Zhong Hongbo bocui...@163.com
*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH www.elinos.com
- * Marius Groeger mgroe...@sysgo.de
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH www.elinos.com
- * Alex Zuepke a...@sysgo.de
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, ga...@denx.de
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. philippe.ro...@arm.com
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de
+ * based on arch/arm/cpu/armv7/s5p-common/timer.c
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -39,64 +24,29 @@
*/
#include common.h
-#include asm/proc-armv/ptrace.h
+#include asm/io.h
#include asm/arch/s3c6400.h
-#include div64.h
-
-static ulong timer_load_val;
+#include asm/arch/pwm.h
+#include pwm.h
-#define PRESCALER 167
+DECLARE_GLOBAL_DATA_PTR;
-static s3c64xx_timers *s3c64xx_get_base_timers(void)
-{
- return (s3c64xx_timers *)ELFIN_TIMER_BASE;
-}
+static unsigned long get_current_tick(void);
/* macro to read the 16 bit timer */
-static inline ulong read_timer(void)
+static inline struct s3c_timer *s3c_get_base_timer(void)
{
- s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
- return timers-TCNTO4;
+ return (struct s3c_timer *)s3c64xx_get_base_timer();
}
-/* Internal tick units */
-/* Last decremneter snapshot */
-static unsigned long lastdec;
-/* Monotonic incrementing timer */
-static unsigned long long timestamp;
-
int timer_init(void)
{
- s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
- /* use PWM Timer 4 because it has no output */
- /*
-* We use the following scheme for the timer:
-* Prescaler is hard fixed at 167, divider at 1/4.
-* This gives at PCLK frequency 66MHz approx. 10us ticks
-* The timer is set to wrap after 100s, at 66MHz this obviously
-* happens after 10,000,000 ticks. A long variable can thus
-* keep values up to 40,000s, i.e., 11 hours. This should be
-* enough for most uses:-) Possible optimizations: select a
-* binary-friendly frequency, e.g., 1ms / 128. Also calculate
-* the prescaler automatically for other PCLK frequencies.
-*/
- timers-TCFG0 = PRESCALER 8;
- if (timer_load_val == 0) {
- timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */
- timers-TCFG1 = (timers-TCFG1 ~0xf) | 0x2;
- }
-
- /* load value for 10 ms timeout */
- lastdec = timers-TCNTB4 = timer_load_val;
- /* auto load, manual update of Timer 4 */
- timers-TCON = (timers-TCON ~0x0070) | TCON_4_AUTO |
- TCON_4_UPDATE;
+ /* PWM Timer 4 */
+ pwm_init(4, MUX_DIV_2, 0);
+ pwm_config(4, 0, 0);
+ pwm_enable(4);
- /* auto load, start Timer 4 */
- timers-TCON = (timers-TCON ~0x0070) | TCON_4_AUTO | COUNT_4_ON;
- timestamp = 0;
+ reset_timer_masked();
return 0;
}
@@ -104,57 +54,100 @@ int timer_init(void)
/*
* timer without interrupts
*/
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
+unsigned long get_timer(unsigned long base)
{
- ulong now = read_timer();
+ return get_timer_masked() - base;
+}
- if (lastdec = now) {
- /* normal mode */
- timestamp += lastdec - now;
+/* delay x useconds */
+void __udelay(unsigned long usec)
+{
+ struct s3c_timer *timer = s3c_get_base_timer();
+ unsigned long tmo, tmp, count_value;
+
+ count_value = readl(timer-tcntb4);
+
+ if (usec = 1000) {
+ /*
+* if big number, spread normalization
+* to seconds
+* 1. start to normalize for usec to ticks per sec
+* 2. find number of ticks to wait to achieve target
+* 3. finish normalize.
+*/
+ tmo = usec / 1000;
+ tmo *= (CONFIG_SYS_HZ * count_value);
+ tmo /=
[U-Boot] [PATCH 06/14] S3C64xx: mov cpu_init.S to the board directory
From: Zhong Hongbo bocui...@gmail.com It just only do the memory init. The memory depend on the design of board. Signed-off-by: Zhong Hongbo bocui...@gmail.com --- Change for V4: - None. Change for V3: - None. Change for V2: - None. --- arch/arm/cpu/arm1176/s3c64xx/Makefile |2 +- arch/arm/cpu/arm1176/s3c64xx/cpu_init.S | 135 --- board/samsung/smdk6400/Makefile |2 +- board/samsung/smdk6400/mem_init.S | 135 +++ 4 files changed, 137 insertions(+), 137 deletions(-) delete mode 100644 arch/arm/cpu/arm1176/s3c64xx/cpu_init.S create mode 100644 board/samsung/smdk6400/mem_init.S diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile b/arch/arm/cpu/arm1176/s3c64xx/Makefile index 93f..2f37431 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/Makefile +++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile @@ -30,7 +30,7 @@ LIB = $(obj)lib$(SOC).o SOBJS = reset.o -COBJS-$(CONFIG_S3C6400)+= cpu_init.o speed.o +COBJS-$(CONFIG_S3C64XX)+= speed.o COBJS-y+= timer.o COBJS-$(CONFIG_PWM) += pwm.o diff --git a/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S b/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S deleted file mode 100644 index df88cba..000 --- a/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400 - * - * Copyright (C) 2008 - * Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include config.h -#include asm/arch/s3c6400.h - - .globl mem_ctrl_asm_init -mem_ctrl_asm_init: - /* DMC1 base address 0x7e001000 */ - ldr r0, =ELFIN_DMC1_BASE - - ldr r1, =0x4 - str r1, [r0, #INDEX_DMC_MEMC_CMD] - - ldr r1, =DMC_DDR_REFRESH_PRD - str r1, [r0, #INDEX_DMC_REFRESH_PRD] - - ldr r1, =DMC_DDR_CAS_LATENCY - str r1, [r0, #INDEX_DMC_CAS_LATENCY] - - ldr r1, =DMC_DDR_t_DQSS - str r1, [r0, #INDEX_DMC_T_DQSS] - - ldr r1, =DMC_DDR_t_MRD - str r1, [r0, #INDEX_DMC_T_MRD] - - ldr r1, =DMC_DDR_t_RAS - str r1, [r0, #INDEX_DMC_T_RAS] - - ldr r1, =DMC_DDR_t_RC - str r1, [r0, #INDEX_DMC_T_RC] - - ldr r1, =DMC_DDR_t_RCD - ldr r2, =DMC_DDR_schedule_RCD - orr r1, r1, r2 - str r1, [r0, #INDEX_DMC_T_RCD] - - ldr r1, =DMC_DDR_t_RFC - ldr r2, =DMC_DDR_schedule_RFC - orr r1, r1, r2 - str r1, [r0, #INDEX_DMC_T_RFC] - - ldr r1, =DMC_DDR_t_RP - ldr r2, =DMC_DDR_schedule_RP - orr r1, r1, r2 - str r1, [r0, #INDEX_DMC_T_RP] - - ldr r1, =DMC_DDR_t_RRD - str r1, [r0, #INDEX_DMC_T_RRD] - - ldr r1, =DMC_DDR_t_WR - str r1, [r0, #INDEX_DMC_T_WR] - - ldr r1, =DMC_DDR_t_WTR - str r1, [r0, #INDEX_DMC_T_WTR] - - ldr r1, =DMC_DDR_t_XP - str r1, [r0, #INDEX_DMC_T_XP] - - ldr r1, =DMC_DDR_t_XSR - str r1, [r0, #INDEX_DMC_T_XSR] - - ldr r1, =DMC_DDR_t_ESR - str r1, [r0, #INDEX_DMC_T_ESR] - - ldr r1, =DMC1_MEM_CFG - str r1, [r0, #INDEX_DMC_MEMORY_CFG] - - ldr r1, =DMC1_MEM_CFG2 - str r1, [r0, #INDEX_DMC_MEMORY_CFG2] - - ldr r1, =DMC1_CHIP0_CFG - str r1, [r0, #INDEX_DMC_CHIP_0_CFG] - - ldr r1, =DMC_DDR_32_CFG - str r1, [r0, #INDEX_DMC_USER_CONFIG] - - /* DMC0 DDR Chip 0 configuration direct command reg */ - ldr r1, =DMC_NOP0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Precharge All */ - ldr r1, =DMC_PA0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Auto Refresh 2 time */ - ldr r1, =DMC_AR0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* MRS */ - ldr r1, =DMC_mDDR_EMR0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Mode Reg */ - ldr r1, =DMC_mDDR_MR0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Enable
[U-Boot] [PATCH 07/14] S3C6400: Adopt SPL framwork to support spl for nand flash
From: Zhong Hongbo bocui...@gmail.com Adopt the new SPL framework to implement the SPL booting of the nand flash for S3C6400. Signed-off-by: Zhong Hongbo bocui...@gmail.com --- Change for V4: - Adjust the patch's order. Change for V3: - None. Change for V2: - seprate some code. --- arch/arm/cpu/arm1176/start.S| 16 +--- board/samsung/smdk6400/Makefile | 29 +- board/samsung/smdk6400/lowlevel_init.S | 22 ++-- board/samsung/smdk6400/smdk6400_nand_spl.c | 61 ++-- board/samsung/smdk6400/tools/mksmdk6400_image.c | 117 +++ drivers/mtd/nand/s3c64xx.c |4 +- include/configs/smdk6400.h | 21 +++-- 7 files changed, 221 insertions(+), 49 deletions(-) create mode 100644 board/samsung/smdk6400/tools/mksmdk6400_image.c diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index d613641..761b7fe 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -51,7 +51,7 @@ .globl _start _start: b reset -#ifndef CONFIG_NAND_SPL +#ifndef CONFIG_SPL_BUILD ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -164,7 +164,7 @@ cpu_init_crit: * When booting from NAND - it has definitely been a reset, so, no need * to flush caches and disable the MMU */ -#ifndef CONFIG_NAND_SPL +#ifndef CONFIG_SPL_BUILD /* * flush v4 I/D caches */ @@ -357,21 +357,14 @@ clbss_l:cmp r0, r1 /* clear loop... */ add r0, r0, #4 b clbss_l clbss_e: -#ifndef CONFIG_NAND_SPL bl coloured_LED_init bl red_led_on #endif -#endif /* * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. */ -#ifdef CONFIG_NAND_SPL - ldr pc, _nand_boot - -_nand_boot: .word nand_boot -#else ldr r0, _board_init_r_ofs adr r1, _start add lr, r0, r1 @@ -384,7 +377,6 @@ _nand_boot: .word nand_boot _board_init_r_ofs: .word board_init_r - _start -#endif _rel_dyn_start_ofs: .word __rel_dyn_start - _start @@ -398,7 +390,7 @@ _mmu_table_base: .word mmu_table #endif -#ifndef CONFIG_NAND_SPL +#ifndef CONFIG_SPL_BUILD /* * we assume that cache operation is done before. (eg. cleanup_before_linux()) * actually, we don't need to do anything about cache if not use d-cache in @@ -576,4 +568,4 @@ fiq: get_bad_stack bad_save_user_regs bl do_fiq -#endif /* CONFIG_NAND_SPL */ +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/samsung/smdk6400/Makefile b/board/samsung/smdk6400/Makefile index 645c8e2..f7fa667 100644 --- a/board/samsung/smdk6400/Makefile +++ b/board/samsung/smdk6400/Makefile @@ -28,15 +28,34 @@ include $(TOPDIR)/config.mk LIB= $(obj)lib$(BOARD).o +ifndef CONFIG_SPL_BUILD COBJS-y:= smdk6400.o +endif + SOBJS := lowlevel_init.o mem_init.o -SRCS:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +ifdef CONFIG_SPL_BUILD +COBJS-y += smdk6400_nand_spl.o +endif + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) + +ALL:= $(obj).depend $(LIB) + +ifdef CONFIG_SPL_BUILD +ALL+= $(OBJTREE)/tools/mk$(BOARD)spl +endif + +all: $(ALL) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) -$(LIB):$(obj).depend $(SOBJS) $(OBJS) - $(call cmd_link_o_target, $(SOBJS) $(OBJS)) +ifdef CONFIG_SPL_BUILD +$(OBJTREE)/tools/mk$(BOARD)spl:tools/mksmdk6400_image.c + $(HOSTCC) tools/mksmdk6400_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl +endif # diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S index 45887f3..93172e7 100644 --- a/board/samsung/smdk6400/lowlevel_init.S +++ b/board/samsung/smdk6400/lowlevel_init.S @@ -84,18 +84,12 @@ lowlevel_init: str r3, [r0, #oVECTADDR] str r3, [r1, #oVECTADDR] +#ifdef CONFIG_SPL_BUILD /* init system clock */ - bl system_clock_init + bl system_clock_init -#ifndef CONFIG_NAND_SPL - /* for UART */ - bl uart_asm_init -#endif - -#ifdef CONFIG_BOOT_NAND /* simple init for NAND */ - bl nand_asm_init -#endif + bl nand_asm_init /* Memory subsystem address 0x7e00f120 */ ldr r0, =ELFIN_MEM_SYS_CFG @@ -105,6 +99,12 @@ lowlevel_init: str r1, [r0] bl mem_ctrl_asm_init +#endif + +#ifndef CONFIG_SPL_BUILD + /* for UART */ + bl uart_asm_init +#endif /* Wakeup support. Don't know if it's going to be used, untested. */ ldr r0, =(ELFIN_CLOCK_POWER_BASE +
[U-Boot] [PATCH 09/14] S3C64XX: Change SROM init to use read/write operation
From: Zhong Hongbo bocui...@gmail.com
Signed-off-by: Zhong Hongbo bocui...@gmail.com
---
Change for V4:
- None.
Change for V3:
- None.
Change for V2:
- Change the type of return for s3c64xx_get_base_sromc function.
---
arch/arm/cpu/arm1176/s3c64xx/Makefile |2 +-
arch/arm/cpu/arm1176/s3c64xx/srom.c | 51 +++
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 13 +++
arch/arm/include/asm/arch-s3c64xx/sromc.h | 49 +
board/samsung/smdk6400/smdk6400.c | 38 ++--
include/configs/smdk6400.h |1 +
6 files changed, 134 insertions(+), 20 deletions(-)
create mode 100644 arch/arm/cpu/arm1176/s3c64xx/srom.c
create mode 100644 arch/arm/include/asm/arch-s3c64xx/sromc.h
diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile
b/arch/arm/cpu/arm1176/s3c64xx/Makefile
index 2f37431..28786bf 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/Makefile
+++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile
@@ -30,7 +30,7 @@ LIB = $(obj)lib$(SOC).o
SOBJS = reset.o
-COBJS-$(CONFIG_S3C64XX)+= speed.o
+COBJS-$(CONFIG_S3C64XX)+= speed.o srom.o
COBJS-y+= timer.o
COBJS-$(CONFIG_PWM) += pwm.o
diff --git a/arch/arm/cpu/arm1176/s3c64xx/srom.c
b/arch/arm/cpu/arm1176/s3c64xx/srom.c
new file mode 100644
index 000..f1b2b34
--- /dev/null
+++ b/arch/arm/cpu/arm1176/s3c64xx/srom.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2012
+ * Zhong Hongbo bocui1...@gmail.com
+ * base on arch/arm/cpu/armv7/s5p-common/sromc.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/sromc.h
+#include asm/arch/s3c6400.h
+/*
+ * s3c64xx_config_sromc() - select the proper SROMC Bank and configure the
+ * band width control and bank control registers
+ * srom_bank - SROM
+ * srom_bw_conf - SMC Band witdh reg configuration value
+ * srom_bc_conf - SMC Bank Control reg configuration value
+ */
+void s3c64xx_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf)
+{
+ u32 tmp;
+ struct s3c64xx_sromc *srom =
+ (struct s3c64xx_sromc *)s3c64xx_get_base_sromc();
+
+ /* Configure SMC_BW register to handle proper SROMC bank */
+ tmp = srom-bw;
+ tmp = ~(0xF (srom_bank * 4));
+ tmp |= srom_bw_conf;
+
+ writel(tmp, srom-bw);
+
+ /* Configure SMC_BC register */
+ writel(srom_bc_conf, srom-bc[srom_bank]);
+}
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index b884763..d2ee9d2 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -471,14 +471,6 @@
*/
#define ELFIN_SROM_BASE0x7000
-#define SROM_BW_REG__REG(ELFIN_SROM_BASE + 0x0)
-#define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4)
-#define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8)
-#define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC)
-#define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10)
-#define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14)
-#define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18)
-
/*
* SDRAM Controller
*/
@@ -722,6 +714,11 @@ static inline unsigned long s3c64xx_get_base_timer(void)
{
return ELFIN_TIMER_BASE;
}
+
+static inline unsigned long s3c64xx_get_base_sromc(void)
+{
+ return ELFIN_SROM_BASE;
+}
#endif
#endif /*__S3C6400_H__*/
diff --git a/arch/arm/include/asm/arch-s3c64xx/sromc.h
b/arch/arm/include/asm/arch-s3c64xx/sromc.h
new file mode 100644
index 000..fcad635
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c64xx/sromc.h
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2012
+ * Zhong Hongbo bocui...@gmail.com
+ *
+ * base on arch/arm/include/asm/arch-s5pc1xx/sromc.h
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A
[U-Boot] [PATCH 08/14] S3C6400: Delete nand_spl for S3C6400
From: Zhong Hongbo bocui...@gmail.com
The old spl use nand_spl directory file to support
nand flash boot. We will adopt the new SPL framework
to implement it.
Signed-off-by: Zhong Hongbo bocui...@gmail.com
---
Change for V4:
- Adjust the patch's order.
Change for V3:
- Delete u-boot-nand.lds.
Change for V2:
- None.
---
board/samsung/smdk6400/config.mk | 28 ---
board/samsung/smdk6400/u-boot-nand.lds | 84
boards.cfg |4 +-
include/configs/smdk6400.h |2 +-
nand_spl/board/samsung/smdk6400/Makefile | 117
nand_spl/board/samsung/smdk6400/config.mk | 40 --
nand_spl/board/samsung/smdk6400/u-boot.lds | 78 --
7 files changed, 3 insertions(+), 350 deletions(-)
delete mode 100644 board/samsung/smdk6400/config.mk
delete mode 100644 board/samsung/smdk6400/u-boot-nand.lds
delete mode 100644 nand_spl/board/samsung/smdk6400/Makefile
delete mode 100644 nand_spl/board/samsung/smdk6400/config.mk
delete mode 100644 nand_spl/board/samsung/smdk6400/u-boot.lds
diff --git a/board/samsung/smdk6400/config.mk b/board/samsung/smdk6400/config.mk
deleted file mode 100644
index 93a1a0d..000
--- a/board/samsung/smdk6400/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, ga...@denx.de
-# David Mueller, ELSOFT AG, d.muel...@elsoft.ch
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de
-#
-# SAMSUNG SMDK6400 board with mDirac3 (ARM1176) cpu
-#
-# see http://www.samsung.com/ for more information on SAMSUNG
-
-# On SMDK6400 we use the 64 MB SDRAM bank at
-#
-# 0x5000 to 0x5800
-#
-# Linux-Kernel is expected to be at 0x50008000, entry 0x50008000
-#
-# we load ourselves to 0x57e0 without MMU
-# with MMU, load address is changed to 0xc7e0
-#
-# download area is 0x5000c000
-
-ifndef CONFIG_NAND_SPL
-CONFIG_SYS_TEXT_BASE = $(CONFIG_RAM_TEXT)
-else
-CONFIG_SYS_TEXT_BASE = 0
-endif
diff --git a/board/samsung/smdk6400/u-boot-nand.lds
b/board/samsung/smdk6400/u-boot-nand.lds
deleted file mode 100644
index f162815..000
--- a/board/samsung/smdk6400/u-boot-nand.lds
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, ga...@denx.de
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT(elf32-littlearm, elf32-littlearm, elf32-littlearm)
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x;
-
- . = ALIGN(4);
- .text :
- {
- arch/arm/cpu/arm1176/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
- .mmudata : { *(.mmudata) }
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end__ = .;
- }
-
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
diff --git a/boards.cfg b/boards.cfg
index 0363b41..491459a 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -47,8 +47,8 @@ flea3arm arm1136 -
CarMedi
mx35pdk arm arm1136 -
freescale mx35
apollon arm arm1136 apollon
- omap24xx
omap2420h4 arm
[U-Boot] [PATCH 10/14] S3C64XX: Switch to use read/writel to operation clock system
From: Zhong Hongbo bocui...@gmail.com
Switch to use read/writel function and clear the relevant variable.
Signed-off-by: Zhong Hongbo bocui...@gmail.com
---
Change for V4:
- None.
Change for V3:
- Use C language to re-write reset function.
- Replace the magic numbers witch variale name.
Change for V2:
- merge clock patch.
- Change the type of return for s3c64xx_get_base_clock function.
---
arch/arm/cpu/arm1176/s3c64xx/Makefile |6 +-
arch/arm/cpu/arm1176/s3c64xx/reset.S| 34
arch/arm/cpu/arm1176/s3c64xx/reset.c| 39 +
arch/arm/cpu/arm1176/s3c64xx/speed.c| 50 +--
arch/arm/include/asm/arch-s3c64xx/clock.h | 163
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 219 +--
board/samsung/smdk6400/lowlevel_init.S |3 +
board/samsung/smdk6400/setup.h | 47 ++
drivers/usb/host/s3c64xx-hcd.c | 30 -
9 files changed, 321 insertions(+), 270 deletions(-)
delete mode 100644 arch/arm/cpu/arm1176/s3c64xx/reset.S
create mode 100644 arch/arm/cpu/arm1176/s3c64xx/reset.c
create mode 100644 arch/arm/include/asm/arch-s3c64xx/clock.h
create mode 100644 board/samsung/smdk6400/setup.h
diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile
b/arch/arm/cpu/arm1176/s3c64xx/Makefile
index 28786bf..16be887 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/Makefile
+++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile
@@ -28,13 +28,11 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
-SOBJS = reset.o
-
-COBJS-$(CONFIG_S3C64XX)+= speed.o srom.o
+COBJS-$(CONFIG_S3C64XX)+= speed.o srom.o reset.o
COBJS-y+= timer.o
COBJS-$(CONFIG_PWM) += pwm.o
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+OBJS := $(addprefix $(obj), $(COBJS-y))
all: $(obj).depend $(START) $(LIB)
diff --git a/arch/arm/cpu/arm1176/s3c64xx/reset.S
b/arch/arm/cpu/arm1176/s3c64xx/reset.S
deleted file mode 100644
index eae572e..000
--- a/arch/arm/cpu/arm1176/s3c64xx/reset.S
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2009 Samsung Electronics.
- * Minkyu Kang mk7.k...@samsung.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include asm/arch/s3c6400.h
-
-.globl reset_cpu
-reset_cpu:
- ldr r1, =ELFIN_CLOCK_POWER_BASE
- ldr r2, [r1, #SYS_ID_OFFSET]
- ldr r3, =0x
- and r2, r3, r2, lsr #12
- str r2, [r1, #SW_RST_OFFSET]
-_loop_forever:
- b _loop_forever
diff --git a/arch/arm/cpu/arm1176/s3c64xx/reset.c
b/arch/arm/cpu/arm1176/s3c64xx/reset.c
new file mode 100644
index 000..773cffa
--- /dev/null
+++ b/arch/arm/cpu/arm1176/s3c64xx/reset.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2012
+ * Zhong Hongbo bocui...@gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/s3c6400.h
+#include asm/arch/clock.h
+
+void reset_cpu(ulong addr)
+{
+ unsigned long sys_id;
+ struct s3c64xx_clock *clk =
+ (struct s3c64xx_clock *)s3c64xx_get_base_clock();
+
+ sys_id = readl(clk-sys_id);
+ sys_id = 12;
+ sys_id = 0x;
+ writel(sys_id, clk-sw_rst);
+}
diff --git a/arch/arm/cpu/arm1176/s3c64xx/speed.c
b/arch/arm/cpu/arm1176/s3c64xx/speed.c
index 11962ac..05b44b9 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/speed.c
+++ b/arch/arm/cpu/arm1176/s3c64xx/speed.c
@@ -31,12 +31,13 @@
[U-Boot] [PATCH 11/14] S3c64xx: clear GPIO, Interrupt, Watchdog variable.
From: Zhong Hongbo bocui...@gmail.com Signed-off-by: Zhong Hongbo bocui...@gmail.com --- Change for V4: - None. Change for V3: - Replace the magic numbers with the variable name. Change for V2: - None. --- arch/arm/include/asm/arch-s3c64xx/gpio.h | 38 arch/arm/include/asm/arch-s3c64xx/interrupt.h | 31 +++ arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 258 - board/samsung/smdk6400/lowlevel_init.S| 16 +- board/samsung/smdk6400/setup.h| 11 +- 5 files changed, 86 insertions(+), 268 deletions(-) create mode 100644 arch/arm/include/asm/arch-s3c64xx/gpio.h create mode 100644 arch/arm/include/asm/arch-s3c64xx/interrupt.h diff --git a/arch/arm/include/asm/arch-s3c64xx/gpio.h b/arch/arm/include/asm/arch-s3c64xx/gpio.h new file mode 100644 index 000..979173c --- /dev/null +++ b/arch/arm/include/asm/arch-s3c64xx/gpio.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2012 + * Zhong Hongbo bocui...@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_GPIO_H_ +#define __ASM_ARM_ARCH_GPIO_H_ + +#define GPACON_OFFSET 0x00 +#define GPADAT_OFFSET 0x04 +#define GPAPUD_OFFSET 0x08 + +#define GPNCON_OFFSET 0x830 +#define GPNDAT_OFFSET 0x834 +#define GPNPUD_OFFSET 0x838 + +#define GPKCON0_OFFSET 0x800 +#define GPKCON1_OFFSET 0x804 +#define GPKDAT_OFFSET 0x808 +#define GPKPUD_OFFSET 0x80C + +#endif diff --git a/arch/arm/include/asm/arch-s3c64xx/interrupt.h b/arch/arm/include/asm/arch-s3c64xx/interrupt.h new file mode 100644 index 000..49e3ae4 --- /dev/null +++ b/arch/arm/include/asm/arch-s3c64xx/interrupt.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2012 + * Zhong Hongbo bocui...@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_INTERRUPT_H_ +#define __ASM_ARM_ARCH_INTERRUPT_H_ + +#define INTMOD 0x0C/* VIC INT SELECT (IRQ or FIQ) */ +#define INTUNMSK 0x10/* VIC INT EN (write 1 to unmask) */ +#define INTMSK 0x14/* VIC INT EN CLEAR (write 1 to mask) */ +#define INTSUBMSK 0x1C/* VIC SOFT INT CLEAR */ +#define VECTADDR 0xF00 /* VIC ADDRESS */ +#define EINTPEND_OFFSET0x924 +#endif diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h index b1537c1..1da327a 100644 --- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h +++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h @@ -47,172 +47,6 @@ */ #define ELFIN_GPIO_BASE0x7f008000 -#define GPACON_OFFSET 0x00 -#define GPADAT_OFFSET 0x04 -#define GPAPUD_OFFSET 0x08 -#define GPACONSLP_OFFSET 0x0C -#define GPAPUDSLP_OFFSET 0x10 -#define GPBCON_OFFSET 0x20 -#define GPBDAT_OFFSET 0x24 -#define GPBPUD_OFFSET 0x28 -#define GPBCONSLP_OFFSET 0x2C -#define GPBPUDSLP_OFFSET 0x30 -#define GPCCON_OFFSET 0x40 -#define GPCDAT_OFFSET 0x44 -#define GPCPUD_OFFSET 0x48 -#define GPCCONSLP_OFFSET 0x4C -#define GPCPUDSLP_OFFSET 0x50 -#define GPDCON_OFFSET 0x60 -#define GPDDAT_OFFSET 0x64 -#define GPDPUD_OFFSET 0x68 -#define GPDCONSLP_OFFSET 0x6C -#define GPDPUDSLP_OFFSET 0x70 -#define GPECON_OFFSET 0x80 -#define GPEDAT_OFFSET 0x84 -#define GPEPUD_OFFSET 0x88 -#define GPECONSLP_OFFSET 0x8C -#define GPEPUDSLP_OFFSET 0x90 -#define GPFCON_OFFSET 0xA0 -#define GPFDAT_OFFSET 0xA4
[U-Boot] [PATCH 12/14] S3C6400: clear memory init variable
From: Zhong Hongbo bocui...@gmail.com
Signed-off-by: Zhong Hongbo bocui...@gmail.com
---
Change for V4:
- None.
Change for V3:
- Replace the magic numbers with variable name.
- Use C language to implement memory initialization.
Change for V2:
- None.
---
arch/arm/include/asm/arch-s3c64xx/dmc.h | 62 +
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 178 +--
board/samsung/smdk6400/Makefile |3 +-
board/samsung/smdk6400/dmc_init.c | 110 +
board/samsung/smdk6400/lowlevel_init.S |2 +-
board/samsung/smdk6400/mem_init.S | 135
board/samsung/smdk6400/setup.h | 85 +
7 files changed, 265 insertions(+), 310 deletions(-)
create mode 100644 arch/arm/include/asm/arch-s3c64xx/dmc.h
create mode 100644 board/samsung/smdk6400/dmc_init.c
delete mode 100644 board/samsung/smdk6400/mem_init.S
diff --git a/arch/arm/include/asm/arch-s3c64xx/dmc.h
b/arch/arm/include/asm/arch-s3c64xx/dmc.h
new file mode 100644
index 000..758e750
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c64xx/dmc.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2012
+ * Zhong Hongbo bocui...@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#ifndef __ASM_ARCH_DMC_H__
+#define __ASM_ARCH_DMC_H__
+
+#ifndef __ASSEMBLY__
+
+struct s3c64xx_dmc {
+ unsigned intmemstat;
+ unsigned intmemcmd;
+ unsigned intdirectcmd;
+ unsigned intmemcfg;
+ unsigned intrefresh;
+ unsigned intcaslat;
+ unsigned intt_dqss;
+ unsigned intt_mrd;
+ unsigned intt_ras;
+ unsigned intt_rc;
+ unsigned intt_rcd;
+ unsigned intt_rfc;
+ unsigned intt_rp;
+ unsigned intt_rrd;
+ unsigned intt_wr;
+ unsigned intt_wtr;
+ unsigned intt_xp;
+ unsigned intt_xsr;
+ unsigned intt_esr;
+ unsigned intmemcfg2;
+#if defined(CONFIG_S3C6410)
+ unsigned intmemcfg3;
+ unsigned char res1[0xac];
+#else
+ unsigned char res1[0xb0];
+#endif
+ unsigned intid_0_cfg[16];
+ unsigned char res2[0xc0];
+ unsigned intchip_0_cfg;
+ unsigned intchip_1_cfg;
+ unsigned char res3[0xf8];
+ unsigned intuser_status;
+ unsigned intuser_config;
+};
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index 1da327a..45a8918 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -41,191 +41,18 @@
#include asm/hardware.h
#define ELFIN_CLOCK_POWER_BASE 0x7e00f000
-
-/*
- * GPIO
- */
#define ELFIN_GPIO_BASE0x7f008000
-
-/*
- * Bus Matrix
- */
#define ELFIN_MEM_SYS_CFG 0x7e00f120
-
-#define S3C64XX_MEM_SYS_CFG_16BIT (1 12)
-
-#define S3C64XX_MEM_SYS_CFG_NAND 0x0008
-
-/*
- * Memory controller
- */
#define ELFIN_SROM_BASE0x7000
-
-/*
- * SDRAM Controller
- */
#define ELFIN_DMC0_BASE0x7e00
#define ELFIN_DMC1_BASE0x7e001000
-
-#define INDEX_DMC_MEMC_STATUS 0x00
-#define INDEX_DMC_MEMC_CMD 0x04
-#define INDEX_DMC_DIRECT_CMD 0x08
-#define INDEX_DMC_MEMORY_CFG 0x0C
-#define INDEX_DMC_REFRESH_PRD 0x10
-#define INDEX_DMC_CAS_LATENCY 0x14
-#define INDEX_DMC_T_DQSS 0x18
-#define INDEX_DMC_T_MRD0x1C
-#define INDEX_DMC_T_RAS0x20
-#define INDEX_DMC_T_RC 0x24
-#define INDEX_DMC_T_RCD0x28
-#define INDEX_DMC_T_RFC0x2C
-#define INDEX_DMC_T_RP 0x30
-#define INDEX_DMC_T_RRD0x34
-#define INDEX_DMC_T_WR 0x38
-#define INDEX_DMC_T_WTR0x3C
-#define INDEX_DMC_T_XP 0x40
-#define INDEX_DMC_T_XSR0x44
-#define INDEX_DMC_T_ESR0x48
-#define INDEX_DMC_MEMORY_CFG2 0x4C
-#define INDEX_DMC_CHIP_0_CFG 0x200
-#define INDEX_DMC_CHIP_1_CFG 0x204
-#define INDEX_DMC_CHIP_2_CFG 0x208
-#define INDEX_DMC_CHIP_3_CFG 0x20C
-#define INDEX_DMC_USER_STATUS 0x300
-#define INDEX_DMC_USER_CONFIG 0x304
-
-/*
- * Memory Chip direct
[U-Boot] [PATCH 14/14] S3C6400: Remove the unused variable for S3C6400
From: Zhong Hongbo bocui...@gmail.com Signed-off-by: Zhong Hongbo bocui...@gmail.com --- Change for V4: - None. Change for V3: - None. Change for V2: - None. --- include/configs/smdk6400.h | 15 --- 1 files changed, 0 insertions(+), 15 deletions(-) diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index b770463..e005be1 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -108,9 +108,6 @@ #define CONFIG_CMD_LOADB #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_NAND -#if defined(CONFIG_BOOT_ONENAND) -#define CONFIG_CMD_ONENAND -#endif #define CONFIG_CMD_PING #define CONFIG_CMD_ELF #define CONFIG_CMD_FAT @@ -266,13 +263,6 @@ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63} -/* None of these are currently implemented. Left from the original Samsung - * version for reference -#define CONFIG_BOOT_NOR -#define CONFIG_BOOT_MOVINAND -#define CONFIG_BOOT_ONENAND -*/ - #define CONFIG_SPL #define CONFIG_SPL_NAND #define CONFIG_SPL_NAND_SIMPLE @@ -283,11 +273,6 @@ #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_NAND_S3C64XX -/* Unimplemented or unsupported. See comment above. -#define CONFIG_ONENAND -#define CONFIG_MOVINAND -*/ - /* Settings as above boot configuration */ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_BOOTARGSconsole=ttySAC,115200 -- 1.7.5.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 13/14] S3C64XX: Move s3c6400.h to cpu.h to support s3c6410 board
From: Zhong Hongbo bocui...@gmail.com Signed-off-by: Zhong Hongbo bocui...@gmail.com --- Change for V4: - None. Change for V3: - Replace ELFIN with S3C64XX for all the variable of cpu.h - Change __S3C6400_H__ into __CPU__H__ Change for V2: - New. --- arch/arm/cpu/arm1176/s3c64xx/pwm.c |2 +- arch/arm/cpu/arm1176/s3c64xx/reset.c|2 +- arch/arm/cpu/arm1176/s3c64xx/speed.c|2 +- arch/arm/cpu/arm1176/s3c64xx/srom.c |2 +- arch/arm/cpu/arm1176/s3c64xx/timer.c|2 +- arch/arm/include/asm/arch-s3c64xx/cpu.h | 89 +++ arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 89 --- board/samsung/smdk6400/dmc_init.c |2 +- board/samsung/smdk6400/lowlevel_init.S | 26 board/samsung/smdk6400/smdk6400.c |2 +- drivers/mtd/nand/s3c64xx.c |2 +- drivers/serial/s3c64xx.c|2 +- drivers/usb/host/s3c64xx-hcd.c |2 +- 13 files changed, 112 insertions(+), 112 deletions(-) create mode 100644 arch/arm/include/asm/arch-s3c64xx/cpu.h delete mode 100644 arch/arm/include/asm/arch-s3c64xx/s3c6400.h diff --git a/arch/arm/cpu/arm1176/s3c64xx/pwm.c b/arch/arm/cpu/arm1176/s3c64xx/pwm.c index fff2c68..534901a 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/pwm.c +++ b/arch/arm/cpu/arm1176/s3c64xx/pwm.c @@ -27,7 +27,7 @@ #include errno.h #include pwm.h #include asm/io.h -#include asm/arch/s3c6400.h +#include asm/arch/cpu.h #include asm/arch/pwm.h int pwm_enable(int pwm_id) diff --git a/arch/arm/cpu/arm1176/s3c64xx/reset.c b/arch/arm/cpu/arm1176/s3c64xx/reset.c index 773cffa..03cb306 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/reset.c +++ b/arch/arm/cpu/arm1176/s3c64xx/reset.c @@ -23,7 +23,7 @@ #include common.h #include asm/io.h -#include asm/arch/s3c6400.h +#include asm/arch/cpu.h #include asm/arch/clock.h void reset_cpu(ulong addr) diff --git a/arch/arm/cpu/arm1176/s3c64xx/speed.c b/arch/arm/cpu/arm1176/s3c64xx/speed.c index 05b44b9..5e68090 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/speed.c +++ b/arch/arm/cpu/arm1176/s3c64xx/speed.c @@ -32,7 +32,7 @@ #include common.h #include asm/io.h -#include asm/arch/s3c6400.h +#include asm/arch/cpu.h #include asm/arch/clock.h #define APLL 0 diff --git a/arch/arm/cpu/arm1176/s3c64xx/srom.c b/arch/arm/cpu/arm1176/s3c64xx/srom.c index f1b2b34..92fb7af 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/srom.c +++ b/arch/arm/cpu/arm1176/s3c64xx/srom.c @@ -25,7 +25,7 @@ #include common.h #include asm/io.h #include asm/arch/sromc.h -#include asm/arch/s3c6400.h +#include asm/arch/cpu.h /* * s3c64xx_config_sromc() - select the proper SROMC Bank and configure the * band width control and bank control registers diff --git a/arch/arm/cpu/arm1176/s3c64xx/timer.c b/arch/arm/cpu/arm1176/s3c64xx/timer.c index 47d7731..eebd0c0 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/timer.c +++ b/arch/arm/cpu/arm1176/s3c64xx/timer.c @@ -25,7 +25,7 @@ #include common.h #include asm/io.h -#include asm/arch/s3c6400.h +#include asm/arch/cpu.h #include asm/arch/pwm.h #include pwm.h diff --git a/arch/arm/include/asm/arch-s3c64xx/cpu.h b/arch/arm/include/asm/arch-s3c64xx/cpu.h new file mode 100644 index 000..90c5328 --- /dev/null +++ b/arch/arm/include/asm/arch-s3c64xx/cpu.h @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2007 + * Byungjae Lee, Samsung Erectronics, bj...@samsung.com. + * - only support for S3C6400 + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/ + * NAME: cpu.h + * + * Based on S3C6400 User's manual Rev 0.0 + / + +#ifndef __CPU_H__ +#define __CPU_H__ + +#if defined(CONFIG_SYNC_MODE) defined(CONFIG_S3C6400) +#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration! +#endif + +#define S3C64XX_UART_CHANNELS 3 +#define S3C64XX_SPI_CHANNELS 2 + +#include asm/hardware.h + +#define S3C64XX_CLOCK_POWER_BASE 0x7e00f000 +#define S3C64XX_GPIO_BASE 0x7f008000 +#define S3C64XX_MEM_SYS_CFG0x7e00f120 +#define S3C64XX_SROM_BASE
[U-Boot] [PATCH] powerpc/mpc85xx:Enable debugger support to missed e500v2 SoC
Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some restrictions on external debugging (JTAG). Need to define define CONFIG_SYS_PPC_E500_DEBUG_TLB to enable a temporary TLB entry to be used during boot to work around the limitations. Enable missed e500v2 SoC i.e. MPC8536, MPC8544, MPC8548 and MPC8572 for debug support. Signed-off-by: Radu Lazarescu radu.lazare...@freescale.com Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com Cc: Tang Yuantian yuantian.t...@freescale.com --- Based upon git://git.denx.de/u-boot.git (branch master) arch/powerpc/include/asm/config_mpc85xx.h |4 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index b6c44bb..dd69837 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -37,6 +37,7 @@ #if defined(CONFIG_MPC8536) #define CONFIG_MAX_CPUS1 #define CONFIG_SYS_FSL_NUM_LAWS12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70 @@ -54,12 +55,14 @@ #elif defined(CONFIG_MPC8544) #define CONFIG_MAX_CPUS1 #define CONFIG_SYS_FSL_NUM_LAWS10 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70 #elif defined(CONFIG_MPC8548) #define CONFIG_MAX_CPUS1 #define CONFIG_SYS_FSL_NUM_LAWS10 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 @@ -113,6 +116,7 @@ #elif defined(CONFIG_MPC8572) #define CONFIG_MAX_CPUS2 #define CONFIG_SYS_FSL_NUM_LAWS12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] powerpc/fsl-corenet: remove dead variant symbols
On Aug 14, 2012, at 4:45 PM, Scott Wood wrote: On 08/14/2012 04:31 PM, Kumar Gala wrote: On Aug 14, 2012, at 3:14 PM, Scott Wood wrote: These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood scottw...@freescale.com --- arch/powerpc/cpu/mpc85xx/Makefile |3 -- arch/powerpc/include/asm/config_mpc85xx.h | 68 ++--- arch/powerpc/include/asm/immap_85xx.h |2 +- drivers/net/fm/Makefile |1 - include/configs/P2041RDB.h|2 +- include/configs/P4080DS.h |1 + include/configs/P5020DS.h |2 +- 7 files changed, 7 insertions(+), 72 deletions(-) I had put these in for customer specific boards... Why wouldn't they use the p2041/p4080/p5020 symbol? The point is we support both at runtime. I understand we might have bit rot, but I guess I'd rather we added: P2040RDB, P4040DS, and P5010DS to boards.cfg to test these SoC builds than remove the code. I disagree. That adds extra builds to test and maintain for no real gain. It was an attempt to try and reduce some confusion for customers if they happen to utilize a P4040/P2040/P5010. We have the same issue with P1/P2 SoCs and single core vs dual core devices. - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/5] mpc iim: Switch to common fsl_iim
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com
Cc: Wolfgang Denk w...@denx.de
Cc: Stefano Babic sba...@denx.de
Adding missing board maintainers to Cc.
---
.../arch/powerpc/cpu/mpc512x/Makefile |1 -
.../arch/powerpc/cpu/mpc512x/iim.c = /dev/null| 394
.../board/davedenx/aria/aria.c |2 +-
.../board/esd/mecp5123/mecp5123.c |2 +-
.../board/freescale/mpc5121ads/mpc5121ads.c|2 +-
.../board/pdm360ng/pdm360ng.c |2 +-
.../include/configs/aria.h |2 +-
.../include/configs/mecp5123.h |2 +-
.../include/configs/mpc5121ads.h |2 +-
9 files changed, 7 insertions(+), 402 deletions(-)
delete mode 100644
u-boot-4d3c95f.orig/arch/powerpc/cpu/mpc512x/iim.c
diff --git u-boot-4d3c95f.orig/arch/powerpc/cpu/mpc512x/Makefile
u-boot-4d3c95f/arch/powerpc/cpu/mpc512x/Makefile
index b53232f..4f4c9ec 100644
--- u-boot-4d3c95f.orig/arch/powerpc/cpu/mpc512x/Makefile
+++ u-boot-4d3c95f/arch/powerpc/cpu/mpc512x/Makefile
@@ -38,7 +38,6 @@ COBJS-y += serial.o
COBJS-y += speed.o
COBJS-$(CONFIG_FSL_DIU_FB) += diu.o
COBJS-$(CONFIG_CMD_IDE) += ide.o
-COBJS-$(CONFIG_IIM) += iim.o
COBJS-$(CONFIG_PCI) += pci.o
# Stub implementations of cache management functions for USB
diff --git u-boot-4d3c95f.orig/arch/powerpc/cpu/mpc512x/iim.c
u-boot-4d3c95f.orig/arch/powerpc/cpu/mpc512x/iim.c
deleted file mode 100644
index abec8f6..000
--- u-boot-4d3c95f.orig/arch/powerpc/cpu/mpc512x/iim.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * Copyright 2008 Silicon Turnkey Express, Inc.
- * Martha Marx mm...@silicontkx.com
- *
- * ADS5121 IIM (Fusebox) Interface
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include common.h
-#include command.h
-#include asm/io.h
-
-#ifdef CONFIG_CMD_FUSE
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static char cur_bank = '1';
-
-char *iim_err_msg(u32 err)
-{
- static char *IIM_errs[] = {
- Parity Error in cache,
- Explicit Sense Cycle Error,
- Write to Locked Register Error,
- Read Protect Error,
- Override Protect Error,
- Write Protect Error};
-
- int i;
-
- if (!err)
- return ;
- for (i = 1; i 8; i++)
- if (err (1 i))
- printf(IIM - %s\n, IIM_errs[i-1]);
- return ;
-}
-
-int in_range(int n, int min, int max, char *err, char *usg)
-{
- if (n max || n min) {
- printf(err);
- printf(Usage:\n%s\n, usg);
- return 0;
- }
- return 1;
-}
-
-int ads5121_fuse_read(int bank, int fstart, int num)
-{
- iim512x_t *iim = ((immap_t *) CONFIG_SYS_IMMR)-iim;
- u32 *iim_fb, dummy;
- int f, ctr;
-
- out_be32(iim-err, in_be32(iim-err));
- if (bank == 0)
- iim_fb = (u32 *)(iim-fbac0);
- else
- iim_fb = (u32 *)(iim-fbac1);
-/* try a read to see if Read Protect is set */
- dummy = in_be32(iim_fb[0]);
- if (in_be32(iim-err) IIM_ERR_RPE) {
- printf(\tRead protect fuse is set\n);
- out_be32(iim-err, IIM_ERR_RPE);
- return 0;
- }
- printf(Reading Bank %d cache\n, bank);
- for (f = fstart, ctr = 0; num 0; ctr++, num--, f++) {
- if (ctr % 4 == 0)
- printf(F%2d:, f);
- printf(\t%#04x, (u8)(iim_fb[f]));
- if (ctr % 4 == 3)
- printf(\n);
- }
- if (ctr % 4 != 0)
- printf(\n);
-}
-
-int ads5121_fuse_override(int bank, int f, u8 val)
-{
- iim512x_t *iim = ((immap_t *) CONFIG_SYS_IMMR)-iim;
- u32 *iim_fb;
- u32 iim_stat;
- int i;
-
- out_be32(iim-err, in_be32(iim-err));
- if (bank == 0)
- iim_fb = (u32 *)(iim-fbac0);
- else
- iim_fb = (u32 *)(iim-fbac1);
-/* try a read to see if Read Protect is set */
- iim_stat = in_be32(iim_fb[0]);
- if (in_be32(iim-err) IIM_ERR_RPE) {
- printf(Read
Re: [U-Boot] [PATCH 4/4] mx5: Mark lowlevel_init board-specific code
The mx5 lowlevel_init.S contains board-specific code based on the reference design. Let's keep it since it avoids creating new lowlevel_init files and it may be used by many boards. But add a config to make it optional in order not to cause issues on boards not following this part of the reference design. Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com Cc: Stefano Babic sba...@denx.de Adding missing board maintainers to Cc. --- .../arch/arm/cpu/armv7/mx5/lowlevel_init.S |2 +- .../doc/README.imx5|5 + .../include/configs/efikamx.h |1 + .../include/configs/mx51evk.h |1 + .../include/configs/vision2.h |1 + 5 files changed, 9 insertions(+), 1 deletion(-) diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S index d0f75fa..b25b3a7 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -330,7 +330,7 @@ ENTRY(lowlevel_init) mov r10, lr mov r4, #0 /* Fix R4 to 0 */ -#if defined(CONFIG_MX51) +#if defined(CONFIG_SYS_MAIN_PWR_ON) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] orr r1, r1, #1 23 diff --git u-boot-4d3c95f.orig/doc/README.imx5 u-boot-4d3c95f/doc/README.imx5 index 938d3da..85d476f 100644 --- u-boot-4d3c95f.orig/doc/README.imx5 +++ u-boot-4d3c95f/doc/README.imx5 @@ -20,3 +20,8 @@ i.MX5x SoCs. mode), which causes the effect of this failure to be much lower (in terms of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. + +1.3 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup. +This option should be enabled for boards having a SYS_ON_OFF_CTL signal +connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the +reference designs. diff --git u-boot-4d3c95f.orig/include/configs/efikamx.h u-boot-4d3c95f/include/configs/efikamx.h index 143b0f0..792b51b 100644 --- u-boot-4d3c95f.orig/include/configs/efikamx.h +++ u-boot-4d3c95f/include/configs/efikamx.h @@ -270,5 +270,6 @@ #define CONFIG_SYS_DDR_CLKSEL0 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35145 +#define CONFIG_SYS_MAIN_PWR_ON #endif diff --git u-boot-4d3c95f.orig/include/configs/mx51evk.h u-boot-4d3c95f/include/configs/mx51evk.h index e975f54..6867f7b 100644 --- u-boot-4d3c95f.orig/include/configs/mx51evk.h +++ u-boot-4d3c95f/include/configs/mx51evk.h @@ -242,6 +242,7 @@ #define CONFIG_SYS_DDR_CLKSEL0 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 +#define CONFIG_SYS_MAIN_PWR_ON /*--- * FLASH and environment organization diff --git u-boot-4d3c95f.orig/include/configs/vision2.h u-boot-4d3c95f/include/configs/vision2.h index ed004a6..3ce4906 100644 --- u-boot-4d3c95f.orig/include/configs/vision2.h +++ u-boot-4d3c95f/include/configs/vision2.h @@ -203,6 +203,7 @@ /* 166 MHz DDR RAM */ #define CONFIG_SYS_DDR_CLKSEL0 #define CONFIG_SYS_CLKTL_CBCDR 0x19239100 +#define CONFIG_SYS_MAIN_PWR_ON #define CONFIG_SYS_NO_FLASH ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] mx5: Use default pin initializers
Use the newly created mx5 default pin initialization functions in mx5
board
files.
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com
Cc: Stefano Babic sba...@denx.de
Adding missing board maintainers to Cc.
---
.../board/efikamx/efikamx.c| 133
++--
.../board/freescale/mx51evk/mx51evk.c | 121
+-
.../board/ttcontrol/vision2/vision2.c | 72
+--
3 files changed, 15 insertions(+), 311 deletions(-)
diff --git u-boot-4d3c95f.orig/board/efikamx/efikamx.c
u-boot-4d3c95f/board/efikamx/efikamx.c
index e88b2ed..6810433 100644
--- u-boot-4d3c95f.orig/board/efikamx/efikamx.c
+++ u-boot-4d3c95f/board/efikamx/efikamx.c
@@ -143,38 +143,12 @@ int dram_init(void)
}
/*
- * UART configuration
- */
-static void setup_iomux_uart(void)
-{
- unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
- PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
-
- mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
- mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
-}
-
-/*
* SPI configuration
*/
#ifdef CONFIG_MXC_SPI
static void setup_iomux_spi(void)
{
- /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
- mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-
- /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1.
*/
- mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mx51_ecspi1_init_pins();
/* Configure SS0 as a GPIO */
mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
@@ -183,16 +157,6 @@ static void setup_iomux_spi(void)
/* Configure SS1 as a GPIO */
mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO);
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1);
-
- /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
- /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1.
*/
- mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
}
#else
static inline void setup_iomux_spi(void) { }
@@ -333,7 +297,12 @@ int board_mmc_init(bd_t *bis)
int ret;
uint32_t cd = efika_mmc_cd();
- /* SDHC1 is used on all revisions, setup control pins first */
+ /* SDHC1 is used on all revisions */
+
+ /* SDHC1 IOMUX */
+ mx51_esdhc1_init_pins();
+
+ /* SDHC1 Control lines IOMUX */
mxc_request_iomux(cd,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(cd,
@@ -354,65 +323,8 @@ int board_mmc_init(bd_t *bis)
/* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */
if (machine_is_efikasb() || (machine_is_efikamx()
(get_efika_rev() EFIKAMX_BOARD_REV_12))) {
- /* SDHC1 IOMUX */
- mxc_request_iomux(MX51_PIN_SD1_CMD,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
- PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_CLK,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
- PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
- PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
- PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA2,
Re: [U-Boot] [PATCH] mx31: Fix PDR0_CSI_PODF
The CSI PODF bit-field used by the previous code for the i.MX31 CCM
PDR0
register is actually composed of two bit-fields: one pre-divider and
one
post-divider. This patch fixes the CCM access macros and the code
using them
accordingly.
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com
Cc: Stefano Babic sba...@denx.de
Adding missing board maintainers to Cc.
---
.../arch/arm/include/asm/arch-mx31/imx-regs.h |6 --
.../board/freescale/mx31ads/lowlevel_init.S|4 ++--
.../board/hale/tt01/tt01.c |2 +-
.../board/imx31_phycore/lowlevel_init.S|2 +-
.../board/logicpd/imx31_litekit/lowlevel_init.S|2 +-
.../include/configs/mx31pdk.h | 10 +-
6 files changed, 14 insertions(+), 12 deletions(-)
diff --git
u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx31/imx-regs.h
u-boot-4d3c95f/arch/arm/include/asm/arch-mx31/imx-regs.h
index 7ddbbd6..6ec5fa7 100644
--- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -567,7 +567,8 @@ struct esdc_regs {
#define MX31_IIM_BASE_ADDR 0x5001C000
-#define PDR0_CSI_PODF(x) (((x) 0x1ff) 23)
+#define PDR0_CSI_PODF(x) (((x) 0x3f) 26)
+#define PDR0_CSI_PRDF(x) (((x) 0x7) 23)
#define PDR0_PER_PODF(x) (((x) 0x1f) 16)
#define PDR0_HSP_PODF(x) (((x) 0x7) 11)
#define PDR0_NFC_PODF(x) (((x) 0x7) 8)
@@ -580,7 +581,8 @@ struct esdc_regs {
#define PLL_MFI(x) (((x) 0xf) 10)
#define PLL_MFN(x) (((x) 0x3ff) 0)
-#define GET_PDR0_CSI_PODF(x) (((x) 23) 0x1ff)
+#define GET_PDR0_CSI_PODF(x) (((x) 26) 0x3f)
+#define GET_PDR0_CSI_PRDF(x) (((x) 23) 0x7)
#define GET_PDR0_PER_PODF(x) (((x) 16) 0x1f)
#define GET_PDR0_HSP_PODF(x) (((x) 11) 0x7)
#define GET_PDR0_NFC_PODF(x) (((x) 8) 0x7)
diff --git
u-boot-4d3c95f.orig/board/freescale/mx31ads/lowlevel_init.S
u-boot-4d3c95f/board/freescale/mx31ads/lowlevel_init.S
index 5c18bc1..2972065 100644
--- u-boot-4d3c95f.orig/board/freescale/mx31ads/lowlevel_init.S
+++ u-boot-4d3c95f/board/freescale/mx31ads/lowlevel_init.S
@@ -246,8 +246,8 @@ lowlevel_init:
/* COSR */
str r1, [r0, #0x1c]
- /* RedBoot sets 0x1ff, 7, 3, 5, 1, 3, 0 */
-/* REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) |
PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) |
PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
+ /* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */
+/* REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) |
PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) |
PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
/* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) |
PLL_MFN(0x23)*/
diff --git u-boot-4d3c95f.orig/board/hale/tt01/tt01.c
u-boot-4d3c95f/board/hale/tt01/tt01.c
index 02e75ed..143fcef 100644
--- u-boot-4d3c95f.orig/board/hale/tt01/tt01.c
+++ u-boot-4d3c95f/board/hale/tt01/tt01.c
@@ -52,7 +52,7 @@ static void board_setup_clocks(void)
writel((CCM_CCMR_SETUP | CCMR_MPE) ~CCMR_MDS, ccm-ccmr);
/* Set up clock to 532MHz */
- writel(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) |
+ writel(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) |
PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |
PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |
PDR0_MCU_PODF(0), ccm-pdr0);
diff --git u-boot-4d3c95f.orig/board/imx31_phycore/lowlevel_init.S
u-boot-4d3c95f/board/imx31_phycore/lowlevel_init.S
index c47137d..4dd78b6 100644
--- u-boot-4d3c95f.orig/board/imx31_phycore/lowlevel_init.S
+++ u-boot-4d3c95f/board/imx31_phycore/lowlevel_init.S
@@ -54,7 +54,7 @@ lowlevel_init:
REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) ~CCMR_MDS
- REG CCM_PDR0, PDR0_CSI_PODF(0xff1) | PDR0_PER_PODF(7) |
PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) |
PDR0_MAX_PODF(3) |PDR0_MCU_PODF(0)
+ REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) |
PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |
PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
diff --git
u-boot-4d3c95f.orig/board/logicpd/imx31_litekit/lowlevel_init.S
u-boot-4d3c95f/board/logicpd/imx31_litekit/lowlevel_init.S
index 95b0c08..0ce8905 100644
--- u-boot-4d3c95f.orig/board/logicpd/imx31_litekit/lowlevel_init.S
+++ u-boot-4d3c95f/board/logicpd/imx31_litekit/lowlevel_init.S
@@ -54,7 +54,7 @@ lowlevel_init:
REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) ~CCMR_MDS
- REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) |
PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) |
Re: [U-Boot] [PATCH] km/arm: set SPI NOR Flash default parameters
Hi Prafulla, On 08/14/2012 03:17 PM, Prafulla Wadaskar wrote: -Original Message- From: Valentin Longchamp [mailto:valentin.longch...@keymile.com] Sent: 14 August 2012 17:09 To: Prafulla Wadaskar Cc: u-boot@lists.denx.de; Valentin Longchamp; Holger Brunck Subject: [PATCH] km/arm: set SPI NOR Flash default parameters These parameters are used by the the sf probe command that are used by our update script and they therefore need to be set for all of our boards. The timing is the same as for the ENV SPI NOR Flash (since it's the same physical device) and takes the boco2 delay on the bus into What is boco2? Is it typo mistake? No typo mistake. It's the name of a chip developped at Keymile that is the the SPI bus as well. account. Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com cc: Holger Brunck holger.bru...@keymile.com --- include/configs/km/km_arm.h |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 2d573e4..055d946 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -57,6 +57,10 @@ #define CONFIG_CMD_SF #define CONFIG_SOFT_I2C /* I2C bit-banged */ +/* SPI NOR Flash default params, used by sf commands */ +#define CONFIG_SF_DEFAULT_SPEED 810 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 + #if defined CONFIG_KM_ENV_IS_IN_SPI_NOR #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 -- Regards... Prafulla . . . -- Valentin Longchamp Embedded Software Engineer Hardware and Chip Integration __ KEYMILE AG Schwarzenburgstr. 73 CH-3097 Liebefeld Phone +41 31 377 1318 Fax +41 31 377 1212 valentin.longch...@keymile.com www.keymile.com __ KEYMILE: A Specialist as a Partner ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] kw_spi: fix clock prescaler computation
Hi Prafulla, On 08/14/2012 03:15 PM, Prafulla Wadaskar wrote: -Original Message- From: Valentin Longchamp [mailto:valentin.longch...@keymile.com] Sent: 14 August 2012 15:02 To: Prafulla Wadaskar Cc: u-boot@lists.denx.de; Holger Brunck Subject: Re: [PATCH] kw_spi: fix clock prescaler computation Hi Prafulla, I haven't received feedback about this patch from you. Can I please kindly remind you about it since I am about to send patches that deal with SPI clk setting. Dear Valentin My bad :-( I am really sorry about this. I missed this patch. Please find my comments in lined. Thank you. On 06/29/2012 02:17 PM, Valentin Longchamp wrote: The computation was not correct with low clock values: setting a 1MHz clock would result in an overlap that would then configure a 25Mhz clock. This patch implements a correct computation method according to the kirkwood functionnal spec. table 629 (Serial Memory Interface Configuration Register). I think this is table 600 (ref: MV-S104860-00 Rev. E specs available on extranet) This is a cosmetic change. Otherwise I ack for this patch. Please kindly let me know, should I pull this patch or you will resend it with above change? Ok, I had taken rev. C of the document as a reference, I will resend the patch with the updated commit message. Valentin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] kw_spi: fix clock prescaler computation
The computation was not correct with low clock values: setting a 1MHz
clock would result in an overlap that would then configure a 25Mhz
clock.
This patch implements a correct computation method according to the
kirkwood functionnal spec. table 600 (Serial Memory Interface
Configuration Register).
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
cc: Holger Brunck holger.bru...@keymile.com
cc: Prafulla Wadaskar prafu...@marvell.com
---
changes for v2:
- table nb in commit message
arch/arm/include/asm/arch-kirkwood/spi.h |1 +
drivers/spi/kirkwood_spi.c |5 +++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-kirkwood/spi.h
b/arch/arm/include/asm/arch-kirkwood/spi.h
index 1d5043f..5a38dc5 100644
--- a/arch/arm/include/asm/arch-kirkwood/spi.h
+++ b/arch/arm/include/asm/arch-kirkwood/spi.h
@@ -38,6 +38,7 @@ struct kwspi_registers {
};
#define KWSPI_CLKPRESCL_MASK 0x1f
+#define KWSPI_CLKPRESCL_MIN0x12
#define KWSPI_CSN_ACT 1 /* Activates serial memory interface */
#define KWSPI_SMEMRDY (1 1) /* SerMem Data xfer ready */
#define KWSPI_IRQUNMASK1 /* unmask SPI interrupt */
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index ee14669..9b3f6a4 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -57,8 +57,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned
int cs,
writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, spireg-ctrl);
/* calculate spi clock prescaller using max_hz */
- data = ((CONFIG_SYS_TCLK / 2) / max_hz) KWSPI_CLKPRESCL_MASK;
- data |= 0x10;
+ data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
+ data = data KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
+ data = data KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
/* program spi clock prescaller using max_hz */
writel(KWSPI_ADRLEN_3BYTE | data, spireg-cfg);
--
1.7.1
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[U-Boot] [PATCH] powerpc/mpc85xx: Add IFC LAW target ID for FSL High-End SoC
Freescale's High-End SoC are going to have Integrated Flash controller
(IFC)'s support.
So add IFC LAW target ID support for High-End SoC or corenet SoC.
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Based upon git://git.denx.de/u-boot.git (branch master)
arch/powerpc/include/asm/fsl_law.h |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/include/asm/fsl_law.h
b/arch/powerpc/include/asm/fsl_law.h
index 13caffd..dc3985e 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -68,6 +68,7 @@ enum law_trgt_if {
LAW_TRGT_IF_QMAN = 0x3c,
};
#define LAW_TRGT_IF_DDRLAW_TRGT_IF_DDR_1
+#define LAW_TRGT_IF_IFCLAW_TRGT_IF_LBC
#else
enum law_trgt_if {
LAW_TRGT_IF_PCI = 0x00,
--
1.7.9.5
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Re: [U-Boot] usb_test_unit_ready called every block read - performance
Oh yeah, forgot about that...;)
I just downloaded the ext4 branch tarball and built it.
The test_unit_ready calls were still in there.
With or without those it took 0m 45s to load a ~150MB image.
In our original branch (2011.12), the test_unit_ready calls had more of an
impact. The stock 2011.12 u-boot image took 6m 22s to load the 150MB file.
Without test_unit_ready, it took 3m 15s. Without test_unit_ready and
wait_ms(5) in usb_stor_BBB_transport() it took 0m 16s.
In the ext4 branch, I removed test_unit_ready and the mdelay(5) call
from usb_stor_BBB_transport() function and was able to load the same file
in 0m 8s.
So, removing the mdelay(5) call is the biggest improvement. Removing both
is the best.
To recap:
with w/o w/o
TUR TUR TUR and 5ms wait
2011.12 6:25 3:15 0:16
ext40:45 0:45 0:08
Note: all these time include the 3-4 seconds it takes to do the usb start.
Regards,
-Steve
On Wed, Aug 15, 2012 at 10:19 AM, Jim Shimer mgi2...@motorola.com wrote:
Hi Marek,
I looked at the ext4 branch. It looks like he has the patch to remove the
usb_test_unit_ready() calls which were not needed. Actually those calls are
commented out on that branch:
#if 0
if (usb_test_unit_ready(srb, ss)) {
printf(Device NOT ready\n Request Sense returned %02X
%02X
%02X\n, srb-sense_buf[2], srb-sense_buf[12],
srb-sense_buf[13]);
return 0;
}
#endif
In the u-boot-usb.git, this code is removed so at some point there will be
a merge conflict.
Also the ext4 branch still has the mdelay(5) always being done in
usb_stor_BBB_transport() line 696 which we found to be the largest
performance killer.
Regards,
Jim
On Sun, Aug 12, 2012 at 7:54 PM, Marek Vasut ma...@denx.de wrote:
Dear Jim Shimer,
While tuning ext2load, we found that usb_test_unit_ready was being
called
every block read. We compared the usb block storage to the scsi block
storage cmd_scsi.c, and found that the scsi device was only calling its
scsi_setup_test_unit_ready() during scsi_can. It appears that
usb_test_unit_ready() really only needs to be called once during
usb_stor_scan(), via usb_stor_get_info(). Is there a particular reason
usb_test_unit_ready is called for every block read, or do you think its
ok
to only call during usb_stor_scan()? We're finding this speeds up
ext2load
quite a bit.
Jim, did we get anywhere on this one ? Can you try with the new ext4 code
in
Wolfgangs' u-boot-master/ext4 branch?
Regards,
Jim
Best regards,
Marek Vasut
--
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Motorola Mobility T3-12-HH72
900 Chelmsford Street
Lowell MA 08151
978-614-3550
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Re: [U-Boot] Please pull u-boot-staging/tr...@ti.com
On Tue, Aug 14, 2012 at 03:06:17AM +0200, Albert ARIBAUD wrote: Hi Albert, On Tue, 14 Aug 2012 02:04:15 +0200, Albert ARIBAUD (U-Boot) albert.u.b...@aribaud.net wrote: Hi Tom, On Fri, 10 Aug 2012 22:06:59 +0200, Wolfgang Denk w...@denx.de wrote: Dear Tom, In message 20120810161021.GG3306@bill-the-cat you wrote: To try and ease the backlog of ARM changes, I've taken the liberty of grabbing the Snowball and Raspberry Pi model B board support patches and putting them into the staging tree. Both of these series have been posted for some time and been reviewed. Wolfgang, if you would like to wait for Albert to pick up this request, that's fine. I just wanted to make sure the submitters weren't left waiting. Thanks! Thanks, highly appreciated. As this contains a lot of ARM, indeed I would like to wait for Albert's ACK or pulling (whichever he prefers). Best regards, Wolfgang Denk Applied to u-boot-arm/master, thanks! But I might hold this a little, as commit snowball: Adding architecture dependent initialisation 7e2b895eb5aa10890910eed8921d042d13b828c0 seems to play bad with my stock Ubuntu 12.04 GCC on u8500_href: uboot@lilith:~/src/u-boot-arm$ git checkout f917361b988f69ddc0dbe2bd2beb93b296065b70^ HEAD is now at 1b5d8d5... u8500: Moving prcmu to cpu directory uboot@lilith:~/src/u-boot-arm$ LANG=C ./MAKEALL u8500_href Configuring for u8500_href board... text data bss dec hex filename 1395844408 221728 365720 59498 ./u-boot - SUMMARY Boards compiled: 1 -- uboot@lilith:~/src/u-boot-arm$ git checkout f917361b988f69ddc0dbe2bd2beb93b296065b70 Previous HEAD position was 1b5d8d5... u8500: Moving prcmu to cpu directory HEAD is now at f917361... snowball: Adding architecture dependent initialisation uboot@lilith:~/src/u-boot-arm$ LANG=C ./MAKEALL u8500_href Configuring for u8500_href board... text data bss dec hex filename 1397444408 221696 365848 59518 ./u-boot u8500_href.c:45:0: warning: PRCMU_BASE redefined [enabled by default] /home/uboot/src/u-boot-arm/include/asm/arch/prcmu.h:30:0: note: this is the location of the previous definition - SUMMARY Boards compiled: 1 Boards with warnings but no errors: 1 ( u8500_href ) -- Granted, this is only a warning, but I'd like to see it fixed. I've taken Mathieu's updated patch and pushed the series again to u-boot-staging/tr...@ti.com. A git reset --hard a1cd53c6b6e2e7fbf4ffa20d3548646e4c94efe5 and then pull of my tree will get things back in shape. I've done a MAKEALL -s u8500 and it's fine now and I'm kicking off a -a arm. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] davinci: ea20: reorganisation LCD startup
On Fri, Aug 10, 2012 at 09:26:41AM +0200, Bastian Ruppert wrote: Signed-off-by: Bastian Ruppert bastian.rupp...@sewerin.de CC: Tom Rini tr...@ti.com CC: Stefano Babic sba...@denx.de For the series, I'm fine with the davinci side of the changes but want Anatolij and Stefano to ack as well before I pull into u-boot-ti, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/6] davinci: ea20: add some configs and default environmet variables
On 10/08/2012 09:26, Bastian Ruppert wrote:
Signed-off-by: Bastian Ruppert bastian.rupp...@sewerin.de
CC: Tom Rini tr...@ti.com
CC: Stefano Babic sba...@denx.de
---
include/configs/ea20.h | 106
++--
1 files changed, 66 insertions(+), 40 deletions(-)
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index f9a1462..373db74 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -30,6 +30,7 @@
#define CONFIG_USE_SPIFLASH
#define CONFIG_SYS_USE_NAND
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_DRIVER_TI_EMAC_RMII_NONEG
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_VIDEO
@@ -98,6 +99,7 @@
* Network Ethernet Configuration
*/
#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM 0
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
@@ -121,9 +123,11 @@
#define CONFIG_VIDEO_DA8XX
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_VIDEO_LOGO
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_CMD_BMP
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
@@ -197,6 +201,7 @@
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_NO_SUBPAGE
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
#undef CONFIG_SYS_NAND_HW_ECC
@@ -235,31 +240,39 @@
#define xstr(s) str(s)
#define str(s) #s
-
#define CONFIG_HOSTNAME ea20
-#define CONFIG_EXTRA_ENV_SETTINGS
\
+#define CONFIG_EXTRA_ENV_SETTINGS \
as=3\0\
- netdev=eth0\0 \
+ netdev=eth0\0 \
nfsargs=setenv bootargs root=/dev/nfs rw \
nfsroot=${serverip}:${rootpath}\0 \
rfsbargs=setenv bootargs root=/dev/nfs rw \
nfsroot=${serverip}:${rfsbpath}\0 \
- ramargs=setenv bootargs root=/dev/ram rw\0\
- mtdids=nand0=davinci_nand.0\0 \
- mtdparts=mtdparts=davinci_nand.0:8m(Settings),8m(aKernel),\
- 8m(bKernel),76m(aRootfs),76m(bRootfs),-(MassSD)\0 \
+ testrfsargs=setenv bootargs root=/dev/nfs rw \
+ nfsroot=${serverip}:${testrfspath}\0 \
+ ramargs=setenv bootargs root=/dev/ram rw initrd= \
+ 0x${ramdisk_addr_r},4M\0 \
+ mtdids=nand0=davinci_nand.0\0 \
+ serverip=192.168.5.249\0 \
+ ipaddr=192.168.5.248\0\
+ rootpath=/opt/eldk/arm\0 \
+ splashpos=230,180\0 \
+ testrfspath=/opt/eldk/test_arm\0 \
+ tempmac=setenv ethaddr 02:ea:20:ff:ff:ff\0\
nandargs=setenv bootargs rootfstype=ubifs ro chk_data_crc \
ubi.mtd=${as} root=ubi0:rootfs\0 \
+ nandrwargs=setenv bootargs rootfstype=ubifs rw chk_data_crc \
+ ubi.mtd=${as} root=ubi0:rootfs\0 \
addip_sta=setenv bootargs ${bootargs} \
ip=${ipaddr}:${serverip}:${gatewayip}:${netmask} \
:${hostname}:${netdev}:off panic=1\0 \
addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0 \
- addip=if test -n ${ipdyn};then run addip_dyn; \
+ addip=if test -n ${ipdyn};then run addip_dyn; \
else run addip_sta;fi\0 \
addmtd=setenv bootargs ${bootargs} ${mtdparts}\0 \
addtty=setenv bootargs ${bootargs}\
console=${consoledev},${baudrate}n8\0\
- addmisc=setenv bootargs ${bootargs} ${misc}\0 \
+ addmisc=setenv bootargs ${bootargs} ${misc}\0 \
addmem=setenv bootargs ${bootargs} mem=${memory}\0\
consoledev=ttyS0\0\
loadaddr=c014\0 \
@@ -267,44 +280,57 @@
kernel_addr_r=c070\0 \
hostname= xstr(CONFIG_HOSTNAME) \0 \
bootfile= xstr(CONFIG_HOSTNAME) /uImage\0
Re: [U-Boot] [PATCH 5/6] da850/omap-l138: davinci_emac: Suppress auto negotiation if needed
On 10/08/2012 09:26, Bastian Ruppert wrote:
From this commit id: b78375a806ed04eb22b963255cfdef8df702de47 auto
negotiation is enabled in RMII mode. Some boards based on da850 need
to suppress this procedure.
CC: Rajashekhara, Sudhakar sudhakar@ti.com
CC: Lad, Prabhakar prabhakar@ti.com
CC: Hadli, Manjunath manjunath.ha...@ti.com
CC: sba...@denx.de
CC: Tom Rini tr...@ti.com
Signed-off-by: Bastian Ruppert bastian.rupp...@sewerin.de
---
drivers/net/davinci_emac.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index b2516d1..fe988d7 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -897,7 +897,8 @@ int davinci_emac_initialize(void)
}
#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) \
- defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+ defined(CONFIG_MACH_DAVINCI_DA850_EVM) \
+ !defined(CONFIG_DRIVER_TI_EMAC_RMII_NONEG)
for (i = 0; i num_phy; i++) {
if (phy[i].is_phy_connected(i))
phy[i].auto_negotiate(i);
Acked-by: Stefano Babic sba...@denx.de
Best regards,
Stefano Babic
--
=
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Re: [U-Boot] [PATCH 1/6] davinci: ea20: reorganisation LCD startup
On 10/08/2012 09:26, Bastian Ruppert wrote:
Signed-off-by: Bastian Ruppert bastian.rupp...@sewerin.de
CC: Tom Rini tr...@ti.com
CC: Stefano Babic sba...@denx.de
---
board/davinci/ea20/ea20.c | 23 +++
1 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c
index 7e00040..69307e4 100644
--- a/board/davinci/ea20/ea20.c
+++ b/board/davinci/ea20/ea20.c
@@ -176,6 +176,9 @@ int board_early_init_f(void)
if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
return 1;
+ /* Set DISP_ON high to enable LCD output*/
+ gpio_direction_output(97, 1);
+
/* Set the RESETOUTn low */
gpio_direction_output(111, 0);
@@ -188,9 +191,6 @@ int board_early_init_f(void)
/* Set LCD_B_PWR low to power down LCD Backlight*/
gpio_direction_output(102, 0);
- /* Set DISP_ON low to disable LCD output*/
- gpio_direction_output(97, 0);
-
#ifndef CONFIG_USE_IRQ
irq_init();
#endif
@@ -250,11 +250,6 @@ int board_early_init_f(void)
writel(readl(davinci_syscfg_regs-mstpri[2]) 0x0fff,
davinci_syscfg_regs-mstpri[2]);
- /* Set LCD_B_PWR low to power up LCD Backlight*/
- gpio_set_value(102, 1);
-
- /* Set DISP_ON low to disable LCD output*/
- gpio_set_value(97, 1);
return 0;
}
@@ -276,6 +271,9 @@ int board_init(void)
int board_late_init(void)
{
+ unsigned char buf[2];
+ int ret;
+
/* PinMux for HALTEN */
if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0)
return 1;
@@ -285,6 +283,15 @@ int board_late_init(void)
setenv(stdout, serial);
+ /* Set fixed contrast settings for LCD via I2C potentiometer */
+ buf[0] = 0x00;
+ buf[1] = 0xd7;
+ ret = i2c_write(0x2e, 6, 1, buf, 2);
+ if (ret)
+ puts(\nContrast Settings FAILED\n);
+
+ /* Set LCD_B_PWR high to power up LCD Backlight*/
+ gpio_set_value(102, 1);
return 0;
}
#endif /* CONFIG_BOARD_LATE_INIT */
Acked-by: Stefano Babic sba...@denx.de
Best regards,
Stefano Babic
--
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Re: [U-Boot] [PATCH 2/6] davinci: ea20: the console is always set to the serial line
On 10/08/2012 09:26, Bastian Ruppert wrote: Do not allow to overwrite it when video is enabled. Signed-off-by: Bastian Ruppert bastian.rupp...@sewerin.de CC: Tom Rini tr...@ti.com CC: Stefano Babic sba...@denx.de --- Acked-by: Stefano Babic sba...@denx.de Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] lib, panic: don't call do_reset in SPL (debug).
On Tue, Aug 14, 2012 at 10:40:50PM +0200, Jeroen Hofstee wrote: Several omap boards won't build when DEBUG is defined, SPL build error: vsprintf.c:791: undefined reference to `do_reset', since SPL has no commands. Therefore don't call do_reset in SPL. SPL panic will end in an endless loop or call hang if CONFIG_PANIC_HANG is defined. cc: Tom Rini tr...@ti.com Signed-off-by: Jeroen Hofstee jhofs...@victronenergy.com OK, the problem I see with this is it forces a policy on everyone, even non-DEBUG cases. What I'd like to see, and I'll submit the patch, is to document that when debugging SPL one should also set CONFIG_PANIC_HANG as do_reset is often (but it could be defined!) undefined for SPL. -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] serial: Add Dragonfire serial driver
On Wed, Aug 15, 2012 at 3:17 AM, Michal Simek mon...@monstr.eu wrote:
On 08/14/2012 06:45 PM, Joe Hershberger wrote:
Hi Michal,
On Tue, Aug 14, 2012 at 11:38 AM, Michal Simek mon...@monstr.eu wrote:
On 08/14/2012 04:09 PM, Joe Hershberger wrote:
Hi Michal,
On Tue, Aug 14, 2012 at 6:42 AM, Michal Simek mon...@monstr.eu wrote:
The driver is used on Xilinx Zynq platform.
Signed-off-by: Michal Simek mon...@monstr.eu
---
drivers/serial/Makefile |1 +
drivers/serial/serial_**xpssuart.c | 218
++**
2 files changed, 219 insertions(+), 0 deletions(-)
create mode 100644 drivers/serial/serial_**xpssuart.c
I think this would be clearer if it was named serial_zynq.c
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 65d0f23..81350d0 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -56,6 +56,7 @@ COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
COBJS-$(CONFIG_XILINX_**UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
+COBJS-$(CONFIG_XPSS_SERIAL) += serial_xpssuart.o
Replace every reference to XPSS with ZYNQ.
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_**xpssuart.c
b/drivers/serial/serial_**xpssuart.c
new file mode 100644
index 000..3c6d838
--- /dev/null
+++ b/drivers/serial/serial_**xpssuart.c
@@ -0,0 +1,218 @@
+/*
+ * U-Boot driver for Xilinx Dragonfire UART.
Use the released name Zynq not the old codename Dragonfire.
ok.
+ *
+ * Copyright (C) 2012 Michal Simek mon...@monstr.eu
+ * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include watchdog.h
+#include asm/io.h
+#include serial.h
+
+#define XDFUART_SR_TXFULL 0x0010 /* TX FIFO full */
+#define XDFUART_SR_RXEMPTY 0x0002 /* RX FIFO empty */
Replace all references to XDFUART with ZYNQ_UART.
agree.
+
+#define XDFUART_CR_TX_EN 0x0010 /* TX enabled */
+#define XDFUART_CR_RX_EN 0x0004 /* RX enabled */
+#define XDFUART_CR_TXRST 0x0002 /* TX logic reset */
+#define XDFUART_CR_RXRST 0x0001 /* RX logic reset */
+
+#define XDFUART_MR_PARITY_NONE 0x0020 /* No parity mode */
+
+/* Some clock/baud constants */
+#define XDFUART_BDIV 15 /* Default/reset BDIV value */
+#define XDFUART_BASECLK3125000L /* master / (bdiv + 1) */
+
+struct xdfuart {
+ u32 control; /* Control Register [8:0] */
+ u32 mode; /* Mode Register [10:0] */
+ u32 reserved1[4];
+ u32 baud_rate_gen; /* Baud Rate Generator [15:0] */
+ u32 reserved2[4];
+ u32 channel_sts; /* Channel Status [11:0] */
+ u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */
+ u32 baud_rate_divider; /* Baud Rate Divider [7:0] */
+};
+
+static struct xdfuart *xdf_ports[4] = {
+#ifdef CONFIG_XPSS_SERIAL_BASEADDR0
+ [0] = (struct xdfuart *)CONFIG_XPSS_SERIAL_**BASEADDR0,
+#endif
+#ifdef CONFIG_XPSS_SERIAL_BASEADDR1
+ [1] = (struct xdfuart *)CONFIG_XPSS_SERIAL_**BASEADDR1,
+#endif
There are 2 UARTS in hard silicon.
My fault.
They should be supported with
their known base addresses (0xE000 and 0xE0001000) here without
pushing that into the config header.
I am not sure that hardcoding addresses here is the right thing to do.
The main reason is that none has tested option that hard IPs can be
also used from programmable logic. It means that this driver
could be possible to use from Microblaze with address translation.
No problem to setup these addresses in config file.
I accept that you can access these from microblaze, but I think that
will be the 1% use-case. You can make the base address overridable,
but use the ARM core address space by default and have them here
instead of copied to every config.
None has shown any table with use cases that why you can't say it will be
1% use-cases.
+ I don't think that hardcode IP address in generic driver is right way to
go.
For
Re: [U-Boot] usb_test_unit_ready called every block read - performance
Marek/Benoit, Thanks so much for integrating this. I like the way you reused the flags, and simplified the code. Regards, Jim On Tue, Aug 14, 2012 at 1:57 PM, Steve Heckman mgi2...@motorola.com wrote: Marek, That looks good to me. Jim? Thanks, Steve On Tue, Aug 14, 2012 at 1:50 PM, Marek Vasut ma...@denx.de wrote: Dear Jim Shimer, Hi Marek, Here's a patch. -Jim [...] I applied modified patch, please check u-boot-usb.git if you agree. btw please read http://www.denx.de/wiki/U-Boot/Patches Best regards, Marek Vasut -- *James H Shimer* Motorola Mobility T3-12-HH72 900 Chelmsford Street Lowell MA 08151 978-614-3550 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] usb_test_unit_ready called every block read - performance
Hi Marek,
I looked at the ext4 branch. It looks like he has the patch to remove the
usb_test_unit_ready() calls which were not needed. Actually those calls are
commented out on that branch:
#if 0
if (usb_test_unit_ready(srb, ss)) {
printf(Device NOT ready\n Request Sense returned %02X
%02X
%02X\n, srb-sense_buf[2], srb-sense_buf[12],
srb-sense_buf[13]);
return 0;
}
#endif
In the u-boot-usb.git, this code is removed so at some point there will be
a merge conflict.
Also the ext4 branch still has the mdelay(5) always being done in
usb_stor_BBB_transport() line 696 which we found to be the largest
performance killer.
Regards,
Jim
On Sun, Aug 12, 2012 at 7:54 PM, Marek Vasut ma...@denx.de wrote:
Dear Jim Shimer,
While tuning ext2load, we found that usb_test_unit_ready was being called
every block read. We compared the usb block storage to the scsi block
storage cmd_scsi.c, and found that the scsi device was only calling its
scsi_setup_test_unit_ready() during scsi_can. It appears that
usb_test_unit_ready() really only needs to be called once during
usb_stor_scan(), via usb_stor_get_info(). Is there a particular reason
usb_test_unit_ready is called for every block read, or do you think its
ok
to only call during usb_stor_scan()? We're finding this speeds up
ext2load
quite a bit.
Jim, did we get anywhere on this one ? Can you try with the new ext4 code
in
Wolfgangs' u-boot-master/ext4 branch?
Regards,
Jim
Best regards,
Marek Vasut
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Lowell MA 08151
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Re: [U-Boot] [PATCHv2 1/2] mpc85xx: Initial SP alignment is wrong.
On 08/15/2012 02:10 AM, Joakim Tjernlund wrote: Kumar Gala ga...@kernel.crashing.org wrote on 2012/08/14 23:28:45: On Jul 23, 2012, at 3:58 PM, Joakim Tjernlund wrote: PowerPC mandates SP to be 16 bytes aligned. Furthermore, a stack frame is added, pointing to the reset vector which may in the way when gdb is walking the stack because the reset vector may not accessible depending on emulator settings. Also use a temp register so gdb doesn't pick up intermediate values. Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se --- v2 - Address Scott Wood's comments arch/powerpc/cpu/mpc85xx/start.S | 16 +--- 1 files changed, 5 insertions(+), 11 deletions(-) Acked-by: Kumar Gala ga...@kernel.crashing.org Thanks Kumar Will you pick up? [PATCHv2 2/2] powerpc: Stack Pointer not properly aligned It is not 85xx specific but for all PowerPC I don't think Kumar has a U-Boot tree to pull it into. There's no general PPC custodian. Probably both patches should go via Andy. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] powerpc/fsl-corenet: remove dead variant symbols
On 08/15/2012 09:21 AM, Kumar Gala wrote: On Aug 14, 2012, at 4:45 PM, Scott Wood wrote: On 08/14/2012 04:31 PM, Kumar Gala wrote: On Aug 14, 2012, at 3:14 PM, Scott Wood wrote: These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood scottw...@freescale.com --- arch/powerpc/cpu/mpc85xx/Makefile |3 -- arch/powerpc/include/asm/config_mpc85xx.h | 68 ++--- arch/powerpc/include/asm/immap_85xx.h |2 +- drivers/net/fm/Makefile |1 - include/configs/P2041RDB.h|2 +- include/configs/P4080DS.h |1 + include/configs/P5020DS.h |2 +- 7 files changed, 7 insertions(+), 72 deletions(-) I had put these in for customer specific boards... Why wouldn't they use the p2041/p4080/p5020 symbol? The point is we support both at runtime. I understand we might have bit rot, but I guess I'd rather we added: P2040RDB, P4040DS, and P5010DS to boards.cfg to test these SoC builds than remove the code. I disagree. That adds extra builds to test and maintain for no real gain. It was an attempt to try and reduce some confusion for customers if they happen to utilize a P4040/P2040/P5010. Well, I did add comments saying this also supports foo. I think documentation is the way to deal with this, or maybe a target name alias mechanism if we're really having problems with customers unable to figure this out. If we do add separate builds I predict they will receive approximately zero test coverage beyond the occasional (now slightly slower) MAKEALL. We have the same issue with P1/P2 SoCs and single core vs dual core devices. I'd be happy to see those extra builds go away too. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] README.SPL: Add a small Debugging section
Signed-off-by: Tom Rini tr...@ti.com --- doc/README.SPL |7 +++ 1 file changed, 7 insertions(+) diff --git a/doc/README.SPL b/doc/README.SPL index e4a5ac3..bd375a0 100644 --- a/doc/README.SPL +++ b/doc/README.SPL @@ -78,3 +78,10 @@ an SPL CPU in boards.cfg as follows: This this case CPU will be set to normal_cpu during the main u-boot build and spl_cpu during the SPL build. + + +Debugging +- + +When building SPL with DEBUG set you may also need to set CONFIG_PANIC_HANG +as in most cases do_reset is not defined within SPL. -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 01/13] mxc nand: Merge mtd and spl register definitions
Hi Stefano, On 08/14/2012 04:29:04 PM, Benoît Thébaudeau wrote: Hi Stefano, On 14/08/2012 13:13, Benoît Thébaudeau wrote: Hi Stefano, Hi Benoît, We have currently only two boards supporting this mechanismus, using MX25 (karo tx25) and MX31. Both MX25 and MX31 have an internal RAM (128KB) that is is suitable for installing the SPL. Note that TI SOCs have less RAM available, and they support SPL. The available RAM size is not the issue. i.MX boards using nand_spl can use internal or external RAM. The issue comes from the i.MX ROM bootloader that only uses the NFC buffer. On i.MX31, that means max 2 kiB for SPL, and 4 kiB on i.MX25/35/51. What can be done on the latter if using internal boot (with DCD header) is to use at most one NF block (more is not possible because the i.MX bootloader goes back to serial mode if any bad block is found, and one of the 1st or 2nd block has to be good). We are both a little off-topic here, but because we are reading probably the same part of the manuals I would like to clear this point. OK. What you are saying is not exactly what I read from the manual - I checked it now in mx35, I will take a look also on the other ones. In 7.4.1.6 NAND Flash Boot Operation, I read: 1. On device power-on, the boot ROM copies the first 4 Kbytes of boot code from the NAND Flash to the NFC buffer. So this correspond to your statement - and DCD tables go into NFC buffer. DCD table must be smaller as 4KB, but this is always the case. Indeed. 2. ROM code checks the first 4 Kbytes of boot data copied in step 1 above. a) If no ECC error, then DCD is verified. – If DCD verification is successful, then the rest of the boot code image is copied to destination RAM (internal RAM or SDRAM) and secure boot is performed. I understand this part as the mx35 goes on to copy the whole image, depending on the size set into the header, to the address specified in the table itself. There is no limitation. Exactly in the same way it works on i.MX5 (I know, this does not mean nothing, but..) I think the limitation of 2KB or 4KB is not correct and is valid only for the DCD data. Do you agree ? No, it's way more complicated than that. First, there various boot modes available depending on the device for NAND: i.MX31: external only Note that internal NAND Flash boot is also mentioned in the RM, but without further details. FSL should be contacted to know more. But the RM refers to secure boot and HAB, so it's probably something close to the internal boot modes of i.MX25 and i.MX35. Anyway, it does not seem to be used by U-Boot i.MX31 boards. i.MX25 and i.MX35: internal or external i.MX51: internal only External means that the NFC buffer is filled from NAND and executed without any DCD or flash header. The limit is 2 kiB on i.MX31. On i.MX25 and i.MX35, it is not clear from the RMs if only a single NF page is read, or if the NFC buffer is fully filled (4 kiB). This is the use case for mx31pdk and tx25. The details about external NF boot are in the NFC chapter of the RMs. For i.MX31, it's perfectly clear: The whole 2-kiB NFC buffer is filled whether the NF pages are 512-B or 2-kiB. For i.MX25 and i.MX35, it's more difficult to find the details, but I interpret the RMs as meaning that the whole 4-kiB NFC buffer is filled whatever the NF page sizes. In both cases, the code is run from the NFC buffer, so that the SPL size cannot exceed 2 kiB for mx31pdk, and 4 kiB for tx25. Internal means that 4 kiB are read from NF. If this fails from the 1st block, it is retried with the 2nd block. If it fails again, boot is aborted. If it succeeds, DCD and Flash headers are checked and executed. The behavior of the ROM bootloader while loading the image indicated by the headers is not clear from the RMs in case of bad blocks, so I asked FSL support which told me that as soon as a bad block is found, the boot is aborted. This means that an SPL is required for NAND boot to be reliable, even with internal boot. This also means that this SPL can not be larger than a single block. Best regards, Benoît ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2]: arm: Provide lowlevel_init C function wrapper for v7
On Thu, Aug 09, 2012 at 09:01:54AM -0700, Tom Rini wrote: Hey all, As Allen Martin noted, on tegra platforms a bug is exposed when using certain toolchains that currently calls to lowlevel_init must be calls to another assembly function as the stack is not explicitly setup / saved and thus register corruption can occur. Over in TI-land Aneesh V wrote a lowlevel_init that sets up the stack and calls s_init which is a C function that does what lowlevel_init does on other platforms. The code is generic to at least v7, so this series moves it to arch/arm/cpu/armv7. The initial version of the code made use of LOW_LEVEL_SRAM_STACK as the stack to be setup. This define is essentially another name for CONFIG_SYS_INIT_SP_ADDR without taking GENERATED_GBL_DATA_SIZE into consideration. So we switch to that instead. Finally, Wolfgang question me as to if the stack really only needed the alignment that we had been giving it. To be safe, I grabbed the alignmnet that we do when setting up the initial stack for real and placed it into lowlevel_init as well. Tested on AM335x GP EVM and OMAP4 Pandaboard ES2. Converted tegra to use the new lowlevel_init wrapper and tested on seaboard. Verified it works with the previously failing CodeSourcery 2011.09-70 toolchain. I'll respin my tegra SPL series to depend on these. -Allen --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] omap4/5/am33xx: Make lowlevel_init available to all armv7 platforms
On Thu, Aug 09, 2012 at 09:01:55AM -0700, Tom Rini wrote: Make the lowlevel_init function that these platforms have which just sets up the stack and calls a C function available to all armv7 platforms. As part of this we change some of the macros that are used to be more clear. Previously (except for am335x evm) we had been setting CONFIG_SYS_INIT_SP_ADDR to a series of new defines that are equivalent to simply referencing NON_SECURE_SRAM_END. On am335x evm we should have been doing this initially and do now. Cc: Sricharan R r.sricha...@ti.com Signed-off-by: Tom Rini tr...@ti.com --- Tested-by: Allen Martin amar...@nvidia.com -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] armv7: Make lowlevel_init.S's lowlevel_init do ABI compatible stack
On Thu, Aug 09, 2012 at 09:01:56AM -0700, Tom Rini wrote: Make sure that when we setup the stack before calling s_init() we have the stack have 8-byte alignment for ABI compliance. Signed-off-by: Tom Rini tr...@ti.com --- Tested-by: Allen Martin amar...@nvidia.com -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] MX28: config: Allow different target generation in elftosb call
The elftosb call needs to use a target param specific for i.MX28. This
patch allow for later addition of i.MX233.
Signed-off-by: Otavio Salvador ota...@ossystems.com.br
---
Makefile |5 -
arch/arm/cpu/arm926ejs/mxs/{u-boot.bd = u-boot.bd.imx28} |0
2 files changed, 4 insertions(+), 1 deletion(-)
rename arch/arm/cpu/arm926ejs/mxs/{u-boot.bd = u-boot.bd.imx28} (100%)
diff --git a/Makefile b/Makefile
index f6471e2..5f11bb7 100644
--- a/Makefile
+++ b/Makefile
@@ -452,8 +452,11 @@ $(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin
$(obj)u-boot.bin
cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.bin \
$(obj)u-boot.ais
+# Specify the target for use in elftosb call
+ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
+
$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
- elftosb -zdf imx28 -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot.bd \
+ elftosb -zdf $(ELFTOSB_TARGET-y) -c
$(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot.bd.$(ELFTOSB_TARGET-y) \
-o $(obj)u-boot.sb
# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot.bd
b/arch/arm/cpu/arm926ejs/mxs/u-boot.bd.imx28
similarity index 100%
rename from arch/arm/cpu/arm926ejs/mxs/u-boot.bd
rename to arch/arm/cpu/arm926ejs/mxs/u-boot.bd.imx28
--
1.7.10.4
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[U-Boot] [PATCH 2/2] MX28: Move regs-base.h include after SoC type configuration
For i.MX233 addition the base registers need to be change so the SoC definition needs to be known before the header include. The following boards has been changed: * apx4devkit * m28evk * mx28evk * sc_sps_1 Signed-off-by: Otavio Salvador ota...@ossystems.com.br --- include/configs/apx4devkit.h |4 ++-- include/configs/m28evk.h |4 ++-- include/configs/mx28evk.h|5 +++-- include/configs/sc_sps_1.h |4 ++-- 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h index b5ae44f..af0b714 100644 --- a/include/configs/apx4devkit.h +++ b/include/configs/apx4devkit.h @@ -22,8 +22,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include asm/arch/regs-base.h - /* SoC configurations */ #define CONFIG_MX28/* i.MX28 SoC */ #define CONFIG_MXS_GPIO/* GPIO control */ @@ -32,6 +30,8 @@ #define MACH_TYPE_APX4DEVKIT 3712 #define CONFIG_MACH_TYPE MACH_TYPE_APX4DEVKIT +#include asm/arch/regs-base.h + #define CONFIG_SYS_NO_FLASH #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_CPU_INIT diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index b3ac316..91c6bb9 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -20,8 +20,6 @@ #ifndef __M28EVK_CONFIG_H__ #define __M28EVK_CONFIG_H__ -#include asm/arch/regs-base.h - /* * SoC configurations */ @@ -36,6 +34,8 @@ #defineCONFIG_MACH_TYPEMACH_TYPE_M28EVK +#include asm/arch/regs-base.h + #defineCONFIG_SYS_NO_FLASH #defineCONFIG_BOARD_EARLY_INIT_F #defineCONFIG_ARCH_MISC_INIT diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 4e70617..ac06caf 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -19,17 +19,18 @@ #ifndef __MX28EVK_CONFIG_H__ #define __MX28EVK_CONFIG_H__ -#include asm/arch/regs-base.h - /* * SoC configurations */ #define CONFIG_MX28/* i.MX28 SoC */ + #define CONFIG_MXS_GPIO/* GPIO control */ #define CONFIG_SYS_HZ 1000/* Ticks per second */ #define CONFIG_MACH_TYPE MACH_TYPE_MX28EVK +#include asm/arch/regs-base.h + #define CONFIG_SYS_NO_FLASH #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_MISC_INIT diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h index f0b6f2b..0ebdfb8 100644 --- a/include/configs/sc_sps_1.h +++ b/include/configs/sc_sps_1.h @@ -22,8 +22,6 @@ #ifndef __SC_SPS_1_H__ #define __SC_SPS_1_H__ -#include asm/arch/regs-base.h - /* * SoC configurations */ @@ -38,6 +36,8 @@ #define CONFIG_MACH_TYPE MACH_TYPE_SC_SPS_1 +#include asm/arch/regs-base.h + #define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_DCACHE_OFF -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] patman: Do not Cc addresses included in To list
In case an address is listed in the To list, those will be skipped on Cc list or user might end with a duplicated message. This fixes the case when a tag points to same address used as series destination thus avoiding duplicated sending. Signed-off-by: Otavio Salvador ota...@ossystems.com.br --- tools/patman/series.py |6 ++ 1 file changed, 6 insertions(+) diff --git a/tools/patman/series.py b/tools/patman/series.py index eda1e9b..c338ccb 100644 --- a/tools/patman/series.py +++ b/tools/patman/series.py @@ -114,6 +114,12 @@ class Series(dict): cc_list += gitutil.BuildEmailList(commit.tags) cc_list += gitutil.BuildEmailList(commit.cc_list) +# Remove items on To list +try: +map(cc_list.remove, gitutil.BuildEmailList(self.to)) +except ValueError: +pass + for email in cc_list: if email == None: email = col.Color(col.YELLOW, alias '%s' not found -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/1] iomux: move IOMUX_GPR13_xxx defines
Move mx6 specific defines to arch-mx6 directory. Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com --- arch/arm/include/asm/arch-mx6/iomux.h | 129 + arch/arm/include/asm/imx-common/iomux-v3.h| 111 - board/freescale/mx6qsabrelite/mx6qsabrelite.c |1 + 3 files changed, 130 insertions(+), 111 deletions(-) create mode 100644 arch/arm/include/asm/arch-mx6/iomux.h diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h new file mode 100644 index 000..a1255f9 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -0,0 +1,129 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_IOMUX_H__ +#define __ASM_ARCH_IOMUX_H__ +/* + * IOMUXC_GPR13 bit fields + */ +#define IOMUXC_GPR13_SDMA_STOP_REQ (130) +#define IOMUXC_GPR13_CAN2_STOP_REQ (129) +#define IOMUXC_GPR13_CAN1_STOP_REQ (128) +#define IOMUXC_GPR13_ENET_STOP_REQ (127) +#define IOMUXC_GPR13_SATA_PHY_8_MASK (724) +#define IOMUXC_GPR13_SATA_PHY_7_MASK (0x1f19) +#define IOMUXC_GPR13_SATA_PHY_6_SHIFT 16 +#define IOMUXC_GPR13_SATA_PHY_6_MASK (7IOMUXC_GPR13_SATA_PHY_6_SHIFT) +#define IOMUXC_GPR13_SATA_SPEED_MASK (115) +#define IOMUXC_GPR13_SATA_PHY_5_MASK (114) +#define IOMUXC_GPR13_SATA_PHY_4_MASK (711) +#define IOMUXC_GPR13_SATA_PHY_3_MASK (0x1f7) +#define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f2) +#define IOMUXC_GPR13_SATA_PHY_1_MASK (30) + +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0b00024) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (0b00124) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (0b01024) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (0b01124) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (0b10024) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (0b10124) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (0b11024) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (0b11124) + +#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0b119) +#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0b119) +#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0b1101019) +#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0b1001019) +#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0b1001019) +#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0b1101019) + +#define IOMUXC_GPR13_SATA_SPEED_1P5G (015) +#define IOMUXC_GPR13_SATA_SPEED_3G (115) + +#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED (014) +#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_ENABLED(114) + +#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_16_16 (011) +#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_14_16 (111) +#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16 (211) +#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_10_16 (311) +#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16(411) +#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16(511) + +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB(0b7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB(0b00017) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB(0b00107) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB(0b00117) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB(0b01007) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB(0b01017) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB(0b01107) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB(0b01117) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB(0b10007) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB(0b10017) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB(0b10107) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB(0b10117) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB(0b11007) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB(0b11017) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB(0b11107) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB(0b7) + +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0b02) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (0b12) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (0b000102) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (0b000112) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (0b001002) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (0b001012) +#define
[U-Boot] [PATCH V4 3/3] mx53evk: add boot_mode support
This allows a watchdog reset to start the ROM's
usb/serial downloader, or boot from an sdcard.
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
---
Compile tested only, I don't have a mx53evk.
---
board/freescale/mx53evk/mx53evk.c | 13 +
include/configs/mx53evk.h |3 +++
2 files changed, 16 insertions(+)
diff --git a/board/freescale/mx53evk/mx53evk.c
b/board/freescale/mx53evk/mx53evk.c
index 8a6e31d..7f50938 100644
--- a/board/freescale/mx53evk/mx53evk.c
+++ b/board/freescale/mx53evk/mx53evk.c
@@ -28,6 +28,7 @@
#include asm/arch/crm_regs.h
#include asm/arch/iomux.h
#include asm/errno.h
+#include asm/imx-common/boot_mode.h
#include netdev.h
#include i2c.h
#include mmc.h
@@ -367,11 +368,23 @@ int board_init(void)
return 0;
}
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {mmc0,MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
+ {mmc1,MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
+ {NULL, 0},
+};
+#endif
+
int board_late_init(void)
{
setup_i2c(1);
power_init();
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
return 0;
}
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index 67def93..bfb9706 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -89,6 +89,9 @@
#define CONFIG_CMD_NET
#define CONFIG_CMD_DATE
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
--
1.7.9.5
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[U-Boot] [PATCH V4 2/3] mx6qsabrelite: add boot_mode support
This allows a watchdog reset to start the ROM's
usb downloader, or boot from an sdcard.
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
---
board/freescale/mx6qsabrelite/mx6qsabrelite.c | 14 ++
include/configs/mx6qsabrelite.h |3 +++
2 files changed, 17 insertions(+)
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index a1e3acc..cb85597 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -30,6 +30,7 @@
#include asm/gpio.h
#include asm/imx-common/iomux-v3.h
#include asm/imx-common/mxc_i2c.h
+#include asm/imx-common/boot_mode.h
#include mmc.h
#include fsl_esdhc.h
#include micrel.h
@@ -488,10 +489,23 @@ static void preboot_keys(void)
}
#endif
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {mmc0,MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {mmc1,MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
int misc_init_r(void)
{
#ifdef CONFIG_PREBOOT
preboot_keys();
#endif
+
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
return 0;
}
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 0d376ba..782abc8 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -117,6 +117,9 @@
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
--
1.7.9.5
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[U-Boot] [PATCH V4 1/3] imx-common/cmd_bmode.c: add imx bmode (bootmode) command
This is useful for forcing the ROM's
usb downloader to activate upon a watchdog reset.
Or, you can boot from either SD Card.
Currently, support added for MX53 and MX6Q
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
Note: MX53 support untested.
---
v4: replaced some occurrances of reset s/reset/boot/ or s/reset/b/
renamed files
only bmode command now, added noreset argument.
add static keywords
---
arch/arm/cpu/armv7/imx-common/Makefile |1 +
arch/arm/cpu/armv7/imx-common/cmd_bmode.c | 119 +++
arch/arm/cpu/armv7/mx5/soc.c| 31 +++
arch/arm/cpu/armv7/mx6/soc.c| 36
arch/arm/include/asm/arch-mx5/imx-regs.h| 18
arch/arm/include/asm/arch-mx6/imx-regs.h| 21 +
arch/arm/include/asm/imx-common/boot_mode.h | 36
7 files changed, 262 insertions(+)
create mode 100644 arch/arm/cpu/armv7/imx-common/cmd_bmode.c
create mode 100644 arch/arm/include/asm/imx-common/boot_mode.h
diff --git a/arch/arm/cpu/armv7/imx-common/Makefile
b/arch/arm/cpu/armv7/imx-common/Makefile
index bf36be5..16fba8d 100644
--- a/arch/arm/cpu/armv7/imx-common/Makefile
+++ b/arch/arm/cpu/armv7/imx-common/Makefile
@@ -29,6 +29,7 @@ LIB = $(obj)libimx-common.o
COBJS-y= iomux-v3.o timer.o cpu.o speed.o
COBJS-$(CONFIG_I2C_MXC) += i2c.o
+COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
COBJS := $(sort $(COBJS-y))
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/imx-common/cmd_bmode.c
b/arch/arm/cpu/armv7/imx-common/cmd_bmode.c
new file mode 100644
index 000..02fe72e
--- /dev/null
+++ b/arch/arm/cpu/armv7/imx-common/cmd_bmode.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include common.h
+#include asm/errno.h
+#include asm/io.h
+#include asm/imx-common/boot_mode.h
+#include malloc.h
+
+static const struct boot_mode *modes[2];
+
+static const struct boot_mode *search_modes(char *arg)
+{
+ int i;
+
+ for (i = 0; i ARRAY_SIZE(modes); i++) {
+ const struct boot_mode *p = modes[i];
+ if (p) {
+ while (p-name) {
+ if (!strcmp(p-name, arg))
+ return p;
+ p++;
+ }
+ }
+ }
+ return NULL;
+}
+
+static int create_usage(char *dest)
+{
+ int i;
+ int size = 0;
+
+ for (i = 0; i ARRAY_SIZE(modes); i++) {
+ const struct boot_mode *p = modes[i];
+ if (p) {
+ while (p-name) {
+ int len = strlen(p-name);
+ if (dest) {
+ memcpy(dest, p-name, len);
+ dest += len;
+ *dest++ = '|';
+ }
+ size += len + 1;
+ p++;
+ }
+ }
+ }
+ if (dest)
+ memcpy(dest - 1, [noreset], 11); /* include trailing 0 */
+ size += 10;
+ return size;
+}
+
+static int do_boot_mode(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ const struct boot_mode *p;
+ int reset_requested = 1;
+
+ if (argc 2)
+ return CMD_RET_USAGE;
+ p = search_modes(argv[1]);
+ if (!p)
+ return CMD_RET_USAGE;
+ if (argc == 3) {
+ if (strcmp(argv[2], noreset))
+ return CMD_RET_USAGE;
+ reset_requested = 0;
+ }
+
+ boot_mode_apply(p-cfg_val);
+ if (reset_requested p-cfg_val)
+ do_reset(NULL, 0, 0, NULL);
+ return 0;
+}
+
+U_BOOT_CMD(
+ bmode, 3, 0, do_boot_mode,
+ NULL,
+ );
+
+void add_board_boot_modes(const struct boot_mode *p)
+{
+ int size;
+ char *dest;
+
+ if (__u_boot_cmd_bmode.usage) {
+ free(__u_boot_cmd_bmode.usage);
+ __u_boot_cmd_bmode.usage = NULL;
+
[U-Boot] [PATCH 3/3] mx6qsabrelite: set CONFIG_FEC_MXC_PHYMASK
Different ethernet jacks parts can result in the Micrel KSZ9021 getting a different phy address. Let's support all parts. Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com --- include/configs/mx6qsabrelite.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 782abc8..44b8c7f 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -99,7 +99,7 @@ #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPERGMII #define CONFIG_ETHPRIMEFEC -#define CONFIG_FEC_MXC_PHYADDR 6 +#define CONFIG_FEC_MXC_PHYMASK (0xf 4) /* scan phy 4,5,6,7 */ #define CONFIG_PHYLIB #define CONFIG_PHY_MICREL #define CONFIG_PHY_MICREL_KSZ9021 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] fec_mxc: use phy_connect_by_mask
Allow board config files to list a range
of possible phy addresses, in case the
exact phy address is not certain.
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
---
drivers/net/fec_mxc.c | 21 +++--
drivers/net/fec_mxc.h |3 ++-
2 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index fbfc842..4af4976 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -391,7 +391,7 @@ static void fec_eth_phy_config(struct eth_device *dev)
struct fec_priv *fec = (struct fec_priv *)dev-priv;
struct phy_device *phydev;
- phydev = phy_connect(fec-bus, fec-phy_id, dev,
+ phydev = phy_connect_by_mask(fec-bus, fec-phy_mask, dev,
PHY_INTERFACE_MODE_RGMII);
if (phydev) {
fec-phydev = phydev;
@@ -898,7 +898,8 @@ static int fec_recv(struct eth_device *dev)
return len;
}
-static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
+static int fec_probe(bd_t *bd, int dev_id, unsigned phy_mask,
+ uint32_t base_addr)
{
struct eth_device *edev;
struct fec_priv *fec;
@@ -958,8 +959,11 @@ static int fec_probe(bd_t *bd, int dev_id, int phy_id,
uint32_t base_addr)
sprintf(edev-name, FEC%i, dev_id);
fec-dev_id = dev_id;
}
- fec-phy_id = phy_id;
-
+#ifdef CONFIG_PHYLIB
+ fec-phy_mask = phy_mask;
+#else
+ fec-phy_id = ffs(phy_mask) - 1;
+#endif
bus = mdio_alloc();
if (!bus) {
printf(mdio_alloc failed\n);
@@ -1008,9 +1012,14 @@ err1:
int fecmxc_initialize(bd_t *bd)
{
int lout = 1;
+#ifdef CONFIG_FEC_MXC_PHYMASK
+ unsigned phy_mask = CONFIG_FEC_MXC_PHYMASK;
+#else
+ unsigned phy_mask = 1 CONFIG_FEC_MXC_PHYADDR;
+#endif
debug(eth_init: fec_probe(bd)\n);
- lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+ lout = fec_probe(bd, -1, phy_mask, IMX_FEC_BASE);
return lout;
}
@@ -1021,7 +1030,7 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int
phy_id, uint32_t addr)
int lout = 1;
debug(eth_init: fec_probe(bd, %i, %i) @ %08x\n, dev_id, phy_id, addr);
- lout = fec_probe(bd, dev_id, phy_id, addr);
+ lout = fec_probe(bd, dev_id, 1 phy_id, addr);
return lout;
}
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 852b2e0..a0f50af 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -268,11 +268,12 @@ struct fec_priv {
bd_t *bd;
uint8_t *tdb_ptr;
int dev_id;
- int phy_id;
struct mii_dev *bus;
#ifdef CONFIG_PHYLIB
+ int phy_mask;
struct phy_device *phydev;
#else
+ int phy_id;
int (*mii_postcall)(int);
#endif
};
--
1.7.9.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] phy: add phy_connect_by_mask
It is useful to be able to try a range of
possible phy addresses to connect.
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
---
drivers/net/phy/phy.c | 108 +++--
include/phy.h |2 +
2 files changed, 71 insertions(+), 39 deletions(-)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index baef60f..a22d2e0 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -31,6 +31,7 @@
#include miiphy.h
#include phy.h
#include errno.h
+#include linux/err.h
/* Generic PHY support and helper functions */
@@ -573,6 +574,61 @@ int get_phy_id(struct mii_dev *bus, int addr, int devad,
u32 *phy_id)
return 0;
}
+static struct phy_device *create_phy_by_mask(struct mii_dev *bus,
+ unsigned phy_mask, int devad, phy_interface_t interface)
+{
+ u32 phy_id = 0x;
+ while (phy_mask) {
+ int addr = ffs(phy_mask) - 1;
+ int r = get_phy_id(bus, addr, devad, phy_id);
+ if (r 0)
+ return ERR_PTR(r);
+ /* If the PHY ID is mostly f's, we didn't find anything */
+ if ((phy_id 0x1fff) != 0x1fff)
+ return phy_device_create(bus, addr, phy_id, interface);
+ phy_mask = ~(1 addr);
+ }
+ return NULL;
+}
+
+static struct phy_device *search_for_existing_phy(struct mii_dev *bus,
+ unsigned phy_mask, phy_interface_t interface)
+{
+ /* If we have one, return the existing device, with new interface */
+ while (phy_mask) {
+ int addr = ffs(phy_mask) - 1;
+ if (bus-phymap[addr]) {
+ bus-phymap[addr]-interface = interface;
+ return bus-phymap[addr];
+ }
+ phy_mask = ~(1 addr);
+ }
+ return NULL;
+}
+
+static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus,
+ unsigned phy_mask, phy_interface_t interface)
+{
+ int i;
+ struct phy_device *phydev;
+
+ phydev = search_for_existing_phy(bus, phy_mask, interface);
+ if (phydev)
+ return phydev;
+ /* Try Standard (ie Clause 22) access */
+ /* Otherwise we have to try Clause 45 */
+ for (i = 0; i 5; i++) {
+ phydev = create_phy_by_mask(bus, phy_mask,
+ i ? i : MDIO_DEVAD_NONE, interface);
+ if (IS_ERR(phydev))
+ return NULL;
+ if (phydev)
+ return phydev;
+ }
+ printf(Phy not found\n);
+ return phy_device_create(bus, ffs(phy_mask) - 1, 0x, interface);
+}
+
/**
* get_phy_device - reads the specified PHY device and returns its @phy_device
struct
* @bus: the target MII bus
@@ -584,38 +640,7 @@ int get_phy_id(struct mii_dev *bus, int addr, int devad,
u32 *phy_id)
struct phy_device *get_phy_device(struct mii_dev *bus, int addr,
phy_interface_t interface)
{
- u32 phy_id = 0x1fff;
- int i;
- int r;
-
- /* If we have one, return the existing device, with new interface */
- if (bus-phymap[addr]) {
- bus-phymap[addr]-interface = interface;
-
- return bus-phymap[addr];
- }
-
- /* Try Standard (ie Clause 22) access */
- r = get_phy_id(bus, addr, MDIO_DEVAD_NONE, phy_id);
- if (r)
- return NULL;
-
- /* If the PHY ID is mostly f's, we didn't find anything */
- if ((phy_id 0x1fff) != 0x1fff)
- return phy_device_create(bus, addr, phy_id, interface);
-
- /* Otherwise we have to try Clause 45 */
- for (i = 1; i 5; i++) {
- r = get_phy_id(bus, addr, i, phy_id);
- if (r)
- return NULL;
-
- /* If the phy_id is mostly Fs, there is no device there */
- if ((phy_id 0x1fff) != 0x1fff)
- break;
- }
-
- return phy_device_create(bus, addr, phy_id, interface);
+ return get_phy_device_by_mask(bus, 1 addr, interface);
}
int phy_reset(struct phy_device *phydev)
@@ -688,9 +713,8 @@ int miiphy_reset(const char *devname, unsigned char addr)
return phy_reset(phydev);
}
-struct phy_device *phy_connect(struct mii_dev *bus, int addr,
- struct eth_device *dev,
- phy_interface_t interface)
+struct phy_device *phy_connect_by_mask(struct mii_dev *bus, unsigned phy_mask,
+ struct eth_device *dev, phy_interface_t interface)
{
struct phy_device *phydev;
@@ -701,11 +725,11 @@ struct phy_device *phy_connect(struct mii_dev *bus, int
addr,
/* Wait 15ms to make sure the PHY has come out of hard reset */
udelay(15000);
- phydev = get_phy_device(bus, addr, interface);
+ phydev =
[U-Boot] [PATCH v8 03/15] tegra20: rename CONFIG_MACH_TEGRA_GENERIC
Rename CONFIG_MACH_TEGRA_GENERIC to the less confusing CONFIG_TEGRA. The meaning of the config options is now: CONFIG_TEGRA - Any tegra chip CONFIG_TEGRA20 - A tegra20 family chip CONFIG_TEGRA30 - A tegra30 family chip (not added yet) Signed-off-by: Allen Martin amar...@nvidia.com Acked-by: Stephen Warren swar...@wwwdotorg.org Tested-by: Thierry Reding thierry.red...@avionic-design.de Signed-off-by: Tom Warren twar...@nvidia.com --- include/configs/tegra20-common.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 91cf28c..769728b 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -38,7 +38,7 @@ */ #define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */ #define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */ -#define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */ +#define CONFIG_TEGRA /* which is a Tegra generic machine */ #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ #define CONFIG_SYS_CACHELINE_SIZE 32 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v8 00/15] split tegra20 arm7 code into separate SPL
This patch series fixes a long standing problem with the tegra20
u-boot build. Tegra20 contains an ARM7TDMI boot processor and a
Cortex A9 main processor. Prior to this patch series this was
accomplished by #ifdefing out any armv7 code from the early boot
sequence and creating a single binary that runs on both both the
ARM7TDMI and A9. This was very fragile as changes to compiler options
or any additions or rearranging of the early boot code could add
additional armv7 specific code causing it to fail on the ARM7TDMI.
This patch series pulls all the armv4t code out into a separate SPL
that does nothing more than initialize the A9 and transfer control to
it. The resultint SPL and armv7 u-boot are concatenated together into
a single image.
This patch series is also available from:
git://github.com/arm000/u-boot.git
branch: tegra-spl-v8
Changes:
v8:
- rebased to u-boot-tegra/master
- added changes to work with arm: Provide lowlevel_init C function
wrapper for v7
- Moved JTAG init in SPL to earlier
- fixed TEXT_BASE in SPL to use SPL TEXT_BASE not main u-boot
TEXT_BASE
- pad exception handlers in arm720t to 64 bytes with 0x12345678 to
match armv7
v7:
- rebased to u-boot-tegra/next
- added Acks and Tested-Bys
v6:
- changed combined SPL/u-boot target names to u-boot-dtb-tegra.bin
and u-boot-nodtb-tegra.bin
- fixed regression introduced in v5 that caused git bisect to fail to
build at one of the patches
- fix USE_PRIVATE_LIBGCC for SPL build and enable it
- fix libtegra20-common.so link so it works if building with out of
tree OBJDIR
v5:
- added missing mkdir rules in all tegra20 board Makefiles that
include common code and changed them to be unconditional
- make new u-boot-dtb-t2.bin rule default for tegra20 and copy
resulting binary over u-boot.bin
v4:
- rebased to u-boot-tegra/next
- reordered entire patch series to preserve git bisect, verified
build and boot at each patch
- merged patches that add SPL config defines and removes duplicate
code from u-boot init, these have to go in atomically to preserve
building at each patch
- fixed compiler warnings introduced
- fixed blank line at end of file on cpu.c
- renamed u-boot.t2 to u-boot-t2.bin
- cleaned up config.mk generation in mkconfig to make it more
readable
- added some text to clarify using arm720t code for arm7tdmi
- rearranged SPL memory map to make resulting SPL + u-boot image much
smaller
- removed separate PAD_TO define in favor of just using
CONFIG_SYS_TEXT_BASE
- moved warmboot_save_sdram_params() from dram_init() to board_init()
v3:
- git bisect still does not work across this series, I'm saving that
for the next revision, but I had enough changes that I wanted to get
this out for review
- expanded the tegra2 - tegra20 rename to include
functions/variables/
defines
- rebased to u-boot-tegra/next
- removed some extra -march=armv4t flags, kept armv4t flags on
warmboot_avp since it's special
- removed bashisms from mkconfig
- renamed CONFIG_MACH_TEGRA_GENERIC to CONFIG_TEGRA
- moved SPL overrides to tegra2-common-post.h
- changed SPL base address to 0x108000, u-boot goes to 0x208000
- moved warboot_save_sdram_params fix to separate patch
- remove USE_PRIVATE_LIBGCC from non SPL build
- expanded SPL support to all tegra20 boards, not just seaboard
v2:
- renamed tegra2 to tegra20 to match kernel and devicetree naming
policy
- pulled all SPL related config overrides to a separate file to clean
up ifdefs from seabard.h
- rebased to TOT u-boot/master and fixed a bug related to init
sequence changes between this patch series and new EMC code
- made u-boot.t2 target work even if CONFIG_OF is disabled
- added back USE_PRIVATE_LIBGCC
Allen Martin (15):
tegra20: rename tegra2 - tegra20
tegra20: move tegra20 SoC code to arch/arm/cpu/tegra20-common
tegra20: rename CONFIG_MACH_TEGRA_GENERIC
tegra20: tec: add tegra20-common-post.h
tegra20: make board mkdir commands unconditional
mkconfig: add support for SPL CPU
ARM: Fix arm720t SPL build
tegra20: remove timer_init from SPL build
ARM: add tegra20 support to arm720t
tegra20: add u-boot-*-tegra.bin targets
tegra20: move SDRAM param save to later in boot
tegra20: enable SPL for tegra20 boards
arm: enable libgcc build for SPL
spl: fix SPL build of private libgcc
tegra20: Remove armv4t build flags
MAINTAINERS| 18 +--
Makefile | 26
arch/arm/cpu/arm720t/cpu.c |2 +
arch/arm/cpu/arm720t/interrupts.c |5 +
arch/arm/cpu/arm720t/start.S | 25 +++-
arch/arm/cpu/{armv7 = arm720t/tegra20}/Makefile | 27 ++--
.../arch-tegra2 = cpu/arm720t/tegra20}/board.h| 11 +-
.../{armv7/tegra2 = arm720t/tegra20}/config.mk| 12 --
.../{armv7/tegra2/ap20.c = arm720t/tegra20/cpu.c} | 148 ++--
.../ap20.h = cpu/arm720t/tegra20/cpu.h} |
[U-Boot] [PATCH v8 04/15] tegra20: tec: add tegra20-common-post.h
Add tegra20-common-post.h to be consistent with other tegra20 boards. Signed-off-by: Allen Martin amar...@nvidia.com Acked-by: Thierry Reding thierry.red...@avionic-design.de Acked-by: Stephen Warren swar...@wwwdotorg.org Tested-by: Thierry Reding thierry.red...@avionic-design.de Signed-off-by: Tom Warren twar...@nvidia.com --- include/configs/tec.h |2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/tec.h b/include/configs/tec.h index 39400d9..9b3f88d 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -79,4 +79,6 @@ ext2load mmc 0 0x1700 /boot/uImage; \ bootm +#include tegra20-common-post.h + #endif /* __CONFIG_H */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v8 11/15] tegra20: move SDRAM param save to later in boot
Move warmboot_save_sdram_params() to later in the boot sequence. This code relies on devicetree to get the address of the memory controller and with upcoming changes for SPL boot it gets called early in the boot process when devicetree is not initialized yet. Signed-off-by: Allen Martin amar...@nvidia.com Acked-by: Stephen Warren swar...@wwwdotorg.org Tested-by: Thierry Reding thierry.red...@avionic-design.de Signed-off-by: Tom Warren twar...@nvidia.com --- arch/arm/cpu/tegra20-common/ap20.c |5 - board/nvidia/common/board.c|3 +++ 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/tegra20-common/ap20.c b/arch/arm/cpu/tegra20-common/ap20.c index 8b6afbc..6ff71e0 100644 --- a/arch/arm/cpu/tegra20-common/ap20.c +++ b/arch/arm/cpu/tegra20-common/ap20.c @@ -345,11 +345,6 @@ void init_pmc_scratch(void) /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ odmdata = get_odmdata(); writel(odmdata, pmc-pmc_scratch20); - -#ifdef CONFIG_TEGRA20_LP0 - /* save Sdram params to PMC 2, 4, and 24 for WB0 */ - warmboot_save_sdram_params(); -#endif } void tegra20_start(void) diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 6753f95..7ab2040 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -133,6 +133,9 @@ int board_init(void) #endif #ifdef CONFIG_TEGRA20_LP0 + /* save Sdram params to PMC 2, 4, and 24 for WB0 */ + warmboot_save_sdram_params(); + /* prepare the WB code to LP0 location */ warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); #endif -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v8 14/15] spl: fix SPL build of private libgcc
This fixes the SPL build to link with the SPL version of libgcc if USE_PRIVATE_LIBGCC is set to yes. Previously it was linking with the libgcc from the normal u-boot build because it gets set in PLATFORM_LIBS and passed down the to the SPL build. Signed-off-by: Allen Martin amar...@nvidia.com Acked-by: Stephen Warren swar...@wwwdotorg.org Tested-by: Thierry Reding thierry.red...@avionic-design.de Signed-off-by: Tom Warren twar...@nvidia.com --- spl/Makefile |6 ++ 1 file changed, 6 insertions(+) diff --git a/spl/Makefile b/spl/Makefile index d04d2f2..c82e9de 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -66,6 +66,12 @@ ifeq ($(SOC),tegra20) LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o endif +# Add GCC lib +ifeq ($(USE_PRIVATE_LIBGCC), yes) +PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o +PLATFORM_LIBS := $(filter-out %/libgcc.o, $(filter-out -lgcc, $(PLATFORM_LIBS))) $(PLATFORM_LIBGCC) +endif + START := $(addprefix $(SPLTREE)/,$(START)) LIBS := $(addprefix $(SPLTREE)/,$(sort $(LIBS-y))) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v8 08/15] tegra20: remove timer_init from SPL build
Don't use timer_init from tegra board.c. This comes out of arm720t
for the SPL build.
Signed-off-by: Allen Martin amar...@nvidia.com
Acked-by: Stephen Warren swar...@wwwdotorg.org
Tested-by: Thierry Reding thierry.red...@avionic-design.de
Signed-off-by: Tom Warren twar...@nvidia.com
---
board/nvidia/common/board.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index d1a7f3a..6753f95 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -49,6 +49,7 @@ const struct tegra20_sysinfo sysinfo = {
CONFIG_TEGRA20_BOARD_STRING
};
+#ifndef CONFIG_SPL_BUILD
/*
* Routine: timer_init
* Description: init the timestamp and lastinc value
@@ -57,6 +58,7 @@ int timer_init(void)
{
return 0;
}
+#endif
void __pin_mux_usb(void)
{
--
1.7.9.5
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[U-Boot] [PATCH v8 13/15] arm: enable libgcc build for SPL
Enable the building of private libgcc for SPL Signed-off-by: Allen Martin amar...@nvidia.com Acked-by: Stephen Warren swar...@wwwdotorg.org Tested-by: Thierry Reding thierry.red...@avionic-design.de Signed-off-by: Tom Warren twar...@nvidia.com --- arch/arm/lib/Makefile |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 39a9550..bd3b77f 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk LIB= $(obj)lib$(ARCH).o LIBGCC = $(obj)libgcc.o -ifndef CONFIG_SPL_BUILD GLSOBJS+= _ashldi3.o GLSOBJS+= _ashrdi3.o GLSOBJS+= _divsi3.o @@ -37,6 +36,7 @@ GLSOBJS += _umodsi3.o GLCOBJS+= div0.o +ifndef CONFIG_SPL_BUILD COBJS-y+= board.o COBJS-y+= bootm.o COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v8 07/15] ARM: Fix arm720t SPL build
Take a few SPL fixes from armv7 and apply them to arm720t: -Use dummy exception handlers for SPL build -Initialize relocation register r9 to 0 for the case of no relocation -ifdef out interrupt handler code Signed-off-by: Allen Martin amar...@nvidia.com Acked-by: Stephen Warren swar...@wwwdotorg.org Tested-by: Thierry Reding thierry.red...@avionic-design.de Signed-off-by: Tom Warren twar...@nvidia.com --- arch/arm/cpu/arm720t/start.S | 13 + 1 file changed, 13 insertions(+) diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 3b97e80..dc047b8 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -51,6 +51,15 @@ _start: breset ldr pc, _irq ldr pc, _fiq +#ifdef CONFIG_SPL_BUILD +_undefined_instruction: .word _undefined_instruction +_software_interrupt: .word _software_interrupt +_prefetch_abort: .word _prefetch_abort +_data_abort: .word _data_abort +_not_used: .word _not_used +_irq: .word _irq +_fiq: .word _fiq +#else _undefined_instruction: .word undefined_instruction _software_interrupt: .word software_interrupt _prefetch_abort: .word prefetch_abort @@ -58,6 +67,7 @@ _data_abort: .word data_abort _not_used: .word not_used _irq: .word irq _fiq: .word fiq +#endif /* CONFIG_SPL_BUILD */ .balignl 16,0xdeadbeef @@ -167,6 +177,7 @@ stack_setup: adr r0, _start cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ mov r1, r6 /* r1 - scratch for copy_loop */ ldr r3, _bss_start_ofs @@ -427,6 +438,7 @@ lock_loop: mov pc, lr +#ifndef CONFIG_SPL_BUILD /* * * @@ -589,6 +601,7 @@ fiq: bl do_fiq #endif +#endif /* CONFIG_SPL_BUILD */ #if defined(CONFIG_NETARM) .align 5 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v8 10/15] tegra20: add u-boot-*-tegra.bin targets
Add target for tegra20 u-boot image. This is a concatenation of tegra
spl and normal u-boot binaries. For non-devicetree builds this is
named u-boot-nodtb-tegra.bin for devicetree builds is named
u-boot-dtb-tegra.bin.
Signed-off-by: Allen Martin amar...@nvidia.com
Acked-by: Stephen Warren swar...@wwwdotorg.org
Tested-by: Thierry Reding thierry.red...@avionic-design.de
Signed-off-by: Tom Warren twar...@nvidia.com
---
Makefile | 14 ++
1 file changed, 14 insertions(+)
diff --git a/Makefile b/Makefile
index 08d58cf..001df10 100644
--- a/Makefile
+++ b/Makefile
@@ -475,6 +475,20 @@ $(obj)u-boot.spr: $(obj)u-boot.img
$(obj)spl/u-boot-spl.bin
conv=notrunc 2/dev/null
cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img $@
+ifeq ($(SOC),tegra20)
+ifeq ($(CONFIG_OF_SEPARATE),y)
+$(obj)u-boot-dtb-tegra.bin:$(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(obj)u-boot.dtb
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O
binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
+ cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin
$(obj)u-boot.dtb $@
+ rm $(obj)spl/u-boot-spl-pad.bin
+else
+$(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O
binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
+ cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $@
+ rm $(obj)spl/u-boot-spl-pad.bin
+endif
+endif
+
ifeq ($(CONFIG_SANDBOX),y)
GEN_UBOOT = \
cd $(LNDIR) $(CC) $(SYMS) -T $(obj)u-boot.lds \
--
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[U-Boot] [PATCH v8 06/15] mkconfig: add support for SPL CPU
Add support for specifying a different CPU for main u-boot and SPL
u-boot builds. This is done by adding an optional SPL CPU after the
main CPU in boards.cfg as follows:
normal_cpu:spl_cpu
This this case CPU will be set to normal_cpu during the main u-boot
build and spl_cpu during the SPL build.
Signed-off-by: Allen Martin amar...@nvidia.com
Acked-by: Stephen Warren swar...@wwwdotorg.org
Tested-by: Thierry Reding thierry.red...@avionic-design.de
Signed-off-by: Tom Warren twar...@nvidia.com
---
boards.cfg |5 +
doc/README.SPL | 12
mkconfig | 25 +
3 files changed, 34 insertions(+), 8 deletions(-)
diff --git a/boards.cfg b/boards.cfg
index 32ba7ae..0377350 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -11,6 +11,11 @@
# Lines starting with '#' are comments.
# Blank lines are ignored.
#
+# The CPU field takes the form:
+# cpu[:spl_cpu]
+# If spl_cpu is specified the make variable CPU will be set to this
+# during the SPL build.
+#
# The options field takes the form:
# board config name[:comma separated config options]
# Each config option has the form (value defaults to 1):
diff --git a/doc/README.SPL b/doc/README.SPL
index 0276953..e4a5ac3 100644
--- a/doc/README.SPL
+++ b/doc/README.SPL
@@ -66,3 +66,15 @@ CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o)
CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o)
CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o)
CONFIG_SPL_SPI_LOAD (drivers/mtd/spi/spi_spl_load.o)
+
+
+Normally CPU is assumed to be the same between the SPL and normal
+u-boot build. However it is possible to specify a different CPU for
+the SPL build for cases where the SPL is expected to run on a
+different CPU model from the main u-boot. This is done by specifying
+an SPL CPU in boards.cfg as follows:
+
+ normal_cpu:spl_cpu
+
+This this case CPU will be set to normal_cpu during the main u-boot
+build and spl_cpu during the SPL build.
diff --git a/mkconfig b/mkconfig
index 801f921..d3363c6 100755
--- a/mkconfig
+++ b/mkconfig
@@ -59,7 +59,8 @@ CONFIG_NAME=${1%_config}
[ ${BOARD_NAME} ] || BOARD_NAME=${1%_config}
arch=$2
-cpu=$3
+cpu=`echo $3 | awk 'BEGIN {FS = :} ; {print $1}'`
+spl_cpu=`echo $3 | awk 'BEGIN {FS = :} ; {print $2}'`
if [ $4 = - ] ; then
board=${BOARD_NAME}
else
@@ -130,13 +131,21 @@ fi
#
# Create include file for Make
#
-echo ARCH = ${arch}config.mk
-echo CPU= ${cpu}config.mk
-echo BOARD = ${board} config.mk
-
-[ ${vendor} ] echo VENDOR = ${vendor} config.mk
-
-[ ${soc}] echo SOC= ${soc} config.mk
+( echo ARCH = ${arch}
+if [ ! -z $spl_cpu ] ; then
+ echo 'ifeq ($(CONFIG_SPL_BUILD),y)'
+ echo CPU= ${spl_cpu}
+ echo else
+ echo CPU= ${cpu}
+ echo endif
+else
+ echo CPU= ${cpu}
+fi
+echo BOARD = ${board}
+
+[ ${vendor} ] echo VENDOR = ${vendor}
+[ ${soc}] echo SOC= ${soc}
+exit 0 ) config.mk
# Assign board directory to BOARDIR variable
if [ -z ${vendor} ] ; then
--
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[U-Boot] [PATCH v8 02/15] tegra20: move tegra20 SoC code to arch/arm/cpu/tegra20-common
In preparation for splitting out the armv4t code from tegra20, move
the tegra20 SoC code to arch/arm/cpu/tegra20-common. This code will
be compiled armv4t for the arm7tdmi and armv7 for the cortex A9.
Signed-off-by: Allen Martin amar...@nvidia.com
Acked-by: Stephen Warren swar...@wwwdotorg.org
Tested-by: Thierry Reding thierry.red...@avionic-design.de
Signed-off-by: Tom Warren twar...@nvidia.com
---
Makefile |3 ++
arch/arm/cpu/armv7/tegra20/Makefile| 15 ++
.../cpu/{armv7/tegra20 = tegra20-common}/Makefile | 31 +---
.../cpu/{armv7/tegra20 = tegra20-common}/ap20.c |0
.../cpu/{armv7/tegra20 = tegra20-common}/board.c |0
.../cpu/{armv7/tegra20 = tegra20-common}/clock.c |0
.../cpu/{armv7/tegra20 = tegra20-common}/crypto.c |0
.../cpu/{armv7/tegra20 = tegra20-common}/crypto.h |0
.../cpu/{armv7/tegra20 = tegra20-common}/emc.c|0
.../{armv7/tegra20 = tegra20-common}/funcmux.c|0
.../tegra20 = tegra20-common}/lowlevel_init.S |0
.../cpu/{armv7/tegra20 = tegra20-common}/pinmux.c |0
.../cpu/{armv7/tegra20 = tegra20-common}/pmu.c|0
.../{armv7/tegra20 = tegra20-common}/sys_info.c |0
.../cpu/{armv7/tegra20 = tegra20-common}/timer.c |0
.../{armv7/tegra20 = tegra20-common}/warmboot.c |0
.../tegra20 = tegra20-common}/warmboot_avp.c |0
.../tegra20 = tegra20-common}/warmboot_avp.h |0
spl/Makefile |4 +++
19 files changed, 23 insertions(+), 30 deletions(-)
copy arch/arm/cpu/{armv7/tegra20 = tegra20-common}/Makefile (66%)
rename arch/arm/cpu/{armv7/tegra20 = tegra20-common}/ap20.c (100%)
rename arch/arm/cpu/{armv7/tegra20 = tegra20-common}/board.c (100%)
rename arch/arm/cpu/{armv7/tegra20 = tegra20-common}/clock.c (100%)
rename arch/arm/cpu/{armv7/tegra20 = tegra20-common}/crypto.c (100%)
rename arch/arm/cpu/{armv7/tegra20 = tegra20-common}/crypto.h (100%)
rename arch/arm/cpu/{armv7/tegra20 = tegra20-common}/emc.c (100%)
rename arch/arm/cpu/{armv7/tegra20 = tegra20-common}/funcmux.c (100%)
rename arch/arm/cpu/{armv7/tegra20 = tegra20-common}/lowlevel_init.S (100%)
rename arch/arm/cpu/{armv7/tegra20 = tegra20-common}/pinmux.c (100%)
rename arch/arm/cpu/{armv7/tegra20 = tegra20-common}/pmu.c (100%)
rename arch/arm/cpu/{armv7/tegra20 = tegra20-common}/sys_info.c (100%)
rename arch/arm/cpu/{armv7/tegra20 = tegra20-common}/timer.c (100%)
rename arch/arm/cpu/{armv7/tegra20 = tegra20-common}/warmboot.c (100%)
rename arch/arm/cpu/{armv7/tegra20 = tegra20-common}/warmboot_avp.c (100%)
rename arch/arm/cpu/{armv7/tegra20 = tegra20-common}/warmboot_avp.h (100%)
diff --git a/Makefile b/Makefile
index f6471e2..08d58cf 100644
--- a/Makefile
+++ b/Makefile
@@ -322,6 +322,9 @@ endif
ifeq ($(SOC),exynos)
LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
endif
+ifeq ($(SOC),tegra20)
+LIBS += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
+endif
LIBS := $(addprefix $(obj),$(sort $(LIBS)))
.PHONY : $(LIBS)
diff --git a/arch/arm/cpu/armv7/tegra20/Makefile
b/arch/arm/cpu/armv7/tegra20/Makefile
index da62646..5f4035d 100644
--- a/arch/arm/cpu/armv7/tegra20/Makefile
+++ b/arch/arm/cpu/armv7/tegra20/Makefile
@@ -23,27 +23,16 @@
# MA 02111-1307 USA
#
-# The AVP is ARMv4T architecture so we must use special compiler
-# flags for any startup files it might use.
-CFLAGS_arch/arm/cpu/armv7/tegra20/ap20.o += -march=armv4t
-CFLAGS_arch/arm/cpu/armv7/tegra20/clock.o += -march=armv4t
-CFLAGS_arch/arm/cpu/armv7/tegra20/warmboot_avp.o += -march=armv4t
-
include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
-SOBJS := lowlevel_init.o
-COBJS-y:= ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
-COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
-COBJS-$(CONFIG_TEGRA_PMU) += pmu.o
COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
-COBJS-$(CONFIG_TEGRA20_LP0) += crypto.o warmboot.o warmboot_avp.o
COBJS-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
COBJS := $(COBJS-y)
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
all:$(obj).depend $(LIB)
diff --git a/arch/arm/cpu/armv7/tegra20/Makefile
b/arch/arm/cpu/tegra20-common/Makefile
similarity index 66%
copy from arch/arm/cpu/armv7/tegra20/Makefile
copy to arch/arm/cpu/tegra20-common/Makefile
index da62646..60be2a6 100644
--- a/arch/arm/cpu/armv7/tegra20/Makefile
+++ b/arch/arm/cpu/tegra20-common/Makefile
@@ -1,7 +1,7 @@
#
# (C) Copyright 2010,2011 Nvidia Corporation.
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -14,7 +14,7 @@
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS
[U-Boot] [PATCH v8 15/15] tegra20: Remove armv4t build flags
These flags were necessary when building tegra20 as a single binary that supported ARM7TDMI and Cortex A9. Now that the ARM7TDMI support is split into a separate SPL, this is no longer necessary. Signed-off-by: Allen Martin amar...@nvidia.com Acked-by: Stephen Warren swar...@wwwdotorg.org Tested-by: Thierry Reding thierry.red...@avionic-design.de Signed-off-by: Tom Warren twar...@nvidia.com --- arch/arm/cpu/armv7/tegra20/config.mk | 12 arch/arm/cpu/tegra20-common/Makefile |2 -- 2 files changed, 14 deletions(-) diff --git a/arch/arm/cpu/armv7/tegra20/config.mk b/arch/arm/cpu/armv7/tegra20/config.mk index 714daaf..6432e75 100644 --- a/arch/arm/cpu/armv7/tegra20/config.mk +++ b/arch/arm/cpu/armv7/tegra20/config.mk @@ -23,16 +23,4 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # - -# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build these -# files with compatible flags -ifdef CONFIG_TEGRA20 -CFLAGS_arch/arm/lib/board.o += -march=armv4t -CFLAGS_arch/arm/lib/memset.o += -march=armv4t -CFLAGS_lib/string.o += -march=armv4t -CFLAGS_common/cmd_nvedit.o += -march=armv4t -endif - -USE_PRIVATE_LIBGCC = yes - CONFIG_ARCH_DEVICE_TREE := tegra20 diff --git a/arch/arm/cpu/tegra20-common/Makefile b/arch/arm/cpu/tegra20-common/Makefile index 60be2a6..43c96c6 100644 --- a/arch/arm/cpu/tegra20-common/Makefile +++ b/arch/arm/cpu/tegra20-common/Makefile @@ -27,8 +27,6 @@ include $(TOPDIR)/config.mk # The AVP is ARMv4T architecture so we must use special compiler # flags for any startup files it might use. -CFLAGS_arch/arm/cpu/tegra20-common/ap20.o += -march=armv4t -CFLAGS_arch/arm/cpu/tegra20-common/clock.o += -march=armv4t CFLAGS_arch/arm/cpu/tegra20-common/warmboot_avp.o += -march=armv4t LIB= $(obj)lib$(SOC)-common.o -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v8 05/15] tegra20: make board mkdir commands unconditional
Change the mkdir commands for the object directories to be unconditional. This fixes an issue when building for SPL where SRCTREE and OBJTREE are the same, but $(obj) is under SPLTREE. Signed-off-by: Allen Martin amar...@nvidia.com Acked-by: Stephen Warren swar...@wwwdotorg.org Tested-by: Thierry Reding thierry.red...@avionic-design.de Signed-off-by: Tom Warren twar...@nvidia.com --- board/avionic-design/medcom/Makefile |2 -- board/avionic-design/plutux/Makefile |2 -- board/avionic-design/tec/Makefile|2 -- board/compal/paz00/Makefile |2 -- board/compulab/trimslice/Makefile|2 -- 5 files changed, 10 deletions(-) diff --git a/board/avionic-design/medcom/Makefile b/board/avionic-design/medcom/Makefile index d96d043..864bc0e 100644 --- a/board/avionic-design/medcom/Makefile +++ b/board/avionic-design/medcom/Makefile @@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) $(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) -endif LIB= $(obj)lib$(BOARD).o diff --git a/board/avionic-design/plutux/Makefile b/board/avionic-design/plutux/Makefile index d96d043..864bc0e 100644 --- a/board/avionic-design/plutux/Makefile +++ b/board/avionic-design/plutux/Makefile @@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) $(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) -endif LIB= $(obj)lib$(BOARD).o diff --git a/board/avionic-design/tec/Makefile b/board/avionic-design/tec/Makefile index d96d043..864bc0e 100644 --- a/board/avionic-design/tec/Makefile +++ b/board/avionic-design/tec/Makefile @@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) $(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) -endif LIB= $(obj)lib$(BOARD).o diff --git a/board/compal/paz00/Makefile b/board/compal/paz00/Makefile index 488e381..7f7287e 100644 --- a/board/compal/paz00/Makefile +++ b/board/compal/paz00/Makefile @@ -16,9 +16,7 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) $(shell mkdir -p $(obj)../../nvidia/common) -endif LIB= $(obj)lib$(BOARD).o diff --git a/board/compulab/trimslice/Makefile b/board/compulab/trimslice/Makefile index bf624f4..ff07879 100644 --- a/board/compulab/trimslice/Makefile +++ b/board/compulab/trimslice/Makefile @@ -24,9 +24,7 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) $(shell mkdir -p $(obj)../../nvidia/common) -endif LIB= $(obj)lib$(BOARD).o -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v8 09/15] ARM: add tegra20 support to arm720t
Add support for tegra20 arm7 boot processor. This processor is used to power on the Cortex A9 and transfer control to it. In tegra this processor is an ARM7TDMI not an ARM720T, but since we don't use cache it was easier to just reuse the ARM720T code as the processors are otherwise identical except for cache and MMU. Signed-off-by: Allen Martin amar...@nvidia.com Acked-by: Stephen Warren swar...@wwwdotorg.org Tested-by: Thierry Reding thierry.red...@avionic-design.de Signed-off-by: Tom Warren twar...@nvidia.com --- arch/arm/cpu/arm720t/cpu.c |2 + arch/arm/cpu/arm720t/interrupts.c|5 + arch/arm/cpu/arm720t/start.S | 12 +- arch/arm/cpu/arm720t/tegra20/Makefile| 48 + arch/arm/cpu/arm720t/tegra20/board.h | 25 +++ arch/arm/cpu/arm720t/tegra20/config.mk | 26 +++ arch/arm/cpu/arm720t/tegra20/cpu.c | 258 ++ arch/arm/cpu/arm720t/tegra20/cpu.h | 100 ++ arch/arm/cpu/arm720t/tegra20/spl.c | 133 + arch/arm/include/asm/arch-tegra20/hardware.h | 29 +++ 10 files changed, 637 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/arm720t/tegra20/Makefile create mode 100644 arch/arm/cpu/arm720t/tegra20/board.h create mode 100644 arch/arm/cpu/arm720t/tegra20/config.mk create mode 100644 arch/arm/cpu/arm720t/tegra20/cpu.c create mode 100644 arch/arm/cpu/arm720t/tegra20/cpu.h create mode 100644 arch/arm/cpu/arm720t/tegra20/spl.c create mode 100644 arch/arm/include/asm/arch-tegra20/hardware.h diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c index 974f288..b6eee7e 100644 --- a/arch/arm/cpu/arm720t/cpu.c +++ b/arch/arm/cpu/arm720t/cpu.c @@ -51,6 +51,8 @@ int cleanup_before_linux (void) /* Nothing more needed */ #elif defined(CONFIG_INTEGRATOR) defined(CONFIG_ARCH_INTEGRATOR) /* No cleanup before linux for IntegratorAP/CM720T as yet */ +#elif defined (CONFIG_TEGRA) + /* No cleanup before linux for tegra as yet */ #else #error No cleanup_before_linux() defined for this CPU type #endif diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c index 464dd30..c2f898f 100644 --- a/arch/arm/cpu/arm720t/interrupts.c +++ b/arch/arm/cpu/arm720t/interrupts.c @@ -180,6 +180,9 @@ int timer_init (void) PUT32(T0TC, 0); PUT32(T0TCR, 1);/* enable timer0 */ +#elif defined(CONFIG_TEGRA) + /* No timer routines for tegra as yet */ + lastdec = 0; #else #error No timer_init() defined for this CPU type #endif @@ -282,6 +285,8 @@ void __udelay (unsigned long usec) #elif defined(CONFIG_INTEGRATOR) defined(CONFIG_ARCH_INTEGRATOR) /* No timer routines for IntegratorAP/CM720T as yet */ +#elif defined(CONFIG_TEGRA) + /* No timer routines for tegra as yet */ #else #error Timer routines not defined for this CPU type #endif diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index dc047b8..2f914e9 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -59,6 +59,7 @@ _data_abort: .word _data_abort _not_used: .word _not_used _irq: .word _irq _fiq: .word _fiq +_pad: .word 0x12345678 /* now 16*4=64 */ #else _undefined_instruction: .word undefined_instruction _software_interrupt: .word software_interrupt @@ -67,6 +68,7 @@ _data_abort: .word data_abort _not_used: .word not_used _irq: .word irq _fiq: .word fiq +_pad: .word 0x12345678 /* now 16*4=64 */ #endif /* CONFIG_SPL_BUILD */ .balignl 16,0xdeadbeef @@ -87,7 +89,11 @@ _fiq:.word fiq .globl _TEXT_BASE _TEXT_BASE: +#ifdef CONFIG_SPL_BUILD + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif /* * These are defined in the board-specific linker script. @@ -409,6 +415,8 @@ lock_loop: ldr r0, VPBDIV_ADR mov r1, #0x01 /* VPB clock is same as process clock */ str r1, [r0] +#elif defined(CONFIG_TEGRA) + /* No cpu_init_crit for tegra as yet */ #else #error No cpu_init_crit() defined for current CPU type #endif @@ -424,7 +432,7 @@ lock_loop: str r1, [r0] #endif -#ifndef CONFIG_LPC2292 +#if !defined(CONFIG_LPC2292) !defined(CONFIG_TEGRA) mov ip, lr /* * before relocating, we have to setup RAM timing @@ -633,6 +641,8 @@ reset_cpu: .globl reset_cpu reset_cpu: mov pc, r0 +#elif defined(CONFIG_TEGRA) + /* No specific reset actions for tegra as yet */ #else #error No reset_cpu() defined for current CPU type #endif diff --git a/arch/arm/cpu/arm720t/tegra20/Makefile b/arch/arm/cpu/arm720t/tegra20/Makefile new file mode 100644 index 000..6e48475 --- /dev/null +++ b/arch/arm/cpu/arm720t/tegra20/Makefile @@ -0,0
[U-Boot] [PATCH v8 12/15] tegra20: enable SPL for tegra20 boards
Add SPL options to tegra20 config files and enable SPL build for
tegra20 boards. Also remove redundant code from u-boot that is not
contained in SPL.
Signed-off-by: Allen Martin amar...@nvidia.com
Acked-by: Stephen Warren swar...@wwwdotorg.org
Tested-by: Thierry Reding thierry.red...@avionic-design.de
Signed-off-by: Tom Warren twar...@nvidia.com
---
Makefile |9 ++
arch/arm/cpu/armv7/Makefile |2 +-
arch/arm/cpu/armv7/start.S|2 -
arch/arm/cpu/tegra20-common/ap20.c| 258 +
arch/arm/cpu/tegra20-common/board.c | 23 +--
boards.cfg| 18 +--
include/configs/tegra20-common-post.h | 65 +
include/configs/tegra20-common.h | 22 ++-
8 files changed, 105 insertions(+), 294 deletions(-)
diff --git a/Makefile b/Makefile
index 001df10..3a6f49b 100644
--- a/Makefile
+++ b/Makefile
@@ -384,6 +384,15 @@ ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin
ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
+# enable combined SPL/u-boot/dtb rules for tegra
+ifeq ($(SOC),tegra20)
+ifeq ($(CONFIG_OF_SEPARATE),y)
+ALL-y += $(obj)u-boot-dtb-tegra.bin
+else
+ALL-y += $(obj)u-boot-nodtb-tegra.bin
+endif
+endif
+
all: $(ALL-y) $(SUBDIR_EXAMPLES)
$(obj)u-boot.dtb: $(obj)u-boot
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 788eada..4fdbee4 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,7 @@ COBJS += cache_v7.o
COBJS += cpu.o
COBJS += syslib.o
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
SOBJS += lowlevel_init.o
endif
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 38cce93..b06bafd 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -133,7 +133,6 @@ reset:
orr r0, r0, #0xd3
msr cpsr,r0
-#if !defined(CONFIG_TEGRA20)
/*
* Setup vector:
* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
@@ -149,7 +148,6 @@ reset:
ldr r0, =_start
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
#endif
-#endif /* !Tegra20 */
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/arch/arm/cpu/tegra20-common/ap20.c
b/arch/arm/cpu/tegra20-common/ap20.c
index 6ff71e0..00588da 100644
--- a/arch/arm/cpu/tegra20-common/ap20.c
+++ b/arch/arm/cpu/tegra20-common/ap20.c
@@ -20,16 +20,11 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-
#include asm/io.h
-#include asm/arch/tegra20.h
#include asm/arch/ap20.h
-#include asm/arch/clk_rst.h
-#include asm/arch/clock.h
#include asm/arch/fuse.h
#include asm/arch/gp_padctrl.h
#include asm/arch/pmc.h
-#include asm/arch/pinmux.h
#include asm/arch/scu.h
#include asm/arch/warmboot.h
#include common.h
@@ -68,235 +63,7 @@ int tegra_get_chip_type(void)
return TEGRA_SOC_UNKNOWN;
}
-/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
-static int ap20_cpu_is_cortexa9(void)
-{
- u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0);
- return id == (PG_UP_TAG_0_PID_CPU 0xff);
-}
-
-void init_pllx(void)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- struct clk_pll_simple *pll =
- clkrst-crc_pll_simple[CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE];
- u32 reg;
-
- /* If PLLX is already enabled, just return */
- if (readl(pll-pll_base) PLL_ENABLE_MASK)
- return;
-
- /* Set PLLX_MISC */
- writel(1 PLL_CPCON_SHIFT, pll-pll_misc);
-
- /* Use 12MHz clock here */
- reg = PLL_BYPASS_MASK | (12 PLL_DIVM_SHIFT);
- reg |= 1000 PLL_DIVN_SHIFT;
- writel(reg, pll-pll_base);
-
- reg |= PLL_ENABLE_MASK;
- writel(reg, pll-pll_base);
-
- reg = ~PLL_BYPASS_MASK;
- writel(reg, pll-pll_base);
-}
-
-static void enable_cpu_clock(int enable)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 clk;
-
- /*
-* NOTE:
-* Regardless of whether the request is to enable or disable the CPU
-* clock, every processor in the CPU complex except the master (CPU 0)
-* will have it's clock stopped because the AVP only talks to the
-* master. The AVP does not know (nor does it need to know) that there
-* are multiple processors in the CPU complex.
-*/
-
- if (enable) {
- /* Initialize PLLX */
- init_pllx();
-
- /* Wait until all clocks are stable */
- udelay(PLL_STABILIZATION_DELAY);
-
- writel(CCLK_BURST_POLICY, clkrst-crc_cclk_brst_pol);
- writel(SUPER_CCLK_DIVIDER,
[U-Boot] [PATCH 1/1] mx51/mx53/mx6: add watchdog
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
---
arch/arm/cpu/armv7/imx-common/Makefile |1 +
arch/arm/cpu/armv7/imx-common/watchdog.c | 32 ++
2 files changed, 33 insertions(+)
create mode 100644 arch/arm/cpu/armv7/imx-common/watchdog.c
diff --git a/arch/arm/cpu/armv7/imx-common/Makefile
b/arch/arm/cpu/armv7/imx-common/Makefile
index 16fba8d..f3a8e22 100644
--- a/arch/arm/cpu/armv7/imx-common/Makefile
+++ b/arch/arm/cpu/armv7/imx-common/Makefile
@@ -30,6 +30,7 @@ LIB = $(obj)libimx-common.o
COBJS-y= iomux-v3.o timer.o cpu.o speed.o
COBJS-$(CONFIG_I2C_MXC) += i2c.o
COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
+COBJS-$(CONFIG_IMX_WATCHDOG) += watchdog.o
COBJS := $(sort $(COBJS-y))
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/imx-common/watchdog.c
b/arch/arm/cpu/armv7/imx-common/watchdog.c
new file mode 100644
index 000..eadf3e8
--- /dev/null
+++ b/arch/arm/cpu/armv7/imx-common/watchdog.c
@@ -0,0 +1,32 @@
+/*
+ * watchdog.c - driver for i.mx on-chip watchdog
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include common.h
+#include asm/io.h
+#include watchdog.h
+#include asm/arch/imx-regs.h
+
+struct watchdog_regs {
+ u16 wcr;
+ u16 wsr;
+ u16 wrsr;
+ u16 wicr;
+ u16 wmcr;
+};
+
+void hw_watchdog_reset(void)
+{
+ struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+ writew(0x, wdog-wsr);
+ writew(0x, wdog-wsr);
+}
+
+void hw_watchdog_init(void)
+{
+ struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+ writew(0xFF8F, wdog-wcr);
+ hw_watchdog_reset();
+}
--
1.7.9.5
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Re: [U-Boot] [PATCH v8 00/15] split tegra20 arm7 code into separate SPL
On Wed, Aug 15, 2012 at 01:44:17PM -0700, Allen Martin wrote: This patch series fixes a long standing problem with the tegra20 u-boot build. Tegra20 contains an ARM7TDMI boot processor and a Cortex A9 main processor. Prior to this patch series this was accomplished by #ifdefing out any armv7 code from the early boot sequence and creating a single binary that runs on both both the ARM7TDMI and A9. This was very fragile as changes to compiler options or any additions or rearranging of the early boot code could add additional armv7 specific code causing it to fail on the ARM7TDMI. This patch series pulls all the armv4t code out into a separate SPL that does nothing more than initialize the A9 and transfer control to it. The resultint SPL and armv7 u-boot are concatenated together into a single image. This patch series is also available from: git://github.com/arm000/u-boot.git branch: tegra-spl-v8 Changes: v8: - rebased to u-boot-tegra/master - added changes to work with arm: Provide lowlevel_init C function wrapper for v7 - Moved JTAG init in SPL to earlier - fixed TEXT_BASE in SPL to use SPL TEXT_BASE not main u-boot TEXT_BASE - pad exception handlers in arm720t to 64 bytes with 0x12345678 to match armv7 Two additional changes I neglected to mention: - added another tegra2-tegra20 rename for some new code that was added to arch/arm/cpu/armv7/start.S - rolled in the mkconfig fix that was breaking ARM platforms that don't define SoC -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 00/17]: ARM: SPL: Make more generic, merge DaVinci and OMAP
Hey all, The following patch series merges the davinci and omap-common SPL frameworks into a single framework, CONFIG_SPL_FRAMEWORK along with a few small cleanups to the code to make it a little smaller and more flexible. The end result is that davinci can now opt in on SPL-boots-Linux by just setting the right defines and other platforms would just need to adapt to this framework. In my testing, davinci gains between 300 and 700 bytes for this (not enabling the SPL OS feature) and omap4/5/etc lose just a little bit (from the printf-puts changes). I've tested this on omap3_beagle (xM and classic) and omap4_panda. I don't have any davinci platforms that were previously using SPL so I can't boot-test those changes but since everyone sets CONFIG_SPL_MAX_SIZE, we're OK in that department. To make this series easier to test I've placed it on http://github.com/trini/u-boot WIP/spl-improvements I've looked a little into re-reducing the size and the biggest problem I see is that SPI a lot of informational prints that we don't need, strictly speaking, but are nice in a normal U-Boot context. I'm unsure of the best way to quiet these as I don't like the idea of sprinkling #ifndef CONFIG_SPL_BUILD in random places. -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 01/17] spl_mmc: Make FAT checks / calls guarded with CONFIG_SPL_FAT_SUPPORT
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/omap-common/spl_mmc.c |4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap-common/spl_mmc.c
b/arch/arm/cpu/armv7/omap-common/spl_mmc.c
index 2f921bb..7552f6c 100644
--- a/arch/arm/cpu/armv7/omap-common/spl_mmc.c
+++ b/arch/arm/cpu/armv7/omap-common/spl_mmc.c
@@ -84,6 +84,7 @@ end:
}
}
+#ifdef CONFIG_SPL_FAT_SUPPORT
static void mmc_load_image_fat(struct mmc *mmc)
{
s32 err;
@@ -116,6 +117,7 @@ end:
hang();
}
}
+#endif
void spl_mmc_load_image(void)
{
@@ -140,9 +142,11 @@ void spl_mmc_load_image(void)
if (boot_mode == MMCSD_MODE_RAW) {
debug(boot mode - RAW\n);
mmc_load_image_raw(mmc);
+#ifdef CONFIG_SPL_FAT_SUPPORT
} else if (boot_mode == MMCSD_MODE_FAT) {
debug(boot mode - FAT\n);
mmc_load_image_fat(mmc);
+#endif
} else {
puts(spl: wrong MMC boot mode\n);
hang();
--
1.7.9.5
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[U-Boot] [PATCH 02/17] omap-common: SPL: Add CONFIG_SPL_DISPLAY_PRINT / spl_display_print()
Only omap4/5 currently have a meaningful set of display text and overo
had been adding a function to display nothing. Change how this works to
be opt-in and only turned on for omap4/5 now.
Signed-off-by: Tom Rini tr...@ti.com
---
README |4
arch/arm/cpu/armv7/omap-common/hwinit-common.c |5 +
arch/arm/cpu/armv7/omap-common/spl.c |9 +++--
arch/arm/include/asm/arch-omap4/sys_proto.h|1 -
arch/arm/include/asm/arch-omap5/sys_proto.h|1 -
arch/arm/include/asm/omap_common.h |2 +-
board/overo/overo.c| 10 --
include/configs/omap4_common.h |1 +
include/configs/omap5_evm.h|1 +
9 files changed, 15 insertions(+), 19 deletions(-)
diff --git a/README b/README
index fb9d904..f1a12a5 100644
--- a/README
+++ b/README
@@ -2564,6 +2564,10 @@ FIT uImage format:
CONFIG_SYS_SPL_MALLOC_SIZE
The size of the malloc pool used in SPL.
+ CONFIG_SPL_DISPLAY_PRINT
+ For ARM, enable an optional function to print more information
+ about the running system.
+
CONFIG_SPL_LIBCOMMON_SUPPORT
Support for common/libcommon.o in SPL binary
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 459ebb5..4d7ef5c 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -92,6 +92,11 @@ static void init_boot_params(void)
{
boot_params_ptr = (u32 *) boot_params;
}
+
+void spl_display_print(void)
+{
+ omap_rev_string();
+}
#endif
/*
diff --git a/arch/arm/cpu/armv7/omap-common/spl.c
b/arch/arm/cpu/armv7/omap-common/spl.c
index 4d1ac85..b10832a 100644
--- a/arch/arm/cpu/armv7/omap-common/spl.c
+++ b/arch/arm/cpu/armv7/omap-common/spl.c
@@ -219,10 +219,7 @@ void preloader_console_init(void)
printf(\nU-Boot SPL %s (%s - %s)\n, u_boot_rev, U_BOOT_DATE,
U_BOOT_TIME);
- omap_rev_string();
-}
-
-void __weak omap_rev_string()
-{
- printf(Texas Instruments Revision detection unimplemented\n);
+#ifdef CONFIG_SPL_DISPLAY_PRINT
+ spl_display_print();
+#endif
}
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h
b/arch/arm/include/asm/arch-omap4/sys_proto.h
index d633573..b48f81d 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -42,7 +42,6 @@ void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void set_pl310_ctrl_reg(u32 val);
-void omap_rev_string(void);
void setup_clocks_for_console(void);
void prcm_init(void);
void bypass_dpll(u32 *const base);
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h
b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 74feb90..72e9df7 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -42,7 +42,6 @@ void set_muxconf_regs_non_essential(void);
void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
-void omap_rev_string(void);
void setup_clocks_for_console(void);
void prcm_init(void);
void bypass_dpll(u32 *const base);
diff --git a/arch/arm/include/asm/omap_common.h
b/arch/arm/include/asm/omap_common.h
index 4e95eee..19df5ea 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -94,9 +94,9 @@ u32 omap_boot_mode(void);
/* SPL common function s*/
void spl_parse_image_header(const struct image_header *header);
-void omap_rev_string(void);
void spl_board_prepare_for_linux(void);
int spl_start_uboot(void);
+void spl_display_print(void);
/* NAND SPL functions */
void spl_nand_load_image(void);
diff --git a/board/overo/overo.c b/board/overo/overo.c
index f973870..c6d50a0 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -101,16 +101,6 @@ int board_init(void)
}
/*
- * Routine: omap_rev_string
- * Description: For SPL builds output board rev
- */
-#ifdef CONFIG_SPL_BUILD
-void omap_rev_string(void)
-{
-}
-#endif
-
-/*
* Routine: get_board_revision
* Description: Returns the board revision
*/
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index 2192c2b..685fde9 100644
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -249,6 +249,7 @@
#define CONFIG_SPL_TEXT_BASE 0x40304350
#define CONFIG_SPL_MAX_SIZE(38 * 1024)
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+#define CONFIG_SPL_DISPLAY_PRINT
/*
* 64 bytes before this address should be set aside for u-boot.img's
diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h
index c5874bb..ef4034c 100644
--- a/include/configs/omap5_evm.h
+++ b/include/configs/omap5_evm.h
@@ -246,6 +246,7 @@
#define
[U-Boot] [PATCH 06/17] ARM: SPL: Rename omap_boot_mode to spl_boot_mode()
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/omap-common/boot-common.c |2 +-
arch/arm/cpu/armv7/omap3/board.c |2 +-
arch/arm/include/asm/omap_common.h |2 +-
arch/arm/lib/spl_mmc.c |2 +-
arch/arm/lib/spl_nand.c |2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c
b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 102a381..53568ac 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -42,7 +42,7 @@ u32 spl_boot_device(void)
return (u32) (boot_params.omap_bootdevice);
}
-u32 omap_boot_mode(void)
+u32 spl_boot_mode(void)
{
return omap_bootmode;
}
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index b4f4fee..1640696 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -69,7 +69,7 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
u32 omap3_boot_device = BOOT_DEVICE_NAND;
/* auto boot mode detection is not possible for OMAP3 - hard code */
-u32 omap_boot_mode(void)
+u32 spl_boot_mode(void)
{
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC2:
diff --git a/arch/arm/include/asm/omap_common.h
b/arch/arm/include/asm/omap_common.h
index a3853ce..9ac0cc2 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -90,7 +90,7 @@ extern struct spl_image_info spl_image;
extern u32* boot_params_ptr;
u32 spl_boot_device(void);
-u32 omap_boot_mode(void);
+u32 spl_boot_mode(void);
/* SPL common function s*/
void spl_parse_image_header(const struct image_header *header);
diff --git a/arch/arm/lib/spl_mmc.c b/arch/arm/lib/spl_mmc.c
index 3ad382b..62b308b 100644
--- a/arch/arm/lib/spl_mmc.c
+++ b/arch/arm/lib/spl_mmc.c
@@ -138,7 +138,7 @@ void spl_mmc_load_image(void)
printf(spl: mmc init failed: err - %d\n, err);
hang();
}
- boot_mode = omap_boot_mode();
+ boot_mode = spl_boot_mode();
if (boot_mode == MMCSD_MODE_RAW) {
debug(boot mode - RAW\n);
mmc_load_image_raw(mmc);
diff --git a/arch/arm/lib/spl_nand.c b/arch/arm/lib/spl_nand.c
index 8cf55c9..ea7cc8a 100644
--- a/arch/arm/lib/spl_nand.c
+++ b/arch/arm/lib/spl_nand.c
@@ -35,7 +35,7 @@ void spl_nand_load_image(void)
int *src __attribute__((unused));
int *dst __attribute__((unused));
- switch (omap_boot_mode()) {
+ switch (spl_boot_mode()) {
case NAND_MODE_HW_ECC:
debug(spl: nand - using hw ecc\n);
gpmc_init();
--
1.7.9.5
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[U-Boot] [PATCH 05/17] ARM: SPL: Rename omap_boot_device to spl_boot_device
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/omap-common/boot-common.c |2 +-
arch/arm/cpu/armv7/omap-common/lowlevel_init.S |4 ++--
arch/arm/cpu/armv7/omap3/board.c |4 ++--
arch/arm/include/asm/omap_common.h |2 +-
arch/arm/lib/spl.c |2 +-
arch/arm/lib/spl_mmc.c |2 +-
6 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c
b/arch/arm/cpu/armv7/omap-common/boot-common.c
index f211f76..102a381 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -37,7 +37,7 @@ struct omap_boot_parameters boot_params __attribute__
((section(.data)));
*/
u32 omap_bootmode = MMCSD_MODE_FAT;
-u32 omap_boot_device(void)
+u32 spl_boot_device(void)
{
return (u32) (boot_params.omap_bootdevice);
}
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
index ccc6bb6..d4ce0af 100644
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -52,11 +52,11 @@ ENTRY(save_boot_params)
ldr r1, =boot_params
str r0, [r1]
#ifdef CONFIG_SPL_BUILD
- /* Store the boot device in omap_boot_device */
+ /* Store the boot device in spl_boot_device */
ldrbr2, [r0, #BOOT_DEVICE_OFFSET] @ r1 - value of boot device
and r2, #BOOT_DEVICE_MASK
ldr r3, =boot_params
- strbr2, [r3, #BOOT_DEVICE_OFFSET] @ omap_boot_device - r1
+ strbr2, [r3, #BOOT_DEVICE_OFFSET] @ spl_boot_device - r1
/* boot mode is passed only for devices that can raw/fat mode */
cmp r2, #2
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index f2e52e9..b4f4fee 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -71,7 +71,7 @@ u32 omap3_boot_device = BOOT_DEVICE_NAND;
/* auto boot mode detection is not possible for OMAP3 - hard code */
u32 omap_boot_mode(void)
{
- switch (omap_boot_device()) {
+ switch (spl_boot_device()) {
case BOOT_DEVICE_MMC2:
return MMCSD_MODE_RAW;
case BOOT_DEVICE_MMC1:
@@ -86,7 +86,7 @@ u32 omap_boot_mode(void)
}
}
-u32 omap_boot_device(void)
+u32 spl_boot_device(void)
{
return omap3_boot_device;
}
diff --git a/arch/arm/include/asm/omap_common.h
b/arch/arm/include/asm/omap_common.h
index 19df5ea..a3853ce 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -89,7 +89,7 @@ struct spl_image_info {
extern struct spl_image_info spl_image;
extern u32* boot_params_ptr;
-u32 omap_boot_device(void);
+u32 spl_boot_device(void);
u32 omap_boot_mode(void);
/* SPL common function s*/
diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c
index b10832a..4d33f99 100644
--- a/arch/arm/lib/spl.c
+++ b/arch/arm/lib/spl.c
@@ -156,7 +156,7 @@ void board_init_r(gd_t *id, ulong dummy)
spl_board_init();
#endif
- boot_device = omap_boot_device();
+ boot_device = spl_boot_device();
debug(boot device - %d\n, boot_device);
switch (boot_device) {
#ifdef CONFIG_SPL_MMC_SUPPORT
diff --git a/arch/arm/lib/spl_mmc.c b/arch/arm/lib/spl_mmc.c
index 7552f6c..3ad382b 100644
--- a/arch/arm/lib/spl_mmc.c
+++ b/arch/arm/lib/spl_mmc.c
@@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
- switch (omap_boot_device()) {
+ switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
omap_mmc_init(0, 0, 0);
break;
--
1.7.9.5
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[U-Boot] [PATCH 08/17] ARM: SPL: Remove NAND_MODE_HW_ECC from spl_nand.c
This detection code doesn't (and can't) do anything currently, so
remove.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/omap3/board.c |3 ---
arch/arm/include/asm/omap_common.h |1 -
arch/arm/lib/spl_nand.c| 13 +++--
3 files changed, 3 insertions(+), 14 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 1640696..a487374 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -77,9 +77,6 @@ u32 spl_boot_mode(void)
case BOOT_DEVICE_MMC1:
return MMCSD_MODE_FAT;
break;
- case BOOT_DEVICE_NAND:
- return NAND_MODE_HW_ECC;
- break;
default:
puts(spl: ERROR: unknown device - can't select boot mode\n);
hang();
diff --git a/arch/arm/include/asm/omap_common.h
b/arch/arm/include/asm/omap_common.h
index 9ac0cc2..1e8f59b 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -76,7 +76,6 @@ void preloader_console_init(void);
#defineMMCSD_MODE_UNDEFINED0
#define MMCSD_MODE_RAW 1
#define MMCSD_MODE_FAT 2
-#define NAND_MODE_HW_ECC 3
struct spl_image_info {
const char *name;
diff --git a/arch/arm/lib/spl_nand.c b/arch/arm/lib/spl_nand.c
index ea7cc8a..39221d5 100644
--- a/arch/arm/lib/spl_nand.c
+++ b/arch/arm/lib/spl_nand.c
@@ -35,16 +35,9 @@ void spl_nand_load_image(void)
int *src __attribute__((unused));
int *dst __attribute__((unused));
- switch (spl_boot_mode()) {
- case NAND_MODE_HW_ECC:
- debug(spl: nand - using hw ecc\n);
- gpmc_init();
- nand_init();
- break;
- default:
- puts(spl: ERROR: This bootmode is not implemented - hanging);
- hang();
- }
+ debug(spl: nand - using hw ecc\n);
+ gpmc_init();
+ nand_init();
/*use CONFIG_SYS_TEXT_BASE as temporary storage area */
header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
--
1.7.9.5
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[U-Boot] [PATCH 07/17] omap-common: Fix typo in lowlevel_init.S::save_boot_params
Signed-off-by: Tom Rini tr...@ti.com --- arch/arm/cpu/armv7/omap-common/lowlevel_init.S |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index d4ce0af..dafe18b 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -63,7 +63,7 @@ ENTRY(save_boot_params) blt 2f cmp r2, #7 bgt 2f - /* Store the boot mode (raw/FAT) in omap_boot_mode */ + /* Store the boot mode (raw/FAT) in omap_bootmode */ ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr ldr r2, [r2, #DEV_DATA_PTR_OFFSET] @ get the pDeviceData ptr ldr r2, [r2, #BOOT_MODE_OFFSET] @ get the boot mode -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 09/17] ARM: SPL: Only call mem_malloc_init if configured
We can only attempt to setup a malloc pool if CONFIG_SYS_SPL_MALLOC_START is defined, and not all boards require it. Make the call depend on the define. Signed-off-by: Tom Rini tr...@ti.com --- arch/arm/lib/spl.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index 4d33f99..71a467e 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -149,8 +149,10 @@ void board_init_r(gd_t *id, ulong dummy) u32 boot_device; debug(spl:board_init_r()\n); +#ifdef CONFIG_SYS_SPL_MALLOC_START mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START, CONFIG_SYS_SPL_MALLOC_SIZE); +#endif #ifdef CONFIG_SPL_BOARD_INIT spl_board_init(); -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 13/17] ARM: SPL: Start hooking in the current SPI SPL support
Signed-off-by: Tom Rini tr...@ti.com --- arch/arm/include/asm/spl.h |3 +++ arch/arm/lib/spl.c |5 + 2 files changed, 8 insertions(+) diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 41036e9..f0eb96f 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -60,6 +60,9 @@ void spl_mmc_load_image(void); /* YMODEM SPL functions */ void spl_ymodem_load_image(void); +/* SPI SPL functions */ +void spi_boot(void); + #ifdef CONFIG_SPL_BOARD_INIT void spl_board_init(void); #endif diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index 3a1029f..dc26750 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -175,6 +175,11 @@ void board_init_r(gd_t *id, ulong dummy) spl_ymodem_load_image(); break; #endif +#ifdef CONFIG_SPL_SPI_SUPPORT + case BOOT_DEVICE_SPI: + spi_boot(); + break; +#endif default: puts(SPL: Un-supported Boot Device\n); debug(Found: %d\n, boot_device); -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
