Re: [U-Boot] [RFC Patch v6] Consolidate bool type
On 01/30/2013 11:40 AM, Allen Martin wrote: On Wed, Jan 30, 2013 at 10:37:30AM -0800, York Sun wrote: On 01/24/2013 05:00 PM, Allen Martin wrote: I think you can drop the RFC from your patch at this point. Built on all tegra20 and tegra30 devices with USE_PRIVATE_LIBGCC. Tested on seaboard (tegra20). I've also submitted your patch to my build regression script which will build all 1100+ boards against your patch and tell if there are any build regressions. I'll let you know the results tomorrow. Allen, Is any change needed? Hi York, sorry I forgot to get back to you. I ran your patch through all boards and so no warning or error build regressions. Looking at the logs it looks like I ran it on version 5 not version 6 of your patch though. I'll do another run tonight on version 6 and let you know the results. I don't anticipate any problems though as it looks like the only differences are dropping the python files and whitespace changes. Allen, Your help is greatly appreciated. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/6] imx: mx6q DDR3 init: Fix tXPR
MMDC1_MDOR.tXPR should be set as specified for the JEDEC DDR3 timing tXPR. For all DDR3 speed bins: tXPR(min) = max(5 nCK, tRFC(min) + 10 ns) tRFC(2 Gb) = 160 ns All the users of mx6q_4x_mt41j128.cfg have a 2-Gb density (Micron MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and Micron MT41K128M16JT-125:K for i.MX6 SABRE SD). Hence, MMDC1_MDOR.tXPR should be set to max(5 nCK, 170 ns), which is 170 ns and 91 nCK at 532 MHz, encoded as 0x5A in the bit-field MMDC1_MDOR[23:16]. Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 9ac8027..1c24da8 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x26D2 -DATA 4 0x021b0030 0x005B0E21 +DATA 4 0x021b0030 0x005A0E21 DATA 4 0x021b0008 0x09444040 DATA 4 0x021b0004 0x00025576 DATA 4 0x021b0040 0x0027 -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/6] imx: mx6q DDR3 init: Fix tMRD
MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3. For all DDR3 speed bins: tMRD(min) = 4 nCK tMOD(min) = max(12 nCK, 15 ns) Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5]. Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index c86cd40..9ac8027 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -110,7 +110,7 @@ DATA 4 0x021b0018 0x00081740 DATA 4 0x021b001c 0x8000 DATA 4 0x021b000c 0x555A7975 -DATA 4 0x021b0010 0xFF538E64 +DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x26D2 -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/6] imx: mx6q DDR3 init: Fix RST_to_CKE
MMDC1_MDOR.RST_to_CKE should be set to 500 µs according to the JEDEC specification for DDR3. With a cycle of 15.258 µs, this gives 33 cycles encoded as 0x23 for the bit-field MMDC1_MDOR[5:0]. Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 73317b5..51f8c35 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x26D2 -DATA 4 0x021b0030 0x005A1021 +DATA 4 0x021b0030 0x005A1023 DATA 4 0x021b0008 0x09444040 DATA 4 0x021b0004 0x00025576 DATA 4 0x021b0040 0x0027 -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/6] imx: mx6q DDR3 init: Fix MR0.PPD
MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28]. Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 51f8c35..d50858d 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -126,8 +126,8 @@ DATA 4 0x021b001c 0x8033 DATA 4 0x021b001c 0x803B DATA 4 0x021b001c 0x00428031 DATA 4 0x021b001c 0x00428039 -DATA 4 0x021b001c 0x09408030 -DATA 4 0x021b001c 0x09408038 +DATA 4 0x021b001c 0x19408030 +DATA 4 0x021b001c 0x19408038 DATA 4 0x021b001c 0x04008040 DATA 4 0x021b001c 0x04008048 -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/6] imx: mx6q DDR3 init: Fix SDE_to_RST
MMDC1_MDOR.SDE_to_RST should be set to 200 µs according to the JEDEC specification for DDR3. With a cycle of 15.258 µs, this gives 14 cycles encoded as 0x10 for the bit-field MMDC1_MDOR[13:8]. Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 1c24da8..73317b5 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64 DATA 4 0x021b0014 0x01FF00DB DATA 4 0x021b002c 0x26D2 -DATA 4 0x021b0030 0x005A0E21 +DATA 4 0x021b0030 0x005A1021 DATA 4 0x021b0008 0x09444040 DATA 4 0x021b0004 0x00025576 DATA 4 0x021b0040 0x0027 -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 6/6] imx: mx6q DDR3 init: Benefit from available CL = 7
All the users of mx6q_4x_mt41j128.cfg (DDR3-1333H Micron MT41J128M16HA-15E or SK
hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and DDR3-1600K Micron
MT41K128M16JT-125:K for i.MX6 SABRE SD) support the optional down binning to
DDR3-1066F (CL = 7, CWL = 6), which is possible at 532 MHz, so use it.
In these conditions:
tRCD(min) = 13.125 ns
tRP(min) = 13.125 ns
tRC(min) = max(tRAS(min, DDR3-1333H), tRAS(min, DDR3-1600K)) + tRP(min)
tRAS(min, DDR3-1333H) = 36 ns
tRAS(min, DDR3-1600K) = 35 ns
MMDC1_MDCFG0.tCL should be set to 7 nCK, encoded as 0x4 in the bit-field
MMDC1_MDCFG0[3:0].
MR0.CL should be set as in MMDC1_MDCFG0.tCL, i.e. to 7 nCK, which is encoded
as 0x6 in MRS.LMR.MR0.{A6:A4, A2} and MMDC1_MDSCR[22:20, 18].
MMDC1_MDCFG1.tCWL should be set to 6 nCK, encoded as 0x4 in the bit-field
MMDC1_MDCFG1[2:0].
MMDC1_MDCFG1.tRCD should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded
as 0x6 in the bit-field MMDC1_MDCFG1[31:29].
MMDC1_MDCFG1.tRP should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded
as 0x6 in the bit-field MMDC1_MDCFG1[28:26].
MMDC1_MDCFG1.tRC should be set to 49.125 ns, which is 27 nCK at 532 MHz, encoded
as 0x1A in the bit-field MMDC1_MDCFG1[25:21].
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com
---
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index d50858d..f4cae5e 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -109,8 +109,8 @@ DATA 4 0x021b4828 0x
DATA 4 0x021b0018 0x00081740
DATA 4 0x021b001c 0x8000
-DATA 4 0x021b000c 0x555A7975
-DATA 4 0x021b0010 0xFF538F64
+DATA 4 0x021b000c 0x555A7974
+DATA 4 0x021b0010 0xDB538F64
DATA 4 0x021b0014 0x01FF00DB
DATA 4 0x021b002c 0x26D2
@@ -126,8 +126,8 @@ DATA 4 0x021b001c 0x8033
DATA 4 0x021b001c 0x803B
DATA 4 0x021b001c 0x00428031
DATA 4 0x021b001c 0x00428039
-DATA 4 0x021b001c 0x19408030
-DATA 4 0x021b001c 0x19408038
+DATA 4 0x021b001c 0x19308030
+DATA 4 0x021b001c 0x19308038
DATA 4 0x021b001c 0x04008040
DATA 4 0x021b001c 0x04008048
--
1.7.10.4
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Re: [U-Boot] [RFC Patch v6] Consolidate bool type
On Wed, Jan 30, 2013 at 11:47:57AM -0800, York Sun wrote: On 01/30/2013 11:40 AM, Allen Martin wrote: On Wed, Jan 30, 2013 at 10:37:30AM -0800, York Sun wrote: On 01/24/2013 05:00 PM, Allen Martin wrote: I think you can drop the RFC from your patch at this point. Built on all tegra20 and tegra30 devices with USE_PRIVATE_LIBGCC. Tested on seaboard (tegra20). I've also submitted your patch to my build regression script which will build all 1100+ boards against your patch and tell if there are any build regressions. I'll let you know the results tomorrow. Allen, Is any change needed? Hi York, sorry I forgot to get back to you. I ran your patch through all boards and so no warning or error build regressions. Looking at the logs it looks like I ran it on version 5 not version 6 of your patch though. I'll do another run tonight on version 6 and let you know the results. I don't anticipate any problems though as it looks like the only differences are dropping the python files and whitespace changes. Allen, Your help is greatly appreciated. York Compiled against all boards, no warning or error regressions detected. Tested on tegra20 trimslice and tegra30 cardhu. Acked-by: Allen Martin amar...@nvidia.com -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] arm: fix CONFIG_DELAY_ENVIRONMENT to act like it claims in the README
On Tue, Jan 22, 2013 at 06:12:47AM -0800, Simon Glass wrote:
On Tue, Jan 22, 2013 at 2:15 AM, Lucas Stach d...@lynxeye.de wrote:
No one expects to end up in a delayed environment if
CONFIG_DELAY_ENVIRONMENT isn't defined.
Signed-off-by: Lucas Stach d...@lynxeye.de
Good with me, and solves the immediate problem. Thanks for doing the patch.
Acked-by: Simon Glass s...@chromium.org
Adding Tom Rini and Albert. What's the best way to get this up to
u-boot/master as quickly as possible? Environment is broken on all
boards that use fdt until this goes in.
-Allen
---
v2: keep preference of CONFIG_OF_CONTROL and just change default value
---
arch/arm/lib/board.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index cfe32cc..9f861cc 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -488,7 +488,7 @@ static char *failed = *** failed ***\n;
static int should_load_env(void)
{
#ifdef CONFIG_OF_CONTROL
- return fdtdec_get_config_int(gd-fdt_blob, load-environment, 0);
+ return fdtdec_get_config_int(gd-fdt_blob, load-environment, 1);
#elif defined CONFIG_DELAY_ENVIRONMENT
return 0;
#else
--
1.8.0.2
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Re: [U-Boot] [RFC Patch v6] Consolidate bool type
On 01/30/2013 02:53 PM, Allen Martin wrote: On Wed, Jan 30, 2013 at 11:47:57AM -0800, York Sun wrote: On 01/30/2013 11:40 AM, Allen Martin wrote: On Wed, Jan 30, 2013 at 10:37:30AM -0800, York Sun wrote: On 01/24/2013 05:00 PM, Allen Martin wrote: I think you can drop the RFC from your patch at this point. Built on all tegra20 and tegra30 devices with USE_PRIVATE_LIBGCC. Tested on seaboard (tegra20). I've also submitted your patch to my build regression script which will build all 1100+ boards against your patch and tell if there are any build regressions. I'll let you know the results tomorrow. Allen, Is any change needed? Hi York, sorry I forgot to get back to you. I ran your patch through all boards and so no warning or error build regressions. Looking at the logs it looks like I ran it on version 5 not version 6 of your patch though. I'll do another run tonight on version 6 and let you know the results. I don't anticipate any problems though as it looks like the only differences are dropping the python files and whitespace changes. Allen, Your help is greatly appreciated. York Compiled against all boards, no warning or error regressions detected. Tested on tegra20 trimslice and tegra30 cardhu. Acked-by: Allen Martin amar...@nvidia.com Thanks a lot, Allen. I will send v7 with RFC removed from subject and add your ack. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-mpc85xx.git
On Wed, Jan 30, 2013 at 11:34:47AM -0600, Andy Fleming wrote: Merge branch 'master' of git://git.denx.de/u-boot-i2c (2013-01-29 15:36:27 -0500) are available in the git repository at: git://www.denx.de/git/u-boot-mpc85xx.git master for you to fetch changes up to d4ed6542788169b789c7eed142efc0a6fa5ca698: corenet: Disable video on P2020DS (2013-01-30 11:25:16 -0600) Anatolij Gustschin (1): mpc8xxx: fix DDR init value to use CONFIG_MEM_INIT_VALUE Andy Fleming (1): corenet: Disable video on P2020DS Hongtao Jia (2): powerpc/mpc8572ds: Enable bank interleaving to cs0+cs1 for dual-rank DIMMs powerpc/mpc8544ds: Add USB controller support for MPC8544DS James Yang (5): Move DDR command parsing to separate function Fix data stage name matching issue Add copy command to FSL DDR interactive README.fsl-ddr typos and update to reflect hotkey powerpc/mpc8: FSL DDR debugger auto run of stored commands Poonam Aggrwal (2): powerpc/mpc85xx: Few updates for B4860 cpu changes powerpc/mpc85xx:Add support of B4420 SoC Prabhakar Kushwaha (8): board/T4240qds:Fix TLB and LAW size of NAND flash boards/T4240qds:Fix IFC AMASK init as per FPGA register space board/freescale/common:Add support of QTAG register powerpc/mpc85xx:Fix Core cluster configuration loop powerpc/t4240qds: Print FPGA detail version powerpc/mpc85xx: Add BSC9132/BSC9232 processor support powerpc/85xx: Add BSC9132QDS support board/common: Add support for QIXIS read/write using i2c Scott Wood (1): powerpc/mpc85xx: add support for MMUv2 page sizes Shaohui Xie (1): powerpc/p2041: move Lanes mux to board early init Shaveta Leekha (3): powerpc/qixis: enable qixis dump command and add switch dumping command powerpc/b4860qds: Add support to dump switch settings on b4860qds board powerpc/t4240qds: Add support to dump switch settings on t4240qds board Shengzhou Liu (1): powerpc/t4240: Adding workaround errata A-005871 Timur Tabi (1): powerpc/t4qds: move VSC3316 config data from t4qds.h to t4qds.c Vakul Garg (1): powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto' Valentin Longchamp (2): powerpc/p2041: add RCW file for P2041RDB powerpc/p2041: set RCW and PBI files for .pbl build or P2041RDB York Sun (4): powerpc/mpc85xx: Reserve default boot page powerpc/t4240qds: Update IFC timing for NOR flash powerpc/b4860qds: Added Support for B4860QDS powerpc/mpc8xxx: Enable entering DDR debugging by key press MAINTAINERS |4 + arch/powerpc/cpu/mpc85xx/Makefile|5 + arch/powerpc/cpu/mpc85xx/b4860_ids.c |6 + arch/powerpc/cpu/mpc85xx/b4860_serdes.c | 60 ++ arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c| 96 +++ arch/powerpc/cpu/mpc85xx/cmd_errata.c|4 + arch/powerpc/cpu/mpc85xx/cpu_init.c | 44 +- arch/powerpc/cpu/mpc85xx/fdt.c | 24 + arch/powerpc/cpu/mpc85xx/start.S |2 +- arch/powerpc/cpu/mpc85xx/tlb.c | 19 +- arch/powerpc/cpu/mpc8xxx/cpu.c |2 + arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |4 + arch/powerpc/cpu/mpc8xxx/ddr/ddr.h |3 +- arch/powerpc/cpu/mpc8xxx/ddr/interactive.c | 324 ++--- arch/powerpc/cpu/mpc8xxx/ddr/main.c |8 +- arch/powerpc/cpu/mpc8xxx/fdt.c | 78 +- arch/powerpc/include/asm/config_mpc85xx.h| 39 +- arch/powerpc/include/asm/immap_85xx.h| 34 +- arch/powerpc/include/asm/mmu.h | 52 +- arch/powerpc/include/asm/processor.h |2 + board/freescale/b4860qds/Makefile| 54 ++ board/freescale/b4860qds/b4860qds.c | 505 + board/freescale/b4860qds/b4860qds.h | 26 + board/freescale/b4860qds/b4860qds_crossbar_con.h | 67 ++ board/freescale/b4860qds/b4860qds_qixis.h| 37 + board/freescale/b4860qds/ddr.c | 190 + board/freescale/b4860qds/eth_b4860qds.c | 338 + board/freescale/b4860qds/law.c | 44 ++ board/freescale/b4860qds/pci.c | 39 + board/freescale/b4860qds/tlb.c | 127 board/freescale/bsc9132qds/Makefile | 52 ++ board/freescale/bsc9132qds/README| 150 board/freescale/bsc9132qds/bsc9132qds.c | 403 +++ board/freescale/bsc9132qds/ddr.c | 209 ++ board/freescale/bsc9132qds/law.c | 35 + board/freescale/bsc9132qds/tlb.c | 92 +++
Re: [U-Boot] Please pull u-boot-mpc85xx.git
Yes. I have some internal review stuff to finish, but I will get to MMC next. On Wed, Jan 30, 2013 at 5:17 PM, Tom Rini tr...@ti.com wrote: On Wed, Jan 30, 2013 at 11:34:47AM -0600, Andy Fleming wrote: Merge branch 'master' of git://git.denx.de/u-boot-i2c (2013-01-29 15:36:27 -0500) are available in the git repository at: git://www.denx.de/git/u-boot-mpc85xx.git master for you to fetch changes up to d4ed6542788169b789c7eed142efc0a6fa5ca698: corenet: Disable video on P2020DS (2013-01-30 11:25:16 -0600) Anatolij Gustschin (1): mpc8xxx: fix DDR init value to use CONFIG_MEM_INIT_VALUE Andy Fleming (1): corenet: Disable video on P2020DS Hongtao Jia (2): powerpc/mpc8572ds: Enable bank interleaving to cs0+cs1 for dual-rank DIMMs powerpc/mpc8544ds: Add USB controller support for MPC8544DS James Yang (5): Move DDR command parsing to separate function Fix data stage name matching issue Add copy command to FSL DDR interactive README.fsl-ddr typos and update to reflect hotkey powerpc/mpc8: FSL DDR debugger auto run of stored commands Poonam Aggrwal (2): powerpc/mpc85xx: Few updates for B4860 cpu changes powerpc/mpc85xx:Add support of B4420 SoC Prabhakar Kushwaha (8): board/T4240qds:Fix TLB and LAW size of NAND flash boards/T4240qds:Fix IFC AMASK init as per FPGA register space board/freescale/common:Add support of QTAG register powerpc/mpc85xx:Fix Core cluster configuration loop powerpc/t4240qds: Print FPGA detail version powerpc/mpc85xx: Add BSC9132/BSC9232 processor support powerpc/85xx: Add BSC9132QDS support board/common: Add support for QIXIS read/write using i2c Scott Wood (1): powerpc/mpc85xx: add support for MMUv2 page sizes Shaohui Xie (1): powerpc/p2041: move Lanes mux to board early init Shaveta Leekha (3): powerpc/qixis: enable qixis dump command and add switch dumping command powerpc/b4860qds: Add support to dump switch settings on b4860qds board powerpc/t4240qds: Add support to dump switch settings on t4240qds board Shengzhou Liu (1): powerpc/t4240: Adding workaround errata A-005871 Timur Tabi (1): powerpc/t4qds: move VSC3316 config data from t4qds.h to t4qds.c Vakul Garg (1): powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto' Valentin Longchamp (2): powerpc/p2041: add RCW file for P2041RDB powerpc/p2041: set RCW and PBI files for .pbl build or P2041RDB York Sun (4): powerpc/mpc85xx: Reserve default boot page powerpc/t4240qds: Update IFC timing for NOR flash powerpc/b4860qds: Added Support for B4860QDS powerpc/mpc8xxx: Enable entering DDR debugging by key press MAINTAINERS |4 + arch/powerpc/cpu/mpc85xx/Makefile|5 + arch/powerpc/cpu/mpc85xx/b4860_ids.c |6 + arch/powerpc/cpu/mpc85xx/b4860_serdes.c | 60 ++ arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c| 96 +++ arch/powerpc/cpu/mpc85xx/cmd_errata.c|4 + arch/powerpc/cpu/mpc85xx/cpu_init.c | 44 +- arch/powerpc/cpu/mpc85xx/fdt.c | 24 + arch/powerpc/cpu/mpc85xx/start.S |2 +- arch/powerpc/cpu/mpc85xx/tlb.c | 19 +- arch/powerpc/cpu/mpc8xxx/cpu.c |2 + arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |4 + arch/powerpc/cpu/mpc8xxx/ddr/ddr.h |3 +- arch/powerpc/cpu/mpc8xxx/ddr/interactive.c | 324 ++--- arch/powerpc/cpu/mpc8xxx/ddr/main.c |8 +- arch/powerpc/cpu/mpc8xxx/fdt.c | 78 +- arch/powerpc/include/asm/config_mpc85xx.h| 39 +- arch/powerpc/include/asm/immap_85xx.h| 34 +- arch/powerpc/include/asm/mmu.h | 52 +- arch/powerpc/include/asm/processor.h |2 + board/freescale/b4860qds/Makefile| 54 ++ board/freescale/b4860qds/b4860qds.c | 505 + board/freescale/b4860qds/b4860qds.h | 26 + board/freescale/b4860qds/b4860qds_crossbar_con.h | 67 ++ board/freescale/b4860qds/b4860qds_qixis.h| 37 + board/freescale/b4860qds/ddr.c | 190 + board/freescale/b4860qds/eth_b4860qds.c | 338 + board/freescale/b4860qds/law.c | 44 ++ board/freescale/b4860qds/pci.c | 39 + board/freescale/b4860qds/tlb.c | 127 board/freescale/bsc9132qds/Makefile | 52 ++ board/freescale/bsc9132qds/README| 150
Re: [U-Boot] [RFC Patch v6] Consolidate bool type
On Wed, Jan 30, 2013 at 03:09:56PM -0800, York Sun wrote: On 01/30/2013 02:53 PM, Allen Martin wrote: On Wed, Jan 30, 2013 at 11:47:57AM -0800, York Sun wrote: On 01/30/2013 11:40 AM, Allen Martin wrote: On Wed, Jan 30, 2013 at 10:37:30AM -0800, York Sun wrote: On 01/24/2013 05:00 PM, Allen Martin wrote: I think you can drop the RFC from your patch at this point. Built on all tegra20 and tegra30 devices with USE_PRIVATE_LIBGCC. Tested on seaboard (tegra20). I've also submitted your patch to my build regression script which will build all 1100+ boards against your patch and tell if there are any build regressions. I'll let you know the results tomorrow. Allen, Is any change needed? Hi York, sorry I forgot to get back to you. I ran your patch through all boards and so no warning or error build regressions. Looking at the logs it looks like I ran it on version 5 not version 6 of your patch though. I'll do another run tonight on version 6 and let you know the results. I don't anticipate any problems though as it looks like the only differences are dropping the python files and whitespace changes. Allen, Your help is greatly appreciated. York Compiled against all boards, no warning or error regressions detected. Tested on tegra20 trimslice and tegra30 cardhu. Acked-by: Allen Martin amar...@nvidia.com Thanks a lot, Allen. I will send v7 with RFC removed from subject and add your ack. York Thank you for taking on such a monster of a patch! Also, either my blackfin toolchain is broken, or every blackfin board doesn't compile (even without this patch). You may want to have someone who has a known working blackfin build check the patch too. -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] MIPS: simplify relocated _G_O_T_ address calculation
2013/1/30 Gabor Juhos juh...@openwrt.org: The difference between the address of the original and the relocated _GLOBAL_OFFSET_TABLE_ is always the same as the relocation offset. The relocation offset is already computed and it is available in the 's1/t6' register. Use that to adjust the relocated _G_O_T_ address, instead of calculating the offset again from the _gp value. Signed-off-by: Gabor Juhos juh...@openwrt.org Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com Cc: Xiangfu Liu xian...@openmobilefree.net --- Changes since v1: modify Xburst code as well This depends on the: 'MIPS: xburst: simplify relocation offset calculation' patch http://patchwork.ozlabs.org/patch/216934/ and supersedes this one: http://patchwork.ozlabs.org/patch/214350/ --- arch/mips/cpu/mips32/start.S |5 + arch/mips/cpu/mips64/start.S |5 + arch/mips/cpu/xburst/start.S |5 + 3 files changed, 3 insertions(+), 12 deletions(-) applied to u-boot-mips/master, thanks -- Best regards, Daniel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] MIPS: xburst: simplify relocation offset calculation
2013/1/30 Gabor Juhos juh...@openwrt.org: The current code uses four instructions and a temporary register to calculate the relocation offset and to adjust the gp register. The relocation offset can be calculated directly from the CONFIG_SYS_MONITOR_BASE constant and from the destination address. The resulting offset can be used to adjust the gp pointer. This approach makes the code a bit simpler because it needs two instructions only. Signed-off-by: Gabor Juhos juh...@openwrt.org Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com Cc: Xiangfu Liu xian...@openmobilefree.net --- arch/mips/cpu/xburst/start.S | 12 +++- 1 file changed, 3 insertions(+), 9 deletions(-) applied to u-boot-mips/master, thanks -- Best regards, Daniel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] MIPS: remove OUTPUT_FORMAT from linker scripts
2013/1/30 Gabor Juhos juh...@openwrt.org: The OUTPUT_FORMAT command in linker scripts was always misused due to some endianess and toolchain problems. Use GCC flags to ensure proper output format, and get rid of the OUTPUT_FORMAT commands in the board specific u-boot.lds files. Signed-off-by: Gabor Juhos juh...@openwrt.org Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com Cc: Stefan Roese s...@denx.de Cc: Wolfgang Denk w...@denx.de Cc: Xiangfu Liu xian...@openmobilefree.net --- arch/mips/cpu/mips32/config.mk |6 ++ arch/mips/cpu/xburst/config.mk |6 ++ board/dbau1x00/u-boot.lds |4 board/incaip/u-boot.lds|4 board/micronas/vct/u-boot.lds |1 - board/pb1x00/u-boot.lds|4 board/qemu-mips/u-boot.lds |8 board/qi/qi_lb60/u-boot.lds|2 -- 8 files changed, 12 insertions(+), 23 deletions(-) applied to u-boot-mips/master, thanks -- Best regards, Daniel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/7] MIPS: use an unified u-boot.lds script
2013/1/30 Gabor Juhos juh...@openwrt.org: This patch-set adds an unfied u-boot.lds file for the MIPS architecture, and removes the linker scripts of the individual boards. The series depends on the following patch: MIPS: remove OUTPUT_FORMAT from linker scripts http://patchwork.ozlabs.org/patch/216892/ Gabor Juhos (7): MIPS: add unified u-boot.lds file MIPS: qemu-mips: use the unified u-boot.lds script MIPS: pb1x00: remove custom u-boot.lds script MIPS: vct: remove custom u-boot.lds script MIPS: incaip: remove custom u-boot.lds script MIPS: dbau1x00: remove custom u-boot.lds script MIPS: qi_lb60: remove custom u-boot.lds script arch/mips/cpu/u-boot.lds | 84 + board/dbau1x00/u-boot.lds | 65 --- board/incaip/u-boot.lds | 65 --- board/micronas/vct/u-boot.lds | 68 - board/pb1x00/u-boot.lds | 65 --- board/qemu-mips/u-boot.lds| 70 -- board/qi/qi_lb60/u-boot.lds | 61 -- 7 files changed, 84 insertions(+), 394 deletions(-) create mode 100644 arch/mips/cpu/u-boot.lds delete mode 100644 board/dbau1x00/u-boot.lds delete mode 100644 board/incaip/u-boot.lds delete mode 100644 board/micronas/vct/u-boot.lds delete mode 100644 board/pb1x00/u-boot.lds delete mode 100644 board/qemu-mips/u-boot.lds delete mode 100644 board/qi/qi_lb60/u-boot.lds all patches in this series applied to u-boot-mips/master, thanks -- Best regards, Daniel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [GIT PULL] u-boot-mips/master
On Thu, Jan 31, 2013 at 01:21:39AM +0100, Daniel Schwierzeck wrote:
The following changes since commit 54b08efcf2f4ff532ce99c53f341a59c193331a5:
README.mips: update known issues and TODOs (2013-01-16 10:52:08 +0100)
are available in the git repository at:
git://git.denx.de/u-boot-mips.git master
for you to fetch changes up to e93b98e216831d56b3fb0150f9723b1a15fb42a2:
MIPS: qi_lb60: remove custom u-boot.lds script (2013-01-31 00:27:58 +0100)
Gabor Juhos (18):
MIPS: use inline directive for __in*s functions
MIPS: convert IO port accessor functions to 'static inline'
MIPS: start{, 64}.S: fill branch delay slots with NOP instructions
MIPS: start.S: fix boundary check in relocate_code
MIPS: start.S: set sp register directly
MIPS: start.S: save reused arguments earlier in relocate_code
MIPS: start.S: simplify relocation offset calculation
MIPS: start.S: don't save flush_cache parameters in advance
MIPS: simplify relocated _G_O_T_ address calculation
MIPS: xburst: simplify relocation offset calculation
MIPS: remove OUTPUT_FORMAT from linker scripts
MIPS: add unified u-boot.lds file
MIPS: qemu-mips: use the unified u-boot.lds script
MIPS: pb1x00: remove custom u-boot.lds script
MIPS: vct: remove custom u-boot.lds script
MIPS: incaip: remove custom u-boot.lds script
MIPS: dbau1x00: remove custom u-boot.lds script
MIPS: qi_lb60: remove custom u-boot.lds script
arch/mips/cpu/mips32/config.mk | 6 ++
arch/mips/cpu/mips32/start.S | 41
+
arch/mips/cpu/mips64/start.S | 40
{board/micronas/vct = arch/mips/cpu}/u-boot.lds | 45
++---
arch/mips/cpu/xburst/config.mk | 6 ++
arch/mips/cpu/xburst/start.S | 19 +--
arch/mips/include/asm/io.h | 8
board/dbau1x00/u-boot.lds| 69
-
board/incaip/u-boot.lds | 69
-
board/pb1x00/u-boot.lds | 69
-
board/qemu-mips/u-boot.lds | 78
--
board/qi/qi_lb60/u-boot.lds | 63
---
12 files changed, 76 insertions(+), 437 deletions(-)
rename {board/micronas/vct = arch/mips/cpu}/u-boot.lds (73%)
delete mode 100644 board/dbau1x00/u-boot.lds
delete mode 100644 board/incaip/u-boot.lds
delete mode 100644 board/pb1x00/u-boot.lds
delete mode 100644 board/qemu-mips/u-boot.lds
delete mode 100644 board/qi/qi_lb60/u-boot.lds
Applied to u-boot/master, thanks!
--
Tom
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Re: [U-Boot] [PATCH v2] arm: fix CONFIG_DELAY_ENVIRONMENT to act like it claims in the README
On Wed, Jan 30, 2013 at 03:04:53PM -0800, Allen Martin wrote: On Tue, Jan 22, 2013 at 06:12:47AM -0800, Simon Glass wrote: On Tue, Jan 22, 2013 at 2:15 AM, Lucas Stach d...@lynxeye.de wrote: No one expects to end up in a delayed environment if CONFIG_DELAY_ENVIRONMENT isn't defined. Signed-off-by: Lucas Stach d...@lynxeye.de Good with me, and solves the immediate problem. Thanks for doing the patch. Acked-by: Simon Glass s...@chromium.org Adding Tom Rini and Albert. What's the best way to get this up to u-boot/master as quickly as possible? Environment is broken on all boards that use fdt until this goes in. I can just grab this directly since everyone is happy. now. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] MIPS: start.S: unify and simplify reset vector handling
From: Daniel Schwierzeck daniel.schwierz...@gmail.com Adopt reset vector handling from Yamon. Signed-off-by: Daniel Schwierzeck daniel.schwierz...@gmail.com --- arch/mips/cpu/mips32/start.S | 185 +-- arch/mips/cpu/mips64/start.S | 55 +++-- 2 files changed, 64 insertions(+), 176 deletions(-) diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index 65acf7d..a7cd2c4 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -47,19 +47,16 @@ .setpop .endm -#define RVECENT(f,n) \ - b f; nop -#define XVECENT(f,bev) \ - b f ; \ - li k0,bev - .set noreorder .globl _start .text _start: - RVECENT(reset,0)# U-boot entry point - RVECENT(reset,1)# software reboot + /* U-boot entry point */ + b reset +nop +nop +nop #ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG /* * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to @@ -71,139 +68,40 @@ _start: .word CONFIG_SYS_XWAY_EBU_BOOTCFG .word 0x #else - RVECENT(romReserved,2) + .word 0x + .word 0x #endif - RVECENT(romReserved,3) - RVECENT(romReserved,4) - RVECENT(romReserved,5) - RVECENT(romReserved,6) - RVECENT(romReserved,7) - RVECENT(romReserved,8) - RVECENT(romReserved,9) - RVECENT(romReserved,10) - RVECENT(romReserved,11) - RVECENT(romReserved,12) - RVECENT(romReserved,13) - RVECENT(romReserved,14) - RVECENT(romReserved,15) - RVECENT(romReserved,16) - RVECENT(romReserved,17) - RVECENT(romReserved,18) - RVECENT(romReserved,19) - RVECENT(romReserved,20) - RVECENT(romReserved,21) - RVECENT(romReserved,22) - RVECENT(romReserved,23) - RVECENT(romReserved,24) - RVECENT(romReserved,25) - RVECENT(romReserved,26) - RVECENT(romReserved,27) - RVECENT(romReserved,28) - RVECENT(romReserved,29) - RVECENT(romReserved,30) - RVECENT(romReserved,31) - RVECENT(romReserved,32) - RVECENT(romReserved,33) - RVECENT(romReserved,34) - RVECENT(romReserved,35) - RVECENT(romReserved,36) - RVECENT(romReserved,37) - RVECENT(romReserved,38) - RVECENT(romReserved,39) - RVECENT(romReserved,40) - RVECENT(romReserved,41) - RVECENT(romReserved,42) - RVECENT(romReserved,43) - RVECENT(romReserved,44) - RVECENT(romReserved,45) - RVECENT(romReserved,46) - RVECENT(romReserved,47) - RVECENT(romReserved,48) - RVECENT(romReserved,49) - RVECENT(romReserved,50) - RVECENT(romReserved,51) - RVECENT(romReserved,52) - RVECENT(romReserved,53) - RVECENT(romReserved,54) - RVECENT(romReserved,55) - RVECENT(romReserved,56) - RVECENT(romReserved,57) - RVECENT(romReserved,58) - RVECENT(romReserved,59) - RVECENT(romReserved,60) - RVECENT(romReserved,61) - RVECENT(romReserved,62) - RVECENT(romReserved,63) - XVECENT(romExcHandle,0x200) # bfc00200: R4000 tlbmiss vector - RVECENT(romReserved,65) - RVECENT(romReserved,66) - RVECENT(romReserved,67) - RVECENT(romReserved,68) - RVECENT(romReserved,69) - RVECENT(romReserved,70) - RVECENT(romReserved,71) - RVECENT(romReserved,72) - RVECENT(romReserved,73) - RVECENT(romReserved,74) - RVECENT(romReserved,75) - RVECENT(romReserved,76) - RVECENT(romReserved,77) - RVECENT(romReserved,78) - RVECENT(romReserved,79) - XVECENT(romExcHandle,0x280) # bfc00280: R4000 xtlbmiss vector - RVECENT(romReserved,81) - RVECENT(romReserved,82) - RVECENT(romReserved,83) - RVECENT(romReserved,84) - RVECENT(romReserved,85) - RVECENT(romReserved,86) - RVECENT(romReserved,87) - RVECENT(romReserved,88) - RVECENT(romReserved,89) - RVECENT(romReserved,90) - RVECENT(romReserved,91) - RVECENT(romReserved,92) - RVECENT(romReserved,93) - RVECENT(romReserved,94) - RVECENT(romReserved,95) - XVECENT(romExcHandle,0x300) # bfc00300: R4000 cache vector - RVECENT(romReserved,97) - RVECENT(romReserved,98) - RVECENT(romReserved,99) - RVECENT(romReserved,100) - RVECENT(romReserved,101) - RVECENT(romReserved,102) - RVECENT(romReserved,103) - RVECENT(romReserved,104) - RVECENT(romReserved,105) - RVECENT(romReserved,106) - RVECENT(romReserved,107) - RVECENT(romReserved,108) - RVECENT(romReserved,109) - RVECENT(romReserved,110) - RVECENT(romReserved,111) - XVECENT(romExcHandle,0x380) # bfc00380: R4000 general vector -
Re: [U-Boot] [U-Boot, v2] arm: fix CONFIG_DELAY_ENVIRONMENT to act like it claims in the README
On Tue, Jan 22, 2013 at 12:15:49AM -, Lucas Stach wrote: No one expects to end up in a delayed environment if CONFIG_DELAY_ENVIRONMENT isn't defined. Signed-off-by: Lucas Stach d...@lynxeye.de Acked-by: Simon Glass s...@chromium.org Acked-by: Allen Martin amar...@nvidia.com Applied to u-boot/master, thanks! -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] arm: fix CONFIG_DELAY_ENVIRONMENT to act like it claims in the README
On Wed, Jan 30, 2013 at 04:31:42PM -0800, Tom Rini wrote: * PGP Signed by an unknown key On Wed, Jan 30, 2013 at 03:04:53PM -0800, Allen Martin wrote: On Tue, Jan 22, 2013 at 06:12:47AM -0800, Simon Glass wrote: On Tue, Jan 22, 2013 at 2:15 AM, Lucas Stach d...@lynxeye.de wrote: No one expects to end up in a delayed environment if CONFIG_DELAY_ENVIRONMENT isn't defined. Signed-off-by: Lucas Stach d...@lynxeye.de Good with me, and solves the immediate problem. Thanks for doing the patch. Acked-by: Simon Glass s...@chromium.org Adding Tom Rini and Albert. What's the best way to get this up to u-boot/master as quickly as possible? Environment is broken on all boards that use fdt until this goes in. I can just grab this directly since everyone is happy. now. That would be great, thanks! -Allen -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] MIPS: start.S: remove obsolete 64 bit handling in setup_c0_status
From: Daniel Schwierzeck daniel.schwierz...@gmail.com Signed-off-by: Daniel Schwierzeck daniel.schwierz...@gmail.com --- arch/mips/cpu/mips32/start.S | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index 51ce914..65acf7d 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -47,14 +47,6 @@ .setpop .endm - .macro setup_c0_status_reset -#ifdef CONFIG_64BIT - setup_c0_status ST0_KX 0 -#else - setup_c0_status 0 0 -#endif - .endm - #define RVECENT(f,n) \ b f; nop #define XVECENT(f,bev) \ @@ -222,7 +214,7 @@ reset: /* WP(Watch Pending), SW0/1 should be cleared */ mtc0zero, CP0_CAUSE - setup_c0_status_reset + setup_c0_status 0 0 /* Init Timer */ mtc0zero, CP0_COUNT -- 1.8.1.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] MMC - Error detected in status(0x208100)!
Dear Jagannadha, Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki at xilinx.com writes: Hi Andy, The latest patch mmc: Properly determine maximum supported bus width (sha1: 7798f6dbd5e1a3030ed81a81da5dfb57c3307cac) is causing some error status issue on zynq platform with MMC Plus cards. Here the out what I get with inclusion of this patch on u-boot tree. zynq-uboot mmcinfo Error detected in status(0x208100)! Device: zynq_sdhci Manufacturer ID: 1e OEM: Name: MMC Tran Speed: 5200 Rd Block Len: 512 MMC version 4.0 High Capacity: No Capacity: 1.9 GiB Bus Width: 4-bit When I revert this path, I am unable to see the status error. zynq-uboot mmcinfo Device: zynq_sdhci Manufacturer ID: 1e OEM: Name: MMC Tran Speed: 5200 Rd Block Len: 512 MMC version 4.0 High Capacity: No Capacity: 1.9 GiB Bus Width: 12-bit I think the above one is also a buggy as my controller is unable to support 12-bit bus width.? I've been using the latest u-boot (v2013.01) on ML507 with a custom SDHCI IP. No problems detected with this patch. The output of both patched and unpatched u-boot seems to be correct. Except for the Data CRC Error (bit 21) in the patched version. Several things to check: 1) Verify the controller settings on both patched and unpatched u-boot. The printf()s are just prints some IPs (like the one I'm using) don't allow changing the register value on some conditions (ie during CMD_INHIBIT and/or DAT_INHIBIT). This would make the printf()s look correct but the actual register value is incorrect. 2) Try lowering your SDCLK (ie 25Mhz High-speed mode). 3) Try disabling High-speed mode (which limits you to 25MHz Legacy mode). All the best, Rommel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mmc: check the revision for sd3.0
Dear Jaehoon, Jaehoon Chung jh80.chung at samsung.com writes: Support to check whether the SD3.0 or not. Signed-off-by: Jaehoon Chung jh80.chung at samsung.com Signed-off-by: Kyungmin Park kyungmin.park at samsung.com --- drivers/mmc/mmc.c |2 ++ include/mmc.h |1 + 2 files changed, 3 insertions(+), 0 deletions(-) Tested-by: Rommel Custodio sessya...@gmail.com Note: The change only reflects in the output of mmcinfo. The functionality of mmc_send_if_cond() and sd_send_op_cond() is unaffected. All the best, Rommel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] env: Allow accessing non-mtd devices
In certain cases, memory device is present as flat file or block device (via
mmc or mtdblock layer). Do not attempt MTD operations against it.
---
tools/env/fw_env.c | 21 -
tools/env/fw_env.config |3 +++
2 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 37b60b8..0d8052d 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -838,7 +838,7 @@ static int flash_write_buf (int dev, int fd, void *buf,
size_t count,
ioctl (fd, MEMUNLOCK, erase);
/* Dataflash does not need an explicit erase cycle */
- if (mtd_type != MTD_DATAFLASH)
+ if (mtd_type mtd_type != MTD_DATAFLASH)
if (ioctl (fd, MEMERASE, erase) != 0) {
fprintf (stderr, MTD erase error on %s: %s\n,
DEVNAME (dev),
@@ -949,23 +949,34 @@ static int flash_write (int fd_current, int fd_target,
int dev_target)
static int flash_read (int fd)
{
struct mtd_info_user mtdinfo;
+ struct stat st;
int rc;
- rc = ioctl (fd, MEMGETINFO, mtdinfo);
+ rc = fstat (fd, st);
if (rc 0) {
- perror (Cannot get MTD information);
+ perror (Cannot access MTD device);
return -1;
}
+ if (S_ISCHR (st.st_mode)) {
+ rc = ioctl (fd, MEMGETINFO, mtdinfo);
+ if (rc 0) {
+ perror (Cannot get MTD information);
+ return -1;
+ }
+ } else {
+ memset (mtdinfo, 0, sizeof (mtdinfo));
+ }
+
if (mtdinfo.type != MTD_NORFLASH
mtdinfo.type != MTD_NANDFLASH
- mtdinfo.type != MTD_DATAFLASH) {
+ mtdinfo.type != MTD_DATAFLASH
+ mtdinfo.type) {
fprintf (stderr, Unsupported flash type %u\n, mtdinfo.type);
return -1;
}
DEVTYPE(dev_current) = mtdinfo.type;
-
rc = flash_read_buf(dev_current, fd, environment.image, CUR_ENVSIZE,
DEVOFFSET (dev_current), mtdinfo.type);
diff --git a/tools/env/fw_env.config b/tools/env/fw_env.config
index 8e21d5a..c086512 100644
--- a/tools/env/fw_env.config
+++ b/tools/env/fw_env.config
@@ -17,3 +17,6 @@
# NAND example
#/dev/mtd0 0x4000 0x4000 0x2
2
+
+# Block device example
+#/dev/mmcblk0 0xc 0x2
--
1.7.1
___
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[U-Boot] [PATCH 0/7] ARM: OMAP4+: Cleanup clocks, control and emif code
This series is intended to cleanup code which is duplicated across soc specific files. This is accomplished by moving soc specifc data to one place and having the code common. This helps in avoiding un necessary cpu checks and minimal code addition for future socs. Tested this on OMAP5 ES1.0, OMAP4460 Panda boards and verified MAKEALL for all armv7 boards. Lokesh Vutla (4): ARM: OMAP4+: emif: Detect SDRAM from SDRAM config register ARM: OMAP4+: Cleanup emif specific files ARM: OMAP4+: Make control module register structure generic ARM: OMAP5: Clean up iosettings code R Sricharan (3): ARM: OMAP4+: Change the PRCM structure prototype common for all Socs ARM: OMAP4+: Cleanup the clocks layer ARM: OMAP4+: Clean up the pmic code arch/arm/cpu/armv7/omap-common/clocks-common.c | 284 arch/arm/cpu/armv7/omap-common/emif-common.c | 71 ++- arch/arm/cpu/armv7/omap-common/hwinit-common.c | 10 +- arch/arm/cpu/armv7/omap-common/vc.c| 11 +- arch/arm/cpu/armv7/omap4/Makefile |3 +- arch/arm/cpu/armv7/omap4/clocks.c | 517 -- arch/arm/cpu/armv7/omap4/hw_data.c | 461 +++ arch/arm/cpu/armv7/omap4/hwinit.c | 36 +- arch/arm/cpu/armv7/omap4/prcm-regs.c | 287 arch/arm/cpu/armv7/omap4/sdram_elpida.c| 16 +- arch/arm/cpu/armv7/omap5/Makefile |3 +- arch/arm/cpu/armv7/omap5/clocks.c | 494 - arch/arm/cpu/armv7/omap5/hw_data.c | 465 arch/arm/cpu/armv7/omap5/hwinit.c | 131 +++--- arch/arm/cpu/armv7/omap5/prcm-regs.c | 352 +++ arch/arm/cpu/armv7/omap5/sdram.c | 119 +++-- arch/arm/include/asm/arch-omap4/clocks.h | 562 ++-- arch/arm/include/asm/arch-omap4/omap.h | 33 +- arch/arm/include/asm/arch-omap4/sys_proto.h|4 +- arch/arm/include/asm/arch-omap5/clocks.h | 506 + arch/arm/include/asm/arch-omap5/omap.h | 96 +--- arch/arm/include/asm/arch-omap5/sys_proto.h|5 +- arch/arm/include/asm/emif.h| 18 +- arch/arm/include/asm/omap_common.h | 482 drivers/mmc/omap_hsmmc.c | 25 +- include/configs/omap5_evm.h|1 + 26 files changed, 2535 insertions(+), 2457 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap4/hw_data.c create mode 100644 arch/arm/cpu/armv7/omap4/prcm-regs.c create mode 100644 arch/arm/cpu/armv7/omap5/hw_data.c create mode 100644 arch/arm/cpu/armv7/omap5/prcm-regs.c -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/7] ARM: OMAP4+: emif: Detect SDRAM from SDRAM config register
From: Lokesh Vutla lokeshvu...@ti.com
Now SDRAM initialization is done on the basis of omap revision.
Instead this should be done on basis of SDRAM type read from
EMIF_SDRAM_CONFIG register. This will be helpful to avoid
unnessecary cpu checks for new boards
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c | 10 +-
arch/arm/cpu/armv7/omap-common/emif-common.c | 21 +
arch/arm/cpu/armv7/omap5/hwinit.c |2 +-
arch/arm/include/asm/emif.h|6 ++
4 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c
b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index b1fd277..0b818b8 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -36,6 +36,7 @@
#include asm/arch/sys_proto.h
#include asm/utils.h
#include asm/omap_gpio.h
+#include asm/emif.h
#ifndef CONFIG_SPL_BUILD
/*
@@ -299,7 +300,7 @@ static void setup_dplls(void)
* Core DPLL will be locked after setting up EMIF
* using the FREQ_UPDATE method(freq_update_core())
*/
- if (omap_revision() != OMAP5432_ES1_0)
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
do_setup_dpll(prcm-cm_clkmode_dpll_core, params,
DPLL_NO_LOCK, core);
else
@@ -414,6 +415,13 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
vcore_reg, offset_code))
printf(Scaling voltage failed for 0x%x\n, vcore_reg);
+
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
+ /* Configure LDO SRAM magic bits */
+ writel(2, (*prcm)-prm_sldo_core_setup);
+ writel(2, (*prcm)-prm_sldo_mpu_setup);
+ writel(2, (*prcm)-prm_sldo_mm_setup);
+ }
}
static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c
b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 88253cf..8864abc 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -66,6 +66,19 @@ inline u32 emif_num(u32 base)
return 0;
}
+/*
+ * Get SDRAM type connected to EMIF.
+ * Assuming similar SDRAM parts are connected to both EMIF's
+ * which is typically the case. So it is sufficient to get
+ * SDRAM type from EMIF1.
+ */
+u32 emif_sdram_type()
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+
+ return (readl(emif-emif_sdram_config)
+ EMIF_REG_SDRAM_TYPE_MASK) EMIF_REG_SDRAM_TYPE_SHIFT;
+}
static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
{
@@ -1079,7 +1092,7 @@ static void do_sdram_init(u32 base)
* OPP to another)
*/
if (!(in_sdram || warm_reset())) {
- if (omap_revision() != OMAP5432_ES1_0)
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
lpddr2_init(base, regs);
else
ddr3_init(base, regs);
@@ -1264,7 +1277,7 @@ void dmm_init(u32 base)
void sdram_init(void)
{
u32 in_sdram, size_prog, size_detect;
- u32 omap_rev = omap_revision();
+ u32 sdram_type = emif_sdram_type();
debug(sdram_init()\n);
@@ -1275,7 +1288,7 @@ void sdram_init(void)
debug(in_sdram = %d\n, in_sdram);
if (!(in_sdram || warm_reset())) {
- if (omap_rev != OMAP5432_ES1_0)
+ if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
bypass_dpll(prcm-cm_clkmode_dpll_core);
else
writel(CM_DLL_CTRL_NO_OVERRIDE, prcm-cm_dll_ctrl);
@@ -1298,7 +1311,7 @@ void sdram_init(void)
}
/* for the shadow registers to take effect */
- if (omap_rev != OMAP5432_ES1_0)
+ if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
freq_update_core();
/* Do some testing after the init */
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c
b/arch/arm/cpu/armv7/omap5/hwinit.c
index d0c3ff7..4def422 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -191,7 +191,7 @@ void do_io_settings(void)
(sc_fast 17) | (sc_fast 14);
writel(io_settings, (ioregs_base-control_smart3io_padconf_1));
- if (omap_revision() = OMAP5430_ES1_0)
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
io_settings_lpddr2();
else
io_settings_ddr3();
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index ed251ec..0824a80 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -1027,6 +1027,11 @@ extern const u32
[U-Boot] [PATCH 5/7] ARM: OMAP4+: Cleanup emif specific files
From: Lokesh Vutla lokeshvu...@ti.com
Removing the duplicated code in ddr3 initialization.
Also creating structure for lpddr2 mode registers to
avoid unnessecary revision checks.
These change reduces code addition for future Socs.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap-common/emif-common.c | 46 ++
arch/arm/cpu/armv7/omap4/sdram_elpida.c | 16 +++-
arch/arm/cpu/armv7/omap5/sdram.c | 119 +-
arch/arm/include/asm/emif.h | 12 ++-
4 files changed, 108 insertions(+), 85 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c
b/arch/arm/cpu/armv7/omap-common/emif-common.c
index bb37cf3..0683b9f 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -123,11 +123,13 @@ void emif_reset_phy(u32 base)
static void do_lpddr2_init(u32 base, u32 cs)
{
u32 mr_addr;
+ const struct lpddr2_mr_regs *mr_regs;
+ get_lpddr2_mr_regs(mr_regs);
/* Wait till device auto initialization is complete */
while (get_mr(base, cs, LPDDR2_MR0) LPDDR2_MR0_DAI_MASK)
;
- set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
+ set_mr(base, cs, LPDDR2_MR10, mr_regs-mr10);
/*
* tZQINIT = 1 us
* Enough loops assuming a maximum of 2GHz
@@ -135,22 +137,18 @@ static void do_lpddr2_init(u32 base, u32 cs)
sdelay(2000);
- if (omap_revision() = OMAP5430_ES1_0)
- set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8);
- else
- set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
-
- set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
+ set_mr(base, cs, LPDDR2_MR1, mr_regs-mr1);
+ set_mr(base, cs, LPDDR2_MR16, mr_regs-mr16);
/*
* Enable refresh along with writing MR2
* Encoding of RL in MR2 is (RL - 2)
*/
mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
- set_mr(base, cs, mr_addr, RL_FINAL - 2);
+ set_mr(base, cs, mr_addr, mr_regs-mr2);
- if (omap_revision() = OMAP5430_ES1_0)
- set_mr(base, cs, LPDDR2_MR3, 0x1);
+ if (mr_regs-mr3 0)
+ set_mr(base, cs, LPDDR2_MR3, mr_regs-mr3);
}
static void lpddr2_init(u32 base, const struct emif_regs *regs)
@@ -268,9 +266,6 @@ static void ddr3_leveling(u32 base, const struct emif_regs
*regs)
static void ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- u32 *ext_phy_ctrl_base = 0;
- u32 *emif_ext_phy_ctrl_base = 0;
- u32 i = 0;
/*
* Set SDRAM_CONFIG and PHY control registers to locked frequency
@@ -290,27 +285,7 @@ static void ddr3_init(u32 base, const struct emif_regs
*regs)
writel(regs-ref_ctrl, emif-emif_sdram_ref_ctrl);
writel(regs-read_idle_ctrl, emif-emif_read_idlectrl);
- ext_phy_ctrl_base = (u32 *) (regs-emif_ddr_ext_phy_ctrl_1);
- emif_ext_phy_ctrl_base = (u32 *) (emif-emif_ddr_ext_phy_ctrl_1);
-
- /* Configure external phy control timing registers */
- for (i = 0; i EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
- writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
- }
-
- /*
-* external phy 6-24 registers do not change with
-* ddr frequency
-*/
- for (i = 0; i EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
- writel(ddr3_ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(ddr3_ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
- }
+ do_ext_phy_settings(base, regs);
/* enable leveling */
writel(regs-emif_rd_wr_lvl_rmp_ctl, emif-emif_rd_wr_lvl_rmp_ctl);
@@ -1109,9 +1084,6 @@ void emif_post_init_config(u32 base)
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
u32 omap_rev = omap_revision();
- if (omap_rev == OMAP5430_ES1_0)
- return;
-
/* reset phy on ES2.0 */
if (omap_rev == OMAP4430_ES2_0)
emif_reset_phy(base);
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index b9128fa..01da790 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -90,9 +90,6 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
.emif_ddr_phy_ctlr_1= 0x049ff418
};
-/* Dummy registers for OMAP44xx */
-const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
-
const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
[U-Boot] [PATCH 7/7] ARM: OMAP5: Clean up iosettings code
From: Lokesh Vutla lokeshvu...@ti.com
There is some code duplication in the ddr io settings code.
This is avoided by moving the data to a Soc specific place and
letting the code generic.
This avoids unnessecary code addition for future socs.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c | 36 +
arch/arm/cpu/armv7/omap5/hwinit.c | 75 +++
arch/arm/include/asm/arch-omap5/omap.h | 10
arch/arm/include/asm/arch-omap5/sys_proto.h |1 +
4 files changed, 78 insertions(+), 44 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index e1388bb..68e76d4 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -32,6 +32,7 @@
#include asm/arch/clocks.h
#include asm/omap_gpio.h
#include asm/io.h
+#include asm/emif.h
struct prcm_regs const **prcm =
(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
@@ -402,6 +403,24 @@ void enable_non_essential_clocks(void)
MODULE_CLKCTRL_MODULEMODE_SHIFT);
}
+const struct ctrl_ioregs ioregs_omap5430 = {
+ .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+ .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+ .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
+ .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
+ .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
+};
+
+const struct ctrl_ioregs ioregs_omap5432_es1 = {
+ .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ .ctrl_lpddr2ch = 0x0,
+ .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
+ .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
+ .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
+ .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+};
+
void hw_data_init(void)
{
u32 omap_rev = omap_revision();
@@ -427,3 +446,20 @@ void hw_data_init(void)
*ctrl = omap5_ctrl;
prcm_init(omap_vcores);
}
+
+void get_ioregs(const struct ctrl_ioregs **regs)
+{
+ u32 omap_rev = omap_revision();
+
+ switch (omap_rev) {
+ case OMAP5430_ES1_0:
+ *regs = ioregs_omap5430;
+ break;
+ case OMAP5432_ES1_0:
+ *regs = ioregs_omap5432_es1;
+ break;
+
+ default:
+ printf(\n INVALID OMAP REVISION );
+ }
+}
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c
b/arch/arm/cpu/armv7/omap5/hwinit.c
index 1863c69..dfc0e44 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -56,60 +56,47 @@ const struct gpio_bank *const omap_gpio_bank =
gpio_bank_54xx;
/* LPDDR2 specific IO settings */
static void io_settings_lpddr2(void)
{
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- (*ctrl)-control_ddrch1_0);
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- (*ctrl)-control_ddrch1_1);
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- (*ctrl)-control_ddrch2_0);
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- (*ctrl)-control_ddrch2_1);
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
- (*ctrl)-control_lpddr2ch1_0);
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
- (*ctrl)-control_lpddr2ch1_1);
- writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
- (*ctrl)-control_ddrio_0);
- writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
- (*ctrl)-control_ddrio_1);
- writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
- (*ctrl)-control_ddrio_2);
+ const struct ctrl_ioregs *ioregs;
+
+ get_ioregs(ioregs);
+ writel(ioregs-ctrl_ddrch, (*ctrl)-control_ddrch1_0);
+ writel(ioregs-ctrl_ddrch, (*ctrl)-control_ddrch1_1);
+ writel(ioregs-ctrl_ddrch, (*ctrl)-control_ddrch2_0);
+ writel(ioregs-ctrl_ddrch, (*ctrl)-control_ddrch2_1);
+ writel(ioregs-ctrl_lpddr2ch, (*ctrl)-control_lpddr2ch1_0);
+ writel(ioregs-ctrl_lpddr2ch, (*ctrl)-control_lpddr2ch1_1);
+ writel(ioregs-ctrl_ddrio_0, (*ctrl)-control_ddrio_0);
+ writel(ioregs-ctrl_ddrio_1, (*ctrl)-control_ddrio_1);
+ writel(ioregs-ctrl_ddrio_2, (*ctrl)-control_ddrio_2);
}
/* DDR3 specific IO settings */
static void io_settings_ddr3(void)
{
u32 io_settings = 0;
+ const struct ctrl_ioregs *ioregs;
- writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
- (*ctrl)-control_ddr3ch1_0);
-
[U-Boot] [PATCH 6/7] ARM: OMAP4+: Make control module register structure generic
From: Lokesh Vutla lokeshvu...@ti.com
A seperate omap_sys_ctrl_regs structure is defined for
omap4 5. If there is any change in control module for
any of the ES versions, a new structure needs to be created.
In order to remove this dependency, making the register
structure generic for all the omap4+ boards.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap-common/hwinit-common.c |5 +-
arch/arm/cpu/armv7/omap4/hw_data.c |4 +
arch/arm/cpu/armv7/omap4/hwinit.c | 36 -
arch/arm/cpu/armv7/omap4/prcm-regs.c | 20 +
arch/arm/cpu/armv7/omap5/hw_data.c |4 +-
arch/arm/cpu/armv7/omap5/hwinit.c | 102 +++-
arch/arm/cpu/armv7/omap5/prcm-regs.c | 74 +
arch/arm/include/asm/arch-omap4/omap.h | 31 +--
arch/arm/include/asm/arch-omap5/omap.h | 84 +--
arch/arm/include/asm/omap_common.h | 91 +
drivers/mmc/omap_hsmmc.c | 25 +++---
11 files changed, 269 insertions(+), 207 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index c93794d..277dc66 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -244,10 +244,7 @@ int checkboard(void)
*/
u32 get_device_type(void)
{
- struct omap_sys_ctrl_regs *ctrl =
- (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
-
- return (readl(ctrl-control_status)
+ return (readl((*ctrl)-control_status)
(DEVICE_TYPE_MASK)) DEVICE_TYPE_SHIFT;
}
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c
b/arch/arm/cpu/armv7/omap4/hw_data.c
index 17c1453..de449e4 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -37,6 +37,8 @@ struct prcm_regs const **prcm =
(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
struct dplls const **dplls_data =
(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
+struct omap_sys_ctrl_regs const **ctrl =
+ (struct omap_sys_ctrl_regs const **)OMAP4_SRAM_SCRATCH_SYS_CTRL;
/*
* The M N values in the following tables are created using the
@@ -454,4 +456,6 @@ void hw_data_init(void)
printf(\n INVALID OMAP REVISION );
}
+ *ctrl = omap4_ctrl;
+ prcm_init(omap_vcores);
}
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c
b/arch/arm/cpu/armv7/omap4/hwinit.c
index f4123aa..2db517b 100644
--- a/arch/arm/cpu/armv7/omap4/hwinit.c
+++ b/arch/arm/cpu/armv7/omap4/hwinit.c
@@ -57,10 +57,6 @@ const struct gpio_bank *const omap_gpio_bank =
gpio_bank_44xx;
void do_io_settings(void)
{
u32 lpddr2io;
- struct control_lpddr2io_regs *lpddr2io_regs =
- (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
- struct omap_sys_ctrl_regs *const ctrl =
- (struct omap_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
u32 omap4_rev = omap_revision();
@@ -72,20 +68,20 @@ void do_io_settings(void)
lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
/* EMIF1 */
- writel(lpddr2io, lpddr2io_regs-control_lpddr2io1_0);
- writel(lpddr2io, lpddr2io_regs-control_lpddr2io1_1);
+ writel(lpddr2io, (*ctrl)-control_lpddr2io1_0);
+ writel(lpddr2io, (*ctrl)-control_lpddr2io1_1);
/* No pull for GR10 as per hw team's recommendation */
writel(lpddr2io ~LPDDR2IO_GR10_WD_MASK,
- lpddr2io_regs-control_lpddr2io1_2);
- writel(CONTROL_LPDDR2IO_3_VAL, lpddr2io_regs-control_lpddr2io1_3);
+ (*ctrl)-control_lpddr2io1_2);
+ writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)-control_lpddr2io1_3);
/* EMIF2 */
- writel(lpddr2io, lpddr2io_regs-control_lpddr2io2_0);
- writel(lpddr2io, lpddr2io_regs-control_lpddr2io2_1);
+ writel(lpddr2io, (*ctrl)-control_lpddr2io2_0);
+ writel(lpddr2io, (*ctrl)-control_lpddr2io2_1);
/* No pull for GR10 as per hw team's recommendation */
writel(lpddr2io ~LPDDR2IO_GR10_WD_MASK,
- lpddr2io_regs-control_lpddr2io2_2);
- writel(CONTROL_LPDDR2IO_3_VAL, lpddr2io_regs-control_lpddr2io2_3);
+ (*ctrl)-control_lpddr2io2_2);
+ writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)-control_lpddr2io2_3);
/*
* Some of these settings (TRIM values) come from eFuse and are
@@ -93,16 +89,16 @@ void do_io_settings(void)
* calibration of the device. Do the software over-ride only if
* the device is not correctly trimmed
*/
- if (!(readl(ctrl-control_std_fuse_opp_bgap) 0x)) {
+ if (!(readl((*ctrl)-control_std_fuse_opp_bgap) 0x)) {
[U-Boot] [PATCH 4/7] ARM: OMAP4+: Clean up the pmic code
The pmic code is duplicated for OMAP 4 and 5.
Instead move the data to Soc specific place and
share the code.
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c | 79 +--
arch/arm/cpu/armv7/omap4/Makefile |1 -
arch/arm/cpu/armv7/omap4/clocks.c | 123
arch/arm/cpu/armv7/omap4/hw_data.c | 54 +++
arch/arm/cpu/armv7/omap5/Makefile |1 -
arch/arm/cpu/armv7/omap5/clocks.c | 97 ---
arch/arm/cpu/armv7/omap5/hw_data.c | 32 ++
arch/arm/include/asm/arch-omap4/clocks.h |5 -
arch/arm/include/asm/arch-omap5/clocks.h |4 -
arch/arm/include/asm/omap_common.h | 24 +
include/configs/omap5_evm.h|1 +
11 files changed, 163 insertions(+), 258 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c
b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 3bf4e7a..9a98873 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -443,44 +443,45 @@ static void setup_non_essential_dplls(void)
}
#endif
-void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv)
+u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
{
- u32 step;
- int ret = 0;
-
- /* See if we can first get the GPIO if needed */
- if (gpio = 0)
- ret = gpio_request(gpio, TPS62361_VSEL0_GPIO);
- if (ret 0) {
- printf(%s: gpio %d request failed %d\n, __func__, gpio, ret);
- gpio = -1;
- }
-
- /* Pull the GPIO low to select SET0 register, while we program SET1 */
- if (gpio = 0)
- gpio_direction_output(gpio, 0);
+ u32 offset_code;
- step = volt_mv - TPS62361_BASE_VOLT_MV;
- step /= 10;
+ volt_offset -= pmic-base_offset;
- debug(do_scale_tps62361: volt - %d step - 0x%x\n, volt_mv, step);
- if (omap_vc_bypass_send_value(TPS62361_I2C_SLAVE_ADDR, reg, step))
- puts(Scaling voltage failed for vdd_mpu from TPS\n);
+ offset_code = (volt_offset + pmic-step - 1) / pmic-step;
- /* Pull the GPIO high to select SET1 register */
- if (gpio = 0)
- gpio_direction_output(gpio, 1);
+ /*
+* Offset codes 1-6 all give the base voltage in Palmas
+* Offset code 0 switches OFF the SMPS
+*/
+ return offset_code + pmic-start_code;
}
-void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
+void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
{
u32 offset_code;
u32 offset = volt_mv;
+ int ret = 0;
+
+ /* See if we can first get the GPIO if needed */
+ if (pmic-gpio_en)
+ ret = gpio_request(pmic-gpio, PMIC_GPIO);
+
+ if (ret 0) {
+ printf(%s: gpio %d request failed %d\n, __func__,
+ pmic-gpio, ret);
+ return;
+ }
+
+ /* Pull the GPIO low to select SET0 register, while we program SET1 */
+ if (pmic-gpio_en)
+ gpio_direction_output(pmic-gpio, 0);
/* convert to uV for better accuracy in the calculations */
offset *= 1000;
- offset_code = get_offset_code(offset);
+ offset_code = get_offset_code(offset, pmic);
debug(do_scale_vcore: volt - %d offset_code - 0x%x\n, volt_mv,
offset_code);
@@ -489,7 +490,31 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
vcore_reg, offset_code))
printf(Scaling voltage failed for 0x%x\n, vcore_reg);
- if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
+ /* Pull the GPIO high to select SET1 register */
+ if (pmic-gpio_en)
+ gpio_direction_output(pmic-gpio, 1);
+}
+
+/*
+ * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
+ * We set the maximum voltages allowed here because Smart-Reflex is not
+ * enabled in bootloader. Voltage initialization in the kernel will set
+ * these to the nominal values after enabling Smart-Reflex
+ */
+void scale_vcores(struct vcores_data *vcores)
+{
+ omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
+
+ do_scale_vcore(vcores-core.addr, vcores-core.value,
+ vcores-core.pmic);
+
+ do_scale_vcore(vcores-mpu.addr, vcores-mpu.value,
+ vcores-mpu.pmic);
+
+ do_scale_vcore(vcores-mm.addr, vcores-mm.value,
+ vcores-mm.pmic);
+
+if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
/* Configure LDO SRAM magic bits */
writel(2, (*prcm)-prm_sldo_core_setup);
writel(2, (*prcm)-prm_sldo_mpu_setup);
@@ -663,7 +688,7 @@ void prcm_init(struct vcores_data *omap_vcores)
[U-Boot] [PATCH 1/5] ARM: OMAP5: Add silicon id support for ES2.0 revision.
Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap5/hwinit.c | 13 +++--
arch/arm/include/asm/arch-omap5/omap.h |2 ++
arch/arm/include/asm/armv7.h |1 +
arch/arm/include/asm/omap_common.h |2 ++
4 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c
b/arch/arm/cpu/armv7/omap5/hwinit.c
index dfc0e44..0d8c95d 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -216,8 +216,17 @@ void init_omap_revision(void)
break;
}
break;
- default:
- *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
+ case MIDR_CORTEX_A15_R2P2:
+ switch (readl(CONTROL_ID_CODE)) {
+ case OMAP5430_CONTROL_ID_CODE_ES2_0:
+ *omap_si_rev = OMAP5430_ES2_0;
+ break;
+ case OMAP5432_CONTROL_ID_CODE_ES2_0:
+ *omap_si_rev = OMAP5432_ES2_0;
+ break;
+ default:
+ *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
+ }
}
}
diff --git a/arch/arm/include/asm/arch-omap5/omap.h
b/arch/arm/include/asm/arch-omap5/omap.h
index 3eb7202..c79d833 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -57,7 +57,9 @@
/* To be verified */
#define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F
+#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F
#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
+#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
/* STD_FUSE_PROD_ID_1 */
#define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218)
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index ad9a875..a73630b 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -33,6 +33,7 @@
/* Cortex-A15 revisions */
#define MIDR_CORTEX_A15_R0P0 0x410FC0F0
+#define MIDR_CORTEX_A15_R2P2 0x412FC0F2
/* CCSIDR */
#define CCSIDR_LINE_SIZE_OFFSET0
diff --git a/arch/arm/include/asm/omap_common.h
b/arch/arm/include/asm/omap_common.h
index ef1621f..03cf7d7 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -542,4 +542,6 @@ static inline u32 omap_revision(void)
#define OMAP5430_SILICON_ID_INVALID0
#define OMAP5430_ES1_0 0x54300100
#define OMAP5432_ES1_0 0x54320100
+#define OMAP5430_ES2_0 0x54300200
+#define OMAP5432_ES2_0 0x54320200
#endif /* _OMAP_COMMON_H_ */
--
1.7.9.5
___
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[U-Boot] [PATCH 3/5] ARM: OMAP5: clocks: Add OPP settings required for OMAP543X ES2.0 soc
Change OPP settings as per the latest 0.4 version of
addendum for OMAP5430 ES2.0
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c |4 +
arch/arm/cpu/armv7/omap4/hw_data.c | 140 +++---
arch/arm/cpu/armv7/omap5/hw_data.c | 238 +++-
arch/arm/include/asm/arch-omap5/clocks.h |4 +
arch/arm/include/asm/omap_common.h |6 +-
5 files changed, 236 insertions(+), 156 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c
b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 9a98873..6e48138 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -103,10 +103,14 @@ void setup_post_dividers(u32 const base, const struct
dpll_params *params)
writel(params-m6_h13, dpll_regs-cm_div_m6_h13_dpll);
if (params-m7_h14 = 0)
writel(params-m7_h14, dpll_regs-cm_div_m7_h14_dpll);
+ if (params-h21 = 0)
+ writel(params-h21, dpll_regs-cm_div_h21_dpll);
if (params-h22 = 0)
writel(params-h22, dpll_regs-cm_div_h22_dpll);
if (params-h23 = 0)
writel(params-h23, dpll_regs-cm_div_h23_dpll);
+ if (params-h24 = 0)
+ writel(params-h24, dpll_regs-cm_div_h24_dpll);
}
static inline void do_bypass_dpll(u32 const base)
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c
b/arch/arm/cpu/armv7/omap4/hw_data.c
index de449e4..81af745 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -49,113 +49,113 @@ struct omap_sys_ctrl_regs const **ctrl =
/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */
static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
- {175, 2, 1, -1, -1, -1, -1, -1},/* 12 MHz */
- {700, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {125, 2, 1, -1, -1, -1, -1, -1},/* 16.8 MHz */
- {401, 10, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {350, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {700, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {638, 34, 1, -1, -1, -1, -1, -1}/* 38.4 MHz */
+ {175, 2, 1, -1, -1, -1, -1, -1, -1, -1},/* 12 MHz */
+ {700, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {125, 2, 1, -1, -1, -1, -1, -1, -1, -1},/* 16.8 MHz */
+ {401, 10, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {350, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {700, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {638, 34, 1, -1, -1, -1, -1, -1, -1, -1}/* 38.4 MHz */
};
/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
- {200, 2, 1, -1, -1, -1, -1, -1},/* 12 MHz */
- {800, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {619, 12, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {125, 2, 1, -1, -1, -1, -1, -1},/* 19.2 MHz */
- {400, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {800, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {200, 2, 1, -1, -1, -1, -1, -1, -1, -1},/* 12 MHz */
+ {800, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {619, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {125, 2, 1, -1, -1, -1, -1, -1, -1, -1},/* 19.2 MHz */
+ {400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {800, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{125, 5, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* dpll locked at 1200 MHz - MPU clk at 600 MHz */
static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
- {50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {250, 6, 1, -1, -1, -1, -1, -1},/* 16.8 MHz */
- {125, 3, 1, -1, -1, -1, -1, -1},/* 19.2 MHz */
- {300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {200, 8, 1, -1, -1, -1, -1, -1},/* 27 MHz */
- {125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+ {50, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {600, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {250, 6, 1, -1, -1, -1, -1, -1, -1, -1},/* 16.8 MHz */
+ {125, 3, 1, -1, -1, -1, -1, -1, -1, -1},/* 19.2 MHz */
+ {300, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {200, 8, 1, -1, -1, -1, -1, -1, -1, -1},/* 27 MHz */
+ {125, 7, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS]
[U-Boot] [PATCH 2/5] ARM: OMAP5: clock: Add the prcm register changes required for ES2.0
PRCM register addresses are changed from ES1.0 to ES2.0 due to
PER power domain getting moved to CORE power domain.
So adding the nessecary register changes for the same.
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c |4 +
arch/arm/cpu/armv7/omap5/prcm-regs.c | 283 ++
arch/arm/include/asm/omap_common.h |4 +
3 files changed, 291 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 68e76d4..86886d5 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -440,6 +440,10 @@ void hw_data_init(void)
omap_vcores = omap5432_volts;
break;
+ case OMAP5430_ES2_0:
+ *prcm = omap5_es2_prcm;
+ break;
+
default:
printf(\n INVALID OMAP REVISION );
}
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c
b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 07e7ade..5c4c985 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -350,3 +350,286 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
.control_efuse_12 = 0x4AE0CDF4,
.control_efuse_13 = 0x4AE0CDF8,
};
+
+struct prcm_regs const omap5_es2_prcm = {
+ /* cm1.ckgen */
+ .cm_clksel_core = 0x4a004100,
+ .cm_clksel_abe = 0x4a004108,
+ .cm_dll_ctrl = 0x4a004110,
+ .cm_clkmode_dpll_core = 0x4a004120,
+ .cm_idlest_dpll_core = 0x4a004124,
+ .cm_autoidle_dpll_core = 0x4a004128,
+ .cm_clksel_dpll_core = 0x4a00412c,
+ .cm_div_m2_dpll_core = 0x4a004130,
+ .cm_div_m3_dpll_core = 0x4a004134,
+ .cm_div_h11_dpll_core = 0x4a004138,
+ .cm_div_h12_dpll_core = 0x4a00413c,
+ .cm_div_h13_dpll_core = 0x4a004140,
+ .cm_div_h14_dpll_core = 0x4a004144,
+ .cm_ssc_deltamstep_dpll_core = 0x4a004148,
+ .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
+ .cm_div_h21_dpll_core = 0x4a004150,
+ .cm_div_h22_dpllcore = 0x4a004154,
+ .cm_div_h23_dpll_core = 0x4a004158,
+ .cm_div_h24_dpll_core = 0x4a00415c,
+ .cm_clkmode_dpll_mpu = 0x4a004160,
+ .cm_idlest_dpll_mpu = 0x4a004164,
+ .cm_autoidle_dpll_mpu = 0x4a004168,
+ .cm_clksel_dpll_mpu = 0x4a00416c,
+ .cm_div_m2_dpll_mpu = 0x4a004170,
+ .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
+ .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
+ .cm_bypclk_dpll_mpu = 0x4a00419c,
+ .cm_clkmode_dpll_iva = 0x4a0041a0,
+ .cm_idlest_dpll_iva = 0x4a0041a4,
+ .cm_autoidle_dpll_iva = 0x4a0041a8,
+ .cm_clksel_dpll_iva = 0x4a0041ac,
+ .cm_div_h11_dpll_iva = 0x4a0041b8,
+ .cm_div_h12_dpll_iva = 0x4a0041bc,
+ .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
+ .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
+ .cm_bypclk_dpll_iva = 0x4a0041dc,
+ .cm_clkmode_dpll_abe = 0x4a0041e0,
+ .cm_idlest_dpll_abe = 0x4a0041e4,
+ .cm_autoidle_dpll_abe = 0x4a0041e8,
+ .cm_clksel_dpll_abe = 0x4a0041ec,
+ .cm_div_m2_dpll_abe = 0x4a0041f0,
+ .cm_div_m3_dpll_abe = 0x4a0041f4,
+ .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
+ .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
+ .cm_clkmode_dpll_ddrphy = 0x4a004220,
+ .cm_idlest_dpll_ddrphy = 0x4a004224,
+ .cm_autoidle_dpll_ddrphy = 0x4a004228,
+ .cm_clksel_dpll_ddrphy = 0x4a00422c,
+ .cm_div_m2_dpll_ddrphy = 0x4a004230,
+ .cm_div_h11_dpll_ddrphy = 0x4a004238,
+ .cm_div_h12_dpll_ddrphy = 0x4a00423c,
+ .cm_div_h13_dpll_ddrphy = 0x4a004240,
+ .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
+ .cm_shadow_freq_config1 = 0x4a004260,
+ .cm_mpu_mpu_clkctrl = 0x4a004320,
+
+ /* cm1.dsp */
+ .cm_dsp_clkstctrl = 0x4a004400,
+ .cm_dsp_dsp_clkctrl = 0x4a004420,
+
+ /* cm1.abe */
+ .cm1_abe_clkstctrl = 0x4a004500,
+ .cm1_abe_l4abe_clkctrl = 0x4a004520,
+ .cm1_abe_aess_clkctrl = 0x4a004528,
+ .cm1_abe_pdm_clkctrl = 0x4a004530,
+ .cm1_abe_dmic_clkctrl = 0x4a004538,
+ .cm1_abe_mcasp_clkctrl = 0x4a004540,
+ .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
+ .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
+ .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
+ .cm1_abe_slimbus_clkctrl = 0x4a004560,
+ .cm1_abe_timer5_clkctrl = 0x4a004568,
+ .cm1_abe_timer6_clkctrl = 0x4a004570,
+ .cm1_abe_timer7_clkctrl = 0x4a004578,
+ .cm1_abe_timer8_clkctrl = 0x4a004580,
+ .cm1_abe_wdt3_clkctrl = 0x4a004588,
+
+
+
+ /* cm2.ckgen */
+ .cm_clksel_mpu_m3_iss_root = 0x4a008100,
+ .cm_clksel_usb_60mhz = 0x4a008104,
+ .cm_scale_fclk = 0x4a008108,
+ .cm_core_dvfs_perf1 = 0x4a008110,
+ .cm_core_dvfs_perf2 = 0x4a008114,
+ .cm_core_dvfs_perf3 = 0x4a008118,
+ .cm_core_dvfs_perf4 = 0x4a00811c,
+ .cm_core_dvfs_current = 0x4a008124,
+
[U-Boot] [PATCH 4/5] ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs
From: Lokesh Vutla lokeshvu...@ti.com
Add pre calculated timing settings of LPDDR2 and DDR3 memories
present in OMAP5430 and OMAP5432 ES2.0 versions.
Also adding the DDR pad io settings required for
OMAP543X SOCs here.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c | 13 ++
arch/arm/cpu/armv7/omap5/sdram.c | 75 +++-
arch/arm/include/asm/arch-omap5/omap.h |6 +++
arch/arm/include/asm/emif.h|1 +
4 files changed, 93 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 3a317dd..7d3e1bd 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -486,6 +486,16 @@ const struct ctrl_ioregs ioregs_omap5432_es1 = {
.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
};
+const struct ctrl_ioregs ioregs_omap5432_es2 = {
+ .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
+ .ctrl_lpddr2ch = 0x0,
+ .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
+ .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
+ .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
+ .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
+ .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+};
+
void hw_data_init(void)
{
u32 omap_rev = omap_revision();
@@ -530,6 +540,9 @@ void get_ioregs(const struct ctrl_ioregs **regs)
case OMAP5432_ES1_0:
*regs = ioregs_omap5432_es1;
break;
+ case OMAP5432_ES2_0:
+ *regs = ioregs_omap5432_es2;
+ break;
default:
printf(\n INVALID OMAP REVISION );
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 687800f..2ef7fcd 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -67,6 +67,25 @@ const struct emif_regs emif_regs_532_mhz_2cs = {
.emif_ddr_ext_phy_ctrl_5= 0x04010040
};
+const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
+ .sdram_config_init = 0x80800EBA,
+ .sdram_config = 0x808022BA,
+ .ref_ctrl = 0x081A,
+ .sdram_tim1 = 0x772F6873,
+ .sdram_tim2 = 0x304a129a,
+ .sdram_tim3 = 0x02f7e45f,
+ .read_idle_ctrl = 0x0005,
+ .zq_config = 0x100b3215,
+ .temp_alert_config = 0x08000a05,
+ .emif_ddr_phy_ctlr_1_init = 0x0E30400d,
+ .emif_ddr_phy_ctlr_1= 0x0E30400d,
+ .emif_ddr_ext_phy_ctrl_1= 0x04020080,
+ .emif_ddr_ext_phy_ctrl_2= 0x28C518A3,
+ .emif_ddr_ext_phy_ctrl_3= 0x518A3146,
+ .emif_ddr_ext_phy_ctrl_4= 0x0014628C,
+ .emif_ddr_ext_phy_ctrl_5= 0xC330CC33,
+};
+
const struct emif_regs emif_regs_266_mhz_2cs = {
.sdram_config_init = 0x80800EBA,
.sdram_config = 0x808022BA,
@@ -109,6 +128,29 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
.emif_rd_wr_exec_thresh = 0x0305
};
+const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
+ .sdram_config_init = 0x61851B32,
+ .sdram_config = 0x61851B32,
+ .ref_ctrl = 0x1035,
+ .sdram_tim1 = 0xCCCF36B3,
+ .sdram_tim2 = 0x308F7FDA,
+ .sdram_tim3 = 0x027F88A8,
+ .read_idle_ctrl = 0x0005,
+ .zq_config = 0x1007190B,
+ .temp_alert_config = 0x,
+ .emif_ddr_phy_ctlr_1_init = 0x0030400A,
+ .emif_ddr_phy_ctlr_1= 0x0034400A,
+ .emif_ddr_ext_phy_ctrl_1= 0x04040100,
+ .emif_ddr_ext_phy_ctrl_2= 0x,
+ .emif_ddr_ext_phy_ctrl_3= 0x,
+ .emif_ddr_ext_phy_ctrl_4= 0x,
+ .emif_ddr_ext_phy_ctrl_5= 0x4350D435,
+ .emif_rd_wr_lvl_rmp_win = 0x,
+ .emif_rd_wr_lvl_rmp_ctl = 0x8000,
+ .emif_rd_wr_lvl_ctl = 0x,
+ .emif_rd_wr_exec_thresh = 0x4305
+};
+
const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
@@ -125,8 +167,12 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const
struct emif_regs **regs)
case OMAP5432_ES1_0:
*regs = emif_regs_ddr3_532_mhz_1cs;
break;
+ case OMAP5430_ES2_0:
+ *regs = emif_regs_532_mhz_2cs_es2;
+ break;
+ case OMAP5432_ES2_0:
default:
-
[U-Boot] [PATCH 5/5] ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup
From: Lokesh Vutla lokeshvu...@ti.com
After power-up SRCOMP cells are by-passed by default in OMAP5.
Software has to enable these SRCOMP sells.
For ES2: All 5 SRCOMP cells needs to be enabled.
For ES1: Only 4 SRCOMP cells in core power domain are enabled.
The 1 in wkup domain is not enabled because smart i/os
of wkup domain work with default compensation code.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap-common/hwinit-common.c |6 ++
arch/arm/cpu/armv7/omap5/hwinit.c | 116
arch/arm/cpu/armv7/omap5/prcm-regs.c |5 +-
arch/arm/include/asm/arch-omap5/clocks.h |4 +
arch/arm/include/asm/arch-omap5/omap.h | 19
arch/arm/include/asm/arch-omap5/sys_proto.h|1 +
arch/arm/include/asm/omap_common.h |2 +
7 files changed, 152 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 277dc66..92109fa 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -35,6 +35,7 @@
#include asm/cache.h
#include asm/system.h
#include asm/omap_common.h
+#include linux/compiler.h
#define ARMV7_DCACHE_WRITEBACK 0xe
#defineARMV7_DOMAIN_CLIENT 1
@@ -106,6 +107,10 @@ void spl_display_print(void)
}
#endif
+void __weak srcomp_enable(void)
+{
+}
+
/*
* Routine: s_init
* Description: Does early system init of watchdog, muxing, andclocks
@@ -132,6 +137,7 @@ void s_init(void)
watchdog_init();
set_mux_conf_regs();
#ifdef CONFIG_SPL_BUILD
+ srcomp_enable();
setup_clocks_for_console();
gd = gdata;
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c
b/arch/arm/cpu/armv7/omap5/hwinit.c
index 0d8c95d..620b99a 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -32,6 +32,7 @@
#include asm/armv7.h
#include asm/arch/cpu.h
#include asm/arch/sys_proto.h
+#include asm/arch/clocks.h
#include asm/sizes.h
#include asm/utils.h
#include asm/arch/gpio.h
@@ -182,6 +183,121 @@ void do_io_settings(void)
writel(EFUSE_3, (*ctrl)-control_efuse_3);
writel(EFUSE_4, (*ctrl)-control_efuse_4);
}
+
+static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
+ {0x45, 0x1},/* 12 MHz */
+ {-1, -1}, /* 13 MHz */
+ {0x63, 0x2},/* 16.8 MHz */
+ {0x57, 0x2},/* 19.2 MHz */
+ {0x20, 0x1},/* 26 MHz */
+ {-1, -1}, /* 27 MHz */
+ {0x41, 0x3} /* 38.4 MHz */
+};
+
+void srcomp_enable(void)
+{
+ u32 srcomp_value, mul_factor, div_factor, clk_val, i;
+ u32 sysclk_ind = get_sys_clk_index();
+ u32 omap_rev= omap_revision();
+
+ mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
+ div_factor = srcomp_parameters[sysclk_ind].divide_factor;
+
+ for (i = 0; i 4; i++) {
+ srcomp_value = readl((*ctrl)-control_srcomp_north_side + i*4);
+ srcomp_value =
+ ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
+ srcomp_value |= (mul_factor MULTIPLY_FACTOR_XS_SHIFT) |
+ (div_factor DIVIDE_FACTOR_XS_SHIFT);
+ writel(srcomp_value, (*ctrl)-control_srcomp_north_side + i*4);
+ }
+
+ if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
+ clk_val = readl((*prcm)-cm_coreaon_io_srcomp_clkctrl);
+ clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
+ writel(clk_val, (*prcm)-cm_coreaon_io_srcomp_clkctrl);
+
+ for (i = 0; i 4; i++) {
+ srcomp_value =
+ readl((*ctrl)-control_srcomp_north_side + i*4);
+ srcomp_value = ~PWRDWN_XS_MASK;
+ writel(srcomp_value,
+ (*ctrl)-control_srcomp_north_side + i*4);
+
+ while (((readl((*ctrl)-control_srcomp_north_side + i*4)
+SRCODE_READ_XS_MASK)
+ SRCODE_READ_XS_SHIFT) == 0)
+ ;
+
+ srcomp_value =
+ readl((*ctrl)-control_srcomp_north_side + i*4);
+ srcomp_value = ~OVERRIDE_XS_MASK;
+ writel(srcomp_value,
+ (*ctrl)-control_srcomp_north_side + i*4);
+ }
+ } else {
+ srcomp_value = readl((*ctrl)-control_srcomp_east_side_wkup);
+ srcomp_value = ~(MULTIPLY_FACTOR_XS_MASK |
+ DIVIDE_FACTOR_XS_MASK);
+ srcomp_value |= (mul_factor MULTIPLY_FACTOR_XS_SHIFT) |
+ (div_factor DIVIDE_FACTOR_XS_SHIFT);
+
[U-Boot] [PATCH 0/5] ARM: OMAP5: Add support for OMAP543x ES2.0 Socs
ES2.0 is the latest silicon revision for OMAP543X socs. The SOC supports enhanced opps for MPU (up to 1.5GHz). This series essentially adds the support for both 5430 and 5432 versions. This is on top of the below U-Boot cleanup series. http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/152563 Lokesh Vutla (2): ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup R Sricharan (3): ARM: OMAP5: Add silicon id support for ES2.0 revision. ARM: OMAP5: clock: Add the prcm register changes required for ES2.0 ARM: OMAP5: clocks: Add OPP settings required for OMAP543X ES2.0 soc arch/arm/cpu/armv7/omap-common/clocks-common.c |4 + arch/arm/cpu/armv7/omap-common/hwinit-common.c |6 + arch/arm/cpu/armv7/omap4/hw_data.c | 140 ++-- arch/arm/cpu/armv7/omap5/hw_data.c | 255 ++--- arch/arm/cpu/armv7/omap5/hwinit.c | 129 ++- arch/arm/cpu/armv7/omap5/prcm-regs.c | 286 arch/arm/cpu/armv7/omap5/sdram.c | 75 ++- arch/arm/include/asm/arch-omap5/clocks.h |8 + arch/arm/include/asm/arch-omap5/omap.h | 27 +++ arch/arm/include/asm/arch-omap5/sys_proto.h|1 + arch/arm/include/asm/armv7.h |1 + arch/arm/include/asm/emif.h|1 + arch/arm/include/asm/omap_common.h | 14 +- 13 files changed, 787 insertions(+), 160 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/mpc85xx: add setting of clock-frequency for mpic node
Set the device tree property associated with the mpic source frequency. The frequency is used for mpic timer. Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com --- arch/powerpc/cpu/mpc85xx/fdt.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 3a268aa..f07d1cf 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -663,6 +663,11 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_CORENET do_fixup_by_compat_u32(blob, fsl,qoriq-clockgen-1.0, clock-frequency, CONFIG_SYS_CLK_FREQ, 1); + do_fixup_by_compat_u32(blob, fsl,mpic, + clock-frequency, get_bus_freq(0)/2, 1); +#else + do_fixup_by_compat_u32(blob, fsl,mpic, + clock-frequency, get_bus_freq(0), 1); #endif fdt_fixup_memory(blob, (u64)bd-bi_memstart, (u64)bd-bi_memsize); -- 1.7.5.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] env: Allow accessing non-mtd devices
Dear Lubomir Rintel,
In message 1359589584-19846-1-git-send-email-lkund...@v3.sk you wrote:
In certain cases, memory device is present as flat file or block device (via
mmc or mtdblock layer). Do not attempt MTD operations against it.
What exactly would be such cases?
diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 37b60b8..0d8052d 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -838,7 +838,7 @@ static int flash_write_buf (int dev, int fd, void *buf,
size_t count,
ioctl (fd, MEMUNLOCK, erase);
/* Dataflash does not need an explicit erase cycle */
- if (mtd_type != MTD_DATAFLASH)
+ if (mtd_type mtd_type != MTD_DATAFLASH)
This change appears to be redundant. If mtd_type is null, then this
is already caught iun te test mtd_type != MTD_DATAFLASH, isn't it?
- rc = ioctl (fd, MEMGETINFO, mtdinfo);
+ rc = fstat (fd, st);
if (rc 0) {
- perror (Cannot get MTD information);
+ perror (Cannot access MTD device);
I don't understand this. You talk about a MTD device here, but expect
that MEMGETINFO will not work on it? Please explain in which exact
circumstances such a situation wouldhappen.
if (mtdinfo.type != MTD_NORFLASH
mtdinfo.type != MTD_NANDFLASH
- mtdinfo.type != MTD_DATAFLASH) {
+ mtdinfo.type != MTD_DATAFLASH
+ mtdinfo.type) {
Again, this last line appears to be redundant.
}
DEVTYPE(dev_current) = mtdinfo.type;
-
rc = flash_read_buf(dev_current, fd, environment.image, CUR_ENVSIZE,
Please don't make such unrelated white space changes in this commit.
diff --git a/tools/env/fw_env.config b/tools/env/fw_env.config
index 8e21d5a..c086512 100644
--- a/tools/env/fw_env.config
+++ b/tools/env/fw_env.config
@@ -17,3 +17,6 @@
# NAND example
#/dev/mtd0 0x4000 0x4000 0x2
2
+
+# Block device example
+#/dev/mmcblk00xc 0x2
I don't see why one would use that. Please elucidate.
Please also make sure to run your patch through checkpatch - it
catches a number of space prohibited between function name and open
parenthesis warnings and tells you that your Signed-off-by: line is
missing.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
Conceptual integrity in turn dictates that the design must proceed
from one mind, or from a very small number of agreeing resonant
minds. - Frederick Brooks Jr., The Mythical Man Month
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Re: [U-Boot] [PATCH] serial/ns16550: don't generate functions for undefined ports
On Fri, Jan 18, 2013 at 7:42 PM, Scott Wood scottw...@freescale.com wrote:
This saved 640 bytes on MPC8536DS (a board with two of the six
ports defined).
Signed-off-by: Scott Wood scottw...@freescale.com
I noticed the same issue on SPL builds.
Ack.
-M
---
drivers/serial/serial_ns16550.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index fc01a3c..b92eef4 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -247,24 +247,36 @@ serial_setbrg_dev(unsigned int dev_index)
_serial_setbrg(dev_index);
}
+#if defined(CONFIG_SYS_NS16550_COM1)
DECLARE_ESERIAL_FUNCTIONS(1);
struct serial_device eserial1_device =
INIT_ESERIAL_STRUCTURE(1, eserial0);
+#endif
+#if defined(CONFIG_SYS_NS16550_COM2)
DECLARE_ESERIAL_FUNCTIONS(2);
struct serial_device eserial2_device =
INIT_ESERIAL_STRUCTURE(2, eserial1);
+#endif
+#if defined(CONFIG_SYS_NS16550_COM3)
DECLARE_ESERIAL_FUNCTIONS(3);
struct serial_device eserial3_device =
INIT_ESERIAL_STRUCTURE(3, eserial2);
+#endif
+#if defined(CONFIG_SYS_NS16550_COM4)
DECLARE_ESERIAL_FUNCTIONS(4);
struct serial_device eserial4_device =
INIT_ESERIAL_STRUCTURE(4, eserial3);
+#endif
+#if defined(CONFIG_SYS_NS16550_COM5)
DECLARE_ESERIAL_FUNCTIONS(5);
struct serial_device eserial5_device =
INIT_ESERIAL_STRUCTURE(5, eserial4);
+#endif
+#if defined(CONFIG_SYS_NS16550_COM6)
DECLARE_ESERIAL_FUNCTIONS(6);
struct serial_device eserial6_device =
INIT_ESERIAL_STRUCTURE(6, eserial5);
+#endif
__weak struct serial_device *default_serial_console(void)
{
--
1.7.9.5
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[U-Boot] [PATCH V3 0/7] Add splash screen for CM-T35
This patchset adds splash screen support for CM-T35. It includes the ability to initialize the display subsystem either using predefines (selected via env variable displaytype), or user supplied configuration options, also stored in an environment variables and pointed to by displaytype. The splash image data is currently read from NAND. As a preparation for the above functionality this patchset adds: - new DSS #defines - an option for board-specific splash screen preparation, which can be invoked in lcd_logo() right before displaying the splash screen (typical use case: load the image data from non-memory mapped storage in time for it to be displayed). - struct panel_config is extended to support setting the gfx_format dynamically - protection from data aborts due to unaligned bmp headers is added to lcd_logo's splashscreen section (I'm also looking into refining this protection later on). Changes in V3: - No unnecessary #defines in arch-omap3/dss.h [Wolfgang Denk] - Reworded patch 2 comment [Wolfgang Denk] - Used a #define for cmap addr [Wolfgang Denk] Changes in V2: - DSS #defines are defined shiften where possible [Jeroen Hofstee] - GFXFORMAT_RGB16 now passed to omap3_dss_panel_config() in a new field of panel_cfg. Updated existing panel_config structs to set this field to the value that was originally hardcoded into omap3_dss_panel_config(). [Jeroen Hofstee] - Used LCD_BPP for vl_bpix. [Jeroen Hofstee] - Added a comment to explain the choice of GFXFORMAT_RGB16. [Jeroen Hofstee] - Added an address check (and fix) to the address of splashimage in order to avoid alignment problems with bmp header. A similar check appears in board_splash_screen_prepare() for cm_t35. [Albert ARIBAUD] - Do not manually set gfx burst size to GFXBURSTSIZE16, as it is apparently not necessary. GFXBURSTSIZE* #defines were kept in patch 1 anyway in the hope they will be useful for someone. Nikita Kiryanov (7): omap3: add useful dss defines omap3: allow dynamic selection of gfx_format lcd: prevent unaligned memory access when displaying splash screen lcd: add option for board specific splash screen preparation cm-t35: add support for dvi displays cm-t35: add support for user defined lcd parameters cm-t35: add support for loading splash image from NAND README|8 + arch/arm/include/asm/arch-omap3/dss.h | 31 +++ board/cm_t35/Makefile |1 + board/cm_t35/cm_t35.c | 68 ++ board/cm_t35/display.c| 428 + board/htkw/mcx/mcx.c |1 + board/teejet/mt_ventoux/mt_ventoux.c |2 + board/ti/beagle/beagle.h |6 +- common/lcd.c | 23 ++ drivers/video/omap3_dss.c |2 +- include/configs/cm_t35.h | 11 + include/lcd.h |1 + 12 files changed, 579 insertions(+), 3 deletions(-) create mode 100644 board/cm_t35/display.c -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 1/7] omap3: add useful dss defines
Add useful omap3 dss defines for: polarity, TFT data lines, lcd
display type, gfx burst size, and gfx format
Cc: Anatolij Gustschin ag...@denx.de
Cc: Jeroen Hofstee jer...@myspectrum.nl
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
Signed-off-by: Igor Grinberg grinb...@compulab.co.il
---
Changes in V3:
- Removed unused #define (burst size) [Wolfgang Denk]
Changes in V2:
- GFX format #define values are shifted [Jeroen Hofstee]
arch/arm/include/asm/arch-omap3/dss.h | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/include/asm/arch-omap3/dss.h
b/arch/arm/include/asm/arch-omap3/dss.h
index ffaffbb..0cbef84 100644
--- a/arch/arm/include/asm/arch-omap3/dss.h
+++ b/arch/arm/include/asm/arch-omap3/dss.h
@@ -167,6 +167,36 @@ struct venc_regs {
#define VENC_OUT_SEL (1 6)
#define DIG_LPP_SHIFT 16
+/* LCD display type */
+#define PASSIVE_DISPLAY0
+#define ACTIVE_DISPLAY 1
+
+/* TFTDATALINES */
+#define LCD_INTERFACE_12_BIT 0
+#define LCD_INTERFACE_16_BIT 1
+#define LCD_INTERFACE_18_BIT 2
+#define LCD_INTERFACE_24_BIT 3
+
+/* Polarity */
+#define DSS_IVS(1 12)
+#define DSS_IHS(1 13)
+#define DSS_IPC(1 14)
+#define DSS_IEO(1 15)
+
+/* GFX format */
+#define GFXFORMAT_BITMAP1 (0x0 1)
+#define GFXFORMAT_BITMAP2 (0x1 1)
+#define GFXFORMAT_BITMAP4 (0x2 1)
+#define GFXFORMAT_BITMAP8 (0x3 1)
+#define GFXFORMAT_RGB12(0x4 1)
+#define GFXFORMAT_ARGB16 (0x5 1)
+#define GFXFORMAT_RGB16(0x6 1)
+#define GFXFORMAT_RGB24_UNPACKED (0x8 1)
+#define GFXFORMAT_RGB24_PACKED (0x9 1)
+#define GFXFORMAT_ARGB32 (0xC 1)
+#define GFXFORMAT_RGBA32 (0xD 1)
+#define GFXFORMAT_RGBx32 (0xE 1)
+
/* Panel Configuration */
struct panel_config {
u32 timing_h;
--
1.7.10.4
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[U-Boot] [PATCH V2 7/7] cm-t35: add support for loading splash image from NAND
Add support for loading splash image from NAND
Cc: Anatolij Gustschin ag...@denx.de
Cc: Jeroen Hofstee jer...@myspectrum.nl
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
Signed-off-by: Igor Grinberg grinb...@compulab.co.il
---
Changes in V2:
- Added fix to bmp_load_addr to comply with what happens in lcd.c
following patch number 3.
board/cm_t35/cm_t35.c| 65 ++
include/configs/cm_t35.h |4 +++
2 files changed, 69 insertions(+)
diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c
index 8f3d735..5fd71f9 100644
--- a/board/cm_t35/cm_t35.c
+++ b/board/cm_t35/cm_t35.c
@@ -33,7 +33,9 @@
#include net.h
#include i2c.h
#include usb.h
+#include nand.h
#include twl4030.h
+#include bmp_layout.h
#include linux/compiler.h
#include asm/io.h
@@ -75,6 +77,69 @@ static u32 gpmc_nand_config[GPMC_MAX_REG] = {
0,
};
+#ifdef CONFIG_LCD
+#ifdef CONFIG_CMD_NAND
+static int splash_load_from_nand(u32 bmp_load_addr)
+{
+ struct bmp_header *bmp_hdr;
+ int res, splash_screen_nand_offset = 0x10;
+ size_t bmp_size, bmp_header_size = sizeof(struct bmp_header);
+
+ if (bmp_load_addr + bmp_header_size = gd-start_addr_sp)
+ goto splash_address_too_high;
+
+ res = nand_read_skip_bad(nand_info[nand_curr_device],
+ splash_screen_nand_offset, bmp_header_size,
+ (u_char *)bmp_load_addr);
+ if (res 0)
+ return res;
+
+ bmp_hdr = (struct bmp_header *)bmp_load_addr;
+ bmp_size = le32_to_cpu(bmp_hdr-file_size);
+
+ if (bmp_load_addr + bmp_size = gd-start_addr_sp)
+ goto splash_address_too_high;
+
+ return nand_read_skip_bad(nand_info[nand_curr_device],
+ splash_screen_nand_offset, bmp_size,
+ (u_char *)bmp_load_addr);
+
+splash_address_too_high:
+ printf(Error: splashimage address too high. Data overwrites U-Boot
+ and/or placed beyond DRAM boundaries.\n);
+
+ return -1;
+}
+#else
+static inline int splash_load_from_nand(void)
+{
+ return -1;
+}
+#endif /* CONFIG_CMD_NAND */
+
+int board_splash_screen_prepare(void)
+{
+ char *env_splashimage_value;
+ u32 bmp_load_addr;
+
+ env_splashimage_value = getenv(splashimage);
+ if (env_splashimage_value == NULL)
+ return -1;
+
+ bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16);
+ if (bmp_load_addr == 0) {
+ printf(Error: bad splashimage address specified\n);
+ return -1;
+ }
+
+ /* Fix bmp_load_addr to the alignment that lcd.c expects */
+ if (bmp_load_addr % 4 != 2)
+ bmp_load_addr += (bmp_load_addr % 4) ?: 2;
+
+ return splash_load_from_nand(bmp_load_addr);
+}
+#endif /* CONFIG_LCD */
+
/*
* Routine: board_init
* Description: hardware init.
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 46d35ba..53c4e3c 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -344,5 +344,9 @@
#define LCD_BPPLCD_COLOR16
#define CONFIG_LCD
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_SPLASH_SCREEN_PREPARE
#endif /* __CONFIG_H */
--
1.7.10.4
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[U-Boot] [PATCH V3 2/7] omap3: allow dynamic selection of gfx_format
Currently, omap3_dss_panel_config() sets gfx_format to a value that is hardcoded
in the code. This forces anyone who wants to use a different gfx_format to make
adjustments after calling omap3_dss_panel_config(). This could be avoided if the
value of gfx_format were parameterized as input for omap3_dss_panel_config().
Make gfx_format a field in struct panel_config, and update existing structs to
set this field to the value that was originally hard coded.
Cc: Wolfgang Denk w...@denx.de
Cc: Jeroen Hofstee jer...@myspectrum.nl
Cc: Tom Rini tr...@ti.com
Cc: Anatolij Gustschin ag...@denx.de
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
Signed-off-by: Igor Grinberg grinb...@compulab.co.il
---
Changes in V3:
- Commit message rephrased [Wolfgang Denk]
Changes in V2: None. Patch introduced in V2.
arch/arm/include/asm/arch-omap3/dss.h |1 +
board/htkw/mcx/mcx.c |1 +
board/teejet/mt_ventoux/mt_ventoux.c |2 ++
board/ti/beagle/beagle.h |6 --
drivers/video/omap3_dss.c |2 +-
5 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap3/dss.h
b/arch/arm/include/asm/arch-omap3/dss.h
index 0cbef84..ae0babf 100644
--- a/arch/arm/include/asm/arch-omap3/dss.h
+++ b/arch/arm/include/asm/arch-omap3/dss.h
@@ -208,6 +208,7 @@ struct panel_config {
u32 data_lines;
u32 load_mode;
u32 panel_color;
+ u32 gfx_format;
void *frame_buffer;
};
diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c
index 9fe6408..5eda6c4 100644
--- a/board/htkw/mcx/mcx.c
+++ b/board/htkw/mcx/mcx.c
@@ -130,6 +130,7 @@ static struct panel_config lcd_cfg = {
.load_mode = 0x02, /* Frame Mode */
.panel_color= 0,
.lcd_size = PANEL_LCD_SIZE(800, 480),
+ .gfx_format = GFXFORMAT_RGB24_UNPACKED,
};
int board_video_init(void)
diff --git a/board/teejet/mt_ventoux/mt_ventoux.c
b/board/teejet/mt_ventoux/mt_ventoux.c
index c516c75..78d81d6 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.c
+++ b/board/teejet/mt_ventoux/mt_ventoux.c
@@ -81,6 +81,7 @@ static struct panel_config lcd_cfg[] = {
.data_lines = 0x03, /* 24 Bit RGB */
.load_mode = 0x02, /* Frame Mode */
.panel_color= 0,
+ .gfx_format = GFXFORMAT_RGB24_UNPACKED,
},
{
.timing_h = PANEL_TIMING_H(20, 192, 4),
@@ -91,6 +92,7 @@ static struct panel_config lcd_cfg[] = {
.data_lines = 0x03, /* 24 Bit RGB */
.load_mode = 0x02, /* Frame Mode */
.panel_color= 0,
+ .gfx_format = GFXFORMAT_RGB24_UNPACKED,
}
};
#endif
diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
index c0a94a9..6d71bbc 100644
--- a/board/ti/beagle/beagle.h
+++ b/board/ti/beagle/beagle.h
@@ -544,7 +544,8 @@ static const struct panel_config dvid_cfg = {
.panel_type = 0x01, /* TFT */
.data_lines = 0x03, /* 24 Bit RGB */
.load_mode = 0x02, /* Frame Mode */
- .panel_color= DVI_BEAGLE_ORANGE_COL /* ORANGE */
+ .panel_color= DVI_BEAGLE_ORANGE_COL, /* ORANGE */
+ .gfx_format = GFXFORMAT_RGB24_UNPACKED,
};
static const struct panel_config dvid_cfg_xm = {
@@ -556,6 +557,7 @@ static const struct panel_config dvid_cfg_xm = {
.panel_type = 0x01, /* TFT */
.data_lines = 0x03, /* 24 Bit RGB */
.load_mode = 0x02, /* Frame Mode */
- .panel_color= DVI_BEAGLE_ORANGE_COL /* ORANGE */
+ .panel_color= DVI_BEAGLE_ORANGE_COL, /* ORANGE */
+ .gfx_format = GFXFORMAT_RGB24_UNPACKED,
};
#endif
diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c
index b1424bf..6efba12 100644
--- a/drivers/video/omap3_dss.c
+++ b/drivers/video/omap3_dss.c
@@ -121,7 +121,7 @@ void omap3_dss_panel_config(const struct panel_config
*panel_cfg)
if (!panel_cfg-frame_buffer)
return;
- writel(8 GFX_FORMAT_SHIFT | GFX_ENABLE, dispc-gfx_attributes);
+ writel(panel_cfg-gfx_format | GFX_ENABLE, dispc-gfx_attributes);
writel(1, dispc-gfx_row_inc);
writel(1, dispc-gfx_pixel_inc);
writel(panel_cfg-lcd_size, dispc-gfx_size);
--
1.7.10.4
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[U-Boot] [PATCH V3 5/7] cm-t35: add support for dvi displays
Add support for dvi displays with user selectable dvi presets.
Cc: Wolfgang Denk w...@denx.de
Cc: Jeroen Hofstee jer...@myspectrum.nl
Cc: Anatolij Gustschin ag...@denx.de
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
Signed-off-by: Igor Grinberg grinb...@compulab.co.il
---
Changes in V3:
- Added a #define for CMAP [Wolfgang Denk]
Changes in V2:
- Used LCD_BPP for vl_bpix [Jeroen Hofstee]
- GFXFORMAT_RGB16 now passed to omap3_dss_panel_config() as part of
panel_cfg predefines. [Jeroen Hofstee]
- Added a comment to explain the choice of GFXFORMAT_RGB16.
[Jeroen Hofstee]
- Do not set gfx burst size to GFXBURSTSIZE16, as it is apparently not
necessary.
board/cm_t35/Makefile|1 +
board/cm_t35/cm_t35.c|3 +
board/cm_t35/display.c | 220 ++
include/configs/cm_t35.h |7 ++
4 files changed, 231 insertions(+)
create mode 100644 board/cm_t35/display.c
diff --git a/board/cm_t35/Makefile b/board/cm_t35/Makefile
index 894fa09..bde56e6 100644
--- a/board/cm_t35/Makefile
+++ b/board/cm_t35/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(BOARD).o
COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o
+COBJS-$(CONFIG_LCD) += display.o
COBJS := cm_t35.o leds.o $(COBJS-y)
diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c
index edbb941..8f3d735 100644
--- a/board/cm_t35/cm_t35.c
+++ b/board/cm_t35/cm_t35.c
@@ -216,6 +216,9 @@ static void cm_t3x_set_common_muxconf(void)
/* SB-T35 Ethernet */
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
+ /* DVI enable */
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/
+
/* CM-T3x Ethernet */
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/
diff --git a/board/cm_t35/display.c b/board/cm_t35/display.c
new file mode 100644
index 000..43f0628
--- /dev/null
+++ b/board/cm_t35/display.c
@@ -0,0 +1,220 @@
+/*
+ * (C) Copyright 2012 CompuLab, Ltd. www.compulab.co.il
+ *
+ * Authors: Nikita Kiryanov nik...@compulab.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#include common.h
+#include asm/gpio.h
+#include asm/io.h
+#include stdio_dev.h
+#include asm/arch/dss.h
+#include lcd.h
+#include asm/arch-omap3/dss.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum display_type {
+ NONE,
+ DVI,
+};
+
+#define CMAP_ADDR 0x8010
+
+/*
+ * The frame buffer is allocated before we have the chance to parse user input.
+ * To make sure enough memory is allocated for all resolutions, we define
+ * vl_{col | row} to the maximal resolution supported by OMAP3.
+ */
+vidinfo_t panel_info = {
+ .vl_col = 1400,
+ .vl_row = 1050,
+ .vl_bpix = LCD_BPP,
+ .cmap = (ushort *)CMAP_ADDR,
+};
+
+static struct panel_config panel_cfg;
+static enum display_type lcd_def;
+
+/*
+ * A note on DVI presets;
+ * U-Boot can convert 8 bit BMP data to 16 bit BMP data, and OMAP DSS can
+ * convert 16 bit data into 24 bit data. Thus, GFXFORMAT_RGB16 allows us to
+ * support two BMP types with one setting.
+ */
+static const struct panel_config preset_dvi_640X480 = {
+ .lcd_size = PANEL_LCD_SIZE(640, 480),
+ .timing_h = DSS_HBP(48) | DSS_HFP(16) | DSS_HSW(96),
+ .timing_v = DSS_VBP(33) | DSS_VFP(10) | DSS_VSW(2),
+ .divisor= 12 | (1 16),
+ .data_lines = LCD_INTERFACE_24_BIT,
+ .panel_type = ACTIVE_DISPLAY,
+ .load_mode = 2,
+ .gfx_format = GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_800X600 = {
+ .lcd_size = PANEL_LCD_SIZE(800, 600),
+ .timing_h = DSS_HBP(88) | DSS_HFP(40) | DSS_HSW(128),
+ .timing_v = DSS_VBP(23) | DSS_VFP(1) | DSS_VSW(4),
+ .divisor= 8 | (1 16),
+ .data_lines = LCD_INTERFACE_24_BIT,
+ .panel_type = ACTIVE_DISPLAY,
+ .load_mode = 2,
+ .gfx_format = GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_1024X768 = {
+ .lcd_size = PANEL_LCD_SIZE(1024, 768),
+ .timing_h =
[U-Boot] [PATCH V1 4/7] lcd: add option for board specific splash screen preparation
Currently there is no logical place to put the code that prepares the
splash image data. The splash image data should be ready in memory
before bmp_display() is called, and after the environment is ready
(since lcd.c looks for the splash image in an address specified by
the environment variable splashimage).
Our window of opportunity in board_init_r() is therefore: between
env_relocate() and bmp_display(), and from the available options
only the lcd related functions in drv_lcd_init() seem appropriate
for such lcd oriented code.
Add the option to prepare the splash image data in lcd_logo() right
before it is sent to be displayed.
Cc: Anatolij Gustschin ag...@denx.de
Cc: Jeroen Hofstee jer...@myspectrum.nl
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
Signed-off-by: Igor Grinberg grinb...@compulab.co.il
---
README|8
common/lcd.c | 15 +++
include/lcd.h |1 +
3 files changed, 24 insertions(+)
diff --git a/README b/README
index a336476..89694d7 100644
--- a/README
+++ b/README
@@ -1550,6 +1550,14 @@ CBFS (Coreboot Filesystem) support
= vertically centered image
at x = dspWidth - bmpWidth - 9
+ CONFIG_SPLASH_SCREEN_PREPARE
+
+ If this option is set then the board_splash_screen_prepare()
+ function, which must be defined in your code, is called as part
+ of the splash screen display sequence. It gives the board an
+ opportunity to prepare the splash image data before it is
+ processed and sent to the frame buffer by U-Boot.
+
- Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP
If this option is set, additionally to standard BMP
diff --git a/common/lcd.c b/common/lcd.c
index 104125d..bb8a7d2 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -1034,6 +1034,18 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
}
#endif
+#ifdef CONFIG_SPLASH_SCREEN_PREPARE
+static inline int splash_screen_prepare(void)
+{
+ return board_splash_screen_prepare();
+}
+#else
+static inline int splash_screen_prepare(void)
+{
+ return 0;
+}
+#endif
+
static void *lcd_logo(void)
{
#ifdef CONFIG_SPLASH_SCREEN
@@ -1045,6 +1057,9 @@ static void *lcd_logo(void)
int x = 0, y = 0;
do_splash = 0;
+ if (splash_screen_prepare())
+ return (void *)gd-fb_base;
+
addr = simple_strtoul (s, NULL, 16);
/*
* In order for the fields of bmp header to be properly aligned
diff --git a/include/lcd.h b/include/lcd.h
index c24164a..4ac4ddd 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -47,6 +47,7 @@ extern struct vidinfo panel_info;
extern void lcd_ctrl_init (void *lcdbase);
extern void lcd_enable (void);
+extern int board_splash_screen_prepare(void);
/* setcolreg used in 8bpp/16bpp; initcolregs used in monochrome */
extern void lcd_setcolreg (ushort regno,
--
1.7.10.4
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[U-Boot] [PATCH V2 3/7] lcd: prevent unaligned memory access when displaying splash screen
When the bmp file is loaded to an address specified by the environment
variable splashimage, its header members might be unaligned.
This happens because the bmp header starts with two byte size fields followd by
mostly 32 bit fields. When the address in splashimage is not equal to aligned
address plus/minus 2, the 32 bit members will be placed in unaligned addresses
and the result would be a data abort on targets that cannot handle unaligned
memory accesses.
Check that the address is safe to use, and fix it if it's not.
Cc: Anatolij Gustschin ag...@denx.de
Cc: Albert ARIBAUD albert.u.b...@aribaud.net
Cc: Jeroen Hofstee jer...@myspectrum.nl
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
Signed-off-by: Igor Grinberg grinb...@compulab.co.il
---
Changes in V2: None. Patch introduced in V2.
common/lcd.c |8
1 file changed, 8 insertions(+)
diff --git a/common/lcd.c b/common/lcd.c
index 66d4f94..104125d 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -1046,6 +1046,14 @@ static void *lcd_logo(void)
do_splash = 0;
addr = simple_strtoul (s, NULL, 16);
+ /*
+* In order for the fields of bmp header to be properly aligned
+* in memory, splash image addr must be aligned to aligned
+* address plus 2. Fix addr if necessary.
+*/
+ if (addr % 4 != 2)
+ addr += (addr % 4) ?: 2;
+
#ifdef CONFIG_SPLASH_SCREEN_ALIGN
s = getenv(splashpos);
if (s != NULL) {
--
1.7.10.4
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[U-Boot] [PATCH V2 6/7] cm-t35: add support for user defined lcd parameters
Add support for user defined lcd parameters for cm-t35 splash screen.
Cc: Jeroen Hofstee jer...@myspectrum.nl
Cc: Anatolij Gustschin ag...@denx.de
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
Signed-off-by: Igor Grinberg grinb...@compulab.co.il
---
Changes in V2:
- Set gfx_format to GFXFORMAT_RGB16 after parsing custom lcd settings.
board/cm_t35/display.c | 214 +++-
1 file changed, 211 insertions(+), 3 deletions(-)
diff --git a/board/cm_t35/display.c b/board/cm_t35/display.c
index 43f0628..2f78bad 100644
--- a/board/cm_t35/display.c
+++ b/board/cm_t35/display.c
@@ -3,6 +3,8 @@
*
* Authors: Nikita Kiryanov nik...@compulab.co.il
*
+ * Parsing code based on linux/drivers/video/pxafb.c
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -33,6 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
enum display_type {
NONE,
DVI,
+ DVI_CUSTOM,
};
#define CMAP_ADDR 0x8010
@@ -152,6 +155,206 @@ static enum display_type set_dvi_preset(const struct
panel_config preset,
}
/*
+ * parse_mode() - parse the mode parameter of custom lcd settings
+ *
+ * @mode: res_xxres_y
+ *
+ * Returns -1 on error, 0 on success.
+ */
+static int parse_mode(const char *mode)
+{
+ unsigned int modelen = strlen(mode);
+ int res_specified = 0;
+ unsigned int xres = 0, yres = 0;
+ int yres_specified = 0;
+ int i;
+
+ for (i = modelen - 1; i = 0; i--) {
+ switch (mode[i]) {
+ case 'x':
+ if (!yres_specified) {
+ yres = simple_strtoul(mode[i + 1], NULL, 0);
+ yres_specified = 1;
+ } else {
+ goto done_parsing;
+ }
+
+ break;
+ case '0' ... '9':
+ break;
+ default:
+ goto done_parsing;
+ }
+ }
+
+ if (i 0 yres_specified) {
+ xres = simple_strtoul(mode, NULL, 0);
+ res_specified = 1;
+ }
+
+done_parsing:
+ if (res_specified) {
+ set_resolution_params(xres, yres);
+ } else {
+ printf(LCD: invalid mode: %s\n, mode);
+ return -1;
+ }
+
+ return 0;
+}
+
+#define PIXEL_CLK_NUMERATOR (26 * 432 / 39)
+/*
+ * parse_pixclock() - Parse the pixclock parameter of custom lcd settings
+ *
+ * @pixclock: the desired pixel clock
+ *
+ * Returns -1 on error, 0 on success.
+ *
+ * Handling the pixel_clock:
+ *
+ * Pixel clock is defined in the OMAP35x TRM as follows:
+ * pixel_clock =
+ * (SYS_CLK * 2 * PRCM.CM_CLKSEL2_PLL[18:8]) /
+ * (DSS.DISPC_DIVISOR[23:16] * DSS.DISPC_DIVISOR[6:0] *
+ * PRCM.CM_CLKSEL_DSS[4:0] * (PRCM.CM_CLKSEL2_PLL[6:0] + 1))
+ *
+ * In practice, this means that in order to set the
+ * divisor for the desired pixel clock one needs to
+ * solve the following equation:
+ *
+ * 26 * 432 / (39 * pixel_clock) = DSS.DISPC_DIVISOR[6:0]
+ *
+ * NOTE: the explicit equation above is reduced. Do not
+ * try to infer anything from these numbers.
+ */
+static int parse_pixclock(char *pixclock)
+{
+ int divisor, pixclock_val;
+ char *pixclk_start = pixclock;
+
+ pixclock_val = simple_strtoul(pixclock, pixclock, 10);
+ divisor = DIV_ROUND_UP(PIXEL_CLK_NUMERATOR, pixclock_val);
+ /* 0 and 1 are illegal values for PCD */
+ if (divisor = 1)
+ divisor = 2;
+
+ panel_cfg.divisor = divisor | (1 16);
+ if (pixclock[0] != '\0') {
+ printf(LCD: invalid value for pixclock:%s\n, pixclk_start);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * parse_setting() - parse a single setting of custom lcd parameters
+ *
+ * @setting: The custom lcd setting name:value
+ *
+ * Returns -1 on failure, 0 on success.
+ */
+static int parse_setting(char *setting)
+{
+ int num_val;
+ char *setting_start = setting;
+
+ if (!strncmp(setting, mode:, 5)) {
+ return parse_mode(setting + 5);
+ } else if (!strncmp(setting, pixclock:, 9)) {
+ return parse_pixclock(setting + 9);
+ } else if (!strncmp(setting, left:, 5)) {
+ num_val = simple_strtoul(setting + 5, setting, 0);
+ panel_cfg.timing_h |= DSS_HBP(num_val);
+ } else if (!strncmp(setting, right:, 6)) {
+ num_val = simple_strtoul(setting + 6, setting, 0);
+ panel_cfg.timing_h |= DSS_HFP(num_val);
+ } else if (!strncmp(setting, upper:, 6)) {
+ num_val = simple_strtoul(setting + 6, setting, 0);
+ panel_cfg.timing_v |= DSS_VBP(num_val);
+ } else if (!strncmp(setting, lower:, 6)) {
+ num_val = simple_strtoul(setting + 6, setting, 0);
+ panel_cfg.timing_v |= DSS_VFP(num_val);
+ } else if
Re: [U-Boot] [PATCH 0/7] omap mmc: implement card detect and write protection
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 01/07/13 16:43, Tom Rini wrote: On 12/30/2012 01:13 AM, Nikita Kiryanov wrote: Gentle ping. On 12/03/2012 02:19 PM, Nikita Kiryanov wrote: This patchset implements card detection and write protection check for omap mmc. The write protect implementation also adds generic code that is usable by other mmc drivers. The first 3 patches are preparation patches that contain general maintenance for omap mmc driver. This patchset depends on http://patchwork.ozlabs.org/patch/202384/ [...] Andy, do you want this in your tree or should I put it in u-boot-ti/next? Thanks! Andy, Tom? - -- Regards, Igor. -BEGIN PGP SIGNATURE- Version: GnuPG v2.0.17 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQIcBAEBAgAGBQJRCiDeAAoJEBDE8YO64EfagmMP/ApwvIUgrbNuHFoZVV1wnD8l 7Vl7ORaqN7Ep9gB8feN43GQ2xMhEFAByFJ0pb1jUXUbAoqkTy7i61XBAAqIMpmgY kPHWKOcArKc7tsbggOgOGKsKMd3T5KgE9+noRujmAFraiVvhmSQAH5Lm8nI9sGId eXv7krIgmDuf/p+S568O1RPKVD/6YItH7RYuniArUplm2v6opjDkc/ZbQM8FSowR OiD5Y5BAMhX8mD30LhUHqJZXcsy3rpZGi6xu3ZrUmllWziTNs/NmCel2Jz7Rw5XM ZG3+xafov4Y/YLwoxz5thgkDsC/3rX0NHkx2wfXiTmR40VXafSX0t03qrN6Zf08u kCL3lWiwuRBsC/92JWKOHvi7U1Qos+t9hwhCdJJ1xeNWiZscWbvg1qNdv1vrrHK/ HQJJBkU40lOI0pg/JBBo70Xwp8TUIJLGf0Y1X71QulN74S+TuINQ6jSncPYTJIsC 7O5kZ6l6jst48KgCm9OH0BYcThexANOBe1x++AbDJjxRHxeLdLujDhz1e+qd+NyV ussFLEMR4Xl+xoH8fcX7+kD9+eCDt0MlEKGJFMtw2LnK0jJtQvT9W6ltXPeD7QMK Fc7EkNrtBzu9lt1dqFBn5yOtt5KcBw8pN4VjnqsGHUkyxOXEiY5BOcJS01ynpOXw kBJAH0MVJVSsFQa8Y5cB =ABJ2 -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 6/7] cm-t35: add support for user defined lcd parameters
Hi Wolfgang Denk, On 01/29/2013 03:48 PM, Wolfgang Denk wrote: Dear Nikita Kiryanov, In message 1359463349-11649-7-git-send-email-nik...@compulab.co.il you wrote: Add support for user defined lcd parameters for cm-t35 splash screen. Why do you implement another custom method to configure the display? This has been done before, and we should reuse existing methods. This patch implements a user interface, not reimplements methods that configure the DSS. For that, I'm still using omap3_dss_panel_config(), struct panel_config, and omap3_dss.h #defines. Best regards, Wolfgang Denk -- Regards, Nikita. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 7/7] cm-t35: add support for loading splash image from NAND
Hi Wolfgang Denk, On 01/29/2013 03:50 PM, Wolfgang Denk wrote: Dear Nikita Kiryanov, In message 1359463349-11649-8-git-send-email-nik...@compulab.co.il you wrote: Add support for loading splash image from NAND Signed-off-by: Nikita Kiryanov nik...@compulab.co.il Signed-off-by: Igor Grinberg grinb...@compulab.co.il --- Changes in V2: - Added fix to bmp_load_addr to comply with what happens in lcd.c following patch number 3. board/cm_t35/cm_t35.c| 65 ++ include/configs/cm_t35.h |4 +++ 2 files changed, 69 insertions(+) Why exactly do you need to add code here? Is it not sufficient to add, for example, a nand read command as part of your preboot settings? The preboot commands are executed after lcd is turned on; ideally, the splashimage should be in the frame buffer before that. There is also the issue of having to fix the bmp load address to the appropriate alignment (to comply with a similar fix in lcd.c from patch 3), and checking for problems such as overwriting U-Boot data with the bmp. I don't think Hush is the right tool for these actions. Best regards, Wolfgang Denk -- Regards, Nikita. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] mmc: check the revision for sd3.0
Support to check whether the SD3.0 or not. Signed-off-by: Jaehoon Chung jh80.ch...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- drivers/mmc/mmc.c |2 ++ include/mmc.h |1 + 2 files changed, 3 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 72e8ce6..b704d8b 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -759,6 +759,8 @@ retry_scr: break; case 2: mmc-version = SD_VERSION_2; + if ((mmc-scr[0] 15) 0x1) + mmc-version = SD_VERSION_3; break; default: mmc-version = SD_VERSION_1_0; diff --git a/include/mmc.h b/include/mmc.h index a13e2bd..7c8f325 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -30,6 +30,7 @@ #include linux/compiler.h #define SD_VERSION_SD 0x2 +#define SD_VERSION_3 (SD_VERSION_SD | 0x30) #define SD_VERSION_2 (SD_VERSION_SD | 0x20) #define SD_VERSION_1_0 (SD_VERSION_SD | 0x10) #define SD_VERSION_1_10(SD_VERSION_SD | 0x1a) -- 1.7.5.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] MMC - Error detected in status(0x208100)!
Hi Andy, The latest patch mmc: Properly determine maximum supported bus width (sha1: 7798f6dbd5e1a3030ed81a81da5dfb57c3307cac) is causing some error status issue on zynq platform with MMC Plus cards. Here the out what I get with inclusion of this patch on u-boot tree. zynq-uboot mmcinfo Error detected in status(0x208100)! Device: zynq_sdhci Manufacturer ID: 1e OEM: Name: MMC Tran Speed: 5200 Rd Block Len: 512 MMC version 4.0 High Capacity: No Capacity: 1.9 GiB Bus Width: 4-bit When I revert this path, I am unable to see the status error. zynq-uboot mmcinfo Device: zynq_sdhci Manufacturer ID: 1e OEM: Name: MMC Tran Speed: 5200 Rd Block Len: 512 MMC version 4.0 High Capacity: No Capacity: 1.9 GiB Bus Width: 12-bit I think the above one is also a buggy as my controller is unable to support 12-bit bus width.? Request for any inputs. Thanks, Jagan. This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 01/10] mxs: Rename CONFIG_SPL_MX28_PSWITCH_WAIT to CONFIG_SPL_MXS_PSWITCH_WAIT
The power switch option is compatible with i.MX23 and i.MX28 so the
configration option needs to reflect it. We choose
'CONFIG_SPL_MXS_PSWITCH_WAIT' for the option name.
Signed-off-by: Otavio Salvador ota...@ossystems.com.br
---
arch/arm/cpu/arm926ejs/mxs/mxs_init.h | 2 +-
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs_init.h
b/arch/arm/cpu/arm926ejs/mxs/mxs_init.h
index 2ddc5bc..084def5 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs_init.h
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs_init.h
@@ -30,7 +30,7 @@ void early_delay(int delay);
void mxs_power_init(void);
-#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
+#ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
void mxs_power_wait_pswitch(void);
#else
static inline void mxs_power_wait_pswitch(void) { }
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index e9d6302..287c698 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -921,7 +921,7 @@ void mxs_power_init(void)
early_delay(1000);
}
-#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
+#ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
void mxs_power_wait_pswitch(void)
{
struct mxs_power_regs *power_regs =
--
1.8.1
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[U-Boot] [PATCH 0/10] mx23/mxs pending patches
This patchset includes the pending patches we have in our tree. It fixes issues for mx23evk and mx23_olinuxino boards. Otavio Salvador (10): mxs: Rename CONFIG_SPL_MX28_PSWITCH_WAIT to CONFIG_SPL_MXS_PSWITCH_WAIT mx23: Document the tRAS lockout setting in memory initialization mx23evk: Adjust DRAM control register to use full 128MB of RAM led: Use STATUS_LED_ON and STATUS_LED_OFF when calling __led_set mxs: Fix iomux.h to not break build during assembly stage mx23_olinuxino: Add support for status LED usb: mxs: Disable USB Port 1 for i.MX23 mx23evk: Enable USB support mx23_olinuxino: Enable USB support mx23_olinuxino: Add ethernet support arch/arm/cpu/arm926ejs/mxs/mxs_init.h| 2 +- arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c| 1 + arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 2 +- arch/arm/include/asm/arch-mxs/iomux.h| 5 +++ board/freescale/mx23evk/spl_boot.c | 10 + board/olimex/mx23_olinuxino/mx23_olinuxino.c | 13 ++ board/olimex/mx23_olinuxino/spl_boot.c | 8 common/cmd_led.c | 6 ++- drivers/usb/host/ehci-mxs.c | 2 + include/configs/mx23_olinuxino.h | 62 ++-- include/configs/mx23evk.h| 10 + 11 files changed, 114 insertions(+), 7 deletions(-) -- 1.8.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 02/10] mx23: Document the tRAS lockout setting in memory initialization
Add a comment about the tRAS lockout setting of HW_DRAM_CTL08 to enable the 'Fast Auto Pre-Charge' found in the memory chip. The setting is applied after memory initialization and it is worth document it. Signed-off-by: Otavio Salvador ota...@ossystems.com.br --- arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index f8392f6..37b50e9 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -119,6 +119,7 @@ static void initialize_dram_values(void) writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); #ifdef CONFIG_MX23 + /* Enable tRAS lockout in HW_DRAM_CTL08 */ writel((1 24), MXS_DRAM_BASE + (4 * 8)); #endif } -- 1.8.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 04/10] led: Use STATUS_LED_ON and STATUS_LED_OFF when calling __led_set
This fixes the gpio_led driver which needs to compare againt a STATUS_LED_ON to enable a led. Signed-off-by: Otavio Salvador ota...@ossystems.com.br --- common/cmd_led.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/common/cmd_led.c b/common/cmd_led.c index 7f5ab43..84f79fa 100644 --- a/common/cmd_led.c +++ b/common/cmd_led.c @@ -110,13 +110,15 @@ int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (led_commands[i].on) led_commands[i].on(); else - __led_set(led_commands[i].mask, 1); + __led_set(led_commands[i].mask, + STATUS_LED_ON); break; case LED_OFF: if (led_commands[i].off) led_commands[i].off(); else - __led_set(led_commands[i].mask, 0); + __led_set(led_commands[i].mask, + STATUS_LED_OFF); break; case LED_TOGGLE: if (led_commands[i].toggle) -- 1.8.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 05/10] mxs: Fix iomux.h to not break build during assembly stage
This fixes the build failure when included in mx23_olinuxino.h board config; the addition of asm/types.h is due u32 being otherwise undefined. Signed-off-by: Otavio Salvador ota...@ossystems.com.br --- arch/arm/include/asm/arch-mxs/iomux.h | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/include/asm/arch-mxs/iomux.h b/arch/arm/include/asm/arch-mxs/iomux.h index 7abdf58..4288715 100644 --- a/arch/arm/include/asm/arch-mxs/iomux.h +++ b/arch/arm/include/asm/arch-mxs/iomux.h @@ -21,6 +21,10 @@ #ifndef __MACH_MXS_IOMUX_H__ #define __MACH_MXS_IOMUX_H__ +#ifndef __ASSEMBLY__ + +#include asm/types.h + /* * IOMUX/PAD Bit field definitions * @@ -165,4 +169,5 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad); */ int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count); +#endif /* __ASSEMBLY__ */ #endif /* __MACH_MXS_IOMUX_H__*/ -- 1.8.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 03/10] mx23evk: Adjust DRAM control register to use full 128MB of RAM
Adjust HW_DRAM_CTL14 to enable the chip selects to allow usage of full
128MB of RAM.
Signed-off-by: Otavio Salvador ota...@ossystems.com.br
---
board/freescale/mx23evk/spl_boot.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/board/freescale/mx23evk/spl_boot.c
b/board/freescale/mx23evk/spl_boot.c
index 6007433..b6f4e7e 100644
--- a/board/freescale/mx23evk/spl_boot.c
+++ b/board/freescale/mx23evk/spl_boot.c
@@ -98,6 +98,16 @@ const iomux_cfg_t iomux_setup[] = {
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
};
+#define HW_DRAM_CTL14 (0x38 2)
+#define CS_MAP 0x3
+#define INTAREF0x2
+#define HW_DRAM_CTL14_CONFIG (INTAREF 8 | CS_MAP)
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+ dram_vals[HW_DRAM_CTL14] = HW_DRAM_CTL14_CONFIG;
+}
+
void board_init_ll(void)
{
mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
--
1.8.1
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[U-Boot] [PATCH 06/10] mx23_olinuxino: Add support for status LED
This allow user to know if the bootloader is running, even without a
serial console.
Signed-off-by: Otavio Salvador ota...@ossystems.com.br
---
board/olimex/mx23_olinuxino/mx23_olinuxino.c | 7 +++
board/olimex/mx23_olinuxino/spl_boot.c | 4
include/configs/mx23_olinuxino.h | 12
3 files changed, 23 insertions(+)
diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c
b/board/olimex/mx23_olinuxino/mx23_olinuxino.c
index 6a6053b..2501417 100644
--- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c
+++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c
@@ -28,6 +28,9 @@
#include asm/arch/imx-regs.h
#include asm/arch/clock.h
#include asm/arch/sys_proto.h
+#ifdef CONFIG_STATUS_LED
+#include status_led.h
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -67,5 +70,9 @@ int board_init(void)
/* Adress of boot parameters */
gd-bd-bi_boot_params = PHYS_SDRAM_1 + 0x100;
+#if defined(CONFIG_STATUS_LED) defined(STATUS_LED_BOOT)
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_STATE);
+#endif
+
return 0;
}
diff --git a/board/olimex/mx23_olinuxino/spl_boot.c
b/board/olimex/mx23_olinuxino/spl_boot.c
index 7def8bc..3bbf5ad 100644
--- a/board/olimex/mx23_olinuxino/spl_boot.c
+++ b/board/olimex/mx23_olinuxino/spl_boot.c
@@ -84,6 +84,10 @@ const iomux_cfg_t iomux_setup[] = {
MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+ /* Green LED */
+ MX23_PAD_SSP1_DETECT__GPIO_2_1 |
+ (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL),
+
/* MMC 0 */
MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP,
MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP,
diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h
index 7983c5d..968aec8 100644
--- a/include/configs/mx23_olinuxino.h
+++ b/include/configs/mx23_olinuxino.h
@@ -56,6 +56,7 @@
#defineCONFIG_CMD_EXT2
#defineCONFIG_CMD_FAT
#defineCONFIG_CMD_GPIO
+#defineCONFIG_CMD_LED
#defineCONFIG_CMD_MMC
/*
@@ -112,6 +113,17 @@
#defineCONFIG_BAUDRATE 115200 /* Default baud rate */
/*
+ * Status LED
+ */
+#defineCONFIG_STATUS_LED
+#defineCONFIG_GPIO_LED
+#defineCONFIG_BOARD_SPECIFIC_LED
+#defineSTATUS_LED_BOOT 0
+#defineSTATUS_LED_BIT 10
+#defineSTATUS_LED_STATESTATUS_LED_ON
+#defineSTATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
+
+/*
* MMC Driver
*/
#ifdef CONFIG_CMD_MMC
--
1.8.1
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[U-Boot] [PATCH 07/10] usb: mxs: Disable USB Port 1 for i.MX23
The i.MX23 just one USB port so disable the second controller probe when building for i.MX23. Signed-off-by: Otavio Salvador ota...@ossystems.com.br --- drivers/usb/host/ehci-mxs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c index 5062af5..28c8cde 100644 --- a/drivers/usb/host/ehci-mxs.c +++ b/drivers/usb/host/ehci-mxs.c @@ -50,10 +50,12 @@ int mxs_ehci_get_port(struct ehci_mxs *mxs_usb, int port) usb_base = MXS_USBCTRL0_BASE; phy_base = MXS_USBPHY0_BASE; break; +#ifdef CONFIG_MX28 case 1: usb_base = MXS_USBCTRL1_BASE; phy_base = MXS_USBPHY1_BASE; break; +#endif default: printf(CONFIG_EHCI_MXS_PORT (port = %d)\n, port); return -1; -- 1.8.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 08/10] mx23evk: Enable USB support
This enabled USB support for the mx23evk board. Signed-off-by: Otavio Salvador ota...@ossystems.com.br --- include/configs/mx23evk.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index c44a8b8..8db6283 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -60,6 +60,7 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_GPIO #define CONFIG_CMD_MMC +#define CONFIG_CMD_USB #define CONFIG_CMD_BOOTZ /* Memory configurations */ @@ -125,6 +126,15 @@ #define CONFIG_MXS_MMC #endif +/* USB */ +#ifdef CONFIG_CMD_USB +#defineCONFIG_USB_EHCI +#defineCONFIG_USB_EHCI_MXS +#defineCONFIG_EHCI_MXS_PORT 0 +#defineCONFIG_EHCI_IS_TDI +#defineCONFIG_USB_STORAGE +#endif + /* Boot Linux */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS -- 1.8.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 09/10] mx23_olinuxino: Enable USB support
This enabled USB support for the mx23_olinuxino board. Signed-off-by: Otavio Salvador ota...@ossystems.com.br --- include/configs/mx23_olinuxino.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h index 968aec8..7e17809 100644 --- a/include/configs/mx23_olinuxino.h +++ b/include/configs/mx23_olinuxino.h @@ -58,6 +58,7 @@ #defineCONFIG_CMD_GPIO #defineCONFIG_CMD_LED #defineCONFIG_CMD_MMC +#defineCONFIG_CMD_USB /* * Memory configurations @@ -138,6 +139,15 @@ */ #define CONFIG_APBH_DMA +/* USB */ +#ifdef CONFIG_CMD_USB +#defineCONFIG_USB_EHCI +#defineCONFIG_USB_EHCI_MXS +#defineCONFIG_EHCI_MXS_PORT 0 +#defineCONFIG_EHCI_IS_TDI +#defineCONFIG_USB_STORAGE +#endif + /* * Boot Linux */ -- 1.8.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 10/10] mx23_olinuxino: Add ethernet support
This adds support to the LAN9512 chip included in the board and extend
the environment to easy netboot use.
Signed-off-by: Otavio Salvador ota...@ossystems.com.br
---
board/olimex/mx23_olinuxino/mx23_olinuxino.c | 6 +
board/olimex/mx23_olinuxino/spl_boot.c | 4 +++
include/configs/mx23_olinuxino.h | 40 +---
3 files changed, 47 insertions(+), 3 deletions(-)
diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c
b/board/olimex/mx23_olinuxino/mx23_olinuxino.c
index 2501417..9ed7718 100644
--- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c
+++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c
@@ -23,6 +23,7 @@
*/
#include common.h
+#include asm/gpio.h
#include asm/io.h
#include asm/arch/iomux-mx23.h
#include asm/arch/imx-regs.h
@@ -45,6 +46,11 @@ int board_early_init_f(void)
/* SSP0 clock at 96MHz */
mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+#ifdef CONFIG_CMD_USB
+ /* Enable LAN9512 */
+ gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 1);
+#endif
+
return 0;
}
diff --git a/board/olimex/mx23_olinuxino/spl_boot.c
b/board/olimex/mx23_olinuxino/spl_boot.c
index 3bbf5ad..a96c293 100644
--- a/board/olimex/mx23_olinuxino/spl_boot.c
+++ b/board/olimex/mx23_olinuxino/spl_boot.c
@@ -95,6 +95,10 @@ const iomux_cfg_t iomux_setup[] = {
MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP,
MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP,
MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP,
+
+ /* Ethernet */
+ MX23_PAD_GPMI_ALE__GPIO_0_17 |
+ (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
};
void board_init_ll(void)
diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h
index 7e17809..42de557 100644
--- a/include/configs/mx23_olinuxino.h
+++ b/include/configs/mx23_olinuxino.h
@@ -53,11 +53,13 @@
#defineCONFIG_DOS_PARTITION
#defineCONFIG_CMD_CACHE
+#defineCONFIG_CMD_DHCP
#defineCONFIG_CMD_EXT2
#defineCONFIG_CMD_FAT
#defineCONFIG_CMD_GPIO
#defineCONFIG_CMD_LED
#defineCONFIG_CMD_MMC
+#defineCONFIG_CMD_NET
#defineCONFIG_CMD_USB
/*
@@ -148,6 +150,12 @@
#defineCONFIG_USB_STORAGE
#endif
+/* Ethernet */
+#ifdef CONFIG_CMD_NET
+#defineCONFIG_USB_HOST_ETHER
+#defineCONFIG_USB_ETHER_SMSC95XX
+#endif
+
/*
* Boot Linux
*/
@@ -173,6 +181,7 @@
/*
* Extra Environments
*/
+
#define CONFIG_EXTRA_ENV_SETTINGS \
update_sd_firmware_filename=u-boot.sd\0 \
update_sd_firmware= /* Update the SD firmware partition */ \
@@ -189,6 +198,7 @@
fdt_file=imx23-olinuxino.dtb\0 \
fdt_addr=0x4100\0 \
boot_fdt=try\0 \
+ ip_dyn=yes\0 \
mmcdev=0\0 \
mmcpart=2\0 \
mmcroot=/dev/mmcblk0p3 rw rootwait\0 \
@@ -214,6 +224,31 @@
fi; \
else \
bootm; \
+ fi;\0 \
+ netargs=setenv bootargs console=${console_mainline},${baudrate} \
+ root=/dev/nfs \
+ ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0 \
+ netboot=echo Booting from net ...; \
+ usb start; \
+ run netargs; \
+ if test ${ip_dyn} = yes; then \
+ setenv get_cmd dhcp; \
+ else \
+ setenv get_cmd tftp; \
+ fi; \
+ ${get_cmd} ${uimage}; \
+ if test ${boot_fdt} = yes; then \
+ if ${get_cmd} ${fdt_addr} ${fdt_file}; then \
+ bootm ${loadaddr} - ${fdt_addr}; \
+ else \
+ if test ${boot_fdt} = try; then \
+ bootm; \
+ else \
+ echo WARN: Cannot load the DT; \
+ fi; \
+ fi; \
+ else \
+ bootm; \
fi;\0
#define CONFIG_BOOTCOMMAND \
@@ -223,10 +258,9 @@
else \
if run loaduimage; then \
run mmcboot; \
- else \
- echo ERR: Fail to boot from MMC; \
+ else run netboot; \
fi; \
fi; \
- else exit; fi
+ else run netboot; fi
#endif /* __MX23_OLINUXINO_CONFIG_H__ */
--
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Re: [U-Boot] MMC - Error detected in status(0x208100)!
On 01/30/2013 07:48 PM, Jagannadha Sutradharudu Teki wrote: Hi Andy, The latest patch mmc: Properly determine maximum supported bus width (sha1: 7798f6dbd5e1a3030ed81a81da5dfb57c3307cac) is causing some error status issue on zynq platform with MMC Plus cards. Here the out what I get with inclusion of this patch on u-boot tree. zynq-uboot mmcinfo Error detected in status(0x208100)! Device: zynq_sdhci Manufacturer ID: 1e OEM: Name: MMC Tran Speed: 5200 Rd Block Len: 512 MMC version 4.0 High Capacity: No Capacity: 1.9 GiB Bus Width: 4-bit When I revert this path, I am unable to see the status error. zynq-uboot mmcinfo Device: zynq_sdhci Manufacturer ID: 1e OEM: Name: MMC Tran Speed: 5200 Rd Block Len: 512 MMC version 4.0 High Capacity: No Capacity: 1.9 GiB Bus Width: 12-bit I think the above one is also a buggy as my controller is unable to support 12-bit bus width.? Could you check which bus_width support at your controller? I guess it is set to wrong buswidth. Best Regards, Jaehoon Chung Request for any inputs. Thanks, Jagan. This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] MMC - Error detected in status(0x208100)!
Hi Jaehoon Chung, -Original Message- From: Jaehoon Chung [mailto:jh80.ch...@samsung.com] Sent: 30 January 2013 17:44 To: Jagannadha Sutradharudu Teki Cc: aflem...@freescale.com; u-boot@lists.denx.de Subject: Re: [U-Boot] MMC - Error detected in status(0x208100)! On 01/30/2013 07:48 PM, Jagannadha Sutradharudu Teki wrote: Hi Andy, The latest patch mmc: Properly determine maximum supported bus width (sha1: 7798f6dbd5e1a3030ed81a81da5dfb57c3307cac) is causing some error status issue on zynq platform with MMC Plus cards. Here the out what I get with inclusion of this patch on u-boot tree. zynq-uboot mmcinfo Error detected in status(0x208100)! Device: zynq_sdhci Manufacturer ID: 1e OEM: Name: MMC Tran Speed: 5200 Rd Block Len: 512 MMC version 4.0 High Capacity: No Capacity: 1.9 GiB Bus Width: 4-bit When I revert this path, I am unable to see the status error. zynq-uboot mmcinfo Device: zynq_sdhci Manufacturer ID: 1e OEM: Name: MMC Tran Speed: 5200 Rd Block Len: 512 MMC version 4.0 High Capacity: No Capacity: 1.9 GiB Bus Width: 12-bit I think the above one is also a buggy as my controller is unable to support 12-bit bus width.? Could you check which bus_width support at your controller? I guess it is set to wrong buswidth. Yes, this what the buggy message is for. My controller supports only 1 and 4-bit. Thanks, Jagan. This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] MIPS: remove OUTPUT_FORMAT from linker scripts
The OUTPUT_FORMAT command in linker scripts was always misused due to some endianess and toolchain problems. Use GCC flags to ensure proper output format, and get rid of the OUTPUT_FORMAT commands in the board specific u-boot.lds files. Signed-off-by: Gabor Juhos juh...@openwrt.org Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com Cc: Stefan Roese s...@denx.de Cc: Wolfgang Denk w...@denx.de Cc: Xiangfu Liu xian...@openmobilefree.net --- arch/mips/cpu/mips32/config.mk |6 ++ arch/mips/cpu/xburst/config.mk |6 ++ board/dbau1x00/u-boot.lds |4 board/incaip/u-boot.lds|4 board/micronas/vct/u-boot.lds |1 - board/pb1x00/u-boot.lds|4 board/qemu-mips/u-boot.lds |8 board/qi/qi_lb60/u-boot.lds|2 -- 8 files changed, 12 insertions(+), 23 deletions(-) diff --git a/arch/mips/cpu/mips32/config.mk b/arch/mips/cpu/mips32/config.mk index 481e984..7399701 100644 --- a/arch/mips/cpu/mips32/config.mk +++ b/arch/mips/cpu/mips32/config.mk @@ -30,5 +30,11 @@ MIPSFLAGS := -march=mips32r2 PLATFORM_CPPFLAGS += $(MIPSFLAGS) +PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT +ifdef CONFIG_SYS_BIG_ENDIAN +PLATFORM_LDFLAGS += -m elf32btsmip +else +PLATFORM_LDFLAGS += -m elf32ltsmip +endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x8020 -T mips.lds diff --git a/arch/mips/cpu/xburst/config.mk b/arch/mips/cpu/xburst/config.mk index 1536746..cf5fa6a 100644 --- a/arch/mips/cpu/xburst/config.mk +++ b/arch/mips/cpu/xburst/config.mk @@ -21,5 +21,11 @@ # PLATFORM_CPPFLAGS += -march=mips32 +PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT +ifdef CONFIG_SYS_BIG_ENDIAN +PLATFORM_LDFLAGS += -m elf32btsmip +else +PLATFORM_LDFLAGS += -m elf32ltsmip +endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x8020 -T mips.lds diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds index 8a871cf..d9c01af 100644 --- a/board/dbau1x00/u-boot.lds +++ b/board/dbau1x00/u-boot.lds @@ -21,10 +21,6 @@ * MA 02111-1307 USA */ -/* -OUTPUT_FORMAT(elf32-bigmips, elf32-bigmips, elf32-bigmips) -*/ -OUTPUT_FORMAT(elf32-tradbigmips, elf32-tradbigmips, elf32-tradlittlemips) OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds index 8a871cf..d9c01af 100644 --- a/board/incaip/u-boot.lds +++ b/board/incaip/u-boot.lds @@ -21,10 +21,6 @@ * MA 02111-1307 USA */ -/* -OUTPUT_FORMAT(elf32-bigmips, elf32-bigmips, elf32-bigmips) -*/ -OUTPUT_FORMAT(elf32-tradbigmips, elf32-tradbigmips, elf32-tradlittlemips) OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/micronas/vct/u-boot.lds b/board/micronas/vct/u-boot.lds index 2ce8d0e..cc7db1b 100644 --- a/board/micronas/vct/u-boot.lds +++ b/board/micronas/vct/u-boot.lds @@ -21,7 +21,6 @@ * MA 02111-1307 USA */ -OUTPUT_FORMAT(elf32-tradbigmips, elf32-tradbigmips, elf32-tradlittlemips) OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds index 07ddd36..d9c01af 100644 --- a/board/pb1x00/u-boot.lds +++ b/board/pb1x00/u-boot.lds @@ -21,10 +21,6 @@ * MA 02111-1307 USA */ -/* -OUTPUT_FORMAT(elf32-bigmips, elf32-bigmips, elf32-bigmips) -*/ -OUTPUT_FORMAT(elf32-tradlittlemips, elf32-tradbigmips, elf32-tradlittlemips) OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds index cb2356f..33b42f3 100644 --- a/board/qemu-mips/u-boot.lds +++ b/board/qemu-mips/u-boot.lds @@ -21,14 +21,6 @@ * MA 02111-1307 USA */ -/* -OUTPUT_FORMAT(elf32-bigmips, elf32-bigmips, elf32-bigmips) -*/ -#if defined(CONFIG_64BIT) -OUTPUT_FORMAT(elf64-tradbigmips, elf64-tradbigmips, elf64-tradlittlemips) -#else -OUTPUT_FORMAT(elf32-tradbigmips, elf32-tradbigmips, elf32-tradlittlemips) -#endif OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/qi/qi_lb60/u-boot.lds b/board/qi/qi_lb60/u-boot.lds index b3cb869..d074a27 100644 --- a/board/qi/qi_lb60/u-boot.lds +++ b/board/qi/qi_lb60/u-boot.lds @@ -18,8 +18,6 @@ * MA 02111-1307 USA */ -OUTPUT_FORMAT(elf32-tradlittlemips, elf32-tradlittlemips, elf32-tradlittlemips) - OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS -- 1.7.10 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 05/10] mxs: Fix iomux.h to not break build during assembly stage
On Wed, Jan 30, 2013 at 10:13 AM, Otavio Salvador ota...@ossystems.com.br wrote: This fixes the build failure when included in mx23_olinuxino.h board Which build failure? Can you post the error? I think you can drop this patch from the series now that you do not pass the iomux definitions in patch 6/10. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] board: xilinx: Remove unused ancient i2c driver
Dear Michal, On 2013.01/23, Michal Simek wrote: There is new driver in the driver folder. Signed-off-by: Michal Simek michal.si...@xilinx.com --- board/xilinx/xilinx_iic/xiic_l.c | 484 -- board/xilinx/xilinx_iic/xiic_l.h | 150 2 files changed, 0 insertions(+), 634 deletions(-) delete mode 100644 board/xilinx/xilinx_iic/xiic_l.c delete mode 100644 board/xilinx/xilinx_iic/xiic_l.h Tested-by: Rommel Custodio sessya...@gmail.com All the best, Rommel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 05/10] mxs: Fix iomux.h to not break build during assembly stage
On Wed, Jan 30, 2013 at 10:24 AM, Fabio Estevam feste...@gmail.com wrote: On Wed, Jan 30, 2013 at 10:13 AM, Otavio Salvador ota...@ossystems.com.br wrote: This fixes the build failure when included in mx23_olinuxino.h board Which build failure? Can you post the error? I think you can drop this patch from the series now that you do not pass the iomux definitions in patch 6/10. Yes; we do not use this anymore. Without this patch it fails badly as it try to use the functions in assembly. This fixes it anyway so I think it could go in anyway so if someone needs it in mx23evk or mx23_olinuxino board files it won't fail to build anymore. -- Otavio Salvador O.S. Systems E-mail: ota...@ossystems.com.br http://www.ossystems.com.br Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] board: xilinx: Remove common folder
Dear Michal, On 2013.01/23, Michal Simek wrote: All these files was used for ancient xilinx drivers which are finally gone. Signed-off-by: Michal Simek michal.si...@xilinx.com --- board/xilinx/common/xbasic_types.c | 165 board/xilinx/common/xbasic_types.h | 283 -- board/xilinx/common/xbuf_descriptor.h | 252 -- board/xilinx/common/xdma_channel.c | 738 board/xilinx/common/xdma_channel.h | 291 -- board/xilinx/common/xdma_channel_i.h | 110 --- board/xilinx/common/xdma_channel_sg.c | 1317 board/xilinx/common/xio.h | 81 -- board/xilinx/common/xipif_v1_23_b.c| 331 --- board/xilinx/common/xipif_v1_23_b.h| 746 board/xilinx/common/xpacket_fifo_v1_00_b.c | 448 -- board/xilinx/common/xpacket_fifo_v1_00_b.h | 306 --- board/xilinx/common/xstatus.h | 347 board/xilinx/common/xversion.c | 350 board/xilinx/common/xversion.h | 97 -- board/xilinx/zynq/Makefile |3 - 16 files changed, 0 insertions(+), 5865 deletions(-) delete mode 100644 board/xilinx/common/xbasic_types.c delete mode 100644 board/xilinx/common/xbasic_types.h delete mode 100644 board/xilinx/common/xbuf_descriptor.h delete mode 100644 board/xilinx/common/xdma_channel.c delete mode 100644 board/xilinx/common/xdma_channel.h delete mode 100644 board/xilinx/common/xdma_channel_i.h delete mode 100644 board/xilinx/common/xdma_channel_sg.c delete mode 100644 board/xilinx/common/xio.h delete mode 100644 board/xilinx/common/xipif_v1_23_b.c delete mode 100644 board/xilinx/common/xipif_v1_23_b.h delete mode 100644 board/xilinx/common/xpacket_fifo_v1_00_b.c delete mode 100644 board/xilinx/common/xpacket_fifo_v1_00_b.h delete mode 100644 board/xilinx/common/xstatus.h delete mode 100644 board/xilinx/common/xversion.c delete mode 100644 board/xilinx/common/xversion.h Tested-by: Rommel Custodio sessya...@gmail.com All the best, Rommel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Help : Marvell SDIO/MMC driver for Sheevaplug
On 2013.01/29, DrEagle wrote: Hi all, -Original Message- From: u-boot-bounces at lists.denx.de [mailto:u-boot- bounces at lists.denx.de] On Behalf Of DrEagle Sent: 22 September 2012 12:45 To: DrEagle Cc: Lior Amsalem; u-boot at lists.denx.de; uboot at doukki.net Subject: [U-Boot] [PATCH v2 0/5] Marvell SDIO/MMC driver for Sheevaplug This serie of patch add SDIO/MMC support to Sheevaplug board Change from v1: - Fix an issue with most SDHC cards because of timeout delay drEagle (5): Add Marvell SDIO/MMC driver for Kirkwood SoC Add SDIO/MMC support for kirkwood SoC Add SDIO/MMC support for Sheevaplug board Fix env address for Sheevaplug board Fix timeout in Marvell SDIO MMC driver Hi DrEagle I still request you to study mvsdhci.c which is similar framework used for Pantheon family of SoCs, try to use this infrastructure is possible for Kirkwood support. Regards... Prafulla . . . I have started looking at sdhci component but I find only theses small details : ... 9) mv_sdhci.c - This is a component of the SDHCI support, allowing it to run on Marvell Kirkwood chip. It is probable the SDHCI support will have to be modified to allow calling functions from this file based on information passed via platform_data. Slow down ... AFAIK u-boot does not have a platform_data. You might be confusing the Linux kernel with u-boot code. ... 16) sdhci.c --- Follows the new API and also has a good encapsulation of the whole driver. The conversion here will be simple, though it'd be necessary to modify this driver to also support the Kirkwood series and probably also Tegra series of CPUs. See the respective parts of this section for details. ... Can anybody give me more advice on how to port efficiently a patch for SDIO/MMC for SheevaPlug/Kirkwood SoC while using, as Prafulla asked, the *sdhci* framework. The u-boot SDHCI framework is simple. mmc.c and sdhci.c implements the basic core functionality for SD/MMC access. The developer has to define the controller as Jagan mentioned in another e-mail. In defining the controller you can provide your register access functions (XXX_ACCESSORS) for those host controllers that don't follow the SD Host contoller register layout or for quirks in accessing the registers. All the best, Rommel What are the best practices and the technical details which can help me into this ? Regards, drEagle ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] board: xilinx: Remove unused ancient i2c driver
Hello Michal, On 23.01.2013 14:31, Michal Simek wrote: There is new driver in the driver folder. Signed-off-by: Michal Simek michal.si...@xilinx.com --- board/xilinx/xilinx_iic/xiic_l.c | 484 -- board/xilinx/xilinx_iic/xiic_l.h | 150 2 files changed, 0 insertions(+), 634 deletions(-) delete mode 100644 board/xilinx/xilinx_iic/xiic_l.c delete mode 100644 board/xilinx/xilinx_iic/xiic_l.h Thanks! Acked-by: Heiko Schocher h...@denx.de bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] can i in u-boot partition a device and format it in fat ?
Hi, i had a look at the u-boot cmd's. I can read/write a file from/to a dos partition but I didn't find a command for partitioning and formatting a device. Pls ,I need help in this context Mit freundlichen Grüßen / Best regards Sabri Altunbas (DC-IA/EAH2) Tel. +49 (0) 6062/78-526 Fax +49 (0) 6062/78-771 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] PHY: micrel.c: add support for KSZ9031
Add support for Micrel PHY KSZ9031 in phylib,
including small rework for KSZ9021 to avoid code
duplication
Signed-off-by: David Andrey david.and...@netmodule.com
---
drivers/net/phy/micrel.c | 83 +++---
1 files changed, 63 insertions(+), 20 deletions(-)
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 30f3264..a7d53a1 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -18,6 +18,7 @@
*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
+ * (C) 2012 NetModule AG, added KSZ9031
*
*/
#include config.h
@@ -52,16 +53,49 @@ static struct phy_driver KS8721_driver = {
};
#endif
+
+/**
+ * KSZ9021 - KSZ9031 common
+ */
+
+#define MII_KSZ90xx_PHY_CTL0x1f
+#define MIIM_KSZ90xx_PHYCTL_1000 (1 6)
+#define MIIM_KSZ90xx_PHYCTL_100(1 5)
+#define MIIM_KSZ90xx_PHYCTL_10 (1 4)
+#define MIIM_KSZ90xx_PHYCTL_DUPLEX (1 3)
+
+/* Update speed and duplex state */
+static int ksz90xx_phy_state(struct phy_device *phydev)
+{
+ unsigned phy_ctl;
+
+ phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
+
+ if (phy_ctl MIIM_KSZ90xx_PHYCTL_DUPLEX)
+ phydev-duplex = DUPLEX_FULL;
+ else
+ phydev-duplex = DUPLEX_HALF;
+
+ if (phy_ctl MIIM_KSZ90xx_PHYCTL_1000)
+ phydev-speed = SPEED_1000;
+ else if (phy_ctl MIIM_KSZ90xx_PHYCTL_100)
+ phydev-speed = SPEED_100;
+ else if (phy_ctl MIIM_KSZ90xx_PHYCTL_10)
+ phydev-speed = SPEED_10;
+ return 0;
+}
+
+
#ifdef CONFIG_PHY_MICREL_KSZ9021
-/* ksz9021 PHY Registers */
+
+/*
+ * KSZ9031
+ */
+
+/* PHY Registers */
#define MII_KSZ9021_EXTENDED_CTRL 0x0b
#define MII_KSZ9021_EXTENDED_DATAW 0x0c
#define MII_KSZ9021_EXTENDED_DATAR 0x0d
-#define MII_KSZ9021_PHY_CTL0x1f
-#define MIIM_KSZ9021_PHYCTL_1000 (1 6)
-#define MIIM_KSZ9021_PHYCTL_100(1 5)
-#define MIIM_KSZ9021_PHYCTL_10 (1 4)
-#define MIIM_KSZ9021_PHYCTL_DUPLEX (1 3)
#define CTRL1000_PREFER_MASTER (1 10)
#define CTRL1000_CONFIG_MASTER (1 11)
@@ -108,21 +142,8 @@ static int ksz9021_config(struct phy_device *phydev)
static int ksz9021_startup(struct phy_device *phydev)
{
- unsigned phy_ctl;
genphy_update_link(phydev);
- phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_PHY_CTL);
-
- if (phy_ctl MIIM_KSZ9021_PHYCTL_DUPLEX)
- phydev-duplex = DUPLEX_FULL;
- else
- phydev-duplex = DUPLEX_HALF;
-
- if (phy_ctl MIIM_KSZ9021_PHYCTL_1000)
- phydev-speed = SPEED_1000;
- else if (phy_ctl MIIM_KSZ9021_PHYCTL_100)
- phydev-speed = SPEED_100;
- else if (phy_ctl MIIM_KSZ9021_PHYCTL_10)
- phydev-speed = SPEED_10;
+ ksz90xx_phy_state(phydev);
return 0;
}
@@ -137,6 +158,27 @@ static struct phy_driver ksz9021_driver = {
};
#endif
+/*
+ * KSZ9031
+ */
+static int ksz9031_startup(struct phy_device *phydev)
+{
+ genphy_update_link(phydev);
+ ksz90xx_phy_state(phydev);
+ return 0;
+}
+
+static struct phy_driver ksz9031_driver = {
+ .name = Micrel ksz9031,
+ .uid = 0x221620,
+ .mask = 0xfe,
+ .features = PHY_GBIT_FEATURES,
+ .config = genphy_config,
+ .startup = ksz9031_startup,
+ .shutdown = genphy_shutdown,
+};
+
+
int phy_micrel_init(void)
{
phy_register(KSZ804_driver);
@@ -145,5 +187,6 @@ int phy_micrel_init(void)
#else
phy_register(KS8721_driver);
#endif
+ phy_register(ksz9031_driver);
return 0;
}
--
1.7.4.1
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Re: [U-Boot] [PATCH 02/10] mx23: Document the tRAS lockout setting in memory initialization
Dear Otavio Salvador, Add a comment about the tRAS lockout setting of HW_DRAM_CTL08 to enable the 'Fast Auto Pre-Charge' found in the memory chip. The setting is applied after memory initialization and it is worth document it. Signed-off-by: Otavio Salvador ota...@ossystems.com.br --- arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index f8392f6..37b50e9 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -119,6 +119,7 @@ static void initialize_dram_values(void) writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); #ifdef CONFIG_MX23 + /* Enable tRAS lockout in HW_DRAM_CTL08 */ This does not explain why it must be here and not in the dram_vals table. It would be nice to explain it here, since it'd prevent others from sending patch stuffing it into the dram_vals table without knowing it must definitelly be here. But why does it have to be here? I wonder ... writel((1 24), MXS_DRAM_BASE + (4 * 8)); #endif } Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 01/10] mxs: Rename CONFIG_SPL_MX28_PSWITCH_WAIT to CONFIG_SPL_MXS_PSWITCH_WAIT
Dear Otavio Salvador, The power switch option is compatible with i.MX23 and i.MX28 so the configration option needs to reflect it. We choose 'CONFIG_SPL_MXS_PSWITCH_WAIT' for the option name. Acked-by: Marek Vasut ma...@denx.de I'm missing cover letter for this large series. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 03/10] mx23evk: Adjust DRAM control register to use full 128MB of RAM
Dear Otavio Salvador,
Adjust HW_DRAM_CTL14 to enable the chip selects to allow usage of full
128MB of RAM.
Signed-off-by: Otavio Salvador ota...@ossystems.com.br
Just enable the full set for all in the generic memory register set (dram_vals)?
---
board/freescale/mx23evk/spl_boot.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/board/freescale/mx23evk/spl_boot.c
b/board/freescale/mx23evk/spl_boot.c index 6007433..b6f4e7e 100644
--- a/board/freescale/mx23evk/spl_boot.c
+++ b/board/freescale/mx23evk/spl_boot.c
@@ -98,6 +98,16 @@ const iomux_cfg_t iomux_setup[] = {
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
};
+#define HW_DRAM_CTL14(0x38 2)
+#define CS_MAP 0x3
+#define INTAREF 0x2
+#define HW_DRAM_CTL14_CONFIG (INTAREF 8 | CS_MAP)
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+ dram_vals[HW_DRAM_CTL14] = HW_DRAM_CTL14_CONFIG;
+}
+
void board_init_ll(void)
{
mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 10/10] mx23_olinuxino: Add ethernet support
Dear Otavio Salvador,
This adds support to the LAN9512 chip included in the board and extend
the environment to easy netboot use.
Signed-off-by: Otavio Salvador ota...@ossystems.com.br
---
board/olimex/mx23_olinuxino/mx23_olinuxino.c | 6 +
board/olimex/mx23_olinuxino/spl_boot.c | 4 +++
include/configs/mx23_olinuxino.h | 40
+--- 3 files changed, 47 insertions(+), 3
deletions(-)
diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c
b/board/olimex/mx23_olinuxino/mx23_olinuxino.c index 2501417..9ed7718
100644
--- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c
+++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c
@@ -23,6 +23,7 @@
*/
#include common.h
+#include asm/gpio.h
#include asm/io.h
#include asm/arch/iomux-mx23.h
#include asm/arch/imx-regs.h
@@ -45,6 +46,11 @@ int board_early_init_f(void)
/* SSP0 clock at 96MHz */
mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+#ifdef CONFIG_CMD_USB
+ /* Enable LAN9512 */
+ gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 1);
+#endif
+
return 0;
}
diff --git a/board/olimex/mx23_olinuxino/spl_boot.c
b/board/olimex/mx23_olinuxino/spl_boot.c index 3bbf5ad..a96c293 100644
--- a/board/olimex/mx23_olinuxino/spl_boot.c
+++ b/board/olimex/mx23_olinuxino/spl_boot.c
@@ -95,6 +95,10 @@ const iomux_cfg_t iomux_setup[] = {
MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP,
MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP,
MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP,
+
+ /* Ethernet */
+ MX23_PAD_GPMI_ALE__GPIO_0_17 |
+ (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
};
void board_init_ll(void)
diff --git a/include/configs/mx23_olinuxino.h
b/include/configs/mx23_olinuxino.h index 7e17809..42de557 100644
--- a/include/configs/mx23_olinuxino.h
+++ b/include/configs/mx23_olinuxino.h
@@ -53,11 +53,13 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_LED
#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
#define CONFIG_CMD_USB
/*
@@ -148,6 +150,12 @@
#define CONFIG_USB_STORAGE
#endif
+/* Ethernet */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#endif
+
/*
* Boot Linux
*/
Split the env from this patch into separate one ; merge the rest into the 09/10
as the SMC device is also a hub etc.
Best regards,
Marek Vasut
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[U-Boot] [PATCH v2 0/7] MIPS: use an unified u-boot.lds script
This patch-set adds an unfied u-boot.lds file for the MIPS architecture, and removes the linker scripts of the individual boards. The series depends on the following patch: MIPS: remove OUTPUT_FORMAT from linker scripts http://patchwork.ozlabs.org/patch/216892/ Gabor Juhos (7): MIPS: add unified u-boot.lds file MIPS: qemu-mips: use the unified u-boot.lds script MIPS: pb1x00: remove custom u-boot.lds script MIPS: vct: remove custom u-boot.lds script MIPS: incaip: remove custom u-boot.lds script MIPS: dbau1x00: remove custom u-boot.lds script MIPS: qi_lb60: remove custom u-boot.lds script arch/mips/cpu/u-boot.lds | 84 + board/dbau1x00/u-boot.lds | 65 --- board/incaip/u-boot.lds | 65 --- board/micronas/vct/u-boot.lds | 68 - board/pb1x00/u-boot.lds | 65 --- board/qemu-mips/u-boot.lds| 70 -- board/qi/qi_lb60/u-boot.lds | 61 -- 7 files changed, 84 insertions(+), 394 deletions(-) create mode 100644 arch/mips/cpu/u-boot.lds delete mode 100644 board/dbau1x00/u-boot.lds delete mode 100644 board/incaip/u-boot.lds delete mode 100644 board/micronas/vct/u-boot.lds delete mode 100644 board/pb1x00/u-boot.lds delete mode 100644 board/qemu-mips/u-boot.lds delete mode 100644 board/qi/qi_lb60/u-boot.lds -- 1.7.10 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 0/7] MIPS: use an unified u-boot.lds script
This patch-set adds an unfied u-boot.lds file for the MIPS architecture, and removes the linker scripts of the individual boards. The series depends on the following patch: MIPS: remove OUTPUT_FORMAT from linker scripts http://patchwork.ozlabs.org/patch/216892/ Gabor Juhos (7): MIPS: add unified u-boot.lds file MIPS: qemu-mips: use the unified u-boot.lds script MIPS: pb1x00: remove custom u-boot.lds script MIPS: vct: remove custom u-boot.lds script MIPS: incaip: remove custom u-boot.lds script MIPS: dbau1x00: remove custom u-boot.lds script MIPS: qi_lb60: remove custom u-boot.lds script arch/mips/cpu/u-boot.lds | 84 + board/dbau1x00/u-boot.lds | 65 --- board/incaip/u-boot.lds | 65 --- board/micronas/vct/u-boot.lds | 68 - board/pb1x00/u-boot.lds | 65 --- board/qemu-mips/u-boot.lds| 70 -- board/qi/qi_lb60/u-boot.lds | 61 -- 7 files changed, 84 insertions(+), 394 deletions(-) create mode 100644 arch/mips/cpu/u-boot.lds delete mode 100644 board/dbau1x00/u-boot.lds delete mode 100644 board/incaip/u-boot.lds delete mode 100644 board/micronas/vct/u-boot.lds delete mode 100644 board/pb1x00/u-boot.lds delete mode 100644 board/qemu-mips/u-boot.lds delete mode 100644 board/qi/qi_lb60/u-boot.lds -- 1.7.10 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 5/7] MIPS: incaip: remove custom u-boot.lds script
Remove the board specific linker script. It is not
needed anymore, the unified MIPS linker script can
be used instead.
All incaip targets are producing identical binary
images after the change than before.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
Cc: Wolfgang Denk w...@denx.de
---
Changes since v1: ---
---
board/incaip/u-boot.lds | 65 ---
1 file changed, 65 deletions(-)
delete mode 100644 board/incaip/u-boot.lds
diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds
deleted file mode 100644
index d9c01af..000
--- a/board/incaip/u-boot.lds
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, w...@denx.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x;
-
- . = ALIGN(4);
- .text :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data*) }
-
- . = .;
- _gp = ALIGN(16) + 0x7ff0;
-
- .got : {
- __got_start = .;
- *(.got)
- __got_end = .;
- }
-
- .sdata : { *(.sdata*) }
-
- . = ALIGN(4);
- .u_boot_list : {
- #include u-boot.lst
- }
-
- uboot_end_data = .;
- num_got_entries = (__got_end - __got_start) 2;
-
- . = ALIGN(4);
- .sbss (NOLOAD) : { *(.sbss*) }
- .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
- uboot_end = .;
-}
--
1.7.10
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[U-Boot] [PATCH v2 4/7] MIPS: vct: remove custom u-boot.lds script
Remove the board specific linker script. It is not
needed anymore, the unified MIPS linker script can
be used instead.
All vct targets are producing identical binary
images after the change than before.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Acked-by: Stefan Roese s...@denx.de
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
---
Changes since v1: ---
---
board/micronas/vct/u-boot.lds | 68 -
1 file changed, 68 deletions(-)
delete mode 100644 board/micronas/vct/u-boot.lds
diff --git a/board/micronas/vct/u-boot.lds b/board/micronas/vct/u-boot.lds
deleted file mode 100644
index cc7db1b..000
--- a/board/micronas/vct/u-boot.lds
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, w...@denx.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x;
-
- . = ALIGN(4);
- .text :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data*) }
-
- . = .;
- _gp = ALIGN(16) + 0x7ff0;
-
- .got : {
- __got_start = .;
- *(.got)
- __got_end = .;
- }
-
- . = ALIGN(4);
- .sdata : { *(.sdata*) }
-
- . = ALIGN(4);
- .u_boot_list : {
- #include u-boot.lst
- }
-
- . = ALIGN(4);
- uboot_end_data = .;
- num_got_entries = (__got_end - __got_start) 2;
-
- . = ALIGN(4);
- .sbss (NOLOAD) : { *(.sbss*) }
- . = ALIGN(4);
- .bss (NOLOAD) : { *(.bss*) }
- uboot_end = .;
-}
--
1.7.10
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[U-Boot] [PATCH v2 3/7] MIPS: pb1x00: remove custom u-boot.lds script
Remove the board specific linker script. It is not
needed anymore, the unified MIPS linker script can
be used instead.
All pb1x00 targets are producing identical binary
images after the change than before.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
---
Changes since v1: ---
---
board/pb1x00/u-boot.lds | 65 ---
1 file changed, 65 deletions(-)
delete mode 100644 board/pb1x00/u-boot.lds
diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds
deleted file mode 100644
index d9c01af..000
--- a/board/pb1x00/u-boot.lds
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, w...@denx.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x;
-
- . = ALIGN(4);
- .text :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data*) }
-
- . = .;
- _gp = ALIGN(16) + 0x7ff0;
-
- .got : {
- __got_start = .;
- *(.got)
- __got_end = .;
- }
-
- .sdata : { *(.sdata*) }
-
- . = ALIGN(4);
- .u_boot_list : {
- #include u-boot.lst
- }
-
- uboot_end_data = .;
- num_got_entries = (__got_end - __got_start) 2;
-
- . = ALIGN(4);
- .sbss (NOLOAD) : { *(.sbss*) }
- .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
- uboot_end = .;
-}
--
1.7.10
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[U-Boot] [PATCH v2 2/7] MIPS: qemu-mips: use the unified u-boot.lds script
Remove the board specific linker script. It is not
needed anymore, the unified MIPS linker script can
be used instead.
All qemu_mips targets are producing identical binary
images after the change than before.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
---
Changes since v1: ---
---
board/qemu-mips/u-boot.lds | 70
1 file changed, 70 deletions(-)
delete mode 100644 board/qemu-mips/u-boot.lds
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds
deleted file mode 100644
index 33b42f3..000
--- a/board/qemu-mips/u-boot.lds
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, w...@denx.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x;
-
- . = ALIGN(4);
- .text :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data*) }
-
- . = .;
- _gp = ALIGN(16) +0x7ff0;
-
- .got : {
- __got_start = .;
- *(.got)
- __got_end = .;
- }
-
- . = ALIGN(4);
- .sdata : { *(.sdata*) }
-
- . = ALIGN(4);
- .u_boot_list : {
- #include u-boot.lst
- }
-
- uboot_end_data = .;
-#if defined(CONFIG_64BIT)
- num_got_entries = (__got_end - __got_start) 3;
-#else
- num_got_entries = (__got_end - __got_start) 2;
-#endif
-
- . = ALIGN(4);
- .sbss : { *(.sbss*) }
- .bss : { *(.bss*) . = ALIGN(4); }
- uboot_end = .;
-}
--
1.7.10
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[U-Boot] [PATCH v2 1/7] MIPS: add unified u-boot.lds file
The patch adds an unified linker script file which
can be used for all currently supported MIPS targets.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
Cc: Stefan Roese s...@denx.de
Cc: Wolfgang Denk w...@denx.de
Cc: Xiangfu Liu xian...@openmobilefree.net
---
Changes since v1:
- use consistent coding style for all sections
- remove the OUTPUT_FORMAT command from the
unified script
---
arch/mips/cpu/u-boot.lds | 84 ++
1 file changed, 84 insertions(+)
create mode 100644 arch/mips/cpu/u-boot.lds
diff --git a/arch/mips/cpu/u-boot.lds b/arch/mips/cpu/u-boot.lds
new file mode 100644
index 000..37c9d23
--- /dev/null
+++ b/arch/mips/cpu/u-boot.lds
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, w...@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#if defined(CONFIG_64BIT)
+#define PTR_COUNT_SHIFT3
+#else
+#define PTR_COUNT_SHIFT2
+#endif
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x;
+
+ . = ALIGN(4);
+ .text : {
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
+
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
+
+ . = ALIGN(4);
+ .sdata : {
+ *(.sdata*)
+ }
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include u-boot.lst
+ }
+
+ uboot_end_data = .;
+
+ num_got_entries = (__got_end - __got_start) PTR_COUNT_SHIFT;
+
+ . = ALIGN(4);
+ .sbss : {
+ *(.sbss*)
+ }
+
+ .bss : {
+ *(.bss*)
+ . = ALIGN(4);
+ }
+ uboot_end = .;
+}
--
1.7.10
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[U-Boot] [PATCH v2 6/7] MIPS: dbau1x00: remove custom u-boot.lds script
Remove the board specific linker script. It is not
needed anymore, the unified MIPS linker script can
be used instead.
All dbau1x00 targets are producing identical binary
images after the change than before.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
---
Changes since v1: ---
---
board/dbau1x00/u-boot.lds | 65 -
1 file changed, 65 deletions(-)
delete mode 100644 board/dbau1x00/u-boot.lds
diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds
deleted file mode 100644
index d9c01af..000
--- a/board/dbau1x00/u-boot.lds
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, w...@denx.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x;
-
- . = ALIGN(4);
- .text :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data*) }
-
- . = .;
- _gp = ALIGN(16) + 0x7ff0;
-
- .got : {
- __got_start = .;
- *(.got)
- __got_end = .;
- }
-
- .sdata : { *(.sdata*) }
-
- . = ALIGN(4);
- .u_boot_list : {
- #include u-boot.lst
- }
-
- uboot_end_data = .;
- num_got_entries = (__got_end - __got_start) 2;
-
- . = ALIGN(4);
- .sbss (NOLOAD) : { *(.sbss*) }
- .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
- uboot_end = .;
-}
--
1.7.10
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[U-Boot] [PATCH v2 7/7] MIPS: qi_lb60: remove custom u-boot.lds script
Remove the board specific linker script. It is not
needed anymore, the unified MIPS linker script can
be used instead.
The qi_lb60 target produces a slightly different
image after the change than before. The value of
'num_got_entries' symbol is different:
@@ -49,7 +49,7 @@
801000b4: 80122d00lb s2,11520(zero)
801000b8: 80123500lb s2,13568(zero)
801000bc: 80123ef8lb s2,16120(zero)
-801000c0: 01390x139
+801000c0: 0136tne zero,zero,0x4
801000c4 in_ram:
801000c4: 8d0bfffclw t3,-4(t0)
This is caused by the different placement of the
'__got_start' and '__got_end' symbols between the
board specific scrip and the unified script.
board specific script:
__got_start = .;
.got : { *(.got) }
__got_end = .;
unified script:
.got : {
__got_start = .;
*(.got)
__got_end = .;
}
Despite this difference, the resulting images are
functionally identical.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
Cc: Xiangfu Liu xian...@openmobilefree.net
---
Changes since v1: ---
---
board/qi/qi_lb60/u-boot.lds | 61 ---
1 file changed, 61 deletions(-)
delete mode 100644 board/qi/qi_lb60/u-boot.lds
diff --git a/board/qi/qi_lb60/u-boot.lds b/board/qi/qi_lb60/u-boot.lds
deleted file mode 100644
index d074a27..000
--- a/board/qi/qi_lb60/u-boot.lds
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * (C) Copyright 2006
- * Ingenic Semiconductor, jl...@ingenic.cn
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x;
-
- . = ALIGN(4);
- .text :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data*) }
-
- . = .;
- _gp = ALIGN(16) + 0x7ff0;
-
- __got_start = .;
- .got : { *(.got) }
- __got_end = .;
-
- .sdata : { *(.sdata*) }
-
-
- . = ALIGN(4);
- .u_boot_list : {
- #include u-boot.lst
- }
-
- uboot_end_data = .;
- num_got_entries = (__got_end - __got_start) 2;
-
- . = ALIGN(4);
- .sbss : { *(.sbss*) }
- .bss : { *(.bss*) . = ALIGN(4); }
- uboot_end = .;
-}
--
1.7.10
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Re: [U-Boot] [PATCH v2 1/7] MIPS: add unified u-boot.lds file
On 01/30/2013 03:31 PM, Gabor Juhos wrote: The patch adds an unified linker script file which can be used for all currently supported MIPS targets. Signed-off-by: Gabor Juhos juh...@openwrt.org Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com Cc: Stefan Roese s...@denx.de Cc: Wolfgang Denk w...@denx.de Cc: Xiangfu Liu xian...@openmobilefree.net Again, can't test but looks good. Thanks. Acked-by: Stefan Roese s...@denx.de Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] MIPS: xburst: simplify relocation offset calculation
The current code uses four instructions and a temporary register to calculate the relocation offset and to adjust the gp register. The relocation offset can be calculated directly from the CONFIG_SYS_MONITOR_BASE constant and from the destination address. The resulting offset can be used to adjust the gp pointer. This approach makes the code a bit simpler because it needs two instructions only. Signed-off-by: Gabor Juhos juh...@openwrt.org Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com Cc: Xiangfu Liu xian...@openmobilefree.net --- arch/mips/cpu/xburst/start.S | 12 +++- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S index 194d745..35728eb 100644 --- a/arch/mips/cpu/xburst/start.S +++ b/arch/mips/cpu/xburst/start.S @@ -64,19 +64,13 @@ relocate_code: movesp, a0 # set new stack pointer li t0, CONFIG_SYS_MONITOR_BASE + sub t6, a2, t0 # t6 -- relocation offset + la t3, in_ram lw t2, -12(t3) # t2 -- uboot_end_data movet1, a2 - /* -* Fix $gp: -* -* New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address -*/ - movet6, gp - sub gp, CONFIG_SYS_MONITOR_BASE - add gp, a2 # gp now adjusted - sub t6, gp, t6 # t6 -- relocation offset + add gp, t6 # adjust gp /* * t0 = source address -- 1.7.10 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] MIPS: simplify relocated _G_O_T_ address calculation
The difference between the address of the original and the relocated _GLOBAL_OFFSET_TABLE_ is always the same as the relocation offset. The relocation offset is already computed and it is available in the 's1/t6' register. Use that to adjust the relocated _G_O_T_ address, instead of calculating the offset again from the _gp value. Signed-off-by: Gabor Juhos juh...@openwrt.org Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com Cc: Xiangfu Liu xian...@openmobilefree.net --- Changes since v1: modify Xburst code as well This depends on the: 'MIPS: xburst: simplify relocation offset calculation' patch http://patchwork.ozlabs.org/patch/216934/ and supersedes this one: http://patchwork.ozlabs.org/patch/214350/ --- arch/mips/cpu/mips32/start.S |5 + arch/mips/cpu/mips64/start.S |5 + arch/mips/cpu/xburst/start.S |5 + 3 files changed, 3 insertions(+), 12 deletions(-) diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index 77f1103..51ce914 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -314,7 +314,6 @@ relocate_code: jr t0 nop - .word _gp .word _GLOBAL_OFFSET_TABLE_ .word uboot_end_data .word uboot_end @@ -329,9 +328,7 @@ in_ram: */ lw t3, -4(t0) # t3 -- num_got_entries lw t4, -16(t0) # t4 -- _GLOBAL_OFFSET_TABLE_ - lw t5, -20(t0) # t5 -- _gp - sub t4, t5 # compute offset - add t4, t4, gp # t4 now holds relocated _G_O_T_ + add t4, s1 # t4 now holds relocated _G_O_T_ addit4, t4, 8 # skipping first two entries li t2, 2 1: diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S index 80e6bb1..1522594 100644 --- a/arch/mips/cpu/mips64/start.S +++ b/arch/mips/cpu/mips64/start.S @@ -193,7 +193,6 @@ relocate_code: jr t0 nop - .dword _gp .dword _GLOBAL_OFFSET_TABLE_ .dword uboot_end_data .dword uboot_end @@ -208,9 +207,7 @@ in_ram: */ ld t3, -8(t0) # t3 -- num_got_entries ld t8, -32(t0) # t8 -- _GLOBAL_OFFSET_TABLE_ - ld t9, -40(t0) # t9 -- _gp - dsubt8, t9 # compute offset - daddt8, t8, gp # t8 now holds relocated _G_O_T_ + daddt8, s1 # t8 now holds relocated _G_O_T_ daddi t8, t8, 16 # skipping first two entries dli t2, 2 1: diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S index 35728eb..50b7fb1 100644 --- a/arch/mips/cpu/xburst/start.S +++ b/arch/mips/cpu/xburst/start.S @@ -116,7 +116,6 @@ relocate_code: jr t0 nop - .word _gp .word _GLOBAL_OFFSET_TABLE_ .word uboot_end_data .word uboot_end @@ -131,9 +130,7 @@ in_ram: */ lw t3, -4(t0) # t3 -- num_got_entries lw t4, -16(t0) # t4 -- _GLOBAL_OFFSET_TABLE_ - lw t5, -20(t0) # t5 -- _gp - sub t4, t5 # compute offset - add t4, t4, gp # t4 now holds relocated _G_O_T_ + add t4, t6 # t4 now holds relocated _G_O_T_ addit4, t4, 8 # skipping first two entries li t2, 2 1: -- 1.7.10 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/7] MIPS: add unified u-boot.lds file
2013.01.30. 15:34 keltezéssel, Stefan Roese írta: On 01/30/2013 03:31 PM, Gabor Juhos wrote: The patch adds an unified linker script file which can be used for all currently supported MIPS targets. Signed-off-by: Gabor Juhos juh...@openwrt.org Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com Cc: Stefan Roese s...@denx.de Cc: Wolfgang Denk w...@denx.de Cc: Xiangfu Liu xian...@openmobilefree.net Again, can't test but looks good. Thanks. Acked-by: Stefan Roese s...@denx.de Thanks! -Gabor ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] can i in u-boot partition a device and format it in fat ?
Dear Altunbas Sabri (DC-IA/EAH2), In message eada2943bac14c4ab625a3550a3be9800966d80...@si-mbx04.de.bosch.com you wrote: i had a look at the u-boot cmd's. I can read/write a file from/to a dos par tition but I didn't find a command for partitioning and formatting a device. No, you cannot (at least not unless you are willing to manually build the boot sector using mw commands and then writing it to the drive). Boot an OS for this purpose... Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de About the use of language: it is impossible to sharpen a pencil with a blunt ax. It is equally vain to try to do it with ten blunt axes instead. -- Edsger Dijkstra ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] Tegra114: fdt: Update DT files with I2C info for T114/Dalmore
Laxman, On Wed, Jan 30, 2013 at 12:01 AM, Laxman Dewangan ldewan...@nvidia.com wrote: Tegra30 i2c driver will not work as straight. There is los of change which need to be taken care. I posted the change for kernel driver. Changes are: - Enable/disable control for per packet transfer complete interrupt. Earlier SoCs could not disable this. - Single clock source for standard/fast and HS mode clock speed. The clock divisor for fast/standard mode is added into the i2c controller to meet the HS and standard/fast mode of clock speed from single source. The Linux driver changes in that patch Stephen pointed to don't look _that_ extensive - not what I would call 'lots of changes'. I don't know that the transfer-complete interrupt disable is needed in U-Boot, since interrupts aren't used at all. I'll modify the clock source divisor calculation, though, and see what difference that makes, if any. Thanks, Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 02/10] mx23: Document the tRAS lockout setting in memory initialization
On Wed, Jan 30, 2013 at 12:10 PM, Marek Vasut ma...@denx.de wrote: Dear Otavio Salvador, Add a comment about the tRAS lockout setting of HW_DRAM_CTL08 to enable the 'Fast Auto Pre-Charge' found in the memory chip. The setting is applied after memory initialization and it is worth document it. Signed-off-by: Otavio Salvador ota...@ossystems.com.br --- arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index f8392f6..37b50e9 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -119,6 +119,7 @@ static void initialize_dram_values(void) writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); #ifdef CONFIG_MX23 + /* Enable tRAS lockout in HW_DRAM_CTL08 */ This does not explain why it must be here and not in the dram_vals table. It would be nice to explain it here, since it'd prevent others from sending patch stuffing it into the dram_vals table without knowing it must definitelly be here. Ok; I will extend the comment. But why does it have to be here? I wonder ... Yes; I don't know as well. We may try to find it out in future but for now let's keep it as is. Will change it for v2. -- Otavio Salvador O.S. Systems E-mail: ota...@ossystems.com.br http://www.ossystems.com.br Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 01/10] mxs: Rename CONFIG_SPL_MX28_PSWITCH_WAIT to CONFIG_SPL_MXS_PSWITCH_WAIT
On Wed, Jan 30, 2013 at 12:11 PM, Marek Vasut ma...@denx.de wrote: Dear Otavio Salvador, The power switch option is compatible with i.MX23 and i.MX28 so the configration option needs to reflect it. We choose 'CONFIG_SPL_MXS_PSWITCH_WAIT' for the option name. Acked-by: Marek Vasut ma...@denx.de I'm missing cover letter for this large series. Hum, patman seems to be doing something wrong here. It should copy the cover to all Cced people I think. Simon? -- Otavio Salvador O.S. Systems E-mail: ota...@ossystems.com.br http://www.ossystems.com.br Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 03/10] mx23evk: Adjust DRAM control register to use full 128MB of RAM
On Wed, Jan 30, 2013 at 12:12 PM, Marek Vasut ma...@denx.de wrote:
Dear Otavio Salvador,
Adjust HW_DRAM_CTL14 to enable the chip selects to allow usage of full
128MB of RAM.
Signed-off-by: Otavio Salvador ota...@ossystems.com.br
Just enable the full set for all in the generic memory register set
(dram_vals)?
Per datasheet description it shouldn't be done for LQFP; so the safest
setting is to the default we're using as it will work for new boards
and the chip select can be adjusted when need.
---
board/freescale/mx23evk/spl_boot.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/board/freescale/mx23evk/spl_boot.c
b/board/freescale/mx23evk/spl_boot.c index 6007433..b6f4e7e 100644
--- a/board/freescale/mx23evk/spl_boot.c
+++ b/board/freescale/mx23evk/spl_boot.c
@@ -98,6 +98,16 @@ const iomux_cfg_t iomux_setup[] = {
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
};
+#define HW_DRAM_CTL14(0x38 2)
+#define CS_MAP 0x3
+#define INTAREF 0x2
+#define HW_DRAM_CTL14_CONFIG (INTAREF 8 | CS_MAP)
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+ dram_vals[HW_DRAM_CTL14] = HW_DRAM_CTL14_CONFIG;
+}
+
void board_init_ll(void)
{
mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
Best regards,
Marek Vasut
--
Otavio Salvador O.S. Systems
E-mail: ota...@ossystems.com.br http://www.ossystems.com.br
Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br
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Re: [U-Boot] [PATCH 06/10] mx23_olinuxino: Add support for status LED
On Wed, Jan 30, 2013 at 12:13 PM, Marek Vasut ma...@denx.de wrote: Dear Otavio Salvador, This allow user to know if the bootloader is running, even without a serial console. Signed-off-by: Otavio Salvador ota...@ossystems.com.br Uh oh, how does this know which GPIO to toggle to drive the led this time ? The problem wasn't the code but me. I wasn't able to find the right GPIO number at that time. -- Otavio Salvador O.S. Systems E-mail: ota...@ossystems.com.br http://www.ossystems.com.br Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 07/10] usb: mxs: Disable USB Port 1 for i.MX23
On Wed, Jan 30, 2013 at 12:17 PM, Marek Vasut ma...@denx.de wrote: Dear Otavio Salvador, The i.MX23 just one USB port so disable the second controller probe when building for i.MX23. Signed-off-by: Otavio Salvador ota...@ossystems.com.br --- drivers/usb/host/ehci-mxs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c index 5062af5..28c8cde 100644 --- a/drivers/usb/host/ehci-mxs.c +++ b/drivers/usb/host/ehci-mxs.c @@ -50,10 +50,12 @@ int mxs_ehci_get_port(struct ehci_mxs *mxs_usb, int port) usb_base = MXS_USBCTRL0_BASE; phy_base = MXS_USBPHY0_BASE; break; +#ifdef CONFIG_MX28 case 1: usb_base = MXS_USBCTRL1_BASE; phy_base = MXS_USBPHY1_BASE; break; +#endif default: printf(CONFIG_EHCI_MXS_PORT (port = %d)\n, port); return -1; This is not enough. For example this portion will do something undefined on mx23: 98 writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE, 99 digctl_ctrl-reg_clr); THis ehci-mxs.c needs full review for mx23. Ok; I will handle it for v2. -- Otavio Salvador O.S. Systems E-mail: ota...@ossystems.com.br http://www.ossystems.com.br Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
