Re: [U-Boot] [PATCH] VCMA9: Enable CONFIG_CMD_NAND_YAFFS
Tom Rini wrote: As this board has NAND and supports YAFFS2, add CONFIG_MD_NAND_YAFFS Cc: David Müller d.muel...@elsoft.ch Signed-off-by: Tom Rini tr...@ti.com Acked-by: David Müller d.muel...@elsoft.ch ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 0/2] usb: ehci: exynos: Fixes for non-fdt systems
Based on 'master' branch of u-boot-samsung. Changes from v3: - Adding necesasry check for return error of exynos_usb_parse_dt() and returning accordingly from ehci_hcd_init(). - Removing unnecessary parentheses around ctx-hcd. Vivek Gautam (2): usb: ehci: exynos: Fix multiple FDT decode usb: ehci: exynos: Enable non-dt path drivers/usb/host/ehci-exynos.c | 51 ++-- 1 files changed, 23 insertions(+), 28 deletions(-) -- 1.7.6.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 2/2] usb: ehci: exynos: Enable non-dt path
Enabling the non-dt path for the driver so that
we don't get any build errors for non-dt configuration.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
Changes from v3:
- No change
Changes from v2:
- Adding necessary typecast (struct ehci_hccr *) for ctx-hcd.
Changes from v1:
- Using CONFIG_OF_CONTROL around exynos_usb_parse_dt() definition
since it is used for DT systems only.
drivers/usb/host/ehci-exynos.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
index c4c90be..0c797aa 100644
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
@@ -47,6 +47,7 @@ struct exynos_ehci {
static struct exynos_ehci exynos;
+#ifdef CONFIG_OF_CONTROL
static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
{
fdt_addr_t addr;
@@ -90,6 +91,7 @@ static int exynos_usb_parse_dt(const void *blob, struct
exynos_ehci *exynos)
return 0;
}
+#endif
/* Setup the EHCI host controller. */
static void setup_usb_phy(struct exynos_usb_phy *usb)
@@ -151,10 +153,15 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr,
struct ehci_hcor **hcor)
{
struct exynos_ehci *ctx = exynos;
+#ifdef CONFIG_OF_CONTROL
if (exynos_usb_parse_dt(gd-fdt_blob, ctx)) {
debug(Unable to parse device tree for ehci-exynos\n);
return -ENODEV;
}
+#else
+ ctx-usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
+ ctx-hcd = (struct ehci_hccr *)samsung_get_base_usb_ehci();
+#endif
setup_usb_phy(ctx-usb);
--
1.7.6.5
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[U-Boot] [PATCH v4 1/2] usb: ehci: exynos: Fix multiple FDT decode
With current FDT support driver tries to parse device node
twice in ehci_hcd_init() and ehci_hcd_stop(), which shouldn't
happen ideally.
Making provision to store data in a global structure and thereby
passing its pointer when needed.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
Changes from v3:
- Checking for error return in exynos_usb_parse_dt() and returning
there only in case of failure for DT systems.
- Removed unnecesassry parentheses.
Changes from v2:
- Using hcd as struct ehci_hccr * rather than unsigned int to
avoid unnecessary typecasting later in the code.
- Further using local variable of type fdt_addr_t in
exynos_usb_parse_dt() and modifying the code as required.
Changes from v1:
- Added patch to fix problem of multiple FDT decode.
drivers/usb/host/ehci-exynos.c | 44 ++-
1 files changed, 16 insertions(+), 28 deletions(-)
diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
index 3ca4c5c..c4c90be 100644
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
@@ -42,11 +42,14 @@ DECLARE_GLOBAL_DATA_PTR;
*/
struct exynos_ehci {
struct exynos_usb_phy *usb;
- unsigned int *hcd;
+ struct ehci_hccr *hcd;
};
+static struct exynos_ehci exynos;
+
static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
{
+ fdt_addr_t addr;
unsigned int node;
int depth;
@@ -59,12 +62,14 @@ static int exynos_usb_parse_dt(const void *blob, struct
exynos_ehci *exynos)
/*
* Get the base address for EHCI controller from the device node
*/
- exynos-hcd = (unsigned int *)fdtdec_get_addr(blob, node, reg);
- if (exynos-hcd == NULL) {
+ addr = fdtdec_get_addr(blob, node, reg);
+ if (addr == FDT_ADDR_T_NONE) {
debug(Can't get the EHCI register address\n);
return -ENXIO;
}
+ exynos-hcd = (struct ehci_hccr *)addr;
+
depth = 0;
node = fdtdec_next_compatible_subnode(blob, node,
COMPAT_SAMSUNG_EXYNOS_USB_PHY, depth);
@@ -144,20 +149,16 @@ static void reset_usb_phy(struct exynos_usb_phy *usb)
*/
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- struct exynos_ehci *exynos = NULL;
+ struct exynos_ehci *ctx = exynos;
- exynos = (struct exynos_ehci *)
- kzalloc(sizeof(struct exynos_ehci), GFP_KERNEL);
- if (!exynos) {
- debug(failed to allocate exynos ehci context\n);
- return -ENOMEM;
+ if (exynos_usb_parse_dt(gd-fdt_blob, ctx)) {
+ debug(Unable to parse device tree for ehci-exynos\n);
+ return -ENODEV;
}
- exynos_usb_parse_dt(gd-fdt_blob, exynos);
+ setup_usb_phy(ctx-usb);
- setup_usb_phy(exynos-usb);
-
- *hccr = (struct ehci_hccr *)(exynos-hcd);
+ *hccr = ctx-hcd;
*hcor = (struct ehci_hcor *)((uint32_t) *hccr
+ HC_LENGTH(ehci_readl((*hccr)-cr_capbase)));
@@ -165,8 +166,6 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr,
struct ehci_hcor **hcor)
(uint32_t)*hccr, (uint32_t)*hcor,
(uint32_t)HC_LENGTH(ehci_readl((*hccr)-cr_capbase)));
- kfree(exynos);
-
return 0;
}
@@ -176,20 +175,9 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr,
struct ehci_hcor **hcor)
*/
int ehci_hcd_stop(int index)
{
- struct exynos_ehci *exynos = NULL;
-
- exynos = (struct exynos_ehci *)
- kzalloc(sizeof(struct exynos_ehci), GFP_KERNEL);
- if (!exynos) {
- debug(failed to allocate exynos ehci context\n);
- return -ENOMEM;
- }
-
- exynos_usb_parse_dt(gd-fdt_blob, exynos);
-
- reset_usb_phy(exynos-usb);
+ struct exynos_ehci *ctx = exynos;
- kfree(exynos);
+ reset_usb_phy(ctx-usb);
return 0;
}
--
1.7.6.5
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Re: [U-Boot] [PATCH] I2C: S3C24X0: Bug fixes in i2c_transfer
On Tue, Feb 19, 2013 at 8:19 PM, Rajeshwari Shinde rajeshwar...@samsung.com wrote: This patch corrects the following issues 1) Write the correct M/T Stop value to I2CSTAT after i2c write. According to the spec, after finish the data transmission, we should write a M/T Stop (I2C_MODE_MT | I2C_TXRX_ENA) to I2CSTAT instead of a M/R Stop (I2C_MODE_MR | I2C_TXRX_ENA). 2) Not split the write to I2CSTAT into 2 steps in i2c read. According to the spec, we should write the combined M/R Start value to I2CSTAT after setting the slave address to I2CDS 3) Fix the mistake of making an equality check to an assignment. In the case of I2C write with the zero-length address, while tranfering the data, it should be an equality check (==) instead of an assignment (=). Signed-off-by: Tom Wai-Hong Tam waih...@chromium.org Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com Tested-by: Hung-ying Tyan ty...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V7 10/10] EXYNOS5: I2C: Added FDT and non-FDT support for I2C
On Tue, Mar 5, 2013 at 9:11 PM, Amar amarendra...@samsung.com wrote: This patch adds FDT and non-FDT support for I2C, and initialise the I2C channels. Signed-off-by: Amar amarendra...@samsung.com Tested-by: Hung-ying Tyan ty...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Hang issue when applied patch spi: Add SPI flash test
-Original Message-
From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
Sent: Monday, March 04, 2013 9:59 PM
To: Hu Mingkai-B21284
Cc: U-Boot Mailing List
Subject: Re: Hang issue when applied patch spi: Add SPI flash test
+U-Boot mailing list
Hi Mingkai,
On Mon, Mar 4, 2013 at 12:48 AM, Hu Mingkai-B21284 b21...@freescale.com
wrote:
Hi Simon,
After applied following patch, read from SPI flash will hang on
p2041rdb board.
From 2400727318a0a1ecf15a9deae85b0719c4c47aba Mon Sep 17 00:00:00 2001
From: Simon Glass s...@chromium.org
Date: Mon, 8 Oct 2012 13:16:02 +
Subject: [PATCH] spi: Add SPI flash test
It is useful to have a basic SPI flash test, which tests that the SPI
chip,
the SPI bus and the driver are behaving.
This test erases part of the flash, writes data and reads it back as a
sanity check that all is well.
Use CONFIG_SF_TEST to enable it.
Signed-off-by: Simon Glass s...@chromium.org
If included the div64 header file after common.h, it doesn't hang
anymore.
Do you have any suggestions?
+#include div64.h
#include common.h
Well I think div64.h should be after common, so it is fine to move it.
I am not sure why that causes a hang though - do you have more details
- e.g. what did you do when it hangs, what is console output? Also do you
define CONFIG_CMD_SF_TEST?
I used sf read 100 0 1 command to read from SPI flash. I didn't
Define CONFIG_CMD_SF_TEST.
The header file div64.h includes asm/types.h which defines the phys_addr_t
according to the macro CONFIG_PHYS_64BIT, while the macro CONFIG_PHYS_64BIT
is included in common.h, so the phys_addr_t in file cmd_sf.c will be defined as
unsigned long and will be defined as unsigned long long in other files
when CONFIG_PHYS_64BIT is defined.
In this case, when we pass 32bit address to map_physmem, the address will be
put into higher 32 bit, and lower 32bit is a wild value owning to call
conventions.
static int do_spi_flash_read_write(int argc, char * const argv[])
{
map_physmem(addr, len, MAP_WRBACK);
}
For example, when we use sf read 0x100 0 1000 to read SPI flash, the
address
0x100 will be passed into map_physmem, but we get address 0x1a
in
function addrmap_phys_to_virt. Obviously the value 0x1a is out of
the
range of address_map which will return memory address 0x for memory map.
The interrupt vectors in U-Boot are put at address 0x100/0x200/0x300 etc, so sf
read
command will overlap the interrupt vectors which will cause unexpected behavior.
I will submit a patch for this later.
Thanks,
Mingkai
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Re: [U-Boot] [PATCH] usb:composite:fix Provide function data when addressing device with only one interface
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 03/06/2013 02:45 AM, Pantelis Antoniou wrote: [snip] Sorry about missing this thread. I've been busy with other stuff. What kind of regressions are we talking about? I'm trying to get around to looking into all of this, but this shouldn't be causing all that trouble. There's two problems. The first big problem is that file writes become impossible as we don't support appending to files at an offset today. The second problem is that Lukasz is seeing a regression with regards to raw block operations (I think akin to how we have to account for bad blocks, on eMMC we have to deal with lba block sizes). - -- Tom -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQIcBAEBAgAGBQJRNz6dAAoJENk4IS6UOR1WsuAQAKZ+tXycZbgIvwa2QnKpU11g eaZiD0JcWUbi1xa1Novy4qLxgnzz+x1cMFE2GtExWywPbrF5K+tdgvPp2H6O04aS PUfw1EdgoFMANkEHfuQx7NjDiS1ye25Ik6SFvVCRxUjprRJ7nyOxRWpzvMpLU3zb al8ByraUiGhciz73tcT2wKBQNAfuwcauW5omJgwSVdhMfxG25HD7DOv+CiBFugs1 g6Gawls5lr4e9C7dSAmI8H8TbC99YbxZ5eBYQbkYWwbH2kd6/7VYfMJQHeqAsgcu Qb/gpXt3pFHgq+zQz0k4RdbN1m1WXcp1o72PV3sKA4ElNsnUzRc1ddJ4NLL+UsfS mVVYkLIK46nnoKsOlEP/g4T0BLi0R0DNkBg4TZ/l2EDRG3MOkpT9OwCcxkYW5Rs1 3PVsajYaMOmYk4LLHK33hY6Xe0cQv8ieQ1VM45djlGdkGX5PjxRyrE82Ewm0jwyS y1B0+naXlvCe15A7eFmYZyjDN/WndRECaAWshyXjHGThXhzoCULQcSUqhItzCPWG 50zcFi4GZz2KRLHOoJkl3AwC4ItMUAIAbIeWR5k2Vh4jQYJc5oFKAQu6pQxT9NEG IQdks3nRkHylXENR5lStTm4lmI6uuSgfOnALOft5vJCDPPlY7Mkb+Jjoy2v4oFMR WpxIAgeJ/4fJrYWUo9kv =9/Lh -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] mxs: spl_mem_init: Align DDR2 init with FSL bootlets source
On Thu, Feb 28, 2013 at 7:59 PM, Fabio Estevam feste...@gmail.com wrote: From: Fabio Estevam fabio.este...@freescale.com Currently the following kernel hang happens when loading a 2.6.35 kernel from Freeescale on a mx28evk board: RPC: Registered tcp transport module. RPC: Registered tcp NFSv4.1 backchannel transport module. Bus freq driver module loaded IMX usb wakeup probe usb h1 wakeup device is registered mxs_cpu_init: cpufreq init finished ... Loading the same kernel using the bootlets from the imx-bootlets-src-10.12.01 package, the hang does not occur. Comparing the DDR2 initialization from the bootlets code against the U-boot one, we can notice some mismatches, and after applying the same initialization into U-boot the 2.6.35 kernel can boot normally. Also tested with 'mtest' command, which runs succesfully. Signed-off-by: Fabio Estevam fabio.este...@freescale.com Acked-by: Otavio Salvador ota...@ossystems.com.br -- Otavio Salvador O.S. Systems E-mail: ota...@ossystems.com.br http://www.ossystems.com.br Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/4 v5] Add ACE HW support for SHA256 and SHA1
This patch set adds hardware acceleration for SHA 256 with the help of ACE. Changes since v1: - Patch-1: Fixed few nits. - Patch-2: Removed not required config. - Patch-3: Added sha256 to hash command instead of new sha256 command. Changes since v2: - Patch-1: - Added falling back to software sha256 in case length exceeds buffer limit. - Reduced one tab at lines 533, 559 and 571 in the patch. - Removed space after a cast at line 506 in the patch. - Removed blank line at line 561 in the patch. - Removed space before semicolon at line 576 in the patch. - Patch-2: - Added SHA1 in the comment for config. - Patch-3: - Added new nodes for SHA1 and SHA256 in struct hash_algo for the case when ACE is enabled. - Added new declaration for function pointer hash_func_ws with different return type. - Patch-4: - New patch to enable config for hash command. Changes since v3: - Patch-1: - Removed buffer limit since there are 2 regs for address hash_msg_size_high and low. That means buffer length could go upto 2^64 bits which is practically - Removed falling back to software sha256 because there is no buffer limit. - Removed / 4 to sha1 and sha256 lengths and added increment to 4 in for loop at line 573. - Timed out still kept to be 100 ms since this is enough for hardware to switch status to idle from busy. In case it couldn't that means h/w is faulty. - Patch-2: - Added Acked-by: Simon Glass s...@chromium.org. - Patch-3: - New patch. - Patch-4: - Changed command names to lower case in algo struct. - Added generic ace_sha config. - Patch-5: Added acked-by Simon Glass - Added new generic config for ace_sha to enable ace support in hash.c. Changes since v4: - Patch-1: - Added include for clk.h. - Added define for MAX_FREQ. - Added timeout calculation as per frequency. - Changed i+=4 to i++ and len to len/4 in for loop at line 591 in this patch. - Added two new functions ace_sha256 and ace_sha1. - Patch-2: None. - Patch-3: - Changed function names in struct algo. - Replaced ACE_SHA_TYPE to CHUNSZ in struct algo. - Patch-4: Added Acked-by: Simon Glass s...@chromium.org. Akshay Saraswat (4): Exynos: Add hardware accelerated SHA 256 Exynos: config: Enable ACE HW for SHA 256 for Exynos gen: Add ACE acceleration to hash Exynos: config: Enable hash command Makefile | 1 + arch/arm/include/asm/arch-exynos/cpu.h | 4 + common/hash.c | 14 ++ drivers/crypto/Makefile| 47 + drivers/crypto/ace_sfr.h | 310 + drivers/crypto/ace_sha.c | 138 +++ include/ace_sha.h | 67 +++ include/configs/exynos5250-dt.h| 5 + 8 files changed, 586 insertions(+) create mode 100644 drivers/crypto/Makefile create mode 100644 drivers/crypto/ace_sfr.h create mode 100644 drivers/crypto/ace_sha.c create mode 100644 include/ace_sha.h -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/4 v5] Exynos: Add hardware accelerated SHA256 and SHA1
SHA-256 and SHA-1 accelerated using ACE hardware. Signed-off-by: ARUN MANKUZHI aru...@samsung.com Signed-off-by: Akshay Saraswat aksha...@samsung.com --- Changes since v1: - Moved code to drivers/crypto. - Fixed few other nits. Changes since v2: - Added falling back to software sha256 in case length exceeds buffer limit. - Reduced one tab at lines 533, 559 and 571 in this patch. - Removed space after a cast at line 506 in this patch. - Removed blank line at line 561 in this patch. - Removed space before semicolon at line 576 in this patch. Changes since v3: - Removed buffer limit since there are 2 regs for address hash_msg_size_high and low. That means buffer length could go upto 2^64 bits which is practically - Removed falling back to software sha256 because there is no buffer limit. - Removed / 4 to sha1 and sha256 lengths and added increment to 4 in for loop at line 573. - Timed out still kept to be 100 ms since this is enough for hardware to switch status to idle from busy. In case it couldn't that means h/w is faulty. Changes since v4: - Added include for clk.h. - Added define for MAX_FREQ. - Added timeout calculation as per frequency. - Changed i+=4 to i++ and len to len/4 in for loop at line 591 in this patch. - Added two new functions ace_sha256 and ace_sha1. Makefile | 1 + arch/arm/include/asm/arch-exynos/cpu.h | 4 + drivers/crypto/Makefile| 47 + drivers/crypto/ace_sfr.h | 310 + drivers/crypto/ace_sha.c | 138 +++ include/ace_sha.h | 67 +++ 6 files changed, 567 insertions(+) create mode 100644 drivers/crypto/Makefile create mode 100644 drivers/crypto/ace_sfr.h create mode 100644 drivers/crypto/ace_sha.c create mode 100644 include/ace_sha.h diff --git a/Makefile b/Makefile index fc18dd4..4c41130 100644 --- a/Makefile +++ b/Makefile @@ -272,6 +272,7 @@ LIBS-y += disk/libdisk.o LIBS-y += drivers/bios_emulator/libatibiosemu.o LIBS-y += drivers/block/libblock.o LIBS-$(CONFIG_BOOTCOUNT_LIMIT) += drivers/bootcount/libbootcount.o +LIBS-y += drivers/crypto/libcrypto.o LIBS-y += drivers/dma/libdma.o LIBS-y += drivers/fpga/libfpga.o LIBS-y += drivers/gpio/libgpio.o diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index eb34422..2a20558 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -62,6 +62,7 @@ #define EXYNOS4_GPIO_PART4_BASEDEVICE_NOT_AVAILABLE #define EXYNOS4_DP_BASEDEVICE_NOT_AVAILABLE #define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4_ACE_SFR_BASE DEVICE_NOT_AVAILABLE /* EXYNOS4X12 */ #define EXYNOS4X12_GPIO_PART3_BASE 0x0386 @@ -95,6 +96,7 @@ #define EXYNOS4X12_I2S_BASEDEVICE_NOT_AVAILABLE #define EXYNOS4X12_SPI_BASEDEVICE_NOT_AVAILABLE #define EXYNOS4X12_SPI_ISP_BASEDEVICE_NOT_AVAILABLE +#define EXYNOS4X12_ACE_SFR_BASEDEVICE_NOT_AVAILABLE /* EXYNOS5 Common*/ #define EXYNOS5_I2C_SPACING0x1 @@ -106,6 +108,7 @@ #define EXYNOS5_SWRESET0x10040400 #define EXYNOS5_SYSREG_BASE0x1005 #define EXYNOS5_WATCHDOG_BASE 0x101D +#define EXYNOS5_ACE_SFR_BASE0x1083 #define EXYNOS5_DMC_PHY0_BASE 0x10C0 #define EXYNOS5_DMC_PHY1_BASE 0x10C1 #define EXYNOS5_GPIO_PART3_BASE0x10D1 @@ -205,6 +208,7 @@ static inline unsigned int samsung_get_base_##device(void) \ SAMSUNG_BASE(adc, ADC_BASE) SAMSUNG_BASE(clock, CLOCK_BASE) +SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE) SAMSUNG_BASE(dp, DP_BASE) SAMSUNG_BASE(sysreg, SYSREG_BASE) SAMSUNG_BASE(fimd, FIMD_BASE) diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile new file mode 100644 index 000..2c54793 --- /dev/null +++ b/drivers/crypto/Makefile @@ -0,0 +1,47 @@ +# +# Copyright (c) 2013 Samsung Electronics Co., Ltd. +# http://www.samsung.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation,
[U-Boot] [PATCH 2/4 v5] Exynos: config: Enable ACE HW for SHA 256 for Exynos
This enables SHA 256 for exynos. Signed-off-by: ARUN MANKUZHI aru...@samsung.com Signed-off-by: Akshay Saraswat aksha...@samsung.com Acked-by: Simon Glass s...@chromium.org --- Changes since v1: - Removed not required config. Changes sice v2: - Added SHA1 in the comment for config. Changes sice v3: - Added Acked-by: Simon Glass s...@chromium.org. Changes sice v4: - None. include/configs/exynos5250-dt.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index cabd2f2..0b43984 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -45,6 +45,9 @@ /* Keep L2 Cache Disabled */ #define CONFIG_SYS_DCACHE_OFF +/* Enable ACE acceleration for SHA1 and SHA256 */ +#define CONFIG_EXYNOS_ACE_SHA + #define CONFIG_SYS_SDRAM_BASE 0x4000 #define CONFIG_SYS_TEXT_BASE 0x43E0 -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4 v5] gen: Add ACE acceleration to hash
ACE H/W acceleration support is added to hash
which can be used to test SHA 256 hash algorithm.
Signed-off-by: ARUN MANKUZHI aru...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v1:
- Added sha256 support to hash command instead of new sha256 command.
Changes sice v2:
- Added new nodes for SHA1 and SHA256 in struct hash_algo for the case
when ACE is enabled.
- Added new declaration for function pointer hash_func_ws with
different return type.
Changes sice v3:
- Changed command names to lower case in algo struct.
- Added generic ace_sha config.
Changes sice v4:
- Changed function names in struct algo.
- Replaced ACE_SHA_TYPE to CHUNSZ in struct algo.
common/hash.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/common/hash.c b/common/hash.c
index e3a6e43..1aa23fb 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -28,12 +28,26 @@
#include hash.h
#include sha1.h
#include sha256.h
+#include ace_sha.h
/*
* These are the hash algorithms we support. Chips which support accelerated
* crypto could perhaps add named version of these algorithms here.
*/
static struct hash_algo hash_algo[] = {
+#ifdef CONFIG_ACE_SHA
+ {
+ sha1,
+ SHA1_SUM_LEN,
+ ace_sha1,
+ CHUNKSZ_SHA1,
+ }, {
+ sha256,
+ SHA256_SUM_LEN,
+ ace_sha256,
+ CHUNKSZ_SHA256,
+ },
+#endif
#ifdef CONFIG_SHA1
{
SHA1,
--
1.8.0
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[U-Boot] [PATCH 4/4 v5] Exynos: config: Enable hash command
This enables hash command. Tested with command hash sha256 0x40008000 0x2B 0x40009000. Used mm and md to write a standard string to memory location 0x40008000 and ran the above command to verify the output. Signed-off-by: ARUN MANKUZHI aru...@samsung.com Signed-off-by: Akshay Saraswat aksha...@samsung.com Acked-by: Simon Glass s...@chromium.org --- Changes since v2: - New patch to enable config for hash command. Changes since v3: - Added new generic config for ace_sha to enable ace support in hash.c. Changes since v4: - Added Acked-by: Simon Glass s...@chromium.org. include/configs/exynos5250-dt.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 0b43984..7e1acbd 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -47,6 +47,7 @@ /* Enable ACE acceleration for SHA1 and SHA256 */ #define CONFIG_EXYNOS_ACE_SHA +#define CONFIG_ACE_SHA #define CONFIG_SYS_SDRAM_BASE 0x4000 #define CONFIG_SYS_TEXT_BASE 0x43E0 @@ -116,6 +117,7 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_NET +#define CONFIG_CMD_HASH #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/2 v3] Exynos5: spl: Reduce spl size
This patch set tries to gain some space in spl by restructuring and reorganising some code in two different clock init's for two different times of execution. Compiler arm-2011.09: With patches u-boot-spl.bin size - 3900 bytes. Without patches u-boot-spl.bin size - 4924 bytes. Compiler arm-2009q3: With patches u-boot-spl.bin size - 4412 bytes. Without patches u-boot-spl.bin size - 5692 bytes. Changes since v1: - Patch1: Rebased on ToT. - Patch2: Rebased on ToT. Changes since v2: - Patch1: - Replaced non_spl_clock_div with clock_div. - Replaced ns_clk_div with clk_div. - Added few new comments. - Modified few comments. - Patch2: None. Akshay Saraswat (2): Exynos5: spl: Reorganize mem_timing struct to gain space in spl Exynos5: spl: Reduce clock init in spl board/samsung/smdk5250/Makefile | 3 +- board/samsung/smdk5250/clock_init.c | 493 +--- board/samsung/smdk5250/clock_init.h | 76 +++-- board/samsung/smdk5250/dmc_common.c | 40 +-- board/samsung/smdk5250/dmc_init_ddr3.c | 116 board/samsung/smdk5250/lowlevel_init.S | 4 +- board/samsung/smdk5250/setup.h | 16 +- board/samsung/smdk5250/smdk5250.c | 4 + board/samsung/smdk5250/spl_clock_init.c | 469 ++ 9 files changed, 641 insertions(+), 580 deletions(-) create mode 100644 board/samsung/smdk5250/spl_clock_init.c -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2 v3] Exynos5: spl: Reorganize mem_timing struct to gain space in spl
Distributes struct mem_timings into new different structures
to gain space in spl by removing necessity of maintaining
two big and almost similar mem_timings instances.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v1:
- None.
Changes since v2:
- Replaced non_spl_clock_div with clock_div.
- Replaced ns_clk_div with clk_div.
- Added few new comments.
- Modified few comments.
board/samsung/smdk5250/clock_init.c| 177 -
board/samsung/smdk5250/clock_init.h| 74 ++
board/samsung/smdk5250/dmc_common.c| 40
board/samsung/smdk5250/dmc_init_ddr3.c | 116 +++--
board/samsung/smdk5250/setup.h | 15 ++-
5 files changed, 211 insertions(+), 211 deletions(-)
diff --git a/board/samsung/smdk5250/clock_init.c
b/board/samsung/smdk5250/clock_init.c
index c009ae5..2a07f44 100644
--- a/board/samsung/smdk5250/clock_init.c
+++ b/board/samsung/smdk5250/clock_init.c
@@ -127,14 +127,17 @@ struct arm_clk_ratios arm_clk_ratios[] = {
.arm_ratio = 0x0,
}
};
-struct mem_timings mem_timings[] = {
- {
- .mem_manuf = MEM_MANUF_ELPIDA,
- .mem_type = DDR_MODE_DDR3,
- .frequency_mhz = 800,
+
+struct spl_clock_div spl_clock_div = {
.mpll_mdiv = 0xc8,
.mpll_pdiv = 0x3,
.mpll_sdiv = 0x0,
+ .bpll_mdiv = 0x64,
+ .bpll_pdiv = 0x3,
+ .bpll_sdiv = 0x0,
+};
+
+struct clock_div clock_div = {
.cpll_mdiv = 0xde,
.cpll_pdiv = 0x4,
.cpll_sdiv = 0x2,
@@ -147,14 +150,10 @@ struct mem_timings mem_timings[] = {
.vpll_mdiv = 0x96,
.vpll_pdiv = 0x3,
.vpll_sdiv = 0x2,
+};
- .bpll_mdiv = 0x64,
- .bpll_pdiv = 0x3,
- .bpll_sdiv = 0x0,
+struct mem_timings mem_timings = {
.pclk_cdrex_ratio = 0x5,
- .direct_cmd_msr = {
- 0x00020018, 0x0003, 0x00010042, 0x0d70
- },
.timing_ref = 0x00bb,
.timing_row = 0x8c36650e,
.timing_data = 0x3630580b,
@@ -163,8 +162,6 @@ struct mem_timings mem_timings[] = {
.phy1_dqs = 0x08080808,
.phy0_dq = 0x08080808,
.phy1_dq = 0x08080808,
- .phy0_tFS = 0x4,
- .phy1_tFS = 0x4,
.phy0_pulld_dqs = 0xf,
.phy1_pulld_dqs = 0xf,
@@ -186,10 +183,6 @@ struct mem_timings mem_timings[] = {
.rd_fetch = 0x3,
- .zq_mode_dds = 0x7,
- .zq_mode_term = 0x1,
- .zq_mode_noterm = 0,
-
/*
* Dynamic Clock: Always Running
* Memory Burst length: 8
@@ -229,114 +222,49 @@ struct mem_timings mem_timings[] = {
.chips_per_channel = 2,
.chips_to_configure = 1,
.send_zq_init = 1,
+};
+
+struct mem_params mem_params[] = {
+ {
+ .mem_manuf = MEM_MANUF_ELPIDA,
+ .mem_type = DDR_MODE_DDR3,
+ .frequency_mhz = 800,
+
+ .direct_cmd_msr = {
+ 0x00020018, 0x0003, 0x00010042, 0x0d70
+ },
+
+ .phy0_tFS = 0x4,
+ .phy1_tFS = 0x4,
+
+ .zq_mode_dds = 0x7,
+ .zq_mode_term = 0x1,
+ .zq_mode_noterm = 0,
+
.impedance = IMP_OUTPUT_DRV_30_OHM,
.gate_leveling_enable = 0,
}, {
.mem_manuf = MEM_MANUF_SAMSUNG,
.mem_type = DDR_MODE_DDR3,
.frequency_mhz = 800,
- .mpll_mdiv = 0xc8,
- .mpll_pdiv = 0x3,
- .mpll_sdiv = 0x0,
- .cpll_mdiv = 0xde,
- .cpll_pdiv = 0x4,
- .cpll_sdiv = 0x2,
- .gpll_mdiv = 0x215,
- .gpll_pdiv = 0xc,
- .gpll_sdiv = 0x1,
- .epll_mdiv = 0x60,
- .epll_pdiv = 0x3,
- .epll_sdiv = 0x3,
- .vpll_mdiv = 0x96,
- .vpll_pdiv = 0x3,
- .vpll_sdiv = 0x2,
- .bpll_mdiv = 0x64,
- .bpll_pdiv = 0x3,
- .bpll_sdiv = 0x0,
- .pclk_cdrex_ratio = 0x5,
.direct_cmd_msr = {
0x00020018, 0x0003, 0x0001, 0x0d70
},
- .timing_ref = 0x00bb,
- .timing_row = 0x8c36650e,
- .timing_data = 0x3630580b,
- .timing_power = 0x41000a44,
- .phy0_dqs = 0x08080808,
- .phy1_dqs = 0x08080808,
- .phy0_dq = 0x08080808,
- .phy1_dq = 0x08080808,
+
.phy0_tFS = 0x8,
[U-Boot] [PATCH 2/2 v3] Exynos5: spl: Reduce clock init in spl
This patch subtracts a part of clock init from spl
and executes it after relocation. spl_clock_init
executes in spl and system_clock_init executes after
relocation in u-boot. This is done to gain some space by
removing initially not necessary code.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v1:
- Rebased on ToT.
Changes since v2:
- None.
board/samsung/smdk5250/Makefile | 3 +-
board/samsung/smdk5250/clock_init.c | 428 +
board/samsung/smdk5250/clock_init.h | 2 +
board/samsung/smdk5250/lowlevel_init.S | 4 +-
board/samsung/smdk5250/setup.h | 1 +
board/samsung/smdk5250/smdk5250.c | 4 +
board/samsung/smdk5250/spl_clock_init.c | 469
7 files changed, 481 insertions(+), 430 deletions(-)
create mode 100644 board/samsung/smdk5250/spl_clock_init.c
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 47c6a5a..3ceb7e2 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -26,12 +26,13 @@ LIB = $(obj)lib$(BOARD).o
SOBJS := lowlevel_init.o
-COBJS := clock_init.o
+COBJS := spl_clock_init.o
COBJS += dmc_common.o dmc_init_ddr3.o
COBJS += tzpc_init.o
COBJS += smdk5250_spl.o
ifndef CONFIG_SPL_BUILD
+COBJS += clock_init.o
COBJS += smdk5250.o
endif
diff --git a/board/samsung/smdk5250/clock_init.c
b/board/samsung/smdk5250/clock_init.c
index 2a07f44..73dc13d 100644
--- a/board/samsung/smdk5250/clock_init.c
+++ b/board/samsung/smdk5250/clock_init.c
@@ -34,109 +34,6 @@
DECLARE_GLOBAL_DATA_PTR;
-struct arm_clk_ratios arm_clk_ratios[] = {
- {
- .arm_freq_mhz = 600,
-
- .apll_mdiv = 0xc8,
- .apll_pdiv = 0x4,
- .apll_sdiv = 0x1,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x1,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x2,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x1,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 800,
-
- .apll_mdiv = 0x64,
- .apll_pdiv = 0x3,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x1,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x3,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x2,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 1000,
-
- .apll_mdiv = 0x7d,
- .apll_pdiv = 0x3,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x1,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x4,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x2,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 1200,
-
- .apll_mdiv = 0x96,
- .apll_pdiv = 0x3,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x3,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x5,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x3,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 1400,
-
- .apll_mdiv = 0xaf,
- .apll_pdiv = 0x3,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x3,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x6,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x3,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 1700,
-
- .apll_mdiv = 0x1a9,
- .apll_pdiv = 0x6,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x3,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x6,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x3,
- .arm_ratio = 0x0,
- }
-};
-
-struct spl_clock_div spl_clock_div = {
- .mpll_mdiv = 0xc8,
- .mpll_pdiv = 0x3,
- .mpll_sdiv = 0x0,
- .bpll_mdiv = 0x64,
- .bpll_pdiv = 0x3,
- .bpll_sdiv = 0x0,
-};
-
struct clock_div clock_div = {
.cpll_mdiv = 0xde,
.cpll_pdiv = 0x4,
@@ -152,255 +49,20 @@ struct clock_div clock_div = {
.vpll_sdiv = 0x2,
};
-struct mem_timings mem_timings = {
- .pclk_cdrex_ratio = 0x5,
- .timing_ref = 0x00bb,
- .timing_row = 0x8c36650e,
- .timing_data = 0x3630580b,
-
Re: [U-Boot] [PATCH 1/4] Exynos: Add hardware accelerated SHA 256
Hi Kim, On Fri, 1 Mar 2013 16:11:36 + Akshay Saraswat aksha...@samsung.com wrote: Samsung Enterprise Portal mySingle Hi Kim, On Thu, 28 Feb 2013 11:08:21 + Akshay Saraswat aksha...@samsung.com wrote: As you can see, no. It looks like you didn't change anything. I have to manually single-space things below. So, I have incremented this value to 500 which shall be good enough for the lowest of all frequencies. But I guess what we need here is some formula, to calculate timeout on the basis of frequency, which is nowhere defined. That's odd - I see a bunch of frequencies advertised in arch/arm/cpu/armv7/exynos/clock.c. Or how about using a cycle counter instead? btw, where can I find documentation for the ACE? I tried with different frequencies and data sizes and found that it takes 2 to 3 msecs in all the cases. Since, it is hardware accelerated encoding it is supposed to behave in this same manner. But the current version of u-boot behaves mysteriously and slow downs when pressed enter for long. In the above case mentioned I even saw time took to be more than 100 msecs for all the cases. I think it would not be a better idea to timeout encoding acceleration. But still if it is needed, cycle counter suggestion would be a great solution. it depends on whether the h/w can fault during its operation. You can read Exynos5250 manual's Security subsystem section, which I referred for this. you mean this?: http://www.samsung.com/global/business/semiconductor/file/product/Exynos_5_Dual_User_Manaul_Public_REV100-0.pdf Yes, this is the manual. But this ine is just a part of it which has been made public by Samsung. The one I have has 64 chapters in it and security subsystems is the 57th chapter. There is no Security subsystem section. Kim Regards, Akshay Saraswat ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4 v3] Exynos: Add hardware accelerated SHA 256
Hi Kim,
On Fri, 1 Mar 2013 11:16:22 -0500
Akshay Saraswat aksha...@samsung.com wrote:
SHA-256 and SHA-1 accelerated using ACE hardware.
curious about the rationale: how much faster is this than software?
Time taken by s/w and h/w sha256 are as given below:
Size: 0x1000
s/w - 11 ticks
h/w - 10 ticks
Size: 0x2000
s/w - 11 ticks
h/w - 10 ticks
Size: 0x4000
s/w - 13 ticks
h/w - 10 ticks
Size: 0x8000
s/w - 16 ticks
h/w - 10 ticks
Size: 0x80
s/w - 1775 ticks
h/w - 45 ticks
Size: 0x40
s/w - 893 ticks
h/w - 27 ticks
Size: 0x20
s/w - 451 ticks
h/w - 18 ticks
Size: 0x800
s/w - 28270 ticks
h/w - 110 ticks
Size: 0x4000
s/w - 225896 ticks
h/w - 110 ticks
---
Changes since v2:
- Added falling back to software sha256 in case length exceeds buffer
limit.
- Reduced one tab at lines 533, 559 and 571 in this patch.
- Removed space after a cast at line 506 in this patch.
- Removed blank line at line 561 in this patch.
- Removed space before semicolon at line 576 in this patch.
you should retain the list of changes since v1 here. Read:
http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions
+/* Hash status */
+#define ACE_HASH_BUFRDY_MASK(1 0)
+#define ACE_HASH_BUFRDY_OFF (0 0)
+#define ACE_HASH_BUFRDY_ON (1 0)
+#define ACE_HASH_SEEDSETTING_MASK (1 1)
+#define ACE_HASH_SEEDSETTING_OFF(0 1)
+#define ACE_HASH_SEEDSETTING_ON (1 1)
+#define ACE_HASH_PRNGBUSY_MASK (1 2)
+#define ACE_HASH_PRNGBUSY_OFF (0 2)
+#define ACE_HASH_PRNGBUSY_ON(1 2)
+#define ACE_HASH_PARTIALDONE_MASK (1 4)
+#define ACE_HASH_PARTIALDONE_OFF(0 4)
+#define ACE_HASH_PARTIALDONE_ON (1 4)
based on the nomenclature of the above definitions, this hardware
obviously has support for breaking up hash requests into multiple
buffer submissions, so do that, and not this:
+} else if (buf_len BUF_LIMIT) {
+/*
+ * ACE H/W cannot compute hash value for buffer 8 MB.
+ * Falling back to software.
+ */
+if (hash_type == ACE_SHA_TYPE_SHA1)
+sha1_csum_wd(pbuf, buf_len, pout, CHUNKSZ_SHA1);
+else
+sha256_csum_wd(pbuf, buf_len, pout, CHUNKSZ_SHA256);
+return 0;
+}
Kim
Regards,
Akshay Saraswat
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Re: [U-Boot] [PATCH v2] mxs: spl_mem_init: Align DDR2 init with FSL bootlets source
Dear Otavio Salvador, On Thu, Feb 28, 2013 at 7:59 PM, Fabio Estevam feste...@gmail.com wrote: From: Fabio Estevam fabio.este...@freescale.com Currently the following kernel hang happens when loading a 2.6.35 kernel from Freeescale on a mx28evk board: RPC: Registered tcp transport module. RPC: Registered tcp NFSv4.1 backchannel transport module. Bus freq driver module loaded IMX usb wakeup probe usb h1 wakeup device is registered mxs_cpu_init: cpufreq init finished ... Loading the same kernel using the bootlets from the imx-bootlets-src-10.12.01 package, the hang does not occur. Comparing the DDR2 initialization from the bootlets code against the U-boot one, we can notice some mismatches, and after applying the same initialization into U-boot the 2.6.35 kernel can boot normally. Also tested with 'mtest' command, which runs succesfully. Signed-off-by: Fabio Estevam fabio.este...@freescale.com Acked-by: Otavio Salvador ota...@ossystems.com.br Otavio, did you review the changes done in this patch ? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/5 v4] gen: Add ACE acceleration to hash
Hi Kim,
On Tue, 5 Mar 2013 17:51:00 -0800
Simon Glass s...@chromium.org wrote:
Hi Kim,
On Tue, Mar 5, 2013 at 2:43 PM, Kim Phillips kim.phill...@freescale.com
wrote:
On Tue, 5 Mar 2013 08:19:59 -0500
Akshay Saraswat aksha...@samsung.com wrote:
Tested with command hash sha256 0x40008000 0x2B 0x40009000.
Used mm and md to write a standard string to memory location
0x40008000 and ran the above command to verify the output.
patches 1,2,4,5 all contain this tested with text, yet obviously
were not. It also indicates that a data buffer that's 8MB was not
tested?
Would be useful to test a larger transfer.
esp. since it's now advertised.
I have removed tested with in the new set of patches. And I tested those
patches with that command
before mailing for review. I have tested them for various sizes this time which
includes 8 MB as well.
I have shared benchmark results in another mail.
I also asked about speed relative to software running on the core
and didn't get a response. Software should be faster up to
a certain buffer size: what is that threshold?
You can fairly easily do that by temporarily modifying your patch to
use acesha1 for the name, enable CONFIG_CMD_TIME, then you can
compare the two with:
time hash sha1 addr size
time hash acesha1 addr size
sure, but I don't have an ACE - that's why I asked.
Changes sice v3:
- Changed command names to lower case in algo struct.
- Added generic ace_sha config.
I wouldn't call ace a generic name - crypto units other than
ACE should be able to use this code.
I don't really understand this comment. A new CONFIG has been added,
and this is specific to that unit. Are you suggesting that it be
right, and that's the problem - it needn't be specific to that unit.
CONFIG_EXYNOS_ACE_SHA? Will the ACE unit not appear on any other SOC?
my point is other SoCs can use the same entry in the array - there's
nothing h/w-vendor or model-specific about it.
Something like CONFIG_HW_SHA{1,256} ought to do it.
These instances of struct algo were created specifically for ace because
we need function name different for ace to distinguish it from others.
Hence, config name includes ace as well.
But I don't think crypto units other than ACE will use the code in
this patch - it is intended to implement ACE support, and put it ahead
of software support in terms of priority.
the same priority that any h/w accelerated device would get - higher
than that of software crypto.
Another question for Akshay wrt the timeout (since I never got a
reply re: documentation): how can the h/w fault?
Regarding documentation, I have replied to that mail itself. Sorry for the
delay.
Since it is obvious that in case of h/w fault all readl and writel's would
result
incorrectly and since we know that status register should change it's value
quickly,
we have a good option to depend upon 100 ms as the time more than enough for
wait.
And I tried to handle our concern over frequency change and early timeout
with the proportional timeout calculation in the new patch. Please have a look.
Kim
Regards,
Akshay Saraswat
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Re: [U-Boot] [PATCH 2/2 v2] Exynos5: spl: Reduce clock init in spl
Hi Simon, Hi Akshay, On Tue, Mar 5, 2013 at 2:53 AM, Akshay Saraswat aksha...@samsung.com wrote: This patch subtracts a part of clock init from spl and executes it after relocation. spl_clock_init executes in spl and system_clock_init executes after relocation in u-boot. This is done to gain some space by removing initially not necessary code. Signed-off-by: Akshay Saraswat aksha...@samsung.com --- Looks good - just one question below. Changes since v1: - Rebased on ToT. board/samsung/smdk5250/Makefile | 3 +- board/samsung/smdk5250/clock_init.c | 429 + board/samsung/smdk5250/clock_init.h | 2 + board/samsung/smdk5250/lowlevel_init.S | 4 +- board/samsung/smdk5250/setup.h | 1 + board/samsung/smdk5250/smdk5250.c | 4 + board/samsung/smdk5250/spl_clock_init.c | 469 7 files changed, 482 insertions(+), 430 deletions(-) create mode 100644 board/samsung/smdk5250/spl_clock_init.c diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile index 47c6a5a..3ceb7e2 100644 --- a/board/samsung/smdk5250/Makefile +++ b/board/samsung/smdk5250/Makefile @@ -26,12 +26,13 @@ LIB = $(obj)lib$(BOARD).o SOBJS := lowlevel_init.o -COBJS := clock_init.o +COBJS := spl_clock_init.o Shouldn't this only be included in the SPL build? I tried to do that but, since other files are using some of the data defined in this file, we need it in u-boot as well. Please tell me if it's required I'll make another file for common data. COBJS += dmc_common.o dmc_init_ddr3.o COBJS += tzpc_init.o COBJS += smdk5250_spl.o ifndef CONFIG_SPL_BUILD +COBJS += clock_init.o COBJS += smdk5250.o endif ... Regards, Simon Thanks Regards, Akshay Saraswat ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2 v2] Exynos5: spl: Reduce clock init in spl
Hi Simon, Hi Akshay, On Tue, Mar 5, 2013 at 2:53 AM, Akshay Saraswat aksha...@samsung.com wrote: This patch subtracts a part of clock init from spl and executes it after relocation. spl_clock_init executes in spl and system_clock_init executes after relocation in u-boot. This is done to gain some space by removing initially not necessary code. Signed-off-by: Akshay Saraswat aksha...@samsung.com --- Looks good - just one question below. Changes since v1: - Rebased on ToT. board/samsung/smdk5250/Makefile | 3 +- board/samsung/smdk5250/clock_init.c | 429 + board/samsung/smdk5250/clock_init.h | 2 + board/samsung/smdk5250/lowlevel_init.S | 4 +- board/samsung/smdk5250/setup.h | 1 + board/samsung/smdk5250/smdk5250.c | 4 + board/samsung/smdk5250/spl_clock_init.c | 469 7 files changed, 482 insertions(+), 430 deletions(-) create mode 100644 board/samsung/smdk5250/spl_clock_init.c diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile index 47c6a5a..3ceb7e2 100644 --- a/board/samsung/smdk5250/Makefile +++ b/board/samsung/smdk5250/Makefile @@ -26,12 +26,13 @@ LIB = $(obj)lib$(BOARD).o SOBJS := lowlevel_init.o -COBJS := clock_init.o +COBJS := spl_clock_init.o Shouldn't this only be included in the SPL build? I tried to do that but, since other files are using some of the data defined in this file, we need it in u-boot as well. Please tell me if it's required I'll make another file for common data. COBJS += dmc_common.o dmc_init_ddr3.o COBJS += tzpc_init.o COBJS += smdk5250_spl.o ifndef CONFIG_SPL_BUILD +COBJS += clock_init.o COBJS += smdk5250.o endif ... Regards, Simon Thanks Regards, Akshay Saraswat ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mtd: nand: fix the written length when nand_write_skip_bad failed
Hi, Scott
Thanks for your review.
On Tue, Mar 5, 2013 at 9:58 AM, Scott Wood scottw...@freescale.com wrote:
On 03/02/2013 03:01:10 AM, Tao Hou wrote:
When the data has been partially written into the NAND Flash,
returning the written length instead of 0. The written length
may be useful when the upper level decides to continue the writing
after skipping the block causing the write failure.
We already do that in some code paths.
Signed-off-by: Tao Hou hotfor...@gmail.com
Cc: Scott Wood scottw...@freescale.com
Cc: Ben Gardiner bengardi...@nanometrics.ca
Cc: Lei Wen lei...@marvell.com
---
drivers/mtd/nand/nand_util.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
Could you rebase this on top of this patch:
http://patchwork.ozlabs.org/patch/224842/
Do you mean a V2 patch ?
BTW, are you actually using WITH_YAFFS_OOB? I think there are some other
things wrong with it at the moment, as mentioned here:
http://lists.denx.de/pipermail/u-boot/2013-March/148378.html
No, I don't use it.
diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index de1d13e..f57d723 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -496,8 +496,10 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t
offset, size_t *length,
#ifdef CONFIG_CMD_NAND_YAFFS
if (flags WITH_YAFFS_OOB) {
- if (flags ~WITH_YAFFS_OOB)
+ if (flags ~WITH_YAFFS_OOB) {
+ *length = 0;
return -EINVAL;
+ }
int pages;
pages = nand-erasesize / nand-writesize;
@@ -505,6 +507,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t
offset, size_t *length,
if (*length % (nand-writesize + nand-oobsize)) {
printf(Attempt to write incomplete page
in yaffs mode\n);
+ *length = 0;
return -EINVAL;
}
} else
@@ -542,7 +545,6 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t
offset, size_t *length,
if (rval == 0)
return 0;
- *length = 0;
printf(NAND write to offset %llx failed %d\n,
offset, rval);
return rval;
OK so far...
@@ -550,7 +552,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t
offset, size_t *length,
while (left_to_write 0) {
size_t block_offset = offset (nand-erasesize - 1);
- size_t write_size, truncated_write_size;
+ size_t write_size, truncated_write_size, written_size;
WATCHDOG_RESET();
@@ -586,8 +588,10 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t
offset, size_t *length,
ops.oobbuf = ops.datbuf + pagesize;
rval = nand-write_oob(nand, offset,
ops);
- if (rval != 0)
+ if (rval != 0) {
+ written_size = pagesize_oob *
page;
break;
+ }
offset += pagesize;
p_buffer += pagesize_oob;
@@ -605,14 +609,18 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t
offset, size_t *length,
rval = nand_write(nand, offset,
truncated_write_size,
p_buffer);
- offset += write_size;
- p_buffer += write_size;
+ if (rval == 0) {
+ offset += write_size;
+ p_buffer += write_size;
+ } else {
+ written_size = truncated_write_size;
+ }
}
if (rval != 0) {
printf(NAND write to offset %llx failed %d\n,
offset, rval);
- *length -= left_to_write;
+ *length -= left_to_write - written_size;
return rval;
}
...but I don't see why this part is needed (or correct). Why doesn't
*length -= left_to_write already get you what you want?
-Scott
I just use *length -= left_to_write - written_size to tell the upper
level that what
had been actually happened. For the current block, written_size has
been written to the NAND Flash yet, so left_to_write should be
subtracted by written_size.
Cheers,
Hou.
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Re: [U-Boot] [PATCH v2] mxs: spl_mem_init: Align DDR2 init with FSL bootlets source
On Wed, Mar 6, 2013 at 11:31 AM, Marek Vasut ma...@denx.de wrote: Dear Otavio Salvador, On Thu, Feb 28, 2013 at 7:59 PM, Fabio Estevam feste...@gmail.com wrote: From: Fabio Estevam fabio.este...@freescale.com Currently the following kernel hang happens when loading a 2.6.35 kernel from Freeescale on a mx28evk board: RPC: Registered tcp transport module. RPC: Registered tcp NFSv4.1 backchannel transport module. Bus freq driver module loaded IMX usb wakeup probe usb h1 wakeup device is registered mxs_cpu_init: cpufreq init finished ... Loading the same kernel using the bootlets from the imx-bootlets-src-10.12.01 package, the hang does not occur. Comparing the DDR2 initialization from the bootlets code against the U-boot one, we can notice some mismatches, and after applying the same initialization into U-boot the 2.6.35 kernel can boot normally. Also tested with 'mtest' command, which runs succesfully. Signed-off-by: Fabio Estevam fabio.este...@freescale.com Acked-by: Otavio Salvador ota...@ossystems.com.br Otavio, did you review the changes done in this patch ? This is the setup used in FSL U-Boot and it fixes 2.6.35.3 cpufreq kernel hang; it is good enough for me to accept it. If you care enough, go ahead and check every change bit. -- Otavio Salvador O.S. Systems E-mail: ota...@ossystems.com.br http://www.ossystems.com.br Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 0/3] i.MX6 SabreSD and SabreAUTO bmode support
This adds the bmode support for i.MX6 SabreSD and SabreAUTO
boards. This allows user to choose the boot mode at runtime making it
easy to boot from USB or other media.
Changes in v3:
- Drop change in bootdelay; the change where done by me while testing
it and I mistakenly included it.
Changes in v2:
- Rework code to use a 'ret' variable (Fabio)
- Improve commit log
Otavio Salvador (3):
mx6qsabresd: Fix card detection for invalid card id case
mx6qsabresd: Document the mapping of USDHC[2-4]
mx6qsabre{sd,auto}: Add boot mode select
board/freescale/mx6qsabreauto/mx6qsabreauto.c | 17 +
board/freescale/mx6qsabresd/mx6qsabresd.c | 35 ---
include/configs/mx6qsabre_common.h| 2 ++
3 files changed, 50 insertions(+), 4 deletions(-)
--
1.8.1
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[U-Boot] [PATCH v3 1/3] mx6qsabresd: Fix card detection for invalid card id case
This changes the code so in case an unkown value is passed it will
return as invalid.
Signed-off-by: Otavio Salvador ota...@ossystems.com.br
---
Changes in v3: None
Changes in v2:
- Rework code to use a 'ret' variable (Fabio)
board/freescale/mx6qsabresd/mx6qsabresd.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c
b/board/freescale/mx6qsabresd/mx6qsabresd.c
index 65c4a1a..e556476 100644
--- a/board/freescale/mx6qsabresd/mx6qsabresd.c
+++ b/board/freescale/mx6qsabresd/mx6qsabresd.c
@@ -145,15 +145,18 @@ struct fsl_esdhc_cfg usdhc_cfg[3] = {
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc-priv;
+ int ret = 0;
switch (cfg-esdhc_base) {
case USDHC2_BASE_ADDR:
- return !gpio_get_value(USDHC2_CD_GPIO);
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
case USDHC3_BASE_ADDR:
- return !gpio_get_value(USDHC3_CD_GPIO);
- default:
- return 1; /* eMMC/uSDHC4 is always present */
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ case USDHC4_BASE_ADDR:
+ ret = 1; /* eMMC/uSDHC4 is always present */
}
+
+ return ret;
}
int board_mmc_init(bd_t *bis)
--
1.8.1
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[U-Boot] [PATCH v3 2/3] mx6qsabresd: Document the mapping of USDHC[2-4]
This documents the SD card identifier so it is easier for user to spot
which card number will be used, if need.
Signed-off-by: Otavio Salvador ota...@ossystems.com.br
---
Changes in v3: None
Changes in v2:
- Improve commit log
board/freescale/mx6qsabresd/mx6qsabresd.c | 4
1 file changed, 4 insertions(+)
diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c
b/board/freescale/mx6qsabresd/mx6qsabresd.c
index e556476..3fe8bb6 100644
--- a/board/freescale/mx6qsabresd/mx6qsabresd.c
+++ b/board/freescale/mx6qsabresd/mx6qsabresd.c
@@ -26,6 +26,7 @@
#include asm/errno.h
#include asm/gpio.h
#include asm/imx-common/iomux-v3.h
+#include asm/imx-common/boot_mode.h
#include mmc.h
#include fsl_esdhc.h
#include miiphy.h
@@ -165,18 +166,21 @@ int board_mmc_init(bd_t *bis)
for (i = 0; i CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
+ /* SD2 - mmc0 */
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
+ /* SD3 - mmc1 */
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
gpio_direction_input(USDHC3_CD_GPIO);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
+ /* eMMC - mmc2 */
case 2:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
--
1.8.1
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[U-Boot] [PATCH v3 3/3] mx6qsabre{sd,auto}: Add boot mode select
Adds support for 'bmode' command which let user to choose where to
boot from; this allows U-Boot to load system from another storage
without messing with jumpers.
Signed-off-by: Otavio Salvador ota...@ossystems.com.br
---
Changes in v3:
- Drop change in bootdelay; the change where done by me while testing
it and I mistakenly included it.
Changes in v2: None
board/freescale/mx6qsabreauto/mx6qsabreauto.c | 17 +
board/freescale/mx6qsabresd/mx6qsabresd.c | 20
include/configs/mx6qsabre_common.h| 2 ++
3 files changed, 39 insertions(+)
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 9e3700e..9650563 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -216,6 +216,23 @@ int board_init(void)
return 0;
}
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {mmc0, MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+ return 0;
+}
+
int checkboard(void)
{
int rev = mx6sabre_rev();
diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c
b/board/freescale/mx6qsabresd/mx6qsabresd.c
index 3fe8bb6..02f2924 100644
--- a/board/freescale/mx6qsabresd/mx6qsabresd.c
+++ b/board/freescale/mx6qsabresd/mx6qsabresd.c
@@ -266,6 +266,26 @@ int board_init(void)
return 0;
}
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {sd2, MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ {sd3, MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ /* 8 bit bus width */
+ {emmc, MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+ return 0;
+}
+
int checkboard(void)
{
puts(Board: MX6Q-SabreSD\n);
diff --git a/include/configs/mx6qsabre_common.h
b/include/configs/mx6qsabre_common.h
index f7e8779..63e73a7 100644
--- a/include/configs/mx6qsabre_common.h
+++ b/include/configs/mx6qsabre_common.h
@@ -33,6 +33,7 @@
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
@@ -72,6 +73,7 @@
/* Command definition */
#include config_cmd_default.h
+#define CONFIG_CMD_BMODE
#define CONFIG_CMD_BOOTZ
#undef CONFIG_CMD_IMLS
--
1.8.1
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Re: [U-Boot] [PATCH v2] mxs: spl_mem_init: Align DDR2 init with FSL bootlets source
Dear Otavio Salvador, On Wed, Mar 6, 2013 at 11:31 AM, Marek Vasut ma...@denx.de wrote: Dear Otavio Salvador, On Thu, Feb 28, 2013 at 7:59 PM, Fabio Estevam feste...@gmail.com wrote: From: Fabio Estevam fabio.este...@freescale.com Currently the following kernel hang happens when loading a 2.6.35 kernel from Freeescale on a mx28evk board: RPC: Registered tcp transport module. RPC: Registered tcp NFSv4.1 backchannel transport module. Bus freq driver module loaded IMX usb wakeup probe usb h1 wakeup device is registered mxs_cpu_init: cpufreq init finished ... Loading the same kernel using the bootlets from the imx-bootlets-src-10.12.01 package, the hang does not occur. Comparing the DDR2 initialization from the bootlets code against the U-boot one, we can notice some mismatches, and after applying the same initialization into U-boot the 2.6.35 kernel can boot normally. Also tested with 'mtest' command, which runs succesfully. Signed-off-by: Fabio Estevam fabio.este...@freescale.com Acked-by: Otavio Salvador ota...@ossystems.com.br Otavio, did you review the changes done in this patch ? This is the setup used in FSL U-Boot and it fixes 2.6.35.3 cpufreq kernel hang; it is good enough for me to accept it. If you care enough, go ahead and check every change bit. That is indeed the plan, I will Ack this after I am done with it. It will still make it for .04, dont worry. You should not Ack patches you did not even test nor validate, since the value of your Ack is declining. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] mxs: spl_mem_init: Align DDR2 init with FSL bootlets source
On Wed, Mar 6, 2013 at 12:41 PM, Marek Vasut ma...@denx.de wrote: Dear Otavio Salvador, On Wed, Mar 6, 2013 at 11:31 AM, Marek Vasut ma...@denx.de wrote: Dear Otavio Salvador, On Thu, Feb 28, 2013 at 7:59 PM, Fabio Estevam feste...@gmail.com wrote: From: Fabio Estevam fabio.este...@freescale.com Currently the following kernel hang happens when loading a 2.6.35 kernel from Freeescale on a mx28evk board: RPC: Registered tcp transport module. RPC: Registered tcp NFSv4.1 backchannel transport module. Bus freq driver module loaded IMX usb wakeup probe usb h1 wakeup device is registered mxs_cpu_init: cpufreq init finished ... Loading the same kernel using the bootlets from the imx-bootlets-src-10.12.01 package, the hang does not occur. Comparing the DDR2 initialization from the bootlets code against the U-boot one, we can notice some mismatches, and after applying the same initialization into U-boot the 2.6.35 kernel can boot normally. Also tested with 'mtest' command, which runs succesfully. Signed-off-by: Fabio Estevam fabio.este...@freescale.com Acked-by: Otavio Salvador ota...@ossystems.com.br Otavio, did you review the changes done in this patch ? This is the setup used in FSL U-Boot and it fixes 2.6.35.3 cpufreq kernel hang; it is good enough for me to accept it. If you care enough, go ahead and check every change bit. That is indeed the plan, I will Ack this after I am done with it. It will still make it for .04, dont worry. You should not Ack patches you did not even test nor validate, since the value of your Ack is declining. Are you sure you read my comment? ... it fixes 2.6.35.3 cpufreq kernel hang; ... Regards, -- Otavio Salvador O.S. Systems E-mail: ota...@ossystems.com.br http://www.ossystems.com.br Mobile: +55 53 9981-7854 http://projetos.ossystems.com.br ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] mxs: spl_mem_init: Align DDR2 init with FSL bootlets source
Dear Otavio Salvador, On Wed, Mar 6, 2013 at 12:41 PM, Marek Vasut ma...@denx.de wrote: Dear Otavio Salvador, On Wed, Mar 6, 2013 at 11:31 AM, Marek Vasut ma...@denx.de wrote: Dear Otavio Salvador, On Thu, Feb 28, 2013 at 7:59 PM, Fabio Estevam feste...@gmail.com wrote: From: Fabio Estevam fabio.este...@freescale.com Currently the following kernel hang happens when loading a 2.6.35 kernel from Freeescale on a mx28evk board: RPC: Registered tcp transport module. RPC: Registered tcp NFSv4.1 backchannel transport module. Bus freq driver module loaded IMX usb wakeup probe usb h1 wakeup device is registered mxs_cpu_init: cpufreq init finished ... Loading the same kernel using the bootlets from the imx-bootlets-src-10.12.01 package, the hang does not occur. Comparing the DDR2 initialization from the bootlets code against the U-boot one, we can notice some mismatches, and after applying the same initialization into U-boot the 2.6.35 kernel can boot normally. Also tested with 'mtest' command, which runs succesfully. Signed-off-by: Fabio Estevam fabio.este...@freescale.com Acked-by: Otavio Salvador ota...@ossystems.com.br Otavio, did you review the changes done in this patch ? This is the setup used in FSL U-Boot and it fixes 2.6.35.3 cpufreq kernel hang; it is good enough for me to accept it. If you care enough, go ahead and check every change bit. That is indeed the plan, I will Ack this after I am done with it. It will still make it for .04, dont worry. You should not Ack patches you did not even test nor validate, since the value of your Ack is declining. Are you sure you read my comment? ... it fixes 2.6.35.3 cpufreq kernel hang; ... Yes, I did read it. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4] addition of btrfs to u-boot
Adnan Ali (1): Introduced btrfs file-system with btrload command Makefile |1 + common/Makefile|1 + common/cmd_btr.c | 65 +++ fs/btrfs/Makefile | 51 ++ fs/btrfs/btrfs.c | 1209 fs/btrfs/crc32_c.c | 54 ++ fs/fs.c| 86 +++- include/btrfs.h| 391 ++ include/config_fallbacks.h |4 + include/fs.h |1 + 10 files changed, 1860 insertions(+), 3 deletions(-) create mode 100644 common/cmd_btr.c create mode 100644 fs/btrfs/Makefile create mode 100644 fs/btrfs/btrfs.c create mode 100644 fs/btrfs/crc32_c.c create mode 100644 include/btrfs.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4] Introduced btrfs file-system with btrload command
Introduces btrfs file-system to read file
from volume/sub-volumes with btrload command. This
implementation has read-only support.
This btrfs implementation is based on syslinux btrfs
code, commit 269ebc845ebc8b46ef4b0be7fa0005c7fdb95b8d.
v4: btrls command added.
v3: patch re-formated.
v2: patch error removed.
Signed-off-by: Adnan Ali adnan@codethink.co.uk
---
Makefile |1 +
common/Makefile|1 +
common/cmd_btr.c | 65 +++
fs/btrfs/Makefile | 51 ++
fs/btrfs/btrfs.c | 1209
fs/btrfs/crc32_c.c | 54 ++
fs/fs.c| 86 +++-
include/btrfs.h| 391 ++
include/config_fallbacks.h |4 +
include/fs.h |1 +
10 files changed, 1860 insertions(+), 3 deletions(-)
create mode 100644 common/cmd_btr.c
create mode 100644 fs/btrfs/Makefile
create mode 100644 fs/btrfs/btrfs.c
create mode 100644 fs/btrfs/crc32_c.c
create mode 100644 include/btrfs.h
diff --git a/Makefile b/Makefile
index 3305e8c..cc35e7b 100644
--- a/Makefile
+++ b/Makefile
@@ -261,6 +261,7 @@ endif
LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o
LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
LIBS-y += fs/libfs.o \
+fs/btrfs/libbtrfs.o \
fs/cbfs/libcbfs.o \
fs/cramfs/libcramfs.o \
fs/ext4/libext4fs.o \
diff --git a/common/Makefile b/common/Makefile
index 54fcc81..093dd35 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -73,6 +73,7 @@ COBJS-$(CONFIG_CMD_BEDBUG) += bedbug.o cmd_bedbug.o
COBJS-$(CONFIG_CMD_BMP) += cmd_bmp.o
COBJS-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o
COBJS-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o
+COBJS-$(CONFIG_CMD_BTR) += cmd_btr.o
COBJS-$(CONFIG_CMD_CACHE) += cmd_cache.o
COBJS-$(CONFIG_CMD_CBFS) += cmd_cbfs.o
COBJS-$(CONFIG_CMD_CONSOLE) += cmd_console.o
diff --git a/common/cmd_btr.c b/common/cmd_btr.c
new file mode 100644
index 000..387e846
--- /dev/null
+++ b/common/cmd_btr.c
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2013 Codethink Limited
+ * Btrfs port to Uboot by
+ * Adnan Ali adnan@codethink.co.uk
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Boot support
+ */
+#include fs.h
+#include btrfs.h
+
+char subvolname[MAX_SUBVOL_NAME];
+
+int do_btr_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc 5)
+ strcpy(subvolname, argv[5]);
+ else
+ strcpy(subvolname, );
+
+ return do_load(cmdtp, flag, argc, argv, FS_TYPE_BTR, 16);
+}
+
+
+U_BOOT_CMD(
+ btrload,7, 0, do_btr_fsload,
+ load binary file from a btr filesystem,
+ interface [dev[:part]] addr filename [subvol_name]\n
+ - Load binary file 'filename' from 'dev' on 'interface'\n
+ to address 'addr' from better filesystem.\n
+ the load stops on end of file.\n
+ subvol_name is used read that file from this subvolume.\n
+ All numeric parameters are assumed to be hex.
+);
+
+static int do_btr_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+return do_ls(cmdtp, flag, argc, argv, FS_TYPE_BTR);
+}
+
+U_BOOT_CMD(
+btrls, 4, 1, do_btr_ls,
+list files in a directory (default /),
+interface [dev[:part]] [directory]\n
+- list files from 'dev' on 'interface' in a 'directory'
+);
+
diff --git a/fs/btrfs/Makefile b/fs/btrfs/Makefile
new file mode 100644
index 000..0dd469c
--- /dev/null
+++ b/fs/btrfs/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# (C) Copyright 2003
+# Pavel Bartusek, Sysgo Real-Time Solutions AG, p...@sysgo.de
+#
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty
Re: [U-Boot] [PATCH] mtd: nand: fix the written length when nand_write_skip_bad failed
On 03/06/2013 08:56:56 AM, htbegin wrote:
Hi, Scott
Thanks for your review.
On Tue, Mar 5, 2013 at 9:58 AM, Scott Wood scottw...@freescale.com
wrote:
On 03/02/2013 03:01:10 AM, Tao Hou wrote:
When the data has been partially written into the NAND Flash,
returning the written length instead of 0. The written length
may be useful when the upper level decides to continue the writing
after skipping the block causing the write failure.
We already do that in some code paths.
Signed-off-by: Tao Hou hotfor...@gmail.com
Cc: Scott Wood scottw...@freescale.com
Cc: Ben Gardiner bengardi...@nanometrics.ca
Cc: Lei Wen lei...@marvell.com
---
drivers/mtd/nand/nand_util.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
Could you rebase this on top of this patch:
http://patchwork.ozlabs.org/patch/224842/
Do you mean a V2 patch ?
Yes.
BTW, are you actually using WITH_YAFFS_OOB? I think there are some
other
things wrong with it at the moment, as mentioned here:
http://lists.denx.de/pipermail/u-boot/2013-March/148378.html
No, I don't use it.
Changes to that code should be tested by someone...
if (rval != 0) {
printf(NAND write to offset %llx failed
%d\n,
offset, rval);
- *length -= left_to_write;
+ *length -= left_to_write - written_size;
return rval;
}
...but I don't see why this part is needed (or correct). Why
doesn't
*length -= left_to_write already get you what you want?
-Scott
I just use *length -= left_to_write - written_size to tell the upper
level that what
had been actually happened. For the current block, written_size has
been written to the NAND Flash yet, so left_to_write should be
subtracted by written_size.
But left_to_write isn't decreased until after this error return, so
that's already the case. Subtracting written_size from left_to_write
has the effect of increasing length by written_size, so the return
value will now look like the error page has been written.
-Scott
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[U-Boot] [PATCH v9 01/30] mtd: nand: Introduce CONFIG_SYS_NAND_BUSWIDTH_16BIT
From: Fabio Estevam fabio.este...@freescale.com Introduce CONFIG_SYS_NAND_BUSWIDTH_16BIT option so that other NAND controller drivers could use it when a 16-bit NAND is deployed. drivers/mtd/nand/ndfc has CONFIG_SYS_NDFC_16BIT, so just rename it, so that other NAND drivers could reuse the same symbol. Signed-off-by: Fabio Estevam fabio.este...@freescale.com Reviewed-by: Benoît Thébaudeau benoit.thebaud...@advansee.com --- Changes in v9: None Changes in v8: - New patch. Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None README |9 ++--- drivers/mtd/nand/ndfc.c |4 ++-- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/README b/README index d8cb394..830c45e 100644 --- a/README +++ b/README @@ -3713,9 +3713,12 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_SRIOn_MEM_SIZE: Size of SRIO port 'n' memory region -- CONFIG_SYS_NDFC_16 - Defined to tell the NDFC that the NAND chip is using a - 16 bit bus. +- CONFIG_SYS_NAND_BUSWIDTH_16BIT + Defined to tell the NAND controller that the NAND chip is using + a 16 bit bus. + Not all NAND drivers use this symbol. + Example of driver that uses it: + - drivers/mtd/nand/ndfc.c - CONFIG_SYS_NDFC_EBC0_CFG Sets the EBC0_CFG register for the NDFC. If not defined diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c index 6ebbb5e..213d2c9 100644 --- a/drivers/mtd/nand/ndfc.c +++ b/drivers/mtd/nand/ndfc.c @@ -156,7 +156,7 @@ static uint8_t ndfc_read_byte(struct mtd_info *mtd) struct nand_chip *chip = mtd-priv; -#ifdef CONFIG_SYS_NDFC_16BIT +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT return (uint8_t) readw(chip-IO_ADDR_R); #else return readb(chip-IO_ADDR_R); @@ -218,7 +218,7 @@ int board_nand_init(struct nand_chip *nand) nand-ecc.bytes = 3; nand-select_chip = ndfc_select_chip; -#ifdef CONFIG_SYS_NDFC_16BIT +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT nand-options |= NAND_BUSWIDTH_16; #endif -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v9 02/30] mtd: nand: mxc_nand: Fix is_16bit_nand()
From: Fabio Estevam fabio.este...@freescale.com
Currently is_16bit_nand() is a per SoC function and it decides the bus nand
width by reading some boot related registers.
This method works when NAND is the boot medium, but does not work if another
boot medium is used. For example: booting from a SD card and then using NAND
to store the environment variables, would lead to the following error:
NAND bus width 16 instead 8 bit
No NAND device found!!!
0 MiB
Use CONFIG_SYS_NAND_BUSWIDTH_16BIT symbol to decide the bus width.
If it is defined in the board file, then consider 16-bit NAND bus-width,
otherwise assume 8-bit NAND is used.
This also aligns with Documentation/devicetree/bindings/mtd/nand.txt, which
states:
nand-bus-width : 8 or 16 bus width if not present 8
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
Reviewed-by: Benoît Thébaudeau benoit.thebaud...@advansee.com
---
Changes in v9: None
Changes in v8:
- New patch.
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
README |3 ++-
drivers/mtd/nand/mxc_nand.c | 37 +++--
2 files changed, 5 insertions(+), 35 deletions(-)
diff --git a/README b/README
index 830c45e..11ffa71 100644
--- a/README
+++ b/README
@@ -3717,8 +3717,9 @@ Low Level (hardware related) configuration options:
Defined to tell the NAND controller that the NAND chip is using
a 16 bit bus.
Not all NAND drivers use this symbol.
- Example of driver that uses it:
+ Example of drivers that use it:
- drivers/mtd/nand/ndfc.c
+ - drivers/mtd/nand/mxc_nand.c
- CONFIG_SYS_NDFC_EBC0_CFG
Sets the EBC0_CFG register for the NDFC. If not defined
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index d0ded48..bb475f2 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -98,45 +98,14 @@ static struct nand_ecclayout nand_hw_eccoob2k = {
#endif
#endif
-#ifdef CONFIG_MX27
static int is_16bit_nand(void)
{
- struct system_control_regs *sc_regs =
- (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
-
- if (readl(sc_regs-fmcr) NF_16BIT_SEL)
- return 1;
- else
- return 0;
-}
-#elif defined(CONFIG_MX31)
-static int is_16bit_nand(void)
-{
- struct clock_control_regs *sc_regs =
- (struct clock_control_regs *)CCM_BASE;
-
- if (readl(sc_regs-rcsr) CCM_RCSR_NF16B)
- return 1;
- else
- return 0;
-}
-#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
-static int is_16bit_nand(void)
-{
- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-
- if (readl(ccm-rcsr) CCM_RCSR_NF_16BIT_SEL)
- return 1;
- else
- return 0;
-}
+#if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
+ return 1;
#else
-#warning 8/16 bit NAND autodetection not supported
-static int is_16bit_nand(void)
-{
return 0;
-}
#endif
+}
static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t
size)
{
--
1.7.10.4
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[U-Boot] [PATCH v9 04/30] nand: mxc: Add support for i.MX5
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com
Tested-by: Fabio Estevam fabio.este...@freescale.com
---
Changes in v9:
- Drop the now unused SRC register definitions.
Changes in v8:
- Rebase on Fabio's patches using CONFIG_SYS_NAND_BUSWIDTH_16BIT instead of
NAND Flash boot config pins to determine NAND Flash bus width.
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Separate code reformatting from behavioral changes.
Changes in v2: None
drivers/mtd/nand/mxc_nand.c | 119 ++
include/fsl_nfc.h| 79 +++-
nand_spl/nand_boot_fsl_nfc.c | 67 +++-
3 files changed, 250 insertions(+), 15 deletions(-)
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 6ae95d6..db72cdc 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -22,7 +22,8 @@
#include nand.h
#include linux/err.h
#include asm/io.h
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
+ defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include asm/arch/imx-regs.h
#endif
#include fsl_nfc.h
@@ -36,6 +37,9 @@ struct mxc_nand_host {
struct nand_chip*nand;
struct fsl_nfc_regs __iomem *regs;
+#ifdef MXC_NFC_V3_2
+ struct fsl_nfc_ip_regs __iomem *ip_regs;
+#endif
int spare_only;
int status_request;
int pagesize_2k;
@@ -77,7 +81,7 @@ static struct nand_ecclayout nand_hw_eccoob2k = {
.oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
};
#endif
-#elif defined(MXC_NFC_V2_1)
+#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
#ifndef CONFIG_SYS_NAND_LARGEPAGE
static struct nand_ecclayout nand_hw_eccoob = {
.eccbytes = 9,
@@ -127,10 +131,17 @@ static void wait_op_done(struct mxc_nand_host *host, int
max_retries,
uint32_t tmp;
while (max_retries-- 0) {
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
tmp = readnfc(host-regs-config2);
if (tmp NFC_V1_V2_CONFIG2_INT) {
tmp = ~NFC_V1_V2_CONFIG2_INT;
writenfc(tmp, host-regs-config2);
+#elif defined(MXC_NFC_V3_2)
+ tmp = readnfc(host-ip_regs-ipc);
+ if (tmp NFC_V3_IPC_INT) {
+ tmp = ~NFC_V3_IPC_INT;
+ writenfc(tmp, host-ip_regs-ipc);
+#endif
break;
}
udelay(1);
@@ -182,7 +193,7 @@ static void send_prog_page(struct mxc_nand_host *host,
uint8_t buf_id,
if (spare_only)
MTDDEBUG(MTD_DEBUG_LEVEL1, send_prog_page (%d)\n, spare_only);
- if (is_mxc_nfc_21()) {
+ if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
int i;
/*
* The controller copies the 64 bytes of spare data from
@@ -198,11 +209,18 @@ static void send_prog_page(struct mxc_nand_host *host,
uint8_t buf_id,
}
}
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
writenfc(buf_id, host-regs-buf_addr);
+#elif defined(MXC_NFC_V3_2)
+ uint32_t tmp = readnfc(host-regs-config1);
+ tmp = ~NFC_V3_CONFIG1_RBA_MASK;
+ tmp |= NFC_V3_CONFIG1_RBA(buf_id);
+ writenfc(tmp, host-regs-config1);
+#endif
/* Configure spare or page+spare access */
if (!host-pagesize_2k) {
- uint16_t config1 = readnfc(host-regs-config1);
+ uint32_t config1 = readnfc(host-regs-config1);
if (spare_only)
config1 |= NFC_CONFIG1_SP_EN;
else
@@ -225,7 +243,14 @@ static void send_read_page(struct mxc_nand_host *host,
uint8_t buf_id,
{
MTDDEBUG(MTD_DEBUG_LEVEL3, send_read_page (%d)\n, spare_only);
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
writenfc(buf_id, host-regs-buf_addr);
+#elif defined(MXC_NFC_V3_2)
+ uint32_t tmp = readnfc(host-regs-config1);
+ tmp = ~NFC_V3_CONFIG1_RBA_MASK;
+ tmp |= NFC_V3_CONFIG1_RBA(buf_id);
+ writenfc(tmp, host-regs-config1);
+#endif
/* Configure spare or page+spare access */
if (!host-pagesize_2k) {
@@ -242,7 +267,7 @@ static void send_read_page(struct mxc_nand_host *host,
uint8_t buf_id,
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, spare_only);
- if (is_mxc_nfc_21()) {
+ if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
int i;
/*
@@ -262,10 +287,16 @@ static void send_read_page(struct mxc_nand_host *host,
uint8_t buf_id,
/* Request the NANDFC to perform a read of the NAND device ID. */
static void send_read_id(struct mxc_nand_host *host)
{
- uint16_t tmp;
+
[U-Boot] [PATCH v9 03/30] nand: mxc: Prepare to add support for i.MX5
Add some abstraction to NFC definitions so that some parts of the current code
can also be used for future i.MX5 code.
Clean up a few things by the way.
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com
Tested-by: Fabio Estevam fabio.este...@freescale.com
---
Changes in v9: None
Changes in v8: None
Changes in v7:
- Fix typo in patch description.
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Separate code reformatting from behavioral changes.
Changes in v2:
- Fix warning for unused tmp variable in board_nand_init() for NFC V1.
drivers/mtd/nand/mxc_nand.c | 92 +-
include/fsl_nfc.h| 72 -
nand_spl/nand_boot_fsl_nfc.c | 47 +++--
3 files changed, 97 insertions(+), 114 deletions(-)
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index bb475f2..6ae95d6 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -119,7 +119,7 @@ static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t
*source, size_t size
/*
* This function polls the NANDFC to wait for the basic operation to
- * complete by checking the INT bit of config2 register.
+ * complete by checking the INT bit.
*/
static void wait_op_done(struct mxc_nand_host *host, int max_retries,
uint16_t param)
@@ -127,10 +127,10 @@ static void wait_op_done(struct mxc_nand_host *host, int
max_retries,
uint32_t tmp;
while (max_retries-- 0) {
- if (readw(host-regs-config2) NFC_INT) {
- tmp = readw(host-regs-config2);
- tmp = ~NFC_INT;
- writew(tmp, host-regs-config2);
+ tmp = readnfc(host-regs-config2);
+ if (tmp NFC_V1_V2_CONFIG2_INT) {
+ tmp = ~NFC_V1_V2_CONFIG2_INT;
+ writenfc(tmp, host-regs-config2);
break;
}
udelay(1);
@@ -149,8 +149,8 @@ static void send_cmd(struct mxc_nand_host *host, uint16_t
cmd)
{
MTDDEBUG(MTD_DEBUG_LEVEL3, send_cmd(host, 0x%x)\n, cmd);
- writew(cmd, host-regs-flash_cmd);
- writew(NFC_CMD, host-regs-config2);
+ writenfc(cmd, host-regs-flash_cmd);
+ writenfc(NFC_CMD, host-regs-operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, cmd);
@@ -165,8 +165,8 @@ static void send_addr(struct mxc_nand_host *host, uint16_t
addr)
{
MTDDEBUG(MTD_DEBUG_LEVEL3, send_addr(host, 0x%x)\n, addr);
- writew(addr, host-regs-flash_addr);
- writew(NFC_ADDR, host-regs-config2);
+ writenfc(addr, host-regs-flash_addr);
+ writenfc(NFC_ADDR, host-regs-operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, addr);
@@ -198,19 +198,19 @@ static void send_prog_page(struct mxc_nand_host *host,
uint8_t buf_id,
}
}
- writew(buf_id, host-regs-buf_addr);
+ writenfc(buf_id, host-regs-buf_addr);
/* Configure spare or page+spare access */
if (!host-pagesize_2k) {
- uint16_t config1 = readw(host-regs-config1);
+ uint16_t config1 = readnfc(host-regs-config1);
if (spare_only)
- config1 |= NFC_SP_EN;
+ config1 |= NFC_CONFIG1_SP_EN;
else
- config1 = ~NFC_SP_EN;
- writew(config1, host-regs-config1);
+ config1 = ~NFC_CONFIG1_SP_EN;
+ writenfc(config1, host-regs-config1);
}
- writew(NFC_INPUT, host-regs-config2);
+ writenfc(NFC_INPUT, host-regs-operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, spare_only);
@@ -225,19 +225,19 @@ static void send_read_page(struct mxc_nand_host *host,
uint8_t buf_id,
{
MTDDEBUG(MTD_DEBUG_LEVEL3, send_read_page (%d)\n, spare_only);
- writew(buf_id, host-regs-buf_addr);
+ writenfc(buf_id, host-regs-buf_addr);
/* Configure spare or page+spare access */
if (!host-pagesize_2k) {
- uint32_t config1 = readw(host-regs-config1);
+ uint32_t config1 = readnfc(host-regs-config1);
if (spare_only)
- config1 |= NFC_SP_EN;
+ config1 |= NFC_CONFIG1_SP_EN;
else
- config1 = ~NFC_SP_EN;
- writew(config1, host-regs-config1);
+ config1 = ~NFC_CONFIG1_SP_EN;
+ writenfc(config1, host-regs-config1);
}
- writew(NFC_OUTPUT, host-regs-config2);
+ writenfc(NFC_OUTPUT, host-regs-operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, spare_only);
@@ -265,14 +265,14 @@ static void
[U-Boot] [PATCH v9 05/30] imx: mx5: lowlevel_init: Simplify code
Don't use several instructions to build constant values. Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com Acked-by: Stefano Babic sba...@denx.de --- Changes in v9: None Changes in v8: None Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: - New patch. Changes in v2: None arch/arm/cpu/armv7/mx5/lowlevel_init.S |8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 6d9396a..dfce0ca 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -309,8 +309,7 @@ setup_pll_func: ldr r0, =CCM_BASE_ADDR ldr r1, =0x00015154 str r1, [r0, #CLKCTL_CBCMR] -ldr r1, =0x02888945 -orr r1, r1, #(1 16) +ldr r1, =0x02898945 str r1, [r0, #CLKCTL_CBCDR] /* make sure change is effective */ 1: ldr r1, [r0, #CLKCTL_CDHIPR] @@ -321,10 +320,7 @@ setup_pll_func: /* Switch peripheral to PLL2 */ ldr r0, =CCM_BASE_ADDR - ldr r1, =0x00808145 - orr r1, r1, #(2 10) - orr r1, r1, #(0 16) - orr r1, r1, #(1 19) + ldr r1, =0x00888945 str r1, [r0, #CLKCTL_CBCDR] ldr r1, =0x00016154 -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v9 07/30] nand: mxc: Fix debug trace in mxc_nand_read_oob_syndrome()
The page number indicated in the debug trace of mxc_nand_read_oob_syndrome() did
not match the page being worked on.
By the way, replace the GCC-specific __FUNCTION__ with __func__.
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com
---
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- Replace __FUNCTION__ with __func__.
Changes in v4:
- New patch.
Changes in v3: None
Changes in v2: None
drivers/mtd/nand/mxc_nand.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index db72cdc..62d6965 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -409,7 +409,7 @@ static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
MTDDEBUG(MTD_DEBUG_LEVEL0,
%s: Reading OOB area of page %u to oob %p\n,
-__FUNCTION__, host-page_addr, buf);
+__func__, page, buf);
chip-cmdfunc(mtd, NAND_CMD_READOOB, mtd-writesize, page);
for (i = 0; i chip-ecc.steps; i++) {
--
1.7.10.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v9 06/30] imx: mx53ard: Add support for NAND Flash
Add support for the Samsung K9LAG08U0M NAND Flash (2-GiB MLC NAND Flash, 2-kiB
pages, 256-kiB blocks, 30-ns R/W cycles, 1 CS) on mx53ard.
eNFC_CLK_ROOT is set up with a cycle time of 37.5 ns (400 MHz / 3 / 5) for this
board, which satisfies the 30-ns NF R/W cycle requirement.
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com
Tested-by: Fabio Estevam fabio.este...@freescale.com
---
Changes in v9: None
Changes in v8:
- Fix NFC pad setup using Freescale's.
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- New patch.
Changes in v2: None
board/freescale/mx53ard/mx53ard.c | 66 +
include/configs/mx53ard.h | 10 ++
2 files changed, 76 insertions(+)
diff --git a/board/freescale/mx53ard/mx53ard.c
b/board/freescale/mx53ard/mx53ard.c
index 2fc8570..8d433a3 100644
--- a/board/freescale/mx53ard/mx53ard.c
+++ b/board/freescale/mx53ard/mx53ard.c
@@ -58,6 +58,71 @@ void dram_init_banksize(void)
gd-bd-bi_dram[1].size = PHYS_SDRAM_2_SIZE;
}
+#ifdef CONFIG_NAND_MXC
+static void setup_iomux_nand(void)
+{
+ u32 i, reg;
+ #define M4IF_GENP_WEIM_MM_MASK 0x0001
+ #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x1000
+
+ reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
+ reg = ~M4IF_GENP_WEIM_MM_MASK;
+ __raw_writel(reg, M4IF_BASE_ADDR + 0xc);
+ for (i = 0x4; i 0x94; i += 0x18) {
+ reg = __raw_readl(WEIM_BASE_ADDR + i);
+ reg = ~WEIM_GCR2_MUX16_BYP_GRANT_MASK;
+ __raw_writel(reg, WEIM_BASE_ADDR + i);
+ }
+
+ mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_CS1, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
+ mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
+ mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA0, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA1, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA2, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA3, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA4, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA5, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA6, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA7, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA7, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+}
+#else
+static void setup_iomux_nand(void)
+{
+}
+#endif
+
static void setup_iomux_uart(void)
{
/* UART1 RXD */
@@ -277,6 +342,7 @@ static void weim_cs1_settings(void)
int board_early_init_f(void)
{
+ setup_iomux_nand();
setup_iomux_uart();
return 0;
}
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index 62cb42b..148f7a2 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -41,6 +41,16 @@
#define
[U-Boot] [PATCH v9 10/30] arm: relocate_code() is no longer noreturn
Commit e05e5de7fae5bec79617e113916dac6631251156 made ARM's relocate_code() return to its caller, but it did not update its declaration accordingly. Fixing this function declaration fixes dropped C code following calls to relocate_code(). Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com --- Changes in v9: None Changes in v8: - Update relocate_code() description in ARM start.S comments. Changes in v7: None Changes in v6: - New patch, extracted from nand: mxc: Switch NAND SPL to generic SPL. Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/cpu/arm1136/start.S |4 +--- arch/arm/cpu/arm1176/start.S |4 +--- arch/arm/cpu/arm720t/start.S |4 +--- arch/arm/cpu/arm920t/start.S |4 +--- arch/arm/cpu/arm925t/start.S |4 +--- arch/arm/cpu/arm926ejs/start.S |4 +--- arch/arm/cpu/arm946es/start.S |4 +--- arch/arm/cpu/arm_intcm/start.S |4 +--- arch/arm/cpu/armv7/start.S |4 +--- arch/arm/cpu/ixp/start.S |4 +--- arch/arm/cpu/pxa/start.S |4 +--- arch/arm/cpu/s3c44b0/start.S |4 +--- arch/arm/cpu/sa1100/start.S|4 +--- include/common.h |6 +- 14 files changed, 18 insertions(+), 40 deletions(-) diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 4053e86..f1cb1d5 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -176,9 +176,7 @@ next: /* * void relocate_code (addr_sp, gd, addr_moni) * - * This function does not return, instead it continues in RAM - * after relocating the monitor code. - * + * This function relocates the monitor code. */ .globl relocate_code relocate_code: diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index d11386a..fe947cc 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -239,9 +239,7 @@ skip_tcmdisable: /* * void relocate_code (addr_sp, gd, addr_moni) * - * This function does not return, instead it continues in RAM - * after relocating the monitor code. - * + * This function relocates the monitor code. */ .globl relocate_code relocate_code: diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 83722aa..a3d06ce 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -154,9 +154,7 @@ reset: /* * void relocate_code (addr_sp, gd, addr_moni) * - * This function does not return, instead it continues in RAM - * after relocating the monitor code. - * + * This function relocates the monitor code. */ .globl relocate_code relocate_code: diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index f4f14e1..e11460c 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -193,9 +193,7 @@ copyex: /* * void relocate_code (addr_sp, gd, addr_moni) * - * This function does not return, instead it continues in RAM - * after relocating the monitor code. - * + * This function relocates the monitor code. */ .globl relocate_code relocate_code: diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S index 95a0de7..4030d49 100644 --- a/arch/arm/cpu/arm925t/start.S +++ b/arch/arm/cpu/arm925t/start.S @@ -183,9 +183,7 @@ poll1: /* * void relocate_code (addr_sp, gd, addr_moni) * - * This function does not return, instead it continues in RAM - * after relocating the monitor code. - * + * This function relocates the monitor code. */ .globl relocate_code relocate_code: diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 39f9a2e..5600599 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -200,9 +200,7 @@ reset: /* * void relocate_code (addr_sp, gd, addr_moni) * - * This function does not return, instead it continues in RAM - * after relocating the monitor code. - * + * This function relocates the monitor code. */ .globl relocate_code relocate_code: diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 0d57294..79ba8e3 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -158,9 +158,7 @@ reset: /* * void relocate_code (addr_sp, gd, addr_moni) * - * This function does not return, instead it continues in RAM - * after relocating the monitor code. - * + * This function relocates the monitor code. */ .globl relocate_code relocate_code: diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index f5e5381..039677e 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -154,9 +154,7 @@ reset: /* * void relocate_code (addr_sp, gd, addr_moni) * - * This function does not return, instead it continues in RAM - * after relocating the monitor code. - * + * This function relocates the monitor code. */ .globl relocate_code relocate_code: diff --git
[U-Boot] [PATCH v9 09/30] arm: start.S: Fix _TEXT_BASE for SPL
_TEXT_BASE must be set to CONFIG_SPL_TEXT_BASE for generic SPL, and to CONFIG_SYS_TEXT_BASE for non-SPL builds. Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com Reviewed-by: Tom Rini tr...@ti.com --- Changes in v9: None Changes in v8: - Apply to mxs SPL too. Changes in v7: None Changes in v6: - New patch. Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/cpu/arm1136/start.S |4 arch/arm/cpu/arm1176/start.S |8 arch/arm/cpu/arm720t/start.S |2 +- arch/arm/cpu/arm920t/start.S |4 arch/arm/cpu/arm925t/start.S |4 arch/arm/cpu/arm926ejs/mxs/start.S |4 arch/arm/cpu/arm926ejs/start.S |2 +- arch/arm/cpu/arm946es/start.S |4 arch/arm/cpu/arm_intcm/start.S |6 +- arch/arm/cpu/armv7/start.S |4 arch/arm/cpu/ixp/start.S |4 arch/arm/cpu/pxa/start.S |2 +- arch/arm/cpu/s3c44b0/start.S |4 arch/arm/cpu/sa1100/start.S|4 14 files changed, 52 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index a067b8a..4053e86 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -88,7 +88,11 @@ _end_vect: .globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif /* * These are defined in the board-specific linker script. diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 40df4b1..d11386a 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -98,7 +98,15 @@ _end_vect: .globl _TEXT_BASE _TEXT_BASE: +#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ .word CONFIG_SYS_TEXT_BASE +#else +#if defined(CONFIG_SPL_BUILD) defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else + .word CONFIG_SYS_TEXT_BASE +#endif +#endif /* * Below variable is very important because we use MMU in U-Boot. diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 771d386..83722aa 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -85,7 +85,7 @@ _pad: .word 0x12345678 /* now 16*4=64 */ .globl _TEXT_BASE _TEXT_BASE: -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) defined(CONFIG_SPL_TEXT_BASE) .word CONFIG_SPL_TEXT_BASE #else .word CONFIG_SYS_TEXT_BASE diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 511d21d..f4f14e1 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -73,7 +73,11 @@ _fiq:.word fiq .globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif /* * These are defined in the board-specific linker script. diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S index e8d6d71..95a0de7 100644 --- a/arch/arm/cpu/arm925t/start.S +++ b/arch/arm/cpu/arm925t/start.S @@ -79,7 +79,11 @@ _fiq:.word fiq .globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif /* * These are defined in the board-specific linker script. diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index 7ccd337..94da398 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -119,7 +119,11 @@ fiq: .globl _TEXT_BASE _TEXT_BASE: +#ifdef CONFIG_SPL_TEXT_BASE + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif /* * These are defined in the board-specific linker script. diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 66a8b65..39f9a2e 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -123,7 +123,7 @@ _TEXT_BASE: #ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ .word CONFIG_SYS_TEXT_BASE #else -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) defined(CONFIG_SPL_TEXT_BASE) .word CONFIG_SPL_TEXT_BASE #else .word CONFIG_SYS_TEXT_BASE diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index a7a98a4..0d57294 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -89,7 +89,11 @@ _vectors_end: .globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif /* * These are defined in the board-specific linker script. diff --git
[U-Boot] [PATCH v9 08/30] nand: mxc: Use appropriate page number in syndrome functions
The syndrome functions should use the page number passed as argument instead of
the page number saved upon NAND_CMD_READ0.
This does not make any difference if the NAND_NO_AUTOINCR option is set, but
otherwise this fixes accesses to the wrong pages.
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com
---
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- New patch.
Changes in v3: None
Changes in v2: None
drivers/mtd/nand/mxc_nand.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 62d6965..29ceab3 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -463,7 +463,7 @@ static int mxc_nand_read_page_raw_syndrome(struct mtd_info
*mtd,
int n;
_mxc_nand_enable_hwecc(mtd, 0);
- chip-cmdfunc(mtd, NAND_CMD_READ0, 0x00, host-page_addr);
+ chip-cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
for (n = 0, steps = chip-ecc.steps; steps 0; n++, steps--) {
host-col_addr = n * eccsize;
@@ -507,7 +507,7 @@ static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
uint8_t *oob = chip-oob_poi;
MTDDEBUG(MTD_DEBUG_LEVEL1, Reading page %u to buf %p oob %p\n,
- host-page_addr, buf, oob);
+ page, buf, oob);
/* first read the data area and the available portion of OOB */
for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
@@ -545,7 +545,7 @@ static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
/* Then switch ECC off and read the OOB area to get the ECC code */
_mxc_nand_enable_hwecc(mtd, 0);
- chip-cmdfunc(mtd, NAND_CMD_READOOB, mtd-writesize, host-page_addr);
+ chip-cmdfunc(mtd, NAND_CMD_READOOB, mtd-writesize, page);
eccsteps = chip-ecc.steps;
oob = chip-oob_poi + chip-ecc.prepad;
for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
--
1.7.10.4
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[U-Boot] [PATCH v9 11/30] arm1136: Remove redundant relocate_code() return
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com --- Changes in v9: None Changes in v8: None Changes in v7: None Changes in v6: - New patch, extracted from nand: mxc: Switch NAND SPL to generic SPL. Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/cpu/arm1136/start.S |2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index f1cb1d5..889fd53 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -237,8 +237,6 @@ fixnext: add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ cmp r2, r3 blo fixloop - bx lr - #endif relocate_done: -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v9 12/30] arm: relocate_code(): Remove useless relocation offset computation
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com
---
Changes in v9: None
Changes in v8:
- Make sure that r9 is initialized in all cases because it may be used after
relocate_code().
Changes in v7: None
Changes in v6:
- New patch.
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/arm1136/start.S |8 +++-
arch/arm/cpu/arm1176/start.S |8 +++-
arch/arm/cpu/arm720t/start.S |8 +++-
arch/arm/cpu/arm920t/start.S |8 +++-
arch/arm/cpu/arm925t/start.S |8 +++-
arch/arm/cpu/arm926ejs/start.S |9 +++--
arch/arm/cpu/arm946es/start.S |8 +++-
arch/arm/cpu/arm_intcm/start.S |8 +++-
arch/arm/cpu/armv7/start.S |8 +++-
arch/arm/cpu/ixp/start.S |8 +++-
arch/arm/cpu/pxa/start.S |8 +++-
arch/arm/cpu/s3c44b0/start.S |8 +++-
arch/arm/cpu/sa1100/start.S|8 +++-
13 files changed, 39 insertions(+), 66 deletions(-)
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index 889fd53..131fd99 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -185,16 +185,15 @@ relocate_code:
mov r6, r2 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subsr9, r6, r0 /* r9 - relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 - scratch for copy_loop */
ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 - source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0]*/
- stmia r1!, {r9-r10} /* copy to target address [r1]*/
+ ldmia r0!, {r10-r11} /* copy from source address [r0]*/
+ stmia r1!, {r10-r11} /* copy to target address [r1]*/
cmp r0, r2 /* until source end address [r2]*/
blo copy_loop
@@ -203,7 +202,6 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 - Text base */
- sub r9, r6, r0 /* r9 - relocation offset */
ldr r10, _dynsym_start_ofs /* r10 - sym table ofs */
add r10, r10, r0/* r10 - sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 - rel dyn start ofs */
diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index fe947cc..7be4e43 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -248,16 +248,15 @@ relocate_code:
mov r6, r2 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subsr9, r6, r0 /* r9 - relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 - scratch for copy_loop */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 - source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0]*/
- stmia r1!, {r9-r10} /* copy to target address [r1]*/
+ ldmia r0!, {r10-r11} /* copy from source address [r0]*/
+ stmia r1!, {r10-r11} /* copy to target address [r1]*/
cmp r0, r2 /* until source end address [r2]*/
blo copy_loop
@@ -266,7 +265,6 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 - Text base */
- sub r9, r6, r0 /* r9 - relocation offset */
ldr r10, _dynsym_start_ofs /* r10 - sym table ofs */
add r10, r10, r0/* r10 - sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 - rel dyn start ofs */
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index a3d06ce..74c0664 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -163,16 +163,15 @@ relocate_code:
mov r6, r2 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subsr9, r6, r0 /* r9 - relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 - scratch for copy_loop */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 - source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0]*/
- stmia r1!, {r9-r10} /*
[U-Boot] [PATCH v9 14/30] arm: crt0.S: Remove bogus .globl
The purpose of .globl is to export symbols for ld, not to declare external symbols. By the way, use the ENTRY() and ENDPROC() macros to define functions rather than using .global directly. Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com --- Changes in v9: None Changes in v8: - Use ENTRY() and ENDPROC() to define functions. Changes in v7: None Changes in v6: - New patch. Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/lib/crt0.S | 28 1 file changed, 4 insertions(+), 24 deletions(-) diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 4f60958..56b433e 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -24,6 +24,7 @@ #include config.h #include asm-offsets.h +#include linux/linkage.h /* * This file handles the target-independent stages of the U-Boot @@ -67,33 +68,10 @@ */ /* - * declare nand_boot() or board_init_r() to jump to at end of crt0 - */ - -#if defined(CONFIG_NAND_SPL) - -.globl nand_boot - -#elif ! defined(CONFIG_SPL_BUILD) - -.globl board_init_r - -#endif - -/* - * start and end of BSS - */ - -.globl __bss_start -.globl __bss_end__ - -/* * entry point of crt0 sequence */ -.global _main - -_main: +ENTRY(_main) /* * Set up initial C runtime environment and call board_init_f(0). @@ -171,3 +149,5 @@ clbss_l:cmp r0, r1 /* while not at end of BSS */ /* we should not return here. */ #endif + +ENDPROC(_main) -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v9 13/30] arm: relocate_code(): Use __image_copy_end for end of relocation
Use __image_copy_end instead of __bss_start for the end of the image to
relocate. This is the same as commit 033ca72, but applied to all ARM start.S.
This is a more appropriate symbol naming for an image copy relocate feature,
and this also saves a useless copy of data put between __image_copy_end and
__bss_start in linker scripts (e.g. relocation information, or MMU
initialization tables used only before jumping to the relocated image).
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com
---
Changes in v9: None
Changes in v8:
- Fix space before tab warning.
- Give more details in patch description.
Changes in v7: None
Changes in v6:
- New patch.
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/arm1136/start.S |4 ++--
arch/arm/cpu/arm1176/start.S |6 +-
arch/arm/cpu/arm720t/start.S |6 +-
arch/arm/cpu/arm920t/ep93xx/u-boot.lds |3 +++
arch/arm/cpu/arm920t/start.S |6 +-
arch/arm/cpu/arm925t/start.S |6 +-
arch/arm/cpu/arm926ejs/start.S |6 +-
arch/arm/cpu/arm946es/start.S |6 +-
arch/arm/cpu/arm_intcm/start.S |6 +-
arch/arm/cpu/armv7/start.S |4 ++--
arch/arm/cpu/ixp/start.S |6 +-
arch/arm/cpu/ixp/u-boot.lds|2 ++
arch/arm/cpu/pxa/start.S |6 +-
arch/arm/cpu/s3c44b0/start.S |6 +-
arch/arm/cpu/sa1100/start.S|6 +-
board/actux1/u-boot.lds|3 +++
board/actux2/u-boot.lds|3 +++
board/actux3/u-boot.lds|3 +++
board/davinci/da8xxevm/u-boot-spl-hawk.lds |1 +
board/dvlhost/u-boot.lds |3 +++
board/samsung/smdk6400/u-boot-nand.lds |4
board/vpac270/u-boot-spl.lds |2 ++
nand_spl/board/karo/tx25/u-boot.lds|2 ++
nand_spl/board/samsung/smdk6400/u-boot.lds |2 ++
24 files changed, 87 insertions(+), 15 deletions(-)
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index 131fd99..b3e3e37 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -104,9 +104,9 @@ _TEXT_BASE:
_bss_start_ofs:
.word __bss_start - _start
-.global_image_copy_end_ofs
+.globl _image_copy_end_ofs
_image_copy_end_ofs:
- .word __image_copy_end - _start
+ .word __image_copy_end - _start
.globl _bss_end_ofs
_bss_end_ofs:
diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index 7be4e43..4f98f8b 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -127,6 +127,10 @@ _TEXT_PHY_BASE:
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end__ - _start
@@ -251,7 +255,7 @@ relocate_code:
subsr9, r6, r0 /* r9 - relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 - scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 - source end address */
copy_loop:
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index 74c0664..850fce0 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -101,6 +101,10 @@ _TEXT_BASE:
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end__ - _start
@@ -166,7 +170,7 @@ relocate_code:
subsr9, r6, r0 /* r9 - relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 - scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 - source end address */
copy_loop:
diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
index 008ae89..62315de 100644
--- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
+++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
@@ -55,6 +55,9 @@ SECTIONS
}
. = ALIGN(4);
+
+ __image_copy_end = .;
+
__bss_start = .;
.bss : { *(.bss) }
__bss_end__ = .;
diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
index ba4dd85..e2958d3 100644
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -89,6 +89,10 @@ _TEXT_BASE:
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word
[U-Boot] [PATCH v9 16/30] Makefile: Change CONFIG_SPL_PAD_TO to image offset
Change CONFIG_SPL_PAD_TO from a link address to an image offset since this is
more handy and closer to the purpose of this config.
Automatically define CONFIG_SPL_PAD_TO to CONFIG_SPL_MAX_SIZE (or 0 without
CONFIG_SPL_MAX_SIZE).
Test that CONFIG_SPL_PAD_TO = CONFIG_SPL_MAX_SIZE if CONFIG_SPL_PAD_TO is
non-zero.
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com
---
Changes in v9: None
Changes in v8:
- Rebase on latest u-boot-imx/master.
- Use CONFIG_SPL_PAD_TO instead of CONFIG_SPL_MAX_SIZE for u-boot-with-spl.bin
padding.
Changes in v7:
- Use u-boot-spl.bin instead of u-boot-spl in order to avoid having to use
--change-addresses.
Changes in v6:
- Fix size passed to --pad-to thanks to --change-addresses.
Changes in v5: None
Changes in v4:
- New patch.
Changes in v3: None
Changes in v2: None
Makefile |5 ++---
README|7 +--
include/config_fallbacks.h| 16
include/configs/MPC8313ERDB.h |2 +-
4 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/Makefile b/Makefile
index 33d4253..5bcc914 100644
--- a/Makefile
+++ b/Makefile
@@ -484,9 +484,8 @@ $(obj)u-boot.dis: $(obj)u-boot
$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(or $(CONFIG_SPL_PAD_TO),0) \
- -O binary $(obj)spl/u-boot-spl \
- $(obj)spl/u-boot-spl-pad.bin
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
+ -I binary -O binary $ $(obj)spl/u-boot-spl-pad.bin
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $@
rm $(obj)spl/u-boot-spl-pad.bin
diff --git a/README b/README
index 11ffa71..938c38a 100644
--- a/README
+++ b/README
@@ -2883,8 +2883,11 @@ FIT uImage format:
Support for lib/libgeneric.o in SPL binary
CONFIG_SPL_PAD_TO
- Linker address to which the SPL should be padded before
- appending the SPL payload.
+ Image offset to which the SPL should be padded before appending
+ the SPL payload. By default, this is defined as
+ CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
+ CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
+ payload without any padding, or = CONFIG_SPL_MAX_SIZE.
CONFIG_SPL_TARGET
Final target image containing SPL and payload. Some SPLs
diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h
index bfb9680..457c99e 100644
--- a/include/config_fallbacks.h
+++ b/include/config_fallbacks.h
@@ -9,6 +9,22 @@
#ifndef __CONFIG_FALLBACKS_H
#define __CONFIG_FALLBACKS_H
+#ifdef CONFIG_SPL
+#ifdef CONFIG_SPL_PAD_TO
+#ifdef CONFIG_SPL_MAX_SIZE
+#if CONFIG_SPL_PAD_TO CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
+#error CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
+#endif
+#endif
+#else
+#ifdef CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
+#else
+#define CONFIG_SPL_PAD_TO 0
+#endif
+#endif
+#endif
+
#ifndef CONFIG_SYS_BAUDRATE_TABLE
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#endif
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 275d4f2..c28dfe0 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -52,7 +52,7 @@
#define CONFIG_SYS_TEXT_BASE 0x0010 /* CONFIG_SYS_NAND_U_BOOT_DST */
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff0
#define CONFIG_SPL_MAX_SIZE(4 * 1024)
-#define CONFIG_SPL_PAD_TO 0xfff04000
+#define CONFIG_SPL_PAD_TO 0x4000
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x0010
--
1.7.10.4
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[U-Boot] [PATCH v9 15/30] autoconfig.mk: Make it possible to define configs from other configs
Give more flexibility to define configs that can be interpreted by make, e.g. to define fallback values of configs like in the example below. Before this change, the config lines: #define CONFIG_SPL_MAX_SIZE2048 #define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE would have been changed in autoconfig.mk into: CONFIG_SPL_MAX_SIZE=2048 CONFIG_SPL_PAD_TO=CONFIG_SPL_MAX_SIZE Hence, a make recipe using as an argument to $(OBJCOPY): --pad-to=$(CONFIG_SPL_PAD_TO) would have issued: --pad-to=CONFIG_SPL_MAX_SIZE which means nothing for $(OBJCOPY) and makes it fail. Thanks to this change, the config lines above are changed in autoconfig.mk into: CONFIG_SPL_MAX_SIZE=2048 CONFIG_SPL_PAD_TO=$(CONFIG_SPL_MAX_SIZE) Hence, the make recipe above now issues: --pad-to=2048 as expected from the defined config. Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com --- Changes in v9: - Add detailed patch description. Changes in v8: - New patch. Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None tools/scripts/define2mk.sed |2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/scripts/define2mk.sed b/tools/scripts/define2mk.sed index 13e2845..c641edf 100644 --- a/tools/scripts/define2mk.sed +++ b/tools/scripts/define2mk.sed @@ -24,6 +24,8 @@ s/=\([0-9][0-9]*\)/=\1/; # ... and from hex numbers s/=\(0[Xx][0-9a-fA-F][0-9a-fA-F]*\)/=\1/; + # ... and from configs defined from other configs + s/=\(CONFIG_[A-Za-z0-9_][A-Za-z0-9_]*\)/=$(\1)/; # Change '1' and empty values to y (not perfect, but # supports conditional compilation in the makefiles s/=$/=y/; -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v9 17/30] imx: Fix automatic make targets for imx images
Automatically build the 'u-boot.imx' (i.e. imx header + u-boot.bin) and 'SPL' (i.e. imx header + u-boot-spl.bin) make targets for all imx processors supporting this header, so for arm926ejs, arm1136 and armv7. Some combinations were missing. At the same time, fix the build of SPL targets not supporting the imx header on arm1136. For arm1136, the 'SPL' make target was forced to build in all cases if CONFIG_SPL_BUILD was defined, even for non-imx platforms or imx setups without an imx header. Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com --- Changes in v9: None Changes in v8: None Changes in v7: None Changes in v6: - New patch, extracted from nand: mxc: Switch NAND SPL to generic SPL. Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/cpu/arm1136/config.mk |7 +++ arch/arm/cpu/arm926ejs/config.mk |8 ++-- arch/arm/cpu/armv7/config.mk |6 ++ 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk index 9092d91..797d122 100644 --- a/arch/arm/cpu/arm1136/config.mk +++ b/arch/arm/cpu/arm1136/config.mk @@ -31,6 +31,13 @@ PLATFORM_CPPFLAGS += -march=armv5 # = PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) + +ifneq ($(CONFIG_IMX_CONFIG),) +ifdef CONFIG_SPL ifdef CONFIG_SPL_BUILD ALL-y += $(OBJTREE)/SPL endif +else +ALL-y += $(obj)u-boot.imx +endif +endif diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk index 6a3a1bb..f0e31d1 100644 --- a/arch/arm/cpu/arm926ejs/config.mk +++ b/arch/arm/cpu/arm926ejs/config.mk @@ -33,7 +33,11 @@ PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-mali PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) ifneq ($(CONFIG_IMX_CONFIG),) - +ifdef CONFIG_SPL +ifdef CONFIG_SPL_BUILD +ALL-y += $(OBJTREE)/SPL +endif +else ALL-y += $(obj)u-boot.imx - +endif endif diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk index 9c3e2f3..56b8053 100644 --- a/arch/arm/cpu/armv7/config.mk +++ b/arch/arm/cpu/armv7/config.mk @@ -40,5 +40,11 @@ PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,) PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED) ifneq ($(CONFIG_IMX_CONFIG),) +ifdef CONFIG_SPL +ifdef CONFIG_SPL_BUILD +ALL-y += $(OBJTREE)/SPL +endif +else ALL-y += $(obj)u-boot.imx endif +endif -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v9 19/30] arm926ejs: Remove deprecated and now unused NAND SPL
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com --- Changes in v9: None Changes in v8: None Changes in v7: None Changes in v6: - New patch. Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/cpu/arm926ejs/start.S | 10 -- 1 file changed, 10 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 9121af2..fd2803e 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -120,15 +120,11 @@ _fiq: .globl _TEXT_BASE _TEXT_BASE: -#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ - .word CONFIG_SYS_TEXT_BASE -#else #if defined(CONFIG_SPL_BUILD) defined(CONFIG_SPL_TEXT_BASE) .word CONFIG_SPL_TEXT_BASE #else .word CONFIG_SYS_TEXT_BASE #endif -#endif /* * These are defined in the board-specific linker script. @@ -152,12 +148,6 @@ _bss_end_ofs: _end_ofs: .word _end - _start -#ifdef CONFIG_NAND_U_BOOT -.globl _end -_end: - .word __bss_end__ -#endif - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v9 22/30] .gitignore: Add /SPL
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com --- Changes in v9: None Changes in v8: - New patch. Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None .gitignore |1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index e40eb7b..a803651 100644 --- a/.gitignore +++ b/.gitignore @@ -25,6 +25,7 @@ # /MLO +/SPL /System.map /u-boot /u-boot.hex -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v9 20/30] arm: Remove unused relocate_code() parameters
Commit e05e5de7fae5bec79617e113916dac6631251156 made the 2 1st parameters of ARM's relocate_code() useless since it moved the code handling them to crt0.S. So, drop these parameters. Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com --- Changes in v9: None Changes in v8: - Update the function prototype in start.S comments. Changes in v7: None Changes in v6: - New patch. Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/cpu/arm1136/start.S |6 ++ arch/arm/cpu/arm1176/start.S |6 ++ arch/arm/cpu/arm720t/start.S |6 ++ arch/arm/cpu/arm920t/start.S |6 ++ arch/arm/cpu/arm925t/start.S |6 ++ arch/arm/cpu/arm926ejs/start.S |6 ++ arch/arm/cpu/arm946es/start.S |6 ++ arch/arm/cpu/arm_intcm/start.S |6 ++ arch/arm/cpu/armv7/start.S |6 ++ arch/arm/cpu/ixp/start.S |6 ++ arch/arm/cpu/pxa/start.S |6 ++ arch/arm/cpu/s3c44b0/start.S |6 ++ arch/arm/cpu/sa1100/start.S|6 ++ arch/arm/lib/crt0.S|8 +++- board/freescale/mx31pdk/mx31pdk.c |2 +- board/karo/tx25/tx25.c |2 +- board/samsung/smdk6400/smdk6400_nand_spl.c |3 +-- include/common.h |8 18 files changed, 36 insertions(+), 65 deletions(-) diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index b3e3e37..eb11b69 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -174,15 +174,13 @@ next: /*--*/ /* - * void relocate_code (addr_sp, gd, addr_moni) + * void relocate_code(addr_moni) * * This function relocates the monitor code. */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */ adr r0, _start subsr9, r6, r0 /* r9 - relocation offset */ diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 4f98f8b..97d347c 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -241,15 +241,13 @@ skip_tcmdisable: /*--*/ /* - * void relocate_code (addr_sp, gd, addr_moni) + * void relocate_code(addr_moni) * * This function relocates the monitor code. */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */ adr r0, _start subsr9, r6, r0 /* r9 - relocation offset */ diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 850fce0..d455793 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -156,15 +156,13 @@ reset: /*--*/ /* - * void relocate_code (addr_sp, gd, addr_moni) + * void relocate_code(addr_moni) * * This function relocates the monitor code. */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */ adr r0, _start subsr9, r6, r0 /* r9 - relocation offset */ diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index e2958d3..a6cb33f 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -195,15 +195,13 @@ copyex: /*--*/ /* - * void relocate_code (addr_sp, gd, addr_moni) + * void relocate_code(addr_moni) * * This function relocates the monitor code. */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */ adr r0, _start subsr9, r6, r0 /* r9 - relocation offset */ diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S index 4b64122..78d5ab4 100644 --- a/arch/arm/cpu/arm925t/start.S +++ b/arch/arm/cpu/arm925t/start.S @@ -185,15 +185,13 @@ poll1: /*--*/ /* - * void relocate_code (addr_sp, gd,
[U-Boot] [PATCH v9 18/30] nand: mxc: Switch NAND SPL to generic SPL
This also fixes support for mx31pdk and tx25, which had been broken by commit
e05e5de7fae5bec79617e113916dac6631251156.
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com
Tested-by: Fabio Estevam fabio.este...@freescale.com
---
Changes in v9: None
Changes in v8:
- Update doc/README.arm-relocation.
- Drop useless line feed at end of inline asm.
- Set CONFIG_SYS_NAND_U_BOOT_OFFS to CONFIG_SPL_PAD_TO instead of
CONFIG_SPL_MAX_SIZE (this is a cosmetic change since they now have the same
value).
- Enlarge CONFIG_SYS_NAND_U_BOOT_SIZE from 0x3 to 0x32000 to let u-boot.bin
fit in.
Changes in v7: None
Changes in v6:
- Automate 'u-boot.imx' and 'SPL' make targets for all imx processors.
- Move board_init_f() to board.c.
- Get rid of board SPL linker scripts.
- Define CONFIG_SYS_NAND_U_BOOT_OFFS as CONFIG_SPL_MAX_SIZE rather than
duplicating the constant value.
- Define CONFIG_SYS_NAND_U_BOOT_DST as CONFIG_SYS_TEXT_BASE rather than
duplicating the constant value.
- Pass 0 as the 1st argument to relocate_code() since it's unused.
- Fix stack pointers.
- Rebase on latest u-boot-imx/master.
- Move unrelated changes to separate patches.
Changes in v5:
- Remove spaces between function name and open parenthesis.
- Fix mx31pdk and tx25 Makefile-s and SPL linker scripts.
- Remove the useless definition of CONFIG_SPL_LDSCRIPT.
- Fix the call to nand_boot().
Changes in v4:
- New patch.
Changes in v3: None
Changes in v2: None
arch/arm/cpu/arm926ejs/start.S |3 +-
board/freescale/mx31pdk/Makefile |3 +
board/freescale/mx31pdk/config.mk |5 --
board/freescale/mx31pdk/mx31pdk.c |8 ++
board/karo/tx25/Makefile |4 +-
board/karo/tx25/config.mk |5 --
board/karo/tx25/tx25.c |8 ++
boards.cfg |2 +-
doc/README.arm-relocation | 14 +--
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/mxc_nand.c| 10 +--
include/fsl_nfc.h = drivers/mtd/nand/mxc_nand.h | 10 +--
.../mtd/nand/mxc_nand_spl.c| 26 ++
include/configs/mx31pdk.h | 19 +++--
include/configs/tx25.h | 22 +++--
nand_spl/board/freescale/mx31pdk/Makefile | 68 ---
nand_spl/board/freescale/mx31pdk/u-boot.lds| 87 ---
nand_spl/board/karo/tx25/Makefile | 89
nand_spl/board/karo/tx25/config.mk |1 -
nand_spl/board/karo/tx25/u-boot.lds| 87 ---
20 files changed, 80 insertions(+), 392 deletions(-)
delete mode 100644 board/freescale/mx31pdk/config.mk
delete mode 100644 board/karo/tx25/config.mk
rename include/fsl_nfc.h = drivers/mtd/nand/mxc_nand.h (98%)
rename nand_spl/nand_boot_fsl_nfc.c = drivers/mtd/nand/mxc_nand_spl.c (92%)
delete mode 100644 nand_spl/board/freescale/mx31pdk/Makefile
delete mode 100644 nand_spl/board/freescale/mx31pdk/u-boot.lds
delete mode 100644 nand_spl/board/karo/tx25/Makefile
delete mode 100644 nand_spl/board/karo/tx25/config.mk
delete mode 100644 nand_spl/board/karo/tx25/u-boot.lds
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index edff38a..9121af2 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -200,7 +200,6 @@ reset:
/*--*/
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_NAND_SPL)
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
@@ -269,6 +268,8 @@ relocate_done:
bx lr
+#ifndef CONFIG_SPL_BUILD
+
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
diff --git a/board/freescale/mx31pdk/Makefile b/board/freescale/mx31pdk/Makefile
index 5b7cafd..b910722 100644
--- a/board/freescale/mx31pdk/Makefile
+++ b/board/freescale/mx31pdk/Makefile
@@ -27,6 +27,9 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(BOARD).o
+ifdef CONFIG_SPL_BUILD
+SOBJS := lowlevel_init.o
+endif
COBJS := mx31pdk.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/freescale/mx31pdk/config.mk
b/board/freescale/mx31pdk/config.mk
deleted file mode 100644
index de2c642..000
--- a/board/freescale/mx31pdk/config.mk
+++ /dev/null
@@ -1,5 +0,0 @@
-ifdef CONFIG_NAND_SPL
-CONFIG_SYS_TEXT_BASE = 0x87ec
-else
-CONFIG_SYS_TEXT_BASE = 0x87f0
-endif
diff --git a/board/freescale/mx31pdk/mx31pdk.c
b/board/freescale/mx31pdk/mx31pdk.c
index 895396c..3d0d419 100644
--- a/board/freescale/mx31pdk/mx31pdk.c
+++ b/board/freescale/mx31pdk/mx31pdk.c
@@ -36,6 +36,14 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong bootflag)
+{
+ relocate_code(0, NULL,
[U-Boot] [PATCH v9 25/30] arm: Remove support for smdk6400
The migration of boards from Makefile to boards.cfg was due for v2012.03, but smdk6400 did not follow, and it does not build, so move it to scrapyard. It will still be possible to restore it from the Git history before fixing it. Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com --- Changes in v9: - Rebase following upstream changes on doc/README.scrapyard. Changes in v8: - New patch. Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None MAINTAINERS|4 - Makefile | 17 -- arch/arm/include/asm/mach-types.h | 13 -- board/samsung/smdk6400/.gitignore |5 - board/samsung/smdk6400/Makefile| 48 - board/samsung/smdk6400/config.mk | 30 --- board/samsung/smdk6400/lowlevel_init.S | 323 board/samsung/smdk6400/smdk6400.c | 134 board/samsung/smdk6400/smdk6400_nand_spl.c | 36 board/samsung/smdk6400/u-boot-nand.lds | 90 doc/README.scrapyard |1 + include/configs/smdk6400.h | 296 - nand_spl/board/samsung/smdk6400/Makefile | 117 -- nand_spl/board/samsung/smdk6400/config.mk | 40 nand_spl/board/samsung/smdk6400/u-boot.lds | 82 --- 15 files changed, 1 insertion(+), 1235 deletions(-) delete mode 100644 board/samsung/smdk6400/.gitignore delete mode 100644 board/samsung/smdk6400/Makefile delete mode 100644 board/samsung/smdk6400/config.mk delete mode 100644 board/samsung/smdk6400/lowlevel_init.S delete mode 100644 board/samsung/smdk6400/smdk6400.c delete mode 100644 board/samsung/smdk6400/smdk6400_nand_spl.c delete mode 100644 board/samsung/smdk6400/u-boot-nand.lds delete mode 100644 include/configs/smdk6400.h delete mode 100644 nand_spl/board/samsung/smdk6400/Makefile delete mode 100644 nand_spl/board/samsung/smdk6400/config.mk delete mode 100644 nand_spl/board/samsung/smdk6400/u-boot.lds diff --git a/MAINTAINERS b/MAINTAINERS index 175bbe2..b7b3f0f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1020,10 +1020,6 @@ Vladimir Zapolskiy v...@mleia.com devkit3250 lpc32xx -Zhong Hongbo bocui...@gmail.com - - SMDK6400ARM1176 (S3C6400 SoC) - Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com Tetsuyuki Kobayashi k...@kmckk.co.jp diff --git a/Makefile b/Makefile index 0069c86..f09021b 100644 --- a/Makefile +++ b/Makefile @@ -788,23 +788,6 @@ lcname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/') ucname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/') # -## ARM1176 Systems -# -smdk6400_noUSB_config \ -smdk6400_config: unconfig - @mkdir -p $(obj)include $(obj)board/samsung/smdk6400 - @mkdir -p $(obj)nand_spl/board/samsung/smdk6400 - @echo #define CONFIG_NAND_U_BOOT $(obj)include/config.h - @echo CONFIG_NAND_U_BOOT = y $(obj)include/config.mk - @if [ -z $(findstring smdk6400_noUSB_config,$@) ]; then \ - echo RAM_TEXT = 0x57e0 $(obj)board/samsung/smdk6400/config.tmp;\ - else \ - echo RAM_TEXT = 0xc7e0 $(obj)board/samsung/smdk6400/config.tmp;\ - fi - @$(MKCONFIG) smdk6400 arm arm1176 smdk6400 samsung s3c64xx - @echo CONFIG_NAND_U_BOOT = y $(obj)include/config.mk - -# # clean: diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index a676b6d..440b041 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -223,7 +223,6 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_MIOA701 1257 #define MACH_TYPE_ARMADILLO5X0 1260 #define MACH_TYPE_CC9P9360JS 1264 -#define MACH_TYPE_SMDK6400 1270 #define MACH_TYPE_NOKIA_N800 1271 #define MACH_TYPE_EP80219 1281 #define MACH_TYPE_GORAMO_MLR 1292 @@ -3640,18 +3639,6 @@ extern unsigned int __machine_arch_type; # define machine_is_cc9p9360js() (0) #endif -#ifdef CONFIG_MACH_SMDK6400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type__machine_arch_type -# else -# define machine_arch_typeMACH_TYPE_SMDK6400 -# endif -# define machine_is_smdk6400() (machine_arch_type == MACH_TYPE_SMDK6400) -#else -# define machine_is_smdk6400() (0) -#endif - #ifdef CONFIG_MACH_NOKIA_N800 # ifdef machine_arch_type # undef machine_arch_type diff --git
[U-Boot] [PATCH v9 29/30] arm1176: Remove unused MMU setup from start.S
Following the removal of the smdk6400 board, the MMU setup code in arm1176/start.S becomes unused, so remove it. It will still be possible to restore it later from the Git history if necessary, in which case it should be moved out of the relocate_code() function. Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com --- Changes in v9: - Do not use scrapyard in patch description because this is reserved to refer to the board scrapyard file. Changes in v8: - New patch. Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/cpu/arm1176/start.S | 91 +- 1 file changed, 1 insertion(+), 90 deletions(-) diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index b3c686a..18ac8d5 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -33,11 +33,8 @@ #include asm-offsets.h #include config.h #include version.h -#ifdef CONFIG_ENABLE_MMU -#include asm/proc/domain.h -#endif -#if !defined(CONFIG_ENABLE_MMU) !defined(CONFIG_SYS_PHY_UBOOT_BASE) +#ifndef CONFIG_SYS_PHY_UBOOT_BASE #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE #endif @@ -105,14 +102,6 @@ _TEXT_BASE: #endif /* - * Below variable is very important because we use MMU in U-Boot. - * Without it, we cannot run code correctly before MMU is ON. - * by scsuh. - */ -_TEXT_PHY_BASE: - .word CONFIG_SYS_PHY_UBOOT_BASE - -/* * These are defined in the board-specific linker script. * Subtracting _start from them lets the linker put their * relative position in the executable instead of leaving @@ -298,44 +287,6 @@ fixnext: blo fixloop #endif -#ifdef CONFIG_ENABLE_MMU -enable_mmu: - /* enable domain access */ - ldr r5, =0x - mcr p15, 0, r5, c3, c0, 0 /* load domain access register */ - - /* Set the TTB register */ - ldr r0, _mmu_table_base - ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE - ldr r2, =0xfff0 - bic r0, r0, r2 - orr r1, r0, r1 - mcr p15, 0, r1, c2, c0, 0 - - /* Enable the MMU */ - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #1 /* Set CR_M to enable MMU */ - - /* Prepare to enable the MMU */ - adr r1, skip_hw_init - and r1, r1, #0x3fc - ldr r2, _TEXT_BASE - ldr r3, =0xfff0 - and r2, r2, r3 - orr r2, r2, r1 - b mmu_enable - - .align 5 - /* Run in a single cache-line */ -mmu_enable: - - mcr p15, 0, r0, c1, c0, 0 - nop - nop - mov pc, r2 -skip_hw_init: -#endif - relocate_done: bx lr @@ -347,11 +298,6 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start -#ifdef CONFIG_ENABLE_MMU -_mmu_table_base: - .word mmu_table -#endif - .globl c_runtime_cpu_setup c_runtime_cpu_setup: @@ -359,41 +305,6 @@ c_runtime_cpu_setup: #ifndef CONFIG_SPL_BUILD /* - * we assume that cache operation is done before. (eg. cleanup_before_linux()) - * actually, we don't need to do anything about cache if not use d-cache in - * U-Boot. So, in this function we clean only MMU. by scsuh - * - * voidtheLastJump(void *kernel, int arch_num, uint boot_params); - */ -#ifdef CONFIG_ENABLE_MMU - .globl theLastJump -theLastJump: - mov r9, r0 - ldr r3, =0xfff0 - ldr r4, _TEXT_PHY_BASE - adr r5, phy_last_jump - bic r5, r5, r3 - orr r5, r5, r4 - mov pc, r5 -phy_last_jump: - /* -* disable MMU stuff -*/ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x2300 /* clear bits 13, 9:8 (--V- --RS) */ - bic r0, r0, #0x0087 /* clear bits 7, 2:0 (B--- -CAM) */ - orr r0, r0, #0x0002 /* set bit 2 (A) Align */ - orr r0, r0, #0x1000 /* set bit 12 (I) I-Cache */ - mcr p15, 0, r0, c1, c0, 0 - - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - mov r0, #0 - mov pc, r9 -#endif - - -/* * * * Interrupt handling -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v9 21/30] Makefile: Move SHELL setup to config.mk
make never uses the SHELL variable from the environment. Instead, it uses /bin/sh, or the value assigned to the SHELL variable by the Makefile. This makes the export of the SHELL variable useless for sub-makes (but still useful for the environment of recipes). However, we want all makes to use the same shell. This patch fixes this issue by moving the SHELL variable setup and export to the top config.mk, so that all Makefile-s including it use the same shell. Since BASH is used by default, this makes it possible to use things like 'echo -e ...' in sub-makes, which would otherwise fail e.g. with /bin/sh symlinked to /bin/dash on Ubuntu. Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com Reviewed-by: Tom Rini tr...@ti.com --- Changes in v9: None Changes in v8: - New patch. Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None Makefile |7 +-- config.mk |7 +++ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index 5bcc914..b1f0ff0 100644 --- a/Makefile +++ b/Makefile @@ -46,12 +46,7 @@ HOSTARCH := $(shell uname -m | \ HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \ sed -e 's/\(cygwin\).*/cygwin/') -# Set shell to bash if possible, otherwise fall back to sh -SHELL := $(shell if [ -x $$BASH ]; then echo $$BASH; \ - else if [ -x /bin/bash ]; then echo /bin/bash; \ - else echo sh; fi; fi) - -export HOSTARCH HOSTOS SHELL +export HOSTARCH HOSTOS # Deal with colliding definitions from tcsh etc. VENDOR= diff --git a/config.mk b/config.mk index b7cd481..21c0844 100644 --- a/config.mk +++ b/config.mk @@ -23,6 +23,13 @@ # +# Set shell to bash if possible, otherwise fall back to sh +SHELL := $(shell if [ -x $$BASH ]; then echo $$BASH; \ + else if [ -x /bin/bash ]; then echo /bin/bash; \ + else echo sh; fi; fi) + +export SHELL + include $(TOPDIR)/helper.mk ifeq ($(CURDIR),$(SRCTREE)) -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v9 30/30] arm: Make all linker scripts compatible with per-symbol sections
Let all ARM linker scripts handle properly -ffunction-sections
and -fdata-sections. This will be useful for future changes in order to create
symbol-specific sections in common .S files.
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com
---
Changes in v9:
- Reword following the removal of arm: Remove duplicated start.S code.
Changes in v8:
- New patch.
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/arm1136/u-boot-spl.lds|2 +-
arch/arm/cpu/arm920t/ep93xx/u-boot.lds | 10 +-
arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds |6 +++---
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds|6 +++---
arch/arm/cpu/armv7/omap-common/u-boot-spl.lds |2 +-
arch/arm/cpu/armv7/socfpga/u-boot-spl.lds |2 +-
board/ait/cam_enc_4xx/u-boot-spl.lds |2 +-
board/davinci/da8xxevm/u-boot-spl-da850evm.lds |2 +-
board/davinci/da8xxevm/u-boot-spl-hawk.lds |8
board/freescale/mx31ads/u-boot.lds | 20 ++--
board/samsung/smdk5250/smdk5250-uboot-spl.lds |2 +-
board/vpac270/u-boot-spl.lds |4 ++--
12 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/arch/arm/cpu/arm1136/u-boot-spl.lds
b/arch/arm/cpu/arm1136/u-boot-spl.lds
index a0462ab..deae361 100644
--- a/arch/arm/cpu/arm1136/u-boot-spl.lds
+++ b/arch/arm/cpu/arm1136/u-boot-spl.lds
@@ -38,7 +38,7 @@ SECTIONS
.text :
{
__start = .;
- arch/arm/cpu/arm1136/start.o (.text)
+ arch/arm/cpu/arm1136/start.o (.text*)
*(.text*)
} .sram
diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
index 62315de..72912de 100644
--- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
+++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
@@ -31,18 +31,18 @@ SECTIONS
. = ALIGN(4);
.text :
{
- arch/arm/cpu/arm920t/start.o (.text)
+ arch/arm/cpu/arm920t/start.o (.text*)
/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
. = 0x1000;
LONG(0x53555243)
- *(.text)
+ *(.text*)
}
. = ALIGN(4);
- .rodata : { *(.rodata) }
+ .rodata : { *(.rodata*) }
. = ALIGN(4);
- .data : { *(.data) }
+ .data : { *(.data*) }
. = ALIGN(4);
.got : { *(.got) }
@@ -59,7 +59,7 @@ SECTIONS
__image_copy_end = .;
__bss_start = .;
- .bss : { *(.bss) }
+ .bss : { *(.bss*) }
__bss_end__ = .;
_end = .;
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
index 6dc681a..80693da 100644
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
@@ -37,8 +37,8 @@ SECTIONS
. = ALIGN(4);
.text :
{
- arch/arm/cpu/arm926ejs/mxs/start.o (.text)
- *(.text)
+ arch/arm/cpu/arm926ejs/mxs/start.o (.text*)
+ *(.text*)
}
. = ALIGN(4);
@@ -46,7 +46,7 @@ SECTIONS
. = ALIGN(4);
.data : {
- *(.data)
+ *(.data*)
}
. = ALIGN(4);
diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
index f3bd5e7..3146f79 100644
--- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
@@ -37,8 +37,8 @@ SECTIONS
. = ALIGN(4);
.text :
{
- arch/arm/cpu/arm926ejs/spear/start.o(.text)
- *(.text)
+ arch/arm/cpu/arm926ejs/spear/start.o(.text*)
+ *(.text*)
}
. = ALIGN(4);
@@ -46,7 +46,7 @@ SECTIONS
. = ALIGN(4);
.data : {
- *(.data)
+ *(.data*)
}
. = ALIGN(4);
diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
index 9979c30..0b923f8 100644
--- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
@@ -38,7 +38,7 @@ SECTIONS
.text :
{
__start = .;
- arch/arm/cpu/armv7/start.o (.text)
+ arch/arm/cpu/armv7/start.o (.text*)
*(.text*)
} .sram
diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
index 7cd409c..ff309b9 100644
--- a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
@@ -27,7 +27,7 @@ SECTIONS
. = ALIGN(4);
.text :
{
- arch/arm/cpu/armv7/start.o (.text)
+ arch/arm/cpu/armv7/start.o (.text*)
*(.text*)
} .sdram
diff --git
[U-Boot] [PATCH v9 26/30] Revert mkconfig: start deprecating Makefile config targets
This reverts commit 1285a2808a254f3d1a809c1a541f0c0f746e03d7 since the migration
of boards from Makefile to boards.cfg is now complete.
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com
---
Changes in v9: None
Changes in v8:
- New patch.
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
doc/feature-removal-schedule.txt | 16
mkconfig |9 -
2 files changed, 25 deletions(-)
diff --git a/doc/feature-removal-schedule.txt b/doc/feature-removal-schedule.txt
index e04ba2d..6abb7d1 100644
--- a/doc/feature-removal-schedule.txt
+++ b/doc/feature-removal-schedule.txt
@@ -18,22 +18,6 @@ Who: Andy Fleming aflem...@freescale.com and driver
maintainers
---
-What: boards with xxx_config targets in top level Makefile
-When: Release v2012.03
-
-Why: We have a boards.cfg file which the vast majority of boards have
- converted over to. Boards that still manually run mkconfig in the
- top level Makefile are either dead, or the maintainer doesn't care,
- or they are doing something weird/wrong that should be fixed in a
- different way, or they need to extend boards.cfg syntax (unlikely).
-
- In any case, if no one cares about these boards to figure out how
- to make boards.cfg work, then we'll just punt them.
-
-Who: Mike Frysinger vap...@gentoo.org
-
-
What: GPL cleanup
When: August 2009
Why: Over time, a couple of files have sneaked in into the U-Boot
diff --git a/mkconfig b/mkconfig
index 7c9aa74..73f852e 100755
--- a/mkconfig
+++ b/mkconfig
@@ -29,15 +29,6 @@ if [ \( $# -eq 2 \) -a \( $1 = -A \) ] ; then
set ${line}
# add default board name if needed
[ $# = 3 ] set ${line} ${1}
-elif [ ${MAKEFLAGS+set}${MAKELEVEL+set} = setset ] ; then
- # only warn when using a config target in the Makefile
- cat -EOF
-
- warning: Please migrate to boards.cfg. Failure to do so will
-mean removal of your board in the next release.
-
- EOF
- sleep 5
fi
while [ $# -gt 0 ] ; do
--
1.7.10.4
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[U-Boot] [PATCH v9 23/30] imx: Add u-boot-with-spl.imx make target
This image combines the SPL with the i.MX header and U-Boot. This is a
convenient way of having a single image to program on some boot devices.
The i.MX header has to be added to the SPL before appending U-Boot, so that the
boot ROM loads only the SPL.
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com
---
Changes in v9: None
Changes in v8:
- Use CONFIG_SPL_PAD_TO instead of CONFIG_SPL_MAX_SIZE for padding, which
allows to pad the SPL after adding the i.MX header, which may save time when
the boot ROM loads the SPL.
- Add /u-boot-with-spl.imx to .gitignore.
Changes in v7:
- New patch.
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
.gitignore |1 +
Makefile |5 +
arch/arm/imx-common/Makefile |6 ++
3 files changed, 12 insertions(+)
diff --git a/.gitignore b/.gitignore
index a803651..1d07fec 100644
--- a/.gitignore
+++ b/.gitignore
@@ -30,6 +30,7 @@
/u-boot
/u-boot.hex
/u-boot.imx
+/u-boot-with-spl.imx
/u-boot.map
/u-boot.srec
/u-boot.ldr
diff --git a/Makefile b/Makefile
index b1f0ff0..38f2ca5 100644
--- a/Makefile
+++ b/Makefile
@@ -484,6 +484,10 @@ $(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin
$(obj)u-boot.bin
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $@
rm $(obj)spl/u-boot-spl-pad.bin
+$(obj)u-boot-with-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+ $(MAKE) -C $(SRCTREE)/arch/arm/imx-common \
+ $(OBJTREE)/u-boot-with-spl.imx
+
$(obj)u-boot.ubl: $(obj)u-boot-with-spl.bin
$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
-e $(CONFIG_SYS_TEXT_BASE) -d $ $(obj)u-boot.ubl
@@ -855,6 +859,7 @@ clobber:tidy
@rm -f $(obj)u-boot.kwb
@rm -f $(obj)u-boot.pbl
@rm -f $(obj)u-boot.imx
+ @rm -f $(obj)u-boot-with-spl.imx
@rm -f $(obj)u-boot.ubl
@rm -f $(obj)u-boot.ais
@rm -f $(obj)u-boot.dtb
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 6309fcd..2ce182d 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -54,6 +54,12 @@ $(OBJTREE)/SPL: $(OBJTREE)/spl/u-boot-spl.bin
$(OBJTREE)/$(patsubst %,%,$(CONF
$(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \
-e $(CONFIG_SPL_TEXT_BASE) -d $ $@
+$(OBJTREE)/u-boot-with-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
+ -I binary -O binary $ $(OBJTREE)/spl/u-boot-spl-pad.imx
+ cat $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.bin $@
+ rm $(OBJTREE)/spl/u-boot-spl-pad.imx
+
#
--
1.7.10.4
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[U-Boot] [PATCH v9 24/30] imx: Add u-boot-with-nand-spl.imx make target
This image combines the SPL with the i.MX header, the FCB and U-Boot.
For i.MX25/35/51, the FCB is ignored by the boot ROM, so this image is just
useful because it can be programmed on a NAND Flash page boundary.
For i.MX53, the FCB is required by the boot ROM.
This does not support i.MX6 so far because its FCB is more complicated.
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com
---
Changes in v9: None
Changes in v8:
- Change the dummy 1024-byte header into a true FCB in order to add support for
i.MX53.
- Use CONFIG_SPL_PAD_TO instead of CONFIG_SPL_MAX_SIZE for padding, which
allows to pad the SPL after adding the i.MX header and the FCB, which may
save time when the boot ROM loads the SPL.
- Add /u-boot-with-nand-spl.imx to .gitignore.
Changes in v7:
- New patch.
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
.gitignore |1 +
Makefile |5 +
arch/arm/imx-common/Makefile | 11 +++
3 files changed, 17 insertions(+)
diff --git a/.gitignore b/.gitignore
index 1d07fec..c991631 100644
--- a/.gitignore
+++ b/.gitignore
@@ -31,6 +31,7 @@
/u-boot.hex
/u-boot.imx
/u-boot-with-spl.imx
+/u-boot-with-nand-spl.imx
/u-boot.map
/u-boot.srec
/u-boot.ldr
diff --git a/Makefile b/Makefile
index 38f2ca5..0069c86 100644
--- a/Makefile
+++ b/Makefile
@@ -488,6 +488,10 @@ $(obj)u-boot-with-spl.imx: $(obj)spl/u-boot-spl.bin
$(obj)u-boot.bin
$(MAKE) -C $(SRCTREE)/arch/arm/imx-common \
$(OBJTREE)/u-boot-with-spl.imx
+$(obj)u-boot-with-nand-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+ $(MAKE) -C $(SRCTREE)/arch/arm/imx-common \
+ $(OBJTREE)/u-boot-with-nand-spl.imx
+
$(obj)u-boot.ubl: $(obj)u-boot-with-spl.bin
$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
-e $(CONFIG_SYS_TEXT_BASE) -d $ $(obj)u-boot.ubl
@@ -860,6 +864,7 @@ clobber:tidy
@rm -f $(obj)u-boot.pbl
@rm -f $(obj)u-boot.imx
@rm -f $(obj)u-boot-with-spl.imx
+ @rm -f $(obj)u-boot-with-nand-spl.imx
@rm -f $(obj)u-boot.ubl
@rm -f $(obj)u-boot.ais
@rm -f $(obj)u-boot.dtb
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 2ce182d..d54dbee 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -60,6 +60,17 @@ $(OBJTREE)/u-boot-with-spl.imx: $(OBJTREE)/SPL
$(OBJTREE)/u-boot.bin
cat $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.bin $@
rm $(OBJTREE)/spl/u-boot-spl-pad.imx
+$(OBJTREE)/u-boot-with-nand-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin
+ (echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' \
+ dd bs=1015 count=1 if=/dev/zero 2/dev/null) | \
+ cat - $ $(OBJTREE)/spl/u-boot-nand-spl.imx
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
+ -I binary -O binary $(OBJTREE)/spl/u-boot-nand-spl.imx \
+ $(OBJTREE)/spl/u-boot-nand-spl-pad.imx
+ rm $(OBJTREE)/spl/u-boot-nand-spl.imx
+ cat $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.bin $@
+ rm $(OBJTREE)/spl/u-boot-nand-spl-pad.imx
+
#
--
1.7.10.4
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[U-Boot] [PATCH v9 28/30] arm: Remove deprecated and now unused NAND SPL
Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com --- Changes in v9: None Changes in v8: - New patch. Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/config.mk |2 -- arch/arm/cpu/arm1176/start.S | 12 arch/arm/lib/crt0.S | 16 ++-- 3 files changed, 6 insertions(+), 24 deletions(-) diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 24b9d7c..83320cb 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -84,9 +84,7 @@ endif endif # needed for relocation -ifndef CONFIG_NAND_SPL LDFLAGS_u-boot += -pie -endif # # FIXME: binutils versions 2.22 have a bug in the assembler where diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 97d347c..b3c686a 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -51,7 +51,7 @@ .globl _start _start: b reset -#ifndef CONFIG_NAND_SPL +#ifndef CONFIG_SPL_BUILD ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -98,15 +98,11 @@ _end_vect: .globl _TEXT_BASE _TEXT_BASE: -#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ - .word CONFIG_SYS_TEXT_BASE -#else #if defined(CONFIG_SPL_BUILD) defined(CONFIG_SPL_TEXT_BASE) .word CONFIG_SPL_TEXT_BASE #else .word CONFIG_SYS_TEXT_BASE #endif -#endif /* * Below variable is very important because we use MMU in U-Boot. @@ -176,7 +172,7 @@ cpu_init_crit: * When booting from NAND - it has definitely been a reset, so, no need * to flush caches and disable the MMU */ -#ifndef CONFIG_NAND_SPL +#ifndef CONFIG_SPL_BUILD /* * flush v4 I/D caches */ @@ -361,7 +357,7 @@ c_runtime_cpu_setup: mov pc, lr -#ifndef CONFIG_NAND_SPL +#ifndef CONFIG_SPL_BUILD /* * we assume that cache operation is done before. (eg. cleanup_before_linux()) * actually, we don't need to do anything about cache if not use d-cache in @@ -539,4 +535,4 @@ fiq: get_bad_stack bad_save_user_regs bl do_fiq -#endif /* CONFIG_NAND_SPL */ +#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 7950469..6fcb7d1 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -64,7 +64,7 @@ *have some work left to do at this point regarding memory, so *call c_runtime_cpu_setup. * - * 6. Branch to either nand_boot() or board_init_r(). + * 6. Branch to board_init_r(). */ /* @@ -77,10 +77,7 @@ ENTRY(_main) * Set up initial C runtime environment and call board_init_f(0). */ -#if defined(CONFIG_NAND_SPL) - /* deprecated, use instead CONFIG_SPL_BUILD */ - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) -#elif defined(CONFIG_SPL_BUILD) defined(CONFIG_SPL_STACK) +#if defined(CONFIG_SPL_BUILD) defined(CONFIG_SPL_STACK) ldr sp, =(CONFIG_SPL_STACK) #else ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) @@ -129,21 +126,12 @@ clbss_l:cmp r0, r1 /* while not at end of BSS */ bl coloured_LED_init bl red_led_on -#if defined(CONFIG_NAND_SPL) - - /* call _nand_boot() */ - ldr pc, =nand_boot - -#else - /* call board_init_r(gd_t *id, ulong dest_addr) */ mov r0, r8 /* gd_t */ ldr r1, [r8, #GD_RELOCADDR] /* dest_addr */ /* call board_init_r */ ldr pc, =board_init_r /* this is auto-relocated! */ -#endif - /* we should not return here. */ #endif -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v9 01/30] mtd: nand: Introduce CONFIG_SYS_NAND_BUSWIDTH_16BIT
On 03/06/2013 12:59:07 PM, Benoît Thébaudeau wrote: From: Fabio Estevam fabio.este...@freescale.com Introduce CONFIG_SYS_NAND_BUSWIDTH_16BIT option so that other NAND controller drivers could use it when a 16-bit NAND is deployed. drivers/mtd/nand/ndfc has CONFIG_SYS_NDFC_16BIT, so just rename it, so that other NAND drivers could reuse the same symbol. Signed-off-by: Fabio Estevam fabio.este...@freescale.com Reviewed-by: Benoît Thébaudeau benoit.thebaud...@advansee.com NAND bits in the entire patchset are: Acked-by: Scott Wood scottw...@freescale.com -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v9 15/30] autoconfig.mk: Make it possible to define configs from other configs
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 03/06/2013 01:59 PM, Benoît Thébaudeau wrote: Give more flexibility to define configs that can be interpreted by make, e.g. to define fallback values of configs like in the example below. Before this change, the config lines: #define CONFIG_SPL_MAX_SIZE 2048 #define CONFIG_SPL_PAD_TOCONFIG_SPL_MAX_SIZE would have been changed in autoconfig.mk into: CONFIG_SPL_MAX_SIZE=2048 CONFIG_SPL_PAD_TO=CONFIG_SPL_MAX_SIZE Hence, a make recipe using as an argument to $(OBJCOPY): --pad-to=$(CONFIG_SPL_PAD_TO) would have issued: --pad-to=CONFIG_SPL_MAX_SIZE which means nothing for $(OBJCOPY) and makes it fail. Thanks to this change, the config lines above are changed in autoconfig.mk into: CONFIG_SPL_MAX_SIZE=2048 CONFIG_SPL_PAD_TO=$(CONFIG_SPL_MAX_SIZE) Hence, the make recipe above now issues: --pad-to=2048 as expected from the defined config. Signed-off-by: Benoît Thébaudeau benoit.thebaud...@advansee.com Reviewed-by: Tom Rini tr...@ti.com - -- Tom -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQIcBAEBAgAGBQJRN6/MAAoJENk4IS6UOR1WACkQAJAPi/TwObDQvj+cUTlnkgju 51jVn9fgqENaTmDLtiq0yQrj50iIhCjHHJ9Bv6HK6lWjCDK9tjGStYoZsk6TH0Tp M5rhRIUjEZBaceubShP9f9219xmtYVeIt/nC2E9w5QKAx3MHE3KpOMHw+pH3AC6g Bayvt5+TlTrwRlxhUuANB9f5DOyF0FFpKzijWhF9iUzNp4S7hl+QqZpbh2qGSxVd UgZmm43MTvPmhCf7JKjrYXCE/OLTW6poSkaLLEOUMhufipQ1JXAQkltFewmk2jDE lBmQ16Kcwo68J9PMWLpGzpvAdCh2qkGCPPxr2zlwlpw2mSNLZTfKqguoX2BTvnZY NJYQPOSZmBVhoF1+G6CJQE+8ukY4UxyBeG+gD2OPOL25oE4FSWLbMVWkx/slhIWt ujcaW3pw0hGG/CjmQyO1O36raFZfFOkb3mGYwl5xH7cKnXPOMQcYGZ77JWbyyQRV MTaeh9deyszgzecAJ5D6ZnqB7G6XvDKzcphZF3xPHuOMhKKn+03VHHz0vWS0GLT1 cEEymvSCtjID2fl7iRNp/WZ+EYS7EUb/9M9T8iaJ79wQHe6V0xikz62YbMe8NE6+ 7DHuz8N00FdgFEGvtZFW33oXUpVEduTQbwCJwOVSo+tfJ60v48xdsVTvTbUM4QAo Vf3gCKoyudLJtD67ffZs =n8jq -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 4/7] usb: ehci: Fix aliasing issue in EHCI interrupt code
+Julius
Hi Marek,
On Thu, Dec 13, 2012 at 6:21 PM, Simon Glass s...@chromium.org wrote:
From: Vincent Palatin vpala...@chromium.org
The interrupt endpoint handling code stores the buffer pointer in the QH
padding field. We need to make it the size of a pointer to avoid strict
aliasing issue with the compiler.
Signed-off-by: Vincent Palatin vpala...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
I think this patch and a few others are still in the queue. Does that
sound right to you?
9c9f379 x86: Enable USB features for coreboot
ecefc3fc usb: Add multiple controllers support for EHCI PCI
4950984 usb: usbeth: smsc95xx: remove EEPROM loaded check
606a9e0 usb: ehci: Fix aliasing issue in EHCI interrupt code
d2f9f89 usb: ehci: Support interrupt transfers via periodic list
We will be sending a v3 with a few fixes.
Regards,
Simon
---
Changes in v2: None
drivers/usb/host/ehci.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index 8bc2ba1..5370eb0 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -247,7 +247,7 @@ struct QH {
* aligned to 32 bytes
*/
union {
- uint8_t fill[16];
+ uint32_t fill[4];
void *buffer;
};
};
--
1.7.7.3
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[U-Boot] driver for davicom dm9601 usb-ethernet NIC
Hello Everyone,
I'm working on Beagleboard C3, and i'm trying to do an nfs-boot.
Please find below my bootup log. I'm getting the below error.
After digging into the details of the error, could make out that my
Ethernet NIC is not there in the supported drivers list of U-Boot
{drivers/usb/eth/}
I'm using Davicom DM9601 USB-Ethernet NIC. I would like to check with u
guys whether u've got any drivers for the same?
???40V???�H��?ս��сSPL 2011.12-00010-ga3eb89c (Jan 29 2012 - 14:53:43)
Texas Instruments Revision detection unimplemented
OMAP SD/MMC: 0
reading u-boot.img
reading u-boot.img
U-Boot 2013.01 (Feb 22 2013 - 13:00:08)
OMAP3530-GP ES3.0, CPU-OPP2, L3-165MHz, Max CPU Clock 600 mHz
OMAP3 Beagle board + LPDDR/NAND
I2C: ready
DRAM: 256 MiB
NAND: 256 MiB
MMC: OMAP SD/MMC: 0
*** Warning - bad CRC, using default environment
In:serial
Out: serial
Err: serial
Beagle Rev C1/C2/C3
timed out in wait_for_pin: I2C_STAT=0
No EEPROM on expansion board
timed out in wait_for_pin: I2C_STAT=0
No EEPROM on expansion board
Die ID #12ac0003040323090f024015
musb-hdrc: ConfigData=0xde (UTMI-8, dyn FIFOs, bulk combine, bulk split,
HB-ISO Rx, HB-ISO Tx, SoftConn)
musb-hdrc: MHDRC RTL version 1.400
musb-hdrc: setup fifo_mode 4
musb-hdrc: 28/31 max ep, 16384/16384 memory
USB Peripheral mode controller at 480ab000 using PIO, IRQ 0
Net: usb_ether
Hit any key to stop autoboot: 0
mmc0 is current device
gpio: pin 173 (gpio 173) value is 1
gpio: pin 7 (gpio 7) value is 0
SD/MMC found on device 0
reading uEnv.txt
769 bytes read in 3 ms (250 KiB/s)
Loaded environment from uEnv.txt
Importing environment from mmc ...
Running uenvcmd ...
Initializing net ...
(Re)start USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... 4 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
scanning usb for ethernet devices... 0 Ethernet Device(s) found
Loading kernel ...
using musb-hdrc, OUT ep1out IN ep1in
MAC 00:60:6e:00:f1:cd
*ERROR: The remote end did not respond in time.
at ether.c:2395/usb_eth_init()*
Booting from nfs ...
Wrong Image Format for bootm command
ERROR: can't get kernel image!
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[U-Boot] [PATCH] Tegra30: Cardhu: Add pad config tables/code based on pinmux code
Pad config registers exist in APB_MISC_GP space, and control slew
rate, drive strengh, schmidt, high-speed, and low-power modes for
all of the pingroups in Tegra30. This builds off of the pinmux
way of constructing init tables to configure select pads (SDIOCFG,
for instance) during pinmux_init().
Currently, only SDIO1CFG is changed as per the TRM to work with
the SD-card slot on Cardhu.
Thanks to StephenW for the suggestion/original idea.
Signed-off-by: Tom Warren twar...@nvidia.com
---
arch/arm/cpu/tegra30-common/pinmux.c | 210 +---
arch/arm/include/asm/arch-tegra30/gp_padctrl.h |8 +-
arch/arm/include/asm/arch-tegra30/pinmux.h | 68 -
board/nvidia/cardhu/cardhu.c |6 +-
board/nvidia/cardhu/pinmux-config-cardhu.h | 21 ++-
5 files changed, 278 insertions(+), 35 deletions(-)
diff --git a/arch/arm/cpu/tegra30-common/pinmux.c
b/arch/arm/cpu/tegra30-common/pinmux.c
index 9ba0ec8..5a5862a 100644
--- a/arch/arm/cpu/tegra30-common/pinmux.c
+++ b/arch/arm/cpu/tegra30-common/pinmux.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -39,6 +39,19 @@ struct tegra_pingroup_desc {
#define PMUX_LOCK_SHIFT7
#define PMUX_IO_RESET_SHIFT8
+#define PGRP_HSM_SHIFT 2
+#define PGRP_SCHMT_SHIFT 3
+#define PGRP_LPMD_SHIFT4
+#define PGRP_LPMD_MASK (3 PGRP_LPMD_SHIFT)
+#define PGRP_DRVDN_SHIFT 12
+#define PGRP_DRVDN_MASK(0x7F PGRP_DRVDN_SHIFT)
+#define PGRP_DRVUP_SHIFT 20
+#define PGRP_DRVUP_MASK(0x7F PGRP_DRVUP_SHIFT)
+#define PGRP_SLWR_SHIFT28
+#define PGRP_SLWR_MASK (3 PGRP_SLWR_SHIFT)
+#define PGRP_SLWF_SHIFT30
+#define PGRP_SLWF_MASK (3 PGRP_SLWF_SHIFT)
+
/* Convenient macro for defining pin group properties */
#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
{ \
@@ -506,28 +519,177 @@ void pinmux_config_table(struct pingroup_config *config,
int len)
pinmux_config_pingroup(config[i]);
}
-void pinmux_sdio_pad_cfg(void)
+static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad,
+ int slwf)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_slwf = pmt-pmt_drive[pad];
+ u32 reg;
+
+ /* Error check on pad and slwf */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_slw_isvalid(slwf));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (slwf == PGRP_SLWF_NONE)
+ return 0;
+
+ reg = readl(pad_slwf);
+ reg = ~PGRP_SLWF_MASK;
+ reg |= (slwf PGRP_SLWF_SHIFT);
+ writel(reg, pad_slwf);
+
+ return 0;
+}
+
+static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_slwr = pmt-pmt_drive[pad];
+ u32 reg;
+
+ /* Error check on pad and slwr */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_slw_isvalid(slwr));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (slwr == PGRP_SLWR_NONE)
+ return 0;
+
+ reg = readl(pad_slwr);
+ reg = ~PGRP_SLWR_MASK;
+ reg |= (slwr PGRP_SLWR_SHIFT);
+ writel(reg, pad_slwr);
+
+ return 0;
+}
+
+static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_drvup = pmt-pmt_drive[pad];
+ u32 reg;
+
+ /* Error check on pad and drvup */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_drv_isvalid(drvup));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (drvup == PGRP_DRVUP_NONE)
+ return 0;
+
+ reg = readl(pad_drvup);
+ reg = ~PGRP_DRVUP_MASK;
+ reg |= (drvup PGRP_DRVUP_SHIFT);
+ writel(reg, pad_drvup);
+
+ return 0;
+}
+
+static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_drvdn = pmt-pmt_drive[pad];
+ u32 reg;
+
+ /* Error check on pad and drvdn */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_drv_isvalid(drvdn));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (drvdn == PGRP_DRVDN_NONE)
+ return 0;
+
+ reg = readl(pad_drvdn);
+ reg = ~PGRP_DRVDN_MASK;
+ reg |=
[U-Boot] [PATCH v3 0/5] Various USB improvements
This series adds a few USB improvements for Marek: - Support for interupt transfers - Basic 64-bit controller support (used by x86) - Multiple controller support for EHCI PCI Changes in v3: - Set last pointer to correct position in create_int_queue() - Set S-mask bit always, not just on low-speed devices - Correct logic flow in destroy_int_queue() Changes in v2: - Update to use errno - Remove TODOs - Tidy code style a little - Squash timeouts patch into interrupt patch - Add blank line before function return Michael Spang (1): usb: usbeth: smsc95xx: remove EEPROM loaded check Patrick Georgi (1): usb: ehci: Support interrupt transfers via periodic list Simon Glass (1): x86: Enable USB features for coreboot Vincent Palatin (2): usb: ehci: Fix aliasing issue in EHCI interrupt code usb: Add multiple controllers support for EHCI PCI drivers/usb/eth/smsc95xx.c | 4 - drivers/usb/host/ehci-hcd.c | 315 +++- drivers/usb/host/ehci-pci.c | 52 +++- drivers/usb/host/ehci.h | 6 +- include/configs/coreboot.h | 17 +++ 5 files changed, 379 insertions(+), 15 deletions(-) -- 1.8.1.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 1/5] usb: ehci: Support interrupt transfers via periodic list
From: Patrick Georgi patr...@georgi-clan.de
Interrupt transfers aren't meant to be used from the async list
(the EHCI spec indicates trouble with low/full-speed intr on async).
Build a periodic list instead, and provide an API to make use of it.
Then, use that API from the existing interrupt transfer API.
This provides support for USB keyboards using EHCI.
Use timeouts to ensure we cannot get stuck in the keyboard scanning
if something wrong happens (USB device unplugged or fatal I/O error)
Signed-off-by: Vincent Palatin vpala...@chromium.org
Signed-off-by: Julius Werner jwer...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3:
- Set last pointer to correct position in create_int_queue()
- Set S-mask bit always, not just on low-speed devices
- Correct logic flow in destroy_int_queue()
Changes in v2:
- Update to use errno
- Remove TODOs
- Tidy code style a little
- Squash timeouts patch into interrupt patch
drivers/usb/host/ehci-hcd.c | 315 +++-
drivers/usb/host/ehci.h | 6 +-
2 files changed, 316 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 7f98a63..25c2216 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -21,12 +21,14 @@
* MA 02111-1307 USA
*/
#include common.h
+#include errno.h
#include asm/byteorder.h
#include asm/unaligned.h
#include usb.h
#include asm/io.h
#include malloc.h
#include watchdog.h
+#include linux/compiler.h
#include ehci.h
@@ -39,7 +41,10 @@ static struct ehci_ctrl {
struct ehci_hcor *hcor;
int rootdev;
uint16_t portreset;
- struct QH qh_list __attribute__((aligned(USB_DMA_MINALIGN)));
+ struct QH qh_list __aligned(USB_DMA_MINALIGN);
+ struct QH periodic_queue __aligned(USB_DMA_MINALIGN);
+ uint32_t *periodic_list;
+ int ntds;
} ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
#define ALIGN_END_ADDR(type, ptr, size)\
@@ -858,6 +863,8 @@ int usb_lowlevel_init(int index, void **controller)
uint32_t reg;
uint32_t cmd;
struct QH *qh_list;
+ struct QH *periodic;
+ int i;
if (ehci_hcd_init(index, ehcic[index].hccr, ehcic[index].hcor))
return -1;
@@ -884,6 +891,40 @@ int usb_lowlevel_init(int index, void **controller)
qh_list-qh_overlay.qt_token =
cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
+ /* Set async. queue head pointer. */
+ ehci_writel(ehcic[index].hcor-or_asynclistaddr, (uint32_t)qh_list);
+
+ /*
+* Set up periodic list
+* Step 1: Parent QH for all periodic transfers.
+*/
+ periodic = ehcic[index].periodic_queue;
+ memset(periodic, 0, sizeof(*periodic));
+ periodic-qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
+ periodic-qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
+ periodic-qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
+
+ /*
+* Step 2: Setup frame-list: Every microframe, USB tries the same list.
+* In particular, device specifications on polling frequency
+* are disregarded. Keyboards seem to send NAK/NYet reliably
+* when polled with an empty buffer.
+*
+* Split Transactions will be spread across microframes using
+* S-mask and C-mask.
+*/
+ ehcic[index].periodic_list = memalign(4096, 1024*4);
+ if (!ehcic[index].periodic_list)
+ return -ENOMEM;
+ for (i = 0; i 1024; i++) {
+ ehcic[index].periodic_list[i] = (uint32_t)periodic
+ | QH_LINK_TYPE_QH;
+ }
+
+ /* Set periodic list base address */
+ ehci_writel(ehcic[index].hcor-or_periodiclistbase,
+ (uint32_t)ehcic[index].periodic_list);
+
reg = ehci_readl(ehcic[index].hccr-cr_hcsparams);
descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
debug(Register %x NbrPorts %d\n, reg, descriptor.hub.bNbrPorts);
@@ -953,10 +994,254 @@ submit_control_msg(struct usb_device *dev, unsigned long
pipe, void *buffer,
return ehci_submit_async(dev, pipe, buffer, length, setup);
}
+struct int_queue {
+ struct QH *first;
+ struct QH *current;
+ struct QH *last;
+ struct qTD *tds;
+};
+
+#define NEXT_QH(qh) (struct QH *)((qh)-qh_link ~0x1f)
+
+static int
+enable_periodic(struct ehci_ctrl *ctrl)
+{
+ uint32_t cmd;
+ struct ehci_hcor *hcor = ctrl-hcor;
+ int ret;
+
+ cmd = ehci_readl(hcor-or_usbcmd);
+ cmd |= CMD_PSE;
+ ehci_writel(hcor-or_usbcmd, cmd);
+
+ ret = handshake((uint32_t *)hcor-or_usbsts,
+ STS_PSS, STS_PSS, 100 * 1000);
+ if (ret 0) {
+ printf(EHCI failed: timeout when enabling periodic list\n);
+ return -ETIMEDOUT;
+
[U-Boot] [PATCH v3 2/5] usb: ehci: Fix aliasing issue in EHCI interrupt code
From: Vincent Palatin vpala...@chromium.org
The interrupt endpoint handling code stores the buffer pointer in the QH
padding field. We need to make it the size of a pointer to avoid strict
aliasing issue with the compiler.
Signed-off-by: Vincent Palatin vpala...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/usb/host/ehci.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index 46b535f..d090f0a 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -247,7 +247,7 @@ struct QH {
* aligned to 32 bytes
*/
union {
- uint8_t fill[16];
+ uint32_t fill[4];
void *buffer;
};
};
--
1.8.1.3
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[U-Boot] [PATCH v3 5/5] x86: Enable USB features for coreboot
Enable PCI EHCI, storage, keyboard and Ethernet for USB. Signed-off-by: Simon Glass s...@chromium.org --- Changes in v3: None Changes in v2: None include/configs/coreboot.h | 17 + 1 file changed, 17 insertions(+) diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index c7f36ff..ebc165f 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -267,6 +267,23 @@ */ #define CONFIG_PCI +/*--- + * USB configuration + */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_PCI +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12 +#define CONFIG_USB_MAX_CONTROLLER_COUNT2 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL + +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX + +#define CONFIG_CMD_USB + #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_STD_DEVICES_SETTINGS -- 1.8.1.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 4/5] usb: Add multiple controllers support for EHCI PCI
From: Vincent Palatin vpala...@chromium.org
Use the ability to have several active EHCI controller on a system
in the PCI EHCI controller implementation.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2:
- Add blank line before function return
drivers/usb/host/ehci-pci.c | 52 +++--
1 file changed, 46 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 29af02d..61a9909 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -32,30 +32,70 @@ static struct pci_device_id ehci_pci_ids[] = {
{0x12D8, 0x400F}, /* Pericom */
{0, 0}
};
+#else
+static pci_dev_t ehci_find_class(int index)
+{
+ int bus;
+ int devnum;
+ pci_dev_t bdf;
+ uint32_t class;
+
+ for (bus = 0; bus = pci_last_busno(); bus++) {
+ for (devnum = 0; devnum PCI_MAX_PCI_DEVICES-1; devnum++) {
+ pci_read_config_dword(PCI_BDF(bus, devnum, 0),
+ PCI_CLASS_REVISION, class);
+ if (class 16 == 0x)
+ continue;
+
+ for (bdf = PCI_BDF(bus, devnum, 0);
+ bdf = PCI_BDF(bus, devnum,
+ PCI_MAX_PCI_FUNCTIONS - 1);
+ bdf += PCI_BDF(0, 0, 1)) {
+ pci_read_config_dword(bdf, PCI_CLASS_REVISION,
+ class);
+ if ((class 8 == PCI_CLASS_SERIAL_USB_EHCI)
+!index--)
+ return bdf;
+ }
+ }
+ }
+
+ return -ENODEV;
+}
#endif
/*
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, struct ehci_hccr **ret_hccr,
+ struct ehci_hcor **ret_hcor)
{
pci_dev_t pdev;
+ struct ehci_hccr *hccr;
+ struct ehci_hcor *hcor;
+#ifdef CONFIG_PCI_EHCI_DEVICE
pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVICE);
+#else
+ pdev = ehci_find_class(index);
+#endif
if (pdev == -1) {
printf(EHCI host controller not found\n);
return -1;
}
- *hccr = (struct ehci_hccr *)pci_map_bar(pdev,
+ hccr = (struct ehci_hccr *)pci_map_bar(pdev,
PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
- *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
- HC_LENGTH(ehci_readl((*hccr)-cr_capbase)));
+ hcor = (struct ehci_hcor *)((uint32_t) hccr +
+ HC_LENGTH(ehci_readl(hccr-cr_capbase)));
debug(EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n,
- (uint32_t)*hccr, (uint32_t)*hcor,
- (uint32_t)HC_LENGTH(ehci_readl((*hccr)-cr_capbase)));
+ (uint32_t)hccr, (uint32_t)hcor,
+ (uint32_t)HC_LENGTH(ehci_readl(hccr-cr_capbase)));
+
+ *ret_hccr = hccr;
+ *ret_hcor = hcor;
return 0;
}
--
1.8.1.3
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[U-Boot] [PATCH v3 3/5] usb: usbeth: smsc95xx: remove EEPROM loaded check
From: Michael Spang sp...@chromium.org
[port of Linux kernel commit bcd218be5aeb by Steve Glendinning]
The eeprom read write commands currently check the E2P_CMD_LOADED_ bit is
set before allowing any operations. This prevents any reading or writing
unless a correctly programmed EEPROM is installed.
Signed-off-by: Michael Spang sp...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
Acked-by: Marek Vasut ma...@denx.de
---
Changes in v3: None
Changes in v2: None
drivers/usb/eth/smsc95xx.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c
index dc5ca65..fd8f8a7 100644
--- a/drivers/usb/eth/smsc95xx.c
+++ b/drivers/usb/eth/smsc95xx.c
@@ -265,10 +265,6 @@ static int smsc95xx_eeprom_confirm_not_busy(struct
ueth_data *dev)
do {
smsc95xx_read_reg(dev, E2P_CMD, val);
- if (!(val E2P_CMD_LOADED_)) {
- debug(No EEPROM present\n);
- return -1;
- }
if (!(val E2P_CMD_BUSY_))
return 0;
udelay(40);
--
1.8.1.3
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Re: [U-Boot] [PATCH 4/5 v4] gen: Add ACE acceleration to hash
On Tue, 5 Mar 2013 22:22:09 -0800
Simon Glass s...@chromium.org wrote:
On Tue, Mar 5, 2013 at 9:04 PM, Kim Phillips kim.phill...@freescale.com
wrote:
On Tue, 5 Mar 2013 17:51:00 -0800
Simon Glass s...@chromium.org wrote:
[snip for Kim]
and others too, I hope.
Changes sice v3:
- Changed command names to lower case in algo struct.
- Added generic ace_sha config.
I wouldn't call ace a generic name - crypto units other than
ACE should be able to use this code.
I don't really understand this comment. A new CONFIG has been added,
and this is specific to that unit. Are you suggesting that it be
right, and that's the problem - it needn't be specific to that unit.
Really? I think here we have a patch for an ACE unit, and currently
the only implementation is in an Exynos chip. It can easily be
so make the ace_sha.o build depend on whichever level of chip config
applies - CONFIG_S5P, CONFIG_EXYNOS5, or CONFIG_SMDK5250. No need
for a new define specifically for ACE, right?
extended later when someone else has one.
maybe, but we can try to avoid people copying existing code patterns,
i.e. polluting common code when adding crypto routines for their h/w
which are basically the same function declarations but with different
names.
CONFIG_EXYNOS_ACE_SHA? Will the ACE unit not appear on any other SOC?
my point is other SoCs can use the same entry in the array - there's
nothing h/w-vendor or model-specific about it.
OK, know you of such an SOC?
I'm not familiar with Samsung crypto products, and I can't become
familiar either, judging by the state of their public
documentation (if a company doesn't make their crypto unit
documentation public, that only has to mean something's insecure -
and not just through obscurity :).
A large majority of Freescale's PowerQUICC QorIQ chips
have crypto units. A lot of them have crypto as an option, so
discovery has to be done at runtime (but we can add that
later).
The primary objective here is to not add h/w vendor dependencies in
common areas when they can easily be avoided.
Something like CONFIG_HW_SHA{1,256} ought to do it.
But I don't think crypto units other than ACE will use the code in
this patch - it is intended to implement ACE support, and put it ahead
of software support in terms of priority.
the same priority that any h/w accelerated device would get - higher
than that of software crypto.
Another question for Akshay wrt the timeout (since I never got a
reply re: documentation): how can the h/w fault?
Kim
oh, and please stop full-quoting - I'm tired of looking at my
scrollbar go by with no inline content.
I will try harder. You could look at trying another mailer :-)
Thanks, I appreciate it. Gmail? just more clicking, no?
Kim
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Re: [U-Boot] [PATCH 3/4 v5] gen: Add ACE acceleration to hash
On Wed, 6 Mar 2013 09:18:55 -0500 Akshay Saraswat aksha...@samsung.com wrote: ACE H/W acceleration support is added to hash which can be used to test SHA 256 hash algorithm. Signed-off-by: ARUN MANKUZHI aru...@samsung.com Signed-off-by: Akshay Saraswat aksha...@samsung.com --- this doesn't even apply any more: Applying: gen: Add ACE acceleration to hash error: patch failed: common/hash.c:28 error: common/hash.c: patch does not apply Patch failed at 0001 gen: Add ACE acceleration to hash Kim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/5 v4] gen: Add ACE acceleration to hash
On Wed, 6 Mar 2013 10:29:46 -0500
Akshay Saraswat aksha...@samsung.com wrote:
I have removed tested with in the new set of patches. And I tested those
patches with that command
before mailing for review. I have tested them for various sizes this time
which includes 8 MB as well.
I have shared benchmark results in another mail.
thanks - the threshold looks good (although the two largest sizes
looked a bit too close).
my point is other SoCs can use the same entry in the array - there's
nothing h/w-vendor or model-specific about it.
Something like CONFIG_HW_SHA{1,256} ought to do it.
These instances of struct algo were created specifically for ace because
we need function name different for ace to distinguish it from others.
Hence, config name includes ace as well.
no you don't, because no u-boot instance will contain support
for others. SoC vendors don't put more than one crypto unit in
their parts.
But I don't think crypto units other than ACE will use the code in
this patch - it is intended to implement ACE support, and put it ahead
of software support in terms of priority.
the same priority that any h/w accelerated device would get - higher
than that of software crypto.
Another question for Akshay wrt the timeout (since I never got a
reply re: documentation): how can the h/w fault?
Regarding documentation, I have replied to that mail itself. Sorry for the
delay.
Since it is obvious that in case of h/w fault all readl and writel's would
result
incorrectly and since we know that status register should change it's value
quickly,
we have a good option to depend upon 100 ms as the time more than enough for
wait.
And I tried to handle our concern over frequency change and early timeout
with the proportional timeout calculation in the new patch. Please have a
look.
I don't understand this - the question is whether the h/w can
possibly experience an internal failure from submission time to
result ready time.
Kim
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Re: [U-Boot] [PATCH 4/5 v4] gen: Add ACE acceleration to hash
Hi Kim,
On Wed, Mar 6, 2013 at 5:22 PM, Kim Phillips kim.phill...@freescale.com wrote:
On Tue, 5 Mar 2013 22:22:09 -0800
Simon Glass s...@chromium.org wrote:
On Tue, Mar 5, 2013 at 9:04 PM, Kim Phillips kim.phill...@freescale.com
wrote:
On Tue, 5 Mar 2013 17:51:00 -0800
Simon Glass s...@chromium.org wrote:
[snip for Kim]
and others too, I hope.
Changes sice v3:
- Changed command names to lower case in algo struct.
- Added generic ace_sha config.
I wouldn't call ace a generic name - crypto units other than
ACE should be able to use this code.
I don't really understand this comment. A new CONFIG has been added,
and this is specific to that unit. Are you suggesting that it be
right, and that's the problem - it needn't be specific to that unit.
Really? I think here we have a patch for an ACE unit, and currently
the only implementation is in an Exynos chip. It can easily be
so make the ace_sha.o build depend on whichever level of chip config
applies - CONFIG_S5P, CONFIG_EXYNOS5, or CONFIG_SMDK5250. No need
for a new define specifically for ACE, right?
No, the ACE may appear in multiple chips, and anyway we may want to
enable it or disable it. Drivers tend to have their own configs since
some boards want to use (for example) USB, crypto, mmc, and some
don't.
extended later when someone else has one.
maybe, but we can try to avoid people copying existing code patterns,
i.e. polluting common code when adding crypto routines for their h/w
which are basically the same function declarations but with different
names.
Are you referring to adding code in into the hash algorithm table in
hash.c? I specifically designed it so that people could add their
algorithms in there. Once we have device model in place then I'm sure
we can do better, but for now that's the U-Boot way.
CONFIG_EXYNOS_ACE_SHA? Will the ACE unit not appear on any other SOC?
my point is other SoCs can use the same entry in the array - there's
nothing h/w-vendor or model-specific about it.
OK, know you of such an SOC?
I'm not familiar with Samsung crypto products, and I can't become
familiar either, judging by the state of their public
documentation (if a company doesn't make their crypto unit
documentation public, that only has to mean something's insecure -
and not just through obscurity :).
A large majority of Freescale's PowerQUICC QorIQ chips
have crypto units. A lot of them have crypto as an option, so
discovery has to be done at runtime (but we can add that
later).
The primary objective here is to not add h/w vendor dependencies in
common areas when they can easily be avoided.
Please can you point specifically to the lines of code you are wanting changed?
Something like CONFIG_HW_SHA{1,256} ought to do it.
But I don't think crypto units other than ACE will use the code in
this patch - it is intended to implement ACE support, and put it ahead
of software support in terms of priority.
the same priority that any h/w accelerated device would get - higher
than that of software crypto.
Another question for Akshay wrt the timeout (since I never got a
reply re: documentation): how can the h/w fault?
[...]
Regards,
Simon
Kim
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Re: [U-Boot] [PATCH v6 07/31] Define CONFIG_SYS_LEGACY_BOARD everywhere
Dear Simon Glass, In message 1362530405-10824-8-git-send-email-...@chromium.org you wrote: We are introducing a new unified board setup and we want this to be the default. So we need to opt all architectures out first. ... +- CONFIG_SYS_GENERIC_BOARD ... +CONFIG_SYS_LEGACY_BOARD := y Documentation and code mismatch: subject talks about CONFIG_SYS_LEGACY_BOARD, and this is what I also see in the code, but in the README you add a description for CONFIG_SYS_GENERIC_BOARD, but none for CONFIG_SYS_LEGACY_BOARD Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de I believe you find life such a problem because you think there are the good people and the bad people. You're wrong, of course. There are, always and only, the bad people, but some of them are on oppo- site sides. - Terry Pratchett, _Guards! Guards!_ ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mtdparts not agreeing wiht fw_printenv
Dear John Stile, In message 1362532855.20183.135.camel@genx you wrote: I am quite confused about partitions in my NAND flash. Linux can mount my rootfs, so partitions make sense to the kernel, but from the shell fw_printenv can't read the uboot environment, not matter what I use in /etc/fw_env.config. That means that all settings were incorrect. dev:size erasesize name mtd0: 0002 0002 bootstrap1 mtd1: 0004 0002 uboot1 mtd2: 001a 0002 env1 ^^ mtd2 mtd3: 0020 0002 linux1 mtd4: 07c0 0002 rootfs1 mtd5: 0002 0002 bootstrap2 mtd6: 0004 0002 uboot2 mtd7: 001a 0002 env2 ^^ mtd7 mtd8: 0020 0002 linux2 mtd9: 07c0 0002 rootfs2 mtd10: 4200 0420 bootstrap3 mtd11: 4200 0420 env3 ^^ mtd11 mtd12: 00039c00 0420 uboot3 mtd13: 00252000 0420 linux3 mtd14: 005ac000 0420 rootfs3 What's that? This makes no sense to me - either you have a single copy of the environment, or two (in case of redudant env). Three copies is not a supported configuration. I purposefully created more /dev/mtd devices than mtdparts would require, in order to find which partitions actually contain the uboot env. mtdparts does not require anything. You configure your systems as needed, and then set mtdparts to match that setting. SO the setting comes first (starting in your head or - probably better - on a sheet of paper), and then you set mtdparts as needed. /dev/mtd4 and /dev/mtd5 create binary equivalent dumps of env1 /dev/mtd14 and /dev/mtd15 create binary equivalent dumps of env2. The names and use of your partitions is in serious mismatch. Fix this first! /etc/fw_env.config does not like either of those, saying the crc does not checkout. /etc/fw_env.config: /dev/mtd2 0x0 0x2 0x2 /dev/mtd2 0x2 0x2 0x2 Well, if you find the environment in /dev/mtd4 and /dev/mtd5, then you should use these in the fw_env.config Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Making files is easy under the UNIX operating system. Therefore, users tend to create numerous files using large amounts of file space. It has been said that the only standard thing about all UNIX systems is the message-of-the-day telling users to clean up their files. - System V.2 administrator's guide ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v9 15/30] autoconfig.mk: Make it possible to define configs from other configs
Dear Benoît Thébaudeau, In message 1362596377-5827-15-git-send-email-benoit.thebaud...@advansee.com you wrote: + # ... and from configs defined from other configs + s/=\(CONFIG_[A-Za-z0-9_][A-Za-z0-9_]*\)/=$(\1)/; Should we not remove the lower case letters here? Such are not supposed to be used in macro names. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de If all you have is a hammer, everything looks like a nail. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
