Re: [U-Boot] [PATCH] powerpc/ppc4xx: Convert new gdsys files to SPDX license tags
Hi Tom, On 07/26/2013 09:34 PM, Tom Rini wrote: Signed-off-by: Tom Rini tr...@ti.com --- board/gdsys/common/dp501.c | 18 +- board/gdsys/common/fpga.c | 18 +- board/gdsys/common/mclink.c | 18 +- board/gdsys/common/mclink.h | 18 +- common/cmd_fpgad.c | 18 +- 5 files changed, 5 insertions(+), 85 deletions(-) Ah, sorry. I missed those. Will you apply this patch directly or should I send a pull-request? Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Is it permissible to link stubs.o to a standalone application?
Hello, We have made a small build called fpga_loader using 'standalone' approach provided by u-boot, it works well after running 'go' command. Please first refer this http://u-boot.10912.n7.nabble.com/U-Boot-How-to-get-GPL-free-standalone-programs-with-u-boot-td42180.html We need to leave the fpga_loader build GPL free. So we include ' exports.h' which is in u-boot 'allowed' file list in our main.c, but the way we using ' examples/standalone/stubs.c' is a little different. Unlike ' examples/standalone/hello_world.c ', our build is compiled outside u-boot using another make system, so we link 'stubs.o', which is generated by u-boot in advance, to our build. According to the upper link, using of ' examples/standalone/stubs.c' is allowed. But I'm not sure whether the use of 'stubs.o' is allowed. So, is it permissible to link ' examples/standalone/stubs.o' to an outside build? Thanks! Best Regards, Bai Yingjie ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/9] arm926ej-s: Invalidate instruction cache in flush_cache
(although this patch is more than two *years* old, it never got properly answered to. I am doing so here to make sure future readers know why it was not applied and won't be.) Hi Michael, On Thu, 17 Mar 2011 15:46:55 -0400, Michael Spang msp...@csclub.uwaterloo.ca wrote: If U-Boot is loaded from RAM and the OS is loaded into an overlapping region, the instruction cache is not coherent when that OS is started. We must therefore invalidate the instruction cache in addition to cleaning the data cache. Signed-off-by: Michael Spang msp...@csclub.uwaterloo.ca --- arch/arm/lib/cache.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 30686fe..047786a 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -37,6 +37,8 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2) asm(0: mrc p15, 0, r15, c7, c10, 3\n\t bne 0b\n : : : memory); /* disable write buffer as well (page 2-22) */ asm(mcr p15, 0, %0, c7, c10, 4 : : r (0)); + /* invalidate icache for coherence with cleaned dcache */ + asm(mcr p15, 0, %0, c7, c5, 0 : : r (0)); #endif #ifdef CONFIG_OMAP34XX void v7_flush_cache_all(void); This patch has obviously not been applied, and won't be, because of two reasons: i) overwriting part of U-Boot when loading the kernel is a bug which should not be papered over, and ii) if we had to do this anyway, the right place to do it would have been where the issue might occur, that is, in the OS boot sequence, not in the cache handling functions. Apologies for not properly answering in due time. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] OpenRD: relocate environment to 640kB
Hi Sascha, On Mon, 15 Jul 2013 08:19:57 -0400, Tom Rini tr...@ti.com wrote: On Mon, Jul 15, 2013 at 11:23:54AM +0200, Sascha Silbe wrote: Albert ARIBAUD albert.u.b...@aribaud.net writes: The situation has gotten better recently and U-Boot fits into the previous partition size of 384KiB again. So it isn't broken on OpenRD anymore and the above would seem like a good approach. How well does it fit again, and do you have any idea what caused the increase in size, and what caused the decrease? I had the same questions and tried a few buildman runs, but didn't get a clear picture. The size was going up and down for various slices of commits. With v2013.07-rc3, we are now at 376344B (??? 96% of 384KiB) for openrd_ultimate when built on Debian Wheezy using gcc-4.7-arm-linux-gnueabi from Emdebian. Is there an equivalent to CONFIG_SPL_MAX_SIZE for the regular U-Boot? Detecting the overlap at build time would prevent bricking the device using saveenv at run time. As an additional benefit, commits that push the size beyond the limit would also show up in buildman reports as build failures. Yes, you can try using CONFIG_BOARD_SIZE_LIMIT, which is missing from the README, but does have a few examples (git grep around). A patch to document it, and then a patch to enable for openrd would be much appreciated. Thanks! Sascha, does this mean the env relocate patch here is dropped in favor of a CONFIG_BOARD_SIZE_LIMIT check at build time? Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] uboot optimize memmove
Dear Andy Green, In message CAAfg0W4wXdRafRcHvrNVNnkCGd3EvJfNujuzUsjQXgW=wmc...@mail.gmail.com you wrote: Given that code should perferably never be used, maybe it should print a warning like Using default memory ops and leave it like it is. The problem is not correctness just inefficiency. Agreed. You found a problem, and a way to improve it. All this is perfectly fine. I just didn't like your implementation, and rather suggest to copy the 32-bit-copy loop as used in the current memcpy() code and use it also in memmove(). I'm looking forward to seeing your patch v2 with such an improved implementation. Thanks in advance. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de The biggest difference between time and space is that you can't reuse time. - Merrick Furst ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 1/4] mx27: add missing constant for mx27
On 28/07/2013 22:16, Philippe Reynes wrote:
Add some missing constant (chip select, ...)
Signed-off-by: Philippe Reynes trem...@yahoo.fr
Signed-off-by: Eric Jarrige eric.jarr...@armadeus.org
---
arch/arm/cpu/arm926ejs/mx27/asm-offsets.c |5 +
arch/arm/include/asm/arch-mx27/imx-regs.h |2 +-
2 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
index f3a8d7b..215c562 100644
--- a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
+++ b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
@@ -41,5 +41,10 @@ int main(void)
DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
+ DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
+ offsetof(struct system_control_regs, gpcr));
+ DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
+ offsetof(struct system_control_regs, fmcr));
+
return 0;
}
diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h
b/arch/arm/include/asm/arch-mx27/imx-regs.h
index 8867e9f..51257a8 100644
--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
@@ -185,7 +185,7 @@ struct iim_regs {
struct fuse_bank {
u32 fuse_regs[0x20];
u32 fuse_rsvd[0xe0];
- } bank[1];
+ } bank[2];
};
struct fuse_bank0_regs {
Acked-by: Stefano Babic sba...@denx.de
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=
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Re: [U-Boot] [PATCH] uboot optimize memmove
On 26.07.2013 15:42, Andy Green wrote: On 26 July 2013 20:58, Wolfgang Denk w...@denx.de wrote: ... you not make sure that you provide optimized implementations for such functions and consequently #define __HAVE_ARCH_MEMMOVE (and __HAVE_ARCH_MEMCPY) ? Yes I found these afterwards... performance is slightly better than memcpy() thanks to Nicolas Pitre it seems. The U-Boot config for the platform we have didn't know about them, it's much better with them. After I wrote this patch it was also pointed out by Will Newton at Linaro that we have Neon accelerated memcpy lying around with BSD license https://launchpad.net/cortex-strings however for my purposes NOR boot is working good enough with the ARCH versions. I've had a look to https://launchpad.net/cortex-strings and there downloaded https://launchpad.net/cortex-strings/trunk/2013.01/+download/cortex-strings-1.0-2013.01.tar.bz2 (from the green download button on the right side). The README mentions src/neon contains NEON based routines for AArch32. but the cortex-strings-1.0-2013.01.tar.bz2 seems to contain an empty src/neon directory. Is this intended? Best regards Dirk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] uboot optimize memmove
Looping Will... On 29 July 2013 16:28, Dirk Behme dirk.be...@de.bosch.com wrote: On 26.07.2013 15:42, Andy Green wrote: On 26 July 2013 20:58, Wolfgang Denk w...@denx.de wrote: ... you not make sure that you provide optimized implementations for such functions and consequently #define __HAVE_ARCH_MEMMOVE (and __HAVE_ARCH_MEMCPY) ? Yes I found these afterwards... performance is slightly better than memcpy() thanks to Nicolas Pitre it seems. The U-Boot config for the platform we have didn't know about them, it's much better with them. After I wrote this patch it was also pointed out by Will Newton at Linaro that we have Neon accelerated memcpy lying around with BSD license https://launchpad.net/cortex-strings however for my purposes NOR boot is working good enough with the ARCH versions. I've had a look to https://launchpad.net/cortex-strings and there downloaded https://launchpad.net/cortex-strings/trunk/2013.01/+download/cortex-strings-1.0-2013.01.tar.bz2 (from the green download button on the right side). The README mentions src/neon contains NEON based routines for AArch32. but the cortex-strings-1.0-2013.01.tar.bz2 seems to contain an empty src/neon directory. Is this intended? I don't know... I agree that dir is empty... Will, do you know the story? I found nice-looking ones in reference/newlib but I don't think they're NEON. -Andy Best regards Dirk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] gpio: altera_pio: Fix inversed logic of gpio_is_valid() implementation
Hi Axel, On Sat, 15 Jun 2013 17:10:38 +0800, Axel Lin axel@ingics.com wrote: The implementation of gpio_is_valid() has inversed logic, fix it. Signed-off-by: Axel Lin axel@ingics.com --- Hi, I don't have this hardware to test, but current code looks obviously wrong. I'd appreciate if someone can review and test this patch. Axel drivers/gpio/altera_pio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Not sure why this was assigned to me, as this is not ARM related. Delegating to Thomas Chou as the NIOS(II) custodian and Cc:ing him, as well as Scott McNutt, nios2-generic maintainer. diff --git a/drivers/gpio/altera_pio.c b/drivers/gpio/altera_pio.c index fb03760..7ab6df8 100644 --- a/drivers/gpio/altera_pio.c +++ b/drivers/gpio/altera_pio.c @@ -294,6 +294,6 @@ int gpio_is_valid(int number) int gidx = altera_pio_gidx(number); if (gidx 0) - return 1; - return 0; + return 0; + return 1; } Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] mxc_ipuv3: fix memory alignment of framebuffer
On 27/07/2013 02:53, Eric Nelson wrote: The frame-buffer on i.MX boards needs to be aligned for DMA. Signed-off-by: Eric Nelson eric.nel...@boundarydevices.com --- Applied to u-boot-imx, thanks. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] uboot optimize memmove
On 29 July 2013 09:44, Andy Green andy.gr...@linaro.org wrote: Looping Will... On 29 July 2013 16:28, Dirk Behme dirk.be...@de.bosch.com wrote: On 26.07.2013 15:42, Andy Green wrote: On 26 July 2013 20:58, Wolfgang Denk w...@denx.de wrote: ... you not make sure that you provide optimized implementations for such functions and consequently #define __HAVE_ARCH_MEMMOVE (and __HAVE_ARCH_MEMCPY) ? Yes I found these afterwards... performance is slightly better than memcpy() thanks to Nicolas Pitre it seems. The U-Boot config for the platform we have didn't know about them, it's much better with them. After I wrote this patch it was also pointed out by Will Newton at Linaro that we have Neon accelerated memcpy lying around with BSD license https://launchpad.net/cortex-strings however for my purposes NOR boot is working good enough with the ARCH versions. I've had a look to https://launchpad.net/cortex-strings and there downloaded https://launchpad.net/cortex-strings/trunk/2013.01/+download/cortex-strings-1.0-2013.01.tar.bz2 (from the green download button on the right side). The README mentions src/neon contains NEON based routines for AArch32. but the cortex-strings-1.0-2013.01.tar.bz2 seems to contain an empty src/neon directory. Is this intended? I don't know... I agree that dir is empty... Will, do you know the story? I found nice-looking ones in reference/newlib but I don't think they're NEON. The fast memcpy code is in src/linaro-a9/memcpy.S. The directory structure pre-dates my involvement with the project so I cannot explain it completely. ;-) -- Will Newton Toolchain Working Group, Linaro ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/2] usb bug fixes
This series contains two usb related bug fixes, one regarding the power cycling of hub ports, and the other- a memory leak in ehci-hcd. Cc: Marek Vasut ma...@denx.de Cc: Igor Grinberg grinb...@compulab.co.il Nikita Kiryanov (2): usb_hub: fix power cycling logic ehci-hcd: fix memory leak in lowlevel init common/usb_hub.c| 4 ++-- drivers/usb/host/ehci-hcd.c | 4 +++- 2 files changed, 5 insertions(+), 3 deletions(-) -- 1.8.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] usb_hub: fix power cycling logic
When power cycling the hub ports, a misbehaving port will prevent all ports
from being powered on because we quit at the first sign of trouble.
Skip problematic ports instead of failing the entire power on.
Cc: Marek Vasut ma...@denx.de
Cc: Igor Grinberg grinb...@compulab.co.il
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
common/usb_hub.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/usb_hub.c b/common/usb_hub.c
index 754d436..a11b401 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -110,7 +110,7 @@ static void usb_hub_power_on(struct usb_hub_device *hub)
ret = usb_get_port_status(dev, i + 1, portsts);
if (ret 0) {
debug(port %d: get_port_status failed\n, i + 1);
- return;
+ continue;
}
/*
@@ -125,7 +125,7 @@ static void usb_hub_power_on(struct usb_hub_device *hub)
portstatus = le16_to_cpu(portsts-wPortStatus);
if (portstatus (USB_PORT_STAT_POWER 1)) {
debug(port %d: Port power change failed\n, i + 1);
- return;
+ continue;
}
}
--
1.8.1.2
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[U-Boot] [PATCH 2/2] ehci-hcd: fix memory leak in lowlevel init
usb_lowlevel_init() allocates a new periodic_list each time it is invoked,
without freeing the original list. Since it is initialized later on in the code,
just reuse the first-allocated list in future invocations of usb_lowlevel_init.
Cc: Marek Vasut ma...@denx.de
Cc: Igor Grinberg grinb...@compulab.co.il
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
drivers/usb/host/ehci-hcd.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 706cf0c..eab1046 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -954,7 +954,9 @@ int usb_lowlevel_init(int index, void **controller)
* Split Transactions will be spread across microframes using
* S-mask and C-mask.
*/
- ehcic[index].periodic_list = memalign(4096, 1024*4);
+ if (ehcic[index].periodic_list == NULL)
+ ehcic[index].periodic_list = memalign(4096, 1024 * 4);
+
if (!ehcic[index].periodic_list)
return -ENOMEM;
for (i = 0; i 1024; i++) {
--
1.8.1.2
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[U-Boot] Falcon Mode implemented version
Hi all, I have the following queries. 1) Can anyone suggest me the exact version of u-boot in which falcon mode is implemented? I also wanted to know, if is there any readme available for that implementation. Please also tell me, where exactly in the u-boot code it is implemented. 2) The u-boot version in which SPL for NOR flash is implemented. If no such version is available, then please tell me about the patch in which this SPL for NOR flash is implemented. Thanks in advance. Regards, Rajdeep Vaghasia. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Falcon Mode implemented version
Hi Rajdeep, On 29/07/2013 14:04, Rajdeep Vaghasia wrote: Hi all, I have the following queries. 1) Can anyone suggest me the exact version of u-boot in which falcon mode is implemented? There is no exact version - falcon mode was merged more as one year ago. Take simply 2013.07 or u-boot TOT. I also wanted to know, if is there any readme available for that implementation. doc/README.falcon Please also tell me, where exactly in the u-boot code it is implemented. There is no exact the code - to speed up the boot, several parts were changed. You can check for code surrounded by CONFIG_CMD_SPL and CONFIG_SPL_OS_BOOT. 2) The u-boot version in which SPL for NOR flash is implemented. There is at least a couple of boards supporting SPL and booting form NOR: woodburn (MX35) and a3m071(MPC 5200). Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/ppc4xx: Convert new gdsys files to SPDX license tags
On Mon, Jul 29, 2013 at 08:14:19AM +0200, Stefan Roese wrote: Hi Tom, On 07/26/2013 09:34 PM, Tom Rini wrote: Signed-off-by: Tom Rini tr...@ti.com --- board/gdsys/common/dp501.c | 18 +- board/gdsys/common/fpga.c | 18 +- board/gdsys/common/mclink.c | 18 +- board/gdsys/common/mclink.h | 18 +- common/cmd_fpgad.c | 18 +- 5 files changed, 5 insertions(+), 85 deletions(-) Ah, sorry. I missed those. Will you apply this patch directly or should I send a pull-request? Applied directly so we're good. Thanks. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3 v2] arm, am335x: add watchdog support
On Mon, Jul 29, 2013 at 06:58:05AM +0200, Heiko Schocher wrote: Add TI OMAP 16xx 24xx/34xx 32KHz (non-secure) watchdog support. Signed-off-by: Heiko Schocher h...@denx.de Reviewed-by: Tom Rini tr...@ti.com Cc: Albert Aribaud albert.u.b...@aribaud.net [snip] +++ b/drivers/watchdog/omap_wdt.c @@ -0,0 +1,112 @@ +/* + * omap_wdt.c + * + * (C) Copyright 2013 + * Heiko Schocher, DENX Software Engineering, h...@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Based on: + * + * Watchdog driver for the TI OMAP 16xx 24xx/34xx 32KHz (non-secure) watchdog + * + * Author: MontaVista Software, Inc. + *gda...@mvista.com or sou...@mvista.com + * + * History: + * + * 20030527: George G. Davis gda...@mvista.com + * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c So this is clearly based on the kernel, so we can't go adding our own plus and this is just GPL-2.0. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] SPDX-License-Identifier: adding a comment section?
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 07/28/2013 11:40 AM, Wolfgang Denk wrote: Hello all, I need some help / recommendations how we should handle non-trivial license issues. For example, please have a look at the NE2000 network driver code: drivers/net/ne2000.h drivers/net/ne2000.c drivers/net/ne2000_base.h drivers/net/ne2000_base.c - First, these files include a statement that this code has been derived from Linux kernel and from eCOS sources and that it's released unter GPL, but without stating wehter this means GPL-v2 or GPL-v2+ or whatever. - Second, it includes the eCOS license header which basically says it's GPLv2+ plus some additional rights. - Third, if you track down the Linux source code mentioned above, this again says only GPL without additional specification. Two questions arise: - What should the resulting license(s) be in this specific case? I tend to interpret plain GPL as GPLv2+, so we could probably summarize the license terms here as eCos-2.0. What do you think? I grabbed (because of the omap watchdog patch) 2.4.17, and that's (a) older than our ne2k driver and (b) Already a GPLv2 and not 'or later'. This is, I think, GPL-2.0. - I feel it would be helpful for future investigations if we are able to document our current understanding, so we don't have to re-investigate all this again and again each time we run into these files. My proposal is to define an additional magic string SPDX-License-Comments: which could be used to mark a text section that would contain such explanations. Wound this make sense, or do you have a better suggestion? Sounds good. In this case we would say something like Linux Kernel driver and eCos driver files both used as reference. - -- Tom -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQIcBAEBAgAGBQJR9majAAoJENk4IS6UOR1WCFEQAIDnb0TRvv1SL30MQVWkfRG7 oas1HQPBpLX0MUAt5M7NBHSh9KLgl/GA5aHX7CsgAUh0i7x2oO00x0wUdH59HEbV UyJN0QbbYXmlceTXJzIEYP+GALzLtyg3GYE8JBwYOV3r5KV0askqlDoxq6A0354J BjgfEc+GYyBiik1fHvAm64yAHOTd/m02WLYmHA+eNpNvYqrjlOmXI5/Kll6PJ28b YAT4Jn7PY1rwxrFEVbDSWqq0ZsorkJDgpVjB4iwetGSJjS/Ov39kfDT3x8W7qXI8 5R9DzzIvhy80YXY54EUCFt2RvClJJd5uOa4SxTz9SfpI76KpSSzj8qq0hkFyXyOg eRwcsTZUTnfSeNDu9IKV2SrxSDFdMWb58pej0fjkoxKvi2ID+8wuA0GJ/sS04IRo reA7PlRPElc/e0YtsH87487qwNoRf8Bu11T98+QAbLLew6LBdSYKJlif114z+agY 1qzsb9KuC4gkSJYDLdY4pAxmu89GQXrpwAzIT5/mhv0fCmGxXo3HB5TmSxPpMHB+ MlzaBreZozaER7e9WhLpJ52XQK3w4t4C3VPMvz5onVekSs9NEBgf1OgRsYAdep96 dWJKGFpCle75MAs03jE0T8i7AquMpSx94MnsVJ2tJIxEQ6HRMFxg/Ux7IONvzRCa fxRXJ0SYcg3JdFqRYvO0 =oO+C -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3 v2] arm, am335x: add watchdog support
Hello Tom, Am 29.07.2013 14:39, schrieb Tom Rini: On Mon, Jul 29, 2013 at 06:58:05AM +0200, Heiko Schocher wrote: Add TI OMAP 16xx 24xx/34xx 32KHz (non-secure) watchdog support. Signed-off-by: Heiko Schocherh...@denx.de Reviewed-by: Tom Rinitr...@ti.com Cc: Albert Aribaudalbert.u.b...@aribaud.net [snip] +++ b/drivers/watchdog/omap_wdt.c @@ -0,0 +1,112 @@ +/* + * omap_wdt.c + * + * (C) Copyright 2013 + * Heiko Schocher, DENX Software Engineering, h...@denx.de. + * + * SPDX-License-Identifier:GPL-2.0+ + * + * Based on: + * + * Watchdog driver for the TI OMAP 16xx 24xx/34xx 32KHz (non-secure) watchdog + * + * Author: MontaVista Software, Inc. + * gda...@mvista.com orsou...@mvista.com + * + * History: + * + * 20030527: George G. Davisgda...@mvista.com + * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c So this is clearly based on the kernel, so we can't go adding our own plus and this is just GPL-2.0. Yes, you are right, sorry for that, simple copypaste error. I wrote an EMail to the owner of the linux driver if GPL-2.0+ is OK, or if we should leave it GPL-2.0 in u-boot. Thanks! bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3 v2] arm, am335x: add watchdog support
On Mon, Jul 29, 2013 at 03:06:00PM +0200, Heiko Schocher wrote: Hello Tom, Am 29.07.2013 14:39, schrieb Tom Rini: On Mon, Jul 29, 2013 at 06:58:05AM +0200, Heiko Schocher wrote: Add TI OMAP 16xx 24xx/34xx 32KHz (non-secure) watchdog support. Signed-off-by: Heiko Schocherh...@denx.de Reviewed-by: Tom Rinitr...@ti.com Cc: Albert Aribaudalbert.u.b...@aribaud.net [snip] +++ b/drivers/watchdog/omap_wdt.c @@ -0,0 +1,112 @@ +/* + * omap_wdt.c + * + * (C) Copyright 2013 + * Heiko Schocher, DENX Software Engineering, h...@denx.de. + * + * SPDX-License-Identifier:GPL-2.0+ + * + * Based on: + * + * Watchdog driver for the TI OMAP 16xx 24xx/34xx 32KHz (non-secure) watchdog + * + * Author: MontaVista Software, Inc. + * gda...@mvista.com orsou...@mvista.com + * + * History: + * + * 20030527: George G. Davisgda...@mvista.com + * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c So this is clearly based on the kernel, so we can't go adding our own plus and this is just GPL-2.0. Yes, you are right, sorry for that, simple copypaste error. I wrote an EMail to the owner of the linux driver if GPL-2.0+ is OK, or if we should leave it GPL-2.0 in u-boot. George's code is based on someone elses, based on ... So lets just leave it as GPL-2.0. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/9] arm926ej-s: Invalidate instruction cache in flush_cache
Hi Michael, On Mon, 29 Jul 2013 08:57:53 -0400, Michael Spang msp...@csclub.uwaterloo.ca wrote: Albert, That's not a correct characterization of the bug. The incoherent cache lines are from before the relocation stage. If U-Boot is relocating from RAM, and later copies the OS there without invalidating those lines, then that's a bug in U-Boot. Thanks for this pointing out this scenario, which is correct, although it was not raised in the original bug description. I begs however the question whether anything from re-relocation can survive in the icache from between the moment the relocation starts and the moment the OS is given transfer to. IOW, was this issue actually met? Anyway I stand by my statement that even if there is an issue to fix, this patch fixes it in the wrong place. Michael Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/9] arm926ej-s: Invalidate instruction cache in flush_cache
Albert, That's not a correct characterization of the bug. The incoherent cache lines are from before the relocation stage. If U-Boot is relocating from RAM, and later copies the OS there without invalidating those lines, then that's a bug in U-Boot. Michael On Mon, Jul 29, 2013 at 3:19 AM, Albert ARIBAUD albert.u.b...@aribaud.net wrote: (although this patch is more than two *years* old, it never got properly answered to. I am doing so here to make sure future readers know why it was not applied and won't be.) Hi Michael, On Thu, 17 Mar 2011 15:46:55 -0400, Michael Spang msp...@csclub.uwaterloo.ca wrote: If U-Boot is loaded from RAM and the OS is loaded into an overlapping region, the instruction cache is not coherent when that OS is started. We must therefore invalidate the instruction cache in addition to cleaning the data cache. Signed-off-by: Michael Spang msp...@csclub.uwaterloo.ca --- arch/arm/lib/cache.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 30686fe..047786a 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -37,6 +37,8 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2) asm(0: mrc p15, 0, r15, c7, c10, 3\n\t bne 0b\n : : : memory); /* disable write buffer as well (page 2-22) */ asm(mcr p15, 0, %0, c7, c10, 4 : : r (0)); + /* invalidate icache for coherence with cleaned dcache */ + asm(mcr p15, 0, %0, c7, c5, 0 : : r (0)); #endif #ifdef CONFIG_OMAP34XX void v7_flush_cache_all(void); This patch has obviously not been applied, and won't be, because of two reasons: i) overwriting part of U-Boot when loading the kernel is a bug which should not be papered over, and ii) if we had to do this anyway, the right place to do it would have been where the issue might occur, that is, in the OS boot sequence, not in the cache handling functions. Apologies for not properly answering in due time. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/9] arm926ej-s: Invalidate instruction cache in flush_cache
On Mon, Jul 29, 2013 at 10:09 AM, Albert ARIBAUD albert.u.b...@aribaud.net wrote: Hi Michael, On Mon, 29 Jul 2013 08:57:53 -0400, Michael Spang msp...@csclub.uwaterloo.ca wrote: Albert, That's not a correct characterization of the bug. The incoherent cache lines are from before the relocation stage. If U-Boot is relocating from RAM, and later copies the OS there without invalidating those lines, then that's a bug in U-Boot. Thanks for this pointing out this scenario, which is correct, although it was not raised in the original bug description. I begs however the question whether anything from re-relocation can survive in the icache from between the moment the relocation starts and the moment the OS is given transfer to. IOW, was this issue actually met? Yes, I had boot failures without this patch on the device I was porting to (TS-7800). It happened consistently. Anyway I stand by my statement that even if there is an issue to fix, this patch fixes it in the wrong place. Ok, that's fair. I was hoping to repost this series someday and will take that into account. Michael ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Query: Ethernet switch support
Hi List, I am trying to add support of a Vitesse L2 switch in u-boot (in unmanaged configuration). I was analyzing whether advanced features like flow control, link-aggregation etc are required to be supported for a L2 switch working in a u-boot bootloader level. My point-of-view is that the L2 switch, should support only bare-minimum tftp of images, ping to other ethernet entities, bootp .. type of commands on u-boot and as such the L2 switch u-boot driver doesn't need to address flow-control and other such advanced features (probably of interest for a Linux device driver). But, I am not sure about the design approaches used to support previous switch modules in u-boot. Also I had a query whether there is a common switch framework in-place/under-consideration in u-boot, similar to what is already present in OpenWrt code: https://dev.openwrt.org/browser/trunk/package/boot/uboot-lantiq/patches/0019-net-switchlib-add-framework-for-ethernet-switch-driv.patch?rev=35292 Would porting this to u-boot make sense to have a common framework for ethernet switch in-place? Can you please let me know your views on the same and point me to any reference switch drivers that support these features. Regards, Bhupesh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/5] sf: Add support for accessing dual stacked memories
This patch added support for accessing dual memories in
stacked connections with single chipselect line from controller.
this connection mode is implemented in xilinx zynq qspi controller.
For more info, see doc/README.spi-flash-conn-modes
Below are the changes for dual stacked to work:
- mtd layer - sector_size*2, update the U_PAGE flag
when memory change happen.
- driver - on LQSPI_CFG, Enable TWO_MEM[BIT:30] on LQSPI_CFG
Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
doc/README.spi-flash-conn-modes | 36
drivers/mtd/spi/spi_flash.c | 30 --
include/spi.h | 3 +++
include/spi_flash.h | 1 +
4 files changed, 68 insertions(+), 2 deletions(-)
diff --git a/doc/README.spi-flash-conn-modes b/doc/README.spi-flash-conn-modes
index f0c94b7..ab03b22 100644
--- a/doc/README.spi-flash-conn-modes
+++ b/doc/README.spi-flash-conn-modes
@@ -63,6 +63,42 @@ Note: Technically there is only one CS line from the
controller, but
zynq qspi controller has an internal hw logic to enable additional CS
when controller is configured for dual memories.
+SPI_FLASH_CONN_DUALSTACKED:
+ - dual spi/qspi flash memories are connected with a single chipselect
+ line and these two memories are operating stacked fasion with shared
buses.
+ - xilinx zynq qspi controller has implemented this feature.
+ see trm for more info
+
http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
+
+ +-+CS+---+
+ ||--| |
+ || I0[3:0] | Upper Flash |
+ ||+=| memory|
+ ||| CLK | (SPI/QSPI)|
+ |||+| |
+ | Controller |CS || +---+
+ | SPI/QSPI |||| |
+ ||I0[3:0] || | Lower Flash |
+ ||===+|| memory|
+ || CLK| | (SPI/QSPI)|
+ ||-+| |
+ +-+ +---+
+
+ - two memory flash devices should has same hw part attributes (like
size,
+ vendor..etc)
+ - Configurations:
+ on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG
+ Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
+ Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory
+ - Operation:
+ accessing memories serially like one after another.
+ by default, if U_PAGE is unset lower memory sould accessible,
+ once user wants to access upper memory need to set U_PAGE.
+
+Note: Technically there is only one CS line from the controller, but
+zynq qspi controller has an internal hw logic to enable additional CS
+when controller is configured for dual memories.
+
--
Jagannadha Sutradharudu Teki jaga...@xilinx.com
29-07-2013.
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 3ed90bd..f7443fa 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -34,6 +34,9 @@ static int spi_flash_read_write(struct spi_slave *spi,
unsigned long flags = SPI_XFER_BEGIN;
int ret;
+ if ((spi-is_dual == SPI_FLASH_CONN_DUALSTACKED) (spi-u_page == 1))
+ flags |= SPI_FLASH_U_PAGE;
+
if (data_len == 0)
flags |= SPI_XFER_END;
@@ -176,6 +179,13 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32
offset, size_t len)
erase_addr = offset;
if (is_dual == SPI_FLASH_CONN_DUALPARALLEL)
erase_addr /= 2;
+
+ if (is_dual == SPI_FLASH_CONN_DUALSTACKED) {
+ if (erase_addr = (flash-size / 2))
+ flash-spi-u_page = 1;
+ else
+ flash-spi-u_page = 0;
+ }
#ifdef CONFIG_SPI_FLASH_BAR
u8 bank_sel;
@@ -221,6 +231,13 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32
offset,
write_addr = offset;
if (is_dual == SPI_FLASH_CONN_DUALPARALLEL)
write_addr /= 2;
+
+ if (is_dual == SPI_FLASH_CONN_DUALSTACKED) {
+ if (write_addr = (flash-size / 2))
+ flash-spi-u_page = 1;
+ else
+ flash-spi-u_page = 0;
+ }
#ifdef CONFIG_SPI_FLASH_BAR
u8 bank_sel;
@@ -304,6 +321,13 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32
[U-Boot] [PATCH 2/5] sf: spansion|stmicro: Enable dual parallel access
Dual parallel accessing can be done by updating flash part
attributes like page_size*2, sector_size*2
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/spansion.c | 6 ++
drivers/mtd/spi/stmicro.c | 6 ++
2 files changed, 12 insertions(+)
diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
index 47a4897..a4ea16b 100644
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -134,6 +134,12 @@ struct spi_flash *spi_flash_probe_spansion(struct
spi_slave *spi, u8 *idcode)
flash-page_size = 256;
flash-sector_size = 256 * params-pages_per_sector;
+
+ if (flash-spi-is_dual == SPI_FLASH_CONN_DUALPARALLEL) {
+ flash-page_size *= 2;
+ flash-sector_size *= 2;
+ }
+
flash-size = flash-sector_size * params-nr_sectors;
return flash;
diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c
index 0ca00f1..e9b4bc6 100644
--- a/drivers/mtd/spi/stmicro.c
+++ b/drivers/mtd/spi/stmicro.c
@@ -192,6 +192,12 @@ struct spi_flash *spi_flash_probe_stmicro(struct spi_slave
*spi, u8 * idcode)
flash-page_size = 256;
flash-sector_size = 256 * params-pages_per_sector;
+
+ if (flash-spi-is_dual == SPI_FLASH_CONN_DUALPARALLEL) {
+ flash-page_size *= 2;
+ flash-sector_size *= 2;
+ }
+
flash-size = flash-sector_size * params-nr_sectors;
/* for = 512MiB flashes, use flag status instead of read_status */
--
1.8.3
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[U-Boot] [PATCH 5/5] sf: Add bank selection support for dual stacked access
For upper memory, bank selection on dual stacked access
needs to subtract the calculated banks from the number of
banks available on a single memory.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/spi_flash.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index f7443fa..58d5899 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -190,6 +190,9 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32
offset, size_t len)
u8 bank_sel;
bank_sel = erase_addr / SPI_FLASH_16MB_BOUN;
+ if ((is_dual == SPI_FLASH_CONN_DUALSTACKED)
+ (flash-spi-u_page == 1))
+ bank_sel -= ((flash-size / 2) / SPI_FLASH_16MB_BOUN);
ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
if (ret) {
@@ -242,6 +245,9 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32
offset,
u8 bank_sel;
bank_sel = write_addr / SPI_FLASH_16MB_BOUN;
+ if ((is_dual == SPI_FLASH_CONN_DUALSTACKED)
+ (flash-spi-u_page == 1))
+ bank_sel -= ((flash-size / 2) / SPI_FLASH_16MB_BOUN);
ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
if (ret) {
@@ -330,12 +336,19 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32
offset,
}
#ifdef CONFIG_SPI_FLASH_BAR
bank_sel = read_addr / SPI_FLASH_16MB_BOUN;
+ if ((is_dual == SPI_FLASH_CONN_DUALSTACKED)
+ (flash-spi-u_page == 1))
+ bank_sel -= ((flash-size / 2) / SPI_FLASH_16MB_BOUN);
ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
if (ret) {
debug(SF: fail to set bank%d\n, bank_sel);
return ret;
}
+
+ if ((is_dual == SPI_FLASH_CONN_DUALSTACKED)
+ (flash-spi-u_page == 1))
+ bank_sel += ((flash-size / 2) / SPI_FLASH_16MB_BOUN);
#endif
remain_len = (bank_boun * (bank_sel + 1) - read_addr);
if (len remain_len)
--
1.8.3
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[U-Boot] [PATCH 1/5] sf: Add support for accessing dual parallel memories
This patch added support for accessing dual memories in
parallel connections with single chipselect line from controller.
this connection mode is implemented in xilinx zynq qspi controller.
For more info, see doc/README.spi-flash-conn-modes
Below are the changes for dual parallel to work:
- mtd layer - addr/2, page_size*2, sector_size*2
- driver - enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG reg.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
doc/README.spi-flash-conn-modes | 68 +
drivers/mtd/spi/spi_flash.c | 52 ++-
include/spi.h | 2 ++
include/spi_flash.h | 7 +
4 files changed, 114 insertions(+), 15 deletions(-)
create mode 100644 doc/README.spi-flash-conn-modes
diff --git a/doc/README.spi-flash-conn-modes b/doc/README.spi-flash-conn-modes
new file mode 100644
index 000..f0c94b7
--- /dev/null
+++ b/doc/README.spi-flash-conn-modes
@@ -0,0 +1,68 @@
+#
+# (C) Copyright 2013 Xilinx, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+SPI/QSPI flash connection modes:
+
+
+This describes how SPI/QSPI flash memories are connected to a given
+controller in a single chipselect line.
+
+Current spi_flash framework supports, single flash memory connected
+to a given controller with single chipselect line, but there are some
+hw logics(ex: xilinx zynq qspi) that describes two/dual memories are
+connected with a single chipselect line from a controller.
+
+is_dual from include/spi.h decribes these types of connection modes.
+
+Possible connections:
+
+SPI_FLASH_CONN_UNKNOWN:
+SPI_FLASH_CONN_SINGLE:
+ - single spi flash memory connected with single chip select line.
+
+ +-+ CS +---+
+ ||--| |
+ | Controller |I0[3:0]| Flash memory |
+ | SPI/QSPI |=| (SPI/QSPI)|
+ || CLK | |
+ ||--| |
+ +-+ +---+
+
+SPI_FLASH_CONN_DUALPARALLEL:
+ - dual spi/qspi flash memories are connected with a single chipselect
+ line and these two memories are operating parallel with separate
buses.
+ - xilinx zynq qspi controller has implemented this feature.
+ see trm for more info
+
http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
+
+ +-+ CS +---+
+ ||--| |
+ ||I0[3:0]| Upper Flash |
+ ||=| memory|
+ || CLK | (SPI/QSPI)|
+ ||--| |
+ | Controller | CS +---+
+ | SPI/QSPI |--| |
+ ||I0[3:0]| Lower Flash |
+ ||=| memory|
+ || CLK | (SPI/QSPI)|
+ ||--| |
+ +-+ +---+
+
+ - two memory flash devices should has same hw part attributes (like
size,
+ vendor..etc)
+ - Configurations:
+ Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG
register.
+ - Operation:
+ Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the
lower memory
+ and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in
the upper memory.
+
+Note: Technically there is only one CS line from the controller, but
+zynq qspi controller has an internal hw logic to enable additional CS
+when controller is configured for dual memories.
+
+--
+Jagannadha Sutradharudu Teki jaga...@xilinx.com
+29-07-2013.
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 6a6fe37..3ed90bd 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -156,9 +156,10 @@ int spi_flash_write_common(struct spi_flash *flash, const
u8 *cmd,
int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len)
{
- u32 erase_size;
+ u32 erase_size, erase_addr;
u8 cmd[4];
int ret = -1;
+ int is_dual = flash-spi-is_dual;
erase_size = flash-sector_size;
if (offset % erase_size || len % erase_size) {
@@ -172,10 +173,13 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32
offset, size_t len)
cmd[0] = CMD_ERASE_64K;
while (len) {
+ erase_addr = offset;
+ if (is_dual == SPI_FLASH_CONN_DUALPARALLEL)
+ erase_addr /= 2;
#ifdef CONFIG_SPI_FLASH_BAR
u8 bank_sel;
- bank_sel = offset /
[U-Boot] [PATCH 0/5] sf: Add support to access dual flash memory
This patchset adds support for dual flash memory accessing with single chipselect line from the controller. dual flash memory support is implemented in xilinx zynq qspi controllers in which dual stacked and dual parallel are the connection modes. Currently added these connection modes support on winbond and spansion flash parts, request for respective vendor should validate these support. REQUEST FOR ALL SPI CODE CONTRIBUTORS/USERS, PLEASE TEST THESE CHANGES W.R.T YOUR HW IF POSSIBLE. Please let me know for any issues/concerns/questions. -- Thanks, Jagan. Jagannadha Sutradharudu Teki (5): sf: Add support for accessing dual parallel memories sf: spansion|stmicro: Enable dual parallel access sf: Add support for accessing dual stacked memories sf: spansion|stmicro: Enable dual stacked access sf: Add bank selection support for dual stacked access doc/README.spi-flash-conn-modes | 104 drivers/mtd/spi/spansion.c | 9 drivers/mtd/spi/spi_flash.c | 91 +-- drivers/mtd/spi/stmicro.c | 9 include/spi.h | 5 ++ include/spi_flash.h | 8 6 files changed, 211 insertions(+), 15 deletions(-) create mode 100644 doc/README.spi-flash-conn-modes -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/5] sf: spansion|stmicro: Enable dual stacked access
Dual stacked accessing can be done by updating flash part attributes like sector_size*2 Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com --- drivers/mtd/spi/spansion.c | 3 +++ drivers/mtd/spi/stmicro.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c index a4ea16b..49ee842 100644 --- a/drivers/mtd/spi/spansion.c +++ b/drivers/mtd/spi/spansion.c @@ -140,6 +140,9 @@ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) flash-sector_size *= 2; } + if (flash-spi-is_dual == SPI_FLASH_CONN_DUALSTACKED) + flash-sector_size *= 2; + flash-size = flash-sector_size * params-nr_sectors; return flash; diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c index e9b4bc6..a701571 100644 --- a/drivers/mtd/spi/stmicro.c +++ b/drivers/mtd/spi/stmicro.c @@ -198,6 +198,9 @@ struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode) flash-sector_size *= 2; } + if (flash-spi-is_dual == SPI_FLASH_CONN_DUALSTACKED) + flash-sector_size *= 2; + flash-size = flash-sector_size * params-nr_sectors; /* for = 512MiB flashes, use flag status instead of read_status */ -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/6] am335x_evm: am33xx_spl_board_init function and scale core frequency
Hi Tom,
2013/7/23 Dan Murphy dmur...@ti.com:
On 07/19/2013 02:00 PM, Tom Rini wrote:
Add a am33xx_spl_board_init (and enable the PMICs) that we may see,
depending on the board we are running on. In all cases, we see if we
can rely on the efuse_sma register to tell us the maximum speed. In the
case of Beaglebone White, we need to make sure we are on AC power, and
are on later than rev A1, and then we can ramp up to the PG1.0 maximum
of 720Mhz. In the case of Beaglebone Black, we are either on PG2.0 that
supports 1GHz or PG2.1. As PG2.0 may or may not have efuse_sma set, we
cannot rely on this probe. In the case of the GP EVM, EVM SK and IDK we
need to rely on the efuse_sma if we are on PG2.1, and the defaults for
PG1.0/2.0.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |8 ++
board/ti/am335x/board.c | 155
++
include/configs/am335x_evm.h |4 +
3 files changed, 167 insertions(+)
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index 89b63d9..834f24f 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -24,6 +24,14 @@
#define CONFIG_SYS_MPUCLK550
#endif
+/* MAIN PLL Fdll supported frequencies */
+#define MPUPLL_M_10001000
+#define MPUPLL_M_800 800
+#define MPUPLL_M_720 720
+#define MPUPLL_M_600 600
+#define MPUPLL_M_550 550
+#define MPUPLL_M_300 300
+
extern void pll_init(void);
extern void enable_emif_clocks(void);
extern void enable_dmm_clocks(void);
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index fdbe26c..6544931 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -33,6 +33,8 @@
#include i2c.h
#include miiphy.h
#include cpsw.h
+#include power/tps65217.h
+#include power/tps65910.h
#include board.h
DECLARE_GLOBAL_DATA_PTR;
@@ -282,6 +284,159 @@ int spl_start_uboot(void)
}
#endif
+void am33xx_spl_board_init(void)
+{
+ int mpu_vdd, mpu_pll, sil_rev;
+
+ /* Assume PG 1.0 */
+ mpu_pll = MPUPLL_M_720;
+
+ sil_rev = readl(cdev-deviceid) 28;
+ if (sil_rev == 1)
+ /* PG 2.0, efuse may not be set. */
+ mpu_pll = MPUPLL_M_800;
+ else if (sil_rev = 2) {
+ /* Check what the efuse says our max speed is. */
+ int efuse_arm_mpu_max_freq;
+ efuse_arm_mpu_max_freq = readl(cdev-efuse_sma);
+ switch ((efuse_arm_mpu_max_freq DEVICE_ID_MASK)) {
+ case AM335X_ZCZ_1000:
+ mpu_pll = MPUPLL_M_1000;
+ break;
+ case AM335X_ZCZ_800:
+ mpu_pll = MPUPLL_M_800;
+ break;
+ case AM335X_ZCZ_720:
+ mpu_pll = MPUPLL_M_720;
+ break;
+ case AM335X_ZCZ_600:
+ case AM335X_ZCE_600:
+ mpu_pll = MPUPLL_M_600;
+ break;
+ case AM335X_ZCZ_300:
+ case AM335X_ZCE_300:
+ mpu_pll = MPUPLL_M_300;
+ break;
+ }
+ }
+
+ if (board_is_bone() || board_is_bone_lt()) {
+ /* BeagleBone PMIC Code */
+ int usb_cur_lim;
+
+ /*
+ * Only perform PMIC configurations if board rev A1
+ * on Beaglebone White
+ */
+ if (board_is_bone() !strncmp(header.version, 00A1, 4))
+ return;
+
+ if (i2c_probe(TPS65217_CHIP_PM))
+ return;
+
+ /*
+ * On Beaglebone White we need to ensure we have AC power
+ * before increasing the frequency.
+ */
+ if (board_is_bone()) {
+ uchar pmic_status_reg;
+ if (tps65217_reg_read(STATUS, pmic_status_reg))
+ return;
+ if (!(pmic_status_reg PWR_SRC_AC_BITMASK)) {
+ puts(No AC power, disabling frequency
switch\n);
+ return;
+ }
+ }
+
+ /*
+ * Increase USB current limit to 1300mA or 1800mA and set
+ * the MPU voltage controller as needed.
+ */
+ if (mpu_pll == MPUPLL_M_1000) {
+ usb_cur_lim = USB_INPUT_CUR_LIMIT_1800MA;
+ mpu_vdd = DCDC_VOLT_SEL_1325MV;
+ } else {
+ usb_cur_lim = USB_INPUT_CUR_LIMIT_1300MA;
+ mpu_vdd = DCDC_VOLT_SEL_1275MV;
+ }
+
+ if (tps65217_reg_write(PROT_LEVEL_NONE, POWER_PATH,
+usb_cur_lim,
Re: [U-Boot] [PATCH v3 8/9] tegra: i2c: Enable new CONFIG_SYS_I2C framework
On 05/04/2013 06:01 AM, Heiko Schocher wrote: From: Simon Glass s...@chromium.org This enables CONFIG_SYS_I2C on Tegra, updating existing boards and the Tegra i2c driver to support this. Heiko, the latest U-Boot tree hangs during boot on Tegra, and git bisect points at this patch. Olof reported the issue to me. Can you take a look at the code and see what might be wrong? Thanks. I suspect some kind of initialization ordering issue, since the boot messages are: - U-Boot SPL 2013.07-rc3-00038-g880540d (Jul 29 2013 - 10:04:37) U-Boot 2013.07-rc3-00038-g880540d (Jul 29 2013 - 10:04:37) TEGRA30 Board: NVIDIA Beaver I2C: Caller requested bad clock: periph=-49, parent=2 - ... and that bad clock message implies to me that the I2C driver is initializing before it has parsed the correct clock ID out of device tree. Some later commit causes the hang to happen right after printing I2C:, without printing the bad clock message. I didn't investigate that, since I'm assuming the root-cause is the same. Most likely some later commit causes the uninitialized data to be a valid clock, yet not the actual I2C clock, so the I2C clock still isn't turned on, and touching HW (i.e. reading/writing the I2C registers) without a running clock on Tegra caused hard hangs. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC] Remove static display data
Hi Eric, On Sun, Jul 28, 2013 at 1:22 PM, Eric Nelson eric.nel...@boundarydevices.com wrote: Hi Simon, On 07/28/2013 11:09 AM, Simon Glass wrote: Hi Eric, On Sun, Jul 28, 2013 at 10:57 AM, Eric Nelson eric.nelson@boundarydevices.**com eric.nel...@boundarydevices.com mailto:eric.nelson@**boundarydevices.comeric.nel...@boundarydevices.com wrote: On our boards, we store the environment in SPI-NOR, but in a separate 8k block. I presume the bound fdt will be stored immediately after U-Boot, which will move around a bit as the code changes. Yes - it would be nice to have an option to put the FDT anywhere, but that is not supported at present. Even better if SPL could load it. Better again if U-Boot plus its FDTs could be a FIT image and SPL could load that and select the correct FDT. That's a whole bunch of TLAs :) Sorry, I mean: FDT - flat device tree SPL - secondary program loader - the little thing that loads U-Boot FIT - flat image tree - a type of file that can hold multiple kernels/FDTs/ramdisks that can be selected at boot I don't see any major blockers in any of these, though our immediate goals are much more modest: - put display configuration into a read/write spot, and - allow users to specify resolutions for HDMI and timing information for new panels If we can just parse block(s) of DT text, then update or append that to the kernel FDT, I think we can meet our needs. Sounds good. The FDT is normally stored immediately after U-Boot, but I suppose we could add an option for the FDT to live elsewhere, or perhaps be loaded from flash live the environment. Actually the latter is already possible by reading the new FDT into RAM in your boot script, and making U-Boot use it, something like: sf probe sf read addr ... fdt addr -c addr At the moment, we intend to normally load the FDT from the same media as the kernel for a couple of reasons: - It's not needed at all for non-Linux uses (we support Windows Embedded, QNX, et cetera) - We'll likely need separate FDTs for different boards which can execute the same U-Boot binary (Nitrogen6x, SABRE Lite) unless we can figure out a way to place small conditionals in the FDT We attach a kernel FDT to the kernel image. Passing U-Boot's FDT to the kernel is an option that I haven't explored, and is probably only possible if it can be updated. I'm coming at this from the other direction: I've only seen how to load FDT from secondary storage and hand it to the kernel with bootm. That's easy - just put it in a FIT. Then you can package the kernel and various FDTs into that FIT, use bootm to load it. If you do enable CONFIG_OF_CONTROL, then also enable CONFIG_FIT_BEST_MATCH - it will choose the correct one for the kernel based on U-Boot's compatible information. Then the FDT selection becomes automatic. Regards, Eric Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Query: Ethernet switch support
Hi Sharma, On Mon, 29 Jul 2013 15:33:39 +, Sharma Bhupesh-B45370 b45...@freescale.com wrote: Hi List, I am trying to add support of a Vitesse L2 switch in u-boot (in unmanaged configuration). I was analyzing whether advanced features like flow control, link-aggregation etc are required to be supported for a L2 switch working in a u-boot bootloader level. My point-of-view is that the L2 switch, should support only bare-minimum tftp of images, ping to other ethernet entities, bootp .. type of commands on u-boot and as such the L2 switch u-boot driver doesn't need to address flow-control and other such advanced features (probably of interest for a Linux device driver). But, I am not sure about the design approaches used to support previous switch modules in u-boot. Also I had a query whether there is a common switch framework in-place/under-consideration in u-boot, similar to what is already present in OpenWrt code: https://dev.openwrt.org/browser/trunk/package/boot/uboot-lantiq/patches/0019-net-switchlib-add-framework-for-ethernet-switch-driv.patch?rev=35292 Would porting this to u-boot make sense to have a common framework for ethernet switch in-place? Can you please let me know your views on the same and point me to any reference switch drivers that support these features. There is some support for switches in U-Boot (e.g. mv88e61xx) but no framework that I know of; and I suspect what is expected from the switch in U-Boot is that it does not hamper Ethernet operations, nothing more. for mv88e61xx, this is done through a fixed configuration. Regards, Bhupesh Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/6] sf: sst: Fix code cleanup
- line over 80 characters
- add spaces
- add tabs
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sst.c | 32
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/spi/sst.c b/drivers/mtd/spi/sst.c
index 95f5490..6292289 100644
--- a/drivers/mtd/spi/sst.c
+++ b/drivers/mtd/spi/sst.c
@@ -19,7 +19,7 @@
#include spi_flash_internal.h
#define CMD_SST_BP 0x02/* Byte Program */
-#define CMD_SST_AAI_WP 0xAD/* Auto Address Increment Word Program
*/
+#define CMD_SST_AAI_WP 0xAD/* Auto Address Incr Word Program */
#define SST_SR_WIP (1 0)/* Write-in-Progress */
#define SST_SR_WEL (1 1)/* Write enable */
@@ -50,42 +50,50 @@ static const struct sst_spi_flash_params
sst_spi_flash_table[] = {
.flags = SST_FEAT_WP,
.nr_sectors = 128,
.name = SST25VF040B,
- },{
+ },
+ {
.idcode1 = 0x8e,
.flags = SST_FEAT_WP,
.nr_sectors = 256,
.name = SST25VF080B,
- },{
+ },
+ {
.idcode1 = 0x41,
.flags = SST_FEAT_WP,
.nr_sectors = 512,
.name = SST25VF016B,
- },{
+ },
+ {
.idcode1 = 0x4a,
.flags = SST_FEAT_WP,
.nr_sectors = 1024,
.name = SST25VF032B,
- },{
+ },
+ {
.idcode1 = 0x4b,
.flags = SST_FEAT_MBP,
.nr_sectors = 2048,
.name = SST25VF064C,
- },{
+ },
+ {
.idcode1 = 0x01,
.flags = SST_FEAT_WP,
.nr_sectors = 16,
.name = SST25WF512,
- },{
+ },
+ {
.idcode1 = 0x02,
.flags = SST_FEAT_WP,
.nr_sectors = 32,
.name = SST25WF010,
- },{
+ },
+ {
.idcode1 = 0x03,
.flags = SST_FEAT_WP,
.nr_sectors = 64,
.name = SST25WF020,
- },{
+ },
+ {
.idcode1 = 0x04,
.flags = SST_FEAT_WP,
.nr_sectors = 128,
@@ -152,11 +160,11 @@ sst_write_wp(struct spi_flash *flash, u32 offset, size_t
len, const void *buf)
for (; actual len - 1; actual += 2) {
debug(WP[%02x]: 0x%p = cmd = { 0x%02x 0x%06x }\n,
-spi_w8r8(flash-spi, CMD_READ_STATUS), buf + actual,
cmd[0],
-offset);
+spi_w8r8(flash-spi, CMD_READ_STATUS), buf + actual,
+cmd[0], offset);
ret = spi_flash_cmd_write(flash-spi, cmd, cmd_len,
- buf + actual, 2);
+ buf + actual, 2);
if (ret) {
debug(SF: sst word program failed\n);
break;
--
1.8.3
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[U-Boot] [PATCH v2 1/6] sf: eon|spansion|ramtron: Fix code cleanup
- line over 80 characters
- insert the expression in same line
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/eon.c | 3 +--
drivers/mtd/spi/ramtron.c | 6 --
drivers/mtd/spi/spansion.c | 3 ++-
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/spi/eon.c b/drivers/mtd/spi/eon.c
index b16e7ab..25cfc12 100644
--- a/drivers/mtd/spi/eon.c
+++ b/drivers/mtd/spi/eon.c
@@ -54,8 +54,7 @@ struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi,
u8 *idcode)
flash-page_size = 256;
flash-sector_size = 256 * 16 * 16;
- flash-size = 256 * 16
- * params-nr_sectors;
+ flash-size = 256 * 16 * params-nr_sectors;
return flash;
}
diff --git a/drivers/mtd/spi/ramtron.c b/drivers/mtd/spi/ramtron.c
index f67ddd6..27e6411 100644
--- a/drivers/mtd/spi/ramtron.c
+++ b/drivers/mtd/spi/ramtron.c
@@ -230,7 +230,8 @@ struct spi_flash *spi_fram_probe_ramtron(struct spi_slave
*spi, u8 *idcode)
/* JEDEC conformant RAMTRON id */
for (i = 0; i ARRAY_SIZE(ramtron_spi_fram_table); i++) {
params = ramtron_spi_fram_table[i];
- if (idcode[1] == params-id1 idcode[2] ==
params-id2)
+ if (idcode[1] == params-id1
+ idcode[2] == params-id2)
goto found;
}
break;
@@ -251,7 +252,8 @@ struct spi_flash *spi_fram_probe_ramtron(struct spi_slave
*spi, u8 *idcode)
/* now find the device */
for (i = 0; i ARRAY_SIZE(ramtron_spi_fram_table); i++) {
params = ramtron_spi_fram_table[i];
- if (!strcmp(params-name,
CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC))
+ if (!strcmp(params-name,
+ CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC))
goto found;
}
debug(SF: Unsupported non-JEDEC RAMTRON device
diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
index 47a4897..b9a36c2 100644
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -122,7 +122,8 @@ struct spi_flash *spi_flash_probe_spansion(struct spi_slave
*spi, u8 *idcode)
}
if (i == ARRAY_SIZE(spansion_spi_flash_table)) {
- debug(SF: Unsupported SPANSION ID %04x %04x\n, jedec,
ext_jedec);
+ debug(SF: Unsupported SPANSION ID %04x %04x\n,
+ jedec, ext_jedec);
return NULL;
}
--
1.8.3
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[U-Boot] [PATCH v2 5/6] cmd_sf|env_sf: Fix code cleanup
- line over 80 characters
- add tabs
- CHECK: Alignment should match open parenthesis
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
common/cmd_sf.c | 27 ++-
common/env_sf.c | 2 +-
2 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 19b0dc9..34844ac 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -151,12 +151,12 @@ static const char *spi_flash_update_block(struct
spi_flash *flash, u32 offset,
size_t len, const char *buf, char *cmp_buf, size_t *skipped)
{
debug(offset=%#x, sector_size=%#x, len=%#zx\n,
- offset, flash-sector_size, len);
+ offset, flash-sector_size, len);
if (spi_flash_read(flash, offset, len, cmp_buf))
return read;
if (memcmp(cmp_buf, buf, len) == 0) {
debug(Skip region %x size %zx: no change\n,
- offset, len);
+ offset, len);
*skipped += len;
return NULL;
}
@@ -200,7 +200,7 @@ static int spi_flash_update(struct spi_flash *flash, u32
offset,
todo = min(end - buf, flash-sector_size);
if (get_timer(last_update) 100) {
printf( \rUpdating, %zu%% %lu B/s,
- 100 - (end - buf) / scale,
+ 100 - (end - buf) / scale,
bytes_per_second(buf - start_buf,
start_time));
last_update = get_timer(0);
@@ -220,9 +220,9 @@ static int spi_flash_update(struct spi_flash *flash, u32
offset,
delta = get_timer(start_time);
printf(%zu bytes written, %zu bytes skipped, len - skipped,
- skipped);
+ skipped);
printf( in %ld.%lds, speed %ld B/s\n,
- delta / 1000, delta % 1000, bytes_per_second(len, start_time));
+ delta / 1000, delta % 1000, bytes_per_second(len, start_time));
return 0;
}
@@ -252,7 +252,7 @@ static int do_spi_flash_read_write(int argc, char * const
argv[])
/* Consistency checking */
if (offset + len flash-size) {
printf(ERROR: attempting %s past flash size (%#x)\n,
- argv[0], flash-size);
+ argv[0], flash-size);
return 1;
}
@@ -262,9 +262,9 @@ static int do_spi_flash_read_write(int argc, char * const
argv[])
return 1;
}
- if (strcmp(argv[0], update) == 0)
+ if (strcmp(argv[0], update) == 0) {
ret = spi_flash_update(flash, offset, len, buf);
- else if (strncmp(argv[0], read, 4) == 0 ||
+ } else if (strncmp(argv[0], read, 4) == 0 ||
strncmp(argv[0], write, 5) == 0) {
int read;
@@ -275,7 +275,7 @@ static int do_spi_flash_read_write(int argc, char * const
argv[])
ret = spi_flash_write(flash, offset, len, buf);
printf(SF: %zu bytes @ %#x %s: %s\n, (size_t)len, (u32)offset,
- read ? Read : Written, ret ? ERROR : OK);
+ read ? Read : Written, ret ? ERROR : OK);
}
unmap_physmem(buf, len);
@@ -304,13 +304,13 @@ static int do_spi_flash_erase(int argc, char * const
argv[])
/* Consistency checking */
if (offset + len flash-size) {
printf(ERROR: attempting %s past flash size (%#x)\n,
- argv[0], flash-size);
+ argv[0], flash-size);
return 1;
}
ret = spi_flash_erase(flash, offset, len);
printf(SF: %zu bytes @ %#x Erased: %s\n, (size_t)len, (u32)offset,
- ret ? ERROR : OK);
+ ret ? ERROR : OK);
return ret == 0 ? 0 : 1;
}
@@ -470,7 +470,8 @@ static int do_spi_flash_test(int argc, char * const argv[])
}
#endif /* CONFIG_CMD_SF_TEST */
-static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int argc, char * const
argv[])
+static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
const char *cmd;
int ret;
@@ -526,7 +527,7 @@ U_BOOT_CMD(
SPI flash sub-system,
probe [[bus:]cs] [hz] [mode] - init flash device on given SPI bus\n
and chip select\n
- sf read addr offset len- read `len' bytes starting at\n
+ sf read addr offset len- read `len' bytes starting at\n
`offset' to memory at `addr'\n
sf write addr offset len - write `len' bytes from memory\n
at `addr' to flash at `offset'\n
diff --git a/common/env_sf.c b/common/env_sf.c
index e3e1897..9f806fb
[U-Boot] [PATCH v2 4/6] sf: Fix code cleanup
- line over 80 characters.
- CHECK: Alignment should match open parenthesis
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/spi_flash.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 6a6fe37..9814395 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -40,12 +40,13 @@ static int spi_flash_read_write(struct spi_slave *spi,
ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
if (ret) {
debug(SF: Failed to send command (%zu bytes): %d\n,
- cmd_len, ret);
+ cmd_len, ret);
} else if (data_len != 0) {
- ret = spi_xfer(spi, data_len * 8, data_out, data_in,
SPI_XFER_END);
+ ret = spi_xfer(spi, data_len * 8, data_out, data_in,
+ SPI_XFER_END);
if (ret)
debug(SF: Failed to transfer %zu bytes of data: %d\n,
- data_len, ret);
+ data_len, ret);
}
return ret;
@@ -86,7 +87,7 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash,
unsigned long timeout)
ret = spi_xfer(spi, 8, cmd, NULL, SPI_XFER_BEGIN);
if (ret) {
debug(SF: fail to read %s status register\n,
- cmd == CMD_READ_STATUS ? read : flag);
+ cmd == CMD_READ_STATUS ? read : flag);
return ret;
}
@@ -144,7 +145,7 @@ int spi_flash_write_common(struct spi_flash *flash, const
u8 *cmd,
ret = spi_flash_cmd_wait_ready(flash, timeout);
if (ret 0) {
debug(SF: write %s timed out\n,
- timeout == SPI_FLASH_PROG_TIMEOUT ?
+ timeout == SPI_FLASH_PROG_TIMEOUT ?
program : page erase);
return ret;
}
--
1.8.3
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[U-Boot] [PATCH v2 3/6] sf: stmicro: Fix code cleanup
- line over 80 characters
- foo * bar - foo *bar
- removed unnecessary for single statement blocks.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/stmicro.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c
index 0ca00f1..e8cc827 100644
--- a/drivers/mtd/spi/stmicro.c
+++ b/drivers/mtd/spi/stmicro.c
@@ -18,7 +18,7 @@
#include spi_flash_internal.h
/* M25Pxx-specific commands */
-#define CMD_M25PXX_RES 0xab/* Release from DP, and Read Signature
*/
+#define CMD_M25PXX_RES 0xab/* Release from DP, and Read Signature */
struct stmicro_spi_flash_params {
u16 id;
@@ -150,7 +150,7 @@ static const struct stmicro_spi_flash_params
stmicro_spi_flash_table[] = {
},
};
-struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode)
+struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode)
{
const struct stmicro_spi_flash_params *params;
struct spi_flash *flash;
@@ -174,9 +174,8 @@ struct spi_flash *spi_flash_probe_stmicro(struct spi_slave
*spi, u8 * idcode)
for (i = 0; i ARRAY_SIZE(stmicro_spi_flash_table); i++) {
params = stmicro_spi_flash_table[i];
- if (params-id == id) {
+ if (params-id == id)
break;
- }
}
if (i == ARRAY_SIZE(stmicro_spi_flash_table)) {
--
1.8.3
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[U-Boot] [PATCH v2 6/6] sf: Fix code cleanups
- CHECK: Alignment should match open parenthesis
- trailing whitespace
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/atmel.c| 10 +-
drivers/mtd/spi/gigadevice.c | 2 +-
drivers/mtd/spi/ramtron.c | 2 +-
drivers/mtd/spi/spansion.c | 2 +-
drivers/mtd/spi/spi_spl_load.c | 2 +-
drivers/mtd/spi/sst.c | 6 +++---
drivers/mtd/spi/stmicro.c | 5 +++--
drivers/mtd/spi/winbond.c | 2 +-
8 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/drivers/mtd/spi/atmel.c b/drivers/mtd/spi/atmel.c
index 6a92c4b..f34df43 100644
--- a/drivers/mtd/spi/atmel.c
+++ b/drivers/mtd/spi/atmel.c
@@ -252,7 +252,7 @@ static int dataflash_write_p2(struct spi_flash *flash,
}
debug(SF: AT45: Successfully programmed %zu bytes @ 0x%x\n,
- len, offset);
+ len, offset);
ret = 0;
out:
@@ -325,7 +325,7 @@ static int dataflash_write_at45(struct spi_flash *flash,
}
debug(SF: AT45: Successfully programmed %zu bytes @ 0x%x\n,
- len, offset);
+ len, offset);
ret = 0;
out:
@@ -387,7 +387,7 @@ static int dataflash_erase_p2(struct spi_flash *flash, u32
offset, size_t len)
}
debug(SF: AT45: Successfully erased %zu bytes @ 0x%x\n,
- len, offset);
+ len, offset);
ret = 0;
out:
@@ -450,7 +450,7 @@ static int dataflash_erase_at45(struct spi_flash *flash,
u32 offset, size_t len)
}
debug(SF: AT45: Successfully erased %zu bytes @ 0x%x\n,
- len, offset);
+ len, offset);
ret = 0;
out:
@@ -476,7 +476,7 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave
*spi, u8 *idcode)
if (i == ARRAY_SIZE(atmel_spi_flash_table)) {
debug(SF: Unsupported DataFlash ID %02x\n,
- idcode[1]);
+ idcode[1]);
return NULL;
}
diff --git a/drivers/mtd/spi/gigadevice.c b/drivers/mtd/spi/gigadevice.c
index 950c777..b42581a 100644
--- a/drivers/mtd/spi/gigadevice.c
+++ b/drivers/mtd/spi/gigadevice.c
@@ -45,7 +45,7 @@ struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave
*spi, u8 *idcode)
if (i == ARRAY_SIZE(gigadevice_spi_flash_table)) {
debug(SF: Unsupported Gigadevice ID %02x%02x\n,
- idcode[1], idcode[2]);
+ idcode[1], idcode[2]);
return NULL;
}
diff --git a/drivers/mtd/spi/ramtron.c b/drivers/mtd/spi/ramtron.c
index 27e6411..38f9d69 100644
--- a/drivers/mtd/spi/ramtron.c
+++ b/drivers/mtd/spi/ramtron.c
@@ -266,7 +266,7 @@ struct spi_flash *spi_fram_probe_ramtron(struct spi_slave
*spi, u8 *idcode)
/* arriving here means no method has found a device we can handle */
debug(SF/ramtron: unsupported device id0=%02x id1=%02x id2=%02x\n,
- idcode[0], idcode[1], idcode[2]);
+ idcode[0], idcode[1], idcode[2]);
return NULL;
found:
diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
index b9a36c2..fa7ac8c 100644
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -6,7 +6,7 @@
* TsiChung Liew (tsi-chung.l...@freescale.com),
* and Jason McMullan (mcmul...@netapp.com)
*
- * SPDX-License-Identifier:GPL-2.0+
+ * SPDX-License-Identifier:GPL-2.0+
*/
#include common.h
diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c
index 7c799ca..2935530 100644
--- a/drivers/mtd/spi/spi_spl_load.c
+++ b/drivers/mtd/spi/spi_spl_load.c
@@ -39,7 +39,7 @@ void spl_spi_load_image(void)
/* Load u-boot, mkimage header is 64 bytes. */
spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40,
- (void *) header);
+ (void *)header);
spl_parse_image_header(header);
spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
spl_image.size, (void *)spl_image.load_addr);
diff --git a/drivers/mtd/spi/sst.c b/drivers/mtd/spi/sst.c
index 6292289..c9dec3c52 100644
--- a/drivers/mtd/spi/sst.c
+++ b/drivers/mtd/spi/sst.c
@@ -113,7 +113,7 @@ sst_byte_write(struct spi_flash *flash, u32 offset, const
void *buf)
};
debug(BP[%02x]: 0x%p = cmd = { 0x%02x 0x%06x }\n,
- spi_w8r8(flash-spi, CMD_READ_STATUS), buf, cmd[0], offset);
+ spi_w8r8(flash-spi, CMD_READ_STATUS), buf, cmd[0], offset);
ret = spi_flash_cmd_write_enable(flash);
if (ret)
@@ -160,8 +160,8 @@ sst_write_wp(struct spi_flash *flash, u32 offset, size_t
len, const void *buf)
for (; actual len - 1; actual += 2) {
debug(WP[%02x]: 0x%p = cmd = { 0x%02x 0x%06x }\n,
-spi_w8r8(flash-spi, CMD_READ_STATUS), buf + actual,
-cmd[0], offset);
+
[U-Boot] [PATCH v2 0/6] sf: Code cleanup patch set
This patch set consist of code clean-up on sf. Thanks, Jagan. Jagannadha Sutradharudu Teki (6): sf: eon|spansion|ramtron: Fix code cleanup sf: sst: Fix code cleanup sf: stmicro: Fix code cleanup sf: Fix code cleanup cmd_sf|env_sf: Fix code cleanup sf: Fix code cleanups common/cmd_sf.c| 27 ++- common/env_sf.c| 2 +- drivers/mtd/spi/atmel.c| 10 +- drivers/mtd/spi/eon.c | 3 +-- drivers/mtd/spi/gigadevice.c | 2 +- drivers/mtd/spi/ramtron.c | 8 +--- drivers/mtd/spi/spansion.c | 5 +++-- drivers/mtd/spi/spi_flash.c| 11 ++- drivers/mtd/spi/spi_spl_load.c | 2 +- drivers/mtd/spi/sst.c | 34 +- drivers/mtd/spi/stmicro.c | 12 ++-- drivers/mtd/spi/winbond.c | 2 +- 12 files changed, 65 insertions(+), 53 deletions(-) -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/4] sf: macronix: Add support for MX25L51235F
Add support for Macronix MX25L51235F SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/macronix.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mtd/spi/macronix.c b/drivers/mtd/spi/macronix.c
index ce2fb9c..d0e6d6c 100644
--- a/drivers/mtd/spi/macronix.c
+++ b/drivers/mtd/spi/macronix.c
@@ -66,6 +66,11 @@ static const struct macronix_spi_flash_params
macronix_spi_flash_table[] = {
.nr_blocks = 512,
.name = MX25L25635F,
},
+ {
+ .idcode = 0x201A,
+ .nr_blocks = 1024,
+ .name = MX66L51235F,
+ },
};
struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode)
--
1.8.3
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[U-Boot] [PATCH 2/4] sf: Add bank addr access support macronix flash's
This patch adds bank addr access support for macronix flash's so-that the macronix flashes which has 16Mbyte sizes can be accessible in 3-byte addressing mode. Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com --- drivers/mtd/spi/spi_flash.c | 1 + drivers/mtd/spi/spi_flash_internal.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 9814395..2528ebc 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -371,6 +371,7 @@ int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0) break; case SPI_FLASH_STMICRO_IDCODE0: case SPI_FLASH_WINBOND_IDCODE0: + case SPI_FLASH_MACRONIX_IDCODE0: flash-bank_read_cmd = CMD_EXTNADDR_RDEAR; flash-bank_write_cmd = CMD_EXTNADDR_WREAR; break; diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index 20eed7c..30b2749 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -36,6 +36,7 @@ # define SPI_FLASH_SPANSION_IDCODE00x01 # define SPI_FLASH_STMICRO_IDCODE0 0x20 # define SPI_FLASH_WINBOND_IDCODE0 0xef +# define SPI_FLASH_MACRONIX_IDCODE00xc2 /* Bank addr access commands */ # define CMD_BANKADDR_BRWR 0x17 -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4] sf: macronix: Add support for MX25L25635F
Add support for Macronix MX25L25635F SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/macronix.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mtd/spi/macronix.c b/drivers/mtd/spi/macronix.c
index 70435eb..ce2fb9c 100644
--- a/drivers/mtd/spi/macronix.c
+++ b/drivers/mtd/spi/macronix.c
@@ -61,6 +61,11 @@ static const struct macronix_spi_flash_params
macronix_spi_flash_table[] = {
.nr_blocks = 256,
.name = MX25L12855E,
},
+ {
+ .idcode = 0x2019,
+ .nr_blocks = 512,
+ .name = MX25L25635F,
+ },
};
struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode)
--
1.8.3
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[U-Boot] [PATCH 1/4] sf: Move manufacture id code macros to CONFIG_SPI_FLASH_BAR
IDCODE0 are required to find the bank addr read/write commands, as these commands are specific to manufacture id hence moved manu id code macros to CONFIG_SPI_FLASH_BAR. Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com --- drivers/mtd/spi/spi_flash_internal.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index af1afa9..20eed7c 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -31,12 +31,12 @@ #define SPI_FLASH_16MB_BOUN0x100 +#ifdef CONFIG_SPI_FLASH_BAR /* Manufacture ID's */ -#define SPI_FLASH_SPANSION_IDCODE0 0x01 -#define SPI_FLASH_STMICRO_IDCODE0 0x20 -#define SPI_FLASH_WINBOND_IDCODE0 0xef +# define SPI_FLASH_SPANSION_IDCODE00x01 +# define SPI_FLASH_STMICRO_IDCODE0 0x20 +# define SPI_FLASH_WINBOND_IDCODE0 0xef -#ifdef CONFIG_SPI_FLASH_BAR /* Bank addr access commands */ # define CMD_BANKADDR_BRWR 0x17 # define CMD_BANKADDR_BRRD 0x16 -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/4] sf: macronix: Add support for bank addr access
This patch set adds bank addr access support for macronix flash's so-that the macronix flashes which has 16Mbyte sizes can be accessible in 3-byte addressing mode. REQUEST FOR MACRONIX FLASH VENDORS/USERS: PLEASE TEST THESE CHANGES ON YOUR RESPECTIVE HW, FLASH PARTS FROM USER HW IS NOT AVAILABLE ON EXISTING U-BOOT PLEASE ADD THE SAME. -- Thanks, Jagan. Jagannadha Sutradharudu Teki (4): sf: Move manufacture id code macros to CONFIG_SPI_FLASH_BAR sf: Add bank addr access support macronix flash's sf: macronix: Add support for MX25L25635F sf: macronix: Add support for MX25L51235F drivers/mtd/spi/macronix.c | 10 ++ drivers/mtd/spi/spi_flash.c | 1 + drivers/mtd/spi/spi_flash_internal.h | 9 + 3 files changed, 16 insertions(+), 4 deletions(-) -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] spi: Add zynq spi controller driver
Zynq spi controller driver supports 2 buses and
3 chipselects on each bus.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Acked-by: Siva Durga Prasad Paladugu siva...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/include/asm/arch-zynq/hardware.h | 2 +
drivers/spi/Makefile | 1 +
drivers/spi/zynq_spi.c| 280 ++
3 files changed, 283 insertions(+)
create mode 100644 drivers/spi/zynq_spi.c
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h
b/arch/arm/include/asm/arch-zynq/hardware.h
index 25f0e3d..081624e 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -17,6 +17,8 @@
#define ZYNQ_SDHCI_BASEADDR1 0xE0101000
#define ZYNQ_I2C_BASEADDR0 0xE0004000
#define ZYNQ_I2C_BASEADDR1 0xE0005000
+#define ZYNQ_SPI_BASEADDR0 0xE0006000
+#define ZYNQ_SPI_BASEADDR1 0xE0007000
/* Reflect slcr offsets */
struct slcr_regs {
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 019132e..91d24ce 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
+COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
new file mode 100644
index 000..d9424d2
--- /dev/null
+++ b/drivers/spi/zynq_spi.c
@@ -0,0 +1,280 @@
+/*
+ * (C) Copyright 2013 Inc.
+ *
+ * Xilinx PS SPI controller driver (master mode only)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include config.h
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include asm/arch/hardware.h
+
+/* zynq spi register bit masks ZYNQ_SPI_REG_BIT_MASK */
+#define ZYNQ_SPI_CR_MSA_MASK (1 15) /* Manual start enb */
+#define ZYNQ_SPI_CR_MCS_MASK (1 14) /* Manual chip select */
+#define ZYNQ_SPI_CR_CS_MASK(0xF 10) /* Chip select */
+#define ZYNQ_SPI_CR_BRD_MASK (0x7 3) /* Baud rate div */
+#define ZYNQ_SPI_CR_CPHA_MASK (1 2)/* Clock phase */
+#define ZYNQ_SPI_CR_CPOL_MASK (1 1)/* Clock polarity */
+#define ZYNQ_SPI_CR_MSTREN_MASK(1 0)/* Mode select
*/
+#define ZYNQ_SPI_IXR_RXNEMPTY_MASK (1 4)/* RX_FIFO_not_empty */
+#define ZYNQ_SPI_IXR_TXOW_MASK (1 2)/* TX_FIFO_not_full */
+#define ZYNQ_SPI_IXR_ALL_MASK 0x7F/* All IXR bits */
+#define ZYNQ_SPI_ENR_SPI_EN_MASK (1 0)/* SPI Enable */
+
+#define ZYNQ_SPI_FIFO_DEPTH128
+#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
+#define CONFIG_SYS_ZYNQ_SPI_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
+#endif
+
+/* zynq spi register set */
+struct zynq_spi_regs {
+ u32 cr; /* 0x00 */
+ u32 isr;/* 0x04 */
+ u32 ier;/* 0x08 */
+ u32 idr;/* 0x0C */
+ u32 imr;/* 0x10 */
+ u32 enr;/* 0x14 */
+ u32 dr; /* 0x18 */
+ u32 txdr; /* 0x1C */
+ u32 rxdr; /* 0x20 */
+};
+
+/* zynq spi slave */
+struct zynq_spi_slave {
+ struct spi_slave slave;
+ struct zynq_spi_regs *base;
+ u8 mode;
+ u8 fifo_depth;
+ u32 speed_hz;
+ u32 input_hz;
+ u32 req_hz;
+};
+
+static inline struct zynq_spi_slave *to_zynq_spi_slave(struct spi_slave *slave)
+{
+ return container_of(slave, struct zynq_spi_slave, slave);
+}
+
+static inline struct zynq_spi_regs *get_zynq_spi_base(int dev)
+{
+ if (dev)
+ return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR1;
+ else
+ return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR0;
+}
+
+static void zynq_spi_init_hw(struct zynq_spi_slave *zslave)
+{
+ u32 confr;
+
+ /* Disable SPI */
+ writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, zslave-base-enr);
+
+ /* Disable Interrupts */
+ writel(ZYNQ_SPI_IXR_ALL_MASK, zslave-base-idr);
+
+ /* Clear RX FIFO */
+ while (readl(zslave-base-isr)
+ ZYNQ_SPI_IXR_RXNEMPTY_MASK)
+ readl(zslave-base-rxdr);
+
+ /* Clear Interrupts */
+ writel(ZYNQ_SPI_IXR_ALL_MASK, zslave-base-isr);
+
+ /* Manual slave select and Auto start */
+ confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
+ ZYNQ_SPI_CR_MSTREN_MASK;
+ confr = ~ZYNQ_SPI_CR_MSA_MASK;
+ writel(confr, zslave-base-cr);
+
+ /* Enable SPI */
+ writel(ZYNQ_SPI_ENR_SPI_EN_MASK, zslave-base-enr);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ /* 2 bus with 3 chipselect */
+ return bus 2 cs 3;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
[U-Boot] [PATCH 3/3] zynq: Enable CONFIG_ZYNQ_SPI
Tested spi on zynq board with sst flash by enabling CONFIG_ZYNQ_SPI. sf probe 1:1 0 0 SF: Detected SST25WF080 with page size 4 KiB, total 1 MiB Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com Acked-by: Siva Durga Prasad Paladugu siva...@xilinx.com Signed-off-by: Michal Simek michal.si...@xilinx.com --- include/configs/zynq.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 79fa5bb..d93aaea 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -72,6 +72,16 @@ # define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ #endif +#define CONFIG_ZYNQ_SPI + +/* SPI */ +#ifdef CONFIG_ZYNQ_SPI +# define CONFIG_SPI_FLASH +# define CONFIG_SPI_FLASH_SST +# define CONFIG_CMD_SPI +# define CONFIG_CMD_SF +#endif + /* Enable the PL to be downloaded */ #define CONFIG_FPGA #define CONFIG_FPGA_XILINX -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] sf: sst: Add support for SST25WF080
Add support for SST25WF080 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/mtd/spi/sst.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mtd/spi/sst.c b/drivers/mtd/spi/sst.c
index c9dec3c52..256867c 100644
--- a/drivers/mtd/spi/sst.c
+++ b/drivers/mtd/spi/sst.c
@@ -99,6 +99,12 @@ static const struct sst_spi_flash_params
sst_spi_flash_table[] = {
.nr_sectors = 128,
.name = SST25WF040,
},
+ {
+ .idcode1 = 0x05,
+ .flags = SST_FEAT_WP,
+ .nr_sectors = 256,
+ .name = SST25WF080,
+ },
};
static int
--
1.8.3
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[U-Boot] [PATCH 0/3] spi: Add zynq spi controller
This small series patchset will add suuport for zynq spi controller, tested on sst flash. -- Thanks, Jagan. Jagannadha Sutradharudu Teki (3): spi: Add zynq spi controller driver sf: sst: Add support for SST25WF080 zynq: Enable CONFIG_ZYNQ_SPI arch/arm/include/asm/arch-zynq/hardware.h | 2 + drivers/mtd/spi/sst.c | 6 + drivers/spi/Makefile | 1 + drivers/spi/zynq_spi.c| 280 ++ include/configs/zynq.h| 10 ++ 5 files changed, 299 insertions(+) create mode 100644 drivers/spi/zynq_spi.c -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] wandboard: add pxe support, set default boot command like highbank
On Fri, Jul 26, 2013 at 9:20 PM, Dennis Gilmore
dgilm...@fedoraproject.org wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On Fri, 26 Jul 2013 10:52:04 -0300
Otavio Salvador ota...@ossystems.com.br wrote:
On Thu, Jul 25, 2013 at 6:13 PM, dgilm...@fedoraproject.org wrote:
From: Dennis Gilmore den...@ausil.us
highbank? what does this means?
calxeda highbank. the overall goal of this patch set is to simplify
things for distros to support the wandboard
So this should be explained in commit log. I didn't know what Calxeda
Highbank was until I searched Google but this is not important to be
in commit log but it is important to be explained the goal of patch
and why.
Signed-off-by: Dennis Gilmore den...@ausil.us
---
include/configs/wandboard.h | 42
+++--- 1 file changed, 39
insertions(+), 3 deletions(-)
diff --git a/include/configs/wandboard.h
b/include/configs/wandboard.h index ee6bf21..a5052c5 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -58,6 +58,8 @@
#define CONFIG_LOADADDR0x1200
#define CONFIG_SYS_TEXT_BASE 0x1780
+#define CONFIG_SUPPORT_RAW_INITRD
+
/* MMC Configuration */
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
@@ -72,6 +74,14 @@
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
+/* PXE support */
+#define CONFIG_BOOTP_PXE
+#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
+#define CONFIG_BOOTP_VCI_STRING U-boot.armv7.wandboard
+#define CONFIG_CMD_PXE
+#define CONFIG_MENU
+
+
Please use a single empty line.
/* Ethernet Configuration */
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
@@ -117,7 +127,32 @@
initrd_high=0x\0 \
fdt_file= CONFIG_DEFAULT_FDT_FILE \0 \
fdt_addr=0x1100\0 \
+ pxefile_addr_r=0x1200\0 \
+ kernel_addr_r=0x1300\0 \
+ ramdisk_addr_r=0x3200\0 \
+ fdt_addr_r=0x1100\0 \
Seems some vars are duplicated.
the cmd_pxe.c code requires the _r versions
So rework the other variables and avoid duplicating those.
boot_fdt=try\0 \
+ bootcmd_setup=mmc rescan\0 \
+ bootcmd_pxe=setenv bootfile \\ ;dhcp; pxe get; pxe
boot\0 \
+ bootcmd_disk_scr=ext2load ${boot_ifc} ${bootdevice}
${scr_addr_r} boot.scr source ${scr_addr_r}\0 \
+ bootcmd_disk_sysboot1=setenv
bootfile /boot/extlinux/extlinux.conf; sysboot ${boot_ifc}
${bootdevice} ext2\0 \
+ bootcmd_disk_sysboot2=setenv
bootfile /extlinux/extlinux.conf; sysboot ${boot_ifc} ${bootdevice}
ext2\0 \
+ bootcmd_disk_uenv=ext2load ${boot_ifc} ${bootdevice}
${uenv_addr_r} uEnv.txt; env import -t ${uenv_addr_r} ${filesize};
run bootcmd_uenv\0 \
+ bootcmd_disk_kernel=ext2load ${boot_ifc} ${bootdevice}
${kernel_addr_r} vmlinuz ext2load ${boot_ifc} ${bootdevice}
${ramdisk_addr_r} initrd.img bootz ${kernel_addr_r}
${ramdisk_addr_r}:${filesize} ${fdt_addr}\0 \
+ bootcmd_disk=run bootcmd_disk_sysboot1; run
bootcmd_disk_sysboot2; run bootcmd_disk_uenv; run bootcmd_disk_scr;
run bootcmd_disk_kernel\0 \
+ bootcmd_sata=setenv boot_ifc scsi; scsi scan run
bootcmd_disk\0 \
+ bootcmd_mmc=setenv boot_ifc mmc; mmc rescan run
bootcmd_disk\0 \
+ bootcmd_default=run bootcmd_mmc; run bootcmd_sata; run
bootcmd_pxe\0 \
+ bootcmd0=run bootcmd_setup; run bootcmd_default\0 \
+ bootcmd1=run bootcmd_setup; run bootcmd_pxe; run
bootcmd_default\0 \
+ bootcmd2=run bootcmd_setup; run bootcmd_sata; run
bootcmd_default\0 \
+ bootcmd15=run bootcmd_setup; run bootcmd_mmc; run
bootcmd_default\0 \
This all is need? We could have a way to make this extendable and
don't have it all duplicated.
it provides a simple way to setup different boot orders.
I understand what it does but it can be simplified using a single
bootcmd_base or so and this to use an extra var to choose
bootcmd_foo.
The 0, 1, 2 and 15 suffix are due any reason?
+ localcmd=run bootcmd_sata\0 \
+ bootdevice=0\0 \
+ bootargs=console=ttymxc0 root=LABEL=rootfs\0 \
+ bootdelay=2\0 \
+ bootretry=90\0 \
+ netretry=once\0 \
ip_dyn=yes\0 \
mmcdev= __stringify(CONFIG_SYS_MMC_ENV_DEV) \0 \
mmcpart=1\0 \
@@ -139,11 +174,11 @@
mmcargs=setenv bootargs console=${console},${baudrate} \
root=${mmcroot}\0 \
loadbootscript= \
- fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
${script};\0 \
+ load mmc ${mmcdev}:${mmcpart} ${loadaddr}
${script};\0 \ bootscript=echo Running bootscript from mmc ...;
\ source\0 \
- loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
${uimage}\0 \
- loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr}
${fdt_file}\0 \
+ loaduimage=load mmc
Re: [U-Boot] common/cmd_nand.c license terms
On 07/28/2013 07:31:00 AM, Wolfgang Denk wrote: Dear Scott, with commit ea533c2 cmd_nand: some infrastructure fixes and refactoring (Mon Aug 02, 2010), you added the following license header to common/cmd_nand.c : + * Copyright 2010 Freescale Semiconductor + * The portions of this file whose copyright is held by Freescale and which + * are not considered a derived work of GPL v2-only code may be distributed + * and/or modified under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. Looking at this commit, it is totally unclear to me which parts of the newly added code you could be referring to with your which are not considered a derived work of GPL v2-only code. Your addition makes the legal situation of the whole file pretty much indeterminable. Could you please be so kind and explain what exactly your intention was, and what exactly yuou were referring to? The license of the whole file is GPLv2 only. The intent was to preemptively grant relicensing permission for GPLv2 or later, if a similar agreement could be reached from other copyright holders, or if the file eventually changes to the point where none of the original v2-only code remains, and if what is left isn't considered derivative of that older code. Likewise, it could be useful (in conjunction with git history) if code gets moved from one file to another. As for which parts are considered a derivative, I am not a lawyer and can't answer that. It's not a licensing question, but rather a basic copyright question. The point is that it wouldn't be Freescale raising a copyright complaint[1] if you were to license it as v2 or later. It was a response to your asking for no more v2-only code in U-Boot. We can remove the above text (except the actual copyright line) and make it clearly v2-only if you'd prefer. -Scott [1] If you were to actually relicense U-Boot to v3, we'd have a different sort of complaint, in that we'd probably want to fork, but that's separate from licensing. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] SPDX-License-Identifier: adding a comment section?
Dear Tom, In message 51f666a4.9060...@ti.com you wrote: drivers/net/ne2000.h drivers/net/ne2000.c drivers/net/ne2000_base.h drivers/net/ne2000_base.c ... I grabbed (because of the omap watchdog patch) 2.4.17, and that's (a) older than our ne2k driver and (b) Already a GPLv2 and not 'or later'. This is, I think, GPL-2.0. I see. Thanks for pointing out. SPDX-License-Comments: which could be used to mark a text section that would contain such explanations. Wound this make sense, or do you have a better suggestion? Sounds good. In this case we would say something like Linux Kernel driver and eCos driver files both used as reference. Right. Thanks ! Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de If a packet hits a pocket on a socket on a port, And the bus is interrupted as a very last resort, And the address of the memory makes your floppy disk abort, Then the socket packet pocket has an error to report! - Ken Burchill? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] common/cmd_nand.c license terms
Dear Scott, In message 1375127231.30721.54@snotra you wrote: Looking at this commit, it is totally unclear to me which parts of the newly added code you could be referring to with your which are not considered a derived work of GPL v2-only code. Your addition makes the legal situation of the whole file pretty much indeterminable. Could you please be so kind and explain what exactly your intention was, and what exactly yuou were referring to? The license of the whole file is GPLv2 only. The intent was to Is it? Why so? It appears that the first versions of that file did not include any license header at all, which means they were contributed under the project-wide GPLv2+ license. Only your commit added - 7 years later! - a GPLv2 only license header, and I really wonder what the base for this change would be? preemptively grant relicensing permission for GPLv2 or later, if a similar agreement could be reached from other copyright holders, or if the file eventually changes to the point where none of the original v2-only code remains, and if what is left isn't considered derivative Which original v2-only code are you referring to? As for which parts are considered a derivative, I am not a lawyer and can't answer that. It's not a licensing question, but rather a basic copyright question. The point is that it wouldn't be Freescale raising a copyright complaint[1] if you were to license it as v2 or later. It was a response to your asking for no more v2-only code in U-Boot. We can remove the above text (except the actual copyright line) and make it clearly v2-only if you'd prefer. I fail to see where your v2-only notion is coming from. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de I had the rare misfortune of being one of the first people to try and implement a PL/1 compiler. -- T. Cheatham ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Query: Ethernet switch support
Dear Bhupesh, In message a1a6ea40f8503d48bb002b42bd65974e0a0c9...@039-sn2mpn1-012.039d.mgd.msft.net you wrote: I am trying to add support of a Vitesse L2 switch in u-boot (in unmanaged configuration). I was analyzing whether advanced features like flow control, link-aggregation etc are required to be supported for a L2 switch working in a u-boot bootloader level. ... But, I am not sure about the design approaches used to support previous switch modules in u-boot. Things depend _heavily_ on your specific project requiremnts. IF all you need is a working network port then you can probably do with just the default initialization, determined by the pin strapping (i. e. your hardware guys should just to The Right Thing (TM) ). However, if you run a device in a security sensitive environment, it may be strictly forbidden to run the switch even for very short periods in some open configuration that would - for example - allow access from the outside to some (normally) protected inner networks. There is at least one board configuration in mainline which performs a full switch initialization in a time-optimized manner (by just down- loading a register dump to the switch); see enbw_cmc_config_switch() in board/enbw/enbw_cmc/enbw_cmc.c Normally, you should probably leave the switch just turned off / disabled and wait until proper application code in Linux can perform the needed initalizations. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de CAUTION: The Mass of This Product Contains the Energy Equivalent of 85 Million Tons of TNT per Net Ounce of Weight. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 1/1] socfpga: Adding configuration for development kit
Separating the configuration file for Virtual
Target and real hardware Cyclone V development kit
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v2:
- Fixed the word wrap issue within patch
Changes for v3:
- Fixed the long subject of the patch
Changes for v4:
- Added change log for each revision change
Changes for v5:
- Added Reviewed-by: Pavel Machek
- Cc: Tom Rini
---
include/configs/socfpga_cyclone5.h | 28 +---
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/include/configs/socfpga_cyclone5.h
b/include/configs/socfpga_cyclone5.h
index b5a7a9a..06aeba6 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -11,6 +11,8 @@
/*
* High level configuration
*/
+/* Virtual target or real hardware */
+#define CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_ARMV7
#define CONFIG_L2_OFF
@@ -21,11 +23,12 @@
#define CONFIG_SINGLE_BOOTLOADER
#define CONFIG_SOCFPGA
+/* base address for .text section */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_SYS_TEXT_BASE 0x0840
-#define V_NS16550_CLK 100
-#define CONFIG_BAUDRATE57600
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_TIMER_CLOCK_KHZ 2400
+#else
+#define CONFIG_SYS_TEXT_BASE 0x0140
+#endif
#define CONFIG_SYS_LOAD_ADDR 0x7fc0
/* Console I/O Buffer Size */
@@ -154,7 +157,7 @@
/* SDRAM Bank #1 */
#define CONFIG_SYS_SDRAM_BASE 0x
/* SDRAM memory size */
-#define PHYS_SDRAM_1_SIZE 0x8000
+#define PHYS_SDRAM_1_SIZE 0x4000
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_START 0x
@@ -170,8 +173,13 @@
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1UART0_BASE
-
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define V_NS16550_CLK 100
+#else
+#define V_NS16550_CLK 1
+#endif
+#define CONFIG_BAUDRATE115200
/*
* FLASH
@@ -184,9 +192,15 @@
/* This timer use eosc1 where the clock frequency is fixed
* throughout any condition */
#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
-
/* reload value when timer count to zero */
#define TIMER_LOAD_VAL 0x
+/* Timer info */
+#define CONFIG_SYS_HZ 1000
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_TIMER_CLOCK_KHZ 2400
+#else
+#define CONFIG_TIMER_CLOCK_KHZ 25000
+#endif
#define CONFIG_ENV_IS_NOWHERE
--
1.7.9.5
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[U-Boot] [PATCH v6 1/2] socfpga: Adding System Manager driver
Adding System Manager driver which will configure the
pin mux for real hardware Cyclone V development kit
(not Virtual Platform)
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v2:
- Fixed the word wrap issue within patch
Changes for v3:
- Fixed the long subject of the patch
- Fixed the comment within the code
Changes for v4:
- Added change log for each revision change
Changes for v5:
- Updated the license header for system_manager.c
- Cc: Tom Rini
Changes for v6:
- Updated the license header for system_manager.c and .h to SPDX
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/spl.c |6
arch/arm/cpu/armv7/socfpga/system_manager.c| 29
.../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
arch/arm/include/asm/arch-socfpga/system_manager.h | 22 +++
board/altera/socfpga/Makefile |4 ++-
include/configs/socfpga_cyclone5.h |1 +
7 files changed, 63 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/system_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/system_manager.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 5024fc5..0859e44 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -13,7 +13,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
-COBJS-y:= misc.o timer.o reset_manager.o
+COBJS-y:= misc.o timer.o reset_manager.o system_manager.o
COBJS-$(CONFIG_SPL_BUILD) += spl.o
COBJS := $(COBJS-y)
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index 2b9be28..74bceab 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -12,6 +12,7 @@
#include image.h
#include asm/arch/reset_manager.h
#include spl.h
+#include asm/arch/system_manager.h
DECLARE_GLOBAL_DATA_PTR;
@@ -25,6 +26,11 @@ u32 spl_boot_device(void)
*/
void spl_board_init(void)
{
+#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+ /* configure the pin muxing through system manager */
+ sysmgr_pinmux_init();
+#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
+
/* de-assert reset for peripherals and bridges based on handoff */
reset_deassert_peripherals_handoff();
diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c
b/arch/arm/cpu/armv7/socfpga/system_manager.c
new file mode 100644
index 000..0b1bb33
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/system_manager.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright Altera Corporation (C) 2013
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/system_manager.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Configure all the pin muxes
+ */
+void sysmgr_pinmux_init(void)
+{
+ unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET;
+
+ const unsigned long *pval = sys_mgr_init_table;
+ unsigned long i;
+
+ for (i = 0; i ARRAY_SIZE(sys_mgr_init_table);
+ i++, offset += sizeof(unsigned long)) {
+ writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset));
+ }
+}
+
+
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
index 1182a13..50c4ebd 100644
--- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -12,5 +12,6 @@
#define SOCFPGA_UART1_ADDRESS 0xffc03000
#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
#endif /* _SOCFPGA_BASE_ADDRS_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h
b/arch/arm/include/asm/arch-socfpga/system_manager.h
new file mode 100644
index 000..36a83b4
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/system_manager.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright Altera Corporation (C) 2013
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef_SYSTEM_MANAGER_H_
+#define_SYSTEM_MANAGER_H_
+
+#ifndef __ASSEMBLY__
+
+void sysmgr_pinmux_init(void);
+
+/* declaration for handoff table type */
+extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM];
+
+#endif
+
+
+#define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400)
+
+#endif /* _SYSTEM_MANAGER_H_ */
diff --git a/board/altera/socfpga/Makefile b/board/altera/socfpga/Makefile
index 101fc7c..9dc45a9 100644
--- a/board/altera/socfpga/Makefile
+++ b/board/altera/socfpga/Makefile
@@ -10,8 +10,10 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(BOARD).o
-COBJS := socfpga_cyclone5.o
+COBJS-y:=
[U-Boot] [PATCH v5 2/2] socfpga: Adding pin mux handoff files
Adding the generated pin mux
configuration by Preloader Generator tool
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v2:
- Fixed the word wrap issue within patch
Changes for v3:
- Fixed the long subject of the patch
Changes for v4:
- Added change log for each revision change
Changes for v5:
- Updated the license header for reset_manager.c
- Updated the subject
---
board/altera/socfpga/pinmux_config.c | 214 ++
board/altera/socfpga/pinmux_config.h | 54 +
2 files changed, 268 insertions(+)
create mode 100644 board/altera/socfpga/pinmux_config.c
create mode 100644 board/altera/socfpga/pinmux_config.h
diff --git a/board/altera/socfpga/pinmux_config.c
b/board/altera/socfpga/pinmux_config.c
new file mode 100644
index 000..8b09005
--- /dev/null
+++ b/board/altera/socfpga/pinmux_config.c
@@ -0,0 +1,214 @@
+/* This file is generated by Preloader Generator */
+
+#include pinmux_config.h
+
+/* pin mux configuration data */
+unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
+ 0, /* EMACIO0 - Unused */
+ 2, /* EMACIO1 - USB */
+ 2, /* EMACIO2 - USB */
+ 2, /* EMACIO3 - USB */
+ 2, /* EMACIO4 - USB */
+ 2, /* EMACIO5 - USB */
+ 2, /* EMACIO6 - USB */
+ 2, /* EMACIO7 - USB */
+ 2, /* EMACIO8 - USB */
+ 0, /* EMACIO9 - Unused */
+ 2, /* EMACIO10 - USB */
+ 2, /* EMACIO11 - USB */
+ 2, /* EMACIO12 - USB */
+ 2, /* EMACIO13 - USB */
+ 0, /* EMACIO14 - N/A */
+ 0, /* EMACIO15 - N/A */
+ 0, /* EMACIO16 - N/A */
+ 0, /* EMACIO17 - N/A */
+ 0, /* EMACIO18 - N/A */
+ 0, /* EMACIO19 - N/A */
+ 3, /* FLASHIO0 - SDMMC */
+ 3, /* FLASHIO1 - SDMMC */
+ 3, /* FLASHIO2 - SDMMC */
+ 3, /* FLASHIO3 - SDMMC */
+ 0, /* FLASHIO4 - SDMMC */
+ 0, /* FLASHIO5 - SDMMC */
+ 0, /* FLASHIO6 - SDMMC */
+ 0, /* FLASHIO7 - SDMMC */
+ 0, /* FLASHIO8 - SDMMC */
+ 3, /* FLASHIO9 - SDMMC */
+ 3, /* FLASHIO10 - SDMMC */
+ 3, /* FLASHIO11 - SDMMC */
+ 3, /* GENERALIO0 - TRACE */
+ 3, /* GENERALIO1 - TRACE */
+ 3, /* GENERALIO2 - TRACE */
+ 3, /* GENERALIO3 - TRACE */
+ 3, /* GENERALIO4 - TRACE */
+ 3, /* GENERALIO5 - TRACE */
+ 3, /* GENERALIO6 - TRACE */
+ 3, /* GENERALIO7 - TRACE */
+ 3, /* GENERALIO8 - TRACE */
+ 3, /* GENERALIO9 - SPIM0 */
+ 3, /* GENERALIO10 - SPIM0 */
+ 3, /* GENERALIO11 - SPIM0 */
+ 3, /* GENERALIO12 - SPIM0 */
+ 2, /* GENERALIO13 - CAN0 */
+ 2, /* GENERALIO14 - CAN0 */
+ 3, /* GENERALIO15 - I2C0 */
+ 3, /* GENERALIO16 - I2C0 */
+ 2, /* GENERALIO17 - UART0 */
+ 2, /* GENERALIO18 - UART0 */
+ 0, /* GENERALIO19 - N/A */
+ 0, /* GENERALIO20 - N/A */
+ 0, /* GENERALIO21 - N/A */
+ 0, /* GENERALIO22 - N/A */
+ 0, /* GENERALIO23 - N/A */
+ 0, /* GENERALIO24 - N/A */
+ 0, /* GENERALIO25 - N/A */
+ 0, /* GENERALIO26 - N/A */
+ 0, /* GENERALIO27 - N/A */
+ 0, /* GENERALIO28 - N/A */
+ 0, /* GENERALIO29 - N/A */
+ 0, /* GENERALIO30 - N/A */
+ 0, /* GENERALIO31 - N/A */
+ 2, /* MIXED1IO0 - EMAC */
+ 2, /* MIXED1IO1 - EMAC */
+ 2, /* MIXED1IO2 - EMAC */
+ 2, /* MIXED1IO3 - EMAC */
+ 2, /* MIXED1IO4 - EMAC */
+ 2, /* MIXED1IO5 - EMAC */
+ 2, /* MIXED1IO6 - EMAC */
+ 2, /* MIXED1IO7 - EMAC */
+ 2, /* MIXED1IO8 - EMAC */
+ 2, /* MIXED1IO9 - EMAC */
+ 2, /* MIXED1IO10 - EMAC */
+ 2, /* MIXED1IO11 - EMAC */
+ 2, /* MIXED1IO12 - EMAC */
+ 2, /* MIXED1IO13 - EMAC */
+ 0, /* MIXED1IO14 - Unused */
+ 3, /* MIXED1IO15 - QSPI */
+ 3, /* MIXED1IO16 - QSPI */
+ 3, /* MIXED1IO17 - QSPI */
+ 3, /* MIXED1IO18 - QSPI */
+ 3, /* MIXED1IO19 - QSPI */
+ 3, /* MIXED1IO20 - QSPI */
+ 0, /* MIXED1IO21 - GPIO */
+ 0, /* MIXED2IO0 - N/A */
+ 0, /* MIXED2IO1 - N/A */
+ 0, /* MIXED2IO2 - N/A */
+ 0, /* MIXED2IO3 - N/A */
+ 0, /* MIXED2IO4 - N/A */
+ 0, /* MIXED2IO5 - N/A */
+ 0, /* MIXED2IO6 - N/A */
+ 0, /* MIXED2IO7 - N/A */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /*
[U-Boot] [PATCH v5 1/1] socfpga: Creating driver for Reset Manager
Consolidating reset code into reset_manager.c.
Also separating reset configuration for virtual target
and real hardware Cyclone V development kit
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v2:
- Fixed the long subject of the patch
- Consolidated the reset_manager structure between virtual target and dev kit
Changes for v3:
- Added change log for each revision change
- Removed the between the date of copyright header
Changes for v4:
- Updated the license header for reset_manager.c
Changes for v5:
- Updated the license header for reset_manager.c to SPDX
---
arch/arm/cpu/armv7/socfpga/Makefile |2 +-
arch/arm/cpu/armv7/socfpga/misc.c | 27 --
arch/arm/cpu/armv7/socfpga/reset_manager.c| 40 +
arch/arm/include/asm/arch-socfpga/reset_manager.h | 10 --
4 files changed, 48 insertions(+), 31 deletions(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/reset_manager.c
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 3b48ac9..5024fc5 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -13,7 +13,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
-COBJS-y:= misc.o timer.o
+COBJS-y:= misc.o timer.o reset_manager.o
COBJS-$(CONFIG_SPL_BUILD) += spl.o
COBJS := $(COBJS-y)
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
b/arch/arm/cpu/armv7/socfpga/misc.c
index 66edb3c..2f1c716 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -6,36 +6,9 @@
#include common.h
#include asm/io.h
-#include asm/arch/reset_manager.h
DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_reset_manager *reset_manager_base =
- (void *)SOCFPGA_RSTMGR_ADDRESS;
-
-/*
- * Write the reset manager register to cause reset
- */
-void reset_cpu(ulong addr)
-{
- /* request a warm reset */
- writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, reset_manager_base-ctrl);
- /*
-* infinite loop here as watchdog will trigger and reset
-* the processor
-*/
- while (1)
- ;
-}
-
-/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
-{
- writel(0, reset_manager_base-per_mod_reset);
-}
-
int dram_init(void)
{
gd-ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c
b/arch/arm/cpu/armv7/socfpga/reset_manager.c
new file mode 100644
index 000..2281743
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright Altera Corporation (C) 2013
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/reset_manager.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_reset_manager *reset_manager_base =
+ (void *)SOCFPGA_RSTMGR_ADDRESS;
+
+/*
+ * Write the reset manager register to cause reset
+ */
+void reset_cpu(ulong addr)
+{
+ /* request a warm reset */
+ writel((1 RSTMGR_CTRL_SWWARMRSTREQ_LSB),
+ reset_manager_base-ctrl);
+ /*
+* infinite loop here as watchdog will trigger and reset
+* the processor
+*/
+ while (1)
+ ;
+}
+
+/*
+ * Release peripherals from reset based on handoff
+ */
+void reset_deassert_peripherals_handoff(void)
+{
+ writel(0, reset_manager_base-per_mod_reset);
+}
+
+
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h
b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index 13d7357..3e95476 100644
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -11,16 +11,20 @@ void reset_cpu(ulong addr);
void reset_deassert_peripherals_handoff(void);
struct socfpga_reset_manager {
- u32 padding1;
+ u32 status;
u32 ctrl;
- u32 padding2;
- u32 padding3;
+ u32 counts;
+ u32 padding1;
u32 mpu_mod_reset;
u32 per_mod_reset;
u32 per2_mod_reset;
u32 brg_mod_reset;
};
+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
+#else
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+#endif
#endif /* _RESET_MANAGER_H_ */
--
1.7.9.5
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Re: [U-Boot] [PATCH 0/2] usb bug fixes
Dear Nikita Kiryanov, This series contains two usb related bug fixes, one regarding the power cycling of hub ports, and the other- a memory leak in ehci-hcd. Cc: Marek Vasut ma...@denx.de Cc: Igor Grinberg grinb...@compulab.co.il Nikita Kiryanov (2): usb_hub: fix power cycling logic ehci-hcd: fix memory leak in lowlevel init common/usb_hub.c| 4 ++-- drivers/usb/host/ehci-hcd.c | 4 +++- 2 files changed, 5 insertions(+), 3 deletions(-) Applied both, thanks! Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] common/cmd_nand.c license terms
On 07/29/2013 03:08:23 PM, Wolfgang Denk wrote: Dear Scott, In message 1375127231.30721.54@snotra you wrote: Looking at this commit, it is totally unclear to me which parts of the newly added code you could be referring to with your which are not considered a derived work of GPL v2-only code. Your addition makes the legal situation of the whole file pretty much indeterminable. Could you please be so kind and explain what exactly your intention was, and what exactly yuou were referring to? The license of the whole file is GPLv2 only. The intent was to Is it? Why so? It appears that the first versions of that file did not include any license header at all, which means they were contributed under the project-wide GPLv2+ license. Only your commit added - 7 years later! - a GPLv2 only license header, and I really wonder what the base for this change would be? Hmm... The same text appears in drivers/mtd/nand/nand_util.c, which does have a pre-existing v2-only header. I probably applied it to cmd_nand.c as well because it was unclear whether the existing code was also v2-only. The project-wide COPYING did not have the or later language until Jan 9 2011 (commit b9347188729992ef8282a2854889d8dcc25175aa), so it's not clear to me that the project-wide license was GPLv2+ at the time that the older cmd_nand.c code was submitted, or even at the time that I added the above text. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 4/7] ARM: switch to non-secure state during bootm execution
On Wed, Jul 10, 2013 at 01:54:16AM +0200, Andre Przywara wrote:
[...]
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 1b6e0ac..7b0619e 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -34,6 +34,10 @@
#include asm/bootm.h
#include linux/compiler.h
+#ifdef CONFIG_ARMV7_NONSEC
+#include asm/armv7.h
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
static struct tag *params;
@@ -186,6 +190,29 @@ static void setup_end_tag(bd_t *bd)
__weak void setup_board_tags(struct tag **in_params) {}
+static void do_nonsec_virt_switch(void)
+{
+#ifdef CONFIG_ARMV7_NONSEC
+ int ret;
+
+ ret = armv7_switch_nonsec();
+ switch (ret) {
+ case NONSEC_VIRT_SUCCESS:
+ debug(entered non-secure state\n);
+ break;
+ case NONSEC_ERR_NO_SEC_EXT:
+ printf(nonsec: Security extensions not implemented.\n);
+ break;
+ case NONSEC_ERR_NO_GIC_ADDRESS:
+ printf(nonsec: could not determine GIC address.\n);
+ break;
+ case NONSEC_ERR_GIC_ADDRESS_ABOVE_4GB:
+ printf(nonsec: PERIPHBASE is above 4 GB, no access.\n);
+ break;
+ }
+#endif
+}
I still don't get why you just don't make armv7_switch_nonsec a void and
print the error when they occur... ???
-Christoffer
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Re: [U-Boot] [PATCH v3 6/7] ARM: extend non-secure switch to also go into HYP mode
On Wed, Jul 10, 2013 at 01:54:18AM +0200, Andre Przywara wrote: For the KVM and XEN hypervisors to be usable, we need to enter the kernel in HYP mode. Now that we already are in non-secure state, HYP mode switching is within short reach. While doing the non-secure switch, we have to enable the HVC instruction and setup the HYP mode HVBAR (while still secure). The actual switch is done by dropping back from a HYP mode handler without actually leaving HYP mode, so we introduce a new handler routine in our new secure exception vector table. In the assembly switching routine we save and restore the banked LR and SP registers around the hypercall to do the actual HYP mode switch. The C routine first checks whether we are in HYP mode already and also whether the virtualization extensions are available. It also checks whether the HYP mode switch was finally successful. The bootm command part only adds and adjusts some error reporting. Signed-off-by: Andre Przywara andre.przyw...@linaro.org --- arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/nonsec_virt.S | 43 +++- arch/arm/cpu/armv7/virt-v7.c | 31 + arch/arm/include/asm/armv7.h | 9 +++-- arch/arm/lib/bootm.c | 19 +++--- 5 files changed, 93 insertions(+), 11 deletions(-) diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index b59f59e..e5eaa56 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -36,7 +36,7 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONF SOBJS+= lowlevel_init.o endif -ifneq ($(CONFIG_ARMV7_NONSEC),) +ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),) SOBJS += nonsec_virt.o COBJS+= virt-v7.o endif diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index f9b6b39..895c3b0 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -1,5 +1,5 @@ /* - * code for switching cores into non-secure state + * code for switching cores into non-secure state and into HYP mode * * Copyright (c) 2013Andre Przywara andre.przyw...@linaro.org * @@ -28,15 +28,16 @@ #include asm/armv7.h .arch_extension sec +.arch_extension virt -/* the vector table for secure state */ +/* the vector table for secure state and HYP mode */ _monitor_vectors: .word 0 /* reset */ .word 0 /* undef */ adr pc, _secure_monitor .word 0 .word 0 - .word 0 + adr pc, _hyp_trap .word 0 .word 0 .word 0 /* pad */ @@ -53,10 +54,27 @@ _secure_monitor: bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits orr r1, r1, #0x31 @ enable NS, AW, FW bits +#ifdef CONFIG_ARMV7_VIRT + mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 + and r0, r0, #CPUID_ARM_VIRT_MASK@ mask virtualization bits + cmp r0, #(1 CPUID_ARM_VIRT_SHIFT) + orreq r1, r1, #0x100 @ allow HVC instruction +#endif + mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set) +#ifdef CONFIG_ARMV7_VIRT + mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value + mcreq p15, 4, r0, c12, c0, 0 @ write HVBAR +#endif + movspc, lr @ return to non-secure SVC +_hyp_trap: + mrs lr, elr_hyp @ for older asm: .byte 0x00, 0xe3, 0x0e, 0xe1 this comment just confuses: either make it intelligent to support an older compiler or just get rid of these byte encodings. You can always disassemble the file and lookup the byte code with a modern compiler to get back to the byte encoding. + mov pc, lr @ do no switch modes, but + @ return to caller + /* * Secondary CPUs start here and call the code for the core specific parts * of the non-secure and HYP mode transition. The GIC distributor specific @@ -71,9 +89,13 @@ ENTRY(_smp_pen) mcr p15, 0, r1, c12, c0, 0 @ set VBAR bl _nonsec_init + mov r12, r0 @ save GICC address +#ifdef CONFIG_ARMV7_VIRT + bl _switch_to_hyp +#endif - ldr r1, [r0, #GICC_IAR] @ acknowledge IPI - str r1, [r0, #GICC_EOIR]@ signal end of interrupt + ldr r1, [r12, #GICC_IAR]@ acknowledge IPI + str r1, [r12, #GICC_EOIR] @ signal end of interrupt adr r1, _smp_pen waitloop: wfi @@ -164,3 +186,14 @@ ENTRY(_nonsec_init) bx lr ENDPROC(_nonsec_init) + +ENTRY(_switch_to_hyp) + mov r0, lr + mov r1, sp @ save SVC copy of LR and SP + isb did you find out that this isb is indeed
Re: [U-Boot] [PATCH v3 5/7] ARM: add SMP support for non-secure switch
On Wed, Jul 10, 2013 at 01:54:17AM +0200, Andre Przywara wrote:
Currently the non-secure switch is only done for the boot processor.
To enable full SMP support, we have to switch all secondary cores
into non-secure state also.
So we add an entry point for secondary CPUs coming out of low-power
state and make sure we put them into WFI again after having switched
to non-secure state.
For this we acknowledge and EOI the wake-up IPI, then go into WFI.
Once being kicked out of it later, we sanity check that the start
address has actually been changed (since another attempt to switch
to non-secure would block the core) and jump to the new address.
The actual CPU kick is done by sending an inter-processor interrupt
via the GIC to all CPU interfaces except the requesting processor.
The secondary cores will then setup their respective GIC CPU
interface.
The address secondary cores jump to is board specific, we provide
the value here for the Versatile Express board.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/nonsec_virt.S| 27 +++
arch/arm/cpu/armv7/virt-v7.c| 19 ++-
arch/arm/include/asm/armv7.h| 1 +
arch/arm/include/asm/gic.h | 2 ++
include/configs/vexpress_ca15_tc2.h | 3 +++
5 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S
b/arch/arm/cpu/armv7/nonsec_virt.S
index e9ee831..f9b6b39 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -58,6 +58,33 @@ _secure_monitor:
movspc, lr @ return to non-secure SVC
/*
+ * Secondary CPUs start here and call the code for the core specific parts
+ * of the non-secure and HYP mode transition. The GIC distributor specific
+ * code has already been executed by a C function before.
+ * Then they go back to wfi and wait to be woken up by the kernel again.
+ */
+ENTRY(_smp_pen)
+ mrs r0, cpsr
+ orr r0, r0, #0xc0
+ msr cpsr, r0@ disable interrupts
+ ldr r1, =_start
+ mcr p15, 0, r1, c12, c0, 0 @ set VBAR
+
+ bl _nonsec_init
+
+ ldr r1, [r0, #GICC_IAR] @ acknowledge IPI
+ str r1, [r0, #GICC_EOIR]@ signal end of interrupt
+ adr r1, _smp_pen
+waitloop:
+ wfi
+ ldr r0, =CONFIG_SYSFLAGS_ADDR @ load start address
You seem to have ignored my comment about using the sysflags name?
As I understand, the sysflags name is a versatile express specific
register name that just happens to be used for the SMP boot address as
well...
Therefore, this should really be CONFIG_SMP_BOOT_ADDR or something like
that, at the very least.
+ ldr r0, [r0]
+ cmp r0, r1 @ make sure we dont execute this code
+ beq waitloop@ again (due to a spurious wakeup)
+ mov pc, r0
+ENDPROC(_smp_pen)
+
+/*
* Switch a core to non-secure state.
*
* 1. initialize the GIC per-core interface
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index 54f9746..a0d0b34 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -77,6 +77,21 @@ static int get_gicd_base_address(unsigned int *gicdaddr)
#endif
}
+static void kick_secondary_cpus(unsigned int gicdaddr)
+{
+ unsigned int *secondary_boot_addr;
+
+ secondary_boot_addr = (void *)CONFIG_SYSFLAGS_ADDR;
+#ifdef CONFIG_SYSFLAGS_NEED_CLEAR_BITS
+ secondary_boot_addr[1] = (unsigned)-1;
+#endif
again, if you disagreed with my previous comment, please comment on it
and rationalize your choice.
I still feel you're wrapping board specific logic into generic code, and
that you should call out to a more generic function. Imagine an SOC
that uses an implementation defined control register for this instead of
a memory address...
perhaps what you need is:
void set_board_smp_boot_addr(unsigned long addr);
unsigned long get_board_smp_boot_addr(void);
and call these instead of your direct use of sysflags addr here...?
+ *secondary_boot_addr = (uintptr_t)_smp_pen;
+ dmb();
+
+ /* now kick all CPUs (except this one) by writing to GICD_SGIR */
+ writel(1U 24, gicdaddr + GICD_SGIR);
+}
+
enum nonsec_virt_errors armv7_switch_nonsec(void)
{
unsigned int reg, ret;
@@ -110,7 +125,9 @@ enum nonsec_virt_errors armv7_switch_nonsec(void)
for (i = 0; i = itlinesnr; i++)
writel((unsigned)-1, gicdaddr + GICD_IGROUPRn + 4 * i);
- /* call the non-sec switching code on this CPU */
+ kick_secondary_cpus(gicdaddr);
+
+ /* call the non-sec switching code on this CPU also */
_nonsec_init();
return NONSEC_VIRT_SUCCESS;
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index e5c0279..f6582a1 100644
---
Re: [U-Boot] [PATCH v3 2/7] ARM: add secure monitor handler to switch to non-secure state
n Wed, Jul 10, 2013 at 01:54:14AM +0200, Andre Przywara wrote: A prerequisite for using virtualization is to be in HYP mode, which requires the CPU to be in non-secure state first. Add new file in arch/arm/cpu/armv7 to hold a monitor handler routine which switches the CPU to non-secure state by setting the NS and associated bits. According to the ARM architecture reference manual this should not be done in SVC mode, so we have to setup a SMC handler for this. We create a new vector table to avoid interference with other boards. The MVBAR register will be programmed later just before the smc call. Signed-off-by: Andre Przywara andre.przyw...@linaro.org --- arch/arm/cpu/armv7/Makefile | 4 +++ arch/arm/cpu/armv7/nonsec_virt.S | 54 2 files changed, 58 insertions(+) create mode 100644 arch/arm/cpu/armv7/nonsec_virt.S diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 7a8c2d0..5d75077 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -36,6 +36,10 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONF SOBJS+= lowlevel_init.o endif +ifneq ($(CONFIG_ARMV7_NONSEC),) +SOBJS += nonsec_virt.o +endif + SRCS := $(START:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) START:= $(addprefix $(obj),$(START)) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S new file mode 100644 index 000..68a6b38 --- /dev/null +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -0,0 +1,54 @@ +/* + * code for switching cores into non-secure state + * + * Copyright (c) 2013Andre Przywara andre.przyw...@linaro.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include config.h + +/* the vector table for secure state */ +_monitor_vectors: + .word 0 /* reset */ + .word 0 /* undef */ + adr pc, _secure_monitor + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 /* pad */ + +/* + * software interrupt aka. secure monitor handler a software interrupt is not aka. a secure monitor handler, this is misleading, it's just the smc handler. + * This is executed on a smc instruction, we use a smc #0 to switch + * to non-secure state. + * We use only r0 and r1 here, due to constraints in the caller. + */ + .align 5 +_secure_monitor: + mrc p15, 0, r1, c1, c1, 0 @ read SCR + bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits + orr r1, r1, #0x31 @ enable NS, AW, FW bits + + mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set) + + movspc, lr @ return to non-secure SVC + -- 1.7.12.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 4/4] Update u-boot-nand.bin to be used with spl
On 07/28/2013 03:16:56 PM, Philippe Reynes wrote:
Signed-off-by: Philippe Reynes trem...@yahoo.fr
Signed-off-by: Eric Jarrige eric.jarr...@armadeus.org
---
Makefile |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/Makefile b/Makefile
index 4218226..b971f30 100644
--- a/Makefile
+++ b/Makefile
@@ -617,8 +617,14 @@ $(obj)u-boot.lds: $(LDSCRIPT)
nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend
$(MAKE) -C nand_spl/board/$(BOARDDIR) all
+ifeq ($(CONFIG_SPL),y)
+$(obj)u-boot-nand.bin:$(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO)
-O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin \
+ cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin
$(obj)u-boot-nand.bin
+else
$(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin
cat $(obj)nand_spl/u-boot-spl-16k.bin
$(obj)u-boot.bin $(obj)u-boot-nand.bin
+endif
$(obj)spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend
$(MAKE) -C spl all
u-boot-nand.bin is from the legacy nand_spl subsystem. You should be
using u-boot-with-spl.bin if you want this sort of image concatenation
with the new SPL.
-Scott
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Re: [U-Boot] [PATCH v7 03/11] nand: add Faraday FTNANDC021 NAND controller support
On 07/29/2013 12:51:45 AM, Kuo-Jung Su wrote: From: Kuo-Jung Su dant...@faraday-tech.com Faraday FTNANDC021 is an integrated NAND flash controller. It use a build-in command table to abstract the underlying NAND flash control logic. For example: Issuing a command 0x10 to FTNANDC021 would result in a page write + a read status operation. Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com CC: Albert ARIBAUD albert.u.b...@aribaud.net CC: Scott Wood scottw...@freescale.com --- Changes for v7: - ftnandc021.[ch]: Update license to use SPDX identifiers. - ftnandc021.c: put_unaligned() - memcpy() - ftnandc021.c: update ecc relatived function prototypes to fix compile warnnings. [snip] +#include common.h +#include asm/errno.h +#include asm/io.h +#include asm/unaligned.h +#include nand.h +#include malloc.h asm/unaligned.h can come out now that you've switched to memcpy()... In any case: Acked-by: Scott Wood scottw...@freescale.com -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7 03/11] nand: add Faraday FTNANDC021 NAND controller support
2013/7/30 Scott Wood scottw...@freescale.com: On 07/29/2013 12:51:45 AM, Kuo-Jung Su wrote: From: Kuo-Jung Su dant...@faraday-tech.com Faraday FTNANDC021 is an integrated NAND flash controller. It use a build-in command table to abstract the underlying NAND flash control logic. For example: Issuing a command 0x10 to FTNANDC021 would result in a page write + a read status operation. Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com CC: Albert ARIBAUD albert.u.b...@aribaud.net CC: Scott Wood scottw...@freescale.com --- Changes for v7: - ftnandc021.[ch]: Update license to use SPDX identifiers. - ftnandc021.c: put_unaligned() - memcpy() - ftnandc021.c: update ecc relatived function prototypes to fix compile warnnings. [snip] +#include common.h +#include asm/errno.h +#include asm/io.h +#include asm/unaligned.h +#include nand.h +#include malloc.h asm/unaligned.h can come out now that you've switched to memcpy()... In any case: Acked-by: Scott Wood scottw...@freescale.com Got it, thanks. I'll make a separate cosmetic patch for it. (or probably in V8) -- Best wishes, Kuo-Jung Su ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-ti/master
Hey, The following changes since commit 8b485ba12b0defa0c4ed3559789250238f8331a8: Merge branch 'u-boot/master' into u-boot-arm/master (2013-07-25 17:57:46 +0200) are available in the git repository at: git://git.denx.de/u-boot-ti.git master for you to fetch changes up to bb2a5d8f87fffb4fadfb205837decbd1b3e75f88: gpio: omap5-uevm: Configure the tca6424 gpio expander (2013-07-29 18:09:26 -0400) Andreas Bie??mann (1): omap3/sys_info: fix printout of OMAP36XX L3 freqency Christian Riesch (1): da850evm: Use clrbits function with correct endianess Dan Murphy (2): gpio: tca642x: Add the tca642x gpio expander driver gpio: omap5-uevm: Configure the tca6424 gpio expander Heiko Schocher (1): net, phy, cpsw: fix gigabit register access Justin Waters (6): am335x_evm: Make NAND support modular am335x_evm: Add command line editing am335x_evm: Rework bootcmd to handle two MMC devs Add additional MLO images to .gitignore am335x_evm: Add support for eMMC environment am335x_evm: Add am335x_boneblack variant Lokesh Vutla (1): ARM: DRA7xx: Lock DPLL_GMAC Mugunthan V N (6): drivers: net: cpsw: remove hard coding bd ram for cpsw drivers: net: cpsw: Enable statistics for all port ARM: DRA7xx: Enable GMAC clock control ARM: DRA7xx: Add CPSW support to DRA7xx EVM ARM: DRA7xx: Add CPSW and MDIO pinmux support ARM: DRA7xx: Enable CPSW Ethernet support Nishanth Menon (6): omap3_beagle: remove JFFS2 support. omap3_beagle: replace uImage.beagle with generic uImage beagleboard: remove RevB support for BeagleBoard Xm omap3_beagle: enable CMD_FS_GENERIC and simplify load of image/ramdisk omap3_beagle: support findfdt and loadfdt for devicetree support omap3_beagle: support booting from zImage and device tree as last option Stefan Roese (1): arm: omap3: spl: Fix problem with 8bit NAND devices Steve Kipisz (2): am335x_evm: Add support for the NOR module on the memory cape am335x_evm: Add support to boot from NOR. Tom Rini (12): spl_mmc.c: Detect missing kernel image in RAW MMC README.falcon: Note how we determine if we can boot the OS or not am335x_evm: Correct DFU ALT settings for falcon mode am335x_evm: Update eMMC falcon mode locations am335x_evm: Correct CONFIG_CMD_SPL_WRITE_SIZE am335x_evm: Add basic README board/ti/am335x/README: Document NAND programming am335x_evm: Drop useless CONFIG_ENV_IS_NOWHERE am335x_evm: Update SPI_BOOT support, add MTDPARTS info am335x_evm: Rework board_is_foo() checks am33xx: Correct gpmc_cfg-irqstatus/enable board/ti/am335x/README: Document NOR programming .gitignore |2 +- arch/arm/cpu/armv7/am33xx/board.c |2 +- arch/arm/cpu/armv7/am33xx/emif4.c |6 +- arch/arm/cpu/armv7/am33xx/mem.c|8 +- arch/arm/cpu/armv7/omap-common/clocks-common.c | 18 ++ arch/arm/cpu/armv7/omap3/mem.c | 12 + arch/arm/cpu/armv7/omap3/sys_info.c|6 +- arch/arm/cpu/armv7/omap5/hw_data.c | 18 +- arch/arm/cpu/armv7/omap5/prcm-regs.c |7 + arch/arm/include/asm/arch-am33xx/mem.h |9 + arch/arm/include/asm/arch-omap5/cpu.h |6 + arch/arm/include/asm/arch-omap5/omap.h | 26 ++ arch/arm/include/asm/omap_common.h | 10 + board/davinci/da8xxevm/da850evm.c | 14 +- board/ti/am335x/Makefile |2 +- board/ti/am335x/README | 161 board/ti/am335x/board.c| 121 + board/ti/am335x/board.h| 31 +++ board/ti/am335x/mux.c | 65 - board/ti/am335x/u-boot.lds | 117 + board/ti/beagle/beagle.c | 28 +- board/ti/beagle/beagle.h |3 +- board/ti/dra7xx/evm.c | 150 ++- board/ti/dra7xx/mux_data.h | 14 + board/ti/omap5_uevm/evm.c | 22 ++ board/ti/omap5_uevm/mux_data.h |2 + board/ti/ti814x/evm.c |1 + boards.cfg | 17 +- common/spl/spl_mmc.c |4 + doc/README.falcon |2 + drivers/gpio/Makefile |1 + drivers/gpio/tca642x.c | 333 drivers/net/cpsw.c |7 +- drivers/net/phy/phy.c |6 +- include/configs/am335x_evm.h | 225 ++-- include/configs/dra7xx_evm.h | 19 ++
[U-Boot] [PATCH] config.mk: Add -Wundef to CFLAGS
In U-boot source, some '#if' directives evaluate undefined identifiers. To find and fix them, this commit adds -Wundef to CFLAGS. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- config.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config.mk b/config.mk index f71e145..7a92ae3 100644 --- a/config.mk +++ b/config.mk @@ -259,7 +259,7 @@ CPPFLAGS += -I$(TOPDIR)/include CPPFLAGS += -fno-builtin -ffreestanding -nostdinc \ -isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS) -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wundef ifdef BUILD_TAG CFLAGS += -DBUILD_TAG='$(BUILD_TAG)' -- 1.8.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Query: Ethernet switch support
Hi Albert, Thanks for your reply. -Original Message- From: Albert ARIBAUD [mailto:albert.u.b...@aribaud.net] Sent: Monday, July 29, 2013 10:27 PM To: Sharma Bhupesh-B45370 Cc: 'u-boot@lists.denx.de' Subject: Re: [U-Boot] Query: Ethernet switch support Hi Sharma, On Mon, 29 Jul 2013 15:33:39 +, Sharma Bhupesh-B45370 b45...@freescale.com wrote: Hi List, I am trying to add support of a Vitesse L2 switch in u-boot (in unmanaged configuration). I was analyzing whether advanced features like flow control, link-aggregation etc are required to be supported for a L2 switch working in a u-boot bootloader level. My point-of-view is that the L2 switch, should support only bare-minimum tftp of images, ping to other ethernet entities, bootp .. type of commands on u-boot and as such the L2 switch u-boot driver doesn't need to address flow-control and other such advanced features (probably of interest for a Linux device driver). But, I am not sure about the design approaches used to support previous switch modules in u-boot. Also I had a query whether there is a common switch framework in-place/under-consideration in u-boot, similar to what is already present in OpenWrt code: https://dev.openwrt.org/browser/trunk/package/boot/uboot-lantiq/patche s/0019-net-switchlib-add-framework-for-ethernet-switch-driv.patch?rev= 35292 Would porting this to u-boot make sense to have a common framework for ethernet switch in-place? Can you please let me know your views on the same and point me to any reference switch drivers that support these features. There is some support for switches in U-Boot (e.g. mv88e61xx) but no framework that I know of; and I suspect what is expected from the switch in U-Boot is that it does not hamper Ethernet operations, nothing more. for mv88e61xx, this is done through a fixed configuration. In my use-case also the L2 switch is supposed to be configured via a fixed configuration (setting up the switch in an unmanaged configuration). I will try to have a look the mv88e61xx example and then formulate something on similar lines. Regards, Bhupesh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 8/9] tegra: i2c: Enable new CONFIG_SYS_I2C framework
Hello Stephen,
Am 29.07.2013 18:12, schrieb Stephen Warren:
On 05/04/2013 06:01 AM, Heiko Schocher wrote:
From: Simon Glasss...@chromium.org
This enables CONFIG_SYS_I2C on Tegra, updating existing boards and the Tegra
i2c driver to support this.
Heiko, the latest U-Boot tree hangs during boot on Tegra, and git
:-(
Could you enable debug printf?
bisect points at this patch. Olof reported the issue to me.
Thanks!
Can you take a look at the code and see what might be wrong? Thanks.
Yep.
I suspect some kind of initialization ordering issue, since the boot
messages are:
-
U-Boot SPL 2013.07-rc3-00038-g880540d (Jul 29 2013 - 10:04:37)
U-Boot 2013.07-rc3-00038-g880540d (Jul 29 2013 - 10:04:37)
TEGRA30
Board: NVIDIA Beaver
I2C: Caller requested bad clock: periph=-49, parent=2
-
... and that bad clock message implies to me that the I2C driver is
initializing before it has parsed the correct clock ID out of device tree.
Hmm... looking in the patch ... I can see nothing which changes
some initializing order ...
@Simon: Do you have an idea?
just found some wrong settings for tegra30:
In include/configs/tegra30-common.h:
/* Total I2C ports on Tegra30 */
#define TEGRA_I2C_NUM_CONTROLLERS 5
README says:
- drivers/i2c/tegra_i2c.c:
- activate this driver with CONFIG_SYS_I2C_TEGRA
- This driver adds 4 i2c buses with a fix speed from
10 and the slave addr 0!
end yes, in the i2c driver are only 4 ports activated ... this
should be changed ... but I think, this has nothing to do with
your problem ... but try to add in the i2c driver one more i2c adapter
for the case TEGRA_I2C_NUM_CONTROLLERS 4
Some later commit causes the hang to happen right after printing I2C:,
without printing the bad clock message. I didn't investigate that,
since I'm assuming the root-cause is the same. Most likely some later
commit causes the uninitialized data to be a valid clock, yet not the
actual I2C clock, so the I2C clock still isn't turned on, and touching
HW (i.e. reading/writing the I2C registers) without a running clock on
Tegra caused hard hangs.
digging deeper, the above bad clock message
is a result from calling this function from the i2c driver:
./drivers/i2c/tegra_i2c.c:
static void i2c_init_controller(struct i2c_bus *i2c_bus)
{
/*
* Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
* here, in section 23.3.1, but in fact we seem to need a factor of
* 16 to get the right frequency.
*/
clock_start_periph_pll(i2c_bus-periph_id, CLOCK_ID_PERIPH,
i2c_bus-speed * 2 * 8);
Please enable debug printfs and look from where i2c_init_controller()
is called. You should see the following debug printf if it go the right
way (Just reading code, I have no HW ...)
process_nodes():
debug(%s: controller bus %d at %p, periph_id %d, speed %d: ,
is_dvc ? dvc : i2c, i, i2c_bus-regs,
i2c_bus-periph_id, i2c_bus-speed);
called from i2c_init_board in this driver.
This should be called from drivers/i2c/i2c_core.c i2c_init_all()
called from arch/arm/lib/board.c init_func_i2c()
I think i2c_bus-periph_id (periph=-49) is not setup right ... do
you have the correct dt?
bye,
Heiko
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Re: [U-Boot] [PATCH v3 8/9] tegra: i2c: Enable new CONFIG_SYS_I2C framework
Hi Heiko,
On Mon, Jul 29, 2013 at 10:28 PM, Heiko Schocher h...@denx.de wrote:
Hello Stephen,
Am 29.07.2013 18:12, schrieb Stephen Warren:
On 05/04/2013 06:01 AM, Heiko Schocher wrote:
From: Simon Glasss...@chromium.org
This enables CONFIG_SYS_I2C on Tegra, updating existing boards and the
Tegra
i2c driver to support this.
Heiko, the latest U-Boot tree hangs during boot on Tegra, and git
:-(
Could you enable debug printf?
bisect points at this patch. Olof reported the issue to me.
Thanks!
Can you take a look at the code and see what might be wrong? Thanks.
Yep.
I suspect some kind of initialization ordering issue, since the boot
messages are:
-
U-Boot SPL 2013.07-rc3-00038-g880540d (Jul 29 2013 - 10:04:37)
U-Boot 2013.07-rc3-00038-g880540d (Jul 29 2013 - 10:04:37)
TEGRA30
Board: NVIDIA Beaver
I2C: Caller requested bad clock: periph=-49, parent=2
-
... and that bad clock message implies to me that the I2C driver is
initializing before it has parsed the correct clock ID out of device tree.
Hmm... looking in the patch ... I can see nothing which changes
some initializing order ...
@Simon: Do you have an idea?
just found some wrong settings for tegra30:
In include/configs/tegra30-**common.h:
/* Total I2C ports on Tegra30 */
#define TEGRA_I2C_NUM_CONTROLLERS 5
README says:
- drivers/i2c/tegra_i2c.c:
- activate this driver with CONFIG_SYS_I2C_TEGRA
- This driver adds 4 i2c buses with a fix speed from
10 and the slave addr 0!
end yes, in the i2c driver are only 4 ports activated ... this
should be changed ... but I think, this has nothing to do with
your problem ... but try to add in the i2c driver one more i2c adapter
for the case TEGRA_I2C_NUM_CONTROLLERS 4
Some later commit causes the hang to happen right after printing I2C:,
without printing the bad clock message. I didn't investigate that,
since I'm assuming the root-cause is the same. Most likely some later
commit causes the uninitialized data to be a valid clock, yet not the
actual I2C clock, so the I2C clock still isn't turned on, and touching
HW (i.e. reading/writing the I2C registers) without a running clock on
Tegra caused hard hangs.
digging deeper, the above bad clock message
is a result from calling this function from the i2c driver:
./drivers/i2c/tegra_i2c.c:
static void i2c_init_controller(struct i2c_bus *i2c_bus)
{
/*
* Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
* here, in section 23.3.1, but in fact we seem to need a factor of
* 16 to get the right frequency.
*/
clock_start_periph_pll(i2c_**bus-periph_id, CLOCK_ID_PERIPH,
i2c_bus-speed * 2 * 8);
Please enable debug printfs and look from where i2c_init_controller()
is called. You should see the following debug printf if it go the right
way (Just reading code, I have no HW ...)
process_nodes():
debug(%s: controller bus %d at %p, periph_id %d, speed
%d: ,
is_dvc ? dvc : i2c, i, i2c_bus-regs,
i2c_bus-periph_id, i2c_bus-speed);
called from i2c_init_board in this driver.
This should be called from drivers/i2c/i2c_core.c i2c_init_all()
called from arch/arm/lib/board.c init_func_i2c()
I think i2c_bus-periph_id (periph=-49) is not setup right ... do
you have the correct dt?
I am not sure what is wrong here - Stephen if you have a board and can
debug please do, otherwise I might be able to dig one out.
49 looks to be PERIPH_ID_TVO.
Regards,
Simon
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[U-Boot] [PATCH v2 1/3] arm, spl: add watchdog library to SPL
Signed-off-by: Heiko Schocher h...@denx.de Cc: Tom Rini tr...@ti.com --- - changes for v2: none doc/README.SPL | 2 +- spl/Makefile | 1 + 2 Dateien geändert, 2 Zeilen hinzugefügt(+), 1 Zeile entfernt(-) diff --git a/doc/README.SPL b/doc/README.SPL index ac9a213..312a6a6 100644 --- a/doc/README.SPL +++ b/doc/README.SPL @@ -67,7 +67,7 @@ CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o) CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o) CONFIG_SPL_SPI_LOAD (drivers/mtd/spi/spi_spl_load.o) CONFIG_SPL_RAM_DEVICE (common/spl/spl.c) - +CONFIG_SPL_WATCHDOG_SUPPORT (drivers/watchdog/libwatchdog.o) Normally CPU is assumed to be the same between the SPL and normal u-boot build. However it is possible to specify a different CPU for diff --git a/spl/Makefile b/spl/Makefile index 6e5299b..9a46e7e 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -82,6 +82,7 @@ LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/libusb_musb-new.o LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/libusb_gadget.o +LIBS-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/libwatchdog.o ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o -- 1.7.11.7 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 2/3] arm, am335x: add watchdog support
Add TI OMAP 16xx 24xx/34xx 32KHz (non-secure) watchdog support.
Signed-off-by: Heiko Schocher h...@denx.de
Reviewed-by: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
- changes for v2:
- add Reviedwed-by from Tom Rini
- fixed subject
- add SPDX-License-Identifier
- changes for v3:
- add a more detailed comment, from where this file is based
- fixed SPDX-License-Identifier to GPL-2.0
---
arch/arm/include/asm/arch-am33xx/cpu.h | 20 ++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/omap_wdt.c| 121 +
3 Dateien geändert, 142 Zeilen hinzugefügt(+)
create mode 100644 drivers/watchdog/omap_wdt.c
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h
b/arch/arm/include/asm/arch-am33xx/cpu.h
index 945a09b..ce24080 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -53,6 +53,26 @@
#define PRM_RSTCTRL_RESET 0x01
#define PRM_RSTST_WARM_RESET_MASK 0x232
+/*
+ * Watchdog:
+ * Using the prescaler, the OMAP watchdog could go for many
+ * months before firing. These limits work without scaling,
+ * with the 60 second default assumed by most tools and docs.
+ */
+#define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */
+#define TIMER_MARGIN_DEFAULT 60 /* 60 secs */
+#define TIMER_MARGIN_MIN 1
+
+#define PTV0 /* prescale */
+#define GET_WLDR_VAL(secs) (0x - ((secs) * (32768/(1PTV))) + 1)
+#define WDT_WWPS_PEND_WCLR BIT(0)
+#define WDT_WWPS_PEND_WLDR BIT(2)
+#define WDT_WWPS_PEND_WTGR BIT(3)
+#define WDT_WWPS_PEND_WSPR BIT(4)
+
+#define WDT_WCLR_PRE BIT(5)
+#define WDT_WCLR_PTV_OFF 2
+
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct gpmc_cs {
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 7e255ce..3ade624 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -18,6 +18,7 @@ COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
COBJS-$(CONFIG_S5P) += s5p_wdt.o
COBJS-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
COBJS-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
+COBJS-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c
new file mode 100644
index 000..7ea4b60
--- /dev/null
+++ b/drivers/watchdog/omap_wdt.c
@@ -0,0 +1,121 @@
+/*
+ * omap_wdt.c
+ *
+ * (C) Copyright 2013
+ * Heiko Schocher, DENX Software Engineering, h...@denx.de.
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ *
+ * Based on:
+ *
+ * Watchdog driver for the TI OMAP 16xx 24xx/34xx 32KHz (non-secure) watchdog
+ *
+ * commit 2d991a164a61858012651e13c59521975504e260
+ * Author: Bill Pemberton wf...@virginia.edu
+ * Date: Mon Nov 19 13:21:41 2012 -0500
+ *
+ * watchdog: remove use of __devinit
+ *
+ * CONFIG_HOTPLUG is going away as an option so __devinit is no longer
+ * needed.
+ *
+ * Author: MontaVista Software, Inc.
+ * gda...@mvista.com or sou...@mvista.com
+ *
+ * History:
+ *
+ * 20030527: George G. Davis gda...@mvista.com
+ * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
+ * (c) Copyright 2000 Oleg Drokin gr...@crimea.edu
+ * Based on SoftDog driver by Alan Cox a...@lxorguk.ukuu.org.uk
+ *
+ * Copyright (c) 2004 Texas Instruments.
+ * 1. Modified to support OMAP1610 32-KHz watchdog timer
+ * 2. Ported to 2.6 kernel
+ *
+ * Copyright (c) 2005 David Brownell
+ * Use the driver model and standard identifiers; handle bigger timeouts.
+ */
+
+#include common.h
+#include watchdog.h
+#include asm/arch/hardware.h
+#include asm/io.h
+#include asm/processor.h
+#include asm/arch/cpu.h
+
+/* Hardware timeout in seconds */
+#define WDT_HW_TIMEOUT 60
+
+static unsigned int wdt_trgr_pattern = 0x1234;
+
+void hw_watchdog_reset(void)
+{
+ struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
+
+ /* wait for posted write to complete */
+ while ((readl(wdt-wdtwwps)) WDT_WWPS_PEND_WTGR)
+ ;
+
+ wdt_trgr_pattern = ~wdt_trgr_pattern;
+ writel(wdt_trgr_pattern, wdt-wdtwtgr);
+
+ /* wait for posted write to complete */
+ while ((readl(wdt-wdtwwps) WDT_WWPS_PEND_WTGR))
+ ;
+}
+
+static int omap_wdt_set_timeout(unsigned int timeout)
+{
+ struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
+ u32 pre_margin = GET_WLDR_VAL(timeout);
+
+ /* just count up at 32 KHz */
+ while (readl(wdt-wdtwwps) WDT_WWPS_PEND_WLDR)
+ ;
+
+ writel(pre_margin, wdt-wdtwldr);
+ while (readl(wdt-wdtwwps) WDT_WWPS_PEND_WLDR)
+ ;
+
+ return 0;
+}
+
+void hw_watchdog_init(void)
+{
+ struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
+
+ /* initialize prescaler */
+ while (readl(wdt-wdtwwps) WDT_WWPS_PEND_WCLR)
+ ;
+
+ writel(WDT_WCLR_PRE | (PTV
[U-Boot] [PATCH v2 0/3] arm, am335x: add support for siemens boards
add support for the am335x based boards from siemens: dxr2: - DDR3 128MiB - NAND 256MiB - Ethernet with external Switch SMSC LAN9303 - no PMIC - internal Watchdog - DFU support pxm2: - DDR2 512 MiB - NAND 1024 MiB - PMIC - PHY atheros ar803x - USB Host - internal Watchdog - DFU support rut: - DDR3 256 MiB - NAND 256 MiB - PMIC - PHY natsemi dp83630 - external Watchdog - DFU support based on current mainline commit 9fab4bf4cc077c21e43941866f3f2c196f28670d Needed patches: - [U-Boot] arm, spl: add watchdog library to SPL http://patchwork.ozlabs.org/patch/248503/ reposted with this patchserie - [U-Boot] arm, arm335x: add watchdog support http://patchwork.ozlabs.org/patch/248504/ reposted with this patchserie - [U-Boot,v2] arm, am33xx: add defines for gmii_sel_register bits http://patchwork.ozlabs.org/patch/248916/ - patches from Lokesh Vutla: [U-Boot,1/4] ARM: AM33xx: Cleanup dplls data http://patchwork.ozlabs.org/patch/253831/ [U-Boot,2/4] ARM: AM33xx: Cleanup clocks layer http://patchwork.ozlabs.org/patch/253833/ [U-Boot,3/4] ARM: AM33xx: Move s_init to a common place http://patchwork.ozlabs.org/patch/253834/ [U-Boot,4/4] musb: Disable extra prints http://patchwork.ozlabs.org/patch/253832/ - [U-Boot,v5] dfu, nand, ubi: add partubi alt settings for updating ubi partition http://patchwork.ozlabs.org/patch/261583/ - [U-Boot] net, phy, cpsw: fix gigabit register access http://patchwork.ozlabs.org/patch/261087/ Tested patches with this patch: - [U-Boot] dfu: Implementation of target reset after communication with dfu-util's -R switch http://patchwork.ozlabs.org/patch/260041/ - [U-Boot] ARM: OMAP: GPIO: Fix valid range and enable usage of all GPIOs on OMAP5 http://patchwork.ozlabs.org/patch/253185/ - changes for v2: - add a more detailed comment, from where the files are based - fixed SPDX-License-Identifier to GPL-2.0 for drivers/watchdog/omap_wdt.c Heiko Schocher (3): arm, spl: add watchdog library to SPL arm, am335x: add watchdog support arm, am335x: add support for 3 siemens boards MAINTAINERS| 5 + arch/arm/include/asm/arch-am33xx/cpu.h | 20 ++ board/siemens/common/board.c | 158 +++ board/siemens/common/factoryset.c | 268 +++ board/siemens/common/factoryset.h | 21 ++ board/siemens/dxr2/Makefile| 49 board/siemens/dxr2/board.c | 240 + board/siemens/dxr2/board.h | 69 + board/siemens/dxr2/mux.c | 112 board/siemens/pxm2/Makefile| 49 board/siemens/pxm2/board.c | 237 + board/siemens/pxm2/board.h | 22 ++ board/siemens/pxm2/mux.c | 140 ++ board/siemens/pxm2/pmic.h | 71 + board/siemens/rut/Makefile | 49 board/siemens/rut/board.c | 179 + board/siemens/rut/board.h | 22 ++ board/siemens/rut/mux.c| 341 boards.cfg | 3 + doc/README.SPL | 2 +- drivers/watchdog/Makefile | 1 + drivers/watchdog/omap_wdt.c| 121 + include/configs/dxr2.h | 94 +++ include/configs/pxm2.h | 134 ++ include/configs/rut.h | 135 ++ include/configs/siemens-am33x-common.h | 464 + spl/Makefile | 1 + 27 Dateien geändert, 3006 Zeilen hinzugefügt(+), 1 Zeile entfernt(-) create mode 100644 board/siemens/common/board.c create mode 100644 board/siemens/common/factoryset.c create mode 100644 board/siemens/common/factoryset.h create mode 100644 board/siemens/dxr2/Makefile create mode 100644 board/siemens/dxr2/board.c create mode 100644 board/siemens/dxr2/board.h create mode 100644 board/siemens/dxr2/mux.c create mode 100644 board/siemens/pxm2/Makefile create mode 100644 board/siemens/pxm2/board.c create mode 100644 board/siemens/pxm2/board.h create mode 100644 board/siemens/pxm2/mux.c create mode 100644 board/siemens/pxm2/pmic.h create mode 100644 board/siemens/rut/Makefile create mode 100644 board/siemens/rut/board.c create mode 100644 board/siemens/rut/board.h create mode 100644 board/siemens/rut/mux.c create mode 100644 drivers/watchdog/omap_wdt.c create mode 100644 include/configs/dxr2.h create mode 100644 include/configs/pxm2.h create mode 100644 include/configs/rut.h create mode 100644 include/configs/siemens-am33x-common.h Cc: Tom Rini tr...@ti.com -- 1.7.11.7 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 1/4] ARM: AM33xx: Cleanup dplls data
Locking sequence for all the dplls is same.
In the current code same sequence is done repeatedly
for each dpll. Instead have a generic function
for locking dplls and pass dpll data to that function.
This is derived from OMAP4 boards.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/am33xx/Makefile |1 +
arch/arm/cpu/armv7/am33xx/clock.c| 111 +
arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 220 +-
arch/arm/cpu/armv7/am33xx/emif4.c|4 +
arch/arm/include/asm/arch-am33xx/clock.h | 70
arch/arm/include/asm/arch-am33xx/ddr_defs.h |2 +
arch/arm/include/asm/arch-am33xx/sys_proto.h |1 +
board/isee/igep0033/board.c | 10 ++
board/phytec/pcm051/board.c |9 ++
board/ti/am335x/board.c | 27
10 files changed, 273 insertions(+), 182 deletions(-)
create mode 100644 arch/arm/cpu/armv7/am33xx/clock.c
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile
b/arch/arm/cpu/armv7/am33xx/Makefile
index dbd1ec3..7fd21af 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -10,6 +10,7 @@ LIB = $(obj)lib$(SOC).o
COBJS-$(CONFIG_AM33XX) += clock_am33xx.o
COBJS-$(CONFIG_TI814X) += clock_ti814x.o
+COBJS-$(CONFIG_AM33XX) += clock.o
COBJS += sys_info.o
COBJS += mem.o
COBJS += ddr.o
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c
b/arch/arm/cpu/armv7/am33xx/clock.c
new file mode 100644
index 000..15f4a2c
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -0,0 +1,111 @@
+/*
+ * clock.c
+ *
+ * Clock initialization for AM33XX boards.
+ * Derived from OMAP4 boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include common.h
+#include asm/arch/cpu.h
+#include asm/arch/clock.h
+#include asm/arch/hardware.h
+#include asm/arch/sys_proto.h
+#include asm/io.h
+
+static void setup_post_dividers(const struct dpll_regs *dpll_regs,
+const struct dpll_params *params)
+{
+ /* Setup post-dividers */
+ if (params-m2 = 0)
+ writel(params-m2, dpll_regs-cm_div_m2_dpll);
+ if (params-m3 = 0)
+ writel(params-m3, dpll_regs-cm_div_m3_dpll);
+ if (params-m4 = 0)
+ writel(params-m4, dpll_regs-cm_div_m4_dpll);
+ if (params-m5 = 0)
+ writel(params-m5, dpll_regs-cm_div_m5_dpll);
+ if (params-m6 = 0)
+ writel(params-m6, dpll_regs-cm_div_m6_dpll);
+}
+
+static inline void do_lock_dpll(const struct dpll_regs *dpll_regs)
+{
+ clrsetbits_le32(dpll_regs-cm_clkmode_dpll,
+ CM_CLKMODE_DPLL_DPLL_EN_MASK,
+ DPLL_EN_LOCK CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_lock(const struct dpll_regs *dpll_regs)
+{
+ if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
+ (void *)dpll_regs-cm_idlest_dpll, LDELAY)) {
+ printf(DPLL locking failed for 0x%x\n,
+ dpll_regs-cm_clkmode_dpll);
+ hang();
+ }
+}
+
+static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs)
+{
+ clrsetbits_le32(dpll_regs-cm_clkmode_dpll,
+ CM_CLKMODE_DPLL_DPLL_EN_MASK,
+ DPLL_EN_MN_BYPASS CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_bypass(const struct dpll_regs *dpll_regs)
+{
+ if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
+ (void *)dpll_regs-cm_idlest_dpll, LDELAY)) {
+ printf(Bypassing DPLL failed 0x%x\n,
+ dpll_regs-cm_clkmode_dpll);
+ }
+}
+
+static void bypass_dpll(const struct dpll_regs *dpll_regs)
+{
+ do_bypass_dpll(dpll_regs);
+ wait_for_bypass(dpll_regs);
+}
+
+void do_setup_dpll(const struct dpll_regs *dpll_regs,
+ const struct dpll_params *params)
+{
+ u32 temp;
+
+ if (!params)
+ return;
+
+ temp = readl(dpll_regs-cm_clksel_dpll);
+
+ bypass_dpll(dpll_regs);
+
+ /* Set M N */
+ temp = ~CM_CLKSEL_DPLL_M_MASK;
+ temp |= (params-m CM_CLKSEL_DPLL_M_SHIFT) CM_CLKSEL_DPLL_M_MASK;
+
+ temp = ~CM_CLKSEL_DPLL_N_MASK;
+ temp |= (params-n CM_CLKSEL_DPLL_N_SHIFT) CM_CLKSEL_DPLL_N_MASK;
+
+ writel(temp, dpll_regs-cm_clksel_dpll);
+
+ setup_post_dividers(dpll_regs, params);
+
+ /* Wait till the DPLL locks */
+ do_lock_dpll(dpll_regs);
+ wait_for_lock(dpll_regs);
+}
+
+void setup_dplls(void)
+{
+ const struct dpll_params *params;
+ do_setup_dpll(dpll_core_regs, dpll_core);
+ do_setup_dpll(dpll_mpu_regs, dpll_mpu);
+ do_setup_dpll(dpll_per_regs, dpll_per);
+ writel(0x300, cmwkup-clkdcoldodpllper);
+
+ params = get_dpll_ddr_params();
+ do_setup_dpll(dpll_ddr_regs, params);
+}
diff --git
[U-Boot] [PATCH V2 0/4]ARM: AM33xx: Cleanup clocks and hwinit
This series tries to cleanup code for AM33xx, inorder to ensure code reusabilty by moving the duplicated code to common place. This also helps in addition of new Soc with minimal changes. Testing: Boot tested on BeagleBone White/Black, AM35xx EVM/EVMSK. Verified ./MAKEALL -s am33xx. Changes Since V1: - Rebased on top of u-boot-ti - Created a function get_dpll_ddr_params() for getting ddr dpll params from board files. - Updated License header for newly created files. Heiko Schocher (1): ARM: AM33xx: Move s_init to a common place Lokesh Vutla (3): ARM: AM33xx: Cleanup dplls data ARM: AM33xx: Cleanup clocks layer musb: Disable extra prints arch/arm/cpu/armv7/am33xx/Makefile |1 + arch/arm/cpu/armv7/am33xx/board.c| 68 ++- arch/arm/cpu/armv7/am33xx/clock.c| 171 arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 495 +- arch/arm/cpu/armv7/am33xx/clock_ti814x.c | 25 +- arch/arm/cpu/armv7/am33xx/emif4.c|5 +- arch/arm/include/asm/arch-am33xx/clock.h | 94 arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |6 +- arch/arm/include/asm/arch-am33xx/sys_proto.h |9 +- board/isee/igep0033/board.c | 55 +-- board/phytec/pcm051/board.c | 57 +-- board/ti/am335x/board.c | 102 ++--- board/ti/am335x/mux.c| 19 + board/ti/ti814x/evm.c| 65 +-- drivers/usb/musb-new/musb_core.c | 20 +- 15 files changed, 573 insertions(+), 619 deletions(-) create mode 100644 arch/arm/cpu/armv7/am33xx/clock.c -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 4/4] musb: Disable extra prints
There are many musb prints in SPL and U-Boot log.
These prints are required only during musb debug.
So replacing printk with pr_debug in musb_core.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
drivers/usb/musb-new/musb_core.c | 20
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index da93571..36681b6 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -1311,9 +1311,7 @@ static int __devinit ep_config_from_table(struct musb
*musb)
break;
}
- printk(KERN_DEBUG %s: setup fifo_mode %d\n,
- musb_driver_name, fifo_mode);
-
+ pr_debug(%s: setup fifo_mode %d\n, musb_driver_name, fifo_mode);
done:
offset = fifo_setup(musb, hw_ep, ep0_cfg, 0);
@@ -1341,10 +1339,9 @@ done:
musb-nr_endpoints = max(epn, musb-nr_endpoints);
}
- printk(KERN_DEBUG %s: %d/%d max ep, %d/%d memory\n,
- musb_driver_name,
- n + 1, musb-config-num_eps * 2 - 1,
- offset, (1 (musb-config-ram_bits + 2)));
+ pr_debug(%s: %d/%d max ep, %d/%d memory\n, musb_driver_name, n + 1,
+musb-config-num_eps * 2 - 1, offset,
+(1 (musb-config-ram_bits + 2)));
if (!musb-bulk_ep) {
pr_debug(%s: missing bulk\n, musb_driver_name);
@@ -1447,8 +1444,7 @@ static int __devinit musb_core_init(u16 musb_type, struct
musb *musb)
if (reg MUSB_CONFIGDATA_SOFTCONE)
strcat(aInfo, , SoftConn);
- printk(KERN_DEBUG %s: ConfigData=0x%02x (%s)\n,
- musb_driver_name, reg, aInfo);
+ pr_debug(%s:ConfigData=0x%02x (%s)\n, musb_driver_name, reg, aInfo);
aDate[0] = 0;
if (MUSB_CONTROLLER_MHDRC == musb_type) {
@@ -1469,8 +1465,8 @@ static int __devinit musb_core_init(u16 musb_type, struct
musb *musb)
snprintf(aRevision, 32, %d.%d%s, MUSB_HWVERS_MAJOR(musb-hwvers),
MUSB_HWVERS_MINOR(musb-hwvers),
(musb-hwvers MUSB_HWVERS_RC) ? RC : );
- printk(KERN_DEBUG %s: %sHDRC RTL version %s %s\n,
- musb_driver_name, type, aRevision, aDate);
+ pr_debug(%s: %sHDRC RTL version %s %s\n, musb_driver_name, type,
+aRevision, aDate);
/* configure ep0 */
musb_configure_ep0(musb);
@@ -2122,7 +2118,7 @@ musb_init_controller(struct musb_hdrc_platform_data
*plat, struct device *dev,
pm_runtime_put(musb-controller);
- dev_info(dev, USB %s mode controller at %p using %s, IRQ %d\n,
+ pr_debug(USB %s mode controller at %p using %s, IRQ %d\n,
({char *s;
switch (musb-board_mode) {
case MUSB_HOST:s = Host; break;
--
1.7.9.5
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[U-Boot] [PATCH V2 3/4] ARM: AM33xx: Move s_init to a common place
From: Heiko Schocher h...@denx.de
s_init has the same outline for all the AM33xx based
board. So making it generic.
This also helps in addition of new Soc with minimal changes.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Heiko Schocher h...@denx.de
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/board.c| 62 +++--
arch/arm/cpu/armv7/am33xx/clock_ti814x.c |6 ++
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |6 +-
arch/arm/include/asm/arch-am33xx/sys_proto.h |8 ++-
board/isee/igep0033/board.c | 50 +++---
board/phytec/pcm051/board.c | 48 +++--
board/ti/am335x/board.c | 80 --
board/ti/am335x/mux.c| 19 +
board/ti/ti814x/evm.c| 67 +++---
9 files changed, 128 insertions(+), 218 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu/armv7/am33xx/board.c
index 64a3af7..2ea3d69 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -137,7 +137,7 @@ int arch_misc_init(void)
}
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
-void rtc32k_enable(void)
+static void rtc32k_enable(void)
{
struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
@@ -153,11 +153,7 @@ void rtc32k_enable(void)
writel((1 3) | (1 6), rtc-osc);
}
-#define UART_RESET (0x1 1)
-#define UART_CLK_RUNNING_MASK 0x1
-#define UART_SMART_IDLE_EN (0x1 0x3)
-
-void uart_soft_reset(void)
+static void uart_soft_reset(void)
{
struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
u32 regval;
@@ -174,4 +170,58 @@ void uart_soft_reset(void)
regval |= UART_SMART_IDLE_EN;
writel(regval, uart_base-uartsyscfg);
}
+
+static void watchdog_disable(void)
+{
+ struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+ writel(0x, wdtimer-wdtwspr);
+ while (readl(wdtimer-wdtwwps) != 0x0)
+ ;
+ writel(0x, wdtimer-wdtwspr);
+ while (readl(wdtimer-wdtwwps) != 0x0)
+ ;
+}
#endif
+
+void s_init(void)
+{
+ /*
+* The ROM will only have set up sufficient pinmux to allow for the
+* first 4KiB NOR to be read, we must finish doing what we know of
+* the NOR mux in this space in order to continue.
+*/
+#ifdef CONFIG_NOR_BOOT
+ enable_norboot_pin_mux();
+#endif
+ /*
+* Save the boot parameters passed from romcode.
+* We cannot delay the saving further than this,
+* to prevent overwrites.
+*/
+#ifdef CONFIG_SPL_BUILD
+ save_omap_boot_params();
+#endif
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+ watchdog_disable();
+ timer_init();
+ set_uart_mux_conf();
+ setup_clocks_for_console();
+ uart_soft_reset();
+#endif
+#ifdef CONFIG_NOR_BOOT
+ gd-baudrate = CONFIG_BAUDRATE;
+ serial_init();
+ gd-have_console = 1;
+#else
+ gd = gdata;
+ preloader_console_init();
+#endif
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+ prcm_init();
+ set_mux_conf_regs();
+ /* Enable RTC32K clock */
+ rtc32k_enable();
+ sdram_init();
+#endif
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
index 965e875..93c7f7b 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -277,6 +277,12 @@ static void enable_per_clocks(void)
writel(PRCM_MOD_EN, cmalwon-ethernet1clkctrl);
while ((readl(cmalwon-ethernet1clkctrl) ENET_CLKCTRL_CMPL) != 0)
;
+
+ /* RTC clocks */
+ writel(PRCM_MOD_EN, cmalwon-rtcclkstctrl);
+ writel(PRCM_MOD_EN, cmalwon-rtcclkctrl);
+ while (readl(cmalwon-rtcclkctrl) != PRCM_MOD_EN)
+ ;
}
/*
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index 80e1899..140379f 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -16,8 +16,10 @@
#define CONFIG_SYS_MPUCLK 550
#endif
-extern void pll_init(void);
-extern void enable_emif_clocks(void);
+#define UART_RESET (0x1 1)
+#define UART_CLK_RUNNING_MASK 0x1
+#define UART_SMART_IDLE_EN (0x1 0x3)
+
extern void enable_dmm_clocks(void);
#endif /* endif _CLOCKS_AM33XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h
b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index dbcede0..c6070a3 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -35,7 +35,11 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct
gpmc_cs *cs, u32 base,
u32
[U-Boot] [PATCH V2 2/4] ARM: AM33xx: Cleanup clocks layer
Cleaning up the clocks layer.
This helps in addition of new Soc with minimal
changes.
This is derived from OMAP4 boards.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/am33xx/board.c |6 -
arch/arm/cpu/armv7/am33xx/clock.c | 62 +-
arch/arm/cpu/armv7/am33xx/clock_am33xx.c| 275 ---
arch/arm/cpu/armv7/am33xx/clock_ti814x.c| 19 +-
arch/arm/cpu/armv7/am33xx/emif4.c |1 -
arch/arm/include/asm/arch-am33xx/clock.h| 28 ++-
arch/arm/include/asm/arch-am33xx/ddr_defs.h |2 -
board/isee/igep0033/board.c | 11 +-
board/ti/am335x/board.c | 13 +-
board/ti/ti814x/evm.c | 12 +-
10 files changed, 193 insertions(+), 236 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu/armv7/am33xx/board.c
index f1623db..64a3af7 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -56,12 +56,6 @@ int cpu_mmc_init(bd_t *bis)
}
#endif
-void setup_clocks_for_console(void)
-{
- /* Not yet implemented */
- return;
-}
-
/* AM33XX has two MUSB controllers which can be host or gadget */
#if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) \
(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c
b/arch/arm/cpu/armv7/am33xx/clock.c
index 15f4a2c..8e5f3c6 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -98,7 +98,7 @@ void do_setup_dpll(const struct dpll_regs *dpll_regs,
wait_for_lock(dpll_regs);
}
-void setup_dplls(void)
+static void setup_dplls(void)
{
const struct dpll_params *params;
do_setup_dpll(dpll_core_regs, dpll_core);
@@ -109,3 +109,63 @@ void setup_dplls(void)
params = get_dpll_ddr_params();
do_setup_dpll(dpll_ddr_regs, params);
}
+
+static inline void wait_for_clk_enable(u32 *clkctrl_addr)
+{
+ u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+ u32 bound = LDELAY;
+
+ while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+ (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+ clkctrl = readl(clkctrl_addr);
+ idlest = (clkctrl MODULE_CLKCTRL_IDLEST_MASK)
+MODULE_CLKCTRL_IDLEST_SHIFT;
+ if (--bound == 0) {
+ printf(Clock enable failed for 0x%p idlest 0x%x\n,
+ clkctrl_addr, clkctrl);
+ return;
+ }
+ }
+}
+
+static inline void enable_clock_module(u32 *const clkctrl_addr, u32
enable_mode,
+ u32 wait_for_enable)
+{
+ clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+ enable_mode MODULE_CLKCTRL_MODULEMODE_SHIFT);
+ debug(Enable clock module - %p\n, clkctrl_addr);
+ if (wait_for_enable)
+ wait_for_clk_enable(clkctrl_addr);
+}
+
+static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
+{
+ clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+ enable_mode CD_CLKCTRL_CLKTRCTRL_SHIFT);
+ debug(Enable clock domain - %p\n, clkctrl_reg);
+}
+
+void do_enable_clocks(u32 *const *clk_domains,
+ u32 *const *clk_modules_explicit_en, u8 wait_for_enable)
+{
+ u32 i, max = 100;
+
+ /* Put the clock domains in SW_WKUP mode */
+ for (i = 0; (i max) clk_domains[i]; i++) {
+ enable_clock_domain(clk_domains[i],
+ CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+ }
+
+ /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+ for (i = 0; (i max) clk_modules_explicit_en[i]; i++) {
+ enable_clock_module(clk_modules_explicit_en[i],
+ MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+ wait_for_enable);
+ };
+}
+
+void prcm_init()
+{
+ enable_basic_clocks();
+ setup_dplls();
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index d5d47ad..e5f287b 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -14,17 +14,12 @@
#include asm/arch/hardware.h
#include asm/io.h
-#define PRCM_MOD_EN0x2
-#define PRCM_FORCE_WAKEUP 0x2
-#define PRCM_FUNCTL0x0
-
-#define CPGMAC0_IDLE 0x3
#define OSC(V_OSCK/100)
-const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
-const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
-const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
-const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
+struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
Re: [U-Boot] [PATCH] cfi_flash: Add prototypes of overridable functions
Hello Stefan Is this patch still needed? Yes, I think so. Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
