[U-Boot] Merging multiple ARM start.S files, what about copyright lines?
Hello all, I am continuing my effort to merge all arch/arm/cpu/**/start.S files into a single arch/arm/cpu/start.S one, keeping as little cpu-specific code as I can. However, there is a non-technical issue: there are many copyright lines in the files, plus in some case inherited copyright when the file's code comes from some other source. Many of these copyright lines are repeated across series of CPUs. How should I handle this in the final file? The quickest, and preferred by me, way would be to create the new file with all copyright lines simply merged, and rely on the git repo to find out who contributed what. I could also put one copyright lines block per original start.S file. That would help make quite a big copyrights section. And there are certainly many other ways I could do it. But IANAL (AIDPOOTV, either) and I prefer gathering some input from people who have more experience in this area than I do. So... any advice welcome on how I should proceed on this point. :) Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ppc4xx: Remove CANBT board
Dear Matthias Fuchs, In message 5201ec5b.9070...@esd.eu you wrote: This board and especially the CPU (PPC405CR) is EOL. Signed-off-by: Matthias Fuchs matthias.fu...@esd.eu --- MAINTAINERS|1 - board/esd/canbt/Makefile | 31 -- board/esd/canbt/canbt.c| 164 - board/esd/canbt/canbt.h| 28 -- board/esd/canbt/flash.c| 68 board/esd/canbt/fpgadata.c | 807 boards.cfg |1 - include/configs/CANBT.h| 215 8 files changed, 1315 deletions(-) delete mode 100644 board/esd/canbt/Makefile delete mode 100644 board/esd/canbt/canbt.c delete mode 100644 board/esd/canbt/canbt.h delete mode 100644 board/esd/canbt/flash.c delete mode 100644 board/esd/canbt/fpgadata.c delete mode 100644 include/configs/CANBT.h Please add an entry to doc/README.scrapyard Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Romulan women are not like Vulcan females. We are not dedicated to pure logic and the sterility of non-emotion. -- Romulan Commander, The Enterprise Incident, stardate 5027.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Merging multiple ARM start.S files, what about copyright lines?
Dear Albert, In message 20130807092318.1fd9bab5@lilith you wrote: The quickest, and preferred by me, way would be to create the new file with all copyright lines simply merged, and rely on the git repo to find out who contributed what. Yes, this makes sense. I could also put one copyright lines block per original start.S file. That would help make quite a big copyrights section. This would not add any real information, but just blow up the file. My vote is going for a merge. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de The easiest way to figure the cost of living is to take your income and add ten percent. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] question about selecting a stable U-Boot source code package
Hi, experts: How to select a stable uboot source code for developing a commercial product? There are so many official release package, such as: u-boot-2012.04.tar.bz2 u-boot-2012.10.tar.bz2 u-boot-2013.04.tar.bz2 u-boot-2013.07.tar.bz2 ... So, how to identify which package is more stable than another package?! For PandaBoard (TI Company): It seems TI selected u-boot-2012.10.tar.bz2 as its code base. Best wishes, ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] edid: rename struct member to fix two EDID_* macros
Without this change EDID_DETAILED_TIMING_VSYNC_OFFSET
and EDID_DETAILED_TIMING_VSYNC_PULSE_WIDTH macros can
not be used (compile error).
The fix is quite trivial: rename struct member to the
expected name.
Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com
---
include/edid.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/edid.h b/include/edid.h
index f153091..480a773 100644
--- a/include/edid.h
+++ b/include/edid.h
@@ -54,7 +54,7 @@ struct edid_detailed_timing {
(_x).vertical_blanking)
unsigned char hsync_offset;
unsigned char hsync_pulse_width;
- unsigned char sync_offset_pulse_width;
+ unsigned char vsync_offset_pulse_width;
unsigned char hsync_vsync_offset_pulse_width_hi;
#define EDID_DETAILED_TIMING_HSYNC_OFFSET(_x) \
((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 7, 6) 8) + \
--
1.7.10.4
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[U-Boot] [PATCH 1/4] Sound: WM8994: Support I2S0 channel
This patch modifies the WM8994 codec to support I2S0 channel
in codec slave mode
Signed-off-by: Dani Krishna Mohan krishna...@samsung.com
---
drivers/sound/sound.c|2 +-
drivers/sound/wm8994.c | 95 +++---
drivers/sound/wm8994_registers.h | 77 --
3 files changed, 81 insertions(+), 93 deletions(-)
diff --git a/drivers/sound/sound.c b/drivers/sound/sound.c
index 6fcc75d..47879a4 100644
--- a/drivers/sound/sound.c
+++ b/drivers/sound/sound.c
@@ -130,7 +130,7 @@ static int codec_init(const void *blob, struct i2stx_info
*pi2s_tx)
#endif
if (!strcmp(codectype, wm8994)) {
/* Check the codec type and initialise the same */
- ret = wm8994_init(blob, WM8994_AIF2,
+ ret = wm8994_init(blob, WM8994_AIF1,
pi2s_tx-samplingrate,
(pi2s_tx-samplingrate * (pi2s_tx-rfs)),
pi2s_tx-bitspersample, pi2s_tx-channels);
diff --git a/drivers/sound/wm8994.c b/drivers/sound/wm8994.c
index 37e354c..57c8f8d 100644
--- a/drivers/sound/wm8994.c
+++ b/drivers/sound/wm8994.c
@@ -477,9 +477,9 @@ static int configure_aif_clock(struct wm8994_priv *wm8994,
int aif)
reg1);
ret |= wm8994_update_bits(WM8994_CLOCKING_1,
- WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK |
+ WM8994_SYSCLK_SRC | WM8994_AIF1DSPCLK_ENA_MASK |
WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC |
- WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
+ WM8994_AIF1DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
if (ret 0) {
debug(%s: codec register access error\n, __func__);
@@ -536,7 +536,7 @@ static int wm8994_set_sysclk(struct wm8994_priv *wm8994,
int aif_id,
break;
if (i == ARRAY_SIZE(opclk_divs)) {
debug(%s frequency divisor not found\n,
- __func__);
+ __func__);
return -1;
}
ret = wm8994_update_bits(WM8994_CLOCKING_2,
@@ -565,28 +565,17 @@ static int wm8994_set_sysclk(struct wm8994_priv *wm8994,
int aif_id,
}
/*
- * Initializes Volume for AIF2 to HP path
+ * Initializes Volume for AIF1 to HP path
*
* @returns -1 for error and 0 Success.
*
*/
-static int wm8994_init_volume_aif2_dac1(void)
+static int wm8994_init_volume_aif1_dac1(void)
{
- int ret;
-
- /* Unmute AIF2DAC */
- ret = wm8994_update_bits(WM8994_AIF2_DAC_FILTERS_1,
- WM8994_AIF2DAC_MUTE_MASK, 0);
-
-
- ret |= wm8994_update_bits(WM8994_AIF2_DAC_LEFT_VOLUME,
- WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK,
- WM8994_AIF2DAC_VU | 0xff);
-
- ret |= wm8994_update_bits(WM8994_AIF2_DAC_RIGHT_VOLUME,
- WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK,
- WM8994_AIF2DAC_VU | 0xff);
+ int ret = 0;
+ /* unmute AIF1DAC1 */
+ ret |= wm8994_i2c_write(WM8994_AIF1_DAC_FILTERS_1, 0x);
ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME,
WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
@@ -661,12 +650,19 @@ static int wm8994_device_init(struct wm8994_priv *wm8994)
ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA);
- /* Power enable for AIF2 and DAC1 */
- ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5,
- WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
- WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK,
- WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA | WM8994_DAC1L_ENA |
- WM8994_DAC1R_ENA);
+
+ ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_2, WM8994_TSHUT_ENA
+ | WM8994_MIXINL_ENA | WM8994_MIXINR_ENA
+ | WM8994_IN2L_ENA | WM8994_IN2R_ENA);
+
+ ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_4, WM8994_ADCL_ENA
+ | WM8994_ADCR_ENA | WM8994_AIF1ADC1R_ENA
+ | WM8994_AIF1ADC1L_ENA);
+
+ /* Power enable for AIF1 and DAC1 */
+ ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_5, WM8994_AIF1DACL_ENA
+ | WM8994_AIF1DACR_ENA | WM8994_DAC1L_ENA
+ | WM8994_DAC1R_ENA);
/* Head Phone Initialisation */
ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1,
@@ -695,35 +691,20 @@ static int wm8994_device_init(struct wm8994_priv *wm8994)
ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_2,
WM8994_DAC1R_TO_HPOUT1R_MASK, WM8994_DAC1R_TO_HPOUT1R);
-
[U-Boot] [PATCH 4/4] Sound: I2S: Replacing I2S1 with I2S0 channel.
This patch makes required changes to make use
of I2S0 channel instead of I2S1 channel on exynos5250.
Signed-off-by: Dani Krishna Mohan krishna...@samsung.com
---
arch/arm/include/asm/arch-exynos/i2s-regs.h |6 ++
drivers/sound/samsung-i2s.c | 16 ++--
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/i2s-regs.h
b/arch/arm/include/asm/arch-exynos/i2s-regs.h
index 613b9b7..4a4a7a0 100644
--- a/arch/arm/include/asm/arch-exynos/i2s-regs.h
+++ b/arch/arm/include/asm/arch-exynos/i2s-regs.h
@@ -8,10 +8,12 @@
#ifndef __I2S_REGS_H__
#define __I2S_REGS_H__
+#define CON_RESET (1 31)
#define CON_TXFIFO_FULL(1 8)
#define CON_TXCH_PAUSE (1 4)
#define CON_ACTIVE (1 0)
+#define MOD_OP_CLK (3 30)
#define MOD_BLCP_SHIFT 24
#define MOD_BLCP_16BIT (0 MOD_BLCP_SHIFT)
#define MOD_BLCP_8BIT (1 MOD_BLCP_SHIFT)
@@ -24,6 +26,7 @@
#define MOD_BLC_MASK (3 13)
#define MOD_SLAVE (1 11)
+#define MOD_RCLKSRC(0 10)
#define MOD_MASK (3 8)
#define MOD_LR_LLOW(0 7)
#define MOD_LR_RLOW(1 7)
@@ -47,4 +50,7 @@
#define FIC_TXFLUSH(1 15)
#define FIC_RXFLUSH(1 7)
+#define PSREN (1 15)
+#define PSVAL (3 8)
+
#endif /* __I2S_REGS_H__ */
diff --git a/drivers/sound/samsung-i2s.c b/drivers/sound/samsung-i2s.c
index 49921e5..8e8a2bc 100644
--- a/drivers/sound/samsung-i2s.c
+++ b/drivers/sound/samsung-i2s.c
@@ -303,21 +303,25 @@ int i2s_tx_init(struct i2stx_info *pi2s_tx)
(struct i2s_reg *)pi2s_tx-base_address;
/* Initialize GPIO for I2s */
- exynos_pinmux_config(PERIPH_ID_I2S1, 0);
+ exynos_pinmux_config(PERIPH_ID_I2S0, 0);
/* Set EPLL Clock */
- ret = set_epll_clk(pi2s_tx-audio_pll_clk);
+ ret = set_epll_clk(pi2s_tx-samplingrate * pi2s_tx-rfs * 4);
if (ret != 0) {
debug(%s: epll clock set rate falied\n, __func__);
return -1;
}
- /* Select Clk Source for Audio1 */
+ /* Select Clk Source for Audio0 */
set_i2s_clk_source();
- /* Set Prescaler to get MCLK */
- set_i2s_clk_prescaler(pi2s_tx-audio_pll_clk,
- (pi2s_tx-samplingrate * (pi2s_tx-rfs)));
+ /*Reset the i2s module */
+ writel(CON_RESET, i2s_reg-con);
+
+ writel(MOD_OP_CLK | MOD_RCLKSRC, i2s_reg-mod);
+
+ /* set i2s prescaler */
+ writel(PSREN | PSVAL, i2s_reg-psr);
/* Configure I2s format */
ret = i2s_set_fmt(i2s_reg, (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
--
1.7.9.5
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[U-Boot] [PATCH 3/4] ARM: Change from I2S1 to I2S0 for audio on SMDK5250
This patch makes the necessary changes for making use of
I2S0 channel instead of I2S1 channel on smdk board. This
changes are done to maintain the uniformity to use I2S0 channel.
Signed-off-by: Dani Krishna Mohan krishna...@samsung.com
---
arch/arm/cpu/armv7/exynos/clock.c | 13 +
arch/arm/cpu/armv7/exynos/pinmux.c| 15 +--
arch/arm/include/asm/arch-exynos/clock.h |8 +---
arch/arm/include/asm/arch-exynos/cpu.h|2 ++
arch/arm/include/asm/arch-exynos/periph.h |1 +
5 files changed, 30 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 0cb1a61..2a1b681 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -282,6 +282,9 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
src = readl(clk-src_peric0);
div = readl(clk-div_peric3);
break;
+ case PERIPH_ID_I2S0:
+ src = readl(clk-src_mau);
+ div = readl(clk-div_mau);
case PERIPH_ID_SPI0:
case PERIPH_ID_SPI1:
src = readl(clk-src_peric1);
@@ -1151,8 +1154,10 @@ void exynos5_set_i2s_clk_source(void)
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
- clrsetbits_le32(clk-src_peric1, AUDIO1_SEL_MASK,
+ setbits_le32(clk-src_top2, CLK_SRC_MOUT_EPLL);
+ clrsetbits_le32(clk-src_mau, AUDIO_SEL_MASK,
(CLK_SRC_SCLK_EPLL));
+ setbits_le32(EXYNOS_AUDSS, CLKMUX_ASS);
}
int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
@@ -1169,13 +1174,13 @@ int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
}
div = (src_frq / dst_frq);
- if (div AUDIO_1_RATIO_MASK) {
+ if (div AUDIO_RATIO_MASK) {
debug(%s: Frequency ratio is out of range\n, __func__);
debug(src frq = %d des frq = %d , src_frq, dst_frq);
return -1;
}
- clrsetbits_le32(clk-div_peric4, AUDIO_1_RATIO_MASK,
- (div AUDIO_1_RATIO_MASK));
+ clrsetbits_le32(clk-div_mau, AUDIO_RATIO_MASK,
+ (div AUDIO_RATIO_MASK));
return 0;
}
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
b/arch/arm/cpu/armv7/exynos/pinmux.c
index 1b05ebf..59f445a 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -221,9 +221,19 @@ static void exynos5_i2s_config(int peripheral)
int i;
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+ struct exynos5_gpio_part4 *gpio4 =
+ (struct exynos5_gpio_part4 *)samsung_get_base_gpio_part4();
- for (i = 0; i 5; i++)
- s5p_gpio_cfg_pin(gpio1-b0, i, GPIO_FUNC(0x02));
+ switch (peripheral) {
+ case PERIPH_ID_I2S0:
+ for (i = 0; i 5; i++)
+ s5p_gpio_cfg_pin(gpio4-z, i, GPIO_FUNC(0x02));
+ break;
+ case PERIPH_ID_I2S1:
+ for (i = 0; i 5; i++)
+ s5p_gpio_cfg_pin(gpio1-b0, i, GPIO_FUNC(0x02));
+ break;
+ }
}
void exynos5_spi_config(int peripheral)
@@ -296,6 +306,7 @@ static int exynos5_pinmux_config(int peripheral, int flags)
case PERIPH_ID_I2C7:
exynos5_i2c_config(peripheral, flags);
break;
+ case PERIPH_ID_I2S0:
case PERIPH_ID_I2S1:
exynos5_i2s_config(peripheral);
break;
diff --git a/arch/arm/include/asm/arch-exynos/clock.h
b/arch/arm/include/asm/arch-exynos/clock.h
index 2b97b9a..d55424e 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -873,11 +873,13 @@ struct set_epll_con_val {
#define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/
#define TIMEOUT_EPLL_LOCK 1000
-#define AUDIO_0_RATIO_MASK 0x0f
-#define AUDIO_1_RATIO_MASK 0x0f
+#define AUDIO_RATIO_MASK 0x0f
+
+#define AUDIO_SEL_MASK 0xf
-#define AUDIO1_SEL_MASK0xf
#define CLK_SRC_SCLK_EPLL 0x7
+#define CLK_SRC_MOUT_EPLL (112)
+#define CLKMUX_ASS (10)
/* CON0 bit-fields */
#define EPLL_CON0_MDIV_MASK0x1ff
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
b/arch/arm/include/asm/arch-exynos/cpu.h
index cb924fb..552b64f 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -89,6 +89,8 @@
/* EXYNOS5 Common*/
#define EXYNOS5_I2C_SPACING0x1
+#define EXYNOS_AUDSS 0x0381
+
#define EXYNOS5_GPIO_PART4_BASE0x0386
#define EXYNOS5_PRO_ID 0x1000
#define EXYNOS5_CLOCK_BASE 0x1001
[U-Boot] Getting U-Boot running on Toradex Colibri T20 on Iris board
Hi, I'm trying to get the U-Boot running on the Iris board with the Toradex Colibri T20 module. I was able to flash the U-Boot and it starts but then immediately stops with the only message being: U-Boot 2013.07 (Aug 06 2013 - 17:47:43) TEGRA20 Board: Toradex Colibri T20 on Iris DRAM: The Colibri T20 board used is: 256MB RAM V1.2A Could you please give me any idea what I might be doing wrong? -- Best regards, Andrzej Telszewski Embedded Systems Developer Versa Design S.L. phone: +34 633 535 308 e-mail: atelszew...@versades.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/4] DTS: Addition of I2S0 channel and replacing I2S1
This patch enables default I2S0 channel and replaces I2S1.
I2S platform parameter has been moved to a common file viz
exynos5.dtsi.
Signed-off-by: Dani Krishna Mohan krishna...@samsung.com
---
arch/arm/dts/exynos5250.dtsi | 10 --
board/samsung/dts/exynos5250-smdk5250.dts |8 +---
board/samsung/dts/exynos5250-snow.dts |6 --
3 files changed, 9 insertions(+), 15 deletions(-)
diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi
index 4fff5e3..da7ce24 100644
--- a/arch/arm/dts/exynos5250.dtsi
+++ b/arch/arm/dts/exynos5250.dtsi
@@ -93,9 +93,15 @@
interrupts = 0 63 0;
};
- sound@12d6 {
+ sound@383 {
compatible = samsung,exynos-sound;
- reg = 0x12d6 0x20;
+ reg = 0x383 0x50;
+ samsung,i2s-epll-clock-frequency = 19200;
+ samsung,i2s-sampling-rate = 48000;
+ samsung,i2s-bits-per-sample = 16;
+ samsung,i2s-channels = 2;
+ samsung,i2s-lr-clk-framesize = 256;
+ samsung,i2s-bit-clk-framesize = 32;
};
spi@12d2 {
diff --git a/board/samsung/dts/exynos5250-smdk5250.dts
b/board/samsung/dts/exynos5250-smdk5250.dts
index 80ffe30..0067130 100644
--- a/board/samsung/dts/exynos5250-smdk5250.dts
+++ b/board/samsung/dts/exynos5250-smdk5250.dts
@@ -49,13 +49,7 @@
};
};
- sound@12d6 {
- samsung,i2s-epll-clock-frequency = 19200;
- samsung,i2s-sampling-rate = 48000;
- samsung,i2s-bits-per-sample = 16;
- samsung,i2s-channels = 2;
- samsung,i2s-lr-clk-framesize = 256;
- samsung,i2s-bit-clk-framesize = 32;
+ sound@383 {
samsung,codec-type = wm8994;
};
diff --git a/board/samsung/dts/exynos5250-snow.dts
b/board/samsung/dts/exynos5250-snow.dts
index dca3386..d0407b5 100644
--- a/board/samsung/dts/exynos5250-snow.dts
+++ b/board/samsung/dts/exynos5250-snow.dts
@@ -66,12 +66,6 @@
};
sound@12d6 {
- samsung,i2s-epll-clock-frequency = 19200;
- samsung,i2s-sampling-rate = 48000;
- samsung,i2s-bits-per-sample = 16;
- samsung,i2s-channels = 2;
- samsung,i2s-lr-clk-framesize = 256;
- samsung,i2s-bit-clk-framesize = 32;
samsung,codec-type = max98095;
};
--
1.7.9.5
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[U-Boot] [PATCH] ppc4xx: Remove support for PPC405CR CPUs
This patch removes support for the APM 405CR CPU.
This CPU is EOL and no board uses this chip.
Signed-off-by: Matthias Fuchs matthias.fu...@esd.eu
---
arch/powerpc/cpu/ppc4xx/4xx_uart.c| 10 ++--
arch/powerpc/cpu/ppc4xx/cpu.c | 18 +--
arch/powerpc/cpu/ppc4xx/cpu_init.c|2 +-
arch/powerpc/cpu/ppc4xx/speed.c |4 +-
arch/powerpc/cpu/ppc4xx/start.S |4 +-
arch/powerpc/include/asm/ppc405cr.h | 92 -
arch/powerpc/include/asm/ppc4xx-ebc.h |6 +--
arch/powerpc/include/asm/ppc4xx.h |4 --
arch/powerpc/include/asm/processor.h |3 --
arch/powerpc/include/asm/u-boot.h |1 -
common/cmd_bdinfo.c |6 +--
include/asm-generic/u-boot.h |1 -
include/serial.h |2 +-
13 files changed, 18 insertions(+), 135 deletions(-)
delete mode 100644 arch/powerpc/include/asm/ppc405cr.h
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_uart.c
b/arch/powerpc/cpu/ppc4xx/4xx_uart.c
index 1ad19ab..da5bda8 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_uart.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_uart.c
@@ -40,7 +40,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+#if defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || defined(CONFIG_440)
@@ -91,7 +91,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define UDIV_SUBTRACT 0
#define UART0_SDR SDR0_UART0
#define UART1_SDR SDR0_UART1
-#else /* CONFIG_405GP || CONFIG_405CR */
+#else /* CONFIG_405GP */
#define CR0_MASK0x1fff
#define CR0_EXTCLK_ENA 0x00c0
#define CR0_UDIV_POS1
@@ -196,7 +196,7 @@ int get_serial_clock(void)
* Let's handle this in some #ifdef's for the SoC's.
*/
-#if defined(CONFIG_405CR) || defined(CONFIG_405GP)
+#if defined(CONFIG_405GP)
reg = mfdcr(CPC0_CR0) ~CR0_MASK;
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
@@ -223,7 +223,7 @@ int get_serial_clock(void)
#else
clk = CONFIG_SYS_BASE_BAUD * 16;
#endif
-#endif /* CONFIG_405CR */
+#endif
#if defined(CONFIG_405EP)
{
@@ -288,4 +288,4 @@ int get_serial_clock(void)
return clk;
}
-#endif /* CONFIG_405GP || CONFIG_405CR */
+#endif /* CONFIG_405GP */
diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c
index fe05098..5cebafd 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu.c
@@ -320,25 +320,9 @@ int checkcpu (void)
puts(405GP Rev. D);
break;
-#ifdef CONFIG_405GP
- case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
+ case PVR_405GP_RE:
puts(405GP Rev. E);
break;
-#endif
-
- case PVR_405CR_RA:
- puts(405CR Rev. A);
- break;
-
- case PVR_405CR_RB:
- puts(405CR Rev. B);
- break;
-
-#ifdef CONFIG_405CR
- case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
- puts(405CR Rev. C);
- break;
-#endif
case PVR_405GPR_RB:
puts(405GPr Rev. B);
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c
b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index d53d882..d465dcd 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -326,7 +326,7 @@ cpu_init_f (void)
* External Bus Controller (EBC) Setup
*/
#if (defined(CONFIG_SYS_EBC_PB0AP) defined(CONFIG_SYS_EBC_PB0CR))
-#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+#if (defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || defined(CONFIG_405))
/*
diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c
index 3345e73..7e077d5 100644
--- a/arch/powerpc/cpu/ppc4xx/speed.c
+++ b/arch/powerpc/cpu/ppc4xx/speed.c
@@ -21,7 +21,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR)
+#if defined(CONFIG_405GP)
void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
{
@@ -1184,7 +1184,7 @@ ulong get_bus_freq (ulong dummy)
{
ulong val;
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+#if defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || defined(CONFIG_405) || \
defined(CONFIG_440)
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 57ae1d3..1f1ddde 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -833,7 +833,7 @@ _start:
#endif /* CONFIG_440 */
/*/
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+#if defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) ||
Re: [U-Boot] Merging multiple ARM start.S files, what about copyright lines?
Hi Wolfgang, On Wed, 07 Aug 2013 09:33:18 +0200, Wolfgang Denk w...@denx.de wrote: Dear Albert, In message 20130807092318.1fd9bab5@lilith you wrote: The quickest, and preferred by me, way would be to create the new file with all copyright lines simply merged, and rely on the git repo to find out who contributed what. Yes, this makes sense. I could also put one copyright lines block per original start.S file. That would help make quite a big copyrights section. s/help// :) This would not add any real information, but just blow up the file. My vote is going for a merge. Thanks. Best regards, Wolfgang Denk Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] question about selecting a stable U-Boot source code package
Dear TigerLiu, In message fe7aded5c2218b4786c09cd97dc4c49f9eb...@exchbj02.viatech.com.bj you wrote: How to select a stable uboot source code for developing a commercial product? Just use the latest offical release (unless there are specific reasons not to). So, how to identify which package is more stable than another package?! U-Boot provides bug fixes to releases when really needed. Usually this is not the case. Exceptions were v2009.11.1, v2012.04.01, and v2013.01.01. IN all other cases, the release is stable enough. For PandaBoard (TI Company): It seems TI selected u-boot-2012.10.tar.bz2 as its code base. But the latest release. v2013.07 also supports it so why would you got for a version that is already 9 months old? Just use v2013.07. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Summit meetings tend to be like panda matings. The expectations are always high, and the results usually disappointing. - Robert Orben ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2] ppc4xx: Remove CANBT board
Dear Matthias Fuchs, In message 520211c2.2030...@esd.eu you wrote: This board and especially the CPU (PPC405CR) is EOL. Signed-off-by: Matthias Fuchs matthias.fu...@esd.eu --- V2: add entry to doc/README.scrapyard ... diff --git a/doc/README.scrapyard b/doc/README.scrapyard index a0f1fa3..f5ee1ff 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... BoardArchCPUCommit Removed Last known maintainer/contact = +CANBTpowerpc 405CR - 2013-08-07 Matthias Fuchs matthias.fu...@esd.eu Alaska8220 powerpc mpc8220- - Yukon8220powerpc mpc8220- - sorcery powerpc mpc8220- - Could you please use the opportunity of touching this file and insert the missing commit IDs of the last change? As you have to bequeath this task for your board removal to the next committer, you inherit the duty from the previous one. Sorry... Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de No, I'm not going to explain it. If you can't figure it out, you didn't want to know anyway... :-) - Larry Wall in 1991aug7.180856.2...@netlabs.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] fdt_support.c: avoid unintended return from fdt_fixup_memory_banks()
From: Miao Yan miao@windriver.com
fdt_fixup_memory_banks() will add and update /memory node in
device tree blob. In the case that /memory node doesn't exist,
after adding a new one, this function returns error.
The correct behavior should be continuing to update its properties.
Signed-off-by: Miao Yan miao@windriver.com
---
Not sure whether this is fixed or not, we are seeing this error
when trying to update a device tree without the /memory node.
common/fdt_support.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 6b9fa05..65056d7 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -405,10 +405,11 @@ int fdt_fixup_memory_banks(void *blob, u64 start[], u64
size[], int banks)
nodeoffset = fdt_path_offset(blob, /memory);
if (nodeoffset 0) {
nodeoffset = fdt_add_subnode(blob, 0, memory);
- if (nodeoffset 0)
+ if (nodeoffset 0) {
printf(WARNING: could not create /memory: %s.\n,
fdt_strerror(nodeoffset));
- return nodeoffset;
+ return nodeoffset;
+ }
}
err = fdt_setprop(blob, nodeoffset, device_type, memory,
sizeof(memory));
--
1.7.9.5
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Re: [U-Boot] [PATCH V3] ppc4xx: Remove CANBT board
Dear Matthias Fuchs, In message 52022de2.9090...@esd.eu you wrote: This board and especially the CPU (PPC405CR) is EOL. Signed-off-by: Matthias Fuchs matthias.fu...@esd.eu --- V2: add entry to doc/README.scrapyard V3: add missing commit IDs in README.scrapyard Thanks! Acked-by: Wolfgang Denk w...@denx.de Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Bureaucracy is the enemy of innovation. - Mark Shepherd, former President and CEO of Texas Instruments ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2 5/8] drivers: mtd: spi: Modify read/write command for sfl256s flash.
Hi,
On Wed, Aug 7, 2013 at 11:27 AM, Sourav Poddar sourav.pod...@ti.com wrote:
Hi Jagan,
On Wednesday 31 July 2013 12:23 PM, Sourav Poddar wrote:
Hi Jagan,
On Tuesday 23 July 2013 07:53 PM, Sourav Poddar wrote:
+ jagan,
On Tuesday 23 July 2013 02:29 PM, Sourav Poddar wrote:
Reading using the already supported read command is causing regression
after 4k bytes, as a result doing a page by page read. Its happening,
because
ti qpsi controller CS will get de asserted after 4096 bytes.
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
drivers/mtd/spi/spi_flash.c | 32 +++-
1 files changed, 31 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 6a6fe37..5f8db7b 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -303,6 +303,36 @@ int spi_flash_cmd_read_fast(struct spi_flash
*flash, u32 offset,
else
read_len = remain_len;
+#ifdef CONFIG_TI_QSPI
+unsigned long page_addr, byte_addr, page_size;
+size_t chunk_len, actual;
+int ret = 0;
+
+page_size = flash-page_size;
+page_addr = offset / page_size;
+byte_addr = offset % page_size;
+
+for (actual = 0; actual read_len; actual += chunk_len) {
+chunk_len = min(read_len - actual, page_size - byte_addr);
+
+cmd[1] = page_addr 8;
+cmd[2] = page_addr;
+cmd[3] = byte_addr;
+
+ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
+data + actual, chunk_len);
+if (ret 0) {
+debug(SF: read failed);
+break;
+}
+
+byte_addr += chunk_len;
+if (byte_addr == page_size) {
+page_addr++;
+byte_addr = 0;
+}
+}
+#else
spi_flash_addr(offset, cmd);
ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
@@ -311,7 +341,7 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash,
u32 offset,
debug(SF: read failed\n);
break;
}
-
+#endif
offset += read_len;
len -= read_len;
data += read_len;
Elaborating a bit more on this,
There is a constrain on our hardware, which goes like this..
As soon as the words transfered is 4096 bytes, the CS gets deasserted
automatically.
As a result of this bottleneck, I am not able to use the current use read
api in mtd framework.
This requires me to send the read command every time in range upto 4096
bytes only.
To overcome this, I have updated the mtd read based on TI_QSPI config as
done above.
[Jagan]:
Do you have any suggestion of dealing this in a better way?
I don't see a way to get around this apart from updating mtd read
depending on TI_QSPI config.
Any inputs on this?
Any suggestions on the patch?
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Yes, this part is pretty much working as with other s25fl.
Can you point me the respective controller driver for this.
Does linux support this ti_qspi, please point the defconfig if you have.
--
Thanks,
Jagan.
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Re: [U-Boot] [PATCHv2 5/8] drivers: mtd: spi: Modify read/write command for sfl256s flash.
Hi Jagan,
On Wednesday 07 August 2013 05:21 PM, Jagan Teki wrote:
Hi,
On Wed, Aug 7, 2013 at 11:27 AM, Sourav Poddarsourav.pod...@ti.com wrote:
Hi Jagan,
On Wednesday 31 July 2013 12:23 PM, Sourav Poddar wrote:
Hi Jagan,
On Tuesday 23 July 2013 07:53 PM, Sourav Poddar wrote:
+ jagan,
On Tuesday 23 July 2013 02:29 PM, Sourav Poddar wrote:
Reading using the already supported read command is causing regression
after 4k bytes, as a result doing a page by page read. Its happening,
because
ti qpsi controller CS will get de asserted after 4096 bytes.
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
drivers/mtd/spi/spi_flash.c | 32 +++-
1 files changed, 31 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 6a6fe37..5f8db7b 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -303,6 +303,36 @@ int spi_flash_cmd_read_fast(struct spi_flash
*flash, u32 offset,
else
read_len = remain_len;
+#ifdef CONFIG_TI_QSPI
+unsigned long page_addr, byte_addr, page_size;
+size_t chunk_len, actual;
+int ret = 0;
+
+page_size = flash-page_size;
+page_addr = offset / page_size;
+byte_addr = offset % page_size;
+
+for (actual = 0; actual read_len; actual += chunk_len) {
+chunk_len = min(read_len - actual, page_size - byte_addr);
+
+cmd[1] = page_addr 8;
+cmd[2] = page_addr;
+cmd[3] = byte_addr;
+
+ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
+data + actual, chunk_len);
+if (ret 0) {
+debug(SF: read failed);
+break;
+}
+
+byte_addr += chunk_len;
+if (byte_addr == page_size) {
+page_addr++;
+byte_addr = 0;
+}
+}
+#else
spi_flash_addr(offset, cmd);
ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
@@ -311,7 +341,7 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash,
u32 offset,
debug(SF: read failed\n);
break;
}
-
+#endif
offset += read_len;
len -= read_len;
data += read_len;
Elaborating a bit more on this,
There is a constrain on our hardware, which goes like this..
As soon as the words transfered is 4096 bytes, the CS gets deasserted
automatically.
As a result of this bottleneck, I am not able to use the current use read
api in mtd framework.
This requires me to send the read command every time in range upto 4096
bytes only.
To overcome this, I have updated the mtd read based on TI_QSPI config as
done above.
[Jagan]:
Do you have any suggestion of dealing this in a better way?
I don't see a way to get around this apart from updating mtd read
depending on TI_QSPI config.
Any inputs on this?
Any suggestions on the patch?
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Yes, this part is pretty much working as with other s25fl.
Can you point me the respective controller driver for this.
Thanks for the response.
This is the link to uboot patches which I submitted to uboot mailing list.
http://patchwork.ozlabs.org/patch/260989/
http://patchwork.ozlabs.org/patch/260990/
http://patchwork.ozlabs.org/patch/260991/
http://patchwork.ozlabs.org/patch/260992/
http://patchwork.ozlabs.org/patch/260994/
http://patchwork.ozlabs.org/patch/260993/
http://patchwork.ozlabs.org/patch/260996/
http://patchwork.ozlabs.org/patch/260995/
Above are the links to uboot patches containing all def configs and
uboot ti qspi driver.
As communicated earlier, there is a limitation in our qspi controller
driver, wherein after every
4096 bytes CS gets de asserted. So, I had to modify the above read
framework to do a page read.
Need better way to handle this limitation, so that the above patch
series can get upstreamed.
Does linux support this ti_qspi, please point the defconfig if you have.
Patches for linux is under review and still not mainlined.
https://patchwork.kernel.org/patch/2838342/
Thanks,
Sourav
--
Thanks,
Jagan.
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Re: [U-Boot] [PATCH] wandboard: add pxe support, set default boot command like highbank
On Tue, Aug 06, 2013 at 06:11:25PM -0500, Dennis Gilmore wrote: On Tue, 6 Aug 2013 17:42:31 -0400 Tom Rini tr...@ti.com wrote: On Tue, Aug 06, 2013 at 11:22:22AM -0500, Dennis Gilmore wrote: [snip] The only way I could see having us write a file to disk with the environment working is if all boards implement standard variable to define the memory locations and that is compiled into the u-boot binary. some variables that would need to be compiled in fdt_addr fdt_addr_r Why two? from cmd_pxe.c [snip] u-boot by default would load a dtb to fdt_addr but a user could at least in the pxe/extlinux case load their own dtb if the want/need to. the only way a dtb would be optional is if fdtfile is not set OK, so fdt_addr is for a memory-mapped location of the DT existing somewhere already, basically. kernel_addr_r ramdisk_addr_r pxefile_addr_r scr_addr_r uenv_addr_r this should allow for for people to use boot.scr uEnv.txt or pxe/extlinux This is what I think we need to work towards. A board opting into this standard must set CONFIG_CMD_A/B/C (or maybe we add a CONFIG_SUPPORT_GENERIC_LINUX_DISTRO that does this in one of the fallback files, whatever) and provide the following variables PLUS a, and this needs some thinking I think, auto-boot tries to load said file from ... ? We cannot provide a built-in environment that works for every distro and case, we want the distro to tell us things it knows, and we'll tell it what it can't easily know. we absolutely can, I would like for u-boot to load a dtb before doing anything. u-boot should know what devices can be booted from and likely an order of preference. i.e. removable media through to fixed, and finally pxe. Looking at a couple of device trees, no, we can't. I don't see any useful information like this is an SD controller for example (and all of the mmc bindings that might provide a reliable clue are optional ones). So, at the high level, if U-Boot relied on DTs in every driver, we might be able to do what you're talking about. But we don't do that today, and probably won't for a long time, if ever. But we will know what devices are likely to exist and be bootable, at build time. What we can do is try and load a file from everywhere we expect might be someplace with this file in it. We could even set some standard variables based on having found and loaded this file, so it can assume that everything else exists in this same place (or the file we have loaded knows better). i would like for u-boot to first try to load /boot/extlinux/extlinux.conf then /extlinux/extlinux.conf failing that try to load a /boot/uEnv.txt then /uEnv.txt and import that running with what is in it, then falling back to a /boot/boot.scr then /boot.scr then finally running dhcp, pxe get, and pxe boot. I'd like to see most of that logic held in the file we load (so that when something replaces extlinux.conf as the preferred method, it just works still, or whatever) and run a command from. And fall back to dhcp+pxe for the install case. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESEND PATCH v5 1/1] socfpga: Adding configuration for development kit
On Tue, 2013-08-06 at 11:00 -0500, Dinh Nguyen wrote: On Tue, 2013-08-06 at 09:08 -0500, Chin Liang See wrote: Separating the configuration file for Virtual Target and real hardware Cyclone V development kit Signed-off-by: Chin Liang See cl...@altera.com Reviewed-by: Pavel Machek Include Pavel's email address. Noted will fix in v6 Cc: Wolfgang Denk w...@denx.de CC: Pavel Machek pa...@denx.de Cc: Dinh Nguyen dingu...@altera.com Cc: Tom Rini tr...@ti.com Cc: Albert Aribaud albert.u.b...@aribaud.net --- Changes for v2: - Fixed the word wrap issue within patch Changes for v3: - Fixed the long subject of the patch Changes for v4: - Added change log for each revision change Changes for v5: - Added Reviewed-by: Pavel Machek - Cc: Tom Rini Re-org this to have the latest, v5 at the top. Noted will fix in v6 Thanks Chin Liang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESEND PATCH v6 1/2] socfpga: Adding System Manager driver
On Tue, 2013-08-06 at 11:03 -0500, Dinh Nguyen wrote: On Tue, 2013-08-06 at 09:10 -0500, Chin Liang See wrote: Adding System Manager driver which will configure the pin mux for real hardware Cyclone V development kit (not Virtual Platform) Signed-off-by: Chin Liang See cl...@altera.com Reviewed-by: Pavel Machek pa...@denx.de Cc: Wolfgang Denk w...@denx.de CC: Pavel Machek pa...@denx.de Cc: Dinh Nguyen dingu...@altera.com Cc: Tom Rini tr...@ti.com Cc: Albert Aribaud albert.u.b...@aribaud.net --- Changes for v2: - Fixed the word wrap issue within patch Changes for v3: - Fixed the long subject of the patch - Fixed the comment within the code Changes for v4: - Added change log for each revision change Changes for v5: - Updated the license header for system_manager.c - Cc: Tom Rini Changes for v6: - Updated the license header for system_manager.c and .h to SPDX Re-org this with latest at the top. Noted will fix in v7 Thanks Chin Liang Besides that: Acked-by: Dinh Nguyen dingu...@altera.com Dinh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESEND PATCH v5 2/2] socfpga: Adding pin mux handoff files
On Tue, 2013-08-06 at 11:04 -0500, Dinh Nguyen wrote: On Tue, 2013-08-06 at 09:10 -0500, Chin Liang See wrote: Adding the generated pin mux configuration by Preloader Generator tool Signed-off-by: Chin Liang See cl...@altera.com Reviewed-by: Pavel Machek pa...@denx.de Cc: Wolfgang Denk w...@denx.de CC: Pavel Machek pa...@denx.de Cc: Dinh Nguyen dingu...@altera.com Cc: Tom Rini tr...@ti.com Cc: Albert Aribaud albert.u.b...@aribaud.net --- Changes for v2: - Fixed the word wrap issue within patch Changes for v3: - Fixed the long subject of the patch Changes for v4: - Added change log for each revision change Changes for v5: - Updated the license header for reset_manager.c - Updated the subject Re-org with latest changes on top. Noted will fix in v6 Thanks Chin Liang Acked-by: Dinh Nguyen dingu...@altera.com Dinh --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2 5/8] drivers: mtd: spi: Modify read/write command for sfl256s flash.
On Wed, Aug 7, 2013 at 5:34 PM, Sourav Poddar sourav.pod...@ti.com wrote:
Hi Jagan,
On Wednesday 07 August 2013 05:21 PM, Jagan Teki wrote:
Hi,
On Wed, Aug 7, 2013 at 11:27 AM, Sourav Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Wednesday 31 July 2013 12:23 PM, Sourav Poddar wrote:
Hi Jagan,
On Tuesday 23 July 2013 07:53 PM, Sourav Poddar wrote:
+ jagan,
On Tuesday 23 July 2013 02:29 PM, Sourav Poddar wrote:
Reading using the already supported read command is causing regression
after 4k bytes, as a result doing a page by page read. Its happening,
because
ti qpsi controller CS will get de asserted after 4096 bytes.
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
drivers/mtd/spi/spi_flash.c | 32 +++-
1 files changed, 31 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 6a6fe37..5f8db7b 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -303,6 +303,36 @@ int spi_flash_cmd_read_fast(struct spi_flash
*flash, u32 offset,
else
read_len = remain_len;
+#ifdef CONFIG_TI_QSPI
+unsigned long page_addr, byte_addr, page_size;
+size_t chunk_len, actual;
+int ret = 0;
+
+page_size = flash-page_size;
+page_addr = offset / page_size;
+byte_addr = offset % page_size;
+
+for (actual = 0; actual read_len; actual += chunk_len) {
+chunk_len = min(read_len - actual, page_size -
byte_addr);
+
+cmd[1] = page_addr 8;
+cmd[2] = page_addr;
+cmd[3] = byte_addr;
+
+ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
+data + actual, chunk_len);
+if (ret 0) {
+debug(SF: read failed);
+break;
+}
+
+byte_addr += chunk_len;
+if (byte_addr == page_size) {
+page_addr++;
+byte_addr = 0;
+}
+}
+#else
spi_flash_addr(offset, cmd);
ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
@@ -311,7 +341,7 @@ int spi_flash_cmd_read_fast(struct spi_flash
*flash,
u32 offset,
debug(SF: read failed\n);
break;
}
-
+#endif
offset += read_len;
len -= read_len;
data += read_len;
Elaborating a bit more on this,
There is a constrain on our hardware, which goes like this..
As soon as the words transfered is 4096 bytes, the CS gets deasserted
automatically.
As a result of this bottleneck, I am not able to use the current use
read
api in mtd framework.
This requires me to send the read command every time in range upto 4096
bytes only.
To overcome this, I have updated the mtd read based on TI_QSPI config
as
done above.
[Jagan]:
Do you have any suggestion of dealing this in a better way?
I don't see a way to get around this apart from updating mtd read
depending on TI_QSPI config.
Any inputs on this?
Any suggestions on the patch?
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Yes, this part is pretty much working as with other s25fl.
Can you point me the respective controller driver for this.
Thanks for the response.
This is the link to uboot patches which I submitted to uboot mailing list.
http://patchwork.ozlabs.org/patch/260989/
http://patchwork.ozlabs.org/patch/260990/
http://patchwork.ozlabs.org/patch/260991/
http://patchwork.ozlabs.org/patch/260992/
http://patchwork.ozlabs.org/patch/260994/
http://patchwork.ozlabs.org/patch/260993/
http://patchwork.ozlabs.org/patch/260996/
http://patchwork.ozlabs.org/patch/260995/
Above are the links to uboot patches containing all def configs and uboot ti
qspi driver.
As communicated earlier, there is a limitation in our qspi controller
driver, wherein after every
4096 bytes CS gets de asserted. So, I had to modify the above read framework
to do a page read.
Need better way to handle this limitation, so that the above patch series
can get upstreamed.
Does linux support this ti_qspi, please point the defconfig if you have.
Patches for linux is under review and still not mainlined.
https://patchwork.kernel.org/patch/2838342/
Thanks, please give me some time I will look at these and let u know
early next week.
--
Thanks,
Jagan.
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[U-Boot] [PATCH v6 2/2] socfpga: Adding pin mux handoff files
Adding the generated pin mux configuration by Preloader
Generator tool
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
Acked-by: Dinh Nguyen dingu...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v6:
- Re-shuffle the change list
Changes for v5:
- Updated the subject
Changes for v4:
- Added change log for each revision change
Changes for v3:
- Fixed the long subject of the patch
Changes for v2:
- Fixed the word wrap issue within patch
---
board/altera/socfpga/pinmux_config.c | 214 ++
board/altera/socfpga/pinmux_config.h | 54 +
2 files changed, 268 insertions(+)
create mode 100644 board/altera/socfpga/pinmux_config.c
create mode 100644 board/altera/socfpga/pinmux_config.h
diff --git a/board/altera/socfpga/pinmux_config.c
b/board/altera/socfpga/pinmux_config.c
new file mode 100644
index 000..8b09005
--- /dev/null
+++ b/board/altera/socfpga/pinmux_config.c
@@ -0,0 +1,214 @@
+/* This file is generated by Preloader Generator */
+
+#include pinmux_config.h
+
+/* pin mux configuration data */
+unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
+ 0, /* EMACIO0 - Unused */
+ 2, /* EMACIO1 - USB */
+ 2, /* EMACIO2 - USB */
+ 2, /* EMACIO3 - USB */
+ 2, /* EMACIO4 - USB */
+ 2, /* EMACIO5 - USB */
+ 2, /* EMACIO6 - USB */
+ 2, /* EMACIO7 - USB */
+ 2, /* EMACIO8 - USB */
+ 0, /* EMACIO9 - Unused */
+ 2, /* EMACIO10 - USB */
+ 2, /* EMACIO11 - USB */
+ 2, /* EMACIO12 - USB */
+ 2, /* EMACIO13 - USB */
+ 0, /* EMACIO14 - N/A */
+ 0, /* EMACIO15 - N/A */
+ 0, /* EMACIO16 - N/A */
+ 0, /* EMACIO17 - N/A */
+ 0, /* EMACIO18 - N/A */
+ 0, /* EMACIO19 - N/A */
+ 3, /* FLASHIO0 - SDMMC */
+ 3, /* FLASHIO1 - SDMMC */
+ 3, /* FLASHIO2 - SDMMC */
+ 3, /* FLASHIO3 - SDMMC */
+ 0, /* FLASHIO4 - SDMMC */
+ 0, /* FLASHIO5 - SDMMC */
+ 0, /* FLASHIO6 - SDMMC */
+ 0, /* FLASHIO7 - SDMMC */
+ 0, /* FLASHIO8 - SDMMC */
+ 3, /* FLASHIO9 - SDMMC */
+ 3, /* FLASHIO10 - SDMMC */
+ 3, /* FLASHIO11 - SDMMC */
+ 3, /* GENERALIO0 - TRACE */
+ 3, /* GENERALIO1 - TRACE */
+ 3, /* GENERALIO2 - TRACE */
+ 3, /* GENERALIO3 - TRACE */
+ 3, /* GENERALIO4 - TRACE */
+ 3, /* GENERALIO5 - TRACE */
+ 3, /* GENERALIO6 - TRACE */
+ 3, /* GENERALIO7 - TRACE */
+ 3, /* GENERALIO8 - TRACE */
+ 3, /* GENERALIO9 - SPIM0 */
+ 3, /* GENERALIO10 - SPIM0 */
+ 3, /* GENERALIO11 - SPIM0 */
+ 3, /* GENERALIO12 - SPIM0 */
+ 2, /* GENERALIO13 - CAN0 */
+ 2, /* GENERALIO14 - CAN0 */
+ 3, /* GENERALIO15 - I2C0 */
+ 3, /* GENERALIO16 - I2C0 */
+ 2, /* GENERALIO17 - UART0 */
+ 2, /* GENERALIO18 - UART0 */
+ 0, /* GENERALIO19 - N/A */
+ 0, /* GENERALIO20 - N/A */
+ 0, /* GENERALIO21 - N/A */
+ 0, /* GENERALIO22 - N/A */
+ 0, /* GENERALIO23 - N/A */
+ 0, /* GENERALIO24 - N/A */
+ 0, /* GENERALIO25 - N/A */
+ 0, /* GENERALIO26 - N/A */
+ 0, /* GENERALIO27 - N/A */
+ 0, /* GENERALIO28 - N/A */
+ 0, /* GENERALIO29 - N/A */
+ 0, /* GENERALIO30 - N/A */
+ 0, /* GENERALIO31 - N/A */
+ 2, /* MIXED1IO0 - EMAC */
+ 2, /* MIXED1IO1 - EMAC */
+ 2, /* MIXED1IO2 - EMAC */
+ 2, /* MIXED1IO3 - EMAC */
+ 2, /* MIXED1IO4 - EMAC */
+ 2, /* MIXED1IO5 - EMAC */
+ 2, /* MIXED1IO6 - EMAC */
+ 2, /* MIXED1IO7 - EMAC */
+ 2, /* MIXED1IO8 - EMAC */
+ 2, /* MIXED1IO9 - EMAC */
+ 2, /* MIXED1IO10 - EMAC */
+ 2, /* MIXED1IO11 - EMAC */
+ 2, /* MIXED1IO12 - EMAC */
+ 2, /* MIXED1IO13 - EMAC */
+ 0, /* MIXED1IO14 - Unused */
+ 3, /* MIXED1IO15 - QSPI */
+ 3, /* MIXED1IO16 - QSPI */
+ 3, /* MIXED1IO17 - QSPI */
+ 3, /* MIXED1IO18 - QSPI */
+ 3, /* MIXED1IO19 - QSPI */
+ 3, /* MIXED1IO20 - QSPI */
+ 0, /* MIXED1IO21 - GPIO */
+ 0, /* MIXED2IO0 - N/A */
+ 0, /* MIXED2IO1 - N/A */
+ 0, /* MIXED2IO2 - N/A */
+ 0, /* MIXED2IO3 - N/A */
+ 0, /* MIXED2IO4 - N/A */
+ 0, /* MIXED2IO5 - N/A */
+ 0, /* MIXED2IO6 - N/A */
+ 0, /* MIXED2IO7 - N/A */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /*
[U-Boot] [PATCH v7 1/2] socfpga: Adding System Manager driver
Adding System Manager driver which will configure the
pin mux for real hardware Cyclone V development kit
(not Virtual Platform)
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
Acked-by: Dinh Nguyen dingu...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v7:
- Re-shuffle the change list
Changes for v6:
- Updated the license header for system_manager.c and .h to SPDX
Changes for v5:
- Updated the license header for system_manager.c
- Cc: Tom Rini
Changes for v4:
- Added change log for each revision change
Changes for v3:
- Fixed the long subject of the patch
- Fixed the comment within the code
Changes for v2:
- Fixed the word wrap issue within patch
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/spl.c |6
arch/arm/cpu/armv7/socfpga/system_manager.c| 29
.../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
arch/arm/include/asm/arch-socfpga/system_manager.h | 22 +++
board/altera/socfpga/Makefile |4 ++-
include/configs/socfpga_cyclone5.h |1 +
7 files changed, 63 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/system_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/system_manager.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 5024fc5..0859e44 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -13,7 +13,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
-COBJS-y:= misc.o timer.o reset_manager.o
+COBJS-y:= misc.o timer.o reset_manager.o system_manager.o
COBJS-$(CONFIG_SPL_BUILD) += spl.o
COBJS := $(COBJS-y)
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index 2b9be28..74bceab 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -12,6 +12,7 @@
#include image.h
#include asm/arch/reset_manager.h
#include spl.h
+#include asm/arch/system_manager.h
DECLARE_GLOBAL_DATA_PTR;
@@ -25,6 +26,11 @@ u32 spl_boot_device(void)
*/
void spl_board_init(void)
{
+#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+ /* configure the pin muxing through system manager */
+ sysmgr_pinmux_init();
+#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
+
/* de-assert reset for peripherals and bridges based on handoff */
reset_deassert_peripherals_handoff();
diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c
b/arch/arm/cpu/armv7/socfpga/system_manager.c
new file mode 100644
index 000..b992221
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/system_manager.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2013 Altera Corporation www.altera.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/system_manager.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Configure all the pin muxes
+ */
+void sysmgr_pinmux_init(void)
+{
+ unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET;
+
+ const unsigned long *pval = sys_mgr_init_table;
+ unsigned long i;
+
+ for (i = 0; i ARRAY_SIZE(sys_mgr_init_table);
+ i++, offset += sizeof(unsigned long)) {
+ writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset));
+ }
+}
+
+
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
index 1182a13..50c4ebd 100644
--- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -12,5 +12,6 @@
#define SOCFPGA_UART1_ADDRESS 0xffc03000
#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
#endif /* _SOCFPGA_BASE_ADDRS_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h
b/arch/arm/include/asm/arch-socfpga/system_manager.h
new file mode 100644
index 000..d965d25
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/system_manager.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2013 Altera Corporation www.altera.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef_SYSTEM_MANAGER_H_
+#define_SYSTEM_MANAGER_H_
+
+#ifndef __ASSEMBLY__
+
+void sysmgr_pinmux_init(void);
+
+/* declaration for handoff table type */
+extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM];
+
+#endif
+
+
+#define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400)
+
+#endif /* _SYSTEM_MANAGER_H_ */
diff --git a/board/altera/socfpga/Makefile b/board/altera/socfpga/Makefile
index 43bbc37..3092387 100644
--- a/board/altera/socfpga/Makefile
+++ b/board/altera/socfpga/Makefile
@@ -26,8 +26,10 @@ include
[U-Boot] [PATCH v6 1/1] socfpga: Adding configuration for development kit
Separating the configuration file for Virtual
Target and real hardware Cyclone V development kit
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v6:
- Re-shuffle the change list
Changes for v5:
- Added Reviewed-by: Pavel Machek
- Cc: Tom Rini
Changes for v4:
- Added change log for each revision change
Changes for v3:
- Fixed the long subject of the patch
Changes for v2:
- Fixed the word wrap issue within patch
---
include/configs/socfpga_cyclone5.h | 28 +---
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/include/configs/socfpga_cyclone5.h
b/include/configs/socfpga_cyclone5.h
index b5a7a9a..06aeba6 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -11,6 +11,8 @@
/*
* High level configuration
*/
+/* Virtual target or real hardware */
+#define CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_ARMV7
#define CONFIG_L2_OFF
@@ -21,11 +23,12 @@
#define CONFIG_SINGLE_BOOTLOADER
#define CONFIG_SOCFPGA
+/* base address for .text section */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_SYS_TEXT_BASE 0x0840
-#define V_NS16550_CLK 100
-#define CONFIG_BAUDRATE57600
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_TIMER_CLOCK_KHZ 2400
+#else
+#define CONFIG_SYS_TEXT_BASE 0x0140
+#endif
#define CONFIG_SYS_LOAD_ADDR 0x7fc0
/* Console I/O Buffer Size */
@@ -154,7 +157,7 @@
/* SDRAM Bank #1 */
#define CONFIG_SYS_SDRAM_BASE 0x
/* SDRAM memory size */
-#define PHYS_SDRAM_1_SIZE 0x8000
+#define PHYS_SDRAM_1_SIZE 0x4000
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_START 0x
@@ -170,8 +173,13 @@
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1UART0_BASE
-
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define V_NS16550_CLK 100
+#else
+#define V_NS16550_CLK 1
+#endif
+#define CONFIG_BAUDRATE115200
/*
* FLASH
@@ -184,9 +192,15 @@
/* This timer use eosc1 where the clock frequency is fixed
* throughout any condition */
#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
-
/* reload value when timer count to zero */
#define TIMER_LOAD_VAL 0x
+/* Timer info */
+#define CONFIG_SYS_HZ 1000
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_TIMER_CLOCK_KHZ 2400
+#else
+#define CONFIG_TIMER_CLOCK_KHZ 25000
+#endif
#define CONFIG_ENV_IS_NOWHERE
--
1.7.9.5
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Re: [U-Boot] [PATCHv2 5/8] drivers: mtd: spi: Modify read/write command for sfl256s flash.
On Wednesday 07 August 2013 08:35 PM, Jagan Teki wrote:
On Wed, Aug 7, 2013 at 5:34 PM, Sourav Poddarsourav.pod...@ti.com wrote:
Hi Jagan,
On Wednesday 07 August 2013 05:21 PM, Jagan Teki wrote:
Hi,
On Wed, Aug 7, 2013 at 11:27 AM, Sourav Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Wednesday 31 July 2013 12:23 PM, Sourav Poddar wrote:
Hi Jagan,
On Tuesday 23 July 2013 07:53 PM, Sourav Poddar wrote:
+ jagan,
On Tuesday 23 July 2013 02:29 PM, Sourav Poddar wrote:
Reading using the already supported read command is causing regression
after 4k bytes, as a result doing a page by page read. Its happening,
because
ti qpsi controller CS will get de asserted after 4096 bytes.
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
drivers/mtd/spi/spi_flash.c | 32 +++-
1 files changed, 31 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 6a6fe37..5f8db7b 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -303,6 +303,36 @@ int spi_flash_cmd_read_fast(struct spi_flash
*flash, u32 offset,
else
read_len = remain_len;
+#ifdef CONFIG_TI_QSPI
+unsigned long page_addr, byte_addr, page_size;
+size_t chunk_len, actual;
+int ret = 0;
+
+page_size = flash-page_size;
+page_addr = offset / page_size;
+byte_addr = offset % page_size;
+
+for (actual = 0; actualread_len; actual += chunk_len) {
+chunk_len = min(read_len - actual, page_size -
byte_addr);
+
+cmd[1] = page_addr8;
+cmd[2] = page_addr;
+cmd[3] = byte_addr;
+
+ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
+data + actual, chunk_len);
+if (ret0) {
+debug(SF: read failed);
+break;
+}
+
+byte_addr += chunk_len;
+if (byte_addr == page_size) {
+page_addr++;
+byte_addr = 0;
+}
+}
+#else
spi_flash_addr(offset, cmd);
ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
@@ -311,7 +341,7 @@ int spi_flash_cmd_read_fast(struct spi_flash
*flash,
u32 offset,
debug(SF: read failed\n);
break;
}
-
+#endif
offset += read_len;
len -= read_len;
data += read_len;
Elaborating a bit more on this,
There is a constrain on our hardware, which goes like this..
As soon as the words transfered is 4096 bytes, the CS gets deasserted
automatically.
As a result of this bottleneck, I am not able to use the current use
read
api in mtd framework.
This requires me to send the read command every time in range upto 4096
bytes only.
To overcome this, I have updated the mtd read based on TI_QSPI config
as
done above.
[Jagan]:
Do you have any suggestion of dealing this in a better way?
I don't see a way to get around this apart from updating mtd read
depending on TI_QSPI config.
Any inputs on this?
Any suggestions on the patch?
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Yes, this part is pretty much working as with other s25fl.
Can you point me the respective controller driver for this.
Thanks for the response.
This is the link to uboot patches which I submitted to uboot mailing list.
http://patchwork.ozlabs.org/patch/260989/
http://patchwork.ozlabs.org/patch/260990/
http://patchwork.ozlabs.org/patch/260991/
http://patchwork.ozlabs.org/patch/260992/
http://patchwork.ozlabs.org/patch/260994/
http://patchwork.ozlabs.org/patch/260993/
http://patchwork.ozlabs.org/patch/260996/
http://patchwork.ozlabs.org/patch/260995/
Above are the links to uboot patches containing all def configs and uboot ti
qspi driver.
As communicated earlier, there is a limitation in our qspi controller
driver, wherein after every
4096 bytes CS gets de asserted. So, I had to modify the above read framework
to do a page read.
Need better way to handle this limitation, so that the above patch series
can get upstreamed.
Does linux support this ti_qspi, please point the defconfig if you have.
Patches for linux is under review and still not mainlined.
https://patchwork.kernel.org/patch/2838342/
Thanks, please give me some time I will look at these and let u know
early next week.
Thanks!!
--
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Re: [U-Boot] [RESEND PATCH v5 1/1] socfpga: Creating driver for Reset Manager
On Tue, 2013-08-06 at 11:01 -0500, Dinh Nguyen wrote: On Tue, 2013-08-06 at 09:09 -0500, Chin Liang See wrote: Consolidating reset code into reset_manager.c. Also separating reset configuration for virtual target and real hardware Cyclone V development kit Signed-off-by: Chin Liang See cl...@altera.com Reviewed-by: Pavel Machek Add Pavel's email address. Noted will fix in v6 Cc: Wolfgang Denk w...@denx.de CC: Pavel Machek pa...@denx.de Cc: Dinh Nguyen dingu...@altera.com Cc: Tom Rini tr...@ti.com Cc: Albert Aribaud albert.u.b...@aribaud.net --- Changes for v2: - Fixed the long subject of the patch - Consolidated the reset_manager structure between virtual target and dev kit Changes for v3: - Added change log for each revision change - Removed the between the date of copyright header Changes for v4: - Updated the license header for reset_manager.c Changes for v5: - Updated the license header for reset_manager.c to SPDX re-org to have latest changes, v5, at the top. Noted will fix in v6 Thanks Chin Liang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 1/1] socfpga: Creating driver for Reset Manager
Consolidating reset code into reset_manager.c. Also
separating reset configuration for virtual target and
real hardware Cyclone V development kit
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v6:
- Re-shuffle the change list
Changes for v5:
- Updated the license header for reset_manager.c to SPDX
Changes for v4:
- Updated the license header for reset_manager.c
Changes for v3:
- Added change log for each revision change
- Removed the between the date of copyright header
Changes for v2:
- Fixed the long subject of the patch
- Consolidated the reset_manager structure between virtual
target and dev kit
---
arch/arm/cpu/armv7/socfpga/Makefile |2 +-
arch/arm/cpu/armv7/socfpga/misc.c | 27 --
arch/arm/cpu/armv7/socfpga/reset_manager.c| 41 +
arch/arm/include/asm/arch-socfpga/reset_manager.h | 10 +++--
4 files changed, 49 insertions(+), 31 deletions(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/reset_manager.c
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index 3b48ac9..5024fc5 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -13,7 +13,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
-COBJS-y:= misc.o timer.o
+COBJS-y:= misc.o timer.o reset_manager.o
COBJS-$(CONFIG_SPL_BUILD) += spl.o
COBJS := $(COBJS-y)
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
b/arch/arm/cpu/armv7/socfpga/misc.c
index 66edb3c..2f1c716 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -6,36 +6,9 @@
#include common.h
#include asm/io.h
-#include asm/arch/reset_manager.h
DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_reset_manager *reset_manager_base =
- (void *)SOCFPGA_RSTMGR_ADDRESS;
-
-/*
- * Write the reset manager register to cause reset
- */
-void reset_cpu(ulong addr)
-{
- /* request a warm reset */
- writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, reset_manager_base-ctrl);
- /*
-* infinite loop here as watchdog will trigger and reset
-* the processor
-*/
- while (1)
- ;
-}
-
-/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
-{
- writel(0, reset_manager_base-per_mod_reset);
-}
-
int dram_init(void)
{
gd-ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c
b/arch/arm/cpu/armv7/socfpga/reset_manager.c
new file mode 100644
index 000..95a3e92
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2013 Altera Corporation www.altera.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+
+#include common.h
+#include asm/io.h
+#include asm/arch/reset_manager.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_reset_manager *reset_manager_base =
+ (void *)SOCFPGA_RSTMGR_ADDRESS;
+
+/*
+ * Write the reset manager register to cause reset
+ */
+void reset_cpu(ulong addr)
+{
+ /* request a warm reset */
+ writel((1 RSTMGR_CTRL_SWWARMRSTREQ_LSB),
+ reset_manager_base-ctrl);
+ /*
+* infinite loop here as watchdog will trigger and reset
+* the processor
+*/
+ while (1)
+ ;
+}
+
+/*
+ * Release peripherals from reset based on handoff
+ */
+void reset_deassert_peripherals_handoff(void)
+{
+ writel(0, reset_manager_base-per_mod_reset);
+}
+
+
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h
b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index 13d7357..3e95476 100644
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -11,16 +11,20 @@ void reset_cpu(ulong addr);
void reset_deassert_peripherals_handoff(void);
struct socfpga_reset_manager {
- u32 padding1;
+ u32 status;
u32 ctrl;
- u32 padding2;
- u32 padding3;
+ u32 counts;
+ u32 padding1;
u32 mpu_mod_reset;
u32 per_mod_reset;
u32 per2_mod_reset;
u32 brg_mod_reset;
};
+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
+#else
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+#endif
#endif /* _RESET_MANAGER_H_ */
--
1.7.9.5
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[U-Boot] [PATCH 2/2] OMAP3: igep00x0: allow booting with a FDT from MMC
IGEP boards now have Device Tree support in the mainline
kernel. To boot an IGEP board using a DT, a uEnv.txt plain
text file could be used to define a custom uenvcmd that will
be run by the default boot command.
It is more convenient to change the default boot command to
allow loading a FDT if it is stored in the boot dir of the
rootfs uSD/MMC partition.
If no FDT is found then the defaul command tries to boot a
zImage without a DT using legacy boot.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
board/isee/igep00x0/igep00x0.c | 14 ++
include/configs/igep00x0.h | 13 -
2 files changed, 26 insertions(+), 1 deletions(-)
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index 77a9bc6..7a7500b 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -138,6 +138,18 @@ int board_mmc_init(bd_t *bis)
}
#endif
+void set_fdt(void)
+{
+ switch (gd-bd-bi_arch_number) {
+ case MACH_TYPE_IGEP0020:
+ setenv(dtbfile, omap3-igep0020.dtb);
+ break;
+ case MACH_TYPE_IGEP0030:
+ setenv(dtbfile, omap3-igep0030.dtb);
+ break;
+ }
+}
+
/*
* Routine: misc_init_r
* Description: Configure board specific parts
@@ -150,6 +162,8 @@ int misc_init_r(void)
dieid_num_r();
+ set_fdt();
+
return 0;
}
diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h
index b3c57f4..13d58a4 100644
--- a/include/configs/igep00x0.h
+++ b/include/configs/igep00x0.h
@@ -137,6 +137,9 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
usbtty=cdc_acm\0 \
loadaddr=0x8200\0 \
+ dtbaddr=0x8160\0 \
+ bootdir=/boot\0 \
+ bootfile=zImage\0 \
usbtty=cdc_acm\0 \
console=ttyO2,115200n8\0 \
mpurate=auto\0 \
@@ -167,10 +170,13 @@
loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0 \
importbootenv=echo Importing environment from mmc ...; \
env import -t $loadaddr $filesize\0 \
- loadzimage=load mmc ${mmcdev} ${loadaddr} zImage\0 \
+ loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0 \
+ loadfdt=load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0 \
mmcboot=echo Booting from mmc ...; \
run mmcargs; \
bootz ${loadaddr}\0 \
+ mmcbootfdt=echo Booting with DT from mmc ...; \
+ bootz ${loadaddr} - ${dtbaddr}\0 \
nandboot=echo Booting from onenand ...; \
run nandargs; \
onenand read ${loadaddr} 28 40; \
@@ -187,6 +193,11 @@
run uenvcmd; \
fi; \
if run loadzimage; then \
+ if test -n $dtbfile; then \
+ if run loadfdt; then \
+ run mmcbootfdt; \
+ fi; \
+ fi; \
run mmcboot; \
fi; \
fi; \
--
1.7.7.6
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[U-Boot] [PATCH 1/2] ARM: igep00x0.h: Enable the use of CMD_EXT4, CMD_FS_GENERIC and zImage.
From: Enric Balletbo i Serra eballe...@gmail.com
Able to load the kernel from some form of ext[234] or FAT. Also, with v3.9 and
later of the Linux Kernel, uImage isn't builtable anymore by default, so we
should switch to use the bootz command.
Signed-off-by: Enric Balletbo i Serra eballe...@gmail.com
---
include/configs/igep00x0.h | 13 +++--
1 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h
index c17267e..b3c57f4 100644
--- a/include/configs/igep00x0.h
+++ b/include/configs/igep00x0.h
@@ -97,8 +97,9 @@
#include config_cmd_default.h
#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2/* EXT2 Support */
+#define CONFIG_CMD_EXT4
#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
#ifdef CONFIG_BOOT_ONENAND
@@ -163,17 +164,17 @@
omapdss.def_disp=${defaultdisplay} \
root=${nandroot} \
rootfstype=${nandrootfstype}\0 \
- loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0 \
+ loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0 \
importbootenv=echo Importing environment from mmc ...; \
env import -t $loadaddr $filesize\0 \
- loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0 \
+ loadzimage=load mmc ${mmcdev} ${loadaddr} zImage\0 \
mmcboot=echo Booting from mmc ...; \
run mmcargs; \
- bootm ${loadaddr}\0 \
+ bootz ${loadaddr}\0 \
nandboot=echo Booting from onenand ...; \
run nandargs; \
onenand read ${loadaddr} 28 40; \
- bootm ${loadaddr}\0 \
+ bootz ${loadaddr}\0 \
#define CONFIG_BOOTCOMMAND \
mmc dev ${mmcdev}; if mmc rescan; then \
@@ -185,7 +186,7 @@
echo Running uenvcmd ...; \
run uenvcmd; \
fi; \
- if run loaduimage; then \
+ if run loadzimage; then \
run mmcboot; \
fi; \
fi; \
--
1.7.7.6
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Re: [U-Boot] [PATCH 1/5] ARM: IGEP0033: Remove undef of CONFIG_CMD_MEMTEST
On Thu, Jul 25, 2013 at 9:27 AM, Enric Balletbo i Serra eballe...@gmail.com wrote: From: Enric Balletbo i Serra eballe...@iseebcn.com After commit: 79cd2f814b1c75efd47161ac27f4cbebf768240f config_cmd_default.h: Remove CONFIG_CMD_MEMTEST It's not necessary to undef the CONFIG_CMD_MEMTEST, so we can remove it from configuration file. Signed-off-by: Enric Balletbo i Serra eballe...@iseebcn.com --- include/configs/igep0033.h | 7 --- 1 file changed, 7 deletions(-) diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h index 12f28f8..41c083e 100644 --- a/include/configs/igep0033.h +++ b/include/configs/igep0033.h @@ -59,13 +59,6 @@ #define CONFIG_CMD_UBI #define CONFIG_CMD_UBIFS -/* - * Because the issues explained in doc/README.memory-test, the mtest command - * is considered deprecated. It should not be enabled in most normal ports of - * U-Boot. - */ -#undef CONFIG_CMD_MEMTEST - #define CONFIG_BOOTDELAY 1 /* negative for no autoboot */ #define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG -- 1.8.1.2 Reviewed-by: Javier Martinez Canillas jav...@dowhile0.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC 00/10] New board-specific USB initialization interface
On 08/06/13 13:40, Wolfgang Denk wrote: Dear Mateusz Zalega, In message 1375786242-11734-1-git-send-email-m.zal...@samsung.com you wrote: Current implementation of do_dfu() and do_usb_mass_storage() requires board-specific board_usb_init() which performs USB hardware initialization. I noticed that several boards have such a function defined, named either usb_board_init() (which binds to ohci-hcd.c driver and had been used solely by it) or board_usb_init() (as in ehci-omap.c). I _assumed_ that these functions do what's required by do_*() and renamed the earlier in order to unify the naming convention. I appreciate your efforts, but this whole area clearly falls into the domain of the device model rework. Is your suggested implementation in any way synchronized with what has been discussed about this topic before? Hello, I've caught up with driver model discussion. The changes I submitted are related to sharing of board-specific hardware initialization functions between drivers, therefore my patches, if I don't miss anything, do not collide with driver model rework - these changes would have to be done anyway. Regards, -- Mateusz Zalega Samsung RD Institute Poland (SRPOL) | Kernel and System Framework group ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/5] ARM: IGEP0033: Add support for Flattened Device Tree.
On Thu, Jul 25, 2013 at 9:27 AM, Enric Balletbo i Serra
eballe...@gmail.com wrote:
Now, the default kernel to boot the IGEP COM AQUILA is device tree based. As
old kernel is deprecated we should adapt the boot commands to use DTB files.
Also, with v3.9 and later of the Linux Kernel, uImage isn't builtable anymore
by default, so we should switch to use the bootz command.
Signed-off-by: Enric Balletbo i Serra eballe...@iseebcn.com
---
include/configs/igep0033.h | 33 +
1 file changed, 13 insertions(+), 20 deletions(-)
diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h
index 41c083e..be210a5 100644
--- a/include/configs/igep0033.h
+++ b/include/configs/igep0033.h
@@ -41,6 +41,9 @@
/* Display cpuinfo */
#define CONFIG_DISPLAY_CPUINFO
+/* Flattened Device Tree */
+#define CONFIG_OF_LIBFDT
+
/* Commands to include */
#include config_cmd_default.h
@@ -63,37 +66,27 @@
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
- loadaddr=0x8020\0 \
- rdaddr=0x8100\0 \
- bootfile=/boot/uImage\0 \
+ loadaddr=0x80F8\0 \
+ dtbaddr=0x8020\0 \
+ bootdir=/boot\0 \
+ bootfile=zImage\0 \
+ dtbfile=am335x-base0033.dtb\0 \
console=ttyO0,115200n8\0 \
- optargs=\0 \
mmcdev=0\0 \
mmcroot=/dev/mmcblk0p2 rw\0 \
mmcrootfstype=ext4 rootwait\0 \
- ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0 \
- ramrootfstype=ext2\0 \
mmcargs=setenv bootargs console=${console} \
- ${optargs} \
root=${mmcroot} \
rootfstype=${mmcrootfstype}\0 \
bootenv=uEnv.txt\0 \
loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0 \
importbootenv=echo Importing environment from mmc ...; \
- env import -t $loadaddr $filesize\0 \
- ramargs=setenv bootargs console=${console} \
- ${optargs} \
- root=${ramroot} \
- rootfstype=${ramrootfstype}\0 \
- loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0 \
- loaduimagefat=load mmc ${mmcdev} ${loadaddr} ${bootfile}\0 \
- loaduimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0 \
+ env import -t ${loadaddr} ${filesize}\0 \
+ mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; \
+ load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0 \
mmcboot=echo Booting from mmc ...; \
run mmcargs; \
- bootm ${loadaddr}\0 \
- ramboot=echo Booting from ramdisk ...; \
- run ramargs; \
- bootm ${loadaddr}\0 \
+ bootz ${loadaddr} - ${dtbaddr}\0 \
#define CONFIG_BOOTCOMMAND \
mmc dev ${mmcdev}; if mmc rescan; then \
@@ -106,7 +99,7 @@
echo Running uenvcmd ...; \
run uenvcmd; \
fi; \
- if run loaduimage; then \
+ if run mmcload; then \
run mmcboot; \
fi; \
fi; \
--
1.8.1.2
Reviewed-by: Javier Martinez Canillas jav...@dowhile0.org
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[U-Boot] [PATCH 0/2] OMAP3: igep00x0: allow DeviceTree booting
Now that Device Tree support for IGEP boards has been included
in the mainline Linux kernel, it's better if the default boot
command has proper support for booting with DT.
This patch-set his composed of the following patches:
Enric Balletbo i Serra (1):
ARM: igep00x0.h: Enable the use of CMD_EXT4, CMD_FS_GENERIC and zImage.
Javier Martinez Canillas (1):
OMAP3: igep00x0: allow booting with a FDT from MMC
The first patch adds some improvements to igep00x0.h to support
loading kernel images from ext{2,3,4} partitions besides FAT and
using by default a zImage instead of a uImage now that multiplatform
support has been added to OMAP.
The second patch adds support to boot using a FDT if is present
in the /boot dir of the rootfs partition and fallback to legacy
boot if is not present so users that have not migrated to DT can
still use the default boot command.
Thanks a lot and best regards,
Javier
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Re: [U-Boot] [PATCH 3/5] ARM: IGEP0033: Remove CYGNUS name from header.
On Thu, Jul 25, 2013 at 9:27 AM, Enric Balletbo i Serra eballe...@gmail.com wrote: From: Enric Balletbo i Serra eballe...@iseebcn.com We will not use CYGNUS names for any IGEP COM based on AM335x processor, so, to avoid confusion, remove from headers. Signed-off-by: Enric Balletbo i Serra eballe...@iseebcn.com --- board/isee/igep0033/board.c | 2 +- board/isee/igep0033/board.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index ea3bea5..b3fcbb3 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -1,5 +1,5 @@ /* - * Board functions for IGEP COM AQUILA/CYGNUS based boards + * Board functions for IGEP COM AQUILA based boards * * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ * diff --git a/board/isee/igep0033/board.h b/board/isee/igep0033/board.h index 37988e0..4368ee6 100644 --- a/board/isee/igep0033/board.h +++ b/board/isee/igep0033/board.h @@ -1,5 +1,5 @@ /* - * IGEP COM AQUILA/CYGNUS boards information header + * IGEP COM AQUILA boards information header * * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ * -- 1.8.1.2 Reviewed-by: Javier Martinez Canillas jav...@dowhile0.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/5] ARM: IGEP0033: Add support to boot from NAND.
On Thu, Jul 25, 2013 at 9:27 AM, Enric Balletbo i Serra
eballe...@gmail.com wrote:
From: Enric Balletbo i Serra eballe...@iseebcn.com
Add to the default environment the possibily to boot from NAND using
a ubi rootfs. Also the partition scheme is set as follows:
Start Size
SPL : 0x 0x0008 (512KiB)
U-Boot : 0x0008 0x0010 (1MiB)
U-Boot Env : 0x0018 0x0002 (128KiB)
File System : 0x001C -
The ubiboot script gets the kernel and the dtb file from the boot directory
of the File System.
Signed-off-by: Enric Balletbo i Serra eballe...@iseebcn.com
---
include/configs/igep0033.h | 32 +++-
1 file changed, 27 insertions(+), 5 deletions(-)
diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h
index be210a5..3d08cfa 100644
--- a/include/configs/igep0033.h
+++ b/include/configs/igep0033.h
@@ -62,6 +62,10 @@
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
+/* Make the verbose messages from UBI stop printing */
+#define CONFIG_UBI_SILENCE_MSG
+#define CONFIG_UBIFS_SILENCE_MSG
+
#define CONFIG_BOOTDELAY 1 /* negative for no autoboot */
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
@@ -72,21 +76,34 @@
bootfile=zImage\0 \
dtbfile=am335x-base0033.dtb\0 \
console=ttyO0,115200n8\0 \
+ mtdids= MTDIDS_DEFAULT \0 \
+ mtdparts= MTDPARTS_DEFAULT \0 \
mmcdev=0\0 \
mmcroot=/dev/mmcblk0p2 rw\0 \
+ ubiroot=ubi0:filesystem rw ubi.mtd=3,2048\0 \
mmcrootfstype=ext4 rootwait\0 \
+ ubirootfstype=ubifs rootwait\0 \
mmcargs=setenv bootargs console=${console} \
root=${mmcroot} \
rootfstype=${mmcrootfstype}\0 \
+ ubiargs=setenv bootargs console=${console} \
+ root=${ubiroot} \
+ rootfstype=${ubirootfstype}\0 \
bootenv=uEnv.txt\0 \
loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0 \
importbootenv=echo Importing environment from mmc ...; \
env import -t ${loadaddr} ${filesize}\0 \
mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; \
load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0 \
+ ubiload=ubi part filesystem 2048; ubifsmount ubi0; \
+ ubifsload ${loadaddr} ${bootdir}/${bootfile}; \
+ ubifsload ${dtbaddr} ${bootdir}/${dtbfile} \0 \
mmcboot=echo Booting from mmc ...; \
run mmcargs; \
bootz ${loadaddr} - ${dtbaddr}\0 \
+ ubiboot=echo Booting from nand (ubifs) ...; \
+ run ubiargs; run ubiload; \
+ bootz ${loadaddr} - ${dtbaddr}\0 \
#define CONFIG_BOOTCOMMAND \
mmc dev ${mmcdev}; if mmc rescan; then \
@@ -102,6 +119,8 @@
if run mmcload; then \
run mmcboot; \
fi; \
+ else \
+ run ubiboot; \
fi; \
/* Max number of command args */
@@ -181,18 +200,21 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_ONFI_DETECTION 1
#define CONFIG_SYS_ENV_SECT_SIZE (128 10) /* 128 KiB */
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x26 /* environment starts here */
+#define CONFIG_ENV_OFFSET 0x18 /* environment starts here */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_OFFSET +
CONFIG_SYS_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_RBTREE
#define CONFIG_LZO
-#define MTDIDS_DEFAULT nand0=nand
-#define MTDPARTS_DEFAULT mtdparts=nand:512k(SPL),\
- 1m(U-Boot),128k(U-Boot Env),\
- 5m(Kernel),-(File System)
+#define MTDIDS_DEFAULT nand0=omap2-nand.0
+#define MTDPARTS_DEFAULT mtdparts=omap2-nand.0:512k(spl),\
+ 1m(uboot),256k(environment),\
+ -(filesystem)
/* Unsupported features */
#undef CONFIG_USE_IRQ
--
1.8.1.2
Reviewed-by: Javier Martinez Canillas jav...@dowhile0.org
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Re: [U-Boot] u-boot.2013.07 build fails: serial_puts() undefined.
Hi Fabio, Thanks for your reply, but common.h is already included. Specifically, I am looking at inserting a few debug() or serial_puts() calls to arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c, and this is where I see the build error. -Randy On Tue, Aug 6, 2013 at 9:43 PM, Fabio Estevam feste...@gmail.com wrote: On Tue, Aug 6, 2013 at 8:18 PM, Randy Graham surfby...@gmail.com wrote: Hello, I am building u-boot.2013.07 for the mx28evk board. After I insert a few 'serial_puts()' calls for debugging, the build fails and complains that serial_puts() is undefined. Just add this include: #include common.h ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/5] ARM: IGEP0033: Remove duplicate / unused #defines.
Hi Enric, On Thu, Jul 25, 2013 at 9:27 AM, Enric Balletbo i Serra eballe...@gmail.com wrote: From: Enric Balletbo i Serra eballe...@iseebcn.com As config was originally based on am335x_evm.h we have also some duplicate / unnused #defines. Commit 15191c91 removed these #defines on various AM335x boards but not for IGEP COM AQUILA. This patch simply removes them for this board. Hi Enric, This is why I think we should rename igep0033.h = am335x_igep0033.h or something and do the same for igep00x0.h. Otherwise we miss fixes/cleanups when people search for a pattern (i.e: include/configs/omap3_*). This is totally unrelated to this patch though, I just wanted to point this out to take into account once we do the refactor to make both igep0033.h and igep00x0.h share common code. Signed-off-by: Enric Balletbo i Serra eballe...@iseebcn.com --- include/configs/igep0033.h | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h index 3d08cfa..de60f75 100644 --- a/include/configs/igep0033.h +++ b/include/configs/igep0033.h @@ -136,7 +136,6 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE #define CONFIG_SYS_LOAD_ADDR 0x8100 /* Default load address */ -#define CONFIG_SYS_HZ 1000 /* 1ms clock */ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ @@ -149,7 +148,7 @@ /* Platform/Board specific defs */ #define CONFIG_SYS_TIMERBASE 0x4804 /* Use Timer2 */ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) = 8 */ -#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_HZ 1000/* 1ms clock */ /* NS16550 Configuration */ #define CONFIG_SYS_NS16550 @@ -158,7 +157,6 @@ #define CONFIG_SYS_NS16550_CLK (4800) #define CONFIG_SYS_NS16550_COM10x44e09000 /* UART0 */ -#define CONFIG_SERIAL_MULTI #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE115200 @@ -272,10 +270,6 @@ #define CONFIG_SYS_NAND_ECCSIZE512 #define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_SYS_NAND_ECCSTEPS 4 -#defineCONFIG_SYS_NAND_ECCTOTAL(CONFIG_SYS_NAND_ECCBYTES * \ - CONFIG_SYS_NAND_ECCSTEPS) - #defineCONFIG_SYS_NAND_U_BOOT_STARTCONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS0x8 -- 1.8.1.2 Reviewed-by: Javier Martinez Canillas jav...@dowhile0.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] RFC: tegra: Avoid using I2C prior to relocation
On 08/06/2013 11:52 PM, Simon Glass wrote: Tegra recently moved to the new I2C framework, which sets up I2C prior to relocation, and prior to calling i2c_init_board(). This causes a crash on Tegra boards. note: There are many ways to fix this. I believe this is one. It disables i2c_init() until relocation is complete. I have been unable to test it so far due to problems getting my Seaboard to work. I will try another Tegra board, but send this for comment in the meantime. Tested-by: Stephen Warren swar...@nvidia.com (On Beaver and Dalmore, tested booting to U-Boot command prompt followed by i2c dev 0; i2c probe) Note: I believe this is an enormous hack that hacks around the problem of dynamic device initialization just not being well thought out relative to the restrictions of U-Boot's various boot stages. I'd still prefer an outright revert of the broken code. In other words, tegra_i2c_init() simply shouldn't be called at the wrong time; it shouldn't have to handle being called at the wrong time and null itself out when that happens. However, if this is what it takes to get U-Boot working again, then let's apply it ASAP. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/6] am335x_evm: am33xx_spl_board_init function and scale core frequency
On Mon, Jul 29, 2013 at 05:57:22PM +0200, Enric Balletbo Serra wrote:
Hi Tom,
2013/7/23 Dan Murphy dmur...@ti.com:
On 07/19/2013 02:00 PM, Tom Rini wrote:
Add a am33xx_spl_board_init (and enable the PMICs) that we may see,
depending on the board we are running on. In all cases, we see if we
can rely on the efuse_sma register to tell us the maximum speed. In the
case of Beaglebone White, we need to make sure we are on AC power, and
are on later than rev A1, and then we can ramp up to the PG1.0 maximum
of 720Mhz. In the case of Beaglebone Black, we are either on PG2.0 that
supports 1GHz or PG2.1. As PG2.0 may or may not have efuse_sma set, we
cannot rely on this probe. In the case of the GP EVM, EVM SK and IDK we
need to rely on the efuse_sma if we are on PG2.1, and the defaults for
PG1.0/2.0.
[snip]
+ /*
+ * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
+ * MPU frequencies we support we use a CORE voltage of
+ * 1.1375V. For MPU voltage we need to switch based on
+ * the frequency we are running at.
+ */
+ if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
+ return;
+
+ /* VDD1/2 voltage selection register access by control i/f */
+ if (i2c_read(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1,
+ buf, 1))
Would it not be better to have an API in the pmic driver file that
you can call to access the pmic instead of calling the pmic
explicitly?
So, somewhat.
[snip]
+ /* Depending on MPU clock we need different MPU VDD */
+
+ /* Default to PG1.0/PG2.0 values. */
+ mpu_vdd = TPS65910_OP_REG_SEL_1_1_3;
+
+ if (sil_rev = 2) {
+ switch (mpu_pll) {
+ case MPUPLL_M_1000:
+ mpu_vdd = TPS65910_OP_REG_SEL_1_3_2_5;
+ break;
+ case MPUPLL_M_800:
+ mpu_vdd = TPS65910_OP_REG_SEL_1_2_6;
+ break;
+ case MPUPLL_M_720:
+ mpu_vdd = TPS65910_OP_REG_SEL_1_2_0;
+ break;
+ case MPUPLL_M_600:
+ case MPUPLL_M_300:
+ mpu_vdd = TPS65910_OP_REG_SEL_1_1_3;
+ break;
+ }
+ }
[snip]
As example, I just pushed[1] in my personal git an implementation of
am33xx_spl_board_init for IGEP COM AQUILA AM335x based on your
patches. As you can see this function is very similar to the function
implemented in your patch. I wonder if it's possible implement a more
generic form in order to avoid repeating code in board files. Maybe
something like this :
For am335x_evm :
am33xx_spl_board_init {
/* Get MPU max frequency */
mpu_pll = am335x_get_efuse_mpu_max_freq()
if (board_is_bone() || board_is_bone_lt())
tps65217_set_mpu_voltagel(mpu_pll) /* not sure if this can be generic
*/
else
tp65910_set_mpu_voltagel(mpu_pll)
The problem is that the TPS65910 family supports a wide range of non-TI
platforms (s5p, rockchip rk29xx, i.mx) so we can't hide the PG A.B -
voltage required bit in the tps65910 call. I'll see how something looks
in arch/arm/cpu/armv7/am33xx/sys_info.c along with the
efuse_mpu_max_freq function.
--
Tom
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Re: [U-Boot] [RFC 01/10] New board-specific USB initialization interface
On 08/06/2013 04:50 AM, Mateusz Zalega wrote:
This commit unifies board-specific USB initialization implementations
under one symbol (usb_board_init), declaration of which is available in
usb.h.
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
-int board_usb_init(const void *blob)
+int usb_process_devicetree(const void *blob)
{
int node_list[USB_PORTS_MAX];
int count, err = 0;
With just this patch applied, nothing calls that function. This breaks
git bisect.
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Re: [U-Boot] [RFC 02/10] nvidia, tegra: new USB hardware init interface
On 08/06/2013 04:50 AM, Mateusz Zalega wrote:
This commit postpones initialization of USB hardware until
usb_board_init() is called by a command implementation
(ie. do_dfu()) or a driver.
diff --git a/arch/arm/include/asm/arch-tegra/usb.h
b/arch/arm/include/asm/arch-tegra/usb.h
/* Setup USB on the board */
-int board_usb_init(const void *blob);
+int usb_process_devicetree(const void *blob);
This needs to be part of the previous patch (or part of that patch needs
to be split out and put into this patch) so that this prototype change
happens in the same patch that the implementation is renamed. Perhaps
this can happen before the current patch 1?
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
@@ -151,10 +152,6 @@ int board_init(void)
# endif /* CONFIG_TEGRA_PMU */
#endif /* CONFIG_SYS_I2C_TEGRA */
-#ifdef CONFIG_USB_EHCI_TEGRA
- pin_mux_usb();
- board_usb_init(gd-fdt_blob);
-#endif
+#ifdef CONFIG_USB_EHCI_TEGRA
+int board_usb_init(enum board_usb_init_type what_to_init)
+{
+ pin_mux_usb();
+ usb_process_devicetree(gd-fdt_blob);
+ return 0;
+}
+#endif
Moving the pinmux initialization might be dangerous; pin_mux_usb() might
prevent the pins used for USB having a mux function selected that
conflicts with some other pins selected mux function. We really do need
to initialize all of the pinmux early, and not defer it.
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Re: [U-Boot] [PATCH 0/4] sf: macronix: Add support for bank addr access
Hi, On Mon, Jul 29, 2013 at 11:38 PM, Jagannadha Sutradharudu Teki jagannadha.sutradharudu-t...@xilinx.com wrote: This patch set adds bank addr access support for macronix flash's so-that the macronix flashes which has 16Mbyte sizes can be accessible in 3-byte addressing mode. REQUEST FOR MACRONIX FLASH VENDORS/USERS: PLEASE TEST THESE CHANGES ON YOUR RESPECTIVE HW, FLASH PARTS FROM USER HW IS NOT AVAILABLE ON EXISTING U-BOOT PLEASE ADD THE SAME. -- Thanks, Jagan. Jagannadha Sutradharudu Teki (4): sf: Move manufacture id code macros to CONFIG_SPI_FLASH_BAR sf: Add bank addr access support macronix flash's sf: macronix: Add support for MX25L25635F sf: macronix: Add support for MX25L51235F drivers/mtd/spi/macronix.c | 10 ++ drivers/mtd/spi/spi_flash.c | 1 + drivers/mtd/spi/spi_flash_internal.h | 9 + 3 files changed, 16 insertions(+), 4 deletions(-) Developers from macronix or macronix user, please test these BAR changes on your hardware. Feel free to ask any kind of questions/issues. -- Thanks, Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/6] am335x_evm: am33xx_spl_board_init function and scale core frequency
On Mon, Jul 29, 2013 at 05:57:22PM +0200, Enric Balletbo Serra wrote:
Hi Tom,
[snip]
As example, I just pushed[1] in my personal git an implementation of
am33xx_spl_board_init for IGEP COM AQUILA AM335x based on your
patches. As you can see this function is very similar to the function
implemented in your patch. I wonder if it's possible implement a more
generic form in order to avoid repeating code in board files. Maybe
something like this :
For am335x_evm :
am33xx_spl_board_init {
/* Get MPU max frequency */
mpu_pll = am335x_get_efuse_mpu_max_freq()
if (board_is_bone() || board_is_bone_lt())
tps65217_set_mpu_voltagel(mpu_pll) /* not sure if this can be generic
*/
else
tp65910_set_mpu_voltagel(mpu_pll)
/* Set MPU Frequency to what we detected now that voltages are set */
mpu_pll_config_val(mpu_pll);
}
For IGEP COM AQUILA:
am33xx_spl_board_init {
/* Get MPU max frequency */
mpu_pll = am335x_get_efuse_mpu_max_freq()
/* Set PMIC MPU voltage */
tp65910_set_mpu_voltagel(mpu_pll)
/* Set MPU Frequency to what we detected now that voltages are set */
mpu_pll_config_val(mpu_pll);
}
[1]
https://github.com/eballetbo/u-boot/commit/2f5b68bd9b6978d7571c846d7ce8d183ead571b1
OK, I've done some consolidation, but the per-board part is still a few
calls since as I noted in my other reply, tps65910 is not a
am335x-specific chip. Heiko, can you take a quick look at how the
siemens boards would use this? Are they also using the tps65910 or
something else? I'm not opposed to throwing a
am335x_tps65910_set_max_mpu() or so in sys_info.c or something and
marking it weak just in case another way of using the 65910 ends up
existing, but I don't want to throw it into
drivers/power/pmic/pmic_tps65910.c. Thanks!
--
Tom
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Re: [U-Boot] [RFC 00/10] New board-specific USB initialization interface
On 08/06/13 13:40, Wolfgang Denk wrote: Dear Mateusz Zalega, In message 1375786242-11734-1-git-send-email-m.zal...@samsung.com you wrote: Current implementation of do_dfu() and do_usb_mass_storage() requires board-specific board_usb_init() which performs USB hardware initialization. I noticed that several boards have such a function defined, named either usb_board_init() (which binds to ohci-hcd.c driver and had been used solely by it) or board_usb_init() (as in ehci-omap.c). I _assumed_ that these functions do what's required by do_*() and renamed the earlier in order to unify the naming convention. I appreciate your efforts, but this whole area clearly falls into the domain of the device model rework. Is your suggested implementation in any way synchronized with what has been discussed about this topic before? I've caught up with driver model discussion. The changes I submitted are related to sharing of board-specific hardware initialization functions between drivers, therefore my patches, if I don't miss anything, do not collide with driver model rework - these changes would have to be done anyway. If new USB driver model would use some other API to deal with board-specific functions, please correct me. I didn't manage to find related information, maybe I didn't look for it carefully enough. -- Mateusz Zalega Samsung RD Institute Poland (SRPOL) | Kernel and System Framework group ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC 00/10] New board-specific USB initialization interface
Dear Mateusz Zalega, In message 52026e5a.4040...@samsung.com you wrote: I appreciate your efforts, but this whole area clearly falls into the domain of the device model rework. Is your suggested implementation in any way synchronized with what has been discussed about this topic before? I've caught up with driver model discussion. The changes I submitted are related to sharing of board-specific hardware initialization functions between drivers, therefore my patches, if I don't miss anything, do not collide with driver model rework - these changes would have to be done anyway. OK, thanks for checking! Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de The one charm of marriage is that it makes a life of deception a neccessity.- Oscar Wilde ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC 01/10] New board-specific USB initialization interface
On 08/07/13 18:23, Stephen Warren wrote:
This commit unifies board-specific USB initialization implementations
under one symbol (usb_board_init), declaration of which is available in
usb.h.
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
-int board_usb_init(const void *blob)
+int usb_process_devicetree(const void *blob)
{
int node_list[USB_PORTS_MAX];
int count, err = 0;
With just this patch applied, nothing calls that function. This breaks
git bisect.
Yup, I suppose I should squash this RFC PATCH. It's not so large anyway.
Thanks,
--
Mateusz Zalega
Samsung RD Institute Poland (SRPOL) | Kernel and System Framework group
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[U-Boot] [PATCH v2 00/10] sf: Add support for extended/quad read and write commands
This is v2 series for past read/write instruction support. this series also includes zynq qspi driver patch set for knowing usage of these extended/quad read and write commnads. http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/150148 http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/167026 There is a bit discussion going on for supporting this: http://u-boot.10912.n7.nabble.com/PATCH-00-12-cmd-sf-Add-support-for-read-and-write-instructions-td143749.html This patchset adds support for extended and quad read and write commands support. It's been long back the actual idea came up, but i feel right now the sf framework is pretty nice to add these kinds of add ons. Concept: Initially I tried to add individual sf write/read commands to respective flash read/write commands, but later some discussion to mainline about this and changed the implementation. As Michal and me were trying to change this as like the implementation will discover the fastest command by taking the supported commands from flash and a controller. Controller supported commands will always been a priority. Means I have added rd_cmd and wr_cmd params on spi_flash_id_params table. So the flash user may fill these with flash supported commands, and also spi controller use is also have rd_cmd and wr_cmd from spi.h, so the spi user will fill these with controller supported commands. and the resultent command is calculated based fastest commands by taking inputs from spi and flash, but spi(controller) has always a priority. Supported commands: - CMD_READ_ARRAY_SLOW - CMD_READ_ARRAY_FAST - CMD_READ_DUAL_OUTPUT_FAST - CMD_READ_DUAL_IO_FAST - CMD_READ_QUAD_OUTPUT_FAST - CMD_PAGE_PROGRAM - CMD_QUAD_PAGE_PROGRAM REQUEST FOR ALL SPI CODE CONTRIBUTORS/USERS, PLEASE TEST THESE CHANGES W.R.T YOUR HW IF POSSIBLE. Please let me know for any issues/concerns/questions. -- Thanks, Jagan. Jagannadha Sutradharudu Teki (10): sf: Remove spi_flash_do_alloc references sf: Add extended read commands support sf: Add quad read/write commands support sf: ops: Add configuration register writing support sf: Set quad enable bit support spi: Add zynq qspi controller driver zynq: Enable CONFIG_ZYNQ_QSPI zynq: Define CONFIG_SPI_FLASH_BAR spi: zynq_qspi: Add quad read/write commands support spi: zynq_qspi: Enable READ_CMD_FULL and WRITE_CMD_FULL arch/arm/include/asm/arch-zynq/hardware.h | 1 + drivers/mtd/spi/spi_flash_internal.h | 8 + drivers/mtd/spi/spi_flash_ops.c | 52 +++- drivers/mtd/spi/spi_flash_probe.c | 190 - drivers/spi/Makefile | 1 + drivers/spi/spi.c | 3 + drivers/spi/zynq_qspi.c | 454 ++ include/configs/zynq.h| 11 + include/spi.h | 4 + include/spi_flash.h | 84 +++--- 10 files changed, 690 insertions(+), 118 deletions(-) create mode 100644 drivers/spi/zynq_qspi.c -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 01/10] sf: Remove spi_flash_do_alloc references
Added a support for common probe, hence removed removed
spi_flash_do_alloc reference.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
include/spi_flash.h | 38 --
1 file changed, 38 deletions(-)
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 34a167b..18fc6a7 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -79,44 +79,6 @@ struct spi_flash {
int (*erase)(struct spi_flash *flash, u32 offset, size_t len);
};
-/**
- * spi_flash_do_alloc - Allocate a new spi flash structure
- *
- * The structure is allocated and cleared with default values for
- * read, write and erase, which the caller can modify. The caller must set
- * up size, page_size and sector_size.
- *
- * Use the helper macro spi_flash_alloc() to call this.
- *
- * @offset: Offset of struct spi_slave within slave structure
- * @size: Size of slave structure
- * @spi: SPI slave
- * @name: Name of SPI flash device
- */
-void *spi_flash_do_alloc(int offset, int size, struct spi_slave *spi,
-const char *name);
-
-/**
- * spi_flash_alloc - Allocate a new SPI flash structure
- *
- * @_struct: Name of structure to allocate (e.g. struct ramtron_spi_fram). This
- * structure must contain a member 'struct spi_flash *flash'.
- * @spi: SPI slave
- * @name: Name of SPI flash device
- */
-#define spi_flash_alloc(_struct, spi, name) \
- spi_flash_do_alloc(offsetof(_struct, flash), sizeof(_struct), \
- spi, name)
-
-/**
- * spi_flash_alloc_base - Allocate a new SPI flash structure with no private
data
- *
- * @spi: SPI slave
- * @name: Name of SPI flash device
- */
-#define spi_flash_alloc_base(spi, name) \
- spi_flash_do_alloc(0, sizeof(struct spi_flash), spi, name)
-
struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode);
void spi_flash_free(struct spi_flash *flash);
--
1.8.3
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[U-Boot] [PATCH v2 04/10] sf: ops: Add configuration register writing support
This patch provides support to program a flash config register.
Configuration register contains the control bits used to configure
the different configurations and security features of a device.
User need to set these bits through spi_flash_cmd_write_config()
based on their usage.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/mtd/spi/spi_flash_internal.h | 3 +++
drivers/mtd/spi/spi_flash_ops.c | 24
2 files changed, 27 insertions(+)
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index 286082a..580c06b 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -94,6 +94,9 @@ static inline int spi_flash_cmd_write_disable(struct
spi_flash *flash)
/* Program the status register. */
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
+/* Program the config register */
+int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr);
+
#ifdef CONFIG_SPI_FLASH_BAR
/* Program the bank address register */
int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel);
diff --git a/drivers/mtd/spi/spi_flash_ops.c b/drivers/mtd/spi/spi_flash_ops.c
index e461feb..c1c4465 100644
--- a/drivers/mtd/spi/spi_flash_ops.c
+++ b/drivers/mtd/spi/spi_flash_ops.c
@@ -38,6 +38,30 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8
sr)
return 0;
}
+int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
+{
+ u8 data[2];
+ u8 cmd;
+ int ret;
+
+ cmd = CMD_READ_STATUS;
+ ret = spi_flash_read_common(flash, cmd, 1, data[0], 1);
+ if (ret 0) {
+ debug(SF: fail to read status register\n);
+ return ret;
+ }
+
+ cmd = CMD_WRITE_STATUS;
+ data[1] = cr;
+ ret = spi_flash_write_common(flash, cmd, 1, data, 2);
+ if (ret) {
+ debug(SF: fail to write config register\n);
+ return ret;
+ }
+
+ return 0;
+}
+
#ifdef CONFIG_SPI_FLASH_BAR
int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
{
--
1.8.3
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[U-Boot] [PATCH v2 07/10] zynq: Enable CONFIG_ZYNQ_QSPI
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-t...@xilinx.com Tested qspi on zynq board with stmicro, spansion and winbond flashes by enabling CONFIG_ZYNQ_QSPI. Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com --- Changes for v2: - none include/configs/zynq.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/include/configs/zynq.h b/include/configs/zynq.h index b9f381f..16cc3bc 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -81,6 +81,16 @@ # define CONFIG_CMD_SF #endif +/* QSPI */ +#ifdef CONFIG_ZYNQ_QSPI +# define CONFIG_SF_DEFAULT_SPEED 3000 +# define CONFIG_SPI_FLASH +# define CONFIG_SPI_FLASH_SPANSION +# define CONFIG_SPI_FLASH_STMICRO +# define CONFIG_SPI_FLASH_WINBOND +# define CONFIG_CMD_SF +#endif + /* Enable the PL to be downloaded */ #define CONFIG_FPGA #define CONFIG_FPGA_XILINX -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 08/10] zynq: Define CONFIG_SPI_FLASH_BAR
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-t...@xilinx.com Enabled bank/extn' addr register support for accessing 16Mbyte flash devices. Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com --- Changes for v2: - none include/configs/zynq.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 16cc3bc..a94814a 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -85,6 +85,7 @@ #ifdef CONFIG_ZYNQ_QSPI # define CONFIG_SF_DEFAULT_SPEED 3000 # define CONFIG_SPI_FLASH +# define CONFIG_SPI_FLASH_BAR # define CONFIG_SPI_FLASH_SPANSION # define CONFIG_SPI_FLASH_STMICRO # define CONFIG_SPI_FLASH_WINBOND -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 02/10] sf: Add extended read commands support
Current sf uses FAST_READ command, this patch adds support to
use the different/extended read command.
This implementation will determine the fastest command by taking
the supported commands from the flash and the controller, controller
is always been a priority.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/mtd/spi/spi_flash_ops.c | 2 +-
drivers/mtd/spi/spi_flash_probe.c | 169 --
drivers/spi/spi.c | 2 +
include/spi.h | 2 +
include/spi_flash.h | 25 ++
5 files changed, 121 insertions(+), 79 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash_ops.c b/drivers/mtd/spi/spi_flash_ops.c
index c408e27..a0ea3f9 100644
--- a/drivers/mtd/spi/spi_flash_ops.c
+++ b/drivers/mtd/spi/spi_flash_ops.c
@@ -273,7 +273,7 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32
offset,
return 0;
}
- cmd[0] = CMD_READ_ARRAY_FAST;
+ cmd[0] = flash-read_cmd;
cmd[4] = 0x00;
while (len) {
diff --git a/drivers/mtd/spi/spi_flash_probe.c
b/drivers/mtd/spi/spi_flash_probe.c
index 86fbb07..82d77de 100644
--- a/drivers/mtd/spi/spi_flash_probe.c
+++ b/drivers/mtd/spi/spi_flash_probe.c
@@ -26,6 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;
* @ext_jedec: Device ext_jedec ID
* @sector_size: Sector size of this device
* @nr_sectors:No.of sectors on this device
+ * @rd_cmd:Read command
* @flags: Importent param, for flash specific behaviour
*/
struct spi_flash_params {
@@ -34,103 +35,104 @@ struct spi_flash_params {
u16 ext_jedec;
u32 sector_size;
u32 nr_sectors;
+ u8 rd_cmd;
u16 flags;
};
static const struct spi_flash_params spi_flash_params_table[] = {
#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
- {AT45DB011D, 0x1f2200, 0x0, 64 * 1024, 4,
SECT_4K},
- {AT45DB021D, 0x1f2300, 0x0, 64 * 1024, 8,
SECT_4K},
- {AT45DB041D, 0x1f2400, 0x0, 64 * 1024, 8,
SECT_4K},
- {AT45DB081D, 0x1f2500, 0x0, 64 * 1024,16,
SECT_4K},
- {AT45DB161D, 0x1f2600, 0x0, 64 * 1024,32,
SECT_4K},
- {AT45DB321D, 0x1f2700, 0x0, 64 * 1024,64,
SECT_4K},
- {AT45DB641D, 0x1f2800, 0x0, 64 * 1024, 128,
SECT_4K},
+ {AT45DB011D, 0x1f2200, 0x0, 64 * 1024, 4,
0, SECT_4K},
+ {AT45DB021D, 0x1f2300, 0x0, 64 * 1024, 8,
0, SECT_4K},
+ {AT45DB041D, 0x1f2400, 0x0, 64 * 1024, 8,
0, SECT_4K},
+ {AT45DB081D, 0x1f2500, 0x0, 64 * 1024,16,
0, SECT_4K},
+ {AT45DB161D, 0x1f2600, 0x0, 64 * 1024,32,
0, SECT_4K},
+ {AT45DB321D, 0x1f2700, 0x0, 64 * 1024,64,
0, SECT_4K},
+ {AT45DB641D, 0x1f2800, 0x0, 64 * 1024, 128,
0, SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_EON/* EON */
- {EN25Q32B, 0x1c3016, 0x0, 64 * 1024,64,
0},
- {EN25Q64,0x1c3017, 0x0, 64 * 1024, 128,
SECT_4K},
- {EN25Q128B, 0x1c3018, 0x0, 64 * 1024, 256,
0},
+ {EN25Q32B, 0x1c3016, 0x0, 64 * 1024,64,
0, 0},
+ {EN25Q64,0x1c3017, 0x0, 64 * 1024, 128,
0, SECT_4K},
+ {EN25Q128B, 0x1c3018, 0x0, 64 * 1024, 256,
0, 0},
#endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
- {GD25Q64B, 0xc84017, 0x0, 64 * 1024, 128,
SECT_4K},
- {GD25LQ32, 0xc86016, 0x0, 64 * 1024,64,
SECT_4K},
+ {GD25Q64B, 0xc84017, 0x0, 64 * 1024, 128,
0, SECT_4K},
+ {GD25LQ32, 0xc86016, 0x0, 64 * 1024,64,
0, SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
- {MX25L4005, 0xc22013, 0x0, 64 * 1024, 8,
0},
- {MX25L8005, 0xc22014, 0x0, 64 * 1024,16,
0},
- {MX25L1605D, 0xc22015, 0x0, 64 * 1024,32,
0},
- {MX25L3205D, 0xc22016, 0x0, 64 * 1024,64,
0},
- {MX25L6405D, 0xc22017, 0x0, 64 * 1024, 128,
0},
- {MX25L12805, 0xc22018, 0x0, 64 * 1024, 256,
0},
- {MX25L12855E,0xc22618, 0x0, 64 * 1024, 256,
0},
+ {MX25L4005, 0xc22013, 0x0,
[U-Boot] [PATCH v2 09/10] spi: zynq_qspi: Add quad read/write commands support
QPP - Quad Page Program
DIOR - Dual IO high perf read
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/spi/zynq_qspi.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index df090d7..02a1a80 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -42,8 +42,10 @@
#define ZYNQ_QSPI_FLASH_INST_WREN 0x06/* Write enable */
#define ZYNQ_QSPI_FLASH_INST_AFR 0x0B/* Fast read data bytes */
#define ZYNQ_QSPI_FLASH_INST_BE_4K 0x20/* Erase 4KiB block */
+#define ZYNQ_QSPI_FLASH_INST_QPP 0x32/* Quad page program */
#define ZYNQ_QSPI_FLASH_INST_RDSR2 0x35/* Read status register 2 */
#define ZYNQ_QSPI_FLASH_INST_BE_32K0x52/* Erase 32KiB block */
+#define ZYNQ_QSPI_FLASH_INST_QFR 0x6B/* Quad output fast read */
#define ZYNQ_QSPI_FLASH_INST_RDID 0x9F/* Read JEDEC ID */
#define ZYNQ_QSPI_FLASH_INST_SE0xD8/* Sector erase
(usually 64KB)*/
@@ -94,8 +96,10 @@ static struct zynq_qspi_inst_format flash_inst[] = {
{ZYNQ_QSPI_FLASH_INST_WREN, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
{ZYNQ_QSPI_FLASH_INST_AFR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
{ZYNQ_QSPI_FLASH_INST_BE_4K, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
+ {ZYNQ_QSPI_FLASH_INST_QPP, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
{ZYNQ_QSPI_FLASH_INST_RDSR2, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
{ZYNQ_QSPI_FLASH_INST_BE_32K, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
+ {ZYNQ_QSPI_FLASH_INST_QFR, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
{ZYNQ_QSPI_FLASH_INST_RDID, 1, ZYNQ_QSPI_TXD_00_01_OFFSET},
{ZYNQ_QSPI_FLASH_INST_SE, 4, ZYNQ_QSPI_TXD_00_00_OFFSET},
/* Add all the instructions supported by the flash device */
--
1.8.3
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[U-Boot] [PATCH v2 10/10] spi: zynq_qspi: Enable READ_CMD_FULL and WRITE_CMD_FULL
Zynq controller supports all basic, extended read and quad read/write commands, so enable them in the driver so-that the sf will look for the fastest cmd w.r.t flash supported one. Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com --- Changes for v2: - none drivers/spi/zynq_qspi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index 02a1a80..6a33719 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -10,6 +10,7 @@ #include common.h #include malloc.h #include spi.h +#include spi_flash.h #include asm/io.h #include asm/arch/hardware.h @@ -324,6 +325,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return NULL; } + zslave-slave.rd_cmd = READ_CMD_FULL; + zslave-slave.wr_cmd = WRITE_CMD_FULL; zslave-base = (struct zynq_qspi_regs *)ZYNQ_QSPI_BASEADDR; zslave-mode = mode; zslave-fifo_depth = ZYNQ_QSPI_FIFO_DEPTH; -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 06/10] spi: Add zynq qspi controller driver
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-t...@xilinx.com
Zynq qspi controller driver supports single bus
with singe chipselect.
Zynq qspi can be operated in below connection modes
- single qspi
- dual qspi, with dual stacked
- dual qspi, with dual parallel
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
arch/arm/include/asm/arch-zynq/hardware.h | 1 +
drivers/spi/Makefile | 1 +
drivers/spi/zynq_qspi.c | 447 ++
3 files changed, 449 insertions(+)
create mode 100644 drivers/spi/zynq_qspi.c
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h
b/arch/arm/include/asm/arch-zynq/hardware.h
index 081624e..3b86195 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -19,6 +19,7 @@
#define ZYNQ_I2C_BASEADDR1 0xE0005000
#define ZYNQ_SPI_BASEADDR0 0xE0006000
#define ZYNQ_SPI_BASEADDR1 0xE0007000
+#define ZYNQ_QSPI_BASEADDR 0xE000D000
/* Reflect slcr offsets */
struct slcr_regs {
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..5b09eac 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -40,6 +40,7 @@ COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
+COBJS-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
new file mode 100644
index 000..df090d7
--- /dev/null
+++ b/drivers/spi/zynq_qspi.c
@@ -0,0 +1,447 @@
+/*
+ * (C) Copyright 2013 Inc.
+ *
+ * Xilinx Zynq PS Quad-SPI(QSPI) controller driver (master mode only)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include config.h
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include asm/arch/hardware.h
+
+/* zynq spi register bit masks ZYNQ_QSPI_REG_BIT_MASK */
+#define ZYNQ_QSPI_CR_IFMODE_MASK (1 31) /* Flash intrface mode*/
+#define ZYNQ_QSPI_CR_MSA_MASK (1 15) /* Manual start enb */
+#define ZYNQ_QSPI_CR_MCS_MASK (1 14) /* Manual chip select */
+#define ZYNQ_QSPI_CR_PCS_MASK (1 10) /* Peri chip select */
+#define ZYNQ_QSPI_CR_FW_MASK (0x3 6) /* FIFO width */
+#define ZYNQ_QSPI_CR_BRD_MASK (0x7 3) /* Baud rate div */
+#define ZYNQ_QSPI_CR_CPHA_MASK (1 2)/* Clock phase */
+#define ZYNQ_QSPI_CR_CPOL_MASK (1 1)/* Clock polarity */
+#define ZYNQ_QSPI_CR_MSTREN_MASK (1 0)/* Mode select */
+#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK(1 4)/* RX_FIFO_not_empty */
+#define ZYNQ_QSPI_IXR_TXOW_MASK(1 2)/*
TX_FIFO_not_full */
+#define ZYNQ_QSPI_IXR_ALL_MASK 0x7F/* All IXR bits */
+#define ZYNQ_QSPI_ENR_SPI_EN_MASK (1 0)/* SPI Enable */
+
+/* QSPI Transmit Data Register */
+#define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
+#define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
+#define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
+#define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
+
+/* Definitions of the flash commands - Flash insts in ascending order */
+#define ZYNQ_QSPI_FLASH_INST_WRSR 0x01/* Write status register */
+#define ZYNQ_QSPI_FLASH_INST_PP0x02/* Page program */
+#define ZYNQ_QSPI_FLASH_INST_WRDS 0x04/* Write disable */
+#define ZYNQ_QSPI_FLASH_INST_RDSR1 0x05/* Read status register 1 */
+#define ZYNQ_QSPI_FLASH_INST_WREN 0x06/* Write enable */
+#define ZYNQ_QSPI_FLASH_INST_AFR 0x0B/* Fast read data bytes */
+#define ZYNQ_QSPI_FLASH_INST_BE_4K 0x20/* Erase 4KiB block */
+#define ZYNQ_QSPI_FLASH_INST_RDSR2 0x35/* Read status register 2 */
+#define ZYNQ_QSPI_FLASH_INST_BE_32K0x52/* Erase 32KiB block */
+#define ZYNQ_QSPI_FLASH_INST_RDID 0x9F/* Read JEDEC ID */
+#define ZYNQ_QSPI_FLASH_INST_SE0xD8/* Sector erase
(usually 64KB)*/
+
+#define ZYNQ_QSPI_FIFO_DEPTH 63
+#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT
+#define CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
+#endif
+
+/* zynq qspi register set */
+struct zynq_qspi_regs {
+ u32 cr; /* 0x00 */
+ u32 isr;/* 0x04 */
+ u32 ier;/* 0x08 */
+ u32 idr;/* 0x0C */
+ u32 imr;/* 0x10 */
+ u32 enr;/* 0x14 */
+ u32 dr; /* 0x18 */
+ u32 txd0r; /* 0x1C */
+ u32 rxdr; /* 0x20 */
+ u32 sicr; /* 0x24 */
+ u32 txftr; /* 0x28 */
+ u32 rxftr; /* 0x2C */
+ u32 gpior; /* 0x30 */
+ u32 reserved0[19];
+ u32
[U-Boot] [PATCH v2 03/10] sf: Add quad read/write commands support
Current sf uses PAGE_PROGRAM command for write and FAST_READ,
SLOW_READ, DUAL_READ and DUAL_IO_READ commands for read this
patch adds support to use the quad read/write commands.
- QUAD_PAGE_PROGRAM
- QUAD_OUTPUT_FAST
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/mtd/spi/spi_flash_ops.c | 2 +-
drivers/mtd/spi/spi_flash_probe.c | 168 --
drivers/spi/spi.c | 1 +
include/spi.h | 2 +
include/spi_flash.h | 23 +-
5 files changed, 116 insertions(+), 80 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash_ops.c b/drivers/mtd/spi/spi_flash_ops.c
index a0ea3f9..e461feb 100644
--- a/drivers/mtd/spi/spi_flash_ops.c
+++ b/drivers/mtd/spi/spi_flash_ops.c
@@ -200,7 +200,7 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32
offset,
page_size = flash-page_size;
- cmd[0] = CMD_PAGE_PROGRAM;
+ cmd[0] = flash-write_cmd;
for (actual = 0; actual len; actual += chunk_len) {
#ifdef CONFIG_SPI_FLASH_BAR
u8 bank_sel;
diff --git a/drivers/mtd/spi/spi_flash_probe.c
b/drivers/mtd/spi/spi_flash_probe.c
index 82d77de..45554cc 100644
--- a/drivers/mtd/spi/spi_flash_probe.c
+++ b/drivers/mtd/spi/spi_flash_probe.c
@@ -27,6 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
* @sector_size: Sector size of this device
* @nr_sectors:No.of sectors on this device
* @rd_cmd:Read command
+ * @wr_cmd:Write command
* @flags: Importent param, for flash specific behaviour
*/
struct spi_flash_params {
@@ -36,103 +37,104 @@ struct spi_flash_params {
u32 sector_size;
u32 nr_sectors;
u8 rd_cmd;
+ u8 wr_cmd;
u16 flags;
};
static const struct spi_flash_params spi_flash_params_table[] = {
#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
- {AT45DB011D, 0x1f2200, 0x0, 64 * 1024, 4,
0, SECT_4K},
- {AT45DB021D, 0x1f2300, 0x0, 64 * 1024, 8,
0, SECT_4K},
- {AT45DB041D, 0x1f2400, 0x0, 64 * 1024, 8,
0, SECT_4K},
- {AT45DB081D, 0x1f2500, 0x0, 64 * 1024,16,
0, SECT_4K},
- {AT45DB161D, 0x1f2600, 0x0, 64 * 1024,32,
0, SECT_4K},
- {AT45DB321D, 0x1f2700, 0x0, 64 * 1024,64,
0, SECT_4K},
- {AT45DB641D, 0x1f2800, 0x0, 64 * 1024, 128,
0, SECT_4K},
+ {AT45DB011D, 0x1f2200, 0x0, 64 * 1024, 4,
0, 0, SECT_4K},
+ {AT45DB021D, 0x1f2300, 0x0, 64 * 1024, 8,
0, 0, SECT_4K},
+ {AT45DB041D, 0x1f2400, 0x0, 64 * 1024, 8,
0, 0, SECT_4K},
+ {AT45DB081D, 0x1f2500, 0x0, 64 * 1024,16,
0, 0, SECT_4K},
+ {AT45DB161D, 0x1f2600, 0x0, 64 * 1024,32,
0, 0, SECT_4K},
+ {AT45DB321D, 0x1f2700, 0x0, 64 * 1024,64,
0, 0, SECT_4K},
+ {AT45DB641D, 0x1f2800, 0x0, 64 * 1024, 128,
0, 0, SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_EON/* EON */
- {EN25Q32B, 0x1c3016, 0x0, 64 * 1024,64,
0, 0},
- {EN25Q64,0x1c3017, 0x0, 64 * 1024, 128,
0, SECT_4K},
- {EN25Q128B, 0x1c3018, 0x0, 64 * 1024, 256,
0, 0},
+ {EN25Q32B, 0x1c3016, 0x0, 64 * 1024,64,
0, 0, 0},
+ {EN25Q64,0x1c3017, 0x0, 64 * 1024, 128,
0, 0, SECT_4K},
+ {EN25Q128B, 0x1c3018, 0x0, 64 * 1024, 256,
0, 0, 0},
#endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
- {GD25Q64B, 0xc84017, 0x0, 64 * 1024, 128,
0, SECT_4K},
- {GD25LQ32, 0xc86016, 0x0, 64 * 1024,64,
0, SECT_4K},
+ {GD25Q64B, 0xc84017, 0x0, 64 * 1024, 128,
0, 0, SECT_4K},
+ {GD25LQ32, 0xc86016, 0x0, 64 * 1024,64,
0, 0, SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
- {MX25L4005, 0xc22013, 0x0, 64 * 1024, 8,
0, 0},
- {MX25L8005, 0xc22014, 0x0, 64 * 1024,16,
0, 0},
- {MX25L1605D, 0xc22015, 0x0, 64 * 1024,32,
0, 0},
- {MX25L3205D, 0xc22016,
[U-Boot] [PATCH v2 05/10] sf: Set quad enable bit support
This patch provides support to set the quad enable bit on flash.
quad enable bit needs to set before performing any quad IO
operations on respective SPI flashes.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v2:
- none
drivers/mtd/spi/spi_flash_internal.h | 5 +
drivers/mtd/spi/spi_flash_ops.c | 24
drivers/mtd/spi/spi_flash_probe.c| 9 +
3 files changed, 38 insertions(+)
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index 580c06b..8257020 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -22,6 +22,7 @@
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
#define CMD_READ_STATUS0x05
+#define CMD_READ_CONFIG0x35
#define CMD_FLAG_STATUS0x70
#define CMD_WRITE_ENABLE 0x06
#define CMD_ERASE_4K 0x20
@@ -41,6 +42,7 @@
/* Common status */
#define STATUS_WIP 0x01
+#define STATUS_QEB 0x02
#define STATUS_PEC 0x80
/* Send a single-byte command to the device and read the response */
@@ -97,6 +99,9 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8
sr);
/* Program the config register */
int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr);
+/* Set quad enbale bit */
+int spi_flash_set_qeb(struct spi_flash *flash);
+
#ifdef CONFIG_SPI_FLASH_BAR
/* Program the bank address register */
int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel);
diff --git a/drivers/mtd/spi/spi_flash_ops.c b/drivers/mtd/spi/spi_flash_ops.c
index c1c4465..defd88c 100644
--- a/drivers/mtd/spi/spi_flash_ops.c
+++ b/drivers/mtd/spi/spi_flash_ops.c
@@ -62,6 +62,30 @@ int spi_flash_cmd_write_config(struct spi_flash *flash, u8
cr)
return 0;
}
+int spi_flash_set_qeb(struct spi_flash *flash)
+{
+ u8 qeb_status;
+ u8 cmd;
+ int ret;
+
+ cmd = CMD_READ_CONFIG;
+ ret = spi_flash_read_common(flash, cmd, 1, qeb_status, 1);
+ if (ret 0) {
+ debug(SF: fail to read config register\n);
+ return ret;
+ }
+
+ if (qeb_status STATUS_QEB) {
+ debug(SF: Quad enable bit is already set\n);
+ } else {
+ ret = spi_flash_cmd_write_config(flash, STATUS_QEB);
+ if (ret 0)
+ return ret;
+ }
+
+ return ret;
+}
+
#ifdef CONFIG_SPI_FLASH_BAR
int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
{
diff --git a/drivers/mtd/spi/spi_flash_probe.c
b/drivers/mtd/spi/spi_flash_probe.c
index 45554cc..0fc15cf 100644
--- a/drivers/mtd/spi/spi_flash_probe.c
+++ b/drivers/mtd/spi/spi_flash_probe.c
@@ -224,6 +224,15 @@ struct spi_flash *spi_flash_validate_ids(struct spi_slave
*spi, u8 *idcode)
flash-write_cmd = flash-spi-wr_cmd;
}
+ /* Set the quad enable bit - only for quad commands */
+ if ((flash-read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
+ (flash-write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
+ if (spi_flash_set_qeb(flash)) {
+ debug(SF: Fail to set quad enable bit\n);
+ return NULL;
+ }
+ }
+
/* Compute erase sector and command */
if (params-flags SECT_4K) {
flash-erase_cmd = CMD_ERASE_4K;
--
1.8.3
___
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U-Boot@lists.denx.de
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Re: [U-Boot] [PATCH] RFC: tegra: Avoid using I2C prior to relocation
Hi Stephen, On Wed, Aug 7, 2013 at 10:20 AM, Stephen Warren swar...@wwwdotorg.orgwrote: On 08/06/2013 11:52 PM, Simon Glass wrote: Tegra recently moved to the new I2C framework, which sets up I2C prior to relocation, and prior to calling i2c_init_board(). This causes a crash on Tegra boards. note: There are many ways to fix this. I believe this is one. It disables i2c_init() until relocation is complete. I have been unable to test it so far due to problems getting my Seaboard to work. I will try another Tegra board, but send this for comment in the meantime. Tested-by: Stephen Warren swar...@nvidia.com (On Beaver and Dalmore, tested booting to U-Boot command prompt followed by i2c dev 0; i2c probe) Note: I believe this is an enormous hack that hacks around the problem of dynamic device initialization just not being well thought out relative to the restrictions of U-Boot's various boot stages. I'd still prefer an outright revert of the broken code. In other words, tegra_i2c_init() simply shouldn't be called at the wrong time; it shouldn't have to handle being called at the wrong time and null itself out when that happens. However, if this is what it takes to get U-Boot working again, then let's apply it ASAP. Fair enough. Restricting my comments to I2C only, I think that we could have (at least until driver model happens) an I2C init for each driver (in this case it is i2c_init_board() that is called by the I2C subsystem twice during init (once from board_init_f() and once from board_init_r()). The i2c_init() call is odd because it does an init of a single I2C bus, which isn't really necessary for most hardware. But I'm not sure it is worth worrying about this until we have driver model. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] wandboard: add pxe support, set default boot command like highbank
On Wed, 7 Aug 2013 09:19:21 -0400 Tom Rini tr...@ti.com wrote: On Tue, Aug 06, 2013 at 06:11:25PM -0500, Dennis Gilmore wrote: On Tue, 6 Aug 2013 17:42:31 -0400 Tom Rini tr...@ti.com wrote: On Tue, Aug 06, 2013 at 11:22:22AM -0500, Dennis Gilmore wrote: [snip] The only way I could see having us write a file to disk with the environment working is if all boards implement standard variable to define the memory locations and that is compiled into the u-boot binary. some variables that would need to be compiled in fdt_addr fdt_addr_r Why two? from cmd_pxe.c [snip] u-boot by default would load a dtb to fdt_addr but a user could at least in the pxe/extlinux case load their own dtb if the want/need to. the only way a dtb would be optional is if fdtfile is not set OK, so fdt_addr is for a memory-mapped location of the DT existing somewhere already, basically. right, how that gets there would be up to the vendor. but distros should put dtbs in a known place so that they can pulled from there. kernel_addr_r ramdisk_addr_r pxefile_addr_r scr_addr_r uenv_addr_r this should allow for for people to use boot.scr uEnv.txt or pxe/extlinux This is what I think we need to work towards. A board opting into this standard must set CONFIG_CMD_A/B/C (or maybe we add a CONFIG_SUPPORT_GENERIC_LINUX_DISTRO that does this in one of the fallback files, whatever) and provide the following variables PLUS a, and this needs some thinking I think, auto-boot tries to load said file from ... ? We cannot provide a built-in environment that works for every distro and case, we want the distro to tell us things it knows, and we'll tell it what it can't easily know. we absolutely can, I would like for u-boot to load a dtb before doing anything. u-boot should know what devices can be booted from and likely an order of preference. i.e. removable media through to fixed, and finally pxe. Looking at a couple of device trees, no, we can't. I don't see any useful information like this is an SD controller for example (and all of the mmc bindings that might provide a reliable clue are optional ones). So, at the high level, if U-Boot relied on DTs in every driver, we might be able to do what you're talking about. But we don't do that today, and probably won't for a long time, if ever. But we will know what devices are likely to exist and be bootable, at build time. What we can do is try and load a file from everywhere we expect might be someplace with this file in it. We could even set some standard variables based on having found and loaded this file, so it can assume that everything else exists in this same place (or the file we have loaded knows better). I was thinking more along the lines of us knowing what is likely to be there than pulling it from the DT and basically doing something like you mentioned here. i would like for u-boot to first try to load /boot/extlinux/extlinux.conf then /extlinux/extlinux.conf failing that try to load a /boot/uEnv.txt then /uEnv.txt and import that running with what is in it, then falling back to a /boot/boot.scr then /boot.scr then finally running dhcp, pxe get, and pxe boot. I'd like to see most of that logic held in the file we load (so that when something replaces extlinux.conf as the preferred method, it just works still, or whatever) and run a command from. And fall back to dhcp+pxe for the install case. where should the file we load come from? i would think when something comes along to replace extlinux.conf its likely going to need an updated u-boot to add some new functionality Dennis ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Purpose of Data partition in Partition Layout
Hi all, My current default partition layout is as follow: 1) u-boot, 2) environment variables 3) kernel, 4) filesystem I have seen in some implementations, that there is one partition of data after the filesystem's partition as follow: 1) u-boot, 2) environment variables 3) kernel, 4) filesystem 5) data(or rest) What is the purpose of this data partition? Who reads/writes there (kernel or filesystem(like jffs2)) and *How*? If kernel writes there, then do we have to change kernel configuration? If yes, then what changes are required? What happens in case, when I don't keep that separate partition of data and only filesystem is given the rest of the flash memory(as I have used)? And How it differs from the partition layout with data as the last partition? I don't know about this. Please, help me understand these. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
