Re: [U-Boot] [PATCH v1 8/8] mpc85xx: introduce the kmp204x reference design support
On 08/20/2013 02:48 AM, Scott Wood wrote: On Mon, 2013-08-19 at 17:50 +0200, Valentin Longchamp wrote: On 08/13/2013 11:38 PM, Scott Wood wrote: On Fri, 2013-07-26 at 12:02 +0200, Valentin Longchamp wrote: This patch introduces the support for Keymile's kmp204x reference design. This design is based on Freescale's P2040/P2041 SoC. The peripherals used by this design are: - DDR3 RAM with SPD support - SPI NOR Flash as boot medium - NAND Flash - 2 PCIe busses (hosts 1 and 3) - 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5) - 3 Local Bus windows, with one dedicated to the QRIO reset/power mgmt FPGA - 2 HW I2C busses - last but not least, the mandatory serial port The board/keymile/kmp204x code is mostly based on Freescale's P2041rdb support and was changed according to our design (that means essentially removing what is not present on the designs and a few adaptations). A lot of the copied files have had Freescale copyrights removed... Also please try to factor shared code out rather than duplicate, where practical. Well, I had tried to come a first proposal that factored shared code but I was advised to copy the code: [1]. For the copyrights I will fix it. [1] Did you mean to cite something here? Oops, yes sorry: http://u-boot.10912.n7.nabble.com/RFC-PATCH-mpc85xx-move-generic-corenet-to-cpu-mpc85xxx-tt153910.html#none ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] U-Boot timeout
Hi Simon, I saw that you had proposed a patch for increasing the U-Boot timeout to work with some USB flash devices: http://lists.denx.de/pipermail/u-boot/2010-December/083467.html I have also ran into this problem in U-Boot, with the same root cause. I realize that this mailer is primarily for U-Boot, but I was curious whether this was an issue that you had encountered only in U-Boot, or whether you had also observed this problem after booting into an operating system. For example, I have observed that once booted into Linux, the USB devices will return I/O errors after heavy read/write activity, which I suspect to have the same root cause. Thanks, Marshall ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Enabling L2 cache on mx53
Hi Marek, On 19/08/2013 22:31, Marek Vasut wrote: Dear Fabio Estevam, Hi Marek, On Mon, Aug 19, 2013 at 4:51 PM, Marek Vasut ma...@denx.de wrote: L2CC on MX53 is enabled by setting just the L2ON and C bits in CP15, there's no configuration. Not even Linux enables the L2CC on MX53, so if it's not on in U- Boot, then it's not on at all (and that sucks). This is what I have done: --- a/arch/arm/cpu/armv7/mx5/ lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -45,6 +45,11 @@ #endif mcr 15, 1, r0, c9, c0, 2 + + /* enable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + orr r0, r0, #(1 1)/* enable l2 cache */ + mcr 15, 0, r0, c1, c0, 1 .endm /* init_l2cc */ /* AIPS setup - Only setup MPROTx registers. Anything else I am missing? Try profiling the RX routine, maybe it's looping somewhere there for too long. But the RX routine belongs to the FEC driver that it is used by all i.MXes. Is there maybe a problem with the phy and the negotiated speed is less than expected ? Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-Boot Driver Development on Atmel's sama5d3xek
Hi On Tue, Aug 20, 2013 at 01:46:55PM +0800, Bo Shen wrote: Hi Steven, On 8/20/2013 12:51, Steven Rosenberg wrote: Hi Bo To clarify we need to run when booting with no human intervention and to be able to use gmac so the questions are mainly for the procedures on how to create a driver under uboot I am still not fully get what you mean. what you mean 'run when booting with no human intervention and to be able to use gmac'? Using it for tftp, nfs, or anything else? Which driver do you want to create under uboot? GMAC driver? or anything else? I dont' know if I understand correclty but I think that he wants to use the driver from a binary that is lunched from uboot. What I don't understand if he wants to run in parallel with the bootloader. Michael We would also need to call into the current ethernet drivers as well and I did notice a gmacb driver but the main issue now seems to be how to create a driver in uboot Again, Which driver do you want to create under uboot? GMAC driver? or anything else? The procedures for creating a driver seems complex and some guidance would be appreciated For different driver, you can check different subsystem in uboot for more detail information. Thank you for the link to the patch With Best Regards Steven Best Regards, Bo Shen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [ANN] v2013.10-rc1
Hi Heiko, On 20/08/2013 06:14, Heiko Schocher wrote: Hello Tom, Am 20.08.2013 00:02, schrieb Tom Rini: Hey all, I've put v2013.10-rc1 out, and I hope Detlev can get the tarball uploaded soon. I just tried to sync u-boot-i2c.git with u-boot.git to prepare a u-boot-i2c pull request ... and got this error: [hs@pollux u-boot]$ git fetch origin error: refs/remotes/origin/GPL-Cleanup does not point to a valid object! error: refs/remotes/origin/env does not point to a valid object! error: refs/remotes/origin/i.MX31 does not point to a valid object! error: refs/remotes/origin/lwmon5 does not point to a valid object! error: refs/remotes/origin/tx25 does not point to a valid object! error: refs/remotes/origin/GPL-Cleanup does not point to a valid object! error: refs/remotes/origin/env does not point to a valid object! error: refs/remotes/origin/i.MX31 does not point to a valid object! error: refs/remotes/origin/lwmon5 does not point to a valid object! error: refs/remotes/origin/tx25 does not point to a valid object! error: refs/remotes/origin/GPL-Cleanup does not point to a valid object! error: refs/remotes/origin/env does not point to a valid object! error: refs/remotes/origin/i.MX31 does not point to a valid object! error: refs/remotes/origin/lwmon5 does not point to a valid object! error: refs/remotes/origin/tx25 does not point to a valid object! error: refs/remotes/origin/GPL-Cleanup does not point to a valid object! error: refs/remotes/origin/env does not point to a valid object! error: refs/remotes/origin/i.MX31 does not point to a valid object! error: refs/remotes/origin/lwmon5 does not point to a valid object! error: refs/remotes/origin/tx25 does not point to a valid object! I cannot confirm this on my site - everything seems ok. All remote branches are available issueing git branch -r. Regards, Stefano -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ARM: omap3: Implement dpll5 (HSUSB clk) workaround for OMAP36xx/AM/DM37xx according to errata sprz318e.
Hi,
Am 16.08.2013 17:30, schrieb Robert Nelson:
On Fri, Aug 16, 2013 at 10:07 AM, Robert Nelson robertcnel...@gmail.com wrote:
On Fri, Aug 16, 2013 at 9:34 AM, Peter A. Bigot p...@pabigot.com wrote:
On 08/16/2013 08:38 AM, Tom Rini wrote:
On Wed, Aug 14, 2013 at 09:53:16PM -0500, Peter A. Bigot wrote:
On 07/09/2013 02:43 AM, Naumann Andreas wrote:
In chapter 'Advisory 2.1 USB Host Clock Drift Causes USB Spec
Non-compliance in Certain Configurations' of the TI Errata it is recommended
to use certain div/mult values for the DPLL5 clock setup.
So far u-boot used the old 34xx values, so I added the errata
recommended values specificly for 36xx init only.
Also, the FSEL registers exist no longer, so removed them from init.
Tested this on a AM3703 board with 19.2MHz oscillator, which previously
couldnt lock the dpll5 (kernel complained). As a consequence the EHCI USB
port wasnt usable in U-Boot and kernel. With this patch, kernel panics
disappear and USB working fine in u-boot and kernel.
Signed-off-by: Andreas Naumann anaum...@ultratronik.de
While this patch works with Linux that has been patched for this
erratum, it will cause problems with some unpatched versions of
Linux.
Right. So Linux also needs to be patched for the erratum.
Yes. My point was that if you update u-boot alone, then try to use it to
boot an unpatched Linux that assumes CM_CLKSEL5_PLL has its power-on value,
USB will not work.
Oh, I was not aware of that. But indeed i use a patched 3.1 kernel, see
below.
Some info on the history: In our design (19.2MHz crystal) we could
clearly see the errata problem of high jitter on the 60MHz USB clock
when (re-)booting a board that was already warmed up.
Back then I applied a slightly extended kernel patch (see below) that I
found on some kernel list. This reproducably did solve the problem with
the jitter. We verified this with a high quality oscilloscope and
numerous powercycles at different temperatures. The U-Boot in use was
2010.09 and some old X-Loader, both of which dont touch the PLL4/5 stuff.
Introducing the current U-Boot (to make use of SPL) brought up above
described problems with the clock, probably due to setting the lock mode
active. Hence this patch for DM37xx.
I think it's dangerous to assume that the mixture of an unpatched Linux with
a patched u-boot will never occur, and the cause of the failure that results
is pretty subtle. So whatever gets merged would be safer if it restored the
default setting of CM_CLKSEL5_PLL prior to handing off control to Linux.
Agree, we should not apply this, till we also have an 'approved' patch
for mainline linux posted. Right now we have a set of kernel hacks,
but no agreed on method as the kernel maintainer did not have a board
that suffered from the errata..
Unfortunately I dont find the origin of the kernel patch anymore, can
somebody point me in the right direction? Otherwise I could open a new
post on the linux-omap list. What do you think?
btw: here's a version that seems to work on v3.11-rc5:
https://raw.github.com/RobertCNelson/armv7-multiplatform/v3.11.x/patches/omap_sprz319_erratum_v2.1/0001-hack-omap-clockk-dpll5-apply-sprz319e-2.1-erratum-kernel-3.11-rc2.patch
Here my applied kernel patch. I had it working both on kernel 3.1 as
well as 3.4:
diff --git a/arch/arm/mach-omap2/clkt_clksel.c
b/arch/arm/mach-omap2/clkt_clksel.c
index e25364d..e378fe7 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -460,6 +460,21 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned
long rate)
return 0;
}
+int omap2_clksel_force_divisor(struct clk *clk, int new_div)
+{
+ u32 field_val;
+
+ field_val = _divisor_to_clksel(clk, new_div);
+ if (field_val == ~0)
+ return -EINVAL;
+
+ _write_clksel_reg(clk, field_val);
+
+ clk-rate = clk-parent-rate / new_div;
+
+ return 0;
+}
+
/*
* Clksel parent setting function - not passed in struct clk function
* pointer - instead, the OMAP clock code currently assumes that any
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 48ac568..3d2c899 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -61,6 +61,12 @@ void omap3_dpll_allow_idle(struct clk *clk);
void omap3_dpll_deny_idle(struct clk *clk);
u32 omap3_dpll_autoidle_read(struct clk *clk);
int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
+#if CONFIG_ARCH_OMAP3
+int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel);
+/* If you are using this function and not on OMAP3, you are
+ * Doing It Wrong(tm), so there is no stub.
+ */
+#endif
int omap3_noncore_dpll_enable(struct clk *clk);
void omap3_noncore_dpll_disable(struct clk *clk);
int omap4_dpllmx_gatectrl_read(struct clk *clk);
@@ -84,6 +90,7 @@ unsigned long omap2_clksel_recalc(struct clk *clk);
long omap2_clksel_round_rate(struct clk *clk, unsigned long
[U-Boot] The sched standalone app is not working on MPC8308RDB
First of all, the examples/standalone/Makefile is still using architecture ppc instead of powerpc. The sched application is never compiled. I replace ppc with powerpc inside this Makefile, the sched application is now compiled. But the sched application is not working correctly. Once one thread is finished and returned, there will be a program check exception. Run log attached: U-Boot 2012.10-00571-g2c624f4 (Aug 13 2013 - 14:02:12)MPC83XX Reset Status: Software Hard, External/Internal Soft, External/Internal Hard CPU: e300c3, MPC8308, Rev: 1.0 at 400 MHz, CSB: 133.333 MHz Board: Freescale MPC8308RDB Rev 1.0 I2C: ready DRAM: 128 MiB (DDR2, 32-bit, ECC off, 266.667 MHz) Flash: 8 MiB PCIE0: No link In:serial Out: serial Err: serial Net: PHY reset timed out eTSEC0 [PRIME], eTSEC1 Auto-update from TFTP: failed, env. variable 'updatefile' not found Hit any key to stop autoboot: 0 = boot Speed: 1000, full duplex Using eTSEC0 device TFTP from server 192.168.1.1; our IP address is 192.168.0.123; sending through gateway 192.168.1.1 Filename 'mpc8308rdb/standalone.bin'. Load address: 0x4 Loading: # done Bytes transferred = 3120 (c30 hex) ## Starting application at 0x0004 ... schedtest: Created thread with id 1, name 0 schedtest: Created thread with id 2, name 1 schedtest: Created thread with id 3, name 2 schedtest: Created thread with id 4, name 3 schedtest: Created thread with id 5, name 4 schedtest: Created thread with id 6, name 5 schedtest: Created thread with id 7, name 6 schedtest: Threads created sched_test: function=0x00040338 schedtest: Setting thread 1 runnable testthread: Begin executing thread, myname 0, i=0x00054e30 Thread 00, i=0 schedtest: Setting thread 2 runnable testthread: Begin executing thread, myname 1, i=0x00057040 Thread 01, i=0 schedtest: Setting thread 3 runnable testthread: Begin executing thread, myname 2, i=0x00059250 Thread 02, i=0 schedtest: Setting thread 4 runnable testthread: Begin executing thread, myname 3, i=0x0005b460 Thread 03, i=0 schedtest: Setting thread 5 runnable testthread: Begin executing thread, myname 4, i=0x0005d670 Thread 04, i=0 schedtest: Setting thread 6 runnable testthread: Begin executing thread, myname 5, i=0x0005f880 Thread 05, i=0 schedtest: Setting thread 7 runnable testthread: Begin executing thread, myname 6, i=0x00061a90 Thread 06, i=0 schedtest: Started 7 threads schedtest: Waiting for threads to complete testthread: returning 1, i=0x NIP: 07F2FF2C XER: 2000 LR: 07F2FF2C REGS: 00054d58 TRAP: 0700 DAR: MSR: 0008b002 EE: 1 PR: 0 FP: 1 ME: 1 IR/DR: 00 GPR00: 07F2FF2C 00054E48 07F2FF2C 0001 000A 0010 GPR08: FFFC 0020 FFFA 00054E48 42042044 FA6FABBC 07F306B8 GPR16: 07F30778 07FF53E8 07FF4EB8 00052E40 0002 GPR24: 2210 000409EA 0001 00040A11 00052E40 0006 00050C30 Call backtrace: 07F2FF2C 0007 A67EB143 Program Check Exception Resetting the board. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 2/2] fsl_i2c: add workaround for the erratum I2C A004447
Hello Chunhe, Am 16.08.2013 09:10, schrieb Chunhe Lan: This workaround is for the erratum I2C A004447. Device reference manual provides a scheme that allows the I2C master controller to generate nine SCL pulses, which enable an I2C slave device that held SDA low to release SDA. However, due to this erratum, this scheme no longer works. In addition, when I2C is used as a source of the PBL, the state machine is not able to recover. At the same time, delete the reduplicative definition of SVR_VER and SVR_REV. The SVR_REV is the low 8 bits rather than the low 16 bits of svr. And we use the CONFIG_SYS_FSL_A004447_SVR_REV macro instead of hard-code value 0x10, 0x11 and 0x20. The CONFIG_SYS_FSL_A004447_SVR_REV = 0x00 represents that one version of platform has this I2C errata. So enable this errata by IS_SVR_REV(svr, maj, min) function. Signed-off-by: Zhao Chenhuichenhui.z...@freescale.com Signed-off-by: Chunhe Lanchunhe@freescale.com Cc: Scott Woodscottw...@freescale.com Cc: Heiko Schocherh...@denx.de --- Changes for v2: - Caller directly uses CONFIG_SYS_FSL_A004447_SVR_REV to judge whether SVR_REV is less than or equal CONFIG_SYS_FSL_A004447_SVR_REV - SVR_REV is the low 8 bits rather than the low 16 bits of svr Changes for v3: - Rework codes for the newest mainline arch/powerpc/cpu/mpc85xx/cmd_errata.c |5 + arch/powerpc/include/asm/config_mpc85xx.h | 16 arch/powerpc/include/asm/fsl_i2c.h|1 + arch/powerpc/include/asm/processor.h |5 + drivers/i2c/fsl_i2c.c | 14 +++--- 5 files changed, 34 insertions(+), 7 deletions(-) Applied to u-boot-i2c.git, thanks. bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/2] fsl_i2c: generate nine pulses on SCL if the I2C bus is hung
Hello Chunhe, Am 16.08.2013 09:10, schrieb Chunhe Lan: When the code detected that the bus is hung (e.g. SDA stuck low), send 9 pulses on SCL to try to fixup the bus. Signed-off-by: Zhao Chenhuichenhui.z...@freescale.com Signed-off-by: Chunhe Lanchunhe@freescale.com Cc: Scott Woodscottw...@freescale.com Cc: Heiko Schocherh...@denx.de --- Changes for v2: - No change Changes for v3: - Rework codes for the newest mainline drivers/i2c/fsl_i2c.c | 59 +++- 1 files changed, 57 insertions(+), 2 deletions(-) Applied to u-boot-i2c.git, thanks. bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] i2c:multibus:fix: Correct I2C_MULTI_BUS value when support for many buses is enabled
Hello Lukasz, Am 16.08.2013 15:31, schrieb Lukasz Majewski: The I2C_MULTI_BUS needs to be defined for correct I2C operation with many software emulated I2C controllers. This fix restores correct value of the I2C_MULTI_BUS changed by following commit: SHA1: 385c9ef5a7215b2b0c22836fee6c692dfc8559d7 i2c: add i2c_core and prepare for new multibus support Signed-off-by: Lukasz Majewskil.majew...@samsung.com Cc: Heiko Schocherh...@denx.de --- include/i2c.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Applied to u-boot-i2c.git, thanks. bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] i2c:samsung: Adjust Trats, GONI and Universal_c210 boards to work with new I2C framework
Hello Lukasz, Am 16.08.2013 15:33, schrieb Lukasz Majewski: New I2C framework, introduced after v2013.07 final release, imposed I2C code adjustment for some Samsung boards - namely Trats, GONI and Universal_c210. Those boards were using schematic based I2C enumeration (I2C_5, I2C_9). However, new I2C framework imposes usage of logical I2C adapters numbering (e.g. I2C_0, I2C_1, etc). Additionally, I2C_GET_* macros were replaced with i2c_*_bus_num() functions. Trats board gained definition of second soft I2C adapter. Signed-off-by: Lukasz Majewskil.majew...@samsung.com Cc: Minkyu Kangmk7.k...@samsung.com Cc: Heiko Schocherh...@denx.de --- board/samsung/common/multi_i2c.c | 14 ++ board/samsung/goni/goni.c|6 +- board/samsung/trats/trats.c | 17 - board/samsung/universal_c210/universal.c |4 include/configs/trats.h |3 +++ 5 files changed, 30 insertions(+), 14 deletions(-) Applied to u-boot-i2c.git, thanks. bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ARM: omap3: Implement dpll5 (HSUSB clk) workaround for OMAP36xx/AM/DM37xx according to errata sprz318e.
Hi, On 08/20/2013 11:50 AM, Andreas Naumann wrote: Hi, Am 16.08.2013 17:30, schrieb Robert Nelson: On Fri, Aug 16, 2013 at 10:07 AM, Robert Nelson robertcnel...@gmail.com wrote: On Fri, Aug 16, 2013 at 9:34 AM, Peter A. Bigot p...@pabigot.com wrote: On 08/16/2013 08:38 AM, Tom Rini wrote: On Wed, Aug 14, 2013 at 09:53:16PM -0500, Peter A. Bigot wrote: On 07/09/2013 02:43 AM, Naumann Andreas wrote: In chapter 'Advisory 2.1 USB Host Clock Drift Causes USB Spec Non-compliance in Certain Configurations' of the TI Errata it is recommended to use certain div/mult values for the DPLL5 clock setup. So far u-boot used the old 34xx values, so I added the errata recommended values specificly for 36xx init only. Also, the FSEL registers exist no longer, so removed them from init. Tested this on a AM3703 board with 19.2MHz oscillator, which previously couldnt lock the dpll5 (kernel complained). As a consequence the EHCI USB port wasnt usable in U-Boot and kernel. With this patch, kernel panics disappear and USB working fine in u-boot and kernel. Signed-off-by: Andreas Naumann anaum...@ultratronik.de While this patch works with Linux that has been patched for this erratum, it will cause problems with some unpatched versions of Linux. Right. So Linux also needs to be patched for the erratum. Yes. My point was that if you update u-boot alone, then try to use it to boot an unpatched Linux that assumes CM_CLKSEL5_PLL has its power-on value, USB will not work. Oh, I was not aware of that. But indeed i use a patched 3.1 kernel, see below. Some info on the history: In our design (19.2MHz crystal) we could clearly see the errata problem of high jitter on the 60MHz USB clock when (re-)booting a board that was already warmed up. Back then I applied a slightly extended kernel patch (see below) that I found on some kernel list. This reproducably did solve the problem with the jitter. We verified this with a high quality oscilloscope and numerous powercycles at different temperatures. The U-Boot in use was 2010.09 and some old X-Loader, both of which dont touch the PLL4/5 stuff. Introducing the current U-Boot (to make use of SPL) brought up above described problems with the clock, probably due to setting the lock mode active. Hence this patch for DM37xx. What are the symptoms you see when this issue triggers? What is the test case to trigger the error? Is it just running any USB I/O for long enough time? I have a beagle-xm (DM3730 ES1.2) with me and would like to reproduce the error. cheers, -roger ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] mtd: driver _read() returns max_bitflips; mtd_read() returns -EUCLEAN
I'm not entirely sure whether it's a regression from the MTD merge or not, I only started adding support for my board in the past few months so I haven't tried older versions. From a glance at the history I suspect it might have always been possible, but since it only affects setups using software ECC with UBI nobody hit it before. Indeed I've since switched to using hardware ECC for my board so it wouldn't hit it any more either. I can't remember the exact call chain off the top of my head, but it essentially led to UBI constantly scrubbing PEBs since they often (almost always) had some small number of correctable errors. It happened enough that the boot just appeared to hang. Prior to the patch a single bit flip caused mtd to return -EUCLEAN signalling to UBI that the data is potentially at risk and leading it to start scrubbing. In reality since a single bit flip is fine there's no need to. I can switch to software ECC without my patch to rediscover the exact call chain if you require, but it'll probably be a while before I do - busy week! Thanks, Paul On 19/08/13 09:55, Stefan Roese wrote: On 06.08.2013 12:13, Paul Burton wrote: Linux modified the MTD driver interface in commit edbc4540 (with the same name as this commit). The effect is that calls to mtd_read will not return -EUCLEAN if the number of ECC-corrected bit errors is below a certain threshold, which defaults to the strength of the ECC. This allows -EUCLEAN to stop indicating some bits were corrected and begin indicating a large number of bits were corrected, the data held in this region of flash may be lost soon. UBI makes use of this and when -EUCLEAN is returned from mtd_read it will move data to another block of flash. Without adopting this interface change UBI on U-boot attempts to move data between blocks every time a single bit is corrected using the ECC, which is a very common occurance on some devices. For some devices it can be so common that UBI gets stuck constantly moving data around because each block it attempts to use has a single bit error. This patch adopts the interface change as in Linux commit edbc4540 in order to avoid such situations. Given that none of the drivers under drivers/mtd return -EUCLEAN, this should only affect those using software ECC. I have tested that it works on a board which is currently out of tree, but which I hope to be able to begin upstreaming soon. Paul, a quick question to clarify this. This patch fixes a regression in the current mtd-_read implementation (used by UBI) that was introduced by the MTD sync to v3.7.1? Is this correct? And what error exactly did occur on your system? Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] cmd_ubi: add write.part command, to write a volume in multiple parts
Thanks, I'll fix the style issues and send v2 soon.
Paul
On 19/08/13 10:07, Stefan Roese wrote:
Hi Paul,
On 06.08.2013 12:13, Paul Burton wrote:
This allows you to write data to an UBI volume when the amount of memory
available to write that data from is less than the total size of the
data. For example, you may split a root filesystem UBIFS image into
parts, provide the total size of the image to the first write.part
command and then use multiple write.part commands to write the
subsequent parts of the volume. This results in a sequence of commands
akin to:
ext4load mmc 0:1 0x8000 rootfs.ubifs.0
ubi write.part 0x8000 root 0x0800 0x1800
ext4load mmc 0:1 0x8000 rootfs.ubifs.1
ubi write.part 0x8000 root 0x0800
ext4load mmc 0:1 0x8000 rootfs.ubifs.2
ubi write.part 0x8000 root 0x0800
This would write 384MiB of data to the UBI volume 'root' whilst only
requiring 128MiB of said data to be held in memory at a time.
Some coding-style (nitpicking) comments below.
Signed-off-by: Paul Burton paul.bur...@imgtec.com
---
common/cmd_ubi.c | 62 ++--
doc/README.ubi | 3 +++
2 files changed, 50 insertions(+), 15 deletions(-)
diff --git a/common/cmd_ubi.c b/common/cmd_ubi.c
index 5ba4feb..dadb27b 100644
--- a/common/cmd_ubi.c
+++ b/common/cmd_ubi.c
@@ -266,28 +266,15 @@ out_err:
return err;
}
-int ubi_volume_write(char *volume, void *buf, size_t size)
+int ubi_volume_continue_write(char *volume, void *buf, size_t size)
{
int err = 1;
- int rsvd_bytes = 0;
struct ubi_volume *vol;
vol = ubi_find_volume(volume);
if (vol == NULL)
return ENODEV;
- rsvd_bytes = vol-reserved_pebs * (ubi-leb_size - vol-data_pad);
- if (size 0 || size rsvd_bytes) {
- printf(size volume size! Aborting!\n);
- return EINVAL;
- }
-
- err = ubi_start_update(ubi, vol, size);
- if (err 0) {
- printf(Cannot start volume update\n);
- return -err;
- }
-
err = ubi_more_update_data(ubi, vol, buf, size);
if (err 0) {
printf(Couldnt or partially wrote data\n);
@@ -314,6 +301,37 @@ int ubi_volume_write(char *volume, void *buf, size_t size)
return 0;
}
+int ubi_volume_begin_write(char *volume, void *buf, size_t size,
+ size_t full_size)
+{
+ int err = 1;
+ int rsvd_bytes = 0;
+ struct ubi_volume *vol;
+
+ vol = ubi_find_volume(volume);
+ if (vol == NULL)
+ return ENODEV;
+
+ rsvd_bytes = vol-reserved_pebs * (ubi-leb_size - vol-data_pad);
+ if (size 0 || size rsvd_bytes) {
+ printf(size volume size! Aborting!\n);
+ return EINVAL;
+ }
+
+ err = ubi_start_update(ubi, vol, full_size);
+ if (err 0) {
+ printf(Cannot start volume update\n);
+ return -err;
+ }
+
+ return ubi_volume_continue_write(volume, buf, size);
+}
+
+int ubi_volume_write(char *volume, void *buf, size_t size)
+{
+ return ubi_volume_begin_write(volume, buf, size, size);
+}
+
int ubi_volume_read(char *volume, char *buf, size_t size)
{
int err, lnum, off, len, tbuf_size;
@@ -588,7 +606,19 @@ static int do_ubi(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
addr = simple_strtoul(argv[2], NULL, 16);
size = simple_strtoul(argv[4], NULL, 16);
- ret = ubi_volume_write(argv[3], (void *)addr, size);
+ if (strlen(argv[1]) == 10
+ strncmp(argv[1] + 5, .part, 5) == 0) {
+ if (argc 6)
+ ret = ubi_volume_continue_write(argv[3],
+ (void *)addr, size);
Please use braces for multi-line statements.
+ else {
+ size_t full_size;
+ full_size = simple_strtoul(argv[5], NULL, 16);
+ ret = ubi_volume_begin_write(argv[3],
+ (void *)addr, size, full_size);
+ }
Especially when the other branch also uses braces.
+ } else
+ ret = ubi_volume_write(argv[3], (void *)addr, size);
Here again, please braces since the other branch also uses them.
Thanks,
Stefan
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-Boot Driver Development on Atmel's sama5d3xek
Hi Steven, On 8/20/2013 14:04, Steven Rosenberg wrote: Hi Bo, To keep it simple, we need a microcontroller driver that accesses a few peripherals on the board, not just Ethernet(GMAC), also UART, GPIO, I2C, etc. No human intervention. One boots on power up and the driver would need to load and run at boot time and access the hardware (hopefully by interfacing with existing dedicated drivers or by replacing them). I think the peripherals you mentioned are working with the mainline u-boot. If the one you tested doesn't work, please just let us know that. Hence the questions on creating a device driver under uboot. If you can point to specific documentation (possibly a miscellaneous driver category) we would greatly appreciate it. Creating a device tree file from scratch (because atmel did not provide one) seemed like a good deal of work without proper examples and we were looking for more tutorial. Thank you for your help. With Best Regards. Steven. Best Regards, Bo Shen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ARM: omap3: Implement dpll5 (HSUSB clk) workaround for OMAP36xx/AM/DM37xx according to errata sprz318e.
Hi Roger, What are the symptoms you see when this issue triggers? The symptoms are erroneous USB transaction, seen with a USB port analyzer. These only sometimes (not always) stall the USB communication, e.g. a USB mass storage device cant be read any longer. What is the test case to trigger the error? Is it just running any USB I/O for long enough time? Our scenario to reproduce was rebooting a warmed up board (either let it run for 5min or heat up in climate chamber). However, the beagle probably uses a 26 MHz crystal oscillator (our board uses 19.2MHz), so the PLL5 dividers may be set in a way that the problem never occurs. I have a beagle-xm (DM3730 ES1.2) with me and would like to reproduce the error. cheers, -roger regards, Andreas ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [i2c] Pull request
Hello Tom, please pull from u-boot-i2c.git The following changes since commit 40a60c6e8bdd00330310eaa351c9391e74d0bc2c: Prepare v2013.10-rc1 (2013-08-19 17:26:15 -0400) are available in the git repository at: git://git.denx.de/u-boot-i2c.git master for you to fetch changes up to 3fbb517f30fe68e29640bee63ab366569914d898: pmic:i2c: Replace legacy I2C_SET_BUS macro with i2c_set_bus_num() (2013-08-20 11:15:32 +0200) Chunhe Lan (2): fsl_i2c: generate nine pulses on SCL if the I2C bus is hung fsl_i2c: add workaround for the erratum I2C A004447 Łukasz Majewski (3): i2c:multibus:fix: Correct I2C_MULTI_BUS value when support for many buses is enabled i2c:samsung: Adjust Trats, GONI and Universal_c210 boards to work with new I2C framework pmic:i2c: Replace legacy I2C_SET_BUS macro with i2c_set_bus_num() arch/powerpc/cpu/mpc85xx/cmd_errata.c | 5 + arch/powerpc/include/asm/config_mpc85xx.h | 16 arch/powerpc/include/asm/fsl_i2c.h| 1 + arch/powerpc/include/asm/processor.h | 5 + board/samsung/common/multi_i2c.c | 14 ++ board/samsung/goni/goni.c | 6 +- board/samsung/trats/trats.c | 17 - board/samsung/universal_c210/universal.c | 4 drivers/i2c/fsl_i2c.c | 67 +-- drivers/power/power_i2c.c | 2 +- include/configs/trats.h | 3 +++ include/i2c.h | 2 +- 12 Dateien geändert, 120 Zeilen hinzugefügt(+), 22 Zeilen entfernt(-) Thanks! bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] pmic:i2c: Replace legacy I2C_SET_BUS macro with i2c_set_bus_num()
Hello Lukasz, Am 16.08.2013 15:35, schrieb Lukasz Majewski: After introduction of unified i2c model, the I2C_SET_BUS() macro is regarded as obsolete. Hence it is replaced with i2c_set_bus_num() function call. Signed-off-by: Lukasz Majewskil.majew...@samsung.com Cc: Heiko Schocherh...@denx.de Cc: Tom Rinitr...@ti.com --- drivers/power/power_i2c.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Applied to u-boot-i2c.git, thanks. bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 4/4] 64bit initrd start address support
From: David Feng feng...@phytium.com.cn
This patch fix the fdt_initrd function.
It will get #adress_cells property fisrt, then write linux,initrd-start
and linux,initrd-end property value to fdt according to address cell size
such that the 64bit initrd start address could be supported.
Signed-off-by: David Feng feng...@phytium.com.cn
---
common/fdt_support.c | 66 ++
1 file changed, 34 insertions(+), 32 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index b034c98..9bc5821 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -21,6 +21,34 @@
*/
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Get cells len in bytes
+ * if #-cells property is 2 then len is 8
+ * otherwise len is 4
+ */
+static int get_cells_len(void *blob, char *nr_cells_name)
+{
+ const fdt32_t *cell;
+
+ cell = fdt_getprop(blob, 0, nr_cells_name, NULL);
+ if (cell fdt32_to_cpu(*cell) == 2)
+ return 8;
+
+ return 4;
+}
+
+/*
+ * Write a 4 or 8 byte big endian cell
+ */
+static void write_cell(u8 *addr, u64 val, int size)
+{
+ int shift = (size - 1) * 8;
+ while (size-- 0) {
+ *addr++ = (val shift) 0xff;
+ shift -= 8;
+ }
+}
+
/**
* fdt_getprop_u32_default - Find a node and return it's property or a default
*
@@ -131,9 +159,9 @@ static int fdt_fixup_stdout(void *fdt, int chosenoff)
int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force)
{
- int nodeoffset;
+ int nodeoffset, addr_cell_len;
int err, j, total;
- fdt32_t tmp;
+ fdt64_t tmp;
const char *path;
uint64_t addr, size;
@@ -170,9 +198,11 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong
initrd_end, int force)
return err;
}
+ addr_cell_len = get_cells_len(fdt, #address-cells);
+
path = fdt_getprop(fdt, nodeoffset, linux,initrd-start, NULL);
if ((path == NULL) || force) {
- tmp = cpu_to_fdt32(initrd_start);
+ write_cell((u8 *)tmp, initrd_start, addr_cell_len);
err = fdt_setprop(fdt, nodeoffset,
linux,initrd-start, tmp, sizeof(tmp));
if (err 0) {
@@ -181,7 +211,7 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong
initrd_end, int force)
fdt_strerror(err));
return err;
}
- tmp = cpu_to_fdt32(initrd_end);
+ write_cell((u8 *)tmp, initrd_end, addr_cell_len);
err = fdt_setprop(fdt, nodeoffset,
linux,initrd-end, tmp, sizeof(tmp));
if (err 0) {
@@ -343,34 +373,6 @@ void do_fixup_by_compat_u32(void *fdt, const char *compat,
do_fixup_by_compat(fdt, compat, prop, tmp, 4, create);
}
-/*
- * Get cells len in bytes
- * if #-cells property is 2 then len is 8
- * otherwise len is 4
- */
-static int get_cells_len(void *blob, char *nr_cells_name)
-{
- const fdt32_t *cell;
-
- cell = fdt_getprop(blob, 0, nr_cells_name, NULL);
- if (cell fdt32_to_cpu(*cell) == 2)
- return 8;
-
- return 4;
-}
-
-/*
- * Write a 4 or 8 byte big endian cell
- */
-static void write_cell(u8 *addr, u64 val, int size)
-{
- int shift = (size - 1) * 8;
- while (size-- 0) {
- *addr++ = (val shift) 0xff;
- shift -= 8;
- }
-}
-
#ifdef CONFIG_NR_DRAM_BANKS
#define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS
#else
--
1.7.9.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 2/4] board support of arm64
From: David Feng feng...@phytium.com.cn
Signed-off-by: David Feng feng...@phytium.com.cn
---
board/armltd/dts/vexpress64.dts | 439 ++
board/armltd/vexpress64/Makefile | 43
board/armltd/vexpress64/vexpress64.c | 79 ++
boards.cfg |1 +
include/configs/vexpress_aemv8a.h| 203
5 files changed, 765 insertions(+)
create mode 100644 board/armltd/dts/vexpress64.dts
create mode 100644 board/armltd/vexpress64/Makefile
create mode 100644 board/armltd/vexpress64/vexpress64.c
create mode 100644 include/configs/vexpress_aemv8a.h
diff --git a/board/armltd/dts/vexpress64.dts b/board/armltd/dts/vexpress64.dts
new file mode 100644
index 000..067fea7
--- /dev/null
+++ b/board/armltd/dts/vexpress64.dts
@@ -0,0 +1,439 @@
+/*
+ * ARM Ltd. Fast Models
+ *
+ * Architecture Envelope Model (AEM) ARMv8-A
+ * ARMAEMv8AMPCT
+ *
+ * RTSM_VE_AEMv8A.lisa
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x8000 0x0001;
+
+/ {
+ /* boot configurations for u-boot */
+ config {
+ /*bootdelay = 1;*/
+ kernel-offset = 0x10;
+ rootdisk-offset = 0x80;
+ bootcmd = bootm 0x10 0x80:0x200;
+ };
+};
+
+/ {
+ model = RTSM_VE_AEMv8A;
+ compatible = arm,rtsm_ve,aemv8a, arm,vexpress;
+ interrupt-parent = gic;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ /* chosen */
+ /* generated by u-boot */
+
+
+ aliases {
+ serial0 = v2m_serial0;
+ serial1 = v2m_serial1;
+ serial2 = v2m_serial2;
+ serial3 = v2m_serial3;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,armv8;
+ reg = 0;
+ enable-method = spin-table;
+ cpu-release-addr = 0x0 0x8000fff8;
+ };
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,armv8;
+ reg = 1;
+ enable-method = spin-table;
+ cpu-release-addr = 0x0 0x8000fff8;
+ };
+ cpu@2 {
+ device_type = cpu;
+ compatible = arm,armv8;
+ reg = 2;
+ enable-method = spin-table;
+ cpu-release-addr = 0x0 0x8000fff8;
+ };
+ cpu@3 {
+ device_type = cpu;
+ compatible = arm,armv8;
+ reg = 3;
+ enable-method = spin-table;
+ cpu-release-addr = 0x0 0x8000fff8;
+ };
+ };
+
+ memory@8000 {
+ device_type = memory;
+ reg = 0x 0x8000 0 0x8000,
+ 0x0008 0x8000 0 0x8000;
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = arm,cortex-a15-gic, arm,cortex-a9-gic;
+ #interrupt-cells = 3;
+ #address-cells = 0;
+ interrupt-controller;
+ reg = 0x0 0x2c001000 0 0x1000,
+ 0x0 0x2c002000 0 0x1000,
+ 0x0 0x2c004000 0 0x2000,
+ 0x0 0x2c006000 0 0x2000;
+ interrupts = 1 9 0xf04;
+ };
+
+ timer {
+ compatible = arm,armv8-timer;
+ interrupts = 1 13 0xff01,
+1 14 0xff01,
+1 11 0xff01,
+1 10 0xff01;
+ clock-frequency = 1;
+ };
+
+ pmu {
+ compatible = arm,armv8-pmuv3;
+ interrupts = 0 60 4,
+0 61 4,
+0 62 4,
+0 63 4;
+ };
+
+ smb {
+ compatible = simple-bus;
+
+ #address-cells = 2;
+ #size-cells = 1;
+ ranges = 0 0 0 0x0800 0x0400,
+1 0 0 0x1400 0x0400,
+2 0 0 0x1800 0x0400,
+3 0 0 0x1c00 0x0400,
+4 0 0 0x0c00 0x0400,
+5 0 0 0x1000 0x0400;
+
+ #interrupt-cells = 1;
+ interrupt-map-mask = 0 0 63;
+ interrupt-map = 0 0 0 gic 0 0 4,
+ 0 0 1 gic 0 1 4,
+ 0 0 2 gic 0 2 4,
+ 0 0 3 gic 0 3 4,
+ 0 0 4 gic 0 4 4,
+ 0 0 5 gic 0 5 4,
+ 0 0 6 gic 0 6 4,
+
[U-Boot] [PATCH v4 0/4] arm64 patch
From: David Feng feng...@phytium.com.cn *** BLURB HERE *** The porting has been merged with arm architecture. There are many arguments about whether the porting should be made as a seperated architecture. We could make comparition now. Most architecture codes are placed in arch/arm/cpu/armv8 directory, but CONFIG_ARMV8 is needed in many place espetially in arm include files. Generic board is also supported after a few bugs are fixed. David Feng (4): core support of arm64 board support of arm64 generic board patch of manual reloc and zero gd_t 64bit initrd start address support arch/arm/config.mk |6 + arch/arm/cpu/armv8/Makefile | 56 arch/arm/cpu/armv8/cache.S | 145 ++ arch/arm/cpu/armv8/cache_v8.c | 291 arch/arm/cpu/armv8/config.mk| 29 ++ arch/arm/cpu/armv8/cpu.c| 68 + arch/arm/cpu/armv8/crt0.S | 130 + arch/arm/cpu/armv8/exceptions.S | 182 + arch/arm/cpu/armv8/interrupts.c | 116 arch/arm/cpu/armv8/relocate.S | 71 + arch/arm/cpu/armv8/start.S | 200 ++ arch/arm/cpu/armv8/timer.c | 95 +++ arch/arm/cpu/armv8/tlb.S| 38 +++ arch/arm/cpu/armv8/u-boot.lds | 83 ++ arch/arm/include/asm/arch-armv8/armv8.h | 44 arch/arm/include/asm/arch-armv8/gpio.h | 26 ++ arch/arm/include/asm/arch-armv8/mmu.h | 117 arch/arm/include/asm/config.h | 10 + arch/arm/include/asm/global_data.h |6 +- arch/arm/include/asm/io.h | 12 +- arch/arm/include/asm/macro.h| 26 ++ arch/arm/include/asm/posix_types.h | 31 +++ arch/arm/include/asm/proc-armv/ptrace.h | 38 +++ arch/arm/include/asm/proc-armv/system.h | 58 +++- arch/arm/include/asm/types.h| 14 + arch/arm/include/asm/u-boot.h |4 + arch/arm/lib/Makefile |8 + arch/arm/lib/board.c| 18 ++ arch/arm/lib/bootm.c| 16 ++ board/armltd/dts/vexpress64.dts | 439 +++ board/armltd/vexpress64/Makefile| 43 +++ board/armltd/vexpress64/vexpress64.c| 79 ++ boards.cfg |1 + common/board_f.c| 12 +- common/board_r.c| 17 ++ common/fdt_support.c| 66 ++--- common/image.c |1 + examples/standalone/stubs.c | 15 ++ include/configs/vexpress_aemv8a.h | 203 ++ include/image.h |1 + 40 files changed, 2774 insertions(+), 41 deletions(-) create mode 100644 arch/arm/cpu/armv8/Makefile create mode 100644 arch/arm/cpu/armv8/cache.S create mode 100644 arch/arm/cpu/armv8/cache_v8.c create mode 100644 arch/arm/cpu/armv8/config.mk create mode 100644 arch/arm/cpu/armv8/cpu.c create mode 100644 arch/arm/cpu/armv8/crt0.S create mode 100644 arch/arm/cpu/armv8/exceptions.S create mode 100644 arch/arm/cpu/armv8/interrupts.c create mode 100644 arch/arm/cpu/armv8/relocate.S create mode 100644 arch/arm/cpu/armv8/start.S create mode 100644 arch/arm/cpu/armv8/timer.c create mode 100644 arch/arm/cpu/armv8/tlb.S create mode 100644 arch/arm/cpu/armv8/u-boot.lds create mode 100644 arch/arm/include/asm/arch-armv8/armv8.h create mode 100644 arch/arm/include/asm/arch-armv8/gpio.h create mode 100644 arch/arm/include/asm/arch-armv8/mmu.h create mode 100644 board/armltd/dts/vexpress64.dts create mode 100644 board/armltd/vexpress64/Makefile create mode 100644 board/armltd/vexpress64/vexpress64.c create mode 100644 include/configs/vexpress_aemv8a.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 3/4] generic board patch of manual reloc and zero gd_t
From: David Feng feng...@phytium.com.cn
1. function board_init_f in board_f.c should firstly zero gd_t structure
before it call initcall_run_list, otherwise the debug print will go run
if DEBUG is defined. Because the printf function will use global data
to determine whether serial port is initialized and could be written.
2. function board_init_r in board_r.c should firstly relocate init_sequence_r
table before it call initcall_run_list. Command table also should be
relocated.
Signed-off-by: David Feng feng...@phytium.com.cn
---
common/board_f.c |6 ++
common/board_r.c | 17 +
2 files changed, 23 insertions(+)
diff --git a/common/board_f.c b/common/board_f.c
index 5e738fb..f437bcb 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -1009,6 +1009,12 @@ void board_init_f(ulong boot_flags)
gd = data;
#endif
+ /*
+* Zero gd_t first, otherwise the debug print in initcall_run_list
+* function before zero_global_data is called will go wrong.
+*/
+ memset((void *)gd, 0, sizeof(gd_t));
+
gd-flags = boot_flags;
if (initcall_run_list(init_sequence_f))
diff --git a/common/board_r.c b/common/board_r.c
index 86ca1cb..1b4bdd2 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -157,6 +157,13 @@ static int initr_reloc_global_data(void)
*/
gd-env_addr += gd-relocaddr - CONFIG_SYS_MONITOR_BASE;
#endif
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+ /*
+* We have to relocate the command table manually
+*/
+ fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+ ll_entry_count(cmd_tbl_t, cmd));
+#endif /* CONFIG_NEEDS_MANUAL_RELOC */
return 0;
}
@@ -899,6 +906,7 @@ init_fnc_t init_sequence_r[] = {
initr_modem,
#endif
run_main_loop,
+ NULL,
};
void board_init_r(gd_t *new_gd, ulong dest_addr)
@@ -906,6 +914,15 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
#ifndef CONFIG_X86
gd = new_gd;
#endif
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+ /*
+* We have to relocate the init_sequence_r table manually
+*/
+ init_fnc_t *init_fnc_ptr;
+ for (init_fnc_ptr = init_sequence_r; *init_fnc_ptr; ++init_fnc_ptr)
+ *init_fnc_ptr = (init_fnc_t *)((unsigned long)(*init_fnc_ptr) +
gd-reloc_off);
+#endif /* CONFIG_NEEDS_MANUAL_RELOC */
+
if (initcall_run_list(init_sequence_r))
hang();
--
1.7.9.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] arm:goni:mmc: Add sd card detection and initialization.
This change allow to use sd card on Goni the same like mmc 0.
SD card is mmc dev 1, so it can be used like this: fatls mmc 1:2.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
CC: Minkyu Kang mk7.k...@samsung.com
---
board/samsung/goni/goni.c | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
index c05801d..3b236b4 100644
--- a/board/samsung/goni/goni.c
+++ b/board/samsung/goni/goni.c
@@ -69,6 +69,7 @@ int checkboard(void)
int board_mmc_init(bd_t *bis)
{
int i;
+ int ret;
/* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */
s5p_gpio_direction_output(s5pc110_gpio-j2, 7, 1);
@@ -91,7 +92,36 @@ int board_mmc_init(bd_t *bis)
s5p_gpio_set_drv(s5pc110_gpio-g0, i, GPIO_DRV_4X);
}
- return s5p_mmc_init(0, 4);
+ ret = s5p_mmc_init(0, 4);
+ if (ret) {
+ puts(MMC: Failed to init MMC:0.\n);
+ return ret;
+ }
+
+ /*
+* SD card (T_FLASH) detect and init
+* T_FLASH_DETECT: EINT28: GPH3[4] input mode
+*/
+ s5p_gpio_cfg_pin(s5pc110_gpio-h3, 4, GPIO_INPUT);
+ s5p_gpio_set_pull(s5pc110_gpio-h3, 4, GPIO_PULL_UP);
+
+ if (!s5p_gpio_get_value(s5pc110_gpio-h3, 4)) {
+ for (i = 0; i 7; i++) {
+ if (i == 2)
+ continue;
+ /* GPG2[0:6] special function 2 */
+ s5p_gpio_cfg_pin(s5pc110_gpio-g2, i, 0x2);
+ /* GPG2[0:6] pull disable */
+ s5p_gpio_set_pull(s5pc110_gpio-g2, i, GPIO_PULL_NONE);
+ /* GPG2[0:6] drv 4x */
+ s5p_gpio_set_drv(s5pc110_gpio-g2, i, GPIO_DRV_4X);
+ }
+ if (s5p_mmc_init(2, 4))
+ puts(MMC: Failed to init SD card (MMC:2).\n);
+ }
+
+ /* SD card init is optional so print information when it fails only */
+ return ret;
}
#endif
--
1.7.9.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] ums: Extend ums to use all mmc devices.
This change allows using every mmc device instance with ums,
like eMMC or SD cards.
Example: ums device_number for mmc devices.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
CC: Marek Vasut marek.va...@gmail.com
---
common/cmd_usb_mass_storage.c |7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/common/cmd_usb_mass_storage.c b/common/cmd_usb_mass_storage.c
index 33a4715..4181d3a 100644
--- a/common/cmd_usb_mass_storage.c
+++ b/common/cmd_usb_mass_storage.c
@@ -14,6 +14,7 @@
int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
+ struct mmc *mmc = NULL;
char *ep;
unsigned int dev_num = 0, offset = 0, part_size = 0;
int rc;
@@ -28,8 +29,10 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
dev_num = (int)simple_strtoul(argv[1], ep, 16);
- if (dev_num) {
- puts(\nSet eMMC device to 0! - e.g. ums 0\n);
+ mmc = find_mmc_device(dev_num);
+
+ if (!mmc) {
+ printf(\neMMC device: %d not found! Try ums 0.\n, dev_num);
goto fail;
}
--
1.7.9.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] arm:mmc:goni/exynos: Fix wrong mmc base register devices offset.
On s5pc1xx mmc devices offset is multiply of 0x10,
wrong value was 0x1. Register offset always points
to mmc 0 before this change.
Add macro definition of mmc dev register offset to s5pc1xx and
exynos mmc.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
CC: Minkyu Kang mk7.k...@samsung.com
---
arch/arm/include/asm/arch-exynos/mmc.h |6 +-
arch/arm/include/asm/arch-s5pc1xx/mmc.h |6 +-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/mmc.h
b/arch/arm/include/asm/arch-exynos/mmc.h
index 96610b8..98312d1 100644
--- a/arch/arm/include/asm/arch-exynos/mmc.h
+++ b/arch/arm/include/asm/arch-exynos/mmc.h
@@ -8,6 +8,8 @@
#ifndef __ASM_ARCH_MMC_H_
#define __ASM_ARCH_MMC_H_
+#define S5P_MMC_DEV_OFFSET 0x1
+
#define SDHCI_CONTROL2 0x80
#define SDHCI_CONTROL3 0x84
#define SDHCI_CONTROL4 0x8C
@@ -55,7 +57,9 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width);
static inline unsigned int s5p_mmc_init(int index, int bus_width)
{
- unsigned int base = samsung_get_base_mmc() + (0x1 * index);
+ unsigned int base = samsung_get_base_mmc() +
+ (S5P_MMC_DEV_OFFSET * index);
+
return s5p_sdhci_init(base, index, bus_width);
}
#endif
diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h
b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
index 96610b8..55ff10b 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
@@ -8,6 +8,8 @@
#ifndef __ASM_ARCH_MMC_H_
#define __ASM_ARCH_MMC_H_
+#define S5P_MMC_DEV_OFFSET 0x10
+
#define SDHCI_CONTROL2 0x80
#define SDHCI_CONTROL3 0x84
#define SDHCI_CONTROL4 0x8C
@@ -55,7 +57,9 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width);
static inline unsigned int s5p_mmc_init(int index, int bus_width)
{
- unsigned int base = samsung_get_base_mmc() + (0x1 * index);
+ unsigned int base = samsung_get_base_mmc() +
+(S5P_MMC_DEV_OFFSET * index);
+
return s5p_sdhci_init(base, index, bus_width);
}
#endif
--
1.7.9.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] arm64 porting
hi, The merging of arm64 to arm is complete. I have updated the PATCH v4. There are many arguments about whether the porting should be made as a seperated architecture. now we can make comparison. When porting as a seperated architecture, all architecture specific files and include files are located in arm64 directory. the code is simple and clear because any unused code could be got rid of. After merging it to arm, a few files are shared in which CONFIG_ARMV8 is used to distinguish arm64 specific part. That's ok except that there are two architecture code in arm architecture, ARM and ARM64(IH_ARCH_ARM and IH_ARCH_ARM64). It's hard to say which implementation is better. All things depends on how u-boot want it's code to be. Regards. David Feng ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 02/12] TI:armv7: Move CONFIG_SPL_LIBDISK_SUPPORT to MMC section
We only need this library when we're doing disk access to MMC/SD. Update comment around the rest of CONFIG_SPL_LIB* to note that the others are always required. Signed-off-by: Tom Rini tr...@ti.com --- include/configs/ti_armv7_common.h |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index e0ab691..1e4bca5 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -223,14 +223,14 @@ #endif #ifdef CONFIG_MMC +#define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_FAT_SUPPORT #endif -/* General parts of the framework. */ +/* General parts of the framework, required. */ #define CONFIG_SPL_I2C_SUPPORT #define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 04/12] TI:am335x: Better comment and organize the networking related options
While in here, drop CONFIG_BOOTP_DEFAULT as it is unused in the code. Signed-off-by: Tom Rini tr...@ti.com --- include/configs/am335x_evm.h | 11 +-- include/configs/ti_am335x_common.h | 11 +-- 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index e0a87f8..5ed1dca 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -228,17 +228,24 @@ /* SPL */ #ifndef CONFIG_NOR_BOOT #define CONFIG_SPL_YMODEM_SUPPORT + +/* CPSW support */ +#define CONFIG_SPL_ETH_SUPPORT + +/* USB gadget RNDIS */ +#define CONFIG_SPL_MUSB_NEW_SUPPORT + +/* General network SPL, both CPSW and USB gadget RNDIS */ #define CONFIG_SPL_NET_SUPPORT #define CONFIG_SPL_ENV_SUPPORT #define CONFIG_SPL_NET_VCI_STRING AM335x U-Boot SPL -#define CONFIG_SPL_ETH_SUPPORT + #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_BUS 0 #define CONFIG_SPL_SPI_CS 0 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x2 -#define CONFIG_SPL_MUSB_NEW_SUPPORT #define CONFIG_SPL_LDSCRIPT$(CPUDIR)/am33xx/u-boot-spl.lds #ifdef CONFIG_NAND diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 0eae9c8..837c02c 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -28,18 +28,17 @@ #define CONFIG_SYS_NS16550_CLK 4800 /* Network defines. */ -#define CONFIG_CMD_NET +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ #define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_DRIVER_TI_CPSW -#define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_SUBNETMASK #define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_CMD_PING +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ /* * SPL related defines. The Public RAM memory map the ROM defines the -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 01/12] am33xx: Correct and expand comments on CONFIG_SPL_MAX_SIZE
We had been allowing the max size to be larger than actually allowed by the ROM. Expand the commentary here to explain why we set these locations. Signed-off-by: Tom Rini tr...@ti.com --- arch/arm/include/asm/arch-am33xx/omap.h |2 +- include/configs/ti_am335x_common.h | 10 -- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 1f84311..2250721 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -18,7 +18,7 @@ #ifdef CONFIG_AM33XX #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END0x4031 -#define SRAM_SCRATCH_SPACE_ADDR0x4030C000 +#define SRAM_SCRATCH_SPACE_ADDR0x4030B800 #elif defined(CONFIG_TI81XX) #define NON_SECURE_SRAM_START 0x4030 #define NON_SECURE_SRAM_END0x4032 diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index fd3ffab..0eae9c8 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -41,9 +41,15 @@ #define CONFIG_BOOTP_SUBNETMASK #define CONFIG_NET_RETRY_COUNT 10 -/* SPL defines. */ +/* + * SPL related defines. The Public RAM memory map the ROM defines the + * area between 0x402F0400 and 0x4030B800 as a download area and + * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also + * supports X-MODEM loading via UART, and we leverage this and then use + * Y-MODEM to load u-boot.img, when booted over UART. + */ #define CONFIG_SPL_TEXT_BASE 0x402F0400 -#define CONFIG_SPL_MAX_SIZE(0x4030C000 - CONFIG_SPL_TEXT_BASE) +#define CONFIG_SPL_MAX_SIZE(0x4030B800 - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_YMODEM_SUPPORT /* -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 03/12] omap5: Expand CONFIG_SPL_MAX_SIZE and comment upon SRAM_SCRATCH_SPACE_ADDR
After examining both TRMs and doing some experimentation, we can rely on
using the start of the download area for CONFIG_SPL_TEXT_BASE and then
move SRAM_SCRATCH_SPACE_ADDR up, just like am335x. This is required for
peripheral boot modes such as UART.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/include/asm/arch-omap5/omap.h | 11 ++-
include/configs/omap5_common.h |4 ++--
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h
b/arch/arm/include/asm/arch-omap5/omap.h
index 597c692..e9a51d3 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -153,6 +153,15 @@ struct s32ktimer {
#define EFUSE_4 0x45145100
#endif /* __ASSEMBLY__ */
+/*
+ * In all cases, the TRM defines the RAM Memory Map for the processor
+ * and indicates the area for the downloaded image. We use all of that
+ * space for download and once up and running may use other parts of the
+ * map for our needs. We set a scratch space that is at the end of the
+ * OMAP5 download area, but within the DRA7xx download area (as it is
+ * much larger) and do not, at this time, make use of the additional
+ * space.
+ */
#ifdef CONFIG_DRA7XX
#define NON_SECURE_SRAM_START 0x4030
#define NON_SECURE_SRAM_END0x4038 /* Not inclusive */
@@ -160,7 +169,7 @@ struct s32ktimer {
#define NON_SECURE_SRAM_START 0x4030
#define NON_SECURE_SRAM_END0x4032 /* Not inclusive */
#endif
-#define SRAM_SCRATCH_SPACE_ADDRNON_SECURE_SRAM_START
+#define SRAM_SCRATCH_SPACE_ADDR0x4031E000
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4031F000
diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h
index 8e82fed..0345c57 100644
--- a/include/configs/omap5_common.h
+++ b/include/configs/omap5_common.h
@@ -128,8 +128,8 @@
/* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE 0x40300350
-#define CONFIG_SPL_MAX_SIZE0x19000 /* 100K */
+#define CONFIG_SPL_TEXT_BASE 0x4030
+#define CONFIG_SPL_MAX_SIZE(0x4031E000 - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_DISPLAY_PRINT
#define CONFIG_SPL_LDSCRIPT $(CPUDIR)/omap-common/u-boot-spl.lds
--
1.7.9.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 00/12] am33xx/omap5: Improve docs for customization
Hey all, The following series aims to make it easier to take the various ARMv7 TI reference platforms and use them as the base for a custom hardware project. The main outputs here are some re-shuffling of the config headers to try and group things somewhat logically, expanding on comments to make it clear where some values come from and finally correcting a few values based on careful reading of the TRM. The big change here is that we've changed where OMAP5/DRA7xx loads SPL to. Based on reading the TRM as well as testing DRA7xx with UART loading, we're moving the load address to the start of the ROM defined download area, and using another area for scratch space. The series has been boot tested on am335x and omap5_uevm. -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 06/12] am335x_evm: Regroup USB options
Signed-off-by: Tom Rini tr...@ti.com --- include/configs/am335x_evm.h | 80 ++ 1 file changed, 41 insertions(+), 39 deletions(-) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 4e6429c..eae5a19 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -171,44 +171,6 @@ run mmcboot; \ run nandboot; -/* USB Composite download gadget - g_dnl */ -#define CONFIG_USB_GADGET -#define CONFIG_USBDOWNLOAD_GADGET - -/* USB TI's IDs */ -#define CONFIG_G_DNL_VENDOR_NUM 0x0403 -#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 -#define CONFIG_G_DNL_MANUFACTURER Texas Instruments - -/* USB Device Firmware Update support */ -#define CONFIG_DFU_FUNCTION -#define CONFIG_DFU_MMC -#define CONFIG_CMD_DFU -#define DFU_ALT_INFO_MMC \ - boot part 0 1; \ - rootfs part 0 2; \ - MLO fat 0 1; \ - MLO.raw mmc 100 100; \ - u-boot.img.raw mmc 300 400; \ - spl-os-args.raw mmc 80 80; \ - spl-os-image.raw mmc 900 2000; \ - spl-os-args fat 0 1; \ - spl-os-image fat 0 1; \ - u-boot.img fat 0 1; \ - uEnv.txt fat 0 1 -#ifdef CONFIG_NAND -#define CONFIG_DFU_NAND -#define DFU_ALT_INFO_NAND \ - SPL part 0 1; \ - SPL.backup1 part 0 2; \ - SPL.backup2 part 0 3; \ - SPL.backup3 part 0 4; \ - u-boot part 0 5; \ - u-boot-spl-os part 0 6; \ - kernel part 0 8; \ - rootfs part 0 9 -#endif - /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM10x44e09000 /* Base EVM has UART0 */ #define CONFIG_SYS_NS16550_COM20x48022000 /* UART1 */ @@ -283,13 +245,19 @@ #endif /* - * USB configuration + * USB configuration. We enable MUSB support, both for host and for + * gadget. We set USB0 as peripheral and USB1 as host, based on the + * board schematic and physical port wired to each. Then for host we + * add mass storage support and for gadget we add both RNDIS ethernet + * and DFU. */ #define CONFIG_USB_MUSB_DSPS #define CONFIG_ARCH_MISC_INIT #define CONFIG_MUSB_GADGET #define CONFIG_MUSB_PIO_ONLY #define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +#define CONFIG_USB_GADGET +#define CONFIG_USBDOWNLOAD_GADGET #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW2 #define CONFIG_MUSB_HOST @@ -307,6 +275,11 @@ #define CONFIG_USB_ETHER #define CONFIG_USB_ETH_RNDIS #define CONFIG_USBNET_HOST_ADDRde:ad:be:af:00:00 + +/* USB TI's IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x0403 +#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 +#define CONFIG_G_DNL_MANUFACTURER Texas Instruments #endif /* CONFIG_MUSB_GADGET */ #if defined(CONFIG_SPL_BUILD) defined(CONFIG_SPL_USBETH_SUPPORT) @@ -318,6 +291,35 @@ #undef CONFIG_SPL_ETH_SUPPORT #endif +/* USB Device Firmware Update support */ +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC +#define CONFIG_CMD_DFU +#define DFU_ALT_INFO_MMC \ + boot part 0 1; \ + rootfs part 0 2; \ + MLO fat 0 1; \ + MLO.raw mmc 100 100; \ + u-boot.img.raw mmc 300 400; \ + spl-os-args.raw mmc 80 80; \ + spl-os-image.raw mmc 900 2000; \ + spl-os-args fat 0 1; \ + spl-os-image fat 0 1; \ + u-boot.img fat 0 1; \ + uEnv.txt fat 0 1 +#ifdef CONFIG_NAND +#define CONFIG_DFU_NAND +#define DFU_ALT_INFO_NAND \ + SPL part 0 1; \ + SPL.backup1 part 0 2; \ + SPL.backup2 part 0 3; \ + SPL.backup3 part 0 4; \ + u-boot part 0 5; \ + u-boot-spl-os part 0 6; \ + kernel part 0 8; \ + rootfs part 0 9 +#endif + /* * Default to using SPI for environment, etc. * 0x00 - 0x02 : SPL (128KiB) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 05/12] am335x_evm: Add comment by SPL SPI support
Signed-off-by: Tom Rini tr...@ti.com --- include/configs/am335x_evm.h |2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 5ed1dca..4e6429c 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -240,12 +240,14 @@ #define CONFIG_SPL_ENV_SUPPORT #define CONFIG_SPL_NET_VCI_STRING AM335x U-Boot SPL +/* SPI flash. */ #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_BUS 0 #define CONFIG_SPL_SPI_CS 0 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x2 + #define CONFIG_SPL_LDSCRIPT$(CPUDIR)/am33xx/u-boot-spl.lds #ifdef CONFIG_NAND -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 07/12] TI:armv7: Re-order slightly the generic CONFIG options, expand related comments
Re-group the general options to note things that can be removed safely to reduce binary size when not required, and expand the comment about what commands we do include to note it could be replaced with a specific list of required one. While at it, move the CMD parts of various blocks IP to the end of the list for consistency. Signed-off-by: Tom Rini tr...@ti.com --- include/configs/ti_armv7_common.h | 22 -- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 1e4bca5..e89e874 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -60,12 +60,12 @@ /* I2C IP block */ #define CONFIG_I2C -#define CONFIG_CMD_I2C #define CONFIG_HARD_I2C #define CONFIG_SYS_I2C_SPEED 10 #define CONFIG_SYS_I2C_SLAVE 1 #define CONFIG_I2C_MULTI_BUS #define CONFIG_DRIVER_OMAP24XX_I2C +#define CONFIG_CMD_I2C /* MMC/SD IP block */ #define CONFIG_MMC @@ -87,10 +87,10 @@ * access CS0 at is 0x800. */ #ifdef CONFIG_NAND -#define CONFIG_CMD_NAND #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_BASE 0x800 #define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_CMD_NAND #endif /* @@ -103,14 +103,18 @@ * console baudrate of 115200 and use the default baud rate table. */ #define CONFIG_SYS_MALLOC_LEN (1024 10) -#define CONFIG_SYS_LONGHELP #define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT U-Boot# +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_BAUDRATE115200 +#define CONFIG_ENV_VARS_UBOOT_CONFIG /* Strongly encouraged */ +#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ + +/* As stated above, the following choices are optional. */ +#define CONFIG_SYS_LONGHELP #define CONFIG_AUTO_COMPLETE #define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_PROMPT U-Boot# #define CONFIG_VERSION_VARIABLE -#define CONFIG_ENV_VARS_UBOOT_CONFIG -#define CONFIG_BAUDRATE115200 /* We set the max number of command args high to avoid HUSH bugs. */ #define CONFIG_SYS_MAXARGS 64 @@ -123,9 +127,6 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_CONSOLE_INFO_QUIET - /* * When we have SPI, NOR or NAND flash we expect to be making use of * mtdparts, both for ease of use in U-Boot and for passing information @@ -141,7 +142,8 @@ * useful commands. Note that we must have set CONFIG_SYS_NO_FLASH * prior to this include, in order to skip a few commands. When we do * have flash, if we expect these commands they must be enabled in that - * config. + * config. If desired, a specific list of desired commands can be used + * instead. */ #include config_cmd_default.h #define CONFIG_CMD_ASKENV -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 11/12] omap5_uevm: Better comment why we have TCA642X and the reset time
Signed-off-by: Tom Rini tr...@ti.com --- include/configs/omap5_uevm.h |3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index d10c2b5..3948709 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -35,12 +35,15 @@ #define CONFIG_PARTITION_UUIDS #define CONFIG_CMD_PART +/* Required support for the TCA642X GPIO we have on the uEVM */ #define CONFIG_TCA642X #define CONFIG_CMD_TCA642X #define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4 #define CONFIG_SYS_I2C_TCA642X_ADDR 0x22 #define CONSOLEDEV ttyO2 + +/* Max time to hold reset on this board, see doc/README.omap-reset-time */ #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296 #include configs/omap5_common.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 10/12] TI:omap5: Clarify comments about SPL and DDR timings in common config
Signed-off-by: Tom Rini tr...@ti.com --- include/configs/omap5_common.h | 15 --- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index 0345c57..98ba559 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -28,9 +28,12 @@ /* Use General purpose timer 1 */ #define CONFIG_SYS_TIMERBASE GPT2_BASE +/* + * For the DDR timing information we can either dynamically determine + * the timings to use or use pre-determined timings (based on using the + * dynamic method. Default to the static timing infomation. + */ #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - -/* Defines for SDRAM init */ #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS @@ -127,7 +130,13 @@ fi -/* Defines for SPL */ +/* + * SPL related defines. The Public RAM memory map the ROM defines the + * area between 0x4030 and 0x4031E000 as a download area for OMAP5 + * (dra7xx is larger, but we do not need to be larger at this time). We + * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and + * print some information. + */ #define CONFIG_SPL_TEXT_BASE 0x4030 #define CONFIG_SPL_MAX_SIZE(0x4031E000 - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_DISPLAY_PRINT -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 12/12] dra7xx_evm: Re-order and comment the networking related config options
Signed-off-by: Tom Rini tr...@ti.com --- include/configs/dra7xx_evm.h | 18 -- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 58786ff..4fbe768 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -26,21 +26,19 @@ #include configs/omap5_common.h /* CPSW Ethernet */ -#define CONFIG_CMD_NET +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ #define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_MII -#define CONFIG_DRIVER_TI_CPSW -#define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_NET_MULTI -#define CONFIG_PHY_GIGE +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ +#define CONFIG_PHY_GIGE/* per-board part of CPSW */ #define CONFIG_PHYLIB #define CONFIG_PHY_ADDR2 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 08/12] am335x_evm: Update README for customization
As this is a reference platform, update the README to note which IP blocks are required for use due to design choices of the reference rather than required by the SoC itself. Signed-off-by: Tom Rini tr...@ti.com --- board/ti/am335x/README | 28 +++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/board/ti/am335x/README b/board/ti/am335x/README index 67b5246..2a30ab8 100644 --- a/board/ti/am335x/README +++ b/board/ti/am335x/README @@ -13,7 +13,33 @@ documented in TI's reference designs: - AM335x EVM SK - Beaglebone White - Beaglebone Black -' + +Customization += + +Given that all of the above boards are reference platforms (and the +Beaglebone platforms are OSHA), it is likely that this platform code and +configuration will be used as the basis of a custom platform. It is +worth noting that aside from things such as NAND or MMC only being +required if a custom platform makes use of these blocks, the following +are required, depending on design: + +- GPIO is only required if DDR3 power is controlled in a way similar to + EVM SK +- SPI is only required for SPI flash, or exposing the SPI bus. + +The following blocks are required: +- I2C, to talk with the PMIC and ensure that we do not run afoul of + errata 1.0.24. + +When removing options as part of customization, +CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your +needs and to remove no longer relevant options as in some cases we +define additional text blocks (such as for NAND or DFU strings). Also +note that all of the SPL options are grouped together, rather than with +the IP blocks, so both areas will need their choices updated to reflect +the custom design. + NAND -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 09/12] TI:am33xx: Move SPL YMODEM support to the per-board config
Signed-off-by: Tom Rini tr...@ti.com --- include/configs/ti_am335x_common.h |1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 837c02c..d2e34ae 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -49,7 +49,6 @@ */ #define CONFIG_SPL_TEXT_BASE 0x402F0400 #define CONFIG_SPL_MAX_SIZE(0x4030B800 - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SPL_YMODEM_SUPPORT /* * Since SPL did pll and ddr initialization for us, -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5] SPL: Makefile: Build a separate autoconf.mk for SPL
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 08/19/2013 06:07 PM, York Sun wrote: On 08/19/2013 03:04 PM, Tom Rini wrote: On Mon, Aug 19, 2013 at 02:20:25PM -0700, York Sun wrote: On 08/19/2013 12:54 PM, Tom Rini wrote: On Mon, Aug 19, 2013 at 02:47:53PM -0500, Scott Wood wrote: On Mon, 2013-08-19 at 16:14 +0800, ying.zh...@freescale.com wrote: From: Ying Zhang b40...@freescale.com No. You added one line AFAICT. Preserve the original author here. Indeed. Do we need Ying to send a new version? We can reset the author to Joe when applying this patch. SPL defines CONFIG_SPL_BUILD but this does not percolate to the autoconf.mk Makefile. As a result the build breaks when CONFIG_SPL_BUILD is used in the board-specific include header file. With this, there is a possibility of having a CONFIG option defined in the header file but not defined in the Makefile causing all kinds of build failure and problems. It also messes things for up, for example, when one might want to undefine options to keep the SPL small and doesn't want to be stuck with the CONFIG options used for U-boot. Lastly, this also avoids defining special CONFIG_SPL_ variables for cases where some options are required in U-boot but not in SPL. We add a spl-autoconf.mk rule that is generated for SPL with the CONFIG_SPL_BUILD flag and conditionally include it for SPL builds. Signed-off-by: Joel A Fernandes joelag...@ti.com Signed-off-by: Ying Zhang b40...@freescale.com --- Change from v4: - No change. Change from v3: - No change. Surely there was *some* change or you wouldn't have reposted... v4 was adding Joel's S-o-b line back to the changelog. I tried to run MAKEALL for arm and powerpc. Powerpc all passed but I am having errors for arm, before applying this patch. I am using Linaro's gcc 4.8.2 for arm. Should I use a different toolchain? I am not used to work on arm platforms. That's expected as the Linaro toolchain isn't good for all ARMs. I'll pass this through some testing locally as well. Any suggestion on cross toolchain for ARM. I want to extend my MAKEALL coverage, but don't want to deal with too many varieties of toolchains. ELDK 5.2.x works for all ARM (and MIPS). - -- Tom -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQIcBAEBAgAGBQJSE2g7AAoJENk4IS6UOR1WMUIP/0adzkiNhsKBhjn39KNCpOSB mwlRxpPMlDzzlUPWJCcZ+sWuxqRw7tpdq309x6G4ojUU4mXdZGv5kcs22kEJoTze 48GxFJQG30AMk0smgoAS9DgBoHS2UYPTQtnza77HBM9LlvOKzq0X9/xqJBn1jFOK CJ+BPNh6HbAN3plwd0Oj2QgBvzR0K6yYmsVAhIliDv6KBhLfWA6Rakj4NqSoO3n3 e3zd3v2PR7WGXS0wGmSlCx48ORiSTxuIRY4Y3dZPV0qaxoQ5KuJDw8ASuPmj2YGz zwSYrFTSbMVuIRB+pXtKRpxu2UjgKS/a0I074WM2ObMoNo00L5o3CWMBbQdllouL AHdASNbGIm7XWN9SI2lcvOIIKAizoELxnzvB9eETsrzUk5n7YYBeM6yyXeZcpZ6q hXPSRPyh9vae5rV5hbNs1ReBG+Dr73YtMFcUBUqbcyCHWFxe3O5CFjlPaKdwiQ1X eIeK+7p4YmCJJJAQy6Qq0RqUuNVPZn6EXUgbuizDRZgny7ssOHya8dQHfLU6+wP6 PcLvTh8ix1bTNKPXye/bzMBc0NrJDVwoa2RQqZBehnSZpTfpu/eHQaIFHJaBxDRl QQgKCwEkRvcmJsJTrGcrPI6G9h4a74kl7sKmGkhq6rq7qAz1zpm5tsPJ16s4RRwR GcBF/qLc6iUBntQmAtM9 =JXfU -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5] SPL: Makefile: Build a separate autoconf.mk for SPL
On Mon, Aug 19, 2013 at 04:14:14PM +0800, ying.zh...@freescale.com wrote: From: Ying Zhang b40...@freescale.com SPL defines CONFIG_SPL_BUILD but this does not percolate to the autoconf.mk Makefile. As a result the build breaks when CONFIG_SPL_BUILD is used in the board-specific include header file. With this, there is a possibility of having a CONFIG option defined in the header file but not defined in the Makefile causing all kinds of build failure and problems. It also messes things for up, for example, when one might want to undefine options to keep the SPL small and doesn't want to be stuck with the CONFIG options used for U-boot. Lastly, this also avoids defining special CONFIG_SPL_ variables for cases where some options are required in U-boot but not in SPL. We add a spl-autoconf.mk rule that is generated for SPL with the CONFIG_SPL_BUILD flag and conditionally include it for SPL builds. Signed-off-by: Joel A Fernandes joelag...@ti.com Signed-off-by: Ying Zhang b40...@freescale.com After fixing up the author and changing Joel's email to his current one, applied to u-boot/master (and boot tested on am335x_evm_usbspl), thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ARM: omap3: Implement dpll5 (HSUSB clk) workaround for OMAP36xx/AM/DM37xx according to errata sprz318e.
On Tue, Aug 20, 2013 at 5:15 AM, Andreas Naumann d...@andin.de wrote: Hi Roger, What are the symptoms you see when this issue triggers? The symptoms are erroneous USB transaction, seen with a USB port analyzer. These only sometimes (not always) stall the USB communication, e.g. a USB mass storage device cant be read any longer. What is the test case to trigger the error? Is it just running any USB I/O for long enough time? Our scenario to reproduce was rebooting a warmed up board (either let it run for 5min or heat up in climate chamber). However, the beagle probably uses a 26 MHz crystal oscillator (our board uses 19.2MHz), so the PLL5 dividers may be set in a way that the problem never occurs. The xM uses a 26Mhz, but the errata still applies, as a number of customer boards do show the issue.. http://www.ti.com/lit/er/sprz319e/sprz319e.pdf page 113 I have a beagle-xm (DM3730 ES1.2) with me and would like to reproduce the error. Roger, this only seems to effect a small number of xM's, as it seems to vary on pll drift. So if your xM is fine, i do have a spare xM C, that pretty reliably shows the issue after transferring a large amount of data over the usb port... I had traded a good xM with a customer such that i could keep re-basing our out of tree dpll5 tweak.. Regards, -- Robert Nelson http://www.rcn-ee.com/ ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ARM: DRA: EMIF: Change DDR3 settings to use hw leveling
Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using
software leveling. This was done since hardware leveling was not
working. Now that the right sequence to do hw leveling is identified,
use it. This is required for EMIF clockdomain to idle and come back
during lowpower usecases.
Boot tested on DRA7 evm, OMAP5 uevm, OMAP4 panda
Signed-off-by: Sricharan R r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap-common/emif-common.c | 96 +
arch/arm/cpu/armv7/omap5/hw_data.c |9 +-
arch/arm/cpu/armv7/omap5/hwinit.c| 12 ++-
arch/arm/cpu/armv7/omap5/sdram.c | 146 +++---
arch/arm/include/asm/arch-omap5/omap.h |1 +
arch/arm/include/asm/emif.h |4 +-
6 files changed, 153 insertions(+), 115 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c
b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 9ede3f5..8ff796a 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -226,24 +226,40 @@ static void ddr3_leveling(u32 base, const struct
emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- /* keep sdram in self-refresh */
- writel(((LP_MODE_SELF_REFRESH EMIF_REG_LP_MODE_SHIFT)
-EMIF_REG_LP_MODE_MASK), emif-emif_pwr_mgmt_ctrl);
- __udelay(130);
+ if (omap_revision() != DRA752_ES1_0){
+ /* keep sdram in self-refresh */
+ writel(((LP_MODE_SELF_REFRESH EMIF_REG_LP_MODE_SHIFT)
+EMIF_REG_LP_MODE_MASK), emif-emif_pwr_mgmt_ctrl);
+ __udelay(130);
+
+ /*
+* Set invert_clkout (if activated)--DDR_PHYCTRL_1
+* Invert clock adds an additional half cycle delay on the
+* command interface. The additional half cycle, is usually
+* meant to enable leveling in the situation that DQS is later
+* than CK on the board.It also helps provide some additional
+* margin for leveling.
+*/
+ writel(regs-emif_ddr_phy_ctlr_1,
+ emif-emif_ddr_phy_ctrl_1);
+
+ writel(regs-emif_ddr_phy_ctlr_1,
+ emif-emif_ddr_phy_ctrl_1_shdw);
+ __udelay(130);
+
+ writel(((LP_MODE_DISABLE EMIF_REG_LP_MODE_SHIFT)
+EMIF_REG_LP_MODE_MASK), emif-emif_pwr_mgmt_ctrl);
+ } else {
+ u32 fifo_reg;
- /*
-* Set invert_clkout (if activated)--DDR_PHYCTRL_1
-* Invert clock adds an additional half cycle delay on the command
-* interface. The additional half cycle, is usually meant to enable
-* leveling in the situation that DQS is later than CK on the board.It
-* also helps provide some additional margin for leveling.
-*/
- writel(regs-emif_ddr_phy_ctlr_1, emif-emif_ddr_phy_ctrl_1);
- writel(regs-emif_ddr_phy_ctlr_1, emif-emif_ddr_phy_ctrl_1_shdw);
- __udelay(130);
+ fifo_reg = readl(emif-emif_ddr_fifo_misaligned_clear_1);
+ writel(fifo_reg | 0x0100,
+ emif-emif_ddr_fifo_misaligned_clear_1);
- writel(((LP_MODE_DISABLE EMIF_REG_LP_MODE_SHIFT)
-EMIF_REG_LP_MODE_MASK), emif-emif_pwr_mgmt_ctrl);
+ fifo_reg = readl(emif-emif_ddr_fifo_misaligned_clear_2);
+ writel(fifo_reg | 0x0100,
+ emif-emif_ddr_fifo_misaligned_clear_2);
+ }
/* Launch Full leveling */
writel(DDR3_FULL_LVL, emif-emif_rd_wr_lvl_ctl);
@@ -255,25 +271,19 @@ static void ddr3_leveling(u32 base, const struct
emif_regs *regs)
/* Read data eye leveling no of samples */
config_data_eye_leveling_samples(base);
- /* Launch 8 incremental WR_LVL- to compensate for PHY limitation */
- writel(0x2 EMIF_REG_WRLVLINC_INT_SHIFT, emif-emif_rd_wr_lvl_ctl);
- __udelay(130);
-
- /* Launch Incremental leveling */
- writel(DDR3_INC_LVL, emif-emif_rd_wr_lvl_ctl);
- __udelay(130);
-}
-
-static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs)
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
- writel(regs-emif_ddr_phy_ctlr_1, emif-emif_ddr_phy_ctrl_1);
- writel(regs-emif_ddr_phy_ctlr_1, emif-emif_ddr_phy_ctrl_1_shdw);
- config_data_eye_leveling_samples(base);
-
- writel(regs-emif_rd_wr_lvl_ctl, emif-emif_rd_wr_lvl_ctl);
- writel(regs-sdram_config, emif-emif_sdram_config);
+ if (omap_revision() == DRA752_ES1_0) {
+ /*
+* Launch 8 incremental WR_LVL- to compensate
+* for PHY limitation
+*/
+ writel(0x2 EMIF_REG_WRLVLINC_INT_SHIFT,
+ emif-emif_rd_wr_lvl_ctl);
+ __udelay(130);
[U-Boot] [PATCH] usb: new board-specific USB init interface
This commit unifies board-specific USB initialization implementations
under one symbol (usb_board_init), declaration of which is available in
usb.h.
---
Changes since RFC:
- NVIDIA Tegra doesn't postpone its USB init anymore
- board_usb_init()'s sole argument name was shortened
- networking code comment style (/* blurb...) dropped
- squashed RFC changes so that patch won't break bisect
Signed-off-by: Mateusz Zalega m.zal...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Reviewed-by: Lukasz Majewski l.majew...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Marek Vasut ma...@denx.de
Cc: Tom Warren twar...@nvidia.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
arch/arm/include/asm/arch-tegra/usb.h | 3 +--
board/amcc/canyonlands/canyonlands.c | 5 +++--
board/balloon3/balloon3.c | 5 +++--
board/esd/apc405/apc405.c | 5 +++--
board/esd/pmc440/pmc440.c | 5 +++--
board/icpdas/lp8x4x/lp8x4x.c | 5 +++--
board/nvidia/common/board.c | 4 +++-
board/samsung/trats/trats.c | 5 +++--
board/toradex/colibri_pxa270/colibri_pxa270.c | 5 +++--
board/trizepsiv/conxs.c | 5 +++--
board/vpac270/vpac270.c | 5 +++--
common/cmd_dfu.c | 5 ++---
common/cmd_usb_mass_storage.c | 3 ++-
common/usb.c | 5 +
drivers/usb/host/ehci-omap.c | 8 +---
drivers/usb/host/ehci-tegra.c | 2 +-
drivers/usb/host/ohci-hcd.c | 4 ++--
drivers/usb/host/ohci.h | 12 +---
include/g_dnl.h | 2 --
include/usb.h | 19 ++-
include/usb_mass_storage.h| 12 +---
21 files changed, 72 insertions(+), 52 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/usb.h
b/arch/arm/include/asm/arch-tegra/usb.h
index f66257c..a1efd07 100644
--- a/arch/arm/include/asm/arch-tegra/usb.h
+++ b/arch/arm/include/asm/arch-tegra/usb.h
@@ -131,8 +131,7 @@
/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
#define VBUS_VLD_STS (1 26)
-
/* Setup USB on the board */
-int board_usb_init(const void *blob);
+int usb_process_devicetree(const void *blob);
#endif /* _TEGRA_USB_H_ */
diff --git a/board/amcc/canyonlands/canyonlands.c
b/board/amcc/canyonlands/canyonlands.c
index cc36f45..27ab243 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -16,6 +16,7 @@
#include asm/4xx_pcie.h
#include asm/ppc4xx-gpio.h
#include asm/errno.h
+#include usb.h
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH
chips */
@@ -188,7 +189,7 @@ int board_early_init_f(void)
}
#if defined(CONFIG_USB_OHCI_NEW) defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
-int usb_board_init(void)
+int board_usb_init(enum board_usb_init_type init)
{
struct board_bcsr *bcsr_data =
(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
@@ -229,7 +230,7 @@ int usb_board_stop(void)
return 0;
}
-int usb_board_init_fail(void)
+int board_usb_init_fail(void)
{
return usb_board_stop();
}
diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c
index ecbac16..b15d60f 100644
--- a/board/balloon3/balloon3.c
+++ b/board/balloon3/balloon3.c
@@ -13,6 +13,7 @@
#include asm/io.h
#include spartan3.h
#include command.h
+#include usb.h
DECLARE_GLOBAL_DATA_PTR;
@@ -59,7 +60,7 @@ void dram_init_banksize(void)
}
#ifdef CONFIG_CMD_USB
-int usb_board_init(void)
+int board_usb_init(enum board_usb_init_type init)
{
writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL)
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
@@ -90,7 +91,7 @@ int usb_board_init(void)
return 0;
}
-void usb_board_init_fail(void)
+void board_usb_init_fail(void)
{
return;
}
diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c
index f13f088..8f0fd1c 100644
--- a/board/esd/apc405/apc405.c
+++ b/board/esd/apc405/apc405.c
@@ -17,6 +17,7 @@
#include mtd/cfi_flash.h
#include asm/4xx_pci.h
#include pci.h
+#include usb.h
DECLARE_GLOBAL_DATA_PTR;
@@ -428,7 +429,7 @@ void reset_phy(void)
}
#if defined(CONFIG_USB_OHCI_NEW) defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
-int usb_board_init(void)
+int board_usb_init(enum board_usb_init_type init)
{
return 0;
}
@@ -453,7 +454,7 @@ int usb_board_stop(void)
return 0;
}
-int usb_board_init_fail(void)
+int board_usb_init_fail(void)
{
usb_board_stop();
return 0;
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
index 549b3b7..6a3b52a 100644
--- a/board/esd/pmc440/pmc440.c
+++ b/board/esd/pmc440/pmc440.c
@@ -27,6 +27,7 @@
#endif
#include serial.h
#include asm/4xx_pci.h
+#include usb.h
Re: [U-Boot] [PATCH 1/2] usb:dfu:g_dnl: Change number of exported configurations at composite gadget
Hi Lukasz, -Original Message- From: Lukasz Majewski [mailto:l.majew...@samsung.com] Sent: Montag, 19. August 2013 17:17 To: u-boot@lists.denx.de Cc: Lukasz Majewski; Heiko Schocher; Tormod Volden; Lukasz Majewski; Marek Vasut; Egli, Samuel Subject: [PATCH 1/2] usb:dfu:g_dnl: Change number of exported configurations at composite gadget USB composite gadget (g_dnl) supports only one configuration. Due to that the corresponding field - bConfigurationValue has been changed. Moreover more descriptive names were chosen for relevant fields. Windows XP setup: - Thesyscon USB Descriptor Dumper - zadig_xp program for WinUSB installation (which is required by dfu- util) - dfu-util for windows (version 0.6) - TRATS target connected via USB hub to test Win XP machine. Tested at: Trats - Exynos4210 I applied both patches and tested download from windows 7 with dfu-util 0.7 and it worked all fine. Thanks! Best Sam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [ANN] v2013.10-rc1
On Mon, Aug 19, 2013 at 06:02:26PM -0400, Tom Rini wrote: Hey all, I've put v2013.10-rc1 out, and I hope Detlev can get the tarball uploaded soon. We've got a lot of changes in here, including the SPDX license conversion. I'd like to ask folks to test things and let me know what's in patchwork and should be applied, but hasn't been just yet. So, with -rc1 out, I'd like custodians to focus on looking at patchwork and their todo list there and reviewing / applying things and geting pull requests sent out. I've taken a pass at assigning everything that wasn't assigned and trying to fix the obvious superseded patches. If you've got something in PW and you think someone else should have it, my fault, just re-assign. Thanks all, and lets see if we can't get things cleared out by the time I snap -rc2 in about 2 weeks time. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/7 v11] powerpc: p1022ds: add TPL for p1022ds nand boot
On 08/16/2013 12:16 AM, ying.zh...@freescale.com wrote: From: Ying Zhang b40...@freescale.com TPL is introduced in the patch NAND: TPL : introduce the TPL based on the SPL, here enable TPL for p1022ds nand boot. Signed-off-by: Ying Zhang b40...@freescale.com --- Change from v10: - No change. Change from v9: - Modify drivers/mtd/nand/Makefile. - Modify drivers/mtd/nand/fsl_elbc_spl.c. - Modify include/configs/P1022DS.h, fix checkpatch warnings. Change from v8: - Add new symbol CONFIG_SPL_ENV_IN_NAND. Change from v7: - No change. Change from v6: - Delete the file board/freescale/p1022ds/tpl.c. - Reuse the file board/freescale/p1022ds/spl.c in the TPL. Change from v5: - Change functionality nand_load_image to nand_load, it is called in TPL. Change from v4: - No change. Change from v3: - No change. Change from v2: - No change. Change from v1: - Split from powerpc/p1022ds: nand: introduce the TPL based on the SPL. board/freescale/p1022ds/spl.c | 16 +++ board/freescale/p1022ds/spl_minimal.c | 53 ++ drivers/mtd/nand/Makefile |1 + drivers/mtd/nand/fsl_elbc_spl.c | 27 +--- include/configs/P1022DS.h | 77 ++--- 5 files changed, 103 insertions(+), 71 deletions(-) Applied to u-boot-mpc85xx.git. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/7 v11] powerpc : spi flash : Support to start from eSPI with SPL
On 08/16/2013 12:16 AM, ying.zh...@freescale.com wrote: From: Ying Zhang b40...@freescale.com This patch introduces SPL to enable a loader stub that being loaded by the code from the internal on-chip ROM. It loads the final uboot image into DDR, then jump to it to begin execution. The SPL's size is sizeable, the maximum size must not exceed the size of L2 SRAM. It initializes the DDR through SPD code, and copys final uboot image to DDR. So there are two stage uboot images: * spl_boot, 96KB size. The env variables are copied to L2 SRAM, so that ddr spd code can get the interleaving mode setting in env. It loads final uboot image from offset 96KB. * final uboot image, size is variable depends on the functions enabled. Signed-off-by: Ying Zhang b40...@freescale.com --- Change from v10: - No change. Change from v9: - Modify drivers/mtd/spi/fsl_espi_spl.c, fix checkpatch warnings. Change from v8: - No change. Change from v7: - No change. Change from v6: - No change. Change from v5: - Split from powerpc/p1022ds: boot from spi flash with SPL. - this patch add the capability starting from eSPI with SPL. Change from v4: - No change. Change from v3: - No change. Change from v2: - No change. Change from v1: - Split from boot from SD card/SPI flash with SPL. drivers/mtd/spi/Makefile |1 + drivers/mtd/spi/fsl_espi_spl.c | 77 drivers/mtd/spi/spi_flash.c|2 + 3 files changed, 80 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/spi/fsl_espi_spl.c Applied to u-boot-mpc85xx.git. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 06/10 v5] spl: env_common.c: make CONFIG_SPL_BUILD contain function env_import
On 08/14/2013 07:48 PM, Zhang Ying-B40530 wrote: Hi, York, I see. I am sure there isn't newer version. Applied to u-boot-mpc85xx.git/master. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/7 v11] powerpc: deleted unused symbol CONFIG_SPL_NAND_MINIMAL and enabled some functionality for common SPL
On 08/16/2013 12:16 AM, ying.zh...@freescale.com wrote: From: Ying Zhang b40...@freescale.com 1. The symbol CONFIG_SPL_NAND_MINIMAL is unused, so deleted it. 2. Some functions were unused in the minimal SPL, but it is useful in the common SPL. So, enabled some functionality for common SPL. Signed-off-by: Ying Zhang b40...@freescale.com --- Change from v10: - No change. Change from v9: - No change. Change from v8: - No change. Change from v7: - No change. Change from v6: - No change. Change from v5: - No change. Change from v4: - Use !defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL). - to replace to new symbols. Change from v3: - Give up new symbol and delete the line. - ifndef CONFIG_SPL_BUILD in common/env_common.c. Change from v2: - Split from Add the symbol for the minimal SPL to eliminate unused code. Change from v1: - Split from boot from SD card/SPI flash with SPL. arch/powerpc/cpu/mpc85xx/tlb.c |3 ++- arch/powerpc/cpu/mpc8xxx/law.c |6 -- include/configs/MPC8313ERDB.h |1 - include/configs/P1022DS.h |1 - include/configs/p1_p2_rdb_pc.h |1 - 5 files changed, 6 insertions(+), 6 deletions(-) Applied to u-boot-mpc85xx/master. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/7 v11] powerpc: p1022ds: Enable P1022DS to boot from SD Card with SPL
On 08/16/2013 12:16 AM, ying.zh...@freescale.com wrote: From: Ying Zhang b40...@freescale.com Enable p1022ds to start from eSDHC with SPL. Signed-off-by: Ying Zhang b40...@freescale.com --- Change from v10: - Fix the warning from spl.c. Change from v9: - Mofidy board/freescale/p1022ds/spl.c, fix checkpatch warnings. Change from v8: - No change. Change from v7: - No change. Change from v6: - Split from the patch powerpc/p1022ds: boot from SD Card with SPL. - this patch only enables p1022ds to boot from SD Card with SPL. Change from v5: - No change. Change from v4: - No change. Change from v3: - No change. Change from v2: - No change. Change from v1: - No change. README |4 ++ board/freescale/common/Makefile |2 - board/freescale/p1022ds/Makefile |3 + board/freescale/p1022ds/spl.c| 110 ++ board/freescale/p1022ds/tlb.c| 23 +--- include/configs/P1022DS.h| 54 --- 6 files changed, 179 insertions(+), 17 deletions(-) create mode 100644 board/freescale/p1022ds/spl.c Applied to u-boot-mpc85xx.git. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH][v2] powerpc: Fix CamelCase checkpatch warnings
On 08/16/2013 02:22 AM, Prabhakar Kushwaha wrote: 85xx, 86xx PowerPC folders have code variables with CamelCase naming conventions. because of this code checkpatch script generates WARNING: Avoid CamelCase. Convert variables name to normal naming convention and modify board, driver files with updated the new structure. Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com --- Chages for v2: Incorporated Thomas's comments - Take care of git bisectable arch/powerpc/cpu/mpc85xx/cpu.c | 43 +- arch/powerpc/cpu/mpc85xx/fdt.c | 10 +-- arch/powerpc/cpu/mpc85xx/speed.c| 142 +++ arch/powerpc/cpu/mpc86xx/cpu.c | 16 ++-- arch/powerpc/cpu/mpc86xx/speed.c| 40 - board/freescale/mpc8540ads/mpc8540ads.c |2 +- board/freescale/mpc8541cds/mpc8541cds.c |2 +- board/freescale/mpc8555cds/mpc8555cds.c |2 +- board/freescale/mpc8560ads/mpc8560ads.c |2 +- board/freescale/p1_p2_rdb_pc/ddr.c |2 +- board/freescale/p1_twr/ddr.c|2 +- board/sbc8548/sbc8548.c |4 +- board/socrates/socrates.c |2 +- board/xes/xpedite537x/ddr.c |2 +- drivers/spi/fsl_espi.c |2 +- include/e500.h | 16 ++-- include/mpc86xx.h |6 +- 17 files changed, 149 insertions(+), 146 deletions(-) Applied to u-boot-mpc85xx.git. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/7 v11] powerpc : p1022ds : Enable p1022ds to start from eSPI with SPL
On 08/16/2013 12:16 AM, ying.zh...@freescale.com wrote: From: Ying Zhang b40...@freescale.com Enable p1022ds to start from eSPI with SPL. Signed-off-by: Ying Zhang b40...@freescale.com --- Change from v10: - No change. Change from v9: - No change. Change from v8: - No change. Change from v7: - No change. Change from v6: - No longer changes the header file included by the file. - board/freescale/p1022ds/spl.c. Change from v5: - Split from powerpc/p1022ds: boot from spi flash with SPL. - this patch enable P1022DS to start from eSPI with SPL. Change from v4: - No change. Change from v3: - No change. Change from v2: - No change. Change from v1: - Split from boot from SD card/SPI flash with SPL. board/freescale/p1022ds/spl.c | 10 ++ include/configs/P1022DS.h | 36 +--- 2 files changed, 39 insertions(+), 7 deletions(-) Applied to u-boot-mpc85xx.git. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/7 v11] NAND: TPL : introduce the TPL based on the SPL
On 08/16/2013 12:16 AM, ying.zh...@freescale.com wrote: From: Ying Zhang b40...@freescale.com Due to the nand SPL on some board(e.g. P1022DS)has a size limit, it can not be more than 4K. So, the SPL cannot initialize the DDR with the SPD code. This patch introduces TPL to enable a loader stub that is loaded by the code from the SPL. It initializes the DDR with the SPD or other operations. The TPL's size is sizeable, the maximum size is decided by the memory's size that TPL runs. It initializes the DDR through SPD code, and copys final uboot image to DDR. So there are three stage uboot images: * spl_boot, * tpl_boot, * final uboot image This patch is on top of the patch: SPL: Makefile: Build a separate autoconf.mk for SPL These two lines are removed when applying. Signed-off-by: Ying Zhang b40...@freescale.com --- Change from v10: - No change. Change from v9: - Move the part revision to the other patch. for example:fsl_elbc_spl.c. - Modify the Makefile. - Modify doc/README.TPL, fix checkpatch warnings. Change from v8: - Modify the doc/README.TPL. - Modify the Makefile. - Modify the drivers/mtd/nand/fsl_elbc_spl.c. - Modify the spl/Makefile. Change from v7: - Modify the doc/README.TPL - Modify the spl/Makefile. Change from v6: - Modify the description of the patch. - Add the separate the autoconf.mk for TPL. - Delete the file tpl/Makefile and the directory tpl. - Reuse the spl/Makefie in TPL. Change from v5: - Use ifdef to define nand_load_image to non-static for non-SPL. Change from v4: - No change. Change from v3: - No change. Change from v2: - No change. Change from v1: - Split from powerpc/p1022ds: nand: introduce the TPL based on the SPL. Makefile | 50 ++ README | 16 config.mk | 30 -- doc/README.TPL | 45 + spl/Makefile | 20 5 files changed, 147 insertions(+), 14 deletions(-) create mode 100644 doc/README.TPL Applied to u-boot-mpc85xx.git after removing NAND from the subject. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/7 v11] powerpc: mpc85xx: Support booting from SD Card with SPL
On 08/16/2013 12:16 AM, ying.zh...@freescale.com wrote: From: Ying Zhang b40...@freescale.com The code from the internal on-chip ROM. It loads the final uboot image into DDR, then jump to it to begin execution. The SPL's size is sizeable, the maximum size must not exceed the size of L2 SRAM. It initializes the DDR through SPD code, and copys final uboot image to DDR. So there are two stage uboot images: * spl_boot, 96KB size. The env variables are copied to L2 SRAM, so that ddr spd code can get the interleaving mode setting in env. It loads final uboot image from offset 96KB. * final uboot image, size is variable depends on the functions enabled. Signed-off-by: Ying Zhang b40...@freescale.com --- Change from v10: - No change. Change from v9: - Mofidy drivers/mmc/fsl_esdhc_spl.c, fix checkpatch warnings. Change from v8: - No change. Change from v7: - No change. Change from v6: - Split to the patch Support booting from SD Card with SPL and the patch. - Enable P1022DS to boot from SD Card with SPL. this patch only support. - booting from SD Card with SPL. Change from v5: - Add new symbol CONFIG_SPL_ENV_IMPORT for contain the functionality. - env_import. Change from v4: - No change. Change from v3: - No change. Change from v2: - No change. Change from v1: - Split from boot from SD card/SPI flash with SPL. README |4 + arch/powerpc/cpu/mpc85xx/u-boot-spl.lds|5 + .../cpu/mpc8xxx/ddr/lc_common_dimm_params.c|4 + doc/README.mpc85xx-sd-spi-boot | 81 drivers/mmc/Makefile |3 + drivers/mmc/fsl_esdhc_spl.c| 130 drivers/mmc/mmc.c |2 + include/fsl_esdhc.h|1 + spl/Makefile |3 + 9 files changed, 233 insertions(+), 0 deletions(-) create mode 100644 doc/README.mpc85xx-sd-spi-boot create mode 100644 drivers/mmc/fsl_esdhc_spl.c Applied to u-boot-mpc85xx.git. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] SPDX-License-Identifier: clean up license header
This patch cleans up license header in these files: board/freescale/p1022ds/spl.c drivers/mmc/fsl_esdhc_spl.c drivers/mtd/spi/fsl_espi_spl.c Signed-off-by: York Sun york...@freescale.com --- board/freescale/p1022ds/spl.c | 17 + drivers/mmc/fsl_esdhc_spl.c| 17 + drivers/mtd/spi/fsl_espi_spl.c | 17 + 3 files changed, 3 insertions(+), 48 deletions(-) diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c index 358b2e3..b9dbf81 100644 --- a/board/freescale/p1022ds/spl.c +++ b/board/freescale/p1022ds/spl.c @@ -1,22 +1,7 @@ /* * Copyright 2013 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * + * SPDX-License-Identifier:GPL-2.0+ */ #include common.h diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index 25a1dff..65c52a2 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -1,22 +1,7 @@ /* * Copyright 2013 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * + * SPDX-License-Identifier:GPL-2.0+ */ #include common.h diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c index 9e216a6..6263d8c 100644 --- a/drivers/mtd/spi/fsl_espi_spl.c +++ b/drivers/mtd/spi/fsl_espi_spl.c @@ -1,22 +1,7 @@ /* * Copyright 2013 Freescale Semiconductor, Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * + * SPDX-License-Identifier:GPL-2.0+ */ #include common.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-boot] question about pl310.h / armv7.h
I would agree with the idea moving pl310 functionality into pl310-specific files - armv7 doesn't dictate use of pl310 (or an external cache controller of any nature) at least for about half the possible cores you could go find. Those that need/configure for an external L2 controller may not even really use pl310 (Marvell for example?) even if they're compatible with v7 in nature, so it makes no sense to just lump all the prototypes into a generic header. Obviously it depends on what those functions are and if they're actually implemented elsewhere... in which case they should be moved to the pl310 support so they're not compiled in or needlessly cluttering up other source files. -- Matt On Mon, Aug 19, 2013 at 3:04 AM, tiger...@viatech.com.cn wrote: Hi, experts: There are 4 functions definition in arch/arm/include/asm/pl310.h . But not implemented in cache-pl310.c file. And the implemented functions in cache-pl310.c file are defined in arch/arm/include/asm/armv7.h . So, maybe pl310.h should be deleted? Or function declarations are moved from armv7.h to pl310.h ? Best wishes, ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] powerpc/t4240: fix lanes routing for QSGMII protocols
On 08/19/2013 03:57 AM, Shaohui Xie wrote: From: Shaohui Xie shaohui@freescale.com When using QSGMII protocols, the first lane and third lane on each slot need to be swapped. Signed-off-by: Shaohui Xie shaohui@freescale.com --- Applied to u-boot-mpc85xx/master. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] powerpc/t4240: add QSGMII interface support
On 08/19/2013 03:58 AM, Shaohui Xie wrote: From: Shaohui Xie shaohui@freescale.com Also some fix for QSGMII. 1. fix QSGMII configure of Serdes2. 2. fix PHY address of QSGMII MAC9 MAC10 for each FMAN. 3. fix dtb for QSGMII interface. Signed-off-by: Shaohui Xie shaohui@freescale.com --- Applied to u-boot-mpc85xx/master. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/sec: Add workaround for SEC A-003571
On 08/14/2013 06:31 PM, Shengzhou Liu wrote: Multiple read/write transactions initiated by security engine may cause system to hang. Workaround: set MCFGR[AXIPIPE] to 0 to avoid hang. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 arch/powerpc/cpu/mpc85xx/cpu_init.c | 10 +- arch/powerpc/include/asm/config_mpc85xx.h | 1 + 3 files changed, 14 insertions(+), 1 deletion(-) Applied to u-boot-mpc85xx/master after resolving conflicts. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] powerpc: Print hardcoded size like print_size() does
On 07/31/2013 08:31 AM, Shruti Kanetkar wrote: Makes the startup output more consistent Signed-off-by: Shruti Kanetkar shr...@freescale.com Acked-by: Andy Fleming aflem...@freescale.com --- arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 14 +++--- arch/powerpc/cpu/mpc86xx/cpu.c | 6 +++--- arch/powerpc/cpu/mpc8xx/video.c | 4 ++-- arch/powerpc/cpu/ppc4xx/cpu.c | 6 +++--- 5 files changed, 16 insertions(+), 16 deletions(-) Applied to u-boot-mpc85xx/master after resolving conflicts. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 8/8] mpc85xx: introduce the kmp204x reference design support
On Tue, 2013-08-20 at 08:28 +0200, Valentin Longchamp wrote: On 08/20/2013 02:48 AM, Scott Wood wrote: On Mon, 2013-08-19 at 17:50 +0200, Valentin Longchamp wrote: On 08/13/2013 11:38 PM, Scott Wood wrote: On Fri, 2013-07-26 at 12:02 +0200, Valentin Longchamp wrote: This patch introduces the support for Keymile's kmp204x reference design. This design is based on Freescale's P2040/P2041 SoC. The peripherals used by this design are: - DDR3 RAM with SPD support - SPI NOR Flash as boot medium - NAND Flash - 2 PCIe busses (hosts 1 and 3) - 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5) - 3 Local Bus windows, with one dedicated to the QRIO reset/power mgmt FPGA - 2 HW I2C busses - last but not least, the mandatory serial port The board/keymile/kmp204x code is mostly based on Freescale's P2041rdb support and was changed according to our design (that means essentially removing what is not present on the designs and a few adaptations). A lot of the copied files have had Freescale copyrights removed... Also please try to factor shared code out rather than duplicate, where practical. Well, I had tried to come a first proposal that factored shared code but I was advised to copy the code: [1]. For the copyrights I will fix it. [1] Did you mean to cite something here? Oops, yes sorry: http://u-boot.10912.n7.nabble.com/RFC-PATCH-mpc85xx-move-generic-corenet-to-cpu-mpc85xxx-tt153910.html#none I think the problem there was that you shared too much, not that sharing is bad in general. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 8/8] mpc85xx: introduce the kmp204x reference design support
On Tue, 2013-08-20 at 13:20 -0500, Scott Wood wrote: On Mon, 2013-08-19 at 18:02 -0700, York Sun wrote: On 08/19/2013 05:48 PM, Scott Wood wrote: On Mon, 2013-08-19 at 17:50 +0200, Valentin Longchamp wrote: On 08/13/2013 11:38 PM, Scott Wood wrote: On Fri, 2013-07-26 at 12:02 +0200, Valentin Longchamp wrote: snip + /* TLB 1 */ + /* *I*** - Covers boot page */ + /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff0, it covered the 0xf000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, +MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, +0, 0, BOOKE_PAGESZ_1M, 1), What does that covers boot page comment refer to? Why is L3SRAM I+G? I have taken this from the corenet SYS_RAMBOOT boot scenario since it's also the way our board boots. York, can you answer this? I suspect the covers boot page comment is left over from before the recent spin table changes. Look at the context, this is used as SRAM with PBL boot method. Notice these macros in header file I'm not talking about the SRAM comment, but the covers boot page comment before it. At the very least this mapping can't be *I*G and *I** at the same time. +#define CONFIG_SYS_RAMBOOT +#define CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE and +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDRCONFIG_RAMBOOT_TEXT_BASE +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xfull | \ + CONFIG_RAMBOOT_TEXT_BASE) +#define CONFIG_SYS_L3_SIZE (1024 10) +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) ...and this doesn't cover the boot page. Also, can you answer the question about why the L3 SRAM mapping is cache-inhibited? -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/p1010rdb: fix calculating ddr_freq_mhz
On 08/13/2013 01:41 AM, Shengzhou Liu wrote: There was a bug for calculating ddr_freq_mhz, it should be divided by 100 rather than 0x100. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- board/freescale/p1010rdb/spl_minimal.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) Applied to u-boot-mpc85xx/master. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3][v3] powerpc/common/vsc3316: remove const from vsc3316_config parameter define
On 08/19/2013 03:43 AM, Shaohui Xie wrote: From: Shaohui Xie shaohui@freescale.com Since the parameters need to be modified according to different Serdes protocols at runtime, the const will block this. Also remove const from arrays define used by vsc3316_config. Signed-off-by: Shaohui Xie shaohui@freescale.com --- changes for V3: 1. rebased on top of master branch. changes for V2: 1. changed subject; 2. fix broken on B4xxx boards; board/freescale/b4860qds/b4860qds_crossbar_con.h | 12 ++-- board/freescale/common/vsc3316_3308.c|2 +- board/freescale/common/vsc3316_3308.h|2 +- board/freescale/t4qds/t4240qds.c |8 4 files changed, 12 insertions(+), 12 deletions(-) Applied to u-boot-mpc85xx/master. BTW, very confusing when you submit patches with your name but with another email address shengzhou@freescale.com. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] powerpc: Use print_size() where appropriate
On 07/31/2013 08:31 AM, Shruti Kanetkar wrote: Makes the startup output more consistent Signed-off-by: Shruti Kanetkar shr...@freescale.com Acked-by: Andy Fleming aflem...@freescale.com --- arch/powerpc/cpu/mpc824x/cpu.c | 8 +++- arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 +--- arch/powerpc/cpu/mpc8xx/cpu.c | 24 +++- arch/powerpc/cpu/mpc8xxx/ddr/main.c | 3 ++- 4 files changed, 21 insertions(+), 22 deletions(-) Applied to u-boot-mpc85xx/master. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 8/8] mpc85xx: introduce the kmp204x reference design support
On Mon, 2013-08-19 at 18:02 -0700, York Sun wrote: On 08/19/2013 05:48 PM, Scott Wood wrote: On Mon, 2013-08-19 at 17:50 +0200, Valentin Longchamp wrote: On 08/13/2013 11:38 PM, Scott Wood wrote: On Fri, 2013-07-26 at 12:02 +0200, Valentin Longchamp wrote: snip +/* TLB 1 */ +/* *I*** - Covers boot page */ +/* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff0, it covered the 0xf000. + */ +SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), What does that covers boot page comment refer to? Why is L3SRAM I+G? I have taken this from the corenet SYS_RAMBOOT boot scenario since it's also the way our board boots. York, can you answer this? I suspect the covers boot page comment is left over from before the recent spin table changes. Look at the context, this is used as SRAM with PBL boot method. Notice these macros in header file I'm not talking about the SRAM comment, but the covers boot page comment before it. At the very least this mapping can't be *I*G and *I** at the same time. +#define CONFIG_SYS_RAMBOOT +#define CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE and +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xfull | \ + CONFIG_RAMBOOT_TEXT_BASE) +#define CONFIG_SYS_L3_SIZE (1024 10) +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) ...and this doesn't cover the boot page. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] i.MX6: nitrogen6x: force HDMI onto IPU0/DI0
Our Linux kernel switches the HDMI connector onto IPU0/DI1, but the U-Boot display driver only supports IPU0/DI0 for the time being. Because of this, a soft re-boot will leave the HDMI output connected to the wrong display port and prevent video from being displayed. Signed-off-by: Eric Nelson eric.nel...@boundarydevices.com --- board/boundary/nitrogen6x/nitrogen6x.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 79ab449..1419f36 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -666,7 +666,8 @@ static void setup_display(void) writel(reg, iomux-gpr[2]); reg = readl(iomux-gpr[3]); - reg = (reg ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) + reg = (reg ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK + |IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); writel(reg, iomux-gpr[3]); -- 1.8.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,V3] ppc4xx: Remove CANBT board
On Wed, Aug 07, 2013 at 01:22:10PM +0200, Matthias Fuchs wrote: This board and especially the CPU (PPC405CR) is EOL. Signed-off-by: Matthias Fuchs matthias.fu...@esd.eu Acked-by: Wolfgang Denk w...@denx.de Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [i2c] Pull request
On Tue, Aug 20, 2013 at 12:20:29PM +0200, Heiko Schocher wrote: Hello Tom, please pull from u-boot-i2c.git The following changes since commit 40a60c6e8bdd00330310eaa351c9391e74d0bc2c: Prepare v2013.10-rc1 (2013-08-19 17:26:15 -0400) are available in the git repository at: git://git.denx.de/u-boot-i2c.git master for you to fetch changes up to 3fbb517f30fe68e29640bee63ab366569914d898: pmic:i2c: Replace legacy I2C_SET_BUS macro with i2c_set_bus_num() (2013-08-20 11:15:32 +0200) Chunhe Lan (2): fsl_i2c: generate nine pulses on SCL if the I2C bus is hung fsl_i2c: add workaround for the erratum I2C A004447 ??ukasz Majewski (3): i2c:multibus:fix: Correct I2C_MULTI_BUS value when support for many buses is enabled i2c:samsung: Adjust Trats, GONI and Universal_c210 boards to work with new I2C framework pmic:i2c: Replace legacy I2C_SET_BUS macro with i2c_set_bus_num() arch/powerpc/cpu/mpc85xx/cmd_errata.c | 5 + arch/powerpc/include/asm/config_mpc85xx.h | 16 arch/powerpc/include/asm/fsl_i2c.h| 1 + arch/powerpc/include/asm/processor.h | 5 + board/samsung/common/multi_i2c.c | 14 ++ board/samsung/goni/goni.c | 6 +- board/samsung/trats/trats.c | 17 - board/samsung/universal_c210/universal.c | 4 drivers/i2c/fsl_i2c.c | 67 +-- drivers/power/power_i2c.c | 2 +- include/configs/trats.h | 3 +++ include/i2c.h | 2 +- 12 Dateien ge??ndert, 120 Zeilen hinzugef??gt(+), 22 Zeilen entfernt(-) Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ppc4xx: Remove support for PPC405CR CPUs
On Wed, Aug 07, 2013 at 12:10:38PM +0200, Matthias Fuchs wrote: This patch removes support for the APM 405CR CPU. This CPU is EOL and no board uses this chip. Signed-off-by: Matthias Fuchs matthias.fu...@esd.eu Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] SPDX-License-Identifier: clean up license header
On Tue, Aug 20, 2013 at 10:20:55AM -0700, York Sun wrote: This patch cleans up license header in these files: board/freescale/p1022ds/spl.c drivers/mmc/fsl_esdhc_spl.c drivers/mtd/spi/fsl_espi_spl.c Signed-off-by: York Sun york...@freescale.com Acked-by: Tom Rini tr...@ti.com And please take them in the mpc85xx tree, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: DRA: EMIF: Change DDR3 settings to use hw leveling
On Tue, Aug 20, 2013 at 06:47:36PM +0530, Sricharan R wrote: Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using software leveling. This was done since hardware leveling was not working. Now that the right sequence to do hw leveling is identified, use it. This is required for EMIF clockdomain to idle and come back during lowpower usecases. [snip] #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS OK, so this reminds me, should we be printing out something more now then, when we're calculating timings, rather than using precalculated ones? Or is that a different issue I'm thinking of? -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 8/8] mpc85xx: introduce the kmp204x reference design support
On 08/20/2013 11:21 AM, Scott Wood wrote: On Tue, 2013-08-20 at 13:20 -0500, Scott Wood wrote: On Mon, 2013-08-19 at 18:02 -0700, York Sun wrote: On 08/19/2013 05:48 PM, Scott Wood wrote: On Mon, 2013-08-19 at 17:50 +0200, Valentin Longchamp wrote: On 08/13/2013 11:38 PM, Scott Wood wrote: On Fri, 2013-07-26 at 12:02 +0200, Valentin Longchamp wrote: snip + /* TLB 1 */ + /* *I*** - Covers boot page */ + /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the +* SRAM is at 0xfff0, it covered the 0xf000. +*/ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), What does that covers boot page comment refer to? Why is L3SRAM I+G? I have taken this from the corenet SYS_RAMBOOT boot scenario since it's also the way our board boots. York, can you answer this? I suspect the covers boot page comment is left over from before the recent spin table changes. Look at the context, this is used as SRAM with PBL boot method. Notice these macros in header file I'm not talking about the SRAM comment, but the covers boot page comment before it. I think this entry replaces the default TLB out of reset and it does cover the boot page 0xf000~0x. It is not unique to this platform. You can find many similar existing code. At the very least this mapping can't be *I*G and *I** at the same time. I agree the G bit shouldn't be set here. +#define CONFIG_SYS_RAMBOOT +#define CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE and +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDRCONFIG_RAMBOOT_TEXT_BASE +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xfull | \ + CONFIG_RAMBOOT_TEXT_BASE) +#define CONFIG_SYS_L3_SIZE (1024 10) +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) ...and this doesn't cover the boot page. Also, can you answer the question about why the L3 SRAM mapping is cache-inhibited? I suspect this is the idea carried from early NAND boot implementation. You are mostly familiar with NAND and SPL boot, can you examine if we can turn on the cache for these cases? York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request : u-boot-mpc85xx
Tom, The following changes since commit 39bc12ddc36c9e30199471da0f3a929b178a04b2: SPL: Makefile: Build a separate autoconf.mk for SPL (2013-08-19 18:05:19 -0400) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git master for you to fetch changes up to e6394e9e8f83b77b61f0b240fcd39622571be690: Fix for incorrect conversion hex string to number (FMAN firmware address). (2013-08-20 11:51:26 -0700) Prabhakar Kushwaha (1): powerpc: Fix CamelCase checkpatch warnings Shaohui Xie (3): powerpc/common/vsc3316: remove const from vsc3316_config parameter define powerpc/t4240: fix lanes routing for QSGMII protocols powerpc/t4240: add QSGMII interface support Shengzhou Liu (2): powerpc/p1010rdb: fix calculating ddr_freq_mhz powerpc/sec: Add workaround for SEC A-003571 Shruti Kanetkar (2): powerpc: Use print_size() where appropriate powerpcv2: Print hardcoded size like print_size() does Ying Zhang (8): spl: env_common.c: make CONFIG_SPL_BUILD contain function env_import powerpc: deleted unused symbol CONFIG_SPL_NAND_MINIMAL and enabled some functionality for common SPL powerpc: mpc85xx: Support booting from SD Card with SPL powerpc: p1022ds: Enable P1022DS to boot from SD Card with SPL powerpc : spi flash : Support to start from eSPI with SPL powerpc : p1022ds : Enable p1022ds to start from eSPI with SPL TPL : introduce the TPL based on the SPL powerpc: p1022ds: add TPL for p1022ds nand boot York Sun (1): SPDX-License-Identifier: clean up license header Николай Пузанов (1): Fix for incorrect conversion hex string to number (FMAN firmware address). Makefile | 50 +- README | 24 +++ arch/powerpc/cpu/mpc824x/cpu.c |8 +- arch/powerpc/cpu/mpc85xx/cmd_errata.c |4 + arch/powerpc/cpu/mpc85xx/cpu.c | 45 +++--- arch/powerpc/cpu/mpc85xx/cpu_init.c| 32 ++-- arch/powerpc/cpu/mpc85xx/fdt.c | 12 +- arch/powerpc/cpu/mpc85xx/speed.c | 142 - arch/powerpc/cpu/mpc85xx/t4240_serdes.c| 14 +- arch/powerpc/cpu/mpc85xx/tlb.c |3 +- arch/powerpc/cpu/mpc85xx/u-boot-spl.lds|5 + arch/powerpc/cpu/mpc86xx/cpu.c | 22 +-- arch/powerpc/cpu/mpc86xx/speed.c | 40 ++--- arch/powerpc/cpu/mpc8xx/cpu.c | 24 ++- arch/powerpc/cpu/mpc8xx/video.c|4 +- .../cpu/mpc8xxx/ddr/lc_common_dimm_params.c|4 + arch/powerpc/cpu/mpc8xxx/ddr/main.c|3 +- arch/powerpc/cpu/mpc8xxx/law.c |6 +- arch/powerpc/cpu/ppc4xx/cpu.c |8 +- arch/powerpc/include/asm/config_mpc85xx.h |1 + board/freescale/b4860qds/b4860qds_crossbar_con.h | 12 +- board/freescale/common/Makefile|2 - board/freescale/common/vsc3316_3308.c |2 +- board/freescale/common/vsc3316_3308.h |2 +- board/freescale/mpc8540ads/mpc8540ads.c|2 +- board/freescale/mpc8541cds/mpc8541cds.c|2 +- board/freescale/mpc8555cds/mpc8555cds.c|2 +- board/freescale/mpc8560ads/mpc8560ads.c|2 +- board/freescale/p1010rdb/spl_minimal.c |2 +- board/freescale/p1022ds/Makefile |3 + board/freescale/p1022ds/spl.c | 121 ++ board/freescale/p1022ds/spl_minimal.c | 53 +-- board/freescale/p1022ds/tlb.c | 23 ++- board/freescale/p1_p2_rdb_pc/ddr.c |2 +- board/freescale/p1_twr/ddr.c |2 +- board/freescale/t4qds/eth.c| 80 +++--- board/freescale/t4qds/t4240qds.c | 47 +- board/sbc8548/sbc8548.c|4 +- board/socrates/socrates.c |2 +- board/xes/xpedite537x/ddr.c|2 +- common/env_common.c|2 - config.mk | 30 +++- doc/README.TPL | 45 ++ doc/README.mpc85xx-sd-spi-boot | 81 ++ drivers/mmc/Makefile |3 + drivers/mmc/fsl_esdhc_spl.c| 115 ++ drivers/mmc/mmc.c |2 + drivers/mtd/nand/Makefile |1 + drivers/mtd/nand/fsl_elbc_spl.c| 27 +++- drivers/mtd/spi/Makefile |1 + drivers/mtd/spi/fsl_espi_spl.c
Re: [U-Boot] Fix for incorrect conversion hex string to number (FMAN firmware address).
On 08/08/2013 05:30 PM, York Sun wrote: On 06/19/2013 12:48 AM, Николай Пузанов wrote: --- arch/powerpc/cpu/mpc85xx/fdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- 1.8.1.2 diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 24eb978..ece1336 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -492,7 +492,7 @@ void fdt_fixup_fman_firmware(void *blob) if (!p) return; - fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 0); + fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 16); if (!fmanfw) return; Applied to u-boot-mpc85xx/master, added sign-off-by line. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 8/8] mpc85xx: introduce the kmp204x reference design support
On Tue, 2013-08-20 at 12:40 -0700, York Sun wrote: On 08/20/2013 11:21 AM, Scott Wood wrote: On Tue, 2013-08-20 at 13:20 -0500, Scott Wood wrote: On Mon, 2013-08-19 at 18:02 -0700, York Sun wrote: On 08/19/2013 05:48 PM, Scott Wood wrote: On Mon, 2013-08-19 at 17:50 +0200, Valentin Longchamp wrote: On 08/13/2013 11:38 PM, Scott Wood wrote: On Fri, 2013-07-26 at 12:02 +0200, Valentin Longchamp wrote: snip + /* TLB 1 */ + /* *I*** - Covers boot page */ + /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff0, it covered the 0xf000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), What does that covers boot page comment refer to? Why is L3SRAM I+G? I have taken this from the corenet SYS_RAMBOOT boot scenario since it's also the way our board boots. York, can you answer this? I suspect the covers boot page comment is left over from before the recent spin table changes. Look at the context, this is used as SRAM with PBL boot method. Notice these macros in header file I'm not talking about the SRAM comment, but the covers boot page comment before it. I think this entry replaces the default TLB out of reset and it does cover the boot page 0xf000~0x. That's not what the comment appears to say (unless you read the word cover in a non-intuitive and ambiguous way). These comments generally talk about what the new TLB is, not what is being replaced. It is not unique to this platform. You can find many similar existing code. I know that. That's why I'm asking you to explain it rather than Valentin. :-) At the very least this mapping can't be *I*G and *I** at the same time. I agree the G bit shouldn't be set here. Usually I and G go together... +#define CONFIG_SYS_RAMBOOT +#define CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE and +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xfull | \ + CONFIG_RAMBOOT_TEXT_BASE) +#define CONFIG_SYS_L3_SIZE (1024 10) +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) ...and this doesn't cover the boot page. Also, can you answer the question about why the L3 SRAM mapping is cache-inhibited? I suspect this is the idea carried from early NAND boot implementation. You are mostly familiar with NAND and SPL boot, can you examine if we can turn on the cache for these cases? NAND SPL on some targets is so space constrained that adding a few instructions to turn cache on might go over the limit. :-) Are you talking about mapping the NAND buffer that we boot directly out of, or the L2SRAM that we sometimes load the SPL payload into? If the former, that is I+G because we proceed to use it for I/O after relocating out of it. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 8/8] mpc85xx: introduce the kmp204x reference design support
On 08/20/2013 12:47 PM, Scott Wood wrote: On Tue, 2013-08-20 at 12:40 -0700, York Sun wrote: On 08/20/2013 11:21 AM, Scott Wood wrote: On Tue, 2013-08-20 at 13:20 -0500, Scott Wood wrote: On Mon, 2013-08-19 at 18:02 -0700, York Sun wrote: On 08/19/2013 05:48 PM, Scott Wood wrote: On Mon, 2013-08-19 at 17:50 +0200, Valentin Longchamp wrote: On 08/13/2013 11:38 PM, Scott Wood wrote: On Fri, 2013-07-26 at 12:02 +0200, Valentin Longchamp wrote: snip + /* TLB 1 */ + /* *I*** - Covers boot page */ + /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff0, it covered the 0xf000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), What does that covers boot page comment refer to? Why is L3SRAM I+G? I have taken this from the corenet SYS_RAMBOOT boot scenario since it's also the way our board boots. York, can you answer this? I suspect the covers boot page comment is left over from before the recent spin table changes. Look at the context, this is used as SRAM with PBL boot method. Notice these macros in header file I'm not talking about the SRAM comment, but the covers boot page comment before it. I think this entry replaces the default TLB out of reset and it does cover the boot page 0xf000~0x. That's not what the comment appears to say (unless you read the word cover in a non-intuitive and ambiguous way). These comments generally talk about what the new TLB is, not what is being replaced. It is not unique to this platform. You can find many similar existing code. I know that. That's why I'm asking you to explain it rather than Valentin. :-) We have many developers around the globe so people understand cover differently. I interpret the cover here as this TLB translates the address space which includes the boot page. At the very least this mapping can't be *I*G and *I** at the same time. I agree the G bit shouldn't be set here. Usually I and G go together... The default TLB out of reset has I bit but not G bit. I have to admit that I don't remember when I used G bit intentionally. +#define CONFIG_SYS_RAMBOOT +#define CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE and +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xfull | \ + CONFIG_RAMBOOT_TEXT_BASE) +#define CONFIG_SYS_L3_SIZE (1024 10) +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) ...and this doesn't cover the boot page. Also, can you answer the question about why the L3 SRAM mapping is cache-inhibited? I suspect this is the idea carried from early NAND boot implementation. You are mostly familiar with NAND and SPL boot, can you examine if we can turn on the cache for these cases? NAND SPL on some targets is so space constrained that adding a few instructions to turn cache on might go over the limit. :-) Are you talking about mapping the NAND buffer that we boot directly out of, or the L2SRAM that we sometimes load the SPL payload into? If the former, that is I+G because we proceed to use it for I/O after relocating out of it. I am talking aout the latter one. For SPL cases, the code is copied to some type of volatile memory and the core boots from there. I am not sure if we can turn on cache for all cases. Probably yes. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 8/8] mpc85xx: introduce the kmp204x reference design support
On Tue, 2013-08-20 at 12:57 -0700, York Sun wrote: On 08/20/2013 12:47 PM, Scott Wood wrote: On Tue, 2013-08-20 at 12:40 -0700, York Sun wrote: On 08/20/2013 11:21 AM, Scott Wood wrote: On Tue, 2013-08-20 at 13:20 -0500, Scott Wood wrote: On Mon, 2013-08-19 at 18:02 -0700, York Sun wrote: On 08/19/2013 05:48 PM, Scott Wood wrote: On Mon, 2013-08-19 at 17:50 +0200, Valentin Longchamp wrote: On 08/13/2013 11:38 PM, Scott Wood wrote: On Fri, 2013-07-26 at 12:02 +0200, Valentin Longchamp wrote: snip + /* TLB 1 */ + /* *I*** - Covers boot page */ + /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the +* SRAM is at 0xfff0, it covered the 0xf000. +*/ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), What does that covers boot page comment refer to? Why is L3SRAM I+G? I have taken this from the corenet SYS_RAMBOOT boot scenario since it's also the way our board boots. York, can you answer this? I suspect the covers boot page comment is left over from before the recent spin table changes. Look at the context, this is used as SRAM with PBL boot method. Notice these macros in header file I'm not talking about the SRAM comment, but the covers boot page comment before it. I think this entry replaces the default TLB out of reset and it does cover the boot page 0xf000~0x. That's not what the comment appears to say (unless you read the word cover in a non-intuitive and ambiguous way). These comments generally talk about what the new TLB is, not what is being replaced. It is not unique to this platform. You can find many similar existing code. I know that. That's why I'm asking you to explain it rather than Valentin. :-) We have many developers around the globe so people understand cover differently. I interpret the cover here as this TLB translates the address space which includes the boot page. That's how I'd interpret it as well, but then the comment that this entry replaces... doesn't make sense. This entry is for L3SRAM which is 1 MiB at 0xf which is nowhere near the boot page. At the very least this mapping can't be *I*G and *I** at the same time. I agree the G bit shouldn't be set here. Usually I and G go together... The default TLB out of reset has I bit but not G bit. That entry would have already been replaced by asm code. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 1/2] exynos5250: Add arndale board support
On Tue, 6 Aug 2013 20:05:46 +0530
Chander Kashyap chander.kash...@linaro.org wrote:
Arndale board is based on samsung's exynos5250 soc.
Signed-off-by: Inderpal Singh inderpal.si...@linaro.org
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
---
This patchseries gives me:
make[1]: Entering directory
`/home/kim/git/u-boot-arndale-upstream/board/samsung/arndale'
arm-linux-gnueabihf-gcc -g -Os -ffunction-sections -fdata-sections
-fno-common -ffixed-r8 -msoft-float -D__KERNEL__
-DCONFIG_SYS_TEXT_BASE=0x43E0 -DCONFIG_SPL_TEXT_BASE=0x02023400
-DCONFIG_SPL_PAD_TO=0 -I/home/kim/git/u-boot-arndale-upstream/include
-fno-builtin -ffreestanding -nostdinc -isystem
/home/kim/toolchain/gcc-linaro-arm-linux-gnueabihf-4.8-2013.07-1_linux/bin/../lib/gcc/arm-linux-gnueabihf/4.8.2/include
-pipe -DCONFIG_ARM -D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux
-march=armv7-a -Wall -Wstrict-prototypes -fno-stack-protector
-Wno-format-nonliteral -Wno-format-security -fstack-usage -o arndale.o
arndale.c -c
arndale.c: In function ‘board_uart_init’:
arndale.c:74:11: error: ‘ret’ undeclared (first use in this function)
return ret;
^
arndale.c:74:11: note: each undeclared identifier is reported only once for
each function it appears in
arndale.c:78:1: warning: control reaches end of non-void function
[-Wreturn-type]
}
^
make[1]: *** [arndale.o] Error 1
make[1]: Leaving directory
`/home/kim/git/u-boot-arndale-upstream/board/samsung/arndale'
I manually fixed it with:
diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c
index 6d81b90..4e021c3 100644
--- a/board/samsung/arndale/arndale.c
+++ b/board/samsung/arndale/arndale.c
@@ -71,10 +71,10 @@ static int board_uart_init(void)
if (err) {
debug(UART%d not configured\n,
(uart_id - PERIPH_ID_UART0));
- return ret;
+ return err;
}
}
- return ret;
+ return err;
}
#ifdef CONFIG_BOARD_EARLY_INIT_F
btw, I noticed that misaligned parenthesis above, and asked checkpatch
if it did, and it did:
CHECK: Alignment should match open parenthesis
#73: FILE: samsung/arndale/arndale.c:73:
+ debug(UART%d not configured\n,
+ (uart_id - PERIPH_ID_UART0));
so it's obvious that you're not build-testing nor running checkpatch
between each patchseries version submission.
Even after fixing the above, I get:
arm-linux-gnueabihf-objcopy --gap-fill=0xff -O binary
/home/kim/git/u-boot-arndale-upstream/spl/u-boot-spl
/home/kim/git/u-boot-arndale-upstream/spl/u-boot-spl.bin
/home/kim/git/u-boot-arndale-upstream/tools/mkarndalespl \
/home/kim/git/u-boot-arndale-upstream/spl/u-boot-spl.bin
/home/kim/git/u-boot-arndale-upstream/spl/arndale-spl.bin
/bin/bash: line 1: /home/kim/git/u-boot-arndale-upstream/tools/mkarndalespl: No
such file or directory
make[1]: *** [/home/kim/git/u-boot-arndale-upstream/spl/arndale-spl.bin] Error
127
make[1]: Leaving directory `/home/kim/git/u-boot-arndale-upstream/spl'
make: *** [spl/u-boot-spl.bin] Error 2
this is v6 of the patchseries - could you *please* establish a decent
test regimen prior to your patch submissions?
Thanks,
Kim
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 7/7] imx: add status reporting for HAB status
Hi,
Am 12.08.13 16:39, schrieb Stefano Babic:
+
+bool is_hab_enabled(void)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = ocotp-bank[0];
+ struct fuse_bank0_regs *fuse =
+ (struct fuse_bank0_regs *)bank-fuse_regs;
+ uint32_t reg = readl(fuse-cfg5);
+
+ return (reg 0x2) == 0x2;
+}
With the exception of that function and the required structure
definitions, the whole code also works with i.MX53 (tested with LOCO
board), too. Also AN4581 [1] that describes HAB doesn't differentiate
between i.MX53 and i.MX6 in that case as they both use HAB v4.
I think you have more experience how to organize the code (I added a few
symlinks and modified only the Makefile, but I guess that symlink are
not the best solution).
Regards,
Bernhard
[1] http://cache.freescale.com/files/32bit/doc/app_note/AN4581.pdf
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 8/8] mpc85xx: introduce the kmp204x reference design support
On 08/20/2013 01:03 PM, Scott Wood wrote: On Tue, 2013-08-20 at 12:57 -0700, York Sun wrote: On 08/20/2013 12:47 PM, Scott Wood wrote: On Tue, 2013-08-20 at 12:40 -0700, York Sun wrote: On 08/20/2013 11:21 AM, Scott Wood wrote: On Tue, 2013-08-20 at 13:20 -0500, Scott Wood wrote: On Mon, 2013-08-19 at 18:02 -0700, York Sun wrote: On 08/19/2013 05:48 PM, Scott Wood wrote: On Mon, 2013-08-19 at 17:50 +0200, Valentin Longchamp wrote: On 08/13/2013 11:38 PM, Scott Wood wrote: On Fri, 2013-07-26 at 12:02 +0200, Valentin Longchamp wrote: snip + /* TLB 1 */ + /* *I*** - Covers boot page */ + /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the +* SRAM is at 0xfff0, it covered the 0xf000. +*/ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), What does that covers boot page comment refer to? Why is L3SRAM I+G? I have taken this from the corenet SYS_RAMBOOT boot scenario since it's also the way our board boots. York, can you answer this? I suspect the covers boot page comment is left over from before the recent spin table changes. Look at the context, this is used as SRAM with PBL boot method. Notice these macros in header file I'm not talking about the SRAM comment, but the covers boot page comment before it. I think this entry replaces the default TLB out of reset and it does cover the boot page 0xf000~0x. That's not what the comment appears to say (unless you read the word cover in a non-intuitive and ambiguous way). These comments generally talk about what the new TLB is, not what is being replaced. It is not unique to this platform. You can find many similar existing code. I know that. That's why I'm asking you to explain it rather than Valentin. :-) We have many developers around the globe so people understand cover differently. I interpret the cover here as this TLB translates the address space which includes the boot page. That's how I'd interpret it as well, but then the comment that this entry replaces... doesn't make sense. The default TLB is TLB1 entry 0. This is the same TLB. Along the booting process, we switch to AS=1 and replace the default TLB with this one, then switch back. That's why I said replace. I am sure you are very familiar with this process. This entry is for L3SRAM which is 1 MiB at 0xf which is nowhere near the boot page. It maps from CONFIG_SYS_INIT_L3_ADDR ( == CONFIG_RAMBOOT_TEXT_BASE == CONFIG_SYS_TEXT_BASE == 0xfff8) to CONFIG_SYS_INIT_L3_ADDR_PHYS ( == 0xfull | CONFIG_RAMBOOT_TEXT_BASE). At the very least this mapping can't be *I*G and *I** at the same time. I agree the G bit shouldn't be set here. Usually I and G go together... The default TLB out of reset has I bit but not G bit. That entry would have already been replaced by asm code. No argument here. I was pointing out one case I and G don't go together. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] should print_mmc_devices() not add an extraneous blank between devices?
playing on my beaglebone black and:
U-Boot# mmc list
OMAP SD/MMC: 0
OMAP SD/MMC: 1 -- ???
U-Boot#
puzzled as to why the second line is indented, and discovered, first
from cmd_mmc.c:
print_mmc_devices('\n');
which reasonably defines a newline as a separator, but then there's
this in drivers/mmc/mmc.c:
list_for_each(entry, mmc_devices) {
m = list_entry(entry, struct mmc, link);
printf(%s: %d, m-name, m-block_dev.dev);
if (entry-next != mmc_devices)
printf(%c , separator);
}
where that loop inserts the separator *and* a blank. is that
deliberate? it just looks weird.
rday
--
Robert P. J. Day Ottawa, Ontario, CANADA
http://crashcourse.ca
Twitter: http://twitter.com/rpjday
LinkedIn: http://ca.linkedin.com/in/rpjday
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/mpc85xx: Add workaround for erratum A-005125
In a very rare condition, a system hang is possible when the e500 core initiates a guarded load to PCI / PCIe /SRIO performs a coherent write to memory. Please refer to errata document for more details. This erratum applies to the following SoCs and their variants, if any. BSC9132 BSC9131 MPC8536 MPC8544 MPC8548 MPC8569 MPC8572 P1010 P1020 P1021 P1022 P1023 P2020 C29x Signed-off-by: York Sun york...@freescale.com CC: Scott Wood scottw...@freescale.com --- arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 +++ arch/powerpc/cpu/mpc85xx/start.S |8 arch/powerpc/include/asm/config_mpc85xx.h | 21 + 3 files changed, 32 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 8a2a3ee..b98a7cb 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -252,6 +252,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 puts(Work-around for Erratum A-005812 enabled\n); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005125 + puts(Work-around for Erratum A005125 enabled\n); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index ad57a9c..be4f4ae 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -108,6 +108,14 @@ _start_e500: isync 2: #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005125 + msync + isync + mfspr r3, SPRN_HDBCR0 + orisr3, r3, 0x0080 + mtspr SPRN_HDBCR0, r3 +#endif + #if defined(CONFIG_SECURE_BOOT) defined(CONFIG_E500MC) /* ISBC uses L2 as stack. diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index d748cb6..6fdade2 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -34,6 +34,7 @@ #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70 +#define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_MPC8540) #define CONFIG_MAX_CPUS1 @@ -52,6 +53,7 @@ #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70 +#define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_MPC8548) #define CONFIG_MAX_CPUS1 @@ -67,6 +69,7 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_MPC8555) #define CONFIG_MAX_CPUS1 @@ -106,6 +109,7 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_MPC8572) #define CONFIG_MAX_CPUS2 @@ -115,6 +119,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 +#define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1010) #define CONFIG_MAX_CPUS1 @@ -133,6 +138,7 @@ #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 +#define CONFIG_SYS_FSL_ERRATUM_A005125 /* P1011 is single core version of P1020 */ #elif defined(CONFIG_P1011) @@ -145,6 +151,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A005125 /* P1012 is single core version of P1021 */ #elif defined(CONFIG_P1012) @@ -160,6 +167,7 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_ERRATUM_A005125 /* P1013 is single core version of P1022 */ #elif defined(CONFIG_P1013) @@ -172,6 +180,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 +#define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1014) #define CONFIG_MAX_CPUS1 @@ -201,6 +210,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x1 #define CONFIG_SYS_FSL_PCIE_COMPAT fsl,qoriq-pcie-v2.2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff60 +#define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1020) #define CONFIG_MAX_CPUS2 @@ -212,6 +222,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1021) #define CONFIG_MAX_CPUS2 @@ -226,6 +237,7 @@ #define
Re: [U-Boot] [RFC PATCH 1/1] powerpc/embedded6xx: Add support for Motorola/Emerson MVME5100.
On Tue, 2013-08-20 at 13:26 -0700, York Sun wrote: On 08/20/2013 01:03 PM, Scott Wood wrote: On Tue, 2013-08-20 at 12:57 -0700, York Sun wrote: On 08/20/2013 12:47 PM, Scott Wood wrote: On Tue, 2013-08-20 at 12:40 -0700, York Sun wrote: On 08/20/2013 11:21 AM, Scott Wood wrote: On Tue, 2013-08-20 at 13:20 -0500, Scott Wood wrote: On Mon, 2013-08-19 at 18:02 -0700, York Sun wrote: On 08/19/2013 05:48 PM, Scott Wood wrote: On Mon, 2013-08-19 at 17:50 +0200, Valentin Longchamp wrote: On 08/13/2013 11:38 PM, Scott Wood wrote: On Fri, 2013-07-26 at 12:02 +0200, Valentin Longchamp wrote: snip + /* TLB 1 */ + /* *I*** - Covers boot page */ + /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff0, it covered the 0xf000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), What does that covers boot page comment refer to? Why is L3SRAM I+G? I have taken this from the corenet SYS_RAMBOOT boot scenario since it's also the way our board boots. York, can you answer this? I suspect the covers boot page comment is left over from before the recent spin table changes. Look at the context, this is used as SRAM with PBL boot method. Notice these macros in header file I'm not talking about the SRAM comment, but the covers boot page comment before it. I think this entry replaces the default TLB out of reset and it does cover the boot page 0xf000~0x. That's not what the comment appears to say (unless you read the word cover in a non-intuitive and ambiguous way). These comments generally talk about what the new TLB is, not what is being replaced. It is not unique to this platform. You can find many similar existing code. I know that. That's why I'm asking you to explain it rather than Valentin. :-) We have many developers around the globe so people understand cover differently. I interpret the cover here as this TLB translates the address space which includes the boot page. That's how I'd interpret it as well, but then the comment that this entry replaces... doesn't make sense. The default TLB is TLB1 entry 0. This is the same TLB. It's the same ESEL, but the entry itself should have been cleared by now (see Clear out any other TLB entries... in arch/powerpc/cpu/mpc85xx/start.S). In any case, the entry that we're describing in the comments should be the new entry which does not cover the boot page. We're no longer using the boot page at this point (on the boot core). -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] usb: gadget: Fix data aborts during USB ethernet boot
As seen on GCC 4.6 Linaro compiler, control_req buffer is not aligned
on 4 byte boundaray causing data aborts in eth_setup - conf_buf
during dhcp boot over usb_ether. Fix the issue my aligning control_req
buffer to 4-byte boundary.
Tested on am335x_evm platform (beaglebone).
Applies on 2013.10-rc1 branch.
Cc: Tom Rini tr...@ti.com
Signed-off-by: Joel Fernandes jo...@ti.com
---
drivers/usb/gadget/ether.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index 579893c..251d7b2 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -849,7 +849,7 @@ static struct usb_gadget_stringsstringtab = {
};
/**/
-static u8 control_req[USB_BUFSIZ];
+static u8 control_req[USB_BUFSIZ] __attribute__ ((aligned(4)));
#if defined(CONFIG_USB_ETH_CDC) || defined(CONFIG_USB_ETH_RNDIS)
static u8 status_req[STATUS_BYTECOUNT] __attribute__ ((aligned(4)));
#endif
--
1.7.9.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 1/2] exynos5250: Add arndale board support
Dear Kim,
On 21 August 2013 00:54, Kim Phillips kim.phill...@linaro.org wrote:
On Tue, 6 Aug 2013 20:05:46 +0530
Chander Kashyap chander.kash...@linaro.org wrote:
Arndale board is based on samsung's exynos5250 soc.
Signed-off-by: Inderpal Singh inderpal.si...@linaro.org
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
---
This patchseries gives me:
make[1]: Entering directory
`/home/kim/git/u-boot-arndale-upstream/board/samsung/arndale'
arm-linux-gnueabihf-gcc -g -Os -ffunction-sections -fdata-sections
-fno-common -ffixed-r8 -msoft-float -D__KERNEL__
-DCONFIG_SYS_TEXT_BASE=0x43E0 -DCONFIG_SPL_TEXT_BASE=0x02023400
-DCONFIG_SPL_PAD_TO=0 -I/home/kim/git/u-boot-arndale-upstream/include
-fno-builtin -ffreestanding -nostdinc -isystem
/home/kim/toolchain/gcc-linaro-arm-linux-gnueabihf-4.8-2013.07-1_linux/bin/../lib/gcc/arm-linux-gnueabihf/4.8.2/include
-pipe -DCONFIG_ARM -D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux
-march=armv7-a -Wall -Wstrict-prototypes -fno-stack-protector
-Wno-format-nonliteral -Wno-format-security -fstack-usage -o arndale.o
arndale.c -c
arndale.c: In function ‘board_uart_init’:
arndale.c:74:11: error: ‘ret’ undeclared (first use in this function)
return ret;
^
arndale.c:74:11: note: each undeclared identifier is reported only once for
each function it appears in
arndale.c:78:1: warning: control reaches end of non-void function
[-Wreturn-type]
}
^
make[1]: *** [arndale.o] Error 1
make[1]: Leaving directory
`/home/kim/git/u-boot-arndale-upstream/board/samsung/arndale'
I manually fixed it with:
diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c
index 6d81b90..4e021c3 100644
--- a/board/samsung/arndale/arndale.c
+++ b/board/samsung/arndale/arndale.c
@@ -71,10 +71,10 @@ static int board_uart_init(void)
if (err) {
debug(UART%d not configured\n,
(uart_id - PERIPH_ID_UART0));
- return ret;
+ return err;
}
}
- return ret;
+ return err;
}
#ifdef CONFIG_BOARD_EARLY_INIT_F
btw, I noticed that misaligned parenthesis above, and asked checkpatch
if it did, and it did:
CHECK: Alignment should match open parenthesis
#73: FILE: samsung/arndale/arndale.c:73:
+ debug(UART%d not configured\n,
+ (uart_id - PERIPH_ID_UART0));
so it's obvious that you're not build-testing nor running checkpatch
between each patchseries version submission.
Even after fixing the above, I get:
arm-linux-gnueabihf-objcopy --gap-fill=0xff -O binary
/home/kim/git/u-boot-arndale-upstream/spl/u-boot-spl
/home/kim/git/u-boot-arndale-upstream/spl/u-boot-spl.bin
/home/kim/git/u-boot-arndale-upstream/tools/mkarndalespl \
/home/kim/git/u-boot-arndale-upstream/spl/u-boot-spl.bin
/home/kim/git/u-boot-arndale-upstream/spl/arndale-spl.bin
/bin/bash: line 1: /home/kim/git/u-boot-arndale-upstream/tools/mkarndalespl:
No such file or directory
make[1]: *** [/home/kim/git/u-boot-arndale-upstream/spl/arndale-spl.bin]
Error 127
make[1]: Leaving directory `/home/kim/git/u-boot-arndale-upstream/spl'
make: *** [spl/u-boot-spl.bin] Error 2
this is v6 of the patchseries - could you *please* establish a decent
test regimen prior to your patch submissions?
Thanks for pointing out.
Sorry for the all the mess. I will fix all the issues properly and resend it.
Thanks,
Kim
--
with warm regards,
Chander Kashyap
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 1/2] exynos5250: Add arndale board support
On 21 August 2013 08:56, Chander Kashyap chander.kash...@linaro.org wrote:
Dear Kim,
On 21 August 2013 00:54, Kim Phillips kim.phill...@linaro.org wrote:
On Tue, 6 Aug 2013 20:05:46 +0530
Chander Kashyap chander.kash...@linaro.org wrote:
Arndale board is based on samsung's exynos5250 soc.
Signed-off-by: Inderpal Singh inderpal.si...@linaro.org
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
---
This patchseries gives me:
make[1]: Entering directory
`/home/kim/git/u-boot-arndale-upstream/board/samsung/arndale'
arm-linux-gnueabihf-gcc -g -Os -ffunction-sections -fdata-sections
-fno-common -ffixed-r8 -msoft-float -D__KERNEL__
-DCONFIG_SYS_TEXT_BASE=0x43E0 -DCONFIG_SPL_TEXT_BASE=0x02023400
-DCONFIG_SPL_PAD_TO=0 -I/home/kim/git/u-boot-arndale-upstream/include
-fno-builtin -ffreestanding -nostdinc -isystem
/home/kim/toolchain/gcc-linaro-arm-linux-gnueabihf-4.8-2013.07-1_linux/bin/../lib/gcc/arm-linux-gnueabihf/4.8.2/include
-pipe -DCONFIG_ARM -D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux
-march=armv7-a -Wall -Wstrict-prototypes -fno-stack-protector
-Wno-format-nonliteral -Wno-format-security -fstack-usage -o arndale.o
arndale.c -c
arndale.c: In function ‘board_uart_init’:
arndale.c:74:11: error: ‘ret’ undeclared (first use in this function)
return ret;
^
arndale.c:74:11: note: each undeclared identifier is reported only once for
each function it appears in
arndale.c:78:1: warning: control reaches end of non-void function
[-Wreturn-type]
}
^
make[1]: *** [arndale.o] Error 1
make[1]: Leaving directory
`/home/kim/git/u-boot-arndale-upstream/board/samsung/arndale'
I manually fixed it with:
diff --git a/board/samsung/arndale/arndale.c
b/board/samsung/arndale/arndale.c
index 6d81b90..4e021c3 100644
--- a/board/samsung/arndale/arndale.c
+++ b/board/samsung/arndale/arndale.c
@@ -71,10 +71,10 @@ static int board_uart_init(void)
if (err) {
debug(UART%d not configured\n,
(uart_id - PERIPH_ID_UART0));
- return ret;
+ return err;
}
}
- return ret;
+ return err;
}
#ifdef CONFIG_BOARD_EARLY_INIT_F
btw, I noticed that misaligned parenthesis above, and asked checkpatch
if it did, and it did:
CHECK: Alignment should match open parenthesis
#73: FILE: samsung/arndale/arndale.c:73:
+ debug(UART%d not configured\n,
+ (uart_id - PERIPH_ID_UART0));
so it's obvious that you're not build-testing nor running checkpatch
between each patchseries version submission.
Even after fixing the above, I get:
arm-linux-gnueabihf-objcopy --gap-fill=0xff -O binary
/home/kim/git/u-boot-arndale-upstream/spl/u-boot-spl
/home/kim/git/u-boot-arndale-upstream/spl/u-boot-spl.bin
/home/kim/git/u-boot-arndale-upstream/tools/mkarndalespl \
/home/kim/git/u-boot-arndale-upstream/spl/u-boot-spl.bin
/home/kim/git/u-boot-arndale-upstream/spl/arndale-spl.bin
/bin/bash: line 1: /home/kim/git/u-boot-arndale-upstream/tools/mkarndalespl:
No such file or directory
make[1]: *** [/home/kim/git/u-boot-arndale-upstream/spl/arndale-spl.bin]
Error 127
make[1]: Leaving directory `/home/kim/git/u-boot-arndale-upstream/spl'
make: *** [spl/u-boot-spl.bin] Error 2
This patch depends on
CONFIG: EXYNOS5: Replace misnomer SMDK5250 with EXYNOS5250 and update Makefiles
http://u-boot.10912.n7.nabble.com/PATCH-v2-CONFIG-EXYNOS5-Replace-misnomer-SMDK5250-with-EXYNOS5250-and-update-Makefiles-td160016.html
Kindly apply this patch before compiling for arndale.
this is v6 of the patchseries - could you *please* establish a decent
test regimen prior to your patch submissions?
Thanks for pointing out.
Sorry for the all the mess. I will fix all the issues properly and resend it.
Thanks,
Kim
--
with warm regards,
Chander Kashyap
--
with warm regards,
Chander Kashyap
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] usb:dfu:g_dnl: Change number of exported configurations at composite gadget
Dear Egli, Samuel, Hi Lukasz, -Original Message- From: Lukasz Majewski [mailto:l.majew...@samsung.com] Sent: Montag, 19. August 2013 17:17 To: u-boot@lists.denx.de Cc: Lukasz Majewski; Heiko Schocher; Tormod Volden; Lukasz Majewski; Marek Vasut; Egli, Samuel Subject: [PATCH 1/2] usb:dfu:g_dnl: Change number of exported configurations at composite gadget USB composite gadget (g_dnl) supports only one configuration. Due to that the corresponding field - bConfigurationValue has been changed. Moreover more descriptive names were chosen for relevant fields. Windows XP setup: - Thesyscon USB Descriptor Dumper - zadig_xp program for WinUSB installation (which is required by dfu- util) - dfu-util for windows (version 0.6) - TRATS target connected via USB hub to test Win XP machine. Tested at: Trats - Exynos4210 I applied both patches and tested download from windows 7 with dfu-util 0.7 and it worked all fine. Thanks! Will it also work with my playstation and/or other game loaders ? (lol) Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] usb: new board-specific USB init interface
Dear Mateusz Zalega, This commit unifies board-specific USB initialization implementations under one symbol (usb_board_init), declaration of which is available in usb.h. --- Changes since RFC: - NVIDIA Tegra doesn't postpone its USB init anymore - board_usb_init()'s sole argument name was shortened - networking code comment style (/* blurb...) dropped - squashed RFC changes so that patch won't break bisect Signed-off-by: Mateusz Zalega m.zal...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com Reviewed-by: Lukasz Majewski l.majew...@samsung.com Cc: Minkyu Kang mk7.k...@samsung.com Cc: Marek Vasut ma...@denx.de Cc: Tom Warren twar...@nvidia.com Cc: Albert Aribaud albert.u.b...@aribaud.net --- arch/arm/include/asm/arch-tegra/usb.h | 3 +-- board/amcc/canyonlands/canyonlands.c | 5 +++-- board/balloon3/balloon3.c | 5 +++-- board/esd/apc405/apc405.c | 5 +++-- board/esd/pmc440/pmc440.c | 5 +++-- board/icpdas/lp8x4x/lp8x4x.c | 5 +++-- board/nvidia/common/board.c | 4 +++- board/samsung/trats/trats.c | 5 +++-- board/toradex/colibri_pxa270/colibri_pxa270.c | 5 +++-- board/trizepsiv/conxs.c | 5 +++-- board/vpac270/vpac270.c | 5 +++-- common/cmd_dfu.c | 5 ++--- common/cmd_usb_mass_storage.c | 3 ++- common/usb.c | 5 + drivers/usb/host/ehci-omap.c | 8 +--- drivers/usb/host/ehci-tegra.c | 2 +- drivers/usb/host/ohci-hcd.c | 4 ++-- drivers/usb/host/ohci.h | 12 +--- include/g_dnl.h | 2 -- include/usb.h | 19 ++- include/usb_mass_storage.h| 12 +--- 21 files changed, 72 insertions(+), 52 deletions(-) The EHCI supports multi-bus thing (passing the controller *), will this be viable to pass in this case too, so the busses can be inited selectively in host/gadget functions? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: DRA: EMIF: Change DDR3 settings to use hw leveling
Hi Tom, On Wednesday 21 August 2013 01:08 AM, Tom Rini wrote: On Tue, Aug 20, 2013 at 06:47:36PM +0530, Sricharan R wrote: Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using software leveling. This was done since hardware leveling was not working. Now that the right sequence to do hw leveling is identified, use it. This is required for EMIF clockdomain to idle and come back during lowpower usecases. [snip] #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS OK, so this reminds me, should we be printing out something more now then, when we're calculating timings, rather than using precalculated ones? Or is that a different issue I'm thinking of? This is not something to do with precalculated timings or auto config. This patch is specific only to DDR3 memory and EMIF supports auto leveling feature for DDR3. This feature was disabled for DRA7 till now, but this patch enables that. Regards, Sricharan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v9 2/2] console: usb: kbd: To improve TFTP booting performance
Dear Jim Lin, TFTP booting is slow when a USB keyboard is installed and stdin has usbkbd added. This fix is to change Ctrl-C polling for USB keyboard to every second when NET transfer is running. Signed-off-by: Jim Lin ji...@nvidia.com --- Changes in v2: 1. Change configuration name from CONFIG_CTRLC_POLL_MS to CONFIG_CTRLC_POLL_S. 2. New code will be executed only when CONFIG_CTRLC_POLL_S is defined in configuration header file. 3. Add description in README.console. Changes in v3: 1. Move changes to common/usb_kbd.c and doc/README.usb 2. Rename config setting to CONFIG_USBKB_TESTC_PERIOD. 3. Remove slow response on USB-keyboard input when TFTP boot is not running. Changes in v4: 1. Remove changes in doc/README.usb, common/usb_kbd.c and CONFIG_USBKB_TESTC_PERIOD 2. Modify net/net.c Changes in v5: 1. Change variable name to ctrlc_t_start. 2. Use two calls of get_timer(0) to get time gap. Changes in v6: 1. In common/usb_kbd.c, check net_busy_flag to determine whether we poll USB keyboard status. 2. In include/usb.h, add external variable declaration net_busy_flag Changes in v7: 1. In common/usb_kbd.c and include/usb.h, add #ifdef CONFIG_CMD_NET. 2. In common/usb_kbd.c, modify code to get correct time gap. Changes in v8: 1. Add __maybe_unused for variable kbd_testc_tms. Changes in v9: 1. Move external variable declaration from include/usb.h to common/usb_kbd.c common/usb_kbd.c | 15 +++ 1 files changed, 15 insertions(+), 0 deletions(-) Applied, thanks. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v9 1/2] NET: Add net_busy_flag if CONFIG_USB_KEYBOARD is defined
Dear Jim Lin, This flag is to make console aware that NET transfer is running or not. Signed-off-by: Jim Lin ji...@nvidia.com --- Changes in v2: 1. Change configuration name from CONFIG_CTRLC_POLL_MS to CONFIG_CTRLC_POLL_S. 2. New code will be executed only when CONFIG_CTRLC_POLL_S is defined in configuration header file. 3. Add description in README.console. Changes in v3: 1. Move changes to common/usb_kbd.c and doc/README.usb 2. Rename config setting to CONFIG_USBKB_TESTC_PERIOD. 3. Remove slow response on USB-keyboard input when TFTP boot is not running. Changes in v4: 1. Remove changes in doc/README.usb, common/usb_kbd.c and CONFIG_USBKB_TESTC_PERIOD 2. Modify net/net.c Changes in v5: 1. Change variable name to ctrlc_t_start. 2. Use two calls of get_timer(0) to get time gap. Changes in v6: 1. In common/usb_kbd.c, check net_busy_flag to determine whether we poll USB keyboard status. 2. In include/usb.h, add external variable declaration net_busy_flag Changes in v7: 1. Add CONFIG_USB_KEYBOARD Changes in v8: 1. net/net.c, add __maybe_unused for variable net_busy_flag. Changes in v9: None net/net.c | 11 +++ 1 files changed, 11 insertions(+), 0 deletions(-) Applied, thanks. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] config.mk: Add -Wundef to CFLAGS
Hello, Albert and U-Boot developers. The current status of this patch is Changes Requested. I love -Wundef option to be in, but it looks like difficult for me to post the version 2. The first choice to meet Albert's requirement is Therefore I ask: - that this patch be submitted along fixes to build failures it causes, as a proper patch series, by a single individual, Sorry, I cannot do this because: I am not familiar with architectures other than ARM. I understand only a few devices. To fix warnings in a correct way, a close look is often needed, but I cannot cover the whole code in the U-Boot tree. If possible, could anyone take over this task? The other option is collected by someone in an officially created git repo or branch; OK, I can do this. But I am not sure this will go well. Even if I create a new repo u-boot-wundef, how many people will pay attention to this repository? Most of users/developers track upstream repos where -Wundef warnings are never displayed. This means no one will have the motivation to fix the warnings. If this patch is desired, in which way should we continue? Comments are welcome. Best Regards, Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch v7 0/2] Add Arndale board support
The Arndale board is based on samsung's exynos5250 SOC. For spl generation, it depends on the patch at [5]. First patch provides the basic arndale board support. The second patch adds the MMC support. Changes in v2: - split from earlier patchset at [3] as per Minkyu - Removed checkpatch errors pointed out by Wolfgang - rebased to latest u-boot-samsung master branch - created mmc_boot.c to remove dependency on consolidation patch at [4] - split the mmc support to new patch as it depends on [2] [1] http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/162883 [2] http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/159887 [3] http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/157101 [4] http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/156272 Changes in v3: - Used dt based serial - rebased to latest u-boot-samsung master branch Changes in v4: - Removed the config dependency on exynos5_dt.h as it contains smdk5250 configurations rather than the common exynos5 generic configurations. - rebased to latest u-boot-samsung master branch Changes in v5: - Fix comments suggested by Minkyu - Added SPDX-License-Identifier to new files Changes in v6: - Fixed missed out sorting of Maintainers entry Changes in v7: - Fixed regression caused due to v6. - rebased to latest u-boot-samsung master branch - Fixed checkpatch warning for parenthesis alignment. [5] [PATCH v2] CONFIG: EXYNOS5: Replace misnomer SMDK5250 with EXYNOS5250 and update Makefiles Chander Kashyap (1): exynos5250: Add arndale board support Inderpal Singh (1): exynos5250: arndale: Add mmc support MAINTAINERS |4 + board/samsung/arndale/Makefile | 34 board/samsung/arndale/arndale.c | 101 board/samsung/arndale/arndale_spl.c | 50 ++ board/samsung/dts/exynos5250-arndale.dts | 39 + boards.cfg |1 + include/configs/arndale.h| 255 ++ 7 files changed, 484 insertions(+) create mode 100644 board/samsung/arndale/Makefile create mode 100644 board/samsung/arndale/arndale.c create mode 100644 board/samsung/arndale/arndale_spl.c create mode 100644 board/samsung/dts/exynos5250-arndale.dts create mode 100644 include/configs/arndale.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch v7 1/2] exynos5250: Add arndale board support
Arndale board is based on samsung's exynos5250 soc.
Signed-off-by: Inderpal Singh inderpal.si...@linaro.org
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
---
MAINTAINERS |4 +
board/samsung/arndale/Makefile | 34
board/samsung/arndale/arndale.c | 87 ++
board/samsung/arndale/arndale_spl.c | 50 ++
board/samsung/dts/exynos5250-arndale.dts | 21 +++
boards.cfg |1 +
include/configs/arndale.h| 255 ++
7 files changed, 452 insertions(+)
create mode 100644 board/samsung/arndale/Makefile
create mode 100644 board/samsung/arndale/arndale.c
create mode 100644 board/samsung/arndale/arndale_spl.c
create mode 100644 board/samsung/dts/exynos5250-arndale.dts
create mode 100644 include/configs/arndale.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 081cf96..f937761 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -464,6 +464,10 @@ Andre Schwarz andre.schw...@matrix-vision.de
mvblm7 MPC8343
mvsmr MPC5200
+Inderpal Singh inderpal.si...@linaro.org
+
+ Arndale ARM ARMV7 (EXYNOS5250 SoC)
+
Jon Smirl jonsm...@gmail.com
pcm030 MPC5200
diff --git a/board/samsung/arndale/Makefile b/board/samsung/arndale/Makefile
new file mode 100644
index 000..afd8db3
--- /dev/null
+++ b/board/samsung/arndale/Makefile
@@ -0,0 +1,34 @@
+#
+# Copyright (C) 2013 Samsung Electronics
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS += arndale_spl.o
+
+ifndef CONFIG_SPL_BUILD
+COBJS += arndale.o
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+ALL:= $(obj).depend $(LIB)
+
+all: $(ALL)
+
+$(LIB):$(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c
new file mode 100644
index 000..84d8f19
--- /dev/null
+++ b/board/samsung/arndale/arndale.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/pinmux.h
+#include asm/arch/power.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ gd-bd-bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+ return 0;
+}
+
+int dram_init(void)
+{
+ int i;
+ u32 addr;
+
+ for (i = 0; i CONFIG_NR_DRAM_BANKS; i++) {
+ addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ gd-ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+ }
+ return 0;
+}
+
+int power_init_board(void)
+{
+ set_ps_hold_ctrl();
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ int i;
+ u32 addr, size;
+
+ for (i = 0; i CONFIG_NR_DRAM_BANKS; i++) {
+ addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+
+ gd-bd-bi_dram[i].start = addr;
+ gd-bd-bi_dram[i].size = size;
+ }
+}
+
+static int board_uart_init(void)
+{
+ int err = 0, uart_id;
+
+ for (uart_id = PERIPH_ID_UART0; uart_id = PERIPH_ID_UART3; uart_id++) {
+ err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
+ if (err) {
+ debug(UART%d not configured\n,
+ (uart_id - PERIPH_ID_UART0));
+ return err;
+ }
+ }
+ return err;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ int err;
+
+ err = board_uart_init();
+ if (err) {
+ debug(UART init failed\n);
+ return err;
+ }
+ return err;
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ printf(\nBoard: Arndale\n);
+
+ return 0;
+}
+#endif
diff --git a/board/samsung/arndale/arndale_spl.c
b/board/samsung/arndale/arndale_spl.c
new file mode 100644
index 000..2949c08
--- /dev/null
+++ b/board/samsung/arndale/arndale_spl.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/spl.h
+
+#define SIGNATURE 0xdeadbeef
+
+/* Parameters of early board initialization in SPL */
+static struct spl_machine_param machine_param
+ __attribute__((section(.machine_param))) = {
+ .signature = SIGNATURE,
+ .version= 1,
+ .params = vmubfasirM,
+ .size = sizeof(machine_param),
+
+ .mem_iv_size= 0x1f,
+ .mem_type
[U-Boot] [Patch v7 2/2] exynos5250: arndale: Add mmc support
From: Inderpal Singh inderpal.si...@linaro.org
This patch adds mmc support to the arndale board.
Signed-off-by: Inderpal Singh inderpal.si...@linaro.org
---
board/samsung/arndale/arndale.c | 14 ++
board/samsung/dts/exynos5250-arndale.dts | 18 ++
2 files changed, 32 insertions(+)
diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c
index 84d8f19..052fecd 100644
--- a/board/samsung/arndale/arndale.c
+++ b/board/samsung/arndale/arndale.c
@@ -6,6 +6,7 @@
#include common.h
#include asm/arch/pinmux.h
+#include asm/arch/dwmmc.h
#include asm/arch/power.h
DECLARE_GLOBAL_DATA_PTR;
@@ -48,6 +49,19 @@ void dram_init_banksize(void)
}
}
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+ /* dwmmc initializattion for available channels */
+ ret = exynos_dwmmc_init(gd-fdt_blob);
+ if (ret)
+ debug(dwmmc init failed\n);
+
+ return ret;
+}
+#endif
+
static int board_uart_init(void)
{
int err = 0, uart_id;
diff --git a/board/samsung/dts/exynos5250-arndale.dts
b/board/samsung/dts/exynos5250-arndale.dts
index d3c0527..c700e45 100644
--- a/board/samsung/dts/exynos5250-arndale.dts
+++ b/board/samsung/dts/exynos5250-arndale.dts
@@ -18,4 +18,22 @@
serial0 = /serial@12C2;
console = /serial@12C2;
};
+
+ mmc@1220 {
+ samsung,bus-width = 8;
+ samsung,timing = 1 3 3;
+ };
+
+ mmc@1221 {
+ status = disabled;
+ };
+
+ mmc@1222 {
+ samsung,bus-width = 4;
+ samsung,timing = 1 2 3;
+ };
+
+ mmc@1223 {
+ status = disabled;
+ };
};
--
1.7.9.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 03/12] omap5: Expand CONFIG_SPL_MAX_SIZE and comment upon SRAM_SCRATCH_SPACE_ADDR
Hi Tom,
On Tuesday 20 August 2013 06:23 PM, Tom Rini wrote:
After examining both TRMs and doing some experimentation, we can rely on
using the start of the download area for CONFIG_SPL_TEXT_BASE and then
move SRAM_SCRATCH_SPACE_ADDR up, just like am335x. This is required for
peripheral boot modes such as UART.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/include/asm/arch-omap5/omap.h | 11 ++-
include/configs/omap5_common.h |4 ++--
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h
b/arch/arm/include/asm/arch-omap5/omap.h
index 597c692..e9a51d3 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -153,6 +153,15 @@ struct s32ktimer {
#define EFUSE_4 0x45145100
#endif /* __ASSEMBLY__ */
+/*
+ * In all cases, the TRM defines the RAM Memory Map for the processor
+ * and indicates the area for the downloaded image. We use all of that
+ * space for download and once up and running may use other parts of the
+ * map for our needs. We set a scratch space that is at the end of the
+ * OMAP5 download area, but within the DRA7xx download area (as it is
+ * much larger) and do not, at this time, make use of the additional
+ * space.
+ */
#ifdef CONFIG_DRA7XX
#define NON_SECURE_SRAM_START0x4030
#define NON_SECURE_SRAM_END 0x4038 /* Not inclusive */
@@ -160,7 +169,7 @@ struct s32ktimer {
#define NON_SECURE_SRAM_START0x4030
#define NON_SECURE_SRAM_END 0x4032 /* Not inclusive */
#endif
-#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
+#define SRAM_SCRATCH_SPACE_ADDR 0x4031E000
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4031F000
diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h
index 8e82fed..0345c57 100644
--- a/include/configs/omap5_common.h
+++ b/include/configs/omap5_common.h
@@ -128,8 +128,8 @@
/* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE 0x40300350
-#define CONFIG_SPL_MAX_SIZE 0x19000 /* 100K */
+#define CONFIG_SPL_TEXT_BASE 0x4030
+#define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_DISPLAY_PRINT
#define CONFIG_SPL_LDSCRIPT $(CPUDIR)/omap-common/u-boot-spl.lds
Ok, we keep the SPL stack at
#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END -
GENERATED_GBL_DATA_SIZE)
So does this now create any possiblity of STACK overlap with the SCRATCH PAD
area ? or
since we have 8K at TOP, this is enough to avoid overlap ?
Is it good to keep NON_SECURE_SRAM_END 0x4031E000 otherwise ?
Also with the base address change to 0x4030, wanted to check this once on
HS devices.
I can check this and let you know.
Regards,
Sricharan
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 3/4] generic board patch of manual reloc and zero gd_t
Hi David,
On Tue, Aug 20, 2013 at 4:48 AM, feng...@phytium.com.cn wrote:
From: David Feng feng...@phytium.com.cn
1. function board_init_f in board_f.c should firstly zero gd_t structure
before it call initcall_run_list, otherwise the debug print will go run
if DEBUG is defined. Because the printf function will use global data
to determine whether serial port is initialized and could be written.
2. function board_init_r in board_r.c should firstly relocate init_sequence_r
table before it call initcall_run_list. Command table also should be
relocated.
Signed-off-by: David Feng feng...@phytium.com.cn
---
common/board_f.c |6 ++
common/board_r.c | 17 +
2 files changed, 23 insertions(+)
diff --git a/common/board_f.c b/common/board_f.c
index 5e738fb..f437bcb 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -1009,6 +1009,12 @@ void board_init_f(ulong boot_flags)
gd = data;
#endif
+ /*
+* Zero gd_t first, otherwise the debug print in initcall_run_list
+* function before zero_global_data is called will go wrong.
+*/
+ memset((void *)gd, 0, sizeof(gd_t));
+
Yes, we need this. You should drop the zero_global_data() or whatever
currently does the memset()
gd-flags = boot_flags;
if (initcall_run_list(init_sequence_f))
diff --git a/common/board_r.c b/common/board_r.c
index 86ca1cb..1b4bdd2 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -157,6 +157,13 @@ static int initr_reloc_global_data(void)
*/
gd-env_addr += gd-relocaddr - CONFIG_SYS_MONITOR_BASE;
#endif
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+ /*
+* We have to relocate the command table manually
+*/
+ fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+ ll_entry_count(cmd_tbl_t, cmd));
+#endif /* CONFIG_NEEDS_MANUAL_RELOC */
Should this be done here or in main_loop()? How is this currently done
when not using generic board?
return 0;
}
@@ -899,6 +906,7 @@ init_fnc_t init_sequence_r[] = {
initr_modem,
#endif
run_main_loop,
+ NULL,
};
void board_init_r(gd_t *new_gd, ulong dest_addr)
@@ -906,6 +914,15 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
#ifndef CONFIG_X86
gd = new_gd;
#endif
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+ /*
+* We have to relocate the init_sequence_r table manually
+*/
+ init_fnc_t *init_fnc_ptr;
+ for (init_fnc_ptr = init_sequence_r; *init_fnc_ptr; ++init_fnc_ptr)
+ *init_fnc_ptr = (init_fnc_t *)((unsigned long)(*init_fnc_ptr)
+ gd-reloc_off);
+#endif /* CONFIG_NEEDS_MANUAL_RELOC */
+
if (initcall_run_list(init_sequence_r))
hang();
Regards,
Simon
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
