[U-Boot] please pull u-boot-samsung master
Dear Albert, The following changes since commit 8ee950dd273aef6a074d41bf2ee4ef11d6f848fb: Prepare v2014.04-rc2 (2014-03-10 17:21:06 -0400) are available in the git repository at: http://git.denx.de/u-boot-samsung for you to fetch changes up to b627eb461bb281a00b543e72e74edc197b5f7b5e: usb: dfu: add static alt num count in dfu_config_entities() (2014-03-13 10:30:56 +0900) Marek Vasut (1): arm: exynos: Squash bogus warnings in pinmux Piotr Wilczek (12): exynos4:pinmux:fdt: decode peripheral id video:mipidsim:fdt: Add DT support for mipi dsim driver video:exynos_fb:fdt: add additional fdt data drivers:mmc:sdhci: enable support for DT board:samsung: move checkboard to common file arm:exynos: add common DTS file for exynos 4 board:samsung:common: move max77686 init function arm:exynos: enable sdhci and misc_init to common board board:origen: Enable device tree on Origen board:universal: Enable device tree on Universal board:trats: Enable device tree on Trats board:trats2: Enable device tree on Trats2 Przemyslaw Marczak (2): Trats/Trats2: Update Tizen partitions layout and dfu entities usb: dfu: add static alt num count in dfu_config_entities() arch/arm/cpu/armv7/exynos/pinmux.c | 29 ++ arch/arm/dts/Makefile |5 + arch/arm/dts/exynos4.dtsi | 138 +++ arch/arm/dts/exynos4210-origen.dts | 45 ++ arch/arm/dts/exynos4210-trats.dts | 120 ++ arch/arm/dts/exynos4210-universal_c210.dts | 83 arch/arm/dts/exynos4412-trats2.dts | 434 arch/arm/include/asm/arch-exynos/board.h | 12 + arch/arm/include/asm/arch-exynos/mipi_dsim.h |5 + arch/arm/include/asm/arch-exynos/mmc.h |7 + board/samsung/common/board.c | 180 +++- board/samsung/origen/origen.c | 112 + board/samsung/smdk5250/exynos5-dt.c| 15 - board/samsung/smdk5250/smdk5250.c | 125 ++ board/samsung/smdk5420/smdk5420.c | 15 - board/samsung/trats/trats.c| 213 +- board/samsung/trats2/trats2.c | 233 +-- board/samsung/universal_c210/universal.c | 204 +++-- doc/device-tree-bindings/video/exynos_mipi_dsi.txt | 82 drivers/dfu/dfu.c |6 +- drivers/mmc/s5p_sdhci.c| 129 ++ drivers/video/exynos_fb.c | 12 + drivers/video/exynos_mipi_dsi.c| 96 + include/configs/exynos4-dt.h | 138 +++ include/configs/origen.h | 110 ++--- include/configs/s5pc210_universal.h| 152 +++ include/configs/trats.h| 225 +++--- include/configs/trats2.h | 218 +++--- include/fdtdec.h |2 + include/sdhci.h|5 + lib/fdtdec.c |2 + 31 files changed, 1802 insertions(+), 1350 deletions(-) create mode 100644 arch/arm/dts/exynos4.dtsi create mode 100644 arch/arm/dts/exynos4210-origen.dts create mode 100644 arch/arm/dts/exynos4210-trats.dts create mode 100644 arch/arm/dts/exynos4210-universal_c210.dts create mode 100644 arch/arm/dts/exynos4412-trats2.dts create mode 100644 doc/device-tree-bindings/video/exynos_mipi_dsi.txt create mode 100644 include/configs/exynos4-dt.h -- Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: exynos: Squash bogus warnings in pinmux
Hi Minkyu,
On 12/03/14 21:27, Marek Vasut wrote:
On Wednesday, March 12, 2014 at 01:21:15 PM, Lukasz Majewski wrote:
Hi Marek,
On Wednesday, March 12, 2014 at 08:51:56 AM, Lukasz Majewski
wrote:
Hi Simon, Marek,
Hi Marek,
On 10 March 2014 13:04, Marek Vasut ma...@denx.de wrote:
Squash these warnings in pinmux.c found with GCC 4.8:
/arch/arm/cpu/armv7/exynos/pinmux.c: In function
'exynos_pinmux_config': /arch/arm/cpu/armv7/exynos/pinmux.c:687:28:
warning: 'count' may be used uninitialized in this function
[-Wmaybe-uninitialized] for (i = start; i start + count; i++)
{ ^ /arch/arm/cpu/armv7/exynos/pinmux.c:663:16: note: 'count'
was declared here int i, start, count;
^
/arch/arm/cpu/armv7/exynos/pinmux.c:687:28: warning: 'start'
may be used uninitialized in this function
[-Wmaybe-uninitialized] for (i = start; i start + count; i++)
{ ^ /arch/arm/cpu/armv7/exynos/pinmux.c:663:9: note: 'start'
was declared here int i, start, count;
^
/arch/arm/cpu/armv7/exynos/pinmux.c:689:19: warning: 'bank' may
be used uninitialized in this function [-Wmaybe-uninitialized]
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); ^
/arch/arm/cpu/armv7/exynos/pinmux.c:662:24: note: 'bank' was
declared here struct s5p_gpio_bank *bank;
^
/arch/arm/cpu/armv7/exynos/pinmux.c: In function
'exynos_pinmux_config': /arch/arm/cpu/armv7/exynos/pinmux.c:687:28:
warning: 'count' may be used uninitialized in this function
[-Wmaybe-uninitialized] for (i = start; i start + count; i++)
{ ^ /arch/arm/cpu/armv7/exynos/pinmux.c:663:16: note: 'count'
was declared here int i, start, count;
^
/arch/arm/cpu/armv7/exynos/pinmux.c:687:28: warning: 'start'
may be used uninitialized in this function
[-Wmaybe-uninitialized] for (i = start; i start + count; i++)
{ ^ /arch/arm/cpu/armv7/exynos/pinmux.c:663:9: note: 'start'
was declared here int i, start, count;
^
/arch/arm/cpu/armv7/exynos/pinmux.c:689:19: warning: 'bank' may
be used uninitialized in this function [-Wmaybe-uninitialized]
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); ^
/arch/arm/cpu/armv7/exynos/pinmux.c:662:24: note: 'bank' was
declared here struct s5p_gpio_bank *bank;
^
Note that the warning is bogus, the function can never be
called with invalid 'peripheral' argument. GCC just cannot
analyze this.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Akshay Saraswat aksha...@samsung.com
Cc: Rajeshwari S Shinde rajeshwar...@samsung.com
Cc: Simon Glass s...@chromium.org
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Tom Rini tr...@ti.com
Acked-by: Simon Glass s...@chromium.org
Thanks Marek, great to get that annoyance fixed.
Fix for this issue has been already posted :-) (one week ago)
http://patchwork.ozlabs.org/patch/327065/
But I don't mind if Marek's patch will be applied directly by Tom
before v2014.04 is released :-)
Aren't you missing the exynos5_mmc_config() in your patch ?
Yes, my work miss it. Lets apply your patch and be happy with
clean build results from gcc 4.8 :-).
Roger that.
applied to u-boot-samsung.
Lukasz,
your patch will abandon because of this patch.
OK, no problem for me :-)
Thanks,
Minkyu Kang.
--
Best regards,
Lukasz Majewski
Samsung RD Institute Poland (SRPOL) | Linux Platform Group
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Re: [U-Boot] ref: virt-v7.c switching to non_secure mode
Hi Christoffer / uboot,
We are able to figure out the issue. PERIPHBASE returned on ARNDALE board was
0x1050 and adding GIC offset was creating an incorrect address.
Setting CONFIG_ARM_GIC_BASE_ADDRESS as 0x1048 in arndale.h solves the issue.
The u-boot code needs to be fixed for arndale right ? Please confirm
Regards
Manish
armdev Team @FTM
On 13-Mar-2014, at 11:20 am, armdev armdev@gmail.com wrote:
Got a mail that Andre is not with linaro, Adding Christoffer Dall
On 13-Mar-2014, at 11:17 am, armdev armdev@gmail.com wrote:
Hi Andrey ,
This is wrt your patch set which enabled the switch to non-sec and hip mode
in armv7.
We have a small piece of code which we run in hypmode using the bootm
command on arndale board
While this code was trying to access the GICD_ISENABLR0 (0x10481100), read
was always returning 0, while as per the reset value it should be
0x. Debugged more in u-boot and added prints.
This is the log, our observation is that in _nonsec_init() there is
something that is causing the issue. Now It can be an issue or a gap in our
understanding. Ideally we should be able to read the GICD_ISENABLR value as
0x.
Can you please help us in find out how to read GIC values properly in hyp
mode.
armv7_switch_nonsec
cpsr =61d3
REGS
Before write to group regs
cpsr =61d3
REGS
Before _nonsec_init()
cpsr =61d3
REGS
After _nonsec_init()
cpsr =61d3
REGS 0
HYP mode: successful.
armv7_switch_hyp
cpsr =61da
REGS 0
Here is the diff of our modifications. (just added prints)
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index 2cd604f..f38f125 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -107,6 +107,10 @@ int armv7_switch_hyp(void)
printf(HYP mode: switch not successful.\n);
return -1;
}
+printf(HYP mode: successful.\n);
+printf(%s \r\n,__FUNCTION__);
+printf(cpsr =%x\n, read_cpsr());
+printf(REGS %x \n, *(uint32_t*)0x10481100);
return 0;
}
@@ -116,6 +120,10 @@ int armv7_switch_nonsec(void)
unsigned int reg;
unsigned itlinesnr, i;
+printf(%s \r\n,__FUNCTION__);
+printf(cpsr =%x\n, read_cpsr());
+printf(REGS %x \n, *(uint32_t*)0x10481100);
+
/* check whether the CPU supports the security extensions */
reg = read_id_pfr1();
if ((reg 0xF0) == 0) {
@@ -140,6 +148,9 @@ int armv7_switch_nonsec(void)
/* TYPER[4:0] contains an encoded number of available interrupts */
itlinesnr = readl(gic_dist_addr + GICD_TYPER) 0x1f;
+printf(Before write to group regs \r\n);
+printf(cpsr =%x\n, read_cpsr());
+printf(REGS %x \n, *(uint32_t*)0x10481100);
/* set all bits in the GIC group registers to one to allow access
* from non-secure state. The first 32 interrupts are private per
* CPU and will be set later when enabling the GIC for each core
@@ -147,11 +158,19 @@ int armv7_switch_nonsec(void)
for (i = 1; i = itlinesnr; i++)
writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
-smp_set_core_boot_addr((unsigned long)_smp_pen, -1);
-smp_kick_all_cpus();
+//smp_set_core_boot_addr((unsigned long)_smp_pen, -1);
+//smp_kick_all_cpus();
+printf(Before _nonsec_init() \r\n);
+printf(cpsr =%x\n, read_cpsr());
+printf(REGS %x \n, *(uint32_t*)0x10481100);
/* call the non-sec switching code on this CPU also */
_nonsec_init();
+printf(After _nonsec_init() \r\n);
+printf(cpsr =%x\n, read_cpsr());
+printf(REGS %x \n, *(uint32_t*)0x10481100);
+
+
return 0;
}
diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index 515facf..53a1212 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -62,7 +62,6 @@
/* select serial console configuration */
#define CONFIG_BAUDRATE 115200
#define EXYNOS5_DEFAULT_UART_OFFSET 0x01
-#define CONFIG_SILENT_CONSOLE
/* Console configuration */
#define CONFIG_CONSOLE_MUX
@@ -249,4 +248,7 @@
/* Enable Time Command */
#define CONFIG_CMD_TIME
+/* Enable jump to hypervisor */
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_SMP_PEN_ADDR 0x0
#endif /* __CONFIG_H */
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Re: [U-Boot] [PATCH] powerpc/t208x: enable command MEMTEST DDR_INTERACTIVE EEPROM
Dear York Sun, In message 88c8c779-b636-4abf-9751-33e471307...@freescale.com you wrote: On Mar 12, 2014, at 8:17 PM, Shengzhou Liu wrote: Enable CONFIG_CMD_MEMTEST, CONFIG_FSL_DDR_INTERACTIVE, CONFIG_CMD_EEPROM I can see the ddr debugging and eeprom command are useful. But I am not convinced memtest is effective as it is intended to be. There was a discussion a while ago. Except for some very specific cases (like watching signals on a scope while running the test) memtest is almost totally worthless. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Once upon a time, PC meant personal computer. Now it seems to only mean Prisoner of Bill. Alas! All my PCs run Unix, and those include Intel, Sparc, and other processors. -- Tom Bring back the non-PC meaning of `PC' Christiansen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] post_memory_tests
Hello, I need to run memory RAM test on an ARM based platform. I saw that there is the POST tests framework in u-boot and I had some questions about it. What is the purpose of the _POST_WORD_ADDR variable in include/post.h? How should I define the value of that variable? Also, I try to run the post_memory_test in normal mode, before relocation ( the test verifies only small 4Kb regions of RAM around each 1Mb boundary). That seems to work. But when I tried to change the value of the region from 4K to 8K, it does not work anymore. Does anyone have a clue on that? Thanks for your help chirong ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] post_memory_tests
Dear chi l, In message bay180-w137a35527f40147a2e3fd587...@phx.gbl you wrote: What is the purpose of the _POST_WORD_ADDR variable in include/post.h? How should I define the value of that variable? See post_word_load() and post_word_store() [both in include/post.h] how _POST_WORD_ADDR gets used. You need a persistent (across resets of the CPU) non-RAM memory cell. Also, I try to run the post_memory_test in normal mode, before relocation ( the test verifies only small 4Kb regions of RAM around each 1Mb boundary). That seems to work. But when I tried to change the value of the regionfrom 4K to 8K, it does not work anymore. Does anyone have a clue on that ? You are aware that you must not (under no circumstances) be executing this code from system RAM? It can only be run rom a memory device that is not currently being tested (parallel NOR flash, SRAM, OCM or such). Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de 365 Days of drinking Lo-Cal beer. = 1 Lite-year ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] post_memory_tests
Hello, Thank you for your answer. Yes. the test runs from the NOR flash (post_run function calls the test in arch/arm/lib/board.c before the relocation of U-Boot in the RAM). That is why I'm kind of confuse about why the tests works for 4K regions and not for 8K regions. Maybe, even if the test runs in ROM, are there some regions in the RAM that I should prevent from testing? Regards To: chi-r...@outlook.com CC: u-boot@lists.denx.de From: w...@denx.de Subject: Re: [U-Boot] post_memory_tests Date: Thu, 13 Mar 2014 09:25:35 +0100 Dear chi l, In message bay180-w137a35527f40147a2e3fd587...@phx.gbl you wrote: What is the purpose of the _POST_WORD_ADDR variable in include/post.h? How should I define the value of that variable? See post_word_load() and post_word_store() [both in include/post.h] how _POST_WORD_ADDR gets used. You need a persistent (across resets of the CPU) non-RAM memory cell. Also, I try to run the post_memory_test in normal mode, before relocation ( the test verifies only small 4Kb regions of RAM around each 1Mb boundary). That seems to work. But when I tried to change the value of the regionfrom 4K to 8K, it does not work anymore. Does anyone have a clue on that ? You are aware that you must not (under no circumstances) be executing this code from system RAM? It can only be run rom a memory device that is not currently being tested (parallel NOR flash, SRAM, OCM or such). Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de 365 Days of drinking Lo-Cal beer. = 1 Lite-year ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ref: virt-v7.c switching to non_secure mode
Dear Andre,
Thanks for replying.
On 13-Mar-2014, at 3:11 pm, Andre Przywara andre.przyw...@arm.com wrote:
Hi,
We are able to figure out the issue. PERIPHBASE returned on ARNDALE
board was 0x1050 and adding GIC offset was creating an incorrect
address.
please see:
https://github.com/apritzel/u-boot-hypmode/commit/5d9c4209907c6d67dadd033887a30c2f10efeb4c
Setting CONFIG_ARM_GIC_BASE_ADDRESS as 0x1048 in arndale.h solves the
issue.
Yes, I spotted that before and deliberately introduced that variable for
the Exynos SoCs.
So it turns out that this is the only way.
The u-boot code needs to be fixed for arndale right ? Please confirm
I could get the Arndale to boot with this above patch. But only after a
warm reboot:
Can you please describe more on the warm reboot problem. I am not facing
anything like it.
1) boot the board up, load the kernel and launch it: Linux will reboot
very early (before any useful output via earlyprintk)
2) (back in u-boot:) load the kernel again and launch it: works
I got both cores in HYP mode and KVM initialized fine.
I lost access to my board, so if you could debug this I would be grateful.
I have 3 boards of exynos family 5250 /5410 /5420. I will try on each and let
you know. If you have anything specific do let me know
Thanks,
Andre.
Regards
Manish
armdev Team @FTM
On 13-Mar-2014, at 11:20 am, armdev armdev@gmail.com wrote:
Got a mail that Andre is not with linaro, Adding Christoffer Dall
On 13-Mar-2014, at 11:17 am, armdev armdev@gmail.com wrote:
Hi Andrey ,
This is wrt your patch set which enabled the switch to non-sec and hip
mode in armv7.
We have a small piece of code which we run in hypmode using the bootm
command on arndale board
While this code was trying to access the GICD_ISENABLR0 (0x10481100), read
was always returning 0, while as per the reset value it should be
0x. Debugged more in u-boot and added prints.
This is the log, our observation is that in _nonsec_init() there is
something that is causing the issue. Now It can be an issue or a gap in
our understanding. Ideally we should be able to read the GICD_ISENABLR
value as 0x.
Can you please help us in find out how to read GIC values properly in hyp
mode.
armv7_switch_nonsec
cpsr =61d3
REGS
Before write to group regs
cpsr =61d3
REGS
Before _nonsec_init()
cpsr =61d3
REGS
After _nonsec_init()
cpsr =61d3
REGS 0
HYP mode: successful.
armv7_switch_hyp
cpsr =61da
REGS 0
Here is the diff of our modifications. (just added prints)
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index 2cd604f..f38f125 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -107,6 +107,10 @@ int armv7_switch_hyp(void)
printf(HYP mode: switch not successful.\n);
return -1;
}
+ printf(HYP mode: successful.\n);
+ printf(%s \r\n,__FUNCTION__);
+ printf(cpsr =%x\n, read_cpsr());
+ printf(REGS %x \n, *(uint32_t*)0x10481100);
return 0;
}
@@ -116,6 +120,10 @@ int armv7_switch_nonsec(void)
unsigned int reg;
unsigned itlinesnr, i;
+ printf(%s \r\n,__FUNCTION__);
+ printf(cpsr =%x\n, read_cpsr());
+ printf(REGS %x \n, *(uint32_t*)0x10481100);
+
/* check whether the CPU supports the security extensions */
reg = read_id_pfr1();
if ((reg 0xF0) == 0) {
@@ -140,6 +148,9 @@ int armv7_switch_nonsec(void)
/* TYPER[4:0] contains an encoded number of available interrupts */
itlinesnr = readl(gic_dist_addr + GICD_TYPER) 0x1f;
+ printf(Before write to group regs \r\n);
+ printf(cpsr =%x\n, read_cpsr());
+ printf(REGS %x \n, *(uint32_t*)0x10481100);
/* set all bits in the GIC group registers to one to allow access
* from non-secure state. The first 32 interrupts are private per
* CPU and will be set later when enabling the GIC for each core
@@ -147,11 +158,19 @@ int armv7_switch_nonsec(void)
for (i = 1; i = itlinesnr; i++)
writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
- smp_set_core_boot_addr((unsigned long)_smp_pen, -1);
- smp_kick_all_cpus();
+ //smp_set_core_boot_addr((unsigned long)_smp_pen, -1);
+ //smp_kick_all_cpus();
+ printf(Before _nonsec_init() \r\n);
+ printf(cpsr =%x\n, read_cpsr());
+ printf(REGS %x \n, *(uint32_t*)0x10481100);
/* call the non-sec switching code on this CPU also */
_nonsec_init();
+ printf(After _nonsec_init() \r\n);
+ printf(cpsr =%x\n, read_cpsr());
+ printf(REGS %x \n, *(uint32_t*)0x10481100);
+
+
return 0;
}
diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index 515facf..53a1212 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -62,7 +62,6 @@
/* select serial console configuration */
#define CONFIG_BAUDRATE 115200
#define
Re: [U-Boot] [PATCH] arm: omap: cm_t35: Fix: Re-add GPMC_NAND_ECC_LP_x8_LAYOUT
From: Stefan Roese [mailto:s...@denx.de] Patch a7e36fc9 (mtd: nand: omap: remove unused #defines from common omap_gpmc.h) removed some MTD related defines. Including GPMC_NAND_ECC_LP_x8_LAYOUT. But this define is also needed for the memory controller configuration (only the x8 defines are needed, the x16 defines are the default). Without it the NAND subsystem is not configured correctly and booting into U-Boot does not work. The root cause of this problem is in .. arch/arm/cpu/armv7/omap3/mem.c #if defined(GPMC_NAND_ECC_SP_x8_LAYOUT) || defined(GPMC_NAND_ECC_LP_x8_LAYOUT) where based on GPMC_NAND_ECC_LP_x8_LAYOUT, different controller configuration is selected. Unless you need a urgent fix, - I would suggest to use [1] instead. I'll try to get a cleaner version of [1] incorporating other comments from Scott, soon. - Alternatively, you can also look at [2], which is more robust but was still under discussion. [1] http://lists.denx.de/pipermail/u-boot/2013-December/168507.html [2] http://lists.denx.de/pipermail/u-boot/2013-September/163882.html http://lists.denx.de/pipermail/u-boot/2013-September/163879.html with regards, pekon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: omap: cm_t35: Fix: Re-add GPMC_NAND_ECC_LP_x8_LAYOUT
Hi Pekon, On 13.03.2014 12:49, Gupta, Pekon wrote: From: Stefan Roese [mailto:s...@denx.de] Patch a7e36fc9 (mtd: nand: omap: remove unused #defines from common omap_gpmc.h) removed some MTD related defines. Including GPMC_NAND_ECC_LP_x8_LAYOUT. But this define is also needed for the memory controller configuration (only the x8 defines are needed, the x16 defines are the default). Without it the NAND subsystem is not configured correctly and booting into U-Boot does not work. The root cause of this problem is in .. arch/arm/cpu/armv7/omap3/mem.c #if defined(GPMC_NAND_ECC_SP_x8_LAYOUT) || defined(GPMC_NAND_ECC_LP_x8_LAYOUT) where based on GPMC_NAND_ECC_LP_x8_LAYOUT, different controller configuration is selected. I know as I introduced this code a while ago for this x8 NAND target. ;) Unless you need a urgent fix, Yes, I need an urgent fix. This board does not boot anymore. Note that Tom already pulled my patch into his TI repo. So this fix is on its way right now. - I would suggest to use [1] instead. I'll try to get a cleaner version of [1] incorporating other comments from Scott, soon. - Alternatively, you can also look at [2], which is more robust but was still under discussion. Yes, your patches look more elegant. I suggest to move to them once the discussion has settled. And then remove these x8_LAYOUT defines completely when they are really not needed any more. But please not sooner. Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] post_memory_tests
Dear chi l, In message bay180-w4040aaed90c5edc765f77f87...@phx.gbl you wrote: Thank you for your answer. Yes. the test runs from the NOR flash (post_run function calls the test in arch/arm/lib/board.c before the relocation of U- Boot in the RAM). That is why I'm kind of confuse about why the tests works for 4K regions and not for 8K regions. Maybe, even if the test runs in R OM, are there some regions in the RAM that I should prevent from testing? Normally not. You should be able to test the whole RAM. Which board / SoC / architecture are you working with? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Don't tell me how hard you work. Tell me how much you get done. - James J. Ling ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ref: virt-v7.c switching to non_secure mode
Hi,
We are able to figure out the issue. PERIPHBASE returned on ARNDALE
board was 0x1050 and adding GIC offset was creating an incorrect
address.
please see:
https://github.com/apritzel/u-boot-hypmode/commit/5d9c4209907c6d67dadd033887a30c2f10efeb4c
Setting CONFIG_ARM_GIC_BASE_ADDRESS as 0x1048 in arndale.h solves the issue.
Yes, I spotted that before and deliberately introduced that variable for
the Exynos SoCs.
The u-boot code needs to be fixed for arndale right ? Please confirm
I could get the Arndale to boot with this above patch. But only after a
warm reboot:
1) boot the board up, load the kernel and launch it: Linux will reboot
very early (before any useful output via earlyprintk)
2) (back in u-boot:) load the kernel again and launch it: works
I got both cores in HYP mode and KVM initialized fine.
I lost access to my board, so if you could debug this I would be grateful.
Thanks,
Andre.
Regards
Manish
armdev Team @FTM
On 13-Mar-2014, at 11:20 am, armdev armdev@gmail.com wrote:
Got a mail that Andre is not with linaro, Adding Christoffer Dall
On 13-Mar-2014, at 11:17 am, armdev armdev@gmail.com wrote:
Hi Andrey ,
This is wrt your patch set which enabled the switch to non-sec and hip mode in
armv7.
We have a small piece of code which we run in hypmode using the bootm command
on arndale board
While this code was trying to access the GICD_ISENABLR0 (0x10481100), read was
always returning 0, while as per the reset value it should be 0x.
Debugged more in u-boot and added prints.
This is the log, our observation is that in _nonsec_init() there is something
that is causing the issue. Now It can be an issue or a gap in our
understanding. Ideally we should be able to read the GICD_ISENABLR value as
0x.
Can you please help us in find out how to read GIC values properly in hyp mode.
armv7_switch_nonsec
cpsr =61d3
REGS
Before write to group regs
cpsr =61d3
REGS
Before _nonsec_init()
cpsr =61d3
REGS
After _nonsec_init()
cpsr =61d3
REGS 0
HYP mode: successful.
armv7_switch_hyp
cpsr =61da
REGS 0
Here is the diff of our modifications. (just added prints)
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index 2cd604f..f38f125 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -107,6 +107,10 @@ int armv7_switch_hyp(void)
printf(HYP mode: switch not successful.\n);
return -1;
}
+ printf(HYP mode: successful.\n);
+ printf(%s \r\n,__FUNCTION__);
+ printf(cpsr =%x\n, read_cpsr());
+ printf(REGS %x \n, *(uint32_t*)0x10481100);
return 0;
}
@@ -116,6 +120,10 @@ int armv7_switch_nonsec(void)
unsigned int reg;
unsigned itlinesnr, i;
+ printf(%s \r\n,__FUNCTION__);
+ printf(cpsr =%x\n, read_cpsr());
+ printf(REGS %x \n, *(uint32_t*)0x10481100);
+
/* check whether the CPU supports the security extensions */
reg = read_id_pfr1();
if ((reg 0xF0) == 0) {
@@ -140,6 +148,9 @@ int armv7_switch_nonsec(void)
/* TYPER[4:0] contains an encoded number of available interrupts */
itlinesnr = readl(gic_dist_addr + GICD_TYPER) 0x1f;
+ printf(Before write to group regs \r\n);
+ printf(cpsr =%x\n, read_cpsr());
+ printf(REGS %x \n, *(uint32_t*)0x10481100);
/* set all bits in the GIC group registers to one to allow access
* from non-secure state. The first 32 interrupts are private per
* CPU and will be set later when enabling the GIC for each core
@@ -147,11 +158,19 @@ int armv7_switch_nonsec(void)
for (i = 1; i = itlinesnr; i++)
writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
- smp_set_core_boot_addr((unsigned long)_smp_pen, -1);
- smp_kick_all_cpus();
+ //smp_set_core_boot_addr((unsigned long)_smp_pen, -1);
+ //smp_kick_all_cpus();
+ printf(Before _nonsec_init() \r\n);
+ printf(cpsr =%x\n, read_cpsr());
+ printf(REGS %x \n, *(uint32_t*)0x10481100);
/* call the non-sec switching code on this CPU also */
_nonsec_init();
+ printf(After _nonsec_init() \r\n);
+ printf(cpsr =%x\n, read_cpsr());
+ printf(REGS %x \n, *(uint32_t*)0x10481100);
+
+
return 0;
}
diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index 515facf..53a1212 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -62,7 +62,6 @@
/* select serial console configuration */
#define CONFIG_BAUDRATE 115200
#define EXYNOS5_DEFAULT_UART_OFFSET 0x01
-#define CONFIG_SILENT_CONSOLE
/* Console configuration */
#define CONFIG_CONSOLE_MUX
@@ -249,4 +248,7 @@
/* Enable Time Command */
#define CONFIG_CMD_TIME
+/* Enable jump to hypervisor */
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_SMP_PEN_ADDR 0x0
#endif /* __CONFIG_H */
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Re: [U-Boot] [PATCH 1/3] usb, dfu: extract flush code into seperate function
On Thursday, March 13, 2014 at 06:31:03 AM, Heiko Schocher wrote:
Hello Marek,
Am 12.03.2014 12:43, schrieb Marek Vasut:
On Wednesday, March 12, 2014 at 11:01:19 AM, Heiko Schocher wrote:
move the flushing code into an extra function dfu_flush(),
so it can be used from other code.
Signed-off-by: Heiko Schocherh...@denx.de
Cc: Lukasz Majewskil.majew...@samsung.com
Cc: Kyungmin Parkkyungmin.p...@samsung.com
Cc: Marek Vasutma...@denx.de
---
drivers/dfu/dfu.c | 46 ++
include/dfu.h | 1 +
2 files changed, 27 insertions(+), 20 deletions(-)
diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c
index 56e69fd..193e047 100644
--- a/drivers/dfu/dfu.c
+++ b/drivers/dfu/dfu.c
@@ -127,6 +127,31 @@ static int dfu_write_buffer_drain(struct dfu_entity
*dfu) return ret;
}
+int dfu_flush(struct dfu_entity *dfu, void *buf, int size, int
blk_seq_num) +{
+ int ret = 0;
+
+ /* end? */
What does this comment mean ? I don't understand it ...
Comes from original code... Thinking about it, it seems better to
let this comment and the below if in the dfu_write function...
+ if (size == 0) {
You can check this like so:
if (size)
return;
... as when moving this if back to dfu_write(), this if kindly
disappears in the patch 2/3 of this series, as calling dfu_flush()
is only in the new dfuMANIFEST state necessary, which is called at
the end of the dfu transfer, so no need for checking, if end of
size is reached!
OK, this makes sense. Thanks for pointing this out.
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Re: [U-Boot] [PATCH 01/12] kbuild, mxs: use short logs for MXS images
On Thu, Mar 13, 2014 at 05:01:59AM +0100, Marek Vasut wrote: Hello Masahiro-san, [...] Yes, I see. We shall eventually rename it to mkimage throughout the code. How shall we proceed? I see we have three options: - Post V2 of this patch - Fix the rest of the files which have this 'UIMAGE' in them and then post V2 - Postpone the fix and then do it globally I would be in favor of the second option. This patch is already on u-boot/master. Can you post a follow-up patch? I think you will have to modify 7 files. ./Makefile:731:quiet_cmd_mkimage = UIMAGE $@ ./arch/arm/imx-common/Makefile:35:quiet_cmd_mkimage = UIMAGE $@ ./arch/arm/cpu/arm926ejs/mxs/Makefile:20:quiet_cmd_mkimage_mxs = UIMAGE $@ ./spl/Makefile:174:quiet_cmd_mkimage = UIMAGE $@ ./board/cray/L1/Makefile:18:quiet_cmd_mkimage = UIMAGE $@ ./board/matrix_vision/mvsmr/Makefile:15:quiet_cmd_mkimage = UIMAGE $@ ./board/matrix_vision/mvblm7/Makefile:11:quiet_cmd_mkimage = UIMAGE $@ Tom, what's your take on this ... UIMAGE or MKIMAGE ? MKIMAGE please, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH 1/6] fpga: spartan2: Avoid CamelCase
No functional changes.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
board/esd/pmc440/fpga.c | 2 +-
board/matrix_vision/mvsmr/fpga.c | 2 +-
drivers/fpga/spartan2.c | 40
drivers/fpga/xilinx.c| 14 +++---
include/spartan2.h | 32
include/xilinx.h | 2 +-
6 files changed, 46 insertions(+), 46 deletions(-)
diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c
index b7b62dd..cef2050 100644
--- a/board/esd/pmc440/fpga.c
+++ b/board/esd/pmc440/fpga.c
@@ -47,7 +47,7 @@ Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = {
};
#endif
-Xilinx_Spartan2_Slave_Serial_fns ngcc_fpga_fns = {
+xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = {
ngcc_fpga_pre_config_fn,
ngcc_fpga_pgm_fn,
ngcc_fpga_clk_fn,
diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c
index 88035a9..639bc7c 100644
--- a/board/matrix_vision/mvsmr/fpga.c
+++ b/board/matrix_vision/mvsmr/fpga.c
@@ -27,7 +27,7 @@ Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
};
Xilinx_desc spartan3 = {
- Xilinx_Spartan2,
+ xilinx_spartan2,
slave_serial,
XILINX_XC3S200_SIZE,
(void *) fpga_fns,
diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c
index 6eab1b5..bd31709 100644
--- a/drivers/fpga/spartan2.c
+++ b/drivers/fpga/spartan2.c
@@ -31,29 +31,29 @@
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
-static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int Spartan2_sp_info(Xilinx_desc *desc ); */
+static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan2_sp_info(Xilinx_desc *desc ); */
-static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int Spartan2_ss_info(Xilinx_desc *desc ); */
+static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan2_ss_info(Xilinx_desc *desc ); */
/* - */
/* Spartan-II Generic Implementation */
-int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+int spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc-iface) {
case slave_serial:
PRINTF (%s: Launching Slave Serial Load\n, __FUNCTION__);
- ret_val = Spartan2_ss_load (desc, buf, bsize);
+ ret_val = spartan2_ss_load(desc, buf, bsize);
break;
case slave_parallel:
PRINTF (%s: Launching Slave Parallel Load\n, __FUNCTION__);
- ret_val = Spartan2_sp_load (desc, buf, bsize);
+ ret_val = spartan2_sp_load(desc, buf, bsize);
break;
default:
@@ -64,19 +64,19 @@ int Spartan2_load(Xilinx_desc *desc, const void *buf,
size_t bsize)
return ret_val;
}
-int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+int spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc-iface) {
case slave_serial:
PRINTF (%s: Launching Slave Serial Dump\n, __FUNCTION__);
- ret_val = Spartan2_ss_dump (desc, buf, bsize);
+ ret_val = spartan2_ss_dump(desc, buf, bsize);
break;
case slave_parallel:
PRINTF (%s: Launching Slave Parallel Dump\n, __FUNCTION__);
- ret_val = Spartan2_sp_dump (desc, buf, bsize);
+ ret_val = spartan2_sp_dump(desc, buf, bsize);
break;
default:
@@ -87,7 +87,7 @@ int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int Spartan2_info( Xilinx_desc *desc )
+int spartan2_info(Xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
@@ -96,10 +96,10 @@ int Spartan2_info( Xilinx_desc *desc )
/* - */
/* Spartan-II Slave Parallel Generic Implementation */
-static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;/* assume the worst */
- Xilinx_Spartan2_Slave_Parallel_fns *fn = desc-iface_fns;
+ xilinx_spartan2_slave_parallel_fns *fn = desc-iface_fns;
PRINTF (%s: start with interface functions @ 0x%p\n,
__FUNCTION__, fn);
@@ -248,10
[U-Boot] [RFC PATCH 2/6] fpga: spartan3: Avoid CamelCase
No functional changes.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
board/armadeus/apf27/fpga.c | 4 ++--
board/astro/mcf5373l/fpga.c | 4 ++--
board/balloon3/balloon3.c| 2 +-
board/esd/pmc440/fpga.c | 4 ++--
board/matrix_vision/mvsmr/fpga.c | 2 +-
board/spear/x600/fpga.c | 2 +-
board/teejet/mt_ventoux/mt_ventoux.c | 2 +-
drivers/fpga/spartan3.c | 40 ++--
drivers/fpga/xilinx.c| 14 ++---
include/spartan3.h | 38 +-
include/xilinx.h | 2 +-
11 files changed, 57 insertions(+), 57 deletions(-)
diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c
index 0c08c06..56fde20 100644
--- a/board/armadeus/apf27/fpga.c
+++ b/board/armadeus/apf27/fpga.c
@@ -26,7 +26,7 @@
* Spartan2 code is used to download our Spartan 3 :) code is compatible.
* Just take care about the file size
*/
-Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = {
+xilinx_spartan3_slave_parallel_fns fpga_fns = {
fpga_pre_fn,
fpga_pgm_fn,
fpga_init_fn,
@@ -43,7 +43,7 @@ Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = {
};
Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
- {Xilinx_Spartan3,
+ {xilinx_spartan3,
slave_parallel,
1196128l/8,
(void *)fpga_fns,
diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c
index c679ad7..152ff1f 100644
--- a/board/astro/mcf5373l/fpga.c
+++ b/board/astro/mcf5373l/fpga.c
@@ -363,7 +363,7 @@ int xilinx_fastwr_fn(void *buf, size_t len, int flush, int
cookie)
* relocated at runtime.
* FIXME: relocation not yet working for coldfire, see below!
*/
-Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = {
+xilinx_spartan3_slave_serial_fns xilinx_fns = {
xilinx_pre_config_fn,
xilinx_pgm_fn,
xilinx_clk_fn,
@@ -375,7 +375,7 @@ Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = {
};
Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
- {Xilinx_Spartan3,
+ {xilinx_spartan3,
slave_serial,
XILINX_XC3S4000_SIZE,
(void *)xilinx_fns,
diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c
index 04e0574..4aa6605 100644
--- a/board/balloon3/balloon3.c
+++ b/board/balloon3/balloon3.c
@@ -191,7 +191,7 @@ int fpga_cs_fn(int assert_clk, int flush, int cookie)
return assert_clk;
}
-Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
+xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_init_fn,
diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c
index cef2050..18a1b63 100644
--- a/board/esd/pmc440/fpga.c
+++ b/board/esd/pmc440/fpga.c
@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define USE_SP_CODE
#ifdef USE_SP_CODE
-Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = {
+xilinx_spartan3_slave_parallel_fns pmc440_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_init_fn,
@@ -36,7 +36,7 @@ Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = {
fpga_post_config_fn,
};
#else
-Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = {
+xilinx_spartan3_slave_serial_fns pmc440_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c
index 639bc7c..b207455 100644
--- a/board/matrix_vision/mvsmr/fpga.c
+++ b/board/matrix_vision/mvsmr/fpga.c
@@ -16,7 +16,7 @@
#include fpga.h
#include mvsmr.h
-Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
+xilinx_spartan3_slave_serial_fns fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c
index c06c994..c26eba4 100644
--- a/board/spear/x600/fpga.c
+++ b/board/spear/x600/fpga.c
@@ -163,7 +163,7 @@ static int fpga_wr_fn(int assert_write, int flush, int
cookie)
return assert_write;
}
-static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = {
+static xilinx_spartan3_slave_serial_fns x600_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
diff --git a/board/teejet/mt_ventoux/mt_ventoux.c
b/board/teejet/mt_ventoux/mt_ventoux.c
index c32d554..a361764 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.c
+++ b/board/teejet/mt_ventoux/mt_ventoux.c
@@ -190,7 +190,7 @@ int fpga_clk_fn(int assert_clk, int flush, int cookie)
return assert_clk;
}
-Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = {
+xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c
index 3edc5c2..e40abbf 100644
--- a/drivers/fpga/spartan3.c
+++ b/drivers/fpga/spartan3.c
@@ -35,29 +35,29 @@
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
-static int
[U-Boot] [RFC PATCH 3/6] fpga: virtex2: Avoid CamelCase
No functional changes.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
board/gen860t/fpga.c | 4 ++--
drivers/fpga/virtex2.c | 34 +-
drivers/fpga/xilinx.c | 14 +++---
include/virtex2.h | 34 +-
include/xilinx.h | 2 +-
5 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c
index b7984dd..48a4222 100644
--- a/board/gen860t/fpga.c
+++ b/board/gen860t/fpga.c
@@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* Note that these are pointers to code that is in Flash. They will be
* relocated at runtime.
*/
-Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = {
+xilinx_virtex2_slave_selectmap_fns fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_init_fn,
@@ -57,7 +57,7 @@ Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = {
};
Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
- {Xilinx_Virtex2,
+ {xilinx_virtex2,
slave_selectmap,
XILINX_XC2V3000_SIZE,
(void *) fpga_fns,
diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index b5a895d..1cd9046 100644
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -84,25 +84,25 @@
#define CONFIG_SYS_FPGA_WAIT_CONFIGCONFIG_SYS_HZ/5 /* 200 ms */
#endif
-static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+int virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc-iface) {
case slave_serial:
PRINTF (%s: Launching Slave Serial Load\n, __FUNCTION__);
- ret_val = Virtex2_ss_load (desc, buf, bsize);
+ ret_val = virtex2_ss_load(desc, buf, bsize);
break;
case slave_selectmap:
PRINTF (%s: Launching Slave Parallel Load\n, __FUNCTION__);
- ret_val = Virtex2_ssm_load (desc, buf, bsize);
+ ret_val = virtex2_ssm_load(desc, buf, bsize);
break;
default:
@@ -112,19 +112,19 @@ int Virtex2_load(Xilinx_desc *desc, const void *buf,
size_t bsize)
return ret_val;
}
-int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc-iface) {
case slave_serial:
PRINTF (%s: Launching Slave Serial Dump\n, __FUNCTION__);
- ret_val = Virtex2_ss_dump (desc, buf, bsize);
+ ret_val = virtex2_ss_dump(desc, buf, bsize);
break;
case slave_parallel:
PRINTF (%s: Launching Slave Parallel Dump\n, __FUNCTION__);
- ret_val = Virtex2_ssm_dump (desc, buf, bsize);
+ ret_val = virtex2_ssm_dump(desc, buf, bsize);
break;
default:
@@ -134,7 +134,7 @@ int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int Virtex2_info (Xilinx_desc * desc)
+int virtex2_info(Xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
@@ -153,10 +153,10 @@ int Virtex2_info (Xilinx_desc * desc)
*INIT_B and DONE lines. If both are high, configuration has
*succeeded. Congratulations!
*/
-static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
- Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc-iface_fns;
+ xilinx_virtex2_slave_selectmap_fns *fn = desc-iface_fns;
PRINTF (%s:%d: Start with interface functions @ 0x%p\n,
__FUNCTION__, __LINE__, fn);
@@ -352,10 +352,10 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void
*buf, size_t bsize)
/*
* Read the FPGA configuration data
*/
-static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
- Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc-iface_fns;
+ xilinx_virtex2_slave_selectmap_fns *fn = desc-iface_fns;
if (fn) {
unsigned char *data = (unsigned char *) buf;
@@ -404,13 +404,13 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void
*buf,
[U-Boot] [RFC PATCH 6/6] fpga: xilinx: Simplify load/dump/info function handling
Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/fpga/spartan2.c | 12 +++-
drivers/fpga/spartan3.c | 12 +++-
drivers/fpga/virtex2.c | 12 +++-
drivers/fpga/xilinx.c | 159 +++-
drivers/fpga/zynqpl.c | 13 ++--
include/spartan2.h | 28 -
include/spartan3.h | 36 +--
include/virtex2.h | 28 -
include/xilinx.h| 7 +++
include/zynqpl.h| 16 +++--
10 files changed, 101 insertions(+), 222 deletions(-)
diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c
index 0796729..42c966f 100644
--- a/drivers/fpga/spartan2.c
+++ b/drivers/fpga/spartan2.c
@@ -41,7 +41,7 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void
*buf, size_t bsize);
/* - */
/* Spartan-II Generic Implementation */
-int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@@ -64,7 +64,7 @@ int spartan2_load(xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@@ -87,7 +87,7 @@ int spartan2_dump(xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int spartan2_info(xilinx_desc *desc)
+static int spartan2_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
@@ -447,3 +447,9 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void
*buf, size_t bsize)
__FUNCTION__);
return FPGA_FAIL;
}
+
+struct xilinx_fpga_op spartan2 = {
+ .load = spartan2_load,
+ .dump = spartan2_dump,
+ .info = spartan2_info,
+};
diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c
index 1304b4c..5c9412c 100644
--- a/drivers/fpga/spartan3.c
+++ b/drivers/fpga/spartan3.c
@@ -45,7 +45,7 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void
*buf, size_t bsize);
/* - */
/* Spartan-II Generic Implementation */
-int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@@ -68,7 +68,7 @@ int spartan3_load(xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@@ -91,7 +91,7 @@ int spartan3_dump(xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int spartan3_info(xilinx_desc *desc)
+static int spartan3_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
@@ -465,3 +465,9 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void
*buf, size_t bsize)
__FUNCTION__);
return FPGA_FAIL;
}
+
+struct xilinx_fpga_op spartan3_op = {
+ .load = spartan3_load,
+ .dump = spartan3_dump,
+ .info = spartan3_info,
+};
diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index a582bf2..e092147 100644
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -90,7 +90,7 @@ static int virtex2_ssm_dump(xilinx_desc *desc, const void
*buf, size_t bsize);
static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
-int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@@ -112,7 +112,7 @@ int virtex2_load(xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@@ -134,7 +134,7 @@ int virtex2_dump(xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int virtex2_info(xilinx_desc *desc)
+static int virtex2_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
@@ -417,3 +417,9 @@ static int virtex2_ss_dump(xilinx_desc *desc, const void
*buf, size_t bsize)
}
/* vim: set ts=4 tw=78: */
+
+struct xilinx_fpga_op virtex2_op = {
+ .load = virtex2_load,
+ .dump = virtex2_dump,
+ .info = virtex2_info,
+};
diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c
index b0e9cb3..8837f5c 100644
--- a/drivers/fpga/xilinx.c
+++ b/drivers/fpga/xilinx.c
[U-Boot] [RFC PATCH 5/6] fpga: xilinx: Fix the rest of CamelCases
No functional changes.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
include/spartan2.h | 40
include/spartan3.h | 44 ++--
include/virtex2.h | 34 +-
include/xilinx.h | 42 +-
4 files changed, 80 insertions(+), 80 deletions(-)
diff --git a/include/spartan2.h b/include/spartan2.h
index 33b25e6..25db6e7 100644
--- a/include/spartan2.h
+++ b/include/spartan2.h
@@ -16,30 +16,30 @@ int spartan2_info(xilinx_desc *desc);
/* Slave Parallel Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_init_fn init;
- Xilinx_err_fn err;
- Xilinx_done_fn done;
- Xilinx_clk_fn clk;
- Xilinx_cs_fncs;
- Xilinx_wr_fnwr;
- Xilinx_rdata_fn rdata;
- Xilinx_wdata_fn wdata;
- Xilinx_busy_fn busy;
- Xilinx_abort_fn abort;
- Xilinx_post_fn post;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_init_fn init;
+ xilinx_err_fn err;
+ xilinx_done_fn done;
+ xilinx_clk_fn clk;
+ xilinx_cs_fncs;
+ xilinx_wr_fnwr;
+ xilinx_rdata_fn rdata;
+ xilinx_wdata_fn wdata;
+ xilinx_busy_fn busy;
+ xilinx_abort_fn abort;
+ xilinx_post_fn post;
} xilinx_spartan2_slave_parallel_fns;
/* Slave Serial Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_clk_fn clk;
- Xilinx_init_fn init;
- Xilinx_done_fn done;
- Xilinx_wr_fnwr;
- Xilinx_post_fn post;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_clk_fn clk;
+ xilinx_init_fn init;
+ xilinx_done_fn done;
+ xilinx_wr_fnwr;
+ xilinx_post_fn post;
} xilinx_spartan2_slave_serial_fns;
/* Device Image Sizes
diff --git a/include/spartan3.h b/include/spartan3.h
index e06b99b..56698ac 100644
--- a/include/spartan3.h
+++ b/include/spartan3.h
@@ -16,32 +16,32 @@ int spartan3_info(xilinx_desc *desc);
/* Slave Parallel Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_init_fn init;
- Xilinx_err_fn err;
- Xilinx_done_fn done;
- Xilinx_clk_fn clk;
- Xilinx_cs_fncs;
- Xilinx_wr_fnwr;
- Xilinx_rdata_fn rdata;
- Xilinx_wdata_fn wdata;
- Xilinx_busy_fn busy;
- Xilinx_abort_fn abort;
- Xilinx_post_fn post;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_init_fn init;
+ xilinx_err_fn err;
+ xilinx_done_fn done;
+ xilinx_clk_fn clk;
+ xilinx_cs_fncs;
+ xilinx_wr_fnwr;
+ xilinx_rdata_fn rdata;
+ xilinx_wdata_fn wdata;
+ xilinx_busy_fn busy;
+ xilinx_abort_fn abort;
+ xilinx_post_fn post;
} xilinx_spartan3_slave_parallel_fns;
/* Slave Serial Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_clk_fn clk;
- Xilinx_init_fn init;
- Xilinx_done_fn done;
- Xilinx_wr_fnwr;
- Xilinx_post_fn post;
- Xilinx_bwr_fn bwr; /* block write function */
- Xilinx_abort_fn abort;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_clk_fn clk;
+ xilinx_init_fn init;
+ xilinx_done_fn done;
+ xilinx_wr_fnwr;
+ xilinx_post_fn post;
+ xilinx_bwr_fn bwr; /* block write function */
+ xilinx_abort_fn abort;
} xilinx_spartan3_slave_serial_fns;
/* Device Image Sizes
diff --git a/include/virtex2.h b/include/virtex2.h
index dd47965..d39286c 100644
--- a/include/virtex2.h
+++ b/include/virtex2.h
@@ -19,27 +19,27 @@ int virtex2_info(xilinx_desc *desc);
* Slave SelectMap Implementation function table.
*/
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_init_fn init;
- Xilinx_err_fn err;
- Xilinx_done_fn done;
- Xilinx_clk_fn clk;
- Xilinx_cs_fncs;
- Xilinx_wr_fnwr;
- Xilinx_rdata_fn rdata;
- Xilinx_wdata_fn wdata;
- Xilinx_busy_fn busy;
- Xilinx_abort_fn abort;
- Xilinx_post_fn post;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_init_fn init;
+ xilinx_err_fn err;
+ xilinx_done_fn done;
+ xilinx_clk_fn clk;
+ xilinx_cs_fncs;
+ xilinx_wr_fnwr;
+ xilinx_rdata_fn rdata;
+ xilinx_wdata_fn wdata;
+ xilinx_busy_fn busy;
+ xilinx_abort_fn abort;
+ xilinx_post_fn post;
} xilinx_virtex2_slave_selectmap_fns;
/* Slave Serial Implementation function table */
typedef struct {
- Xilinx_pgm_fn pgm;
- Xilinx_clk_fn clk;
-
[U-Boot] [RFC PATCH 4/6] fpga: xilinx: Avoid CamelCase for in Xilinx_desc
No functional changes.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
board/armadeus/apf27/fpga.c | 2 +-
board/astro/mcf5373l/fpga.c | 2 +-
board/balloon3/balloon3.c| 2 +-
board/esd/pmc440/fpga.c | 2 +-
board/gen860t/fpga.c | 2 +-
board/matrix_vision/mvsmr/fpga.c | 2 +-
board/spear/x600/fpga.c | 2 +-
board/teejet/mt_ventoux/mt_ventoux.c | 2 +-
board/xilinx/zynq/board.c| 14 +++---
drivers/fpga/spartan2.c | 26 +-
drivers/fpga/spartan3.c | 26 +-
drivers/fpga/virtex2.c | 22 +++---
drivers/fpga/xilinx.c| 14 +++---
drivers/fpga/zynqpl.c| 6 +++---
include/spartan2.h | 6 +++---
include/spartan3.h | 6 +++---
include/virtex2.h| 6 +++---
include/xilinx.h | 10 +-
include/zynqpl.h | 6 +++---
19 files changed, 79 insertions(+), 79 deletions(-)
diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c
index 56fde20..7d6e1e4 100644
--- a/board/armadeus/apf27/fpga.c
+++ b/board/armadeus/apf27/fpga.c
@@ -42,7 +42,7 @@ xilinx_spartan3_slave_parallel_fns fpga_fns = {
fpga_post_fn,
};
-Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
{xilinx_spartan3,
slave_parallel,
1196128l/8,
diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c
index 152ff1f..9dc82c5 100644
--- a/board/astro/mcf5373l/fpga.c
+++ b/board/astro/mcf5373l/fpga.c
@@ -374,7 +374,7 @@ xilinx_spartan3_slave_serial_fns xilinx_fns = {
xilinx_fastwr_fn
};
-Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
+xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
{xilinx_spartan3,
slave_serial,
XILINX_XC3S4000_SIZE,
diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c
index 4aa6605..aa108ca 100644
--- a/board/balloon3/balloon3.c
+++ b/board/balloon3/balloon3.c
@@ -207,7 +207,7 @@ xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = {
fpga_post_config_fn,
};
-Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
+xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
(void *)balloon3_fpga_fns, 0);
/* Initialize the FPGA */
diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c
index 18a1b63..f876da8 100644
--- a/board/esd/pmc440/fpga.c
+++ b/board/esd/pmc440/fpga.c
@@ -57,7 +57,7 @@ xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = {
ngcc_fpga_post_config_fn
};
-Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
XILINX_XC3S1200E_DESC(
#ifdef USE_SP_CODE
slave_parallel,
diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c
index 48a4222..dd0ef70 100644
--- a/board/gen860t/fpga.c
+++ b/board/gen860t/fpga.c
@@ -56,7 +56,7 @@ xilinx_virtex2_slave_selectmap_fns fpga_fns = {
fpga_post_config_fn
};
-Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
{xilinx_virtex2,
slave_selectmap,
XILINX_XC2V3000_SIZE,
diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c
index b207455..5189925 100644
--- a/board/matrix_vision/mvsmr/fpga.c
+++ b/board/matrix_vision/mvsmr/fpga.c
@@ -26,7 +26,7 @@ xilinx_spartan3_slave_serial_fns fpga_fns = {
0
};
-Xilinx_desc spartan3 = {
+xilinx_desc spartan3 = {
xilinx_spartan2,
slave_serial,
XILINX_XC3S200_SIZE,
diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c
index c26eba4..b256222 100644
--- a/board/spear/x600/fpga.c
+++ b/board/spear/x600/fpga.c
@@ -173,7 +173,7 @@ static xilinx_spartan3_slave_serial_fns x600_fpga_fns = {
fpga_post_config_fn,
};
-static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+static xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
XILINX_XC3S1200E_DESC(slave_serial, x600_fpga_fns, 0)
};
diff --git a/board/teejet/mt_ventoux/mt_ventoux.c
b/board/teejet/mt_ventoux/mt_ventoux.c
index a361764..b4a0a72 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.c
+++ b/board/teejet/mt_ventoux/mt_ventoux.c
@@ -200,7 +200,7 @@ xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = {
fpga_post_config_fn,
};
-Xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
+xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
(void *)mt_ventoux_fpga_fns, 0);
/* Initialize the FPGA */
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 485a5e4..c8cc2bc 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -14,15 +14,15 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FPGA
-Xilinx_desc fpga;
+xilinx_desc fpga;
/* It can be done differently */
-Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
-Xilinx_desc fpga015 =
Re: [U-Boot] [PATCH] powerpc/t208x: enable command MEMTEST DDR_INTERACTIVE EEPROM
On 03/13/2014 12:10 AM, Wolfgang Denk wrote: Dear York Sun, In message 88c8c779-b636-4abf-9751-33e471307...@freescale.com you wrote: On Mar 12, 2014, at 8:17 PM, Shengzhou Liu wrote: Enable CONFIG_CMD_MEMTEST, CONFIG_FSL_DDR_INTERACTIVE, CONFIG_CMD_EEPROM I can see the ddr debugging and eeprom command are useful. But I am not convinced memtest is effective as it is intended to be. There was a discussion a while ago. Except for some very specific cases (like watching signals on a scope while running the test) memtest is almost totally worthless. Wolfgang, Thanks. I will info our internal team to phase out memtest. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: Handle .gnu.hash section in ldscripts
Hi Albert, Andreas, Hi Andreas, On Sun, 09 Mar 2014 21:52:44 +0100, Andreas Färber afaer...@suse.de wrote: Hi, Am 09.03.2014 21:34, schrieb Albert ARIBAUD: On Sun, 09 Mar 2014 21:22:34 +0100, Andreas Färber afaer...@suse.de wrote: Am 09.03.2014 21:05, schrieb Albert ARIBAUD: On Mon, 3 Mar 2014 08:00:52 +0100, Albert ARIBAUD albert.u.b...@aribaud.net wrote: On Sun, 02 Mar 2014 23:00:19 +0100, Andreas Färber afaer...@suse.de wrote: Am 02.03.2014 21:57, schrieb Andreas Färber: Am 02.03.2014 20:15, schrieb Albert ARIBAUD: On Sun, 02 Mar 2014 18:57:14 +0100, Andreas Färber afaer...@suse.de wrote: Am 22.02.2014 14:27, schrieb Albert ARIBAUD: On Thu, 13 Feb 2014 12:39:07 +0100, Albert ARIBAUD albert.u.b...@aribaud.net wrote: Can you point me to the toolchain you are using, and if you are not building mainline code, can you make this code available to me somehow? [...] Our latest GCC 4.8.2 can be found here: https://build.opensuse.org/package/show/openSUSE:Factory:ARM/gcc48 Matching binutils 2.24 are here: https://build.opensuse.org/package/show/openSUSE:Factory:ARM/binutils Our latest U-Boot tarball and patches: https://build.opensuse.org/package/show/Base:System/u-boot Build logs can be found in the u-boot-* packages in the same project, with underscores stripped, e.g.: https://build.opensuse.org/package/show/Base:System/u-boot-am335xevm Thanks for your reply. Apparently, the problem does not appear for the boards in mainline U-Boot which I listed above with the source code from our v2014.01 tag and using gcc 4.8.1 from Linaro. I can install 4.8.2, but meanwhile, can you try to build v2014.01 for these boards with your setup? am335x_evm colibri_t20_iris highbank mx53loco omap3_beagle omap4_panda paz00 rpi_b I have commented out the patch in: https://build.opensuse.org/project/show/home:a_faerber:branches:Base:System While there are apparently frequent rebuilds scheduled ATM, it seemed like the colibri_t20_iris config intermittently built OK without it. Maybe some gcc 4.8 stable branch update [1] resolved it ... will keep an eye on the build status to confirm. If everything builds, I'm happy. Nah, still fails without the patch: [ 178s] gcc -E -g -Os -ffunction-sections -fdata-sections -fno-common -ffixed-r9 -msoft-float -D__KERNEL__ -DCONFIG_SYS_TEXT_BASE=0x0010E000 -I/home/abuild/rpmbuild/BUILD/u-boot-2014.01/include -I/home/abuild/rpmbuild/BUILD/u-boot-2014.01/arch/arm/include -fno-builtin -ffreestanding -nostdinc -isystem /usr/lib/gcc/armv7hl-suse-linux-gnueabi/4.8/include -pipe -DCONFIG_ARM -D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux -mword-relocations -march=armv7-a -include /home/abuild/rpmbuild/BUILD/u-boot-2014.01/include/u-boot/u-boot.lds.h -DCPUDIR=arch/arm/cpu/armv7 -ansi -D__ASSEMBLY__ -P - /home/abuild/rpmbuild/BUILD/u-boot-2014.01/arch/arm/cpu/u-boot.lds u-boot.lds [ 178s] cd /home/abuild/rpmbuild/BUILD/u-boot-2014.01 ld.bfd -pie -T u-boot.lds --gc-sections -Bstatic -Ttext 0x0010E000 arch/arm/cpu/armv7/start.o --start-group arch/arm/cpu/armv7/built-in.o arch/arm/cpu/armv7/tegra20/built-in.o arch/arm/cpu/built-in.o arch/arm/lib/built-in.o board/toradex/colibri_t20_iris/built-in.o common/built-in.o disk/built-in.o drivers/built-in.o drivers/dma/built-in.o drivers/gpio/built-in.o drivers/i2c/built-in.o drivers/input/built-in.o drivers/mmc/built-in.o drivers/mtd/built-in.o drivers/mtd/nand/built-in.o drivers/mtd/onenand/built-in.o drivers/mtd/spi/built-in.o drivers/net/built-in.o drivers/net/phy/built-in.o drivers/pci/built-in.o drivers/power/battery/built-in.o drivers/power/built-in.o drivers/power/fuel_gauge/built-in.o drivers/power/mfd/built-in.o drivers/power/pmic/built-in.o drivers/serial/built-in.o drivers/spi/built-in.o drivers/usb/eth/built-in.o drivers/usb/gadget/built-in.o drivers/usb/host/built-in.o drivers/usb/musb-new/built-in.o drivers/usb/musb/built-in.o drivers/usb/phy/built-in.o drivers/usb/ulpi/built-in.o fs/built-in.o lib/built-in.o lib/libfdt/built-in.o net/built-in.o test/built-in.o --end-group /home/abuild/rpmbuild/BUILD/u-boot-2014.01/arch/arm/lib/eabi_compat.o -L /usr/lib/gcc/armv7hl-suse-linux-gnueabi/4.8 -lgcc -Map u-boot.map -o u-boot [ 178s] ld.bfd: u-boot: could not find output section .gnu.hash [ 178s] ld.bfd: final link failed: Nonrepresentable section on output [ 178s] Makefile:556: recipe for target 'u-boot' failed [ 178s] make: *** [u-boot] Error 1 You are trying this with your codebase, right? If so, can you try and build vanilla v2014.01 with the exact same build environment? Commented out all our patches at: https://build.opensuse.org/project/show/home:a_faerber:branches:Base:System Failure of any sunxi-added targets is
Re: [U-Boot] Please pull u-boot-ti/master
Hi Tom, On Wed, 12 Mar 2014 16:23:11 -0400, Tom Rini tr...@ti.com wrote: On Wed, Mar 12, 2014 at 04:05:05PM -0400, Tom Rini wrote: Hey, The following changes since commit 8ee950dd273aef6a074d41bf2ee4ef11d6f848fb: Prepare v2014.04-rc2 (2014-03-10 17:21:06 -0400) are available in the git repository at: git://git.denx.de/u-boot-ti.git master for you to fetch changes up to d157776388b2b6cb819e76a56d3c63e604d8b291: arm: am335x: DXR2: Move unconditional LAN9303 reset into command (2014-03-12 14:51:45 -0400) Ooops, updated as.. The following changes since commit 8ee950dd273aef6a074d41bf2ee4ef11d6f848fb: Prepare v2014.04-rc2 (2014-03-10 17:21:06 -0400) are available in the git repository at: git://git.denx.de/u-boot-ti.git master for you to fetch changes up to aadf3192f83a55dbbdb0d395ee5af88b6560edcb: board/BuR/kwb: fix usage of 'i2c_set_bus_speed' (2014-03-12 16:22:16 -0400) Hannes Petermaier (1): board/BuR/kwb: fix usage of 'i2c_set_bus_speed' Ilya Ledvich (1): drivers: net: cpsw: init phy with gigabit features Stefan Roese (2): arm: omap: cm_t35: Fix: Re-add GPMC_NAND_ECC_LP_x8_LAYOUT arm: am335x: DXR2: Move unconditional LAN9303 reset into command Tom Rini (2): am33xx: Rework #ifdef's around s_init for clarity am335x_evm: Remove SPI SPL from NOR support target Vasili Galka (1): drivers/spi/omap3: Bug fix of premature write transfer completion arch/arm/cpu/armv7/am33xx/board.c |8 +++- board/BuR/kwb/board.c |4 ++-- board/siemens/dxr2/board.c| 26 +++--- drivers/net/cpsw.c|6 +- drivers/spi/omap3_spi.c |5 +++-- include/configs/am335x_evm.h |2 ++ include/configs/cm_t35.h |2 ++ 7 files changed, 32 insertions(+), 21 deletions(-) Applied to u-boot-arm/master, thanks! Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PULL] : Please pull u-boot-imx
Hi Stefano, On Wed, 12 Mar 2014 11:44:25 +0100, Stefano Babic sba...@denx.de wrote: Hi Albert, please pull from u-boot-imx, thanks ! The following changes since commit cc07294bc704694ae33db75b25ac557e5917a83f: arm: am335x: DXR2: Reset SMSC LAN9303 switch via GPIO upon bootup (2014-03-04 09:42:07 -0500) are available in the git repository at: git://www.denx.de/git/u-boot-imx.git master for you to fetch changes up to 81a1d6173cd255c5c04c332ed69498c6e173515f: mx25pdk: Align the environment with other FSL boards (2014-03-12 11:19:23 +0100) Fabio Estevam (6): wandboard: Staticize usdhc1_pads mmc: Add a prototype for board_mmc_init() wandboard: Fix sparse warning wandboard: Include input.h fb: Add a prototype for board_video_skip() mx25pdk: Align the environment with other FSL boards Stefano Babic (1): Merge branch 'master' of git://git.denx.de/u-boot-arm Tim Harvey (2): power: add PFUZE100 PMIC driver ventana: Add Gateworks Ventana family support board/gateworks/gw_ventana/Makefile | 10 + board/gateworks/gw_ventana/README | 55 ++ board/gateworks/gw_ventana/clocks.cfg | 42 + board/gateworks/gw_ventana/gsc.c| 129 +++ board/gateworks/gw_ventana/gsc.h| 64 ++ board/gateworks/gw_ventana/gw_ventana.c | 1263 +++ board/gateworks/gw_ventana/gw_ventana.cfg | 44 + board/gateworks/gw_ventana/ventana_eeprom.h | 106 +++ board/wandboard/wandboard.c |4 +- boards.cfg |5 + drivers/power/pmic/Makefile |1 + drivers/power/pmic/pmic_pfuze100.c | 32 + include/configs/gw_ventana.h| 425 + include/configs/mx25pdk.h | 103 ++- include/linux/fb.h |2 + include/mmc.h |2 + include/phy.h |2 + include/power/pfuze100_pmic.h | 96 ++ 18 files changed, 2379 insertions(+), 6 deletions(-) create mode 100644 board/gateworks/gw_ventana/Makefile create mode 100644 board/gateworks/gw_ventana/README create mode 100644 board/gateworks/gw_ventana/clocks.cfg create mode 100644 board/gateworks/gw_ventana/gsc.c create mode 100644 board/gateworks/gw_ventana/gsc.h create mode 100644 board/gateworks/gw_ventana/gw_ventana.c create mode 100644 board/gateworks/gw_ventana/gw_ventana.cfg create mode 100644 board/gateworks/gw_ventana/ventana_eeprom.h create mode 100644 drivers/power/pmic/pmic_pfuze100.c create mode 100644 include/configs/gw_ventana.h create mode 100644 include/power/pfuze100_pmic.h Applied to u-boot-arm/master, thanks! Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 3/3] cmd:gpt: randomly generate each partition uuid if undefined
Hello,
Sorry for silent, but I've had some other work.
I agree with yours previous comments and those will apply to v3 but I
don't agree with few comments to this patch.
On 03/10/2014 06:44 PM, Stephen Warren wrote:
On 03/05/2014 09:45 AM, Przemyslaw Marczak wrote:
Changes:
- randomly generate each partition uuid if undefined
- print info about generated uuid
- save environment on gpt write success
- update doc/README.gpt
diff --git a/common/cmd_gpt.c b/common/cmd_gpt.c
-static char extract_env(const char *str, char **env)
+static int extract_env(const char *str, char **env)
{
+ int ret = -1;
char *e, *s;
+ char uuid_str[37];
if (!str || strlen(str) 4)
return -1;
@@ -43,16 +45,25 @@ static char extract_env(const char *str, char **env)
memset(s + strlen(s) - 1, '\0', 1);
memmove(s, s + 2, strlen(s) - 1);
e = getenv(s);
- free(s);
if (e == NULL) {
- printf(Environmental '%s' not set\n, str);
- return -1; /* env not set */
+ printf(%s unset. , str);
+ gen_rand_uuid_str(uuid_str);
+ setenv(s, uuid_str);
+
In this place ret is -1.
+ e = getenv(s);
+ if (e) {
+ puts(Setting to random.\n);
Shouldn't this be printed right after the if (e == NULL) check above?
That's where the decision is made to generate a random UUID.
Here, if (!e), the code should return an error.
If (!e) then ret is still -1.
If (e) then ret = 0 and proper info is printed.
But, I still don't like changing the environment. Why can't the above
few lines be:
+ gen_rand_uuid_str(uuid_str);
+ e = uuid_str;
Such solution needs more code rewriting and breaking some existing
cmd_gpt design. e is used outside this function but uuid_str is local
here. I don't like to make it static.
Using getenv and return its pointer will work the same as previous.
Please note that variables set by user are not overwritten here so this
code will only set null uuid env variables. Moreover user can see after
gpt command that environment is the same with mmc part shows, I think it
is useful instead of situation when uuid is set but not present in
environment.
diff --git a/doc/README.gpt b/doc/README.gpt
uuid program is recommended to generate UUID string. Moreover it can decode
(-d switch) passed in UUID string. It can be used to generate partitions UUID
passed to u-boot environment variables.
+If each partition uuid no exists then it will be randomly generated.
If each means if all of them, implying that it's an all-or-nothing
solution, and the random generation only happens of none of the UUIDs
were supplied, not on a UUID-by-UUID basis. So, s/each/a/ or s/each/any/.
Ok :)
Thanks
--
Przemyslaw Marczak
Samsung RD Institute Poland
Samsung Electronics
p.marc...@samsung.com
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Re: [U-Boot] [PATCH] arm: Handle .gnu.hash section in ldscripts
Hi Lukasz, On Thu, 13 Mar 2014 16:43:09 +0100, Lukasz Majewski l.majew...@samsung.com wrote: I can report the same issue with OBS build of u-boot. When u-boot is build with qemu emulated environment with gcc-4.8.2 (native armv7l toolchain) in the OBS it needs patch prepared by Andreas. Hmm, ok, so maybe I can reproduce this by building U-Boot on native armv7 hardware. Any target which systematically fails building? However I can build the same code from u-boot directory (without this patch) with following toolchain: arm-v7a-linux-gnueabi-gcc (OSELAS.Toolchain-2013.12.0 linaro-4.8-2013.11) 4.8.3 2013 Hmm... So it depends on the toolchain. Any ideas how to solve this? Are both toolchains you used available somewhere so that I can fetch them and experiment locally? Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 01/11] ARM: tegra: pinctrl: remove func_safe
From: Stephen Warren swar...@nvidia.com
This field isn't used anywhere, so remove it. Note that PIN() macros are
left unchanged for now, to avoid many diffs to them; later commits will
completely rewrite them just one time.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/cpu/tegra114-common/pinmux.c | 6 --
arch/arm/cpu/tegra124-common/pinmux.c | 6 --
arch/arm/cpu/tegra20-common/pinmux.c| 2 --
arch/arm/cpu/tegra30-common/pinmux.c| 6 --
arch/arm/include/asm/arch-tegra114/pinmux.h | 1 -
arch/arm/include/asm/arch-tegra124/pinmux.h | 1 -
arch/arm/include/asm/arch-tegra20/pinmux.h | 1 -
arch/arm/include/asm/arch-tegra30/pinmux.h | 1 -
8 files changed, 24 deletions(-)
diff --git a/arch/arm/cpu/tegra114-common/pinmux.c
b/arch/arm/cpu/tegra114-common/pinmux.c
index 4983a05090a2..7bf494c49a4d 100644
--- a/arch/arm/cpu/tegra114-common/pinmux.c
+++ b/arch/arm/cpu/tegra114-common/pinmux.c
@@ -24,7 +24,6 @@
struct tegra_pingroup_desc {
const char *name;
enum pmux_func funcs[4];
- enum pmux_func func_safe;
enum pmux_vddio vddio;
enum pmux_pin_io io;
};
@@ -62,7 +61,6 @@ struct tegra_pingroup_desc {
PMUX_FUNC_ ## f2, \
PMUX_FUNC_ ## f3, \
}, \
- .func_safe = PMUX_FUNC_RSVD1, \
.io = PMUX_PIN_ ## iod, \
}
@@ -396,10 +394,6 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func
func)
assert(pmux_pingrp_isvalid(pin));
assert(pmux_func_isvalid(func));
- /* Handle special values */
- if (func == PMUX_FUNC_SAFE)
- func = tegra_soc_pingroups[pin].func_safe;
-
if (func PMUX_FUNC_RSVD1) {
mux = func 0x3;
} else {
diff --git a/arch/arm/cpu/tegra124-common/pinmux.c
b/arch/arm/cpu/tegra124-common/pinmux.c
index a4ab4eae408f..b1ac59e5b3c9 100644
--- a/arch/arm/cpu/tegra124-common/pinmux.c
+++ b/arch/arm/cpu/tegra124-common/pinmux.c
@@ -15,7 +15,6 @@
struct tegra_pingroup_desc {
const char *name;
enum pmux_func funcs[4];
- enum pmux_func func_safe;
enum pmux_vddio vddio;
enum pmux_pin_io io;
};
@@ -53,7 +52,6 @@ struct tegra_pingroup_desc {
PMUX_FUNC_ ## f2, \
PMUX_FUNC_ ## f3, \
}, \
- .func_safe = PMUX_FUNC_RSVD1, \
.io = PMUX_PIN_ ## iod, \
}
@@ -387,10 +385,6 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func
func)
assert(pmux_pingrp_isvalid(pin));
assert(pmux_func_isvalid(func));
- /* Handle special values */
- if (func == PMUX_FUNC_SAFE)
- func = tegra_soc_pingroups[pin].func_safe;
-
if (func PMUX_FUNC_RSVD1) {
mux = func 0x3;
} else {
diff --git a/arch/arm/cpu/tegra20-common/pinmux.c
b/arch/arm/cpu/tegra20-common/pinmux.c
index a65e9915194e..1f04d9c7ff7d 100644
--- a/arch/arm/cpu/tegra20-common/pinmux.c
+++ b/arch/arm/cpu/tegra20-common/pinmux.c
@@ -259,7 +259,6 @@ enum pmux_pullid {
struct tegra_pingroup_desc {
const char *name;
enum pmux_func funcs[4];
- enum pmux_func func_safe;
enum pmux_vddio vddio;
enum pmux_ctlid ctl_id;
enum pmux_pullid pull_id;
@@ -294,7 +293,6 @@ struct tegra_pingroup_desc {
PMUX_FUNC_ ## f2, \
PMUX_FUNC_ ## f3, \
}, \
- .func_safe = PMUX_FUNC_ ## f_safe, \
.ctl_id = mux, \
.pull_id = pupd \
}
diff --git a/arch/arm/cpu/tegra30-common/pinmux.c
b/arch/arm/cpu/tegra30-common/pinmux.c
index eecf0580bc90..6fd424981c23 100644
--- a/arch/arm/cpu/tegra30-common/pinmux.c
+++ b/arch/arm/cpu/tegra30-common/pinmux.c
@@ -24,7 +24,6 @@
struct tegra_pingroup_desc {
const char *name;
enum pmux_func funcs[4];
- enum pmux_func func_safe;
enum pmux_vddio vddio;
enum pmux_pin_io io;
};
@@ -61,7 +60,6 @@ struct tegra_pingroup_desc {
PMUX_FUNC_ ## f2, \
PMUX_FUNC_ ## f3, \
}, \
- .func_safe = PMUX_FUNC_RSVD1, \
.io = PMUX_PIN_ ## iod, \
}
@@ -381,10 +379,6 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func
func)
assert(pmux_pingrp_isvalid(pin));
assert(pmux_func_isvalid(func));
- /* Handle special values */
- if (func == PMUX_FUNC_SAFE)
-
[U-Boot] [PATCH 03/11] ARM: tegra: pinctrl: make pmux_func values consistent on Tegra20
From: Stephen Warren swar...@nvidia.com
For consistency with other SoCs, modify Tegra20's enum pmux_func to:
* Remove PMUX_FUNC values that aren't real
* Use the same PMUX_FUNC_RSVD[1-4] values, and ensure (RSVD1 3)==0;
this will be assumed by pinmux_set_func() in a future patch.
Unfortunately, PMUX_FUNC_RSVD is still used in the pin macros. Use a
private define inside the driver to prevent this from causing compilaton
errors. This will be cleaned up when the pin tables are re-written in a
later patch in this series.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/cpu/tegra20-common/pinmux.c | 4 +++-
arch/arm/include/asm/arch-tegra20/pinmux.h | 17 +++--
2 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/tegra20-common/pinmux.c
b/arch/arm/cpu/tegra20-common/pinmux.c
index 40301e13c29d..14467f01f547 100644
--- a/arch/arm/cpu/tegra20-common/pinmux.c
+++ b/arch/arm/cpu/tegra20-common/pinmux.c
@@ -307,7 +307,9 @@ struct tegra_pingroup_desc {
/* A pin group number which is not used */
#define PIN_RESERVED \
- PIN(NONE, NONE, NONE, NONE, NONE, NONE, NONE)
+ PIN(NONE, NONE, RSVD, RSVD, RSVD, RSVD, RSVD)
+
+#define PMUX_FUNC_RSVD ((enum pmux_func)-1)
const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
PIN(ATA, NAND, IDE,NAND, GMI, RSVD,IDE),
diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h
b/arch/arm/include/asm/arch-tegra20/pinmux.h
index 2bfaf53d349d..1980201ce8cc 100644
--- a/arch/arm/include/asm/arch-tegra20/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra20/pinmux.h
@@ -228,21 +228,18 @@ enum pmux_func {
PMUX_FUNC_VI_SENSOR_CLK,
PMUX_FUNC_XIO,
- /* These don't have a name, but can be used in the table */
- PMUX_FUNC_RSVD1,
- PMUX_FUNC_RSVD2,
- PMUX_FUNC_RSVD3,
- PMUX_FUNC_RSVD4,
- PMUX_FUNC_RSVD, /* Not valid and should not be used */
-
PMUX_FUNC_COUNT,
- PMUX_FUNC_NONE = -1,
+ PMUX_FUNC_RSVD1 = 0x8000,
+ PMUX_FUNC_RSVD2 = 0x8001,
+ PMUX_FUNC_RSVD3 = 0x8002,
+ PMUX_FUNC_RSVD4 = 0x8003,
};
/* return 1 if a pmux_func is in range */
-#define pmux_func_isvalid(func) ((func) = 0 (func) PMUX_FUNC_COUNT \
- (func) != PMUX_FUNC_RSVD)
+#define pmux_func_isvalid(func) \
+ func) = 0) ((func) PMUX_FUNC_COUNT)) ||\
+(((func) = PMUX_FUNC_RSVD1) ((func) = PMUX_FUNC_RSVD4)))
/* The pullup/pulldown state of a pin group */
enum pmux_pull {
--
1.8.1.5
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[U-Boot] [PATCH 00/11] ARM: tegra: pinmux driver cleanup
From: Stephen Warren swar...@nvidia.com This series: a) Removes some unused cruft from the Tegra pinmux drivers. b) Creates a single implementation of the Tegra pinmux API thus removing a lot of duplicate code. c) Auto-generates the Tegra30/114/124 pinmux data from the same data source used to auto-generate the Linux kernel pinmux drivers. This ensures that the two SW stacks are consistent. The data source has also been validated against the TRM, and some issues in the existing U-Boot data tables are fixed due to this. (a) and (b) together remove over 1600 lines of code! So far, I haven't looked at the content of the per-board pinmux config tables in detail; I've just fixed issues in the drivers. I will be validating the board configurations next, and will send patches to fix any issues I find in those too. Stephen Warren (11): ARM: tegra: pinctrl: remove func_safe ARM: tegra: pinctrl: remove vddio ARM: tegra: pinctrl: make pmux_func values consistent on Tegra20 ARM: tegra: prototype pinmux_init() in board.h ARM: tegra: pinctrl: remove duplication ARM: tegra: reduce public pinmux API ARM: tegra: pinmux naming consistency fixes ARM: tegra: Tegra20 pinmux cleanup ARM: tegra: Tegra30 pinmux cleanup ARM: tegra: Tegra114 pinmux cleanup ARM: tegra: Tegra124 pinmux cleanup arch/arm/cpu/arm720t/tegra-common/spl.c| 4 +- arch/arm/cpu/arm720t/tegra114/cpu.c| 4 +- arch/arm/cpu/arm720t/tegra124/cpu.c| 4 +- arch/arm/cpu/tegra-common/Makefile | 6 +- arch/arm/cpu/tegra-common/pinmux-common.c | 509 +++ arch/arm/cpu/tegra114-common/funcmux.c | 32 +- arch/arm/cpu/tegra114-common/pinmux.c | 895 +-- arch/arm/cpu/tegra124-common/funcmux.c | 38 +- arch/arm/cpu/tegra124-common/pinmux.c | 898 +-- arch/arm/cpu/tegra20-common/funcmux.c | 185 ++-- arch/arm/cpu/tegra20-common/pinmux.c | 416 +++-- arch/arm/cpu/tegra20-common/warmboot.c | 5 +- arch/arm/cpu/tegra20-common/warmboot_avp.c | 4 +- arch/arm/cpu/tegra30-common/funcmux.c | 20 +- arch/arm/cpu/tegra30-common/pinmux.c | 948 ++-- arch/arm/include/asm/arch-tegra/board.h| 1 + arch/arm/include/asm/arch-tegra/pinmux.h | 185 arch/arm/include/asm/arch-tegra114/pinmux.h| 828 ++ arch/arm/include/asm/arch-tegra124/pinmux.h| 858 +++--- arch/arm/include/asm/arch-tegra20/pinmux.h | 380 +++- arch/arm/include/asm/arch-tegra30/pinmux.h | 955 - .../common/pinmux-config-tamonten-ng.h | 492 +-- board/avionic-design/common/tamonten-ng.c | 12 +- board/avionic-design/common/tamonten.c | 4 +- board/compal/paz00/paz00.c | 22 +- board/compulab/trimslice/trimslice.c | 4 +- board/nvidia/cardhu/cardhu.c | 6 +- board/nvidia/cardhu/pinmux-config-cardhu.h | 498 +-- board/nvidia/common/board.c| 8 +- board/nvidia/dalmore/dalmore.c | 9 +- board/nvidia/dalmore/pinmux-config-dalmore.h | 388 - board/nvidia/harmony/harmony.c | 18 +- board/nvidia/seaboard/seaboard.c | 6 +- board/nvidia/venice2/pinmux-config-venice2.h | 360 board/nvidia/venice2/venice2.c | 15 +- .../colibri_t20-common/colibri_t20-common.c| 8 +- board/toradex/colibri_t20_iris/colibri_t20_iris.c | 4 +- drivers/spi/tegra20_sflash.c | 6 +- drivers/video/tegra.c | 4 +- 39 files changed, 3694 insertions(+), 5345 deletions(-) create mode 100644 arch/arm/cpu/tegra-common/pinmux-common.c create mode 100644 arch/arm/include/asm/arch-tegra/pinmux.h -- 1.8.1.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 02/11] ARM: tegra: pinctrl: remove vddio
From: Stephen Warren swar...@nvidia.com
This field isn't used anywhere, so remove it. Note that PIN() macros are
left unchanged for now, to avoid many diffs to them; later commits will
completely rewrite them just one time.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/cpu/tegra114-common/pinmux.c | 2 --
arch/arm/cpu/tegra124-common/pinmux.c | 2 --
arch/arm/cpu/tegra20-common/pinmux.c| 2 --
arch/arm/cpu/tegra30-common/pinmux.c| 2 --
arch/arm/include/asm/arch-tegra114/pinmux.h | 21 -
arch/arm/include/asm/arch-tegra124/pinmux.h | 21 -
arch/arm/include/asm/arch-tegra20/pinmux.h | 15 ---
arch/arm/include/asm/arch-tegra30/pinmux.h | 21 -
8 files changed, 86 deletions(-)
diff --git a/arch/arm/cpu/tegra114-common/pinmux.c
b/arch/arm/cpu/tegra114-common/pinmux.c
index 7bf494c49a4d..e83a29f43a5f 100644
--- a/arch/arm/cpu/tegra114-common/pinmux.c
+++ b/arch/arm/cpu/tegra114-common/pinmux.c
@@ -24,7 +24,6 @@
struct tegra_pingroup_desc {
const char *name;
enum pmux_func funcs[4];
- enum pmux_vddio vddio;
enum pmux_pin_io io;
};
@@ -54,7 +53,6 @@ struct tegra_pingroup_desc {
/* Convenient macro for defining pin group properties */
#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
{ \
- .vddio = PMUX_VDDIO_ ## vdd,\
.funcs = { \
PMUX_FUNC_ ## f0, \
PMUX_FUNC_ ## f1, \
diff --git a/arch/arm/cpu/tegra124-common/pinmux.c
b/arch/arm/cpu/tegra124-common/pinmux.c
index b1ac59e5b3c9..921dd2119b10 100644
--- a/arch/arm/cpu/tegra124-common/pinmux.c
+++ b/arch/arm/cpu/tegra124-common/pinmux.c
@@ -15,7 +15,6 @@
struct tegra_pingroup_desc {
const char *name;
enum pmux_func funcs[4];
- enum pmux_vddio vddio;
enum pmux_pin_io io;
};
@@ -45,7 +44,6 @@ struct tegra_pingroup_desc {
/* Convenient macro for defining pin group properties */
#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
{ \
- .vddio = PMUX_VDDIO_ ## vdd,\
.funcs = { \
PMUX_FUNC_ ## f0, \
PMUX_FUNC_ ## f1, \
diff --git a/arch/arm/cpu/tegra20-common/pinmux.c
b/arch/arm/cpu/tegra20-common/pinmux.c
index 1f04d9c7ff7d..40301e13c29d 100644
--- a/arch/arm/cpu/tegra20-common/pinmux.c
+++ b/arch/arm/cpu/tegra20-common/pinmux.c
@@ -259,7 +259,6 @@ enum pmux_pullid {
struct tegra_pingroup_desc {
const char *name;
enum pmux_func funcs[4];
- enum pmux_vddio vddio;
enum pmux_ctlid ctl_id;
enum pmux_pullid pull_id;
};
@@ -286,7 +285,6 @@ struct tegra_pingroup_desc {
/* Convenient macro for defining pin group properties */
#define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd)
\
{ \
- .vddio = PMUX_VDDIO_ ## vdd,\
.funcs = { \
PMUX_FUNC_ ## f0, \
PMUX_FUNC_ ## f1, \
diff --git a/arch/arm/cpu/tegra30-common/pinmux.c
b/arch/arm/cpu/tegra30-common/pinmux.c
index 6fd424981c23..8eca0dd65485 100644
--- a/arch/arm/cpu/tegra30-common/pinmux.c
+++ b/arch/arm/cpu/tegra30-common/pinmux.c
@@ -24,7 +24,6 @@
struct tegra_pingroup_desc {
const char *name;
enum pmux_func funcs[4];
- enum pmux_vddio vddio;
enum pmux_pin_io io;
};
@@ -53,7 +52,6 @@ struct tegra_pingroup_desc {
/* Convenient macro for defining pin group properties */
#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
{ \
- .vddio = PMUX_VDDIO_ ## vdd,\
.funcs = { \
PMUX_FUNC_ ## f0, \
PMUX_FUNC_ ## f1, \
diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h
b/arch/arm/include/asm/arch-tegra114/pinmux.h
index edf1a89ce111..93d2ca525cec 100644
--- a/arch/arm/include/asm/arch-tegra114/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra114/pinmux.h
@@ -449,27 +449,6 @@ enum pmux_pin_rcv_sel {
(((rcv_sel) = PMUX_PIN_RCV_SEL_DEFAULT) \
((rcv_sel) = PMUX_PIN_RCV_SEL_HIGH))
-/* Available power domains used by pin groups */
-enum pmux_vddio {
- PMUX_VDDIO_BB = 0,
- PMUX_VDDIO_LCD,
- PMUX_VDDIO_VI,
- PMUX_VDDIO_UART,
- PMUX_VDDIO_DDR,
- PMUX_VDDIO_NAND,
- PMUX_VDDIO_SYS,
- PMUX_VDDIO_AUDIO,
- PMUX_VDDIO_SD,
-
[U-Boot] [PATCH 06/11] ARM: tegra: reduce public pinmux API
From: Stephen Warren swar...@nvidia.com
Remove a few unused functions from the pinmux header. They aren't
currently used, and removing them prevents any new usage from appearing.
This will ease moving to just pinmux_config_table() and
padgrp_config_table() in the future.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/cpu/tegra-common/pinmux-common.c | 4 ++--
arch/arm/include/asm/arch-tegra/pinmux.h | 6 --
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c
b/arch/arm/cpu/tegra-common/pinmux-common.c
index 10f68ba98b52..51ba6eecdfab 100644
--- a/arch/arm/cpu/tegra-common/pinmux-common.c
+++ b/arch/arm/cpu/tegra-common/pinmux-common.c
@@ -131,7 +131,7 @@ void pinmux_set_pullupdown(enum pmux_pingrp pin, enum
pmux_pull pupd)
writel(val, reg);
}
-void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
+static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
{
u32 *reg = TRI_REG(pin);
u32 val;
@@ -275,7 +275,7 @@ static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
#endif /* TEGRA_PMX_HAS_RCV_SEL */
#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
-void pinmux_config_pingroup(const struct pingroup_config *config)
+static void pinmux_config_pingroup(const struct pingroup_config *config)
{
enum pmux_pingrp pin = config-pingroup;
diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h
b/arch/arm/include/asm/arch-tegra/pinmux.h
index e97fffdcf87b..b8d21c1bf92f 100644
--- a/arch/arm/include/asm/arch-tegra/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra/pinmux.h
@@ -86,9 +86,6 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func
func);
/* Set the pull up/down feature for a pin group */
void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
-/* Set a pin group to tristate or normal */
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
-
/* Set a pin group to tristate */
void pinmux_tristate_enable(enum pmux_pingrp pin);
@@ -100,9 +97,6 @@ void pinmux_tristate_disable(enum pmux_pingrp pin);
void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
#endif
-/* Set the complete configuration for a pin group */
-void pinmux_config_pingroup(const struct pingroup_config *config);
-
/**
* Configure a list of pin groups
*
--
1.8.1.5
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[U-Boot] [PATCH 04/11] ARM: tegra: prototype pinmux_init() in board.h
From: Stephen Warren swar...@nvidia.com
pinmux_init() is a board-level function, not a pinmux driver function.
Move the prototype to a board header rather than the driver header.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/include/asm/arch-tegra/board.h | 1 +
arch/arm/include/asm/arch-tegra114/pinmux.h | 3 ---
arch/arm/include/asm/arch-tegra124/pinmux.h | 3 ---
arch/arm/include/asm/arch-tegra30/pinmux.h | 3 ---
board/nvidia/common/board.c | 8 ++--
5 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/board.h
b/arch/arm/include/asm/arch-tegra/board.h
index 0e698644a0a1..ff773646cbec 100644
--- a/arch/arm/include/asm/arch-tegra/board.h
+++ b/arch/arm/include/asm/arch-tegra/board.h
@@ -24,6 +24,7 @@ void gpio_early_init(void); /* overrideable GPIO config
*/
* an empty stub function will be called.
*/
+void pinmux_init(void); /* overrideable general pinmux setup */
void pin_mux_usb(void); /* overrideable USB pinmux setup */
void pin_mux_spi(void); /* overrideable SPI pinmux setup */
void pin_mux_nand(void); /* overrideable NAND pinmux setup*/
diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h
b/arch/arm/include/asm/arch-tegra114/pinmux.h
index 93d2ca525cec..a06b24f412ee 100644
--- a/arch/arm/include/asm/arch-tegra114/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra114/pinmux.h
@@ -580,9 +580,6 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io
io);
*/
void pinmux_config_table(struct pingroup_config *config, int len);
-/* Set a group of pins from a table */
-void pinmux_init(void);
-
/**
* Set the GP pad configs
*
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h
b/arch/arm/include/asm/arch-tegra124/pinmux.h
index 2042f1f7e5a3..900cf4462264 100644
--- a/arch/arm/include/asm/arch-tegra124/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -584,9 +584,6 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io
io);
*/
void pinmux_config_table(struct pingroup_config *config, int len);
-/* Set a group of pins from a table */
-void pinmux_init(void);
-
/**
* Set the GP pad configs
*
diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h
b/arch/arm/include/asm/arch-tegra30/pinmux.h
index 0704e4d4d4a1..1449f53b333e 100644
--- a/arch/arm/include/asm/arch-tegra30/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra30/pinmux.h
@@ -632,9 +632,6 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io
io);
*/
void pinmux_config_table(struct pingroup_config *config, int len);
-/* Set a group of pins from a table */
-void pinmux_init(void);
-
/**
* Set the GP pad configs
*
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 3b18e28cc4fe..d3d7bbd19598 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -48,6 +48,12 @@ const struct tegra_sysinfo sysinfo = {
CONFIG_TEGRA_BOARD_STRING
};
+void __pinmux_init(void)
+{
+}
+
+void pinmux_init(void) __attribute__((weak, alias(__pinmux_init)));
+
void __pin_mux_usb(void)
{
}
@@ -176,9 +182,7 @@ void gpio_early_init(void) __attribute__((weak,
alias(__gpio_early_init)));
int board_early_init_f(void)
{
-#if !defined(CONFIG_TEGRA20)
pinmux_init();
-#endif
board_init_uart_f();
/* Initialize periph GPIOs */
--
1.8.1.5
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[U-Boot] [PATCH 07/11] ARM: tegra: pinmux naming consistency fixes
From: Stephen Warren swar...@nvidia.com
Clean up the naming of pinmux-related objects:
* Refer to drive groups rather than pad groups to match the Linux kernel.
* Ensure all pinmux API types are prefixed with pmux_, values (defines)
are prefixed with PMUX_, and functions prefixed with pinmux_.
* Modify a few type names to make their content clearer.
* Minimal changes to SoC-specific .h/.c files are made so the code still
compiles. A separate per-SoC change will be made immediately following,
in order to keep individual patch size down.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/cpu/tegra-common/pinmux-common.c | 122 +++--
arch/arm/cpu/tegra114-common/pinmux.c | 4 +-
arch/arm/cpu/tegra124-common/pinmux.c | 4 +-
arch/arm/cpu/tegra20-common/funcmux.c | 6 +-
arch/arm/cpu/tegra20-common/pinmux.c | 4 +-
arch/arm/cpu/tegra30-common/pinmux.c | 4 +-
arch/arm/include/asm/arch-tegra/pinmux.h | 88 +++
arch/arm/include/asm/arch-tegra114/pinmux.h| 8 +-
arch/arm/include/asm/arch-tegra124/pinmux.h| 8 +-
arch/arm/include/asm/arch-tegra20/pinmux.h | 2 +-
arch/arm/include/asm/arch-tegra30/pinmux.h | 8 +-
.../common/pinmux-config-tamonten-ng.h | 30 ++---
board/avionic-design/common/tamonten-ng.c | 12 +-
board/nvidia/cardhu/cardhu.c | 6 +-
board/nvidia/cardhu/pinmux-config-cardhu.h | 30 ++---
board/nvidia/dalmore/dalmore.c | 9 +-
board/nvidia/dalmore/pinmux-config-dalmore.h | 40 +++
board/nvidia/venice2/pinmux-config-venice2.h | 40 +++
board/nvidia/venice2/venice2.c | 15 +--
19 files changed, 223 insertions(+), 217 deletions(-)
diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c
b/arch/arm/cpu/tegra-common/pinmux-common.c
index 51ba6eecdfab..32a46d53f068 100644
--- a/arch/arm/cpu/tegra-common/pinmux-common.c
+++ b/arch/arm/cpu/tegra-common/pinmux-common.c
@@ -10,7 +10,7 @@
#include asm/arch/pinmux.h
/* return 1 if a pingrp is in range */
-#define pmux_pingrp_isvalid(pin) (((pin) = 0) ((pin) PINGRP_COUNT))
+#define pmux_pingrp_isvalid(pin) (((pin) = 0) ((pin) PMUX_PINGRP_COUNT))
/* return 1 if a pmux_func is in range */
#define pmux_func_isvalid(func) \
@@ -275,9 +275,9 @@ static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
#endif /* TEGRA_PMX_HAS_RCV_SEL */
#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
-static void pinmux_config_pingroup(const struct pingroup_config *config)
+static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
{
- enum pmux_pingrp pin = config-pingroup;
+ enum pmux_pingrp pin = config-pingrp;
pinmux_set_func(pin, config-func);
pinmux_set_pullupdown(pin, config-pull);
@@ -293,32 +293,33 @@ static void pinmux_config_pingroup(const struct
pingroup_config *config)
#endif
}
-void pinmux_config_table(const struct pingroup_config *config, int len)
+void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
+ int len)
{
int i;
for (i = 0; i len; i++)
- pinmux_config_pingroup(config[i]);
+ pinmux_config_pingrp(config[i]);
}
-#ifdef TEGRA_PMX_HAS_PADGRPS
+#ifdef TEGRA_PMX_HAS_DRVGRPS
-#define pmux_padgrp_isvalid(pd) (((pd) = 0) ((pd) PDRIVE_PINGROUP_COUNT))
+#define pmux_drvgrp_isvalid(pd) (((pd) = 0) ((pd) PMUX_DRVGRP_COUNT))
-#define pmux_pad_slw_isvalid(slw) \
- (((slw) = PGRP_SLWF_MIN) ((slw) = PGRP_SLWF_MAX))
+#define pmux_slw_isvalid(slw) \
+ (((slw) = PMUX_SLWF_MIN) ((slw) = PMUX_SLWF_MAX))
-#define pmux_pad_drv_isvalid(drv) \
- (((drv) = PGRP_DRVUP_MIN) ((drv) = PGRP_DRVUP_MAX))
+#define pmux_drv_isvalid(drv) \
+ (((drv) = PMUX_DRVUP_MIN) ((drv) = PMUX_DRVUP_MAX))
-#define pmux_pad_lpmd_isvalid(lpm) \
- (((lpm) = PGRP_LPMD_X8) ((lpm) = PGRP_LPMD_X))
+#define pmux_lpmd_isvalid(lpm) \
+ (((lpm) = PMUX_LPMD_X8) ((lpm) = PMUX_LPMD_X))
-#define pmux_pad_schmt_isvalid(schmt) \
- (((schmt) = PGRP_SCHMT_DISABLE) ((schmt) = PGRP_SCHMT_ENABLE))
+#define pmux_schmt_isvalid(schmt) \
+ (((schmt) = PMUX_SCHMT_DISABLE) ((schmt) = PMUX_SCHMT_ENABLE))
-#define pmux_pad_hsm_isvalid(hsm) \
- (((hsm) = PGRP_HSM_DISABLE) ((hsm) = PGRP_HSM_ENABLE))
+#define pmux_hsm_isvalid(hsm) \
+ (((hsm) = PMUX_HSM_DISABLE) ((hsm) = PMUX_HSM_ENABLE))
#define HSM_SHIFT 2
#define SCHMT_SHIFT3
@@ -333,18 +334,18 @@ void pinmux_config_table(const struct pingroup_config
*config, int len)
#define SLWF_SHIFT 30
#define SLWF_MASK (3 SLWF_SHIFT)
-static void padgrp_set_drvup_slwf(enum pdrive_pingrp grp, int slwf)
+static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE
[U-Boot] [PATCH 08/11] ARM: tegra: Tegra20 pinmux cleanup
From: Stephen Warren swar...@nvidia.com
This renames all the Tegra20 pinmux pins and functions so they have a
prefix which matches the type name.
The entries in tegra20_pingroups[] are all updated to remove the columns
which are no longer used.
All affected code is updated to match.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/cpu/tegra20-common/funcmux.c | 179 ++---
arch/arm/cpu/tegra20-common/pinmux.c | 288 ++---
arch/arm/include/asm/arch-tegra20/pinmux.h | 266 ++-
board/avionic-design/common/tamonten.c | 4 +-
board/compal/paz00/paz00.c | 22 +-
board/compulab/trimslice/trimslice.c | 4 +-
board/nvidia/harmony/harmony.c | 18 +-
board/nvidia/seaboard/seaboard.c | 6 +-
.../colibri_t20-common/colibri_t20-common.c| 8 +-
board/toradex/colibri_t20_iris/colibri_t20_iris.c | 4 +-
drivers/spi/tegra20_sflash.c | 6 +-
drivers/video/tegra.c | 4 +-
12 files changed, 397 insertions(+), 412 deletions(-)
diff --git a/arch/arm/cpu/tegra20-common/funcmux.c
b/arch/arm/cpu/tegra20-common/funcmux.c
index 8ae28672499a..0df4a0738de4 100644
--- a/arch/arm/cpu/tegra20-common/funcmux.c
+++ b/arch/arm/cpu/tegra20-common/funcmux.c
@@ -14,7 +14,7 @@
* The PINMUX macro is used to set up pinmux tables.
*/
#define PINMUX(grp, mux, pupd, tri) \
- {PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
+ {PMUX_PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
static const struct pmux_pingrp_config disp1_default[] = {
PINMUX(LDI, DISPA, NORMAL,NORMAL),
@@ -42,26 +42,26 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_UART1:
switch (config) {
case FUNCMUX_UART1_IRRX_IRTX:
- pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
- pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PINGRP_IRRX);
- pinmux_tristate_disable(PINGRP_IRTX);
+ pinmux_set_func(PMUX_PINGRP_IRRX, PMUX_FUNC_UARTA);
+ pinmux_set_func(PMUX_PINGRP_IRTX, PMUX_FUNC_UARTA);
+ pinmux_tristate_disable(PMUX_PINGRP_IRRX);
+ pinmux_tristate_disable(PMUX_PINGRP_IRTX);
break;
case FUNCMUX_UART1_UAA_UAB:
- pinmux_set_func(PINGRP_UAA, PMUX_FUNC_UARTA);
- pinmux_set_func(PINGRP_UAB, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PINGRP_UAA);
- pinmux_tristate_disable(PINGRP_UAB);
+ pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_UARTA);
+ pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_UARTA);
+ pinmux_tristate_disable(PMUX_PINGRP_UAA);
+ pinmux_tristate_disable(PMUX_PINGRP_UAB);
bad_config = 0;
break;
case FUNCMUX_UART1_GPU:
- pinmux_set_func(PINGRP_GPU, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PINGRP_GPU);
+ pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_UARTA);
+ pinmux_tristate_disable(PMUX_PINGRP_GPU);
bad_config = 0;
break;
case FUNCMUX_UART1_SDIO1:
- pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PINGRP_SDIO1);
+ pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_UARTA);
+ pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
bad_config = 0;
break;
}
@@ -77,53 +77,53 @@ int funcmux_select(enum periph_id id, int config)
* state the group to avoid driving any signal onto it
* until we know what's connected.
*/
- pinmux_tristate_enable(PINGRP_SDB);
- pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
+ pinmux_tristate_enable(PMUX_PINGRP_SDB);
+ pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3);
}
break;
case PERIPH_ID_UART2:
if (config == FUNCMUX_UART2_UAD) {
- pinmux_set_func(PINGRP_UAD, PMUX_FUNC_UARTB);
- pinmux_tristate_disable(PINGRP_UAD);
+ pinmux_set_func(PMUX_PINGRP_UAD, PMUX_FUNC_UARTB);
+ pinmux_tristate_disable(PMUX_PINGRP_UAD);
}
break;
case PERIPH_ID_UART4:
Re: [U-Boot] [PATCH V2 2/3] lib: uuid: add functions to generate UUID version 4
Hello again,
On 03/10/2014 06:37 PM, Stephen Warren wrote:
On 03/05/2014 09:45 AM, Przemyslaw Marczak wrote:
This patch adds support to generate UUID (Universally Unique Identifier)
in version 4 based on RFC4122, which is randomly.
Source: https://www.ietf.org/rfc/rfc4122.txt
Changes:
- add new config: CONFIG_RANDOM_UUID: compile uuid.c and rand.c
Update files:
- include/common.h
- lib/Makefile
- lib/uuid.c
The patch already contains the list of changed files; there's little
point duplicating this in the patch description.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
cc: Stephen Warren swar...@nvidia.com
cc: tr...@ti.com
s/cc/Cc/
diff --git a/lib/Makefile b/lib/Makefile
index 70962b2..64a430f 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -59,10 +59,12 @@ obj-y += linux_string.o
obj-$(CONFIG_REGEX) += slre.o
obj-y += string.o
obj-y += time.o
+obj-y += vsprintf.o
Moving vsprintf.o seems entirely unrelated to this patch. If you want to
clean that up, it should be a separate patch.
obj-$(CONFIG_TRACE) += trace.o
obj-$(CONFIG_BOOTP_PXE) += uuid.o
obj-$(CONFIG_PARTITION_UUIDS) += uuid.o
-obj-y += vsprintf.o
+obj-$(CONFIG_RANDOM_UUID) += uuid.o
+obj-$(CONFIG_RANDOM_UUID) += rand.o
obj-$(CONFIG_RANDOM_MACADDR) += rand.o
I really hope listing the same object multiple times in obj-y is OK.
Why not sort the lines you added so based on the config variable, so
obj-$(CONFIG_RANDOM_MACADDR) += rand.o
+obj-$(CONFIG_RANDOM_UUID) += rand.o
rather than:
+obj-$(CONFIG_RANDOM_UUID) += rand.o
obj-$(CONFIG_RANDOM_MACADDR) += rand.o
diff --git a/lib/uuid.c b/lib/uuid.c
index 803bdcd..c0218ba 100644
--- a/lib/uuid.c
+++ b/lib/uuid.c
@@ -7,6 +7,29 @@
#include linux/ctype.h
#include errno.h
#include common.h
+#include part_efi.h
+#include malloc.h
+
+#define UUID_STR_LEN 36
+#define UUID_STR_BYTE_LEN 37
If UUID_STR_BYTE_LEN is the length in bytes, what units is UUID_STR_LEN
in? I suppose the difference is the NULL terminator, but the names don't
make that clear at all. I would suggest not defining UUID_STR_BYTE_LEN
at all, but rather just writing + 1 at the appropriate place in the
source code.
+#define UUID_BIN_BYTE_LEN 16
Also, s/_BYTE// there.
+#define UUID_VERSION_CLEAR_BITS0x0fff
s/CLEAR_BITS/MASK/
+struct uuid {
+ unsigned int time_low;
+ unsigned short time_mid;
+ unsigned short time_hi_and_version;
+ unsigned char clock_seq_hi_and_reserved;
+ unsigned char clock_seq_low;
+ unsigned char node[6];
+};
Is that structure definition endianness-safe?
UUID format is big-endian.
Actually for version 4 it doesn't matter because of it is random, and
RFC says that version and variant are the most significant bits of
proper structure field. In this code version and variant mask are stored
at most significant bits - so this is big endian.
Actually we uses it as a string and as you can check in generated uuids
its proper. As wiki says:
Version 4 UUIDs have the form --4xxx-yxxx-
where x is any hexadecimal digit and y is one of 8, 9, A, or B (e.g.,
f47ac10b-58cc-4372-a567-0e02b2c3d479).
Even if this code runs on big-endian machine, version and variant are
still set properly (most significant bits).
+/*
+ * gen_rand_uuid() - this function generates 16 bytes len UUID V4 (randomly)
+ * and stores it at a given pointer.
I think this function generates a random binary UUID v4, and stores it
into the memory pointed at by the supplied pointer, which must be 16
bytes in size would be better.
+void gen_rand_uuid(unsigned char *uuid_bin)
+{
+ struct uuid *uuid = (struct uuid *)uuid_bin;
+ unsigned int *ptr = (unsigned int *)uuid_bin;
+ int i;
+
+ if (!uuid_bin)
+ return;
I think you should either (a) assume NULL will never be passed to this
function, or (b) return an error code if it happens. Silently failing to
do anything doesn't make sense.
+ memset(uuid_bin, 0x0, sizeof(struct uuid));
+
+ /* Set all fields randomly */
+ for (i = 0; i sizeof(struct uuid) / sizeof(*ptr); i++)
+ *(ptr + i) = rand();
If the entire thing is filled randomly, why memset() the struct?
+/*
+ * gen_rand_uuid_str() - this function generates UUID v4 (randomly)
+ * into 36 character hexadecimal ASCII string representation of a 128-bit
+ * (16 octets) UUID (Universally Unique Identifier) version 4 based on RFC4122
+ * and stores it at a given pointer.
There's a lot of duplication in that description. I think this function
generates a random string-formatted UUID v4, and stores it into the
memory pointed at by the supplied pointer, which must be 37 bytes in
size would be better.
+void gen_rand_uuid_str(char *uuid_str)
+{
+ unsigned char uuid_bin[UUID_BIN_BYTE_LEN];
+
+ if (!uuid_str)
+ return;
Again, I would drop that
Re: [U-Boot] [PATCH V2 2/3] lib: uuid: add functions to generate UUID version 4
Dear Przemyslaw Marczak,
In message
cc0f558724a4d3ea3497b84601038f5f18f37a7b.1394037321.git.p.marc...@samsung.com
you wrote:
This patch adds support to generate UUID (Universally Unique Identifier)
in version 4 based on RFC4122, which is randomly.
...
+struct uuid {
+ unsigned int time_low;
+ unsigned short time_mid;
+ unsigned short time_hi_and_version;
+ unsigned char clock_seq_hi_and_reserved;
+ unsigned char clock_seq_low;
+ unsigned char node[6];
+};
This struct starts with an uint, so it requires alignment on a 32 bit
boundary (i. e. an address that is a multiple of 4).
+void gen_rand_uuid(unsigned char *uuid_bin)
+{
+ struct uuid *uuid = (struct uuid *)uuid_bin;
Here you cast a pointer to the (unaligned) character buffer to a
struct buffer, which requires alignment.
+ unsigned int *ptr = (unsigned int *)uuid_bin;
+ /* Set all fields randomly */
+ for (i = 0; i sizeof(struct uuid) / sizeof(*ptr); i++)
+ *(ptr + i) = rand();
This code is dangerous - if the size of the struct should not be a
multiple of sizeof(uint), there would remain uninitialized data.
And note that it is likely that all these accesses are unaligned and
might cause exceptions.
+ /* Set V4 format */
+ uuid-time_hi_and_version = UUID_VERSION_CLEAR_BITS;
+ uuid-time_hi_and_version |= UUID_VERSION UUID_VERSION_SHIFT;
Potentially unaligned accesses.
Best regards,
Wolfgang Denk
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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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Re: [U-Boot] [PATCH V2 2/3] lib: uuid: add functions to generate UUID version 4
Dear Przemyslaw Marczak, In message 5321f4aa.4000...@samsung.com you wrote: Is that structure definition endianness-safe? UUID format is big-endian. OK. Then you must make sure to store the data such that they result in a big endian data format. Actually for version 4 it doesn't matter because of it is random, and RFC says that version and variant are the most significant bits of proper structure field. In this code version and variant mask are stored at most significant bits - so this is big endian. Actually we uses it as a string and as you can check in generated uuids its proper. As wiki says: Version 4 UUIDs have the form --4xxx-yxxx- where x is any hexadecimal digit and y is one of 8, 9, A, or B (e.g., f47ac10b-58cc-4372-a567-0e02b2c3d479). Even if this code runs on big-endian machine, version and variant are still set properly (most significant bits). I don't see how come to this conclusion. As far as I can see, you initialize a binary data structure (where data storage _does_ depend on the endianess), and then simply use this memory area - there is no endianess handling anywhere. Please also note that your code needs fixing due to alignment issues. You cannot just cast a struct pointer which requires 32 bit alignment to an arbitrary (i. e. unaligned) char pointer (comment to patch sent). Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Heavier than air flying machines are impossible. -- Lord Kelvin, President, Royal Society, c. 1895 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 2/3] lib: uuid: add functions to generate UUID version 4
On Thu, Mar 13, 2014 at 07:41:24PM +0100, Wolfgang Denk wrote:
Dear Przemyslaw Marczak,
In message
cc0f558724a4d3ea3497b84601038f5f18f37a7b.1394037321.git.p.marc...@samsung.com
you wrote:
This patch adds support to generate UUID (Universally Unique Identifier)
in version 4 based on RFC4122, which is randomly.
...
+struct uuid {
+ unsigned int time_low;
+ unsigned short time_mid;
+ unsigned short time_hi_and_version;
+ unsigned char clock_seq_hi_and_reserved;
+ unsigned char clock_seq_low;
+ unsigned char node[6];
+};
This struct starts with an uint, so it requires alignment on a 32 bit
boundary (i. e. an address that is a multiple of 4).
And this needs to be marked as packed since we're using this as a direct
representation of things on-disk.
+void gen_rand_uuid(unsigned char *uuid_bin)
+{
+ struct uuid *uuid = (struct uuid *)uuid_bin;
Here you cast a pointer to the (unaligned) character buffer to a
struct buffer, which requires alignment.
Potentially unaligned buffer. There's only one caller thus far, and it
will be aligned there. We do need to comment that the pointer needs to
be aligned.
+ unsigned int *ptr = (unsigned int *)uuid_bin;
+ /* Set all fields randomly */
+ for (i = 0; i sizeof(struct uuid) / sizeof(*ptr); i++)
+ *(ptr + i) = rand();
This code is dangerous - if the size of the struct should not be a
multiple of sizeof(uint), there would remain uninitialized data.
With the struct not packed, it'll be padded out so this works. But
looking at how we later use this as I say above, we do need to pack it,
and then this will not be safe. Some looping of strncpy into the char
buffer, as a char so we whack the rand data in?
+ /* Set V4 format */
+ uuid-time_hi_and_version = UUID_VERSION_CLEAR_BITS;
+ uuid-time_hi_and_version |= UUID_VERSION UUID_VERSION_SHIFT;
Potentially unaligned accesses.
As-is no (hidden padding), with packed yes-but-handled (compiler can see
this too, will behave correctly).
--
Tom
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Re: [U-Boot] [PATCH V2 2/3] lib: uuid: add functions to generate UUID version 4
Dear Tom,
In message 20140313191814.GB16360@bill-the-cat you wrote:
+struct uuid {
+ unsigned int time_low;
+ unsigned short time_mid;
+ unsigned short time_hi_and_version;
+ unsigned char clock_seq_hi_and_reserved;
+ unsigned char clock_seq_low;
+ unsigned char node[6];
+};
This struct starts with an uint, so it requires alignment on a 32 bit
boundary (i. e. an address that is a multiple of 4).
And this needs to be marked as packed since we're using this as a direct
representation of things on-disk.
Not really. The arrangement of the elemnts makes sure that there are
no inter-element gaps, and even if we had arrays of such structs
(which we don;t have) it would work as the struct adds up to a
multiple of 32 bits.
+void gen_rand_uuid(unsigned char *uuid_bin)
+{
+ struct uuid *uuid = (struct uuid *)uuid_bin;
Here you cast a pointer to the (unaligned) character buffer to a
struct buffer, which requires alignment.
Potentially unaligned buffer. There's only one caller thus far, and it
will be aligned there. We do need to comment that the pointer needs to
be aligned.
No. We should rather fix the code such that it works with any
alignment. It is trivial here to use a struct uuid on the stack and
then use memcpy() to cpy the data from the struct to the buffer - no
casting needed anywhere, and no alignment concerns either.
With the struct not packed, it'll be padded out so this works. But
looking at how we later use this as I say above, we do need to pack it,
and then this will not be safe. Some looping of strncpy into the char
buffer, as a char so we whack the rand data in?
I can't see why we would not simply initialize the elements step by
step. It's just such a small struct.
Best regards,
Wolfgang Denk
--
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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Re: [U-Boot] [PATCH V2 3/3] cmd:gpt: randomly generate each partition uuid if undefined
On 03/13/2014 11:28 AM, Przemyslaw Marczak wrote:
On 03/10/2014 06:44 PM, Stephen Warren wrote:
On 03/05/2014 09:45 AM, Przemyslaw Marczak wrote:
Changes:
- randomly generate each partition uuid if undefined
- print info about generated uuid
- save environment on gpt write success
- update doc/README.gpt
diff --git a/common/cmd_gpt.c b/common/cmd_gpt.c
@@ -43,16 +45,25 @@ static char extract_env(const char *str, char **env)
memset(s + strlen(s) - 1, '\0', 1);
memmove(s, s + 2, strlen(s) - 1);
e = getenv(s);
-free(s);
if (e == NULL) {
-printf(Environmental '%s' not set\n, str);
-return -1; /* env not set */
+printf(%s unset. , str);
+gen_rand_uuid_str(uuid_str);
+setenv(s, uuid_str);
+
In this place ret is -1.
+e = getenv(s);
+if (e) {
+puts(Setting to random.\n);
Shouldn't this be printed right after the if (e == NULL) check above?
That's where the decision is made to generate a random UUID.
Here, if (!e), the code should return an error.
If (!e) then ret is still -1.
If (e) then ret = 0 and proper info is printed.
But ret has nothing to do with it; there's no code in this function
which prints messges based on ret.
The code should be:
e = getenv(s);
if (e == NULL) {
printf(Env var '%s' not set; using random UUID\n, str);
// generate random UUID here
if (UUID generation failed) {
printf(ERROR generating random UUID\n);
return -1;
}
}
With the code in your patch, the following happens:
* Env var is set: Nothing printed.
* Env var not set, but problem during UUID generation: %s unset. is
printed without a \n at the end. The error does get propagated back tot
he caller, which might print a message with \n at the end, but you
shouldn't place that kind of requirement on the caller. Rather, this
function should be fully self-contained.
* Env var set, and UUID generated OK: %s unset. Setting to random.\n
is printed.
But, I still don't like changing the environment. Why can't the above
few lines be:
+ gen_rand_uuid_str(uuid_str);
+e = uuid_str;
Such solution needs more code rewriting and breaking some existing
cmd_gpt design. e is used outside this function but uuid_str is local
here. I don't like to make it static.
Using getenv and return its pointer will work the same as previous.
Please note that variables set by user are not overwritten here so this
code will only set null uuid env variables. Moreover user can see after
gpt command that environment is the same with mmc part shows, I think it
is useful instead of situation when uuid is set but not present in
environment.
I don't think convenience of coding or the size of the patch is
justification for writing values to the user's environment when they
didn't ask for it. What if they run saveenv after executing this
function, yet they specifically want the environment variables unset, so
that a random UUID is generated each time this function/command is run?
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Re: [U-Boot] [PATCH V2 2/3] lib: uuid: add functions to generate UUID version 4
Hello,
On 03/13/2014 08:18 PM, Tom Rini wrote:
On Thu, Mar 13, 2014 at 07:41:24PM +0100, Wolfgang Denk wrote:
Dear Przemyslaw Marczak,
In message
cc0f558724a4d3ea3497b84601038f5f18f37a7b.1394037321.git.p.marc...@samsung.com
you wrote:
This patch adds support to generate UUID (Universally Unique Identifier)
in version 4 based on RFC4122, which is randomly.
...
+struct uuid {
+ unsigned int time_low;
+ unsigned short time_mid;
+ unsigned short time_hi_and_version;
+ unsigned char clock_seq_hi_and_reserved;
+ unsigned char clock_seq_low;
+ unsigned char node[6];
+};
This struct starts with an uint, so it requires alignment on a 32 bit
boundary (i. e. an address that is a multiple of 4).
And this needs to be marked as packed since we're using this as a direct
representation of things on-disk.
ok, I will add packed attribute.
+void gen_rand_uuid(unsigned char *uuid_bin)
I can change this pointer above to unsigned int.
+{
+ struct uuid *uuid = (struct uuid *)uuid_bin;
Here you cast a pointer to the (unaligned) character buffer to a
struct buffer, which requires alignment.
Potentially unaligned buffer. There's only one caller thus far, and it
will be aligned there. We do need to comment that the pointer needs to
be aligned.
+ unsigned int *ptr = (unsigned int *)uuid_bin;
+ /* Set all fields randomly */
+ for (i = 0; i sizeof(struct uuid) / sizeof(*ptr); i++)
+ *(ptr + i) = rand();
This code is dangerous - if the size of the struct should not be a
multiple of sizeof(uint), there would remain uninitialized data.
We know that uuid is 16bytes, so change the divider to 4 is better
solution?
With the struct not packed, it'll be padded out so this works. But
looking at how we later use this as I say above, we do need to pack it,
and then this will not be safe. Some looping of strncpy into the char
buffer, as a char so we whack the rand data in?
+ /* Set V4 format */
+ uuid-time_hi_and_version = UUID_VERSION_CLEAR_BITS;
+ uuid-time_hi_and_version |= UUID_VERSION UUID_VERSION_SHIFT;
Potentially unaligned accesses.
Ok, I change this to clrsetbits.
As-is no (hidden padding), with packed yes-but-handled (compiler can see
this too, will behave correctly).
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--
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Samsung RD Institute Poland
Samsung Electronics
p.marc...@samsung.com
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Re: [U-Boot] [PATCH V2 2/3] lib: uuid: add functions to generate UUID version 4
On 03/13/2014 01:48 PM, Wolfgang Denk wrote:
Dear Tom,
In message 20140313191814.GB16360@bill-the-cat you wrote:
+struct uuid {
+ unsigned int time_low;
+ unsigned short time_mid;
+ unsigned short time_hi_and_version;
+ unsigned char clock_seq_hi_and_reserved;
+ unsigned char clock_seq_low;
+ unsigned char node[6];
+};
+void gen_rand_uuid(unsigned char *uuid_bin)
+{
+ struct uuid *uuid = (struct uuid *)uuid_bin;
Here you cast a pointer to the (unaligned) character buffer to a
struct buffer, which requires alignment.
Potentially unaligned buffer. There's only one caller thus far, and it
will be aligned there. We do need to comment that the pointer needs to
be aligned.
No. We should rather fix the code such that it works with any
alignment. It is trivial here to use a struct uuid on the stack and
then use memcpy() to cpy the data from the struct to the buffer - no
casting needed anywhere, and no alignment concerns either.
Why not just change the prototype of the function so that it takes a
pointer to a struct uuid. That way, the compiler will ensure that
everything is aligned correctly (assuming there are no broken casts at
the call site), and we won't have to either document any assumptions
about alignment, nor perform a memcpy() to work around any misalignment.
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[U-Boot] [PATCH] sparc: consolidate CONFIG_{LEON, LEON2, LEON3} definition
CONFIG_LEON is already defined in
arch/sparc/cpu/{leon2,leon3}/config.mk.
Remove the redundant definition in board header files.
All leon3 boards define CONFIG_LEON3 in board header files.
Move the definition to arch/sparc/cpu/leon3/config.mk.
CONFIG_LEON2 can be move to arch/sparc/cpu/leon2/config.mk
as well.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Cc: Daniel Hellstrom dan...@gaisler.com
---
arch/sparc/cpu/leon2/config.mk | 2 +-
arch/sparc/cpu/leon3/config.mk | 2 +-
include/configs/gr_cpci_ax2000.h | 2 --
include/configs/gr_ep2s60.h | 2 --
include/configs/gr_xc3s_1500.h | 2 --
include/configs/grsim.h | 2 --
include/configs/grsim_leon2.h| 2 --
7 files changed, 2 insertions(+), 12 deletions(-)
diff --git a/arch/sparc/cpu/leon2/config.mk b/arch/sparc/cpu/leon2/config.mk
index f9b0d34..c44b093 100644
--- a/arch/sparc/cpu/leon2/config.mk
+++ b/arch/sparc/cpu/leon2/config.mk
@@ -7,4 +7,4 @@
PLATFORM_RELFLAGS += -fPIC
-PLATFORM_CPPFLAGS += -DCONFIG_LEON
+PLATFORM_CPPFLAGS += -DCONFIG_LEON -DCONFIG_LEON2
diff --git a/arch/sparc/cpu/leon3/config.mk b/arch/sparc/cpu/leon3/config.mk
index f9b0d34..ca6c9b1 100644
--- a/arch/sparc/cpu/leon3/config.mk
+++ b/arch/sparc/cpu/leon3/config.mk
@@ -7,4 +7,4 @@
PLATFORM_RELFLAGS += -fPIC
-PLATFORM_CPPFLAGS += -DCONFIG_LEON
+PLATFORM_CPPFLAGS += -DCONFIG_LEON -DCONFIG_LEON3
diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h
index 8f4b85b..a4b5eb3 100644
--- a/include/configs/gr_cpci_ax2000.h
+++ b/include/configs/gr_cpci_ax2000.h
@@ -22,8 +22,6 @@
* (easy to change)
*/
-#define CONFIG_LEON3 /* This is an LEON3 CPU */
-#define CONFIG_LEON1 /* This is an LEON CPU */
#define CONFIG_CPCI_AX2000 1 /* ... on GR-CPCI-AX2000 board */
#define CONFIG_LEON_RAM_SRAM 1
diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h
index 1e829aa..b7f094f 100644
--- a/include/configs/gr_ep2s60.h
+++ b/include/configs/gr_ep2s60.h
@@ -23,8 +23,6 @@
* (easy to change)
*/
-#define CONFIG_LEON3 /* This is an LEON3 CPU */
-#define CONFIG_LEON1 /* This is an LEON CPU */
/* Altera NIOS Development board, Stratix II board */
#define CONFIG_GR_EP2S60 1
diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h
index e9e64f1..789b3ed 100644
--- a/include/configs/gr_xc3s_1500.h
+++ b/include/configs/gr_xc3s_1500.h
@@ -21,8 +21,6 @@
* (easy to change)
*/
-#define CONFIG_LEON3 /* This is an LEON3 CPU */
-#define CONFIG_LEON1 /* This is an LEON CPU */
#define CONFIG_GRXC3S1500 1 /* ... on GR-XC3S-1500 board */
/* CPU / AMBA BUS configuration */
diff --git a/include/configs/grsim.h b/include/configs/grsim.h
index f50dd54..82b7a4e 100644
--- a/include/configs/grsim.h
+++ b/include/configs/grsim.h
@@ -27,8 +27,6 @@
*
*/
-#define CONFIG_LEON3 /* This is an LEON3 CPU */
-#define CONFIG_LEON1 /* This is an LEON CPU */
#define CONFIG_GRSIM 0 /* ... not running on GRSIM */
#define CONFIG_TSIM1 /* ... running on TSIM */
diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h
index 9ea6d9b..8cb077c 100644
--- a/include/configs/grsim_leon2.h
+++ b/include/configs/grsim_leon2.h
@@ -26,8 +26,6 @@
*
*/
-#define CONFIG_LEON2 /* This is an LEON2 CPU */
-#define CONFIG_LEON1 /* This is an LEON CPU */
#define CONFIG_GRSIM 0 /* ... not running on GRSIM */
#define CONFIG_TSIM1 /* ... running on TSIM */
--
1.8.3.2
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Re: [U-Boot] [PATCH V2 3/3] cmd:gpt: randomly generate each partition uuid if undefined
On 03/13/2014 08:49 PM, Stephen Warren wrote:
On 03/13/2014 11:28 AM, Przemyslaw Marczak wrote:
On 03/10/2014 06:44 PM, Stephen Warren wrote:
On 03/05/2014 09:45 AM, Przemyslaw Marczak wrote:
Changes:
- randomly generate each partition uuid if undefined
- print info about generated uuid
- save environment on gpt write success
- update doc/README.gpt
diff --git a/common/cmd_gpt.c b/common/cmd_gpt.c
@@ -43,16 +45,25 @@ static char extract_env(const char *str, char **env)
memset(s + strlen(s) - 1, '\0', 1);
memmove(s, s + 2, strlen(s) - 1);
e = getenv(s);
-free(s);
if (e == NULL) {
-printf(Environmental '%s' not set\n, str);
-return -1; /* env not set */
+printf(%s unset. , str);
+gen_rand_uuid_str(uuid_str);
+setenv(s, uuid_str);
+
In this place ret is -1.
+e = getenv(s);
+if (e) {
+puts(Setting to random.\n);
Shouldn't this be printed right after the if (e == NULL) check above?
That's where the decision is made to generate a random UUID.
Here, if (!e), the code should return an error.
If (!e) then ret is still -1.
If (e) then ret = 0 and proper info is printed.
But ret has nothing to do with it; there's no code in this function
which prints messges based on ret.
The code should be:
e = getenv(s);
if (e == NULL) {
printf(Env var '%s' not set; using random UUID\n, str);
// generate random UUID here
if (UUID generation failed) {
printf(ERROR generating random UUID\n);
return -1;
}
Take a note that gen_rand_uuid_str() doesn't return any error. So this
error is not true.
}
With the code in your patch, the following happens:
* Env var is set: Nothing printed.
And env var is not changed - and this is as before.
* Env var not set, but problem during UUID generation: %s unset. is
printed without a \n at the end. The error does get propagated back tot
he caller, which might print a message with \n at the end, but you
shouldn't place that kind of requirement on the caller. Rather, this
function should be fully self-contained.
* Env var set, and UUID generated OK: %s unset. Setting to random.\n
is printed.
But, I still don't like changing the environment. Why can't the above
few lines be:
+ gen_rand_uuid_str(uuid_str);
+e = uuid_str;
Such solution needs more code rewriting and breaking some existing
cmd_gpt design. e is used outside this function but uuid_str is local
here. I don't like to make it static.
Using getenv and return its pointer will work the same as previous.
Please note that variables set by user are not overwritten here so this
code will only set null uuid env variables. Moreover user can see after
gpt command that environment is the same with mmc part shows, I think it
is useful instead of situation when uuid is set but not present in
environment.
I don't think convenience of coding or the size of the patch is
justification for writing values to the user's environment when they
didn't ask for it. What if they run saveenv after executing this
function, yet they specifically want the environment variables unset, so
that a random UUID is generated each time this function/command is run?
Actually I don't understand what is the problem. What is the difference
when user set manually $uuid_gpt_* or use generated by gpt command if
next he write save, in both situations variables are saved. I don't
think it is a problem.
Thanks
--
Przemyslaw Marczak
Samsung RD Institute Poland
Samsung Electronics
p.marc...@samsung.com
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[U-Boot] [PATCH v6 2/2] Powerpc/QE: Add QE support for T1040
The u-qe of T1040 has addresses different from qe,
modify those addresses value for both u-qe and qe.
Add function qe_board_setup to mux the bus to tdm or uart
according to hwconfig.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
- modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and
CONFIG_SYS_QE_FW_ADDR
Changes for v3:
- use CONFIG_U_QE instead of CONFIG_PPC_T1040
Changes for v4:
- ifdef CONFIG_U_QE, include ../../../../drivers/qe/qe.h
Changes for v5:
- no
Changes for v6:
- rebase
arch/powerpc/cpu/mpc85xx/cpu_init.c | 11 +++
arch/powerpc/cpu/mpc85xx/qe_io.c | 2 +-
arch/powerpc/cpu/mpc85xx/speed.c | 6 ++
arch/powerpc/cpu/mpc85xx/t1040_ids.c | 1 +
arch/powerpc/include/asm/config_mpc85xx.h | 3 +++
arch/powerpc/include/asm/fsl_liodn.h | 4
arch/powerpc/include/asm/immap_85xx.h | 5 -
board/freescale/t1040qds/t1040qds.c | 31 +++
drivers/qe/qe.h | 2 ++
include/configs/T1040QDS.h| 3 +++
10 files changed, 66 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index e0fb3e5..ec17745 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -33,6 +33,9 @@
#endif
#include ../../../../drivers/block/fsl_sata.h
+#ifdef CONFIG_U_QE
+#include ../../../../drivers/qe/qe.h
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -85,6 +88,7 @@ void fsl_erratum_a006261_workaround(struct ccsr_usb_phy
__iomem *usb_phy)
#ifdef CONFIG_QE
+#ifndef CONFIG_U_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
int open_drain, int assign);
@@ -107,6 +111,7 @@ static void config_qe_ioports(void)
}
}
#endif
+#endif
#ifdef CONFIG_CPM2
void config_8560_ioports (volatile ccsr_cpm_t * cpm)
@@ -310,9 +315,11 @@ void cpu_init_f (void)
m8560_cpm_reset();
#endif
#ifdef CONFIG_QE
+#ifndef CONFIG_U_QE
/* Config QE ioports */
config_qe_ioports();
#endif
+#endif
#if defined(CONFIG_FSL_DMA)
dma_init();
#endif
@@ -798,7 +805,11 @@ int sata_initialize(void)
void cpu_secondary_init_r(void)
{
#ifdef CONFIG_QE
+#ifdef CONFIG_U_QE
+ uint qe_base = CONFIG_SYS_IMMR + 0x0014; /* QE immr base */
+#else
uint qe_base = CONFIG_SYS_IMMR + 0x0008; /* QE immr base */
+#endif
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
int ret;
size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
diff --git a/arch/powerpc/cpu/mpc85xx/qe_io.c b/arch/powerpc/cpu/mpc85xx/qe_io.c
index 76c60da..d2825ec 100644
--- a/arch/powerpc/cpu/mpc85xx/qe_io.c
+++ b/arch/powerpc/cpu/mpc85xx/qe_io.c
@@ -12,7 +12,7 @@
#include asm/io.h
#include asm/immap_85xx.h
-#if defined(CONFIG_QE)
+#if defined(CONFIG_QE) !defined(CONFIG_U_QE)
#defineNUM_OF_PINS 32
void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
{
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index adf09ef..25b967d 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -336,6 +336,12 @@ void get_sys_info(sys_info_t *sys_info)
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+#ifdef CONFIG_QE
+#if defined(CONFIG_PPC_T1040)
+ sys_info-freq_qe = sys_info-freq_systembus / 2;
+#endif
+#endif
+
#else /* CONFIG_FSL_CORENET */
uint plat_ratio, e500_ratio, half_freq_systembus;
int i;
diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c
b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
index 68160a9..1034cd4 100644
--- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
@@ -46,6 +46,7 @@ struct liodn_id_table liodn_tbl[] = {
SET_DMA_LIODN(2, 227),
/* SET_NEXUS_LIODN(557), -- not yet implemented */
+ SET_QE_LIODN(559),
};
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 9a20b97..943ca6f 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -734,6 +734,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe00
+#define QE_MURAM_SIZE 0x6000UL
+#define MAX_QE_RISC1
+#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define CONFIG_E6500
diff --git a/arch/powerpc/include/asm/fsl_liodn.h
b/arch/powerpc/include/asm/fsl_liodn.h
index 44bc88d..f658bcb 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -99,6 +99,10 @@ extern void fdt_fixup_liodn(void *blob);
SET_GUTS_LIODN(fsl,esdhc, liodn,
[U-Boot] [PATCH v6 1/2] QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and CONFIG_SYS_QE_FW_ADDR
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
- no
Changes for v3:
- no
Changes for v4:
- no
Changes for v5:
- modify CONFIG_SYS_QE_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR for kmp204x
Changes for v6:
- rebase
README | 9 +++--
arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +-
drivers/net/fm/fm.c | 12 ++--
drivers/qe/qe.c | 2 +-
include/configs/B4860QDS.h | 10 +-
include/configs/MPC8569MDS.h| 2 +-
include/configs/P1023RDB.h | 2 +-
include/configs/P1023RDS.h | 4 ++--
include/configs/P2041RDB.h | 10 +-
include/configs/T1040QDS.h | 8
include/configs/T1040RDB.h | 8
include/configs/T1042RDB_PI.h | 8
include/configs/T208xQDS.h | 10 +-
include/configs/T208xRDB.h | 10 +-
include/configs/T4240EMU.h | 2 +-
include/configs/T4240QDS.h | 10 +-
include/configs/corenet_ds.h| 10 +-
include/configs/km/km8309-common.h | 2 +-
include/configs/km/kmp204x-common.h | 2 +-
include/configs/p1_p2_rdb_pc.h | 2 +-
include/configs/p1_twr.h| 2 +-
21 files changed, 66 insertions(+), 61 deletions(-)
diff --git a/README b/README
index 216f0c7..c49efee 100644
--- a/README
+++ b/README
@@ -4485,8 +4485,13 @@ This firmware often needs to be loaded during U-Boot
booting, so macros
are used to identify the storage device (NOR flash, SPI, etc) and the address
within that device.
-- CONFIG_SYS_QE_FMAN_FW_ADDR
- The address in the storage device where the firmware is located. The
+- CONFIG_SYS_FMAN_FW_ADDR
+ The address in the storage device where the FMAN microcode is located.
The
+ meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
+ is also specified.
+
+- CONFIG_SYS_QE_FW_ADDR
+ The address in the storage device where the QE microcode is located.
The
meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
is also specified.
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 81aeadd..e0fb3e5 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -805,7 +805,7 @@ void cpu_secondary_init_r(void)
/* load QE firmware from NAND flash to DDR first */
ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
- fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
+ fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR);
if (ret ret == -EUCLEAN) {
printf (NAND read for QE firmware at offset %x failed %d\n,
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index bca20b3..400e9dd 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -350,16 +350,16 @@ int fm_init_common(int index, struct ccsr_fman *reg)
{
int rc;
#if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
- void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR;
+ void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
- rc = nand_read(nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_ADDR,
+ rc = nand_read(nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
fw_length, (u_char *)addr);
if (rc == -EUCLEAN) {
printf(NAND read of FMAN firmware at offset 0x%x failed %d\n,
- CONFIG_SYS_QE_FMAN_FW_ADDR, rc);
+ CONFIG_SYS_FMAN_FW_ADDR, rc);
}
#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
struct spi_flash *ucode_flash;
@@ -371,7 +371,7 @@ int fm_init_common(int index, struct ccsr_fman *reg)
if (!ucode_flash)
printf(SF: probe for ucode failed\n);
else {
- ret = spi_flash_read(ucode_flash, CONFIG_SYS_QE_FMAN_FW_ADDR,
+ ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR,
CONFIG_SYS_QE_FMAN_FW_LENGTH, addr);
if (ret)
printf(SF: read for ucode failed\n);
@@ -381,7 +381,7 @@ int fm_init_common(int index, struct ccsr_fman *reg)
int dev = CONFIG_SYS_MMC_ENV_DEV;
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
- u32 blk = CONFIG_SYS_QE_FMAN_FW_ADDR / 512;
+ u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
if (!mmc)
@@ -395,7 +395,7 @@ int
[U-Boot] [PATCH] t1040rdb/qe: add QE support for T1040RDB
add CONFIG_QE, CONFIG_U_QE and CONFIG_SYS_QE_FW_ADDR into include/configs/T1040RDB.h Signed-off-by: Zhao Qiang b45...@freescale.com --- include/configs/T1040RDB.h | 4 1 file changed, 4 insertions(+) diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h index 7420db9..f036192 100644 --- a/include/configs/T1040RDB.h +++ b/include/configs/T1040RDB.h @@ -510,6 +510,9 @@ #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME +#define CONFIG_QE +#define CONFIG_U_QE + /* Default address of microcode for the Linux Fman driver */ #if defined(CONFIG_SPIFLASH) /* @@ -532,6 +535,7 @@ #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_FMAN_FW_ADDR0xEFF0 +#define CONFIG_SYS_QE_FW_ADDR 0xEFF1 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x1 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -- 1.8.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] kbuild: Rename UIMAGE to MKIMAGE
U-Boot uses the 'mkimage' tool to produce various image types,
not only uImage image type. Rename the invocation name from
UIMAGE to MKIMAGE.
The following command was used to do the replacement:
git grep 'quiet_cmd_mkimage.* = UIMAGE' | cut -d : -f 1 | \
xargs -i sed -i s@\(quiet_cmd_mkimage\)\(.*\) = UIMAGE @\1\2 = MKIMAGE@ {}
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Masahiro Yamada yamad...@jp.panasonic.com
---
Makefile| 2 +-
arch/arm/cpu/arm926ejs/mxs/Makefile | 2 +-
arch/arm/imx-common/Makefile| 2 +-
board/cray/L1/Makefile | 2 +-
board/matrix_vision/mvblm7/Makefile | 2 +-
board/matrix_vision/mvsmr/Makefile | 2 +-
spl/Makefile| 2 +-
7 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/Makefile b/Makefile
index 538c3bf..e723218 100644
--- a/Makefile
+++ b/Makefile
@@ -728,7 +728,7 @@ endif
quiet_cmd_objcopy = OBJCOPY $@
cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $ $@
-quiet_cmd_mkimage = UIMAGE $@
+quiet_cmd_mkimage = MKIMAGE $@
cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $ $@ \
$(if $(KBUILD_VERBOSE:1=), /dev/null)
diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile
b/arch/arm/cpu/arm926ejs/mxs/Makefile
index 1eee661..209c73c 100644
--- a/arch/arm/cpu/arm926ejs/mxs/Makefile
+++ b/arch/arm/cpu/arm926ejs/mxs/Makefile
@@ -17,7 +17,7 @@ endif
MKIMAGE_TARGET-$(CONFIG_MX23) = mxsimage.mx23.cfg
MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage.mx28.cfg
-quiet_cmd_mkimage_mxs = UIMAGE $@
+quiet_cmd_mkimage_mxs = MKIMAGE $@
cmd_mkimage_mxs = $(objtree)/tools/mkimage -n $ -T mxsimage $@ \
$(if $(KBUILD_VERBOSE:1=), /dev/null)
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 16809fe..7334e05 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -32,7 +32,7 @@ $(IMX_CONFIG): %.cfgtmp: % FORCE
$(Q)mkdir -p $(dir $@)
$(call if_changed_dep,cpp_cfg)
-quiet_cmd_mkimage = UIMAGE $@
+quiet_cmd_mkimage = MKIMAGE $@
cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $ $@ \
$(if $(KBUILD_VERBOSE:1=), /dev/null)
diff --git a/board/cray/L1/Makefile b/board/cray/L1/Makefile
index 655f530..5540298 100644
--- a/board/cray/L1/Makefile
+++ b/board/cray/L1/Makefile
@@ -15,7 +15,7 @@ quiet_cmd_awk = AWK $@
$(obj)/bootscript.c: $(obj)/bootscript.image $(src)/x2c.awk
$(call cmd,awk)
-quiet_cmd_mkimage = UIMAGE $@
+quiet_cmd_mkimage = MKIMAGE $@
cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $ $@ \
$(if $(KBUILD_VERBOSE:1=), /dev/null)
diff --git a/board/matrix_vision/mvblm7/Makefile
b/board/matrix_vision/mvblm7/Makefile
index b5987fd..9ed2837 100644
--- a/board/matrix_vision/mvblm7/Makefile
+++ b/board/matrix_vision/mvblm7/Makefile
@@ -8,7 +8,7 @@ obj-y := mvblm7.o pci.o fpga.o
extra-y := bootscript.img
-quiet_cmd_mkimage = UIMAGE $@
+quiet_cmd_mkimage = MKIMAGE $@
cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $ $@ \
$(if $(KBUILD_VERBOSE:1=), /dev/null)
diff --git a/board/matrix_vision/mvsmr/Makefile
b/board/matrix_vision/mvsmr/Makefile
index fae7ec2..a9c794e 100644
--- a/board/matrix_vision/mvsmr/Makefile
+++ b/board/matrix_vision/mvsmr/Makefile
@@ -12,7 +12,7 @@ obj-y := mvsmr.o fpga.o
extra-y := bootscript.img
-quiet_cmd_mkimage = UIMAGE $@
+quiet_cmd_mkimage = MKIMAGE $@
cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $ $@ \
$(if $(KBUILD_VERBOSE:1=), /dev/null)
diff --git a/spl/Makefile b/spl/Makefile
index be5fd3b..9f5dbf4 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -171,7 +171,7 @@ LDPPFLAGS += \
$(shell $(LD) --version | \
sed -ne 's/GNU ld version
\([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
-quiet_cmd_mkimage = UIMAGE $@
+quiet_cmd_mkimage = MKIMAGE $@
cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $ $@ \
$(if $(KBUILD_VERBOSE:1=), /dev/null)
--
1.8.5.3
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[U-Boot] [PATCH 2/3 v2] net/phy: update get_phy_device_by_mask to probe more 10G PHY
In function get_phy_device_by_mask(), when trying Clause 45,
we should extend the value of devad(used in create_phy_by_mask)
to zero to cover more PHYs (e.g. devad must be 0 for CS4315 PHY).
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: no change
drivers/net/phy/phy.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index da65329..6d4c05f 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -645,9 +645,9 @@ static struct phy_device *get_phy_device_by_mask(struct
mii_dev *bus,
return phydev;
/* Try Standard (ie Clause 22) access */
/* Otherwise we have to try Clause 45 */
- for (i = 0; i 5; i++) {
+ for (i = 0; i 6; i++) {
phydev = create_phy_by_mask(bus, phy_mask,
- i ? i : MDIO_DEVAD_NONE, interface);
+ i ? i - 1 : MDIO_DEVAD_NONE, interface);
if (IS_ERR(phydev))
return NULL;
if (phydev)
--
1.8.0
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[U-Boot] [PATCH 1/3 v2] net/phy: enable get_phy_id redefinable
As some PHYs have non-standard PHY ID registers, PHY Id can't
be read correctly by current get_phy_id function, so we enable
get_phy_id redefinable to permit specific PHY driver having own
specific get_phy_id function.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: use __weak
drivers/net/phy/phy.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index c691fbb..da65329 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -18,6 +18,7 @@
#include phy.h
#include errno.h
#include linux/err.h
+#include linux/compiler.h
/* Generic PHY support and helper functions */
@@ -577,7 +578,7 @@ static struct phy_device *phy_device_create(struct mii_dev
*bus, int addr,
* Description: Reads the ID registers of the PHY at @addr on the
* @bus, stores it in @phy_id and returns zero on success.
*/
-static int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
+static int __weak get_phy_id(struct mii_dev *bus, int addr, int devad, u32
*phy_id)
{
int phy_reg;
--
1.8.0
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[U-Boot] [PATCH 3/3 v2] net/phy: Add support for CS4315/CS4340 PHY
Add support for Cortina CS4315/CS4340 10G PHY.
- This driver loads CS43xx firmware to initialize Cortina PHY.
- To define macro CONFIG_PHY_CORTINA will enable this driver.
- Cortina PHY has non-standard offset of PHY ID registers, so
define own get_phy_id().
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: no change.
drivers/net/phy/Makefile | 1 +
drivers/net/phy/cortina.c | 265 ++
drivers/net/phy/phy.c | 3 +
include/cortina.h | 73 +
include/phy.h | 2 +
5 files changed, 344 insertions(+)
create mode 100644 drivers/net/phy/cortina.c
create mode 100644 include/cortina.h
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index dbf7bf7..b091962 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_PHY_REALTEK) += realtek.o
obj-$(CONFIG_PHY_SMSC) += smsc.o
obj-$(CONFIG_PHY_TERANETICS) += teranetics.o
obj-$(CONFIG_PHY_VITESSE) += vitesse.o
+obj-$(CONFIG_PHY_CORTINA) += cortina.o
diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
new file mode 100644
index 000..a023b6c
--- /dev/null
+++ b/drivers/net/phy/cortina.c
@@ -0,0 +1,265 @@
+/*
+ * Cortina CS4315/CS4340 10G PHY drivers
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ */
+
+#include config.h
+#include common.h
+#include linux/ctype.h
+#include linux/string.h
+#include linux/err.h
+#include phy.h
+#include cortina.h
+
+#ifndef CONFIG_PHYLIB_10G
+#error The Cortina PHY needs 10G support
+#endif
+
+struct cortina_reg_config cortina_reg_cfg[] = {
+ /* CS4315_enable_sr_mode */
+ {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
+ {VILLA_MSEQ_OPTIONS, 0xf},
+ {VILLA_MSEQ_PC, 0x0},
+ {VILLA_MSEQ_BANKSELECT,0x4},
+ {VILLA_LINE_SDS_COMMON_SRX0_RX_CPA, 0x55},
+ {VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0x30},
+ {VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0x1},
+ {VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT, 0x2},
+ {VILLA_LINE_SDS_COMMON_SRX0_RX_CPB, 0x2003},
+ {VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0xF047},
+ {VILLA_MSEQ_ENABLE_MSB, 0x},
+ {VILLA_MSEQ_SPARE21_LSB, 0x6},
+ {VILLA_MSEQ_RESET_COUNT_LSB, 0x0},
+ {VILLA_MSEQ_SPARE12_MSB, 0x},
+ /*
+* to invert the receiver path, uncomment the next line
+* write (VILLA_MSEQ_SPARE12_MSB, 0x4000)
+*
+* SPARE2_LSB is used to configure the device while in sr mode to
+* enable power savings and to use the optical module LOS signal.
+* in power savings mode, the internal prbs checker can not be used.
+* if the optical module LOS signal is used as an input to the micro
+* code, then the micro code will wait until the optical module
+* LOS = 0 before turning on the adaptive equalizer.
+* Setting SPARE2_LSB bit 0 to 1 places the devie in power savings mode
+* while setting bit 0 to 0 disables power savings mode.
+* Setting SPARE2_LSB bit 2 to 0 configures the device to use the
+* optical module LOS signal while setting bit 2 to 1 configures the
+* device so that it will ignore the optical module LOS SPARE2_LSB = 0
+*/
+
+ /* enable power savings, ignore optical module LOS */
+ {VILLA_MSEQ_SPARE2_LSB, 0x5},
+
+ {VILLA_MSEQ_SPARE7_LSB, 0x1e},
+ {VILLA_MSEQ_BANKSELECT, 0x4},
+ {VILLA_MSEQ_SPARE9_LSB, 0x2},
+ {VILLA_MSEQ_SPARE3_LSB, 0x0F53},
+ {VILLA_MSEQ_SPARE3_MSB, 0x2006},
+ {VILLA_MSEQ_SPARE8_LSB, 0x3FF7},
+ {VILLA_MSEQ_SPARE8_MSB, 0x0A46},
+ {VILLA_MSEQ_COEF8_FFE0_LSB, 0xD500},
+ {VILLA_MSEQ_COEF8_FFE1_LSB, 0x0200},
+ {VILLA_MSEQ_COEF8_FFE2_LSB, 0xBA00},
+ {VILLA_MSEQ_COEF8_FFE3_LSB, 0x0100},
+ {VILLA_MSEQ_COEF8_FFE4_LSB, 0x0300},
+ {VILLA_MSEQ_COEF8_FFE5_LSB, 0x0300},
+ {VILLA_MSEQ_COEF8_DFE0_LSB, 0x0700},
+ {VILLA_MSEQ_COEF8_DFE0N_LSB, 0x0E00},
+ {VILLA_MSEQ_COEF8_DFE1_LSB, 0x0B00},
+ {VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK, 0x2},
+ {VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB, 0xD000},
+ {VILLA_MSEQ_POWER_DOWN_LSB, 0x},
+ {VILLA_MSEQ_POWER_DOWN_MSB, 0x0},
+ {VILLA_MSEQ_CAL_RX_SLICER, 0x80},
+ {VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB, 0x3f},
+ {VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
+ {VILLA_MSEQ_OPTIONS, 0x7},
+
+ /* set up min value for ffe1 */
+ {VILLA_MSEQ_COEF_INIT_SEL, 0x2},
+ {VILLA_DSP_SDS_DSP_PRECODEDINITFFE21, 0x41},
+
+ /* CS4315_sr_rx_pre_eq_set_4in */
+ {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
+ {VILLA_MSEQ_OPTIONS, 0xf},
+ {VILLA_MSEQ_BANKSELECT, 0x4},
+ {VILLA_MSEQ_PC, 0x0},
+
+ /* for lengths from 3.5 to 4.5inches */
+ {VILLA_MSEQ_SERDES_PARAM_LSB, 0x0306},
+ {VILLA_MSEQ_SPARE25_LSB, 0x0306},
+ {VILLA_MSEQ_SPARE21_LSB, 0x2},
+
Re: [U-Boot] [PATCH] kbuild: Rename UIMAGE to MKIMAGE
Hello Marek,
U-Boot uses the 'mkimage' tool to produce various image types,
not only uImage image type. Rename the invocation name from
UIMAGE to MKIMAGE.
The following command was used to do the replacement:
git grep 'quiet_cmd_mkimage.* = UIMAGE' | cut -d : -f 1 | \
xargs -i sed -i s@\(quiet_cmd_mkimage\)\(.*\) = UIMAGE @\1\2 = MKIMAGE@ {}
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Masahiro Yamada yamad...@jp.panasonic.com
Acked-by: Masahiro Yamada yamad...@jp.panasonic.com
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Re: [U-Boot] [PATCH] sh: ecovec: correct romImage address in comment
Appied, thanks!
Best regards,
Nobuhiro
2014-03-10 22:09 GMT+09:00 Baruch Siach bar...@tkos.co.il:
romImage is set by CONFIG_ECOVEC_ROMIMAGE_ADDR to 0xA004.
Signed-off-by: Baruch Siach bar...@tkos.co.il
---
board/renesas/ecovec/lowlevel_init.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/renesas/ecovec/lowlevel_init.S
b/board/renesas/ecovec/lowlevel_init.S
index eeebdd245f78..e4c40c861604 100644
--- a/board/renesas/ecovec/lowlevel_init.S
+++ b/board/renesas/ecovec/lowlevel_init.S
@@ -20,7 +20,7 @@
lowlevel_init:
- /* jump to 0xA002 if bit 1 of PVDR_A */
+ /* jump to CONFIG_ECOVEC_ROMIMAGE_ADDR if bit 1 of PVDR_A */
mov.l PVDR_A, r1
mov.l PVDR_D, r2
mov.b @r1, r0
--
1.9.0
--
Nobuhiro Iwamatsu
iwamatsu at {nigauri.org / debian.org}
GPG ID: 40AD1FA6
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Re: [U-Boot] [PATCH] sh: fix PFC registers definition for SH772{2, 3, 4}
Appied, thanks!
Best regards,
Nobuhiro
2014-03-10 22:05 GMT+09:00 Baruch Siach bar...@tkos.co.il:
Add missing port X data register, and fix the offset of ports Y and Z.
Signed-off-by: Baruch Siach bar...@tkos.co.il
---
I only have access to the SH7724 manual. But since the Linux kernel driver
includes PXDR definition for SH7722 and SH7723, I assume this change is
correct
for them as well.
---
arch/sh/include/asm/cpu_sh7722.h | 5 +++--
arch/sh/include/asm/cpu_sh7723.h | 5 +++--
arch/sh/include/asm/cpu_sh7724.h | 5 +++--
3 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/sh/include/asm/cpu_sh7722.h
b/arch/sh/include/asm/cpu_sh7722.h
index 7be37ae98421..bf57e18a64ee 100644
--- a/arch/sh/include/asm/cpu_sh7722.h
+++ b/arch/sh/include/asm/cpu_sh7722.h
@@ -1250,8 +1250,9 @@
#define PUDR0xA4050162
#define PVDR0xA4050164
#define PWDR0xA4050166
-#define PYDR0xA4050168
-#define PZDR0xA405016A
+#define PXDR0xA4050168
+#define PYDR0xA405016A
+#define PZDR0xA405016C
/* UBC */
#define CBR00xFF20
diff --git a/arch/sh/include/asm/cpu_sh7723.h
b/arch/sh/include/asm/cpu_sh7723.h
index 3af0b0db2f8b..9d8cb8db444d 100644
--- a/arch/sh/include/asm/cpu_sh7723.h
+++ b/arch/sh/include/asm/cpu_sh7723.h
@@ -178,8 +178,9 @@
#define PUDR0xA4050162
#define PVDR0xA4050164
#define PWDR0xA4050166
-#define PYDR0xA4050168
-#define PZDR0xA405016A
+#define PXDR0xA4050168
+#define PYDR0xA405016A
+#define PZDR0xA405016C
/* UBC */
/* H-UDI */
diff --git a/arch/sh/include/asm/cpu_sh7724.h
b/arch/sh/include/asm/cpu_sh7724.h
index 2c2a474d37fa..88c418a17f82 100644
--- a/arch/sh/include/asm/cpu_sh7724.h
+++ b/arch/sh/include/asm/cpu_sh7724.h
@@ -200,8 +200,9 @@
#define PUDR0xA4050162
#define PVDR0xA4050164
#define PWDR0xA4050166
-#define PYDR0xA4050168
-#define PZDR0xA405016A
+#define PXDR0xA4050168
+#define PYDR0xA405016A
+#define PZDR0xA405016C
/* Ether */
#define EDMR 0xA460
--
1.9.0
--
Nobuhiro Iwamatsu
iwamatsu at {nigauri.org / debian.org}
GPG ID: 40AD1FA6
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