[U-Boot] [PATCH v2 0/2] ARM: atmel: sama5d3xek: enable NOR flash support
Add NOR flash support on sama5d3xek board. Then, we can use NOR flash related command to access it. Changes in v2: - Add CONFIG_SYS_FLASH_PROTECTION - Correct the max sector number Bo Shen (2): ARM: atmel: sama5d3xek: add nor flash init function ARM: atmel: sama5d3xek: enable NOR flash support board/atmel/sama5d3xek/sama5d3xek.c | 58 + include/configs/sama5d3xek.h| 13 - 2 files changed, 70 insertions(+), 1 deletion(-) -- 1.8.5.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] ARM: atmel: sama5d3xek: add nor flash init function
Add NOR flash hardware init function, including SMC and PIO
configuration.
Signed-off-by: Bo Shen voice.s...@atmel.com
---
Changes in v2: None
board/atmel/sama5d3xek/sama5d3xek.c | 58 +
1 file changed, 58 insertions(+)
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c
b/board/atmel/sama5d3xek/sama5d3xek.c
index c835c12..f53754b 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -67,6 +67,61 @@ void sama5d3xek_nand_hw_init(void)
}
#endif
+#ifndef CONFIG_SYS_NO_FLASH
+static void sama5d3xek_nor_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+ at91_periph_clk_enable(ATMEL_ID_SMC);
+
+ /* Configure SMC CS0 for NOR flash */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+ smc-cs[0].setup);
+ writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) |
+ AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11),
+ smc-cs[0].pulse);
+ writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14),
+ smc-cs[0].cycle);
+ writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0) |
+ AT91_SMC_TIMINGS_TAR(0) | AT91_SMC_TIMINGS_TRR(0) |
+ AT91_SMC_TIMINGS_TWB(0) | AT91_SMC_TIMINGS_RBNSEL(0)|
+ AT91_SMC_TIMINGS_NFSEL(0), smc-cs[0].timings);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_16 |
+ AT91_SMC_MODE_TDF_CYCLE(1),
+ smc-cs[0].mode);
+
+ /* Address pin (A1 ~ A23) configuration */
+ at91_set_a_periph(AT91_PIO_PORTE, 1, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 2, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 3, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 4, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 5, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 6, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 7, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 8, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 9, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 10, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 11, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 12, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 13, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 14, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 15, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 16, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 17, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 18, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 19, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 20, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 21, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 22, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 23, 0);
+ /* CS0 pin configuration */
+ at91_set_a_periph(AT91_PIO_PORTE, 26, 0);
+}
+#endif
+
#ifdef CONFIG_CMD_USB
static void sama5d3xek_usb_hw_init(void)
{
@@ -181,6 +236,9 @@ int board_init(void)
#ifdef CONFIG_NAND_ATMEL
sama5d3xek_nand_hw_init();
#endif
+#ifndef CONFIG_SYS_NO_FLASH
+ sama5d3xek_nor_hw_init();
+#endif
#ifdef CONFIG_CMD_USB
sama5d3xek_usb_hw_init();
#endif
--
1.8.5.2
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[U-Boot] [PATCH v2 2/2] ARM: atmel: sama5d3xek: enable NOR flash support
Signed-off-by: Bo Shen voice.s...@atmel.com --- Changes in v2: - Add CONFIG_SYS_FLASH_PROTECTION - Correct the max sector number include/configs/sama5d3xek.h | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index da27180..844416f 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -79,8 +79,19 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME -/* No NOR flash */ +/* NOR flash */ +#define CONFIG_CMD_FLASH + +#ifdef CONFIG_CMD_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_BASE 0x1000 +#define CONFIG_SYS_MAX_FLASH_SECT 131 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#else #define CONFIG_SYS_NO_FLASH +#endif /* * Command line configuration. -- 1.8.5.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] km-powerpc: define CONFIG_PRAM to protect PHRAM and PNVRAM
Hello Wolfgang, On 07/17/2014 02:47 PM, Wolfgang Denk wrote: Dear Valentin, In message 1405599840-11984-1-git-send-email-valentin.longch...@keymile.com you wrote: When u-boot initializes the RAM (early in boot) it looks for the pram env variable to know which is area it cannot use. At this early boot stage, the pram env variable is not avaible yet since it gets computed in set_km_env that gets called AFTER the RAM initialization. If the pram env variable is not found, the default CONFIG_PRAM value is used. Note that I am not objecting against this patch, but I highly recommend to fix your board - RAM initialization is actually pretty late in the init sequence, and you should have a valid envionment long before. Maybe my commit message is unclear about this. You are right, at the RAM initialization time, there is a valid environment, and that's the case on our board too. However, at the very first boot on a board, the environment is empty (or unvalid) and the default one is used where this pram env variable is not defined. That's why the CONFIG_PRAM is used in this case and it should be defined. This is not going to be the case at any later boot if a valid environment (with pram defined) is found and used. Best regards, Valentin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/5] sunxi: Add axp209 pmic support
Hi,
On 07/17/2014 09:14 PM, Ian Campbell wrote:
On Thu, 2014-07-17 at 12:37 +0200, Hans de Goede wrote:
Hi,
On 07/16/2014 11:48 PM, Ian Campbell wrote:
On Fri, 2014-06-13 at 22:55 +0200, Hans de Goede wrote:
From: Henrik Nordstrom hen...@henriknordstrom.net
Add support for the x-powers axp209 pmic which is found on most A10, A13
and
A20 boards.
And enable AXP209 support for the Cubietruck and Cubieboard boards.
Something about this breaks booting on my Cubietruck in FEL mode. I get:
U-Boot SPL 2014.07-rc4-00122-g624959a (Jul 16 2014 - 22:34:59)
Error, wrong i2c adapter 0 max 0 possible
Error, wrong i2c adapter 0 max 0 possible
And then nothing.
If you look at the patch adding support for the i2c controller I needed
to make some changes to the link script, I probably forgot to make the
same changes to the fel link script...
That was indeed it. With your ACK I'd like to fold in this change:
- - a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
+ + b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
@@ -27,6 +27,11 @@ SECTIONS
}
. = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
. = .;
. = ALIGN(4);
Looks good, ACK.
While changing the boards.cfg lines for the Cubietruck, add Ian and me as
board
maintainers for the Cubietruck.
You actually factored that bit out in v2...
True, feel free to amend the commit msg, or let me know if you want a v3.
I'll amend while I'm there.
And thanks for looking into merging this into sunxi -next. I was planning to
drop you a mail about coordinating getting this added vs getting your ahci
patches added. I assume you ahci patches are good to go too, or ... ?
I've picked up the non-AHCI bits of that series now but not the common
bits which I'm assuming Albert will pick up when he gets back, the
actual driver then depends on those. So I've picked up and intend to
include in the first PR:
[U-Boot,3/6] sunxi: add Cubieboard2 support
[U-Boot,4/6] sunxi: add gpio driver
[U-Boot,5/6] sunxi: use setbits_le32 to enable the DMA clock
These I am expecting to come via Albert (or for him to ask me to merge):
[U-Boot,1/6] AHCI: Increase link timeout to 200ms
[U-Boot,2/6] board_r: run scsi init() on ARM too
and then the last one
[U-Boot,6/6] ahci: provide sunxi SATA driver using AHCI platform framework
either Albert can pick up or it can come in a subsequent PR.
Ok.
Other than those there are Roman's USB patch which are still under review.
Next I want to start adding support for more boards. For starters I would
like to add all boards which also have a dts file in the upstream kernel.
Ideally I would start working on that once you're done with adding this
series + your ahci patches so that we don't get in each others way. Can you
send me a mail when you're done (for a while at least) then I'll try to
get a set of patches for this to the list based on top of your latest work.
Sure, I'll drop you a line.
Except for sun4i-a10-hackberry.dts and sun4i-a10-inet97fv2.dts I've hardware
to test on for all sun4i, sun5i and sun7i models which have a dts file, not
sure what to do with the 2 I cannot test.
Either leave them out or approach the person who wrote the dts (who
presumably has one, or isthat asking too much) to test?
I can ask some people to test yes, but what do we then put in the MAINTAINER
column of boards.cfg ? I think it would be best to ask people to step us as
board maintainer for these, instead of just test. Do you agree ?
Regards,
Hans
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[U-Boot] [PATCH v1 0/3] ARM: omap: clean GPMC macros
This patch cleans redundant and unused macros from various board-configs and architecture specific header files. Tested using: MAKEALL -s omap 3 -s omap4 -s omap5 -s am33xx with $ARCH=arm $CROSS_COMPILE=arm-linux-gnueabihf- Pekon Gupta (3): ARM: omap: fix GPMC address-map size for NAND and NOR devices ARM: omap: clean redundant PISMO_xx macros used in OMAP3 ARM: omap: move board specific NAND configs out from ti_armv7_common.h arch/arm/cpu/armv7/omap-common/mem-common.c | 14 ++ arch/arm/include/asm/arch-am33xx/mem.h | 7 --- arch/arm/include/asm/arch-omap3/cpu.h | 1 - arch/arm/include/asm/arch-omap3/mem.h | 13 - doc/README.nand | 12 include/configs/am335x_evm.h| 6 ++ include/configs/am3517_crane.h | 7 +-- include/configs/am3517_evm.h| 7 +-- include/configs/cm_t335.h | 5 + include/configs/cm_t35.h| 3 --- include/configs/devkit8000.h| 2 -- include/configs/dig297.h| 4 include/configs/mcx.h | 4 include/configs/nokia_rx51.h| 2 -- include/configs/omap3_beagle.h | 13 +++-- include/configs/omap3_evm_common.h | 7 ++- include/configs/omap3_igep00x0.h| 10 +++--- include/configs/omap3_logic.h | 8 ++-- include/configs/omap3_overo.h | 12 +++- include/configs/omap3_pandora.h | 7 +-- include/configs/omap3_zoom1.h | 13 +++-- include/configs/pengwyn.h | 6 ++ include/configs/tam3517-common.h| 4 include/configs/tao3530.h | 7 +-- include/configs/ti_armv7_common.h | 8 include/configs/tricorder.h | 2 -- 26 files changed, 75 insertions(+), 109 deletions(-) -- 1.8.5.1.163.gd7aced9 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 3/3] ARM: omap: move board specific NAND configs out from ti_armv7_common.h
This patch moves some board specific NAND configs: - FROM: generic config file 'ti_armv7_common.h' - TO: individual board config files using these configs. So that each board can independently set the value as per its design. Following configs are affected in this patch: CONFIG_SYS_NAND_U_BOOT_OFFS: refer doc/README.nand CONFIG_CMD_SPL_NAND_OFS: refer doc/README.falcon CONFIG_SYS_NAND_SPL_KERNEL_OFFS: refer doc/README.falcon CONFIG_CMD_SPL_WRITE_SIZE: refer doc/README.falcon This patch also updates documentation for few of above NAND configs. Signed-off-by: Pekon Gupta pe...@ti.com --- doc/README.nand | 12 include/configs/am335x_evm.h | 5 + include/configs/cm_t335.h | 5 + include/configs/omap3_beagle.h| 6 ++ include/configs/omap3_igep00x0.h | 7 +++ include/configs/omap3_overo.h | 6 ++ include/configs/omap3_zoom1.h | 6 ++ include/configs/pengwyn.h | 6 ++ include/configs/ti_armv7_common.h | 8 9 files changed, 53 insertions(+), 8 deletions(-) diff --git a/doc/README.nand b/doc/README.nand index 70cf768..e29188f 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -89,6 +89,10 @@ Commands: Configuration Options: + CONFIG_SYS_NAND_U_BOOT_OFFS + NAND Offset from where SPL will read u-boot image. This is the starting + address of u-boot MTD partition in NAND. + CONFIG_CMD_NAND Enables NAND support and commmands. @@ -226,6 +230,14 @@ Platform specific options detection. However ECC calculation on such plaforms would still be done by GPMC controller. + CONFIG_SPL_NAND_AM33XX_BCH + Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based +hardware ECC correction. This is useful for platforms which have ELM + hardware engine and use NAND boot mode. + Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, + so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling +SPL-NAND driver with software ECC correction support. + CONFIG_NAND_OMAP_ECCSCHEME On OMAP platforms, this CONFIG specifies NAND ECC scheme. It can take following values: diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index c1a6ada..f5bfd5d 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -254,6 +254,11 @@ #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS0x8 +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS0x0008 /* os parameters */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS0x0020 /* kernel offset */ +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif #endif #endif diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h index 4d1dd28..a3e6452 100644 --- a/include/configs/cm_t335.h +++ b/include/configs/cm_t335.h @@ -150,6 +150,11 @@ #define CONFIG_ENV_OFFSET 0x30 /* environment starts here */ #define CONFIG_SYS_ENV_SECT_SIZE (128 10) /* 128 KiB */ #define CONFIG_SYS_NAND_ONFI_DETECTION +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS0x40 /* un-assigned: (using dtb) */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS0x50 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif /* GPIO pin + bank to pin ID mapping */ #define GPIO_PIN(_bank, _pin) ((_bank 5) + _pin) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 74a3d1a..b665979 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -304,5 +304,11 @@ #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_OFFS0x8 +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS0x24 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS0x28 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 0bb79ab..006c9a9 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -196,6 +196,13 @@ #define CONFIG_SYS_NAND_ECCSIZE512 #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW +#define CONFIG_SYS_NAND_U_BOOT_OFFS0x8 +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS0x24 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS0x28 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif #endif #endif /* __IGEP00X0_H */ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 38f8dab..e66f306 100644 --- a/include/configs/omap3_overo.h +++
[U-Boot] [PATCH v1 1/3] ARM: omap: fix GPMC address-map size for NAND and NOR devices
Fixes commit a0a37183bd75e74608bc78c8d0e2a34454f95a91
ARM: omap: merge GPMC initialization code for all platform
1) NAND device are not directly memory-mapped to CPU address-space, they are
indirectly accessed via following GPMC registers:
- GPMC_NAND_COMMAND_x
- GPMC_NAND_ADDRESS_x
- GPMC_NAND_DATA_x
Therefore from CPU's point of view, NAND address-map can be limited to just
above register addresses. But GPMC chip-select address-map can be configured
in granularity of 16MB only.
So this patch uses GPMC_SIZE_16M for all NAND devices.
2) NOR device are directly memory-mapped to CPU address-space, so its
address-map size depends on actual addressable region in NOR FLASH device.
So this patch uses CONFIG_SYS_FLASH_SIZE to derive GPMC chip-select address-map
size configuration.
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/cpu/armv7/omap-common/mem-common.c | 10 --
include/configs/am335x_evm.h| 1 +
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c
b/arch/arm/cpu/armv7/omap-common/mem-common.c
index 5bc7e1f..05b81e0 100644
--- a/arch/arm/cpu/armv7/omap-common/mem-common.c
+++ b/arch/arm/cpu/armv7/omap-common/mem-common.c
@@ -87,8 +87,13 @@ void gpmc_init(void)
STNOR_GPMC_CONFIG6,
STNOR_GPMC_CONFIG7
};
- u32 size = GPMC_SIZE_16M;
u32 base = CONFIG_SYS_FLASH_BASE;
+ u32 size = (CONFIG_SYS_FLASH_SIZE 0x0800) ? GPMC_SIZE_256M :
+ /* 64MB */((CONFIG_SYS_FLASH_SIZE 0x0400) ? GPMC_SIZE_128M :
+ /* 32MB */((CONFIG_SYS_FLASH_SIZE 0x0200) ? GPMC_SIZE_64M :
+ /* 16MB */((CONFIG_SYS_FLASH_SIZE 0x0100) ? GPMC_SIZE_32M :
+ /* min 16MB */ GPMC_SIZE_16M)));
+
#elif defined(CONFIG_NAND)
/* configure GPMC for NAND */
const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1,
@@ -99,8 +104,9 @@ void gpmc_init(void)
M_NAND_GPMC_CONFIG6,
0
};
- u32 size = GPMC_SIZE_256M;
u32 base = CONFIG_SYS_NAND_BASE;
+ u32 size = GPMC_SIZE_16M;
+
#elif defined(CONFIG_CMD_ONENAND)
const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1,
ONENAND_GPMC_CONFIG2,
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index a48b386..c1a6ada 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -453,6 +453,7 @@
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BASE (0x0800)
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_SIZE 0x0100
#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_FLASH_BASE
/* Reduce SPL size by removing unlikey targets */
#ifdef CONFIG_NOR_BOOT
--
1.8.5.1.163.gd7aced9
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[U-Boot] [PATCH v1 2/3] ARM: omap: clean redundant PISMO_xx macros used in OMAP3
PISMO_xx macros were used to define 'Platform Independent Storage MOdule'
related GPMC configurations. This patch
- Replaces these OMAP3 specific macros with generic CONFIG_xx macros as provided
by current u-boot infrastructure.
- Removes unused redundant macros, which are no longer required after
merging of common platform code in following commit
commit a0a37183bd75e74608bc78c8d0e2a34454f95a91
ARM: omap: merge GPMC initialization code for all platform
+-+---+
| Macro | Reason for removal|
+-+---+
| PISMO1_NOR_BASE | duplicate of CONFIG_SYS_FLASH_BASE|
+-+---+
| PISMO1_NAND_BASE| duplicate of CONFIG_SYS_NAND_BASE |
+-+---+
| PISMO1_ONEN_BASE| duplicate of CONFIG_SYS_ONENAND_BASE |
+-+---+
| PISMO1_NAND_SIZE| GPMC accesses NAND device via I/O mapped registers so |
| | configuring GPMC chip-select for smallest allowable |
| | segment (GPMC_SIZE_16M) is enough.|
+-+---+
| PISMO1_ONEN_SIZE| OneNAND uses a fixed GPMC chip-select address-space of|
| | 128MB (GPMC_SIZE_128M)|
+-+---+
+-+---+
| PISMO1_NOR | Unused Macros|
| PISMO1_NAND | |
| PISMO2_CS0 | |
| PISMO2_CS1 | |
| PISMO1_ONENAND | |
| PISMO2_NAND_CS0 | |
| PISMO2_NAND_CS1 | |
| PISMO1_NOR_BASE | |
| PISMO1_NAND_BASE| |
| PISMO2_CS0_BASE | |
+-+---+
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/cpu/armv7/omap-common/mem-common.c | 4 ++--
arch/arm/include/asm/arch-am33xx/mem.h | 7 ---
arch/arm/include/asm/arch-omap3/cpu.h | 1 -
arch/arm/include/asm/arch-omap3/mem.h | 13 -
include/configs/am3517_crane.h | 7 +--
include/configs/am3517_evm.h| 7 +--
include/configs/cm_t35.h| 3 ---
include/configs/devkit8000.h| 2 --
include/configs/dig297.h| 4
include/configs/mcx.h | 4
include/configs/nokia_rx51.h| 2 --
include/configs/omap3_beagle.h | 7 +--
include/configs/omap3_evm_common.h | 7 ++-
include/configs/omap3_igep00x0.h| 3 ---
include/configs/omap3_logic.h | 8 ++--
include/configs/omap3_overo.h | 6 +-
include/configs/omap3_pandora.h | 7 +--
include/configs/omap3_zoom1.h | 7 +--
include/configs/tam3517-common.h| 4
include/configs/tao3530.h | 7 +--
include/configs/tricorder.h | 2 --
21 files changed, 13 insertions(+), 99 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c
b/arch/arm/cpu/armv7/omap-common/mem-common.c
index 05b81e0..573ea1e 100644
--- a/arch/arm/cpu/armv7/omap-common/mem-common.c
+++ b/arch/arm/cpu/armv7/omap-common/mem-common.c
@@ -116,8 +116,8 @@ void gpmc_init(void)
ONENAND_GPMC_CONFIG6,
0
};
- u32 base = PISMO1_ONEN_BASE;
- u32 size = PISMO1_ONEN_SIZE;
+ u32 size = GPMC_SIZE_128M;
+ u32 base = CONFIG_SYS_ONENAND_BASE;
#else
const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
u32 size = 0;
diff --git a/arch/arm/include/asm/arch-am33xx/mem.h
b/arch/arm/include/asm/arch-am33xx/mem.h
index e7e8c58..b2412b5 100644
--- a/arch/arm/include/asm/arch-am33xx/mem.h
+++ b/arch/arm/include/asm/arch-am33xx/mem.h
@@ -59,13 +59,6 @@
/* max number of GPMC regs */
#define GPMC_MAX_REG 7
Re: [U-Boot] [PATCH v2 3/5] sunxi: Add axp209 pmic support
On Fri, 2014-07-18 at 12:04 +0200, Hans de Goede wrote: Looks good, ACK. Thanks, will prep the PR ASAP. Either leave them out or approach the person who wrote the dts (who presumably has one, or isthat asking too much) to test? I can ask some people to test yes, but what do we then put in the MAINTAINER column of boards.cfg ? I think it would be best to ask people to step us as board maintainer for these, instead of just test. Do you agree ? That seem reasonable to me. Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] enabling ecc on P2041 and QoreIQ familly not valid for memory = 4GB
Hi ,
I found out an issue when enabling ECC for P2041 platform with an amount
of memory of 8GB.
The routine void dma_meminit(uint val, uint size) is not adapted to
manage memory size greater or equal to 4GB due to the 'uint' type.
With this typing the dma_meminit sees 0 as size when memory is for
example at 8GB. So the ECC part of the memory is not initialized and
when going in memory the code crash.
To correct it you need to use phys_size_t type instead of uint.
It is the same thing for all routines that are called by dma_meminit.
I attached a patch that able to correct it easily.
This patch should be integrated in the main branch I think so.
Regards,
Benoit
diff -u vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_ddr_sdram.h:1.1.1.1
vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_ddr_sdram.h:1.2
--- vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_ddr_sdram.h:1.1.1.1
Tue Jan 8 10:23:37 2013
+++ vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_ddr_sdram.h Fri Jul
18 10:31:22 2014
@@ -308,7 +308,7 @@
#endif
#if defined(CONFIG_DDR_ECC)
-extern void ddr_enable_ecc(unsigned int dram_size);
+extern void ddr_enable_ecc(phys_size_t dram_size);
#endif
diff -u vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_dma.h:1.1.1.1
vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_dma.h:1.2
--- vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_dma.h:1.1.1.1Tue Jan
8 10:23:37 2013
+++ vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_dma.hFri Jul 18
10:31:22 2014
@@ -134,7 +134,7 @@
void dma_init(void);
int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n);
#if (defined(CONFIG_DDR_ECC) !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
-void dma_meminit(uint val, uint size);
+void dma_meminit(uint val, phys_size_t size);
#endif
#endif
diff -u vx3240/u-boot-2012.10/drivers/dma/fsl_dma.c:1.1.1.1
vx3240/u-boot-2012.10/drivers/dma/fsl_dma.c:1.2
--- vx3240/u-boot-2012.10/drivers/dma/fsl_dma.c:1.1.1.1 Tue Jan 8 10:23:55 2013
+++ vx3240/u-boot-2012.10/drivers/dma/fsl_dma.c Fri Jul 18 14:28:31 2014
@@ -113,14 +113,13 @@
while (count) {
xfer_size = MIN(FSL_DMA_MAX_SIZE, count);
-
out_dma32(dma-dar, (u32) (dest 0x));
out_dma32(dma-sar, (u32) (src 0x));
#if !defined(CONFIG_MPC83xx)
out_dma32(dma-satr,
- in_dma32(dma-satr) | (u32)((u64)src 32));
+ in_dma32(dma-satr) | (u32)(src 32));
out_dma32(dma-datr,
- in_dma32(dma-datr) | (u32)((u64)dest 32));
+ in_dma32(dma-datr) | (u32)(dest 32));
#endif
out_dma32(dma-bcr, xfer_size);
dma_sync();
@@ -152,33 +151,36 @@
#if ((!defined CONFIG_MPC83xx defined(CONFIG_DDR_ECC)\
!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) || \
(defined(CONFIG_MPC83xx) defined(CONFIG_DDR_ECC_INIT_VIA_DMA)))
-void dma_meminit(uint val, uint size)
+void dma_meminit(uint val, phys_size_t size)
{
- uint *p = 0;
- uint i = 0;
-
- for (*p = 0; p (uint *)(8 * 1024); p++) {
- if (((uint)p 0x1f) == 0)
- ppcDcbz((ulong)p);
-
- *p = (uint)CONFIG_MEM_INIT_VALUE;
-
- if (((uint)p 0x1c) == 0x1c)
- ppcDcbf((ulong)p);
- }
-
- dmacpy(0x002000, 0, 0x002000); /* 8K */
- dmacpy(0x004000, 0, 0x004000); /* 16K */
- dmacpy(0x008000, 0, 0x008000); /* 32K */
- dmacpy(0x01, 0, 0x01); /* 64K */
- dmacpy(0x02, 0, 0x02); /* 128K */
- dmacpy(0x04, 0, 0x04); /* 256K */
- dmacpy(0x08, 0, 0x08); /* 512K */
- dmacpy(0x10, 0, 0x10); /* 1M */
- dmacpy(0x20, 0, 0x20); /* 2M */
- dmacpy(0x40, 0, 0x40); /* 4M */
-
- for (i = 1; i size / 0x80; i++)
- dmacpy((0x80 * i), 0, 0x80);
+ uint *p = 0;
+ u64 i = 0;
+ phys_addr_t addr;
+
+ for (*p = 0; p (uint *)(8 * 1024); p++) {
+if (((uint)p 0x1f) == 0)
+ ppcDcbz((ulong)p);
+
+*p = (uint)CONFIG_MEM_INIT_VALUE;
+
+if (((uint)p 0x1c) == 0x1c)
+ ppcDcbf((ulong)p);
+ }
+
+ dmacpy(0x002000, 0, 0x002000); /* 8K */
+ dmacpy(0x004000, 0, 0x004000); /* 16K */
+ dmacpy(0x008000, 0, 0x008000); /* 32K */
+ dmacpy(0x01, 0, 0x01); /* 64K */
+ dmacpy(0x02, 0, 0x02); /* 128K */
+ dmacpy(0x04, 0, 0x04); /* 256K */
+ dmacpy(0x08, 0, 0x08); /* 512K */
+ dmacpy(0x10, 0, 0x10); /* 1M */
+ dmacpy(0x20, 0, 0x20); /* 2M */
+ dmacpy(0x40, 0, 0x40); /* 4M */
+
+ for (i = 1; i size / 0x80; i++) {
+addr = (phys_addr_t) (i * 0x80);
+dmacpy(addr, (phys_addr_t)0, 0x80);
+ }
}
#endif
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[U-Boot] [PATCH v4] Add TQ Systems TQMa6 board support
From: Markus Niebel markus.nie...@tq-group.com This patch adds the changes to boards.cfg and the board directory under board/tqc. TQMa6 is a family of modules based on Freescale i.MX6. It consists of TQMa6Q (i.MX6 Quad), TQMa6D (i.MX6 Dual) featuring eMMC, and 1 GiB DDR3 TQMa6S (i.MX6 Solo) featuring eMMC and 512 MiB DDR3 The modules need a baseboard. Initially the MBa6x starterkit mainboard is supported. To easy support for other mainboards the functionality is splitted in one file for the module (tqma6.c) and one file for the baseboard (tqma6_ mba6). The modules can be boot from eMMC (on USDHC3) and SPI flash. The following features are supported: - MMC: eMMC on module (on USDHC3) and SD-card (on MBa6x mainboard) - Ethernet: RGMII using micrel KSZ9031 phy on MBa6x mainboard for TQMa6x module. The phy needs special configurations for the pad skew registers to adjust for the signal routing. Also support for standard ethernet commands and uppdate via tftp. - SPI: ECSPI1 with bootable serial flash on module and two additional chip selects on MBa6x - I2C: This patch adds support for the I2C busses on the TQMa6x modules (I2C3) and MBa6x baseboards (I2C1). The LM75 temperature sensors on TQMa6x and MBa6x are also configured. - USB: high speed host 1 on MBa6x and support for USB storage - PMIC: support for pfuze 100 on TQMa6x Signed-off-by: Markus Niebel markus.nie...@tq-group.com --- History: - changes for v4: - rebase to current u-boot-imx - implement suggestions from S. Babic - remove checkpatch warnings - use puts wherever possible - change dynamic env board to board_name - define for PMIC I2C Bus - add comment to the RGMII pad skew settings on baseboard - prefix board specific defines in config header with TQMA6_ instead of CONFIG_ - optimize memory mapping (u-boot to end of DRAM, change FDT placement) - change eMMC DSR fixup (patch posted to linux mainline) - use rootpath instead of nfsroot in env (all other boards do so) - changes for v3: - squash the patches as suggested by S. Babic - fix copy and paste error for MBa6x SD-Card slot - fix WP handling for MBa6x SD-Card slot - move PMIC init to board_late_init (power_init_board() does not work) - changes for v2: - fix long line warning as suggested by W. Denk - remove baudrate from CONFIG_EXTRA_ENV_SETTINGS - remove unused define CONFIG_TQMA6X_BASEBOARD_NAME - add missing mmcblkdev definition to mmcboot logic in CONFIG_EXTRA_ENV_SETTINGS - add missing stuff for tftp and nfs in CONFIG_EXTRA_ENV_SETTINGS - fix fdt_file in env (was partially fdt) - add missing int power_init_board(void) to tqma6.c board/tqc/tqma6/Makefile |9 + board/tqc/tqma6/README | 35 +++ board/tqc/tqma6/clocks.cfg | 24 +++ board/tqc/tqma6/tqma6.c | 262 +++ board/tqc/tqma6/tqma6_bb.h | 30 +++ board/tqc/tqma6/tqma6_mba6.c | 361 +++ board/tqc/tqma6/tqma6q.cfg | 125 +++ board/tqc/tqma6/tqma6s.cfg | 125 +++ boards.cfg |4 + include/configs/tqma6.h | 483 ++ 10 files changed, 1458 insertions(+) create mode 100644 board/tqc/tqma6/Makefile create mode 100644 board/tqc/tqma6/README create mode 100644 board/tqc/tqma6/clocks.cfg create mode 100644 board/tqc/tqma6/tqma6.c create mode 100644 board/tqc/tqma6/tqma6_bb.h create mode 100644 board/tqc/tqma6/tqma6_mba6.c create mode 100644 board/tqc/tqma6/tqma6q.cfg create mode 100644 board/tqc/tqma6/tqma6s.cfg create mode 100644 include/configs/tqma6.h diff --git a/board/tqc/tqma6/Makefile b/board/tqc/tqma6/Makefile new file mode 100644 index 000..9ee6920 --- /dev/null +++ b/board/tqc/tqma6/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2014, Markus Niebel markus.nie...@tq-group.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := tqma6.o + +obj-$(CONFIG_MBA6) += tqma6_mba6.o diff --git a/board/tqc/tqma6/README b/board/tqc/tqma6/README new file mode 100644 index 000..2c012e7 --- /dev/null +++ b/board/tqc/tqma6/README @@ -0,0 +1,35 @@ +U-Boot for the TQ Systems TQMa6 modules + +This file contains information for the port of +U-Boot to the TQ Systems TQMa6 modules. + +1. Boot source +-- + +The following boot source is supported: + +- SD/eMMC +- SPI NOR + +2. Building + + +To build U-Boot for the TQ Systems TQMa6 modules: + + make tqma6x_baseboard_boot_config + make + +x is a placeholder for the CPU variant +q - means i.MX6Q/D: TQMa6Q (i.MX6Q) and TQMa6D (i.MX6D) +s - means i.MX6S: TQMa6S (i.MX6S) + +baseboard is a placeholder for the boot device +mmc - means eMMC +spi - mean SPI NOR + +This gives the following configurations: + +tqma6q_mba6_mmc_config +tqma6q_mba6_spi_config +tqma6s_mba6_mmc_config +tqma6s_mba6_spi_config diff --git a/board/tqc/tqma6/clocks.cfg b/board/tqc/tqma6/clocks.cfg new file mode 100644 index 000..d9dd273 ---
Re: [U-Boot] uboot/odroid test report
Hello Daniel,
On 07/17/2014 05:35 PM, Daniel Drake wrote:
On Thu, Jul 17, 2014 at 3:59 PM, Przemyslaw Marczak
p.marc...@samsung.com wrote:
So BL1, BL2 are running in iRAM(required small size), and u-boot is running
from a RAM.
The main reason for using existing BL1 and BL2 binaries is
that bl1 and bl2 are just working proper.
Fair enough, I was just a bit worried/curious that bl2 is only working
by accident, and we have some strange mashup of 2 uboot versions
involved in the boot process.
I will check it tomorrow but it has works on Ubuntu.
The bootz command takes only 2 arguments here - ${image_addr}
${ramdisk_addr} which are the numbers set by:
run check_dtb and run check_ramdisk
Maybe I made a mistake in my testing then, either way I've moved onto
a custom boot script now.
But just to clarify the bootz usage..
image_addr is defined as:
setenv image_addr ${kerneladdr} - ${fdtaddr};
so with
bootz ${image_addr} ${ramdisk_addr};
you are actually passing
bootz ${kerneladdr} - ${fdtaddr} ${ramdisk_addr};
Maybe it works for you, although the documentation suggests its usage
is not quite like that:
static char bootz_help_text[] =
[addr [initrd[:size]] [fdt]]\n
- boot Linux zImage stored in memory\n
\tThe argument 'initrd' is optional and specifies the address\n
\tof the initrd in memory. The optional argument ':size' allows\n
\tspecifying the size of RAW initrd.\n
#if defined(CONFIG_OF_LIBFDT)
\tWhen booting a Linux kernel which requires a flat device-tree\n
\ta third argument is required which is the address of the\n
\tdevice-tree blob. To boot that kernel without an initrd image,\n
\tuse a '-' for the second argument. If you do not pass a third\n
\ta bd_info struct will be passed instead\n
#endif
;
#endif
Daniel
You were right. I made a mistake, but even that - the ramdisk for ubuntu
was loaded - because of kernel without fdt.
Thank you for testing, I will fix this and send the patches again.
Regards,
--
Przemyslaw Marczak
Samsung RD Institute Poland
Samsung Electronics
p.marc...@samsung.com
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[U-Boot] [PATCH v6 03/12] arch:exynos: boot mode: add get_boot_mode(), code cleanup
This patch introduces code clean-up for exynos boot mode check.
It includes:
- removal of typedef: boot_mode
- move the boot mode enum to arch-exynos/power.h
- add bootmode for sequence: eMMC 4.4 ch4 / SD ch2
- add new function: get_boot_mode() for OM[5:1] pin check
- update spl boot code
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Changes v5:
- exynos: boot mode: add missing bootmode (1st:EMMC 4.4 / 2nd:SD ch2)
---
arch/arm/cpu/armv7/exynos/power.c| 7 +++
arch/arm/cpu/armv7/exynos/spl_boot.c | 5 ++---
arch/arm/include/asm/arch-exynos/power.h | 21 +
arch/arm/include/asm/arch-exynos/spl.h | 17 ++---
4 files changed, 32 insertions(+), 18 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/power.c
b/arch/arm/cpu/armv7/exynos/power.c
index 638ee0b..e1ab3d6 100644
--- a/arch/arm/cpu/armv7/exynos/power.c
+++ b/arch/arm/cpu/armv7/exynos/power.c
@@ -202,3 +202,10 @@ void power_exit_wakeup(void)
else
exynos4_power_exit_wakeup();
}
+
+unsigned int get_boot_mode(void)
+{
+ unsigned int om_pin = samsung_get_base_power();
+
+ return readl(om_pin) OM_PIN_MASK;
+}
diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c
b/arch/arm/cpu/armv7/exynos/spl_boot.c
index 7916630..87f9214 100644
--- a/arch/arm/cpu/armv7/exynos/spl_boot.c
+++ b/arch/arm/cpu/armv7/exynos/spl_boot.c
@@ -20,7 +20,6 @@
#include clock_init.h
DECLARE_GLOBAL_DATA_PTR;
-#define OM_STAT (0x1f 1)
/* Index into irom ptr table */
enum index {
@@ -184,7 +183,7 @@ static void exynos_spi_copy(unsigned int uboot_size,
unsigned int uboot_addr)
*/
void copy_uboot_to_ram(void)
{
- enum boot_mode bootmode = BOOT_MODE_OM;
+ u32 bootmode = BOOT_MODE_OM;
u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
u32 offset = 0, size = 0;
@@ -207,7 +206,7 @@ void copy_uboot_to_ram(void)
#endif
if (bootmode == BOOT_MODE_OM)
- bootmode = readl(samsung_get_base_power()) OM_STAT;
+ bootmode = get_boot_mode();
switch (bootmode) {
#ifdef CONFIG_SPI_BOOTING
diff --git a/arch/arm/include/asm/arch-exynos/power.h
b/arch/arm/include/asm/arch-exynos/power.h
index 4f2447b..1c0f144 100644
--- a/arch/arm/include/asm/arch-exynos/power.h
+++ b/arch/arm/include/asm/arch-exynos/power.h
@@ -1670,6 +1670,27 @@ struct exynos5420_power {
};
#endif /* __ASSEMBLY__ */
+#define OM_PIN_BITS0x1f
+#define OM_PIN_SHIFT 0x1
+#define OM_PIN_MASK(OM_PIN_BITS OM_PIN_SHIFT)
+
+enum {
+ /*
+* Assign the OM pin values for respective boot modes.
+* Exynos4 does not support spi boot and the mmc boot OM
+* pin values are the same across Exynos4 and Exynos5.
+*/
+ BOOT_MODE_MMC = 4, /* SD_CH2 | USB */
+ BOOT_MODE_EMMC = 8, /* EMMC4.4 | USB */
+ BOOT_MODE_EMMC_SD = 40, /* EMMC4.4 | SD_CH2 */
+ BOOT_MODE_SERIAL = 20,
+ /* Boot based on Operating Mode pin settings */
+ BOOT_MODE_OM = 32,
+ BOOT_MODE_USB, /* Boot using USB download */
+};
+
+unsigned int get_boot_mode(void);
+
void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable);
#define EXYNOS_MIPI_PHY_ENABLE (1 0)
diff --git a/arch/arm/include/asm/arch-exynos/spl.h
b/arch/arm/include/asm/arch-exynos/spl.h
index b1d68c3..cdcb2bc 100644
--- a/arch/arm/include/asm/arch-exynos/spl.h
+++ b/arch/arm/include/asm/arch-exynos/spl.h
@@ -8,20 +8,7 @@
#define __ASM_ARCH_EXYNOS_SPL_H__
#include asm/arch-exynos/dmc.h
-
-enum boot_mode {
- /*
-* Assign the OM pin values for respective boot modes.
-* Exynos4 does not support spi boot and the mmc boot OM
-* pin values are the same across Exynos4 and Exynos5.
-*/
- BOOT_MODE_MMC = 4,
- BOOT_MODE_EMMC = 8, /* EMMC4.4 */
- BOOT_MODE_SERIAL = 20,
- /* Boot based on Operating Mode pin settings */
- BOOT_MODE_OM = 32,
- BOOT_MODE_USB, /* Boot using USB download */
-};
+#include asm/arch/power.h
#ifndef __ASSEMBLY__
/* Parameters of early board initialization in SPL */
@@ -62,7 +49,7 @@ struct spl_machine_param {
* table only for mmc boot.
*/
u32 uboot_size;
- enum boot_mode boot_source;/* Boot device */
+ unsignedboot_source;/* Boot device */
unsignedfrequency_mhz; /* Frequency of memory in MHz */
unsignedarm_freq_mhz; /* ARM Frequency in MHz */
u32 serial_base;/* Serial base address */
--
1.9.1
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[U-Boot] [PATCH v6 00/12] Add support to Odroid U3/X2
This patch set introduces changes to common Samsung code as a preparation of new board support: - boot device check - code cleanup - automatic init order of mmc drivers - automatic setting of dfu entities which depends on boot device - pre reset function call for board own implementation - setting board info environment for multi board support New board config: - odroid_config - Odroid U3/X2 support V6 change: - fix ramdisk load issue Przemyslaw Marczak (12): samsung: misc: fix soc revision setting in the set_board_info() exynos: pinmux: fix the gpio names for exynos4x12 mmc arch:exynos: boot mode: add get_boot_mode(), code cleanup board:samsung: check the boot device and init the right mmc driver. samsung: misc: add function for setting $dfu_alt_info samsung:board: misc_init_r: call set_dfu_alt_info() arm:reset: call the reset_misc() before the cpu reset samsung: board: enable support of multiple board types samsung: misc: use board specific functions to set env board info odroid: add board file for Odroid X2/U3 based on Samsung Exynos4412 odroid: add odroid U3/X2 device tree description odroid: add odroid_config arch/arm/cpu/armv7/exynos/pinmux.c | 4 +- arch/arm/cpu/armv7/exynos/power.c| 7 + arch/arm/cpu/armv7/exynos/spl_boot.c | 5 +- arch/arm/dts/Makefile| 3 +- arch/arm/dts/exynos4412-odroid.dts | 70 + arch/arm/include/asm/arch-exynos/power.h | 21 ++ arch/arm/include/asm/arch-exynos/spl.h | 17 +- arch/arm/lib/reset.c | 6 + board/samsung/common/board.c | 55 +++- board/samsung/common/misc.c | 57 +++- board/samsung/odroid/Makefile| 8 + board/samsung/odroid/odroid.c| 470 +++ board/samsung/odroid/setup.h | 255 + boards.cfg | 1 + doc/README.odroid| 143 ++ include/common.h | 1 + include/configs/odroid.h | 216 ++ include/samsung/misc.h | 10 + 18 files changed, 1309 insertions(+), 40 deletions(-) create mode 100644 arch/arm/dts/exynos4412-odroid.dts create mode 100644 board/samsung/odroid/Makefile create mode 100644 board/samsung/odroid/odroid.c create mode 100644 board/samsung/odroid/setup.h create mode 100644 doc/README.odroid create mode 100644 include/configs/odroid.h -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 02/12] exynos: pinmux: fix the gpio names for exynos4x12 mmc
This change fixes the bad gpio configuration for the exynos dwmmc. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Beomho Seo beomho@samsung.com Cc: Minkyu Kang mk7.k...@samsung.com Cc: Jaehoon Chung jh80.ch...@samsung.com --- arch/arm/cpu/armv7/exynos/pinmux.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 86a0c75..b929486 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -704,8 +704,8 @@ static int exynos4x12_mmc_config(int peripheral, int flags) ext_func = S5P_GPIO_FUNC(0x3); break; case PERIPH_ID_SDMMC4: - start = EXYNOS4_GPIO_K00; - start_ext = EXYNOS4_GPIO_K13; + start = EXYNOS4X12_GPIO_K00; + start_ext = EXYNOS4X12_GPIO_K13; func = S5P_GPIO_FUNC(0x3); ext_func = S5P_GPIO_FUNC(0x4); break; -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 06/12] samsung:board: misc_init_r: call set_dfu_alt_info()
This change enable automatic setting of dfu alt info
on every boot. This is useful in case of booting one
u-boot binary from multiple media.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
---
board/samsung/common/board.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 4d3f216..a46e87b 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -324,6 +324,9 @@ int arch_early_init_r(void)
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
+#ifdef CONFIG_SET_DFU_ALT_INFO
+ set_dfu_alt_info();
+#endif
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
set_board_info();
#endif
--
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[U-Boot] [PATCH v6 11/12] odroid: add odroid U3/X2 device tree description
This is a standard description for Odroid boards.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Tom Rini tr...@ti.com
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/exynos4412-odroid.dts | 70 ++
2 files changed, 72 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/exynos4412-odroid.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6e2e313..8bcc69c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1,7 +1,8 @@
dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
exynos4210-universal_c210.dtb \
exynos4210-trats.dtb \
- exynos4412-trats2.dtb
+ exynos4412-trats2.dtb \
+ exynos4412-odroid.dtb
dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
exynos5250-snow.dtb \
diff --git a/arch/arm/dts/exynos4412-odroid.dts
b/arch/arm/dts/exynos4412-odroid.dts
new file mode 100644
index 000..24d0bf1
--- /dev/null
+++ b/arch/arm/dts/exynos4412-odroid.dts
@@ -0,0 +1,70 @@
+/*
+ * Odroid-U3/X2 board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ exynos4.dtsi
+
+/ {
+ model = Odroid based on Exynos4412;
+ compatible = samsung,odroid, samsung,exynos4412;
+
+ aliases {
+ i2c0 = /i2c@1386;
+ serial0 = /serial@1380;
+ console = /serial@1381;
+ mmc2 = sdhci@1253;
+ mmc4 = dwmmc@1255;
+ };
+
+ i2c@1386 {
+ samsung,i2c-sda-delay = 100;
+ samsung,i2c-slave-addr = 0x10;
+ samsung,i2c-max-bus-freq = 10;
+ status = okay;
+
+ max77686_pmic@09 {
+ compatible = maxim,max77686_pmic;
+ interrupts = 7 0;
+ reg = 0x09 0 0;
+ #clock-cells = 1;
+ };
+ };
+
+ serial@1381 {
+ status = okay;
+ };
+
+ sdhci@1251 {
+ status = disabled;
+ };
+
+ sdhci@1252 {
+ status = disabled;
+ };
+
+ sdhci@1253 {
+ samsung,bus-width = 4;
+ samsung,timing = 1 2 3;
+ cd-gpios = gpio 0xC2 0;
+ };
+
+ sdhci@1254 {
+ status = disabled;
+ };
+
+ dwmmc@1255 {
+ samsung,bus-width = 8;
+ samsung,timing = 2 1 0;
+ samsung,removable = 0;
+ fifoth_val = 0x203f0040;
+ bus_hz = 4;
+ div = 0x3;
+ index = 4;
+ };
+};
--
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[U-Boot] [PATCH v6 01/12] samsung: misc: fix soc revision setting in the set_board_info()
The byte order of soc revision was inverted, now it is fixed.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Piotr Wilczek p.wilc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
board/samsung/common/misc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
index 03106fd..a453a82 100644
--- a/board/samsung/common/misc.c
+++ b/board/samsung/common/misc.c
@@ -26,8 +26,8 @@ void set_board_info(void)
{
char info[64];
- snprintf(info, ARRAY_SIZE(info), %d.%d, s5p_cpu_rev 0x0f,
-(s5p_cpu_rev 0xf0) 0x04);
+ snprintf(info, ARRAY_SIZE(info), %u.%u, (s5p_cpu_rev 0xf0) 4,
+s5p_cpu_rev 0xf);
setenv(soc_rev, info);
snprintf(info, ARRAY_SIZE(info), %x, s5p_cpu_id);
--
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[U-Boot] [PATCH v6 10/12] odroid: add board file for Odroid X2/U3 based on Samsung Exynos4412
This board file supports standard features of Odroid X2 and U3 boards:
- Exynos4412 core clock set to 1000MHz and MPLL peripherial clock set to 800MHz,
- MAX77686 power regulator,
- USB PHY,
- enable XCL205 - power for board peripherials
- check board type: U3 or X2.
- enable Odroid U3 FAN cooler
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Tom Rini tr...@ti.com
---
Changes v2:
- enable fan on odroid U3
Changes v3:
- odroid.c: clean up board name related code
- odroid.c: remove static from set_board_type()
- odroid.c: add implementation of functions: get_dfu_alt_*
- odroid.c: include misc.h
Changes v4:
- odroid.c: dfu_get_alt_boot: add call get_boot_mode()
Changes v5:
- odroid.c: set_board_type: change mdelay to sdelay, define XCL205 GPIO config
- odroid.c: board_gpio_init(): fix OTG for Odroid U3+
- odroid.c: reserve the last 1 MB of dram for secure firmware
- odroid.c: board_clock_init(): code cleanup
- odroid.c: get_dfu_alt_boot(): remove setenv()
- odroid.c: remove get_board_name() function definition
- odroid.c: add enum ODROID_TYPES
---
board/samsung/odroid/Makefile | 8 +
board/samsung/odroid/odroid.c | 470 ++
board/samsung/odroid/setup.h | 255 +++
3 files changed, 733 insertions(+)
create mode 100644 board/samsung/odroid/Makefile
create mode 100644 board/samsung/odroid/odroid.c
create mode 100644 board/samsung/odroid/setup.h
diff --git a/board/samsung/odroid/Makefile b/board/samsung/odroid/Makefile
new file mode 100644
index 000..b98aaeb
--- /dev/null
+++ b/board/samsung/odroid/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved.
+# Przemyslaw Marczak p.marc...@samsung.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := odroid.o
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
new file mode 100644
index 000..2c5c107
--- /dev/null
+++ b/board/samsung/odroid/odroid.c
@@ -0,0 +1,470 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Przemyslaw Marczak p.marc...@samsung.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/pinmux.h
+#include asm/arch/power.h
+#include asm/arch/clock.h
+#include asm/arch/gpio.h
+#include asm/gpio.h
+#include asm/arch/cpu.h
+#include power/pmic.h
+#include power/max77686_pmic.h
+#include errno.h
+#include usb.h
+#include usb/s3c_udc.h
+#include samsung/misc.h
+#include setup.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_BOARD_TYPES
+/* Odroid board types */
+enum {
+ ODROID_TYPE_U3,
+ ODROID_TYPE_X2,
+ ODROID_TYPES,
+};
+
+void set_board_type(void)
+{
+ /* Set GPA1 pin 1 to HI - enable XCL205 output */
+ writel(XCL205_EN_GPIO_CON_CFG, XCL205_EN_GPIO_CON);
+ writel(XCL205_EN_GPIO_DAT_CFG, XCL205_EN_GPIO_CON + 0x4);
+ writel(XCL205_EN_GPIO_PUD_CFG, XCL205_EN_GPIO_CON + 0x8);
+ writel(XCL205_EN_GPIO_DRV_CFG, XCL205_EN_GPIO_CON + 0xc);
+
+ /* Set GPC1 pin 2 to IN - check XCL205 output state */
+ writel(XCL205_STATE_GPIO_CON_CFG, XCL205_STATE_GPIO_CON);
+ writel(XCL205_STATE_GPIO_PUD_CFG, XCL205_STATE_GPIO_CON + 0x8);
+
+ /* XCL205 - needs some latch time */
+ sdelay(20);
+
+ /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
+ if (readl(XCL205_STATE_GPIO_DAT) (1 XCL205_STATE_GPIO_PIN))
+ gd-board_type = ODROID_TYPE_X2;
+ else
+ gd-board_type = ODROID_TYPE_U3;
+}
+
+const char *get_board_type(void)
+{
+ const char *board_type[] = {u3, x2};
+
+ return board_type[gd-board_type];
+}
+#endif
+
+#ifdef CONFIG_SET_DFU_ALT_INFO
+char *get_dfu_alt_system(void)
+{
+ return getenv(dfu_alt_system);
+}
+
+char *get_dfu_alt_boot(void)
+{
+ char *alt_boot;
+
+ switch (get_boot_mode()) {
+ case BOOT_MODE_MMC:
+ alt_boot = CONFIG_DFU_ALT_BOOT_SD;
+ break;
+ case BOOT_MODE_EMMC:
+ case BOOT_MODE_EMMC_SD:
+ alt_boot = CONFIG_DFU_ALT_BOOT_EMMC;
+ break;
+ default:
+ alt_boot = NULL;
+ break;
+ }
+ return alt_boot;
+}
+#endif
+
+static void board_clock_init(void)
+{
+ unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
+ struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
+ samsung_get_base_clock();
+
+ /*
+* CMU_CPU clocks src to MPLL
+* Bit values: 0 ; 1
+* MUX_APLL_SEL:FIN_PLL ; FOUT_APLL
+* MUX_CORE_SEL:MOUT_APLL ; SCLK_MPLL
+* MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
+* MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL
+ */
+ clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) |
+ MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1);
+ set = MUX_APLL_SEL(0) |
[U-Boot] [PATCH v6 12/12] odroid: add odroid_config
This config is valid for two devices: - Odroid X2, - Odroid U3. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Minkyu Kang mk7.k...@samsung.com Cc: Tom Rini tr...@ti.com --- Changes v2: - odroid config: add CONFIG_DFU_ALT_BOOTLOADER - odroid config: change name of CONFIG_DFU_BOOT_ALT_* to CONFIG_DFU_ALT_BOOT_* Changes v3: - odroid.h: update CONFIG_DFU_ALT_BOOT_** with required bootloader binaries - odroid.h: add multi image support (CONFIG_FIT) - odroid.h: add autoboot script for multi boot options - odroid.h: change env name: dfu_alt_info - dfu_alt_system - odroid.h: update config name: CONFIG_SET_DFU_ALT_INFO - odroid.h: reduce boot delay to 0 seconds - update: doc/README.odroid Changes v5: - odroid.h: default environment cleanup - odroid.h: remove unused definitions - odroid.h: dfu_alt_system update - odroid.h: define CONFIG_SET_DFU_ALT_BUF_LEN to 1k - odroid.h: add init ramdisk support - update: doc/README.odroid Changes v6: - odroid.h: fix ramdisk load issue --- boards.cfg | 1 + doc/README.odroid| 143 +++ include/configs/odroid.h | 216 +++ 3 files changed, 360 insertions(+) create mode 100644 doc/README.odroid create mode 100644 include/configs/odroid.h diff --git a/boards.cfg b/boards.cfg index 1ba2081..da16ec2 100644 --- a/boards.cfg +++ b/boards.cfg @@ -298,6 +298,7 @@ Active arm armv7 exynos samsung smdk5420 Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap k.chan...@samsung.com Active arm armv7 exynos samsung trats trats - Lukasz Majewski l.majew...@samsung.com Active arm armv7 exynos samsung trats2 trats2- Piotr Wilczek p.wilc...@samsung.com +Active arm armv7 exynos samsung odroid odroid- Przemyslaw Marczak p.marc...@samsung.com Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Przemyslaw Marczak p.marc...@samsung.com Active arm armv7 highbank- highbank highbank - Rob Herring r...@kernel.org Active arm armv7 keystoneti k2hk_evm k2hk_evm - Vitaly Andrianov vita...@ti.com diff --git a/doc/README.odroid b/doc/README.odroid new file mode 100644 index 000..528bb95 --- /dev/null +++ b/doc/README.odroid @@ -0,0 +1,143 @@ + U-boot for Odroid X2/U3 + + +1. Summary +== +This is a quick instruction for setup Odroid boards based on Exynos4412. +Board config: odroid_config + +2. Supported devices + +This U-BOOT config can be used on two boards: +- Odroid U3 +- Odroid X2 +with CPU Exynos 4412 rev 2.0 and 2GB of RAM + +3. Boot sequence + +iROM-BL1-(BL2 + TrustZone)-U-BOOT + +This version of U-BOOT doesn't implement SPL but it is required(BL2) +and can be found in boot.tar.gz from here: +http://dev.odroid.com/projects/4412boot/wiki/FrontPage?action=downloadvalue=boot.tar.gz +or here: +http://odroid.in/guides/ubuntu-lfs/boot.tar.gz + +4. Boot media layout + +The table below shows SD/eMMC cards layout for U-boot. +The block offset is starting from 0 and the block size is 512B. + - +| Binary | Block offset| part type | +| name| SD | eMMC |(eMMC only)| + - +| Bl1 | 1| 0| 1 (boot) | +| Bl2 | 31 | 30 | 1 (boot) | +| U-boot| 63 | 62 | 1 (boot) | +| Tzsw | 2111 | 2110 | 1 (boot) | +| Uboot Env | 2500 | 2500 | 0 (user) | + - + +5. Prepare the SD boot card - with SD card reader
[U-Boot] [PATCH v6 05/12] samsung: misc: add function for setting $dfu_alt_info
This change introduces new common function:
- set_dfu_alt_info() - put dfu system and bootloader setting
into $dfu_alt_info.
functions declaration:
- char *get_dfu_alt_system(void)
- char *get_dfu_alt_boot(void)
- void set_dfu_alt_info(void)
and new config:
- CONFIG_SET_DFU_ALT_INFO
This function can be used for auto setting dfu configuration on boot.
Such feature is useful for multi board support by one u-boot binary.
Each board should define two functions:
- get_dfu_alt_system()
- get_dfu_alt_boot()
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Piotr Wilczek p.wilc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
Changes v2:
- change config names:
CONFIG_SET_DFU_BOOT_ALT to CONFIG_DFU_ALT_BOOTLOADER and
CONFIG_DFU_BOOT_ALT_* to CONFIG_DFU_ALT_BOOT_*
- change function name: set_dfu_boot_alt() to set_dfu_alt_boot()
- remove superfluous ifdefs
Changes v3:
- set $dfu_alt_info at every boot
- new config: CONFIG_SET_DFU_ALT_INFO
- update commit msg
Changes v4:
- set_dfu_alt_info(): add checking the pointer returned by malloc
Changes v5:
- set_dfu_alt_info(): remove malloc and declare cache aligned buffer
- set_dfu_alt_info(): introduce CONFIG_SET_DFU_ALT_BUF_LEN
---
board/samsung/common/misc.c | 41 +
include/samsung/misc.h | 6 ++
2 files changed, 47 insertions(+)
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
index a453a82..9e52452 100644
--- a/board/samsung/common/misc.c
+++ b/board/samsung/common/misc.c
@@ -11,6 +11,7 @@
#include samsung/misc.h
#include errno.h
#include version.h
+#include malloc.h
#include linux/sizes.h
#include asm/arch/cpu.h
#include asm/arch/gpio.h
@@ -21,6 +22,46 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SET_DFU_ALT_INFO
+void set_dfu_alt_info(void)
+{
+ size_t buf_size = CONFIG_SET_DFU_ALT_BUF_LEN;
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, buf_size);
+ char *alt_info = Settings not found!;
+ char *status = error!\n;
+ char *alt_setting;
+ char *alt_sep;
+ int offset = 0;
+
+ puts(DFU alt info setting: );
+
+ alt_setting = get_dfu_alt_boot();
+ if (alt_setting) {
+ setenv(dfu_alt_boot, alt_setting);
+ offset = snprintf(buf, buf_size, %s, alt_setting);
+ }
+
+ alt_setting = get_dfu_alt_system();
+ if (alt_setting) {
+ if (offset)
+ alt_sep = ;;
+ else
+ alt_sep = ;
+
+ offset += snprintf(buf + offset, buf_size - offset,
+ %s%s, alt_sep, alt_setting);
+ }
+
+ if (offset) {
+ alt_info = buf;
+ status = done\n;
+ }
+
+ setenv(dfu_alt_info, alt_info);
+ puts(status);
+}
+#endif
+
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
void set_board_info(void)
{
diff --git a/include/samsung/misc.h b/include/samsung/misc.h
index 10653a1..e82bf32 100644
--- a/include/samsung/misc.h
+++ b/include/samsung/misc.h
@@ -28,4 +28,10 @@ void check_boot_mode(void);
void draw_logo(void);
#endif
+#ifdef CONFIG_SET_DFU_ALT_INFO
+char *get_dfu_alt_system(void);
+char *get_dfu_alt_boot(void);
+void set_dfu_alt_info(void);
+#endif
+
#endif /* __SAMSUNG_MISC_COMMON_H__ */
--
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[U-Boot] [PATCH v6 04/12] board:samsung: check the boot device and init the right mmc driver.
It is possible to boot device using a micro SD or eMMC slots.
In this situation, boot device should be registered as a block
device 0 in the MMC framework, because CONFIG_SYS_MMC_ENV_DEV
is usually set to 0 in the most config cases.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
---
Changes V3:
- separate two changes into two commits
Changes V4:
- board.c: add functions: init_mmc() and init_dwmmc()
- board_mmc_init(): call get_boot_mode()
---
board/samsung/common/board.c | 37 +++--
1 file changed, 27 insertions(+), 10 deletions(-)
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 9dc7c83..4d3f216 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -240,22 +240,39 @@ int board_eth_init(bd_t *bis)
}
#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
+static int init_mmc(void)
+{
+#ifdef CONFIG_SDHCI
+ return exynos_mmc_init(gd-fdt_blob);
+#else
+ return 0;
+#endif
+}
+
+static int init_dwmmc(void)
{
- int ret;
#ifdef CONFIG_DWMMC
- /* dwmmc initializattion for available channels */
- ret = exynos_dwmmc_init(gd-fdt_blob);
- if (ret)
- debug(dwmmc init failed\n);
+ return exynos_dwmmc_init(gd-fdt_blob);
+#else
+ return 0;
#endif
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ if (get_boot_mode() == BOOT_MODE_MMC) {
+ ret = init_mmc();
+ ret |= init_dwmmc();
+ } else {
+ ret = init_dwmmc();
+ ret |= init_mmc();
+ }
-#ifdef CONFIG_SDHCI
- /* mmc initializattion for available channels */
- ret = exynos_mmc_init(gd-fdt_blob);
if (ret)
debug(mmc init failed\n);
-#endif
+
return ret;
}
#endif
--
1.9.1
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[U-Boot] [PATCH v6 09/12] samsung: misc: use board specific functions to set env board info
This change adds setup of environmental board info using get_board_name() and get_board_type() functions for config CONFIG_BOARD_TYPES. This is useful in case of running many boards with just one config. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Piotr Wilczek p.wilc...@samsung.com Cc: Minkyu Kang mk7.k...@samsung.com --- Changes v2: - set_board_info: move the bdtype pointer to avoid unused pointer compilation warning Changes v3: - samsung: misc: change get_board_type_fdt() to get_board_type() - samsung: misc: set env $boardname using get_board_* functions for CONFIG_BOARD_TYPES - update commit msg Changes v5: - misc.c: set_bard_info(): remove a call to get_board_name() --- board/samsung/common/misc.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index 9e52452..8766f0c 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -79,8 +79,16 @@ void set_board_info(void) setenv(board_rev, info); #endif #ifdef CONFIG_OF_LIBFDT - snprintf(info, ARRAY_SIZE(info), %s%x-%s.dtb, -CONFIG_SYS_SOC, s5p_cpu_id, CONFIG_SYS_BOARD); + const char *bdtype = ; + const char *bdname = CONFIG_SYS_BOARD; + +#ifdef CONFIG_BOARD_TYPES + bdtype = get_board_type(); + sprintf(info, %s%s, bdname, bdtype); + setenv(boardname, info); +#endif + snprintf(info, ARRAY_SIZE(info), %s%x-%s%s.dtb, +CONFIG_SYS_SOC, s5p_cpu_id, bdname, bdtype); setenv(fdtfile, info); #endif } -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 08/12] samsung: board: enable support of multiple board types
This change adds declaration of functions:
- set_board_type() - called at board_early_init_f()
- get_board_type() - called at checkboard()
For supporting multiple board types in a one config - it is welcome
to display the current board model. This is what get_board_type()
should return.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Piotr Wilczek p.wilc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
Changes v3:
- change the commit order
- include/samsung/misc.h: add new functions declaration
- update a commit message
Changes v4:
- checkboard(): remove redundant variable
Changes v5:
- board.c: move call to set_board_type() into board_early_init_f()
- misc.h: remove get_board_name() function declaration
---
board/samsung/common/board.c | 15 ++-
include/samsung/misc.h | 4
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index a46e87b..3de828a 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -137,7 +137,9 @@ static int board_uart_init(void)
int board_early_init_f(void)
{
int err;
-
+#ifdef CONFIG_BOARD_TYPES
+ set_board_type();
+#endif
err = board_uart_init();
if (err) {
debug(UART init failed\n);
@@ -147,7 +149,6 @@ int board_early_init_f(void)
#ifdef CONFIG_SYS_I2C_INIT_BOARD
board_i2c_init(gd-fdt_blob);
#endif
-
return exynos_early_init_f();
}
#endif
@@ -280,11 +281,15 @@ int board_mmc_init(bd_t *bis)
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
- const char *board_name;
+ const char *board_info;
- board_name = fdt_getprop(gd-fdt_blob, 0, model, NULL);
- printf(Board: %s\n, board_name ? board_name : unknown);
+ board_info = fdt_getprop(gd-fdt_blob, 0, model, NULL);
+ printf(Board: %s\n, board_info ? board_info : unknown);
+#ifdef CONFIG_BOARD_TYPES
+ board_info = get_board_type();
+ printf(Model: %s\n, board_info ? board_info : unknown);
+#endif
return 0;
}
#endif
diff --git a/include/samsung/misc.h b/include/samsung/misc.h
index e82bf32..607e8d4 100644
--- a/include/samsung/misc.h
+++ b/include/samsung/misc.h
@@ -33,5 +33,9 @@ char *get_dfu_alt_system(void);
char *get_dfu_alt_boot(void);
void set_dfu_alt_info(void);
#endif
+#ifdef CONFIG_BOARD_TYPES
+void set_board_type(void);
+const char *get_board_type(void);
+#endif
#endif /* __SAMSUNG_MISC_COMMON_H__ */
--
1.9.1
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[U-Boot] [PATCH v6 07/12] arm:reset: call the reset_misc() before the cpu reset
On an Odroid U3 board, the SOC is unable to reset the eMMC card
in the DWMMC mode by the cpu software reset. Manual reset of the card
by switching proper gpio pin - fixes this issue.
Such solution needs to add a call to pre reset function.
This is done by the reset_misc() function, which is called before reset_cpu().
The function reset_misc() is a weak function.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
Cc: Albert ARIBAUD albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Changes v4:
- arch/arm/reset: fix weak function attribute to proper style
---
arch/arm/lib/reset.c | 6 ++
include/common.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c
index 7a03580..9a95f08 100644
--- a/arch/arm/lib/reset.c
+++ b/arch/arm/lib/reset.c
@@ -23,6 +23,10 @@
#include common.h
+__weak void reset_misc(void)
+{
+}
+
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
puts (resetting ...\n);
@@ -30,6 +34,8 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
udelay (5); /* wait 50 ms */
disable_interrupts();
+
+ reset_misc();
reset_cpu(0);
/*NOTREACHED*/
diff --git a/include/common.h b/include/common.h
index 82c0a5a..48e4cbd 100644
--- a/include/common.h
+++ b/include/common.h
@@ -619,6 +619,7 @@ int checkicache (void);
intcheckdcache (void);
void upmconfig (unsigned int, unsigned int *, unsigned int);
ulong get_tbclk (void);
+void reset_misc(void);
void reset_cpu (ulong addr);
#if defined (CONFIG_OF_LIBFDT) defined (CONFIG_OF_BOARD_SETUP)
void ft_cpu_setup(void *blob, bd_t *bd);
--
1.9.1
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[U-Boot] [PATCH v3 2/5] TI:armv7: Change CONFIG_SPL_STACK to not be CONFIG_SYS_INIT_SP_ADDR
There are times where we may need more than a few kilobytes of stack space. We also will not be using CONFIG_SPL_STACK location prior to DDR being initialized (CONFIG_SYS_INIT_SP_ADDR is still used there) so pick a good location within DDR for this to be. Tested on OMAP4/AM335x/OMAP5/DRA7xx. Signed-off-by: Tom Rini tr...@ti.com --- Changes in v3: - Change CONFIG_SPL_STACK to CONFIG_SYS_SDRAM_BASE + 32MB, reword comment --- include/configs/ti_armv7_common.h | 19 +++ 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 6e0bf09..9f4ba5e 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -203,15 +203,18 @@ #define CONFIG_SPL_OS_BOOT /* - * Place the image at the start of the ROM defined image space. - * We limit our size to the ROM-defined downloaded image area, and use the - * rest of the space for stack. We load U-Boot itself into memory at - * 0x8080 for legacy reasons (to not conflict with older SPLs). We - * have our BSS be placed 1MiB after this, to allow for the default - * Linux kernel address of 0x80008000 to work, in the Falcon Mode case. - * We have the SPL malloc pool at the end of the BSS area. + * Place the image at the start of the ROM defined image space (per + * CONFIG_SPL_TEXT_BASE and we limit our size to the ROM-defined + * downloaded image area. We initalize DRAM as soon as we can so that + * we can place stack, malloc and BSS there. We load U-Boot itself into + * memory at 0x8080 for legacy reasons (to not conflict with older + * SPLs). We have our BSS be placed 2MiB after this, to allow for the + * default Linux kernel address of 0x80008000 to work with most sized + * kernels, in the Falcon Mode case. We have the SPL malloc pool at the + * end of the BSS area. We place our stack at 32MiB after the start of + * DRAM to allow room for all of the above. */ -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SPL_STACK (CONFIG_SYS_SDRAM_BASE + (32 20)) #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x8080 #endif -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/5] tseries: Set CONFIG_ENV_IS_NOWHERE for SPL+NAND
In the case of SPL on these boards we only need environment for SPL_USBETH, so it's safe to normally use ENV_IS_NOWHERE and SPL+NAND does not support environment today. Cc: Hannes Petermaier oe5...@oevsv.at Signed-off-by: Tom Rini tr...@ti.com --- include/configs/tseries.h |6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/configs/tseries.h b/include/configs/tseries.h index 1fd6e32..1dd13fd 100644 --- a/include/configs/tseries.h +++ b/include/configs/tseries.h @@ -243,8 +243,12 @@ #define CONFIG_SYS_REDUNDAND_ENVIRONMENT #elif defined(CONFIG_NAND) -#undef CONFIG_ENV_IS_NOWHERE +/* No NAND env support in SPL */ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_ENV_IS_NOWHERE +#else #define CONFIG_ENV_IS_IN_NAND +#endif #define CONFIG_ENV_OFFSET 0x12 /* TODO: Adresse definieren */ #define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE #else -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/5] am335x_evm: Move SPL network defines
On am335x_evm we only support USBETH for a networking SPL option so move the rest of the defines under that area as that's the only time we need (and want) environment support here. Signed-off-by: Tom Rini tr...@ti.com --- include/configs/am335x_evm.h | 13 - 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index a48b386..b681e81 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -223,11 +223,6 @@ /* USB gadget RNDIS */ #define CONFIG_SPL_MUSB_NEW_SUPPORT -/* General network SPL, both CPSW and USB gadget RNDIS */ -#define CONFIG_SPL_NET_SUPPORT -#define CONFIG_SPL_ENV_SUPPORT -#define CONFIG_SPL_NET_VCI_STRING AM335x U-Boot SPL - #define CONFIG_SPL_LDSCRIPT$(CPUDIR)/am33xx/u-boot-spl.lds #ifdef CONFIG_NAND @@ -309,10 +304,10 @@ /* disable EFI partitions and partition UUID support */ #undef CONFIG_PARTITION_UUIDS #undef CONFIG_EFI_PARTITION -/* - * Disable CPSW SPL support so we fit within the 101KiB limit. - */ -#undef CONFIG_SPL_ETH_SUPPORT +/* General network SPL */ +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING AM335x U-Boot SPL #endif /* USB Device Firmware Update support */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/5] common/Makefile: Consolidate SPL ENV options, correct inclusion
CONFIG_SPL_NET_SUPPORT is not the only time we want SPL to ahve environment, CONFIG_SPL_ENV_SUPPORT is when we want it. Signed-off-by: Tom Rini tr...@ti.com --- common/Makefile | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/common/Makefile b/common/Makefile index de5cce8..aca0f7f 100644 --- a/common/Makefile +++ b/common/Makefile @@ -219,10 +219,6 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o -# environment -obj-$(CONFIG_SPL_ENV_SUPPORT) += env_attr.o -obj-$(CONFIG_SPL_ENV_SUPPORT) += env_flags.o -obj-$(CONFIG_SPL_ENV_SUPPORT) += env_callback.o ifdef CONFIG_SPL_USB_HOST_SUPPORT obj-$(CONFIG_SPL_USB_SUPPORT) += usb.o usb_hub.o obj-$(CONFIG_USB_STORAGE) += usb_storage.o @@ -230,14 +226,16 @@ endif ifdef CONFIG_SPL_SATA_SUPPORT obj-$(CONFIG_CMD_SCSI) += cmd_scsi.o endif -ifneq ($(CONFIG_SPL_NET_SUPPORT),y) +# environment +ifdef CONFIG_SPL_ENV_SUPPORT +obj-$(CONFIG_SPL_ENV_SUPPORT) += env_attr.o +obj-$(CONFIG_SPL_ENV_SUPPORT) += env_flags.o +obj-$(CONFIG_SPL_ENV_SUPPORT) += env_callback.o obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o obj-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o -else -obj-y += env_nowhere.o endif endif # core command -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/5] am335x_evm: Enable CONFIG_SPL_ENV_SUPPORT on EMMC_BOOT
When we're using EMMC_BOOT that means we have environment on eMMC so we can make use of CONFIG_SPL_ENV_SUPPORT within Falcon Mode. Signed-off-by: Tom Rini tr...@ti.com --- include/configs/am335x_evm.h |1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index b681e81..ea93eb1 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -389,6 +389,7 @@ #elif defined(CONFIG_EMMC_BOOT) #undef CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SPL_ENV_SUPPORT #define CONFIG_SYS_MMC_ENV_DEV 1 #define CONFIG_SYS_MMC_ENV_PART2 #define CONFIG_ENV_OFFSET 0x0 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Random number generator - why I need it
Hi, I'm using customized U-Boot 2011.03 (for Amlogic platform). What I need is solution for getting random number (on first boot) which will be written to ubootenv. Let's say I have 100 strings stored in string array of board file. On first boot I have to pick one random string from list and write it to ubootenv (range 0..99). Writing to ubootenv is not problem, problem is randomization. My current tries ended up in getting same number each time (2 different algorithms). Does anyone have solution for this? Keep in mind that my PCB does not have RTC battery and does not store time, so on each power on clock is back to default (1970). Thanx and best regards, Stanislav Vlasic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 10/14] sunxi: dram: Configurable DQS gating window mode and delay
The hardware DQS gate training is a bit unreliable and does not
always find the best delay settings.
So we introduce a 32-bit 'dqs_gating_delay' variable, where each
byte encodes the DQS gating delay for each byte lane. The delay
granularity is 1/4 cycle.
Also we allow to enable the active DQS gating window mode, which
works better than the passive mode in practice. The DDR3 spec
says that there is a 0.9 cycles preamble and 0.3 cycle postamble.
The DQS window has to be opened during preamble and closed during
postamble. In the passive window mode, the gating window is opened
and closed by just using the gating delay settings. And because
of the 1/4 cycle delay granularity, accurately hitting the 0.3
cycle long postamble is a bit tough. In the active window mode,
the gating window is auto-closing with the help of monitoring
the DQS line, which relaxes the gating delay accuracy requirements.
But the hardware DQS gate training is still performed in the passive
window mode. It is a more strict test, which is reducing the results
variance compared to the training with active window mode.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c| 55 +-
arch/arm/include/asm/arch-sunxi/dram.h | 2 ++
2 files changed, 56 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 49d1770..2e994db 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -99,6 +99,14 @@ static void mctl_itm_enable(void)
clrbits_le32(dram-ccr, DRAM_CCR_ITM_OFF);
}
+static void mctl_itm_reset(void)
+{
+ mctl_itm_disable();
+ udelay(1); /* ITM reset needs a bit of delay */
+ mctl_itm_enable();
+ udelay(1);
+}
+
static void mctl_enable_dll0(u32 phase)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
@@ -291,6 +299,37 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
udelay(22);
}
+/*
+ * The data from rslrX and rdgrX registers (X=rank) is stored
+ * in a single 32-bit value using the following format:
+ * bits [31:26] - DQS gating system latency for byte lane 3
+ * bits [25:24] - DQS gating phase select for byte lane 3
+ * bits [23:18] - DQS gating system latency for byte lane 2
+ * bits [17:16] - DQS gating phase select for byte lane 2
+ * bits [15:10] - DQS gating system latency for byte lane 1
+ * bits [ 9:8 ] - DQS gating phase select for byte lane 1
+ * bits [ 7:2 ] - DQS gating system latency for byte lane 0
+ * bits [ 1:0 ] - DQS gating phase select for byte lane 0
+ */
+static void mctl_set_dqs_gating_delay(int rank, u32 dqs_gating_delay)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+ u32 lane, number_of_lanes = mctl_get_number_of_lanes();
+ /* rank0 gating system latency (3 bits per lane: cycles) */
+ u32 slr = readl(rank == 0 ? dram-rslr0 : dram-rslr1);
+ /* rank0 gating phase select (2 bits per lane: 90, 180, 270, 360) */
+ u32 dgr = readl(rank == 0 ? dram-rdgr0 : dram-rdgr1);
+ for (lane = 0; lane number_of_lanes; lane++) {
+ u32 tmp = dqs_gating_delay (lane * 8);
+ slr = ~(7 (lane * 3));
+ slr |= ((tmp 2) 7) (lane * 3);
+ dgr = ~(3 (lane * 2));
+ dgr |= (tmp 3) (lane * 2);
+ }
+ writel(slr, rank == 0 ? dram-rslr0 : dram-rslr1);
+ writel(dgr, rank == 0 ? dram-rdgr0 : dram-rdgr1);
+}
+
static int dramc_scan_readpipe(void)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
@@ -534,7 +573,7 @@ unsigned long dramc_init(struct dram_para *para)
writel(para-emr2, dram-emr2);
writel(para-emr3, dram-emr3);
- /* set DQS window mode */
+ /* disable drift compensation and set passive DQS window mode */
clrsetbits_le32(dram-ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
#ifdef CONFIG_SUN7I
@@ -547,11 +586,25 @@ unsigned long dramc_init(struct dram_para *para)
/* scan read pipe value */
mctl_itm_enable();
+
+ /* Hardware DQS gate training */
ret_val = dramc_scan_readpipe();
if (ret_val 0)
return 0;
+ /* allow to override the DQS training results with a custom delay */
+ if (para-dqs_gating_delay)
+ mctl_set_dqs_gating_delay(0, para-dqs_gating_delay);
+
+ /* set the DQS gating window type */
+ if (para-active_windowing)
+ clrbits_le32(dram-ccr, DRAM_CCR_DQS_GATE);
+ else
+ setbits_le32(dram-ccr, DRAM_CCR_DQS_GATE);
+
+ mctl_itm_reset();
+
/* configure all host port */
mctl_configure_hostport();
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h
b/arch/arm/include/asm/arch-sunxi/dram.h
index 11e3507..3b21225 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++
[U-Boot] [PATCH 02/14] sunxi: dram: Remove broken super-standby remnants
If the dram-ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this
means that DRAM is currently in self-refresh mode and retaining the old
data. Since we have no idea what to do in this situation yet, just set this
register to 0 and initialize DRAM in the same way as on any normal reboot
(discarding whatever was stored there).
This part of code was apparently used by the Allwinner boot0 bootloader to
handle resume from the so-called super-standby mode. But this particular
code got somehow mangled on the way from the boot0 bootloader to the
u-boot-sunxi bootloader and has no chance of doing anything even remotely
sane. For example:
1. in the original boot0 code we had mctl_write_w(SDR_DPCR, 0x1651)
(write to the register) and in the u-boot it now looks like
setbits_le32(dram-ppwrsctl, 0x1651) (set bits in the register)
2. in the original boot0 code it was issuing three commands 0x12, 0x17, 0x13
(Self-Refresh entry, Self-Refresh exit, Refresh), but in the u-boot they
have become 0x12, 0x12, 0x13 (Self-Refresh entry, Self-Refresh entry,
Refresh)
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c | 67 ++---
1 file changed, 22 insertions(+), 45 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 76a7106..beaf95a 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -295,6 +295,24 @@ static void dramc_set_autorefresh_cycle(u32 clk, u32 type,
u32 density)
writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), dram-drr);
}
+/*
+ * If the dram-ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this
+ * means that DRAM is currently in self-refresh mode and retaining the old
+ * data. Since we have no idea what to do in this situation yet, just set this
+ * register to 0 and initialize DRAM in the same way as on any normal reboot
+ * (discarding whatever was stored there).
+ *
+ * Note: on sun7i hardware, the highest 16 bits need to be set to 0x1651 magic
+ * value for this write operation to have any effect. On sun5i hadware this
+ * magic value is not necessary. And on sun4i hardware the writes to this
+ * register seem to have no effect at all.
+ */
+static void mctl_disable_power_save(void)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+ writel(0x1651, dram-ppwrsctl);
+}
+
unsigned long dramc_init(struct dram_para *para)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
@@ -309,6 +327,9 @@ unsigned long dramc_init(struct dram_para *para)
/* setup DRAM relative clock */
mctl_setup_dram_clock(para-clock);
+ /* Disable any pad power save control */
+ mctl_disable_power_save();
+
/* reset external DRAM */
mctl_set_drive();
@@ -366,12 +387,7 @@ unsigned long dramc_init(struct dram_para *para)
setbits_le32(dram-idcr, 0x1);
#endif
-#ifdef CONFIG_SUN7I
- if ((readl(dram-ppwrsctl) 0x1) != 0x1)
- mctl_ddr3_reset();
- else
- setbits_le32(dram-mcr, DRAM_MCR_RESET);
-#endif
+ mctl_ddr3_reset();
udelay(1);
@@ -417,45 +433,6 @@ unsigned long dramc_init(struct dram_para *para)
setbits_le32(dram-ccr, DRAM_CCR_INIT);
await_completion(dram-ccr, DRAM_CCR_INIT);
-#ifdef CONFIG_SUN7I
- /* setup zq calibration manual */
- reg_val = readl(dram-ppwrsctl);
- if ((reg_val 0x1) == 1) {
- /* super_standby_flag = 1 */
-
- reg_val = readl(0x01c20c00 + 0x120); /* rtc */
- reg_val = 0x000f;
- reg_val |= 0x17b0;
- writel(reg_val, dram-zqcr0);
-
- /* exit self-refresh state */
- clrsetbits_le32(dram-dcr, 0x1f 27, 0x12 27);
- /* check whether command has been executed */
- await_completion(dram-dcr, 0x1 31);
-
- udelay(2);
-
- /* dram pad hold off */
- setbits_le32(dram-ppwrsctl, 0x1651);
-
- await_completion(dram-ppwrsctl, 0x1);
-
- /* exit self-refresh state */
- clrsetbits_le32(dram-dcr, 0x1f 27, 0x12 27);
-
- /* check whether command has been executed */
- await_completion(dram-dcr, 0x1 31);
-
- udelay(2);
-
- /* issue a refresh command */
- clrsetbits_le32(dram-dcr, 0x1f 27, 0x13 27);
- await_completion(dram-dcr, 0x1 31);
-
- udelay(2);
- }
-#endif
-
/* scan read pipe value */
mctl_itm_enable();
ret_val = dramc_scan_readpipe();
--
1.8.3.2
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[U-Boot] [PATCH 12/14] sunxi: dram: Drop DDR2 support and assume only single rank DDR3 memory
All the known Allwinner A10/A13/A20 devices are using just single rank
DDR3 memory. So don't pretend that we support DDR2 or more than one
rank, because nobody could ever test these configurations for real and
they are likely broken. Support for these features can be added back
in the case if such hardware actually exists.
As part of this code cleanup, also replace division by 1024 with
division by 1000 for the refresh timing calculations. This allows
to use the original non-skewed tRFC timing table from the DRR3 spec
and make code less confusing.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c | 41 +++--
1 file changed, 19 insertions(+), 22 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 8f35e1b..2db4f5a 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -406,20 +406,18 @@ static void dramc_clock_output_en(u32 on)
#endif
}
-static const u16 tRFC_table[2][6] = {
- /* 256Mb512Mb1Gb 2Gb 4Gb 8Gb */
- /* DDR2 75ns 105ns127.5ns 195ns327.5ns invalid */
- {77, 108, 131, 200, 336, 336 },
- /* DDR3 invalid 90ns 110ns160ns300ns350ns*/
- {93, 93, 113, 164, 308, 359 }
+/* tRFC in nanoseconds for different densities (from the DDR3 spec) */
+static const u16 tRFC_DDR3_table[6] = {
+ /* 256Mb512Mb1Gb 2Gb 4Gb 8Gb */
+ 90, 90, 110, 160, 300, 350
};
-static void dramc_set_autorefresh_cycle(u32 clk, u32 type, u32 density)
+static void dramc_set_autorefresh_cycle(u32 clk, u32 density)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
u32 tRFC, tREFI;
- tRFC = (tRFC_table[type][density] * clk + 1023) 10;
+ tRFC = (tRFC_DDR3_table[density] * clk + 999) / 1000;
tREFI = (7987 * clk) 10; /* = 7.8us */
writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), dram-drr);
@@ -534,6 +532,13 @@ unsigned long dramc_init(struct dram_para *para)
if (!para)
return 0;
+ /*
+* only single rank DDR3 is supported by this code even though the
+* hardware can theoretically support DDR2 and up to two ranks
+*/
+ if (para-type != DRAM_MEMORY_TYPE_DDR3 || para-rank_num != 1)
+ return 0;
+
/* setup DRAM relative clock */
mctl_setup_dram_clock(para-clock, para-mbus_clock);
@@ -555,9 +560,7 @@ unsigned long dramc_init(struct dram_para *para)
mctl_enable_dll0(para-tpr3);
/* configure external DRAM */
- reg_val = 0x0;
- if (para-type == DRAM_MEMORY_TYPE_DDR3)
- reg_val |= DRAM_DCR_TYPE_DDR3;
+ reg_val = DRAM_DCR_TYPE_DDR3;
reg_val |= DRAM_DCR_IO_WIDTH(para-io_width 3);
if (para-density == 256)
@@ -597,25 +600,19 @@ unsigned long dramc_init(struct dram_para *para)
mctl_enable_dllx(para-tpr3);
/* set refresh period */
- dramc_set_autorefresh_cycle(para-clock, para-type - 2, density);
+ dramc_set_autorefresh_cycle(para-clock, density);
/* set timing parameters */
writel(para-tpr0, dram-tpr0);
writel(para-tpr1, dram-tpr1);
writel(para-tpr2, dram-tpr2);
- if (para-type == DRAM_MEMORY_TYPE_DDR3) {
- reg_val = DRAM_MR_BURST_LENGTH(0x0);
+ reg_val = DRAM_MR_BURST_LENGTH(0x0);
#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
- reg_val |= DRAM_MR_POWER_DOWN;
+ reg_val |= DRAM_MR_POWER_DOWN;
#endif
- reg_val |= DRAM_MR_CAS_LAT(para-cas - 4);
- reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
- } else if (para-type == DRAM_MEMORY_TYPE_DDR2) {
- reg_val = DRAM_MR_BURST_LENGTH(0x2);
- reg_val |= DRAM_MR_CAS_LAT(para-cas);
- reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
- }
+ reg_val |= DRAM_MR_CAS_LAT(para-cas - 4);
+ reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
writel(reg_val, dram-mr);
writel(para-emr1, dram-emr);
--
1.8.3.2
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[U-Boot] [PATCH 08/14] sunxi: dram: Improve DQS gate data training error handling
The stale error status should be cleared for all sun4i/sun5i/sun7i
hardware and not just for sun7i. Also there are two types of DQS
gate training errors (found no result and found more than one
possible result). Both are handled now.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c| 2 --
arch/arm/include/asm/arch-sunxi/dram.h | 4 +++-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index f756f23..18a5c3b 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -289,9 +289,7 @@ static int dramc_scan_readpipe(void)
u32 reg_val;
/* data training trigger */
-#ifdef CONFIG_SUN7I
clrbits_le32(dram-csr, DRAM_CSR_FAILED);
-#endif
setbits_le32(dram-ccr, DRAM_CCR_DATA_TRAINING);
/* check whether data training process has completed */
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h
b/arch/arm/include/asm/arch-sunxi/dram.h
index 3c29256..11e3507 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -133,7 +133,9 @@ struct dram_para {
#define DRAM_DCR_MODE_SEQ 0x0
#define DRAM_DCR_MODE_INTERLEAVE 0x1
-#define DRAM_CSR_FAILED (0x1 20)
+#define DRAM_CSR_DTERR (0x1 20)
+#define DRAM_CSR_DTIERR (0x1 21)
+#define DRAM_CSR_FAILED (DRAM_CSR_DTERR | DRAM_CSR_DTIERR)
#define DRAM_DRR_TRFC(n) ((n) 0xff)
#define DRAM_DRR_TREFI(n) (((n) 0x) 8)
--
1.8.3.2
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[U-Boot] [PATCH 04/14] sunxi: dram: Code cleanup and comments for the CKE delay handling
Before driving the CKE pin (Clock Enable) high, the DDR3 spec requires
to wait for additional 500 us after the RESET pin is de-asserted.
The DRAM controller takes care of this delay by itself, using a
configurable counter in the SDR_IDCR register. This works in the same
way on sun4i/sun5i/sun7i hardware (even the default register value
0x00c80064 is identical). Except that the counter is ticking a bit
slower on sun7i (3 DRAM clock cycles instead of 2), resulting in
longer actual delays for the same settings.
This patch keeps the old code and only removes the CONFIG_SUN7I ifdef.
But maybe we should drop all of this and just add 'udelay(500)' after
the DDR3 reset without bothering to play with these undocumented
registers.
Another interesting observation is that the u-boot-sunxi code (derived
from the Allwinner boot0) did not configure the SDR_IDCR register
for sun4i/sun5i, but performed the DDR3 reset very early. Possibly
resulting in a sufficient time gap between the DDR3 reset and the DDR3
initialization steps.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c | 45 ++---
1 file changed, 38 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 01c492f..def4247 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -318,6 +318,41 @@ static void mctl_disable_power_save(void)
writel(0x1651, dram-ppwrsctl);
}
+/*
+ * After the DRAM is powered up or reset, the DDR3 spec requires to wait at
+ * least 500 us before driving the CKE pin (Clock Enable) high. The dram-idct
+ * (SDR_IDCR) register appears to configure this delay, which gets applied
+ * right at the time when the DRAM initialization is activated in the
+ * 'mctl_ddr3_initialize' function.
+ */
+static void mctl_set_cke_delay(void)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+ /* The CKE delay is represented in dram clock cycles, multiplied by N
+* (where N=2 for sun4i/sun5i and N=3 for sun7i). We are being lazy
+* to do proper calculations and just set it to the maximum possible
+* value 0x1. This is enough to provide the needed 500 us delay
+* at the DRAM clock freqencies up to ~524MHz on sun4i/sun5i hardware.
+* The sun7i hardware has even more headroom due to a larger multiplier.
+*/
+ setbits_le32(dram-idcr, 0x1);
+}
+
+/*
+ * This triggers the DRAM initialization. It performs sending the mode
registers
+ * to the DRAM among other things. Very likely the ZQCL command is also getting
+ * executed (to do the initial impedance calibration on the DRAM side of the
+ * wire). The memory controller and the PHY must be already configured before
+ * calling this function.
+ */
+static void mctl_ddr3_initialize(void)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+ setbits_le32(dram-ccr, DRAM_CCR_INIT);
+ await_completion(dram-ccr, DRAM_CCR_INIT);
+}
+
unsigned long dramc_init(struct dram_para *para)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
@@ -387,10 +422,7 @@ unsigned long dramc_init(struct dram_para *para)
writel(reg_val, dram-zqcr0);
#endif
-#ifdef CONFIG_SUN7I
- /* Set CKE Delay to about 1ms */
- setbits_le32(dram-idcr, 0x1);
-#endif
+ mctl_set_cke_delay();
mctl_ddr3_reset();
@@ -434,9 +466,8 @@ unsigned long dramc_init(struct dram_para *para)
if (para-tpr4 0x1)
setbits_le32(dram-ccr, DRAM_CCR_COMMAND_RATE_1T);
#endif
- /* reset external DRAM */
- setbits_le32(dram-ccr, DRAM_CCR_INIT);
- await_completion(dram-ccr, DRAM_CCR_INIT);
+ /* initialize external DRAM */
+ mctl_ddr3_initialize();
/* scan read pipe value */
mctl_itm_enable();
--
1.8.3.2
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[U-Boot] [PATCH 03/14] sunxi: dram: Respect the DDR3 reset timing requirements
The RESET pin needs to be kept low for at least 200 us according
to the DDR3 spec. So just do it the right way.
This issue did not cause any visible major problems earlier, because
the DRAM RESET pin is usually already low after the board reset. And
the time gap before reaching the sunxi u-boot DRAM initialization
code appeared to be sufficient.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index beaf95a..01c492f 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -48,13 +48,18 @@ static void await_completion(u32 *reg, u32 mask)
}
}
+/*
+ * This performs the external DRAM reset by driving the RESET pin low and
+ * then high again. According to the DDR3 spec, the RESET pin needs to be
+ * kept low for at least 200 us.
+ */
static void mctl_ddr3_reset(void)
{
struct sunxi_dram_reg *dram =
(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
clrbits_le32(dram-mcr, DRAM_MCR_RESET);
- udelay(2);
+ udelay(200);
setbits_le32(dram-mcr, DRAM_MCR_RESET);
}
--
1.8.3.2
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[U-Boot] [PATCH 07/14] sunxi: dram: Use divisor P=1 for PLL5
This configures the PLL5P clock frequency to something in the ballpark of
1GHz and allows more choices for MBUS and G2D clock frequency selection
(using their own divisors). In particular, it enables the use of 2/3 clock
speed ratio between MBUS and DRAM.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c | 28 +++-
1 file changed, 11 insertions(+), 17 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index d41fb1e..f756f23 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -186,7 +186,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
/* PLL5P and PLL6 are the potential clock sources for MBUS */
u32 pll6x_div, pll5p_div;
u32 pll6x_clk = clock_get_pll6() / 100;
- u32 pll5p_clk = clk / 24 * 24;
+ u32 pll5p_clk = clk / 24 * 48;
#ifdef CONFIG_SUN7I
pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
#endif
@@ -198,46 +198,40 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
reg_val = ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */
reg_val = ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */
if (clk = 540 clk 552) {
- /* dram = 540MHz, pll5p = 540MHz */
- pll5p_clk = 540;
+ /* dram = 540MHz, pll5p = 1080MHz */
+ pll5p_clk = 1080;
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15));
- reg_val |= CCM_PLL5_CTRL_P(1);
} else if (clk = 512 clk 528) {
- /* dram = 512MHz, pll5p = 384MHz */
- pll5p_clk = 384;
+ /* dram = 512MHz, pll5p = 1536MHz */
+ pll5p_clk = 1536;
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16));
- reg_val |= CCM_PLL5_CTRL_P(2);
} else if (clk = 496 clk 504) {
- /* dram = 496MHz, pll5p = 372MHz */
- pll5p_clk = 372;
+ /* dram = 496MHz, pll5p = 1488MHz */
+ pll5p_clk = 1488;
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31));
- reg_val |= CCM_PLL5_CTRL_P(2);
} else if (clk = 468 clk 480) {
- /* dram = 468MHz, pll5p = 468MHz */
- pll5p_clk = 468;
+ /* dram = 468MHz, pll5p = 936MHz */
+ pll5p_clk = 936;
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13));
- reg_val |= CCM_PLL5_CTRL_P(1);
} else if (clk = 396 clk 408) {
- /* dram = 396MHz, pll5p = 396MHz */
- pll5p_clk = 396;
+ /* dram = 396MHz, pll5p = 792MHz */
+ pll5p_clk = 792;
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
- reg_val |= CCM_PLL5_CTRL_P(1);
} else {
/* any other frequency that is a multiple of 24 */
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24));
- reg_val |= CCM_PLL5_CTRL_P(CCM_PLL5_CTRL_P_X(2));
}
reg_val = ~CCM_PLL5_CTRL_VCO_GAIN; /* PLL VCO Gain off */
reg_val |= CCM_PLL5_CTRL_EN;/* PLL On */
--
1.8.3.2
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[U-Boot] [PATCH 13/14] sunxi: dram: Derive write recovery delay from DRAM clock speed
The write recovery time is 15ns for all JEDEC DDR3 speed bins. And
instead of hardcoding it to 10 cycles, it is possible to set tighter
timings based on accurate calculations. For example, DRAM clock
frequencies up to 533MHz need only 8 cycles for write recovery.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 2db4f5a..9f55799 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -423,6 +423,21 @@ static void dramc_set_autorefresh_cycle(u32 clk, u32
density)
writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), dram-drr);
}
+/* Calculate the value for A11, A10, A9 bits in MR0 (write recovery) */
+static u32 ddr3_write_recovery(u32 clk)
+{
+ u32 twr_ns = 15; /* DDR3 spec says that it is 15ns for all speed bins */
+ u32 twr_ck = (twr_ns * clk + 999) / 1000;
+ if (twr_ck 5)
+ return 1;
+ else if (twr_ck = 8)
+ return twr_ck - 4;
+ else if (twr_ck = 10)
+ return 5;
+ else
+ return 6;
+}
+
/*
* If the dram-ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this
* means that DRAM is currently in self-refresh mode and retaining the old
@@ -612,7 +627,7 @@ unsigned long dramc_init(struct dram_para *para)
reg_val |= DRAM_MR_POWER_DOWN;
#endif
reg_val |= DRAM_MR_CAS_LAT(para-cas - 4);
- reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
+ reg_val |= DRAM_MR_WRITE_RECOVERY(ddr3_write_recovery(para-clock));
writel(reg_val, dram-mr);
writel(para-emr1, dram-emr);
--
1.8.3.2
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[U-Boot] [PATCH 11/14] sunxi: dram: Support sun4i (Allwinner A10) and sun5i (Allwinner A13)
Add the necessary missing bits from the legacy u-boot-sunxi for the
Allwinner A10 and A13 support (originally authored by Henrik Nordstrom,
Stefan Roese, Oliver Schinagl and Hans de Goede).
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c | 55 ++---
1 file changed, 52 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 2e994db..8f35e1b 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -71,9 +71,26 @@ static void mctl_ddr3_reset(void)
struct sunxi_dram_reg *dram =
(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
- clrbits_le32(dram-mcr, DRAM_MCR_RESET);
- udelay(200);
- setbits_le32(dram-mcr, DRAM_MCR_RESET);
+#ifdef CONFIG_SUN4I
+ struct sunxi_timer_reg *timer =
+ (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
+ u32 reg_val;
+
+ writel(0, timer-cpu_cfg);
+ reg_val = readl(timer-cpu_cfg);
+
+ if ((reg_val CPU_CFG_CHIP_VER_MASK) !=
+ CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
+ setbits_le32(dram-mcr, DRAM_MCR_RESET);
+ udelay(200);
+ clrbits_le32(dram-mcr, DRAM_MCR_RESET);
+ } else
+#endif
+ {
+ clrbits_le32(dram-mcr, DRAM_MCR_RESET);
+ udelay(200);
+ setbits_le32(dram-mcr, DRAM_MCR_RESET);
+ }
}
static void mctl_set_drive(void)
@@ -168,6 +185,26 @@ static void mctl_enable_dllx(u32 phase)
}
static u32 hpcr_value[32] = {
+#ifdef CONFIG_SUN5I
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0x1031, 0x1031, 0x0735, 0x1035,
+ 0x1035, 0x0731, 0x1031, 0,
+ 0x0301, 0x0301, 0x0301, 0x0301,
+ 0x0301, 0x0301, 0x0301, 0
+#endif
+#ifdef CONFIG_SUN4I
+ 0x0301, 0x0301, 0x0301, 0x0301,
+ 0x0301, 0x0301, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0x1031, 0x1031, 0x0735, 0x5031,
+ 0x1035, 0x0731, 0x1031, 0x0735,
+ 0x1035, 0x1031, 0x0731, 0x1035,
+ 0x1031, 0x0301, 0x0301, 0x0731
+#endif
#ifdef CONFIG_SUN7I
0x0301, 0x0301, 0x0301, 0x0301,
0x0301, 0x0301, 0x0301, 0x0301,
@@ -360,6 +397,13 @@ static void dramc_clock_output_en(u32 on)
else
clrbits_le32(dram-mcr, DRAM_MCR_DCLK_OUT);
#endif
+#ifdef CONFIG_SUN4I
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ if (on)
+ setbits_le32(ccm-dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
+ else
+ clrbits_le32(ccm-dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
+#endif
}
static const u16 tRFC_table[2][6] = {
@@ -502,6 +546,11 @@ unsigned long dramc_init(struct dram_para *para)
/* dram clock off */
dramc_clock_output_en(0);
+#ifdef CONFIG_SUN4I
+ /* select dram controller 1 */
+ writel(DRAM_CSEL_MAGIC, dram-csel);
+#endif
+
mctl_itm_disable();
mctl_enable_dll0(para-tpr3);
--
1.8.3.2
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[U-Boot] [PATCH 14/14] sunxi: dram: Autodetect DDR3 bus width and density
In the case if the 'dram_para' struct does not specify the exact bus width
or chip density, just use a trial and error method to find a usable
configuration.
Because all the major bugs in the DRAM initialization sequence are now
hopefully fixed, it should be safe to re-initialize the DRAM controller
multiple times until we get it configured right. The original Allwinner's
boot0 bootloader also used a similar autodetection trick.
The DDR3 spec contains the package pinout and addressing table for different
possible chip densities. It appears to be impossible to distinguish between a
single chip with 16 I/O data lines and a pair of chips with 8 I/O data lines
in the case if they provide the same storage capacity. Because a single 16-bit
chip has a higher density than a pair of equivalent 8-bit chips, it has
stricter refresh timings. So in the case of doubt, we assume that 16-bit
chips are used. Additionally, only Allwinner A20 has all A0-A15 address
lines and can support densities up to 8192. The older Allwinner A10 and
Allwinner A13 can only support densities up to 4096.
We deliberately leave out DDR2, dual-rank configurations and the special case
of a 8-bit chip with density 8192. None of these configurations seem to have
been ever used in real devices. And no new devices are likely to use these
exotic configurations (because only up to 2GB of RAM can be populated in any
case).
This DRAM autodetection feature potentially allows to have a single low
performance fail-safe DDR3 initialiazation for a universal single bootloader
binary, which can be compatible with all Allwinner A10/A13/A20 based devices
(if the ifdefs are replaced with a runtime SoC type detection).
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c | 52 +
1 file changed, 47 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 9f55799..3778cc9 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -536,17 +536,13 @@ static void mctl_set_impedance(u32 zq, u32 odt_en)
writel(DRAM_IOCR_ODT_EN(odt_en), dram-iocr);
}
-unsigned long dramc_init(struct dram_para *para)
+static unsigned long dramc_init_helper(struct dram_para *para)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
u32 reg_val;
u32 density;
int ret_val;
- /* check input dram parameter structure */
- if (!para)
- return 0;
-
/*
* only single rank DDR3 is supported by this code even though the
* hardware can theoretically support DDR2 and up to two ranks
@@ -671,3 +667,49 @@ unsigned long dramc_init(struct dram_para *para)
return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
}
+
+unsigned long dramc_init(struct dram_para *para)
+{
+ unsigned long dram_size, actual_density;
+
+ /* If the dram configuration is not provided, use a default */
+ if (!para)
+ return 0;
+
+ /* if everything is known, then autodetection is not necessary */
+ if (para-io_width para-bus_width para-density)
+ return dramc_init_helper(para);
+
+ /* try to autodetect the DRAM bus width and density */
+ para-io_width = 16;
+ para-bus_width = 32;
+#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I)
+ /* only A0-A14 address lines on A10/A13, limiting max density to 4096 */
+ para-density = 4096;
+#else
+ /* all A0-A15 address lines on A20, which allow density 8192 */
+ para-density = 8192;
+#endif
+
+ dram_size = dramc_init_helper(para);
+ if (!dram_size) {
+ /* if 32-bit bus width failed, try 16-bit bus width instead */
+ para-bus_width = 16;
+ dram_size = dramc_init_helper(para);
+ if (!dram_size) {
+ /* if 16-bit bus width also failed, then bail out */
+ return dram_size;
+ }
+ }
+
+ /* check if we need to adjust the density */
+ actual_density = (dram_size 17) * para-io_width / para-bus_width;
+
+ if (actual_density != para-density) {
+ /* update the density and re-initialize DRAM again */
+ para-density = actual_density;
+ dram_size = dramc_init_helper(para);
+ }
+
+ return dram_size;
+}
--
1.8.3.2
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[U-Boot] [PATCH 06/14] sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6)
The sun5i hardware (Allwinner A13) introduced configurable MBUS clock speed.
Allwinner A13 uses only 16-bit data bus width to connect the external DRAM,
which is halved compared to the 32-bit data bus of sun4i (Allwinner A10), so
it does not make much sense to clock a wider internal bus at a very high speed.
The Allwinner A13 manual specifies 300 MHz MBUS clock speed limit and 533 MHz
DRAM clock speed limit. Newer sun7i hardware (Allwinner A20) has a full width
32-bit external memory interface again, but still keeps the MBUS clock speed
configurable. Clocking MBUS too low inhibits memory performance and one has
to find the optimal MBUS/DRAM clock speed ratio, which may depend on many
factors.
This patch introduces a new 'mbus_clock' parameter for the 'dram_para' struct
and uses it as a desired MBUS clock speed target. If 'mbus_clock' is not set,
300 MHz is used by default to match the older hardcoded settings.
Attempting to set the MBUS clock speed has no effect on sun4i, but does no
harm either.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c| 41 +-
arch/arm/include/asm/arch-sunxi/dram.h | 1 +
2 files changed, 36 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index afeb2df..d41fb1e 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -178,11 +178,19 @@ static void mctl_configure_hostport(void)
writel(hpcr_value[i], dram-hpcr[i]);
}
-static void mctl_setup_dram_clock(u32 clk)
+static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
{
u32 reg_val;
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ /* PLL5P and PLL6 are the potential clock sources for MBUS */
+ u32 pll6x_div, pll5p_div;
+ u32 pll6x_clk = clock_get_pll6() / 100;
+ u32 pll5p_clk = clk / 24 * 24;
+#ifdef CONFIG_SUN7I
+ pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
+#endif
+
/* setup DRAM PLL */
reg_val = readl(ccm-pll5_cfg);
reg_val = ~CCM_PLL5_CTRL_M_MASK; /* set M to 0 (x1) */
@@ -191,30 +199,35 @@ static void mctl_setup_dram_clock(u32 clk)
reg_val = ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */
if (clk = 540 clk 552) {
/* dram = 540MHz, pll5p = 540MHz */
+ pll5p_clk = 540;
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15));
reg_val |= CCM_PLL5_CTRL_P(1);
} else if (clk = 512 clk 528) {
/* dram = 512MHz, pll5p = 384MHz */
+ pll5p_clk = 384;
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16));
reg_val |= CCM_PLL5_CTRL_P(2);
} else if (clk = 496 clk 504) {
/* dram = 496MHz, pll5p = 372MHz */
+ pll5p_clk = 372;
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31));
reg_val |= CCM_PLL5_CTRL_P(2);
} else if (clk = 468 clk 480) {
/* dram = 468MHz, pll5p = 468MHz */
+ pll5p_clk = 468;
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13));
reg_val |= CCM_PLL5_CTRL_P(1);
} else if (clk = 396 clk 408) {
/* dram = 396MHz, pll5p = 396MHz */
+ pll5p_clk = 396;
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
@@ -242,10 +255,26 @@ static void mctl_setup_dram_clock(u32 clk)
#endif
/* setup MBUS clock */
- reg_val = CCM_MBUS_CTRL_GATE |
- CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
- CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) |
- CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
+ if (!mbus_clk)
+ mbus_clk = 300;
+ pll6x_div = (pll6x_clk + mbus_clk - 1) / mbus_clk;
+ pll5p_div = (pll5p_clk + mbus_clk - 1) / mbus_clk;
+
+ if (pll6x_div = 16 pll6x_clk / pll6x_div pll5p_clk / pll5p_div) {
+ /* use PLL6 as the MBUS clock source */
+ reg_val = CCM_MBUS_CTRL_GATE |
+ CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
+ CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
+
[U-Boot] [PATCH 00/14] sunxi: Allwinner A10/A13/A20 DRAM controller fixes
Hello, First of all, it may be worth reminding that no accurate documentation for this particular DRAM controller exists in public access. However it is suspected that Allwinner uses one of the revisions of Synopsys DesignWare DDR2/3-Lite Memory Controller IP (MCTL) combined with DDR2/3-Lite PHY IP in A10/A13/A20. Also this DRAM controller apparently has siblings in Rockchip RK29XX, RK30XX and TI KeyStone2 hardware, which have some documentation and some bits of kernel and bootloader sources available in the Internet. Not to mention the original Allwinner boot0 bootloader sources and the suspend support code from the linux-sunxi kernel. This provides enough hints for finding out how the DRAM controller actually works by checking various bits of information via the trial and error method. In other words, a few people from the linux-sunxi community (me included) are essentially doing reverse engineering of the DRAM controller and using the linux-sunxi wiki to document all the findings: http://linux-sunxi.org/DRAM_Controller If Allwinner Technology, Synopsys DesignWare or anyone else can share real documentation or at least provide some hints or review the code, that would be really appreciated. Nevertheless, here is a patch set, which tries to improve the current u-boot sunxi dram code in the following way: * remove the convoluted dead code paths, which have no real use * fix obvious bugs and timing violations * add real ZQ calibration and ODT support for better reliability and higher clock speed potential * remove duplication and share code between sun4i/sun5i/sun7i * add more configuration knobs (such as MBUS clock frequency) * optional support for automatic detection of the bus width and chip density This patch set only modifies the dram.c and dram.h source files and applies cleanly to u-boot v2014.07 (but is intended for v2014.10). The patch set is organized in such a way, that we first fix bugs in the current sun7i implementation, and only after that add the missing sun4i/sun5i support bits. As such, it clashes with the dram parts of the sun4i/sun5i support patches, earlier submitted by Hans de Goede. Most of this work has been done during the last 3 months (and apart from the u-boot patches, it also includes improving the DRAM controler documentation in the wiki and developing extra tools, which assist in finding optimal DRAM configuration for each device). Many thanks to Jens Kuske, who helped really a lot in brainstorming and testing. To sum it up, the main purpose of these patches is to provide: 1) The potential ability to have a universal generic failsafe DRAM initialization for all Allwinner A10/A13/A20 devices using the same u-boot binary (or at least the same SPL) 2) The configuration knobs, which allow to reach extreme clock speeds and maximize performance for the selected boards with the help of extra tuning. These patches are also available at: https://github.com/ssvb/u-boot-sunxi-dram/commits/sunxi-dram-fixes As a demonstration, there is also a highly experimental test branch with the DRAM performance tuning for the Cubietruck board (initially targeting 600 MHz DRAM clock speed, up from the current 432 MHz), which is compatible with the sunxi-3.4 kernel: https://github.com/ssvb/u-boot-sunxi-dram/commits/highspeedtruck-sunxi-3.4 Or alternatively, a similar branch for the mainline 3.16 kernel: https://github.com/ssvb/u-boot-sunxi-dram/commits/highspeedtruck-mainline-3.16 The 600 MHz clock speed is clearly an overkill and may not work on every device, so we will have to settle with something more modest in the end. But, for example, the DRAM in my Cubietruck can be clocked up to 648 MHz. The preliminary DRAM parameters tuning instructions are available at: http://linux-sunxi.org/A10_DRAM_Controller_Calibration Siarhei Siamashka (14): sunxi: dram: Remove useless 'dramc_scan_dll_para()' function sunxi: dram: Remove broken super-standby remnants sunxi: dram: Respect the DDR3 reset timing requirements sunxi: dram: Code cleanup and comments for the CKE delay handling sunxi: dram: Code cleanup for the impedance calibration sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6) sunxi: dram: Use divisor P=1 for PLL5 sunxi: dram: Improve DQS gate data training error handling sunxi: dram: Add a helper function 'mctl_get_number_of_lanes' sunxi: dram: Configurable DQS gating window mode and delay sunxi: dram: Support sun4i (Allwinner A10) and sun5i (Allwinner A13) sunxi: dram: Drop DDR2 support and assume only single rank DDR3 memory sunxi: dram: Derive write recovery delay from DRAM clock speed sunxi: dram: Autodetect DDR3 bus width and density arch/arm/cpu/armv7/sunxi/dram.c| 606 - arch/arm/include/asm/arch-sunxi/dram.h | 11 +- 2 files changed, 374 insertions(+), 243 deletions(-) -- 1.8.3.2 ___ U-Boot mailing list
[U-Boot] [PATCH 09/14] sunxi: dram: Add a helper function 'mctl_get_number_of_lanes'
It is going to be useful in more than one place.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c | 30 +++---
1 file changed, 19 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 18a5c3b..49d1770 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -115,23 +115,31 @@ static void mctl_enable_dll0(u32 phase)
udelay(22);
}
+/* Get the number of DDR byte lanes */
+static u32 mctl_get_number_of_lanes(void)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+ switch (readl(dram-dcr) DRAM_DCR_BUS_WIDTH_MASK) {
+ case DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT):
+ return 4;
+ case DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_16BIT):
+ return 2;
+ default:
+ return 1;
+ }
+}
+
/*
* Note: This differs from pm/standby in that it checks the bus width
*/
static void mctl_enable_dllx(u32 phase)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
- u32 i, n, bus_width;
-
- bus_width = readl(dram-dcr);
+ u32 i, number_of_lanes;
- if ((bus_width DRAM_DCR_BUS_WIDTH_MASK) ==
- DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT))
- n = DRAM_DCR_NR_DLLCR_32BIT;
- else
- n = DRAM_DCR_NR_DLLCR_16BIT;
+ number_of_lanes = mctl_get_number_of_lanes();
- for (i = 1; i n; i++) {
+ for (i = 1; i = number_of_lanes; i++) {
clrsetbits_le32(dram-dllcr[i], 0xf 14,
(phase 0xf) 14);
clrsetbits_le32(dram-dllcr[i], DRAM_DLLCR_NRESET,
@@ -140,12 +148,12 @@ static void mctl_enable_dllx(u32 phase)
}
udelay(2);
- for (i = 1; i n; i++)
+ for (i = 1; i = number_of_lanes; i++)
clrbits_le32(dram-dllcr[i], DRAM_DLLCR_NRESET |
DRAM_DLLCR_DISABLE);
udelay(22);
- for (i = 1; i n; i++)
+ for (i = 1; i = number_of_lanes; i++)
clrsetbits_le32(dram-dllcr[i], DRAM_DLLCR_DISABLE,
DRAM_DLLCR_NRESET);
udelay(22);
--
1.8.3.2
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[U-Boot] [PATCH 01/14] sunxi: dram: Remove useless 'dramc_scan_dll_para()' function
The attempt to do DRAM parameters calibration in 'dramc_scan_dll_para()'
function by trying different DLL adjustments and using the hardware
DQS gate training result as a feedback is a great source of inspiration,
but it just can't work properly the way it is implemented now. The fatal
problem of this implementation is that the DQS gating window can be
successfully found for almost every DLL delay adjustment setup that
gets tried. Thus making it unable to see any real difference between
'good' and 'bad' settings.
Also this code was supposed to be only activated by setting the highest
bit in the 'dram_tpr3' variable of the 'dram_para' struct (per-board dram
configuration). But none of the linux-sunxi devices has ever used it for
real. Basically, this code is just a dead weight.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c | 125 +---
1 file changed, 1 insertion(+), 124 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index b43c4b4..76a7106 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -264,117 +264,6 @@ static int dramc_scan_readpipe(void)
return 0;
}
-static int dramc_scan_dll_para(void)
-{
- struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
- const u32 dqs_dly[7] = {0x3, 0x2, 0x1, 0x0, 0xe, 0xd, 0xc};
- const u32 clk_dly[15] = {0x07, 0x06, 0x05, 0x04, 0x03,
-0x02, 0x01, 0x00, 0x08, 0x10,
-0x18, 0x20, 0x28, 0x30, 0x38};
- u32 clk_dqs_count[15];
- u32 dqs_i, clk_i, cr_i;
- u32 max_val, min_val;
- u32 dqs_index, clk_index;
-
- /* Find DQS_DLY Pass Count for every CLK_DLY */
- for (clk_i = 0; clk_i 15; clk_i++) {
- clk_dqs_count[clk_i] = 0;
- clrsetbits_le32(dram-dllcr[0], 0x3f 6,
- (clk_dly[clk_i] 0x3f) 6);
- for (dqs_i = 0; dqs_i 7; dqs_i++) {
- for (cr_i = 1; cr_i 5; cr_i++) {
- clrsetbits_le32(dram-dllcr[cr_i],
- 0x4f 14,
- (dqs_dly[dqs_i] 0x4f) 14);
- }
- udelay(2);
- if (dramc_scan_readpipe() == 0)
- clk_dqs_count[clk_i]++;
- }
- }
- /* Test DQS_DLY Pass Count for every CLK_DLY from up to down */
- for (dqs_i = 15; dqs_i 0; dqs_i--) {
- max_val = 15;
- min_val = 15;
- for (clk_i = 0; clk_i 15; clk_i++) {
- if (clk_dqs_count[clk_i] == dqs_i) {
- max_val = clk_i;
- if (min_val == 15)
- min_val = clk_i;
- }
- }
- if (max_val 15)
- break;
- }
-
- /* Check if Find a CLK_DLY failed */
- if (!dqs_i)
- goto fail;
-
- /* Find the middle index of CLK_DLY */
- clk_index = (max_val + min_val) 1;
- if ((max_val == (15 - 1)) (min_val 0))
- /* if CLK_DLY[MCTL_CLK_DLY_COUNT] is very good, then the middle
-* value can be more close to the max_val
-*/
- clk_index = (15 + clk_index) 1;
- else if ((max_val (15 - 1)) (min_val == 0))
- /* if CLK_DLY[0] is very good, then the middle value can be more
-* close to the min_val
-*/
- clk_index = 1;
- if (clk_dqs_count[clk_index] dqs_i)
- clk_index = min_val;
-
- /* Find the middle index of DQS_DLY for the CLK_DLY got above, and Scan
-* read pipe again
-*/
- clrsetbits_le32(dram-dllcr[0], 0x3f 6,
- (clk_dly[clk_index] 0x3f) 6);
- max_val = 7;
- min_val = 7;
- for (dqs_i = 0; dqs_i 7; dqs_i++) {
- clk_dqs_count[dqs_i] = 0;
- for (cr_i = 1; cr_i 5; cr_i++) {
- clrsetbits_le32(dram-dllcr[cr_i],
- 0x4f 14,
- (dqs_dly[dqs_i] 0x4f) 14);
- }
- udelay(2);
- if (dramc_scan_readpipe() == 0) {
- clk_dqs_count[dqs_i] = 1;
- max_val = dqs_i;
- if (min_val == 7)
- min_val = dqs_i;
- }
- }
-
- if (max_val 7) {
- dqs_index = (max_val + min_val) 1;
- if ((max_val == (7-1)) (min_val 0))
- dqs_index = (7 + dqs_index) 1;
- else if ((max_val (7-1)) (min_val == 0))
-
[U-Boot] [PATCH 05/14] sunxi: dram: Code cleanup for the impedance calibration
Moved the impedance setup code part into a separate function. Added explicit
wait for ZQ calibration completion before proceeding to the next initialization
steps. Removed the CONFIG_SUN7I ifdef guard around the code, which has identical
behaviour on sun4i/sun5i/sun7i. And if 'odt_en' is set in the 'dram_para'
struct,
then ODT now actually gets enabled in the DRAM_IOCR register (which the older
code failed to do and was always running without ODT no matter the settings).
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c| 71 --
arch/arm/include/asm/arch-sunxi/dram.h | 4 ++
2 files changed, 63 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index def4247..afeb2df 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -49,6 +49,19 @@ static void await_completion(u32 *reg, u32 mask)
}
/*
+ * Wait up to 1s for mask to be set in given reg.
+ */
+static void await_bits_set(u32 *reg, u32 mask)
+{
+ unsigned long tmo = timer_get_us() + 100;
+
+ while ((readl(reg) mask) != mask) {
+ if (timer_get_us() tmo)
+ panic(Timeout initialising DRAM\n);
+ }
+}
+
+/*
* This performs the external DRAM reset by driving the RESET pin low and
* then high again. According to the DDR3 spec, the RESET pin needs to be
* kept low for at least 200 us.
@@ -353,6 +366,51 @@ static void mctl_ddr3_initialize(void)
await_completion(dram-ccr, DRAM_CCR_INIT);
}
+/*
+ * Perform impedance calibration on the DRAM controller side of the wire.
+ */
+static void mctl_set_impedance(u32 zq, u32 odt_en)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+ u32 reg_val;
+ u32 zprog = zq 0xFF, zdata = (zq 8) 0xF;
+
+#ifndef CONFIG_SUN7I
+ /* wait for the default impedance configuration to settle */
+ await_bits_set(dram-zqsr, DRAM_ZQSR_ZDONE);
+#endif
+
+ if (!odt_en)
+ return;
+
+#ifdef CONFIG_SUN7I
+ /* some weird magic, but sun7i fails to boot without it */
+ writel((1 24) | (1 1), dram-zqcr1);
+#endif
+
+ /* needed at least for sun5i, because it does not self clear there */
+ clrbits_le32(dram-zqcr0, DRAM_ZQCR0_ZCAL);
+
+ if (zdata) {
+ /* set the user supplied impedance data */
+ reg_val = DRAM_ZQCR0_ZDEN | zdata;
+ writel(reg_val, dram-zqcr0);
+ /* no need to wait, this takes effect immediately */
+ } else {
+ /* do the calibration using the external resistor */
+ reg_val = DRAM_ZQCR0_ZCAL | DRAM_ZQCR0_IMP_DIV(zprog);
+ writel(reg_val, dram-zqcr0);
+ /* wait for the new impedance configuration to settle */
+ await_bits_set(dram-zqsr, DRAM_ZQSR_ZDONE);
+ }
+
+ /* needed at least for sun5i, because it does not self clear there */
+ clrbits_le32(dram-zqcr0, DRAM_ZQCR0_ZCAL);
+
+ /* set I/O configure register */
+ writel(DRAM_IOCR_ODT_EN(odt_en), dram-iocr);
+}
+
unsigned long dramc_init(struct dram_para *para)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
@@ -407,20 +465,9 @@ unsigned long dramc_init(struct dram_para *para)
reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
writel(reg_val, dram-dcr);
-#ifdef CONFIG_SUN7I
- setbits_le32(dram-zqcr1, (0x1 24) | (0x1 1));
- if (para-tpr4 0x2)
- clrsetbits_le32(dram-zqcr1, (0x1 24), (0x1 1));
dramc_clock_output_en(1);
-#endif
-#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
- /* set odt impendance divide ratio */
- reg_val = ((para-zq) 8) 0xf;
- reg_val |= ((para-zq) 0xff) 20;
- reg_val |= (para-zq) 0xf000;
- writel(reg_val, dram-zqcr0);
-#endif
+ mctl_set_impedance(para-zq, para-odt_en);
mctl_set_cke_delay();
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h
b/arch/arm/include/asm/arch-sunxi/dram.h
index 67fbfad..4433eeb 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -159,6 +159,10 @@ struct dram_para {
#define DRAM_ZQCR0_IMP_DIV(n) (((n) 0xff) 20)
#define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff)
+#define DRAM_ZQCR0_ZCAL (1 31) /* Starts ZQ calibration when set to 1 */
+#define DRAM_ZQCR0_ZDEN (1 28) /* Uses ZDATA instead of doing calibration */
+
+#define DRAM_ZQSR_ZDONE (1 31) /* ZQ calibration completion flag */
#define DRAM_IOCR_ODT_EN(n) n) 0x3) 30) | ((n) 0x3) 0)
#define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3)
--
1.8.3.2
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[U-Boot] [PATCH 0/2] sunxi: FEL boot mode improvements
Hello, One of the current FEL problems is a very limited available SRAM space, so that trying to add new code to u-boot or even changing the GCC version introduces a risk of exceeding it. Another problem is that booting a Linux system on Allwinner A10/A13 devices in FEL mode ends up with L2 cache disabled, and this is not very nice for the performance. These two patches make FEL boot mode more usable. Siarhei Siamashka (2): sunxi: Use Thumb2 and move stack to gain more SRAM space in FEL mode sunxi: Set the AUXCR L2EN bit for sun4i/sun5i in FEL boot mode arch/arm/cpu/armv7/sunxi/Makefile | 1 + arch/arm/cpu/armv7/sunxi/board.c| 12 + arch/arm/cpu/armv7/sunxi/start_fel.S| 42 + arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds | 4 +-- include/configs/sunxi-common.h | 2 -- 5 files changed, 57 insertions(+), 4 deletions(-) create mode 100644 arch/arm/cpu/armv7/sunxi/start_fel.S -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] sunxi: Set the AUXCR L2EN bit for sun4i/sun5i in FEL boot mode
This is needed to have feature parity with the normal boot mode, where the L2EN bit in the CP15 Auxiliary Control Register is set by the BROM code right from the start. If this is not done, the Linux system ends up booted with the L2 cache disabled. Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com --- arch/arm/cpu/armv7/sunxi/board.c | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 49c9448..86cf4c9 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -69,6 +69,18 @@ void s_init(void) mcr p15, 0, r0, c1, c0, 1\n); #endif +#if defined(CONFIG_SPL_FEL) (defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I)) + /* For ARM Cortex-A8 based hardware (sun4i and sun5i), the L2EN bit is +* set by the BROM code in the normal mode, but not in the FEL mode. +* Here we fix this inconsistency in the Auxiliary Ctl reg by also +* setting the missing L2EN bit. +*/ + asm volatile( + mrc p15, 0, r0, c1, c0, 1\n + orr r0, r0, #2\n + mcr p15, 0, r0, c1, c0, 1\n : : : r0); +#endif + clock_init(); timer_init(); gpio_init(); -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] sunxi: Use Thumb2 and move stack to gain more SRAM space in FEL mode
The Allwinner SoCs support a special FEL boot mode, which can be activated
by users via a button press (or other means). In the FEL mode, the BROM
implements a custom FEL protocol over USB, which allows to upload code to
the device and run it. This protocol had been reverse engineered and
documented by Henrik Nordström:
http://lists.phcomp.co.uk/pipermail/arm-netbook/2012-June/004341.html
Because the BROM code is using some parts of the SRAM for itself, only a
few areas are available for use in u-boot. Currently the SPL is loaded
into the 0x2000-0x5cff Free for program use area and the stack pointer
is at the end of this area. This is barely enough to fit just the current
SPL and leaves almost no headroom for the future code.
This patch enables the use of a more compact Thumb2 mode for compiling the
FEL SPL binary. And also relocates the stack to another 0x8000-0xbfff Free
for program use area. Additionally, the BSS segment is cleared.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/start_fel.S| 42 +
arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds | 4 +--
include/configs/sunxi-common.h | 2 --
4 files changed, 45 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/cpu/armv7/sunxi/start_fel.S
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
index a64bfa1..b3eff98 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -21,5 +21,6 @@ ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SUN7I)+= dram.o
ifdef CONFIG_SPL_FEL
obj-y += start.o
+extra-y += start_fel.o
endif
endif
diff --git a/arch/arm/cpu/armv7/sunxi/start_fel.S
b/arch/arm/cpu/armv7/sunxi/start_fel.S
new file mode 100644
index 000..2789fd9
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/start_fel.S
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2014 Siarhei Siamashka siarhei.siamas...@gmail.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+.syntax unified
+.text
+.arm
+.arch armv7a
+.p2align 2
+
+.globl _start_fel
+.globl s_init
+.globl __bss_start
+.globl __bss_end
+
+_start_fel:
+ /* Relocate stack to the 0x8000-0xBFFF area */
+ mov r0, #0xC000
+ str sp, [r0, #-4]!
+ str lr, [r0, #-4]!
+ adr lr, _exit_fel /* Return back to '_exit_fel' */
+ mov sp, r0
+
+ /* Erase the BSS segment */
+ ldr r0, =__bss_start
+ ldr r1, =__bss_end
+ mov r2, #0
+0: cmp r0, r1
+ strbne r2, [r0], #1
+ bne 0b
+
+ /* Pass control to the 's_init()' function */
+ b s_init
+
+_exit_fel:
+ /* Relocate stack back and return */
+ mov r0, #0xC000
+ ldr sp, [r0, #-4]!
+ ldr lr, [r0, #-4]!
+ bx lr
diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
index 364e35c..418c2fc 100644
--- a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
+++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
@@ -6,7 +6,7 @@
*/
OUTPUT_FORMAT(elf32-littlearm, elf32-littlearm, elf32-littlearm)
OUTPUT_ARCH(arm)
-ENTRY(s_init)
+ENTRY(_start_fel)
SECTIONS
{
. = 0x2000;
@@ -14,7 +14,7 @@ SECTIONS
. = ALIGN(4);
.text :
{
- *(.text.s_init)
+ arch/arm/cpu/armv7/sunxi/start_fel.o(.text)
*(.text*)
}
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 5d72d62..4b980e9 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -18,10 +18,8 @@
*/
#define CONFIG_SUNXI /* sunxi family */
#ifdef CONFIG_SPL_BUILD
-#ifndef CONFIG_SPL_FEL
#define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */
#endif
-#endif
#include asm/arch/cpu.h /* get chip and board defs */
--
1.8.3.2
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Re: [U-Boot] [PATCH 1/3] scripts: add scripts/gnu_make to not hard-code make command
Hello Masahiro, On 17-07-14 11:18, Masahiro Yamada wrote: U-Boot is expected to be built on various platforms but makefiles are written for GNU Make. We should keep in mind that the command 'make' is not always GNU Make. For example, on Linux, people generally do: make board_config; make But FreeBSD folks do gmake board_config; gmake (The command 'make' on FreeBSD is BSD Make, not GNU Make) It is not a good idea to hard-code the command name 'make' in MAKEALL or buildman. indeed, not a good idea. Instead, they should call the make command via this helper script to make sure it is GNU Make. yup, or the name of the executable could be displayed, so it only needs to be checked once at startup (and error out if no GNU make is found at all). +++ b/scripts/gnu_make nitpicking, most script use a dash instead of an underscore. @@ -0,0 +1,30 @@ +#!/bin/sh +# +# Call GNU Make +# +# U-Boot is supposed to be built on various platforms. +# One problem is that the command 'make' is not always GNU Make. +# (For ex. the command name for GNU Make on FreeBSD is usually 'gmake'.) +# It is not a good idea to hard-code the command name 'make' +# in scripts where where GNU Make is expected. +# In that case, call this helper script to make sure to invoke GNU Make. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +gnu_make= + +for m in make gmake +do + if $m --version 2/dev/null | grep -q GNU; then + gnu_make=$m + break + fi +done + +if [ -z $gnu_make ]; then + echo GNU Make not found 2 + exit 1 +fi + +$gnu_make $@ I guess, it could use exec here, since the script itself is no longer needed. Regards, Jeroen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] MAKEALL: make sure to invoke GNU Make
Hello Masahiro,
On 17-07-14 11:18, Masahiro Yamada wrote:
Since the command name 'make' is not GNU Make on some platforms
such as FreeBSD, MAKEALL should call the make via scripts/gnu_make.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
MAKEALL | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/MAKEALL b/MAKEALL
index 37ef71e..02c2f9f 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -630,14 +630,16 @@ build_target() {
output_dir=${OUTPUT_PREFIX}
fi
+ GNU_MAKE=scripts/gnu_make
+
target_arch=$(get_target_arch ${target})
eval cross_toolchain=\$CROSS_COMPILE_`echo $target_arch | tr
'[:lower:]' '[:upper:]'`
if [ ${cross_toolchain} ] ; then
- MAKE=make CROSS_COMPILE=${cross_toolchain}
+ MAKE=$GNU_MAKE CROSS_COMPILE=${cross_toolchain}
elif [ ${CROSS_COMPILE} ] ; then
- MAKE=make CROSS_COMPILE=${CROSS_COMPILE}
+ MAKE=$GNU_MAKE CROSS_COMPILE=${CROSS_COMPILE}
else
- MAKE=make
+ MAKE=$GNU_MAKE
fi
if [ ${output_dir} != . ] ; then
while by itself this might be correct, opt is not a POSIX command
and MAKEALL will not work at all on a BSD host. Perhaps it is
time I have a look at what buildman is
Regards,
Jeroen
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Re: [U-Boot] [PATCH 2/2] sunxi: Set the AUXCR L2EN bit for sun4i/sun5i in FEL boot mode
Hello Siarhei, On 18-07-14 19:09, Siarhei Siamashka wrote: This is needed to have feature parity with the normal boot mode, where the L2EN bit in the CP15 Auxiliary Control Register is set by the BROM code right from the start. If this is not done, the Linux system ends up booted with the L2 cache disabled. I don't know a single about the sunxi, but shouldn't linux be patched instead. The commit message seems to indicate it is not an u-boot issue. Regards, Jeroen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Random number generator - why I need it
Hello Stanislav, On 18-07-14 16:41, Stanislav Vlasic wrote: What I need is solution for getting random number (on first boot) which will be written to ubootenv. mm, you forgot to describe why.. and what you mean with random. Anyway, can't the host programming the device not provide a pseudo random number. It likely has far better provision for that... Regards, Jeroen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-boot] question about nand_scan_bbt()
On Wed, 2014-07-09 at 18:27 +0800, tiger...@via-alliance.com wrote: Hi, Scott: I have a question about nand_scan_bbt() function in drivers/mtd/nand/nand_bbt.c . …… len = (1 this-bbt_erase_shift); // bbt_erase_shift = 18 (256KB) len += (len this-page_shift) * mtd-oobsize; buf = vmalloc(len); …… Why does it need to allocate “1 block size + all pages’ oob size in this block” . It seems other functions called in nand_scan_bbt() only needs a small buf (“one page size + its oob size”). read_bbt() appears to operate one block at a time. This code comes from Linux, so linux-mtd may be a better place to ask questions about it. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-sunxi.git/master
Hi Albert,
Welcome back!
The following changes since commit 23f23f23d509e8e873797884456070c8a47d72b2:
socfpga: Relocate arch common functions away from board (2014-07-05 10:14:46
+0200)
are available in the git repository at:
git://git.denx.de/u-boot-sunxi.git master
for you to fetch changes up to 7c48b015100eeff0e1bbb766394f7beca23afb48:
sunxi: use setbits_le32 to enable the DMA clock (2014-07-18 19:42:25 +0100)
Chen-Yu Tsai (1):
sunxi: Add support for using MII phy-s with the GMAC nic
Hans de Goede (12):
sunxi: mksunxiboot: Fix loading of files with a size which is not a
multiple of 4
sunxi: Fix u-boot-spl.lds to refer to .vectors
sunxi: Remove mmc DMA support
sunxi: Implement reset_cpu
sunxi: Add sun4i support
sunxi: Add sun5i support
sunxi: Add emac glue, enable emac on the cubieboard
sunxi: Add Ian Campbell and Hans de Goede as cubietruck board-maintainers
mvtwsi: convert to CONFIG_SYS_I2C framework
sunxi: Add i2c support
sunxi: Add axp152 pmic support
sunxi: Fix reset hang on sun5i
Henrik Nordstrom (1):
sunxi: Add axp209 pmic support
Ian Campbell (4):
sunxi: Avoid unused variable warning.
sunxi: add Cubieboard2 support
sunxi: add gpio driver
sunxi: use setbits_le32 to enable the DMA clock
Jonathan Liu (1):
sunxi: use random parts of SID to set ethaddr
Stefan Roese (1):
net: Rename and cleanup sunxi (Allwinner) emac driver
arch/arm/cpu/armv7/sunxi/Makefile | 4 +
arch/arm/cpu/armv7/sunxi/board.c| 41 ++-
arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 3 +-
arch/arm/cpu/armv7/sunxi/cpu_info.c | 15 +++
arch/arm/cpu/armv7/sunxi/dram.c | 102 -
arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds | 5 +
arch/arm/cpu/armv7/sunxi/u-boot-spl.lds | 6 +
arch/arm/include/asm/arch-kirkwood/config.h | 3 +-
arch/arm/include/asm/arch-sunxi/gpio.h | 2 +
arch/arm/include/asm/arch-sunxi/i2c.h | 15 +++
arch/arm/include/asm/arch-sunxi/timer.h | 5 +
board/sunxi/Makefile| 4 +
board/sunxi/board.c | 67 +++
board/sunxi/dram_a13_oli_micro.c| 32 ++
board/sunxi/dram_cubieboard.c | 31 ++
board/sunxi/dram_cubieboard2.c | 31 ++
board/sunxi/dram_r7dongle.c | 31 ++
board/sunxi/gmac.c | 11 ++
boards.cfg | 9 +-
drivers/gpio/Makefile | 1 +
drivers/gpio/sunxi_gpio.c | 102 +
drivers/i2c/Makefile| 2 +-
drivers/i2c/mvtwsi.c| 88 ---
drivers/mmc/sunxi_mmc.c | 141 ++-
drivers/net/Makefile| 2 +-
drivers/net/{sunxi_wemac.c = sunxi_emac.c} | 140 +++
drivers/power/Makefile | 2 +
drivers/power/axp152.c | 97
drivers/power/axp209.c | 167
include/axp152.h| 10 ++
include/axp209.h| 14 +++
include/configs/edminiv2.h | 3 +-
include/configs/sun4i.h | 24
include/configs/sun5i.h | 24
include/configs/sun7i.h | 1 +
include/configs/sunxi-common.h | 27 -
include/netdev.h| 2 +-
tools/mksunxiboot.c | 10 +-
38 files changed, 1010 insertions(+), 264 deletions(-)
create mode 100644 arch/arm/include/asm/arch-sunxi/i2c.h
create mode 100644 board/sunxi/dram_a13_oli_micro.c
create mode 100644 board/sunxi/dram_cubieboard.c
create mode 100644 board/sunxi/dram_cubieboard2.c
create mode 100644 board/sunxi/dram_r7dongle.c
create mode 100644 drivers/gpio/sunxi_gpio.c
rename drivers/net/{sunxi_wemac.c = sunxi_emac.c} (78%)
create mode 100644 drivers/power/axp152.c
create mode 100644 drivers/power/axp209.c
create mode 100644 include/axp152.h
create mode 100644 include/axp209.h
create mode 100644 include/configs/sun4i.h
create mode 100644 include/configs/sun5i.h
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Re: [U-Boot] [PATCH v2 2/5] sunxi: add USB EHCI driver
On Tue, 2014-07-15 at 23:56 +0200, Roman Byshko wrote: [...] + /* this should be used instead of next two lines if + * sunxi_gpio.c is merged upstream + * gpio_direction_output(sunxi_ehci-gpio_vbus, 1); */ + sunxi_gpio_set_cfgpin(sunxi_ehci-gpio_vbus, SUNXI_GPIO_OUTPUT); + sunxi_gpio_output(sunxi_ehci-gpio_vbus, 1); Please can you base v3 on: git://git.denx.de/u-boot-sunxi.git master This includes the gpio stuff which you need here. Cheers, Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 0/3] sunxi: AHCI support
Hi Albert, I picked up the GPIO and Cubieboard2 bits of v2 into the sunxi PR which I just sent out[0]. What remains here in v3 is the generic AHCI changes and the sunxi driver itself which I have rebased onto u-boot-sunxi.git#master. Cheers, Ian. [0] http://lists.denx.de/pipermail/u-boot/2014-July/183993.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] board_r: run scsi init() on ARM too
This has been disabled for ARM in initr_scsi since that function was
introduced. However it works fine for me on Cubieboard and Cubietruck (with the
upcoming AHCI glue patch).
I also tested on two random ARM platforms which seem to define CONFIG_CMD_SCSI:
- highbank worked fine (on midway hardware)
- omap5_uevm built OK and I confirmed using objdump that things were as
expected (i.e. the default weak scsi_init nop was used).
While there remove the mismatched comment from the #endif (omitting the comment
seems to be the prevailing style in this file) and add a missing return to
initr_doc which I happened to spot while editing.
Signed-off-by: Ian Campbell i...@hellion.org.uk
Cc: Simon Glass s...@chromium.org
---
common/board_r.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/common/board_r.c b/common/board_r.c
index 602a239..427ee67 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -588,21 +588,19 @@ static int initr_status_led(void)
#if defined(CONFIG_CMD_SCSI)
static int initr_scsi(void)
{
- /* Not supported properly on ARM yet */
-#ifndef CONFIG_ARM
puts(SCSI: );
scsi_init();
-#endif
return 0;
}
-#endif /* CONFIG_CMD_NET */
+#endif
#if defined(CONFIG_CMD_DOC)
static int initr_doc(void)
{
puts(DOC: );
doc_init();
+ return 0
}
#endif
--
2.0.1
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[U-Boot] [PATCH 1/3] AHCI: Increase link timeout to 200ms
In 73545f75b66d ahci: wait longer for link I increased the
timeout to 40ms based on the observed behaviour of a WD disk on a
Cubietruck. Since then Karsten Merker and myself have both
observed timeouts with HGST disks (Karsten on Cubietruck, me on
Cubieboard2). Increasing the timeout to ~175ms fixes this, so go
to 200ms for a bit of headroom.
Signed-off-by: Ian Campbell i...@hellion.org.uk
Cc: Karsten Merker mer...@debian.org
---
drivers/block/ahci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index c8f6573..4df8046 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -41,7 +41,7 @@ u16 *ataid[AHCI_MAX_PORTS];
#define WAIT_MS_SPINUP 2
#define WAIT_MS_DATAIO 5000
#define WAIT_MS_FLUSH 5000
-#define WAIT_MS_LINKUP 40
+#define WAIT_MS_LINKUP 200
static inline u32 ahci_port_base(u32 base, u32 port)
{
--
2.0.1
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[U-Boot] [PATCH 3/3] ahci: provide sunxi SATA driver using AHCI platform framework
This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done
for sun7i only since I don't have access to any other sunxi platforms
with sata included.
The PHY setup is derived from the Alwinner releases and Linux, but is mostly
undocumented.
The Allwinner AHCI controller also requires some magic (and, again,
undocumented) DMA initialisation when starting a port. This is added under a
suitable ifdef.
This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on
contents of Linux DTS files, including SATA power pin config taken from the
DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only.
Signed-off-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/cpu/armv7/sunxi/clock_sun4i.c| 4 ++
arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 11 ++--
board/sunxi/Makefile | 1 +
board/sunxi/ahci.c| 84 +++
boards.cfg| 10 ++--
drivers/block/ahci.c | 16 +
include/ahci.h| 4 ++
include/configs/sunxi-common.h| 12
8 files changed, 133 insertions(+), 9 deletions(-)
create mode 100644 board/sunxi/ahci.c
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index b8b16cf..ecbdb01 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -39,6 +39,10 @@ void clock_init_safe(void)
setbits_le32(ccm-ahb_gate0, 0x1 AHB_GATE_OFFSET_DMA);
#endif
writel(PLL6_CFG_DEFAULT, ccm-pll6_cfg);
+#ifdef CONFIG_SUNXI_AHCI
+ setbits_le32(ccm-ahb_gate0, 0x1 AHB_GATE_OFFSET_SATA);
+ setbits_le32(ccm-pll6_cfg, 0x1 CCM_PLL6_CTRL_SATA_EN_SHIFT);
+#endif
}
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 928f3f2..2531cbd 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -218,10 +218,13 @@ struct sunxi_ccm_reg {
#define CCM_PLL5_CTRL_BYPASS (0x1 30)
#define CCM_PLL5_CTRL_EN (0x1 31)
-#define CCM_PLL6_CTRL_N_SHIFT 8
-#define CCM_PLL6_CTRL_N_MASK (0x1f CCM_PLL6_CTRL_N_SHIFT)
-#define CCM_PLL6_CTRL_K_SHIFT 4
-#define CCM_PLL6_CTRL_K_MASK (0x3 CCM_PLL6_CTRL_K_SHIFT)
+#define CCM_PLL6_CTRL_EN 31
+#define CCM_PLL6_CTRL_BYPASS_EN30
+#define CCM_PLL6_CTRL_SATA_EN_SHIFT14
+#define CCM_PLL6_CTRL_N_SHIFT 8
+#define CCM_PLL6_CTRL_N_MASK (0x1f CCM_PLL6_CTRL_N_SHIFT)
+#define CCM_PLL6_CTRL_K_SHIFT 4
+#define CCM_PLL6_CTRL_K_MASK (0x3 CCM_PLL6_CTRL_K_SHIFT)
#define CCM_GPS_CTRL_RESET (0x1 0)
#define CCM_GPS_CTRL_GATE (0x1 1)
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index 62acb8f..03f55cc 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -10,6 +10,7 @@
#
obj-y += board.o
obj-$(CONFIG_SUNXI_GMAC) += gmac.o
+obj-$(CONFIG_SUNXI_AHCI) += ahci.o
obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o
obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o
obj-$(CONFIG_CUBIEBOARD2) += dram_cubieboard2.o
diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c
new file mode 100644
index 000..0c262ea
--- /dev/null
+++ b/board/sunxi/ahci.c
@@ -0,0 +1,84 @@
+#include common.h
+#include ahci.h
+#include scsi.h
+#include errno.h
+#include asm/io.h
+#include asm/gpio.h
+
+#define AHCI_PHYCS0R 0x00c0
+#define AHCI_PHYCS1R 0x00c4
+#define AHCI_PHYCS2R 0x00c8
+#define AHCI_RWCR0x00fc
+
+/* This magic PHY initialisation was taken from the Allwinner releases
+ * and Linux driver, but is completely undocumented.
+ */
+static int sunxi_ahci_phy_init(u32 base)
+{
+ u8 *reg_base = (u8 *)base;
+ u32 reg_val;
+ int timeout;
+
+ writel(0, reg_base + AHCI_RWCR);
+ mdelay(5);
+
+ setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 19);
+ clrsetbits_le32(reg_base + AHCI_PHYCS0R,
+ (0x7 24),
+ (0x5 24) | (0x1 23) | (0x1 18));
+ clrsetbits_le32(reg_base + AHCI_PHYCS1R,
+ (0x3 16) | (0x1f 8) | (0x3 6),
+ (0x2 16) | (0x6 8) | (0x2 6));
+ setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 28) | (0x1 15));
+ clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 19));
+ clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 20), (0x3 20));
+ clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f 5), (0x19 5));
+ mdelay(5);
+
+ setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 19));
+
+ timeout = 250; /* Power up takes approx 50 us */
+ for (;;) {
+ reg_val = readl(reg_base + AHCI_PHYCS0R) (0x7 28);
+ if (reg_val == (0x2 28))
+ break;
+ if (--timeout == 0) {
+ printf(AHCI PHY power up failed.\n);
+
Re: [U-Boot] Please pull u-boot-sunxi.git/master
On Fri, 18 Jul 2014 20:14:11 +0100 Ian Campbell i...@hellion.org.uk wrote: Hi Albert, Welcome back! The following changes since commit 23f23f23d509e8e873797884456070c8a47d72b2: socfpga: Relocate arch common functions away from board (2014-07-05 10:14:46 +0200) are available in the git repository at: git://git.denx.de/u-boot-sunxi.git master for you to fetch changes up to 7c48b015100eeff0e1bbb766394f7beca23afb48: sunxi: use setbits_le32 to enable the DMA clock (2014-07-18 19:42:25 +0100) Chen-Yu Tsai (1): sunxi: Add support for using MII phy-s with the GMAC nic Hans de Goede (12): sunxi: mksunxiboot: Fix loading of files with a size which is not a multiple of 4 sunxi: Fix u-boot-spl.lds to refer to .vectors sunxi: Remove mmc DMA support sunxi: Implement reset_cpu sunxi: Add sun4i support sunxi: Add sun5i support Can we avoid pushing the sun4i and sun5i patches? They cause clean sunxi dram code rework more difficult. Just to give an example. Here is what we have now in u-boot for the sunxi dram code (a very schematic example): #ifdef SUN7I do_thing_a do_thing_b #endif do_thing_c Here is what is done by the patches from Hans: #ifdef SUN4I do_thing_b do_thing_a #endif #if defined(SUN5I) || defined(SUN7I) do_thing_a do_thing_b #endif do_thing_c And here is what we actually want in the end to support all these SoC variants (with some tweaks and bugfixes for each of these steps): do_thing_a do_thing_b do_thing_c The reordering of the 'do_thing_a' and 'do_thing_b' operations is superfluous. And the fugly resulting ifdef hell does not look like a great improvement, even though the code kinda does the job. Basically, if these patches are pushed, we have a bigger mess to clean compared to what we have now. Also if we have a messy support for sun4, sun5i and sun7i added first, then any future dram code rework needs to keep the dram functional on all of these SoC variant after every patch. This is rather inconvenient. That's why I'm trying to first focus on the sun7i support alone with the patches: http://lists.denx.de/pipermail/u-boot/2014-July/183981.html And add the support for the other SoC variants only after the initial sun7i cleanup is done. Is anyone really in a hurry to get this stuff pushed out of the u-boot-sunxi tree to upstream right now? Can't we get a 'testing' branch in the sunxi repository and have everything reviewed first? -- Best regards, Siarhei Siamashka ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-sunxi.git/master
On Fri, 2014-07-18 at 22:45 +0300, Siarhei Siamashka wrote: Is anyone really in a hurry to get this stuff pushed out of the u-boot-sunxi tree to upstream right now? Can't we get a 'testing' branch in the sunxi repository and have everything reviewed first? This sun4i and sun5i stuff has been on list since the very start of June without any of these concerns being raised, so I hardly think we can be accused of hurry with it or not having given ample opportunity for review. Rebasing over boards.cfg changes dropping and changing boards is really pretty tedious and I've had to do a lot of it lately while preparing this PR so I'm not really very keen to rework it again to drop the sun4i and sun5i stuff. Therefore I'd much prefer if you would rebase the DRAM stuff onto these changes. Sorry. Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 0/2] PSCI backend for sun7i
Hi Albert, This is a followup to my reposting of Marc's PSCI series http://lists.denx.de/pipermail/u-boot/2014-July/183610.html containing more of Marc's patches with the sunxi bits which make use of that new functionality. It is based on those patches. Both sets of patches are also at: git://gitorious.org/ijc/u-boot.git psci-a20-v5 Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 2/2] sunxi: HYP/non-sec: configure CNTFRQ on all CPUs
From: Marc Zyngier marc.zyng...@arm.com CNTFRQ needs to be properly configured on all CPUs. Otherwise, virtual machines hoping to find valuable information on secondary CPUs will be disapointed... Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- include/configs/sun7i.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index 5b5801d..f82431c 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -21,6 +21,7 @@ #define CONFIG_ARMV7_PSCI 1 #define CONFIG_ARMV7_PSCI_NR_CPUS 2 #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE +#define CONFIG_SYS_CLK_FREQ2400 /* * Include common sunxi configuration where most the settings are -- 2.0.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 1/2] sunxi: HYP/non-sec: add sun7i PSCI backend
From: Marc Zyngier marc.zyng...@arm.com So far, only supporting the CPU_ON method. Other functions can be added later. Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- arch/arm/cpu/armv7/sunxi/Makefile | 3 + arch/arm/cpu/armv7/sunxi/psci.S | 162 ++ include/configs/sun7i.h | 6 ++ 3 files changed, 171 insertions(+) create mode 100644 arch/arm/cpu/armv7/sunxi/psci.S diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index a64bfa1..bcc5353 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -15,6 +15,9 @@ obj-$(CONFIG_SUN7I) += clock_sun4i.o ifndef CONFIG_SPL_BUILD obj-y += cpu_info.o +ifdef CONFIG_ARMV7_PSCI +obj-y += psci.o +endif endif ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S new file mode 100644 index 000..0084c81 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/psci.S @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2013 - ARM Ltd + * Author: Marc Zyngier marc.zyng...@arm.com + * + * Based on code by Carl van Schaik c...@ok-labs.com. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#include config.h +#include asm/psci.h +#include asm/arch/cpu.h + +/* + * Memory layout: + * + * SECURE_RAM to text_end : + * ._secure_text section + * text_end to ALIGN_PAGE(text_end): + * nothing + * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000) + * 1kB of stack per CPU (4 CPUs max). + */ + + .pushsection ._secure.text, ax + + .arch_extension sec + +#defineONE_MS (CONFIG_SYS_CLK_FREQ / 1000) +#defineTEN_MS (10 * ONE_MS) + +.macro timer_wait reg, ticks + @ Program CNTP_TVAL + movw\reg, #(\ticks 0x) + movt\reg, #(\ticks 16) + mcr p15, 0, \reg, c14, c2, 0 + isb + @ Enable physical timer, mask interrupt + mov \reg, #3 + mcr p15, 0, \reg, c14, c2, 1 + @ Poll physical timer until ISTATUS is on +1: isb + mrc p15, 0, \reg, c14, c2, 1 + ands\reg, \reg, #4 + bne 1b + @ Disable timer + mov \reg, #0 + mcr p15, 0, \reg, c14, c2, 1 + isb +.endm + +.globl psci_arch_init +psci_arch_init: + mrc p15, 0, r5, c1, c1, 0 @ Read SCR + bic r5, r5, #1 @ Secure mode + mcr p15, 0, r5, c1, c1, 0 @ Write SCR + isb + + mrc p15, 0, r4, c0, c0, 5 @ MPIDR + and r4, r4, #3 @ cpu number in cluster + mov r5, #400@ 1kB of stack per CPU + mul r4, r4, r5 + + adr r5, text_end@ end of text + add r5, r5, #0x2000 @ Skip two pages + lsr r5, r5, #12 @ Align to start of page + lsl r5, r5, #12 + sub sp, r5, r4 @ here's our stack! + + bx lr + + @ r1 = target CPU + @ r2 = target PC +.globl psci_cpu_on +psci_cpu_on: + adr r0, _target_pc + str r2, [r0] + dsb + + movwr0, #(SUNXI_CPUCFG_BASE 0x) + movtr0, #(SUNXI_CPUCFG_BASE 16) + + @ CPU mask + and r1, r1, #3 @ only care about first cluster + mov r4, #1 + lsl r4, r4, r1 + + adr r6, _sunxi_cpu_entry + str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector) + + @ Assert reset on target CPU + mov r6, #0 + lsl r5, r1, #6 @ 64 bytes per CPU + add r5, r5, #0x40 @ Offset from base + add r5, r5, r0 @ CPU control block + str r6, [r5]@ Reset CPU + + @ l1 invalidate + ldr r6, [r0, #0x184] + bic r6, r6, r4 + str r6, [r0, #0x184] + + @ Lock CPU + ldr r6, [r0, #0x1e4] + bic r6, r6, r4 + str r6, [r0, #0x1e4] + + @ Release power clamp + movwr6, #0x1ff + movtr6, #0 +1: lsrsr6, r6, #1 + str r6, [r0, #0x1b0] + bne 1b + + timer_wait r1, TEN_MS + + @ Clear power gating + ldr r6, [r0, #0x1b4] + bic r6, r6, #1 + str r6, [r0, #0x1b4] + + @ Deassert reset on target CPU + mov r6, #3 + str r6, [r5] + + @ Unlock CPU + ldr r6, [r0, #0x1e4] + orr r6, r6, r4
Re: [U-Boot] [PATCH] net: phy/cortina: Add four phy addresses support
On 04/29/2014 07:54 PM, Chunhe Lan wrote: Before CORTINA driver only supports two phy addresses. This patch adds the four phy addresses support for CORTINA PHY module. Signed-off-by: Chunhe Lan chunhe@freescale.com --- drivers/net/phy/cortina.c | 28 ++-- 1 files changed, 22 insertions(+), 6 deletions(-) Chunhe, Does this patch depend on other patches? I don't see cortina.c file. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] net: phy/cortina: Add four phy addresses support
On 07/18/2014 02:12 PM, York Sun wrote: On 04/29/2014 07:54 PM, Chunhe Lan wrote: Before CORTINA driver only supports two phy addresses. This patch adds the four phy addresses support for CORTINA PHY module. Signed-off-by: Chunhe Lan chunhe@freescale.com --- drivers/net/phy/cortina.c | 28 ++-- 1 files changed, 22 insertions(+), 6 deletions(-) Chunhe, Does this patch depend on other patches? I don't see cortina.c file. Looks like you have this patch consolidated into this one http://patchwork.ozlabs.org/patch/350162/. Please confirm so we can drop this. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5] net/phy: Add support for CS4315/CS4340 PHY
On 05/19/2014 01:29 AM, Shengzhou Liu wrote: Add support for Cortina CS4315/CS4340 10G PHY. - This driver loads CS43xx firmware from NOR/NAND/SPI/SD device to initialize Cortina PHY. - Cortina PHY has non-standard offset of PHY ID registers, thus we define own get_phy_id() to override default get_phy_id(). - To define macro CONFIG_PHY_CORTINA will enable this driver. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- v5: fix unclaimed variable in case of nand boot. v4: add support for loading cortina phy ucode from NAND/SPI/SD v3: move devad as '0' in cortina.c instead of in phy.c v2: no change. Joe, Would you take this patch, or ack it so I can take it in? http://patchwork.ozlabs.org/patch/350162/ York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] CPU Wachtog for P2041
Rainer, Would you look into common/board_f.c to see if you can do the same as arch/powerpc/lib/board.c? You know we are steering to use generic board structure. Some boards already made the change. When you do, you will no longer be using arch/powerpc/lib/board.c. York On 07/16/2014 04:20 AM, Boschung, Rainer wrote: Hi, obviously my patches concerning the CPU Watchdog for the kmp204x have not been added to the latest u-boot release. Could you please review my patches and add them for the next release of u-boot. Thanks you. Best regards Rainer Boschung KEYMILE AG -Original Message- From: u-boot-boun...@lists.denx.de [mailto:u-boot- boun...@lists.denx.de] On Behalf Of Rainer Boschung Sent: Tuesday, June 3, 2014 9:05 AM To: u-boot@lists.denx.de Subject: [U-Boot] CPU Wachtog for P2041 I am using the core watchdog of the P2041 on the kmp204x board. For the watchdog initialization I use the mpc85xx framework and the powerpc register definitions. However, I had to modify both for the following reasons (Patches 1 to 4): -the e500mc register implementation differs from other ppc -the watchdog init function was missing Additional function was added to the kmp204x board to use the core WD reset in conjunction with the board specific reset controller (Patches 5 to 9): -trigger a core reset flow upon core WD reset request -check for core WD reset occurance and set the reset reason register accordingly. Regards Rainer ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/9] kmp204x: CPU watchdog enabled
Rainer, Once this patch is enabled, we have warning: implicit declaration of function 'init_85xx_watchdog' [-Wimplicit-function-declaration] Please fix. York On 06/03/2014 12:05 AM, Rainer Boschung wrote: The booting of the board is now protected by the CPU watchdog. A failure during the boot phase will end up in board reset. Signed-off-by: Rainer Boschung rainer.bosch...@keymile.com --- include/configs/km/kmp204x-common.h | 8 1 file changed, 8 insertions(+) diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index efd9635..a0f9d29 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -377,6 +377,14 @@ int get_scl(void); #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ /* + * Hardware Watchdog + */ +#define CONFIG_WATCHDOG /* enable CPU watchdog */ +#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */ +#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ + + +/* * additionnal command line configuration. */ #define CONFIG_CMD_PCI ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/4] Introducing the Broadcom Cygnus and NSP boards.
This series adds the bcm958300k and the bcm958622hr boards which share the iproc architecture code. Scott Branden (4): arm: iproc: Initial commit of iproc architecture code arm: bcmcygnus: Add bcmcygnus u-architecture arm: bcmnsp: Add bcmnsp u-architecture arm: add Cygnus and NSP boards arch/arm/cpu/armv7/Makefile | 1 + arch/arm/cpu/armv7/bcmcygnus/Makefile | 7 + arch/arm/cpu/armv7/bcmcygnus/reset.c| 20 +++ arch/arm/cpu/armv7/bcmnsp/Makefile | 7 + arch/arm/cpu/armv7/bcmnsp/reset.c | 19 +++ arch/arm/cpu/armv7/iproc-common/Makefile| 9 ++ arch/arm/cpu/armv7/iproc-common/armpll.c| 170 arch/arm/cpu/armv7/iproc-common/hwinit-common.c | 16 +++ arch/arm/cpu/armv7/iproc-common/timer.c | 130 ++ arch/arm/include/asm/arch-bcmcygnus/configs.h | 25 arch/arm/include/asm/arch-bcmnsp/configs.h | 22 +++ arch/arm/include/asm/iproc-common/armpll.h | 14 ++ arch/arm/include/asm/iproc-common/configs.h | 20 +++ arch/arm/include/asm/iproc-common/sysmap.h | 47 +++ arch/arm/include/asm/iproc-common/timer.h | 37 ++ board/broadcom/bcm_ep/Makefile | 7 + board/broadcom/bcm_ep/board.c | 62 + boards.cfg | 2 + include/configs/bcm_ep_board.h | 111 19 files changed, 726 insertions(+) create mode 100644 arch/arm/cpu/armv7/bcmcygnus/Makefile create mode 100644 arch/arm/cpu/armv7/bcmcygnus/reset.c create mode 100644 arch/arm/cpu/armv7/bcmnsp/Makefile create mode 100644 arch/arm/cpu/armv7/bcmnsp/reset.c create mode 100644 arch/arm/cpu/armv7/iproc-common/Makefile create mode 100644 arch/arm/cpu/armv7/iproc-common/armpll.c create mode 100644 arch/arm/cpu/armv7/iproc-common/hwinit-common.c create mode 100644 arch/arm/cpu/armv7/iproc-common/timer.c create mode 100644 arch/arm/include/asm/arch-bcmcygnus/configs.h create mode 100644 arch/arm/include/asm/arch-bcmnsp/configs.h create mode 100644 arch/arm/include/asm/iproc-common/armpll.h create mode 100644 arch/arm/include/asm/iproc-common/configs.h create mode 100644 arch/arm/include/asm/iproc-common/sysmap.h create mode 100644 arch/arm/include/asm/iproc-common/timer.h create mode 100644 board/broadcom/bcm_ep/Makefile create mode 100644 board/broadcom/bcm_ep/board.c create mode 100644 include/configs/bcm_ep_board.h -- 1.8.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4] arm: bcmnsp: Add bcmnsp u-architecture
From: Scott Branden sbran...@broadcom.com
Base support for the Broadcom NSP SoC.
Based on iproc-common and the SoC specific reset function.
Signed-off-by: Scott Branden sbran...@broadcom.com
Signed-off-by: Steve Rae s...@broadcom.com
---
arch/arm/cpu/armv7/bcmnsp/Makefile | 7 +++
arch/arm/cpu/armv7/bcmnsp/reset.c | 19 +++
2 files changed, 26 insertions(+)
create mode 100644 arch/arm/cpu/armv7/bcmnsp/Makefile
create mode 100644 arch/arm/cpu/armv7/bcmnsp/reset.c
diff --git a/arch/arm/cpu/armv7/bcmnsp/Makefile
b/arch/arm/cpu/armv7/bcmnsp/Makefile
new file mode 100644
index 000..04afcf9
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcmnsp/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2014 Broadcom Corporation.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += reset.o
diff --git a/arch/arm/cpu/armv7/bcmnsp/reset.c
b/arch/arm/cpu/armv7/bcmnsp/reset.c
new file mode 100644
index 000..d79d9aa
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcmnsp/reset.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+
+#define CRU_RESET_OFFSET 0x1803F184
+
+void reset_cpu(ulong ignored)
+{
+ /* Reset the cpu by setting software reset request bit */
+ writel(0x1, CRU_RESET_OFFSET);
+
+ while (1)
+ ; /* loop forever till reset */
+}
--
1.8.5
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[U-Boot] [PATCH 1/4] arm: iproc: Initial commit of iproc architecture code
From: Scott Branden sbran...@broadcom.com
The iproc architecture code is present in several Broadcom
chip architectures, including Cygnus and NSP.
Signed-off-by: Scott Branden sbran...@broadcom.com
Signed-off-by: Steve Rae s...@broadcom.com
---
arch/arm/cpu/armv7/Makefile | 1 +
arch/arm/cpu/armv7/iproc-common/Makefile| 9 ++
arch/arm/cpu/armv7/iproc-common/armpll.c| 170
arch/arm/cpu/armv7/iproc-common/hwinit-common.c | 16 +++
arch/arm/cpu/armv7/iproc-common/timer.c | 130 ++
arch/arm/include/asm/iproc-common/armpll.h | 14 ++
arch/arm/include/asm/iproc-common/sysmap.h | 47 +++
arch/arm/include/asm/iproc-common/timer.h | 37 ++
8 files changed, 424 insertions(+)
create mode 100644 arch/arm/cpu/armv7/iproc-common/Makefile
create mode 100644 arch/arm/cpu/armv7/iproc-common/armpll.c
create mode 100644 arch/arm/cpu/armv7/iproc-common/hwinit-common.c
create mode 100644 arch/arm/cpu/armv7/iproc-common/timer.c
create mode 100644 arch/arm/include/asm/iproc-common/armpll.h
create mode 100644 arch/arm/include/asm/iproc-common/sysmap.h
create mode 100644 arch/arm/include/asm/iproc-common/timer.h
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 232118d..d0cab8d 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -23,6 +23,7 @@ obj-y += nonsec_virt.o
obj-y += virt-v7.o
endif
+obj-$(CONFIG_IPROC) += iproc-common/
obj-$(CONFIG_KONA) += kona-common/
obj-$(CONFIG_OMAP_COMMON) += omap-common/
obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o
diff --git a/arch/arm/cpu/armv7/iproc-common/Makefile
b/arch/arm/cpu/armv7/iproc-common/Makefile
new file mode 100644
index 000..c071a17
--- /dev/null
+++ b/arch/arm/cpu/armv7/iproc-common/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2014 Broadcom Corporation.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += armpll.o
+obj-y += hwinit-common.o
+obj-y += timer.o
diff --git a/arch/arm/cpu/armv7/iproc-common/armpll.c
b/arch/arm/cpu/armv7/iproc-common/armpll.c
new file mode 100644
index 000..49b61bf
--- /dev/null
+++ b/arch/arm/cpu/armv7/iproc-common/armpll.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/iproc-common/armpll.h
+#include asm/iproc-common/sysmap.h
+
+#define NELEMS(x) (sizeof(x) / sizeof(x[0]))
+
+struct armpll_parameters {
+ unsigned int mode;
+ unsigned int ndiv_int;
+ unsigned int ndiv_frac;
+ unsigned int pdiv;
+ unsigned int freqid;
+};
+
+struct armpll_parameters armpll_clk_tab[] = {
+ { 25, 64, 1, 1, 0},
+ { 100, 64, 1, 1, 2},
+ { 400, 64, 1, 1, 6},
+ { 448, 71, 713050, 1, 6},
+ { 500, 80, 1, 1, 6},
+ { 560, 89, 629145, 1, 6},
+ { 600, 96, 1, 1, 6},
+ { 800, 64, 1, 1, 7},
+ { 896, 71, 713050, 1, 7},
+ { 1000, 80, 1, 1, 7},
+ { 1100, 88, 1, 1, 7},
+ { 1120, 89, 629145, 1, 7},
+ { 1200, 96, 1, 1, 7},
+};
+
+uint32_t armpll_config(uint32_t clkmhz)
+{
+ uint32_t freqid;
+ uint32_t ndiv_frac;
+ uint32_t pll;
+ uint32_t status = 1;
+ uint32_t timeout_countdown;
+ int i;
+
+ for (i = 0; i NELEMS(armpll_clk_tab); i++) {
+ if (armpll_clk_tab[i].mode == clkmhz) {
+ status = 0;
+ break;
+ }
+ }
+
+ if (status) {
+ printf(Error: Clock configuration not supported\n);
+ goto armpll_config_done;
+ }
+
+ /* Enable write access */
+ writel(IPROC_REG_WRITE_ACCESS, IHOST_PROC_CLK_WR_ACCESS);
+
+ if (clkmhz == 25)
+ freqid = 0;
+ else
+ freqid = 2;
+
+ /* Bypass ARM clock and run on sysclk */
+ writel(1 IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE |
+ freqid IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R |
+ freqid IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R |
+ freqid IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R |
+ freqid IHOST_PROC_CLK_POLICY_FREQ__POLICY0_FREQ_R,
+ IHOST_PROC_CLK_POLICY_FREQ);
+
+ writel(1 IHOST_PROC_CLK_POLICY_CTL__GO |
+ 1 IHOST_PROC_CLK_POLICY_CTL__GO_AC,
+ IHOST_PROC_CLK_POLICY_CTL);
+
+ /* Poll CCU until operation complete */
+ timeout_countdown = 0x10;
+ while (readl(IHOST_PROC_CLK_POLICY_CTL)
+ (1 IHOST_PROC_CLK_POLICY_CTL__GO)) {
+ timeout_countdown--;
+ if (timeout_countdown == 0) {
+ printf(CCU polling timedout\n);
+ status = 1;
+ goto armpll_config_done;
+ }
+ }
+
+ if (clkmhz == 25 || clkmhz == 100)
[U-Boot] [PATCH 2/4] arm: bcmcygnus: Add bcmcygnus u-architecture
From: Scott Branden sbran...@broadcom.com
Base support for the Broadcom Cygnus SoC.
Based on iproc-common and the SoC specific reset function.
Signed-off-by: Scott Branden sbran...@broadcom.com
Signed-off-by: Steve Rae s...@broadcom.com
---
arch/arm/cpu/armv7/bcmcygnus/Makefile | 7 +++
arch/arm/cpu/armv7/bcmcygnus/reset.c | 20
2 files changed, 27 insertions(+)
create mode 100644 arch/arm/cpu/armv7/bcmcygnus/Makefile
create mode 100644 arch/arm/cpu/armv7/bcmcygnus/reset.c
diff --git a/arch/arm/cpu/armv7/bcmcygnus/Makefile
b/arch/arm/cpu/armv7/bcmcygnus/Makefile
new file mode 100644
index 000..04afcf9
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcmcygnus/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2014 Broadcom Corporation.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += reset.o
diff --git a/arch/arm/cpu/armv7/bcmcygnus/reset.c
b/arch/arm/cpu/armv7/bcmcygnus/reset.c
new file mode 100644
index 000..53ecc0c
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcmcygnus/reset.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+
+#define CRMU_MAIL_BOX1 0x03024028
+#define CRMU_SOFT_RESET_CMD0x
+
+void reset_cpu(ulong ignored)
+{
+ /* Send soft reset command via Mailbox. */
+ writel(CRMU_SOFT_RESET_CMD, CRMU_MAIL_BOX1);
+
+ while (1)
+ ; /* loop forever till reset */
+}
--
1.8.5
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[U-Boot] [PATCH 4/4] arm: add Cygnus and NSP boards
From: Scott Branden sbran...@broadcom.com
The bcm_ep board configuration is used by a number of boards
including Cygnus and NSP.
Add builds for the bcm958300k and the bcm958622hr boards.
Signed-off-by: Scott Branden sbran...@broadcom.com
Signed-off-by: Steve Rae s...@broadcom.com
---
arch/arm/include/asm/arch-bcmcygnus/configs.h | 25 ++
arch/arm/include/asm/arch-bcmnsp/configs.h| 22 +
arch/arm/include/asm/iproc-common/configs.h | 20 +
board/broadcom/bcm_ep/Makefile| 7 ++
board/broadcom/bcm_ep/board.c | 62 ++
boards.cfg| 2 +
include/configs/bcm_ep_board.h| 111 ++
7 files changed, 249 insertions(+)
create mode 100644 arch/arm/include/asm/arch-bcmcygnus/configs.h
create mode 100644 arch/arm/include/asm/arch-bcmnsp/configs.h
create mode 100644 arch/arm/include/asm/iproc-common/configs.h
create mode 100644 board/broadcom/bcm_ep/Makefile
create mode 100644 board/broadcom/bcm_ep/board.c
create mode 100644 include/configs/bcm_ep_board.h
diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h
b/arch/arm/include/asm/arch-bcmcygnus/configs.h
new file mode 100644
index 000..5354637
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ARCH_CONFIGS_H
+#define __ARCH_CONFIGS_H
+
+#include asm/iproc-common/configs.h
+
+/* uArchitecture specifics */
+
+/* Serial Info */
+/* Post pad 3 bytes after each reg addr */
+#define CONFIG_SYS_NS16550_REG_SIZE(-4)
+#define CONFIG_SYS_NS16550_MEM32
+
+#define CONFIG_SYS_NS16550_CLK 1
+#define CONFIG_SYS_NS16550_CLK_DIV 54
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM30x18023000
+
+#endif /* __ARCH_CONFIGS_H */
diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h
b/arch/arm/include/asm/arch-bcmnsp/configs.h
new file mode 100644
index 000..786deae
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcmnsp/configs.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ARCH_CONFIGS_H
+#define __ARCH_CONFIGS_H
+
+#include asm/iproc-common/configs.h
+
+/* uArchitecture specifics */
+
+/* Serial Info */
+/* no padding */
+#define CONFIG_SYS_NS16550_REG_SIZE1
+
+#define CONFIG_SYS_NS16550_CLK 0x03b9aca0
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_COM10x18000300
+
+#endif /* __ARCH_CONFIGS_H */
diff --git a/arch/arm/include/asm/iproc-common/configs.h
b/arch/arm/include/asm/iproc-common/configs.h
new file mode 100644
index 000..c24de1f
--- /dev/null
+++ b/arch/arm/include/asm/iproc-common/configs.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __IPROC_COMMON_CONFIGS_H
+#define __IPROC_COMMON_CONFIGS_H
+
+#include linux/stringify.h
+
+/* Architecture, CPU, chip, etc */
+#define CONFIG_IPROC
+#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+
+/* Memory Info */
+#define CONFIG_SYS_TEXT_BASE 0x6100
+#define CONFIG_SYS_SDRAM_BASE 0x6100
+
+#endif /* __IPROC_COMMON_CONFIGS_H */
diff --git a/board/broadcom/bcm_ep/Makefile b/board/broadcom/bcm_ep/Makefile
new file mode 100644
index 000..8914e54
--- /dev/null
+++ b/board/broadcom/bcm_ep/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2014 Broadcom Corporation.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += board.o
diff --git a/board/broadcom/bcm_ep/board.c b/board/broadcom/bcm_ep/board.c
new file mode 100644
index 000..df17f72
--- /dev/null
+++ b/board/broadcom/bcm_ep/board.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include config.h
+#include asm/system.h
+#include asm/iproc-common/armpll.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * board_init - early hardware init
+ */
+int board_init(void)
+{
+ /* Address of boot parameters passed to kernel
+* Use default offset 0x100
+*/
+ gd-bd-bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+/*
+ * misc_init_r - miscellaneous platform dependent initializations
+ */
+int misc_init_r(void)
+{
+ return 0;
+}
+
+/*
+ * dram_init - sets u-boot's idea of sdram size
+ */
+int dram_init(void)
+{
+ gd-ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd-bd-bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd-bd-bi_dram[0].size = gd-ram_size;
+}
+
+int board_early_init_f(void)
+{
+ uint32_t status = 0;
+
+ /* Setup PLL if required */
+#if defined(CONFIG_ARMCLK)
+
Re: [U-Boot] [PATCH 2/3] board_r: run scsi init() on ARM too
Hi Ian, On 18 July 2014 13:38, Ian Campbell i...@hellion.org.uk wrote: This has been disabled for ARM in initr_scsi since that function was introduced. However it works fine for me on Cubieboard and Cubietruck (with the upcoming AHCI glue patch). I also tested on two random ARM platforms which seem to define CONFIG_CMD_SCSI: - highbank worked fine (on midway hardware) - omap5_uevm built OK and I confirmed using objdump that things were as expected (i.e. the default weak scsi_init nop was used). While there remove the mismatched comment from the #endif (omitting the comment seems to be the prevailing style in this file) and add a missing return to initr_doc which I happened to spot while editing. That's great, but I think the latter should be a separate patch. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 17/29] dm: Introduce device sequence numbering
Hi Jon,
On 9 July 2014 07:53, Jon Loeliger loeli...@gmail.com wrote:
HI Simon,
On Tue, Jul 8, 2014 at 10:38 PM, Simon Glass s...@chromium.org wrote:
In U-Boot it is pretty common to number devices from 0 and access them
on the command line using this numbering. While it may come to pass that
we will move away from this numbering, the possibility seems remote at
present.
Given that devices within a uclass will have an implied numbering, it
makes sense to build this into driver model as a core feature. The cost
is fairly small in terms of code and data space.
Hmmm. I'm not entirely in agreement here. I think this is the wrong
long-term approach, and this just reinforces the status quo rather than
allowing a migration to a better approach.
If we don't add numbering to driver model, then it will be done badly
(and ad-hoc) in support code. I can't even quite imagine how we might
do it. Also while U-Boot's numbering may not be the right long-term
approach, that would involve a large discussion and long change-over
to an as-yet unknown method. So I think we need to have realistic
expectations of driver mode's place in the world. It can enable new
methods, but not mandate them.
With each uclass having numbered devices we can ask for SPI port 0 or
serial port 1 and receive a single device.
That's nice, but we should allow them to be named by their actual
names as found in the device tree too.
There's nothing in this patch that precludes that. It would require
changes to U-Boot's command processing, probably best done as a
separate series sometime in the future.
Devices typically request a sequence number using aliases in the device
tree. These are resolved when the device is probed, to deal with conflicts.
Sequence numbers need not be sequential and holes are permitted.
So they are unreliably unpredictable, unless you also happen
to have the DTS decoder ring in hand too?
If you compare with how things are now, we only support a single
driver for each class. For example, if you are using SPI, you can only
have one SPI driver - perhaps with multiple ports. If you are not
using DT, then the U_BOOT_DEVICE() macros will all appear in that
driver or the board file (TBD at this stage), and will be parsed in
order. I believe we can honour the numbering in that case, albeit I
don't want to implement something before it is needed.
+This indicates that in the uclass called serial, the named node
+(/serial@2223) will be given sequence number 2. Any command or driver
+which requests serial device 2 will obtain this device.
+
+Some devices represent buses where the devices on the bus are numbered or
+addressed. For example, SPI typically numbers its slaves from 0, and I2C
+uses a 7-bit address. In these cases the 'reg' property of the subnode is
+used, for example:
+
+{
+ aliases {
+ spi2 = /spi@2230;
+ };
+
+ spi@2230 {
+ #address-cells = 1;
+ #size-cells = 1;
+ spi-flash@0 {
+ reg = 0;
+ ...
+ }
+ eeprom@1 {
+ reg = 1;
+ };
+ };
And not everyone agrees that this is the best approach, even in Linux land.
Specifically, we should be in agreement with Linux, and we should not
have our DTS stray from the definitions that Linux will accept for the same
devices. And this approach won't be bought by the Linux crowd. (Yes,
there are some that use a reg = 0; approach here, but there are many
that do not too. It's not a universally accepted approach.)
This concept is crucial.
I've said it before, and I will say it again if needed.
So: Sure, put this approach in, but make it be the backward compatible
approach. Also please put in a correct naming approach so that we can
move forward with a better longer term solution too.
I think you are saying that something like:
sf probe spi1:flash
should be possible instead of
sf probe 1:0
It feels right to me too, but it doesn't belong in this patch, needs
further discussion and the command parsing aspect needs more general
thought. It would be great to figure this out and get it agreed, and
driver model can certainly support it.
Regards,
Simon
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Re: [U-Boot] [PATCH v3] Implement generalised RSA public exponents for verified boot
Hi Michael,
On 2 July 2014 02:17, mich...@smart-africa.com wrote:
From: Michael van der Westhuizen mich...@smart-africa.com
Remove the verified boot limitation that only allows a single
RSA public exponent of 65537 (F4). This change allows use with
existing PKI infrastructure and has been tested with HSM-based
PKI.
Change the configuration OF tree format to store the RSA public
exponent as a 64 bit integer and implement backward compatibility
for verified boot configuration trees without this extra field.
Parameterise vboot_test.sh to test different public exponents.
Mathematics and other hard work by Andrew Bott.
Sorry, I still have a few nits on this, but it looks good.
Tested with the following public exponents: 3, 5, 17, 257, 39981,
50457, 65537 and 4294967297.
Signed-off-by: Andrew Bott andrew.b...@ipaccess.com
Signed-off-by: Andrew Wishart andrew.wish...@ipaccess.com
Signed-off-by: Neil Piercy neil.pie...@ipaccess.com
Signed-off-by: Michael van der Westhuizen mich...@smart-africa.com
Cc: Simon Glass s...@chromium.org
---
Changes for v2:
- None. Resend to address line wrapping issues.
Changes for v3:
- Address review comments, cleaning up variable names and
rewording error messages.
- Rebase against current master.
- Apply as many suggested simplifications as feasible.
doc/uImage.FIT/signature.txt | 4 +-
include/u-boot/rsa.h | 1 +
lib/rsa/rsa-sign.c | 60 ++--
lib/rsa/rsa-verify.c | 93
+---
test/vboot/vboot_test.sh | 10 -
5 files changed, 158 insertions(+), 10 deletions(-)
diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt
index a6ab543..b2f89fc 100644
--- a/doc/uImage.FIT/signature.txt
+++ b/doc/uImage.FIT/signature.txt
@@ -66,7 +66,8 @@ Creating an RSA key and certificate
---
To create a new public key, size 2048 bits:
-$ openssl genrsa -F4 -out keys/dev.key 2048
+$ openssl genpkey -algorithm RSA -out keys/dev.key \
+-pkeyopt rsa_keygen_bits:2048 -pkeyopt rsa_keygen_pubexp:65537
To create a certificate for this:
@@ -159,6 +160,7 @@ For RSA the following are mandatory:
- rsa,num-bits: Number of key bits (e.g. 2048)
- rsa,modulus: Modulus (N) as a big-endian multi-word integer
+- rsa,exponent: Public exponent (E) as a 64 bit unsigned integer
This is listed as mandatory, but the code makes it options. I think it
should probably be optional, and documented that way here.
- rsa,r-squared: (2^num-bits)^2 as a big-endian multi-word integer
- rsa,n0-inverse: -1 / modulus[0] mod 2^32
diff --git a/include/u-boot/rsa.h b/include/u-boot/rsa.h
index 325751a..fd08a61 100644
--- a/include/u-boot/rsa.h
+++ b/include/u-boot/rsa.h
@@ -27,6 +27,7 @@ struct rsa_public_key {
uint32_t n0inv; /* -1 / modulus[0] mod 2^32 */
uint32_t *modulus; /* modulus as little endian array */
uint32_t *rr; /* R^2 as little endian array */
+ uint64_t exponent; /* public exponent */
};
#if IMAGE_ENABLE_SIGN
diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c
index 83f5e87..f4d4338 100644
--- a/lib/rsa/rsa-sign.c
+++ b/lib/rsa/rsa-sign.c
@@ -261,10 +261,57 @@ err_priv:
}
/*
+ * rsa_get_exponent(): - Get the public exponent from an RSA key
+ */
+static int rsa_get_exponent(RSA *key, uint64_t *e)
+{
+ int ret;
+ BIGNUM *bn_te;
+ uint64_t te;
+
+ ret = -EINVAL;
+ bn_te = NULL;
+
+ if (!e)
+ goto cleanup;
+
+ if (BN_num_bits(key-e) 64)
+ goto cleanup;
+
+ *e = BN_get_word(key-e);
+
+ if (BN_num_bits(key-e) 33) {
+ ret = 0;
+ goto cleanup;
+ }
+
+ bn_te = BN_dup(key-e);
+ if (!bn_te)
+ goto cleanup;
+
+ if (!BN_rshift(bn_te, bn_te, 32))
+ goto cleanup;
+
+ if (!BN_mask_bits(bn_te, 32))
+ goto cleanup;
+
+ te = BN_get_word(bn_te);
+ te = 32;
+ *e |= te;
+ ret = 0;
+
+cleanup:
+ if (bn_te)
+ BN_free(bn_te);
+
+ return ret;
+}
+
+/*
* rsa_get_params(): - Get the important parameters of an RSA public key
*/
-int rsa_get_params(RSA *key, uint32_t *n0_invp, BIGNUM **modulusp,
- BIGNUM **r_squaredp)
+int rsa_get_params(RSA *key, uint64_t *exponent, uint32_t *n0_invp,
+ BIGNUM **modulusp, BIGNUM **r_squaredp)
To be consistent, can we use exponentp as the parameter name? It makes
it clear it is a pointer.
{
BIGNUM *big1, *big2, *big32, *big2_32;
BIGNUM *n, *r, *r_squared, *tmp;
@@ -286,6 +333,9 @@ int rsa_get_params(RSA *key, uint32_t *n0_invp, BIGNUM
**modulusp,
return -ENOMEM;
}
+ if (0 != rsa_get_exponent(key, exponent))
+
Re: [U-Boot] [PATCH 1/2] spi: ST33ZP24 SPI TPM driver
Hi Jean-Luc,
On 8 July 2014 16:05, Jean-Luc BLANC stmicroelectronics@gmail.com wrote:
This driver add support for STMicroelectronics ST33ZP24 SPI TPM.
s/add/adds/
Driver support 2 SPI TPMs.
Driver support also hash in Locality 4 feature (the only way to
On both lines s/support/supports/
update PCR17).
---
README | 29 ++
common/cmd_tpm.c | 63 +++-
drivers/tpm/Makefile |1 +
drivers/tpm/tpm_spi_stm_st33.c | 724
include/tis.h | 11 +-
include/tpm.h | 22 ++
lib/tpm.c | 26 ++
7 files changed, 874 insertions(+), 2 deletions(-)
create mode 100644 drivers/tpm/tpm_spi_stm_st33.c
diff --git a/README b/README
index a248ab5..a4aa28a 100644
--- a/README
+++ b/README
@@ -1397,6 +1397,35 @@ The following options need to be configured:
Define this to enable authorized functions in the TPM library.
Requires CONFIG_TPM and CONFIG_SHA1.
+ CONFIG_TPM_ST
+ Support additional hash in locality 4 command for
+ STMicroelectronics TPMs (SPI or I2C). Require CONFIG_CMD_TPM.
+
+ CONFIG_TPM_ST_SPI
+ Support SPI STMicroelectronics TPM. Require SPI support
s/Require/Requires/
+
+ TPM0_SPI_MAX_SPEED
+ Define SPI frequency for TPM, 1000 Hz max
+
+ TPM0_SPI_BUS_NUM
+ Define SPI Bus ID connected to TPM
+
+ TPM0_SPI_CS
+ Define SPI Chip Select ID connected to TPM
+
+ CONFIG_TPM_ST_2TPM
+ Support additional STMicoelectronics SPI TPM.
+ Require CONFIG_TPM_ST_SPI
+
+ TPM1_SPI_MAX_SPEED
+ Define SPI frequency for TPM, 1000 Hz max
+
+ TPM1_SPI_BUS_NUM
+ Define SPI Bus ID connected to TPM
+
+ TPM1_SPI_CS
+ Define SPI Chip Select ID connected to TPM
Not essential, but it would be nice to support CONFIG_OF_CONTROL and
get these parameters from the device tree, as other TPM drivers do.
+
- USB Support:
At the moment only the UHCI host controller is
supported (PIP405, MIP405, MPC5200); define
diff --git a/common/cmd_tpm.c b/common/cmd_tpm.c
index 0294952..63f52e4 100644
--- a/common/cmd_tpm.c
+++ b/common/cmd_tpm.c
@@ -334,6 +334,29 @@ static int do_tpm_extend(cmd_tbl_t *cmdtp, int flag,
return convert_return_code(rc);
}
+#ifdef CONFIG_TPM_ST
Is this a feature only supported by ST, in which case this code is
correct, or is it a standard feature that other chips may support, in
which case you should add a new CONFIG like CONFIG_TPM_HASH_LOC4?
+static int do_tpm_hash_loc4(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ uint32_t rc;
+ size_t count;
+ void *data;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ data = parse_byte_string(argv[1], NULL, count);
+ if (!data) {
+ printf(Couldn't parse byte string %s\n, argv[1]);
Can we move this error into the parse_byte_string() to avoid repeating it?
+ return CMD_RET_FAILURE;
+ }
+
+ rc = tpm_hash_loc4(data, count);
+ free(data);
+ return convert_return_code(rc);
+}
+#endif /* CONFIG_TPM_ST */
+
static int do_tpm_pcr_read(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
@@ -355,6 +378,25 @@ static int do_tpm_pcr_read(cmd_tbl_t *cmdtp, int flag,
return convert_return_code(rc);
}
+#ifdef CONFIG_TPM_ST_2TPM
+static int do_tpm_spi_select(cmd_tbl_t *cmdtp, int flag,
+int argc, char * const argv[])
+{
+ uint32_t rc, spi_number;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+ spi_number = simple_strtoul(argv[1], NULL, 0);
+ if (spi_number CONFIG_TPM_ST_2TPM) {
+ rc = tpm_spi_select(spi_number);
+ } else {
+ printf(Couldn't parse argument %s\n, argv[1]);
+ return CMD_RET_FAILURE;
+ }
+ return convert_return_code(rc);
+}
+#endif /* CONFIG_TPM_ST_2TPM */
This seems quite specific to SPI. Why not have a 'tpm number' and have
it wholly kept in this file? It looks like the tpm.h file should be
changed to add a TPM number to each call? If so, that should be a
separate patch. This is what the 'i2c dev' command does. See how SPI
FLASH works for another example (sf probe command).
+
static int do_tpm_tsc_physical_presence(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
@@ -629,8 +671,16 @@ static cmd_tbl_t tpm_commands[] = {
Re: [U-Boot] [PATCH 2/2] i2c: ST33ZP24 I2C TPM driver
Hi Jean-Luc,
On 9 July 2014 01:40, Jean-Luc BLANC stmicroelectronics@gmail.com wrote:
This driver add support for STMicroelectronics ST33ZP24 I2C TPM.
---
README |6 +
drivers/tpm/Makefile |1 +
drivers/tpm/tpm_i2c_stm_st33.c | 633
3 files changed, 640 insertions(+)
create mode 100644 drivers/tpm/tpm_i2c_stm_st33.c
diff --git a/README b/README
index a4aa28a..c4463d8 100644
--- a/README
+++ b/README
@@ -1426,6 +1426,12 @@ The following options need to be configured:
TPM1_SPI_CS
Define SPI Chip Select ID connected to TPM
+ CONFIG_TPM_ST_I2C
+ Support I2C STMicroelectronics TPM. Require I2C support
+
+ CONFIG_TPM_I2C_BUS
+ Define the i2c bus number for the TPM device
+
- USB Support:
At the moment only the UHCI host controller is
supported (PIP405, MIP405, MPC5200); define
diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile
index 1ee707e..29e1f80 100644
--- a/drivers/tpm/Makefile
+++ b/drivers/tpm/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_TPM_TIS_I2C) += tpm_tis_i2c.o
obj-$(CONFIG_TPM_TIS_LPC) += tpm_tis_lpc.o
obj-$(CONFIG_TPM_TIS_SANDBOX) += tpm_tis_sandbox.o
obj-$(CONFIG_TPM_ST_SPI) += tpm_spi_stm_st33.o
+obj-$(CONFIG_TPM_ST_I2C) += tpm_i2c_stm_st33.o
diff --git a/drivers/tpm/tpm_i2c_stm_st33.c b/drivers/tpm/tpm_i2c_stm_st33.c
new file mode 100644
index 000..6e20f8c
--- /dev/null
+++ b/drivers/tpm/tpm_i2c_stm_st33.c
@@ -0,0 +1,633 @@
+/*
+ * STMicroelectronics TPM I2C UBOOT Linux driver for TPM ST33ZP24
+ * Copyright (C) 2014 STMicroelectronics
+ *
+ * Description: Device driver for ST33ZP24 I2C TPM TCG.
+ *
+ * This device driver implements the TPM interface as defined in
+ * the TCG TPM Interface Spec version 1.21, revision 1.0 and the
+ * STMicroelectronics I2C Protocol Stack Specification version 1.2.0.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * @Author: Jean-Luc BLANC jean-luc.bl...@st.com
+ *
+ * @File: tpm_i2c_stm_st33.c
+ */
+
+#include common.h
+#include i2c.h
+#include linux/types.h
+#include tpm.h
+#include errno.h
+#include asm/unaligned.h
+
+#define MINOR_NUM_I2C 224
+
+#define TPM_ACCESS 0x0
+#define TPM_STS0x18
+#define TPM_HASH_END 0x20
+#define TPM_DATA_FIFO 0x24
+#define TPM_HASH_DATA 0x24
+#define TPM_HASH_START 0x28
+#define TPM_INTF_CAPABILITY0x14
+#define TPM_INT_STATUS 0x10
+#define TPM_INT_ENABLE 0x08
+
+#define TPM_DUMMY_BYTE 0xAA
+#define TPM_WRITE_DIRECTION0x80
+#define TPM_HEADER_SIZE10
+#define TPM_BUFSIZE2048
+
+#define LOCALITY0 0
+#define LOCALITY4 4
+#define LOCALITY0_I2C_ADDR 0x13
+#define LOCALITY4_I2C_ADDR 0x1B
If the chips have a lot of common defines / functions, please put them
in a common header file/interface. Duplicated code creates problems
for refactoring later.
+
+/* Index of Count field in TPM response buffer */
+#define TPM_RSP_SIZE_BYTE 2
+
+/* Maximum command duration */
+#define TPM_MAX_COMMAND_DURATION_MS12
+
+enum stm33zp24_access {
+ TPM_ACCESS_VALID = 0x80,
+ TPM_ACCESS_ACTIVE_LOCALITY = 0x20,
+ TPM_ACCESS_REQUEST_PENDING = 0x04,
+ TPM_ACCESS_REQUEST_USE = 0x02,
+};
+
+enum stm33zp24_status {
+ TPM_STS_VALID = 0x80,
+ TPM_STS_COMMAND_READY = 0x40,
+ TPM_STS_GO = 0x20,
+ TPM_STS_DATA_AVAIL = 0x10,
+ TPM_STS_DATA_EXPECT = 0x08,
+};
+
+enum stm33zp24_int_flags {
+ TPM_GLOBAL_INT_ENABLE = 0x80,
+ TPM_INTF_CMD_READY_INT = 0x080,
+ TPM_INTF_FIFO_AVALAIBLE_INT = 0x040,
+ TPM_INTF_WAKE_UP_READY_INT = 0x020,
+ TPM_INTF_LOCTPM_BUFSIZE4SOFTRELEASE_INT = 0x008,
+ TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
+ TPM_INTF_STS_VALID_INT = 0x002,
+ TPM_INTF_DATA_AVAIL_INT = 0x001,
+};
+
+enum tis_defaults {
+ TIS_SHORT_TIMEOUT_MS = 750, /* ms */
+ TIS_LONG_TIMEOUT_MS = 2000, /* 2 sec */
+};
+
+/**
+ * @addr: TPM I2C address
+ * @i2c_bus: I2C bus ID the TPM is connected to
+ * @is_open: TPM connection establishment information
+ * @locality: active locality of the TPM (0 OR 4)
+ * @buf: command/response buffer
+ * @timeout_*: timeouts for TPM states changes
+ * @duration: maximum time for a TPM command processing
+ */
+struct tpm_chip {
+ uint addr;
+ uint i2c_bus;
+ int is_open;
+ u8 buf[TPM_BUFSIZE];
+ int locality;
+ unsigned long timeout_a, timeout_b, timeout_c, timeout_d; /* msec */
Re: [U-Boot] WIP for SPI
Hi Jon, On 11 June 2014 08:33, Jon Loeliger loeli...@gmail.com wrote: On Tue, Jun 10, 2014 at 10:54 PM, Simon Glass s...@chromium.org wrote: Hi Jon, I thought I should mention that I spent time on a flight to look at SPI with driver model. I have put the WIP code in branch 'working' in u-boot-dm.git. Note it doesn't work, and is very early. Also note that many of the patches have not been posted - I just want to make it clear what I am up to. Awesome! In doing this I had to sort out the numbering of devices. U-Boot has the concept of SPI bus 2 on its command line, and for now at lest we need to keep that working. So I have added sequence numbers to devices - so a device can be considered 'child number 3' of its parent, for example. The numbers don't need to be sequential. I suppose we could generalise this to GPIOs if it works out. And I think I am saying that we already *have* it generalized for the GPIOs but only if we remove that renumbering function! Consider again that the U_CLASS lookup of a GPIO simply matches versus the range in each uclass data (gpio base and count). That search doesn't care about their order within the UCLASS_GPIO list. (Never mind that the renumbering breaks the association of the device base register and pin ranges as set up by the bind/probe code!) I wonder if we could do something similar then, where there is a default numbering if none is provided, but the GPIO devices are able to 'request' particular number ranges? My approach for scanning the SPI bus in the device tree is similar to what I suggested a week or so ago - I took the code from dm_scan_fdt() and put it in a function with a udevice parent and node parameters. It seems to work OK for this simple case. Nice! Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] patman: make No recipient checking more tolerant
On 17 July 2014 23:23, Masahiro Yamada yamad...@jp.panasonic.com wrote: If Series-to tag is missing, Patman exits with a message No recipient. This is just annoying for those who had already added sendemail.to configuration. I guess many developers have [sendemail] to = u-boot@lists.denx.de in their .git/config because the 'To: u-boot@lists.denx.de' field should always be added when sending patches. That seems more reasonable rather than adding 'Series-to: u-boot@lists.denx.de' to every patch series. Patman should exit only when both Series-to tag and sendemail.to configuration are mising. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Cc: Simon Glass s...@chromium.org Acked-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] buildman: make sure to invoke GNU Make
On 17 July 2014 03:18, Masahiro Yamada yamad...@jp.panasonic.com wrote: Since the command name 'make' is not GNU Make on some platforms such as FreeBSD, MAKEALL should call the make via scripts/gnu_make. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Maybe you will rename the script, but the code looks good. Acked-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] MAKEALL: make sure to invoke GNU Make
Hi Jeroen,
On 18 July 2014 12:29, Jeroen Hofstee dasub...@myspectrum.nl wrote:
Hello Masahiro,
On 17-07-14 11:18, Masahiro Yamada wrote:
Since the command name 'make' is not GNU Make on some platforms
such as FreeBSD, MAKEALL should call the make via scripts/gnu_make.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
MAKEALL | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/MAKEALL b/MAKEALL
index 37ef71e..02c2f9f 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -630,14 +630,16 @@ build_target() {
output_dir=${OUTPUT_PREFIX}
fi
+ GNU_MAKE=scripts/gnu_make
+
target_arch=$(get_target_arch ${target})
eval cross_toolchain=\$CROSS_COMPILE_`echo $target_arch | tr
'[:lower:]' '[:upper:]'`
if [ ${cross_toolchain} ] ; then
- MAKE=make CROSS_COMPILE=${cross_toolchain}
+ MAKE=$GNU_MAKE CROSS_COMPILE=${cross_toolchain}
elif [ ${CROSS_COMPILE} ] ; then
- MAKE=make CROSS_COMPILE=${CROSS_COMPILE}
+ MAKE=$GNU_MAKE CROSS_COMPILE=${CROSS_COMPILE}
else
- MAKE=make
+ MAKE=$GNU_MAKE
fi
if [ ${output_dir} != . ] ; then
while by itself this might be correct, opt is not a POSIX command
and MAKEALL will not work at all on a BSD host. Perhaps it is
time I have a look at what buildman is
http://patchwork.ozlabs.org/patch/369788/
:-)
Regards,
Simon
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