date:20150309

These options relate to the sandbox drivers and also sound. There are still
more options to move, but this is a start.


Simon Glass (14):
  sandbox: Move GPIO CONFIGs to Kconfig
  sandbox: Move CONFIG_SYS_VSNPRINTF to Kconfig
  sandbox: Move CONFIG_SANDBOX_SERIAL to Kconfig
  sandbox: Move CONFIG_SYS_I2C_SANDBOX to Kconfig
  sandbox: Move CONFIG_SANDBOX_SPI to Kconfig
  sandbox: Move CONFIG_SPI_FLASH_SANDBOX to Kconfig
  sandbox: Move CONFIG_TPM_TIS_SANDBOX to Kconfig
  sandbox: exynos: Move CONFIG_SOUND to Kconfig
  sandbox: exynos: Move CONFIG_CMD_SOUND to Kconfig
  sandbox: exynos: Move CONFIG_I2S to Kconfig
  sandbox: exynos: Move CONFIG_I2S_SAMSUNG to Kconfig
  sandbox: exynos: Move CONFIG_SOUND_MAX98095 to Kconfig
  sandbox: exynos: Move CONFIG_SOUND_WM8994 to Kconfig
  sandbox: exynos: Move CONFIG_SOUND_SANDBOX to Kconfig

 arch/x86/Kconfig|  3 ++
 common/Kconfig  | 10 +++
 configs/arndale_defconfig   |  5 
 configs/sandbox_defconfig   | 10 +++
 configs/smdk5250_defconfig  |  5 
 configs/snow_defconfig  |  5 
 drivers/gpio/Kconfig| 21 ++
 drivers/i2c/Kconfig | 30 
 drivers/mtd/spi/Kconfig | 10 +++
 drivers/serial/Kconfig  | 20 ++
 drivers/serial/serial-uclass.c  |  5 ++--
 drivers/sound/Kconfig   | 55 +
 drivers/spi/Kconfig | 25 +
 drivers/tpm/Kconfig |  7 +
 include/configs/exynos5250-common.h | 10 ---
 include/configs/sandbox.h   | 16 ---
 include/configs/x86-common.h|  1 -
 include/fdtdec.h|  6 
 lib/Kconfig |  9 ++
 19 files changed, 224 insertions(+), 29 deletions(-)

-- 
2.2.0.rc0.207.ga3a616c

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Re: [U-Boot] [PATCH v6 3/6] dm: tegra: Enable driver model in SPL and adjust the GPIO driver

On 03/04/2015 03:16 PM, Tom Rini wrote:
 On Tue, Mar 03, 2015 at 08:02:59AM -0700, Simon Glass wrote:
 
 Use the full driver model GPIO and serial drivers in SPL now that
 these are supported. Since device tree is not available they will
 use platform data.
 
 Remove the special SPL GPIO function as it is no longer needed.
 
 This is all in one commit to maintain bisectability.
 
 Signed-off-by: Simon Glass s...@chromium.org
 
 Applied to u-boot/master, thanks!

This patch breaks the serial console on at least NVIDIA Tegra
Seaboard. LCD/usbkbd still work though. I can't test any other Tegra
boards right now since I'm not at work. I wonder if the UART/SPI GPIO
is at issue? That would be specific to this board.

(I just happened to test with that board while investigating why
usbkbd was not working right on the RPi, since Seaboard has usbkbd
support... Yay nested bugs!)
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[U-Boot] [PATCH] powerpc/t2080: enable erratum_a007186 for t2080 rev1.1

2015-03-09 Thread Shengzhou Liu

T2080 rev1.1 also needs erratum a007186.

Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
 arch/powerpc/include/asm/fsl_errata.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/include/asm/fsl_errata.h 
b/arch/powerpc/include/asm/fsl_errata.h
index 61c6d70..4861e3bf 100644
--- a/arch/powerpc/include/asm/fsl_errata.h
+++ b/arch/powerpc/include/asm/fsl_errata.h
@@ -45,7 +45,7 @@ static inline bool has_erratum_a007186(void)
return IS_SVR_REV(svr, 2, 0);
case SVR_T2081:
case SVR_T2080:
-   return IS_SVR_REV(svr, 1, 0);
+   return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
}
 
return false;
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH 1/5] usb: dwc2: unify waiting for transfer completion

2015-03-09 Thread Marek Vasut

On Sunday, March 08, 2015 at 06:48:51 AM, Stephen Warren wrote:
 Lift common code out of submit_bulk_msg() and submit_control_msg().
 
 Signed-off-by: Stephen Warren swar...@wwwdotorg.org

Applied to u-boot-usb/topic/dwc2, thanks. I would like to see more
testing from others if possible, otherwise this will go in after
2015.04 if you're fine with that.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH V2 1/2] usb: dwc2: fix aligned buffer usage

2015-03-09 Thread Marek Vasut

On Sunday, March 08, 2015 at 06:08:13 PM, Stephen Warren wrote:
 The original aligned_buffer usage:
 a) Uselessly copied data into the aligned buffer even for IN
transactions. Fix this my making the copy conditional.
 b) Always programmed the HW to transfer to/from the start of the aligned
buffer. This worked fine for OUT transactions since the memcpy copied
the OUT data to this location too. However, for large IN transactions,
since the copy from the aligned buffer to the client buffer was
deferred until after all chunks were transferred. it resulted in each
chunk's transfer over-writing the data for the first transfer. Fix
this by copying IN data as soon as it's received.
 
 Signed-off-by: Stephen Warren swar...@wwwdotorg.org

Applied to u-boot-usb/topic/dwc2, thanks. I would like to see more
testing from others if possible, otherwise this will go in after
2015.04 if you're fine with that.

Best regards,
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[U-Boot] [PATCH] mx6: soc: Switch to cold reset

2015-03-09 Thread Dirk Behme

Disable the warm reset and enable the cold reset for a more reliable
restart ('reset'). This is taken from the Linux kernel, see imx_src_init()
in arch/arm/mach-imx/src.c.

Signed-off-by: Dirk Behme dirk.be...@de.bosch.com
---
 arch/arm/cpu/armv7/mx6/soc.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 5f5f497..12be6ff 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -267,6 +267,22 @@ static void set_preclk_from_osc(void)
 }
 #endif
 
+#define SRC_SCR_WARM_RESET_ENABLE  0
+
+static void init_src(void)
+{
+   struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+   u32 val;
+
+   /*
+* force warm reset sources to generate cold reset
+* for a more reliable restart
+*/
+   val = readl(src_regs-scr);
+   val = ~(1  SRC_SCR_WARM_RESET_ENABLE);
+   writel(val, src_regs-scr);
+}
+
 int arch_cpu_init(void)
 {
init_aips();
@@ -294,6 +310,8 @@ int arch_cpu_init(void)
mxs_dma_init();
 #endif
 
+   init_src();
+
return 0;
 }
 
-- 
1.8.2

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[U-Boot] [PATCH] common/board_f.c: Enable IMX watchdog in init_func_watchdog_init()

2015-03-09 Thread Stefan Roese

Without this patch, the IMX watchdog will not be initialized. And therefor
not active. This patch fixes this by calling hw_watchdog_init() also when
CONFIG_IMX_WATCHDOG is defined.

Signed-off-by: Stefan Roese s...@denx.de
Cc: Simon Glass s...@chromium.org
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Stefano Babic sba...@denx.de
---
 common/board_f.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/common/board_f.c b/common/board_f.c
index 4d8b8a6..1dfaa2a 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -111,7 +111,8 @@ static int init_func_watchdog_init(void)
 {
 # if defined(CONFIG_HW_WATCHDOG)  (defined(CONFIG_BLACKFIN) || \
defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
-   defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG))
+   defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG)) || \
+   defined(CONFIG_IMX_WATCHDOG)
hw_watchdog_init();
 # endif
puts(   Watchdog enabled\n);
-- 
2.3.1

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Re: [U-Boot] MinnowBoard Max uboot

+Bin and Gabriel

Hi Tom,

On 9 March 2015 at 08:08, Beaman, Thomas thomas.bea...@xerox.com wrote:


 Hi Simon,



 I see you have put support for the MinnowBoard Max in the u-boot mainline.
 Thanks this is a very useful addition.  I have been able to follow your
 readme and build a working bare metal uboot. Using the built uboot I can
 load and bring up a Linux Kernel.



 What I noticed from the running kernel is that only one of the two cores on
 the E3825 is running. In the power PC uboots I usually see a section for the
 multiple cores in the .dts file. My questions is how do I get both CPUs
 running on this board. Is it a uboot .dts file setup that will enable this,
 or is something in the kernel start up that does this.



 As a test I boot the same kernel using the EFI BIOS on the minnow board and
 both CPUs are running.



 Any suggestions or comments you have would be welcomed.



My guess is that the LAPIC CPU start-up is missing. It isn't 100%
clear what the FSP does and does not do, but perhaps it does not do
that.

I did make something of a start on this with ivybridge but it isn't
complete, and it seems to be needed here.

Regards,
Simon
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Re: [U-Boot] [linux-sunxi] Re: Basic A33 support including dram init available in my personal repo

2015-03-09 Thread Maxime Ripard

On Mon, Mar 09, 2015 at 05:04:15PM +0800, Chen-Yu Tsai wrote:
 Hi,
 
 On Mon, Mar 9, 2015 at 4:39 PM, Vishnu Patekar
 vishnupatekar0...@gmail.com wrote:
  Hello,
  It's sensible work by Allwinner to release the dram code under GPLv2.
 
  Now, we can have mainline u-boot support for A33 soon.
 
  Hans,
  Yes, I've very basic A33 dts created based on A23, still lot to do.
 
 About the dts, so far the memory maps look the same. I haven't
 checked the clocks or interrupts, but I bet they are the same as
 well.
 
 Could we use an overlay over A23 with just the different pieces
 overriden? Though they're not the same piece of silicon, they are
 damn close. Maybe even the PIO is the same.

I'd prefer something like sun8i.dtsi, and then include it from both
sun8i-a23.dtsi and sun8i-a33.dtsi, like we did recently for sun5i,
but that's a detail.

But yeah, if they're that close, we should definitely share as much as
possible.

Maxime

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Re: [U-Boot] Question about board-specific Makefile actions

2015-03-09 Thread James Chargin


So, is no one willing to offer a hint?

Thanks,
Jim

On 03/03/2015 01:39 PM, James Chargin wrote:

I have a custom board in a git workspace for U-Boot 2014.07. I've copied
most of this from the .../board/ti/beagle. My board directory Makefile
looks like

8---
obj-y := board.o
8---

I'd like to add a few files to this directory that are processed during
make all and have any newly derived files deleted during make clean.

I've experimented with various Makefile contents but I can't get the new
files processed or any newly derived files deleted. U-Boot's makefile
system is quite large for my experience level and it seems I don't have
enough understanding.

A new file might contain some hush commands that are to be executed from
the U-Boot command line. I'd like to use source to process these
commands. The source command requires that its argument be an image (I
get this into memory via TFTP), so I'd like make all to transform the
text file containing the hush commands into the image file. I'd also
like make clean to delete the derived image file.

So, if my hush commands are in a text file called test.txt, I'd like
make all to apply mkimage so that a test.img is generated. I'd also
like make clean to delete test.img.

I tried various changes to my Makefile, but the most likely seeming
changes are

8---
IMG  = test.img

obj-y:= board.o

board.o : $(IMG)

%.img : %.txt
 $(srctree)/tools/mkimage -T script -n $* -C none -d $ $@

CLEAN_FILES += $(IMG)
CLEAN_DIRS  += .
8---

This doesn't work, nor has any other approach I've taken. mkimage is
never run for make all and test.img doesn't get deleted if I create a
fake one and run make clean

Could someone offer a solution, either directly, or by pointing at an
existing board that does something similar?

Thanks
Jim



--
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AJA Video Systems   j...@aja.com
(530) 271-3334  http://www.aja.com
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Re: [U-Boot] Question about board-specific Makefile actions

On Tue, Mar 03, 2015 at 01:39:35PM -0800, James Chargin wrote:
 I have a custom board in a git workspace for U-Boot 2014.07. I've
 copied most of this from the .../board/ti/beagle. My board directory
 Makefile looks like
 
 8---
 obj-y := board.o
 8---
 
 I'd like to add a few files to this directory that are processed
 during make all and have any newly derived files deleted during
 make clean.
 
 I've experimented with various Makefile contents but I can't get the
 new files processed or any newly derived files deleted. U-Boot's
 makefile system is quite large for my experience level and it seems
 I don't have enough understanding.
 
 A new file might contain some hush commands that are to be executed
 from the U-Boot command line. I'd like to use source to process
 these commands. The source command requires that its argument be
 an image (I get this into memory via TFTP), so I'd like make all
 to transform the text file containing the hush commands into the
 image file. I'd also like make clean to delete the derived image
 file.
 
 So, if my hush commands are in a text file called test.txt, I'd like
 make all to apply mkimage so that a test.img is generated. I'd
 also like make clean to delete test.img.
 
 I tried various changes to my Makefile, but the most likely seeming
 changes are
 
 8---
 IMG  = test.img
 
 obj-y := board.o
 
 board.o : $(IMG)
 
 %.img : %.txt
   $(srctree)/tools/mkimage -T script -n $* -C none -d $ $@
 
 CLEAN_FILES += $(IMG)
 CLEAN_DIRS  += .
 8---
 
 This doesn't work, nor has any other approach I've taken. mkimage is
 never run for make all and test.img doesn't get deleted if I
 create a fake one and run make clean
 
 Could someone offer a solution, either directly, or by pointing at
 an existing board that does something similar?

Off the top of my head, try throwing test.img into obj-y ?

-- 
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[U-Boot] [PATCH] mx53ard: Use the standard U-boot prompt

By not defining CONFIG_SYS_PROMPT, the standard = prompt is used, so remove
its definition.

Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
 include/configs/mx53ard.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index 134d680..9b003fc 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -186,7 +186,6 @@
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP/* undef to save memory */
 #define CONFIG_SYS_HUSH_PARSER /* use hush command parser */
-#define CONFIG_SYS_PROMPT  MX53ARD U-Boot  
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE  256 /* Console I/O Buffer Size */
 
-- 
1.9.1

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[U-Boot] MinnowBoard Max uboot

2015-03-09 Thread Beaman, Thomas


Hi Simon,

I see you have put support for the MinnowBoard Max in the u-boot mainline. 
Thanks this is a very useful addition.  I have been able to follow your readme 
and build a working bare metal uboot. Using the built uboot I can load and 
bring up a Linux Kernel.

What I noticed from the running kernel is that only one of the two cores on the 
E3825 is running. In the power PC uboots I usually see a section for the 
multiple cores in the .dts file. My questions is how do I get both CPUs running 
on this board. Is it a uboot .dts file setup that will enable this, or is 
something in the kernel start up that does this.

As a test I boot the same kernel using the EFI BIOS on the minnow board and 
both CPUs are running.

Any suggestions or comments you have would be welcomed.

Thanks,
Tom Beaman

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Re: [U-Boot] ARM: PSCI: Rework the DT handler slightly

On Thu, Mar 05, 2015 at 08:19:36PM -0500, Tom Rini wrote:

 The way the PSCI DT update happens currently means we pull in
 asm/armv7.h everywhere, including on ARMv8 and that in turn brings in
 asm/io.h for some non-PSCI related things that header needs to deal
 with.
 
 To fix this, we rework the hook slightly.  A good portion of
 arch/arm/cpu/armv7/virt-dt.c is common looking and I hope that when PSCI
 is needed on ARMv8 we can re-use this by and large.  So rename the
 current hook to psci_update_dt(), move the prototype to asm/psci.h and
 add an #ifdef that will make re-use later easier.
 
 Reported-by: York Sun york...@freescale.com
 Cc: Marc Zyngier marc.zyng...@arm.com
 Cc: York Sun york...@freescale.com
 Cc: Ian Campbell i...@hellion.org.uk
 Cc: Hans de Goede hdego...@redhat.com
 Cc: Albert ARIBAUD albert.u.b...@aribaud.net
 Signed-off-by: Tom Rini tr...@konsulko.com
 Acked-by: York Sun york...@freescale.com

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [U-Boot, v6, 09/10] ti-armv7-common: increase malloc pool len by dfu mmc file buffer size

On Wed, Mar 04, 2015 at 02:01:29PM +0100, Przemyslaw Marczak wrote:

 The dfu mmc file buffer, which was static, now is allocated
 by memalign(), so the malloc pool len should be also increased.
 
 Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
 Cc: Tom Rini tr...@konsulko.com

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v6, 02/10] arm: relocation: clear .bss section with arch memset if defined

On Wed, Mar 04, 2015 at 02:01:22PM +0100, Przemyslaw Marczak wrote:

 For ARM architecture, enable the CONFIG_USE_ARCH_MEMSET/MEMCPY,
 will highly increase the memset/memcpy performance. This is able
 thanks to the ARM multiple register instructions.
 
 Unfortunatelly the relocation is done without the cache enabled,
 so it takes some time, but zeroing the BSS memory takes much more
 longer, especially for the configs with big static buffers.
 
 A quick test confirms, that the boot time improvement after using
 the arch memcpy for relocation has no significant meaning.
 The same test confirms that enable the memset for zeroing BSS,
 reduces the boot time.
 
 So this patch enables the arch memset for zeroing the BSS after
 the relocation process. For ARM boards, this can be enabled
 in board configs by defining: 'CONFIG_USE_ARCH_MEMSET'.
 
 This was tested on Trats2.
 A quick test with trace. Boot time from start to main_loop() entry:
 - ~1384ms - before this change
 -  ~888ms - after this change
 
 Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
 Reviewed-by: Simon Glass s...@chromium.org
 Cc: Albert Aribaud albert.u.b...@aribaud.net
 Cc: Tom Rini tr...@konsulko.com

Applied to u-boot/master, thanks!

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Re: [U-Boot] Please pull u-boot-dm

On Fri, Mar 06, 2015 at 01:04:47PM -0700, Simon Glass wrote:

 Hi Tom,
 
 The following changes since commit 694cc87b76b1063a2a7a8bd1809e990df0a469f8:
 
   arm, da8xx: convert ipam390 board to generic board support
 (2015-03-05 10:08:13 -0500)
 
 are available in the git repository at:
 
   http://git.denx.de/u-boot-dm.git
 
 for you to fetch changes up to 65eb659e56fadf8183532d95db1d06fb63c60f9f:
 
   README: remove description about driver model configuration options
 (2015-03-05 19:13:43 -0700)
 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v6, 03/10] dfu: mmc: file buffer: remove static allocation

On Wed, Mar 04, 2015 at 02:01:23PM +0100, Przemyslaw Marczak wrote:

 For writing files, DFU implementation requires the file buffer
 with the len at least of file size. For big files it requires
 the same big buffer.
 
 Previously the file buffer was allocated as a static variable,
 so it was a part of U-Boot .bss section. For 32MiB len of buffer
 we have 32MiB of additional space, required for this section.
 
 The .bss needs to be cleared after the relocation.
 This introduces an additional boot delay at every start, but usually
 the dfu feature is not required at the standard boot, so the buffer
 should be allocated only if required.
 
 This patch removes the static allocation of this buffer,
 and alloc it with memalign after first call of function:
 - dfu_fill_entity_mmc()
 and the buffer is freed on dfu_free_entity() call.
 
 This was tested on Trats2.
 A quick test with trace. Boot time from start to main_loop() entry:
 - ~888ms - before this change (arch memset enabled for .bss clear)
 - ~464ms - after this change
 
 Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
 Reviewed-by: Simon Glass s...@chromium.org
 Cc: Lukasz Majewski l.majew...@samsung.com
 Cc: Stephen Warren swar...@nvidia.com
 Cc: Pantelis Antoniou pa...@antoniou-consulting.com
 Cc: Tom Rini tr...@konsulko.com
 Cc: Marek Vasut marek.va...@gmail.com

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v6, 10/10] tegra-common: increase malloc pool len by dfu mmc file buffer size

On Wed, Mar 04, 2015 at 02:01:30PM +0100, Przemyslaw Marczak wrote:

 The dfu mmc file buffer, which was static, now is allocated
 by memalign(), so the malloc pool len should be also increased.
 
 Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
 Cc: Tom Warren twarren.nvi...@gmail.com

Applied to u-boot/master, thanks!

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Re: [U-Boot] common/board_r: Restore non-cached memory setup

On Mon, Mar 09, 2015 at 07:47:18AM +0100, Jan Kiszka wrote:

 This fixes a regression of e310b93ec1, affecting Ethernet on the Jetson
 TK1, e.g.
 
 Signed-off-by: Jan Kiszka jan.kis...@siemens.com

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH v6 3/6] dm: tegra: Enable driver model in SPL and adjust the GPIO driver


On 03/09/2015 11:04 AM, Simon Glass wrote:

Hi Stephen,

On 8 March 2015 at 15:00, Stephen Warren swar...@nvidia.com wrote:


On 03/04/2015 03:16 PM, Tom Rini wrote:

On Tue, Mar 03, 2015 at 08:02:59AM -0700, Simon Glass wrote:


Use the full driver model GPIO and serial drivers in SPL now that
these are supported. Since device tree is not available they will
use platform data.

Remove the special SPL GPIO function as it is no longer needed.

This is all in one commit to maintain bisectability.

Signed-off-by: Simon Glass s...@chromium.org


Applied to u-boot/master, thanks!


This patch breaks the serial console on at least NVIDIA Tegra
Seaboard. LCD/usbkbd still work though. I can't test any other Tegra
boards right now since I'm not at work. I wonder if the UART/SPI GPIO
is at issue? That would be specific to this board.


Could be - what do you have it set to? I should be able to give it
another test sometime today and nut it out.


I assume it must be set to GPIO control (especially since a 
GPIO-related change broke it). IIRC it came this way, and since the 
board boots from NAND and hence SPI isn't useful, I was going to change 
it to always UART. However, when I attempted to modify my other 
Seaboard (actually, Springbank) that way, I broke one of the pads on the 
PCB. Luckily that left the board in the always UART state that I 
wanted, even without any pull-ups/downs present. Anyway, I decided not 
to touch my other board for fear of breaking it in a way that didn't 
work at all!

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[U-Boot] [PATCH 1/1] am335x_evm_usbspl: Remove other SPL modes

The purpose of this build target is to do SPL over USB RNDIS.  We remove
YMODEM, MMC and NAND (and re-set ENV to be built-in) as when those are needed
we can use the other build targets.  This brings us well under size limit again.

Signed-off-by: Tom Rini tr...@konsulko.com
---
 include/configs/am335x_evm.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index f1c270c..a87059c 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -340,6 +340,12 @@
 #endif /* CONFIG_MUSB_GADGET */
 
 #if defined(CONFIG_SPL_BUILD)  defined(CONFIG_SPL_USBETH_SUPPORT)
+/* Remove other SPL modes. */
+#undef CONFIG_SPL_YMODEM_SUPPORT
+#undef CONFIG_SPL_NAND_SUPPORT
+#undef CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_ENV_IS_NOWHERE
+#undef CONFIG_ENV_IS_IN_NAND
 /* disable host part of MUSB in SPL */
 #undef CONFIG_MUSB_HOST
 /* disable EFI partitions and partition UUID support */
-- 
2.1.4

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Re: [U-Boot] [U-Boot, v6, 08/10] zynq-common: increase malloc pool len by dfu mmc file buffer size

On Wed, Mar 04, 2015 at 02:01:28PM +0100, Przemyslaw Marczak wrote:

 The dfu mmc file buffer, which was static, now is allocated
 by memalign(), so the malloc pool len should be also increased.
 
 Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
 Cc: Jagannadha Sutradharudu Teki jaga...@xilinx.com
 Cc: Michal Simek mon...@monstr.eu
 Acked-by: Michal Simek michal.si...@xilinx.com

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v6, 01/10] exynos: config: enable arch memcpy and arch memset

On Wed, Mar 04, 2015 at 02:01:21PM +0100, Przemyslaw Marczak wrote:

 This commit enables the following configs:
 - CONFIG_USE_ARCH_MEMCPY
 - CONFIG_USE_ARCH_MEMSET
 This increases the performance of memcpy/memset
 and also reduces the boot time.
 
 This was tested on Trats2.
 A quick test with trace. Boot time from start to main_loop() entry:
 - ~1527ms - before this change (arch memset enabled for .bss clear)
 - ~1384ms - after this change
 
 Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
 Reviewed-by: Simon Glass s...@chromium.org
 Cc: Minkyu Kang mk7.k...@samsung.com
 Cc: Akshay Saraswat aksha...@samsung.com
 Cc: Simon Glass s...@chromium.org
 Cc: Sjoerd Simons sjoerd.sim...@collabora.co.uk

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, 4/4, v4] armv8/vexpress64: make multientry conditional

On Mon, Mar 09, 2015 at 10:53:21AM +0100, Linus Walleij wrote:

 While the Freescale ARMv8 board LS2085A will enter U-Boot both
 on a master and a secondary (slave) CPU, this is not the common
 behaviour on ARMv8 platforms. The norm is that U-Boot is entered
 from the master CPU only, while the other CPUs are kept in
 WFI (wait for interrupt) state.
 
 The code determining which CPU we are running on is using the
 MPIDR register, but the definition of that register varies with
 platform to some extent, and handling multi-cluster platforms
 (such as the Juno) will become cumbersome. It is better to only
 enable the multiple entry code on machines that actually need
 it and disable it by default.
 
 Make the single entry default and add a special
 ARMV8_MULTIENTRY KConfig option to be used by the
 platforms that need multientry and set it for the LS2085A.
 Delete all use of the CPU_RELEASE_ADDR from the Vexpress64
 boards as it is just totally unused and misleading, and
 make it conditional in the generic start.S code.
 
 This makes the Juno platform start U-Boot properly.
 
 Signed-off-by: Linus Walleij linus.wall...@linaro.org

Applied to u-boot/master, thanks!

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Re: [U-Boot] common: cmd_elf: Add support to disable start of application

On Mon, Mar 09, 2015 at 12:46:47PM +0100, Michal Simek wrote:

 From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
 
 Added support to disable the start of application by using
 a environment variable autostart
 
 Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
 Signed-off-by: Michal Simek michal.si...@xilinx.com

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v6, 07/10] odroid-xu3: defconfig: disable memset at malloc init

On Wed, Mar 04, 2015 at 02:01:27PM +0100, Przemyslaw Marczak wrote:

 Reduce the boot time of Odroid XU3 by disabling the memset
 at malloc init.
 
 Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH V2 1/2] usb: dwc2: fix aligned buffer usage


On 03/09/2015 06:46 AM, Marek Vasut wrote:

On Sunday, March 08, 2015 at 06:08:13 PM, Stephen Warren wrote:

The original aligned_buffer usage:
a) Uselessly copied data into the aligned buffer even for IN
transactions. Fix this my making the copy conditional.
b) Always programmed the HW to transfer to/from the start of the aligned
buffer. This worked fine for OUT transactions since the memcpy copied
the OUT data to this location too. However, for large IN transactions,
since the copy from the aligned buffer to the client buffer was
deferred until after all chunks were transferred. it resulted in each
chunk's transfer over-writing the data for the first transfer. Fix
this by copying IN data as soon as it's received.

Signed-off-by: Stephen Warren swar...@wwwdotorg.org


Applied to u-boot-usb/topic/dwc2, thanks. I would like to see more
testing from others if possible, otherwise this will go in after
2015.04 if you're fine with that.


Yes, that makes sense at this point in the cycle.

BTW, I should have mentioned the result of these on the RPi, although 
they're much the same as with the earlier patch you posted to support 
max_packet_size control transfers:


* I can enumerate a USB keyboard directly attached to the SoC, without 
intervening hub.


* If I enable USB keyboard support in U-Boot, and configure it to poll 
via the control EP or interrupt EP (I implemented the submit_interrupt 
function identically to submit_bulk), it will roughly work, except:


** The system usually hangs up very shortly after detecting the USB 
keyboard. Sometimes it lasts a long time though. This appears to be a 
hard hang; if I force the timer module to generate an IRQ, then 
typically I would see U-Boot spew the PC/SP/... when the IRQ fires. 
However, if the timer IRQ is scheduled to fire after the USB-related 
hang, nothing is printed. I need to try JTAG I guess.


** When polling via the interrupt EP, the character repeat is massively 
too fast; much faster than on e.g. NVIDIA Tegra Seaboard with the same 
keyboard polling option selected. It seems that USB IN transactions 
often repeat without actually writing to the IN data buffer, although I 
can't see any status in the registers indicating that the transaction 
was NAK'd/NYET'd/failed. I wonder if I need to manually delay 
transactions with this controller - do EHCI controllers hold off 
interrupt transactions automatically and only submit them to the bus at 
a low rate?

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Re: [U-Boot] [U-Boot, v6, 04/10] dlmalloc: do memset in malloc init as new default config

On Wed, Mar 04, 2015 at 02:01:24PM +0100, Przemyslaw Marczak wrote:

 This commit introduces new config: CONFIG_SYS_MALLOC_CLEAR_ON_INIT.
 
 This config is an expert option and is enabled by default.
 
 The all amount of memory reserved for the malloc, is by default set
 to zero in mem_malloc_init(). When the malloc reserved memory exceeds
 few MiB, then the boot process can slow down.
 
 So disabling this config, is an expert option to reduce the boot time,
 and can be disabled by Kconfig.
 
 Note:
 After disable this option, only calloc() will return the pointer
 to the zeroed memory area. Previously, without this option,
 the memory pointed to untouched malloc memory region, was filled
 with zeros. So it means, that code with malloc() calls should
 be reexamined.
 
 Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
 Reviewed-by: Simon Glass s...@chromium.org

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v6, 05/10] trats2: defconfig: disable memset at malloc init

On Wed, Mar 04, 2015 at 02:01:25PM +0100, Przemyslaw Marczak wrote:

 Reduce the boot time of Trats2 by disabling the memset
 at malloc init.
 
 This was tested on Trats2.
 A quick test with trace. Boot time from start to main_loop() entry:
 - ~464ms - before this change (arch memset enabled for .bss clear)
 - ~341ms - after this change
 
 Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
 Reviewed-by: Simon Glass s...@chromium.org

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v6, 06/10] odroid: defconfig: disable memset at malloc init

On Wed, Mar 04, 2015 at 02:01:26PM +0100, Przemyslaw Marczak wrote:

 Reduce the boot time of Odroid X2/U3 by disabling the memset
 at malloc init.
 
 This was tested on Odroid X2.
 A quick test with checking gpio pin state using the oscilloscope.
 Boot time from start to bootcmd (change gpio state by memory write command):
 - ~228ms - before this change (arch memset enabled for .bss clear)
 - ~100ms - after this change
 
 Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
 Reviewed-by: Simon Glass s...@chromium.org

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH v6 3/6] dm: tegra: Enable driver model in SPL and adjust the GPIO driver

Hi Stephen,

On 8 March 2015 at 15:00, Stephen Warren swar...@nvidia.com wrote:

 On 03/04/2015 03:16 PM, Tom Rini wrote:
  On Tue, Mar 03, 2015 at 08:02:59AM -0700, Simon Glass wrote:
 
  Use the full driver model GPIO and serial drivers in SPL now that
  these are supported. Since device tree is not available they will
  use platform data.
 
  Remove the special SPL GPIO function as it is no longer needed.
 
  This is all in one commit to maintain bisectability.
 
  Signed-off-by: Simon Glass s...@chromium.org
 
  Applied to u-boot/master, thanks!

 This patch breaks the serial console on at least NVIDIA Tegra
 Seaboard. LCD/usbkbd still work though. I can't test any other Tegra
 boards right now since I'm not at work. I wonder if the UART/SPI GPIO
 is at issue? That would be specific to this board.


Could be - what do you have it set to? I should be able to give it
another test sometime today and nut it out.

 (I just happened to test with that board while investigating why
 usbkbd was not working right on the RPi, since Seaboard has usbkbd
 support... Yay nested bugs!)

The worst type.

Regards,
Simon
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Re: [U-Boot] MIPS UHI spec

2015-03-09 Thread Andrew Bresticker

Hi Daniel,

On Thu, Feb 26, 2015 at 4:37 AM, Daniel Schwierzeck
daniel.schwierz...@gmail.com wrote:
 2015-02-26 11:17 GMT+01:00 Paul Burton paul.bur...@imgtec.com:
 On Thu, Feb 19, 2015 at 01:50:23PM +, Matthew Fortune wrote:
 Hi Daniel,

 The spec for MIPS Unified Hosting Interface is available here:

 http://prplfoundation.org/wiki/MIPS_documentation

 As we have previously discussed, this is an ideal place to
 define the handover of device tree data from bootloader to
 kernel. Using a0 == -2 and defining which register(s) you
 need for the actual data will fit nicely. I'll happily
 include whatever is decided into the next version of the spec.

 this originates from an off-list discussion some months ago started by
 John Crispin.

 (CC +John, Ralf, Jonas, linux-mips)


 (CC +Andrew, Ezequiel, James, James)

 On the talk of DT handover, this recent patchset adding support for a
 system doing so to Linux is relevant:

 http://www.linux-mips.org/archives/linux-mips/2015-02/msg00312.html

 I'm also working on a system for which I'll need to implement DT
 handover very soon. It would be very nice if we could agree on some
 standard way of doing so (and eventually if the code on the Linux side
 can be generic enough to allow a multiplatform kernel).


 to be conformant with UHI I propose $a0 == -2 and $a1 == address of DT
 blob. It is a simple extension and should not interfere with the
 various legacy boot interfaces.

Just to be clear, is $a1 expected to be the physical or virtual
(KSEG0) address of the DTB?

Thanks,
Andrew
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[U-Boot] [PATCH] mx6sabre: Do not enable UMS with SPL

From: Fabio Estevam fabio.este...@freescale.com

Since commit ad8aae82b20ac6a (mx6sabre: Enable User Mass Storage) SPL target
does not boot anymore due to the increased spl image size.

Only enable USB Mass Storage for the non-SPL target.

Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
 include/configs/mx6sabre_common.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/mx6sabre_common.h 
b/include/configs/mx6sabre_common.h
index f0e37f0..9417729 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -278,6 +278,7 @@
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 
+#ifndef CONFIG_SPL
 #define CONFIG_CI_UDC
 #define CONFIG_USBD_HS
 #define CONFIG_USB_GADGET_DUALSPEED
@@ -291,5 +292,6 @@
 #define CONFIG_G_DNL_VENDOR_NUM0x0525
 #define CONFIG_G_DNL_PRODUCT_NUM   0xa4a5
 #define CONFIG_G_DNL_MANUFACTURER  FSL
+#endif
 
 #endif /* __MX6QSABRE_COMMON_CONFIG_H */
-- 
1.9.1

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[U-Boot] [PATCH V6 02/11] ARM: Introduce erratum workaround for 454179

454179: Stale prediction may inhibit target address misprediction on
next predicted taken branch
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around:  Set IBE and disable branch size mispredict to 1

Also provide a hook for SoC specific handling to take place if needed.

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by: Nishanth Menon n...@ti.com
---
 README   |1 +
 arch/arm/cpu/armv7/cp15.c|6 ++
 arch/arm/cpu/armv7/start.S   |   13 +
 arch/arm/include/asm/armv7.h |2 ++
 4 files changed, 22 insertions(+)

diff --git a/README b/README
index 9a0106066b1c..259dbdbd2075 100644
--- a/README
+++ b/README
@@ -693,6 +693,7 @@ The following options need to be configured:
NOTE: The following can be machine specific errata. These
do have ability to provide rudimentary version and machine
specific checks, but expect no product checks.
+   CONFIG_ARM_ERRATA_454179
CONFIG_ARM_ERRATA_798870
 
 - Driver Model
diff --git a/arch/arm/cpu/armv7/cp15.c b/arch/arm/cpu/armv7/cp15.c
index 8ac81c9ba147..b44c9f94a822 100644
--- a/arch/arm/cpu/armv7/cp15.c
+++ b/arch/arm/cpu/armv7/cp15.c
@@ -21,3 +21,9 @@ void __weak v7_arch_cp15_set_l2aux_ctrl(u32 l2actlr, u32 
cpu_midr,
 {
asm volatile (mcr p15, 1, %0, c15, c0, 0\n\t : : r(l2actlr));
 }
+
+void __weak v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+u32 cpu_variant, u32 cpu_rev)
+{
+   asm volatile (mcr p15, 0, %0, c1, c0, 1\n\t : : r(acr));
+}
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 89637e26395d..8483687879ed 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -189,6 +189,19 @@ ENTRY(cpu_init_cp15)
 skip_errata_798870:
 #endif
 
+#ifdef CONFIG_ARM_ERRATA_454179
+   cmp r2, #0x21   @ Only on  r2p1
+   bge skip_errata_454179
+
+   mrc p15, 0, r0, c1, c0, 1   @ Read ACR
+   orr r0, r0, #(0x3  6) @ Set DBSM(BIT7) and IBE(BIT6) bits
+   push{r1-r5} @ Save the cpu info registers
+   bl  v7_arch_cp15_set_acr
+   pop {r1-r5} @ Restore the cpu info - fall through
+
+skip_errata_454179:
+#endif
+
mov pc, r5  @ back to my caller
 ENDPROC(cpu_init_cp15)
 
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index 69abc4791ae5..e9a00e20002c 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -141,6 +141,8 @@ extern char __secure_end[];
 void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
 u32 cpu_rev_comb, u32 cpu_variant,
 u32 cpu_rev);
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+ u32 cpu_variant, u32 cpu_rev);
 #endif /* ! __ASSEMBLY__ */
 
 #endif
-- 
1.7.9.5

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[U-Boot] [PATCH V6 07/11] ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with omap_smc1

omap_smc1 is now generic enough to remove duplicate
omap3_gp_romcode_call logic that omap3 introduced.

As part of this change, move to using the generic lowlevel_init.S for
omap3 as well.

Signed-off-by: Nishanth Menon n...@ti.com
---
 arch/arm/cpu/armv7/omap-common/Makefile|2 +-
 arch/arm/cpu/armv7/omap-common/lowlevel_init.S |2 ++
 arch/arm/cpu/armv7/omap3/board.c   |6 ++
 arch/arm/cpu/armv7/omap3/lowlevel_init.S   |   11 ---
 arch/arm/include/asm/arch-omap3/sys_proto.h|1 -
 5 files changed, 5 insertions(+), 17 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/Makefile 
b/arch/arm/cpu/armv7/omap-common/Makefile
index 7695e16d36f5..f3725b267c99 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -28,7 +28,7 @@ endif
 
 ifeq ($(CONFIG_OMAP34XX),)
 obj-y  += boot-common.o
-obj-y  += lowlevel_init.o
 endif
+obj-y  += lowlevel_init.o
 
 obj-y  += mem-common.o
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S 
b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
index 80619b04df5d..746df922c27d 100644
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -16,11 +16,13 @@
 #include asm/arch/spl.h
 #include linux/linkage.h
 
+#ifndef CONFIG_OMAP34XX
 ENTRY(save_boot_params)
ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
str r0, [r1]
b   save_boot_params_ret
 ENDPROC(save_boot_params)
+#endif
 
 ENTRY(omap_smc1)
PUSH{r4-r12, lr}@ save registers - ROM code may pollute
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index dd53b207f850..6e6a95762b8d 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -429,8 +429,7 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 
clear_bits)
acr |= set_bits;
 
if (get_device_type() == GP_DEVICE) {
-   omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
-  acr);
+   omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
} else {
struct emu_hal_params emu_romcode_params;
emu_romcode_params.num_params = 1;
@@ -470,8 +469,7 @@ static void omap3_update_aux_cr(u32 set_bits, u32 
clear_bits)
 static void omap3_invalidate_l2_cache_secure(void)
 {
if (get_device_type() == GP_DEVICE) {
-   omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
- 0);
+   omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
} else {
struct emu_hal_params emu_romcode_params;
emu_romcode_params.num_params = 1;
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S 
b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index 80cb2639f60c..7a691519bb6b 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -27,17 +27,6 @@ ENTRY(save_boot_params)
 ENDPROC(save_boot_params)
 #endif
 
-ENTRY(omap3_gp_romcode_call)
-   PUSH {r4-r12, lr} @ Save all registers from ROM code!
-   MOV r12, r0 @ Copy the Service ID in R12
-   MOV r0, r1  @ Copy parameter to R0
-   mcr p15, 0, r0, c7, c10, 4  @ DSB
-   mcr p15, 0, r0, c7, c10, 5  @ DMB
-   .word   0xe1600070  @ SMC #0 to enter monitor - hand assembled
-   @ because we use -march=armv5
-   POP {r4-r12, pc}
-ENDPROC(omap3_gp_romcode_call)
-
 /*
  * Funtion for making PPA HAL API calls in secure devices
  * Input:
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h 
b/arch/arm/include/asm/arch-omap3/sys_proto.h
index bcf92fbe658b..0c77a22ccfff 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -73,6 +73,5 @@ void power_init_r(void);
 void dieid_num_r(void);
 void get_dieid(u32 *id);
 void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
-void omap3_gp_romcode_call(u32 service_id, u32 parameter);
 u32 warm_reset(void);
 #endif
-- 
1.7.9.5

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[U-Boot] [PATCH V6 03/11] ARM: Introduce erratum workaround for 430973

430973: Stale prediction on replaced inter working branch causes
Cortex-A8 to execute in the wrong ARM/Thumb state
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE to 1

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by: Nishanth Menon n...@ti.com
---
 README |1 +
 arch/arm/cpu/armv7/start.S |   13 +
 2 files changed, 14 insertions(+)

diff --git a/README b/README
index 259dbdbd2075..82f7e10c71d6 100644
--- a/README
+++ b/README
@@ -693,6 +693,7 @@ The following options need to be configured:
NOTE: The following can be machine specific errata. These
do have ability to provide rudimentary version and machine
specific checks, but expect no product checks.
+   CONFIG_ARM_ERRATA_430973
CONFIG_ARM_ERRATA_454179
CONFIG_ARM_ERRATA_798870
 
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 8483687879ed..41fb24cf321b 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -202,6 +202,19 @@ skip_errata_798870:
 skip_errata_454179:
 #endif
 
+#ifdef CONFIG_ARM_ERRATA_430973
+   cmp r2, #0x21   @ Only on  r2p1
+   bge skip_errata_430973
+
+   mrc p15, 0, r0, c1, c0, 1   @ Read ACR
+   orr r0, r0, #(0x1  6) @ Set IBE bit
+   push{r1-r5} @ Save the cpu info registers
+   bl  v7_arch_cp15_set_acr
+   pop {r1-r5} @ Restore the cpu info - fall through
+
+skip_errata_430973:
+#endif
+
mov pc, r5  @ back to my caller
 ENDPROC(cpu_init_cp15)
 
-- 
1.7.9.5

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[U-Boot] [PATCH V6 11/11] ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973, 621766

RX51 has a secure logic which uses different parameters compared to
traditional implementation. So, make the generic secure acr write
over-ride-able by board file and refactor rx51 code to use this.

While at it, enable the OMAP3 specific errata code for 454179, 430973,
621766.

Signed-off-by: Nishanth Menon n...@ti.com
---
 arch/arm/cpu/armv7/omap3/board.c|   45 ---
 arch/arm/include/asm/arch-omap3/sys_proto.h |1 +
 board/nokia/rx51/rx51.c |   19 ++-
 include/configs/nokia_rx51.h|4 +++
 4 files changed, 37 insertions(+), 32 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 51a1c5816c3e..b064c0cc8343 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -415,31 +415,30 @@ static void omap3_emu_romcode_call(u32 service_id, u32 
*parameters)
do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
 }
 
-void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
- u32 cpu_variant, u32 cpu_rev)
+void __weak omap3_set_aux_cr_secure(u32 acr)
 {
-   if (get_device_type() == GP_DEVICE) {
-   omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
-   } else {
-   struct emu_hal_params emu_romcode_params;
-   emu_romcode_params.num_params = 1;
-   emu_romcode_params.param1 = acr;
-   omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
-  (u32 *)emu_romcode_params);
-   }
+   struct emu_hal_params emu_romcode_params;
+
+   emu_romcode_params.num_params = 1;
+   emu_romcode_params.param1 = acr;
+   omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+  (u32 *)emu_romcode_params);
 }
 
-static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+ u32 cpu_variant, u32 cpu_rev)
 {
-   u32 acr;
+   /* Write ACR - affects secure banked bits */
+   if (get_device_type() == GP_DEVICE)
+   omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
+   else
+   omap3_set_aux_cr_secure(acr);
 
-   /* Read ACR */
-   asm volatile (mrc p15, 0, %0, c1, c0, 1 : =r (acr));
-   acr = ~clear_bits;
-   acr |= set_bits;
-   v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
+   /* Write ACR - affects non-secure banked bits - some erratas need it */
+   asm volatile (mcr p15, 0, %0, c1, c0, 1 : : r (acr));
 }
 
+
 #ifndef CONFIG_SYS_L2CACHE_OFF
 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
 {
@@ -449,9 +448,8 @@ static void omap3_update_aux_cr(u32 set_bits, u32 
clear_bits)
asm volatile (mrc p15, 0, %0, c1, c0, 1 : =r (acr));
acr = ~clear_bits;
acr |= set_bits;
+   v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
 
-   /* Write ACR - affects non-secure banked bits */
-   asm volatile (mcr p15, 0, %0, c1, c0, 1 : : r (acr));
 }
 
 /* Invalidate the entire L2 cache from secure mode */
@@ -470,10 +468,9 @@ static void omap3_invalidate_l2_cache_secure(void)
 
 void v7_outer_cache_enable(void)
 {
-   /* Set L2EN */
-   omap3_update_aux_cr_secure(0x2, 0);
 
/*
+* Set L2EN
 * On some revisions L2EN bit is banked on some revisions it's not
 * No harm in setting both banked bits(in fact this is required
 * by an erratum)
@@ -483,10 +480,8 @@ void v7_outer_cache_enable(void)
 
 void omap3_outer_cache_disable(void)
 {
-   /* Clear L2EN */
-   omap3_update_aux_cr_secure(0, 0x2);
-
/*
+* Clear L2EN
 * On some revisions L2EN bit is banked on some revisions it's not
 * No harm in clearing both banked bits(in fact this is required
 * by an erratum)
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h 
b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 0c77a22ccfff..3e45ce184ba4 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -73,5 +73,6 @@ void power_init_r(void);
 void dieid_num_r(void);
 void get_dieid(u32 *id);
 void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
+void omap3_set_aux_cr_secure(u32 acr);
 u32 warm_reset(void);
 #endif
diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c
index 08fcaf21b3c6..3d019b01428b 100644
--- a/board/nokia/rx51/rx51.c
+++ b/board/nokia/rx51/rx51.c
@@ -341,6 +341,17 @@ static void omap3_emu_romcode_call(u32 service_id, u32 
*parameters)
do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
 }
 
+void omap3_set_aux_cr_secure(u32 acr)
+{
+   struct emu_hal_params_rx51 emu_romcode_params = { 0, };
+
+   emu_romcode_params.num_params = 2;
+   emu_romcode_params.param1 = acr;
+
+   omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+

[U-Boot] [PATCH V6 00/11] ARM: OMAP3-DRA7: CP15 erratum workarounds and improvements

The sixth revision should be proper, I hope. (skipping all the
blurb and pointing to v1 for the blurb).

Changes since v5:
- omap_smc1 is now in omap_common.h
- I hope we can pick up Matt's Tested-by tag from previous rev..
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/214277

v5: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/214219
v4: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/213863
V3: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/213207/focus=213307
V2: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213060
V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174

This time, the series is based on u-boot master
git://git.denx.de/u-boot.git
master 62f3aaf89d01 Merge branch 'buildman' of git://git.denx.de/u-boot-x86

Git tree: https://gitorious.org/nm-kernel/u-boot-nm (at least till gitorious is 
around..)
branch errata-v6-master-62f3aaf89d01

Git link: https://gitorious.org/nm-kernel/u-boot-nm.git 
errata-v6-master-62f3aaf89d01

Nishanth Menon (10):
  ARM: Introduce erratum workaround for 798870
  ARM: Introduce erratum workaround for 454179
  ARM: Introduce erratum workaround for 430973
  ARM: Introduce erratum workaround for 621766
  ARM: OMAP: Change set_pl310_ctrl_reg to be generic
  ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs
  ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with
omap_smc1
  ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended
configuration
  ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766
  ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973,
621766

Praveen Rao (1):
  ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870

 README |8 +++
 arch/arm/cpu/armv7/Makefile|2 +-
 arch/arm/cpu/armv7/cp15.c  |   29 +
 arch/arm/cpu/armv7/omap-common/Makefile|2 +-
 arch/arm/cpu/armv7/omap-common/lowlevel_init.S |   20 +++---
 arch/arm/cpu/armv7/omap3/board.c   |   60 +++---
 arch/arm/cpu/armv7/omap3/lowlevel_init.S   |   11 
 arch/arm/cpu/armv7/omap4/hwinit.c  |4 +-
 arch/arm/cpu/armv7/omap5/hwinit.c  |   23 +++
 arch/arm/cpu/armv7/start.S |   64 +++-
 .../arm/include/asm/arch-omap3/{omap3.h = omap.h} |0
 arch/arm/include/asm/arch-omap3/sys_proto.h|2 +-
 arch/arm/include/asm/arch-omap4/sys_proto.h|4 +-
 arch/arm/include/asm/arch-omap5/sys_proto.h|3 +
 arch/arm/include/asm/armv7.h   |5 ++
 arch/arm/include/asm/omap_common.h |2 +
 board/nokia/rx51/rx51.c|   19 +++---
 include/configs/am3517_crane.h |6 +-
 include/configs/am3517_evm.h   |6 +-
 include/configs/cm_t35.h   |6 +-
 include/configs/cm_t3517.h |6 +-
 include/configs/dig297.h   |6 +-
 include/configs/mcx.h  |6 +-
 include/configs/nokia_rx51.h   |6 +-
 include/configs/omap3_evm.h|2 +-
 include/configs/omap3_evm_common.h |4 ++
 include/configs/omap3_evm_quick_mmc.h  |2 +-
 include/configs/omap3_evm_quick_nand.h |2 +-
 include/configs/omap3_logic.h  |6 +-
 include/configs/omap3_mvblx.h  |6 +-
 include/configs/omap3_pandora.h|6 +-
 include/configs/omap3_sdp3430.h|6 +-
 include/configs/omap3_zoom1.h  |2 +-
 include/configs/tam3517-common.h   |6 +-
 include/configs/tao3530.h  |6 +-
 include/configs/ti_omap3_common.h  |7 ++-
 include/configs/ti_omap5_common.h  |3 +
 include/configs/tricorder.h|6 +-
 38 files changed, 274 insertions(+), 90 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/cp15.c
 rename arch/arm/include/asm/arch-omap3/{omap3.h = omap.h} (100%)

Regards,
Nishanth Menon
-- 
1.7.9.5

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Re: [U-Boot] [PATCHv2 17/20] arm: socfpga: spl: Add SDRAM check

2015-03-09 Thread Dinh Nguyen



On 3/4/15 7:21 AM, Marek Vasut wrote:
 On Monday, March 02, 2015 at 05:28:05 PM, dingu...@opensource.altera.com 
 wrote:
 From: Dinh Nguyen dingu...@opensource.altera.com

 Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com
 ---
  arch/arm/cpu/armv7/socfpga/spl.c | 8 
  1 file changed, 8 insertions(+)

 diff --git a/arch/arm/cpu/armv7/socfpga/spl.c
 b/arch/arm/cpu/armv7/socfpga/spl.c index ea4a1fb..31ac789 100644
 --- a/arch/arm/cpu/armv7/socfpga/spl.c
 +++ b/arch/arm/cpu/armv7/socfpga/spl.c
 @@ -191,4 +191,12 @@ void spl_board_init(void)

  sdram_size = sdram_calculate_size();
  debug(SDRAM: %ld MiB\n, (sdram_size  20));
 +
 +/* Sanity check ensure correct SDRAM size specified */
 +puts(SDRAM: Ensuring specified SDRAM size is correct ...);
 +if (get_ram_size(0, sdram_size) != sdram_size) {
 +puts(failed\n);
 
 Hi!
 
 Maybe just report a failure, the positive state is not interesting
 to the user and just polutes the console with messages which noone
 cares about (unless this would be a debug build maybe).
 
 What do you think please ?
 

Yeah, I think that's fine.

Dinh
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Re: [U-Boot] [PATCH v2] dm: spi: Convert Freescale DSPI driver to driver model

Hi,

On 8 March 2015 at 23:35, Haikun Wang haikun.w...@freescale.com wrote:
 Move the Freescale DSPI driver over to driver model.

 Signed-off-by: Haikun Wang haikun.w...@freescale.com
 ---

 Changes in v2:
 - Coding style cleanup
 - Add some comments
 - Use structures for I/O access
 - Handle timeout case in 'dspi_tx' and 'dspi_rx'
 - Move some register configurations from 'set_mode' to 'claim_bus'
 - Rename structure fsl_dspi_platdata's member baudrate
 - Remove some redundancy code

 Changes in v1: None

  drivers/spi/Makefile   |   1 +
  drivers/spi/fsl_dspi.c | 530 
 +
  include/fsl_dspi.h | 150 ++
  3 files changed, 681 insertions(+)
  create mode 100644 drivers/spi/fsl_dspi.c
  create mode 100644 include/fsl_dspi.h

 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
 index edbd520..9c2b8de 100644
 --- a/drivers/spi/Makefile
 +++ b/drivers/spi/Makefile
 @@ -49,3 +49,4 @@ obj-$(CONFIG_TI_QSPI) += ti_qspi.o
  obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
  obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
  obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
 +obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
 diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c
 new file mode 100644
 index 000..6108041
 --- /dev/null
 +++ b/drivers/spi/fsl_dspi.c
 @@ -0,0 +1,530 @@
 +/*
 + * (C) Copyright 2000-2003
 + * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 + *
 + * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
 + * TsiChung Liew (tsi-chung.l...@freescale.com)
 + * Chao Fu (b44...@freescale.com)
 + * Haikun Wang (b53...@freescale.com)
 + *
 + * SPDX-License-Identifier:GPL-2.0+
 + */
 +#include dm.h
 +#include errno.h
 +#include common.h
 +#include spi.h
 +#include malloc.h
 +#include asm/io.h
 +#include fdtdec.h
 +#include asm/arch/clock.h
 +#include fsl_dspi.h
 +
 +DECLARE_GLOBAL_DATA_PTR;
 +
 +/* fsl_dspi_platdata flags */
 +#define DSPI_FLAG_REGMAP_ENDIAN_BIG(1  0)
 +
 +/* idle data value */
 +#define DSPI_IDLE_VAL  0x0
 +
 +/* max chipselect signals number */
 +#define FSL_DSPI_MAX_CHIPSELECT6
 +
 +/* default SCK frequency, unit: HZ */
 +#define FSL_DSPI_DEFAULT_SCK_FREQ  1000
 +
 +/* tx/rx data wait timeout value, unit: us */
 +#define DSPI_TXRX_WAIT_TIMEOUT 100
 +
 +/* CTAR register pre-configure value */
 +#define DSPI_CTAR_DEFAULT_VALUE(DSPI_CTAR_TRSZ(7) | \
 +   DSPI_CTAR_PCSSCK_1CLK | \
 +   DSPI_CTAR_PASC(0) | \
 +   DSPI_CTAR_PDT(0) | \
 +   DSPI_CTAR_CSSCK(0) | \
 +   DSPI_CTAR_ASC(0) | \
 +   DSPI_CTAR_DT(0))
 +
 +/* CTAR register pre-configure mask */
 +#define DSPI_CTAR_SET_MODE_MASK(DSPI_CTAR_TRSZ(15) | \
 +   DSPI_CTAR_PCSSCK(3) | \
 +   DSPI_CTAR_PASC(3) | \
 +   DSPI_CTAR_PDT(3) | \
 +   DSPI_CTAR_CSSCK(15) | \
 +   DSPI_CTAR_ASC(15) | \
 +   DSPI_CTAR_DT(15))
 +
 +/**
 + * struct fsl_dspi_platdata - platform data for Freescale DSPI
 + *
 + * @flags: Flags for DSPI DSPI_FLAG_...
 + * @speed_hz: Default SCK frequency
 + * @num_chipselect: Number of DSPI chipselect signals
 + * @regs_addr: Base address of DSPI registers
 + */
 +struct fsl_dspi_platdata {
 +   uint flags;
 +   uint speed_hz;
 +   uint num_chipselect;
 +   fdt_addr_t regs_addr;
 +};
 +
 +struct fsl_dspi_priv {

Comments on these members?

 +   uint flags;
 +   uint mode;
 +   uint mcr_val;
 +   uint bus_clk;
 +   uint speed_hz;
 +   uint charbit;
 +   uint num_chipselect;
 +   uint ctar_val[FSL_DSPI_MAX_CHIPSELECT];
 +   struct dspi *regs;
 +   struct dm_spi_slave_platdata *cur_slave_plat;
 +};
 +
 +static uint dspi_read32(uint flags, uint *addr)
 +{
 +   return flags  DSPI_FLAG_REGMAP_ENDIAN_BIG ?
 +   in_be32(addr) : in_le32(addr);
 +}
 +
 +static void dspi_write32(uint flags, uint *addr, uint val)
 +{
 +   flags  DSPI_FLAG_REGMAP_ENDIAN_BIG ?
 +   out_be32(addr, val) : out_le32(addr, val);
 +}
 +
 +static void dspi_halt(struct udevice *bus, u8 halt)

nit: Should pass in priv instead of bus

 +{
 +   uint mcr_val;
 +   struct fsl_dspi_priv *priv = dev_get_priv(bus);
 +
 +   mcr_val = dspi_read32(priv-flags, priv-regs-mcr);
 +
 +   if (halt)
 +   mcr_val |= DSPI_MCR_HALT;
 +   else
 +   mcr_val = ~DSPI_MCR_HALT;
 +
 +   dspi_write32(priv-flags, priv-regs-mcr, mcr_val);
 +}
 +
 +static int fsl_dspi_child_pre_probe(struct udevice *dev)
 +{
 +   struct

Re: [U-Boot] [PATCHv2 02/20] arm: socfpga: spl: Add SRAM section

2015-03-09 Thread Dinh Nguyen



On 3/5/15 2:59 PM, Marek Vasut wrote:
 On Wednesday, March 04, 2015 at 10:34:30 PM, Dinh Nguyen wrote:
 On 03/04/2015 01:39 PM, Marek Vasut wrote:
 On Wednesday, March 04, 2015 at 07:52:04 PM, Dinh Nguyen wrote:
 On 03/04/2015 06:39 AM, Marek Vasut wrote:
 On Monday, March 02, 2015 at 05:27:50 PM,
 dingu...@opensource.altera.com

 wrote:
 From: Dinh Nguyen dingu...@opensource.altera.com

 Add a section of SRAM to the SPL linker file.

 Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com

 Hi!

 Can we not use the generic SPL stuff ( ./arch/arm/cpu/u-boot-spl.lds )
 here instead please ?

 I looked at this, but I didn't see way to overlay in an SRAM section. Do
 you have an example of how to do this?

 Hi!

 Is it really needed at all in the first place ? Why ?

 Isn't this need to specify the SPL to be located in the sram section? I
 see other platforms doing the same thing, ie. zynq, sunxi.
 
 CONFIG_SPL_TEXT_BASE is what specifies the address to which the SPL is linked.
 This is the address where the BootROM should place the SPL and jump to it's 
 first instruction.
 
 I don't think you explicitly need to hack linker scripts to add this section.

Ah yes, I think I can make use of it now.

 
 btw. Tom Rini has a different email address (@konsulko) now.

Right...saw it right after I sent out this series.

 
 btw2. is there any way I can help you with hacking on the SPL please ?
 

Let me post a v3 within this week, and I would appreciate any help. Does
posting the series to git repo help you to help me?

Dinh
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[U-Boot] [PATCH V6 08/11] ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870

From: Praveen Rao p...@ti.com

This patch enables the workaround for ARM errata 798870 for OMAP5 /
DRA7 which says If back-to-back speculative cache line fills (fill
A and fill B) are issued from the L1 data cache of a CPU to the
L2 cache, the second request (fill B) is then cancelled, and the
second request would have detected a hazard against a recent write or
eviction (write B) to the same cache line as fill B then the L2 logic
might deadlock.

An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced
here as well.

Signed-off-by: Praveen Rao p...@ti.com
Signed-off-by: Angela Stegmaier angelaba...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
 arch/arm/cpu/armv7/omap5/hwinit.c   |7 +++
 arch/arm/include/asm/arch-omap5/sys_proto.h |3 +++
 include/configs/ti_omap5_common.h   |3 +++
 3 files changed, 13 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c 
b/arch/arm/cpu/armv7/omap5/hwinit.c
index a8a474a88be9..f8060555b680 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -381,3 +381,10 @@ void setup_warmreset_time(void)
rst_val |= rst_time;
writel(rst_val, (*prcm)-prm_rsttime);
 }
+
+void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
+u32 cpu_rev_comb, u32 cpu_variant,
+u32 cpu_rev)
+{
+   omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
+}
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h 
b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 103830319a41..ea84665f5b97 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -66,4 +66,7 @@ static inline u32 usec_to_32k(u32 usec)
 {
return div_round_up(32768 * usec, 100);
 }
+
+#define OMAP5_SERVICE_L2ACTLR_SET0x104
+
 #endif
diff --git a/include/configs/ti_omap5_common.h 
b/include/configs/ti_omap5_common.h
index 925cb42dd38d..09f05f18a75d 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -21,6 +21,9 @@
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_ARCH_CPU_INIT
 
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_798870
+
 #define CONFIG_SYS_CACHELINE_SIZE  64
 
 /* Use General purpose timer 1 */
-- 
1.7.9.5

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[U-Boot] [PATCH V6 01/11] ARM: Introduce erratum workaround for 798870

Add workaround for Cortex-A15 ARM erratum 798870 which says
If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock.

Implementations for SoC families such as Exynos, OMAP5/DRA7 etc
will be widely different.

Every SoC has slightly different manner of setting up access to L2ACLR
and similar registers since the Secure Monitor handling of Secure
Monitor Call(smc) is diverse. Hence an weak function is introduced
which may be overriden to implement SoC specific accessor implementation.

Based on ARM errata Document revision 18.0 (22 Nov 2013)

Signed-off-by: Nishanth Menon n...@ti.com
---
 README   |5 +
 arch/arm/cpu/armv7/Makefile  |2 +-
 arch/arm/cpu/armv7/cp15.c|   23 +++
 arch/arm/cpu/armv7/start.S   |   25 -
 arch/arm/include/asm/armv7.h |3 +++
 5 files changed, 56 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/cp15.c

diff --git a/README b/README
index 676f41e7f09f..9a0106066b1c 100644
--- a/README
+++ b/README
@@ -690,6 +690,11 @@ The following options need to be configured:
exists, unlike the similar options in the Linux kernel. Do not
set these options unless they apply!
 
+   NOTE: The following can be machine specific errata. These
+   do have ability to provide rudimentary version and machine
+   specific checks, but expect no product checks.
+   CONFIG_ARM_ERRATA_798870
+
 - Driver Model
Driver model is a new framework for devices in U-Boot
introduced in early 2014. U-Boot is being progressively
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index ad22489e1a1f..1312a9db9e84 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -9,7 +9,7 @@ extra-y := start.o
 
 obj-y  += cache_v7.o
 
-obj-y  += cpu.o
+obj-y  += cpu.o cp15.o
 obj-y  += syslib.o
 
 ifneq 
($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),)
diff --git a/arch/arm/cpu/armv7/cp15.c b/arch/arm/cpu/armv7/cp15.c
new file mode 100644
index ..8ac81c9ba147
--- /dev/null
+++ b/arch/arm/cpu/armv7/cp15.c
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2015 Texas Insturments
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * CP15 specific code
+ */
+
+#include common.h
+#include command.h
+#include asm/system.h
+#include asm/cache.h
+#include asm/armv7.h
+#include linux/compiler.h
+
+void __weak v7_arch_cp15_set_l2aux_ctrl(u32 l2actlr, u32 cpu_midr,
+u32 cpu_rev_comb, u32 cpu_variant,
+u32 cpu_rev)
+{
+   asm volatile (mcr p15, 1, %0, c15, c0, 0\n\t : : r(l2actlr));
+}
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 9b49ece2d650..89637e26395d 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -166,7 +166,30 @@ ENTRY(cpu_init_cp15)
mcr p15, 0, r0, c15, c0, 1  @ write diagnostic register
 #endif
 
-   mov pc, lr  @ back to my caller
+   mov r5, lr  @ Store my Caller
+   mrc p15, 0, r1, c0, c0, 0   @ r1 has Read Main ID Register (MIDR)
+   mov r3, r1, lsr #20 @ get variant field
+   and r3, r3, #0xf@ r3 has CPU variant
+   and r4, r1, #0xf@ r4 has CPU revision
+   mov r2, r3, lsl #4  @ shift variant field for combined value
+   orr r2, r4, r2  @ r2 has combined CPU variant + revision
+
+#ifdef CONFIG_ARM_ERRATA_798870
+   cmp r2, #0x30   @ Applies to lower than R3p0
+   bge skip_errata_798870  @ skip if not affected rev
+   cmp r2, #0x20   @ Applies to including and above R2p0
+   blt skip_errata_798870  @ skip if not affected rev
+
+   mrc p15, 1, r0, c15, c0, 0  @ read l2 aux ctrl reg
+   orr r0, r0, #1  7 @ Enable hazard-detect timeout
+   push{r1-r5} @ Save the cpu info registers
+   bl  v7_arch_cp15_set_l2aux_ctrl
+   isb @ Recommended ISB after l2actlr update
+   pop {r1-r5} @ Restore the cpu info - fall through
+skip_errata_798870:
+#endif
+
+   mov pc, r5  @ back to my caller
 ENDPROC(cpu_init_cp15)
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index edb3b80015ba..69abc4791ae5 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@

[U-Boot] [PATCH V6 04/11] ARM: Introduce erratum workaround for 621766

621766: Under a specific set of conditions, executing a sequence of
NEON or vfp load instructions can cause processor deadlock
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set L1NEON to 1

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by: Nishanth Menon n...@ti.com
---
 README |1 +
 arch/arm/cpu/armv7/start.S |   13 +
 2 files changed, 14 insertions(+)

diff --git a/README b/README
index 82f7e10c71d6..e7e90a08145e 100644
--- a/README
+++ b/README
@@ -695,6 +695,7 @@ The following options need to be configured:
specific checks, but expect no product checks.
CONFIG_ARM_ERRATA_430973
CONFIG_ARM_ERRATA_454179
+   CONFIG_ARM_ERRATA_621766
CONFIG_ARM_ERRATA_798870
 
 - Driver Model
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 41fb24cf321b..5050021e0210 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -215,6 +215,19 @@ skip_errata_454179:
 skip_errata_430973:
 #endif
 
+#ifdef CONFIG_ARM_ERRATA_621766
+   cmp r2, #0x21   @ Only on  r2p1
+   bge skip_errata_621766
+
+   mrc p15, 0, r0, c1, c0, 1   @ Read ACR
+   orr r0, r0, #(0x1  5) @ Set L1NEON bit
+   push{r1-r5} @ Save the cpu info registers
+   bl  v7_arch_cp15_set_acr
+   pop {r1-r5} @ Restore the cpu info - fall through
+
+skip_errata_621766:
+#endif
+
mov pc, r5  @ back to my caller
 ENDPROC(cpu_init_cp15)
 
-- 
1.7.9.5

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[U-Boot] [PATCH V6 06/11] ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs

This is in preperation of using generic cross OMAP code.

Signed-off-by: Nishanth Menon n...@ti.com
---
 .../arm/include/asm/arch-omap3/{omap3.h = omap.h} |0
 include/configs/am3517_crane.h |2 +-
 include/configs/am3517_evm.h   |2 +-
 include/configs/cm_t35.h   |2 +-
 include/configs/cm_t3517.h |2 +-
 include/configs/dig297.h   |2 +-
 include/configs/mcx.h  |2 +-
 include/configs/nokia_rx51.h   |2 +-
 include/configs/omap3_evm.h|2 +-
 include/configs/omap3_evm_quick_mmc.h  |2 +-
 include/configs/omap3_evm_quick_nand.h |2 +-
 include/configs/omap3_logic.h  |2 +-
 include/configs/omap3_mvblx.h  |2 +-
 include/configs/omap3_pandora.h|2 +-
 include/configs/omap3_sdp3430.h|2 +-
 include/configs/omap3_zoom1.h  |2 +-
 include/configs/tam3517-common.h   |2 +-
 include/configs/tao3530.h  |2 +-
 include/configs/ti_omap3_common.h  |2 +-
 include/configs/tricorder.h|2 +-
 20 files changed, 19 insertions(+), 19 deletions(-)
 rename arch/arm/include/asm/arch-omap3/{omap3.h = omap.h} (100%)

diff --git a/arch/arm/include/asm/arch-omap3/omap3.h 
b/arch/arm/include/asm/arch-omap3/omap.h
similarity index 100%
rename from arch/arm/include/asm/arch-omap3/omap3.h
rename to arch/arm/include/asm/arch-omap3/omap.h
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 290a6a3e0640..87c850e05df1 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -23,7 +23,7 @@
 #define CONFIG_EMIF4   /* The chip has EMIF4 controller */
 
 #include asm/arch/cpu.h  /* get chip and board defs */
-#include asm/arch/omap3.h
+#include asm/arch/omap.h
 
 /*
  * Display CPU and Board information
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 3de50799621e..c4e19e79b95a 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -23,7 +23,7 @@
 #define CONFIG_EMIF4   /* The chip has EMIF4 controller */
 
 #include asm/arch/cpu.h  /* get chip and board defs */
-#include asm/arch/omap3.h
+#include asm/arch/omap.h
 
 /*
  * Display CPU and Board information
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 9feca1b47b38..e2d5bbb0955d 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -30,7 +30,7 @@
 #define CONFIG_SDRC/* The chip has SDRC controller */
 
 #include asm/arch/cpu.h  /* get chip and board defs */
-#include asm/arch/omap3.h
+#include asm/arch/omap.h
 
 /*
  * Display CPU and Board information
diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h
index 918032bd753a..ee1b7a0cb5a7 100644
--- a/include/configs/cm_t3517.h
+++ b/include/configs/cm_t3517.h
@@ -30,7 +30,7 @@
 #define CONFIG_EMIF4   /* The chip has EMIF4 controller */
 
 #include asm/arch/cpu.h  /* get chip and board defs */
-#include asm/arch/omap3.h
+#include asm/arch/omap.h
 
 /*
  * Display CPU and Board information
diff --git a/include/configs/dig297.h b/include/configs/dig297.h
index c8739ed29490..8791199fc61d 100644
--- a/include/configs/dig297.h
+++ b/include/configs/dig297.h
@@ -36,7 +36,7 @@
 #define CONFIG_SDRC/* The chip has SDRC controller */
 
 #include asm/arch/cpu.h  /* get chip and board defs */
-#include asm/arch/omap3.h
+#include asm/arch/omap.h
 
 /*
  * Display CPU and Board information
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 26eb2203540f..2cf66c40d6fe 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -26,7 +26,7 @@
 #define CONFIG_EMIF4   /* The chip has EMIF4 controller */
 
 #include asm/arch/cpu.h  /* get chip and board defs */
-#include asm/arch/omap3.h
+#include asm/arch/omap.h
 
 #define CONFIG_OF_LIBFDT
 #define CONFIG_FIT
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index 46fc91e5e197..442e16ae686b 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -42,7 +42,7 @@
 #define CONFIG_SDRC/* The chip has SDRC controller */
 
 #include asm/arch/cpu.h  /* get chip and board defs */
-#include asm/arch/omap3.h
+#include asm/arch/omap.h
 #include asm/arch/mem.h
 #include linux/stringify.h
 
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 8bdc08f5864c..4e587e10ffd3 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -18,7 +18,7 @@
 #define __OMAP3EVM_CONFIG_H
 
 #include asm/arch/cpu.h
-#include asm/arch/omap3.h
+#include asm/arch/omap.h
 
 /*

[U-Boot] [PATCH V6 10/11] ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766

Enable the OMAP3 specific errata code for 454179, 430973, 621766
and while at it, remove legacy non-revision checked errata logic.

Signed-off-by: Nishanth Menon n...@ti.com
---
 arch/arm/cpu/armv7/omap3/board.c   |   31 ++-
 include/configs/am3517_crane.h |4 
 include/configs/am3517_evm.h   |4 
 include/configs/cm_t35.h   |4 
 include/configs/cm_t3517.h |4 
 include/configs/dig297.h   |4 
 include/configs/mcx.h  |4 
 include/configs/omap3_evm_common.h |4 
 include/configs/omap3_logic.h  |4 
 include/configs/omap3_mvblx.h  |4 
 include/configs/omap3_pandora.h|4 
 include/configs/omap3_sdp3430.h|4 
 include/configs/tam3517-common.h   |4 
 include/configs/tao3530.h  |4 
 include/configs/ti_omap3_common.h  |5 +
 include/configs/tricorder.h|4 
 16 files changed, 71 insertions(+), 21 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 6e6a95762b8d..51a1c5816c3e 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /* Declarations */
 extern omap3_sysinfo sysinfo;
-static void omap3_setup_aux_cr(void);
 #ifndef CONFIG_SYS_L2CACHE_OFF
 static void omap3_invalidate_l2_cache_secure(void);
 #endif
@@ -244,9 +243,6 @@ void s_init(void)
 
try_unlock_memory();
 
-   /* Errata workarounds */
-   omap3_setup_aux_cr();
-
 #ifndef CONFIG_SYS_L2CACHE_OFF
/* Invalidate L2-cache from secure mode */
omap3_invalidate_l2_cache_secure();
@@ -419,15 +415,9 @@ static void omap3_emu_romcode_call(u32 service_id, u32 
*parameters)
do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
 }
 
-static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+ u32 cpu_variant, u32 cpu_rev)
 {
-   u32 acr;
-
-   /* Read ACR */
-   asm volatile (mrc p15, 0, %0, c1, c0, 1 : =r (acr));
-   acr = ~clear_bits;
-   acr |= set_bits;
-
if (get_device_type() == GP_DEVICE) {
omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
} else {
@@ -439,16 +429,15 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 
clear_bits)
}
 }
 
-static void omap3_setup_aux_cr(void)
+static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
 {
-   /* Workaround for Cortex-A8 errata: #454179 #430973
-*  Set IBE bit
-*  Set Disable Branch Size Mispredicts bit
-* Workaround for erratum #621766
-*  Enable L1NEON bit
-* ACR |= (IBE | DBSM | L1NEON) = ACR |= 0xE0
-*/
-   omap3_update_aux_cr_secure(0xE0, 0);
+   u32 acr;
+
+   /* Read ACR */
+   asm volatile (mrc p15, 0, %0, c1, c0, 1 : =r (acr));
+   acr = ~clear_bits;
+   acr |= set_bits;
+   v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
 }
 
 #ifndef CONFIG_SYS_L2CACHE_OFF
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 87c850e05df1..c3c9169d0555 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -19,6 +19,10 @@
 #define CONFIG_OMAP1   /* in a TI OMAP core */
 #define CONFIG_OMAP3_AM3517CRANE   1   /* working with CRANEBOARD */
 #define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
 
 #define CONFIG_EMIF4   /* The chip has EMIF4 controller */
 
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index c4e19e79b95a..31e758d81bdd 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -19,6 +19,10 @@
 #define CONFIG_OMAP1   /* in a TI OMAP core */
 #define CONFIG_OMAP3_AM3517EVM 1   /* working with AM3517EVM */
 #define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
 
 #define CONFIG_EMIF4   /* The chip has EMIF4 controller */
 
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index e2d5bbb0955d..3eb7886eb69e 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -26,6 +26,10 @@
 #define CONFIG_CM_T3X  /* working with CM-T35 and CM-T3730 */
 #define CONFIG_OMAP_COMMON
 #define CONFIG_SYS_GENERIC_BOARD
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
 
 #define CONFIG_SDRC/* The chip has SDRC controller */
 
diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h
index ee1b7a0cb5a7..8c6313832250 100644
--- a/include/configs/cm_t3517.h
+++ b/include/configs/cm_t3517.h
@@ -17,6 +17,10 @@
 #define

[U-Boot] [PATCH V6 09/11] ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configuration

Update to existing recommendation for L2ACTLR configuration to prevent
system instability and optimize performance.

These apply to both OMAP5 and DRA7.

Reported-by: Vivek Chengalvala vchengalv...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
 arch/arm/cpu/armv7/omap5/hwinit.c |   16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c 
b/arch/arm/cpu/armv7/omap5/hwinit.c
index f8060555b680..8d6b59eeb044 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -304,6 +304,21 @@ void config_data_eye_leveling_samples(u32 emif_base)
   (*ctrl)-control_emif2_sdram_config_ext);
 }
 
+void init_cpu_configuration(void)
+{
+   u32 l2actlr;
+
+   asm volatile(mrc p15, 1, %0, c15, c0, 0 : =r(l2actlr));
+   /*
+* L2ACTLR: Ensure to enable the following:
+* 3: Disable clean/evict push to external
+* 4: Disable WriteUnique and WriteLineUnique transactions from master
+* 8: Disable DVM/CMO message broadcast
+*/
+   l2actlr |= 0x118;
+   omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
+}
+
 void init_omap_revision(void)
 {
/*
@@ -342,6 +357,7 @@ void init_omap_revision(void)
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
}
+   init_cpu_configuration();
 }
 
 void reset_cpu(ulong ignored)
-- 
1.7.9.5

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Re: [U-Boot] Question about board-specific Makefile actions

Hi,

On 9 March 2015 at 08:54, Tom Rini tr...@konsulko.com wrote:
 On Tue, Mar 03, 2015 at 01:39:35PM -0800, James Chargin wrote:
 I have a custom board in a git workspace for U-Boot 2014.07. I've
 copied most of this from the .../board/ti/beagle. My board directory
 Makefile looks like

 8---
 obj-y := board.o
 8---

 I'd like to add a few files to this directory that are processed
 during make all and have any newly derived files deleted during
 make clean.

 I've experimented with various Makefile contents but I can't get the
 new files processed or any newly derived files deleted. U-Boot's
 makefile system is quite large for my experience level and it seems
 I don't have enough understanding.

 A new file might contain some hush commands that are to be executed
 from the U-Boot command line. I'd like to use source to process
 these commands. The source command requires that its argument be
 an image (I get this into memory via TFTP), so I'd like make all
 to transform the text file containing the hush commands into the
 image file. I'd also like make clean to delete the derived image
 file.

 So, if my hush commands are in a text file called test.txt, I'd like
 make all to apply mkimage so that a test.img is generated. I'd
 also like make clean to delete test.img.

 I tried various changes to my Makefile, but the most likely seeming
 changes are

 8---
 IMG  = test.img

 obj-y := board.o

 board.o : $(IMG)

 %.img : %.txt
   $(srctree)/tools/mkimage -T script -n $* -C none -d $ $@

 CLEAN_FILES += $(IMG)
 CLEAN_DIRS  += .
 8---

 This doesn't work, nor has any other approach I've taken. mkimage is
 never run for make all and test.img doesn't get deleted if I
 create a fake one and run make clean

 Could someone offer a solution, either directly, or by pointing at
 an existing board that does something similar?

 Off the top of my head, try throwing test.img into obj-y ?

Also you may want to add a command like cmd_img_txt (see Makefile.lib
for examples). Did you need to add anything to ALL-y?

Another option is to put this outside the U-Boot build system, and
just run mkimage later.

Regards,
Simon
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[U-Boot] [PATCH V6 05/11] ARM: OMAP: Change set_pl310_ctrl_reg to be generic

set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup
PL310 control register, however, that is something that is generic
enough to be used for OMAP5 generation of processors as well. The only
difference being the service being invoked for the function.

So, convert the service to a macro and use a generic name (same as
that used in Linux for some consistency). While at that, also add a
data barrier which is necessary as per recommendation.

While at this, smc #0 is maintained as handcoded assembly thanks to
various gcc version eccentricities, discussion thread:
http://marc.info/?t=14254216681r=1w=2

Signed-off-by: Nishanth Menon n...@ti.com
---
 arch/arm/cpu/armv7/omap-common/lowlevel_init.S |   18 +++---
 arch/arm/cpu/armv7/omap4/hwinit.c  |4 ++--
 arch/arm/include/asm/arch-omap4/sys_proto.h|4 +++-
 arch/arm/include/asm/omap_common.h |2 ++
 4 files changed, 18 insertions(+), 10 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S 
b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
index e19c7aececdd..80619b04df5d 100644
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -22,11 +22,15 @@ ENTRY(save_boot_params)
b   save_boot_params_ret
 ENDPROC(save_boot_params)
 
-ENTRY(set_pl310_ctrl_reg)
-   PUSH{r4-r11, lr}@ save registers - ROM code may pollute
+ENTRY(omap_smc1)
+   PUSH{r4-r12, lr}@ save registers - ROM code may pollute
@ our registers
-   LDR r12, =0x102 @ Set PL310 control register - value in R0
-   .word   0xe1600070  @ SMC #0 - hand assembled because -march=armv5
-   @ call ROM Code API to set control register
-   POP {r4-r11, pc}
-ENDPROC(set_pl310_ctrl_reg)
+   MOV r12, r0 @ Service
+   MOV r0, r1  @ Argument
+   DSB
+   DMB
+   .word   0xe1600070  @ SMC #0 - hand assembled for GCC versions
+   @ call ROM Code API for the service requested
+
+   POP {r4-r12, pc}
+ENDPROC(omap_smc1)
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c 
b/arch/arm/cpu/armv7/omap4/hwinit.c
index db16548fac49..9792761d40a0 100644
--- a/arch/arm/cpu/armv7/omap4/hwinit.c
+++ b/arch/arm/cpu/armv7/omap4/hwinit.c
@@ -159,11 +159,11 @@ void init_omap_revision(void)
 #ifndef CONFIG_SYS_L2CACHE_OFF
 void v7_outer_cache_enable(void)
 {
-   set_pl310_ctrl_reg(1);
+   omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1);
 }
 
 void v7_outer_cache_disable(void)
 {
-   set_pl310_ctrl_reg(0);
+   omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0);
 }
 #endif /* !CONFIG_SYS_L2CACHE_OFF */
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h 
b/arch/arm/include/asm/arch-omap4/sys_proto.h
index e19975efaf50..f30f86539130 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -37,7 +37,6 @@ void do_set_mux(u32 base, struct pad_conf_entry const *array, 
int size);
 void set_muxconf_regs_essential(void);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
-void set_pl310_ctrl_reg(u32 val);
 void setup_clocks_for_console(void);
 void prcm_init(void);
 void bypass_dpll(u32 const base);
@@ -57,4 +56,7 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 
reg_data);
 u32 warm_reset(void);
 void force_emif_self_refresh(void);
 void setup_warmreset_time(void);
+
+#define OMAP4_SERVICE_PL310_CONTROL_REG_SET0x102
+
 #endif
diff --git a/arch/arm/include/asm/omap_common.h 
b/arch/arm/include/asm/omap_common.h
index 323952f5f1b4..123c84ff9593 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -579,6 +579,8 @@ s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
 
 void usb_fake_mac_from_die_id(u32 *id);
 
+void omap_smc1(u32 service, u32 val);
+
 /* ABB */
 #define OMAP_ABB_NOMINAL_OPP   0
 #define OMAP_ABB_FAST_OPP  1
-- 
1.7.9.5

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Re: [U-Boot] [PATCH] mx6sabre: Do not enable UMS with SPL

Hi Tom,

On Mon, Mar 9, 2015 at 8:44 PM, Tom Rini tr...@konsulko.com wrote:
 On Mon, Mar 09, 2015 at 06:44:39PM -0300, Fabio Estevam wrote:

 From: Fabio Estevam fabio.este...@freescale.com

 Since commit ad8aae82b20ac6a (mx6sabre: Enable User Mass Storage) SPL 
 target
 does not boot anymore due to the increased spl image size.

 Only enable USB Mass Storage for the non-SPL target.

 Signed-off-by: Fabio Estevam fabio.este...@freescale.com

 Reviewed-by: Tom Rini tr...@konsulko.com

 Please do a follow up commit that makes use of the existing size checks
 to avoid this problem in the future, thanks!

Yes, it would be useful. Could you please point me to the existing
size checks function, so that I can learn about it?

Thanks,

Fabio Estevam
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Re: [U-Boot] [PATCH v3 2/8] lpc32xx: mtd: nand: add MLC NAND controller

2015-03-09 Thread Scott Wood

On Thu, 2015-03-05 at 07:46 +0100, Albert ARIBAUD (3ADEV) wrote:
 diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c 
 b/drivers/mtd/nand/lpc32xx_nand_mlc.c
 new file mode 100644
 index 000..cb23972
 --- /dev/null
 +++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c
 @@ -0,0 +1,589 @@
 +/*
 + * LPC32xx MLC NAND flash controller driver
 + *
 + * (C) Copyright 2014 3ADEV http://3adev.com
 + * Written by Albert ARIBAUD albert.arib...@3adev.fr
 + *
 + * SPDX-License-Identifier:  GPL-2.0+
 + *
 + * NOTE:
 + *
 + * The MLC NAND flash controller provides hardware Reed-Solomon ECC
 + * covering in- and out-of-band data together. Therefore, in- and out-
 + * of-band data must be written together in order to have a valid ECC.
 + *
 + * Consequently, pages with meaningful in-band data are written with
 + * blank (all-ones) out-of-band data and a valid ECC, and any later
 + * out-of-band data write will void the ECC.
 + *
 + * Therefore, code which reads such late-written out-of-band data
 + * should not rely on the ECC validity.
 + */

When are you expecting later out-of-band writes?

 +static struct lpc32xx_nand_mlc_registers *lpc32xx_nand_mlc_registers
 + = (struct lpc32xx_nand_mlc_registers *)MLC_NAND_BASE;

__iomem

 +unsigned int ctrl)
 +{
 + if (cmd == NAND_CMD_NONE)
 + return;
 +
 + if (ctrl  NAND_CLE)
 + writeb(cmd  0Xff, lpc32xx_nand_mlc_registers-cmd);
 + else if (ctrl  NAND_ALE)
 + writeb(cmd  0Xff, lpc32xx_nand_mlc_registers-addr);
 + else
 + return;
 +}

That last return is superfluous.

 +/**
 + * ECC layout -- this is needed whatever ECC mode we are using.
 + * In a 2KB (4*512B) page, R/S codes occupy 40 (4*10) bytes.
 + * To make U-Boot's life easier, we pack 'useable' OOB at the
 + * front and R/S ECC at the back.
 + */
 +
 +static struct nand_ecclayout lpc32xx_largepage_ecclayout = {
 + .eccbytes = 40,
 + .eccpos = {24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
 +34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
 +44, 45, 46, 47, 48, 48, 50, 51, 52, 53,
 +54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
 +},
 + .oobfree = {
 + {
 + .offset = 0,
 + .length = 24
 + },
 + }
 +};

Is offset zero really free?  Where does the bad block marker go?

 + for (i = 0; i  4; i++) {
 + /* start data input */
 + oob[6*i] = ((0xfe  i)  0xff);
 + oob[6*i+5] = ((0x7f  i)  0xff);
 + chip-cmdfunc(mtd, NAND_CMD_SEQIN, 0x200+0x210*i, page);
 + /* copy 6 non-ECC out-of-band bytes directly into NAND */
 + memcpy(lpc32xx_nand_mlc_registers-data, oob+6*i, 6);

Lots of magic numbers...

 + /* wait for NAND to return to ready state */
 + while (!(readl(lpc32xx_nand_mlc_registers-isr)
 +  ISR_NAND_READY))
 + ;

Timeout?

 + }
 + return 0;
 +}
 +
 +/**
 + * lpc32xx_waitfunc - wait until a command is done
 + * @mtd: MTD device structure
 + * @chip: NAND chip structure
 + *
 + * Wait for controller and FLASH to both be ready.
 + */
 +
 +static int lpc32xx_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
 +{
 + /* FIXME: put a time-out here */
 + int status;
 + /* wait until both controller and NAND are ready */
 + do {
 + status = readl(lpc32xx_nand_mlc_registers-isr);
 + } while ((status  (ISR_CONTROLLER_READY || ISR_NAND_READY))
 +  != (ISR_CONTROLLER_READY || ISR_NAND_READY));

Timeout?  Etc.

 +/*
 + * Initialize the controller
 + */
 +
 +int board_nand_init(struct nand_chip *nand)
 +{

It'd be nice if new NAND drivers used CONFIG_SYS_NAND_SELF_INIT.

 +
 + /* BBT options: read from last two pages, don't write */
 + nand-bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_LASTBLOCK
 + | NAND_BBT_SCANLASTPAGE | NAND_BBT_SCAN2NDPAGE
 + | NAND_BBT_WRITE;

Don't write?

 +#define LARGE_PAGE_SIZE 2048
 +
 +int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
 +{
 + unsigned int page = offs / LARGE_PAGE_SIZE;
 + unsigned int left = (size + LARGE_PAGE_SIZE - 1) / LARGE_PAGE_SIZE;

DIV_ROUND_UP()

 + while (left) {
 + if (read_single_page(dst, page) = 0) {
 + dst += LARGE_PAGE_SIZE;
 + page++;
 + left--;
 + }
 + }

No bad block skipping?

-Scott


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Re: [U-Boot] [PATCH] mx6sabre: Do not enable UMS with SPL

On Mon, Mar 9, 2015 at 9:02 PM, Tom Rini tr...@konsulko.com wrote:

 CONFIG_SPL_MAX_SIZE and CONFIG_SPL_MAX_BSS_SIZE or
 CONFIG_SPL_MAX_FOOTPRINT are what you want for i.MX6 and documented in
 README. I'm not quite sure of all the details on i.MX6 right now so I
 can't say for sure which group it falls into.  On TI ARMv7 parts for
 example we get access to DDR by the time we need BSS, so BSS is in DDR
 and our limit there is semi artificial but CONFIG_SPL_MAX_SIZE (since
 the binary is loaded into SRAM of a limited area) is not.  On some TI
 Davinci platforms we use CONFIG_SPL_MAX_FOOTPRINT since both BSS and the
 binary must be in a limited RAM area.

Thanks, Tom. I will take a look at these options.

Regards,

Fabio Estevam
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Re: [U-Boot] [PATCH] mx6sabre: Do not enable UMS with SPL

On Mon, Mar 09, 2015 at 08:52:52PM -0300, Fabio Estevam wrote:
 Hi Tom,
 
 On Mon, Mar 9, 2015 at 8:44 PM, Tom Rini tr...@konsulko.com wrote:
  On Mon, Mar 09, 2015 at 06:44:39PM -0300, Fabio Estevam wrote:
 
  From: Fabio Estevam fabio.este...@freescale.com
 
  Since commit ad8aae82b20ac6a (mx6sabre: Enable User Mass Storage) SPL 
  target
  does not boot anymore due to the increased spl image size.
 
  Only enable USB Mass Storage for the non-SPL target.
 
  Signed-off-by: Fabio Estevam fabio.este...@freescale.com
 
  Reviewed-by: Tom Rini tr...@konsulko.com
 
  Please do a follow up commit that makes use of the existing size checks
  to avoid this problem in the future, thanks!
 
 Yes, it would be useful. Could you please point me to the existing
 size checks function, so that I can learn about it?

CONFIG_SPL_MAX_SIZE and CONFIG_SPL_MAX_BSS_SIZE or
CONFIG_SPL_MAX_FOOTPRINT are what you want for i.MX6 and documented in
README. I'm not quite sure of all the details on i.MX6 right now so I
can't say for sure which group it falls into.  On TI ARMv7 parts for
example we get access to DDR by the time we need BSS, so BSS is in DDR
and our limit there is semi artificial but CONFIG_SPL_MAX_SIZE (since
the binary is loaded into SRAM of a limited area) is not.  On some TI
Davinci platforms we use CONFIG_SPL_MAX_FOOTPRINT since both BSS and the
binary must be in a limited RAM area.

-- 
Tom


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Re: [U-Boot] [PATCH] mx6sabre: Do not enable UMS with SPL

On Mon, Mar 09, 2015 at 06:44:39PM -0300, Fabio Estevam wrote:

 From: Fabio Estevam fabio.este...@freescale.com
 
 Since commit ad8aae82b20ac6a (mx6sabre: Enable User Mass Storage) SPL target
 does not boot anymore due to the increased spl image size.
 
 Only enable USB Mass Storage for the non-SPL target.
 
 Signed-off-by: Fabio Estevam fabio.este...@freescale.com

Reviewed-by: Tom Rini tr...@konsulko.com

Please do a follow up commit that makes use of the existing size checks
to avoid this problem in the future, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] qemu-ppce500: Add support for 64bit CCSR map

2015-03-09 Thread Scott Wood

On Sat, 2015-03-07 at 02:10 +0100, Alexander Graf wrote:
 QEMU 2.3 changes the address layout of the CCSR map in the PV ppce500 machine
 to reside in higher address space.
 
 Unfortunately, this exposed a glitch in u-boot for ppce500: While providing
 a function to dynamically evaluate the CCSR region's position in physical
 address space, we never used it. Plus we forgot to support 64bit physical
 addresses.
 
 This patch fixes that mishap, making u-boot work fine with latest QEMU again.
 
 Signed-off-by: Alexander Graf ag...@suse.de
 ---
  include/configs/qemu-ppce500.h |8 +++-
  1 file changed, 7 insertions(+), 1 deletion(-)

Reviewed-by: Scott Wood scottw...@freescale.com

-Scott


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[U-Boot] [PATCH 2/2] tegra: seaboard: Correct the gpio_request() call

Requesting a GPIO without a name is not supposed anymore. This causes the
request to fail. Add a name so that the serial console works on seaboard.

Signed-off-by: Simon Glass s...@chromium.org
---

 board/nvidia/seaboard/seaboard.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index 25480e4..2d07001 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -20,7 +20,7 @@
 void gpio_early_init_uart(void)
 {
/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
-   gpio_request(GPIO_PI3, NULL);
+   gpio_request(GPIO_PI3, uart_en);
gpio_direction_output(GPIO_PI3, 0);
 }
 #endif
-- 
2.2.0.rc0.207.ga3a616c

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[U-Boot] [PATCH 1/2] tegra: seaboard: Remove unused CONFIG_UART_DISABLE_GPIO

This CONFIG is not used, so drop it.

Signed-off-by: Simon Glass s...@chromium.org
---

 include/configs/seaboard.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index 5f77051..44daadc 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -27,9 +27,6 @@
 #define CONFIG_TEGRA_ENABLE_UARTD
 #define CONFIG_SYS_NS16550_COM1NV_PA_APB_UARTD_BASE
 
-/* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */
-#define CONFIG_UART_DISABLE_GPIO   GPIO_PI3
-
 #define CONFIG_MACH_TYPE   MACH_TYPE_SEABOARD
 
 #define CONFIG_BOARD_EARLY_INIT_F
-- 
2.2.0.rc0.207.ga3a616c

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[U-Boot] [PATCH] Vexpress64: Fix the compiling error when CONFIG_ARMV8_MULTIENTRY defined

2015-03-09 Thread fenghua

From: David Feng feng...@phytium.com.cn

CPU_RELEASE_ADDR should be defined when CONFIG_ARMV8_MULTIENTRY is used.

Signed-off-by: David Feng feng...@phytium.com.cn
---
 board/armltd/vexpress64/vexpress64.c |8 
 include/configs/vexpress_aemv8a.h|9 +
 2 files changed, 17 insertions(+)

diff --git a/board/armltd/vexpress64/vexpress64.c 
b/board/armltd/vexpress64/vexpress64.c
index de62864..bb6b5f6 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -22,6 +22,14 @@ int board_init(void)
 
 int dram_init(void)
 {
+#ifdef CONFIG_ARMV8_MULTIENTRY
+   /*
+* Clear spin table so that secondary processors
+* observe the correct value after waken up from wfe.
+*/
+   *(unsigned long *)CPU_RELEASE_ADDR = 0;
+#endif
+
gd-ram_size = PHYS_SDRAM_1_SIZE;
return 0;
 }
diff --git a/include/configs/vexpress_aemv8a.h 
b/include/configs/vexpress_aemv8a.h
index 810eef1..6fa651a 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -54,6 +54,15 @@
 /* Flat Device Tree Definitions */
 #define CONFIG_OF_LIBFDT
 
+#ifdef CONFIG_ARMV8_MULTIENTRY
+/* SMP Spin Table Definitions */
+#ifdef CONFIG_BASE_FVP
+#define CPU_RELEASE_ADDR   (CONFIG_SYS_SDRAM_BASE + 0x03f0)
+#else
+#define CPU_RELEASE_ADDR   (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+#endif
+#endif
+
 /* CS register bases for the original memory map. */
 #define V2M_PA_CS0 0x
 #define V2M_PA_CS1 0x1400
-- 
1.7.9.5


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Re: [U-Boot] [PATCH v6 3/6] dm: tegra: Enable driver model in SPL and adjust the GPIO driver

Hi Stephen,

On 9 March 2015 at 11:23, Stephen Warren swar...@wwwdotorg.org wrote:
 On 03/09/2015 11:04 AM, Simon Glass wrote:

 Hi Stephen,

 On 8 March 2015 at 15:00, Stephen Warren swar...@nvidia.com wrote:


 On 03/04/2015 03:16 PM, Tom Rini wrote:

 On Tue, Mar 03, 2015 at 08:02:59AM -0700, Simon Glass wrote:

 Use the full driver model GPIO and serial drivers in SPL now that
 these are supported. Since device tree is not available they will
 use platform data.

 Remove the special SPL GPIO function as it is no longer needed.

 This is all in one commit to maintain bisectability.

 Signed-off-by: Simon Glass s...@chromium.org


 Applied to u-boot/master, thanks!


 This patch breaks the serial console on at least NVIDIA Tegra
 Seaboard. LCD/usbkbd still work though. I can't test any other Tegra
 boards right now since I'm not at work. I wonder if the UART/SPI GPIO
 is at issue? That would be specific to this board.


 Could be - what do you have it set to? I should be able to give it
 another test sometime today and nut it out.


 I assume it must be set to GPIO control (especially since a GPIO-related
 change broke it). IIRC it came this way, and since the board boots from NAND
 and hence SPI isn't useful, I was going to change it to always UART.
 However, when I attempted to modify my other Seaboard (actually, Springbank)
 that way, I broke one of the pads on the PCB. Luckily that left the board in
 the always UART state that I wanted, even without any pull-ups/downs
 present. Anyway, I decided not to touch my other board for fear of breaking
 it in a way that didn't work at all!

Yes that's it. I must have tested it with the switch in the other
position. I sent a patch to fix it - the problem is that
gpio_request() needs a GPIO name now.

Regards,
Simon
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Re: [U-Boot] [PATCH 2/2] tegra: seaboard: Correct the gpio_request() call

Let's try this:

Reported-by: Stephen Warren swar...@nvidia.com


On 9 March 2015 at 19:12, Simon Glass s...@chromium.org wrote:
 Requesting a GPIO without a name is not supposed anymore. This causes the
 request to fail. Add a name so that the serial console works on seaboard.

 Signed-off-by: Simon Glass s...@chromium.org
 ---

  board/nvidia/seaboard/seaboard.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

 diff --git a/board/nvidia/seaboard/seaboard.c 
 b/board/nvidia/seaboard/seaboard.c
 index 25480e4..2d07001 100644
 --- a/board/nvidia/seaboard/seaboard.c
 +++ b/board/nvidia/seaboard/seaboard.c
 @@ -20,7 +20,7 @@
  void gpio_early_init_uart(void)
  {
 /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
 -   gpio_request(GPIO_PI3, NULL);
 +   gpio_request(GPIO_PI3, uart_en);
 gpio_direction_output(GPIO_PI3, 0);
  }
  #endif
 --
 2.2.0.rc0.207.ga3a616c

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Re: [U-Boot] [PATCH v2 00/12] Power(full) framework based on Driver Model

Hi Przemyslaw,

On 6 March 2015 at 07:10, Simon Glass s...@chromium.org wrote:
 Hi Przemyslaw,

 On 3 March 2015 at 09:24, Przemyslaw Marczak p.marc...@samsung.com wrote:
 Hello,
 Here is the second RFC version of the new PMIC framework.
 The changes made in this version are described below each commit.

 So again, a quick summary of:
 Framework:
 - Add new uclass types:
  -- UCLASS_PMIC(for device I/O)
  -- UCLASS_PMIC_REGULATOR (for common regulator ops)
 - Two uclass drivers for the above types
 - A common regulator operations - will easy cover the real devices design
 - V2: pmic: add read/write ops
 - V2: regulator: use regulator type as an argument - not as function name


 Drivers:
 - Introduce new PMIC API for drivers - now everything base on struct 
 udevice
 - Introduce Regulator Voltage descriptors and Operation Mode descriptors
   which are usually taken from the device tree (board dependent data)
 - Two uclass device drivers for MAX77686(PMIC+REGULATOR)
 - V2: don't use the 'hw union' from old pmic
 - V2: remove the files: pmic_i2c.c/pmic_spi.c - now using bus drivers
 - V2: cleanup the pmic_get() functions
 - V2: add pmic_io_dev() function for getting the proper I/O dev for devices
 - V2: add function calls for getting pmic devices platdata
 - V2: remove regulator type from regulator operations function calls,
   use type as an argument

 User Interface:
 - command pmic, unchanged functionality and ported to the driver model
 - command regulator(NEW) for safe regulator setup from commandline,
   - now can check output Voltage and operation mode of the regulators,
   - also can check the board Voltage limits and driver available modes
 - V2: simplify the code after remove the regulator type from function naming
 - V2: add on/off command

 Supported boards:
 - Odroid U3
 - V2: drop the commits for Trats2 - wait for charger and muic uclass types

 The assumptions of this work is:
 - Add new code to independent files
 - Keep two Frameworks as independent and without conflicts
 - Don't mix OLD/NEW Framework code - for the readability

 The future plans:
 - Add additional uclass types: MUIC, CHARGER, BATTERY, MFD and maybe more.
 - Port all U-Boot drivers to the new Framework
 - Remove the old drivers and the old PMIC Framework code

 Need help:
 - After merge this, it is welcome to help with driver porting
 - Every new driver should be tested on real hardware

 Best regards

 Przemyslaw Marczak (12):
   exynos5: fix build break by adding CONFIG_POWER
   dm: device: add function device_get_first_child_by_uclass_id()
   dm: pmic: add implementation of driver model pmic uclass
   dm: pmic: add implementation of driver model regulator uclass
   dm: pmic: new commands: pmic and regulator
   dm: pmic: add max77686 pmic driver
   dm: regulator: add max77686 regulator driver
   doc: driver-model: pmic and regulator uclass documentation
   dm: board:samsung: power_init_board: add requirement of CONFIG_DM_PMIC
   odroid: board: add support to dm pmic api
   odroid: dts: add 'voltage-regulators' description to max77686 node
   odroid: config: enable dm pmic, dm regulator and max77686 driver

  Makefile   |   1 +
  arch/arm/dts/exynos4412-odroid.dts | 249 -
  board/samsung/common/board.c   |   4 +-
  board/samsung/common/misc.c|   1 +
  board/samsung/odroid/odroid.c  |  52 +-
  configs/odroid_defconfig   |   1 -
  doc/driver-model/dm-pmic-framework.txt | 367 +
  drivers/core/device.c  |  15 +
  drivers/power/Makefile |   5 +-
  drivers/power/cmd_pmic.c   | 820 +
  drivers/power/pmic-uclass.c| 191 +++
  drivers/power/pmic/Makefile|   1 +
  drivers/power/pmic/max77686.c  | 102 
  drivers/power/pmic/pmic_max77686.c |   2 +-
  drivers/power/regulator-uclass.c   | 227 
  drivers/power/regulator/Makefile   |   8 +
  drivers/power/regulator/max77686.c | 926 
 +
  include/configs/exynos5-common.h   |   4 +
  include/configs/odroid.h   |   9 +-
  include/dm/device.h|  16 +
  include/dm/uclass-id.h |   4 +
  include/power/max77686_pmic.h  |  26 +-
  include/power/pmic.h   | 265 ++
  include/power/regulator.h  | 310 +++
  24 files changed, 3573 insertions(+), 33 deletions(-)
  create mode 100644 doc/driver-model/dm-pmic-framework.txt
  create mode 100644 drivers/power/cmd_pmic.c
  create mode 100644 drivers/power/pmic-uclass.c
  create mode 100644 drivers/power/pmic/max77686.c
  create mode 100644 drivers/power/regulator-uclass.c
  create mode 100644 drivers/power/regulator/Makefile
  create mode 100644 drivers/power/regulator/max77686.c
  create mode 100644 include/power/regulator.h

 This is an impressive pieces of work! It will be great to get these in.

Re: [U-Boot] [PATCH 1/2] tegra: seaboard: Remove unused CONFIG_UART_DISABLE_GPIO

On 03/09/2015 07:12 PM, Simon Glass wrote:
 This CONFIG is not used, so drop it.

The series,
Tested-by: Stephen Warren swar...@wwwdotorg.org
Acked-by: Stephen Warren swar...@wwwdotorg.org
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Re: [U-Boot] [linux-sunxi] Re: Basic A33 support including dram init available in my personal repo

2015-03-09 Thread Vishnu Patekar

Hello,
It's sensible work by Allwinner to release the dram code under GPLv2.

Now, we can have mainline u-boot support for A33 soon.

Hans,
Yes, I've very basic A33 dts created based on A23, still lot to do.

I'll send the u-boot patches soon. so that, you all can review it.

On Sun, Mar 8, 2015 at 5:33 AM, Siarhei Siamashka
siarhei.siamas...@gmail.com wrote:

On Sat, 07 Mar 2015 20:06:27 +0100
Hans de Goede hdego...@redhat.com wrote:

Hi,

On 02-03-15 11:25, Hans de Goede wrote:
Hi,

On 01-03-15 19:42, Vishnu Patekar wrote:
Allwinner A33 tablets comes with the libdram binary, fortunately I've
found the libdram code at
https://github.com/realthunder/a33_bootloader/tree/master/basic_loader/bsp/bsp_for_a67.

Ah, that is both good and bad...

I've integrated it with mainline u-boot, still lot to do to post it to
upstream

Integrated sounds as if you've copied pieces of code from the bsp code
you've found
into mainline u-boot. That is a big no no (this the bad part). AFAIK the
bsp code
does not come with a GPL license header, and Allwinner does not want to
release
these bits under the GPL for whatever reasons, a lot can be said about
this, but
in the end currently the bsp code is not GPL licensed, so we cannot use
it / copy
from it. There can be no discussion on this, when you're submitting this
upstream
you must not have any literal copied code in the patch you're sending
upstream.

You can use non copyrightable information from the bsp sources like
register
names and the initialization algorithm (IANAL), but you must 100% write
your own
code!

Ok, so something (to me) quite unexpected has happened and Allwinner has
just
released what seems to be ALL there boot0 code under the GPL, it can found
here:

https://github.com/allwinner-zh/bootloader/tree/master/basic_loader/boot0
https://github.com/allwinner-zh/bootloader/tree/master/basic_loader/bsp

Specifically interesting for the discussion at hand is:
https://github.com/allwinner-zh/bootloader/blob/master/basic_loader/bsp/bsp_for_a33/init_dram/mctl_hal.c

Which caries a GPL header now. This completely changes my story above,
whatever
you have (or had, sorry) was fine. It should still be cleaned up a bit, but
all
my worries about copy and pasting non GPL code are gone now.

It is strange that this has caught you by surprise, because you had been
informed about what is going on:

http://lists.denx.de/pipermail/u-boot/2015-March/207174.html

Basically, we need to thank David and Vishnu for negotiating this with
Allwinner (and this communication has been going on for some time
already), which resulted in a reasonable solution in the end. You have
also played your role well. My intervention was only needed to ensure
that Vishnu does not get discouraged by your response, which originally
sounded like only a single less than perfect solution was possible :-)

Yes, we are kinda lucky to have discovered this apparently leaked A33
dram code. I don't approve the actions of whoever is responsible for
this leak. But we ended up in a situation where the bad guys
(competitors?) have already got access to the code to learn all the
secrets, while the good guys (us) could not use the code because
of the missing license notices. And Allwinner just made a rational
decision how to deal with it (in the same way as this happened with
the previous code leaks). Having also the A23, A83T and A80 dram
code open sourced under the GPL license is very much appreciated.
It means that U-Boot can get full support for A83T and A80 too.

Special thanks to Vishu for not trying to hide the origin of the A33
dram code. I particularly like full transparency and honesty in
handling this case.

I'm still not completely happy about the presence of magic numbers all
over the place (for example, Rockchip sources for very similar dram
controllers have proper named identifiers for the hardware register
bitfields) and other code quality problems. In a prefect world, we
would also get full documentation for the dram controllers and the
errata lists. But even the current source code is enough to move
from the dead point.

--
Best regards,
Siarhei Siamashka
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Re: [U-Boot] [PATCH v2 01/22] sandbox: Update device tree 'reg' properties for I2C and SPI

On Fri, Mar 6, 2015 at 3:25 AM, Simon Glass s...@chromium.org wrote:
 We should have a size value for these. Add one in each case. This will
 be needed for PCI.

 Signed-off-by: Simon Glass s...@chromium.org
 ---

 Changes in v2:
 - Update root node #size=cells to 1 in this patch

  arch/sandbox/dts/sandbox.dts | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

 diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
 index 9ce31bf..d090ba8 100644
 --- a/arch/sandbox/dts/sandbox.dts
 +++ b/arch/sandbox/dts/sandbox.dts
 @@ -2,7 +2,7 @@

  / {
 #address-cells = 1;
 -   #size-cells = 0;
 +   #size-cells = 1;

 chosen {
 stdout-path = /serial;
 @@ -144,7 +144,7 @@
 i2c@0 {
 #address-cells = 1;
 #size-cells = 0;
 -   reg = 0;
 +   reg = 0 0;
 compatible = sandbox,i2c;
 clock-frequency = 40;
 eeprom@2c {
 @@ -161,7 +161,7 @@
 spi@0 {
 #address-cells = 1;
 #size-cells = 0;
 -   reg = 0;
 +   reg = 0 0;
 compatible = sandbox,spi;
 cs-gpios = 0, gpio_a 0;
 flash@0 {
 --

Reviewed-by: Bin Meng bmeng...@gmail.com
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Re: [U-Boot] [PATCH v2 04/22] dm: Add a new CPU init function which can use driver model

On Fri, Mar 6, 2015 at 3:25 AM, Simon Glass s...@chromium.org wrote:
 Since driver model is set up after arch_cpu_init(), that function cannot
 use drivers. Add a new arch_cpu_init_dm() function which is called
 immediately after driver model is ready, and can reference devices.

 This can be used to probe essential devices for the CPU.

 Signed-off-by: Simon Glass s...@chromium.org
 ---

 Changes in v2:
 - Add a new patch with a CPU init function which can use driver model

  common/board_f.c |  6 ++
  include/common.h | 11 +++
  2 files changed, 17 insertions(+)

 diff --git a/common/board_f.c b/common/board_f.c
 index 4d8b8a6..8bbece2 100644
 --- a/common/board_f.c
 +++ b/common/board_f.c
 @@ -787,6 +787,11 @@ __weak int reserve_arch(void)
 return 0;
  }

 +__weak int arch_cpu_init_dm(void)
 +{
 +   return 0;
 +}
 +
  static init_fnc_t init_sequence_f[] = {
  #ifdef CONFIG_SANDBOX
 setup_ram_buf,
 @@ -807,6 +812,7 @@ static init_fnc_t init_sequence_f[] = {
 fdtdec_check_fdt,
  #endif
 initf_dm,
 +   arch_cpu_init_dm,
  #if defined(CONFIG_BOARD_EARLY_INIT_F)
 board_early_init_f,
  #endif
 diff --git a/include/common.h b/include/common.h
 index 77c55c6..f95 100644
 --- a/include/common.h
 +++ b/include/common.h
 @@ -253,6 +253,17 @@ int update_flash_size(int flash_size);
  int arch_early_init_r(void);

  /**
 + * arch_cpu_init_dm() - init CPU after driver model is available
 + *
 + * This is called immediately after driver model is available before
 + * relocation. This is similar to arch_cpu_init() but is able to reference
 + * devices
 + *
 + * @return 0 if OK, -ve on error
 + */
 +int arch_cpu_init_dm(void);
 +
 +/**
   * Reserve all necessary stacks
   *
   * This is used in generic board init sequence in common/board_f.c. Each
 --

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Re: [U-Boot] [PATCH v2 06/22] Correct map_sysmem() logic in do_mem_mw()

On Fri, Mar 6, 2015 at 3:25 AM, Simon Glass s...@chromium.org wrote:
 This function does not unmap what it maps. Correct it.

 Signed-off-by: Simon Glass s...@chromium.org
 ---

 Changes in v2: None

  common/cmd_mem.c | 7 ---
  1 file changed, 4 insertions(+), 3 deletions(-)

 diff --git a/common/cmd_mem.c b/common/cmd_mem.c
 index bcb3ee3..855aa57 100644
 --- a/common/cmd_mem.c
 +++ b/common/cmd_mem.c
 @@ -165,7 +165,7 @@ static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int 
 argc, char * const argv[])
  #endif
 ulong   addr, count;
 int size;
 -   void *buf;
 +   void *buf, *start;
 ulong bytes;

 if ((argc  3) || (argc  4))
 @@ -197,7 +197,8 @@ static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int 
 argc, char * const argv[])
 }

 bytes = size * count;
 -   buf = map_sysmem(addr, bytes);
 +   start = map_sysmem(addr, bytes);
 +   buf = start;
 while (count--  0) {
 if (size == 4)
 *((u32 *)buf) = (u32)writeval;
 @@ -211,7 +212,7 @@ static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int 
 argc, char * const argv[])
 *((u8 *)buf) = (u8)writeval;
 buf += size;
 }
 -   unmap_sysmem(buf);
 +   unmap_sysmem(start);
 return 0;
  }

 --

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Re: [U-Boot] [PATCH v2 05/22] x86: Split up arch_cpu_init()

On Fri, Mar 6, 2015 at 3:25 AM, Simon Glass s...@chromium.org wrote:
 At present we do more in this function than we should. Split out the
 post-driver-model part into a separate function.

 Signed-off-by: Simon Glass s...@chromium.org
 ---

 Changes in v2:
 - Use the new arch_cpu_init_dm() function instead of something x86-specific

  arch/x86/cpu/ivybridge/cpu.c | 8 
  1 file changed, 8 insertions(+)

 diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
 index 5fd3753..e6ef481 100644
 --- a/arch/x86/cpu/ivybridge/cpu.c
 +++ b/arch/x86/cpu/ivybridge/cpu.c
 @@ -116,6 +116,14 @@ static void set_spi_speed(void)

  int arch_cpu_init(void)
  {
 +   post_code(POST_CPU_INIT);
 +   timer_set_base(rdtsc());
 +
 +   return x86_cpu_init_f();
 +}
 +
 +int arch_cpu_init_dm(void)
 +{
 const void *blob = gd-fdt_blob;
 struct pci_controller *hose;
 int node;
 --

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Re: [U-Boot] [linux-sunxi] Re: Basic A33 support including dram init available in my personal repo

Hi,

On Mon, Mar 9, 2015 at 4:39 PM, Vishnu Patekar
vishnupatekar0...@gmail.com wrote:
Hello,
It's sensible work by Allwinner to release the dram code under GPLv2.

Now, we can have mainline u-boot support for A33 soon.

Hans,
Yes, I've very basic A33 dts created based on A23, still lot to do.

About the dts, so far the memory maps look the same. I haven't
checked the clocks or interrupts, but I bet they are the same as
well.

Could we use an overlay over A23 with just the different pieces
overriden? Though they're not the same piece of silicon, they are
damn close. Maybe even the PIO is the same.

Maxime, any thoughts?

Regards
ChenYu

I'll send the u-boot patches soon. so that, you all can review it.

On Sun, Mar 8, 2015 at 5:33 AM, Siarhei Siamashka
siarhei.siamas...@gmail.com wrote:

On Sat, 07 Mar 2015 20:06:27 +0100
Hans de Goede hdego...@redhat.com wrote:

Hi,

On 02-03-15 11:25, Hans de Goede wrote:
Hi,

Ah, that is both good and bad...

I've integrated it with mainline u-boot, still lot to do to post it to
upstream

You can use non copyrightable information from the bsp sources like
register
names and the initialization algorithm (IANAL), but you must 100% write
your own
code!

Ok, so something (to me) quite unexpected has happened and Allwinner has
just
released what seems to be ALL there boot0 code under the GPL, it can found
here:

https://github.com/allwinner-zh/bootloader/tree/master/basic_loader/boot0
https://github.com/allwinner-zh/bootloader/tree/master/basic_loader/bsp

Specifically interesting for the discussion at hand is:
https://github.com/allwinner-zh/bootloader/blob/master/basic_loader/bsp/bsp_for_a33/init_dram/mctl_hal.c

Which caries a GPL header now. This completely changes my story above,
whatever
you have (or had, sorry) was fine. It should still be cleaned up a bit,
but all
my worries about copy and pasting non GPL code are gone now.

It is strange that this has caught you by surprise, because you had been
informed about what is going on:

http://lists.denx.de/pipermail/u-boot/2015-March/207174.html

Special thanks to Vishu for not trying to hide the origin of the A33
dram code. I particularly like full transparency and honesty in
handling this case.

--
Best regards,
Siarhei Siamashka

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Re: [U-Boot] [linux-sunxi] Re: Basic A33 support including dram init available in my personal repo

2015-03-09 Thread Vishnu Patekar

Yes,  except couple of additional clocks for A33, others seem to be
same as A23 including PIO.

I think, it's possible to overlay over A23.

On Mon, Mar 9, 2015 at 2:35 PM, Hans de Goede hdego...@redhat.com wrote:
 Hi,

 On 09-03-15 10:04, Chen-Yu Tsai wrote:

 Hi,

 On Mon, Mar 9, 2015 at 4:39 PM, Vishnu Patekar
 vishnupatekar0...@gmail.com wrote:

 Hello,
 It's sensible work by Allwinner to release the dram code under GPLv2.

 Now, we can have mainline u-boot support for A33 soon.

 Hans,
 Yes, I've very basic A33 dts created based on A23, still lot to do.


 About the dts, so far the memory maps look the same. I haven't
 checked the clocks or interrupts, but I bet they are the same as
 well.

 Could we use an overlay over A23 with just the different pieces
 overriden? Though they're not the same piece of silicon, they are
 damn close. Maybe even the PIO is the same.


 +1, I wanted to do / suggest the same myself.

 Regards,

 Hans
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Re: [U-Boot] [linux-sunxi] Re: Basic A33 support including dram init available in my personal repo

2015-03-09 Thread Hans de Goede


Hi,

On 09-03-15 10:04, Chen-Yu Tsai wrote:

Hi,

On Mon, Mar 9, 2015 at 4:39 PM, Vishnu Patekar
vishnupatekar0...@gmail.com wrote:

Hello,
It's sensible work by Allwinner to release the dram code under GPLv2.

Now, we can have mainline u-boot support for A33 soon.

Hans,
Yes, I've very basic A33 dts created based on A23, still lot to do.


About the dts, so far the memory maps look the same. I haven't
checked the clocks or interrupts, but I bet they are the same as
well.

Could we use an overlay over A23 with just the different pieces
overriden? Though they're not the same piece of silicon, they are
damn close. Maybe even the PIO is the same.


+1, I wanted to do / suggest the same myself.

Regards,

Hans
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Re: [U-Boot] [PATCH v2 07/22] fdt: Tighten up error handling in fdtdec_get_pci_addr()

On Fri, Mar 6, 2015 at 3:25 AM, Simon Glass s...@chromium.org wrote:
 This function returns -ENOENT when the property is missing (which the caller
 might forgive) and also when the property is present but incorrectly
 formatted (which many callers would like to report).

 Update the error return value to allow these different situations to be
 distinguished.

 Signed-off-by: Simon Glass s...@chromium.org
 ---

 Changes in v2:
 - Add -ve sign before ENXIO

  include/fdtdec.h | 4 +++-
  lib/fdtdec.c | 4 +++-
  2 files changed, 6 insertions(+), 2 deletions(-)

 diff --git a/include/fdtdec.h b/include/fdtdec.h
 index 21bd6bb..6944048 100644
 --- a/include/fdtdec.h
 +++ b/include/fdtdec.h
 @@ -327,7 +327,9 @@ fdt_addr_t fdtdec_get_addr_size(const void *blob, int 
 node,
   * @param type pci address type (FDT_PCI_SPACE_xxx)
   * @param prop_namename of property to find
   * @param addr returns pci address in the form of fdt_pci_addr
 - * @return 0 if ok, negative on error
 + * @return 0 if ok, -ENOENT if the property did not exist, -EINVAL if the
 + * format of the property was invalid, -ENXIO if the requested
 + * address type was not found
   */
  int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type,
 const char *prop_name, struct fdt_pci_addr *addr);
 diff --git a/lib/fdtdec.c b/lib/fdtdec.c
 index e47fa96..9212f03 100644
 --- a/lib/fdtdec.c
 +++ b/lib/fdtdec.c
 @@ -160,8 +160,10 @@ int fdtdec_get_pci_addr(const void *blob, int node, enum 
 fdt_pci_space type,
 }
 }

 -   if (i == num)
 +   if (i == num) {
 +   ret = -ENXIO;
 goto fail;
 +   }

 return 0;
 } else {
 --

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[U-Boot] [PATCH V2 1/2] usb: dwc2: fix aligned buffer usage

The original aligned_buffer usage:
a) Uselessly copied data into the aligned buffer even for IN
   transactions. Fix this my making the copy conditional.
b) Always programmed the HW to transfer to/from the start of the aligned
   buffer. This worked fine for OUT transactions since the memcpy copied
   the OUT data to this location too. However, for large IN transactions,
   since the copy from the aligned buffer to the client buffer was
   deferred until after all chunks were transferred. it resulted in each
   chunk's transfer over-writing the data for the first transfer. Fix
   this by copying IN data as soon as it's received.

Signed-off-by: Stephen Warren swar...@wwwdotorg.org
---
v2: Move all memcpy()s back into the per-chunk loop; we can't rely on
maxpacket being a multiple of 8-bytes, so we need to copy each chunk to
the aligned_buffer not aligned_buffer+done; the HW requires 8-byte
alignment for the DMA buffer.

 drivers/usb/host/dwc2.c | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 5a1c44a8fb75..05d21b7948f5 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -795,7 +795,9 @@ int chunk_msg(struct usb_device *dev, unsigned long pipe, 
int *pid, int in,
   (*pid  DWC2_HCTSIZ_PID_OFFSET),
   hc_regs-hctsiz);
 
-   memcpy(aligned_buffer, (char *)buffer + done, len - done);
+   if (!in)
+   memcpy(aligned_buffer, (char *)buffer + done, len);
+
writel((uint32_t)aligned_buffer, hc_regs-hcdma);
 
/* Set host channel enable after all other setup is complete. */
@@ -810,16 +812,16 @@ int chunk_msg(struct usb_device *dev, unsigned long pipe, 
int *pid, int in,
break;
}
 
-   done += xfer_len;
if (in) {
-   done -= sub;
+   xfer_len -= sub;
+   memcpy(buffer + done, aligned_buffer, xfer_len);
if (sub)
stop_transfer = 1;
}
-   } while ((done  len)  !stop_transfer);
 
-   if (done  in)
-   memcpy(buffer, aligned_buffer, done);
+   done += xfer_len;
+
+   } while ((done  len)  !stop_transfer);
 
writel(0, hc_regs-hcintmsk);
writel(0x, hc_regs-hcint);
-- 
1.9.1

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Re: [U-Boot] [PATCH] usb: dwc2: fix aligned buffer usage

On 03/07/2015 11:09 PM, Stephen Warren wrote:
 The original aligned_buffer usage:
 a) Uselessly copied data into the aligned buffer even for IN
transactions.
 b) Needlessly split the memcpy() into separate calls per chunk, rather
than doing it all at once, as it did for the post-transfer copy for
IN transactions.
 c) Always programmed the HW to transfer to/from the start of the aligned
buffer, rather than the location of the start of the current chunk.
This worked fine for OUT transactions since the memcpy copied the data
to this location. However, for large IN transactions, it resulted in
each transfer over-writing the data for the first transfer.
 
 This patch assumes that the USB maxpacket is at least 8, so that each
 chunk of the overall transfer is still aligned to the HW's 8-byte
 alignment requirement.

Hmm. Further investigation shows the maxpacket isn't restricted to nice
aligned values. For some reason I thought it was. I'll need to adjust
this patch. Time for sleep!
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Re: [U-Boot] Basic A33 support including dram init available in my personal repo

2015-03-09 Thread Hans de Goede


Hi,

On 02-03-15 11:25, Hans de Goede wrote:

Hi,

On 01-03-15 19:42, Vishnu Patekar wrote:

Allwinner A33 tablets comes with the libdram binary, fortunately I've
found the libdram code at
https://github.com/realthunder/a33_bootloader/tree/master/basic_loader/bsp/bsp_for_a67.


Ah, that is both good and bad...


I've integrated it with mainline u-boot, still lot to do to post it to upstream


Integrated sounds as if you've copied pieces of code from the bsp code you've 
found
into mainline u-boot. That is a big no no (this the bad part). AFAIK the bsp 
code
does not come with a GPL license header, and Allwinner does not want to release
these bits under the GPL for whatever reasons, a lot can be said about this, but
in the end currently the bsp code is not GPL licensed, so we cannot use it / 
copy
from it. There can be no discussion on this, when you're submitting this 
upstream
you must not have any literal copied code in the patch you're sending upstream.

You can use non copyrightable information from the bsp sources like register
names and the initialization algorithm (IANAL), but you must 100% write your own
code!


Ok, so something (to me) quite unexpected has happened and Allwinner has just
released what seems to be ALL there boot0 code under the GPL, it can found here:

https://github.com/allwinner-zh/bootloader/tree/master/basic_loader/boot0
https://github.com/allwinner-zh/bootloader/tree/master/basic_loader/bsp

Specifically interesting for the discussion at hand is:
https://github.com/allwinner-zh/bootloader/blob/master/basic_loader/bsp/bsp_for_a33/init_dram/mctl_hal.c

Which caries a GPL header now. This completely changes my story above, whatever
you have (or had, sorry) was fine. It should still be cleaned up a bit, but all
my worries about copy and pasting non GPL code are gone now.

Regards,

Hans
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Re: [U-Boot] [PATCH 2/4] sun7i: Add support for the Wits Pro A20 DKT board

On Sat, 2015-03-07 at 20:00 +0100, Hans de Goede wrote:
 Hi,
 
 On 07-03-15 15:05, Hans de Goede wrote:
  The Wits Pro A20 DKT is an A20 Development KiT with 1G RAM, 4G NAND, sdio 
  wifi,
  1Gbit ethernet, 1024x768 lcd screen with ft5x_ts touchscreen and a ton of
  IO connectors.
 
  Note there seem to be multiple sdcard slots on the board (4 in total), but
  other then mmc0 none of these are hooked up by default, there is a ton of
  dip-switches which likely allow hooking some of these up, but the 
  documentation
  of the board only describes the use of a fraction of them, so for now we
  only support mmc0.
 
  Also see: http://www.merrii.com/en/pla_d.asp?id=163
 
  Signed-off-by: Hans de Goede hdego...@redhat.com
 
 Ugh I forgot to update MAINTAINERS for this and the 2 other new boards
 (will I ever learn?). I will fix this in my personal tree.

;-)

With the 3 MAINTAINERS entries in the right places you can add
Acked-by: Ian Campbell i...@hellion.org.uk
to all three of them too.

Sigh to YA$PKB (Yet Another $FRUIT Pi Knockoff Board), can no one think
of an original name any more!

Ian.

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Re: [U-Boot] [linux-sunxi] Re: Basic A33 support including dram init available in my personal repo

2015-03-09 Thread Siarhei Siamashka

On Sat, 07 Mar 2015 20:06:27 +0100
Hans de Goede hdego...@redhat.com wrote:

Hi,

On 02-03-15 11:25, Hans de Goede wrote:
Hi,

Ah, that is both good and bad...

I've integrated it with mainline u-boot, still lot to do to post it to
upstream

Integrated sounds as if you've copied pieces of code from the bsp code
you've found
into mainline u-boot. That is a big no no (this the bad part). AFAIK the
bsp code
does not come with a GPL license header, and Allwinner does not want to
release
these bits under the GPL for whatever reasons, a lot can be said about
this, but
in the end currently the bsp code is not GPL licensed, so we cannot use it
/ copy
from it. There can be no discussion on this, when you're submitting this
upstream
you must not have any literal copied code in the patch you're sending
upstream.

You can use non copyrightable information from the bsp sources like register
names and the initialization algorithm (IANAL), but you must 100% write
your own
code!

Ok, so something (to me) quite unexpected has happened and Allwinner has just
released what seems to be ALL there boot0 code under the GPL, it can found
here:

https://github.com/allwinner-zh/bootloader/tree/master/basic_loader/boot0
https://github.com/allwinner-zh/bootloader/tree/master/basic_loader/bsp

Specifically interesting for the discussion at hand is:
https://github.com/allwinner-zh/bootloader/blob/master/basic_loader/bsp/bsp_for_a33/init_dram/mctl_hal.c

It is strange that this has caught you by surprise, because you had been
informed about what is going on:

http://lists.denx.de/pipermail/u-boot/2015-March/207174.html

Special thanks to Vishu for not trying to hide the origin of the A33
dram code. I particularly like full transparency and honesty in
handling this case.

--
Best regards,
Siarhei Siamashka
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Re: [U-Boot] [PATCH v4 00/14] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix

On Fri, 2015-02-27 at 14:27 +0100, Jan Kiszka wrote:

 CC: Ian Campbell i...@hellion.org.uk

I've been running with these on my Jetson (and booting Xen on top) just
fine. So, FWIW:

Tested-by: Ian Campbell i...@hellion.org.uk

Cheers,
Ian.

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[U-Boot] [PATCH V2 2/2] usb: dwc2: remove restriction on buffer length

Each USB transfer is split up into chunks that are held in an aligned
buffer. This imposes a limit on the size of each chunk, but no limit on
the total size of transferred data. Fix the logic in chunk_msg() not to
reject large transfers, but simply take the size of the aligned buffer
into account when calculating the chunk size.

Signed-off-by: Stephen Warren swar...@wwwdotorg.org
---
v2: New patch.

 drivers/usb/host/dwc2.c | 12 +++-
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 05d21b7948f5..e370d29ffc8e 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -756,24 +756,18 @@ int chunk_msg(struct usb_device *dev, unsigned long pipe, 
int *pid, int in,
debug(%s: msg: pipe %lx pid %d in %d len %d\n, __func__, pipe, *pid,
  in, len);
 
-   if (len  DWC2_DATA_BUF_SIZE) {
-   printf(%s: %d is more then available buffer size (%d)\n,
-  __func__, len, DWC2_DATA_BUF_SIZE);
-   dev-status = 0;
-   dev-act_len = 0;
-   return -EINVAL;
-   }
-
do {
/* Initialize channel */
dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep, in, eptype,
max);
 
xfer_len = len - done;
-   /* Make sure that xfer_len is a multiple of max packet size. */
if (xfer_len  CONFIG_DWC2_MAX_TRANSFER_SIZE)
xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1;
+   if (xfer_len  DWC2_DATA_BUF_SIZE)
+   xfer_len = DWC2_DATA_BUF_SIZE - max + 1;
 
+   /* Make sure that xfer_len is a multiple of max packet size. */
if (xfer_len  0) {
num_packets = (xfer_len + max - 1) / max;
if (num_packets  CONFIG_DWC2_MAX_PACKET_COUNT) {
-- 
1.9.1

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Re: [U-Boot] [PATCH] sunxi: Add support for the Forfun Q88DB tablet

On Tue, 2015-03-03 at 22:45 +0100, Jens Lucius wrote:
 The Forfun Q88DB is an A13 tablet in the common Q8 format.
 
 Features are 512MB RAM, 4GB NAND, 7 Display, RTL8188 Wifi, 2 cameras.
 
 For more details see: http://linux-sunxi.org/Forfun_Q88DB
 
 Signed-off-by: Jens Lucius i...@jenslucius.com

Applied to u-boot-sunxi#next, thanks.


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Re: [U-Boot] [PATCH 1/4] sunxi: video: Fix VIDEO_LCD_PANEL_I2C being enabled by default

On Sat, 2015-03-07 at 15:04 +0100, Hans de Goede wrote:
 Fix a type in board/sunxi/Kconfig which caused VIDEO_LCD_PANEL_I2C to be

typo

 +#define CONFIG_VIDEO_LCD_I2C_BUS 1 /* NA, but necessary to compile */

Hrm, should the usage sites not be either ifdef'd or excluded at the
Makefile level when VIDEO_LCD_PANEL_I2C is disabled?

The only use is in
if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) {
unsigned int orig_i2c_bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_VIDEO_LCD_I2C_BUS);
i2c_reg_write(0x5c, 0x04, 0x42); /* Turn on the LCD */
i2c_set_bus_num(orig_i2c_bus);
}

Is the issue that the IS_ENABLED statically false but the compiler still
wants the contents to be valid?

How about a helper set_video_i2c_bus or some such which can be a nop if
CONFIG_VIDEO_LCD_I2C_BUS is not defined, which would keep the ifdef out
of this code?

Or at least #define it to some obviously bogus value (e.g. ~0UL).

Ian.

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[U-Boot] [PATCH 1/3] sunxi: axp221: Add VBUS detection support

Some of the AXP PMICs support VBUS detection, i.e. checking whether
VBUS power input is available and usable (supplied by an external
source). A few boards use this instead of a separate GPIO to detect
VBUS on USB OTG.

Signed-off-by: Chen-Yu Tsai w...@csie.org
---
 drivers/power/axp221.c | 16 
 include/axp221.h   |  7 +++
 2 files changed, 23 insertions(+)

diff --git a/drivers/power/axp221.c b/drivers/power/axp221.c
index 3e07f23..c2c3988 100644
--- a/drivers/power/axp221.c
+++ b/drivers/power/axp221.c
@@ -385,6 +385,22 @@ int axp221_get_sid(unsigned int *sid)
return 0;
 }
 
+int axp_get_vbus(void)
+{
+   int ret;
+   u8 val;
+
+   ret = axp221_init();
+   if (ret)
+   return ret;
+
+   ret = pmic_bus_read(AXP221_POWER_STATUS, val);
+   if (ret)
+   return ret;
+
+   return (val  AXP221_POWER_STATUS_VBUS_USABLE) ? 1 : 0;
+}
+
 static int axp_drivebus_setup(void)
 {
int ret;
diff --git a/include/axp221.h b/include/axp221.h
index a20e25c..be6058e 100644
--- a/include/axp221.h
+++ b/include/axp221.h
@@ -14,6 +14,9 @@
 #define AXP223_RUNTIME_ADDR 0x2d
 
 /* Page 0 addresses */
+#define AXP221_POWER_STATUS0x00
+#define AXP221_POWER_STATUS_VBUS_AVAIL (1  5)
+#define AXP221_POWER_STATUS_VBUS_USABLE(1  4)
 #define AXP221_CHIP_ID 0x03
 #define AXP221_OUTPUT_CTRL10x10
 #define AXP221_OUTPUT_CTRL1_DCDC0_EN   (1  0)
@@ -59,6 +62,9 @@
 /* Page 1 addresses */
 #define AXP221_SID 0x20
 
+/* We support vbus detection */
+#define AXP_VBUS_DETECT
+
 /* We support drivebus control */
 #define AXP_DRIVEBUS
 
@@ -77,5 +83,6 @@ int axp221_set_aldo3(unsigned int mvolt);
 int axp221_set_eldo(int eldo_num, unsigned int mvolt);
 int axp221_init(void);
 int axp221_get_sid(unsigned int *sid);
+int axp_get_vbus(void);
 int axp_drivebus_enable(void);
 int axp_drivebus_disable(void);
-- 
2.1.4

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[U-Boot] [PATCH 3/3] sunxi: Ippo_q8h defconfigs: Enable otg vbus detection using AXP223 PMIC

Use the AXP223 PMIC to detect VBUS for musb otg support.

Signed-off-by: Chen-Yu Tsai w...@csie.org
---
 configs/Ippo_q8h_v1_2_defconfig | 1 +
 configs/Ippo_q8h_v5_defconfig   | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/Ippo_q8h_v1_2_defconfig b/configs/Ippo_q8h_v1_2_defconfig
index 192a461..9b0d0dd 100644
--- a/configs/Ippo_q8h_v1_2_defconfig
+++ b/configs/Ippo_q8h_v1_2_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_EXTRA_OPTIONS=CONS_INDEX=5
 CONFIG_FDTFILE=sun8i-a23-ippo-q8h-v1.2.dtb
 CONFIG_USB_MUSB_SUNXI=y
 CONFIG_USB0_VBUS_PIN=axp_drivebus
+CONFIG_USB0_VBUS_DET=axp_vbus_detect
 
CONFIG_VIDEO_LCD_MODE=x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0
 CONFIG_VIDEO_LCD_DCLK_PHASE=0
 CONFIG_VIDEO_LCD_POWER=PH7
diff --git a/configs/Ippo_q8h_v5_defconfig b/configs/Ippo_q8h_v5_defconfig
index 4786202..5bc90ce 100644
--- a/configs/Ippo_q8h_v5_defconfig
+++ b/configs/Ippo_q8h_v5_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_EXTRA_OPTIONS=CONS_INDEX=5
 CONFIG_FDTFILE=sun8i-a23-ippo-q8h-v5.dtb
 CONFIG_USB_MUSB_SUNXI=y
 CONFIG_USB0_VBUS_PIN=axp_drivebus
+CONFIG_USB0_VBUS_DET=axp_vbus_detect
 
CONFIG_VIDEO_LCD_MODE=x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:168,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0
 CONFIG_VIDEO_LCD_DCLK_PHASE=0
 CONFIG_VIDEO_LCD_POWER=PH7
-- 
2.1.4

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[U-Boot] [PATCH 2/3] sunxi: musb: Support checking VBUS using AXP221 PMIC

This enables the musb glue layer to use the AXP221's VBUS detection
function to check for VBUS. This fixes otg support on the A23 q8h
tablets.

Note that u-boot never calls musb_shutdown(), so once VBUS is enabled,
it is never disabled until the system is powered off, or the OS does
so. This can be used to our advantage to keep VBUS powered into the
OS, where support for AXP221 is not available yet.

Fixes: 52defe8f6570 (sunxi: musb: Check Vbus-det before enabling otg port 
power)
Signed-off-by: Chen-Yu Tsai w...@csie.org
---

A large portion of this patch is whitespace changes.

---
 drivers/usb/musb-new/sunxi.c | 52 
 1 file changed, 38 insertions(+), 14 deletions(-)

diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index fe45db1..4d8c15a 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -27,6 +27,15 @@
 #include asm-generic/gpio.h
 #include linux-compat.h
 #include musb_core.h
+#ifdef CONFIG_AXP152_POWER
+#include axp152.h
+#endif
+#ifdef CONFIG_AXP209_POWER
+#include axp209.h
+#endif
+#ifdef CONFIG_AXP221_POWER
+#include axp221.h
+#endif
 
 /**
  **
@@ -228,29 +237,44 @@ static int sunxi_musb_init(struct musb *musb)
 
if (is_host_enabled(musb)) {
int vbus_det = sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET);
-   if (vbus_det == -1) {
-   eprintf(Error invalid Vusb-det pin\n);
-   return -EINVAL;
-   }
 
-   err = gpio_request(vbus_det, vbus0_det);
-   if (err)
-   return err;
+#ifdef AXP_VBUS_DETECT
+   if (!strcmp(CONFIG_USB0_VBUS_DET, axp_vbus_detect)) {
+   err = axp_get_vbus();
+   if (err  0)
+   return err;
+   } else {
+#endif
+   if (vbus_det == -1) {
+   eprintf(Error invalid Vusb-det pin\n);
+   return -EINVAL;
+   }
+
+   err = gpio_request(vbus_det, vbus0_det);
+   if (err)
+   return err;
+
+   err = gpio_direction_input(vbus_det);
+   if (err) {
+   gpio_free(vbus_det);
+   return err;
+   }
+
+   err = gpio_get_value(vbus_det);
+   if (err) {
+   gpio_free(vbus_det);
+   return -EIO;
+   }
 
-   err = gpio_direction_input(vbus_det);
-   if (err) {
gpio_free(vbus_det);
-   return err;
+#ifdef AXP_VBUS_DETECT
}
+#endif
 
-   err = gpio_get_value(vbus_det);
if (err) {
eprintf(Error: A charger is plugged into the OTG\n);
-   gpio_free(vbus_det);
return -EIO;
}
-
-   gpio_free(vbus_det);
}
 
err = sunxi_usbc_request_resources(0);
-- 
2.1.4

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[U-Boot] [PATCH 0/3] sunxi: Ippo_q8h: Enable OTG VBUS detection using AXP223

Hi Hans,

This series fixes otg support on the A23 q8h tablets. It adds support
for the AXP's (AXP221/223 for now) VBUS detection function.

I've tested this with a USB wireless keyboard dongle, which works fine.
More importantly, I'm using this and your mainline kernel musb work plus
a few A23 dts patches to get musb working on my q8h tablet in host mode.
I have an ethernet dongle plugged in, which works reasonably well.

Note that U-Boot never calls musb_shutdown() to do proper cleanup, like
disabling VBUS, so the current state carries on into Linux.


Regards
ChenYu


Chen-Yu Tsai (3):
  sunxi: axp221: Add VBUS detection support
  sunxi: musb: Support checking VBUS using AXP221 PMIC
  sunxi: Ippo_q8h defconfigs: Enable otg vbus detection using AXP223
PMIC

 configs/Ippo_q8h_v1_2_defconfig |  1 +
 configs/Ippo_q8h_v5_defconfig   |  1 +
 drivers/power/axp221.c  | 16 +
 drivers/usb/musb-new/sunxi.c| 52 ++---
 include/axp221.h|  7 ++
 5 files changed, 63 insertions(+), 14 deletions(-)

-- 
2.1.4

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[U-Boot] [PATCH 02/14] sandbox: Move CONFIG_SYS_VSNPRINTF to Kconfig

Move this over to Kconfig and tidy up.

Signed-off-by: Simon Glass s...@chromium.org
---

 arch/x86/Kconfig | 3 +++
 configs/sandbox_defconfig| 1 +
 include/configs/sandbox.h| 2 --
 include/configs/x86-common.h | 1 -
 lib/Kconfig  | 9 +
 5 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 78a0532..2deadb2 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -7,6 +7,9 @@ config SYS_ARCH
 config USE_PRIVATE_LIBGCC
default y
 
+config SYS_VSNPRINTF
+   default y
+
 choice
prompt Target select
 
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 15d13b5..a6c3252 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -14,3 +14,4 @@ CONFIG_CROS_EC_KEYB=y
 CONFIG_CMD_CROS_EC=y
 CONFIG_BOOTSTAGE=y
 CONFIG_SANDBOX_GPIO=y
+CONFIG_SYS_VSNPRINTF=y
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index a880acb..8d96999 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -46,8 +46,6 @@
 #define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_MD5SUM
 
-#define CONFIG_SYS_VSNPRINTF
-
 #define CONFIG_CMD_GPIO
 
 #define CONFIG_CMD_GPT
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index 75108a9..d89fdca 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -16,7 +16,6 @@
  * (easy to change)
  */
 #define CONFIG_SHOW_BOOT_PROGRESS
-#define CONFIG_SYS_VSNPRINTF
 #define CONFIG_ZBOOT_32
 #define CONFIG_PHYSMEM
 #define CONFIG_DISPLAY_BOARDINFO_LATE
diff --git a/lib/Kconfig b/lib/Kconfig
index c9d2767..d7fd219 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -27,6 +27,15 @@ config SYS_HZ
  get_timer() must operate in milliseconds and this option must be
  set to 1000.
 
+config SYS_VSNPRINTF
+   bool Enable safe version of sprintf()
+   help
+ Since sprintf() can overflow its buffer, it is common to use
+ snprintf() instead, which knows the buffer size and can avoid
+ overflow. However, this does increase code size slightly (for
+ Thumb-2, about 420 bytes). Enable this option for safety when
+ using sprintf() with data you do not control.
+
 source lib/rsa/Kconfig
 
 menu Hashing Support
-- 
2.2.0.rc0.207.ga3a616c

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[U-Boot] [PATCH 08/14] sandbox: exynos: Move CONFIG_SOUND to Kconfig

Move this over to Kconfig and tidy up.

Signed-off-by: Simon Glass s...@chromium.org
---

 configs/arndale_defconfig   |  1 +
 configs/sandbox_defconfig   |  1 +
 configs/smdk5250_defconfig  |  1 +
 configs/snow_defconfig  |  1 +
 drivers/sound/Kconfig   | 11 +++
 include/configs/exynos5250-common.h |  1 -
 include/configs/sandbox.h   |  1 -
 7 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig
index fc30508..934ffed 100644
--- a/configs/arndale_defconfig
+++ b/configs/arndale_defconfig
@@ -3,3 +3,4 @@ CONFIG_SPL=y
 +S:CONFIG_ARCH_EXYNOS=y
 +S:CONFIG_TARGET_ARNDALE=y
 CONFIG_DEFAULT_DEVICE_TREE=exynos5250-arndale
+CONFIG_SOUND=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 30b3548..c9d24d9 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -20,3 +20,4 @@ CONFIG_SYS_I2C_SANDBOX=y
 CONFIG_SANDBOX_SPI=y
 CONFIG_SPI_FLASH_SANDBOX=y
 CONFIG_TPM_TIS_SANDBOX=y
+CONFIG_SOUND=y
diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig
index 9b76d0d..9c73cee 100644
--- a/configs/smdk5250_defconfig
+++ b/configs/smdk5250_defconfig
@@ -3,3 +3,4 @@ CONFIG_SPL=y
 +S:CONFIG_ARCH_EXYNOS=y
 +S:CONFIG_TARGET_SMDK5250=y
 CONFIG_DEFAULT_DEVICE_TREE=exynos5250-smdk5250
+CONFIG_SOUND=y
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index 353ddb0..19c150b 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -8,3 +8,4 @@ CONFIG_DM_CROS_EC=y
 CONFIG_CROS_EC_I2C=y
 CONFIG_CROS_EC_KEYB=y
 CONFIG_CMD_CROS_EC=y
+CONFIG_SOUND=y
diff --git a/drivers/sound/Kconfig b/drivers/sound/Kconfig
index e69de29..599edae 100644
--- a/drivers/sound/Kconfig
+++ b/drivers/sound/Kconfig
@@ -0,0 +1,11 @@
+config SOUND
+   bool Enable sound support
+   help
+ Support making sounds through an audio codec. This is normally a
+ beep at a chosen frequency for a selected length of time. However
+ the drivers support playing arbitrary sound samples using a
+ PCM interface.
+
+ Note: At present the sound setup is somewhat tangled up in that the
+ audio codecs are called from the sound-i2s code. This could be
+ converted to driver model.
diff --git a/include/configs/exynos5250-common.h 
b/include/configs/exynos5250-common.h
index ae0e5ff..e5935b6 100644
--- a/include/configs/exynos5250-common.h
+++ b/include/configs/exynos5250-common.h
@@ -31,7 +31,6 @@
 /* Sound */
 #define CONFIG_CMD_SOUND
 #ifdef CONFIG_CMD_SOUND
-#define CONFIG_SOUND
 #define CONFIG_I2S_SAMSUNG
 #define CONFIG_I2S
 #define CONFIG_SOUND_MAX98095
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 4c21608..47d41d7 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -139,7 +139,6 @@
 #define CONFIG_ARCH_EARLY_INIT_R
 #define CONFIG_BOARD_LATE_INIT
 
-#define CONFIG_SOUND
 #define CONFIG_SOUND_SANDBOX
 #define CONFIG_CMD_SOUND
 
-- 
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[U-Boot] [PATCH 12/14] sandbox: exynos: Move CONFIG_SOUND_MAX98095 to Kconfig

Move this over to Kconfig and tidy up.

Signed-off-by: Simon Glass s...@chromium.org
---

 configs/arndale_defconfig   | 1 +
 configs/smdk5250_defconfig  | 1 +
 drivers/sound/Kconfig   | 8 
 include/configs/exynos5250-common.h | 1 -
 4 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig
index 19f51fe..b176c8f 100644
--- a/configs/arndale_defconfig
+++ b/configs/arndale_defconfig
@@ -7,3 +7,4 @@ CONFIG_SOUND=y
 CONFIG_CMD_SOUND=y
 CONFIG_I2S=y
 CONFIG_I2S_SAMSUNG=y
+CONFIG_SOUND_MAX98095=y
diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig
index 35b8c13..bf2e4de 100644
--- a/configs/smdk5250_defconfig
+++ b/configs/smdk5250_defconfig
@@ -7,3 +7,4 @@ CONFIG_SOUND=y
 CONFIG_CMD_SOUND=y
 CONFIG_I2S=y
 CONFIG_I2S_SAMSUNG=y
+CONFIG_SOUND_MAX98095=y
diff --git a/drivers/sound/Kconfig b/drivers/sound/Kconfig
index 1b97af0..cfc75cb 100644
--- a/drivers/sound/Kconfig
+++ b/drivers/sound/Kconfig
@@ -28,3 +28,11 @@ config I2S_SAMSUNG
  using one of the available audio codec drivers. Enabling this
  option provides an implementation for sound_init() and
  sound_play().
+
+config SOUND_MAX98095
+   bool Support Maxim max98095 audio codec
+   depends on I2S_SAMSUNG
+   help
+ Enable the max98095 audio codec. This is connected via I2S for
+ audio data and I2C for codec control. At present it only works
+ with the Samsung I2S driver.
diff --git a/include/configs/exynos5250-common.h 
b/include/configs/exynos5250-common.h
index 895d6e1..79a7adf 100644
--- a/include/configs/exynos5250-common.h
+++ b/include/configs/exynos5250-common.h
@@ -30,7 +30,6 @@
 
 /* Sound */
 #ifdef CONFIG_CMD_SOUND
-#define CONFIG_SOUND_MAX98095
 #define CONFIG_SOUND_WM8994
 #endif
 
-- 
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Re: [U-Boot] [U-Boot, v2, 06/24] board/BuR/tseries: Enable HW-Watchdog

On Tue, Feb 03, 2015 at 01:22:28PM +0100, Hannes Petermaier wrote:

 Signed-off-by: Hannes Petermaier oe5...@oevsv.at

Applied to u-boot/master, thanks!

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Re: [U-Boot] spl: fix calling spl export .. more than once

On Tue, Feb 24, 2015 at 07:04:38AM +0100, Heiko Schocher wrote:

 running spl export ... more than once fails with:
 
 Trying to execute a command out of order
 Trying to execute a command out of order
 Trying to execute a command out of order
 Trying to execute a command out of order
 Trying to execute a command out of order
 Trying to execute a command out of order
 ERROR prep subcommand failed!
 Subcommand failed
 
 reason is commmit:
 35fc84fa1f: Refactor the bootm command to reduce code duplication
 
 It used state != BOOTM_STATE_START but state is a bitfield, so
 check if the bit BOOTM_STATE_START is not set. With this fix,
 spl export ... can called more than once ...
 
 Signed-off-by: Heiko Schocher h...@denx.de
 Reviewed-by: Simon Glass s...@chromium.org

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v2, 09/24] board/BuR/tseries: Change pinmux for GPIO2_28 from GPIO to PWM-Timeroutput

On Tue, Feb 03, 2015 at 01:22:31PM +0100, Hannes Petermaier wrote:

 From now we use this pin for the Brightness regulation from LED-Backlight.
 
 Signed-off-by: Hannes Petermaier oe5...@oevsv.at

Applied to u-boot/master, thanks!

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[U-Boot] [PATCH 06/14] sandbox: Move CONFIG_SPI_FLASH_SANDBOX to Kconfig

Move this over to Kconfig and tidy up.

Signed-off-by: Simon Glass s...@chromium.org
---

 configs/sandbox_defconfig |  1 +
 drivers/mtd/spi/Kconfig   | 10 ++
 drivers/spi/Kconfig   |  2 +-
 include/configs/sandbox.h |  1 -
 4 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 0e3cb7f..2383b77 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -18,3 +18,4 @@ CONFIG_SYS_VSNPRINTF=y
 CONFIG_SANDBOX_SERIAL=y
 CONFIG_SYS_I2C_SANDBOX=y
 CONFIG_SANDBOX_SPI=y
+CONFIG_SPI_FLASH_SANDBOX=y
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 2dc46b4..176979b 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -12,3 +12,13 @@ config DM_SPI_FLASH
  during the transition parent. SPI and SPI flash must be
  enabled together (it is not possible to use driver model
  for one and not the other).
+
+config SPI_FLASH_SANDBOX
+   bool Support sandbox SPI flash device
+   depends on SANDBOX  DM_SPI_FLASH
+   help
+ Since sandbox cannot access real devices, an emulation mechanism is
+ provided instead. Drivers can be connected up to the sandbox SPI
+ bus (see CONFIG_SANDBOX_SPI) and SPI traffic will be routed to this
+ device. Typically the contents of the emulated SPI flash device is
+ stored in a file on the host filesystem.
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index c50d7ba..c4c112c 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -11,7 +11,7 @@ config DM_SPI
  typically use driver-private data instead of extending the
  spi_slave structure.
 
-config CONFIG_SANDBOX_SPI
+config SANDBOX_SPI
bool Sandbox SPI driver
depends on SANDBOX  DM
help
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index fddb810a..d6af4e9 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -84,7 +84,6 @@
 #define CONFIG_SPI_FLASH_EON
 #define CONFIG_SPI_FLASH_GIGADEVICE
 #define CONFIG_SPI_FLASH_MACRONIX
-#define CONFIG_SPI_FLASH_SANDBOX
 #define CONFIG_SPI_FLASH_SPANSION
 #define CONFIG_SPI_FLASH_SST
 #define CONFIG_SPI_FLASH_STMICRO
-- 
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Re: [U-Boot] omap: gpmc: 'nandecc sw' can use HAM1 or BCH8

On Wed, Feb 18, 2015 at 11:25:11AM -0800, Ash Charles wrote:

 The 'nandecc sw' command selects a software-based error correction
 algorithm.  By default, this is OMAP_ECC_HAM1_CODE_SW but some
 platforms use OMAP_ECC_BCH8_CODE_HW_DETECTION_SW as their
 software-based correction algorithm.  Allow a user to be specific e.g.
  # nandecc sw hamming|bch8
 where 'hamming' is still the default.
 
 Note: we don't just use CONFIG_NAND_OMAP_ECCSCHEME as it might be set
   to a hardware-based ECC scheme---a little strange when the user
   has requested 'sw' ECC.
 
 Signed-off-by: Ash Charles ashchar...@gmail.com

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH] README: remove description about driver model configuration options

On 25 February 2015 at 18:04, Simon Glass s...@chromium.org wrote:
 On 25 February 2015 at 00:54, Masahiro Yamada yamad...@jp.panasonic.com 
 wrote:
 All the DM-related configuration options are described in Kconfig
 helps.  They should not be duplicated in README.

 Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
 ---

  README | 113 
 -
  1 file changed, 113 deletions(-)

 Acked-by: Simon Glass s...@chromium.org

 (should we have a script to generate docs for all of Kconfig?)

Applied to u-boot-dm, thanks!
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Re: [U-Boot] gpt: support random UUIDs without setting environment variables

On Mon, Jan 26, 2015 at 09:44:18AM -0600, Rob Herring wrote:

 Currently, an environment variable must be used to store the randomly
 generated UUID for each partition. This is not necessary, so make storing
 the UUID optional. Now passing uuid_disk and uuid are optional when random
 UUIDs are enabled.
 
 Signed-off-by: Rob Herring r...@kernel.org
 Acked-by: Przemyslaw Marczak p.marc...@samsung.com

Applied to u-boot/master, thanks!

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Re: [U-Boot] use ASM_NL instead of '; ' for assembler new line character in the macro

On Thu, Feb 19, 2015 at 06:51:27PM +0300, Alexey Brodkin wrote:

 From: Chen Gang gang.chen.5...@gmail.com
 
 For some assemblers, they use another character as newline in a macro
 (e.g. arc uses '`'), so for generic assembly code, need use ASM_NL (a
 macro) instead of ';' for it.
 
 Basically this is the same patch as applied to Linux kernel -
 http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/include/linux/linkage.h?id=9df62f054406992ce41ec4558fca6a0fa56fffeb
 
 but modified a bit to fit in U-Boot.
 
 Signed-off-by: Chen Gang gang.chen.5...@gmail.com
 Signed-off-by: Alexey Brodkin abrod...@synopsys.com
 Cc: Masahiro Yamada yamad...@jp.panasonic.com
 Cc: Simon Glass s...@chromium.org
 Cc: Tom Rini tr...@ti.com

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v2, 20/24] board/BuR/kwb: Form a bootline for vxWorks