[U-Boot] [PATCH] boards/t2080rdb: update ddr frequency from 1600MT/s to 1867MT/s
T2080RDB RevC uses new SODIMM 1867MT/s instead of previous 1600MT/s.
So update RCW to support new DDR frequency i.e 1867MT/s
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
board/freescale/t208xrdb/t2080_rcw.cfg | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/t208xrdb/t2080_rcw.cfg
b/board/freescale/t208xrdb/t2080_rcw.cfg
index 59025ea..7c55150 100644
--- a/board/freescale/t208xrdb/t2080_rcw.cfg
+++ b/board/freescale/t208xrdb/t2080_rcw.cfg
@@ -9,8 +9,8 @@ aa55aa55 010e0100
# 0004
#For T2080 v1.1
-#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
-1206001b 1500
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
+1207001b 1500
66150002 e8104000 c100
0080 000307fc
0004
--
2.1.0.27.g96db324
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Re: [U-Boot] Compile x86 minnowboard max got error
gcc --version shows following: gcc (Ubuntu 4.8.2-19ubuntu1) 4.8.2 Copyright (C) 2013 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. Thank you Date: Wed, 1 Apr 2015 14:19:50 +0800 Subject: Re: [U-Boot] Compile x86 minnowboard max got error From: bmeng...@gmail.com To: liyuqia...@outlook.com CC: u-boot@lists.denx.de On Wed, Apr 1, 2015 at 10:51 AM, li yuqian liyuqia...@outlook.com wrote: Hi All, i am trying to compile the x86 minnowboard max uboot support followed this link http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.x86 , but i alway got following error CC net/ping.o CC net/tftp.o LD net/built-in.o LD test/built-in.o CC test/dm/cmd_dm.o LD test/dm/built-in.o CC examples/standalone/stubs.o LD examples/standalone/libstubs.o CC examples/standalone/hello_world.o LD examples/standalone/hello_world OBJCOPY examples/standalone/hello_world.srec OBJCOPY examples/standalone/hello_world.bin LDS u-boot.lds LD u-boot arch/x86/lib/built-in.o: In function `__wrap___udivdi3': /usr/src/u-boot/arch/x86/lib/gcc.c:36: undefined reference to `__normal___udivdi3' arch/x86/lib/built-in.o: In function `__wrap___umoddi3': /usr/src/u-boot/arch/x86/lib/gcc.c:38: undefined reference to `__normal___umoddi3' make: *** [u-boot] Error 1 i used master of git version and also tried v2015.04-rc4 and v2015.04-rc3 same issue, how i can fix it? thank you What's the version of gcc that you are using? Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V3 1/3] dm: gpio: request list: return the count if requests max_count reached
Hello Simon, On 04/01/2015 05:17 AM, Simon Glass wrote: On 31 March 2015 at 10:57, Przemyslaw Marczak p.marc...@samsung.com wrote: The function gpio_request_list_by_name_nodev() returned -ENOSPC error, when the loop count was greater than requested count. This was wrong, because function should return the requested gpio count, when meets the call request without errors. Now, the loop ends on requested max_count. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Simon Glass s...@chromium.org Changes V3: - new commit There's something odd about the change logs here - they are coming in as part of the commit message. Are you using patman? Acked-by: Simon Glass s...@chromium.org Sorry for this, it's by mistake, I don't use patman for generating patches. I add change log manually. Thanks for applying this series :) Best regards, -- Przemyslaw Marczak Samsung RD Institute Poland Samsung Electronics p.marc...@samsung.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] dm: spi: Convert Freescale QSPI driver to driver model
Hi Haikun,
On 4/1/2015 11:10 AM, Haikun Wang wrote:
Move the Freescale QSPI driver over to driver model.
Signed-off-by: Haikun Wang haikun.w...@freescale.com
Signed-off-by: Peng Fan peng@freescale.com
---
Changes in v2:
- Fix build fail on mx6sxsabresd_spl issue
- Add configure regmap endian in NO-DM model
Changes in v1: None.
drivers/spi/fsl_qspi.c | 985 -
1 file changed, 656 insertions(+), 329 deletions(-)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 5e0b069..868df5f 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
*
* Freescale Quad Serial Peripheral Interface (QSPI) driver
*
@@ -11,8 +11,12 @@
#include spi.h
#include asm/io.h
#include linux/sizes.h
+#include dm.h
+#include errno.h
#include fsl_qspi.h
+DECLARE_GLOBAL_DATA_PTR;
+
#define RX_BUFFER_SIZE0x80
#ifdef CONFIG_MX6SX
#define TX_BUFFER_SIZE0x200
@@ -63,35 +67,85 @@
#define QSPI_CMD_PP_4B0x12/* Page program (up to 256
bytes) */
#define QSPI_CMD_SE_4B0xdc/* Sector erase (usually 64KiB)
*/
-#ifdef CONFIG_SYS_FSL_QSPI_LE
-#define qspi_read32in_le32
-#define qspi_write32 out_le32
-#elif defined(CONFIG_SYS_FSL_QSPI_BE)
-#define qspi_read32in_be32
-#define qspi_write32 out_be32
-#endif
+/* fsl_qspi_platdata flags */
+#define QSPI_FLAG_REGMAP_ENDIAN_BIG(1 0)
-static unsigned long spi_bases[] = {
- QSPI0_BASE_ADDR,
-#ifdef CONFIG_MX6SX
- QSPI1_BASE_ADDR,
-#endif
-};
+/* default SCK frequency, unit: HZ */
+#define FSL_QSPI_DEFAULT_SCK_FREQ 5000
-static unsigned long amba_bases[] = {
- QSPI0_AMBA_BASE,
-#ifdef CONFIG_MX6SX
- QSPI1_AMBA_BASE,
+/* QSPI max chipselect signals number */
+#define FSL_QSPI_MAX_CHIPSELECT_NUM 4
+
+#ifdef CONFIG_DM_SPI
+/**
+ * struct fsl_qspi_platdata - platform data for Freescale QSPI
+ *
+ * @flags: Flags for QSPI QSPI_FLAG_...
+ * @speed_hz: Default SCK frequency
+ * @reg_base: Base address of QSPI registers
+ * @amba_base: Base address of QSPI memory mapping
+ * @amba_total_size: size of QSPI memory mapping
+ * @flash_num: Number of active slave devices
+ * @num_chipselect: Number of QSPI chipselect signals
+ */
+struct fsl_qspi_platdata {
+ u32 flags;
+ u32 speed_hz;
+ u32 reg_base;
+ u32 amba_base;
+ u32 amba_total_size;
+ u32 flash_num;
+ u32 num_chipselect;
+};
#endif
+
+/**
+ * struct fsl_qspi_priv - private data for Freescale QSPI
+ *
+ * @flags: Flags for QSPI QSPI_FLAG_...
+ * @bus_clk: QSPI input clk frequency
+ * @speed_hz: Default SCK frequency
+ * @cur_seqid: current LUT table sequence id
+ * @sf_addr: flash access offset
+ * @amba_base: Base address of QSPI memory mapping of every CS
+ * @amba_total_size: size of QSPI memory mapping
+ * @cur_amba_base: Base address of QSPI memory mapping of current CS
+ * @flash_num: Number of active slave devices
+ * @num_chipselect: Number of QSPI chipselect signals
+ * @regs: Point to QSPI register structure for I/O access
+ */
+struct fsl_qspi_priv {
+ u32 flags;
+ u32 bus_clk;
+ u32 speed_hz;
+ u32 cur_seqid;
+ u32 sf_addr;
+ u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
+ u32 amba_total_size;
+ u32 cur_amba_base;
+ u32 flash_num;
+ u32 num_chipselect;
+ struct fsl_qspi_regs *regs;
};
+#ifndef CONFIG_DM_SPI
struct fsl_qspi {
struct spi_slave slave;
- unsigned long reg_base;
- unsigned long amba_base;
- u32 sf_addr;
- u8 cur_seqid;
+ struct fsl_qspi_priv priv;
};
+#endif
+
+static u32 qspi_read32(u32 flags, u32 *addr)
+{
+ return flags QSPI_FLAG_REGMAP_ENDIAN_BIG ?
+ in_be32(addr) : in_le32(addr);
+}
+
+static void qspi_write32(u32 flags, u32 *addr, u32 val)
+{
+ flags QSPI_FLAG_REGMAP_ENDIAN_BIG ?
+ out_be32(addr, val) : out_le32(addr, val);
+}
/* QSPI support swapping the flash read/write data
* in hardware for LS102xA, but not for VF610 */
@@ -104,131 +158,135 @@ static inline u32 qspi_endian_xchg(u32 data)
#endif
}
-static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave)
-{
- return container_of(slave, struct fsl_qspi, slave);
-}
-
-static void qspi_set_lut(struct fsl_qspi *qspi)
+static void qspi_set_lut(struct fsl_qspi_priv *priv)
{
- struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi-reg_base;
+ struct fsl_qspi_regs *regs = priv-regs;
u32 lut_base;
/* Unlock the LUT */
- qspi_write32(regs-lutkey, LUT_KEY_VALUE);
- qspi_write32(regs-lckcr, QSPI_LCKCR_UNLOCK);
+ qspi_write32(priv-flags, regs-lutkey, LUT_KEY_VALUE);
+ qspi_write32(priv-flags, regs-lckcr,
[U-Boot] [RESEND PATCH 1/6] ARM: vf610: Move DDR3 initialization to imx-common
In order to avoid code duplication, move the DDR3 initialization to the
common place under imx-common. Currently ROW_DIFF and COL_DIFF can be
chosen from the board file. The JEDEC timings are specified using a
common ddr3_jedec_timings structure.
Signed-off-by: Stefan Agner ste...@agner.ch
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/imx-common/Makefile | 3 +
arch/arm/imx-common/ddrmc-vf610.c | 278 +
arch/arm/include/asm/arch-vf610/ddrmc-vf610.h | 72 +++
arch/arm/include/asm/arch-vf610/imx-regs.h| 4 +-
board/freescale/vf610twr/vf610twr.c | 282 +-
5 files changed, 408 insertions(+), 231 deletions(-)
create mode 100644 arch/arm/imx-common/ddrmc-vf610.c
create mode 100644 arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 606482f..b9f1ca4 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -22,6 +22,9 @@ ifeq ($(SOC),$(filter $(SOC),mx6))
obj-$(CONFIG_CMD_SATA) += sata.o
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
endif
+ifeq ($(SOC),$(filter $(SOC),vf610))
+obj-y += ddrmc-vf610.o
+endif
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
diff --git a/arch/arm/imx-common/ddrmc-vf610.c
b/arch/arm/imx-common/ddrmc-vf610.c
new file mode 100644
index 000..e462631
--- /dev/null
+++ b/arch/arm/imx-common/ddrmc-vf610.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright 2015 Toradex, Inc.
+ *
+ * Based on vf610twr:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include asm/io.h
+#include asm/arch/imx-regs.h
+#include asm/arch/iomux-vf610.h
+#include asm/arch/ddrmc-vf610.h
+
+void ddrmc_setup_iomux(void)
+{
+ static const iomux_v3_cfg_t ddr_pads[] = {
+ VF610_PAD_DDR_A15__DDR_A_15,
+ VF610_PAD_DDR_A14__DDR_A_14,
+ VF610_PAD_DDR_A13__DDR_A_13,
+ VF610_PAD_DDR_A12__DDR_A_12,
+ VF610_PAD_DDR_A11__DDR_A_11,
+ VF610_PAD_DDR_A10__DDR_A_10,
+ VF610_PAD_DDR_A9__DDR_A_9,
+ VF610_PAD_DDR_A8__DDR_A_8,
+ VF610_PAD_DDR_A7__DDR_A_7,
+ VF610_PAD_DDR_A6__DDR_A_6,
+ VF610_PAD_DDR_A5__DDR_A_5,
+ VF610_PAD_DDR_A4__DDR_A_4,
+ VF610_PAD_DDR_A3__DDR_A_3,
+ VF610_PAD_DDR_A2__DDR_A_2,
+ VF610_PAD_DDR_A1__DDR_A_1,
+ VF610_PAD_DDR_A0__DDR_A_0,
+ VF610_PAD_DDR_BA2__DDR_BA_2,
+ VF610_PAD_DDR_BA1__DDR_BA_1,
+ VF610_PAD_DDR_BA0__DDR_BA_0,
+ VF610_PAD_DDR_CAS__DDR_CAS_B,
+ VF610_PAD_DDR_CKE__DDR_CKE_0,
+ VF610_PAD_DDR_CLK__DDR_CLK_0,
+ VF610_PAD_DDR_CS__DDR_CS_B_0,
+ VF610_PAD_DDR_D15__DDR_D_15,
+ VF610_PAD_DDR_D14__DDR_D_14,
+ VF610_PAD_DDR_D13__DDR_D_13,
+ VF610_PAD_DDR_D12__DDR_D_12,
+ VF610_PAD_DDR_D11__DDR_D_11,
+ VF610_PAD_DDR_D10__DDR_D_10,
+ VF610_PAD_DDR_D9__DDR_D_9,
+ VF610_PAD_DDR_D8__DDR_D_8,
+ VF610_PAD_DDR_D7__DDR_D_7,
+ VF610_PAD_DDR_D6__DDR_D_6,
+ VF610_PAD_DDR_D5__DDR_D_5,
+ VF610_PAD_DDR_D4__DDR_D_4,
+ VF610_PAD_DDR_D3__DDR_D_3,
+ VF610_PAD_DDR_D2__DDR_D_2,
+ VF610_PAD_DDR_D1__DDR_D_1,
+ VF610_PAD_DDR_D0__DDR_D_0,
+ VF610_PAD_DDR_DQM1__DDR_DQM_1,
+ VF610_PAD_DDR_DQM0__DDR_DQM_0,
+ VF610_PAD_DDR_DQS1__DDR_DQS_1,
+ VF610_PAD_DDR_DQS0__DDR_DQS_0,
+ VF610_PAD_DDR_RAS__DDR_RAS_B,
+ VF610_PAD_DDR_WE__DDR_WE_B,
+ VF610_PAD_DDR_ODT1__DDR_ODT_0,
+ VF610_PAD_DDR_ODT0__DDR_ODT_1,
+ VF610_PAD_DDR_RESETB,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
+}
+
+void ddrmc_phy_init(void)
+{
+ struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+ writel(DDRMC_PHY_DQ_TIMING, ddrmr-phy[0]);
+ writel(DDRMC_PHY_DQ_TIMING, ddrmr-phy[16]);
+ writel(DDRMC_PHY_DQ_TIMING, ddrmr-phy[32]);
+
+ writel(DDRMC_PHY_DQS_TIMING, ddrmr-phy[1]);
+ writel(DDRMC_PHY_DQS_TIMING, ddrmr-phy[17]);
+
+ writel(DDRMC_PHY_CTRL, ddrmr-phy[2]);
+ writel(DDRMC_PHY_CTRL, ddrmr-phy[18]);
+ writel(DDRMC_PHY_CTRL, ddrmr-phy[34]);
+
+ writel(DDRMC_PHY_MASTER_CTRL, ddrmr-phy[3]);
+ writel(DDRMC_PHY_MASTER_CTRL, ddrmr-phy[19]);
+ writel(DDRMC_PHY_MASTER_CTRL, ddrmr-phy[35]);
+
+ writel(DDRMC_PHY_SLAVE_CTRL, ddrmr-phy[4]);
+ writel(DDRMC_PHY_SLAVE_CTRL, ddrmr-phy[20]);
+ writel(DDRMC_PHY_SLAVE_CTRL, ddrmr-phy[36]);
+
+ /* LPDDR2
[U-Boot] [RESEND PATCH 2/6] ARM: vf610: Enable external 32KHz oscillator
From: Stefan Agner ste...@agner.ch
Enable the SCSC (Slow Clock Source Controller) and select the external
32KHz oscillator. This improves the accuracy of the RTC.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/include/asm/arch-vf610/crm_regs.h | 1 +
arch/arm/include/asm/arch-vf610/imx-regs.h | 11 ++-
board/freescale/vf610twr/vf610twr.c| 13 -
3 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h
b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 724682c..78708e2 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -199,6 +199,7 @@ struct anadig_reg {
#define CCM_CCGR2_PORTD_CTRL_MASK (0x3 24)
#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 26)
#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
+#define CCM_CCGR3_SCSC_CTRL_MASK(0x3 4)
#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 20)
#define CCM_CCGR4_CCM_CTRL_MASK(0x3 22)
#define CCM_CCGR4_GPC_CTRL_MASK(0x3 24)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 866b303..aa60031 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -65,7 +65,7 @@
#define QSPI0_BASE_ADDR(AIPS0_BASE_ADDR + 0x00044000)
#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005)
-#define SCSCM_BASE_ADDR(AIPS0_BASE_ADDR + 0x00052000)
+#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006)
#define SPDIF_BASE_ADDR(AIPS0_BASE_ADDR + 0x00061000)
#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
@@ -264,6 +264,9 @@
#define SRC_SRSR_WDOG_A5 (0x1 3)
#define SRC_SRSR_POR_RST (0x1 0)
+/* Slow Clock Source Controller Module (SCSC) */
+#define SCSC_SOSC_CTR_SOSC_EN0x1
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include asm/types.h
@@ -448,6 +451,12 @@ struct mscm_ir {
u16 rsvd3[848];
};
+/* SCSC */
+struct scsc_reg {
+ u32 sirc_ctr;
+ u32 sosc_ctr;
+};
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/board/freescale/vf610twr/vf610twr.c
b/board/freescale/vf610twr/vf610twr.c
index eb27542..4160acd 100644
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -227,7 +227,7 @@ static void clock_init(void)
CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
CCM_CCGR2_QSPI0_CTRL_MASK);
clrsetbits_le32(ccm-ccgr3, CCM_REG_CTRL_MASK,
- CCM_CCGR3_ANADIG_CTRL_MASK);
+ CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
clrsetbits_le32(ccm-ccgr4, CCM_REG_CTRL_MASK,
CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
@@ -308,9 +308,20 @@ int board_early_init_f(void)
int board_init(void)
{
+ struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
+
/* address of boot parameters */
gd-bd-bi_boot_params = PHYS_SDRAM + 0x100;
+ /*
+* Enable external 32K Oscillator
+*
+* The internal clock experiences significant drift
+* so we must use the external oscillator in order
+* to maintain correct time in the hwclock
+*/
+ setbits_le32(scsc-sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
+
return 0;
}
--
2.3.4
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[U-Boot] [RESEND PATCH 4/6] ARM: vf610: Enable caches
From: Stefan Agner ste...@agner.ch
Enables caches which provides a rather huge speedup of the boot loader.
Also mark the on-chip RAM as cachable since this is the area U-Boot runs
from.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/cpu/armv7/vf610/generic.c | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/cpu/armv7/vf610/generic.c
b/arch/arm/cpu/armv7/vf610/generic.c
index 3bdc221..1bb9b8e 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -342,3 +342,19 @@ int get_clocks(void)
#endif
return 0;
}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+ enum dcache_option option = DCACHE_WRITETHROUGH;
+#else
+ enum dcache_option option = DCACHE_WRITEBACK;
+#endif
+ dcache_enable();
+ icache_enable();
+
+/* Enable caching on OCRAM */
+ mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option);
+}
+#endif
--
2.3.4
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[U-Boot] [RESEND PATCH 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/include/asm/arch-vf610/crm_regs.h | 14 ++
arch/arm/include/asm/arch-vf610/imx-regs.h | 4 +
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ehci-vf.c | 204 +
4 files changed, 223 insertions(+)
create mode 100644 drivers/usb/host/ehci-vf.c
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h
b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 78708e2..851c3b9 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -124,6 +124,10 @@ struct anadig_reg {
#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 16)
#define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) 0x7) 16)
+#define CCM_CCSR_PLL3_PFD4_EN (1 31)
+#define CCM_CCSR_PLL3_PFD3_EN (1 30)
+#define CCM_CCSR_PLL3_PFD2_EN (1 29)
+#define CCM_CCSR_PLL3_PFD1_EN (1 28)
#define CCM_CCSR_PLL2_PFD4_EN (1 15)
#define CCM_CCSR_PLL2_PFD3_EN (1 14)
#define CCM_CCSR_PLL2_PFD2_EN (1 13)
@@ -189,6 +193,7 @@ struct anadig_reg {
#define CCM_REG_CTRL_MASK 0x
#define CCM_CCGR0_UART0_CTRL_MASK (0x3 14)
#define CCM_CCGR0_UART1_CTRL_MASK (0x3 16)
+#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 8)
#define CCM_CCGR1_PIT_CTRL_MASK(0x3 14)
#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 28)
#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 8)
@@ -207,14 +212,23 @@ struct anadig_reg {
#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 10)
#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 28)
#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 4)
+#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 8)
#define CCM_CCGR9_FEC0_CTRL_MASK 0x3
#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 2)
#define CCM_CCGR10_NFC_CTRL_MASK 0x3
+#define ANADIG_PLL7_CTRL_BYPASS (1 16)
+#define ANADIG_PLL7_CTRL_ENABLE (1 13)
+#define ANADIG_PLL7_CTRL_POWERDOWN (1 12)
+#define ANADIG_PLL7_CTRL_DIV_SELECT (1 1)
#define ANADIG_PLL5_CTRL_BYPASS (1 16)
#define ANADIG_PLL5_CTRL_ENABLE (1 13)
#define ANADIG_PLL5_CTRL_POWERDOWN (1 12)
#define ANADIG_PLL5_CTRL_DIV_SELECT1
+#define ANADIG_PLL3_CTRL_BYPASS (1 16)
+#define ANADIG_PLL3_CTRL_ENABLE (1 13)
+#define ANADIG_PLL3_CTRL_POWERDOWN (1 12)
+#define ANADIG_PLL3_CTRL_DIV_SELECT (1 1)
#define ANADIG_PLL2_CTRL_ENABLE(1 13)
#define ANADIG_PLL2_CTRL_POWERDOWN (1 12)
#define ANADIG_PLL2_CTRL_DIV_SELECT1
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index a5908ca..26057fe 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -52,6 +52,7 @@
#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000)
+#define USBC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000)
#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
@@ -65,6 +66,8 @@
#define QSPI0_BASE_ADDR(AIPS0_BASE_ADDR + 0x00044000)
#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005)
+#define USB_PHY0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050800)
+#define USB_PHY1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050C00)
#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006)
#define SPDIF_BASE_ADDR(AIPS0_BASE_ADDR + 0x00061000)
@@ -84,6 +87,7 @@
#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000)
#define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000)
#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
+#define USBC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00034000)
#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x0005)
#define ENET1_BASE_ADDR(AIPS1_BASE_ADDR + 0x00051000)
#define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x0006)
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index eb6f34b..4bd9321 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
obj-$(CONFIG_USB_EHCI_UNIPHIER) += ehci-uniphier.o
obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
+obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o
obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
diff --git
[U-Boot] [RESEND PATCH 0/6] Add support for Colibri Vybrid Modules
Hello, This patchset adds support for the Toradex Colibri Vybrid VF50 and VF61 modules. Boot up has been tested using the serial loader over UART. First patch in the series refactors the DDR related code for use by both the tower board and colibri modules. It also introduces a DDR3 based JEDEC timing structure. Second third and fourth patch in this series are improvement patches related to RTC, SoC/CPU detection and caches. Fifth patch introduces USB support for Vybrid modules. Much of the code is similar to the ehci-mx6 driver. One open question here would be is there a better way to take care of this similarity and perhaps share the code base among the two drivers? Both host and client modes are working and DFU has also been tested. Currently, we restrict the ports to be in one of host and client mode. Sixth patch adds the actual support for the Colibri modules. Comments and feedback are most welcome. The patchset is based and tested on the latest master branch as of this writing which is 2015.04-rc5. - Sanchayan. Sanchayan Maity (4): ARM: vf610: Move DDR3 initialization to imx-common ARM: vf610: Add SoC and CPU type detection usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's ARM: vf610: Initial integration for Colibri VF50/VF61 Stefan Agner (2): ARM: vf610: Enable external 32KHz oscillator ARM: vf610: Enable caches arch/arm/Kconfig | 5 + arch/arm/cpu/armv7/vf610/generic.c| 45 ++- arch/arm/imx-common/Makefile | 3 + arch/arm/imx-common/ddrmc-vf610.c | 278 ++ arch/arm/include/asm/arch-vf610/crm_regs.h| 15 + arch/arm/include/asm/arch-vf610/ddrmc-vf610.h | 72 + arch/arm/include/asm/arch-vf610/imx-regs.h| 36 ++- board/freescale/vf610twr/vf610twr.c | 295 +-- board/toradex/colibri_vf/Kconfig | 18 ++ board/toradex/colibri_vf/MAINTAINERS | 6 + board/toradex/colibri_vf/Makefile | 7 + board/toradex/colibri_vf/colibri_vf.c | 389 ++ board/toradex/colibri_vf/imximage.cfg | 17 ++ configs/colibri_vf_defconfig | 3 + drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-vf.c| 204 ++ include/configs/colibri_vf.h | 266 ++ 17 files changed, 1425 insertions(+), 235 deletions(-) create mode 100644 arch/arm/imx-common/ddrmc-vf610.c create mode 100644 arch/arm/include/asm/arch-vf610/ddrmc-vf610.h create mode 100644 board/toradex/colibri_vf/Kconfig create mode 100644 board/toradex/colibri_vf/MAINTAINERS create mode 100644 board/toradex/colibri_vf/Makefile create mode 100644 board/toradex/colibri_vf/colibri_vf.c create mode 100644 board/toradex/colibri_vf/imximage.cfg create mode 100644 configs/colibri_vf_defconfig create mode 100644 drivers/usb/host/ehci-vf.c create mode 100644 include/configs/colibri_vf.h -- 2.3.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RESEND PATCH 3/6] ARM: vf610: Add SoC and CPU type detection
Vybrid product family consists of several rather similar SoC which
can be determined by softare during boot time. This allows use of
variable ${soc} for Linux device tree files. Detect VF5xx CPU's by
reading the CPU count register. We can determine the second number
of the CPU type (VF6x0) which indicates the presence of a L2 cache.
Signed-off-by: Stefan Agner ste...@agner.ch
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
---
arch/arm/cpu/armv7/vf610/generic.c | 29 +++--
arch/arm/include/asm/arch-vf610/imx-regs.h | 12
2 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/vf610/generic.c
b/arch/arm/cpu/armv7/vf610/generic.c
index 92aaad9..3bdc221 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -18,6 +18,8 @@
DECLARE_GLOBAL_DATA_PTR;
#endif
+static char soc_type[] = xx0;
+
#ifdef CONFIG_MXC_OCOTP
void enable_ocotp_clk(unsigned char enable)
{
@@ -284,14 +286,37 @@ static char *get_reset_cause(void)
int print_cpuinfo(void)
{
- printf(CPU: Freescale Vybrid VF610 at %d MHz\n,
- mxc_get_clock(MXC_ARM_CLK) / 100);
+ printf(CPU: Freescale Vybrid VF%s at %d MHz\n,
+ soc_type, mxc_get_clock(MXC_ARM_CLK) / 100);
printf(Reset cause: %s\n, get_reset_cause());
return 0;
}
#endif
+int arch_cpu_init(void)
+{
+ struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
+
+ soc_type[0] = mscm-cpxcount ? '6' : '5'; /*Dual Core = VF6x0 */
+ soc_type[1] = mscm-cpxcfg1 ? '1' : '0'; /* L2 Cache = VFx10 */
+
+ return 0;
+}
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+ char soc[6];
+
+ strcat(soc, vf);
+ strcat(soc, soc_type);
+ setenv(soc, soc);
+
+ return 0;
+}
+#endif
+
int cpu_eth_init(bd_t *bis)
{
int rc = -ENODEV;
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index aa60031..a5908ca 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -457,6 +457,18 @@ struct scsc_reg {
u32 sosc_ctr;
};
+/* MSCM */
+struct mscm {
+ u32 cpxtype;
+ u32 cpxnum;
+ u32 cpxmaster;
+ u32 cpxcount;
+ u32 cpxcfg0;
+ u32 cpxcfg1;
+ u32 cpxcfg2;
+ u32 cpxcfg3;
+};
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_IMX_REGS_H__ */
--
2.3.4
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[U-Boot] [RESEND PATCH 6/6] ARM: vf610: Initial integration for Colibri VF50/VF61
This adds initial support for Colibri VF50/VF61 based on Freescale Vybrid SoC. - CPU clocked at 396/500 MHz - DDR3 at 396MHz - for VF50, use PLL2 as memory clock (synchronous mode) - for VF61, use PLL1 as memory clock (asynchronous mode) - Console on UART0 (Colibri UART_A) - Ethernet on FEC1 - PLL5 based RMII clocking (E.g. No external crystal) - UART_A and UART_C I/O muxing - Boot from NAND by default - USB host and client support Tested on Colibri VF50/VF61 booting using serial loader over UART. Signed-off-by: Stefan Agner ste...@agner.ch Signed-off-by: Sanchayan Maity maitysancha...@gmail.com --- arch/arm/Kconfig | 5 + arch/arm/include/asm/arch-vf610/imx-regs.h | 5 + board/toradex/colibri_vf/Kconfig | 18 ++ board/toradex/colibri_vf/MAINTAINERS | 6 + board/toradex/colibri_vf/Makefile | 7 + board/toradex/colibri_vf/colibri_vf.c | 389 + board/toradex/colibri_vf/imximage.cfg | 17 ++ configs/colibri_vf_defconfig | 3 + include/configs/colibri_vf.h | 266 9 files changed, 716 insertions(+) create mode 100644 board/toradex/colibri_vf/Kconfig create mode 100644 board/toradex/colibri_vf/MAINTAINERS create mode 100644 board/toradex/colibri_vf/Makefile create mode 100644 board/toradex/colibri_vf/colibri_vf.c create mode 100644 board/toradex/colibri_vf/imximage.cfg create mode 100644 configs/colibri_vf_defconfig create mode 100644 include/configs/colibri_vf.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 80b0d34..e32a942 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -608,6 +608,10 @@ config TARGET_VF610TWR bool Support vf610twr select CPU_V7 +config TARGET_COLIBRI_VF + bool Support Colibri VF50/61 + select CPU_V7 + config ZYNQ bool Xilinx Zynq Platform select CPU_V7 @@ -864,6 +868,7 @@ source board/ti/ti814x/Kconfig source board/ti/ti816x/Kconfig source board/timll/devkit3250/Kconfig source board/toradex/colibri_pxa270/Kconfig +source board/toradex/colibri_vf/Kconfig source board/tqc/tqma6/Kconfig source board/trizepsiv/Kconfig source board/ttcontrol/vision2/Kconfig diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 26057fe..a7d765a 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -267,6 +267,11 @@ #define SRC_SRSR_WDOG_M4 (0x1 4) #define SRC_SRSR_WDOG_A5 (0x1 3) #define SRC_SRSR_POR_RST (0x1 0) +#define SRC_SBMR2_BMOD_MASK (0x3 24) +#define SRC_SBMR2_BMOD_SHIFT24 +#define SRC_SBMR2_BMOD_FUSES0x0 +#define SRC_SBMR2_BMOD_SERIAL 0x1 +#define SRC_SBMR2_BMOD_RCON 0x2 /* Slow Clock Source Controller Module (SCSC) */ #define SCSC_SOSC_CTR_SOSC_EN0x1 diff --git a/board/toradex/colibri_vf/Kconfig b/board/toradex/colibri_vf/Kconfig new file mode 100644 index 000..2c3cb30 --- /dev/null +++ b/board/toradex/colibri_vf/Kconfig @@ -0,0 +1,18 @@ +if TARGET_COLIBRI_VF + +config SYS_CPU + default armv7 + +config SYS_BOARD + default colibri_vf + +config SYS_VENDOR + default toradex + +config SYS_SOC + default vf610 + +config SYS_CONFIG_NAME + default colibri_vf + +endif diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS new file mode 100644 index 000..551c575 --- /dev/null +++ b/board/toradex/colibri_vf/MAINTAINERS @@ -0,0 +1,6 @@ +Colibri VFxx +M: Stefan Agner stefan.ag...@toradex.com +S: Maintained +F: board/toradex/colibri_vf/ +F: include/configs/colibri_vf.h +F: configs/colibri_vf_defconfig diff --git a/board/toradex/colibri_vf/Makefile b/board/toradex/colibri_vf/Makefile new file mode 100644 index 000..c7e5134 --- /dev/null +++ b/board/toradex/colibri_vf/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := colibri_vf.o diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c new file mode 100644 index 000..62f3013 --- /dev/null +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -0,0 +1,389 @@ +/* + * Copyright 2015 Toradex, Inc. + * + * Based on vf610twr.c: + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include common.h +#include asm/io.h +#include asm/arch/imx-regs.h +#include asm/arch/iomux-vf610.h +#include asm/arch/ddrmc-vf610.h +#include asm/arch/crm_regs.h +#include asm/arch/clock.h +#include mmc.h +#include fsl_esdhc.h +#include miiphy.h +#include netdev.h +#include i2c.h +#include g_dnl.h + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_25ohm
Re: [U-Boot] Compile x86 minnowboard max got error
On Wed, Apr 1, 2015 at 10:51 AM, li yuqian liyuqia...@outlook.com wrote: Hi All, i am trying to compile the x86 minnowboard max uboot support followed this link http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.x86 , but i alway got following error CC net/ping.o CC net/tftp.o LD net/built-in.o LD test/built-in.o CC test/dm/cmd_dm.o LD test/dm/built-in.o CC examples/standalone/stubs.o LD examples/standalone/libstubs.o CC examples/standalone/hello_world.o LD examples/standalone/hello_world OBJCOPY examples/standalone/hello_world.srec OBJCOPY examples/standalone/hello_world.bin LDS u-boot.lds LD u-boot arch/x86/lib/built-in.o: In function `__wrap___udivdi3': /usr/src/u-boot/arch/x86/lib/gcc.c:36: undefined reference to `__normal___udivdi3' arch/x86/lib/built-in.o: In function `__wrap___umoddi3': /usr/src/u-boot/arch/x86/lib/gcc.c:38: undefined reference to `__normal___umoddi3' make: *** [u-boot] Error 1 i used master of git version and also tried v2015.04-rc4 and v2015.04-rc3 same issue, how i can fix it? thank you What's the version of gcc that you are using? Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] spi: omap3: Fix timeout handling
The timeout value is never reset during the transfer. This means that when
transferring more data we eventually trigger the timeout.
This was reported on the mailing list:
Spansion SPI flash read timeout with AM335x
Signed-off-by: David Dueck davidcdu...@googlemail.com
CC: Tom Rini tr...@konsulko.com
CC: Jagannadh Teki jagannadh.t...@gmail.com
CC: Stefan Roese s...@denx.de
CC: Andy Pont andy.p...@sdcsystems.com
---
Changes since v1:
- fix style issue
- fix CC line
drivers/spi/omap3_spi.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 651e46e..85f9e85 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -20,7 +20,7 @@
#include asm/io.h
#include omap3_spi.h
-#define SPI_WAIT_TIMEOUT 300
+#define SPI_WAIT_TIMEOUT 10
static void spi_reset(struct omap3_spi_slave *ds)
{
@@ -227,7 +227,7 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int
len, const void *txp,
{
struct omap3_spi_slave *ds = to_omap3_spi(slave);
int i;
- int timeout = SPI_WAIT_TIMEOUT;
+ ulong start;
int chconf = readl(ds-regs-channel[ds-slave.cs].chconf);
/* Enable the channel */
@@ -241,9 +241,10 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int
len, const void *txp,
for (i = 0; i len; i++) {
/* wait till TX register is empty (TXS == 1) */
+ start = get_timer(0);
while (!(readl(ds-regs-channel[ds-slave.cs].chstat)
OMAP3_MCSPI_CHSTAT_TXS)) {
- if (--timeout = 0) {
+ if (get_timer(start) SPI_WAIT_TIMEOUT) {
printf(SPI TXS timed out, status=0x%08x\n,
readl(ds-regs-channel[ds-slave.cs].chstat));
return -1;
@@ -280,7 +281,7 @@ int omap3_spi_read(struct spi_slave *slave, unsigned int
len, void *rxp,
{
struct omap3_spi_slave *ds = to_omap3_spi(slave);
int i;
- int timeout = SPI_WAIT_TIMEOUT;
+ ulong start;
int chconf = readl(ds-regs-channel[ds-slave.cs].chconf);
/* Enable the channel */
@@ -295,10 +296,11 @@ int omap3_spi_read(struct spi_slave *slave, unsigned int
len, void *rxp,
writel(0, ds-regs-channel[ds-slave.cs].tx);
for (i = 0; i len; i++) {
+ start = get_timer(0);
/* Wait till RX register contains data (RXS == 1) */
while (!(readl(ds-regs-channel[ds-slave.cs].chstat)
OMAP3_MCSPI_CHSTAT_RXS)) {
- if (--timeout = 0) {
+ if (get_timer(start) SPI_WAIT_TIMEOUT) {
printf(SPI RXS timed out, status=0x%08x\n,
readl(ds-regs-channel[ds-slave.cs].chstat));
return -1;
@@ -332,7 +334,7 @@ int omap3_spi_txrx(struct spi_slave *slave, unsigned int
len,
const void *txp, void *rxp, unsigned long flags)
{
struct omap3_spi_slave *ds = to_omap3_spi(slave);
- int timeout = SPI_WAIT_TIMEOUT;
+ ulong start;
int chconf = readl(ds-regs-channel[ds-slave.cs].chconf);
int irqstatus = readl(ds-regs-irqstatus);
int i=0;
@@ -350,9 +352,10 @@ int omap3_spi_txrx(struct spi_slave *slave, unsigned int
len,
for (i=0; i len; i++){
/* Write: wait for TX empty (TXS == 1)*/
irqstatus |= (1 (4*(ds-slave.bus)));
+ start = get_timer(0);
while (!(readl(ds-regs-channel[ds-slave.cs].chstat)
OMAP3_MCSPI_CHSTAT_TXS)) {
- if (--timeout = 0) {
+ if (get_timer(start) SPI_WAIT_TIMEOUT) {
printf(SPI TXS timed out, status=0x%08x\n,
readl(ds-regs-channel[ds-slave.cs].chstat));
return -1;
@@ -368,9 +371,10 @@ int omap3_spi_txrx(struct spi_slave *slave, unsigned int
len,
writel(((u8 *)txp)[i], tx);
/*Read: wait for RX containing data (RXS == 1)*/
+ start = get_timer(0);
while (!(readl(ds-regs-channel[ds-slave.cs].chstat)
OMAP3_MCSPI_CHSTAT_RXS)) {
- if (--timeout = 0) {
+ if (get_timer(start) SPI_WAIT_TIMEOUT) {
printf(SPI RXS timed out, status=0x%08x\n,
readl(ds-regs-channel[ds-slave.cs].chstat));
return -1;
--
2.3.4
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Re: [U-Boot] [PATCH v2] spi: omap3: Fix timeout handling
On 1 April 2015 at 17:50, David Dueck davidcdu...@googlemail.com wrote:
The timeout value is never reset during the transfer. This means that when
transferring more data we eventually trigger the timeout.
This was reported on the mailing list:
Spansion SPI flash read timeout with AM335x
Signed-off-by: David Dueck davidcdu...@googlemail.com
CC: Tom Rini tr...@konsulko.com
CC: Jagannadh Teki jagannadh.t...@gmail.com
CC: Stefan Roese s...@denx.de
CC: Andy Pont andy.p...@sdcsystems.com
---
Changes since v1:
- fix style issue
- fix CC line
drivers/spi/omap3_spi.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
Any Tested-by?
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 651e46e..85f9e85 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -20,7 +20,7 @@
#include asm/io.h
#include omap3_spi.h
-#define SPI_WAIT_TIMEOUT 300
+#define SPI_WAIT_TIMEOUT 10
static void spi_reset(struct omap3_spi_slave *ds)
{
@@ -227,7 +227,7 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int
len, const void *txp,
{
struct omap3_spi_slave *ds = to_omap3_spi(slave);
int i;
- int timeout = SPI_WAIT_TIMEOUT;
+ ulong start;
int chconf = readl(ds-regs-channel[ds-slave.cs].chconf);
/* Enable the channel */
@@ -241,9 +241,10 @@ int omap3_spi_write(struct spi_slave *slave, unsigned
int len, const void *txp,
for (i = 0; i len; i++) {
/* wait till TX register is empty (TXS == 1) */
+ start = get_timer(0);
while (!(readl(ds-regs-channel[ds-slave.cs].chstat)
OMAP3_MCSPI_CHSTAT_TXS)) {
- if (--timeout = 0) {
+ if (get_timer(start) SPI_WAIT_TIMEOUT) {
printf(SPI TXS timed out, status=0x%08x\n,
readl(ds-regs-channel[ds-slave.cs].chstat));
return -1;
@@ -280,7 +281,7 @@ int omap3_spi_read(struct spi_slave *slave, unsigned int
len, void *rxp,
{
struct omap3_spi_slave *ds = to_omap3_spi(slave);
int i;
- int timeout = SPI_WAIT_TIMEOUT;
+ ulong start;
int chconf = readl(ds-regs-channel[ds-slave.cs].chconf);
/* Enable the channel */
@@ -295,10 +296,11 @@ int omap3_spi_read(struct spi_slave *slave, unsigned
int len, void *rxp,
writel(0, ds-regs-channel[ds-slave.cs].tx);
for (i = 0; i len; i++) {
+ start = get_timer(0);
/* Wait till RX register contains data (RXS == 1) */
while (!(readl(ds-regs-channel[ds-slave.cs].chstat)
OMAP3_MCSPI_CHSTAT_RXS)) {
- if (--timeout = 0) {
+ if (get_timer(start) SPI_WAIT_TIMEOUT) {
printf(SPI RXS timed out, status=0x%08x\n,
readl(ds-regs-channel[ds-slave.cs].chstat));
return -1;
@@ -332,7 +334,7 @@ int omap3_spi_txrx(struct spi_slave *slave, unsigned int
len,
const void *txp, void *rxp, unsigned long flags)
{
struct omap3_spi_slave *ds = to_omap3_spi(slave);
- int timeout = SPI_WAIT_TIMEOUT;
+ ulong start;
int chconf = readl(ds-regs-channel[ds-slave.cs].chconf);
int irqstatus = readl(ds-regs-irqstatus);
int i=0;
@@ -350,9 +352,10 @@ int omap3_spi_txrx(struct spi_slave *slave, unsigned int
len,
for (i=0; i len; i++){
/* Write: wait for TX empty (TXS == 1)*/
irqstatus |= (1 (4*(ds-slave.bus)));
+ start = get_timer(0);
while (!(readl(ds-regs-channel[ds-slave.cs].chstat)
OMAP3_MCSPI_CHSTAT_TXS)) {
- if (--timeout = 0) {
+ if (get_timer(start) SPI_WAIT_TIMEOUT) {
printf(SPI TXS timed out, status=0x%08x\n,
readl(ds-regs-channel[ds-slave.cs].chstat));
return -1;
@@ -368,9 +371,10 @@ int omap3_spi_txrx(struct spi_slave *slave, unsigned int
len,
writel(((u8 *)txp)[i], tx);
/*Read: wait for RX containing data (RXS == 1)*/
+ start = get_timer(0);
while (!(readl(ds-regs-channel[ds-slave.cs].chstat)
OMAP3_MCSPI_CHSTAT_RXS)) {
- if (--timeout = 0) {
+ if (get_timer(start) SPI_WAIT_TIMEOUT) {
printf(SPI RXS timed out, status=0x%08x\n,
readl(ds-regs-channel[ds-slave.cs].chstat));
return -1;
--
2.3.4
--
Jagan.
[U-Boot] [PATCH] spi: omap3: Fix timeout handling
The timeout value is never reset during the transfer. This means that when
transferring more data we eventually trigger the timeout.
This was reported on the mailing list:
Spansion SPI flash read timeout with AM335x
Signed-off-by: David Dueck davidcdu...@googlemail.com
CC: Tom Rini tr...@konsulko.com
CC: Jagannadh Teki jagannadh@t...@gmail.com
CC: Stefan Roese s...@denx.de
CC: Andy Pont andy.p...@sdcsystems.com
---
drivers/spi/omap3_spi.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 651e46e..c1b4b33 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -20,7 +20,7 @@
#include asm/io.h
#include omap3_spi.h
-#define SPI_WAIT_TIMEOUT 300
+#define SPI_WAIT_TIMEOUT 10
static void spi_reset(struct omap3_spi_slave *ds)
{
@@ -227,7 +227,7 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int
len, const void *txp,
{
struct omap3_spi_slave *ds = to_omap3_spi(slave);
int i;
- int timeout = SPI_WAIT_TIMEOUT;
+ ulong start;
int chconf = readl(ds-regs-channel[ds-slave.cs].chconf);
/* Enable the channel */
@@ -241,9 +241,10 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int
len, const void *txp,
for (i = 0; i len; i++) {
/* wait till TX register is empty (TXS == 1) */
+ start = get_timer(0);
while (!(readl(ds-regs-channel[ds-slave.cs].chstat)
OMAP3_MCSPI_CHSTAT_TXS)) {
- if (--timeout = 0) {
+ if (get_timer(0) - start SPI_WAIT_TIMEOUT) {
printf(SPI TXS timed out, status=0x%08x\n,
readl(ds-regs-channel[ds-slave.cs].chstat));
return -1;
@@ -280,7 +281,7 @@ int omap3_spi_read(struct spi_slave *slave, unsigned int
len, void *rxp,
{
struct omap3_spi_slave *ds = to_omap3_spi(slave);
int i;
- int timeout = SPI_WAIT_TIMEOUT;
+ ulong start;
int chconf = readl(ds-regs-channel[ds-slave.cs].chconf);
/* Enable the channel */
@@ -295,10 +296,11 @@ int omap3_spi_read(struct spi_slave *slave, unsigned int
len, void *rxp,
writel(0, ds-regs-channel[ds-slave.cs].tx);
for (i = 0; i len; i++) {
+ start = get_timer(0);
/* Wait till RX register contains data (RXS == 1) */
while (!(readl(ds-regs-channel[ds-slave.cs].chstat)
OMAP3_MCSPI_CHSTAT_RXS)) {
- if (--timeout = 0) {
+ if (get_timer(0) - start SPI_WAIT_TIMEOUT) {
printf(SPI RXS timed out, status=0x%08x\n,
readl(ds-regs-channel[ds-slave.cs].chstat));
return -1;
@@ -332,7 +334,7 @@ int omap3_spi_txrx(struct spi_slave *slave, unsigned int
len,
const void *txp, void *rxp, unsigned long flags)
{
struct omap3_spi_slave *ds = to_omap3_spi(slave);
- int timeout = SPI_WAIT_TIMEOUT;
+ ulong start;
int chconf = readl(ds-regs-channel[ds-slave.cs].chconf);
int irqstatus = readl(ds-regs-irqstatus);
int i=0;
@@ -350,9 +352,10 @@ int omap3_spi_txrx(struct spi_slave *slave, unsigned int
len,
for (i=0; i len; i++){
/* Write: wait for TX empty (TXS == 1)*/
irqstatus |= (1 (4*(ds-slave.bus)));
+ start = get_timer(0);
while (!(readl(ds-regs-channel[ds-slave.cs].chstat)
OMAP3_MCSPI_CHSTAT_TXS)) {
- if (--timeout = 0) {
+ if (get_timer(0) - start SPI_WAIT_TIMEOUT) {
printf(SPI TXS timed out, status=0x%08x\n,
readl(ds-regs-channel[ds-slave.cs].chstat));
return -1;
@@ -368,9 +371,10 @@ int omap3_spi_txrx(struct spi_slave *slave, unsigned int
len,
writel(((u8 *)txp)[i], tx);
/*Read: wait for RX containing data (RXS == 1)*/
+ start = get_timer(0);
while (!(readl(ds-regs-channel[ds-slave.cs].chstat)
OMAP3_MCSPI_CHSTAT_RXS)) {
- if (--timeout = 0) {
+ if (get_timer(0) - start SPI_WAIT_TIMEOUT) {
printf(SPI RXS timed out, status=0x%08x\n,
readl(ds-regs-channel[ds-slave.cs].chstat));
return -1;
--
2.3.4
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Re: [U-Boot] [PATCH v4 0/2] ARM: mx5: add support for USB armory board
Hi Chris, On 01/04/2015 04:46, Chris Kuethe wrote: Any chance of this being accepted into 2015.04? It was my intention to put it into the -next branch, ready to be merged after release. Anyway, if there is still time for a new PR, I will try to let it slipping in the current. First version of this patch was sent in February and it is not odd to merge it in 2015.04. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] cmd_mem: cleanups, catch bad usage
Currently, memtest will silently accept bad data. Perform error
checking on user intput.
Signed-off-by: Pavel Machek pa...@denx.de
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index bfca59e..e6623b0 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -994,10 +994,10 @@ static int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int
argc,
{
ulong start, end;
vu_long *buf, *dummy;
- int iteration_limit;
+ int iteration_limit = 0;
int ret;
ulong errs = 0; /* number of errors, or -1 if interrupted */
- ulong pattern;
+ ulong pattern = 0;
int iteration;
#if defined(CONFIG_SYS_ALT_MEMTEST)
const int alt_test = 1;
@@ -1005,25 +1005,29 @@ static int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int
argc,
const int alt_test = 0;
#endif
+ start = CONFIG_SYS_MEMTEST_START;
+ end = CONFIG_SYS_MEMTEST_END;
+
if (argc 1)
- start = simple_strtoul(argv[1], NULL, 16);
- else
- start = CONFIG_SYS_MEMTEST_START;
+ if (strict_strtoul(argv[1], 16, start) 0)
+ return CMD_RET_USAGE;
if (argc 2)
- end = simple_strtoul(argv[2], NULL, 16);
- else
- end = CONFIG_SYS_MEMTEST_END;
+ if (strict_strtoul(argv[2], 16, end) 0)
+ return CMD_RET_USAGE;
if (argc 3)
- pattern = (ulong)simple_strtoul(argv[3], NULL, 16);
- else
- pattern = 0;
+ if (strict_strtoul(argv[3], 16, pattern) 0)
+ return CMD_RET_USAGE;
if (argc 4)
- iteration_limit = (ulong)simple_strtoul(argv[4], NULL, 16);
- else
- iteration_limit = 0;
+ if (strict_strtoul(argv[4], 16, iteration_limit) 0)
+ return CMD_RET_USAGE;
+
+ if (end start) {
+ printf(Refusing to do empty test\n);
+ return -1;
+ }
printf(Testing %08x ... %08x:\n, (uint)start, (uint)end);
debug(%s:%d: start %#08lx end %#08lx\n, __func__, __LINE__,
@@ -1074,7 +1078,7 @@ static int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int
argc,
ret = errs != 0;
}
- return ret; /* not reached */
+ return ret;
}
#endif /* CONFIG_CMD_MEMTEST */
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures)
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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[U-Boot] [PATCH 1/3] config: exynos: common: Provide env variables to support Image.itb
This change allows using Image.itb image format with Exynos4 devices
(especially trats and trats2).
Such change facilitates automated testing since only one binary needs
to be prepared.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
---
include/configs/exynos4-common.h | 54
1 file changed, 54 insertions(+)
diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h
index 41631c7..577afe7 100644
--- a/include/configs/exynos4-common.h
+++ b/include/configs/exynos4-common.h
@@ -66,4 +66,58 @@
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_GADGET_MASS_STORAGE
+/* Common environment variables */
+#define CONFIG_EXTRA_ENV_ITB \
+ loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} \
+ ${kernelname}\0 \
+ loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} \
+ ${initrdname}\0 \
+ loaddtb=load mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} \
+ ${fdtfile}\0 \
+ check_ramdisk= \
+ if run loadinitrd; then \
+ setenv initrd_addr ${initrdaddr}; \
+ else \
+ setenv initrd_addr -; \
+ fi;\0 \
+ check_dtb= \
+ if run loaddtb; then \
+ setenv fdt_addr ${fdtaddr}; \
+ else \
+ setenv fdt_addr; \
+ fi;\0 \
+ kernel_args= \
+ setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} \
+${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};\0 \
+ boot_fit= \
+ setenv kerneladdr 0x4200; \
+ setenv kernelname Image.itb; \
+ run loadkernel; \
+ run kernel_args; \
+ bootm ${kerneladdr}#${board_name}\0 \
+ boot_uimg= \
+ setenv kerneladdr 0x40007FC0; \
+ setenv kernelname uImage; \
+ run check_dtb; \
+ run check_ramdisk; \
+ run loadkernel; \
+ run kernel_args; \
+ bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0 \
+ boot_zimg= \
+ setenv kerneladdr 0x40007FC0; \
+ setenv kernelname zImage; \
+ run check_dtb; \
+ run check_ramdisk; \
+ run loadkernel; \
+ run kernel_args; \
+ bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0 \
+ autoboot= \
+ if test -e mmc ${mmcdev}:${mmcbootpart} Image.itb; then; \
+ run boot_fit; \
+ elif test -e mmc ${mmcdev}:${mmcbootpart} zImage; then; \
+ run boot_zimg; \
+ elif test -e mmc ${mmcdev}:${mmcbootpart} uImage; then; \
+ run boot_uimg; \
+ fi;\0
+
#endif /* __CONFIG_EXYNOS4_COMMON_H */
--
2.0.0.rc2
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[U-Boot] [PATCH 2/3] config: exynos: trats: Enable support for Image.itb at trats device
After this change it is possible to boot trats device with Image.itb, which facilitates automated testing, since only one file is necessary. Signed-off-by: Lukasz Majewski l.majew...@samsung.com --- include/configs/trats.h | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/configs/trats.h b/include/configs/trats.h index b21ea2d..6808e78 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -51,8 +51,10 @@ #define MACH_TYPE_TRATS3928 #define CONFIG_MACH_TYPE MACH_TYPE_TRATS +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE #define CONFIG_BOOTARGSPlease use defined boot -#define CONFIG_BOOTCOMMAND run mmcboot +#define CONFIG_BOOTCOMMAND run autoboot #define CONFIG_DEFAULT_CONSOLE console=ttySAC2,115200n8\0 #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_LOAD_ADDR \ @@ -106,7 +108,8 @@ PARTS_ROOT part 0 5; \ PARTS_DATA part 0 6; \ PARTS_UMS part 0 7; \ - params.bin raw 0x38 0x8\0 + params.bin raw 0x38 0x8; \ + /Image.itb ext4 0 2\0 #define CONFIG_EXTRA_ENV_SETTINGS \ bootk= \ @@ -172,6 +175,7 @@ setenv spl_imgsize; \ setenv spl_imgaddr; \ setenv spl_addr_tmp;\0 \ + CONFIG_EXTRA_ENV_ITB \ fdtaddr=4080\0 \ /* Falcon mode definitions */ -- 2.0.0.rc2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] config: exynos: trats2: Enable support for Image.itb at trats2 device
After this change it is possible to boot trats2 device with Image.itb, which facilitates automated testing, since only one file is necessary. Signed-off-by: Lukasz Majewski l.majew...@samsung.com --- include/configs/trats2.h | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 42481ab..94c31fb 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -44,8 +44,10 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE #define CONFIG_BOOTARGSPlease use defined boot -#define CONFIG_BOOTCOMMAND run mmcboot +#define CONFIG_BOOTCOMMAND run autoboot #define CONFIG_DEFAULT_CONSOLE console=ttySAC2,115200n8\0 #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_LOAD_ADDR \ @@ -96,7 +98,8 @@ PARTS_ROOT part 0 5; \ PARTS_DATA part 0 6; \ PARTS_UMS part 0 7; \ - params.bin raw 0x38 0x8\0 + params.bin raw 0x38 0x8; \ + /Image.itb ext4 0 2\0 #define CONFIG_EXTRA_ENV_SETTINGS \ bootk= \ @@ -153,6 +156,7 @@ setenv spl_imgsize; \ setenv spl_imgaddr; \ setenv spl_addr_tmp;\0 \ + CONFIG_EXTRA_ENV_ITB \ fdtaddr=4080\0 \ /* GPT */ -- 2.0.0.rc2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] buildman: Make -V (verbose_build) really be verbose
The help text for -V says we will pass V=1 but all it really did was not
pass in -s. Change the logic to pass make V=1 with given to buildman -V or
-s to make otherwise.
Cc: Simon Glass s...@chromium.org
Signed-off-by: Tom Rini tr...@konsulko.com
---
tools/buildman/builderthread.py |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py
index efb62f1..d7e7a78 100644
--- a/tools/buildman/builderthread.py
+++ b/tools/buildman/builderthread.py
@@ -197,7 +197,9 @@ class BuilderThread(threading.Thread):
src_dir = os.getcwd()
else:
args.append('O=build')
-if not self.builder.verbose_build:
+if self.builder.verbose_build:
+args.append('V=1')
+else:
args.append('-s')
if self.builder.num_jobs is not None:
args.extend(['-j', str(self.builder.num_jobs)])
--
1.7.9.5
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Re: [U-Boot] [PATCH] spi: omap3: Fix timeout handling
On 1 April 2015 at 17:02, David Dueck davidcdu...@googlemail.com wrote:
The timeout value is never reset during the transfer. This means that when
transferring more data we eventually trigger the timeout.
This was reported on the mailing list:
Spansion SPI flash read timeout with AM335x
Signed-off-by: David Dueck davidcdu...@googlemail.com
CC: Tom Rini tr...@konsulko.com
CC: Jagannadh Teki jagannadh@t...@gmail.com
CC: Stefan Roese s...@denx.de
CC: Andy Pont andy.p...@sdcsystems.com
---
drivers/spi/omap3_spi.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index 651e46e..c1b4b33 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -20,7 +20,7 @@
#include asm/io.h
#include omap3_spi.h
-#define SPI_WAIT_TIMEOUT 300
+#define SPI_WAIT_TIMEOUT 10
static void spi_reset(struct omap3_spi_slave *ds)
{
@@ -227,7 +227,7 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int
len, const void *txp,
{
struct omap3_spi_slave *ds = to_omap3_spi(slave);
int i;
- int timeout = SPI_WAIT_TIMEOUT;
+ ulong start;
int chconf = readl(ds-regs-channel[ds-slave.cs].chconf);
/* Enable the channel */
@@ -241,9 +241,10 @@ int omap3_spi_write(struct spi_slave *slave, unsigned
int len, const void *txp,
for (i = 0; i len; i++) {
/* wait till TX register is empty (TXS == 1) */
+ start = get_timer(0);
while (!(readl(ds-regs-channel[ds-slave.cs].chstat)
OMAP3_MCSPI_CHSTAT_TXS)) {
- if (--timeout = 0) {
+ if (get_timer(0) - start SPI_WAIT_TIMEOUT) {
printf(SPI TXS timed out, status=0x%08x\n,
readl(ds-regs-channel[ds-slave.cs].chstat));
return -1;
@@ -280,7 +281,7 @@ int omap3_spi_read(struct spi_slave *slave, unsigned int
len, void *rxp,
{
struct omap3_spi_slave *ds = to_omap3_spi(slave);
int i;
- int timeout = SPI_WAIT_TIMEOUT;
+ ulong start;
int chconf = readl(ds-regs-channel[ds-slave.cs].chconf);
/* Enable the channel */
@@ -295,10 +296,11 @@ int omap3_spi_read(struct spi_slave *slave, unsigned
int len, void *rxp,
writel(0, ds-regs-channel[ds-slave.cs].tx);
for (i = 0; i len; i++) {
+ start = get_timer(0);
/* Wait till RX register contains data (RXS == 1) */
while (!(readl(ds-regs-channel[ds-slave.cs].chstat)
OMAP3_MCSPI_CHSTAT_RXS)) {
- if (--timeout = 0) {
+ if (get_timer(0) - start SPI_WAIT_TIMEOUT) {
I think this is redundant, please check ie negation to start
what about this
start = get_timer(0);
-
if (get_timer(start) SPI_WAIT_TIMEOUT) {
printf(SPI RXS timed out, status=0x%08x\n,
readl(ds-regs-channel[ds-slave.cs].chstat));
return -1;
@@ -332,7 +334,7 @@ int omap3_spi_txrx(struct spi_slave *slave, unsigned int
len,
const void *txp, void *rxp, unsigned long flags)
{
struct omap3_spi_slave *ds = to_omap3_spi(slave);
- int timeout = SPI_WAIT_TIMEOUT;
+ ulong start;
int chconf = readl(ds-regs-channel[ds-slave.cs].chconf);
int irqstatus = readl(ds-regs-irqstatus);
int i=0;
@@ -350,9 +352,10 @@ int omap3_spi_txrx(struct spi_slave *slave, unsigned int
len,
for (i=0; i len; i++){
/* Write: wait for TX empty (TXS == 1)*/
irqstatus |= (1 (4*(ds-slave.bus)));
+ start = get_timer(0);
while (!(readl(ds-regs-channel[ds-slave.cs].chstat)
OMAP3_MCSPI_CHSTAT_TXS)) {
- if (--timeout = 0) {
+ if (get_timer(0) - start SPI_WAIT_TIMEOUT) {
printf(SPI TXS timed out, status=0x%08x\n,
readl(ds-regs-channel[ds-slave.cs].chstat));
return -1;
@@ -368,9 +371,10 @@ int omap3_spi_txrx(struct spi_slave *slave, unsigned int
len,
writel(((u8 *)txp)[i], tx);
/*Read: wait for RX containing data (RXS == 1)*/
+ start = get_timer(0);
while (!(readl(ds-regs-channel[ds-slave.cs].chstat)
OMAP3_MCSPI_CHSTAT_RXS)) {
- if (--timeout = 0) {
+ if (get_timer(0) - start SPI_WAIT_TIMEOUT) {
printf(SPI RXS timed out, status=0x%08x\n,
Re: [U-Boot] [RESEND PATCH 6/6] ARM: vf610: Initial integration for Colibri VF50/VF61
Hi Sanchayan, Some minor details I stumbled upon: On 2015-04-01 11:54, Sanchayan Maity wrote: This adds initial support for Colibri VF50/VF61 based on Freescale Vybrid SoC. - CPU clocked at 396/500 MHz - DDR3 at 396MHz - for VF50, use PLL2 as memory clock (synchronous mode) - for VF61, use PLL1 as memory clock (asynchronous mode) - Console on UART0 (Colibri UART_A) - Ethernet on FEC1 - PLL5 based RMII clocking (E.g. No external crystal) - UART_A and UART_C I/O muxing - Boot from NAND by default - USB host and client support Tested on Colibri VF50/VF61 booting using serial loader over UART. Signed-off-by: Stefan Agner ste...@agner.ch Signed-off-by: Sanchayan Maity maitysancha...@gmail.com --- arch/arm/Kconfig | 5 + arch/arm/include/asm/arch-vf610/imx-regs.h | 5 + board/toradex/colibri_vf/Kconfig | 18 ++ board/toradex/colibri_vf/MAINTAINERS | 6 + board/toradex/colibri_vf/Makefile | 7 + board/toradex/colibri_vf/colibri_vf.c | 389 + board/toradex/colibri_vf/imximage.cfg | 17 ++ configs/colibri_vf_defconfig | 3 + include/configs/colibri_vf.h | 266 9 files changed, 716 insertions(+) create mode 100644 board/toradex/colibri_vf/Kconfig create mode 100644 board/toradex/colibri_vf/MAINTAINERS create mode 100644 board/toradex/colibri_vf/Makefile create mode 100644 board/toradex/colibri_vf/colibri_vf.c create mode 100644 board/toradex/colibri_vf/imximage.cfg create mode 100644 configs/colibri_vf_defconfig create mode 100644 include/configs/colibri_vf.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 80b0d34..e32a942 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -608,6 +608,10 @@ config TARGET_VF610TWR bool Support vf610twr select CPU_V7 +config TARGET_COLIBRI_VF + bool Support Colibri VF50/61 + select CPU_V7 + config ZYNQ bool Xilinx Zynq Platform select CPU_V7 @@ -864,6 +868,7 @@ source board/ti/ti814x/Kconfig source board/ti/ti816x/Kconfig source board/timll/devkit3250/Kconfig source board/toradex/colibri_pxa270/Kconfig +source board/toradex/colibri_vf/Kconfig source board/tqc/tqma6/Kconfig source board/trizepsiv/Kconfig source board/ttcontrol/vision2/Kconfig diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 26057fe..a7d765a 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -267,6 +267,11 @@ #define SRC_SRSR_WDOG_M4 (0x1 4) #define SRC_SRSR_WDOG_A5 (0x1 3) #define SRC_SRSR_POR_RST (0x1 0) +#define SRC_SBMR2_BMOD_MASK (0x3 24) +#define SRC_SBMR2_BMOD_SHIFT24 +#define SRC_SBMR2_BMOD_FUSES0x0 +#define SRC_SBMR2_BMOD_SERIAL 0x1 +#define SRC_SBMR2_BMOD_RCON 0x2 /* Slow Clock Source Controller Module (SCSC) */ #define SCSC_SOSC_CTR_SOSC_EN0x1 diff --git a/board/toradex/colibri_vf/Kconfig b/board/toradex/colibri_vf/Kconfig new file mode 100644 index 000..2c3cb30 --- /dev/null +++ b/board/toradex/colibri_vf/Kconfig @@ -0,0 +1,18 @@ +if TARGET_COLIBRI_VF + +config SYS_CPU + default armv7 + +config SYS_BOARD + default colibri_vf + +config SYS_VENDOR + default toradex + +config SYS_SOC + default vf610 + +config SYS_CONFIG_NAME + default colibri_vf + +endif diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS new file mode 100644 index 000..551c575 --- /dev/null +++ b/board/toradex/colibri_vf/MAINTAINERS @@ -0,0 +1,6 @@ +Colibri VFxx +M: Stefan Agner stefan.ag...@toradex.com +S: Maintained +F: board/toradex/colibri_vf/ +F: include/configs/colibri_vf.h +F: configs/colibri_vf_defconfig diff --git a/board/toradex/colibri_vf/Makefile b/board/toradex/colibri_vf/Makefile new file mode 100644 index 000..c7e5134 --- /dev/null +++ b/board/toradex/colibri_vf/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y:= colibri_vf.o diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c new file mode 100644 index 000..62f3013 --- /dev/null +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -0,0 +1,389 @@ +/* + * Copyright 2015 Toradex, Inc. + * + * Based on vf610twr.c: + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include common.h +#include asm/io.h +#include asm/arch/imx-regs.h +#include asm/arch/iomux-vf610.h +#include asm/arch/ddrmc-vf610.h +#include asm/arch/crm_regs.h +#include asm/arch/clock.h +#include mmc.h +#include fsl_esdhc.h
Re: [U-Boot] [PATCH v2] MAKEALL: fix get_target_arch() to adjust to '-' in Status field
On Tue, Mar 31, 2015 at 08:39:57PM -0600, Simon Glass wrote: Hi Masahiro, On 30 March 2015 at 05:59, Masahiro Yamada yamada.masah...@socionext.com wrote: Since the Kconfig conversion, boards.cfg scanned by MAKEALL is generated by tools/genboardscfg.py. Every board is supposed to have its own MAINTAINERS that contains maintainer and status information, but, in fact, MAINTAINERS is missing from some boards. For such boards, the first field, Status, is filled with '-'. It causes a problem for set command, which ignores '-' in its arguments. Consequently, get_target_arch() returns a wrong field and MAKEALL fails to get a correct toolchain. Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com - Improve git description Should we perhaps apply the patch to deprecate MAKEALL? With the last patch I posted about what binaries to save all my usecases are covered now. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Hi Simon, On 03/31/2015 07:32 PM, Simon Glass wrote: Hi Gabriel, On 27 February 2015 at 01:52, Bin Meng bmeng...@gmail.com wrote: Hi Gabriel, On Fri, Feb 27, 2015 at 3:54 PM, gabriel huau cont...@huau-gabriel.fr wrote: Hi Bin, On 02/26/2015 07:30 PM, Bin Meng wrote: Hi Gabriel, On Thu, Feb 26, 2015 at 12:27 AM, Gabriel Huau cont...@huau-gabriel.fr wrote: Hi Bin, On 02/24/2015 11:52 PM, Bin Meng wrote: Hi Gabriel, On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau cont...@huau-gabriel.fr wrote: Configure the pinctrl as it required to make some IO controllers working (USB/UART/I2C/...). The idea would be in the next version to modify the pch GPIO driver and configure these pins through the device tree. These modifications are ported from the coreboot project. Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- arch/x86/cpu/baytrail/Makefile| 1 + arch/x86/cpu/baytrail/gpio.c | 206 +++ arch/x86/include/asm/arch-baytrail/gpio.h | 364 ++ arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ arch/x86/include/asm/arch-baytrail/irq.h | 119 + arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++ arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++ board/intel/minnowmax/minnowmax.c | 212 +++ include/configs/minnowmax.h | 11 + 10 files changed, 1450 insertions(+) create mode 100644 arch/x86/cpu/baytrail/gpio.c create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h [snip] diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 823e051..738c6fa 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -69,4 +69,15 @@ /* Avoid a warning in the Realtek Ethernet driver */ #define CONFIG_SYS_CACHELINE_SIZE 16 +/* + * Baytrail has 3 GPIOs bank over PCI, there is no + * driver at the moment so let's disable the command + * and the default x86 driver to avoid any collision + * with the GPIO mapping code. + * @TODO: adding a baytrail-gpio driver and configure + * the muxing through the device tree + */ +#undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_CMD_GPIO + Why undef these two? The BayTrail SoC does support GPIO banks in the legacy bridge. I might misunderstood the GPIO subsystem but I thought there was 2 banks available through the PCU iLB GPIO controller which contains the SCORE and SSUS (102 / 44 pins). The intel_ich6_gpio has a limitation of 32 GPIOs per bank and I thought it was just a different controller from the Baytrail, but if I can use it to control all the GPIOs + doing the IO mapping, I'll be glad to do it! I checked the BayTrail datasheet. Its GPIO is in the iLB (legacy bridge), which is the same as other IA chipset (Ivybridge, TunnelCreek, Quark). It has 4 banks in core domain and 2 banks in sus domain. So 6 banks in total. You need define 6 gpio nodes in the minnowmax board dts file. You should be able to use the existing gpio driver to configure. Thanks for the clarification! Actually, I saw it today when I was doing some tests and I configured the 6 banks in the devices tree. I also fixed the GPIO base address to 0x48 but I got some issues like the fact I'm reading only 0 from all the registers. Yep, the offset should be 0x48 for BayTrail. The registers are configured to be in the IO Space (0x500), I checked the PCI configuration space to make sure that everything is enabled correctly, but I'm still missing something. I checked the gpio driver codes, and it currently has: /* * Okay, I guess we're looking at the right device. The actual * GPIO registers are in the PCI device's I/O space, starting * at the offset that we just read. Bit 0 indicates that it's * an I/O address, not a memory address, so mask that off. */ gpiobase = tmplong 0xfffe; This should be changed to gpiobase = tmplong 0xfffc; as bit1 is the enable bit on BayTrail (Intel changes this GPIO base register again for BayTrail, sigh...) Once I'll be able to use these GPIOs, I will update the entire patch to remove the port from Coreboot as this is not necessary. #endif /* __CONFIG_H */ -- What is the next step with this patch please? It would be good to apply it to with the changes discussed. Sorry, actually I was super busy and wasn't able to work on the minnowboard max ... I should have some time this week end. But you can go ahead and drop this patch, I will submit a new one because most of the modification are actually not needed, we
Re: [U-Boot] [RESEND PATCH 0/6] Add support for Colibri Vybrid Modules
On Wed, Apr 01, 2015 at 03:24:17PM +0530, Sanchayan Maity wrote: Hello, This patchset adds support for the Toradex Colibri Vybrid VF50 and VF61 modules. Boot up has been tested using the serial loader over UART. First patch in the series refactors the DDR related code for use by both the tower board and colibri modules. It also introduces a DDR3 based JEDEC timing structure. Second third and fourth patch in this series are improvement patches related to RTC, SoC/CPU detection and caches. Fifth patch introduces USB support for Vybrid modules. Much of the code is similar to the ehci-mx6 driver. One open question here would be is there a better way to take care of this similarity and perhaps share the code base among the two drivers? Both host and client modes are working and DFU has also been tested. Currently, we restrict the ports to be in one of host and client mode. Sixth patch adds the actual support for the Colibri modules. Comments and feedback are most welcome. Aside from the minor comments, I'll take this after the release, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/2] ARM: tegra: pinmux/colibri_t20: fix nand pinmux
On Wed, 2015-04-01 at 15:24 +0200, Marcel Ziswiler wrote: Do you happen to know about the plans for my remaining three patches? http://article.gmane.org/gmane.comp.boot-loaders.u-boot/216038 http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/216039 http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/216040 Sorry, I just noticed they already made it in there as well. Thank you very much, Tom. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/2] ARM: tegra: pinmux/colibri_t20: fix nand pinmux
On Tue, 2015-03-31 at 22:46 +, Tom Warren wrote: This series applied to u-boot-tegra/next. I'll push an update today or tomorrow to Denx.de. Very good. Thanks! Do you happen to know about the plans for my remaining three patches? http://article.gmane.org/gmane.comp.boot-loaders.u-boot/216038 http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/216039 http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/216040 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] usb: Convert protocol header structures to use explicitly sized variables
This patch converts USB protocol headers to use explicitly sized
fields like the rest of the code
Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com
Signed-off-by: Sergey Temerkhanov s.temerkha...@gmail.com
---
include/usb.h | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/usb.h b/include/usb.h
index a8fee0b..2c3d506 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -45,20 +45,20 @@
/* device request (setup) */
struct devrequest {
- unsigned char requesttype;
- unsigned char request;
- unsigned short value;
- unsigned short index;
- unsigned short length;
+ __u8requesttype;
+ __u8request;
+ __le16 value;
+ __le16 index;
+ __le16 length;
} __attribute__ ((packed));
/* Interface */
struct usb_interface {
struct usb_interface_descriptor desc;
- unsigned char no_of_ep;
- unsigned char num_altsetting;
- unsigned char act_altsetting;
+ __u8no_of_ep;
+ __u8num_altsetting;
+ __u8act_altsetting;
struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS];
/*
@@ -73,7 +73,7 @@ struct usb_interface {
struct usb_config {
struct usb_config_descriptor desc;
- unsigned char no_of_if; /* number of interfaces */
+ __u8no_of_if; /* number of interfaces */
struct usb_interface if_desc[USB_MAXINTERFACES];
} __attribute__ ((packed));
--
2.3.3
___
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[U-Boot] [PATCH 2/3] usb: 64-bit architectures support for xHCI
This commit allows xHCI to use both 64 and 32 bit memory
physical addresses depending on architecture it's being built for.
Also it makes use of readq()/writeq() on 64-bit systems
Signed-off-by: Sergey Temerkhanov s.temerkha...@gmail.com
Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com
---
drivers/usb/host/xhci-mem.c | 20 ++--
drivers/usb/host/xhci-ring.c | 30 +++---
drivers/usb/host/xhci.c | 10 +-
drivers/usb/host/xhci.h | 13 +++--
4 files changed, 41 insertions(+), 32 deletions(-)
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 89908e8..10f11cd 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -31,7 +31,7 @@
* @param len the length of the cache line to be flushed
* @return none
*/
-void xhci_flush_cache(uint32_t addr, u32 len)
+void xhci_flush_cache(uintptr_t addr, u32 len)
{
BUG_ON((void *)addr == NULL || len == 0);
@@ -46,7 +46,7 @@ void xhci_flush_cache(uint32_t addr, u32 len)
* @param len the length of the cache line to be invalidated
* @return none
*/
-void xhci_inval_cache(uint32_t addr, u32 len)
+void xhci_inval_cache(uintptr_t addr, u32 len)
{
BUG_ON((void *)addr == NULL || len == 0);
@@ -175,7 +175,7 @@ static void *xhci_malloc(unsigned int size)
BUG_ON(!ptr);
memset(ptr, '\0', size);
- xhci_flush_cache((uint32_t)ptr, size);
+ xhci_flush_cache((uintptr_t)ptr, size);
return ptr;
}
@@ -400,8 +400,8 @@ int xhci_alloc_virt_device(struct usb_device *udev)
/* Point to output device context in dcbaa. */
ctrl-dcbaa-dev_context_ptrs[slot_id] = byte_64;
- xhci_flush_cache((uint32_t)ctrl-dcbaa-dev_context_ptrs[slot_id],
- sizeof(__le64));
+ xhci_flush_cache((uintptr_t)ctrl-dcbaa-dev_context_ptrs[slot_id],
+sizeof(__le64));
return 0;
}
@@ -478,8 +478,8 @@ int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr
*hccr,
entry-rsvd = 0;
seg = seg-next;
}
- xhci_flush_cache((uint32_t)ctrl-erst.entries,
- ERST_NUM_SEGS * sizeof(struct xhci_erst_entry));
+ xhci_flush_cache((uintptr_t)ctrl-erst.entries,
+ERST_NUM_SEGS * sizeof(struct xhci_erst_entry));
deq = (unsigned long)ctrl-event_ring-dequeue;
@@ -496,7 +496,7 @@ int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr
*hccr,
/* this is the event ring segment table pointer */
val_64 = xhci_readq(ctrl-ir_set-erst_base);
val_64 = ERST_PTR_MASK;
- val_64 |= ((u32)(ctrl-erst.entries) ~ERST_PTR_MASK);
+ val_64 |= ((uintptr_t)(ctrl-erst.entries) ~ERST_PTR_MASK);
xhci_writeq(ctrl-ir_set-erst_base, val_64);
@@ -715,6 +715,6 @@ void xhci_setup_addressable_virt_dev(struct usb_device
*udev)
/* Steps 7 and 8 were done in xhci_alloc_virt_device() */
- xhci_flush_cache((uint32_t)ep0_ctx, sizeof(struct xhci_ep_ctx));
- xhci_flush_cache((uint32_t)slot_ctx, sizeof(struct xhci_slot_ctx));
+ xhci_flush_cache((uintptr_t)ep0_ctx, sizeof(struct xhci_ep_ctx));
+ xhci_flush_cache((uintptr_t)slot_ctx, sizeof(struct xhci_slot_ctx));
}
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index b5aade9..f3759d4 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -122,8 +122,8 @@ static void inc_enq(struct xhci_ctrl *ctrl, struct
xhci_ring *ring,
next-link.control |= cpu_to_le32(chain);
next-link.control ^= cpu_to_le32(TRB_CYCLE);
- xhci_flush_cache((uint32_t)next,
- sizeof(union xhci_trb));
+ xhci_flush_cache((uintptr_t)next,
+sizeof(union xhci_trb));
}
/* Toggle the cycle bit after the last ring segment. */
if (last_trb_on_last_seg(ctrl, ring,
@@ -191,7 +191,7 @@ static struct xhci_generic_trb *queue_trb(struct xhci_ctrl
*ctrl,
for (i = 0; i 4; i++)
trb-field[i] = cpu_to_le32(trb_fields[i]);
- xhci_flush_cache((uint32_t)trb, sizeof(struct xhci_generic_trb));
+ xhci_flush_cache((uintptr_t)trb, sizeof(struct xhci_generic_trb));
inc_enq(ctrl, ring, more_trbs_coming);
@@ -244,7 +244,7 @@ static int prepare_ring(struct xhci_ctrl *ctrl, struct
xhci_ring *ep_ring,
next-link.control ^= cpu_to_le32(TRB_CYCLE);
- xhci_flush_cache((uint32_t)next, sizeof(union xhci_trb));
+ xhci_flush_cache((uintptr_t)next, sizeof(union xhci_trb));
/* Toggle the cycle bit after the last ring segment. */
if (last_trb_on_last_seg(ctrl, ep_ring,
@@ -364,7 +364,7 @@ static void
[U-Boot] [PATCH 0/3] USB subsystem changes for 64 bit
This patch series contains USB fixes and enhancements for more complete support of 64-bit architectures ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] usb_storage:Fix USB storage capacity detection on 64 bit architectures
This patch fixes USB storage capacity detection breakage on 64-bit systems
which arises due to 'unsigned long' length difference. Old code assumes that
to be 32 bit and breaks because of inappropriate response buffer layout.
Also this fixes a number of build warnings and changes big-endian values
treatment style to be architecture-independent
Signed-off-by: Sergey Temerkhanov s.temerkha...@gmail.com
Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com
---
common/usb_storage.c | 44 +++-
1 file changed, 23 insertions(+), 21 deletions(-)
diff --git a/common/usb_storage.c b/common/usb_storage.c
index 1411737..a1dfc58 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -336,8 +336,8 @@ static int us_one_transfer(struct us_data *us, int pipe,
char *buf, int length)
/* set up the transfer loop */
do {
/* transfer the data */
- debug(Bulk xfer 0x%x(%d) try #%d\n,
- (unsigned int)buf, this_xfer, 11 - maxtry);
+ debug(Bulk xfer %p(%d) try #%d\n,
+ buf, this_xfer, 11 - maxtry);
result = usb_bulk_msg(us-pusb_dev, pipe, buf,
this_xfer, partial,
USB_CNTL_TIMEOUT * 5);
@@ -514,6 +514,7 @@ static int usb_stor_BBB_comdat(ccb *srb, struct us_data *us)
cbw-bCDBLength = srb-cmdlen;
/* copy the command data into the CBW command data buffer */
/* DST SRC LEN!!! */
+
memcpy(cbw-CBWCDB, srb-cmd, srb-cmdlen);
result = usb_bulk_msg(us-pusb_dev, pipe, cbw, UMASS_BBB_CBW_SIZE,
actlen, USB_CNTL_TIMEOUT * 5);
@@ -603,7 +604,7 @@ static int usb_stor_CBI_get_status(ccb *srb, struct us_data
*us)
(void *) us-ip_data, us-irqmaxp, us-irqinterval);
timeout = 1000;
while (timeout--) {
- if ((volatile int *) us-ip_wanted == NULL)
+ if (us-ip_wanted == 0)
break;
mdelay(10);
}
@@ -689,6 +690,7 @@ static int usb_stor_BBB_transport(ccb *srb, struct us_data
*us)
pipe = pipein;
else
pipe = pipeout;
+
result = usb_bulk_msg(us-pusb_dev, pipe, srb-pdata, srb-datalen,
data_actlen, USB_CNTL_TIMEOUT * 5);
/* special handling of STALL in DATA phase */
@@ -1067,7 +1069,7 @@ unsigned long usb_stor_read(int device, lbaint_t blknr,
usb_disable_asynch(1); /* asynch transfer not allowed */
srb-lun = usb_dev_desc[device].lun;
- buf_addr = (unsigned long)buffer;
+ buf_addr = (uintptr_t)buffer;
start = blknr;
blks = blkcnt;
@@ -1141,7 +1143,7 @@ unsigned long usb_stor_write(int device, lbaint_t blknr,
usb_disable_asynch(1); /* asynch transfer not allowed */
srb-lun = usb_dev_desc[device].lun;
- buf_addr = (unsigned long)buffer;
+ buf_addr = (uintptr_t)buffer;
start = blknr;
blks = blkcnt;
@@ -1334,9 +1336,9 @@ int usb_stor_get_info(struct usb_device *dev, struct
us_data *ss,
block_dev_desc_t *dev_desc)
{
unsigned char perq, modi;
- ALLOC_CACHE_ALIGN_BUFFER(unsigned long, cap, 2);
- ALLOC_CACHE_ALIGN_BUFFER(unsigned char, usb_stor_buf, 36);
- unsigned long *capacity, *blksz;
+ ALLOC_CACHE_ALIGN_BUFFER(u32, cap, 2);
+ ALLOC_CACHE_ALIGN_BUFFER(u8, usb_stor_buf, 36);
+ u32 capacity, blksz;
ccb *pccb = usb_ccb;
pccb-pdata = usb_stor_buf;
@@ -1362,9 +1364,9 @@ int usb_stor_get_info(struct usb_device *dev, struct
us_data *ss,
/* drive is removable */
dev_desc-removable = 1;
}
- memcpy(dev_desc-vendor[0], (const void *) usb_stor_buf[8], 8);
- memcpy(dev_desc-product[0], (const void *) usb_stor_buf[16], 16);
- memcpy(dev_desc-revision[0], (const void *) usb_stor_buf[32], 4);
+ memcpy(dev_desc-vendor, (const void *)usb_stor_buf[8], 8);
+ memcpy(dev_desc-product, (const void *)usb_stor_buf[16], 16);
+ memcpy(dev_desc-revision, (const void *)usb_stor_buf[32], 4);
dev_desc-vendor[8] = 0;
dev_desc-product[16] = 0;
dev_desc-revision[4] = 0;
@@ -1385,7 +1387,7 @@ int usb_stor_get_info(struct usb_device *dev, struct
us_data *ss,
}
return 0;
}
- pccb-pdata = (unsigned char *)cap[0];
+ pccb-pdata = (unsigned char *)cap;
memset(pccb-pdata, 0, 8);
if (usb_read_capacity(pccb, ss) != 0) {
printf(READ_CAP ERROR\n);
@@ -1393,21 +1395,21 @@ int usb_stor_get_info(struct usb_device *dev, struct
us_data *ss,
cap[1] = 0x200;
}
ss-flags = ~USB_READY;
- debug(Read Capacity returns: 0x%lx,
Re: [U-Boot] [PATCH] dm: eth: Provide a way for drivers to manage packet buffers
Hi Simon,
On Tue, Mar 31, 2015 at 10:32 PM, Simon Glass s...@chromium.org wrote:
Hi Joe,
On 30 March 2015 at 14:44, Joe Hershberger joe.hershber...@ni.com wrote:
Some drivers need a chance to manage their receive buffers after the
packet has been handled by the network stack. Add an operation that
will allow the driver to be called in that case.
Reported-by: Simon Glass s...@chromium.org
Signed-off-by: Joe Hershberger joe.hershber...@ni.com
---
This patch depends on dm/next
include/net.h | 4
net/eth.c | 8 ++--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/include/net.h b/include/net.h
index e7f28d7..f9df532 100644
--- a/include/net.h
+++ b/include/net.h
@@ -98,6 +98,9 @@ struct eth_pdata {
* recv: Check if the hardware received a packet. If so, set the
pointer to the
* packet buffer in the packetp parameter. If not, return an
error or 0 to
* indicate that the hardware receive FIFO is empty
+ * free_pkt: Give the driver an opportunity to manage its packet
buffer memory
+ * when the network stack is finished processing it. This
will only be
+ * called when a packet was successfully returned from recv -
optional
* stop: Stop the hardware from looking for packets - may be called
even if
* state == PASSIVE
* mcast: Join or leave a multicast group (for TFTP) - optional
@@ -113,6 +116,7 @@ struct eth_ops {
int (*start)(struct udevice *dev);
int (*send)(struct udevice *dev, void *packet, int length);
int (*recv)(struct udevice *dev, uchar **packetp);
+ int (*free_pkt)(struct udevice *dev, uchar *packet, int length);
void (*stop)(struct udevice *dev);
#ifdef CONFIG_MCAST_TFTP
int (*mcast)(struct udevice *dev, const u8 *enetaddr, int join);
diff --git a/net/eth.c b/net/eth.c
index 13b7723..889ad8f 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -342,10 +342,14 @@ int eth_rx(void)
/* Process up to 32 packets at one time */
for (i = 0; i 32; i++) {
ret = eth_get_ops(current)-recv(current, packet);
- if (ret 0)
+ if (ret 0) {
To match the old net stack behaviour I wonder if we should process the
packet when it is length 0, and require recv() to return -EAGAIN when
there is no packet? At least with designware, it processes a 0-length
packet for some reason, and we need to call free_pkt() in that case.
I pretty much assumed that since the driver is not expecting the network
stack to do anything with the buffer in the retval == 0 case, the driver
would handle its buffer management before returning from recv().
I'm not sure which is more clear to the driver writer... to expect the
free_pkt() call when returning 0 or to not expect it. I guess my initial
instinct is that you would not expect it.
net_process_received_packet(packet, ret);
- else
+ if (eth_get_ops(current)-free_pkt)
+ eth_get_ops(current)-free_pkt(current,
packet,
+ ret);
+ } else {
break;
+ }
}
if (ret == -EAGAIN)
ret = 0;
--
1.7.11.5
Tested on pcduino3:
Tested-by: Simon Glass s...@chromium.org
Acked-by: Simon Glass s...@chromium.org
Regards,
Simon
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[U-Boot] [PATCH 2/3] armv8:Add SMC calls infrastructure
This commit adds functions issuing calls to firmware. This allows
to use services such as PSCI provided by firmware, e.g. ATF
Signed-off-by: Sergey Temerkhanov s.temerkha...@gmail.com
Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com
---
arch/arm/cpu/armv8/Makefile | 1 +
arch/arm/cpu/armv8/fwcall.c | 88 +++
arch/arm/include/asm/system.h | 8
3 files changed, 97 insertions(+)
create mode 100644 arch/arm/cpu/armv8/fwcall.c
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index dee5e25..208d012 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -14,6 +14,7 @@ obj-y += exceptions.o
obj-y += cache.o
obj-y += tlb.o
obj-y += transition.o
+obj-y += fwcall.o
obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
obj-$(CONFIG_TARGET_XILINX_ZYNQMP) += zynqmp/
diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c
new file mode 100644
index 000..094a0c7
--- /dev/null
+++ b/arch/arm/cpu/armv8/fwcall.c
@@ -0,0 +1,88 @@
+/** @file
+#
+# Copyright (c) 2014, Cavium Inc. All rights reserved.BR
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD
+# License which accompanies this distribution. The full text of the license
+# may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN AS IS BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED.
+#
+#**/
+
+#include asm-offsets.h
+#include config.h
+#include version.h
+#include asm/macro.h
+#include asm/system.h
+
+#define __asmeq(x, y) .ifnc x , y ; .err ; .endif\n\t
+
+/*
+ * void hvc_call(arg0, arg1...arg7)
+ *
+ * issue the hypervisor call
+ *
+ * x0~x7: argument list
+ */
+void hvc_call(struct pt_regs *args)
+{
+ asm volatile(
+ ldr x0, %0\n
+ ldr x1, %1\n
+ ldr x2, %2\n
+ ldr x3, %3\n
+ ldr x4, %4\n
+ ldr x5, %5\n
+ ldr x6, %6\n
+ ldr x7, %7\n
+ hvc#0\n
+ str x0, %0\n
+ str x1, %1\n
+ str x2, %2\n
+ str x3, %3\n
+ : +m (args-regs[0]), +m (args-regs[1]),
+ +m (args-regs[2]), +m (args-regs[3])
+ : m (args-regs[0]), m (args-regs[1]),
+ m (args-regs[2]), m (args-regs[3]),
+ m (args-regs[4]), m (args-regs[5]),
+ m (args-regs[6]), m (args-regs[7])
+ : x0, x1, x2, x3, x4, x5, x6, x7);
+}
+
+/*
+ * void smc_call(arg0, arg1...arg7)
+ *
+ * issue the secure monitor call
+ *
+ * x0~x7: argument list
+ */
+
+void smc_call(struct pt_regs *args)
+{
+ asm volatile(
+ ldr x0, %0\n
+ ldr x1, %1\n
+ ldr x2, %2\n
+ ldr x3, %3\n
+ ldr x4, %4\n
+ ldr x5, %5\n
+ ldr x6, %6\n
+ ldr x7, %7\n
+ smc#0\n
+ str x0, %0\n
+ str x1, %1\n
+ str x2, %2\n
+ str x3, %3\n
+ : +m (args-regs[0]), +m (args-regs[1]),
+ +m (args-regs[2]), +m (args-regs[3])
+ : m (args-regs[0]), m (args-regs[1]),
+ m (args-regs[2]), m (args-regs[3]),
+ m (args-regs[4]), m (args-regs[5]),
+ m (args-regs[6]), m (args-regs[7])
+ : x0, x1, x2, x3, x4, x5, x6, x7);
+}
+
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index b778a6c..aac15cc 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -1,6 +1,9 @@
#ifndef __ASM_ARM_SYSTEM_H
#define __ASM_ARM_SYSTEM_H
+#include common.h
+#include linux/compiler.h
+
#ifdef CONFIG_ARM64
/*
@@ -85,6 +88,11 @@ void smp_kick_all_cpus(void);
void flush_l3_cache(void);
+#define __asmeq(x, y) .ifnc x , y ; .err ; .endif\n\t
+
+void hvc_call(struct pt_regs *args);
+void smc_call(struct pt_regs *args);
+
#endif /* __ASSEMBLY__ */
#else /* CONFIG_ARM64 */
--
2.3.3
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[U-Boot] [PATCH 1/3] armv8:New MMU setup code allowing to set up 2-level page tables
This patch adds code which sets up 2-level page tables on ARM64 thus
extending available VA space. CPUs implementing 64k translation
granule are able to use direct PA-VA mapping of the whole 48 bit
address space.
It also adds the ability to reset the SCTRL register at the very beginning
of execution to avoid interference from stale mappings set up by early
firmware/loaders/etc.
Signed-off-by: Sergey Temerkhanov s.temerkha...@gmail.com
Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com
---
arch/arm/cpu/armv8/cache_v8.c | 95 ++
arch/arm/cpu/armv8/start.S | 36 +++
arch/arm/include/asm/armv8/mmu.h | 79 ---
arch/arm/include/asm/global_data.h | 1 +
arch/arm/include/asm/system.h | 6 +++
arch/arm/lib/board.c | 6 ++-
6 files changed, 215 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index c5ec529..1264caa 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -12,6 +12,8 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DCACHE_OFF
+
+#ifndef CONFIG_SYS_FULL_VA
void set_pgtable_section(u64 *page_table, u64 index, u64 section,
u64 memory_type)
{
@@ -65,6 +67,99 @@ static void mmu_setup(void)
set_sctlr(get_sctlr() | CR_M);
}
+#else
+
+static void set_ptl1_entry(u64 index, u64 ptl2_entry)
+{
+ u64 *pgd = (u64 *)gd-arch.tlb_addr;
+ u64 value;
+
+ value = ptl2_entry | PTL1_TYPE_TABLE;
+ pgd[index] = value;
+}
+
+static void set_ptl2_block(u64 ptl1, u64 bfn, u64 address, u64 memory_type)
+{
+ u64 *pmd = (u64 *)ptl1;
+ u64 value;
+
+ value = address | PTL2_TYPE_BLOCK | PTL2_BLOCK_AF;
+ value |= PMD_ATTRINDX(memory_type);
+ pmd[bfn] = value;
+}
+
+static struct mm_region mem_map[] = CONFIG_SYS_MEM_MAP;
+
+#define PTL1_ENTRIES CONFIG_SYS_PTL1_ENTRIES
+#define PTL2_ENTRIES CONFIG_SYS_PTL2_ENTRIES
+
+static void setup_pgtables(void)
+{
+ int l1_e, l2_e;
+ unsigned long pmd = 0;
+ unsigned long address;
+
+ /* Setup the PMD pointers */
+ for (l1_e = 0; l1_e CONFIG_SYS_MEM_MAP_SIZE; l1_e++) {
+ gd-arch.pmd_addr[l1_e] = gd-arch.tlb_addr +
+ PTL1_ENTRIES * sizeof(u64);
+ gd-arch.pmd_addr[l1_e] += PTL2_ENTRIES * sizeof(u64) * l1_e;
+ gd-arch.pmd_addr[l1_e] += 0xUL;
+ gd-arch.pmd_addr[l1_e] = ~0xUL;
+ }
+
+/* Setup the page tables */
+ for (l1_e = 0; l1_e PTL1_ENTRIES; l1_e++) {
+ if (mem_map[pmd].base ==
+ (uintptr_t)l1_e PTL1_BITS) {
+ set_ptl1_entry(l1_e, gd-arch.pmd_addr[pmd]);
+
+ for (l2_e = 0; l2_e PTL2_ENTRIES; l2_e++) {
+ address = mem_map[pmd].base
+ + (uintptr_t)l2_e * BLOCK_SIZE;
+ set_ptl2_block(gd-arch.pmd_addr[pmd], l2_e,
+ address, mem_map[pmd].attrs);
+ }
+
+ pmd++;
+ } else {
+ set_ptl1_entry(l1_e, 0);
+ }
+}
+}
+
+/* to activate the MMU we need to set up page tables */
+static void mmu_setup(void)
+{
+ int el;
+ unsigned long coreid = read_mpidr() CONFIG_COREID_MASK;
+
+ /* Set up page tables only on BSP */
+ if (coreid == BSP_COREID)
+ setup_pgtables();
+
+ /* load TTBR0 */
+ el = current_el();
+
+ if (el == 1) {
+ set_ttbr_tcr_mair(el, gd-arch.tlb_addr,
+ TCR_FLAGS | TCR_EL1_IPS_BITS,
+ MEMORY_ATTRIBUTES);
+ } else if (el == 2) {
+ set_ttbr_tcr_mair(el, gd-arch.tlb_addr,
+ TCR_FLAGS | TCR_EL2_IPS_BITS,
+ MEMORY_ATTRIBUTES);
+ } else {
+ set_ttbr_tcr_mair(el, gd-arch.tlb_addr,
+ TCR_FLAGS | TCR_EL3_IPS_BITS,
+ MEMORY_ATTRIBUTES);
+ }
+ /* enable the mmu */
+ set_sctlr(get_sctlr() | CR_M);
+}
+
+#endif
+
/*
* Performs a invalidation of the entire data cache at all levels
*/
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index e5f2766..ea686de 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -19,6 +19,9 @@
.globl _start
_start:
+#ifdef CONFIG_SYS_RESET_SCTRL
+ bl reset_sctrl
+#endif
b reset
.align 3
@@ -97,6 +100,39 @@ master_cpu:
bl _main
+#ifdef CONFIG_SYS_RESET_SCTRL
+reset_sctrl:
+ switch_el x1, 3f, 2f, 1f
+3:
+ mrs x0, sctlr_el3
+ b 0f
+2:
+ mrs x0, sctlr_el2
+ b 0f
+1:
+ mrs x0, sctlr_el1
+
[U-Boot] [PATCH 0/3] Extend ARMv8 support
This patchset is meant is created in preparation to submission of patch series which will add support of the Cavium ThunderX SoC. This series adds support of setting up 2-level page tables as well as functions which allow issuing firmware calls ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] armv8:Add psci.h from the Linux kernel
This commit adds the psci.h header file from Linux kernel which contains definitions related to the PSCI interface provided by firmware Signed-off-by: Sergey Temerkhanov s.temerkha...@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com --- include/linux/psci.h | 90 1 file changed, 90 insertions(+) create mode 100644 include/linux/psci.h diff --git a/include/linux/psci.h b/include/linux/psci.h new file mode 100644 index 000..310d83e --- /dev/null +++ b/include/linux/psci.h @@ -0,0 +1,90 @@ +/* + * ARM Power State and Coordination Interface (PSCI) header + * + * This header holds common PSCI defines and macros shared + * by: ARM kernel, ARM64 kernel, KVM ARM/ARM64 and user space. + * + * Copyright (C) 2014 Linaro Ltd. + * Author: Anup Patel anup.pa...@linaro.org + */ + +#ifndef _UAPI_LINUX_PSCI_H +#define _UAPI_LINUX_PSCI_H + +/* + * PSCI v0.1 interface + * + * The PSCI v0.1 function numbers are implementation defined. + * + * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED, + * INVALID_PARAMS, and DENIED defined below are applicable + * to PSCI v0.1. + */ + +/* PSCI v0.2 interface */ +#define PSCI_0_2_FN_BASE 0x8400 +#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n)) +#define PSCI_0_2_64BIT 0x4000 +#define PSCI_0_2_FN64_BASE \ + (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT) +#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n)) + +#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0) +#define PSCI_0_2_FN_CPU_SUSPENDPSCI_0_2_FN(1) +#define PSCI_0_2_FN_CPU_OFFPSCI_0_2_FN(2) +#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3) +#define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4) +#define PSCI_0_2_FN_MIGRATEPSCI_0_2_FN(5) +#define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6) +#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPUPSCI_0_2_FN(7) +#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8) +#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9) + +#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) +#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) +#define PSCI_0_2_FN64_AFFINITY_INFOPSCI_0_2_FN64(4) +#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5) +#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7) + +/* PSCI v0.2 power state encoding for CPU_SUSPEND function */ +#define PSCI_0_2_POWER_STATE_ID_MASK 0x +#define PSCI_0_2_POWER_STATE_ID_SHIFT 0 +#define PSCI_0_2_POWER_STATE_TYPE_SHIFT16 +#define PSCI_0_2_POWER_STATE_TYPE_MASK \ + (0x1 PSCI_0_2_POWER_STATE_TYPE_SHIFT) +#define PSCI_0_2_POWER_STATE_AFFL_SHIFT24 +#define PSCI_0_2_POWER_STATE_AFFL_MASK \ + (0x3 PSCI_0_2_POWER_STATE_AFFL_SHIFT) + +/* PSCI v0.2 affinity level state returned by AFFINITY_INFO */ +#define PSCI_0_2_AFFINITY_LEVEL_ON 0 +#define PSCI_0_2_AFFINITY_LEVEL_OFF1 +#define PSCI_0_2_AFFINITY_LEVEL_ON_PENDING 2 + +/* PSCI v0.2 multicore support in Trusted OS returned by MIGRATE_INFO_TYPE */ +#define PSCI_0_2_TOS_UP_MIGRATE0 +#define PSCI_0_2_TOS_UP_NO_MIGRATE 1 +#define PSCI_0_2_TOS_MP2 + +/* PSCI version decoding (independent of PSCI version) */ +#define PSCI_VERSION_MAJOR_SHIFT 16 +#define PSCI_VERSION_MINOR_MASK\ + ((1U PSCI_VERSION_MAJOR_SHIFT) - 1) +#define PSCI_VERSION_MAJOR_MASK~PSCI_VERSION_MINOR_MASK +#define PSCI_VERSION_MAJOR(ver)\ + (((ver) PSCI_VERSION_MAJOR_MASK) PSCI_VERSION_MAJOR_SHIFT) +#define PSCI_VERSION_MINOR(ver)\ + ((ver) PSCI_VERSION_MINOR_MASK) + +/* PSCI return values (inclusive of all PSCI versions) */ +#define PSCI_RET_SUCCESS 0 +#define PSCI_RET_NOT_SUPPORTED -1 +#define PSCI_RET_INVALID_PARAMS-2 +#define PSCI_RET_DENIED-3 +#define PSCI_RET_ALREADY_ON-4 +#define PSCI_RET_ON_PENDING-5 +#define PSCI_RET_INTERNAL_FAILURE -6 +#define PSCI_RET_NOT_PRESENT -7 +#define PSCI_RET_DISABLED -8 + +#endif /* _UAPI_LINUX_PSCI_H */ -- 2.3.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] spi: omap3: Fix timeout handling
Hi David,
snipped for brevity
for (i = 0; i len; i++) {
/* wait till TX register is empty (TXS == 1) */
+ start = get_timer(0);
while (!(readl(ds-regs-channel[ds-slave.cs].chstat)
OMAP3_MCSPI_CHSTAT_TXS)) {
- if (--timeout = 0) {
+ if (get_timer(start) SPI_WAIT_TIMEOUT) {
printf(SPI TXS timed out, status=0x%08x\n,
readl(ds-regs-channel[ds-
slave.cs].chstat));
return -1;
I have a couple of questions...
Firstly, when in SPL is there access to the get_timer() function?
Secondly, when using Falcon mode to load Linux directly from SPI (Falcon
mode) then we want to maximise the throughput and save every CPU cycle we
possibly can. Adding yet another function call into the for loop and hence
calling it a couple of million times seems, on the face of it, like it is
going to slow things down.
Regards,
Andy.
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Re: [U-Boot] [PATCH 08/12] ARM: socfpga: use select instead of default value in defconfig
Hi Pavel, 2015-04-01 5:40 GMT+09:00 Pavel Machek pa...@denx.de: Hi! On Tue 2015-03-31 12:47:59, Masahiro Yamada wrote: Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com --- arch/arm/Kconfig | 6 ++ configs/socfpga_arria5_defconfig | 3 --- configs/socfpga_cyclone5_defconfig | 3 --- configs/socfpga_socrates_defconfig | 3 --- 4 files changed, 6 insertions(+), 9 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b25a4a9..6ae48c6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -618,11 +618,17 @@ config TARGET_SOCFPGA_ARRIA5 bool Support socfpga_arria5 select CPU_V7 select SUPPORT_SPL + select DM + select DM_SPI_FLASH + select DM_SPI Are you sure? Yes, I'm sure. config DM_SPI_FLASH bool Enable Driver Model for SPI flash depends on DM SPI help DM_SPI_FLASH depends on SPI, you can't just select it... This dependency is wrong. Before this patch, it must be fixed. Please see 01/12 of this series: http://patchwork.ozlabs.org/patch/456458/ -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Can't boot DaVinci EVM with Green Hills' Integrity OS
I'v tried this but it does not change anything. Is there a way to have the u-boot run in a step-by-step mode? In order to try and eliminate the problematic initialization? Thanks, On Tue, Mar 31, 2015 at 10:03 AM, Jeroen Hofstee jer...@myspectrum.nl wrote: Hello Idan, On 31-03-15 06:02, Idan Noti wrote: Why do you think caches have something to do with the problem? By booting the image with the bootelf command you jump to it with some caches still enabled / not flushed (which is likely not what your debug interface does and your kernel might not really like that). A FreeBSD kernel doesn't / didn't at least and wouldn't boot. I never checked, but I guess Linux doesn't like it either, but since it is typically booted by a bootm / bootz command it goes through e.g. arch/arm/lib/bootm.c, which calls cleanup_before_linux in arch/arm/cpu/arm926ejs/cpu.c, all caches are disables and flushes before jumping into it. Of course I don't know if this is related to your problem, but it cannot do any harm to keep caches off until you have the board properly booting. Also, how do I config the compilation to disable caches? The only configuration I'm aware about it modifying the header file: $(uboot_folder)/include/configs/davinci_dvevm.h Yup, see README and doc/README.arm-caches. At least below knobs are documented. You can simply define these in mentioned file. CONFIG_SYS_ICACHE_OFF - Do not enable instruction cache in U-Boot CONFIG_SYS_DCACHE_OFF - Do not enable data cache in U-Boot CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot Regards, Jeroen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESEND PATCH 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's
On Wednesday, April 01, 2015 at 11:54:22 AM, Sanchayan Maity wrote:
The commit message is missing, please fix in v2.
Signed-off-by: Sanchayan Maity maitysancha...@gmail.com
[...]
+#define USB_NC_REG_OFFSET0x0800
+#define USBCx_CTRL_OFFSET0x
+#define USBCx_PHY_CTRL_OFFSET0x0018
Please define the register offsets using the regular struct {} method,
see for example struct mxs_usbphy_regs and it's usage in ehci-mxs.c .
+#define USBPHY_CTRL 0x0030
+#define USBPHY_CTRL_SET 0x0034
+#define USBPHY_CTRL_CLR 0x0038
+#define USBPHY_CTRL_TOG 0x003c
+
+#define USBPHY_PWD 0x
+#define USBPHY_TX0x0010
+#define USBPHY_RX0x0020
+#define USBPHY_DEBUG 0x0050
+#define USBPHY_CTRL_SFTRST 0x8000
+#define USBPHY_CTRL_CLKGATE 0x4000
+#define USBPHY_CTRL_ENUTMILEVEL3 0x8000
+#define USBPHY_CTRL_ENUTMILEVEL2 0x4000
+#define USBPHY_CTRL_OTG_ID 0x0800
+
+#define ANADIG_PLL_CTRL_BYPASS 0x0001
+#define ANADIG_PLL_CTRL_ENABLE 0x2000
+#define ANADIG_PLL_CTRL_POWER0x1000
+#define ANADIG_PLL_CTRL_EN_USB_CLKS 0x0040
+
+#define UCTRL_OVER_CUR_POL (1 8) /* OTG Polarity of Overcurrent */
+#define UCTRL_OVER_CUR_DIS (1 7) /* Disable OTG Overcurrent Detection
*/ +
+/* USBCMD */
+#define UCMD_RUN_STOP(1 0) /* controller run/stop */
+#define UCMD_RESET (1 1) /* controller reset */
This looks very much like the USB PHY used on MX28 , can you double-check this
please ?
Best regards,
Marek Vasut
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[U-Boot] [PATCH] ARM: tegra: CONFIG_{SYS_, }LOAD{_, }ADDR rationalization
From: Stephen Warren swar...@nvidia.com As best I can tell, CONFIG_SYS_LOAD_ADDR and CONFIG_LOADADDR/$loadaddr serve essentially the same purpose. Roughly, if a command takes a load address, then CONFIG_SYS_LOAD_ADDR or $loadaddr (or both) are the default if the command-line does not specify the address. Different U-Boot commands are inconsistent re: which of the two default values they use. As such, set the two to the same value, and move the logic that does this into tegra-common-post.h so it's not duplicated. A number of other non- Tegra boards do this too. The values chosen for these macros are no longer consistent with anything in MEM_LAYOUT_ENV_SETTINGS. Regain consistency by setting $kernel_addr_r to CONFIG_LOADADDR. Older scripts tend to use $loadaddr for the default kernel load address, whereas newer scripts and features tend to use $kernel_addr_r, along with other variables for other purposes such as DTBs and initrds. Hence, it's logical they should share the same value. I had originally thought to make the $kernel_addr_r and CONFIG_LOADADDR have different values. This would guarantee no interference if a script used the two variables for different purposes. However, that scenario is unlikely given the semantic meaning associated with the two variables. The lowest available value is 0x9020; see comments for MEM_LAYOUT_ENV_SETTINGS in tegra30-common-post.h for details. However, that value would be problematic for a script that loaded a raw zImage to $loadaddr, since it's more than 128MB beyond the start of SDRAM, which would interfere with the kernel's CONFIG_AUTO_ZRELADDR. So, let's not do that. The only potential fallout I could foresee from this patch is if someone has a script that loads the kernel to $loadaddr, but some other file (DTB, initrd) to a hard-coded address that the new value of $loadaddr interferes with. This seems unlikely. A user should not do that; they should either hard-code all load addresses, or use U-Boot-supplied variables for all load addresses. Equally, any fallout due to this change is trivial to fix; simply modify the load addresses in that script. Cc: Paul Walmsley pwalms...@nvidia.com Signed-off-by: Stephen Warren swar...@nvidia.com --- include/configs/tegra-common-post.h | 2 ++ include/configs/tegra114-common.h | 7 ++- include/configs/tegra124-common.h | 7 ++- include/configs/tegra20-common.h| 7 ++- include/configs/tegra30-common.h| 7 ++- 5 files changed, 10 insertions(+), 20 deletions(-) diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index c3ad8beb903d..31096d068bb1 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -50,6 +50,8 @@ #define BOARD_EXTRA_ENV_SETTINGS #endif +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_EXTRA_ENV_SETTINGS \ TEGRA_DEVICE_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 9eba5d517db7..252e607d73f4 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -26,13 +26,9 @@ */ #define V_NS16550_CLK 40800 /* 408MHz (pllp_out0) */ -/* Environment information, boards can override if required */ -#define CONFIG_LOADADDR0x80408000 /* def. location for kernel */ - /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ #define CONFIG_STACKBASE 0x8280 /* 40MB */ /*--- @@ -64,10 +60,11 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ +#define CONFIG_LOADADDR 0x8100 #define MEM_LAYOUT_ENV_SETTINGS \ scriptaddr=0x9000\0 \ pxefile_addr_r=0x9010\0 \ - kernel_addr_r=0x8100\0 \ + kernel_addr_r= __stringify(CONFIG_LOADADDR) \0 \ fdt_addr_r=0x8200\0 \ ramdisk_addr_r=0x8210\0 diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index f2b3774da8ff..1aee5c89f4c4 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -18,13 +18,9 @@ */ #define V_NS16550_CLK 40800 /* 408MHz (pllp_out0) */ -/* Environment information, boards can override if required */ -#define CONFIG_LOADADDR0x80408000 /* def. location for kernel */ - /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ #define CONFIG_STACKBASE 0x8280 /* 40MB */ /*--- @@ -56,10 +52,11 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */
Re: [U-Boot] [PATCH 2/3] armv8:Add SMC calls infrastructure
On Wed, Apr 01, 2015 at 06:15:05PM +0300, Sergey Temerkhanov wrote: This commit adds functions issuing calls to firmware. This allows to use services such as PSCI provided by firmware, e.g. ATF [snip] +++ b/arch/arm/cpu/armv8/fwcall.c @@ -0,0 +1,88 @@ +/** @file +# +# Copyright (c) 2014, Cavium Inc. All rights reserved.BR +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD +# License which accompanies this distribution. The full text of the license +# may be found at +# http://opensource.org/licenses/bsd-license.php Please use SPDX tags instead, thanks. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [ANN] U-Boot v2015.04-rc5 released
Dear Tom, In message 20150401005616.GE9524@bill-the-cat you wrote: I've pushed v2015.04-rc5 out to the repository and tarballs should exist soon. Tarballs are out. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de When some people discover the truth, they just can't understand why everybody isn't eager to hear it. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] kbuild: move ARCH, CPU, etc. to top Makefile to fix random build error
On 03/31/2015 06:02 AM, Masahiro Yamada wrote:
Since the Kconfig conversion, some developers have reported that
Kbuild sometimes fails completely at random. According to the error
reports, it seems to occur for any target board, but only on very
fast computers.
The log message for the fail case is like this:
make[1]: *** No rule to make target `../arch//cpu/u-boot.lds',
needed by `u-boot.lds'. Stop.
It looks like the top config.mk has not been included for *some*
reason, and $(ARCH) has been left blank.
I suspect autoconf_is_current is not working in some situation.
That's certainly true. The following code doesn't end up including
config.mk in the bad case:
# We want to include arch/$(ARCH)/config.mk only when include/config/auto.conf
# is up-to-date. When we switch to a different board configuration, old CONFIG
# macros are still remaining in include/config/auto.conf. Without the following
# gimmick, wrong config.mk would be included leading nasty warnings/errors.
autoconf_is_current := $(if $(wildcard $(KCONFIG_CONFIG)),$(shell find . \
-path ./include/config/auto.conf -newer $(KCONFIG_CONFIG)))
ifneq ($(autoconf_is_current),)
include $(srctree)/config.mk
include $(srctree)/arch/$(ARCH)/Makefile
endif
That's because:
[swarren@swarren-lx1 tegra-uboot-flasher]$ ls -l --full-time
u-boot-*/{.config,include/config/auto.conf}|cat
-rw-rw-r-- 1 swarren swarren 9219 2015-04-01 15:50:08.0 -0600
u-boot-bad/.config
-rw-rw-r-- 1 swarren swarren 928 2015-04-01 15:50:08.0 -0600
u-boot-bad/include/config/auto.conf
-rw-rw-r-- 1 swarren swarren 9219 2015-04-01 15:51:25.0 -0600
u-boot-ok/.config
-rw-rw-r-- 1 swarren swarren 928 2015-04-01 15:51:26.0 -0600
u-boot-ok/include/config/auto.conf
In the bad case, the timestamps are equal (and hence the -newer check
fails), whereas in the good case they're different. Recall ext*
filesystems have a 1s timestamp resolution.
Note that this is state left over from make xxx_defconfig; If I just
manually run make all in a tree in this state, it'll stay in this
state forever, and vice-versa for a working tree.
I expect that simulating this condition with some judicious manually
executed touch commands would be extremely easy.
Possible solutions are:
Is there a -newer-or-equal that could be used in the find command rather
than -newer?
When running make xxx_defconfig, can the code there compare the
timestamp of those two files, and keep looping and touching the
auto.conf file until the timestamps differ.
Something else entirely? I couldn't see anything relating to
autoconf_is_current in the kernel's makefiles.
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