[U-Boot] [PATCH RFT] gpio: vybrid: Fix up setting output value in vybrid_gpio_direction_output
Pass correct gpio argument to gpio_set_value().
The calcualation of gpio = gpio + (gpios-chip * VYBRID_GPIO_COUNT);
is required for calling imx_iomux_gpio_* functions so move them close to
improve readability.
Signed-off-by: Axel Lin axel@ingics.com
---
Hi Bhuvanchandra,
I think current code does not pass correct gpio argument to gpio_set_value()
in vybrid_gpio_direction_output(). It only works if gpios-chip is 0.
I don't have the h/w to test, can you double check this?
Thanks,
Axel
drivers/gpio/vybrid_gpio.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/vybrid_gpio.c b/drivers/gpio/vybrid_gpio.c
index 6eaf0a9..33bbf54 100644
--- a/drivers/gpio/vybrid_gpio.c
+++ b/drivers/gpio/vybrid_gpio.c
@@ -36,8 +36,9 @@ static int vybrid_gpio_direction_output(struct udevice *dev,
unsigned gpio,
{
const struct vybrid_gpios *gpios = dev_get_priv(dev);
- gpio = gpio + (gpios-chip * VYBRID_GPIO_COUNT);
gpio_set_value(gpio, value);
+
+ gpio = gpio + (gpios-chip * VYBRID_GPIO_COUNT);
imx_iomux_gpio_set_direction(gpio, VF610_GPIO_DIRECTION_OUT);
return 0;
@@ -54,6 +55,7 @@ static int vybrid_gpio_set_value(struct udevice *dev,
unsigned gpio,
int value)
{
const struct vybrid_gpios *gpios = dev_get_priv(dev);
+
if (value)
writel((1 gpio), gpios-reg-gpio_psor);
else
@@ -68,7 +70,6 @@ static int vybrid_gpio_get_function(struct udevice *dev,
unsigned gpio)
u32 g_state = 0;
gpio = gpio + (gpios-chip * VYBRID_GPIO_COUNT);
-
imx_iomux_gpio_get_function(gpio, g_state);
if (((g_state (0x07 PAD_MUX_MODE_SHIFT)) PAD_MUX_MODE_SHIFT)
0)
--
2.1.0
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[U-Boot] Disabling Autonegotiation
Hi , I am trying to disable auto negotiation in U-boot. I modified drivers/net/phy/phy.c setting dev-autoneg = AUTONEG_DISABLE;. Autonegotion is disabled but u-boot however waits for autonegotiation to complete in the function genphy_update_link( ) Modifying the values of BMCR_ANENABLE BMSR_ANEGCAPABLE in include/linux/mii.h resolves the issue. Since am new to u-boot programming wanted to know if modifying these macros is advisable or if there is a better approach to this issue. TIA ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] patch - arm - define SYS_CACHELINE_SIZE for mx5
Hi Fabio, Chris, On 09/06/2015 00:00, Fabio Estevam wrote: Adding the i.MX maintaner, Stefano Babic. Thanks - it was missed in my last Pr. Applied to u-boot-imx, thanks ! Best regards, Stefano Babic Regards, Fabio Estevam On Mon, Jun 8, 2015 at 6:55 PM, Chris Kuethe chris.kue...@gmail.com wrote: Bump... can this be merged? On Tue, Jun 2, 2015 at 4:42 PM, Fabio Estevam feste...@gmail.com wrote: On Tue, Jun 2, 2015 at 8:31 PM, Chris Kuethe chris.kue...@gmail.com wrote: mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for adding gadget support to usbarmory, but it's a property common the the entire SoC family - may as well make it available to all MX5 boards Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too Signed-off-by: Chris Kuethe chris.kue...@gmail.com Cc: Tom Rini tr...@konsulko.com Cc: Matthew Starr mst...@hedonline.com Cc: Andrej Rosano and...@inversepath.com Cc: Stefano Babic sba...@denx.de Cc: Chris Kuethe chris.kue...@gmail.com Cc: Fabio Estevam feste...@gmail.com Cc: Marek Vasut ma...@denx.de diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index f059d0f..5f0e1e6 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -9,6 +9,8 @@ #define ARCH_MXC +#define CONFIG_SYS_CACHELINE_SIZE 64 + This is correct for Cortex A8: Reviewed-by: Fabio Estevam fabio.este...@freescale.com -- GDB has a 'break' feature; why doesn't it have 'fix' too? -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] tbs2910: add thermal support
On 29/05/2015 20:32, Soeren Moch wrote: Signed-off-by: Soeren Moch sm...@web.de --- Cc: Stefano Babic sba...@denx.de --- configs/tbs2910_defconfig | 2 ++ include/configs/tbs2910.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index cace345..51319d1 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -1,3 +1,5 @@ CONFIG_ARM=y CONFIG_TARGET_TBS2910=y CONFIG_SYS_EXTRA_OPTIONS=IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 13a6e06..2d0de45 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -21,6 +21,8 @@ #define CONFIG_SYS_PROMPTMatrix U-Boot #define CONFIG_SYS_HZ1000 +#define CONFIG_IMX6_THERMAL + /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASEMMDC0_ARB_BASE_ADDR Applied to u-boot-imx, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] tbs2910: add PRE_CONSOLE_BUFFER support
On 29/05/2015 20:32, Soeren Moch wrote: Add PRE_CONSOLE_BUFFER support to display early boot messages over HDMI. Signed-off-by: Soeren Moch sm...@web.de --- Cc: Stefano Babic sba...@denx.de --- include/configs/tbs2910.h | 4 1 file changed, 4 insertions(+) diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 2d0de45..f915b18 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -51,6 +51,10 @@ #define CONFIG_CONSOLE_MUX #define CONFIG_CONS_INDEX1 +#define CONFIG_PRE_CONSOLE_BUFFER +#define CONFIG_PRE_CON_BUF_SZ4096 +#define CONFIG_PRE_CON_BUF_ADDR 0x7C00 + /* *** Command definition *** */ #define CONFIG_CMD_BMODE #define CONFIG_CMD_SETEXPR Applied to u-boot-imx, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/9] x86: Move MP initialization codes into a common place
Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is
common to all x86 processors, except detect_num_cpus() which varies
from cpu to cpu. Move these to arch/x86/cpu/cpu.c and declare a weak
detect_num_cpus() which just returns 2 which is minimally required.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/baytrail/cpu.c | 44 +-
arch/x86/cpu/cpu.c | 47 +
2 files changed, 48 insertions(+), 43 deletions(-)
diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c
index 05156a5..7805056 100644
--- a/arch/x86/cpu/baytrail/cpu.c
+++ b/arch/x86/cpu/baytrail/cpu.c
@@ -12,23 +12,11 @@
#include asm/cpu.h
#include asm/cpu_x86.h
#include asm/lapic.h
-#include asm/mp.h
#include asm/msr.h
#include asm/turbo.h
#ifdef CONFIG_SMP
-static int enable_smis(struct udevice *cpu, void *unused)
-{
- return 0;
-}
-
-static struct mp_flight_record mp_steps[] = {
- MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
- /* Wait for APs to finish initialization before proceeding. */
- MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
-};
-
-static int detect_num_cpus(void)
+int detect_num_cpus(void)
{
int ecx = 0;
@@ -52,38 +40,8 @@ static int detect_num_cpus(void)
ecx++;
}
}
-
-static int baytrail_init_cpus(void)
-{
- struct mp_params mp_params;
-
- lapic_setup();
-
- mp_params.num_cpus = detect_num_cpus();
- mp_params.parallel_microcode_load = 0,
- mp_params.flight_plan = mp_steps[0];
- mp_params.num_records = ARRAY_SIZE(mp_steps);
- mp_params.microcode_pointer = 0;
-
- if (mp_init(mp_params)) {
- printf(Warning: MP init failure\n);
- return -EIO;
- }
-
- return 0;
-}
#endif
-int x86_init_cpus(void)
-{
-#ifdef CONFIG_SMP
- debug(Init additional CPUs\n);
- baytrail_init_cpus();
-#endif
-
- return 0;
-}
-
static void set_max_freq(void)
{
msr_t perf_ctl;
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index ffb6e43..ddc7dc3 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -21,10 +21,13 @@
#include common.h
#include command.h
+#include dm.h
#include errno.h
#include malloc.h
#include asm/control_regs.h
#include asm/cpu.h
+#include asm/lapic.h
+#include asm/mp.h
#include asm/post.h
#include asm/processor.h
#include asm/processor-flags.h
@@ -601,8 +604,52 @@ int last_stage_init(void)
}
#endif
+#ifdef CONFIG_SMP
+static int enable_smis(struct udevice *cpu, void *unused)
+{
+ return 0;
+}
+
+static struct mp_flight_record mp_steps[] = {
+ MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
+ /* Wait for APs to finish initialization before proceeding */
+ MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
+};
+
+__weak int detect_num_cpus(void)
+{
+ /* We need at least 2 cores to perform mp_init() */
+ return 2;
+}
+
+static int x86_mp_init(void)
+{
+ struct mp_params mp_params;
+
+ lapic_setup();
+
+ mp_params.num_cpus = detect_num_cpus();
+ mp_params.parallel_microcode_load = 0,
+ mp_params.flight_plan = mp_steps[0];
+ mp_params.num_records = ARRAY_SIZE(mp_steps);
+ mp_params.microcode_pointer = 0;
+
+ if (mp_init(mp_params)) {
+ printf(Warning: MP init failure\n);
+ return -EIO;
+ }
+
+ return 0;
+}
+#endif
+
__weak int x86_init_cpus(void)
{
+#ifdef CONFIG_SMP
+ debug(Init additional CPUs\n);
+ x86_mp_init();
+#endif
+
return 0;
}
--
1.8.2.1
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[U-Boot] [PATCH 3/9] x86: dm: Clean up cpu drivers
This commit does the following to clean up x86 cpu dm drivers:
- Move cpu_x86 driver codes from arch/x86/cpu/cpu.c to a dedicated
file arch/x86/cpu/cpu_x86.c
- Rename x86_cpu_get_desc() to cpu_x86_get_desc() to keep consistent
naming with other dm drivers
- Add a new cpu_x86_bind() in the cpu_x86 driver which does exactly
the same as the one in the intel baytrail cpu driver
- Update intel baytrail cpu driver to use cpu_x86_get_desc() and
cpu_x86_bind()
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/Makefile | 2 +-
arch/x86/cpu/baytrail/cpu.c| 15 +++--
arch/x86/cpu/cpu.c | 28
arch/x86/cpu/cpu_x86.c | 48 ++
arch/x86/include/asm/cpu.h | 14
arch/x86/include/asm/cpu_x86.h | 34 ++
6 files changed, 86 insertions(+), 55 deletions(-)
create mode 100644 arch/x86/cpu/cpu_x86.c
create mode 100644 arch/x86/include/asm/cpu_x86.h
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 7ff05e6..48197fb 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -10,7 +10,7 @@
extra-y= start.o
obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
-obj-y += interrupts.o cpu.o call64.o
+obj-y += interrupts.o cpu.o cpu_x86.o call64.o
obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
obj-$(CONFIG_SYS_COREBOOT) += coreboot/
diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c
index 1d48206..05156a5 100644
--- a/arch/x86/cpu/baytrail/cpu.c
+++ b/arch/x86/cpu/baytrail/cpu.c
@@ -10,6 +10,7 @@
#include cpu.h
#include dm.h
#include asm/cpu.h
+#include asm/cpu_x86.h
#include asm/lapic.h
#include asm/mp.h
#include asm/msr.h
@@ -175,18 +176,8 @@ static int baytrail_get_info(struct udevice *dev, struct
cpu_info *info)
return 0;
}
-static int cpu_x86_baytrail_bind(struct udevice *dev)
-{
- struct cpu_platdata *plat = dev_get_parent_platdata(dev);
-
- plat-cpu_id = fdtdec_get_int(gd-fdt_blob, dev-of_offset,
- intel,apic-id, -1);
-
- return 0;
-}
-
static const struct cpu_ops cpu_x86_baytrail_ops = {
- .get_desc = x86_cpu_get_desc,
+ .get_desc = cpu_x86_get_desc,
.get_info = baytrail_get_info,
};
@@ -199,7 +190,7 @@ U_BOOT_DRIVER(cpu_x86_baytrail_drv) = {
.name = cpu_x86_baytrail,
.id = UCLASS_CPU,
.of_match = cpu_x86_baytrail_ids,
- .bind = cpu_x86_baytrail_bind,
+ .bind = cpu_x86_bind,
.probe = cpu_x86_baytrail_probe,
.ops= cpu_x86_baytrail_ops,
};
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index bb4a110..ffb6e43 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -21,8 +21,6 @@
#include common.h
#include command.h
-#include cpu.h
-#include dm.h
#include errno.h
#include malloc.h
#include asm/control_regs.h
@@ -520,16 +518,6 @@ char *cpu_get_name(char *name)
return ptr;
}
-int x86_cpu_get_desc(struct udevice *dev, char *buf, int size)
-{
- if (size CPU_MAX_NAME_LEN)
- return -ENOSPC;
-
- cpu_get_name(buf);
-
- return 0;
-}
-
int default_print_cpuinfo(void)
{
printf(CPU: %s, vendor %s, device %xh\n,
@@ -622,19 +610,3 @@ int cpu_init_r(void)
{
return x86_init_cpus();
}
-
-static const struct cpu_ops cpu_x86_ops = {
- .get_desc = x86_cpu_get_desc,
-};
-
-static const struct udevice_id cpu_x86_ids[] = {
- { .compatible = cpu-x86 },
- { }
-};
-
-U_BOOT_DRIVER(cpu_x86_drv) = {
- .name = cpu_x86,
- .id = UCLASS_CPU,
- .of_match = cpu_x86_ids,
- .ops= cpu_x86_ops,
-};
diff --git a/arch/x86/cpu/cpu_x86.c b/arch/x86/cpu/cpu_x86.c
new file mode 100644
index 000..d32ba66
--- /dev/null
+++ b/arch/x86/cpu/cpu_x86.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2015, Bin Meng bmeng...@gmail.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include cpu.h
+#include dm.h
+#include errno.h
+#include asm/cpu.h
+
+int cpu_x86_bind(struct udevice *dev)
+{
+ struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+
+ plat-cpu_id = fdtdec_get_int(gd-fdt_blob, dev-of_offset,
+ intel,apic-id, -1);
+
+ return 0;
+}
+
+int cpu_x86_get_desc(struct udevice *dev, char *buf, int size)
+{
+ if (size CPU_MAX_NAME_LEN)
+ return -ENOSPC;
+
+ cpu_get_name(buf);
+
+ return 0;
+}
+
+static const struct cpu_ops cpu_x86_ops = {
+ .get_desc = cpu_x86_get_desc,
+};
+
+static const struct udevice_id cpu_x86_ids[] = {
+ { .compatible = cpu-x86 },
+ { }
+};
+
+U_BOOT_DRIVER(cpu_x86_drv) = {
+ .name = cpu_x86,
+ .id = UCLASS_CPU,
+ .of_match = cpu_x86_ids,
+ .bind
[U-Boot] [PATCH 5/9] x86: kconfig: Make MAX_CPUS and AP_STACK_SIZE depend on SMP
MAX_CPUS and AP_STACK_SIZE are only meaningful when SMP is on. Signed-off-by: Bin Meng bmeng...@gmail.com --- arch/x86/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 3506ba2..d4cd9ed 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -228,6 +228,7 @@ config FSP_TEMP_RAM_ADDR config MAX_CPUS int Maximum number of CPUs permitted +depends on SMP default 4 help When using multi-CPU chips it is possible for U-Boot to start up @@ -249,6 +250,7 @@ config SMP config AP_STACK_SIZE hex + depends on SMP default 0x1000 help Each additional CPU started by U-Boot requires its own stack. This -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 9/9] x86: crownbay: Add MP initialization
Intel Crown Bay board has a TunnelCreek processor which supports
hyper-threading. Add /cpus node in the crownbay.dts and enable
the MP initialization.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/dts/crownbay.dts | 20
configs/crownbay_defconfig | 4
2 files changed, 24 insertions(+)
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index d68efda..1ec90cd 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -23,6 +23,26 @@
silent_console = 0;
};
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = cpu-x86;
+ reg = 0;
+ intel,apic-id = 0;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = cpu-x86;
+ reg = 1;
+ intel,apic-id = 1;
+ };
+
+ };
+
gpioa {
compatible = intel,ich6-gpio;
u-boot,dm-pre-reloc;
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index d3a370d..630b412 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -2,6 +2,10 @@ CONFIG_X86=y
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE=crownbay
CONFIG_TARGET_CROWNBAY=y
+CONFIG_MAX_CPUS=2
+CONFIG_SMP=y
CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_CMD_CPU=y
CONFIG_CMD_NET=y
CONFIG_OF_CONTROL=y
+CONFIG_CPU=y
--
1.8.2.1
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[U-Boot] [PATCH 6/9] x86: kconfig: Fix minor nits in MAX_CPUS
Move MAX_CPUS definition after SMP so that it shows below SMP in the menuconfig. Also replace the leading spaces in the MAX_CPUS section with tabs to conform coding standard. Signed-off-by: Bin Meng bmeng...@gmail.com --- arch/x86/Kconfig | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index d4cd9ed..4757011 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -226,18 +226,6 @@ config FSP_TEMP_RAM_ADDR Stack top address which is used in FspInit after DRAM is ready and CAR is disabled. -config MAX_CPUS -int Maximum number of CPUs permitted -depends on SMP -default 4 -help - When using multi-CPU chips it is possible for U-Boot to start up - more than one CPU. The stack memory used by all of these CPUs is - pre-allocated so at present U-Boot wants to know the maximum - number of CPUs that may be present. Set this to at least as high - as the number of CPUs in your system (it uses about 4KB of RAM for - each CPU). - config SMP bool Enable Symmetric Multiprocessing default n @@ -248,6 +236,18 @@ config SMP only one CPU will be enabled regardless of the number of CPUs available. +config MAX_CPUS + int Maximum number of CPUs permitted + depends on SMP + default 4 + help + When using multi-CPU chips it is possible for U-Boot to start up + more than one CPU. The stack memory used by all of these CPUs is + pre-allocated so at present U-Boot wants to know the maximum + number of CPUs that may be present. Set this to at least as high + as the number of CPUs in your system (it uses about 4KB of RAM for + each CPU). + config AP_STACK_SIZE hex depends on SMP -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 7/9] x86: Move lapic_setup() call into init_bsp()
Currently lapic_setup() is called before calling mp_init(), which
then calls init_bsp() where it calls enable_lapic(), which was
already enabled in lapic_setup(). Hence move lapic_setup() call
into init_bsp() to avoid the duplication.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/cpu.c | 2 --
arch/x86/cpu/mp_init.c | 2 +-
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index ddc7dc3..dd1b18b 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -626,8 +626,6 @@ static int x86_mp_init(void)
{
struct mp_params mp_params;
- lapic_setup();
-
mp_params.num_cpus = detect_num_cpus();
mp_params.parallel_microcode_load = 0,
mp_params.flight_plan = mp_steps[0];
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index ac5753a..864eb63 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -415,7 +415,7 @@ static int init_bsp(struct udevice **devp)
cpu_get_name(processor_name);
debug(CPU: %s.\n, processor_name);
- enable_lapic();
+ lapic_setup();
apic_id = lapicid();
ret = find_cpu_by_apid_id(apic_id, devp);
--
1.8.2.1
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[U-Boot] [PATCH 8/9] x86: Clean up lapic codes
This commit cleans up the lapic codes:
- Delete arch/x86/include/asm/lapic_def.h, and move register and bit
defines into arch/x86/include/asm/lapic.h
- Use MSR defines from msr-index.h in enable_lapic() and disable_lapic()
- Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and
CONFIG_AP_IN_SIPI_WAIT
- Move struct x86_cpu_priv defines to asm/arch-ivybridge/bd82x6x.h, as
it is not apic related and only used by ivybridge
- Fix coding convention issues
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/ivybridge/model_206ax.c | 2 +-
arch/x86/cpu/lapic.c | 38
arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 14 ++-
arch/x86/include/asm/lapic.h | 131 ++
arch/x86/include/asm/lapic_def.h | 101
5 files changed, 103 insertions(+), 183 deletions(-)
delete mode 100644 arch/x86/include/asm/lapic_def.h
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c
b/arch/x86/cpu/ivybridge/model_206ax.c
index 8b08c40..fd7db97 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -13,12 +13,12 @@
#include asm/acpi.h
#include asm/cpu.h
#include asm/lapic.h
-#include asm/lapic_def.h
#include asm/msr.h
#include asm/mtrr.h
#include asm/processor.h
#include asm/speedstep.h
#include asm/turbo.h
+#include asm/arch/bd82x6x.h
#include asm/arch/model_206ax.h
static void enable_vmx(void)
diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c
index 4690603..6769ae5 100644
--- a/arch/x86/cpu/lapic.c
+++ b/arch/x86/cpu/lapic.c
@@ -8,50 +8,46 @@
*/
#include common.h
-#include asm/msr.h
-#include asm/io.h
#include asm/lapic.h
#include asm/post.h
void lapic_setup(void)
{
-#if NEED_LAPIC == 1
+#ifdef CONFIG_SMP
/* Only Pentium Pro and later have those MSR stuff */
debug(Setting up local apic: );
/* Enable the local apic */
enable_lapic();
- /*
-* Set Task Priority to 'accept all'.
-*/
+ /* Set Task Priority to 'accept all' */
lapic_write_around(LAPIC_TASKPRI,
lapic_read_around(LAPIC_TASKPRI) ~LAPIC_TPRI_MASK);
/* Put the local apic in virtual wire mode */
lapic_write_around(LAPIC_SPIV, (lapic_read_around(LAPIC_SPIV)
- ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
+ ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
lapic_write_around(LAPIC_LVT0, (lapic_read_around(LAPIC_LVT0)
- ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
- LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
- LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
- LAPIC_DELIVERY_MODE_MASK)) |
- (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
-LAPIC_DELIVERY_MODE_EXTINT));
+ ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
+ LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
+ LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
+ LAPIC_DELIVERY_MODE_MASK)) |
+ (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
+ LAPIC_DELIVERY_MODE_EXTINT));
lapic_write_around(LAPIC_LVT1, (lapic_read_around(LAPIC_LVT1)
- ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
- LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
- LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
- LAPIC_DELIVERY_MODE_MASK)) |
- (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
- LAPIC_DELIVERY_MODE_NMI));
+ ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
+ LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
+ LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
+ LAPIC_DELIVERY_MODE_MASK)) |
+ (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
+ LAPIC_DELIVERY_MODE_NMI));
debug(apic_id: 0x%02lx, , lapicid());
-#else /* !NEED_LLAPIC */
+#else /* !CONFIG_SMP */
/* Only Pentium Pro and later have those MSR stuff */
debug(Disabling local apic: );
disable_lapic();
-#endif /* !NEED_LAPIC */
+#endif /* CONFIG_SMP */
debug(done.\n);
post_code(POST_LAPIC);
}
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
index 5ae32f7..7786493 100644
--- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -16,7 +16,19 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller
*hose,
const void *blob, int node);
int bd82x6x_init(void);
-struct x86_cpu_priv;
+/**
+ * struct x86_cpu_priv -
[U-Boot] [PATCH] arm: ls102xa: Add little-endian mode support for audio IPs
As SCFG_ENDIANCR register is added to choose little-endian or big-endian
for audio IPs on Rev2.0 silion, little-endian mode is selected.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 ++-
board/freescale/ls1021aqds/ls1021aqds.c | 3 +++
board/freescale/ls1021atwr/ls1021atwr.c | 3 +++
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index ee547fb..6a330cc 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -149,6 +149,7 @@ struct ccsr_gur {
#define SCFG_ETSECCMCR_GE1_CLK125 0x0800
#define SCFG_PIXCLKCR_PXCKEN 0x8000
#define SCFG_QSPI_CLKSEL 0xc010
+#define SCFG_ENDIANCR_LE 0x8000
/* Supplemental Configuration Unit */
struct ccsr_scfg {
@@ -207,7 +208,7 @@ struct ccsr_scfg {
u32 qos2;
u32 qos3;
u32 cci_cfg;
- u32 resv8[1];
+ u32 endiancr;
u32 etsecdmamcr;
u32 usb3prm3cr;
u32 resv9[1];
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
b/board/freescale/ls1021aqds/ls1021aqds.c
index 92f613a..ce5cb52 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -209,6 +209,9 @@ int board_early_init_f(void)
out_be32(scfg-pixclkcr, SCFG_PIXCLKCR_PXCKEN);
#endif
+ /* Configure Little endian for SAI, ASRC and SPDIF */
+ out_be32(scfg-endiancr, SCFG_ENDIANCR_LE);
+
/*
* Enable snoop requests and DVM message requests for
* Slave insterface S4 (A7 core cluster)
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
b/board/freescale/ls1021atwr/ls1021atwr.c
index 043d938..8fef8e9 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -368,6 +368,9 @@ int board_early_init_f(void)
out_be32(scfg-qspi_cfg, SCFG_QSPI_CLKSEL);
#endif
+ /* Configure Little endian for SAI, ASRC and SPDIF */
+ out_be32(scfg-endiancr, SCFG_ENDIANCR_LE);
+
/*
* Enable snoop requests and DVM message requests for
* Slave insterface S4 (A7 core cluster)
--
2.1.0.27.g96db324
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[U-Boot] [PATCH 2/9] dm: cpu: Test against cpu_ops-get_info in cpu_get_info()
In cpu_get_info() it wrongly tests against cpu_ops-get_desc to see
if it is NULL. It should test against cpu_ops-get_info.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
drivers/cpu/cpu-uclass.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c
index aa0267c..d6be9d4 100644
--- a/drivers/cpu/cpu-uclass.c
+++ b/drivers/cpu/cpu-uclass.c
@@ -26,7 +26,7 @@ int cpu_get_info(struct udevice *dev, struct cpu_info *info)
{
struct cpu_ops *ops = cpu_get_ops(dev);
- if (!ops-get_desc)
+ if (!ops-get_info)
return -ENOSYS;
return ops-get_info(dev, info);
--
1.8.2.1
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[U-Boot] [PATCH 1/9] dm: cpu: Fix undefined ENOSYS build error
Include errno.h otherwise ENOSYS is undefined.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
common/cmd_cpu.c | 1 +
drivers/cpu/cpu-uclass.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/common/cmd_cpu.c b/common/cmd_cpu.c
index c3e229f..b4af64f 100644
--- a/common/cmd_cpu.c
+++ b/common/cmd_cpu.c
@@ -9,6 +9,7 @@
#include command.h
#include cpu.h
#include dm.h
+#include errno.h
static const char *cpu_feature_name[CPU_FEAT_COUNT] = {
L1 cache,
diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c
index ab18ee2..aa0267c 100644
--- a/drivers/cpu/cpu-uclass.c
+++ b/drivers/cpu/cpu-uclass.c
@@ -8,6 +8,7 @@
#include common.h
#include cpu.h
#include dm.h
+#include errno.h
#include dm/lists.h
#include dm/root.h
--
1.8.2.1
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[U-Boot] [PATCH] ARM: UniPhier: drop special CONFIG_AUTOBOOT_ settings
There is no good reason to use a particular key to stop autobooting. The default allows us to stop the autoboot with any key input. Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com --- configs/ph1_ld4_defconfig | 4 configs/ph1_pro4_defconfig | 4 configs/ph1_sld8_defconfig | 4 3 files changed, 12 deletions(-) diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig index 723989c..82ce8c7 100644 --- a/configs/ph1_ld4_defconfig +++ b/configs/ph1_ld4_defconfig @@ -9,10 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE=uniphier-ph1-ld4-ref CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_HUSH_PARSER=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT=Press SPACE to abort autoboot in %d seconds\n -CONFIG_AUTOBOOT_DELAY_STR=d -CONFIG_AUTOBOOT_STOP_STR= CONFIG_CMD_BDI=y CONFIG_CMD_CONSOLE=y CONFIG_CMD_BOOTD=y diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig index a2e2d4f..671d9cc 100644 --- a/configs/ph1_pro4_defconfig +++ b/configs/ph1_pro4_defconfig @@ -8,10 +8,6 @@ CONFIG_DEFAULT_DEVICE_TREE=uniphier-ph1-pro4-ref CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_HUSH_PARSER=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT=Press SPACE to abort autoboot in %d seconds\n -CONFIG_AUTOBOOT_DELAY_STR=d -CONFIG_AUTOBOOT_STOP_STR= CONFIG_CMD_BDI=y CONFIG_CMD_CONSOLE=y CONFIG_CMD_BOOTD=y diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig index dc59dcb..3e763dc 100644 --- a/configs/ph1_sld8_defconfig +++ b/configs/ph1_sld8_defconfig @@ -9,10 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE=uniphier-ph1-sld8-ref CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_HUSH_PARSER=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT=Press SPACE to abort autoboot in %d seconds\n -CONFIG_AUTOBOOT_DELAY_STR=d -CONFIG_AUTOBOOT_STOP_STR= CONFIG_CMD_BDI=y CONFIG_CMD_CONSOLE=y CONFIG_CMD_BOOTD=y -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Disabling Autonegotiation
Dear priyanka sharma, In message CAKynAoevduG20RKAk=4rqa7awbovzkexwa+c2iypg4gxbe-...@mail.gmail.com you wrote: I am trying to disable auto negotiation in U-boot. May I ask why exactly you want to do this? It is almost always a very bad idea to disable autonegotiation. Usually there are other ways to solve the problem, but we cannot help you because you did not mention what the problem is which you are trying to work around. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de The universe is all a spin-off of the Big Bang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv4 1/3] driver/ddr/altera: Add DDR driver for Altera's SDRAM controller
Hi!
+struct sdram_prot_rule {
+ uint64_tsdram_start; /* SDRAM start address */
+ uint64_tsdram_end; /* SDRAM end address */
+ uint32_trule; /* SDRAM protection rule number: 0-19 */
+ int valid; /* Rule valid or not? 1 - valid, 0 not*/
There should be space before */.
diff --git a/arch/arm/include/asm/arch-socfpga/sdram_config.h
b/arch/arm/include/asm/arch-socfpga/sdram_config.h
new file mode 100644
index 000..f6d51ca
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/sdram_config.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright Altera Corporation (C) 2012-2015
+ *
+ * SPDX-License-Identifier:BSD-3-Clause
+ */
+
+/* This file is autogenerated from tools provided by Altera.*/
Here too.
+#endif /*#ifndef__SDRAM_CONFIG_H*/
You should not need to comment for include guards... (and comment
style).
+static int compute_errata_rows(unsigned long long memsize, int cs, int width,
+int rows, int banks, int cols)
+{
Comment what kind of errata this is working around?
+#if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) \
+defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) \
+defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS) \
+defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS) \
+defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS)
+
Hmm? Is this really neccessary? Is it valid to provide configuration
w/o those defines?
+ writel(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS,
+sysmgr_regs-iswgrp_handoff[4]);
+#endif
+
+ /* Restore the SDR PHY Register if valid */
+ if (sdr_phy_reg != 0x)
+ writel(sdr_phy_reg, sdr_ctrl-phy_ctrl0);
+
+/* Final step - apply configuration changes */
Comment style...
+/*
+ * To calculate SDRAM device size based on SDRAM controller parameters.
+ * Size is specified in bytes.
+ *
+ * NOTE:
+ * This function is compiled and linked into the preloader and
+ * Uboot (there may be others). So if this function changes, the Preloader
+ * and UBoot must be updated simultaneously.
+ */
+unsigned long sdram_calculate_size(void)
+{
+ unsigned long temp;
+ unsigned long row, bank, col, cs, width;
+
+ temp = readl(sdr_ctrl-dram_addrw);
+ col = (temp SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK)
+ SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
+
+ /* SDRAM Failure When Accessing Non-Existent Memory
+ * Use ROWBITS from Quartus/QSys to calculate SDRAM size
+ * since the FB specifies we modify ROWBITs to work around SDRAM
+ * controller issue.
+ *
+ * If the stored handoff value for rows is 0, it probably means
+ * the preloader is older than UBoot. Use the
+ * #define from the SOCEDS Tools per Crucible review
+ * uboot-socfpga-204. Note that this is not a supported
+ * configuration and is not tested. The customer
+ * should be using preloader and uboot built from the
+ * same tag.
+ */
U-Boot is normally spelled U-Boot. You have two different variants
in comments here.
Second part of the comment is probably not relevant any more?
Acked-by: Pavel Machek pa...@denx.de
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures)
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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Re: [U-Boot] mxs power initialization
Hi Stefan, -Oorspronkelijk bericht- Van: Stefan Wahren [mailto:stefan.wah...@i2se.com] Verzonden: zaterdag 6 juni 2015 08:38 Aan: Ruud Commandeur Onderwerp: Re: [U-Boot] mxs power initialization Hi, Ruud Commandeur rcommand...@clb.nl hat am 5. Juni 2015 um 16:38 geschrieben: Hi Everyone, I'm trying to make an i.mx28 board work with a Goldcap attached to the Battery pin for RTC backup. This does not work out of the box, but I found a number of useful tips to work with. Most of these tips either refer to the imx bootlets or to code of spl_power_init.c where the mxs power registers are configured. I do not use the imx bootlets, so spl_power_init was the place to be I thought. However, it appears to be that this code is only used if an SPL_BUILD is configured (am I correct?). But if SPL is not used, which (code) part is used then to configure the imx power registers (if there is any)? i don't have answer to your question, but i want to mention that i working on the mxs power driver for Linux mainline. But my focus is on 5V only power supply. Beside the imx bootlets i took the power driver from the Freescale downstream kernel as a source of knowledge [1]. May be that is helpful. Best regards Stefan [1] - http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tr ee/drivers/power/mxs/linux.c?h=imx_2.6.35_maintain I was already wondering if the kernel would play a role here. For some reason this part was never mentioned when looking for these power issues. For some initial config bits this should not matter, but if actions should be taken on e.g. power-fail, this must reside in the kernel part. Anyway: We use the mainline 3.10 LTS and obviously this does not have this mxs directory as for the 2.6.35 Freescale one. Would you happen to know if a similar (mxs-specific) driver should be present here? P.S. I did put the u-boot-list on cc to inform about the answer(s). If the subject would change to kernel related subjects only, we could (or should) stop this I guess. Thanks in advance for your help, Ruud Commandeur ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [ANN] U-Boot v2015.07-rc2 released
Dear Tom, In message 20150608215347.GZ1728@bill-the-cat you wrote: I've pushed v2015.04-rc2 out to the repository and tarballs should exist soon. Tarballs are on the FTP server [1] and the ACD [2]. [1] ftp://ftp.denx.de/pub/u-boot/u-boot-2015.07-rc2.tar.bz2 [2] https://www.amazon.com/clouddrive/share/hW4yQM6fOkljg2eq4B48fIIjQPUsgeLmQqXVenReFQo?ref_=cd_share_link_copy Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de The Gates in my computer are AND, OR and NOT; they are not Bill. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/8] omap-common: Common boot code OMAP3 support and cleanup
On Monday 08 June 2015 23:24:19 Paul Kocialkowski wrote: diff --git a/board/nokia/rx51/lowlevel_init.S b/board/nokia/rx51/lowlevel_init.S index 9d4ea1b..9048f31 100644 --- a/board/nokia/rx51/lowlevel_init.S +++ b/board/nokia/rx51/lowlevel_init.S @@ -28,18 +28,6 @@ imagesize: /* maximal size of image */ ih_magic:/* IH_MAGIC in big endian from include/image.h */ .word 0x56190527 -/* - * Routine: save_boot_params (called after reset from start.S) - * Description: Copy attached kernel to address KERNEL_ADDRESS - * Copy u-boot to address CONFIG_SYS_TEXT_BASE - * Return to copied u-boot address - */ - -.global save_boot_params -save_boot_params: - /* Get return address */ - ldr lr, =save_boot_params_ret - /* Copy valid attached kernel to address KERNEL_ADDRESS */ copy_kernel_start: Hi, I did not tested this code yet, but quick look at it I think effectively means to totally break support for Nokia N900 (RX-51). Routine save_boot_params() was called directly from start.S before U-Boot did any HW setup and configuration. It stored needed data to make U-Boot working and more important it calculated and stored linux kernel image to safe place in RAM (which U-Boot do not touch) to make it able to boot. Nokia N900 setup is special. Nokia internal bootloader (which was not possible to replace) boot arm image stored in MTD nand. That arm image is compiled U-Boot binary with Linux kernel and Nokia bootloader load this image to random address into RAM. To make sure that U-Boot will be able to boot that kernel image we need to do some magic before U-Boot relocates itself. In next weekend (or later) I will try to find some time to test patches on real N900 device. But I think with your changes it will not work... -- Pali Rohár pali.ro...@gmail.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] arm: imx: Kernel not booting when environment is in QSPI
Adding some FSL folks in case they have some suggestions. Regards, Fabio Estevam On Tue, Jun 9, 2015 at 11:41 AM, Matthias Weißer m.weisse...@gmail.com wrote: Hi I work with an imx6sx sdb. I observed that placing u-boot in QSPI flash and also having the environment in QSPI the linux kernel doesn't boot. The backtrace from the kernel contains 'fsl_qspi_probe'. If only u-boot resides in QSPI and the environment is on mmc then the kernel boots successfully. Some more investigation showed that even when u-boot and the environment is on mmc a simple = sf probe 1:0 causing the kernel not to boot. So I suspect a problem with u-boot not leaving the QSPI hardware in a sane state for the kernel driver to take over control. If no serial flash operations are executed in u-boot I can access the flash in linux via mtd. Kernel and u-boot are both current git HEAD with minor changes. Anyone with an idea? Regards Matthias Kernel output: Starting kernel ... [0.00] Booting Linux on physical CPU 0x0 [0.00] Linux version 4.1.0-rc7-00047-g5879ae5-dirty (mweisser@ldev) (gcc version 4.9.2 (crosstool-NG 1.20.0) ) #2 Tue Jun 9 09:40:49 CEST 2015 [0.00] CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d [0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [0.00] Machine model: Freescale i.MX6 SoloX SDB RevB Board [0.00] cma: Reserved 16 MiB at 0xbf00 [0.00] Memory policy: Data cache writeback [0.00] CPU: All CPU(s) started in SVC mode. [0.00] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 260096 [0.00] Kernel command line: console=ttymxc0,115200 ip=dhcp root=/dev/nfs nfsroot=192.168.1.60:/data/users/mweisser/tgt-fs/linux-fs consoleblank=0 [0.00] PID hash table entries: 4096 (order: 2, 16384 bytes) [0.00] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) [0.00] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) [0.00] Memory: 1006056K/1048576K available (6035K kernel code, 321K rwdata, 1960K rodata, 232K init, 8310K bss, 26136K reserved, 16384K cma-reserved, 0K highmem) [0.00] Virtual kernel memory layout: [0.00] vector : 0x - 0x1000 ( 4 kB) [0.00] fixmap : 0xffc0 - 0xfff0 (3072 kB) [0.00] vmalloc : 0xc080 - 0xff00 (1000 MB) [0.00] lowmem : 0x8000 - 0xc000 (1024 MB) [0.00] pkmap : 0x7fe0 - 0x8000 ( 2 MB) [0.00] modules : 0x7f00 - 0x7fe0 ( 14 MB) [0.00] .text : 0x80008000 - 0x807d7044 (7997 kB) [0.00] .init : 0x807d8000 - 0x80812000 ( 232 kB) [0.00] .data : 0x80812000 - 0x808624e0 ( 322 kB) [0.00].bss : 0x808624e0 - 0x8107ff88 (8311 kB) [0.00] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 [0.00] Running RCU self tests [0.00] NR_IRQS:16 nr_irqs:16 16 [0.00] L2C-310 erratum 769419 enabled [0.00] L2C-310 enabling early BRESP for Cortex-A9 [0.00] L2C-310 full line of zeros enabled for Cortex-A9 [0.00] L2C-310 ID prefetch enabled, offset 1 lines [0.00] L2C-310 dynamic clock gating enabled, standby mode enabled [0.00] L2C-310 cache controller enabled, 16 ways, 256 kB [0.00] L2C-310: CACHE_ID 0x41c8, AUX_CTRL 0x76430001 [0.00] Switching to timer-based delay loop, resolution 333ns [0.07] sched_clock: 32 bits at 3000kHz, resolution 333ns, wraps every 715827882841ns [0.35] clocksource mxc_timer1: mask: 0x max_cycles: 0x, max_idle_ns: 637086815595 ns [0.000888] Console: colour dummy device 80x30 [0.000918] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar [0.000927] ... MAX_LOCKDEP_SUBCLASSES: 8 [0.000934] ... MAX_LOCK_DEPTH: 48 [0.000941] ... MAX_LOCKDEP_KEYS:8191 [0.000948] ... CLASSHASH_SIZE: 4096 [0.000955] ... MAX_LOCKDEP_ENTRIES: 32768 [0.000961] ... MAX_LOCKDEP_CHAINS: 65536 [0.000968] ... CHAINHASH_SIZE: 32768 [0.000975] memory used by lock dependency info: 5167 kB [0.000983] per task-struct memory footprint: 1152 bytes [0.001006] Calibrating delay loop (skipped), value calculated using timer frequency.. 6.00 BogoMIPS (lpj=3) [0.001023] pid_max: default: 32768 minimum: 301 [0.001180] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes) [0.001196] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes) [0.002704] CPU: Testing write buffer coherency: ok [0.003382] Setting up static identity map for 0x80008200 - 0x80008258 [0.006410] devtmpfs: initialized [0.028795] VFP support v0.3: implementor 41 architecture 3 part 30
Re: [U-Boot] [PATCH RFT] gpio: vybrid: Fix up setting output value in vybrid_gpio_direction_output
2015-06-09 21:53 GMT+08:00 Bhuvanchandra DV bhuvanchandra...@toradex.com: On 06/09/2015 06:49 PM, Axel Lin wrote: 2015-06-09 20:58 GMT+08:00 Bhuvanchandra DV bhuvanchandra...@toradex.com: Hello Axel, On 06/09/2015 02:45 PM, Axel Lin wrote: Pass correct gpio argument to gpio_set_value(). The calcualation of gpio = gpio + (gpios-chip * VYBRID_GPIO_COUNT); is required for calling imx_iomux_gpio_* functions so move them close to improve readability. Signed-off-by: Axel Lin axel@ingics.com --- Hi Bhuvanchandra, I think current code does not pass correct gpio argument to gpio_set_value() in vybrid_gpio_direction_output(). It only works if gpios-chip is 0. I don't have the h/w to test, can you double check this? gpio_set_value() needs the actual gpio number to be passed not the gpio offset of gpio chip. Are you sure? Please take a look at gpio_get_value()/gpio_set_value() implement in drivers/gpio/gpio-uclass.c. Yes, Ah, my fault actually. Sorry for the noise. Regards, Axel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] gpio: vybrid: Use proper parameter name for gpio offset
On 06/09/2015 07:54 PM, Axel Lin wrote:
It's confusing to use gpio as gpio offset parameter so rename it to offset
for better readability.
Agreed, but IMHO these offsets any way at the end are the gpio numbers
of individual gpio chip instances. e.g: gpio 2 of gpio chip 1 which is
gpio 34.
Signed-off-by: Axel Lin axel@ingics.com
---
drivers/gpio/vybrid_gpio.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpio/vybrid_gpio.c b/drivers/gpio/vybrid_gpio.c
index 6eaf0a9..14ba7e5 100644
--- a/drivers/gpio/vybrid_gpio.c
+++ b/drivers/gpio/vybrid_gpio.c
@@ -21,54 +21,54 @@ struct vybrid_gpios {
struct vybrid_gpio_regs *reg;
};
-static int vybrid_gpio_direction_input(struct udevice *dev, unsigned gpio)
+static int vybrid_gpio_direction_input(struct udevice *dev, unsigned offset)
{
const struct vybrid_gpios *gpios = dev_get_priv(dev);
+ unsigned gpio = offset + (gpios-chip * VYBRID_GPIO_COUNT);
- gpio = gpio + (gpios-chip * VYBRID_GPIO_COUNT);
imx_iomux_gpio_set_direction(gpio, VF610_GPIO_DIRECTION_IN);
return 0;
}
-static int vybrid_gpio_direction_output(struct udevice *dev, unsigned gpio,
+static int vybrid_gpio_direction_output(struct udevice *dev, unsigned offset,
int value)
{
const struct vybrid_gpios *gpios = dev_get_priv(dev);
+ unsigned gpio = offset + (gpios-chip * VYBRID_GPIO_COUNT);
- gpio = gpio + (gpios-chip * VYBRID_GPIO_COUNT);
gpio_set_value(gpio, value);
imx_iomux_gpio_set_direction(gpio, VF610_GPIO_DIRECTION_OUT);
return 0;
}
-static int vybrid_gpio_get_value(struct udevice *dev, unsigned gpio)
+static int vybrid_gpio_get_value(struct udevice *dev, unsigned offset)
{
const struct vybrid_gpios *gpios = dev_get_priv(dev);
- return ((readl(gpios-reg-gpio_pdir) (1 gpio))) ? 1 : 0;
+ return ((readl(gpios-reg-gpio_pdir) (1 offset))) ? 1 : 0;
}
-static int vybrid_gpio_set_value(struct udevice *dev, unsigned gpio,
+static int vybrid_gpio_set_value(struct udevice *dev, unsigned offset,
int value)
{
const struct vybrid_gpios *gpios = dev_get_priv(dev);
+
if (value)
- writel((1 gpio), gpios-reg-gpio_psor);
+ writel((1 offset), gpios-reg-gpio_psor);
else
- writel((1 gpio), gpios-reg-gpio_pcor);
+ writel((1 offset), gpios-reg-gpio_pcor);
return 0;
}
-static int vybrid_gpio_get_function(struct udevice *dev, unsigned gpio)
+static int vybrid_gpio_get_function(struct udevice *dev, unsigned offset)
{
const struct vybrid_gpios *gpios = dev_get_priv(dev);
+ unsigned gpio = offset + (gpios-chip * VYBRID_GPIO_COUNT);
u32 g_state = 0;
- gpio = gpio + (gpios-chip * VYBRID_GPIO_COUNT);
-
imx_iomux_gpio_get_function(gpio, g_state);
if (((g_state (0x07 PAD_MUX_MODE_SHIFT)) PAD_MUX_MODE_SHIFT)
0)
Best regards,
Bhuvan
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[U-Boot] arm: imx: Kernel not booting when environment is in QSPI
Hi I work with an imx6sx sdb. I observed that placing u-boot in QSPI flash and also having the environment in QSPI the linux kernel doesn't boot. The backtrace from the kernel contains 'fsl_qspi_probe'. If only u-boot resides in QSPI and the environment is on mmc then the kernel boots successfully. Some more investigation showed that even when u-boot and the environment is on mmc a simple = sf probe 1:0 causing the kernel not to boot. So I suspect a problem with u-boot not leaving the QSPI hardware in a sane state for the kernel driver to take over control. If no serial flash operations are executed in u-boot I can access the flash in linux via mtd. Kernel and u-boot are both current git HEAD with minor changes. Anyone with an idea? Regards Matthias Kernel output: Starting kernel ... [0.00] Booting Linux on physical CPU 0x0 [0.00] Linux version 4.1.0-rc7-00047-g5879ae5-dirty (mweisser@ldev) (gcc version 4.9.2 (crosstool-NG 1.20.0) ) #2 Tue Jun 9 09:40:49 CEST 2015 [0.00] CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d [0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [0.00] Machine model: Freescale i.MX6 SoloX SDB RevB Board [0.00] cma: Reserved 16 MiB at 0xbf00 [0.00] Memory policy: Data cache writeback [0.00] CPU: All CPU(s) started in SVC mode. [0.00] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 260096 [0.00] Kernel command line: console=ttymxc0,115200 ip=dhcp root=/dev/nfs nfsroot=192.168.1.60:/data/users/mweisser/tgt-fs/linux-fs consoleblank=0 [0.00] PID hash table entries: 4096 (order: 2, 16384 bytes) [0.00] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) [0.00] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) [0.00] Memory: 1006056K/1048576K available (6035K kernel code, 321K rwdata, 1960K rodata, 232K init, 8310K bss, 26136K reserved, 16384K cma-reserved, 0K highmem) [0.00] Virtual kernel memory layout: [0.00] vector : 0x - 0x1000 ( 4 kB) [0.00] fixmap : 0xffc0 - 0xfff0 (3072 kB) [0.00] vmalloc : 0xc080 - 0xff00 (1000 MB) [0.00] lowmem : 0x8000 - 0xc000 (1024 MB) [0.00] pkmap : 0x7fe0 - 0x8000 ( 2 MB) [0.00] modules : 0x7f00 - 0x7fe0 ( 14 MB) [0.00] .text : 0x80008000 - 0x807d7044 (7997 kB) [0.00] .init : 0x807d8000 - 0x80812000 ( 232 kB) [0.00] .data : 0x80812000 - 0x808624e0 ( 322 kB) [0.00].bss : 0x808624e0 - 0x8107ff88 (8311 kB) [0.00] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 [0.00] Running RCU self tests [0.00] NR_IRQS:16 nr_irqs:16 16 [0.00] L2C-310 erratum 769419 enabled [0.00] L2C-310 enabling early BRESP for Cortex-A9 [0.00] L2C-310 full line of zeros enabled for Cortex-A9 [0.00] L2C-310 ID prefetch enabled, offset 1 lines [0.00] L2C-310 dynamic clock gating enabled, standby mode enabled [0.00] L2C-310 cache controller enabled, 16 ways, 256 kB [0.00] L2C-310: CACHE_ID 0x41c8, AUX_CTRL 0x76430001 [0.00] Switching to timer-based delay loop, resolution 333ns [0.07] sched_clock: 32 bits at 3000kHz, resolution 333ns, wraps every 715827882841ns [0.35] clocksource mxc_timer1: mask: 0x max_cycles: 0x, max_idle_ns: 637086815595 ns [0.000888] Console: colour dummy device 80x30 [0.000918] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar [0.000927] ... MAX_LOCKDEP_SUBCLASSES: 8 [0.000934] ... MAX_LOCK_DEPTH: 48 [0.000941] ... MAX_LOCKDEP_KEYS:8191 [0.000948] ... CLASSHASH_SIZE: 4096 [0.000955] ... MAX_LOCKDEP_ENTRIES: 32768 [0.000961] ... MAX_LOCKDEP_CHAINS: 65536 [0.000968] ... CHAINHASH_SIZE: 32768 [0.000975] memory used by lock dependency info: 5167 kB [0.000983] per task-struct memory footprint: 1152 bytes [0.001006] Calibrating delay loop (skipped), value calculated using timer frequency.. 6.00 BogoMIPS (lpj=3) [0.001023] pid_max: default: 32768 minimum: 301 [0.001180] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes) [0.001196] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes) [0.002704] CPU: Testing write buffer coherency: ok [0.003382] Setting up static identity map for 0x80008200 - 0x80008258 [0.006410] devtmpfs: initialized [0.028795] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4 [0.029434] clocksource jiffies: mask: 0x max_cycles: 0x, max_idle_ns: 1911260446275 ns [0.031015] pinctrl core: initialized pinctrl subsystem [0.034119] NET: Registered protocol family 16 [0.037054] DMA:
[U-Boot] [PATCH] gpio: vybrid: Use proper parameter name for gpio offset
It's confusing to use gpio as gpio offset parameter so rename it to offset
for better readability.
Signed-off-by: Axel Lin axel@ingics.com
---
drivers/gpio/vybrid_gpio.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpio/vybrid_gpio.c b/drivers/gpio/vybrid_gpio.c
index 6eaf0a9..14ba7e5 100644
--- a/drivers/gpio/vybrid_gpio.c
+++ b/drivers/gpio/vybrid_gpio.c
@@ -21,54 +21,54 @@ struct vybrid_gpios {
struct vybrid_gpio_regs *reg;
};
-static int vybrid_gpio_direction_input(struct udevice *dev, unsigned gpio)
+static int vybrid_gpio_direction_input(struct udevice *dev, unsigned offset)
{
const struct vybrid_gpios *gpios = dev_get_priv(dev);
+ unsigned gpio = offset + (gpios-chip * VYBRID_GPIO_COUNT);
- gpio = gpio + (gpios-chip * VYBRID_GPIO_COUNT);
imx_iomux_gpio_set_direction(gpio, VF610_GPIO_DIRECTION_IN);
return 0;
}
-static int vybrid_gpio_direction_output(struct udevice *dev, unsigned gpio,
+static int vybrid_gpio_direction_output(struct udevice *dev, unsigned offset,
int value)
{
const struct vybrid_gpios *gpios = dev_get_priv(dev);
+ unsigned gpio = offset + (gpios-chip * VYBRID_GPIO_COUNT);
- gpio = gpio + (gpios-chip * VYBRID_GPIO_COUNT);
gpio_set_value(gpio, value);
imx_iomux_gpio_set_direction(gpio, VF610_GPIO_DIRECTION_OUT);
return 0;
}
-static int vybrid_gpio_get_value(struct udevice *dev, unsigned gpio)
+static int vybrid_gpio_get_value(struct udevice *dev, unsigned offset)
{
const struct vybrid_gpios *gpios = dev_get_priv(dev);
- return ((readl(gpios-reg-gpio_pdir) (1 gpio))) ? 1 : 0;
+ return ((readl(gpios-reg-gpio_pdir) (1 offset))) ? 1 : 0;
}
-static int vybrid_gpio_set_value(struct udevice *dev, unsigned gpio,
+static int vybrid_gpio_set_value(struct udevice *dev, unsigned offset,
int value)
{
const struct vybrid_gpios *gpios = dev_get_priv(dev);
+
if (value)
- writel((1 gpio), gpios-reg-gpio_psor);
+ writel((1 offset), gpios-reg-gpio_psor);
else
- writel((1 gpio), gpios-reg-gpio_pcor);
+ writel((1 offset), gpios-reg-gpio_pcor);
return 0;
}
-static int vybrid_gpio_get_function(struct udevice *dev, unsigned gpio)
+static int vybrid_gpio_get_function(struct udevice *dev, unsigned offset)
{
const struct vybrid_gpios *gpios = dev_get_priv(dev);
+ unsigned gpio = offset + (gpios-chip * VYBRID_GPIO_COUNT);
u32 g_state = 0;
- gpio = gpio + (gpios-chip * VYBRID_GPIO_COUNT);
-
imx_iomux_gpio_get_function(gpio, g_state);
if (((g_state (0x07 PAD_MUX_MODE_SHIFT)) PAD_MUX_MODE_SHIFT)
0)
--
2.1.0
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[U-Boot] [PATCH] Nokia RX-51: Fix calculating return address in save_boot_params
Commit e11c6c279d823dc0d2f470c5c2e3c0a9854a640f broke calculating lr register in function save_boot_params() and caused U-Boot to crash at early boot time on Nokia N900 board. This patch fix calculating return address in lr register and make Nokia N900 board bootable again. Patch was tested in qemu and also on real N900 HW. Signed-off-by: Pali Rohár pali.ro...@gmail.com --- board/nokia/rx51/lowlevel_init.S |4 1 file changed, 4 deletions(-) diff --git a/board/nokia/rx51/lowlevel_init.S b/board/nokia/rx51/lowlevel_init.S index 9d4ea1b..420ad13 100644 --- a/board/nokia/rx51/lowlevel_init.S +++ b/board/nokia/rx51/lowlevel_init.S @@ -105,10 +105,6 @@ fix_start: /* r6 - maximal u-boot size */ ldr r6, imagesize - /* fix return address */ - subhi lr, lr, r5 - addlo lr, lr, r5 - /* r1 - start of u-boot after */ ldr r1, startaddr -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/8] omap-common: Common boot code OMAP3 support and SYS_BOOT-based fallback boot device
On Monday 08 June 2015 23:24:18 Paul Kocialkowski wrote: I would be very glad to see board maintainers give a go at the changeset before it gets merged, especially on devices like the Nokia RX-51 (N900) where some specific adaptation was needed. So U-Boot is broken since e11c6c279d823dc0d2f470c5c2e3c0a9854a640f (see other email thread). Until somebody fix that broken commit, I cannot test your new patches in qemu or on (real) Nokia N900. -- Pali Rohár pali.ro...@gmail.com signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] arm: imx: Kernel not booting when environment is in QSPI
On 06/09/2015 10:02 AM, Fabio Estevam wrote: Adding some FSL folks in case they have some suggestions. Regards, Fabio Estevam On Tue, Jun 9, 2015 at 11:41 AM, Matthias Weißer m.weisse...@gmail.com wrote: Hi I work with an imx6sx sdb. I observed that placing u-boot in QSPI flash and also having the environment in QSPI the linux kernel doesn't boot. The backtrace from the kernel contains 'fsl_qspi_probe'. If only u-boot resides in QSPI and the environment is on mmc then the kernel boots successfully. Some more investigation showed that even when u-boot and the environment is on mmc a simple = sf probe 1:0 causing the kernel not to boot. So I suspect a problem with u-boot not leaving the QSPI hardware in a sane state for the kernel driver to take over control. If no serial flash operations are executed in u-boot I can access the flash in linux via mtd. Kernel and u-boot are both current git HEAD with minor changes. Anyone with an idea? Regards Matthias Kernel output: Starting kernel ... [0.00] Booting Linux on physical CPU 0x0 [0.00] Linux version 4.1.0-rc7-00047-g5879ae5-dirty (mweisser@ldev) (gcc version 4.9.2 (crosstool-NG 1.20.0) ) #2 Tue Jun 9 09:40:49 CEST 2015 [0.00] CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d [0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [0.00] Machine model: Freescale i.MX6 SoloX SDB RevB Board [0.00] cma: Reserved 16 MiB at 0xbf00 [0.00] Memory policy: Data cache writeback [0.00] CPU: All CPU(s) started in SVC mode. [0.00] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 260096 [0.00] Kernel command line: console=ttymxc0,115200 ip=dhcp root=/dev/nfs nfsroot=192.168.1.60:/data/users/mweisser/tgt-fs/linux-fs consoleblank=0 [0.00] PID hash table entries: 4096 (order: 2, 16384 bytes) [0.00] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) [0.00] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) [0.00] Memory: 1006056K/1048576K available (6035K kernel code, 321K rwdata, 1960K rodata, 232K init, 8310K bss, 26136K reserved, 16384K cma-reserved, 0K highmem) [0.00] Virtual kernel memory layout: [0.00] vector : 0x - 0x1000 ( 4 kB) [0.00] fixmap : 0xffc0 - 0xfff0 (3072 kB) [0.00] vmalloc : 0xc080 - 0xff00 (1000 MB) [0.00] lowmem : 0x8000 - 0xc000 (1024 MB) [0.00] pkmap : 0x7fe0 - 0x8000 ( 2 MB) [0.00] modules : 0x7f00 - 0x7fe0 ( 14 MB) [0.00] .text : 0x80008000 - 0x807d7044 (7997 kB) [0.00] .init : 0x807d8000 - 0x80812000 ( 232 kB) [0.00] .data : 0x80812000 - 0x808624e0 ( 322 kB) [0.00].bss : 0x808624e0 - 0x8107ff88 (8311 kB) [0.00] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 [0.00] Running RCU self tests [0.00] NR_IRQS:16 nr_irqs:16 16 [0.00] L2C-310 erratum 769419 enabled [0.00] L2C-310 enabling early BRESP for Cortex-A9 [0.00] L2C-310 full line of zeros enabled for Cortex-A9 [0.00] L2C-310 ID prefetch enabled, offset 1 lines [0.00] L2C-310 dynamic clock gating enabled, standby mode enabled [0.00] L2C-310 cache controller enabled, 16 ways, 256 kB [0.00] L2C-310: CACHE_ID 0x41c8, AUX_CTRL 0x76430001 [0.00] Switching to timer-based delay loop, resolution 333ns [0.07] sched_clock: 32 bits at 3000kHz, resolution 333ns, wraps every 715827882841ns [0.35] clocksource mxc_timer1: mask: 0x max_cycles: 0x, max_idle_ns: 637086815595 ns [0.000888] Console: colour dummy device 80x30 [0.000918] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar [0.000927] ... MAX_LOCKDEP_SUBCLASSES: 8 [0.000934] ... MAX_LOCK_DEPTH: 48 [0.000941] ... MAX_LOCKDEP_KEYS:8191 [0.000948] ... CLASSHASH_SIZE: 4096 [0.000955] ... MAX_LOCKDEP_ENTRIES: 32768 [0.000961] ... MAX_LOCKDEP_CHAINS: 65536 [0.000968] ... CHAINHASH_SIZE: 32768 [0.000975] memory used by lock dependency info: 5167 kB [0.000983] per task-struct memory footprint: 1152 bytes [0.001006] Calibrating delay loop (skipped), value calculated using timer frequency.. 6.00 BogoMIPS (lpj=3) [0.001023] pid_max: default: 32768 minimum: 301 [0.001180] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes) [0.001196] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes) [0.002704] CPU: Testing write buffer coherency: ok [0.003382] Setting up static identity map for 0x80008200 - 0x80008258 [0.006410] devtmpfs: initialized [0.028795] VFP
[U-Boot] Pull request: u-boot-tegra/master
Tom, Please pull u-boot-tegra/master into U-Boot/master. Thanks! ./MAKEALL -s tegra is OK, nyan-big verified by Simon. The following changes since commit 3d0158ae18bef2ac89979f4c90419d3add436c71: Prepare v2015.07-rc2 (2015-06-08 17:48:33 -0400) are available in the git repository at: git://git.denx.de/u-boot-tegra.git master for you to fetch changes up to b7160fabf11f423e879ee9cdcf8f7d0de7964509: tegra: config: nyan-big: Add options required by Chrome OS boot (2015-06-09 09:56:16 -0700) Simon Glass (15): tegra: cros_ec: Add tegra support for Chrome OS EC tegra: spi: Drop the claim_bus() method to correct delays dm: tegra: cros_ec: Enable Chrome OS EC on Nyan-big tegra: spi: Support slow SPI rates tegra: clock: Support enabling external clocks tegra: clock: Adjust PLL access to avoid a warning tegra: Introduce SRAM repair on tegra124 tegra: Add missing tegra124 peripherals tegra: Increase maximum arguments to 32 tegra: lcd: Tidy up clock init tegra: Allow board-specific init tegra: nyan-big: Add additional clock and kernel init tegra: config: Allow Chrome OS environment settings to be included tegra: Replace 'Norrin' with 'Nyan-big' and fix typo tegra: config: nyan-big: Add options required by Chrome OS boot arch/arm/dts/tegra124-nyan-big.dts| 3 + arch/arm/include/asm/arch-tegra/clock.h | 8 +++ arch/arm/include/asm/arch-tegra/sys_proto.h | 7 +++ arch/arm/include/asm/arch-tegra124/clock-tables.h | 12 ++-- arch/arm/include/asm/arch-tegra124/flow.h | 12 arch/arm/mach-tegra/board2.c | 8 ++- arch/arm/mach-tegra/clock.c | 24 +++- arch/arm/mach-tegra/powergate.c | 20 ++- arch/arm/mach-tegra/tegra124/Kconfig | 2 +- arch/arm/mach-tegra/tegra124/clock.c | 2 +- board/nvidia/nyan-big/MAINTAINERS | 2 +- board/nvidia/nyan-big/nyan-big.c | 69 +++ configs/nyan-big_defconfig| 5 ++ drivers/spi/tegra114_spi.c| 40 +++-- drivers/video/tegra124/tegra124-lcd.c | 4 +- include/configs/nyan-big.h| 7 +++ include/configs/tegra-common-post.h | 15 - include/configs/tegra-common.h| 2 +- 18 files changed, 204 insertions(+), 38 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv4 1/3] driver/ddr/altera: Add DDR driver for Altera's SDRAM controller
On 6/9/15 6:55 AM, Pavel Machek wrote:
Hi!
+struct sdram_prot_rule {
+uint64_tsdram_start; /* SDRAM start address */
+uint64_tsdram_end; /* SDRAM end address */
+uint32_trule; /* SDRAM protection rule number: 0-19 */
+int valid; /* Rule valid or not? 1 - valid, 0 not*/
There should be space before */.
Ok...
diff --git a/arch/arm/include/asm/arch-socfpga/sdram_config.h
b/arch/arm/include/asm/arch-socfpga/sdram_config.h
new file mode 100644
index 000..f6d51ca
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/sdram_config.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright Altera Corporation (C) 2012-2015
+ *
+ * SPDX-License-Identifier:BSD-3-Clause
+ */
+
+/* This file is autogenerated from tools provided by Altera.*/
Here too.
Ok...
+#endif /*#ifndef__SDRAM_CONFIG_H*/
You should not need to comment for include guards... (and comment
style).
+static int compute_errata_rows(unsigned long long memsize, int cs, int
width,
+ int rows, int banks, int cols)
+{
Comment what kind of errata this is working around?
I'll have to ask around.
+#if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) \
+defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) \
+defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS) \
+defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS) \
+defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS)
+
Hmm? Is this really neccessary? Is it valid to provide configuration
w/o those defines?
These defines are necessary as I want to keep some level of continuity
with the Altera tools that generates these config files to this.
+writel(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS,
+ sysmgr_regs-iswgrp_handoff[4]);
+#endif
+
+/* Restore the SDR PHY Register if valid */
+if (sdr_phy_reg != 0x)
+writel(sdr_phy_reg, sdr_ctrl-phy_ctrl0);
+
+/* Final step - apply configuration changes */
Comment style...
Ok..
+/*
+ * To calculate SDRAM device size based on SDRAM controller parameters.
+ * Size is specified in bytes.
+ *
+ * NOTE:
+ * This function is compiled and linked into the preloader and
+ * Uboot (there may be others). So if this function changes, the Preloader
+ * and UBoot must be updated simultaneously.
+ */
+unsigned long sdram_calculate_size(void)
+{
+unsigned long temp;
+unsigned long row, bank, col, cs, width;
+
+temp = readl(sdr_ctrl-dram_addrw);
+col = (temp SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK)
+SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
+
+/* SDRAM Failure When Accessing Non-Existent Memory
+ * Use ROWBITS from Quartus/QSys to calculate SDRAM size
+ * since the FB specifies we modify ROWBITs to work around SDRAM
+ * controller issue.
+ *
+ * If the stored handoff value for rows is 0, it probably means
+ * the preloader is older than UBoot. Use the
+ * #define from the SOCEDS Tools per Crucible review
+ * uboot-socfpga-204. Note that this is not a supported
+ * configuration and is not tested. The customer
+ * should be using preloader and uboot built from the
+ * same tag.
+ */
U-Boot is normally spelled U-Boot. You have two different variants
in comments here.
Thanks for the comment here, and will be more cognizant in the future on
this fact.
Second part of the comment is probably not relevant any more?
removed...
Acked-by: Pavel Machek pa...@denx.de
Pavel
Thanks,
Dinh
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[U-Boot] U-Boot: Nokia N900 (RX-51) is broken again
Hello, commit e11c6c279d823dc0d2f470c5c2e3c0a9854a640f Author: Simon Glass s...@chromium.org Date: Sat Feb 7 10:47:28 2015 -0700 arm: Allow lr to be saved by board code The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: Simon Glass s...@chromium.org Acked-by: Siarhei Siamashka siarhei.siamas...@gmail.com Acked-by: Hans de Goede hdego...@redhat.com Signed-off-by: Hans de Goede hdego...@redhat.com This commit broke Nokia N900 board support. When I tried it to boot in qemu I just get this qemu error message: qemu: fatal: Trying to execute code outside RAM or ROM at 0x7fb0fdfc R00=806ffd08 R01=80207800 R02=80207800 R03= R04= R05= R06= R07= R08= R09= R10= R11= R12=8414 R13=804ffb90 R14=7fb0fdfc R15=7fb0fdfc PSR=61df -ZC- A sys32 Aborted U-Boot compiled before above commit working in qemu fine. When I revert commits 5519912164698b634893913b4408fee736d01d06 and e11c6c279d823dc0d2f470c5c2e3c0a9854a640f on top of master, then u-boot from master working fine on Nokia N900. Can you fix broken commit? Because now U-Boot for Nokia N900 board is not working... Thanks. -- Pali Rohár pali.ro...@gmail.com signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Nokia RX-51: Fix calculating return address in save_boot_params
On Tuesday 09 June 2015 20:11:22 Simon Glass wrote: On 9 June 2015 at 10:05, Pali Rohár pali.ro...@gmail.com wrote: Commit e11c6c279d823dc0d2f470c5c2e3c0a9854a640f broke calculating lr register in function save_boot_params() and caused U-Boot to crash at early boot time on Nokia N900 board. This patch fix calculating return address in lr register and make Nokia N900 board bootable again. Patch was tested in qemu and also on real N900 HW. Signed-off-by: Pali Rohár pali.ro...@gmail.com --- board/nokia/rx51/lowlevel_init.S |4 1 file changed, 4 deletions(-) Reviewed-by: Simon Glass s...@chromium.org Tom, can you please apply this patch for 2015.07? Simon others: in future, please can you CC me all patches which touch Nokia N900 board code? We can prevent such breakage. Also you can test u-boot for n900 in qemu. -- Pali Rohár pali.ro...@gmail.com signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Nokia RX-51: Fix calculating return address in save_boot_params
On 9 June 2015 at 10:05, Pali Rohár pali.ro...@gmail.com wrote: Commit e11c6c279d823dc0d2f470c5c2e3c0a9854a640f broke calculating lr register in function save_boot_params() and caused U-Boot to crash at early boot time on Nokia N900 board. This patch fix calculating return address in lr register and make Nokia N900 board bootable again. Patch was tested in qemu and also on real N900 HW. Signed-off-by: Pali Rohár pali.ro...@gmail.com --- board/nokia/rx51/lowlevel_init.S |4 1 file changed, 4 deletions(-) Reviewed-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/8] omap-common: Common boot code OMAP3 support and SYS_BOOT-based fallback boot device
On Tuesday 09 June 2015 18:28:29 Pali Rohár wrote: On Monday 08 June 2015 23:24:18 Paul Kocialkowski wrote: I would be very glad to see board maintainers give a go at the changeset before it gets merged, especially on devices like the Nokia RX-51 (N900) where some specific adaptation was needed. So U-Boot is broken since e11c6c279d823dc0d2f470c5c2e3c0a9854a640f (see other email thread). Until somebody fix that broken commit, I cannot test your new patches in qemu or on (real) Nokia N900. Now I tested this patch series on top of u-boot master with applied my patch Nokia RX-51: Fix calculating return address in save_boot_params. And it really as I thought broke booting U-Boot on Nokia N900 in qemu. So this patch series is NAK from my side. -- Pali Rohár pali.ro...@gmail.com signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Disabling Autonegotiation
Hi all 2015-06-09 21:50 GMT+02:00 Christian Gmeiner christian.gmei...@gmail.com: Hi all 2015-06-09 15:04 GMT+02:00 Wolfgang Denk w...@denx.de: Dear priyanka sharma, please keep the mailinmg list on Cc: In message CAKynAoccK9AwcQrt-ggWRYj5RiTLtnf00+fU71=ymog+8ej...@mail.gmail.com you wrote: Disabling auto negotiation along with limiting ethernet PHY to 100MBit is a part of requirements for a custom solution. This does not actually answer my question. What I'm interested to understand is _why_ you want to do that. As mentioned before, autonegotiation is usually a good thing to have, and mandatory in many cases. If you disable it, you probably want to work around some problem (eventually caused by broken or mis-designed hardware), and depending on the nature of the problem there might be better ways to solve it. I have the same cosmetic issue (and can live with it). The cause to disable autoneg for my case is quite simple. On a custom imx6 based board the fec is directly connected via MII to an Ethernet switch (KSZ8895). In that case the link to the switch is always up and autoneg does not work. Under linux I am using the fixed phy device tree binding. drivers/net/phy/micrel.c has support for the KSZ8895 - will give it a try :) greets -- Christian Gmeiner, MSc https://soundcloud.com/christian-gmeiner ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Disabling Autonegotiation
Hi all 2015-06-09 15:04 GMT+02:00 Wolfgang Denk w...@denx.de: Dear priyanka sharma, please keep the mailinmg list on Cc: In message CAKynAoccK9AwcQrt-ggWRYj5RiTLtnf00+fU71=ymog+8ej...@mail.gmail.com you wrote: Disabling auto negotiation along with limiting ethernet PHY to 100MBit is a part of requirements for a custom solution. This does not actually answer my question. What I'm interested to understand is _why_ you want to do that. As mentioned before, autonegotiation is usually a good thing to have, and mandatory in many cases. If you disable it, you probably want to work around some problem (eventually caused by broken or mis-designed hardware), and depending on the nature of the problem there might be better ways to solve it. I have the same cosmetic issue (and can live with it). The cause to disable autoneg for my case is quite simple. On a custom imx6 based board the fec is directly connected via MII to an Ethernet switch (KSZ8895). In that case the link to the switch is always up and autoneg does not work. Under linux I am using the fixed phy device tree binding. greets -- Christian Gmeiner, MSc https://soundcloud.com/christian-gmeiner ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] What is the expected meaning of CONFIG_SYS_NO_FLASH
Hi, There is a bit of confusion at $dayjob about when CONFIG_SYS_NO_FLASH is used. Initially we thought that this meant I have no parallel NOR flash. So a board with only SPI flash would have CONFIG_SYS_NO_FLASH=1 and CONFIG_SPI_FLASH=1. Is this understanding correct? I'd like to be able to add a blurb to README about how CONFIG_SYS_NO_FLASH should be used. Based on what I can tell from the code there seems to be a requirement that if !defined(CONFIG_SYS_NO_FLASH) something must implement flash_init(), flash_write(), etc as defined in include/flash.h. This could be a driver like cfi_flash.c or a board specific implementation. Thanks, Chris ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv4 2/3] driver/ddr/altera: Add the sdram calibration portion
In title, you can convert sdram-SDRAM
On Tue 2015-06-02 22:52:49, dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
This patch adds the DDR calibration portion of the Altera SDRAM driver.
Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com
+/*
+ * In order to reduce ROM size, most of the selectable calibration steps are
+ * decided at compile time based on the user's calibration mode selection,
+ * as captured by the STATIC_CALIB_STEPS selection below.
+ *
+ * However, to support simulation-time selection of fast simulation mode,
where
+ * we skip everything except the bare minimum, we need a few of the steps to
+ * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
+ * check, which is based on the rtl-supplied value, or we dynamically compute
+ * the value to use based on the dynamically-chosen calibration mode
. at the end of sentence.
+
+#define DLEVEL 0
+#define STATIC_IN_RTL_SIM 0
+#define STATIC_SKIP_DELAY_LOOPS 0
+
+#define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
+ STATIC_SKIP_DELAY_LOOPS)
Would it make sense to drop simulation-time support for initial merge?
+/* calibration steps requested by the rtl */
+uint16_t dyn_calib_steps;
rtl?
+/*
+ * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
+ * instead of static, we use boolean logic to select between
+ * non-skip and skip values
+ *
+ * The mask is set to include all bits when not-skipping, but is
+ * zero when skipping
+ */
. at the end of sentence. Twice here :-).
+
+uint16_t skip_delay_mask;/* mask off bits when skipping/not-skipping */
+
+#define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
+ ((non_skip_value) skip_delay_mask)
+
+struct gbl_type *gbl;
+struct param_type *param;
+uint32_t curr_shadow_reg;
+
+static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
+ uint32_t write_group, uint32_t use_dm,
+ uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
+
+static u32 sdr_get_addr(u32 *base)
+{
+ u32 addr = (u32)base MGR_SELECT_MASK;
You sometimes use uint32_t, and sometimes u32, as seen here. Would it
be more readable to just use u32 everywhere?
And this function would be really helped by taking u32 base, not
u32 *, as youd reduce number of typecasts below...
+ switch (addr) {
+ case BASE_PHY_MGR:
+ addr = (((u32)base 8) (1 6)) | ((u32)base 0x3f) |
+ SDR_PHYGRP_PHYMGRGRP_ADDRESS;
+ break;
+ case BASE_RW_MGR:
+ addr = ((u32)base 0x1fff) | SDR_PHYGRP_RWMGRGRP_ADDRESS;
+ break;
+ case BASE_DATA_MGR:
+ addr = ((u32)base 0x7ff) | SDR_PHYGRP_DATAMGRGRP_ADDRESS;
+ break;
+ case BASE_SCC_MGR:
+ addr = ((u32)base 0xfff) | SDR_PHYGRP_SCCGRP_ADDRESS;
+ break;
+ case BASE_REG_FILE:
+ addr = ((u32)base 0x7ff) | SDR_PHYGRP_REGFILEGRP_ADDRESS;
+ break;
+ case BASE_MMR:
+ addr = ((u32)base 0xfff) | SDR_CTRLGRP_ADDRESS;
+ break;
Or at least introduce temporary variable...
+static void initialize(void)
+{
+ u32 addr = sdr_get_addr(phy_mgr_cfg-mux_sel);
+
+ debug(%s:%d\n, __func__, __LINE__);
Is this debugging neccessary? It will change when you for example
change comment in here...
+ /* USER calibration has control over path to memory */
+ /*
+ * In Hard PHY this is a 2-bit control:
+ * 0: AFI Mux Select
+ * 1: DDIO Mux Select
+ */
+ writel(0x3, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* USER memory clock is not stable we begin initialization */
*/ - */
+ for (i = 0; i 16; i++) {
+ debug_cond(DLEVEL == 1, %s:%d: Clearing SCC RFILE index %u,
+__func__, __LINE__, i);
Ok, custom debugging system. Neccessary?
+static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
+{
+ uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_DQS_EN_DELAY);
Now uint32_t vs. u32 on single line...
+ for (r = 0; r RW_MGR_MEM_NUMBER_OF_RANKS;
+ r += NUM_RANKS_PER_SHADOW_REG) {
+ scc_mgr_set_dqs_en_delay(read_group, delay);
+
+ addr = sdr_get_addr(sdr_scc_mgr-dqs_ena);
+ writel(read_group, SOCFPGA_SDR_ADDRESS + addr);
+ /*
+ * In shadow register mode, the T11 settings are stored in
+ * registers in the core, which are updated by the DQS_ENA
+ * signals. Not issuing the SCC_MGR_UPD command allows us to
+ * save lots of rank switching overhead, by calling
+ * select_shadow_regs_for_update with update_scan_chains
+ * set to 0.
+ */
+ addr = sdr_get_addr(sdr_scc_mgr-update);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ }
+ /*
+ *
Re: [U-Boot] [PATCHv4 3/3] arm: socfpga: enable the Altera SDRAM controller driver
On Tue 2015-06-02 22:52:50, dingu...@opensource.altera.com wrote: From: Dinh Nguyen dingu...@opensource.altera.com Enable the Altera SDRAM driver for the SoCFPGA platform. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com Acked-by: Marek Vasut ma...@denx.de Acked-by: Pavel Machek pa...@denx.de -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH RFT] gpio: vybrid: Fix up setting output value in vybrid_gpio_direction_output
Hello Axel,
On 06/09/2015 02:45 PM, Axel Lin wrote:
Pass correct gpio argument to gpio_set_value().
The calcualation of gpio = gpio + (gpios-chip * VYBRID_GPIO_COUNT);
is required for calling imx_iomux_gpio_* functions so move them close to
improve readability.
Signed-off-by: Axel Lin axel@ingics.com
---
Hi Bhuvanchandra,
I think current code does not pass correct gpio argument to gpio_set_value()
in vybrid_gpio_direction_output(). It only works if gpios-chip is 0.
I don't have the h/w to test, can you double check this?
gpio_set_value() needs the actual gpio number to be passed not the gpio
offset of gpio chip.
The calculation is for getting the actual gpio number from gpio offset,
which we will need for both imx_iomux_gpio* and gpio_*_* functions.
Tested on Colibri VF50 and VF61 modules.
Thanks,
Axel
drivers/gpio/vybrid_gpio.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/vybrid_gpio.c b/drivers/gpio/vybrid_gpio.c
index 6eaf0a9..33bbf54 100644
--- a/drivers/gpio/vybrid_gpio.c
+++ b/drivers/gpio/vybrid_gpio.c
@@ -36,8 +36,9 @@ static int vybrid_gpio_direction_output(struct udevice *dev,
unsigned gpio,
{
const struct vybrid_gpios *gpios = dev_get_priv(dev);
- gpio = gpio + (gpios-chip * VYBRID_GPIO_COUNT);
gpio_set_value(gpio, value);
+
+ gpio = gpio + (gpios-chip * VYBRID_GPIO_COUNT);
imx_iomux_gpio_set_direction(gpio, VF610_GPIO_DIRECTION_OUT);
return 0;
@@ -54,6 +55,7 @@ static int vybrid_gpio_set_value(struct udevice *dev,
unsigned gpio,
int value)
{
const struct vybrid_gpios *gpios = dev_get_priv(dev);
+
if (value)
writel((1 gpio), gpios-reg-gpio_psor);
else
@@ -68,7 +70,6 @@ static int vybrid_gpio_get_function(struct udevice *dev,
unsigned gpio)
u32 g_state = 0;
gpio = gpio + (gpios-chip * VYBRID_GPIO_COUNT);
-
imx_iomux_gpio_get_function(gpio, g_state);
if (((g_state (0x07 PAD_MUX_MODE_SHIFT)) PAD_MUX_MODE_SHIFT)
0)
Best regards,
Bhuvan
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Re: [U-Boot] [PATCHv4 1/3] driver/ddr/altera: Add DDR driver for Altera's SDRAM controller
Dear Pavel, In message 20150609115532.GA29408@amd you wrote: U-Boot is normally spelled U-Boot. You have two different variants in comments here. Thanks for pointing out. This is actually quite important as U-Boot is _not_ a copyrighted name, while some other spellings are (search for text u-boot at [1]). For example, uboot is a registered trade mark of the uboot.com mobile internet services gmbh in Vienna (who actively pursuit violations). [1] http://www.wipo.int/branddb/en/ Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Given a choice between two theories, take the one which is funnier. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Disabling Autonegotiation
Dear priyanka sharma, please keep the mailinmg list on Cc: In message CAKynAoccK9AwcQrt-ggWRYj5RiTLtnf00+fU71=ymog+8ej...@mail.gmail.com you wrote: Disabling auto negotiation along with limiting ethernet PHY to 100MBit is a part of requirements for a custom solution. This does not actually answer my question. What I'm interested to understand is _why_ you want to do that. As mentioned before, autonegotiation is usually a good thing to have, and mandatory in many cases. If you disable it, you probably want to work around some problem (eventually caused by broken or mis-designed hardware), and depending on the nature of the problem there might be better ways to solve it. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de The question of whether a computer can think is no more interesting than the question of whether a submarine can swim - Edsgar W. Dijkstra ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] arm: imx: Kernel not booting when environment is in QSPI
Hi Matthias, I can not reproduce your issue. All is fine in my side. which version/branch are you using for uboot and linux? mainline or fsl vendor? Regards, Peng. On Tue, Jun 09, 2015 at 10:24:38AM -0500, Nitin Garg wrote: On 06/09/2015 10:02 AM, Fabio Estevam wrote: Adding some FSL folks in case they have some suggestions. Regards, Fabio Estevam On Tue, Jun 9, 2015 at 11:41 AM, Matthias Weißer m.weisse...@gmail.com wrote: Hi I work with an imx6sx sdb. I observed that placing u-boot in QSPI flash and also having the environment in QSPI the linux kernel doesn't boot. The backtrace from the kernel contains 'fsl_qspi_probe'. If only u-boot resides in QSPI and the environment is on mmc then the kernel boots successfully. Some more investigation showed that even when u-boot and the environment is on mmc a simple = sf probe 1:0 causing the kernel not to boot. So I suspect a problem with u-boot not leaving the QSPI hardware in a sane state for the kernel driver to take over control. If no serial flash operations are executed in u-boot I can access the flash in linux via mtd. Kernel and u-boot are both current git HEAD with minor changes. Anyone with an idea? Regards Matthias Kernel output: Starting kernel ... [0.00] Booting Linux on physical CPU 0x0 [0.00] Linux version 4.1.0-rc7-00047-g5879ae5-dirty (mweisser@ldev) (gcc version 4.9.2 (crosstool-NG 1.20.0) ) #2 Tue Jun 9 09:40:49 CEST 2015 [0.00] CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d [0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [0.00] Machine model: Freescale i.MX6 SoloX SDB RevB Board [0.00] cma: Reserved 16 MiB at 0xbf00 [0.00] Memory policy: Data cache writeback [0.00] CPU: All CPU(s) started in SVC mode. [0.00] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 260096 [0.00] Kernel command line: console=ttymxc0,115200 ip=dhcp root=/dev/nfs nfsroot=192.168.1.60:/data/users/mweisser/tgt-fs/linux-fs consoleblank=0 [0.00] PID hash table entries: 4096 (order: 2, 16384 bytes) [0.00] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) [0.00] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) [0.00] Memory: 1006056K/1048576K available (6035K kernel code, 321K rwdata, 1960K rodata, 232K init, 8310K bss, 26136K reserved, 16384K cma-reserved, 0K highmem) [0.00] Virtual kernel memory layout: [0.00] vector : 0x - 0x1000 ( 4 kB) [0.00] fixmap : 0xffc0 - 0xfff0 (3072 kB) [0.00] vmalloc : 0xc080 - 0xff00 (1000 MB) [0.00] lowmem : 0x8000 - 0xc000 (1024 MB) [0.00] pkmap : 0x7fe0 - 0x8000 ( 2 MB) [0.00] modules : 0x7f00 - 0x7fe0 ( 14 MB) [0.00] .text : 0x80008000 - 0x807d7044 (7997 kB) [0.00] .init : 0x807d8000 - 0x80812000 ( 232 kB) [0.00] .data : 0x80812000 - 0x808624e0 ( 322 kB) [0.00].bss : 0x808624e0 - 0x8107ff88 (8311 kB) [0.00] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 [0.00] Running RCU self tests [0.00] NR_IRQS:16 nr_irqs:16 16 [0.00] L2C-310 erratum 769419 enabled [0.00] L2C-310 enabling early BRESP for Cortex-A9 [0.00] L2C-310 full line of zeros enabled for Cortex-A9 [0.00] L2C-310 ID prefetch enabled, offset 1 lines [0.00] L2C-310 dynamic clock gating enabled, standby mode enabled [0.00] L2C-310 cache controller enabled, 16 ways, 256 kB [0.00] L2C-310: CACHE_ID 0x41c8, AUX_CTRL 0x76430001 [0.00] Switching to timer-based delay loop, resolution 333ns [0.07] sched_clock: 32 bits at 3000kHz, resolution 333ns, wraps every 715827882841ns [0.35] clocksource mxc_timer1: mask: 0x max_cycles: 0x, max_idle_ns: 637086815595 ns [0.000888] Console: colour dummy device 80x30 [0.000918] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar [0.000927] ... MAX_LOCKDEP_SUBCLASSES: 8 [0.000934] ... MAX_LOCK_DEPTH: 48 [0.000941] ... MAX_LOCKDEP_KEYS:8191 [0.000948] ... CLASSHASH_SIZE: 4096 [0.000955] ... MAX_LOCKDEP_ENTRIES: 32768 [0.000961] ... MAX_LOCKDEP_CHAINS: 65536 [0.000968] ... CHAINHASH_SIZE: 32768 [0.000975] memory used by lock dependency info: 5167 kB [0.000983] per task-struct memory footprint: 1152 bytes [0.001006] Calibrating delay loop (skipped), value calculated using timer frequency.. 6.00 BogoMIPS (lpj=3) [0.001023] pid_max: default: 32768 minimum: 301 [0.001180] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes) [0.001196] Mountpoint-cache hash
Re: [U-Boot] [PATCH] gpio: vybrid: Use proper parameter name for gpio offset
2015-06-09 22:37 GMT+08:00 Bhuvanchandra DV bhuvanchandra...@toradex.com:
On 06/09/2015 07:54 PM, Axel Lin wrote:
It's confusing to use gpio as gpio offset parameter so rename it to offset
for better readability.
Agreed, but IMHO these offsets any way at the end are the gpio numbers of
individual gpio chip instances. e.g: gpio 2 of gpio chip 1 which is gpio 34.
struct dm_gpio_ops {
int (*request)(struct udevice *dev, unsigned offset, const char *label);
int (*free)(struct udevice *dev, unsigned offset);
int (*direction_input)(struct udevice *dev, unsigned offset);
int (*direction_output)(struct udevice *dev, unsigned offset,
int value);
int (*get_value)(struct udevice *dev, unsigned offset);
int (*set_value)(struct udevice *dev, unsigned offset, int value);
int (*get_function)(struct udevice *dev, unsigned offset);
All the callbacks of struct dm_gpio_ops takes offset rather than gpio number,
had better use offset here.
The gpio numbers of individual gpio chip instances actually means offset, don't
mix it with the actually gpio number.
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[U-Boot] [PATCH 0/3] spi: cadence_qspi: sram depth from DT fix for FIFO width
This patchset adds support to get controller sram size from device tree fix to support different FIFO widths. Vikas Manocha (3): spi: cadence_qspi: move the sram partition in init spi: cadence_qspi: get sram size from device tree spi: cadence_qspi: support FIFO width other than 4 bytes arch/arm/dts/socfpga.dtsi |1 + arch/arm/dts/stv0991.dts |1 + drivers/spi/cadence_qspi.c |1 + drivers/spi/cadence_qspi.h |1 + drivers/spi/cadence_qspi_apb.c | 63 +--- 5 files changed, 31 insertions(+), 36 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] spi: cadence_qspi: move the sram partition in init
There is no need to re-configure sram partition for every read/write for better full use of sram for read or write. This patch divides the half sram for read half for write once at initialization. Signed-off-by: Vikas Manocha vikas.mano...@st.com --- drivers/spi/cadence_qspi_apb.c | 16 +--- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 855e5c7..1924f3b 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -38,10 +38,7 @@ /* Controller sram size in word */ #define CQSPI_REG_SRAM_SIZE_WORD (128) -#define CQSPI_REG_SRAM_RESV_WORDS (2) -#define CQSPI_REG_SRAM_PARTITION_WR(1) -#define CQSPI_REG_SRAM_PARTITION_RD\ - (CQSPI_REG_SRAM_SIZE_WORD - CQSPI_REG_SRAM_RESV_WORDS) +#define CQSPI_REG_SRAM_PARTITION_RD(CQSPI_REG_SRAM_SIZE_WORD/2) #define CQSPI_REG_SRAM_THRESHOLD_WORDS (50) /* Transfer mode */ @@ -537,6 +534,10 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat) /* Configure the remap address register, no remap */ writel(0, plat-regbase + CQSPI_REG_REMAP); + /* Indirect mode configurations */ + writel(CQSPI_REG_SRAM_PARTITION_RD, + plat-regbase + CQSPI_REG_SRAMPARTITION); + /* Disable all interrupts */ writel(0, plat-regbase + CQSPI_REG_IRQMASK); @@ -698,10 +699,6 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, /* Setup the indirect trigger address */ writel((u32)plat-ahbbase, plat-regbase + CQSPI_REG_INDIRECTTRIGGER); - /* Configure SRAM partition for read. */ - writel(CQSPI_REG_SRAM_PARTITION_RD, plat-regbase + - CQSPI_REG_SRAMPARTITION); - /* Configure the opcode */ rd_reg = cmdbuf[0] CQSPI_REG_RD_INSTR_OPCODE_LSB; @@ -798,9 +795,6 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, /* Setup the indirect trigger address */ writel((u32)plat-ahbbase, plat-regbase + CQSPI_REG_INDIRECTTRIGGER); - writel(CQSPI_REG_SRAM_PARTITION_WR, - plat-regbase + CQSPI_REG_SRAMPARTITION); - /* Configure the opcode */ reg = cmdbuf[0] CQSPI_REG_WR_INSTR_OPCODE_LSB; writel(reg, plat-regbase + CQSPI_REG_WR_INSTR); -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] spi: cadence_qspi: get sram size from device tree
sram size could be different on different socs, e.g. on stv0991 it is 256 while
on altera platform it is 128. It is better to receive it from device tree.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
arch/arm/dts/socfpga.dtsi |1 +
arch/arm/dts/stv0991.dts |1 +
drivers/spi/cadence_qspi.c |1 +
drivers/spi/cadence_qspi.h |1 +
drivers/spi/cadence_qspi_apb.c |6 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index bf791c5..9b12420 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -639,6 +639,7 @@
ext-decoder = 0; /* external decoder */
num-cs = 4;
fifo-depth = 128;
+ sram-size = 128;
bus-num = 2;
status = disabled;
};
diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts
index 3b1efca..556df82 100644
--- a/arch/arm/dts/stv0991.dts
+++ b/arch/arm/dts/stv0991.dts
@@ -35,6 +35,7 @@
ext-decoder = 0; /* external decoder */
num-cs = 4;
fifo-depth = 256;
+ sram-size = 256;
bus-num = 0;
status = okay;
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index a75fc46..34a0f46 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -309,6 +309,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice
*bus)
plat-tsd2d_ns = fdtdec_get_int(blob, subnode, tsd2d-ns, 255);
plat-tchsh_ns = fdtdec_get_int(blob, subnode, tchsh-ns, 20);
plat-tslch_ns = fdtdec_get_int(blob, subnode, tslch-ns, 20);
+ plat-sram_size = fdtdec_get_int(blob, node, sram-size, 128);
debug(%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n,
__func__, plat-regbase, plat-ahbbase, plat-max_hz,
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index c9a6142..98e57aa 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -25,6 +25,7 @@ struct cadence_spi_platdata {
u32 tsd2d_ns;
u32 tchsh_ns;
u32 tslch_ns;
+ u32 sram_size;
};
struct cadence_spi_priv {
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 1924f3b..5831905 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -36,9 +36,6 @@
#define CQSPI_FIFO_WIDTH (4)
-/* Controller sram size in word */
-#define CQSPI_REG_SRAM_SIZE_WORD (128)
-#define CQSPI_REG_SRAM_PARTITION_RD(CQSPI_REG_SRAM_SIZE_WORD/2)
#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)
/* Transfer mode */
@@ -535,8 +532,7 @@ void cadence_qspi_apb_controller_init(struct
cadence_spi_platdata *plat)
writel(0, plat-regbase + CQSPI_REG_REMAP);
/* Indirect mode configurations */
- writel(CQSPI_REG_SRAM_PARTITION_RD,
- plat-regbase + CQSPI_REG_SRAMPARTITION);
+ writel((plat-sram_size/2), plat-regbase + CQSPI_REG_SRAMPARTITION);
/* Disable all interrupts */
writel(0, plat-regbase + CQSPI_REG_IRQMASK);
--
1.7.9.5
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[U-Boot] [PATCH 3/3] spi: cadence_qspi: support FIFO width other than 4 bytes
This patch makes the code compatible with FIFO depths other than 4
bytes. It also simplify read/write FIFO loops.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
---
drivers/spi/cadence_qspi_apb.c | 47
1 file changed, 24 insertions(+), 23 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 5831905..a168912 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -199,18 +199,16 @@ static void cadence_qspi_apb_read_fifo_data(void *dest,
unsigned int *dest_ptr = (unsigned int *)dest;
unsigned int *src_ptr = (unsigned int *)src_ahb_addr;
- while (remaining 0) {
- if (remaining = CQSPI_FIFO_WIDTH) {
- *dest_ptr = readl(src_ptr);
- remaining -= CQSPI_FIFO_WIDTH;
- } else {
- /* dangling bytes */
- temp = readl(src_ptr);
- memcpy(dest_ptr, temp, remaining);
- break;
- }
+ while (remaining = sizeof(dest_ptr)) {
+ *dest_ptr = readl(src_ptr);
+ remaining -= sizeof(src_ptr);
dest_ptr++;
}
+ if (remaining) {
+ /* dangling bytes */
+ temp = readl(src_ptr);
+ memcpy(dest_ptr, temp, remaining);
+ }
return;
}
@@ -218,24 +216,27 @@ static void cadence_qspi_apb_read_fifo_data(void *dest,
static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
const void *src, unsigned int bytes)
{
- unsigned int temp;
+ unsigned int temp=0;
+ int i;
int remaining = bytes;
unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
unsigned int *src_ptr = (unsigned int *)src;
- while (remaining 0) {
- if (remaining = CQSPI_FIFO_WIDTH) {
- writel(*src_ptr, dest_ptr);
- remaining -= sizeof(unsigned int);
- } else {
- /* dangling bytes */
- memcpy(temp, src_ptr, remaining);
- writel(temp, dest_ptr);
- break;
- }
- src_ptr++;
+ while (remaining = CQSPI_FIFO_WIDTH) {
+ for (i = CQSPI_FIFO_WIDTH/sizeof(src_ptr) - 1; i = 0; i--)
+ writel(*(src_ptr+i), dest_ptr+i);
+ src_ptr += CQSPI_FIFO_WIDTH/sizeof(src_ptr);
+ remaining -= CQSPI_FIFO_WIDTH;
+ }
+ if (remaining)
+ {
+ /* dangling bytes */
+ i = remaining/sizeof(dest_ptr);
+ memcpy(temp, src_ptr+i, remaining % sizeof(dest_ptr));
+ writel(temp, dest_ptr+i);
+ for (--i; i = 0; i--)
+ writel(*(src_ptr+i), dest_ptr+i);
}
-
return;
}
--
1.7.9.5
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Re: [U-Boot] [PATCH RFT] gpio: vybrid: Fix up setting output value in vybrid_gpio_direction_output
On 06/09/2015 06:49 PM, Axel Lin wrote: 2015-06-09 20:58 GMT+08:00 Bhuvanchandra DV bhuvanchandra...@toradex.com: Hello Axel, On 06/09/2015 02:45 PM, Axel Lin wrote: Pass correct gpio argument to gpio_set_value(). The calcualation of gpio = gpio + (gpios-chip * VYBRID_GPIO_COUNT); is required for calling imx_iomux_gpio_* functions so move them close to improve readability. Signed-off-by: Axel Lin axel@ingics.com --- Hi Bhuvanchandra, I think current code does not pass correct gpio argument to gpio_set_value() in vybrid_gpio_direction_output(). It only works if gpios-chip is 0. I don't have the h/w to test, can you double check this? gpio_set_value() needs the actual gpio number to be passed not the gpio offset of gpio chip. Are you sure? Please take a look at gpio_get_value()/gpio_set_value() implement in drivers/gpio/gpio-uclass.c. Yes, Toggling GPIO_34 = GPIO_01 2nd instance, with debug prints: Colibri VFxx # gpio toggle 34 DEBUG: gpio_to_device: gpio: 34 DEBUG: gpio_to_device: desc_offset: 2 DEBUG: gpio_to_device: gpio: 34 DEBUG: gpio_to_device: desc_offset: 2 DEBUG: gpio_to_device: gpio: 34 DEBUG: gpio_to_device: desc_offset: 2 DEBUG: vybrid_gpio_direction_output: gpio(before calculation): 2 DEBUG: vybrid_gpio_direction_output: gpio(after calculation): 34 DEBUG: gpio_set_value: gpio: 34 DEBUG: gpio_to_device: gpio: 34 DEBUG: gpio_to_device: desc_offset: 2 DEBUG: dm_gpio_set_value: gpio_offset: 2 gpio: pin 34 (gpio 34) value is 0 DEBUG: gpio_to_device: gpio: 34 DEBUG: gpio_to_device: desc_offset: 2 Colibri VFxx # gpio toggle 34 DEBUG: gpio_to_device: gpio: 34 DEBUG: gpio_to_device: desc_offset: 2 DEBUG: gpio_to_device: gpio: 34 DEBUG: gpio_to_device: desc_offset: 2 DEBUG: gpio_to_device: gpio: 34 DEBUG: gpio_to_device: desc_offset: 2 DEBUG: vybrid_gpio_direction_output: gpio(before calculation): 2 DEBUG: vybrid_gpio_direction_output: gpio(after calculation): 34 DEBUG: gpio_set_value: gpio: 34 DEBUG: gpio_to_device: gpio: 34 DEBUG: gpio_to_device: desc_offset: 2 DEBUG: dm_gpio_set_value: desc_offset: 2 gpio: pin 34 (gpio 34) value is 1 DEBUG: gpio_to_device: gpio: 34 DEBUG: gpio_to_device: desc_offset: 2 Best regards, Bhuvan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] odroid: dts: cleanup of MAX77686 regulators
On 19/05/15 00:56, Przemyslaw Marczak wrote: This commit cleanup MAX77686 regulator node by: - remove the sub-nodes of unconnected regulators - remove the regulator-compatible properties of all regulators This prevents printing init errors for the regulators, with duplicated name strings. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Minkyu Kang mk7.k...@samsung.com --- arch/arm/dts/exynos4412-odroid.dts | 80 +- 1 file changed, 2 insertions(+), 78 deletions(-) applied to u-boot-samsung. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] arm: imx: Kernel not booting when environment is in QSPI
Hi Peng I use mainline (current HEAD, u-boot 2015.07-rc2, linux 4.1.0-rc7) on both sides. Regards Matthias 2015-06-10 3:45 GMT+02:00 Peng Fan b51...@freescale.com: Hi Matthias, I can not reproduce your issue. All is fine in my side. which version/branch are you using for uboot and linux? mainline or fsl vendor? Regards, Peng. On Tue, Jun 09, 2015 at 10:24:38AM -0500, Nitin Garg wrote: On 06/09/2015 10:02 AM, Fabio Estevam wrote: Adding some FSL folks in case they have some suggestions. Regards, Fabio Estevam On Tue, Jun 9, 2015 at 11:41 AM, Matthias Weißer m.weisse...@gmail.com wrote: Hi I work with an imx6sx sdb. I observed that placing u-boot in QSPI flash and also having the environment in QSPI the linux kernel doesn't boot. The backtrace from the kernel contains 'fsl_qspi_probe'. If only u-boot resides in QSPI and the environment is on mmc then the kernel boots successfully. Some more investigation showed that even when u-boot and the environment is on mmc a simple = sf probe 1:0 causing the kernel not to boot. So I suspect a problem with u-boot not leaving the QSPI hardware in a sane state for the kernel driver to take over control. If no serial flash operations are executed in u-boot I can access the flash in linux via mtd. Kernel and u-boot are both current git HEAD with minor changes. Anyone with an idea? Regards Matthias Kernel output: Starting kernel ... [0.00] Booting Linux on physical CPU 0x0 [0.00] Linux version 4.1.0-rc7-00047-g5879ae5-dirty (mweisser@ldev) (gcc version 4.9.2 (crosstool-NG 1.20.0) ) #2 Tue Jun 9 09:40:49 CEST 2015 [0.00] CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d [0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [0.00] Machine model: Freescale i.MX6 SoloX SDB RevB Board [0.00] cma: Reserved 16 MiB at 0xbf00 [0.00] Memory policy: Data cache writeback [0.00] CPU: All CPU(s) started in SVC mode. [0.00] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 260096 [0.00] Kernel command line: console=ttymxc0,115200 ip=dhcp root=/dev/nfs nfsroot=192.168.1.60:/data/users/mweisser/tgt-fs/linux-fs consoleblank=0 [0.00] PID hash table entries: 4096 (order: 2, 16384 bytes) [0.00] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) [0.00] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) [0.00] Memory: 1006056K/1048576K available (6035K kernel code, 321K rwdata, 1960K rodata, 232K init, 8310K bss, 26136K reserved, 16384K cma-reserved, 0K highmem) [0.00] Virtual kernel memory layout: [0.00] vector : 0x - 0x1000 ( 4 kB) [0.00] fixmap : 0xffc0 - 0xfff0 (3072 kB) [0.00] vmalloc : 0xc080 - 0xff00 (1000 MB) [0.00] lowmem : 0x8000 - 0xc000 (1024 MB) [0.00] pkmap : 0x7fe0 - 0x8000 ( 2 MB) [0.00] modules : 0x7f00 - 0x7fe0 ( 14 MB) [0.00] .text : 0x80008000 - 0x807d7044 (7997 kB) [0.00] .init : 0x807d8000 - 0x80812000 ( 232 kB) [0.00] .data : 0x80812000 - 0x808624e0 ( 322 kB) [0.00].bss : 0x808624e0 - 0x8107ff88 (8311 kB) [0.00] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 [0.00] Running RCU self tests [0.00] NR_IRQS:16 nr_irqs:16 16 [0.00] L2C-310 erratum 769419 enabled [0.00] L2C-310 enabling early BRESP for Cortex-A9 [0.00] L2C-310 full line of zeros enabled for Cortex-A9 [0.00] L2C-310 ID prefetch enabled, offset 1 lines [0.00] L2C-310 dynamic clock gating enabled, standby mode enabled [0.00] L2C-310 cache controller enabled, 16 ways, 256 kB [0.00] L2C-310: CACHE_ID 0x41c8, AUX_CTRL 0x76430001 [0.00] Switching to timer-based delay loop, resolution 333ns [0.07] sched_clock: 32 bits at 3000kHz, resolution 333ns, wraps every 715827882841ns [0.35] clocksource mxc_timer1: mask: 0x max_cycles: 0x, max_idle_ns: 637086815595 ns [0.000888] Console: colour dummy device 80x30 [0.000918] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar [0.000927] ... MAX_LOCKDEP_SUBCLASSES: 8 [0.000934] ... MAX_LOCK_DEPTH: 48 [0.000941] ... MAX_LOCKDEP_KEYS:8191 [0.000948] ... CLASSHASH_SIZE: 4096 [0.000955] ... MAX_LOCKDEP_ENTRIES: 32768 [0.000961] ... MAX_LOCKDEP_CHAINS: 65536 [0.000968] ... CHAINHASH_SIZE: 32768 [0.000975] memory used by lock dependency info: 5167 kB [0.000983] per task-struct memory footprint: 1152 bytes [0.001006] Calibrating delay loop (skipped), value calculated using timer frequency.. 6.00 BogoMIPS
Re: [U-Boot] [PATCH RFT] gpio: vybrid: Fix up setting output value in vybrid_gpio_direction_output
2015-06-09 20:58 GMT+08:00 Bhuvanchandra DV bhuvanchandra...@toradex.com: Hello Axel, On 06/09/2015 02:45 PM, Axel Lin wrote: Pass correct gpio argument to gpio_set_value(). The calcualation of gpio = gpio + (gpios-chip * VYBRID_GPIO_COUNT); is required for calling imx_iomux_gpio_* functions so move them close to improve readability. Signed-off-by: Axel Lin axel@ingics.com --- Hi Bhuvanchandra, I think current code does not pass correct gpio argument to gpio_set_value() in vybrid_gpio_direction_output(). It only works if gpios-chip is 0. I don't have the h/w to test, can you double check this? gpio_set_value() needs the actual gpio number to be passed not the gpio offset of gpio chip. Are you sure? Please take a look at gpio_get_value()/gpio_set_value() implement in drivers/gpio/gpio-uclass.c. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] thermal:imx_thermal: enter busywait cooling loop when over max CPU temp
Remove the check for temperature being within the min/max range and enter the
busywait cooling loop whenever the CPU temperature is over the critical temp.
This fixes the issue where if a board was booted at a temp greater than
the CPU temperature max, it would skip the loop and never indicate or try
to address the overtemp issue.
Cc: Ye Li b37...@freescale.com
Cc: Jason Liu r64...@freescale.com
Signed-off-by: Tim Harvey thar...@gateworks.com
---
drivers/thermal/imx_thermal.c | 16 ++--
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index 0d893c9..42ca8d0 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -130,16 +130,12 @@ int imx_thermal_get_temp(struct udevice *dev, int *temp)
int cpu_tmp = 0;
cpu_tmp = read_cpu_temperature(dev);
- while (cpu_tmp priv-minc cpu_tmp priv-maxc) {
- if (cpu_tmp = priv-critical) {
- printf(CPU Temperature (%dC) too close to max (%dC),
- cpu_tmp, priv-maxc);
- puts( waiting...\n);
- udelay(500);
- cpu_tmp = read_cpu_temperature(dev);
- } else {
- break;
- }
+ while (cpu_tmp = priv-critical) {
+ printf(CPU Temperature (%dC) too close to max (%dC),
+ cpu_tmp, priv-maxc);
+ puts( waiting...\n);
+ udelay(500);
+ cpu_tmp = read_cpu_temperature(dev);
}
*temp = cpu_tmp;
--
1.9.1
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Re: [U-Boot] [PATCH v2 1/3] ARM: cache: add an empty stub function for invalidate/flush dcache
On Tue, Jun 09, 2015 at 11:54:14AM +0800, Josh Wu wrote: Hi, Tom On 6/8/2015 9:20 PM, Tom Rini wrote: On Mon, Jun 08, 2015 at 10:26:29AM +0200, Marek Vasut wrote: On Monday, June 08, 2015 at 04:05:04 AM, Josh Wu wrote: Hi, Marek On 6/5/2015 9:18 PM, Marek Vasut wrote: On Friday, June 05, 2015 at 09:47:30 AM, Josh Wu wrote: Since some driver like ohci, lcd used dcache functions. But some ARM cpu don't implement the invalidate_dcache_range()/flush_dcache_range() functions. To avoid compiling errors this patch adds an weak empty stub function for all ARM cpu. And each cpu can implement its own implementation. If not implemented by default it will use an empty function. Signed-off-by: Josh Wu josh...@atmel.com --- Changes in v2: new added arch/arm/lib/cache.c | 9 + 1 file changed, 9 insertions(+) So, why exactly can't this be entirely common code , but a CPU-specific code ? :) Do you mean to make those empty functions as common code for all arch cpu to use? Yes. It seems there is no place to put common code for all arch cpu. Isn't that what the common/ directory is for ? ;-) No, this is making something common for the sake of making it common rather than good architecutre of the code I think. We aren't going to share real cache functions just these dummy ones. So it is the right place: arch/arm/lib/cache.c to put the dummy cache function. Yes. We may re-evaluate our dummy ones at some point in the future when people try and use some particular combination harder, see for example the PowerPC dummy cache functions we just recently dropped. Thanks! If this patch set are ok for you. I will sent more patches to drop the dummy cache functions in arch/cpu/ folders. Right, that's the best palce I think, baring an existing arch having a location for weak cache functions already (like arm does). Also the flush_cache() in arch/arm/lib/cache.c can be dropped and just call flush_dcache_range() as the ARM1136, ARM926ejs alreay implemented their own flush_cache(). Nope, other things fail if you do that (vpac270_nor_256 and 24 others at least so far in my test build). -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Kconfiglib updates
Hello, I've done lots of internal cleanup and optimization and fixed a few small bugs/incompatibilities in https://github.com/ulfalizer/Kconfiglib: - Unset user values when loading a zero-byte .config. (5e54e2c) - Ignore indented .config assignments. (f8a7510) - Do not require $srctree to be set for non-kernel projects. (d56e9c1) Python 3 is supported now as well. It should be a quick copy-paste (+ add back header) update. Just to be paranoid, I verified that genboardscfg.py generates an identical boards.cfg with the new version. Seems to be slightly faster too, though I guess it's fast enough already. :) https://github.com/ulfalizer/Kconfiglib/commit/d56e9c1d4c3e6f560382ac71fa2419b2a9bef1cb has a summary of the last bug. No need to set $srctree in genboardscfg.py now if it isn't referenced in the Kconfigs, but doing self._conf = kconfiglib.Config(base_dir = .) would be safest if the base directory should always be the current directory regardless of the value of $srctree. The special $srctree handling is to get alternative kernel build directories working with minimal fuss. I haven't run into the first two bugs in the wild by the way. Cheers, Ulf ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Compilation of env error u-boot 2015.07-rc2
Hi all, I have pulled latest code from u-boot main line through git. Using linaro tool chain for am335x board I'm trying to compile tools/env but its giving an error #make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- env HOSTCC tools/env/fw_env.o arm-linux-gnueabihf/include/search.h:173:1 erro: expected '}' before 'NETARGS' make[1]: *** [ tools/env/few.env.o] error 1 With same tool chain I'm able compile 2014 u-boot Regards, Thiru N ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/8] omap-common: Common boot code OMAP3 support and SYS_BOOT-based fallback boot device
On Tuesday, June 09, 2015 at 06:28:29 PM, Pali Rohár wrote: On Monday 08 June 2015 23:24:18 Paul Kocialkowski wrote: I would be very glad to see board maintainers give a go at the changeset before it gets merged, especially on devices like the Nokia RX-51 (N900) where some specific adaptation was needed. So U-Boot is broken since e11c6c279d823dc0d2f470c5c2e3c0a9854a640f (see other email thread Would be nice if you added a link to the thread in some mail archive ... ). Until somebody fix that broken commit, I cannot test your new patches in qemu or on (real) Nokia N900. What about you fixing it ? ;-) Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
