Re: [U-Boot] [PATCH v6 00/10] add support for atheros ath79 based SOCs

[Wills Wang]

On Saturday, January 16, 2016 01:26 PM, Marek Vasut wrote:

On Monday, January 04, 2016 at 12:06:17 PM, Wills Wang wrote:

These series of patch add support for atheros ath79 based SOCs in u-boot,
at the present moment it's just available for ar933x and qca953x chip.

Changes in v6:
- Remove useless "else"
- Move ar933x as separate patch
- Add get_bootstrap in reset.c
- Use map_physmem instead of KSEG1ADDR
- Add arch_cpu_init for detect SOC type for early
- Define magic value in ddr.c
- Remove wait loop in putc and getc
- Use map_physmem instead of KSEG1ADDR
- Add rrw_delay in ath79_spi_priv for more accurate timing
- Remove ath79_spi_delay
- Calculate delay in ath79_spi_set_speed
- Convert SZ_XXX into hex in ap121.h
- Remove useless CONFIG_SYS_INIT_SP_OFFSET in ap121.h
- Add board_early_init_f for DDR and pin initialization
- Select UART and SPI in ap121_defconfig
- Add support for qca953x

I wanted to try this patchset, so I picked [1], since I didn't feel like fishing
out patches from the list. Especially since this wasn't sent as a series, but as
separate patches, which makes things annoying.

The [1] does not even compile, which is surprising. I would expect that if you
submit patches, you would at least compile-test them. Sigh. I needed this patch:

---8<---
diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c
index 2952679..140c65c 100644
--- a/arch/mips/mach-ath79/cpu.c
+++ b/arch/mips/mach-ath79/cpu.c
@@ -9,8 +9,8 @@
  #include 
  #include 
  #include 
-#include 
-#include 
+#include 
+#include 
  
  struct ath79_soc_desc {

 enum ath79_soc_type soc;
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index 410b900..fe32d80 100644
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -9,7 +9,7 @@
  #include 
  #include 
  #include 
-#include 
+#include 
  #include 
   
  void _machine_restart(void)

--->8---
Marek, you can try my repository at 
https://github.com/willswang/u-boot-ath79,

I have fixed the compiling issue about headers.
I'm very sorry about this compiling error, my work tree have a residual 
symbol
link between arch/mips/include/asm/arch and 
arch/mips/mach-ath79/include/mach.
it was not removed when i executed "make clean" to rebuild,  so, my 
compiling
didn't discover this problem before this. now i clone this remote branch 
into a new

location and find this issue.

Once I managed to fix things, I compiled ap121. I tried booting it on arduino
yun (ar9331), but it hung in start.S in setup_c0_status . If I comment this
out, it hangs in lowlevel_init, right at the beginning. That's where I gave up.

[1] http://git.denx.de/?p=u-boot/u-boot-
mips.git;a=shortlog;h=refs/heads/mips_ath79_v6

Best regards,
Marek Vasut


--
Best Regards
Wills

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Re: [U-Boot] x86: Bay Trail support with W83627DHG

[Bin Meng]

Hi Stefan,

On Fri, Jan 15, 2016 at 10:37 PM, Stefan Roese  wrote:
> Hi Simon, Hi Bin!
>
> I'm currently busy with porting U-Boot to a Bay Trail board.
> Equipped with an Intel Atom E3845 and additionally the
> Nuvoton / Winbond W83627DHG Super IO chip.
>
> My staring point for this port is the Minnowboard MAX, which
> works very well btw. I've used the same binaries as described
> in the README.x86 as on the MinnowMAX for this new Bay Trail
> board. But am not able yet to see any output on the DEBUG_UART.
>
> Bin, you already mentioned in a previous mail, that I need to
> enable the legacy UART in the Super IO chip for this. I've
> started adding a small driver for this, similar to the one
> you've introduced for the SMSC:

Ah, looks I delivered inaccurate information before! I just remember
BayTrail SoC integrates a legacy UART at I/O 0x3f8 and it is enabled
by FSP by default. If you use a debug version of FSP (only gold4
release provides a debug version FSP), you will se lots of useful
debug information printed on the serial port (the one connected to the
SoC legacy UART). But, why does your board have an additional Nuvoton
/ Winbond W83627DHG Super IO chip? I guess it's for other legacy
peripherals like 8042 KBC, etc? We need figure out the serial port you
are trying to enable is connected to which chip. If it is connected
directly to BayTrail SoC, then you don't need program this W83627DHG.

>
> --<
> #define WINBOND_ENTRY_KEY   0x87
> #define WINBOND_EXIT_KEY0xAA
>
> /* Enable configuration: pass entry key '0x87' into index port dev. */
> static void pnp_enter_conf_state(u16 dev)
> {
> u16 port = dev >> 8;
>
> outb(WINBOND_ENTRY_KEY, port);
> outb(WINBOND_ENTRY_KEY, port);
> }
>
> /* Disable configuration: pass exit key '0xAA' into index port dev. */
> static void pnp_exit_conf_state(u16 dev)
> {
> u16 port = dev >> 8;
>
> outb(WINBOND_EXIT_KEY, port);
> }
>
> /* Bring up early serial debugging output before the RAM is initialized. */
> void winbond_enable_serial(uint dev, uint iobase, uint irq)
> {
> pnp_enter_conf_state(dev);
> pnp_set_logical_device(dev);
> pnp_set_enable(dev, 0);
> pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
> pnp_set_irq(dev, PNP_IDX_IRQ0, irq);
> pnp_set_enable(dev, 1);
> pnp_exit_conf_state(dev);
> }
> --<
>
> This is called via:
> --<
> /* I/O address of Winbond Super IO chip */
> #define WINBOND_IO_PORT 0x2e
>

If the serial port is connected to winbond, we need make sure this I/O
port 0x2e is correct. Normally the chipset will have several optional
addresses, and which one is used is determined by some strap pins.

> /* Logical device number */
> #define W83627DHG_SP1   2   /* Com1 */
>
> winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1),
>   UART0_BASE, UART0_IRQ);
> --<
>
> As you may notice, this is ported from coreboot. But still, this
> is not enough to get some output on the UART.
>
> Debugging (without JTAG debugger and without DEBUG_UART but with
> POST output) shows, that the board hangs somewhere in the FSP code.
> When called via fsp_init(). POST shows 0x2A in this case. And
> FSP does not return to fsp_continue() at all.
>

0x2A seems to be a U-Boot postcode.

> Do you have any hints what could be missing for the DEBUG
> UART to work on this board? Or what might cause the board
> to hang in the FSP code? Or what the meaning of the FSP 0x2A
> POST code is?
>

If the fsp_init() never returns, the most suspectable one is DDR
initialization failure. If it's a memory-down configuration, you may
need check the DDR chipset datasheet and fill in correct values in the
device tree file.

Regards,
Bin
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Re: [U-Boot] [PATCH 3/4] x86: qemu: add the ability to load and link ACPI tables from QEMU

[Bin Meng]

Hi Miao,

On Fri, Jan 15, 2016 at 11:12 AM, Miao Yan  wrote:
> This patch adds the ability to load and link ACPI tables provided by QEMU.
> QEMU tells guests how to load and patch ACPI tables through its fw_cfg
> interface, by adding a firmware file 'etc/table-loader'. Guests are
> supposed to parse this file and execute corresponding QEMU commands.
>
> Signed-off-by: Miao Yan 
> ---
>  arch/x86/cpu/qemu/fw_cfg.c| 214 
> ++
>  arch/x86/include/asm/fw_cfg.h |  70 ++
>  2 files changed, 284 insertions(+)
>
> diff --git a/arch/x86/cpu/qemu/fw_cfg.c b/arch/x86/cpu/qemu/fw_cfg.c
> index b22026c..755676c 100644
> --- a/arch/x86/cpu/qemu/fw_cfg.c
> +++ b/arch/x86/cpu/qemu/fw_cfg.c
> @@ -10,7 +10,10 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
>  #include 
> +#include 
>
>  static bool fwcfg_present;
>  static bool fwcfg_dma_present;
> @@ -202,6 +205,217 @@ err:
> return -ENOMEM;
>  }
>
> +static struct fw_file *qemu_fwcfg_find_file(const char *name)
> +{
> +   struct list_head *entry;
> +   struct fw_file *file;
> +
> +   list_for_each(entry, _list) {
> +   file = list_entry(entry, struct fw_file, list);
> +   if (!strcmp(file->cfg.name, name))
> +   return file;
> +   }
> +
> +   return NULL;
> +}
> +
> +static int bios_linker_allocate(struct bios_linker_entry *entry,
> +  unsigned long *addr)

Please add a comment block for what this function is doing, its
parameters, return value, etc. Please do the same for the other 2
functions below.

> +{
> +   uint32_t size, align;
> +   struct fw_file *file;
> +   unsigned long aligned_addr;
> +
> +   align = le32_to_cpu(entry->alloc.align);
> +   /* align must be power of 2 */
> +   if (align & (align - 1)) {
> +   printf("error: wrong alignment %u\n", align);
> +   return -EINVAL;
> +   }
> +
> +   file = qemu_fwcfg_find_file(entry->alloc.file);
> +   if (!file) {
> +   printf("error: can't find file %s\n", entry->alloc.file);
> +   return -ENOENT;
> +   }
> +
> +   size = be32_to_cpu(file->cfg.size);
> +
> +   /*
> +* ZONE_HIGH means we need to allocate from high memory, since
> +* malloc space is already at the end of RAM, so we directly use it.
> +* If allocation zone is ZONE_FSEG, then we use the 'addr' passed
> +* in which is low memory
> +*/
> +   if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) {
> +   aligned_addr = (unsigned long)memalign(align, size);
> +   } else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) {
> +   aligned_addr = ALIGN(*addr, align);
> +   } else {
> +   printf("error: invalid allocation zone\n");
> +   return -EINVAL;
> +   }
> +
> +   debug("bios_linker_allocate: allocate file %s, size %u, zone %d, 
> align %u, addr 0x%lx\n",
> + file->cfg.name, size, entry->alloc.zone, align, aligned_addr);
> +
> +   qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
> + size, (void *)aligned_addr);
> +   file->addr = aligned_addr;
> +
> +   /* adjust address for low memory allocation */
> +   if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG)
> +   *addr = (aligned_addr + size);
> +
> +   return 0;
> +}
> +
> +static int bios_linker_add_pointer(struct bios_linker_entry *entry)
> +{
> +   struct fw_file *dest, *src;
> +   uint32_t offset = le32_to_cpu(entry->pointer.offset);
> +   uint64_t pointer = 0;
> +
> +   dest = qemu_fwcfg_find_file(entry->pointer.dest_file);
> +   if (!dest || !dest->addr)
> +   return -ENOENT;
> +   src = qemu_fwcfg_find_file(entry->pointer.src_file);
> +   if (!src || !src->addr)
> +   return -ENOENT;
> +

Remove one blank line here.

> +
> +   memcpy(, (char *)dest->addr + offset, entry->pointer.size);
> +   pointer = le64_to_cpu(pointer);
> +

Remove one blank line here.

> +
> +   debug("bios_linker_add_pointer: dest->addr 0x%lx, src->addr 0x%lx, 
> offset 0x%x size %u, 0x%llx\n",
> + dest->addr, src->addr, offset, entry->pointer.size, pointer);
> +
> +   pointer += (unsigned long)src->addr;
> +   pointer = cpu_to_le64(pointer);
> +   memcpy((char *)dest->addr + offset, , entry->pointer.size);
> +
> +   return 0;
> +}
> +
> +static int bios_linker_add_checksum(struct bios_linker_entry *entry)
> +{
> +   struct fw_file *file;
> +   uint8_t *data, cksum = 0;
> +   uint8_t *cksum_start;
> +
> +   file = qemu_fwcfg_find_file(entry->cksum.file);
> +   if (!file || !file->addr)
> +   return -ENOENT;
> +
> +   data = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.offset));
> + 

Re: [U-Boot] [PATCH 2/4] x86: qemu: setup PM IO base for ACPI in southbridge

[Bin Meng]

Hi Miao,

On Fri, Jan 15, 2016 at 11:12 AM, Miao Yan  wrote:
> Enable ACPI IO space for piix4 (for pc board) and ich9 (for q35 board)
>
> Signed-off-by: Miao Yan 
> ---
>  arch/x86/cpu/qemu/qemu.c| 39 
> +
>  arch/x86/include/asm/arch-qemu/device.h |  8 +++
>  2 files changed, 47 insertions(+)
>
> diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
> index 46111c9..e7d8a6c 100644
> --- a/arch/x86/cpu/qemu/qemu.c
> +++ b/arch/x86/cpu/qemu/qemu.c
> @@ -15,6 +15,41 @@
>
>  static bool i440fx;
>
> +static void enable_pm_piix(void)
> +{
> +   u8 en;
> +   u16 device, cmd;
> +
> +   device = x86_pci_read_config16(PIIX_PM, PCI_DEVICE_ID);
> +   if (device != PCI_DEVICE_ID_INTEL_82371AB_3)
> +   return;

Guess the check is already covered in qemu_chipset_init().

> +
> +   /* Set the PM I/O base. */

nits: please remove the ending period. Please fix this globally in this file.

> +   x86_pci_write_config32(PIIX_PM, PMBA, DEFAULT_PMBASE | 1);
> +
> +   /* Enable access to the PM I/O space. */
> +   cmd = x86_pci_read_config16(PIIX_PM, PCI_COMMAND);
> +   cmd |= PCI_COMMAND_IO;
> +   x86_pci_write_config16(PIIX_PM, PCI_COMMAND, cmd);
> +
> +   /* PM I/O Space Enable (PMIOSE). */
> +   en = x86_pci_read_config8(PIIX_PM, PMREGMISC);
> +   en |= PMIOSE;
> +   x86_pci_write_config8(PIIX_PM, PMREGMISC, en);
> +}
> +
> +static void enable_pm_ich9(void)
> +{
> +   u16 device;
> +
> +   device = x86_pci_read_config16(ICH9_PM, PCI_DEVICE_ID);
> +   if (device != PCI_DEVICE_ID_INTEL_ICH9_8)
> +   return;

Guess the check is already covered in qemu_chipset_init().

> +
> +   /* Set the PM I/O base. */
> +   x86_pci_write_config32(ICH9_PM, PMBA, DEFAULT_PMBASE | 1);
> +}
> +
>  static void qemu_chipset_init(void)
>  {
> u16 device, xbcs;
> @@ -53,10 +88,14 @@ static void qemu_chipset_init(void)
> xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
> xbcs |= APIC_EN;
> x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
> +
> +   enable_pm_piix();
> } else {
> /* Configure PCIe ECAM base address */
> x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
>CONFIG_PCIE_ECAM_BASE | BAR_EN);
> +
> +   enable_pm_ich9();
> }
>
> qemu_fwcfg_init();
> diff --git a/arch/x86/include/asm/arch-qemu/device.h 
> b/arch/x86/include/asm/arch-qemu/device.h
> index 75a435e..2e11100 100644
> --- a/arch/x86/include/asm/arch-qemu/device.h
> +++ b/arch/x86/include/asm/arch-qemu/device.h
> @@ -13,9 +13,17 @@
>  #define PIIX_ISA   PCI_BDF(0, 1, 0)
>  #define PIIX_IDE   PCI_BDF(0, 1, 1)
>  #define PIIX_USB   PCI_BDF(0, 1, 2)
> +#define PIIX_PMPCI_BDF(0, 1, 3)
> +#define ICH9_PMPCI_BDF(0, 0x1f, 0)
>  #define I440FX_VGA PCI_BDF(0, 2, 0)
>
>  #define QEMU_Q35   PCI_BDF(0, 0, 0)
>  #define Q35_VGAPCI_BDF(0, 1, 0)
>
> +#define PMBA   0x40
> +#define DEFAULT_PMBASE 0xe400

See arch/x86/cpu/quark/Kconfig we have ACPI_PM1_BASE already. Maybe we
need consolidate this to introduce a similar one for QEMU.

> +#define PM_IO_BASE DEFAULT_PMBASE

PM_IO_BASE is not referenced anywhere.

> +#define PMREGMISC  0x80
> +#define PMIOSE (1 << 0)
> +

Please move these register defines to include/asm/arch-qemu/qemu.h

>  #endif /* _QEMU_DEVICE_H_ */
> --

Regards,
Bin
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Re: [U-Boot] [PATCH 1/4] x86: qemu: re-structure qemu_fwcfg_list_firmware()

[Bin Meng]

Hi Miao,

On Fri, Jan 15, 2016 at 11:12 AM, Miao Yan  wrote:
> Re-write the logic in qemu_fwcfg_list_firmware(), add a function
> qemu_cfg_read_firmware_list() to handle reading firmware list.

qemu_fwcfg_read_firmware_list()

>
> Signed-off-by: Miao Yan 
> ---
>  arch/x86/cpu/qemu/fw_cfg.c| 60 
> +--
>  arch/x86/include/asm/fw_cfg.h |  8 ++
>  2 files changed, 54 insertions(+), 14 deletions(-)
>
> diff --git a/arch/x86/cpu/qemu/fw_cfg.c b/arch/x86/cpu/qemu/fw_cfg.c
> index 0599214..b22026c 100644
> --- a/arch/x86/cpu/qemu/fw_cfg.c
> +++ b/arch/x86/cpu/qemu/fw_cfg.c
> @@ -10,10 +10,13 @@
>  #include 
>  #include 
>  #include 
> +#include 
>
>  static bool fwcfg_present;
>  static bool fwcfg_dma_present;
>
> +static LIST_HEAD(fw_list);
> +
>  /* Read configuration item using fw_cfg PIO interface */
>  static void qemu_fwcfg_read_entry_pio(uint16_t entry,
> uint32_t size, void *address)
> @@ -162,29 +165,58 @@ static int qemu_fwcfg_setup_kernel(void *load_addr, 
> void *initrd_addr)
> return 0;
>  }
>
> -static int qemu_fwcfg_list_firmware(void)
> +static int qemu_fwcfg_read_firmware_list(void)
>  {
> int i;
> uint32_t count;
> -   struct fw_cfg_files *files;
> +   struct fw_file *file;
> +   struct list_head *entry;
> +
> +   /* don't read it twice */
> +   if (!list_empty(_list))
> +   return 0;
>
> qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, );
> if (!count)
> return 0;
>
> count = be32_to_cpu(count);
> -   files = malloc(count * sizeof(struct fw_cfg_file));
> -   if (!files)
> -   return -ENOMEM;
> -
> -   files->count = count;
> -   qemu_fwcfg_read_entry(FW_CFG_INVALID,
> - count * sizeof(struct fw_cfg_file),
> - files->files);
> -
> -   for (i = 0; i < files->count; i++)
> -   printf("%-56s\n", files->files[i].name);
> -   free(files);
> +   for (i = 0; i < count; i++) {
> +   file = malloc(sizeof(*file));
> +   if (!file) {
> +   printf("error: allocating resource\n");
> +   goto err;
> +   }
> +   qemu_fwcfg_read_entry(FW_CFG_INVALID,
> + sizeof(struct fw_cfg_file), >cfg);
> +   file->addr = 0;
> +   list_add_tail(>list, _list);
> +   }

nits: leave one blank line before return

> +   return 0;
> +
> +err:
> +   list_for_each(entry, _list) {
> +   file = list_entry(entry, struct fw_file, list);
> +   free(file);
> +   }

nits: leave one blank line before return

> +   return -ENOMEM;
> +}
> +
> +static int qemu_fwcfg_list_firmware(void)
> +{
> +   int ret;
> +   struct list_head *entry;
> +   struct fw_file *file;
> +
> +   /* make sure fw_list is loaded */
> +   ret = qemu_fwcfg_read_firmware_list();
> +   if (ret)
> +   return ret;
> +
> +   list_for_each(entry, _list) {
> +   file = list_entry(entry, struct fw_file, list);
> +   printf("%-56s\n", file->cfg.name);
> +   }

nits: leave one blank line before return

> return 0;
>  }
>
> diff --git a/arch/x86/include/asm/fw_cfg.h b/arch/x86/include/asm/fw_cfg.h
> index fb110fa..285d805 100644
> --- a/arch/x86/include/asm/fw_cfg.h
> +++ b/arch/x86/include/asm/fw_cfg.h
> @@ -12,6 +12,8 @@
>  #define FW_DMA_PORT_LOW0x514
>  #define FW_DMA_PORT_HIGH   0x518
>
> +#include 
> +
>  enum qemu_fwcfg_items {
> FW_CFG_SIGNATURE= 0x00,
> FW_CFG_ID   = 0x01,
> @@ -67,6 +69,12 @@ struct fw_cfg_file {
> char name[FW_CFG_MAX_FILE_PATH];
>  };
>
> +struct fw_file {
> +   struct fw_cfg_file cfg;
> +   unsigned long addr;
> +   struct list_head list;
> +};

Can you please put a comment block above to describe what is each member for?

> +
>  struct fw_cfg_files {

Looks that this struct fw_cfg_files is no longer used by any codes.
Please remove this.

> __be32 count;
> struct fw_cfg_file files[];
> --

Regards,
Bin
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Re: [U-Boot] [PATCH 4/4] x86: qemu: loading ACPI table from QEMU

[Bin Meng]

Hi Miao,

On Fri, Jan 15, 2016 at 11:12 AM, Miao Yan  wrote:
> If CONFIG_GENERATE_ACPI_TABLE is not defined, then use ACPI table created
> by QEMU.
>
> Signed-off-by: Miao Yan 
> ---
>  arch/x86/lib/tables.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
> index 14b15cf..1671385 100644
> --- a/arch/x86/lib/tables.c
> +++ b/arch/x86/lib/tables.c
> @@ -10,6 +10,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>
>  u8 table_compute_checksum(void *v, int len)
>  {
> @@ -55,8 +56,10 @@ void write_tables(void)
>  #endif
>  #ifdef CONFIG_GENERATE_ACPI_TABLE
> rom_table_end = write_acpi_tables(rom_table_end);
> -   rom_table_end = ALIGN(rom_table_end, 1024);
> +#else
> +   rom_table_end = qemu_fwcfg_write_acpi_tables(rom_table_end);

This breaks other x86 boards.Can we hide this changes in acpi_table.c
with proper #ifdef and some comments?

For QEMU ACPI, how about:

- GENERATE_ACPI_TABLE is the overall switch to turn on ACPI table by U-Boot
- Introduce another Kconfig option for QEMU to generate ACPI tables
from firmware interface. If this is turned on, the original method
provided in acpi_tables.c will not be used.

>  #endif
> +   rom_table_end = ALIGN(rom_table_end, 1024);
>  #ifdef CONFIG_GENERATE_SMBIOS_TABLE
> rom_table_end = write_smbios_table(rom_table_end);
> rom_table_end = ALIGN(rom_table_end, 1024);
> --

Regards,
Bin
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Re: [U-Boot] [PATCH] include stdint.h where mtd/mtd-user.h is included

[Gerhard Heift]

As Thomas Petazzoni pointed out in [1] this issue is already fixed by
commit 69bf2d2fafe64349be3c3ef1256e3c68f812bb25 [2].
I fixed 2015.10 for me and ported the patch forward to 2016.01 without
further verification if it is still needed and not fixed otherwise.

Regards,
  Gerhard

[1] http://lists.busybox.net/pipermail/buildroot/2016-January/149611.html
[2] 
http://git.denx.de/?p=u-boot.git;a=commit;h=69bf2d2fafe64349be3c3ef1256e3c68f812bb25

2016-01-15 19:11 GMT+01:00 Gerhard Heift :
> Since linux 4.4 mtd/mtd-user.h does not include stdint.h any more, so it
> has to be included explicitly.
>
> See commit 137d36af4a53858b8db7ca83c8480247118b8bdf of the linux kernel.
>
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=137d36af4a53858b8db7ca83c8480247118b8bdf
>
> Signed-off-by: Gerhard Heift 
> ---
>  tools/env/fw_env.c   | 1 +
>  tools/palmtreo680/flash_u-boot.c | 1 +
>  2 files changed, 2 insertions(+)
>
> diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
> index 39f7333..098c7c7 100644
> --- a/tools/env/fw_env.c
> +++ b/tools/env/fw_env.c
> @@ -29,6 +29,7 @@
>  # include 
>  #else
>  # define  __user   /* nothing */
> +# include 
>  # include 
>  #endif
>
> diff --git a/tools/palmtreo680/flash_u-boot.c 
> b/tools/palmtreo680/flash_u-boot.c
> index 3d8296f..7a9b37d 100644
> --- a/tools/palmtreo680/flash_u-boot.c
> +++ b/tools/palmtreo680/flash_u-boot.c
> @@ -28,6 +28,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include "libmtd.h"
>
> --
> 2.7.0.rc3
>
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Re: [U-Boot] [PATCH v3 4/8] dm: Expand the uclass for Platform Controller Hubs (PCH)

[Simon Glass]

Hi Bin,

On 21 December 2015 at 02:16, Bin Meng  wrote:
> Hi Simon,
>
> On Sun, Dec 20, 2015 at 6:42 AM, Simon Glass  wrote:
>> A Platform Controller Hub is an Intel concept - it is like the peripherals
>> on an SoC and is often in a separate chip from the CPU. The chip is typically
>> found on the first PCI bus and integrates multiple devices.
>>
>> We have a very simple uclass to support PCHs. Add a few operations, such as
>> setting up the devices on the PCH and finding the SPI controller base
>> address. Also move it into drivers/pch/ since we will be adding a few PCH
>> drivers.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>> Changes in v3:
>> - Add a PCH method to enable/disable SPI flash protection
>> - Drop the pch_init() call
>>
>> Changes in v2:
>> - Update the commit message and header file comments
>> - Use an enum for the PCH version
>> - Replace SBASE with SPI base
>> - Add a TODO to check if the init() method can be removed later
>>
>>  arch/x86/lib/Makefile  |  1 -
>>  drivers/Makefile   |  1 +
>>  drivers/pch/Makefile   |  5 ++
>>  {arch/x86/lib => drivers/pch}/pch-uclass.c | 32 +
>>  include/pch.h  | 74 
>> ++
>>  5 files changed, 112 insertions(+), 1 deletion(-)
>>  create mode 100644 drivers/pch/Makefile
>>  rename {arch/x86/lib => drivers/pch}/pch-uclass.c (50%)
>>  create mode 100644 include/pch.h
>>
>> diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
>> index cd5ecb6..43792bc 100644
>> --- a/arch/x86/lib/Makefile
>> +++ b/arch/x86/lib/Makefile
>> @@ -24,7 +24,6 @@ obj-$(CONFIG_I8254_TIMER) += i8254.o
>>  ifndef CONFIG_DM_PCI
>>  obj-$(CONFIG_PCI) += pci_type1.o
>>  endif
>> -obj-y  += pch-uclass.o
>>  obj-y  += pirq_routing.o
>>  obj-y  += relocate.o
>>  obj-y += physmem.o
>> diff --git a/drivers/Makefile b/drivers/Makefile
>> index c9031f2..acc6af9 100644
>> --- a/drivers/Makefile
>> +++ b/drivers/Makefile
>> @@ -51,6 +51,7 @@ obj-y += hwmon/
>>  obj-y += misc/
>>  obj-y += pcmcia/
>>  obj-y += dfu/
>> +obj-$(CONFIG_X86) += pch/
>>  obj-y += rtc/
>>  obj-y += sound/
>>  obj-y += timer/
>> diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile
>> new file mode 100644
>> index 000..d69a99c
>> --- /dev/null
>> +++ b/drivers/pch/Makefile
>> @@ -0,0 +1,5 @@
>> +#
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +
>> +obj-y += pch-uclass.o
>> diff --git a/arch/x86/lib/pch-uclass.c b/drivers/pch/pch-uclass.c
>> similarity index 50%
>> rename from arch/x86/lib/pch-uclass.c
>> rename to drivers/pch/pch-uclass.c
>> index 20dfa81..4579ed1 100644
>> --- a/arch/x86/lib/pch-uclass.c
>> +++ b/drivers/pch/pch-uclass.c
>> @@ -7,10 +7,42 @@
>>
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>
>>  DECLARE_GLOBAL_DATA_PTR;
>>
>> +int pch_get_sbase(struct udevice *dev, ulong *sbasep)
>> +{
>> +   struct pch_ops *ops = pch_get_ops(dev);
>> +
>> +   *sbasep = 0;
>> +   if (!ops->get_sbase)
>> +   return -ENOSYS;
>> +
>> +   return ops->get_sbase(dev, sbasep);
>> +}
>> +
>> +enum pch_version pch_get_version(struct udevice *dev)
>
> Should the return value be int given it can return -ENOSYS which is not enum?

An (unpacked) enum is just an int so I think this is OK. Callers
typically check against enum members. The nice thing is that it makes
the return type really clear. I'm happy to change it if you think it
is dodgy.,

[snip]

Regards,
Simon
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Re: [U-Boot] [PATCH v3 6/8] dm: x86: Add a driver for Intel PCH9

[Simon Glass]

Hi Bin,

On 21 December 2015 at 02:16, Bin Meng  wrote:
> Hi Simon,
>
> On Sun, Dec 20, 2015 at 6:42 AM, Simon Glass  wrote:
>> At some point we may need to distinguish between different types of PCHs,
>> but for existing supported platforms we only need to worry about version 7
>> and version 9 bridges. Add a driver for the PCH9.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>> Changes in v3: None
>> Changes in v2:
>> - Rename the PCH functions
>> - Update the get_version() handle to use an enum
>>
>>  drivers/pch/Makefile |  1 +
>>  drivers/pch/pch9.c   | 43 +++
>>  2 files changed, 44 insertions(+)
>>  create mode 100644 drivers/pch/pch9.c
>>
>> diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile
>> index 33aa727..dde9e86 100644
>> --- a/drivers/pch/Makefile
>> +++ b/drivers/pch/Makefile
>> @@ -4,3 +4,4 @@
>>
>>  obj-y += pch-uclass.o
>>  obj-y += pch7.o
>> +obj-y += pch9.o
>> diff --git a/drivers/pch/pch9.c b/drivers/pch/pch9.c
>> new file mode 100644
>> index 000..529cb02
>> --- /dev/null
>> +++ b/drivers/pch/pch9.c
>> @@ -0,0 +1,43 @@
>> +/*
>> + * Copyright (C) 2014 Google, Inc
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#define SBASE_ADDR 0x54
>> +
>> +static int pch9_get_sbase(struct udevice *dev, ulong *sbasep)
>> +{
>> +   uint32_t sbase_addr;
>> +
>> +   dm_pci_read_config32(dev, SBASE_ADDR, _addr);
>> +   *sbasep = sbase_addr & 0xfe00;
>> +
>> +   return 0;
>> +}
>> +
>> +static enum pch_version pch9_get_version(struct udevice *dev)
>> +{
>> +   return PCHV_9;
>> +}
>> +
>> +static const struct pch_ops pch9_ops = {
>> +   .get_sbase  = pch9_get_sbase,
>> +   .get_version= pch9_get_version,
>
> No set_spi_protect() op implementation?

>From my testing minnowmax works fine without this.

>
>> +};
>> +
>> +static const struct udevice_id pch9_ids[] = {
>> +   { .compatible = "intel,pch9" },
>> +   { }
>> +};
>> +
>> +U_BOOT_DRIVER(pch9_drv) = {
>> +   .name   = "intel-pch9",
>> +   .id = UCLASS_PCH,
>> +   .of_match   = pch9_ids,
>> +   .ops= _ops,
>> +};
>> --

Regards,
Simon
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[U-Boot] [REGRESSION] Ethernet broken on Colibri T20/T30

[Marcel Ziswiler]

Hi Simon

As mentioned before I noticed Ethernet (on-module USB ASIX chip) to be
broken on master while it still worked fine in v2016.01. I kind of
remember having once noticed something along those lines when testing
some of your early dm stuff but could not find our discussion about it
anymore plus I don't think it did actually lead anywhere.

FWIW it currently crashes as follows (showing Colibri T20 but the same
happens on Colibri T30):

U-Boot SPL 2016.01-00205-gb8c5b47 (Jan 17 2016 - 01:31:48)
Trying to boot from RAM


U-Boot 2016.01-00205-gb8c5b47 (Jan 17 2016 - 01:31:48 +0100)

TEGRA20
Model: Toradex Colibri T20
Board: Toradex Colibri T20
DRAM:  512 MiB
NAND:  1024 MiB
MMC:   Tegra SD/MMC: 0
*** Warning - bad CRC, using default environment

In:serial
Out:   lcd
Err:   lcd
USB recovery mode
Net:   No ethernet found.
Hit any key to stop autoboot:  2  0 
Colibri T20 # usb start
starting USB...
USB0:   USB EHCI 1.00
USB1:   USB EHCI 1.00
USB2:   USB EHCI 1.00
scanning bus 1 for devices... 1 USB Device(s) found
scanning bus 2 for devices... 
Warning: asix_eth using MAC address from ROM
2 USB Device(s) found
scanning bus 0 for devices... 2 USB Device(s) found
Colibri T20 # dhcp
BOOTP broadcast 1
EHCI timed out on TD - token=0x88008d80
Rx: failed to receive: -5
BOOTP broadcast 2
EHCI timed out on TD - token=0x8008d80
Rx: failed to receive: -5
BOOTP broadcast 3
EHCI timed out on TD - token=0x88008d80
Rx: failed to receive: -5
BOOTP broadcast 4
EHCI timed out on TD - token=0x8008d80
Rx: failed to receive: -5
BOOTP broadcast 5
EHCI timed out on TD - token=0x88008d80
Rx: failed to receive: -5
BOOTP broadcast 6
EHCI timed out on TD - token=0x8008d80
Rx: failed to receive: -5

Retry time exceeded; starting again
data abort
pc : [<1fb4d194>]      lr : [<1fbb9784>]
reloc pc : [<0012d194>]    lr : [<00199784>]
sp : 1d61c5e0  ip : 6aa665ea fp : 1d62bca0
r10:   r9 : 1d61fee0 r8 : 1d62bca0
r7 :   r6 : 1d6312e0 r5 : 1f6da8e0  r4 : 
r3 : 1c585760  r2 : 03155180 r1 :   r0 : caa661ca
Flags: NzCv  IRQs off  FIQs off  Mode SVC_32
Resetting CPU ...

resetting ...

Do you have any clue what could be going on?

Cheers

Marcel
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Re: [U-Boot] [PATCH] image: fix getenv_bootm_size() function

[Masahiro Yamada]

Tom,

This patch is a bug-fix
and still keeping me from using bootm_low on my boards.

Please apply!

-- 
Best Regards
Masahiro Yamada
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[U-Boot] [PATCH] drivers/spi/rk_spi.c: Fix debug format warning

[Tom Rini]

We need to use %lx not %x to describe a fdt_addr_t

Cc: Simon Glass 
Signed-off-by: Tom Rini 
---
 drivers/spi/rk_spi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 5e0c6ad..242a83b 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -135,7 +135,7 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice 
*bus)
5000);
plat->deactivate_delay_us = fdtdec_get_int(blob, node,
"spi-deactivate-delay", 0);
-   debug("%s: base=%x, periph_id=%d, max-frequency=%d, 
deactivate_delay=%d\n",
+   debug("%s: base=%lx, periph_id=%d, max-frequency=%d, 
deactivate_delay=%d\n",
  __func__, plat->base, plat->periph_id, plat->frequency,
  plat->deactivate_delay_us);
 
-- 
2.7.0.rc3

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[U-Boot] [PATCHv4 4/7] spl: support loading from UBI volumes

[Ladislav Michl]

Add support for loading from UBI volumes on the top of NAND.

Signed-off-by: Ladislav Michl 
---
 common/spl/Makefile  |  3 +++
 common/spl/spl.c |  4 
 common/spl/spl_ubi.c | 68 
 include/spl.h|  4 
 4 files changed, 79 insertions(+)
 create mode 100644 common/spl/spl_ubi.c

diff --git a/common/spl/Makefile b/common/spl/Makefile
index 10a4589..36e5338 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -12,8 +12,11 @@ ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
 obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o
 obj-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o
+ifndef CONFIG_SPL_UBI
 obj-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o
+endif
 obj-$(CONFIG_SPL_ONENAND_SUPPORT) += spl_onenand.o
+obj-$(CONFIG_SPL_UBI) += spl_ubi.o
 obj-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o
 obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o
 obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o
diff --git a/common/spl/spl.c b/common/spl/spl.c
index e5167bf..b945a48 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -288,8 +288,12 @@ static int spl_load_image(u32 boot_device)
 #endif
 #ifdef CONFIG_SPL_NAND_SUPPORT
case BOOT_DEVICE_NAND:
+#ifdef CONFIG_SPL_UBI
+   return spl_ubi_load_image(boot_device);
+#else
return spl_nand_load_image();
 #endif
+#endif
 #ifdef CONFIG_SPL_ONENAND_SUPPORT
case BOOT_DEVICE_ONENAND:
return spl_onenand_load_image();
diff --git a/common/spl/spl_ubi.c b/common/spl/spl_ubi.c
new file mode 100644
index 000..dd8ce36
--- /dev/null
+++ b/common/spl/spl_ubi.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2016
+ * Ladislav Michl 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+int spl_ubi_load_image(u32 boot_device)
+{
+   int ret;
+   struct image_header *header;
+   struct ubispl_info info;
+   struct ubispl_load volumes[2];
+
+#ifdef CONFIG_SPL_NAND_SUPPORT
+   if (boot_device == BOOT_DEVICE_NAND)
+   nand_init();
+#endif
+   info.ubi = (struct ubi_scan_info *) CONFIG_SPL_UBI_INFO_ADDR;
+   info.fastmap = 1;
+   info.read = nand_spl_read_block;
+
+   info.peb_offset = CONFIG_SPL_UBI_PEB_OFFSET;
+   info.peb_size = CONFIG_SYS_NAND_BLOCK_SIZE;
+   info.vid_offset = CONFIG_SPL_UBI_VID_OFFSET;
+   info.leb_start = CONFIG_SPL_UBI_LEB_START;
+   info.peb_count = CONFIG_SPL_UBI_MAX_PEBS - info.peb_offset;
+
+#ifdef CONFIG_SPL_OS_BOOT
+   if (!spl_start_uboot()) {
+   volumes[0].vol_id = CONFIG_SPL_UBI_LOAD_KERNEL_ID;
+   volumes[0].load_addr = (void *)CONFIG_SYS_LOAD_ADDR;
+   volumes[1].vol_id = CONFIG_SPL_UBI_LOAD_ARGS_ID;
+   volumes[1].load_addr = (void *)CONFIG_SYS_SPL_ARGS_ADDR;
+
+   ret = ubispl_load_volumes(, volumes, 2);
+   if (!ret) {
+   header = (struct image_header *) volumes[0].load_addr;
+   spl_parse_image_header(header);
+   puts("Linux loaded.\n");
+   goto out;
+   }
+   puts("Loading Linux failed, falling back to U-Boot.\n");
+   }
+#endif
+   header = (struct image_header *)
+   (CONFIG_SYS_TEXT_BASE - sizeof(struct image_header));
+   volumes[0].vol_id = CONFIG_SPL_UBI_LOAD_MONITOR_ID;
+   volumes[0].load_addr = (void *)header;
+
+   ret = ubispl_load_volumes(, volumes, 1);
+   if (!ret)
+   spl_parse_image_header(header);
+#ifdef CONFIG_SPL_OS_BOOT
+out:
+#endif
+#ifdef CONFIG_SPL_NAND_SUPPORT
+   if (boot_device == BOOT_DEVICE_NAND)
+   nand_deselect();
+#endif
+   return ret;
+}
diff --git a/include/spl.h b/include/spl.h
index 92cdc04..1ab9295 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -40,6 +40,7 @@ u32 spl_boot_mode(void);
 void spl_set_header_raw_uboot(void);
 void spl_parse_image_header(const struct image_header *header);
 void spl_board_prepare_for_linux(void);
+int spl_board_ubi_load_image(u32 boot_device);
 void __noreturn jump_to_image_linux(void *arg);
 int spl_start_uboot(void);
 void spl_display_print(void);
@@ -53,6 +54,9 @@ int spl_onenand_load_image(void);
 /* NOR SPL functions */
 int spl_nor_load_image(void);
 
+/* UBI SPL functions */
+int spl_ubi_load_image(u32 boot_device);
+
 /* MMC SPL functions */
 int spl_mmc_load_image(u32 boot_device);
 
-- 
2.1.4

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[U-Boot] [PATCHv4 3/7] spl: Lightweight UBI and UBI fastmap support

[Ladislav Michl]

From: Thomas Gleixner 

Booting a payload out of NAND FLASH from the SPL is a crux today, as
it requires hard partioned FLASH. Not a brilliant idea with the
reliability of todays NAND FLASH chips.

The upstream UBI + UBI fastmap implementation which is about to
brought to u-boot is too heavy weight for SPLs as it provides way more
functionality than needed for a SPL and does not even fit into the
restricted SPL areas which are loaded from the SoC boot ROM.

So this provides a fast and lightweight implementation of UBI scanning
and UBI fastmap attach. The scan and logical to physical block mapping
code is developed from scratch, while the fastmap implementation is
lifted from the linux kernel source and stripped down to fit the SPL
needs.

The text foot print on the board which I used for development is:

68540   0   68541abd
drivers/mtd/ubispl/built-in.o

Attaching a NAND chip with 4096 physical eraseblocks (4 blocks are
reserved for the SPL) takes:

In full scan mode:  1172ms
In fastmap mode:  95ms

The code requires quite some storage. The largest and unknown part of
it is the number of fastmap blocks to read. Therefor the data
structure is not put into the BSS. The code requires a pointer to free
memory handed in which is initialized by the UBI attach code itself.

See doc/README.ubispl for further information on how to use it.

This shares the ubi-media.h and crc32 implementation of drivers/mtd/ubi
There is no way to share the fastmap code, as UBISPL only utilizes the
slightly modified functions ubi_attach_fastmap() and ubi_scan_fastmap()
from the original kernel ubi fastmap implementation.

Signed-off-by: Thomas Gleixner 
Signed-off-by: Ladislav Michl 
Acked-by: Heiko Schocher 
Reviewed-by: Tom Rini 
---
Changes in v2:
  - fixes ubi_calc_fm_size to include also sizeof(struct ubi_fm_sb)
  - dropped private copy of ubi-media.h
  - ubi-wrapper.h now contains only needed definitions from ubi.h
and ubi-user.h
  - used return values from errno.h

Changes in v3:
  - move vol_id check to ubi_scan_vid_hdr to verify it has meaningfull value
before testing ubi->toload
  - fixed checkpatch errors except those present also in linux code

Changes in v4:
  - drop unused name field from ubispl_load structure
  - ipl_load returns lenght read

 README   |   4 +
 doc/README.ubispl| 141 ++
 drivers/Makefile |   1 +
 drivers/mtd/ubispl/Makefile  |   1 +
 drivers/mtd/ubispl/ubi-wrapper.h | 106 +
 drivers/mtd/ubispl/ubispl.c  | 926 +++
 drivers/mtd/ubispl/ubispl.h  | 136 ++
 include/ubispl.h |  90 
 8 files changed, 1405 insertions(+)
 create mode 100644 doc/README.ubispl
 create mode 100644 drivers/mtd/ubispl/Makefile
 create mode 100644 drivers/mtd/ubispl/ubi-wrapper.h
 create mode 100644 drivers/mtd/ubispl/ubispl.c
 create mode 100644 drivers/mtd/ubispl/ubispl.h
 create mode 100644 include/ubispl.h

diff --git a/README b/README
index 9423c34..e3adbdc 100644
--- a/README
+++ b/README
@@ -3611,6 +3611,10 @@ FIT uImage format:
Support for NAND boot using simple NAND drivers that
expose the cmd_ctrl() interface.
 
+   CONFIG_SPL_UBI
+   Support for a lightweight UBI (fastmap) scanner and
+   loader
+
CONFIG_SPL_MTD_SUPPORT
Support for the MTD subsystem within SPL.  Useful for
environment on NAND support within SPL.
diff --git a/doc/README.ubispl b/doc/README.ubispl
new file mode 100644
index 000..ddb629d
--- /dev/null
+++ b/doc/README.ubispl
@@ -0,0 +1,141 @@
+Lightweight UBI and UBI fastmap support
+
+# Copyright (C) Thomas Gleixner 
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+Scans the UBI information and loads the requested static volumes into
+memory.
+
+Configuration Options:
+
+   CONFIG_SPL_UBI
+ Enables the SPL UBI support
+
+   CONFIG_SPL_UBI_MAX_VOL_LEBS
+ The maximum number of logical eraseblocks which a static volume
+ to load can contain. Used for sizing the scan data structure
+
+   CONFIG_SPL_UBI_MAX_PEB_SIZE
+ The maximum physical erase block size. Either a compile time
+ constant or runtime detection. Used for sizing the scan data
+ structure
+
+   CONFIG_SPL_UBI_MAX_PEBS
+ The maximum physical erase block count. Either a compile time
+ constant or runtime detection. Used for sizing the scan data
+ structure
+
+   CONFIG_SPL_UBI_VOL_IDS
+ The maximum volume ids which can be loaded. Used for sizing the
+ scan data structure.
+
+Usage notes:
+
+In the board config file define for example:
+
+#define CONFIG_SPL_UBI
+#define CONFIG_SPL_UBI_MAX_VOL_LEBS256
+#define CONFIG_SPL_UBI_MAX_PEB_SIZE(256*1024)
+#define CONFIG_SPL_UBI_MAX_PEBS4096

[U-Boot] [PATCHv5 5/7] spl: zImage support in Falcon mode

[Ladislav Michl]

Other payload than uImage is currently considered to be raw U-Boot
image. Check also for zImage in Falcon mode.

Signed-off-by: Ladislav Michl 
---
 arch/arm/lib/Makefile |  2 ++
 arch/arm/lib/bootm.c  | 32 
 arch/arm/lib/zimage.c | 40 
 common/spl/spl.c  | 23 +++
 4 files changed, 65 insertions(+), 32 deletions(-)
 create mode 100644 arch/arm/lib/zimage.c

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index f3db7b5..07a9019 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -26,11 +26,13 @@ endif
 obj-$(CONFIG_CPU_V7M) += cmd_boot.o
 obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTM) += zimage.o
 obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
 obj-$(CONFIG_USE_ARCH_MEMSET) += memset.o
 obj-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
 else
 obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
+obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o
 endif
 obj-$(CONFIG_SEMIHOSTING) += semihosting.o
 
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index a477cae..fbfc0ad 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -348,38 +348,6 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
return 0;
 }
 
-#ifdef CONFIG_CMD_BOOTZ
-
-struct zimage_header {
-   uint32_tcode[9];
-   uint32_tzi_magic;
-   uint32_tzi_start;
-   uint32_tzi_end;
-};
-
-#defineLINUX_ARM_ZIMAGE_MAGIC  0x016f2818
-
-int bootz_setup(ulong image, ulong *start, ulong *end)
-{
-   struct zimage_header *zi;
-
-   zi = (struct zimage_header *)map_sysmem(image, 0);
-   if (zi->zi_magic != LINUX_ARM_ZIMAGE_MAGIC) {
-   puts("Bad Linux ARM zImage magic!\n");
-   return 1;
-   }
-
-   *start = zi->zi_start;
-   *end = zi->zi_end;
-
-   printf("Kernel image @ %#08lx [ %#08lx - %#08lx ]\n", image, *start,
- *end);
-
-   return 0;
-}
-
-#endif /* CONFIG_CMD_BOOTZ */
-
 #if defined(CONFIG_BOOTM_VXWORKS)
 void boot_prep_vxworks(bootm_headers_t *images)
 {
diff --git a/arch/arm/lib/zimage.c b/arch/arm/lib/zimage.c
new file mode 100644
index 000..f870d72
--- /dev/null
+++ b/arch/arm/lib/zimage.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2016
+ * Ladislav Michl 
+ *
+ * bootz code:
+ * Copyright (C) 2012 Marek Vasut 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include 
+
+#defineLINUX_ARM_ZIMAGE_MAGIC  0x016f2818
+
+struct arm_z_header {
+   uint32_tcode[9];
+   uint32_tzi_magic;
+   uint32_tzi_start;
+   uint32_tzi_end;
+} __attribute__ ((__packed__));
+
+int bootz_setup(ulong image, ulong *start, ulong *end)
+{
+   struct arm_z_header *zi = (struct arm_z_header *) image;
+
+   if (zi->zi_magic != LINUX_ARM_ZIMAGE_MAGIC) {
+#ifndef CONFIG_SPL_FRAMEWORK
+   puts("Bad Linux ARM zImage magic!\n");
+#endif
+   return 1;
+   }
+
+   *start = zi->zi_start;
+   *end = zi->zi_end;
+#ifndef CONFIG_SPL_FRAMEWORK
+   printf("Kernel image @ %#08lx [ %#08lx - %#08lx ]\n", image, *start,
+ *end);
+#endif
+
+   return 0;
+}
diff --git a/common/spl/spl.c b/common/spl/spl.c
index b945a48..7fd8e5d 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -52,6 +52,15 @@ __weak int spl_start_uboot(void)
puts("SPL: Direct Linux boot not active!\n");
return 1;
 }
+
+/*
+ * Weak default function for arch specific zImage check. Return zero
+ * and fill start and end address if image is recognized.
+ */
+int __weak bootz_setup(ulong image, ulong *start, ulong *end)
+{
+return 1;
+}
 #endif
 
 /*
@@ -112,6 +121,20 @@ void spl_parse_image_header(const struct image_header 
*header)
 */
panic("** no mkimage signature but raw image not supported");
 #else
+#ifdef CONFIG_SPL_OS_BOOT
+   ulong start, end;
+
+   if (!bootz_setup((ulong)header, , )) {
+   spl_image.name = "Linux";
+   spl_image.os = IH_OS_LINUX;
+   spl_image.load_addr = CONFIG_SYS_LOAD_ADDR;
+   spl_image.entry_point = CONFIG_SYS_LOAD_ADDR;
+   spl_image.size = end - start;
+   debug("spl: payload zImage, load addr: 0x%x size: %d\n",
+   spl_image.load_addr, spl_image.size);
+   return;
+   }
+#endif
/* Signature not found - assume u-boot.bin */
debug("mkimage signature not found - ih_magic = %x\n",
header->ih_magic);
-- 
2.1.4

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[U-Boot] [PATCHv4 2/7] nand_spl_simple: Add a simple NAND read function

[Ladislav Michl]

From: Thomas Gleixner 

To support UBI in SPL we need a simple NAND read function. Add one to
nand_spl_simple and keep it as simple as it goes.

Signed-off-by: Thomas Gleixner 
Signed-off-by: Ladislav Michl 
Acked-by: Scott Wood 
Reviewed-by: Tom Rini 
---
Changes in v3:
- Rename nand_spl_read_flash to nand_spl_read_block and optimize it.

 drivers/mtd/nand/nand_spl_simple.c | 62 ++
 include/nand.h |  1 +
 2 files changed, 63 insertions(+)

diff --git a/drivers/mtd/nand/nand_spl_simple.c 
b/drivers/mtd/nand/nand_spl_simple.c
index e69f662..cf80903 100644
--- a/drivers/mtd/nand/nand_spl_simple.c
+++ b/drivers/mtd/nand/nand_spl_simple.c
@@ -209,6 +209,68 @@ static int nand_read_page(int block, int page, void *dst)
 }
 #endif
 
+#ifdef CONFIG_SPL_UBI
+/*
+ * Temporary storage for non NAND page aligned and non NAND page sized
+ * reads. Note: This does not support runtime detected FLASH yet, but
+ * that should be reasonably easy to fix by making the buffer large
+ * enough :)
+ */
+static u8 scratch_buf[CONFIG_SYS_NAND_PAGE_SIZE];
+
+/**
+ * nand_spl_read_block - Read data from physical eraseblock into a buffer
+ * @block: Number of the physical eraseblock
+ * @offset:Data offset from the start of @peb
+ * @len:   Data size to read
+ * @dst:   Address of the destination buffer
+ *
+ * This could be further optimized if we'd have a subpage read
+ * function in the simple code. On NAND which allows subpage reads
+ * this would spare quite some time to readout e.g. the VID header of
+ * UBI.
+ *
+ * Notes:
+ * @offset + @len are not allowed to be larger than a physical
+ * erase block. No sanity check done for simplicity reasons.
+ *
+ * To support runtime detected flash this needs to be extended by
+ * information about the actual flash geometry, but thats beyond the
+ * scope of this effort and for most applications where fast boot is
+ * required it is not an issue anyway.
+ */
+int nand_spl_read_block(int block, int offset, int len, void *dst)
+{
+   int page, read;
+
+   /* Calculate the page number */
+   page = offset / CONFIG_SYS_NAND_PAGE_SIZE;
+
+   /* Offset to the start of a flash page */
+   offset = offset % CONFIG_SYS_NAND_PAGE_SIZE;
+
+   while (len) {
+   /*
+* Non page aligned reads go to the scratch buffer.
+* Page aligned reads go directly to the destination.
+*/
+   if (offset || len < CONFIG_SYS_NAND_PAGE_SIZE) {
+   nand_read_page(block, page, scratch_buf);
+   read = min(len, CONFIG_SYS_NAND_PAGE_SIZE - offset);
+   memcpy(dst, scratch_buf + offset, read);
+   offset = 0;
+   } else {
+   nand_read_page(block, page, dst);
+   read = CONFIG_SYS_NAND_PAGE_SIZE;
+   }
+   page++;
+   len -= read;
+   dst += read;
+   }
+   return 0;
+}
+#endif
+
 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
 {
unsigned int block, lastblock;
diff --git a/include/nand.h b/include/nand.h
index d2a53ab..2f9a1ec 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -124,6 +124,7 @@ int nand_unlock(nand_info_t *meminfo, loff_t start, size_t 
length,
 int nand_get_lock_status(nand_info_t *meminfo, loff_t offset);
 
 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst);
+int nand_spl_read_block(int block, int offset, int len, void *dst);
 void nand_deselect(void);
 
 #ifdef CONFIG_SYS_NAND_SELECT_DEVICE
-- 
2.1.4

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[U-Boot] [PATCHv7 6/7] igep00x0: UBIize

[Ladislav Michl]

Convert IGEP board to use UBI volumes for U-Boot, its environment and
kernel. With exception of first four sectors read by SoC boot
ROM whole NAND is UBI managed. As code is too big now, drop
CONFIG_SPL_EXT_SUPPORT to make it fit.

Signed-off-by: Ladislav Michl 
---
 include/configs/omap3_igep00x0.h | 80 ++--
 1 file changed, 45 insertions(+), 35 deletions(-)

diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 5da6cfd..9afbcbe 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -74,6 +74,8 @@
 #define CONFIG_CMD_CACHE
 #ifdef CONFIG_BOOT_ONENAND
 #define CONFIG_CMD_ONENAND /* ONENAND support  */
+#else
+#define CONFIG_CMD_UBI
 #endif
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PING
@@ -86,6 +88,10 @@
"stdout=serial\0" \
"stderr=serial\0"
 
+#define ENV_MTD_SETTINGS \
+   "mtdids=nand0=gpmc-nand.0\0" \
+   "mtdparts=mtdparts=gpmc-nand.0:512k(SPL),-(UBI)\0"
+
 #define MEM_LAYOUT_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
"scriptaddr=0x87E0\0" \
@@ -96,36 +102,15 @@
 
 #include 
 
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
ENV_DEVICE_SETTINGS \
+   ENV_MTD_SETTINGS \
MEM_LAYOUT_SETTINGS \
BOOTENV
 
 #endif
 
 /*
- * FLASH and environment organization
- */
-
-#ifdef CONFIG_BOOT_ONENAND
-#define CONFIG_SYS_ONENAND_BASEONENAND_MAP
-
-#define ONENAND_ENV_OFFSET 0x26 /* environment starts here */
-
-#define CONFIG_ENV_IS_IN_ONENAND   1
-#define CONFIG_ENV_SIZE(512 << 10) /* Total Size 
Environment */
-#define CONFIG_ENV_ADDRONENAND_ENV_OFFSET
-#endif
-
-#ifdef CONFIG_NAND
-#define CONFIG_ENV_OFFSET  0x26 /* environment starts here */
-#define CONFIG_ENV_IS_IN_NAND  1
-#define CONFIG_ENV_SIZE(512 << 10) /* Total Size 
Environment */
-#define CONFIG_ENV_ADDRNAND_ENV_OFFSET
-#endif
-
-/*
  * SMSC911x Ethernet
  */
 #if defined(CONFIG_CMD_NET)
@@ -134,19 +119,50 @@
 #define CONFIG_SMC911X_BASE0x2C00
 #endif /* (CONFIG_CMD_NET) */
 
+/*
+ * FLASH and environment organization
+ */
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_UBI 1
+#define CONFIG_SPL_UBI_MAX_VOL_LEBS256
+#define CONFIG_SPL_UBI_MAX_PEB_SIZE(256*1024)
+#define CONFIG_SPL_UBI_MAX_PEBS4096
+#define CONFIG_SPL_UBI_VOL_IDS 8
+#define CONFIG_SPL_UBI_LOAD_MONITOR_ID 0
+#define CONFIG_SPL_UBI_LOAD_KERNEL_ID  3
+#define CONFIG_SPL_UBI_LOAD_ARGS_ID4
+#define CONFIG_SPL_UBI_PEB_OFFSET  4
+#define CONFIG_SPL_UBI_VID_OFFSET  512
+#define CONFIG_SPL_UBI_LEB_START   2048
+#define CONFIG_SPL_UBI_INFO_ADDR   0x8808
+
+#define CONFIG_ENV_IS_IN_UBI   1
+#define CONFIG_ENV_UBI_PART"UBI"
+#define CONFIG_ENV_UBI_VOLUME  "config"
+#define CONFIG_ENV_UBI_VOLUME_REDUND   "config_r"
+#define CONFIG_UBI_SILENCE_MSG 1
+#define CONFIG_UBIFS_SILENCE_MSG   1
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#define CONFIG_ENV_SIZE(32*1024)
+
+#define CONFIG_RBTREE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=gpmc-nand.0"
+#define MTDPARTS_DEFAULT   "mtdparts=gpmc-nand.0:512k(SPL),-(UBI)"
+
 /* OneNAND boot config */
 #ifdef CONFIG_BOOT_ONENAND
 #define CONFIG_SPL_ONENAND_SUPPORT
-#define CONFIG_SYS_ONENAND_U_BOOT_OFFS  0x8
 #define CONFIG_SYS_ONENAND_PAGE_SIZE   2048
-#define CONFIG_SPL_ONENAND_LOAD_ADDR0x8
-#define CONFIG_SPL_ONENAND_LOAD_SIZE\
-   (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
-
+#define CONFIG_SYS_ONENAND_BASEONENAND_MAP
+#define CONFIG_SYS_ONENAND_U_BOOT_OFFS 0x8
 #endif
 
 /* NAND boot config */
 #ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT 64
@@ -166,14 +182,8 @@
 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
 #define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_BCH
-
-#define CONFIG_SYS_NAND_U_BOOT_OFFS0x8
-/* NAND: SPL falcon mode configs */
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_CMD_SPL_NAND_OFS0x24
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS0x28
-#define CONFIG_CMD_SPL_WRITE_SIZE  0x2000
-#endif
 #endif
 
+#undef CONFIG_SPL_EXT_SUPPORT
+
 #endif /* __IGEP00X0_H */
-- 
2.1.4

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[U-Boot] [PATCHv4 7/7] igep00x0: Falcon mode

[Ladislav Michl]

Implement spl_start_uboot to let Falcon mode work.

Signed-off-by: Ladislav Michl 
---
 board/isee/igep00x0/igep00x0.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index e2fce50..92811d8 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -212,3 +213,14 @@ int board_eth_init(bd_t *bis)
 #endif
 }
 #endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+   /* break into full u-boot on 'c' */
+   if (serial_tstc() && serial_getc() == 'c')
+   return 1;
+
+   return 0;
+}
+#endif
-- 
2.1.4

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Re: [U-Boot] [PATCH v7 0/7] add support for atheros ath79 based SOCs

[Wills Wang]

On 01/17/2016 03:05 AM, Marek Vasut wrote:

On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote:

These series of patch add support for atheros ath79 based SOCs in u-boot,
at the present moment it's just available for ar933x and qca953x chip.

This patch serises is based on mips_io_v4 branch on u-boot-mips repository
[1] and tested on ar933x and qca953x board.

[1]
http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads/mips_
io_v4

So if I didn't complain about this being sent as separate emails this morning.
Please, do send your patches as a series, not as separate emails.

How to send a patch series by patman?

Best regards,
Marek Vasut


--
Best Regards
Wills

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[U-Boot] [PATCH] drivers/power/regulator/max77686.c: Don't use switch() on bools

[Tom Rini]

With gcc-5.3 we get a warning for using switch() on a bool type.
Rewrite these sections as if/else and update the one section that was
using 1/0 instead of true/false.

Cc: Simon Glass 
Cc: Przemyslaw Marczak 
Signed-off-by: Tom Rini 
---
 drivers/power/regulator/max77686.c | 28 
 1 file changed, 8 insertions(+), 20 deletions(-)

diff --git a/drivers/power/regulator/max77686.c 
b/drivers/power/regulator/max77686.c
index 71678b6..7479af7 100644
--- a/drivers/power/regulator/max77686.c
+++ b/drivers/power/regulator/max77686.c
@@ -515,25 +515,19 @@ static int max77686_ldo_enable(struct udevice *dev, int 
op, bool *enable)
 
switch (on_off) {
case OPMODE_OFF:
-   *enable = 0;
+   *enable = false;
break;
case OPMODE_ON:
-   *enable = 1;
+   *enable = true;
break;
default:
return -EINVAL;
}
} else if (op == PMIC_OP_SET) {
-   switch (*enable) {
-   case 0:
-   on_off = OPMODE_OFF;
-   break;
-   case 1:
+   if (*enable)
on_off = OPMODE_ON;
-   break;
-   default:
-   return -EINVAL;
-   }
+   else
+   on_off = OPMODE_OFF;
 
ret = max77686_ldo_mode(dev, op, _off);
if (ret)
@@ -651,16 +645,10 @@ static int max77686_buck_enable(struct udevice *dev, int 
op, bool *enable)
return -EINVAL;
}
} else if (op == PMIC_OP_SET) {
-   switch (*enable) {
-   case 0:
-   on_off = OPMODE_OFF;
-   break;
-   case 1:
+   if (*enable)
on_off = OPMODE_ON;
-   break;
-   default:
-   return -EINVAL;
-   }
+   else
+   on_off = OPMODE_OFF;
 
ret = max77686_buck_mode(dev, op, _off);
if (ret)
-- 
2.7.0.rc3

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[U-Boot] [PATCH 3/6] usb: dwc2: split transfer core from outer loop

[Stefan Brüns]

Split the movement of data between CPU and Host Controller from the
status handling and tracking of transfer progress.
This will also simplify adding of SPLIT transaction support.

Signed-off-by: Stefan Brüns 
---
 drivers/usb/host/dwc2.c | 112 +++-
 1 file changed, 64 insertions(+), 48 deletions(-)

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index ad097cb..0e710d9 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -426,9 +426,6 @@ static void dwc_otg_hc_init(struct dwc2_core_regs *regs, 
uint8_t hc_num,
if (dev->speed == USB_SPEED_LOW)
hcchar |= DWC2_HCCHAR_LSPDDEV;
 
-   /* Clear old interrupt conditions for this host channel. */
-   writel(0x3fff, _regs->hcint);
-
/*
 * Program the HCCHARn register with the endpoint characteristics
 * for the current transfer.
@@ -729,9 +726,8 @@ static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, 
struct usb_device *dev,
return stat;
 }
 
-int wait_for_chhltd(struct dwc2_core_regs *regs, uint32_t *sub, int *toggle)
+int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, int *toggle)
 {
-   struct dwc2_hc_regs *hc_regs = >hc_regs[DWC2_HC_CHANNEL];
int ret;
uint32_t hcint, hctsiz;
 
@@ -765,6 +761,58 @@ static int dwc2_eptype[] = {
DWC2_HCCHAR_EPTYPE_BULK,
 };
 
+static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
+ int *pid, int in, void *buffer, int num_packets,
+ int xfer_len, int *actual_len)
+{
+   int ret = 0;
+   uint32_t sub;
+
+   debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
+ *pid, xfer_len, num_packets);
+
+   writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
+  (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
+  (*pid << DWC2_HCTSIZ_PID_OFFSET),
+  _regs->hctsiz);
+
+   if (!in && xfer_len) {
+   memcpy(aligned_buffer, buffer, xfer_len);
+
+   flush_dcache_range((unsigned long)aligned_buffer,
+  (unsigned long)aligned_buffer +
+  roundup(xfer_len, ARCH_DMA_MINALIGN));
+   }
+
+   writel(phys_to_bus((unsigned long)aligned_buffer), _regs->hcdma);
+
+   /* Clear old interrupt conditions for this host channel. */
+   writel(0x3fff, _regs->hcint);
+
+   /* Set host channel enable after all other setup is complete. */
+   clrsetbits_le32(_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
+   DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
+   (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
+   DWC2_HCCHAR_CHEN);
+
+   ret = wait_for_chhltd(hc_regs, , pid);
+   if (ret < 0)
+   return ret;
+
+   if (in) {
+   xfer_len -= sub;
+
+   invalidate_dcache_range((unsigned long)aligned_buffer,
+   (unsigned long)aligned_buffer +
+   roundup(xfer_len, ARCH_DMA_MINALIGN));
+
+   memcpy(buffer, aligned_buffer, xfer_len);
+   }
+   *actual_len = xfer_len;
+
+   return ret;
+}
+
 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
  unsigned long pipe, int *pid, int in, void *buffer, int len)
 {
@@ -776,7 +824,6 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device 
*dev,
int eptype = dwc2_eptype[usb_pipetype(pipe)];
int done = 0;
int ret = 0;
-   uint32_t sub;
uint32_t xfer_len;
uint32_t num_packets;
int stop_transfer = 0;
@@ -795,11 +842,12 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device 
*dev,
num_packets = max_xfer_len / max;
max_xfer_len = num_packets * max;
 
-   do {
-   /* Initialize channel */
-   dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
-   eptype, max);
+   /* Initialize channel */
+   dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
+   eptype, max);
 
+   do {
+   int actual_len = 0;
xfer_len = len - done;
 
if (xfer_len > max_xfer_len)
@@ -809,49 +857,17 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device 
*dev,
else
num_packets = 1;
 
-   debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
- *pid, xfer_len, num_packets);
+   ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
+in, (char *)buffer + done, num_packets,
+xfer_len, _len);
 
-   writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
-  (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
- 

[U-Boot] [PATCH 0/6] usb: dwc2: Add support for SPLIT transactions

[Stefan Brüns]

The first patch fixes an out-of-bounds access, and makes the calculation of
maximum transfer size more straightforward. It also makes overriding the
maximum transfer size easier for split transactions

2nd and 3rd patch cleanup and restructure the current code in preparation
for the split support.

Patch 4 and 5 add the actual support for CONTROL and BULK transactions.

Patch 6 adds support for INTERUPT splits.

The patch series uses the same logic as the earlier patch series, but is
otherwise a rewrite.

With the patch series, all my LS/FS devices enumerate behind the RPi 1
onboard hub and an external hub.

Interrupt transfers have been tested with a Logitech K400 and a noname wired
keyboard. Both work if "stdin" includes usbkbd prior to usb start, and u-boot
has been configured with CONFIG_USB_KEYBOARD=y and CONFIG_SYS_USB_EVENT_POLL=y
(but only one at a time).

Stefan Brüns (6):
  usb: dwc2: Fix out-of-bounds access, fix chunk size
  usb: dwc2: Simplify wait_for_chhltd(), remove ignore_ack
  usb: dwc2: split transfer core from outer loop
  usb: dwc2: add helper function for setting SPLIT HC registers
  usb: dwc2: Implement SPLIT transaction support
  usb: dwc2: Add SPLIT INTERRUPT transaction support

 drivers/usb/host/dwc2.c | 280 
 drivers/usb/host/dwc2.h |   1 +
 2 files changed, 187 insertions(+), 94 deletions(-)

-- 
2.1.4

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[U-Boot] [PATCHv4 0/7] spl: Lightweight UBI and UBI fastmap support

[Ladislav Michl]

Hi,

yet another update of ubispl support. Please note, that igep00x0 specific
part depends on yet unapplied "[PATCHv2 0/5] igep00x0: Minor cleanup"
series

---
 README |4
 arch/arm/lib/Makefile  |2
 arch/arm/lib/bootm.c   |   32 -
 arch/arm/lib/zimage.c  |   40 +
 board/isee/igep00x0/igep00x0.c |   12
 common/spl/Makefile|3
 common/spl/spl.c   |   27 +
 common/spl/spl_ubi.c   |   68 ++
 doc/README.ubispl  |  141 +
 drivers/Makefile   |5
 drivers/mtd/nand/nand_spl_simple.c |   62 ++
 drivers/mtd/ubispl/Makefile|1
 drivers/mtd/ubispl/ubi-wrapper.h   |  106 
 drivers/mtd/ubispl/ubispl.c|  926 +
 drivers/mtd/ubispl/ubispl.h|  136 +
 include/configs/omap3_igep00x0.h   |   80 +--
 include/nand.h |1
 include/spl.h  |4
 include/ubispl.h   |   90 +++

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Re: [U-Boot] [PATCH 00/23] dm: tegra: Convert tegra20 and tegra124 video drivers to driver model

[Marcel Ziswiler]

Hi Simon

On Thu, 2016-01-14 at 11:28 -0700, Simon Glass wrote:
> This series moves these two drivers over to use driver model for
> video.
> 
> This involves the following steps:
> - Sync up some device tree files with Linux
> - Implement a proper PWM driver
> - Clean up and unify the driver code
> - Modify the existing drivers to work with driver model
> 
> The tegra20 display driver uses device tree bindings invented in 2011
> before
> Linux had this or anyone was able to agree a standard. It seems
> possible to
> move it to the new bindings (like tegra124) except for the issue of
> time
> delays between stages. It isn't clear how this should work, and Linux
> implements this by including all LCD definitions in the kernel source
> code,
> and not using any delays. This causes strange display artifacts on
> the
> display when starting up, but perhaps is harmless to the display.
> Future
> work will sync up the device tree more for seaboard, and thus tidy
> this up
> for nvidia boards.
> 
> A bug in the keyboard driver is also fixed by this series. The series
> is
> tested on seaboard and nyan-big, the two boards I have which support
> a
> display.

I wanted to give that patch set a shot but could not figure out against
what to get it cleanly applied. Could you reveal its baseline or better
yet a git branch ready for testing?


> Simon Glass (23):
>   tegra: keyboard: Fix the init order
>   dm: video: Flush the cache after a puts()
>   tegra: mmc: Fix comments in the MMC driver init
>   tegra: dts: Sync up the tegra124 device tree files with Linux
>   tegra: dts: Sync up nyan-big files with Linux
>   tegra: gpio: Show the GPIO value for outputs
>   tegra: pwm: Add a driver for the tegra PWM
>   tegra: lcd: Merge tegra124-lcd.c into display.c
>   tegra: Allow driver model to be used for the PWM
>   tegra: Allow CONFIG_DM_VIDEO to be used as well as CONFIG_LCD
>   tegra: nyan-big: Move the LCD driver to driver model
>   tegra: video: Rename CONFIG_VIDEO_TEGRA to CONFIG_VIDEO_TEGRA20
>   tegra: dts: Sync tegra20.dtsi with Linux v4.4
>   tegra: video: Merge the display driver into one file
>   tegra: video: Move the check for CONFIG_OF_CONTROL to Kconfig
>   tegra: video: Merge the two config structures together
>   tegra: video: Convert tegra20 LCD driver to driver model
>   tegra: video: Remove the static variables
>   tegra: video: Move LCD enums into the driver
>   tegra: video: Move all fdt-decoding into a single function
>   tegra: Convert CONFIG_PWM_TEGRA to Kconfig
>   tegra: video: Move LCD driver to use the DM PWM driver
>   tegra: video: Clean up the old LCD/PWM driver code
> 
>  arch/arm/dts/tegra124-jetson-tk1.dts|   13 +
>  arch/arm/dts/tegra124-nyan-big.dts  | 1676
> ++-
>  arch/arm/dts/tegra124-nyan.dtsi |  718 ++
>  arch/arm/dts/tegra124-venice2.dts   |   14 +
>  arch/arm/dts/tegra124.dtsi  |  693 --
>  arch/arm/dts/tegra20-colibri.dts|   22 +-
>  arch/arm/dts/tegra20-harmony.dts|   44 +-
>  arch/arm/dts/tegra20-medcom-wide.dts|   26 +-
>  arch/arm/dts/tegra20-paz00.dts  |   43 +-
>  arch/arm/dts/tegra20-plutux.dts |8 -
>  arch/arm/dts/tegra20-seaboard.dts   |   36 +-
>  arch/arm/dts/tegra20-tamonten.dtsi  |   15 +-
>  arch/arm/dts/tegra20-tec.dts|   10 +-
>  arch/arm/dts/tegra20-trimslice.dts  |   34 +-
>  arch/arm/dts/tegra20-ventana.dts|   43 +-
>  arch/arm/dts/tegra20-whistler.dts   |   35 +-
>  arch/arm/dts/tegra20.dtsi   |  541 ++--
>  arch/arm/include/asm/arch-tegra/dc.h|5 -
>  arch/arm/include/asm/arch-tegra/pwm.h   |   30 -
>  arch/arm/include/asm/arch-tegra20/display.h |  108 --
>  arch/arm/mach-tegra/Kconfig |1 +
>  arch/arm/mach-tegra/Makefile|1 -
>  arch/arm/mach-tegra/board2.c|   24 +-
>  arch/arm/mach-tegra/pwm.c   |   89 --
>  arch/arm/mach-tegra/tegra20/Makefile|2 -
>  arch/arm/mach-tegra/tegra20/display.c   |  378 -
>  board/compal/paz00/paz00.c  |2 +-
>  board/toradex/colibri_t20/colibri_t20.c |2 +-
>  configs/colibri_t20_defconfig   |   13 +-
>  configs/harmony_defconfig   |6 +
>  configs/medcom-wide_defconfig   |6 +
>  configs/nyan-big_defconfig  |   11 +-
>  configs/paz00_defconfig |6 +
>  configs/seaboard_defconfig  |6 +
>  configs/tec_defconfig   |6 +
>  configs/ventana_defconfig   |6 +
>  drivers/gpio/tegra_gpio.c   |5 +-
>  drivers/input/tegra-kbc.c   |2 +-
>  

Re: [U-Boot] [PATCH] udoo:use load instead of fatload

[Fabio Estevam]

On Fri, Jan 15, 2016 at 6:12 PM, Oscar Curero  wrote:
> That way the FS can also be ext2/3/4
>
> Signed-off-by: Oscar Curero 

Acked-by: Fabio Estevam 
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Re: [U-Boot] [PATCH v4 02/19] dm: timer: uclass: add timer init in uclass driver to add timer device

[Mugunthan V N]

On Saturday 16 January 2016 09:33 PM, Mugunthan V N wrote:
> Adding timer init function in timer-uclass driver to create and
> initialize the timer device on platforms where u-boot,dm-pre-reloc
> is not used. Since there will be multiple timer devices in the
> system, adding a tick-timer node in chosen node to know which
> timer device to be used as tick timer in u-boot.
> 
> Signed-off-by: Mugunthan V N 

Please drop this patch, will send a fixup patch as the series is already
applied to u-boot-dm tree.

Regards
Mugunthan V N
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Re: [U-Boot] [PATCH v6 06/10] ns16550: add support for mips

[Wills Wang]

On Saturday, January 09, 2016 10:30 PM, Daniel Schwierzeck wrote:

Am Samstag, den 09.01.2016, 18:46 +0800 schrieb Wills Wang:

On 01/09/2016 12:23 AM, Daniel Schwierzeck wrote:

Am Montag, den 04.01.2016, 19:14 +0800 schrieb Wills Wang:

MIPS archtecture have no "in_le32/in_be32/out_le32/out_be32"
macro,
but usually define CONFIG_SYS_BIG_ENDIAN, this patch use
readl/writel
for register operation in mips when define
CONFIG_SYS_NS16550_MEM32.

Signed-off-by: Wills Wang 
---

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

   drivers/serial/ns16550.c | 24 
   1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 3fab3f1..3b24af0 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -64,12 +64,16 @@ static inline void serial_out_shift(void
*addr,
int shift, int value)
   {
   #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
outb(value, (ulong)addr);
-#elif defined(CONFIG_SYS_NS16550_MEM32) &&
!defined(CONFIG_SYS_BIG_ENDIAN)
-   out_le32(addr, value);
-#elif defined(CONFIG_SYS_NS16550_MEM32) &&
defined(CONFIG_SYS_BIG_ENDIAN)
-   out_be32(addr, value);
   #elif defined(CONFIG_SYS_NS16550_MEM32)
+#ifdef CONFIG_MIPS
writel(value, addr);
+#else
+#ifndef CONFIG_SYS_BIG_ENDIAN
+   out_le32(addr, value);
+#else
+   out_be32(addr, value);
+#endif
+#endif
   #elif defined(CONFIG_SYS_BIG_ENDIAN)
writeb(value, addr + (1 << shift) - 1);
   #else
@@ -81,12 +85,16 @@ static inline int serial_in_shift(void *addr,
int
shift)
   {
   #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
return inb((ulong)addr);
-#elif defined(CONFIG_SYS_NS16550_MEM32) &&
!defined(CONFIG_SYS_BIG_ENDIAN)
-   return in_le32(addr);
-#elif defined(CONFIG_SYS_NS16550_MEM32) &&
defined(CONFIG_SYS_BIG_ENDIAN)
-   return in_be32(addr);
   #elif defined(CONFIG_SYS_NS16550_MEM32)
+#ifdef CONFIG_MIPS
return readl(addr);
+#else
+#ifndef CONFIG_SYS_BIG_ENDIAN
+   return in_le32(addr);
+#else
+   return in_be32(addr);
+#endif
+#endif
   #elif defined(CONFIG_SYS_BIG_ENDIAN)
return readb(addr + (1 << shift) - 1);
   #else

Could you tell us, if you need port IO or MMIO. In case of MMIO do
you
need 8 bit or 32 bit I/O access?

Becasue your CPU is running in Big Endian and the NS16550 is Little
Endian, you need endianess conversion in the 32 bit case.

The 8 bit access should already work without changing anything. The
MIPS Malta board also uses NS16550 and already works in Bit Endian
mode.

To make the 32 bit case working, you need to select
CONFIG_SWAP_IO_SPACE in your SoC Kconfig code. Then all
readl/writel
accessors do an endianess conversion to Little Endian if the CPU is
running in Big Endian.

Anyway I think the current implementation is wrong:

static inline void serial_out_shift(void *addr, int shift, int
value)
{
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
outb(value, (ulong)addr);
#elif defined(CONFIG_SYS_NS16550_MEM32) &&
!defined(CONFIG_SYS_BIG_ENDIAN)
out_le32(addr, value);
#elif defined(CONFIG_SYS_NS16550_MEM32) &&
defined(CONFIG_SYS_BIG_ENDIAN)
out_be32(addr, value);
#elif defined(CONFIG_SYS_NS16550_MEM32)
writel(value, addr);
#elif defined(CONFIG_SYS_BIG_ENDIAN)
writeb(value, addr + (1 << shift) - 1);
#else
writeb(value, addr);
#endif
}

The branch with writel() will never be taken because the two
preceding
branches already catch all conditions for CONFIG_SYS_NS16550_MEM32.
Also if the NS16550 is Little Endian, the branch with out_be32
makes no
sense. All IO accessors must convert from CPU endianess to
NS16550's
Little Endian, but out_be32 converts from CPU endianess to Big
Endian.

To handle port IO, 32 Bit MMIO and 8 Bit MMIO, following code
should be
enough:

static inline void serial_out_shift(void *addr, int shift, int
value)
{
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
outb(value, (ulong)addr);
#elif defined(CONFIG_SYS_NS16550_MEM32)
writel(value, addr);
#elif defined(CONFIG_SYS_BIG_ENDIAN)
writeb(value, addr + (1 << shift) - 1);
#else
writeb(value, addr);
#endif
}

The arch-specific implementation of readl/writel should be
responsible
for the endianess conversion and not the driver. What do you think?


I wholly agree with Daniel, driver should not care the endianness, we
need a general mechanism to deal with this situation, no matter the
endianness of CPU and peripheral IP Core.
But CONFIG_SWAP_IO_SPACE don't resolve this issue, NS16550 is just
one of many peripherals for CPU.
NS16550 use only 8bit register field even if in 32 bit MMIO. In
actual,
driver may just concern the register offset beause the bit field of
register in chip datasheet is coincident with CPU endianness, even
though hardware support both big-endian and little-endian, so the
optimal code should be the following:
static inline void serial_out_shift(void *addr, int 

Re: [U-Boot] [PATCH v4 02/19] dm: timer: uclass: add timer init in uclass driver to add timer device

[Simon Glass]

Hi Mugunthan,

On 16 January 2016 at 09:08, Mugunthan V N  wrote:
> On Saturday 16 January 2016 09:33 PM, Mugunthan V N wrote:
>> Adding timer init function in timer-uclass driver to create and
>> initialize the timer device on platforms where u-boot,dm-pre-reloc
>> is not used. Since there will be multiple timer devices in the
>> system, adding a tick-timer node in chosen node to know which
>> timer device to be used as tick timer in u-boot.
>>
>> Signed-off-by: Mugunthan V N 
>
> Please drop this patch, will send a fixup patch as the series is already
> applied to u-boot-dm tree.

You can send a new patch if you like and I can replace it. Either works for me.

Regards,
Simon
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Re: [U-Boot] [PATCH v6 06/10] ns16550: add support for mips

[Daniel Schwierzeck]

Am Sonntag, den 17.01.2016, 00:15 +0800 schrieb Wills Wang:
> 
> On Saturday, January 09, 2016 10:30 PM, Daniel Schwierzeck wrote:
> > Am Samstag, den 09.01.2016, 18:46 +0800 schrieb Wills Wang:
> > > On 01/09/2016 12:23 AM, Daniel Schwierzeck wrote:
> > > > Am Montag, den 04.01.2016, 19:14 +0800 schrieb Wills Wang:
> > > > > MIPS archtecture have no "in_le32/in_be32/out_le32/out_be32"
> > > > > macro,
> > > > > but usually define CONFIG_SYS_BIG_ENDIAN, this patch use
> > > > > readl/writel
> > > > > for register operation in mips when define
> > > > > CONFIG_SYS_NS16550_MEM32.
> > > > > 
> > > > > Signed-off-by: Wills Wang 
> > > > > ---
> > > > > 
> > > > > Changes in v6: None
> > > > > Changes in v5: None
> > > > > Changes in v4: None
> > > > > Changes in v3: None
> > > > > Changes in v2: None
> > > > > 
> > > > >drivers/serial/ns16550.c | 24 
> > > > >1 file changed, 16 insertions(+), 8 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/serial/ns16550.c
> > > > > b/drivers/serial/ns16550.c
> > > > > index 3fab3f1..3b24af0 100644
> > > > > --- a/drivers/serial/ns16550.c
> > > > > +++ b/drivers/serial/ns16550.c
> > > > > @@ -64,12 +64,16 @@ static inline void serial_out_shift(void
> > > > > *addr,
> > > > > int shift, int value)
> > > > >{
> > > > >#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
> > > > >   outb(value, (ulong)addr);
> > > > > -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
> > > > > !defined(CONFIG_SYS_BIG_ENDIAN)
> > > > > - out_le32(addr, value);
> > > > > -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
> > > > > defined(CONFIG_SYS_BIG_ENDIAN)
> > > > > - out_be32(addr, value);
> > > > >#elif defined(CONFIG_SYS_NS16550_MEM32)
> > > > > +#ifdef CONFIG_MIPS
> > > > >   writel(value, addr);
> > > > > +#else
> > > > > +#ifndef CONFIG_SYS_BIG_ENDIAN
> > > > > + out_le32(addr, value);
> > > > > +#else
> > > > > + out_be32(addr, value);
> > > > > +#endif
> > > > > +#endif
> > > > >#elif defined(CONFIG_SYS_BIG_ENDIAN)
> > > > >   writeb(value, addr + (1 << shift) - 1);
> > > > >#else
> > > > > @@ -81,12 +85,16 @@ static inline int serial_in_shift(void
> > > > > *addr,
> > > > > int
> > > > > shift)
> > > > >{
> > > > >#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
> > > > >   return inb((ulong)addr);
> > > > > -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
> > > > > !defined(CONFIG_SYS_BIG_ENDIAN)
> > > > > - return in_le32(addr);
> > > > > -#elif defined(CONFIG_SYS_NS16550_MEM32) &&
> > > > > defined(CONFIG_SYS_BIG_ENDIAN)
> > > > > - return in_be32(addr);
> > > > >#elif defined(CONFIG_SYS_NS16550_MEM32)
> > > > > +#ifdef CONFIG_MIPS
> > > > >   return readl(addr);
> > > > > +#else
> > > > > +#ifndef CONFIG_SYS_BIG_ENDIAN
> > > > > + return in_le32(addr);
> > > > > +#else
> > > > > + return in_be32(addr);
> > > > > +#endif
> > > > > +#endif
> > > > >#elif defined(CONFIG_SYS_BIG_ENDIAN)
> > > > >   return readb(addr + (1 << shift) - 1);
> > > > >#else
> > > > Could you tell us, if you need port IO or MMIO. In case of MMIO
> > > > do
> > > > you
> > > > need 8 bit or 32 bit I/O access?
> > > > 
> > > > Becasue your CPU is running in Big Endian and the NS16550 is
> > > > Little
> > > > Endian, you need endianess conversion in the 32 bit case.
> > > > 
> > > > The 8 bit access should already work without changing anything.
> > > > The
> > > > MIPS Malta board also uses NS16550 and already works in Bit
> > > > Endian
> > > > mode.
> > > > 
> > > > To make the 32 bit case working, you need to select
> > > > CONFIG_SWAP_IO_SPACE in your SoC Kconfig code. Then all
> > > > readl/writel
> > > > accessors do an endianess conversion to Little Endian if the
> > > > CPU is
> > > > running in Big Endian.
> > > > 
> > > > Anyway I think the current implementation is wrong:
> > > > 
> > > > static inline void serial_out_shift(void *addr, int shift, int
> > > > value)
> > > > {
> > > > #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
> > > > outb(value, (ulong)addr);
> > > > #elif defined(CONFIG_SYS_NS16550_MEM32) &&
> > > > !defined(CONFIG_SYS_BIG_ENDIAN)
> > > > out_le32(addr, value);
> > > > #elif defined(CONFIG_SYS_NS16550_MEM32) &&
> > > > defined(CONFIG_SYS_BIG_ENDIAN)
> > > > out_be32(addr, value);
> > > > #elif defined(CONFIG_SYS_NS16550_MEM32)
> > > > writel(value, addr);
> > > > #elif defined(CONFIG_SYS_BIG_ENDIAN)
> > > > writeb(value, addr + (1 << shift) - 1);
> > > > #else
> > > > writeb(value, addr);
> > > > #endif
> > > > }
> > > > 
> > > > The branch with writel() will never be taken because the two
> > > > preceding
> > > > branches already catch all conditions for
> > > > CONFIG_SYS_NS16550_MEM32.
> > > > Also if the NS16550 is Little Endian, the branch with out_be32
> > > > makes no
> > > > sense. All IO accessors must convert from CPU endianess to
> > > > NS16550's
> > > > Little Endian, but out_be32 converts from CPU endianess to 

Re: [U-Boot] [PATCH v4 02/19] dm: timer: uclass: add timer init in uclass driver to add timer device

[Mugunthan V N]

On Saturday 16 January 2016 10:11 PM, Simon Glass wrote:
> Hi Mugunthan,
> 
> On 16 January 2016 at 09:08, Mugunthan V N  wrote:
>> On Saturday 16 January 2016 09:33 PM, Mugunthan V N wrote:
>>> Adding timer init function in timer-uclass driver to create and
>>> initialize the timer device on platforms where u-boot,dm-pre-reloc
>>> is not used. Since there will be multiple timer devices in the
>>> system, adding a tick-timer node in chosen node to know which
>>> timer device to be used as tick timer in u-boot.
>>>
>>> Signed-off-by: Mugunthan V N 
>>
>> Please drop this patch, will send a fixup patch as the series is already
>> applied to u-boot-dm tree.
> 
> You can send a new patch if you like and I can replace it. Either works for 
> me.
> 

Just sent a follow-up patch. Its good to not change the pushed history.

Regards
Mugunthan V N

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Re: [U-Boot] [PATCH 00/23] dm: tegra: Convert tegra20 and tegra124 video drivers to driver model

[Simon Glass]

Hi Marcel,

On 15 January 2016 at 19:36, Marcel Ziswiler
 wrote:
> Hi Simon
>
> On Thu, 2016-01-14 at 11:28 -0700, Simon Glass wrote:
>> This series moves these two drivers over to use driver model for
>> video.
>>
>> This involves the following steps:
>> - Sync up some device tree files with Linux
>> - Implement a proper PWM driver
>> - Clean up and unify the driver code
>> - Modify the existing drivers to work with driver model
>>
>> The tegra20 display driver uses device tree bindings invented in 2011
>> before
>> Linux had this or anyone was able to agree a standard. It seems
>> possible to
>> move it to the new bindings (like tegra124) except for the issue of
>> time
>> delays between stages. It isn't clear how this should work, and Linux
>> implements this by including all LCD definitions in the kernel source
>> code,
>> and not using any delays. This causes strange display artifacts on
>> the
>> display when starting up, but perhaps is harmless to the display.
>> Future
>> work will sync up the device tree more for seaboard, and thus tidy
>> this up
>> for nvidia boards.
>>
>> A bug in the keyboard driver is also fixed by this series. The series
>> is
>> tested on seaboard and nyan-big, the two boards I have which support
>> a
>> display.
>
> I wanted to give that patch set a shot but could not figure out against
> what to get it cleanly applied. Could you reveal its baseline or better
> yet a git branch ready for testing?

Yes, this plus the next series is at u-boot-dm/rkf-working. Sorry I
didn't point that out.

>
>
>> Simon Glass (23):
>>   tegra: keyboard: Fix the init order
>>   dm: video: Flush the cache after a puts()
>>   tegra: mmc: Fix comments in the MMC driver init
>>   tegra: dts: Sync up the tegra124 device tree files with Linux
>>   tegra: dts: Sync up nyan-big files with Linux
>>   tegra: gpio: Show the GPIO value for outputs
>>   tegra: pwm: Add a driver for the tegra PWM
>>   tegra: lcd: Merge tegra124-lcd.c into display.c
>>   tegra: Allow driver model to be used for the PWM
>>   tegra: Allow CONFIG_DM_VIDEO to be used as well as CONFIG_LCD
>>   tegra: nyan-big: Move the LCD driver to driver model
>>   tegra: video: Rename CONFIG_VIDEO_TEGRA to CONFIG_VIDEO_TEGRA20
>>   tegra: dts: Sync tegra20.dtsi with Linux v4.4
>>   tegra: video: Merge the display driver into one file
>>   tegra: video: Move the check for CONFIG_OF_CONTROL to Kconfig
>>   tegra: video: Merge the two config structures together
>>   tegra: video: Convert tegra20 LCD driver to driver model
>>   tegra: video: Remove the static variables
>>   tegra: video: Move LCD enums into the driver
>>   tegra: video: Move all fdt-decoding into a single function
>>   tegra: Convert CONFIG_PWM_TEGRA to Kconfig
>>   tegra: video: Move LCD driver to use the DM PWM driver
>>   tegra: video: Clean up the old LCD/PWM driver code
>>
>>  arch/arm/dts/tegra124-jetson-tk1.dts|   13 +
>>  arch/arm/dts/tegra124-nyan-big.dts  | 1676
>> ++-
>>  arch/arm/dts/tegra124-nyan.dtsi |  718 ++
>>  arch/arm/dts/tegra124-venice2.dts   |   14 +
>>  arch/arm/dts/tegra124.dtsi  |  693 --
>>  arch/arm/dts/tegra20-colibri.dts|   22 +-
>>  arch/arm/dts/tegra20-harmony.dts|   44 +-
>>  arch/arm/dts/tegra20-medcom-wide.dts|   26 +-
>>  arch/arm/dts/tegra20-paz00.dts  |   43 +-
>>  arch/arm/dts/tegra20-plutux.dts |8 -
>>  arch/arm/dts/tegra20-seaboard.dts   |   36 +-
>>  arch/arm/dts/tegra20-tamonten.dtsi  |   15 +-
>>  arch/arm/dts/tegra20-tec.dts|   10 +-
>>  arch/arm/dts/tegra20-trimslice.dts  |   34 +-
>>  arch/arm/dts/tegra20-ventana.dts|   43 +-
>>  arch/arm/dts/tegra20-whistler.dts   |   35 +-
>>  arch/arm/dts/tegra20.dtsi   |  541 ++--
>>  arch/arm/include/asm/arch-tegra/dc.h|5 -
>>  arch/arm/include/asm/arch-tegra/pwm.h   |   30 -
>>  arch/arm/include/asm/arch-tegra20/display.h |  108 --
>>  arch/arm/mach-tegra/Kconfig |1 +
>>  arch/arm/mach-tegra/Makefile|1 -
>>  arch/arm/mach-tegra/board2.c|   24 +-
>>  arch/arm/mach-tegra/pwm.c   |   89 --
>>  arch/arm/mach-tegra/tegra20/Makefile|2 -
>>  arch/arm/mach-tegra/tegra20/display.c   |  378 -
>>  board/compal/paz00/paz00.c  |2 +-
>>  board/toradex/colibri_t20/colibri_t20.c |2 +-
>>  configs/colibri_t20_defconfig   |   13 +-
>>  configs/harmony_defconfig   |6 +
>>  configs/medcom-wide_defconfig   |6 +
>>  configs/nyan-big_defconfig  |   11 +-
>>  configs/paz00_defconfig |6 +
>>  

Re: [U-Boot] [PATCH] pci_rom.c: Fix may be used uninitialized warning

[Bin Meng]

On Sat, Jan 16, 2016 at 10:50 PM, Tom Rini  wrote:
> With gcc-5.x we get:
> drivers/pci/pci_rom.c: In function 'dm_pci_run_vga_bios':
> drivers/pci/pci_rom.c:352:3: warning: 'ram' may be used uninitialized in
> this function [-Wmaybe-uninitialized]
>
> While unconvinced that this can happen in practice (if we malloc we set
> alloced to true, it will be false otherwise), silence the compiler.
>
> Signed-off-by: Tom Rini 
> ---
>  drivers/pci/pci_rom.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Bin Meng 
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[U-Boot] [PATCH v4 02/19] dm: timer: uclass: add timer init in uclass driver to add timer device

[Mugunthan V N]

Adding timer init function in timer-uclass driver to create and
initialize the timer device on platforms where u-boot,dm-pre-reloc
is not used. Since there will be multiple timer devices in the
system, adding a tick-timer node in chosen node to know which
timer device to be used as tick timer in u-boot.

Signed-off-by: Mugunthan V N 
---
 doc/device-tree-bindings/chosen.txt | 43 
 drivers/timer/timer-uclass.c| 44 +
 include/timer.h |  9 
 lib/time.c  | 17 --
 4 files changed, 96 insertions(+), 17 deletions(-)
 create mode 100644 doc/device-tree-bindings/chosen.txt

Changes from v3:
* removed dm_timer_init() in lib/time.c as it doesn't add
  anything and simply calls uclass driver's init and also
  renamed timer_init() to dm_timer_init() as many platforms
  calls timer_init() before dm init.
* removed re-declaring of ret in dm_timer_init()

Tested this patch on DRA74x EVM  (logs [1]) with sleep 10 with
minicom timestamps and pushed a branch [2] for testing.

[1] - http://pastebin.ubuntu.com/14520385/
[2] - git://git.ti.com/~mugunthanvnm/ti-u-boot/mugunth-ti-u-boot.git dm-timer-v4

---

diff --git a/doc/device-tree-bindings/chosen.txt 
b/doc/device-tree-bindings/chosen.txt
new file mode 100644
index 000..bf9a30a
--- /dev/null
+++ b/doc/device-tree-bindings/chosen.txt
@@ -0,0 +1,43 @@
+The chosen node
+---
+The chosen node does not represent a real device, but serves as a place
+for passing data like which serial device to used to print the logs etc
+
+
+stdout-path property
+
+Device trees may specify the device to be used for boot console output
+with a stdout-path property under /chosen.
+
+Example
+---
+/ {
+   chosen {
+   stdout-path = "/serial@f00:115200";
+   };
+
+   serial@f00 {
+   compatible = "vendor,some-uart";
+   reg = <0xf00 0x10>;
+   };
+};
+
+tick-timer property
+---
+In a system there are multiple timers, specify which timer to be used
+as the tick-timer. Earlier it was hardcoded in the timer driver now
+since device tree has all the timer nodes. Specify which timer to be
+used as tick timer.
+
+Example
+---
+/ {
+   chosen {
+   tick-timer = "/timer2@f00";
+   };
+
+   timer2@f00 {
+   compatible = "vendor,some-timer";
+   reg = <0xf00 0x10>;
+   };
+};
diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index aca421b..0480178 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c
@@ -6,6 +6,8 @@
 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 
@@ -56,6 +58,48 @@ u64 timer_conv_64(u32 count)
return ((u64)gd->timebase_h << 32) | gd->timebase_l;
 }
 
+int notrace dm_timer_init(void)
+{
+   const void *blob = gd->fdt_blob;
+   struct udevice *dev = NULL;
+   int node;
+   int ret;
+
+   if (gd->timer)
+   return 0;
+
+   /* Check for a chosen timer to be used for tick */
+   node = fdtdec_get_chosen_node(blob, "tick-timer");
+   if (node < 0) {
+   /* No chosen timer, trying first available timer */
+   ret = uclass_first_device(UCLASS_TIMER, );
+   if (ret)
+   return ret;
+   if (!dev)
+   return -ENODEV;
+   } else {
+   if (uclass_get_device_by_of_offset(UCLASS_TIMER, node, )) {
+   /*
+* If the timer is not marked to be bound before
+* relocation, bind it anyway.
+*/
+   if (node > 0 &&
+   !lists_bind_fdt(gd->dm_root, blob, node, )) {
+   ret = device_probe(dev);
+   if (ret)
+   return ret;
+   }
+   }
+   }
+
+   if (dev) {
+   gd->timer = dev;
+   return 0;
+   }
+
+   return -ENODEV;
+}
+
 UCLASS_DRIVER(timer) = {
.id = UCLASS_TIMER,
.name   = "timer",
diff --git a/include/timer.h b/include/timer.h
index 7fee17e..f14725c 100644
--- a/include/timer.h
+++ b/include/timer.h
@@ -8,6 +8,15 @@
 #define _TIMER_H_
 
 /*
+ * dm_timer_init - initialize a timer for time keeping. On success
+ * initializes gd->timer so that lib/timer can use it for future
+ * referrence.
+ *
+ * @return - 0 on success or error number
+ */
+int dm_timer_init(void);
+
+/*
  * timer_conv_64 - convert 32-bit counter value to 64-bit
  *
  * @count: 32-bit counter value
diff --git a/lib/time.c b/lib/time.c
index f37a662..e9f6861 100644
--- a/lib/time.c
+++ b/lib/time.c
@@ -41,23 +41,6 @@ extern unsigned long __weak timer_read_counter(void);
 

[U-Boot] [PATCH v7 7/7] mips: ath79: add AP143 reference board

[Wills Wang]

Signed-off-by: Wills Wang 
---

Changes in v7:
- Use KSEG1 address for debug port in ap143

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/mips/dts/Makefile|  1 +
 arch/mips/dts/ap143.dts   | 43 
 arch/mips/dts/qca953x.dtsi| 72 ++
 arch/mips/mach-ath79/Kconfig  |  5 +++
 board/ath79/ap143/Kconfig |  9 +
 board/ath79/ap143/MAINTAINERS |  6 +++
 board/ath79/ap143/Makefile|  5 +++
 board/ath79/ap143/ap143.c | 63 ++
 configs/ap143_defconfig   | 43 
 include/configs/ap143.h   | 91 +++
 10 files changed, 338 insertions(+)
 create mode 100644 arch/mips/dts/ap143.dts
 create mode 100644 arch/mips/dts/qca953x.dtsi
 create mode 100644 board/ath79/ap143/Kconfig
 create mode 100644 board/ath79/ap143/MAINTAINERS
 create mode 100644 board/ath79/ap143/Makefile
 create mode 100644 board/ath79/ap143/ap143.c
 create mode 100644 configs/ap143_defconfig
 create mode 100644 include/configs/ap143.h

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 3fd49eb..7da06c5 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -3,6 +3,7 @@
 #
 
 dtb-$(CONFIG_BOARD_AP121) += ap121.dtb
+dtb-$(CONFIG_BOARD_AP143) += ap143.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/mips/dts/ap143.dts b/arch/mips/dts/ap143.dts
new file mode 100644
index 000..f53207e
--- /dev/null
+++ b/arch/mips/dts/ap143.dts
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "qca953x.dtsi"
+
+/ {
+   model = "AP143 Reference Board";
+   compatible = "qca,ap143", "qca,qca953x";
+
+   aliases {
+   spi0 = 
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+ {
+   clock-frequency = <2500>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   spi-max-frequency = <2500>;
+   status = "okay";
+   spi-flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   memory-map = <0x9f00 0x0080>;
+   spi-max-frequency = <2500>;
+   reg = <0>;
+   };
+};
diff --git a/arch/mips/dts/qca953x.dtsi b/arch/mips/dts/qca953x.dtsi
new file mode 100644
index 000..8487fc9
--- /dev/null
+++ b/arch/mips/dts/qca953x.dtsi
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+   compatible = "qca,qca953x";
+
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "mips,mips24Kc";
+   reg = <0>;
+   };
+   };
+
+   clocks {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   xtal: xtal {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-output-names = "xtal";
+   };
+   };
+
+   ahb {
+   compatible = "simple-bus";
+   ranges;
+
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   apb {
+   compatible = "simple-bus";
+   ranges;
+
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   uart0: uart@1802 {
+   compatible = "ns16550";
+   reg = <0x1802 0x20>;
+   reg-shift = <2>;
+   clock-frequency = <2500>;
+
+   status = "disabled";
+   };
+   };
+
+   spi0: spi@1f00 {
+   compatible = "qca,ar7100-spi";
+   reg = <0x1f00 0x10>;
+
+   status = "disabled";
+
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+   };
+};
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index 0fcd96a..f61efd2 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -34,8 +34,13 @@ config BOARD_AP121
bool "AP121 Reference Board"
select SOC_AR933X
 
+config BOARD_AP143
+   bool "AP143 Reference Board"
+   select SOC_QCA953X
+
 endchoice
 
 source "board/ath79/ap121/Kconfig"
+source "board/ath79/ap143/Kconfig"
 
 endmenu
diff --git 

Re: [U-Boot] [PATCH v6 00/10] add support for atheros ath79 based SOCs

[Marek Vasut]

On Saturday, January 16, 2016 at 02:15:27 PM, Wills Wang wrote:
> On Saturday, January 16, 2016 01:26 PM, Marek Vasut wrote:
> > On Monday, January 04, 2016 at 12:06:17 PM, Wills Wang wrote:
> >> These series of patch add support for atheros ath79 based SOCs in
> >> u-boot, at the present moment it's just available for ar933x and
> >> qca953x chip.
> >> 
> >> Changes in v6:
> >> - Remove useless "else"
> >> - Move ar933x as separate patch
> >> - Add get_bootstrap in reset.c
> >> - Use map_physmem instead of KSEG1ADDR
> >> - Add arch_cpu_init for detect SOC type for early
> >> - Define magic value in ddr.c
> >> - Remove wait loop in putc and getc
> >> - Use map_physmem instead of KSEG1ADDR
> >> - Add rrw_delay in ath79_spi_priv for more accurate timing
> >> - Remove ath79_spi_delay
> >> - Calculate delay in ath79_spi_set_speed
> >> - Convert SZ_XXX into hex in ap121.h
> >> - Remove useless CONFIG_SYS_INIT_SP_OFFSET in ap121.h
> >> - Add board_early_init_f for DDR and pin initialization
> >> - Select UART and SPI in ap121_defconfig
> >> - Add support for qca953x
> > 
> > I wanted to try this patchset, so I picked [1], since I didn't feel like
> > fishing out patches from the list. Especially since this wasn't sent as
> > a series, but as separate patches, which makes things annoying.
> > 
> > The [1] does not even compile, which is surprising. I would expect that
> > if you submit patches, you would at least compile-test them. Sigh. I
> > needed this patch:
> > 
> > ---8<---
> > diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c
> > index 2952679..140c65c 100644
> > --- a/arch/mips/mach-ath79/cpu.c
> > +++ b/arch/mips/mach-ath79/cpu.c
> > @@ -9,8 +9,8 @@
> > 
> >   #include 
> >   #include 
> >   #include 
> > 
> > -#include 
> > -#include 
> > +#include 
> > +#include 
> > 
> >   struct ath79_soc_desc {
> >   
> >  enum ath79_soc_type soc;
> > 
> > diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
> > index 410b900..fe32d80 100644
> > --- a/arch/mips/mach-ath79/reset.c
> > +++ b/arch/mips/mach-ath79/reset.c
> > @@ -9,7 +9,7 @@
> > 
> >   #include 
> >   #include 
> >   #include 
> > 
> > -#include 
> > +#include 
> > 
> >   #include 
> >   
> >   void _machine_restart(void)
> > 
> > --->8---
> 
> Marek, you can try my repository at
> https://github.com/willswang/u-boot-ath79,
> I have fixed the compiling issue about headers.
> I'm very sorry about this compiling error, my work tree have a residual
> symbol
> link between arch/mips/include/asm/arch and
> arch/mips/mach-ath79/include/mach.
> it was not removed when i executed "make clean" to rebuild,  so, my
> compiling
> didn't discover this problem before this. now i clone this remote branch
> into a new
> location and find this issue.

You should do git clean -fdx to zap everything before doing the rebuild and 
repost. This way, you can be sure that you have no residual stuff in your tree.

Also, if make clean doesn't remove objects , there is some other problem which
needs attention.

> > Once I managed to fix things, I compiled ap121. I tried booting it on
> > arduino yun (ar9331), but it hung in start.S in setup_c0_status . If I
> > comment this out, it hangs in lowlevel_init, right at the beginning.
> > That's where I gave up.

What about this one? Did you ever boot-test these patches ? I can probably 
understand why setup_c0_status might hang, but I don't quite understand why
would lowlevel_init hang so early.

> > [1] http://git.denx.de/?p=u-boot/u-boot-
> > mips.git;a=shortlog;h=refs/heads/mips_ath79_v6
> > 
> > Best regards,
> > Marek Vasut

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v6 00/10] add support for atheros ath79 based SOCs

[Wills Wang]

On Saturday, January 16, 2016 11:33 PM, Marek Vasut wrote:

On Saturday, January 16, 2016 at 02:15:27 PM, Wills Wang wrote:

On Saturday, January 16, 2016 01:26 PM, Marek Vasut wrote:

On Monday, January 04, 2016 at 12:06:17 PM, Wills Wang wrote:

These series of patch add support for atheros ath79 based SOCs in
u-boot, at the present moment it's just available for ar933x and
qca953x chip.

Changes in v6:
- Remove useless "else"
- Move ar933x as separate patch
- Add get_bootstrap in reset.c
- Use map_physmem instead of KSEG1ADDR
- Add arch_cpu_init for detect SOC type for early
- Define magic value in ddr.c
- Remove wait loop in putc and getc
- Use map_physmem instead of KSEG1ADDR
- Add rrw_delay in ath79_spi_priv for more accurate timing
- Remove ath79_spi_delay
- Calculate delay in ath79_spi_set_speed
- Convert SZ_XXX into hex in ap121.h
- Remove useless CONFIG_SYS_INIT_SP_OFFSET in ap121.h
- Add board_early_init_f for DDR and pin initialization
- Select UART and SPI in ap121_defconfig
- Add support for qca953x

I wanted to try this patchset, so I picked [1], since I didn't feel like
fishing out patches from the list. Especially since this wasn't sent as
a series, but as separate patches, which makes things annoying.

The [1] does not even compile, which is surprising. I would expect that
if you submit patches, you would at least compile-test them. Sigh. I
needed this patch:

---8<---
diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c
index 2952679..140c65c 100644
--- a/arch/mips/mach-ath79/cpu.c
+++ b/arch/mips/mach-ath79/cpu.c
@@ -9,8 +9,8 @@

   #include 
   #include 
   #include 

-#include 
-#include 
+#include 
+#include 

   struct ath79_soc_desc {
   
  enum ath79_soc_type soc;


diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index 410b900..fe32d80 100644
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -9,7 +9,7 @@

   #include 
   #include 
   #include 

-#include 
+#include 

   #include 
   
   void _machine_restart(void)


--->8---

Marek, you can try my repository at
https://github.com/willswang/u-boot-ath79,
I have fixed the compiling issue about headers.
I'm very sorry about this compiling error, my work tree have a residual
symbol
link between arch/mips/include/asm/arch and
arch/mips/mach-ath79/include/mach.
it was not removed when i executed "make clean" to rebuild,  so, my
compiling
didn't discover this problem before this. now i clone this remote branch
into a new
location and find this issue.

You should do git clean -fdx to zap everything before doing the rebuild and
repost. This way, you can be sure that you have no residual stuff in your tree.

Also, if make clean doesn't remove objects , there is some other problem which
needs attention.


Once I managed to fix things, I compiled ap121. I tried booting it on
arduino yun (ar9331), but it hung in start.S in setup_c0_status . If I
comment this out, it hangs in lowlevel_init, right at the beginning.
That's where I gave up.

What about this one? Did you ever boot-test these patches ? I can probably
understand why setup_c0_status might hang, but I don't quite understand why
would lowlevel_init hang so early.

Did your board still hang if compiling from my repository?

[1] http://git.denx.de/?p=u-boot/u-boot-
mips.git;a=shortlog;h=refs/heads/mips_ath79_v6

Best regards,
Marek Vasut

Best regards,
Marek Vasut


--
Best Regards
Wills

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[U-Boot] [PATCH] drivers: uclass: timer: rename timer_init() to dm_timer_init()

[Mugunthan V N]

Rename timer_init() to dm_timer_init() and remove dm_timer_init()
in lib/time.c as

* timer_init is called from board_f.c or board_r.c on different
  architectures which may result causes timer devices to be
  probed twice.
* lib/time.c dm_timer_init() does nothing other than calling
  timer_init().

Also remove reinitializing of ret in timer_init().

Signed-off-by: Mugunthan V N 
---

Tested this patch on dra74x evm. and pushed a branch [2].

[1] - http://pastebin.ubuntu.com/14524076/
[2] - git://git.ti.com/~mugunthanvnm/ti-u-boot/mugunth-ti-u-boot.git 
dm-timer-fix

---
 drivers/timer/timer-uclass.c | 7 +--
 include/timer.h  | 9 +
 lib/time.c   | 8 
 3 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index 053411f..83d1a35 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c
@@ -68,13 +68,16 @@ u64 timer_conv_64(u32 count)
return ((u64)gd->timebase_h << 32) | gd->timebase_l;
 }
 
-int timer_init(void)
+int notrace dm_timer_init(void)
 {
const void *blob = gd->fdt_blob;
struct udevice *dev = NULL;
int node;
int ret;
 
+   if (gd->timer)
+   return 0;
+
/* Check for a chosen timer to be used for tick */
node = fdtdec_get_chosen_node(blob, "tick-timer");
if (node < 0) {
@@ -92,7 +95,7 @@ int timer_init(void)
 */
if (node > 0 &&
!lists_bind_fdt(gd->dm_root, blob, node, )) {
-   int ret = device_probe(dev);
+   ret = device_probe(dev);
if (ret)
return ret;
}
diff --git a/include/timer.h b/include/timer.h
index 7fee17e..f14725c 100644
--- a/include/timer.h
+++ b/include/timer.h
@@ -8,6 +8,15 @@
 #define _TIMER_H_
 
 /*
+ * dm_timer_init - initialize a timer for time keeping. On success
+ * initializes gd->timer so that lib/timer can use it for future
+ * referrence.
+ *
+ * @return - 0 on success or error number
+ */
+int dm_timer_init(void);
+
+/*
  * timer_conv_64 - convert 32-bit counter value to 64-bit
  *
  * @count: 32-bit counter value
diff --git a/lib/time.c b/lib/time.c
index d4060f1..e9f6861 100644
--- a/lib/time.c
+++ b/lib/time.c
@@ -41,14 +41,6 @@ extern unsigned long __weak timer_read_counter(void);
 #endif
 
 #ifdef CONFIG_TIMER
-static int notrace dm_timer_init(void)
-{
-   if (!gd->timer)
-   return timer_init();
-
-   return 0;
-}
-
 ulong notrace get_tbclk(void)
 {
int ret;
-- 
2.7.0.rc3

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[U-Boot] [PATCH v7 1/7] mips: add base support for QCA/Atheros ath79 SOCs

[Wills Wang]

Signed-off-by: Wills Wang 
---

Changes in v7:
- Use setbits_32
- Fix include path for SoC specific headers

Changes in v6:
- Move ar933x as separate patch
- Add get_bootstrap in reset.c
- Use map_physmem instead of KSEG1ADDR
- Add arch_cpu_init for detect SOC type for early

Changes in v5:
- Add independent Kconfig
- Use SRAM for initial stack
- Move DDR initialization into board_early_init_f
- Convert DDR tap tunning code to C
- Save SOC's version into arch_global_data

Changes in v4:
- Use global_data to save CPU/DDR/AHB clock
- Use arch_global_data to save SOC's type, revison and id

Changes in v3:
- Move SoC specific header files into arch/mips/mach-ath79/include/mach
- Optimize assembly code
- Same code style convertion

Changes in v2:
- Move all SoC specific header files into arch/mips/include/asm/arch-ath79
- Check SOC type and extract common code into arch/mips/mach-ath79

 arch/mips/Kconfig   |6 +
 arch/mips/Makefile  |1 +
 arch/mips/include/asm/global_data.h |6 +
 arch/mips/mach-ath79/Kconfig|   10 +
 arch/mips/mach-ath79/Makefile   |7 +
 arch/mips/mach-ath79/cpu.c  |  203 
 arch/mips/mach-ath79/dram.c |   16 +
 arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1187 +++
 arch/mips/mach-ath79/include/mach/ath79.h   |  143 +++
 arch/mips/mach-ath79/include/mach/ddr.h |   13 +
 arch/mips/mach-ath79/include/mach/reset.h   |   14 +
 arch/mips/mach-ath79/reset.c|   71 ++
 12 files changed, 1677 insertions(+)
 create mode 100644 arch/mips/mach-ath79/Kconfig
 create mode 100644 arch/mips/mach-ath79/Makefile
 create mode 100644 arch/mips/mach-ath79/cpu.c
 create mode 100644 arch/mips/mach-ath79/dram.c
 create mode 100644 arch/mips/mach-ath79/include/mach/ar71xx_regs.h
 create mode 100644 arch/mips/mach-ath79/include/mach/ath79.h
 create mode 100644 arch/mips/mach-ath79/include/mach/ddr.h
 create mode 100644 arch/mips/mach-ath79/include/mach/reset.h
 create mode 100644 arch/mips/mach-ath79/reset.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1b39c4c..3c71090 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -54,6 +54,11 @@ config TARGET_PB1X00
select SYS_MIPS_CACHE_INIT_RAM_LOAD
select MIPS_TUNE_4KC
 
+config ARCH_ATH79
+   bool "Support ath79"
+   select OF_CONTROL
+   select DM
+
 endchoice
 
 source "board/dbau1x00/Kconfig"
@@ -61,6 +66,7 @@ source "board/imgtec/malta/Kconfig"
 source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
+source "arch/mips/mach-ath79/Kconfig"
 
 if MIPS
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 2133e7e..334b1ba 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -8,6 +8,7 @@ libs-y += arch/mips/cpu/
 libs-y += arch/mips/lib/
 
 machine-$(CONFIG_SOC_AU1X00) += au1x00
+machine-$(CONFIG_ARCH_ATH79) += ath79
 
 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
 libs-y += $(machdirs)
diff --git a/arch/mips/include/asm/global_data.h 
b/arch/mips/include/asm/global_data.h
index 2d9a0c9..3799e98 100644
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@@ -20,6 +20,12 @@ struct arch_global_data {
unsigned long tbl;
unsigned long lastinc;
 #endif
+#ifdef CONFIG_ARCH_ATH79
+   unsigned long id;
+   unsigned long soc;
+   unsigned long rev;
+   unsigned long ver;
+#endif
 };
 
 #include 
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
new file mode 100644
index 000..df84876
--- /dev/null
+++ b/arch/mips/mach-ath79/Kconfig
@@ -0,0 +1,10 @@
+menu "QCA/Athroes 7xxx/9xxx platforms"
+   depends on ARCH_ATH79
+
+config SYS_VENDOR
+   default "ath79"
+
+config SYS_SOC
+   default "ath79"
+
+endmenu
diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile
new file mode 100644
index 000..6203cf0
--- /dev/null
+++ b/arch/mips/mach-ath79/Makefile
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += reset.o
+obj-y += cpu.o
+obj-y += dram.o
diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c
new file mode 100644
index 000..d8910a0
--- /dev/null
+++ b/arch/mips/mach-ath79/cpu.c
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct ath79_soc_desc {
+   enum ath79_soc_type soc;
+   const char *chip;
+};
+
+static struct ath79_soc_desc desc[] = {
+   {ATH79_SOC_AR7130,  "7130"},
+   {ATH79_SOC_AR7141,  "7141"},
+   {ATH79_SOC_AR7161,  "7161"},
+   {ATH79_SOC_AR7240,  "7240"},
+   {ATH79_SOC_AR7242,  "7242"},
+   {ATH79_SOC_AR9130,  "9130"},
+   

[U-Boot] [PATCH v7 2/7] mips: ath79: add support for AR933x SOCs

[Wills Wang]

This patch enable work for ar933x SOC.

Signed-off-by: Wills Wang 
---

Changes in v7:
- Use CKSEGxADDR instead of KSEGxADDR for ar933x

Changes in v6:
- Remove board.c
- Define magic value in ddr.c

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/mips/mach-ath79/Kconfig|  10 +
 arch/mips/mach-ath79/Makefile   |   2 +
 arch/mips/mach-ath79/ar933x/Makefile|   7 +
 arch/mips/mach-ath79/ar933x/clk.c   |  89 
 arch/mips/mach-ath79/ar933x/ddr.c   | 316 
 arch/mips/mach-ath79/ar933x/lowlevel_init.S | 279 
 6 files changed, 703 insertions(+)
 create mode 100644 arch/mips/mach-ath79/ar933x/Makefile
 create mode 100644 arch/mips/mach-ath79/ar933x/clk.c
 create mode 100644 arch/mips/mach-ath79/ar933x/ddr.c
 create mode 100644 arch/mips/mach-ath79/ar933x/lowlevel_init.S

diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index df84876..ff2c491 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -7,4 +7,14 @@ config SYS_VENDOR
 config SYS_SOC
default "ath79"
 
+config SOC_AR933X
+   bool
+   select SUPPORTS_BIG_ENDIAN
+   select SUPPORTS_CPU_MIPS32_R1
+   select SUPPORTS_CPU_MIPS32_R2
+   select SYS_MIPS_CACHE_INIT_RAM_LOAD
+   select MIPS_TUNE_24KC
+   help
+ This supports QCA/Atheros ar933x family SOCs.
+
 endmenu
diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile
index 6203cf0..9b9447e 100644
--- a/arch/mips/mach-ath79/Makefile
+++ b/arch/mips/mach-ath79/Makefile
@@ -5,3 +5,5 @@
 obj-y += reset.o
 obj-y += cpu.o
 obj-y += dram.o
+
+obj-$(CONFIG_SOC_AR933X)   += ar933x/
\ No newline at end of file
diff --git a/arch/mips/mach-ath79/ar933x/Makefile 
b/arch/mips/mach-ath79/ar933x/Makefile
new file mode 100644
index 000..fd74f0c
--- /dev/null
+++ b/arch/mips/mach-ath79/ar933x/Makefile
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += clk.o
+obj-y += ddr.o
+obj-y += lowlevel_init.o
diff --git a/arch/mips/mach-ath79/ar933x/clk.c 
b/arch/mips/mach-ath79/ar933x/clk.c
new file mode 100644
index 000..9fcd496
--- /dev/null
+++ b/arch/mips/mach-ath79/ar933x/clk.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 ar933x_get_xtal(void)
+{
+   u32 val;
+
+   val = get_bootstrap();
+   if (val & AR933X_BOOTSTRAP_REF_CLK_40)
+   return 4000;
+   else
+   return 2500;
+}
+
+int get_serial_clock(void)
+{
+   return ar933x_get_xtal();
+}
+
+int get_clocks(void)
+{
+   void __iomem *regs;
+   u32 val, xtal, pll, div;
+
+   regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+  MAP_NOCACHE);
+   xtal = ar933x_get_xtal();
+   val = readl(regs + AR933X_PLL_CPU_CONFIG_REG);
+
+   /* VCOOUT = XTAL * DIV_INT */
+   div = (val >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT)
+   & AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
+   pll = xtal / div;
+
+   /* PLLOUT = VCOOUT * (1/2^OUTDIV) */
+   div = (val >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT)
+   & AR933X_PLL_CPU_CONFIG_NINT_MASK;
+   pll *= div;
+   div = (val >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
+   & AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
+   if (!div)
+   div = 1;
+   pll >>= div;
+
+   val = readl(regs + AR933X_PLL_CLK_CTRL_REG);
+
+   /* CPU_CLK = PLLOUT / CPU_POST_DIV */
+   div = ((val >> AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT)
+   & AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
+   gd->cpu_clk = pll / div;
+
+   /* DDR_CLK = PLLOUT / DDR_POST_DIV */
+   div = ((val >> AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT)
+   & AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1;
+   gd->mem_clk = pll / div;
+
+   /* AHB_CLK = PLLOUT / AHB_POST_DIV */
+   div = ((val >> AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT)
+   & AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1;
+   gd->bus_clk = pll / div;
+
+   return 0;
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+   if (!gd->bus_clk)
+   get_clocks();
+   return gd->bus_clk;
+}
+
+ulong get_ddr_freq(ulong dummy)
+{
+   if (!gd->mem_clk)
+   get_clocks();
+   return gd->mem_clk;
+}
diff --git a/arch/mips/mach-ath79/ar933x/ddr.c 
b/arch/mips/mach-ath79/ar933x/ddr.c
new file mode 100644
index 000..7bc350f
--- /dev/null
+++ b/arch/mips/mach-ath79/ar933x/ddr.c
@@ -0,0 +1,316 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+

[U-Boot] [PATCH v7 6/7] mips: ath79: add AP121 reference board

[Wills Wang]

Signed-off-by: Wills Wang 
---

Changes in v7:
- Use KSEG1 address for debug port in ap121

Changes in v6:
- Convert SZ_XXX into hex in ap121.h
- Remove useless CONFIG_SYS_INIT_SP_OFFSET in ap121.h
- Add board_early_init_f for DDR and pin initialization
- Select UART and SPI in ap121_defconfig

Changes in v5:
- Move CONFIG_SYS_TEXT_BASE into ap121.h, and remove config.mk
- Remove useless README file
- Remove useless checkboard function

Changes in v4: None
Changes in v3:
- Add support for device tree

Changes in v2:
- Add a reference board implemention

 arch/mips/dts/Makefile|  2 +-
 arch/mips/dts/ap121.dts   | 43 +
 arch/mips/dts/ar933x.dtsi | 70 ++
 arch/mips/mach-ath79/Kconfig  | 11 ++
 board/ath79/ap121/Kconfig |  9 +
 board/ath79/ap121/MAINTAINERS |  6 +++
 board/ath79/ap121/Makefile|  5 +++
 board/ath79/ap121/ap121.c | 47 +++
 configs/ap121_defconfig   | 42 +
 include/configs/ap121.h   | 87 +++
 10 files changed, 321 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/dts/ap121.dts
 create mode 100644 arch/mips/dts/ar933x.dtsi
 create mode 100644 board/ath79/ap121/Kconfig
 create mode 100644 board/ath79/ap121/MAINTAINERS
 create mode 100644 board/ath79/ap121/Makefile
 create mode 100644 board/ath79/ap121/ap121.c
 create mode 100644 configs/ap121_defconfig
 create mode 100644 include/configs/ap121.h

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 47b6eb5..3fd49eb 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-dtb-y +=
+dtb-$(CONFIG_BOARD_AP121) += ap121.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/mips/dts/ap121.dts b/arch/mips/dts/ap121.dts
new file mode 100644
index 000..e31f601
--- /dev/null
+++ b/arch/mips/dts/ap121.dts
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "ar933x.dtsi"
+
+/ {
+   model = "AP121 Reference Board";
+   compatible = "qca,ap121", "qca,ar933x";
+
+   aliases {
+   spi0 = 
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+ {
+   clock-frequency = <2500>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   spi-max-frequency = <2500>;
+   status = "okay";
+   spi-flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   memory-map = <0x9f00 0x0080>;
+   spi-max-frequency = <2500>;
+   reg = <0>;
+   };
+};
diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi
new file mode 100644
index 000..b505938
--- /dev/null
+++ b/arch/mips/dts/ar933x.dtsi
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+   compatible = "qca,ar933x";
+
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "mips,mips24Kc";
+   reg = <0>;
+   };
+   };
+
+   clocks {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   xtal: xtal {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-output-names = "xtal";
+   };
+   };
+
+   ahb {
+   compatible = "simple-bus";
+   ranges;
+
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   apb {
+   compatible = "simple-bus";
+   ranges;
+
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   uart0: uart@1802 {
+   compatible = "qca,ar9330-uart";
+   reg = <0x1802 0x20>;
+
+   status = "disabled";
+   };
+   };
+
+   spi0: spi@1f00 {
+   compatible = "qca,ar7100-spi";
+   reg = <0x1f00 0x10>;
+
+   status = "disabled";
+
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+   };
+};
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index f7801e4..0fcd96a 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -27,4 +27,15 @@ config 

[U-Boot] [PATCH v7 3/7] mips: ath79: add support for QCA953x SOCs

[Wills Wang]

This patch enable work for qca953x SOC.

Signed-off-by: Wills Wang 
---

Changes in v7:
- Use CKSEGxADDR instead of KSEGxADDR for qca953x

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/mips/mach-ath79/Kconfig |  10 +
 arch/mips/mach-ath79/Makefile|   3 +-
 arch/mips/mach-ath79/qca953x/Makefile|   7 +
 arch/mips/mach-ath79/qca953x/clk.c   | 111 +++
 arch/mips/mach-ath79/qca953x/ddr.c   | 462 +++
 arch/mips/mach-ath79/qca953x/lowlevel_init.S | 185 +++
 6 files changed, 777 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/mach-ath79/qca953x/Makefile
 create mode 100644 arch/mips/mach-ath79/qca953x/clk.c
 create mode 100644 arch/mips/mach-ath79/qca953x/ddr.c
 create mode 100644 arch/mips/mach-ath79/qca953x/lowlevel_init.S

diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index ff2c491..f7801e4 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -17,4 +17,14 @@ config SOC_AR933X
help
  This supports QCA/Atheros ar933x family SOCs.
 
+config SOC_QCA953X
+   bool
+   select SUPPORTS_BIG_ENDIAN
+   select SUPPORTS_CPU_MIPS32_R1
+   select SUPPORTS_CPU_MIPS32_R2
+   select SYS_MIPS_CACHE_INIT_RAM_LOAD
+   select MIPS_TUNE_24KC
+   help
+ This supports QCA/Atheros qca953x family SOCs.
+
 endmenu
diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile
index 9b9447e..160dfaa 100644
--- a/arch/mips/mach-ath79/Makefile
+++ b/arch/mips/mach-ath79/Makefile
@@ -6,4 +6,5 @@ obj-y += reset.o
 obj-y += cpu.o
 obj-y += dram.o
 
-obj-$(CONFIG_SOC_AR933X)   += ar933x/
\ No newline at end of file
+obj-$(CONFIG_SOC_AR933X)   += ar933x/
+obj-$(CONFIG_SOC_QCA953X)  += qca953x/
\ No newline at end of file
diff --git a/arch/mips/mach-ath79/qca953x/Makefile 
b/arch/mips/mach-ath79/qca953x/Makefile
new file mode 100644
index 000..fd74f0c
--- /dev/null
+++ b/arch/mips/mach-ath79/qca953x/Makefile
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += clk.o
+obj-y += ddr.o
+obj-y += lowlevel_init.o
diff --git a/arch/mips/mach-ath79/qca953x/clk.c 
b/arch/mips/mach-ath79/qca953x/clk.c
new file mode 100644
index 000..ef0a28e
--- /dev/null
+++ b/arch/mips/mach-ath79/qca953x/clk.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 qca953x_get_xtal(void)
+{
+   u32 val;
+
+   val = get_bootstrap();
+   if (val & QCA953X_BOOTSTRAP_REF_CLK_40)
+   return 4000;
+   else
+   return 2500;
+}
+
+int get_serial_clock(void)
+{
+   return qca953x_get_xtal();
+}
+
+int get_clocks(void)
+{
+   void __iomem *regs;
+   u32 val, ctrl, xtal, pll, div;
+
+   regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+  MAP_NOCACHE);
+
+   xtal = qca953x_get_xtal();
+   ctrl = readl(regs + QCA953X_PLL_CLK_CTRL_REG);
+   val = readl(regs + QCA953X_PLL_CPU_CONFIG_REG);
+
+   /* VCOOUT = XTAL * DIV_INT */
+   div = (val >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT)
+   & QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
+   pll = xtal / div;
+
+   /* PLLOUT = VCOOUT * (1/2^OUTDIV) */
+   div = (val >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT)
+   & QCA953X_PLL_CPU_CONFIG_NINT_MASK;
+   pll *= div;
+   div = (val >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
+   & QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
+   if (!div)
+   div = 1;
+   pll >>= div;
+
+   /* CPU_CLK = PLLOUT / CPU_POST_DIV */
+   div = ((ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT)
+   & QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
+   gd->cpu_clk = pll / div;
+
+
+   val = readl(regs + QCA953X_PLL_DDR_CONFIG_REG);
+   /* VCOOUT = XTAL * DIV_INT */
+   div = (val >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT)
+   & QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
+   pll = xtal / div;
+
+   /* PLLOUT = VCOOUT * (1/2^OUTDIV) */
+   div = (val >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT)
+   & QCA953X_PLL_DDR_CONFIG_NINT_MASK;
+   pll *= div;
+   div = (val >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT)
+   & QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
+   if (!div)
+   div = 1;
+   pll >>= div;
+
+   /* DDR_CLK = PLLOUT / DDR_POST_DIV */
+   div = ((ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT)
+   & QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1;
+   gd->mem_clk = pll / div;
+
+   div = ((ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT)
+   & 

[U-Boot] [PATCH v7 4/7] mips: ath79: add serial driver for ar933x SOC

[Wills Wang]

Reviewed-by: Thomas Chou 

Signed-off-by: Wills Wang 
---

Changes in v7:
- remove map_physmem for debug port

Changes in v6:
- Remove wait loop in putc and getc
- Use map_physmem instead of KSEG1ADDR

Changes in v5:
- remove ar933x_serial_platdata
- Import document "qca,ar9330-uart.txt" from kernel
- Add support for debug UART

Changes in v4:
- Auto calculate baudrate for serial driver
- Move pinctrl code in serial driver into arch/mips/mach-ath79
- Use get_serial_clock to serial clock source

Changes in v3:
- Convert serial driver to driver model

Changes in v2:
- Move serial driver code into drivers/serial

 .../serial/qca,ar9330-uart.txt |  24 ++
 drivers/serial/Kconfig |  17 ++
 drivers/serial/Makefile|   1 +
 drivers/serial/serial_ar933x.c | 254 +
 4 files changed, 296 insertions(+)
 create mode 100644 doc/device-tree-bindings/serial/qca,ar9330-uart.txt
 create mode 100644 drivers/serial/serial_ar933x.c

diff --git a/doc/device-tree-bindings/serial/qca,ar9330-uart.txt 
b/doc/device-tree-bindings/serial/qca,ar9330-uart.txt
new file mode 100644
index 000..ec576a1
--- /dev/null
+++ b/doc/device-tree-bindings/serial/qca,ar9330-uart.txt
@@ -0,0 +1,24 @@
+* Qualcomm Atheros AR9330 High-Speed UART
+
+Required properties:
+
+- compatible: Must be "qca,ar9330-uart"
+
+- reg: Specifies the physical base address of the controller and
+  the length of the memory mapped region.
+
+Additional requirements:
+
+  Each UART port must have an alias correctly numbered in "aliases"
+  node.
+
+Example:
+
+   aliases {
+   serial0 = 
+   };
+
+   uart0: uart@1802 {
+   compatible = "qca,ar9330-uart";
+   reg = <0x1802 0x14>;
+   };
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 1fc287e..f147379 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -69,6 +69,14 @@ config DEBUG_UART_ALTERA_UART
  You will need to provide parameters to make this work. The driver will
  be available until the real driver model serial is running.
 
+config DEBUG_UART_AR933X
+   bool "QCA/Atheros ar933x"
+   help
+ Select this to enable a debug UART using the ar933x uart driver.
+ You will need to provide parameters to make this work. The
+ driver will be available until the real driver model serial is
+ running.
+
 config DEBUG_UART_NS16550
bool "ns16550"
help
@@ -186,6 +194,15 @@ config ALTERA_UART
  Select this to enable an UART for Altera devices. Please find
  details on the "Embedded Peripherals IP User Guide" of Altera.
 
+config AR933X_UART
+   bool "QCA/Atheros ar933x UART support"
+   depends on DM_SERIAL
+   help
+ Select this to enable UART support for QCA/Atheros ar933x
+ devices. This driver uses driver model and requires a device
+ tree binding to operate, please refer to the document at
+ doc/device-tree-bindings/serial/qca,ar9330-uart.txt.
+
 config SYS_NS16550
bool "NS16550 UART or compatible"
help
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index dd87147..b7b82ae 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -17,6 +17,7 @@ endif
 
 obj-$(CONFIG_ALTERA_UART) += altera_uart.o
 obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
+obj-$(CONFIG_AR933X_UART) += serial_ar933x.o
 obj-$(CONFIG_ARM_DCC) += arm_dcc.o
 obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
 obj-$(CONFIG_EFI_APP) += serial_efi.o
diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c
new file mode 100644
index 000..ccba2f5
--- /dev/null
+++ b/drivers/serial/serial_ar933x.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define AR933X_UART_DATA_REG0x00
+#define AR933X_UART_CS_REG  0x04
+#define AR933X_UART_CLK_REG 0x08
+
+#define AR933X_UART_DATA_TX_RX_MASK 0xff
+#define AR933X_UART_DATA_RX_CSR BIT(8)
+#define AR933X_UART_DATA_TX_CSR BIT(9)
+#define AR933X_UART_CS_IF_MODE_S2
+#define AR933X_UART_CS_IF_MODE_M0x3
+#define AR933X_UART_CS_IF_MODE_DTE  1
+#define AR933X_UART_CS_IF_MODE_DCE  2
+#define AR933X_UART_CS_TX_RDY_ORIDE BIT(7)
+#define AR933X_UART_CS_RX_RDY_ORIDE BIT(8)
+#define AR933X_UART_CLK_STEP_M  0x
+#define AR933X_UART_CLK_SCALE_M 0xfff
+#define AR933X_UART_CLK_SCALE_S 16
+#define AR933X_UART_CLK_STEP_S  0
+
+struct ar933x_serial_priv {
+   void __iomem *regs;
+};
+
+static inline u32 ar933x_serial_read(struct udevice *dev, u32 offset)
+{
+   struct ar933x_serial_priv *priv = 

[U-Boot] [PATCH v7 5/7] mips: ath79: add spi driver

[Wills Wang]

Reviewed-by: Thomas Chou 

Signed-off-by: Wills Wang 
---

Changes in v7:
- Define spi_cs_activate/spi_cs_deactivate
- Rename MHZ to ATH79_SPI_MHZ
- Use clrsetbits_32

Changes in v6:
- Add rrw_delay in ath79_spi_priv for more accurate timing
- Remove ath79_spi_delay
- Calculate delay in ath79_spi_set_speed

Changes in v5:
- remove ar933x_spi_platdata
- Import document "spi-ath79.txt" from kernel
- Add delay for bitbang operation

Changes in v4:
- Use get_bus_freq instead of hardcode in SPI driver

Changes in v3:
- Convert spi driver to driver model

Changes in v2:
- Add a compatible spi driver

 doc/device-tree-bindings/spi/spi-ath79.txt |  19 +++
 drivers/spi/Kconfig|   8 +
 drivers/spi/Makefile   |   1 +
 drivers/spi/ath79_spi.c| 237 +
 4 files changed, 265 insertions(+)
 create mode 100644 doc/device-tree-bindings/spi/spi-ath79.txt
 create mode 100644 drivers/spi/ath79_spi.c

diff --git a/doc/device-tree-bindings/spi/spi-ath79.txt 
b/doc/device-tree-bindings/spi/spi-ath79.txt
new file mode 100644
index 000..3fd9d67
--- /dev/null
+++ b/doc/device-tree-bindings/spi/spi-ath79.txt
@@ -0,0 +1,19 @@
+Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller
+
+Required properties:
+- compatible: has to be "qca,-spi", "qca,ar7100-spi" as fallback.
+- reg: Base address and size of the controllers memory area
+- #address-cells: <1>, as required by generic SPI binding.
+- #size-cells: <0>, also as required by generic SPI binding.
+
+Child nodes as per the generic SPI binding.
+
+Example:
+
+   spi@1f00 {
+   compatible = "qca,ar9132-spi", "qca,ar7100-spi";
+   reg = <0x1f00 0x10>;
+
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2cdb110..0ab2741 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -23,6 +23,14 @@ config ALTERA_SPI
  IP core. Please find details on the "Embedded Peripherals IP
  User Guide" of Altera.
 
+config ATH79_SPI
+   bool "Atheros SPI driver"
+   help
+ Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used
+ to access SPI NOR flash and other SPI peripherals. This driver
+ uses driver model and requires a device tree binding to operate.
+ please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
+
 config CADENCE_QSPI
bool "Cadence QSPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3eca745..7fb2926 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -17,6 +17,7 @@ endif
 
 obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
 obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
+obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
 obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
 obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
 obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c
new file mode 100644
index 000..568548f
--- /dev/null
+++ b/drivers/spi/ath79_spi.c
@@ -0,0 +1,237 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */
+#define ATH79_SPI_CLK_DIV(x)   (((x) >> 1) - 1)
+#define ATH79_SPI_RRW_DELAY_FACTOR 12000
+#define ATH79_SPI_MHZ  (1000 * 1000)
+
+struct ath79_spi_priv {
+   void __iomem *regs;
+   u32 rrw_delay;
+};
+
+static inline u32 ath79_spi_read(struct udevice *bus, u32 offset)
+{
+   struct ath79_spi_priv *priv = dev_get_priv(bus);
+   return readl(priv->regs + offset);
+}
+
+static inline void ath79_spi_write(struct udevice *bus,
+   u32 val, u32 offset)
+{
+   struct ath79_spi_priv *priv = dev_get_priv(bus);
+   writel(val, priv->regs + offset);
+}
+
+static void spi_cs_activate(struct udevice *dev)
+{
+   struct udevice *bus = dev->parent;
+
+   ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
+   ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC);
+}
+
+static void spi_cs_deactivate(struct udevice *dev)
+{
+   struct udevice *bus = dev->parent;
+
+   ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC);
+   ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
+}
+
+static int ath79_spi_claim_bus(struct udevice *dev)
+{
+   return 0;
+}
+
+static int ath79_spi_release_bus(struct udevice *dev)
+{
+   return 0;
+}
+
+static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen,
+   const void *dout, void *din, unsigned long flags)
+{
+   struct udevice *bus = dev->parent;
+   struct ath79_spi_priv *priv = dev_get_priv(bus);
+   struct dm_spi_slave_platdata 

[U-Boot] [PATCH] pci_rom.c: Fix may be used uninitialized warning

[Tom Rini]

With gcc-5.x we get:
drivers/pci/pci_rom.c: In function 'dm_pci_run_vga_bios':
drivers/pci/pci_rom.c:352:3: warning: 'ram' may be used uninitialized in
this function [-Wmaybe-uninitialized]

While unconvinced that this can happen in practice (if we malloc we set
alloced to true, it will be false otherwise), silence the compiler.

Signed-off-by: Tom Rini 
---
 drivers/pci/pci_rom.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index 8c83be6..ed2f61d 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -266,7 +266,7 @@ int dm_pci_run_vga_bios(struct udevice *dev, int 
(*int15_handler)(void),
int exec_method)
 {
struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
-   struct pci_rom_header *rom, *ram;
+   struct pci_rom_header *rom, *ram = NULL;
int vesa_mode = -1;
bool emulate, alloced;
int ret;
-- 
2.7.0.rc3

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Re: [U-Boot] [PULL] u-boot-socfpga/master

[Tom Rini]

On Sat, Jan 16, 2016 at 07:09:37AM +0100, Marek Vasut wrote:

> The following changes since commit 782acf7b52db6bec1a796773e3033b4afcd6c9e2:
> 
>   Merge git://git.denx.de/u-boot-rockchip (2016-01-15 08:11:15 -0500)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-socfpga.git master
> 
> for you to fetch changes up to 217db227df40e29d6a4726272303499a7cd7b904:
> 
>   socfpga: Modify qts-filter args to allow input for bsp generated files and 
> quartus project directories (2016-01-16 07:07:23 +0100)
> 

Applied to u-boot/master, thanks!

-- 
Tom




   

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Re: [U-Boot] [PULL] u-boot-usb/master

[Tom Rini]

On Sat, Jan 16, 2016 at 07:08:30AM +0100, Marek Vasut wrote:

> The following changes since commit 782acf7b52db6bec1a796773e3033b4afcd6c9e2:
> 
>   Merge git://git.denx.de/u-boot-rockchip (2016-01-15 08:11:15 -0500)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-usb.git master
> 
> for you to fetch changes up to 447b9cdf2c4d8d7c6cb1ff64426c1dfaf7396f93:
> 
>   common: usb: fix checking condition (2016-01-16 07:06:55 +0100)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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[U-Boot] [PATCH 0/2] TPM minor fixes

[Christophe Ricard]

Hi Simon,

Please find in this serie one bug fix and a typo cleanup.

Best Regards
Christophe



Christophe Ricard (2):
  tpm: Fix fault in case CONFIG_DM_TPM is set without any TPM
  tpm: tpm_tis_lpc: fix typo

 common/cmd_tpm.c| 2 +-
 drivers/tpm/Kconfig | 2 +-
 lib/tpm.c   | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

-- 
2.5.0

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Re: [U-Boot] [PATCH v7 4/7] mips: ath79: add serial driver for ar933x SOC

[Daniel Schwierzeck]

Am Sonntag, den 17.01.2016, 02:13 +0800 schrieb Wills Wang:
> Reviewed-by: Thomas Chou 
> 
> Signed-off-by: Wills Wang 

Reviewed-by: Daniel Schwierzeck 

nits below

> ---
> 
> Changes in v7:
> - remove map_physmem for debug port
> 
> Changes in v6:
> - Remove wait loop in putc and getc
> - Use map_physmem instead of KSEG1ADDR
> 
> Changes in v5:
> - remove ar933x_serial_platdata
> - Import document "qca,ar9330-uart.txt" from kernel
> - Add support for debug UART
> 
> Changes in v4:
> - Auto calculate baudrate for serial driver
> - Move pinctrl code in serial driver into arch/mips/mach-ath79
> - Use get_serial_clock to serial clock source
> 
> Changes in v3:
> - Convert serial driver to driver model
> 
> Changes in v2:
> - Move serial driver code into drivers/serial
> 
>  .../serial/qca,ar9330-uart.txt |  24 ++
>  drivers/serial/Kconfig |  17 ++
>  drivers/serial/Makefile|   1 +
>  drivers/serial/serial_ar933x.c | 254
> +
>  4 files changed, 296 insertions(+)
>  create mode 100644 doc/device-tree-bindings/serial/qca,ar9330
> -uart.txt
>  create mode 100644 drivers/serial/serial_ar933x.c
> 
> diff --git a/doc/device-tree-bindings/serial/qca,ar9330-uart.txt
> b/doc/device-tree-bindings/serial/qca,ar9330-uart.txt
> new file mode 100644
> index 000..ec576a1
> --- /dev/null
> +++ b/doc/device-tree-bindings/serial/qca,ar9330-uart.txt
> @@ -0,0 +1,24 @@
> +* Qualcomm Atheros AR9330 High-Speed UART
> +
> +Required properties:
> +
> +- compatible: Must be "qca,ar9330-uart"
> +
> +- reg: Specifies the physical base address of the controller and
> +  the length of the memory mapped region.
> +
> +Additional requirements:
> +
> +  Each UART port must have an alias correctly numbered in "aliases"
> +  node.
> +
> +Example:
> +
> + aliases {
> + serial0 = 
> + };
> +
> + uart0: uart@1802 {
> + compatible = "qca,ar9330-uart";
> + reg = <0x1802 0x14>;
> + };
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index 1fc287e..f147379 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -69,6 +69,14 @@ config DEBUG_UART_ALTERA_UART
> You will need to provide parameters to make this work. The
> driver will
> be available until the real driver model serial is
> running.
>  
> +config DEBUG_UART_AR933X
> + bool "QCA/Atheros ar933x"

you should add

depends on AR933X_UART

> + help
> +   Select this to enable a debug UART using the ar933x uart
> driver.
> +   You will need to provide parameters to make this work. The
> +   driver will be available until the real driver model
> serial is
> +   running.
> +
>  config DEBUG_UART_NS16550
>   bool "ns16550"
>   help
> @@ -186,6 +194,15 @@ config ALTERA_UART
> Select this to enable an UART for Altera devices. Please
> find
> details on the "Embedded Peripherals IP User Guide" of
> Altera.
>  
> +config AR933X_UART
> + bool "QCA/Atheros ar933x UART support"
> + depends on DM_SERIAL

should be

depends on DM_SERIAL && ARCH_ATH79

> + help
> +   Select this to enable UART support for QCA/Atheros ar933x
> +   devices. This driver uses driver model and requires a
> device
> +   tree binding to operate, please refer to the document at
> +   doc/device-tree-bindings/serial/qca,ar9330-uart.txt.
> +
>  config SYS_NS16550
>   bool "NS16550 UART or compatible"
>   help
> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
> index dd87147..b7b82ae 100644
> --- a/drivers/serial/Makefile
> +++ b/drivers/serial/Makefile
> @@ -17,6 +17,7 @@ endif
>  
>  obj-$(CONFIG_ALTERA_UART) += altera_uart.o
>  obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
> +obj-$(CONFIG_AR933X_UART) += serial_ar933x.o
>  obj-$(CONFIG_ARM_DCC) += arm_dcc.o
>  obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
>  obj-$(CONFIG_EFI_APP) += serial_efi.o
> diff --git a/drivers/serial/serial_ar933x.c
> b/drivers/serial/serial_ar933x.c
> new file mode 100644
> index 000..ccba2f5
> --- /dev/null
> +++ b/drivers/serial/serial_ar933x.c
> @@ -0,0 +1,254 @@
> +/*
> + * Copyright (C) 2015-2016 Wills Wang 
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define AR933X_UART_DATA_REG0x00
> +#define AR933X_UART_CS_REG  0x04
> +#define AR933X_UART_CLK_REG 0x08
> +
> +#define AR933X_UART_DATA_TX_RX_MASK 0xff
> +#define AR933X_UART_DATA_RX_CSR BIT(8)
> +#define AR933X_UART_DATA_TX_CSR BIT(9)
> +#define AR933X_UART_CS_IF_MODE_S2
> +#define AR933X_UART_CS_IF_MODE_M0x3
> +#define AR933X_UART_CS_IF_MODE_DTE  1
> +#define 

Re: [U-Boot] [PATCH v7 5/7] mips: ath79: add spi driver

[Daniel Schwierzeck]

Am Sonntag, den 17.01.2016, 02:13 +0800 schrieb Wills Wang:
> Reviewed-by: Thomas Chou 
> 
> Signed-off-by: Wills Wang 

Reviewed-by: Daniel Schwierzeck 

nits below

> ---
> 
> Changes in v7:
> - Define spi_cs_activate/spi_cs_deactivate
> - Rename MHZ to ATH79_SPI_MHZ
> - Use clrsetbits_32
> 
> Changes in v6:
> - Add rrw_delay in ath79_spi_priv for more accurate timing
> - Remove ath79_spi_delay
> - Calculate delay in ath79_spi_set_speed
> 
> Changes in v5:
> - remove ar933x_spi_platdata
> - Import document "spi-ath79.txt" from kernel
> - Add delay for bitbang operation
> 
> Changes in v4:
> - Use get_bus_freq instead of hardcode in SPI driver
> 
> Changes in v3:
> - Convert spi driver to driver model
> 
> Changes in v2:
> - Add a compatible spi driver
> 
>  doc/device-tree-bindings/spi/spi-ath79.txt |  19 +++
>  drivers/spi/Kconfig|   8 +
>  drivers/spi/Makefile   |   1 +
>  drivers/spi/ath79_spi.c| 237
> +
>  4 files changed, 265 insertions(+)
>  create mode 100644 doc/device-tree-bindings/spi/spi-ath79.txt
>  create mode 100644 drivers/spi/ath79_spi.c
> 
> diff --git a/doc/device-tree-bindings/spi/spi-ath79.txt b/doc/device
> -tree-bindings/spi/spi-ath79.txt
> new file mode 100644
> index 000..3fd9d67
> --- /dev/null
> +++ b/doc/device-tree-bindings/spi/spi-ath79.txt
> @@ -0,0 +1,19 @@
> +Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller
> +
> +Required properties:
> +- compatible: has to be "qca,-spi", "qca,ar7100-spi" as
> fallback.
> +- reg: Base address and size of the controllers memory area
> +- #address-cells: <1>, as required by generic SPI binding.
> +- #size-cells: <0>, also as required by generic SPI binding.
> +
> +Child nodes as per the generic SPI binding.
> +
> +Example:
> +
> + spi@1f00 {
> + compatible = "qca,ar9132-spi", "qca,ar7100-spi";
> + reg = <0x1f00 0x10>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 2cdb110..0ab2741 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -23,6 +23,14 @@ config ALTERA_SPI
> IP core. Please find details on the "Embedded Peripherals
> IP
> User Guide" of Altera.
>  
> +config ATH79_SPI
> + bool "Atheros SPI driver"

you should add

depends on ARCH_ATH79

> + help
> +   Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was
> used
> +   to access SPI NOR flash and other SPI peripherals. This
> driver
> +   uses driver model and requires a device tree binding to
> operate.
> +   please refer to doc/device-tree-bindings/spi/spi
> -ath79.txt.
> +
>  config CADENCE_QSPI
>   bool "Cadence QSPI driver"
>   help
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 3eca745..7fb2926 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -17,6 +17,7 @@ endif
>  
>  obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
>  obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
> +obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
>  obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
>  obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
>  obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
> diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c
> new file mode 100644
> index 000..568548f
> --- /dev/null
> +++ b/drivers/spi/ath79_spi.c
> @@ -0,0 +1,237 @@
> +/*
> + * Copyright (C) 2015-2016 Wills Wang 
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */
> +#define ATH79_SPI_CLK_DIV(x)   (((x) >> 1) - 1)
> +#define ATH79_SPI_RRW_DELAY_FACTOR 12000
> +#define ATH79_SPI_MHZ  (1000 * 1000)
> +
> +struct ath79_spi_priv {
> + void __iomem *regs;
> + u32 rrw_delay;
> +};
> +
> +static inline u32 ath79_spi_read(struct udevice *bus, u32 offset)
> +{
> + struct ath79_spi_priv *priv = dev_get_priv(bus);
> + return readl(priv->regs + offset);
> +}
> +
> +static inline void ath79_spi_write(struct udevice *bus,
> + u32 val, u32 offset)
> +{
> + struct ath79_spi_priv *priv = dev_get_priv(bus);
> + writel(val, priv->regs + offset);
> +}

actually you could use the I/O accessors directly, there is no need for
wrapper functions. The same is true for your serial driver.

> +
> +static void spi_cs_activate(struct udevice *dev)
> +{
> + struct udevice *bus = dev->parent;

for a consistent use of the DM API, you should use dev_get_parent(dev)

> +
> + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
> + ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL,
> AR71XX_SPI_REG_IOC);
> +}
> +
> +static void 

Re: [U-Boot] [PATCH v7 0/7] add support for atheros ath79 based SOCs

[Marek Vasut]

On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote:
> These series of patch add support for atheros ath79 based SOCs in u-boot,
> at the present moment it's just available for ar933x and qca953x chip.
> 
> This patch serises is based on mips_io_v4 branch on u-boot-mips repository
> [1] and tested on ar933x and qca953x board.
> 
> [1]
> http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads/mips_
> io_v4

So if I didn't complain about this being sent as separate emails this morning.
Please, do send your patches as a series, not as separate emails.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v7 1/7] mips: add base support for QCA/Atheros ath79 SOCs

[Marek Vasut]

On Saturday, January 16, 2016 at 07:13:47 PM, Wills Wang wrote:

Commit message is missing.

> Signed-off-by: Wills Wang 
> ---
> 
> Changes in v7:
> - Use setbits_32
> - Fix include path for SoC specific headers
> 
> Changes in v6:
> - Move ar933x as separate patch
> - Add get_bootstrap in reset.c
> - Use map_physmem instead of KSEG1ADDR
> - Add arch_cpu_init for detect SOC type for early

[...]

> diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
> new file mode 100644
> index 000..df84876
> --- /dev/null
> +++ b/arch/mips/mach-ath79/Kconfig
> @@ -0,0 +1,10 @@
> +menu "QCA/Athroes 7xxx/9xxx platforms"
> + depends on ARCH_ATH79
> +
> +config SYS_VENDOR
> + default "ath79"

Vendor should be atheros I believe.

> +config SYS_SOC
> + default "ath79"
> +
> +endmenu
> diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile
> new file mode 100644
> index 000..6203cf0
> --- /dev/null
> +++ b/arch/mips/mach-ath79/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# SPDX-License-Identifier:   GPL-2.0+
> +#
> +
> +obj-y += reset.o
> +obj-y += cpu.o
> +obj-y += dram.o
> diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c
> new file mode 100644
> index 000..d8910a0
> --- /dev/null
> +++ b/arch/mips/mach-ath79/cpu.c
> @@ -0,0 +1,203 @@
> +/*
> + * Copyright (C) 2015-2016 Wills Wang 
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +struct ath79_soc_desc {
> + enum ath79_soc_type soc;
> + const char *chip;
> +};
> +
> +static struct ath79_soc_desc desc[] = {
> + {ATH79_SOC_AR7130,  "7130"},
> + {ATH79_SOC_AR7141,  "7141"},
> + {ATH79_SOC_AR7161,  "7161"},

Just curious, were 7161 chips ever tested ?

> + {ATH79_SOC_AR7240,  "7240"},
> + {ATH79_SOC_AR7242,  "7242"},
> + {ATH79_SOC_AR9130,  "9130"},
> + {ATH79_SOC_AR9132,  "9132"},
> + {ATH79_SOC_AR9330,  "9330"},
> + {ATH79_SOC_AR9331,  "9331"},
> + {ATH79_SOC_AR9341,  "9341"},
> + {ATH79_SOC_AR9342,  "9342"},
> + {ATH79_SOC_AR9344,  "9344"},
> + {ATH79_SOC_QCA9533, "9533"},
> + {ATH79_SOC_QCA9556, "9556"},
> + {ATH79_SOC_QCA9558, "9558"},
> + {ATH79_SOC_TP9343,  "9343"},
> + {ATH79_SOC_QCA9561, "9561"},
> +};
> +
> +int arch_cpu_init(void)
> +{
> + void __iomem *base;
> + enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
> + u32 id, major, minor;
> + u32 rev = 0;
> + u32 ver = 1;
> +
> + base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
> +MAP_NOCACHE);
> +
> + id = readl(base + AR71XX_RESET_REG_REV_ID);
> + major = id & REV_ID_MAJOR_MASK;
> +
> + switch (major) {
> + case REV_ID_MAJOR_AR71XX:
> + minor = id & AR71XX_REV_ID_MINOR_MASK;
> + rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
> + rev &= AR71XX_REV_ID_REVISION_MASK;
> + switch (minor) {
> + case AR71XX_REV_ID_MINOR_AR7130:
> + soc = ATH79_SOC_AR7130;
> + break;
> +
> + case AR71XX_REV_ID_MINOR_AR7141:
> + soc = ATH79_SOC_AR7141;
> + break;
> +
> + case AR71XX_REV_ID_MINOR_AR7161:
> + soc = ATH79_SOC_AR7161;
> + break;
> + }
> + break;

This could easily be a lookup-table instead of such big switch statement.

> + case REV_ID_MAJOR_AR7240:
> + soc = ATH79_SOC_AR7240;
> + rev = id & AR71XX_REV_ID_REVISION_MASK;
> + break;


[...]

> diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
> b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file mode 100644
> index 000..5e80eaf
> --- /dev/null
> +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
> @@ -0,0 +1,1187 @@
> +/*
> + * Atheros AR71XX/AR724X/AR913X SoC register definitions
> + *
> + * Copyright (C) 2015-2016 Wills Wang 
> + * Copyright (C) 2010-2011 Jaiganesh Narayanan 
> + * Copyright (C) 2008-2010 Gabor Juhos 
> + * Copyright (C) 2008 Imre Kaloz 
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __ASM_MACH_AR71XX_REGS_H
> +#define __ASM_MACH_AR71XX_REGS_H
> +
> +#ifndef __ASSEMBLY__
> +#include 
> +#else
> +#ifndef BIT
> +#define BIT(nr) (1 << (nr))

Linux defines the macro as (1ul << (nr))

> +#endif
> +#endif

[...]
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[U-Boot] [PATCH 0/3] Add support for st33zp24 i2c and spi TPMs

[Christophe Ricard]

Hi Simon,

After a first tentative in August 2015:
http://lists.denx.de/pipermail/u-boot/2015-August/222596.html

I finally found some spare time for a new round to send a new patchset version
bringing support for ST33ZP24 TPM 1.2 with i2c and spi support.

I have been able to follow all your guidance from my previous tentative
and got able to convert omap24xx_i2c and omap3_spi drivers to DM.
I will send them in a separate patchset as an RFC for your review.

Best Regards
Christophe



Christophe Ricard (3):
  tpm: Rename tpm_tis_infineon.h to tpm_tis.h and move infineon specific
stuff in tpm_infineon.c
  tpm: st33zp24: Add tpm st33zp24 support with i2c
  tpm: st33zp24: Add tpm st33zp24 spi support

 README|  11 +
 drivers/tpm/Kconfig   |  18 +
 drivers/tpm/Makefile  |   2 +
 drivers/tpm/{tpm_tis_infineon.h => tpm_tis.h} |  17 +-
 drivers/tpm/tpm_tis_infineon.c|  17 +-
 drivers/tpm/tpm_tis_st33zp24_i2c.c| 543 +
 drivers/tpm/tpm_tis_st33zp24_spi.c| 672 ++
 7 files changed, 1263 insertions(+), 17 deletions(-)
 rename drivers/tpm/{tpm_tis_infineon.h => tpm_tis.h} (86%)
 create mode 100644 drivers/tpm/tpm_tis_st33zp24_i2c.c
 create mode 100644 drivers/tpm/tpm_tis_st33zp24_spi.c

-- 
2.5.0

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Re: [U-Boot] [PATCH v7 7/7] mips: ath79: add AP143 reference board

[Daniel Schwierzeck]

Am Sonntag, den 17.01.2016, 02:13 +0800 schrieb Wills Wang:
> Signed-off-by: Wills Wang 

my comments in patch 6/7 apply to this patch too

> ---
> 
> Changes in v7:
> - Use KSEG1 address for debug port in ap143
> 
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> 
>  arch/mips/dts/Makefile|  1 +
>  arch/mips/dts/ap143.dts   | 43 
>  arch/mips/dts/qca953x.dtsi| 72
> ++
>  arch/mips/mach-ath79/Kconfig  |  5 +++
>  board/ath79/ap143/Kconfig |  9 +
>  board/ath79/ap143/MAINTAINERS |  6 +++
>  board/ath79/ap143/Makefile|  5 +++
>  board/ath79/ap143/ap143.c | 63 ++
>  configs/ap143_defconfig   | 43 
>  include/configs/ap143.h   | 91
> +++
>  10 files changed, 338 insertions(+)
>  create mode 100644 arch/mips/dts/ap143.dts
>  create mode 100644 arch/mips/dts/qca953x.dtsi
>  create mode 100644 board/ath79/ap143/Kconfig
>  create mode 100644 board/ath79/ap143/MAINTAINERS
>  create mode 100644 board/ath79/ap143/Makefile
>  create mode 100644 board/ath79/ap143/ap143.c
>  create mode 100644 configs/ap143_defconfig
>  create mode 100644 include/configs/ap143.h
> 
> diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
> index 3fd49eb..7da06c5 100644
> --- a/arch/mips/dts/Makefile
> +++ b/arch/mips/dts/Makefile
> @@ -3,6 +3,7 @@
>  #
>  
>  dtb-$(CONFIG_BOARD_AP121) += ap121.dtb
> +dtb-$(CONFIG_BOARD_AP143) += ap143.dtb
>  
>  targets += $(dtb-y)
>  
> diff --git a/arch/mips/dts/ap143.dts b/arch/mips/dts/ap143.dts
> new file mode 100644
> index 000..f53207e
> --- /dev/null
> +++ b/arch/mips/dts/ap143.dts
> @@ -0,0 +1,43 @@
> +/*
> + * Copyright (C) 2015-2016 Wills Wang 
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +/dts-v1/;
> +#include "qca953x.dtsi"
> +
> +/ {
> + model = "AP143 Reference Board";
> + compatible = "qca,ap143", "qca,qca953x";
> +
> + aliases {
> + spi0 = 
> + serial0 = 
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> + {
> + clock-frequency = <2500>;
> +};
> +
> + {
> + status = "okay";
> +};
> +
> + {
> + spi-max-frequency = <2500>;
> + status = "okay";
> + spi-flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "spi-flash";
> + memory-map = <0x9f00 0x0080>;
> + spi-max-frequency = <2500>;
> + reg = <0>;
> + };
> +};
> diff --git a/arch/mips/dts/qca953x.dtsi b/arch/mips/dts/qca953x.dtsi
> new file mode 100644
> index 000..8487fc9
> --- /dev/null
> +++ b/arch/mips/dts/qca953x.dtsi
> @@ -0,0 +1,72 @@
> +/*
> + * Copyright (C) 2015-2016 Wills Wang 
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include "skeleton.dtsi"
> +
> +/ {
> + compatible = "qca,qca953x";
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "mips,mips24Kc";
> + reg = <0>;
> + };
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + xtal: xtal {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-output-names = "xtal";
> + };
> + };
> +
> + ahb {
> + compatible = "simple-bus";
> + ranges;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + apb {
> + compatible = "simple-bus";
> + ranges;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + uart0: uart@1802 {
> + compatible = "ns16550";
> + reg = <0x1802 0x20>;
> + reg-shift = <2>;
> + clock-frequency = <2500>;
> +
> + status = "disabled";
> + };
> + };
> +
> + spi0: spi@1f00 {
> + compatible = "qca,ar7100-spi";
> + reg = <0x1f00 0x10>;
> +
> + status = "disabled";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +};
> diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach
> -ath79/Kconfig
> index 0fcd96a..f61efd2 100644
> --- a/arch/mips/mach-ath79/Kconfig
> +++ 

[U-Boot] [GIT PULL] u-boot-mips/master

[Daniel Schwierzeck]

Hi Tom,

please pull the first bunch of MIPS updates.

There is a possible merge conflict in dts/Makefile due to my patch [1]
in this PR and Thomas' patch [2] waiting in u-boot-fdt tree.

[1] http://patchwork.ozlabs.org/patch/566695/
[2] http://patchwork.ozlabs.org/patch/563669/


The following changes since commit 782acf7b52db6bec1a796773e3033b4afcd6c9e2:

  Merge git://git.denx.de/u-boot-rockchip (2016-01-15 08:11:15 -0500)

are available in the git repository at:

  git://git.denx.de/u-boot-mips.git master

for you to fetch changes up to 0e0efb40b874633360967f532eb1ed59ad02adbe:

  MIPS: implement bit manipulating I/O accessors (2016-01-16 21:06:46 +0100)


Daniel Schwierzeck (16):
  MIPS: fix annotation of _start and relocate_code
  MIPS: create .text sub-sections for assembler functions
  MIPS: do not build position-independent executables for SPL
  MIPS: add initial infrastructure for device-tree files
  MIPS: Kconfig: refactor machine setup
  MIPS: au1x00: move SoC header files to arch/mips/mach-au1x00/include/mach/
  MIPS: Kconfig: optimize gcc -march and -mtune setup
  MIPS: malta: do not pull in target header files in config.h
  MIPS: malta: fix IO accessor call
  MIPS: vct: fix I/O accessor calls
  MIPS: kconfig: add option for MIPS_L1_CACHE_SHIFT
  net: pcnet: refactor mapping of virtual addresses to physical ones
  MIPS: sync I/O related header files with linux-4.4
  MIPS: sync processor and register definitions with linux-4.4
  MIPS: fix SPDX license identifier in remaining arch header files
  MIPS: implement bit manipulating I/O accessors

Purna Chandra Mandal (1):
  MIPS: add asm/gpio.h to fix compilation error with CONFIG_CMD_GPIO.

 arch/Kconfig |1 +
 arch/mips/Kconfig|   33 ++-
 arch/mips/Makefile   |   23 +-
 arch/mips/config.mk  |   25 +-
 arch/mips/cpu/start.S|   12 +-
 arch/mips/dts/.gitignore |1 +
 arch/mips/dts/Makefile   |   16 ++
 arch/mips/dts/include/dt-bindings|1 +
 arch/mips/dts/skeleton.dtsi  |   23 ++
 arch/mips/include/asm/addrspace.h|   10 +-
 arch/mips/include/asm/asm.h  |  126 +-
 arch/mips/include/asm/bitops.h   |6 +-
 arch/mips/include/asm/byteorder.h|6 +-
 arch/mips/include/asm/cache.h|   14 +-
 arch/mips/include/asm/cachectl.h |6 +-
 arch/mips/include/asm/cacheops.h |6 +-
 arch/mips/include/asm/const.h|   31 +++
 arch/mips/include/asm/cpu-features.h |   30 +++
 arch/mips/include/asm/gpio.h |1 +
 arch/mips/include/asm/io.h   |  814
+
 arch/mips/include/asm/isadep.h   |6 +-
 arch/mips/include/asm/mach-generic/cpu-feature-overrides.h   |   11 +
 arch/mips/include/asm/mach-generic/ioremap.h |   32 +++
 arch/mips/include/asm/mach-generic/mangle-port.h |   50 
 arch/mips/include/asm/mach-generic/spaces.h  |  102 
 arch/mips/include/asm/mipsregs.h | 1495
-
 arch/mips/include/asm/pgtable-bits.h |  283
++
 arch/mips/include/asm/posix_types.h  |9 +-
 arch/mips/include/asm/processor.h|6 +-
 arch/mips/include/asm/ptrace.h   |   99 +---
 arch/mips/include/asm/reboot.h   |6 +-
 arch/mips/include/asm/reg.h  |6 +-
 arch/mips/include/asm/regdef.h   |   12 +-
 arch/mips/include/asm/sgidefs.h  |6 +-
 arch/mips/include/asm/string.h   |6 +-
 arch/mips/include/asm/system.h   |6 +-
 arch/mips/include/asm/types.h|6 +-
 arch/mips/include/asm/unaligned.h|6 +-
 arch/mips/lib/cache.c|4 +-
 arch/mips/lib/cache_init.S   |   16 +-
 arch/mips/mach-au1x00/au1x00_eth.c   |2 +-
 

[U-Boot] [PATCH 2/3] tpm: st33zp24: Add tpm st33zp24 support with i2c

[Christophe Ricard]

Add support for TPM ST33ZP24 family with i2c.

For i2c we are relying only on DM_I2C.

Signed-off-by: Christophe Ricard 
---

 README |   7 +
 drivers/tpm/Kconfig|   9 +
 drivers/tpm/Makefile   |   1 +
 drivers/tpm/tpm_tis_st33zp24_i2c.c | 543 +
 4 files changed, 560 insertions(+)
 create mode 100644 drivers/tpm/tpm_tis_st33zp24_i2c.c

diff --git a/README b/README
index 9423c34..e7c41c3 100644
--- a/README
+++ b/README
@@ -1432,6 +1432,13 @@ The following options need to be configured:
CONFIG_TPM_TIS_I2C_BURST_LIMITATION
Define the burst count bytes upper limit
 
+   CONFIG_TPM_ST33ZP24
+   Support for STMicroelectronics TPM devices. Requires DM_TPM 
support.
+
+   CONFIG_TPM_ST33ZP24_I2C
+   Support for STMicroelectronics ST33ZP24 I2C devices.
+   Requires TPM_ST33ZP24 and I2C.
+
CONFIG_TPM_ATMEL_TWI
Support for Atmel TWI TPM device. Requires I2C support.
 
diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig
index 5a75f85..9432160 100644
--- a/drivers/tpm/Kconfig
+++ b/drivers/tpm/Kconfig
@@ -64,4 +64,13 @@ config TPM_AUTH_SESSIONS
  TPM_LoadKey2 and TPM_GetPubKey are provided. Both features are
  available using the 'tpm' command, too.
 
+config TPM_ST33ZP24_I2C
+   bool "STMicroelectronics ST33ZP24 I2C TPM"
+   depends on TPM && DM_I2C
+   ---help---
+ This driver supports STMicroelectronics TPM devices connected on the 
I2C bus.
+ The usual tpm operations and the 'tpm' command can be used to talk
+ to the device using the standard TPM Interface Specification (TIS)
+ protocol
+
 endmenu
diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile
index 1d49e95..cb066d7 100644
--- a/drivers/tpm/Makefile
+++ b/drivers/tpm/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_TPM_ATMEL_TWI) += tpm_atmel_twi.o
 obj-$(CONFIG_TPM_TIS_INFINEON) += tpm_tis_infineon.o
 obj-$(CONFIG_TPM_TIS_LPC) += tpm_tis_lpc.o
 obj-$(CONFIG_TPM_TIS_SANDBOX) += tpm_tis_sandbox.o
+obj-$(CONFIG_TPM_ST33ZP24_I2C) += tpm_tis_st33zp24_i2c.o
diff --git a/drivers/tpm/tpm_tis_st33zp24_i2c.c 
b/drivers/tpm/tpm_tis_st33zp24_i2c.c
new file mode 100644
index 000..9e4829f
--- /dev/null
+++ b/drivers/tpm/tpm_tis_st33zp24_i2c.c
@@ -0,0 +1,543 @@
+/*
+ * STMicroelectronics TPM ST33ZP24 I2C UBOOT driver
+ *
+ * Copyright (C) 2016 STMicroelectronics
+ *
+ * Description: Device driver for ST33ZP24 I2C TPM TCG.
+ *
+ * This device driver implements the TPM interface as defined in
+ * the TCG TPM Interface Spec version 1.21, revision 1.0 and the
+ * STMicroelectronics Protocol Stack Specification version 1.2.0.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "tpm_tis.h"
+#include "tpm_internal.h"
+
+#define TPM_ACCESS 0x0
+#define TPM_STS0x18
+#define TPM_DATA_FIFO  0x24
+
+#define LOCALITY0  0
+
+#define TPM_DUMMY_BYTE 0xAA
+#define TPM_ST33ZP24_I2C_SLAVE_ADDR0x13
+
+#define TPM_WRITE_DIRECTION 0x80
+
+/*
+ * st33zp24_i2c_write8_reg
+ * Send byte to the TIS register according to the ST33ZP24 I2C protocol.
+ * @param: tpm_register, the tpm tis register where the data should be written
+ * @param: tpm_data, the tpm_data to write inside the tpm_register
+ * @param: tpm_size, The length of the data
+ * @return: Number of byte written successfully else an error code.
+ */
+static int st33zp24_i2c_write8_reg(struct udevice *dev, u8 tpm_register,
+  const u8 *tpm_data, size_t tpm_size)
+{
+   struct tpm_chip_priv *chip_priv = dev_get_uclass_priv(dev);
+
+   chip_priv->buf[0] = tpm_register;
+   memcpy(chip_priv->buf + 1, tpm_data, tpm_size);
+
+   return dm_i2c_write(dev, 0, chip_priv->buf, tpm_size + 1);
+}
+
+/*
+* st33zp24_i2c_read8_reg
+* Recv byte from the TIS register according to the ST33ZP24 I2C protocol.
+* @param: tpm_register, the tpm tis register where the data should be read
+* @param: tpm_data, the TPM response
+* @param: tpm_size, tpm TPM response size to read.
+* @return: Number of byte read successfully else an error code.
+*/
+static int st33zp24_i2c_read8_reg(struct udevice *dev, u8 tpm_register,
+ u8 *tpm_data, size_t tpm_size)
+{
+   int status;
+   u8 data;
+
+   data = TPM_DUMMY_BYTE;
+   status = st33zp24_i2c_write8_reg(dev, tpm_register, , 1);
+   if (status < 0)
+   return status;
+
+   return dm_i2c_read(dev, 0, tpm_data, tpm_size);
+}
+
+/*
+ * st33zp24_i2c_write
+ * Send byte to the TIS register according to the ST33ZP24 I2C protocol.
+ * @param: phy_id, the phy 

[U-Boot] [PATCH 3/3] tpm: st33zp24: Add tpm st33zp24 spi support

[Christophe Ricard]

Add support for TPM ST33ZP24 spi.

The ST33ZP24 does have a spi interface.
The transport protocol is proprietary.

For spi we are relying only on DM_SPI.

Signed-off-by: Christophe Ricard 
---

 README |   4 +
 drivers/tpm/Kconfig|   9 +
 drivers/tpm/Makefile   |   1 +
 drivers/tpm/tpm_tis_st33zp24_spi.c | 672 +
 4 files changed, 686 insertions(+)
 create mode 100644 drivers/tpm/tpm_tis_st33zp24_spi.c

diff --git a/README b/README
index e7c41c3..dc2917c 100644
--- a/README
+++ b/README
@@ -1439,6 +1439,10 @@ The following options need to be configured:
Support for STMicroelectronics ST33ZP24 I2C devices.
Requires TPM_ST33ZP24 and I2C.
 
+   CONFIG_TPM_ST33ZP24_SPI
+   Support for STMicroelectronics ST33ZP24 SPI devices.
+   Requires TPM_ST33ZP24 and SPI.
+
CONFIG_TPM_ATMEL_TWI
Support for Atmel TWI TPM device. Requires I2C support.
 
diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig
index 9432160..9a7b7f5 100644
--- a/drivers/tpm/Kconfig
+++ b/drivers/tpm/Kconfig
@@ -73,4 +73,13 @@ config TPM_ST33ZP24_I2C
  to the device using the standard TPM Interface Specification (TIS)
  protocol
 
+config TPM_ST33ZP24_SPI
+   bool "STMicroelectronics ST33ZP24 SPI TPM"
+   depends on TPM && DM_SPI
+   ---help---
+ This driver supports STMicroelectronics TPM devices connected on the 
SPI bus.
+ The usual tpm operations and the 'tpm' command can be used to talk
+ to the device using the standard TPM Interface Specification (TIS)
+ protocol
+
 endmenu
diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile
index cb066d7..c42a93f 100644
--- a/drivers/tpm/Makefile
+++ b/drivers/tpm/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_TPM_TIS_INFINEON) += tpm_tis_infineon.o
 obj-$(CONFIG_TPM_TIS_LPC) += tpm_tis_lpc.o
 obj-$(CONFIG_TPM_TIS_SANDBOX) += tpm_tis_sandbox.o
 obj-$(CONFIG_TPM_ST33ZP24_I2C) += tpm_tis_st33zp24_i2c.o
+obj-$(CONFIG_TPM_ST33ZP24_SPI) += tpm_tis_st33zp24_spi.o
diff --git a/drivers/tpm/tpm_tis_st33zp24_spi.c 
b/drivers/tpm/tpm_tis_st33zp24_spi.c
new file mode 100644
index 000..417bbf1
--- /dev/null
+++ b/drivers/tpm/tpm_tis_st33zp24_spi.c
@@ -0,0 +1,672 @@
+/*
+ * STMicroelectronics TPM ST33ZP24 SPI UBOOT driver
+ *
+ * Copyright (C) 2016 STMicroelectronics
+ *
+ * Description: Device driver for ST33ZP24 SPI TPM TCG.
+ *
+ * This device driver implements the TPM interface as defined in
+ * the TCG TPM Interface Spec version 1.21, revision 1.0 and the
+ * STMicroelectronics Protocol Stack Specification version 1.2.0.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "tpm_tis.h"
+#include "tpm_internal.h"
+
+#define TPM_ACCESS 0x0
+#define TPM_STS0x18
+#define TPM_DATA_FIFO  0x24
+
+#define LOCALITY0  0
+
+#define TPM_DATA_FIFO  0x24
+#define TPM_INTF_CAPABILITY0x14
+
+#define TPM_DUMMY_BYTE 0x00
+#define TPM_WRITE_DIRECTION0x80
+
+#define MAX_SPI_LATENCY15
+#define LOCALITY0  0
+
+#define ST33ZP24_OK0x5A
+#define ST33ZP24_UNDEFINED_ERR 0x80
+#define ST33ZP24_BADLOCALITY   0x81
+#define ST33ZP24_TISREGISTER_UKNOWN0x82
+#define ST33ZP24_LOCALITY_NOT_ACTIVATED0x83
+#define ST33ZP24_HASH_END_BEFORE_HASH_START0x84
+#define ST33ZP24_BAD_COMMAND_ORDER 0x85
+#define ST33ZP24_INCORECT_RECEIVED_LENGTH  0x86
+#define ST33ZP24_TPM_FIFO_OVERFLOW 0x89
+#define ST33ZP24_UNEXPECTED_READ_FIFO  0x8A
+#define ST33ZP24_UNEXPECTED_WRITE_FIFO 0x8B
+#define ST33ZP24_CMDRDY_SET_WHEN_PROCESSING_HASH_END   0x90
+#define ST33ZP24_DUMMY_BYTES   0x00
+
+/*
+ * TPM command can be up to 2048 byte, A TPM response can be up to
+ * 1024 byte.
+ * Between command and response, there are latency byte (up to 15
+ * usually on st33zp24 2 are enough).
+ *
+ * Overall when sending a command and expecting an answer we need if
+ * worst case:
+ * 2048 (for the TPM command) + 1024 (for the TPM answer).  We need
+ * some latency byte before the answer is available (max 15).
+ * We have 2048 + 1024 + 15.
+ */
+#define ST33ZP24_SPI_BUFFER_SIZE (TPM_BUFSIZE + (TPM_BUFSIZE / 2) +\
+ MAX_SPI_LATENCY)
+
+struct st33zp24_spi_phy {
+   int latency;
+
+   u8 tx_buf[ST33ZP24_SPI_BUFFER_SIZE];
+   u8 

[U-Boot] [PATCH 1/3] tpm: Rename tpm_tis_infineon.h to tpm_tis.h and move infineon specific stuff in tpm_infineon.c

[Christophe Ricard]

I2C protocol is not standardize for TPM 1.2.
TIS prococol is define by the Trusted Computing Group and potentially
available on several TPMs.

tpm_tis_infineon.h header is not generic enough.

Rename tpm_tis_infineon.h to tpm_tis.h and move infineon specific
defines/variables to tpm_tis_infineon.c

Signed-off-by: Christophe Ricard 
---

 drivers/tpm/{tpm_tis_infineon.h => tpm_tis.h} | 17 +
 drivers/tpm/tpm_tis_infineon.c| 17 -
 2 files changed, 17 insertions(+), 17 deletions(-)
 rename drivers/tpm/{tpm_tis_infineon.h => tpm_tis.h} (86%)

diff --git a/drivers/tpm/tpm_tis_infineon.h b/drivers/tpm/tpm_tis.h
similarity index 86%
rename from drivers/tpm/tpm_tis_infineon.h
rename to drivers/tpm/tpm_tis.h
index 3b510d1..25b152b 100644
--- a/drivers/tpm/tpm_tis_infineon.h
+++ b/drivers/tpm/tpm_tis.h
@@ -37,18 +37,12 @@ enum tpm_timeout {
 #define TPM_RSP_SIZE_BYTE  2
 #define TPM_RSP_RC_BYTE6
 
-enum i2c_chip_type {
-   SLB9635,
-   SLB9645,
-   UNKNOWN,
-};
-
 struct tpm_chip {
int is_open;
int locality;
u32 vend_dev;
unsigned long timeout_a, timeout_b, timeout_c, timeout_d;  /* msec */
-   enum i2c_chip_type chip_type;
+   ulong chip_type;
 };
 
 struct tpm_input_header {
@@ -134,13 +128,4 @@ enum tis_status {
TPM_STS_DATA_EXPECT = 0x08,
 };
 
-/* expected value for DIDVID register */
-#define TPM_TIS_I2C_DID_VID_9635 0x000b15d1L
-#define TPM_TIS_I2C_DID_VID_9645 0x001a15d1L
-
-#defineTPM_ACCESS(l)   (0x | ((l) << 4))
-#defineTPM_STS(l)  (0x0001 | ((l) << 4))
-#defineTPM_DATA_FIFO(l)(0x0005 | ((l) << 4))
-#defineTPM_DID_VID(l)  (0x0006 | ((l) << 4))
-
 #endif
diff --git a/drivers/tpm/tpm_tis_infineon.c b/drivers/tpm/tpm_tis_infineon.c
index f57c328..a4b6741 100644
--- a/drivers/tpm/tpm_tis_infineon.c
+++ b/drivers/tpm/tpm_tis_infineon.c
@@ -30,17 +30,32 @@
 #include 
 #include 
 
-#include "tpm_tis_infineon.h"
+#include "tpm_tis.h"
 #include "tpm_internal.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+enum i2c_chip_type {
+   SLB9635,
+   SLB9645,
+   UNKNOWN,
+};
+
+/* expected value for DIDVID register */
+#define TPM_TIS_I2C_DID_VID_9635 0x000b15d1L
+#define TPM_TIS_I2C_DID_VID_9645 0x001a15d1L
+
 static const char * const chip_name[] = {
[SLB9635] = "slb9635tt",
[SLB9645] = "slb9645tt",
[UNKNOWN] = "unknown/fallback to slb9635",
 };
 
+#defineTPM_ACCESS(l)   (0x | ((l) << 4))
+#defineTPM_STS(l)  (0x0001 | ((l) << 4))
+#defineTPM_DATA_FIFO(l)(0x0005 | ((l) << 4))
+#defineTPM_DID_VID(l)  (0x0006 | ((l) << 4))
+
 /*
  * tpm_tis_i2c_read() - read from TPM register
  * @addr: register address to read from
-- 
2.5.0

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[U-Boot] [PATCH 2/2] tpm: tpm_tis_lpc: fix typo

[Christophe Ricard]

TPM_TIS_LPC is connected to the LPC bus, not I2C.

Signed-off-by: Christophe Ricard 
---

 drivers/tpm/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig
index 31b35f7..5a75f85 100644
--- a/drivers/tpm/Kconfig
+++ b/drivers/tpm/Kconfig
@@ -50,7 +50,7 @@ config TPM_TIS_LPC
bool "Enable support for Infineon SLB9635/45 TPMs on LPC"
depends on TPM && X86
help
- This driver supports Infineon TPM devices connected on the I2C bus.
+ This driver supports Infineon TPM devices connected on the LPC bus.
  The usual tpm operations and the 'tpm' command can be used to talk
  to the device using the standard TPM Interface Specification (TIS)
  protocol
-- 
2.5.0

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[U-Boot] [PATCH 1/2] tpm: Fix fault in case CONFIG_DM_TPM is set without any TPM

[Christophe Ricard]

In case CONFIG_DM_TPM was set without any TPM chipset configured a fault
was generated (NULL pointer access).

Signed-off-by: Christophe Ricard 
---

 common/cmd_tpm.c | 2 +-
 lib/tpm.c| 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/cmd_tpm.c b/common/cmd_tpm.c
index add6bfb..6edf3e9 100644
--- a/common/cmd_tpm.c
+++ b/common/cmd_tpm.c
@@ -448,7 +448,7 @@ static int get_tpm(struct udevice **devp)
int rc;
 
rc = uclass_first_device(UCLASS_TPM, devp);
-   if (rc) {
+   if (rc || !*devp) {
printf("Could not find TPM (ret=%d)\n", rc);
return CMD_RET_FAILURE;
}
diff --git a/lib/tpm.c b/lib/tpm.c
index 8a62216..f428d45 100644
--- a/lib/tpm.c
+++ b/lib/tpm.c
@@ -262,7 +262,7 @@ int tpm_init(void)
struct udevice *dev;
 
err = uclass_first_device(UCLASS_TPM, );
-   if (err)
+   if (err || !dev)
return err;
return tpm_open(dev);
 }
-- 
2.5.0

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Re: [U-Boot] [PATCH v6 00/10] add support for atheros ath79 based SOCs

[Marek Vasut]

On Saturday, January 16, 2016 at 05:08:37 PM, Wills Wang wrote:
> On Saturday, January 16, 2016 11:33 PM, Marek Vasut wrote:
> > On Saturday, January 16, 2016 at 02:15:27 PM, Wills Wang wrote:
> >> On Saturday, January 16, 2016 01:26 PM, Marek Vasut wrote:
> >>> On Monday, January 04, 2016 at 12:06:17 PM, Wills Wang wrote:
>  These series of patch add support for atheros ath79 based SOCs in
>  u-boot, at the present moment it's just available for ar933x and
>  qca953x chip.
>  
>  Changes in v6:
>  - Remove useless "else"
>  - Move ar933x as separate patch
>  - Add get_bootstrap in reset.c
>  - Use map_physmem instead of KSEG1ADDR
>  - Add arch_cpu_init for detect SOC type for early
>  - Define magic value in ddr.c
>  - Remove wait loop in putc and getc
>  - Use map_physmem instead of KSEG1ADDR
>  - Add rrw_delay in ath79_spi_priv for more accurate timing
>  - Remove ath79_spi_delay
>  - Calculate delay in ath79_spi_set_speed
>  - Convert SZ_XXX into hex in ap121.h
>  - Remove useless CONFIG_SYS_INIT_SP_OFFSET in ap121.h
>  - Add board_early_init_f for DDR and pin initialization
>  - Select UART and SPI in ap121_defconfig
>  - Add support for qca953x
> >>> 
> >>> I wanted to try this patchset, so I picked [1], since I didn't feel
> >>> like fishing out patches from the list. Especially since this wasn't
> >>> sent as a series, but as separate patches, which makes things
> >>> annoying.
> >>> 
> >>> The [1] does not even compile, which is surprising. I would expect that
> >>> if you submit patches, you would at least compile-test them. Sigh. I
> >>> needed this patch:
> >>> 
> >>> ---8<---
> >>> diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c
> >>> index 2952679..140c65c 100644
> >>> --- a/arch/mips/mach-ath79/cpu.c
> >>> +++ b/arch/mips/mach-ath79/cpu.c
> >>> @@ -9,8 +9,8 @@
> >>> 
> >>>#include 
> >>>#include 
> >>>#include 
> >>> 
> >>> -#include 
> >>> -#include 
> >>> +#include 
> >>> +#include 
> >>> 
> >>>struct ath79_soc_desc {
> >>>
> >>>   enum ath79_soc_type soc;
> >>> 
> >>> diff --git a/arch/mips/mach-ath79/reset.c
> >>> b/arch/mips/mach-ath79/reset.c index 410b900..fe32d80 100644
> >>> --- a/arch/mips/mach-ath79/reset.c
> >>> +++ b/arch/mips/mach-ath79/reset.c
> >>> @@ -9,7 +9,7 @@
> >>> 
> >>>#include 
> >>>#include 
> >>>#include 
> >>> 
> >>> -#include 
> >>> +#include 
> >>> 
> >>>#include 
> >>>
> >>>void _machine_restart(void)
> >>> 
> >>> --->8---
> >> 
> >> Marek, you can try my repository at
> >> https://github.com/willswang/u-boot-ath79,
> >> I have fixed the compiling issue about headers.
> >> I'm very sorry about this compiling error, my work tree have a residual
> >> symbol
> >> link between arch/mips/include/asm/arch and
> >> arch/mips/mach-ath79/include/mach.
> >> it was not removed when i executed "make clean" to rebuild,  so, my
> >> compiling
> >> didn't discover this problem before this. now i clone this remote branch
> >> into a new
> >> location and find this issue.
> > 
> > You should do git clean -fdx to zap everything before doing the rebuild
> > and repost. This way, you can be sure that you have no residual stuff in
> > your tree.
> > 
> > Also, if make clean doesn't remove objects , there is some other problem
> > which needs attention.
> > 
> >>> Once I managed to fix things, I compiled ap121. I tried booting it on
> >>> arduino yun (ar9331), but it hung in start.S in setup_c0_status . If I
> >>> comment this out, it hangs in lowlevel_init, right at the beginning.
> >>> That's where I gave up.
> > 
> > What about this one? Did you ever boot-test these patches ? I can
> > probably understand why setup_c0_status might hang, but I don't quite
> > understand why would lowlevel_init hang so early.
> 
> Did your board still hang if compiling from my repository?

I don't see any difference in start.S and lowlevel_init.S , so probably yes.
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Re: [U-Boot] [PATCH v7 3/7] mips: ath79: add support for QCA953x SOCs

[Marek Vasut]

On Saturday, January 16, 2016 at 07:13:49 PM, Wills Wang wrote:
> This patch enable work for qca953x SOC.
> 
> Signed-off-by: Wills Wang 
> ---
> 
> Changes in v7:
> - Use CKSEGxADDR instead of KSEGxADDR for qca953x
> 
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None

[...]

> +int get_serial_clock(void)
> +{
> + return qca953x_get_xtal();
> +}
> +
> +int get_clocks(void)
> +{
> + void __iomem *regs;
> + u32 val, ctrl, xtal, pll, div;

This looks like a copy of the same code in patch 2/7 .

> + regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
> +MAP_NOCACHE);
> +
> + xtal = qca953x_get_xtal();
> + ctrl = readl(regs + QCA953X_PLL_CLK_CTRL_REG);
> + val = readl(regs + QCA953X_PLL_CPU_CONFIG_REG);

[...]

> +void ddr_init(void)
> +{
> + void __iomem *regs;
> + u32 val;

This looks like a copy of the same code in patch 2/7 .

> + regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
> +MAP_NOCACHE);
> + val = get_bootstrap();
> + if (val & QCA953X_BOOTSTRAP_DDR1) {
> + writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF);
> + udelay(10);
> +
> + /* For 16-bit DDR */
> + writel(0x, regs + AR71XX_DDR_REG_RD_CYCLE);
> + udelay(100);
> +
> + /* Burst size */
> + writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
> + udelay(100);
> + writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
> + udelay(100);
> +
> + /* AHB maximum timeout */
> + writel(0xf, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
> + udelay(100);
> +
> + /* DRAM timing */
> + writel(DDR1_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
> + udelay(100);
> + writel(DDR1_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
> + udelay(100);
> + writel(DDR1_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
> + udelay(100);

[...]
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Re: [U-Boot] [PATCH v7 2/7] mips: ath79: add support for AR933x SOCs

[Marek Vasut]

On Saturday, January 16, 2016 at 07:13:48 PM, Wills Wang wrote:
> This patch enable work for ar933x SOC.

And it adds DDR code and clock code ... which is missing from the commit 
message.

> Signed-off-by: Wills Wang 
> ---

[...]

> +void ddr_init(void)
> +{
> + void __iomem *regs;
> + u32 val;
> +
> + regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
> +MAP_NOCACHE);
> +
> + writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
> + writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
> +
> + val = get_bootstrap();
> + if (val & AR933X_BOOTSTRAP_DDR2) {
> + /* AHB maximum timeout */
> + writel(0xf, regs + AR933X_DDR_REG_TIMEOUT_MAX);
> +
> + /* Enable DDR2 */
> + writel(DDR2_CONF_VAL, regs + AR933X_DDR_REG_DDR2_CONFIG);
> +
> + /* Precharge All */
> + writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
> +
> + /* Disable High Temperature Self-Refresh, Full Array */
> + writel(0x00, regs + AR933X_DDR_REG_EMR2);
> + /* Extended Mode Register 2 Set (EMR2S) */
> + writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
> +
> + writel(0x00, regs + AR933X_DDR_REG_EMR3);
> + /* Extended Mode Register 3 Set (EMR3S) */
> + writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
> +
> + /* Enable DLL,  Full strength, ODT Disabled */
> + writel(0x00, regs + AR71XX_DDR_REG_EMR);
> + /* Extended Mode Register Set (EMRS) */
> + writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
> +
> + /* Reset DLL */
> + writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
> + /* Mode Register Set (MRS) */
> + writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);

Make sure that there is at least a newline before comment, to improve the
readability of the code.

> + /* Precharge All */
> + writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
> +
> + /* Auto Refresh */
> + writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
> + writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
> +
> + /* Write recovery (WR) 6 clock, CAS Latency 3,
> +  * Burst Length 8 */

Fix the multiline comments please.

> + writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
> + /* Mode Register Set (MRS) */
> + writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
> +
> + /* Enable OCD defaults, Enable DLL,
> +  * Reduced Drive Strength */
> + writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
> + /* Extended Mode Register Set (EMRS) */
> + writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);

[...]

> +void ddr_tap_tuning(void)
> +{
> + void __iomem *regs;
> + u32 *addr_k0, *addr_k1, *addr;
> + u32 val, tap, upper, lower;
> + int i, j, dir, err, done;
> +
> + regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
> +MAP_NOCACHE);

Explanation of this code would be great. To an external reviewer, this
is entirely inobvious.

> + addr = (void *)CKSEG0ADDR(0x2000);
> + for (i = 0; i < 256; i++) {
> + val = 0;
> + for (j = 0; j < 8; j++) {
> + if (i & (1 << j)) {
> + if (j % 2)
> + val |= 0x;
> + else
> + val |= 0x;
> + }
> +
> + if (j % 2) {
> + *addr++ = val;
> + val = 0;
> + }
> + }
> + }
> +
> + err = 0;
> + done = 0;
> + dir = 1;
> + tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
> + val = tap;
> + while (!done) {
> + err = 0;
> + writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
> + writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
> + for (i = 0; i < 2; i++) {
> + addr_k1 = (void *)CKSEG1ADDR(0x2000);
> + addr_k0 = (void *)CKSEG0ADDR(0x2000);
> + addr = (void *)CKSEG0ADDR(0x3000);
> +
> + while (addr_k0 < addr) {
> + if (*addr_k1++ != *addr_k0++) {
> + err = 1;
> + break;
> + }
> + }
> +
> + if (err)
> + break;
> + }
> +
> + if (err) {
> + if (dir) {
> + dir = 0;
> + 

Re: [U-Boot] [PATCH v7 6/7] mips: ath79: add AP121 reference board

[Daniel Schwierzeck]

Am Sonntag, den 17.01.2016, 02:13 +0800 schrieb Wills Wang:
> Signed-off-by: Wills Wang 
> ---
> 
> Changes in v7:
> - Use KSEG1 address for debug port in ap121
> 
> Changes in v6:
> - Convert SZ_XXX into hex in ap121.h
> - Remove useless CONFIG_SYS_INIT_SP_OFFSET in ap121.h
> - Add board_early_init_f for DDR and pin initialization
> - Select UART and SPI in ap121_defconfig
> 
> Changes in v5:
> - Move CONFIG_SYS_TEXT_BASE into ap121.h, and remove config.mk
> - Remove useless README file
> - Remove useless checkboard function
> 
> Changes in v4: None
> Changes in v3:
> - Add support for device tree
> 
> Changes in v2:
> - Add a reference board implemention
> 
>  arch/mips/dts/Makefile|  2 +-
>  arch/mips/dts/ap121.dts   | 43 +
>  arch/mips/dts/ar933x.dtsi | 70
> ++
>  arch/mips/mach-ath79/Kconfig  | 11 ++
>  board/ath79/ap121/Kconfig |  9 +
>  board/ath79/ap121/MAINTAINERS |  6 +++
>  board/ath79/ap121/Makefile|  5 +++
>  board/ath79/ap121/ap121.c | 47 +++
>  configs/ap121_defconfig   | 42 +
>  include/configs/ap121.h   | 87
> +++
>  10 files changed, 321 insertions(+), 1 deletion(-)
>  create mode 100644 arch/mips/dts/ap121.dts
>  create mode 100644 arch/mips/dts/ar933x.dtsi
>  create mode 100644 board/ath79/ap121/Kconfig
>  create mode 100644 board/ath79/ap121/MAINTAINERS
>  create mode 100644 board/ath79/ap121/Makefile
>  create mode 100644 board/ath79/ap121/ap121.c
>  create mode 100644 configs/ap121_defconfig
>  create mode 100644 include/configs/ap121.h
> 
> diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
> index 47b6eb5..3fd49eb 100644
> --- a/arch/mips/dts/Makefile
> +++ b/arch/mips/dts/Makefile
> @@ -2,7 +2,7 @@
>  # SPDX-License-Identifier:   GPL-2.0+
>  #
>  
> -dtb-y +=
> +dtb-$(CONFIG_BOARD_AP121) += ap121.dtb
>  
>  targets += $(dtb-y)
>  
> diff --git a/arch/mips/dts/ap121.dts b/arch/mips/dts/ap121.dts
> new file mode 100644
> index 000..e31f601
> --- /dev/null
> +++ b/arch/mips/dts/ap121.dts
> @@ -0,0 +1,43 @@
> +/*
> + * Copyright (C) 2015-2016 Wills Wang 
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +/dts-v1/;
> +#include "ar933x.dtsi"
> +
> +/ {
> + model = "AP121 Reference Board";
> + compatible = "qca,ap121", "qca,ar933x";
> +
> + aliases {
> + spi0 = 
> + serial0 = 
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> + {
> + clock-frequency = <2500>;
> +};
> +
> + {
> + status = "okay";
> +};
> +
> + {
> + spi-max-frequency = <2500>;
> + status = "okay";
> + spi-flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "spi-flash";
> + memory-map = <0x9f00 0x0080>;
> + spi-max-frequency = <2500>;
> + reg = <0>;
> + };
> +};
> diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi
> new file mode 100644
> index 000..b505938
> --- /dev/null
> +++ b/arch/mips/dts/ar933x.dtsi
> @@ -0,0 +1,70 @@
> +/*
> + * Copyright (C) 2015-2016 Wills Wang 
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include "skeleton.dtsi"
> +
> +/ {
> + compatible = "qca,ar933x";
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "mips,mips24Kc";
> + reg = <0>;
> + };
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + xtal: xtal {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-output-names = "xtal";
> + };
> + };
> +
> + ahb {
> + compatible = "simple-bus";
> + ranges;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + apb {
> + compatible = "simple-bus";
> + ranges;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + uart0: uart@1802 {
> + compatible = "qca,ar9330-uart";
> + reg = <0x1802 0x20>;
> +
> + status = "disabled";
> + };
> + };
> +
> + spi0: spi@1f00 {
> + compatible = "qca,ar7100-spi";
> + reg = <0x1f00 0x10>;
> +
> + status = "disabled";
> +
> + 

[U-Boot] [PATCH v4 8/8] dm: x86: spi: Convert ICH SPI driver to driver model PCI API

[Simon Glass]

At present this SPI driver works by searching the PCI buses for its
peripheral. It also uses the legacy PCI API.

In addition the driver has code to determine the type of Intel PCH that is
used (version 7 or version 9). Now that we have proper PCH drivers we can
use those to obtain the information we need.

While the device tree has a node for the SPI peripheral it is not in the
right place. It should be on the PCI bus as a sub-peripheral of the LPC
device.

Update the device tree files to show the SPI controller within the PCH, so
that PCI access works as expected.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v4:
- Add BIOS_CTRL address for PCH9

Changes in v3:
- Use the set_spi_protect() PCH method

Changes in v2:
- Adjust code for earlier commits
- Move the SPI base code into the PCH drivers

 arch/x86/cpu/coreboot/pci.c |   3 +-
 arch/x86/cpu/irq.c  |   7 +-
 arch/x86/cpu/ivybridge/bd82x6x.c|  47 ++-
 arch/x86/dts/bayleybay.dts  | 160 +++-
 arch/x86/dts/broadwell_som-6896.dts |  23 --
 arch/x86/dts/chromebook_link.dts|   5 +-
 arch/x86/dts/chromebox_panther.dts  |  33 
 arch/x86/dts/crownbay.dts   | 150 +
 arch/x86/dts/galileo.dts|  98 +++---
 arch/x86/dts/minnowmax.dts  | 158 ++-
 arch/x86/dts/qemu-x86_i440fx.dts|  26 +++---
 arch/x86/dts/qemu-x86_q35.dts   |  38 +
 drivers/spi/ich.c   | 152 --
 13 files changed, 458 insertions(+), 442 deletions(-)

diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index 41e29a6..7f5087a 100644
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -14,7 +14,8 @@
 #include 
 
 static const struct udevice_id generic_pch_ids[] = {
-   { .compatible = "intel,pch" },
+   { .compatible = "intel,pch7" },
+   { .compatible = "intel,pch9" },
{ }
 };
 
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 35b29f6..205405b 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -97,6 +97,7 @@ static int create_pirq_routing_table(void)
struct irq_routing_table *rt;
struct irq_info *slot, *slot_base;
int irq_entries = 0;
+   int parent;
int i;
int ret;
 
@@ -106,7 +107,11 @@ static int create_pirq_routing_table(void)
return -EINVAL;
}
 
-   ret = fdtdec_get_pci_addr(blob, node, FDT_PCI_SPACE_CONFIG,
+   /* TODO(s...@chromium.org): Drop this when PIRQ is a driver */
+   parent = fdt_parent_offset(blob, node);
+   if (parent < 0)
+   return -EINVAL;
+   ret = fdtdec_get_pci_addr(blob, parent, FDT_PCI_SPACE_CONFIG,
  "reg", );
if (ret)
return ret;
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 434dfd6..c000aca 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -3,12 +3,12 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
-
 #include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -16,6 +16,8 @@
 #include 
 #include 
 
+#define BIOS_CTRL  0xdc
+
 void bd82x6x_pci_init(pci_dev_t dev)
 {
u16 reg16;
@@ -96,6 +98,7 @@ static int bd82x6x_probe(struct udevice *dev)
return 0;
 }
 
+/* TODO(s...@chromium.org): Move this to the PCH init() method */
 int bd82x6x_init(void)
 {
const void *blob = gd->fdt_blob;
@@ -116,6 +119,47 @@ int bd82x6x_init(void)
return 0;
 }
 
+static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep)
+{
+   u32 rcba;
+
+   dm_pci_read_config32(dev, PCH_RCBA, );
+   /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
+   rcba = rcba & 0xc000;
+   *sbasep = rcba + 0x3800;
+
+   return 0;
+}
+
+static enum pch_version bd82x6x_pch_get_version(struct udevice *dev)
+{
+   return PCHV_9;
+}
+
+static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
+{
+   uint8_t bios_cntl;
+
+   /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
+   dm_pci_read_config8(dev, BIOS_CTRL, _cntl);
+   if (protect) {
+   bios_cntl &= ~BIOS_CTRL_BIOSWE;
+   bios_cntl |= BIT(5);
+   } else {
+   bios_cntl |= BIOS_CTRL_BIOSWE;
+   bios_cntl &= ~BIT(5);
+   }
+   dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
+
+   return 0;
+}
+
+static const struct pch_ops bd82x6x_pch_ops = {
+   .get_sbase  = bd82x6x_pch_get_sbase,
+   .get_version= bd82x6x_pch_get_version,
+   .set_spi_protect = bd82x6x_set_spi_protect,
+};
+
 static const struct udevice_id bd82x6x_ids[] = {
{ .compatible = "intel,bd82x6x" },
{ 

[U-Boot] [PATCH v4 5/8] dm: x86: Add a driver for Intel PCH7

[Simon Glass]

At some point we may need to distinguish between different types of PCHs,
but for existing supported platforms we only need to worry about version 7
and version 9 bridges. Add a driver for the PCH7.

Signed-off-by: Simon Glass 
---

Changes in v4:
- Correct BIOS_CTRL address for PCH7

Changes in v3: None
Changes in v2:
- Rename the PCH functions
- Update the get_version() handle to use an enum
- Add a function to obtain the SPI base address
- Add enums for BIOS_CTRL register and bits

 drivers/pch/Makefile |  1 +
 drivers/pch/pch7.c   | 61 
 include/pch.h|  8 +++
 3 files changed, 70 insertions(+)
 create mode 100644 drivers/pch/pch7.c

diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile
index d69a99c..33aa727 100644
--- a/drivers/pch/Makefile
+++ b/drivers/pch/Makefile
@@ -3,3 +3,4 @@
 #
 
 obj-y += pch-uclass.o
+obj-y += pch7.o
diff --git a/drivers/pch/pch7.c b/drivers/pch/pch7.c
new file mode 100644
index 000..ef72422
--- /dev/null
+++ b/drivers/pch/pch7.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+#define BIOS_CTRL  0xd8
+
+static int pch7_get_sbase(struct udevice *dev, ulong *sbasep)
+{
+   u32 rcba;
+
+   dm_pci_read_config32(dev, PCH_RCBA, );
+   /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
+   rcba = rcba & 0xc000;
+   *sbasep = rcba + 0x3020;
+
+   return 0;
+}
+
+static enum pch_version pch7_get_version(struct udevice *dev)
+{
+   return PCHV_7;
+}
+
+static int pch7_set_spi_protect(struct udevice *dev, bool protect)
+{
+   uint8_t bios_cntl;
+
+   /* Adjust the BIOS write protect to dis/allow write commands */
+   dm_pci_read_config8(dev, BIOS_CTRL, _cntl);
+   if (protect)
+   bios_cntl &= ~BIOS_CTRL_BIOSWE;
+   else
+   bios_cntl |= BIOS_CTRL_BIOSWE;
+   dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
+
+   return 0;
+}
+
+static const struct pch_ops pch7_ops = {
+   .get_sbase  = pch7_get_sbase,
+   .get_version= pch7_get_version,
+   .set_spi_protect = pch7_set_spi_protect,
+};
+
+static const struct udevice_id pch7_ids[] = {
+   { .compatible = "intel,pch7" },
+   { }
+};
+
+U_BOOT_DRIVER(pch7_drv) = {
+   .name   = "intel-pch7",
+   .id = UCLASS_PCH,
+   .of_match   = pch7_ids,
+   .ops= _ops,
+};
diff --git a/include/pch.h b/include/pch.h
index ff26865..dbfa265 100644
--- a/include/pch.h
+++ b/include/pch.h
@@ -14,6 +14,14 @@ enum pch_version {
PCHV_9,
 };
 
+enum {
+   PCH_RCBA= 0xf0,
+};
+
+enum {
+   BIOS_CTRL_BIOSWE= BIT(0),
+};
+
 /* Operations for the Platform Controller Hub */
 struct pch_ops {
/**
-- 
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[U-Boot] [PATCH v4 3/8] dm: pci: Avoid using pci_bus_to_hose() in the uclass

[Simon Glass]

This function is only available for compatibility with old code. Avoid
using it in the uclass.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
Tested-by: Bin Meng 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/pci/pci_auto.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 5cfa135..88bc416 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -9,6 +9,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 
@@ -167,8 +168,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, 
int sub_bus)
struct pci_region *pci_prefetch;
struct pci_region *pci_io;
u16 cmdstat, prefechable_64;
-   /* The root controller has the region information */
-   struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+   struct udevice *ctlr = pci_get_controller(dev);
+   struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
 
pci_mem = ctlr_hose->pci_mem;
pci_prefetch = ctlr_hose->pci_prefetch;
@@ -248,9 +249,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, 
int sub_bus)
struct pci_region *pci_mem;
struct pci_region *pci_prefetch;
struct pci_region *pci_io;
-
-   /* The root controller has the region information */
-   struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+   struct udevice *ctlr = pci_get_controller(dev);
+   struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
 
pci_mem = ctlr_hose->pci_mem;
pci_prefetch = ctlr_hose->pci_prefetch;
@@ -311,13 +311,13 @@ int dm_pciauto_config_device(struct udevice *dev)
unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
unsigned short class;
bool enum_only = false;
+   struct udevice *ctlr = pci_get_controller(dev);
+   struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
int n;
 
 #ifdef CONFIG_PCI_ENUM_ONLY
enum_only = true;
 #endif
-   /* The root controller has the region information */
-   struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
 
pci_mem = ctlr_hose->pci_mem;
pci_prefetch = ctlr_hose->pci_prefetch;
-- 
2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH v4 1/8] dm: pci: Move pci_bus_to_hose() to compatibility

[Simon Glass]

This function should not be used by driver-model code, so move it to the
compatibility portion.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v4: None
Changes in v3: None
Changes in v2:
- Add more detail to the function comment

 drivers/pci/pci-uclass.c   | 16 +---
 drivers/pci/pci_compat.c   | 15 +++
 drivers/pci/pci_internal.h | 12 
 3 files changed, 28 insertions(+), 15 deletions(-)

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 685df9d..6dd4883 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -22,7 +22,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static int pci_get_bus(int busnum, struct udevice **busp)
+int pci_get_bus(int busnum, struct udevice **busp)
 {
int ret;
 
@@ -41,20 +41,6 @@ static int pci_get_bus(int busnum, struct udevice **busp)
return ret;
 }
 
-struct pci_controller *pci_bus_to_hose(int busnum)
-{
-   struct udevice *bus;
-   int ret;
-
-   ret = pci_get_bus(busnum, );
-   if (ret) {
-   debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret);
-   return NULL;
-   }
-
-   return dev_get_uclass_priv(bus);
-}
-
 struct udevice *pci_get_controller(struct udevice *dev)
 {
while (device_is_on_pci_bus(dev))
diff --git a/drivers/pci/pci_compat.c b/drivers/pci/pci_compat.c
index dd15eb1..ddaf358 100644
--- a/drivers/pci/pci_compat.c
+++ b/drivers/pci/pci_compat.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include "pci_internal.h"
 
 #define PCI_HOSE_OP(rw, name, size, type)  \
 int pci_hose_##rw##_config_##name(struct pci_controller *hose, \
@@ -36,3 +37,17 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int 
index)
return -1;
return dm_pci_get_bdf(dev);
 }
+
+struct pci_controller *pci_bus_to_hose(int busnum)
+{
+   struct udevice *bus;
+   int ret;
+
+   ret = pci_get_bus(busnum, );
+   if (ret) {
+   debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret);
+   return NULL;
+   }
+
+   return dev_get_uclass_priv(bus);
+}
diff --git a/drivers/pci/pci_internal.h b/drivers/pci/pci_internal.h
index 0867575..616b9c1 100644
--- a/drivers/pci/pci_internal.h
+++ b/drivers/pci/pci_internal.h
@@ -47,4 +47,16 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, 
int sub_bus);
  */
 int dm_pciauto_config_device(struct udevice *dev);
 
+/**
+ * pci_get_bus() - Get a pointer to a bus, given its number
+ *
+ * This looks up a PCI bus based on its bus number. The bus is probed if
+ * necessary.
+ *
+ * @busnum:PCI bus number to look up
+ * @busp:  Returns PCI bus on success
+ * @return 0 on success, or -ve error
+ */
+int pci_get_bus(int busnum, struct udevice **busp);
+
 #endif
-- 
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[U-Boot] [PATCH v4 6/8] dm: x86: Add a driver for Intel PCH9

[Simon Glass]

At some point we may need to distinguish between different types of PCHs,
but for existing supported platforms we only need to worry about version 7
and version 9 bridges. Add a driver for the PCH9.

Signed-off-by: Simon Glass 
---

Changes in v4: None
Changes in v3: None
Changes in v2:
- Rename the PCH functions
- Update the get_version() handle to use an enum

 drivers/pch/Makefile |  1 +
 drivers/pch/pch9.c   | 43 +++
 2 files changed, 44 insertions(+)
 create mode 100644 drivers/pch/pch9.c

diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile
index 33aa727..dde9e86 100644
--- a/drivers/pch/Makefile
+++ b/drivers/pch/Makefile
@@ -4,3 +4,4 @@
 
 obj-y += pch-uclass.o
 obj-y += pch7.o
+obj-y += pch9.o
diff --git a/drivers/pch/pch9.c b/drivers/pch/pch9.c
new file mode 100644
index 000..529cb02
--- /dev/null
+++ b/drivers/pch/pch9.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+#define SBASE_ADDR 0x54
+
+static int pch9_get_sbase(struct udevice *dev, ulong *sbasep)
+{
+   uint32_t sbase_addr;
+
+   dm_pci_read_config32(dev, SBASE_ADDR, _addr);
+   *sbasep = sbase_addr & 0xfe00;
+
+   return 0;
+}
+
+static enum pch_version pch9_get_version(struct udevice *dev)
+{
+   return PCHV_9;
+}
+
+static const struct pch_ops pch9_ops = {
+   .get_sbase  = pch9_get_sbase,
+   .get_version= pch9_get_version,
+};
+
+static const struct udevice_id pch9_ids[] = {
+   { .compatible = "intel,pch9" },
+   { }
+};
+
+U_BOOT_DRIVER(pch9_drv) = {
+   .name   = "intel-pch9",
+   .id = UCLASS_PCH,
+   .of_match   = pch9_ids,
+   .ops= _ops,
+};
-- 
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[U-Boot] [PATCH v4 2/8] dm: pci: Add a function to write a BAR

[Simon Glass]

Add a driver-model version of the pci_write_bar32 function so that this is
supported in the new API.

Signed-off-by: Simon Glass 
---

Changes in v4:
- Tidy up mentions on control bits in the header file

Changes in v3: None
Changes in v2:
- Rename the last parameter to 'addr'
- Update the comment to explain usable of this function

 drivers/pci/pci-uclass.c |  8 
 include/pci.h| 17 +++--
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 6dd4883..61292d7 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1053,6 +1053,14 @@ u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
return addr & PCI_BASE_ADDRESS_MEM_MASK;
 }
 
+void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
+{
+   int bar;
+
+   bar = PCI_BASE_ADDRESS_0 + barnum * 4;
+   dm_pci_write_config32(dev, bar, addr);
+}
+
 static int _dm_pci_bus_to_phys(struct udevice *ctlr,
   pci_addr_t bus_addr, unsigned long flags,
   unsigned long skip_mask, phys_addr_t *pa)
diff --git a/include/pci.h b/include/pci.h
index cb2562f..d0d152c 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -757,7 +757,9 @@ extern void pci_mpc85xx_init (struct pci_controller *hose);
 /**
  * pci_write_bar32() - Write the address of a BAR including control bits
  *
- * This writes a raw address (with control bits) to a bar
+ * This writes a raw address (with control bits) to a bar. This can be used
+ * with devices which require hard-coded addresses, not part of the normal
+ * PCI enumeration process.
  *
  * @hose:  PCI hose to use
  * @dev:   PCI device to update
@@ -765,7 +767,7 @@ extern void pci_mpc85xx_init (struct pci_controller *hose);
  * @addr:  BAR address with control bits
  */
 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
-u32 addr_and_ctrl);
+u32 addr);
 
 /**
  * pci_read_bar32() - read the address of a bar
@@ -1167,6 +1169,17 @@ int pci_get_regions(struct udevice *dev, struct 
pci_region **iop,
struct pci_region **memp, struct pci_region **prefp);
 
 /**
+ * dm_pci_write_bar32() - Write the address of a BAR
+ *
+ * This writes a raw address to a bar
+ *
+ * @dev:   PCI device to update
+ * @barnum:BAR number (0-5)
+ * @addr:  BAR address
+ */
+void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
+
+/**
  * dm_pci_read_bar32() - read a base address register from a device
  *
  * @dev:   Device to check
-- 
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[U-Boot] [PATCH v4 7/8] spi: ich: Separate out the read/write trace from normal debugging

[Simon Glass]

The trace is seldom useful for basic debugging. Allow it to be enabled
separately so that it is easier to see the more important init and error
debug messages.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v4: None
Changes in v3:
- Add a new patch to separate out the read/write trace from normal debugging

Changes in v2: None

 drivers/spi/ich.c | 24 +++-
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 59eaaea..887510b 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -20,6 +20,12 @@
 #define SPI_OPCODE_WREN  0x06
 #define SPI_OPCODE_FAST_READ 0x0b
 
+#ifdef DEBUG_TRACE
+#define debug_trace(fmt, args...) debug(fmt, ##args)
+#else
+#define debug_trace(x, args...)
+#endif
+
 struct ich_spi_platdata {
pci_dev_t dev;  /* PCI device number */
int ich_version;/* Controller version, 7 or 9 */
@@ -52,7 +58,7 @@ static u8 ich_readb(struct ich_spi_priv *priv, int reg)
 {
u8 value = readb(priv->base + reg);
 
-   debug("read %2.2x from %4.4x\n", value, reg);
+   debug_trace("read %2.2x from %4.4x\n", value, reg);
 
return value;
 }
@@ -61,7 +67,7 @@ static u16 ich_readw(struct ich_spi_priv *priv, int reg)
 {
u16 value = readw(priv->base + reg);
 
-   debug("read %4.4x from %4.4x\n", value, reg);
+   debug_trace("read %4.4x from %4.4x\n", value, reg);
 
return value;
 }
@@ -70,7 +76,7 @@ static u32 ich_readl(struct ich_spi_priv *priv, int reg)
 {
u32 value = readl(priv->base + reg);
 
-   debug("read %8.8x from %4.4x\n", value, reg);
+   debug_trace("read %8.8x from %4.4x\n", value, reg);
 
return value;
 }
@@ -78,19 +84,19 @@ static u32 ich_readl(struct ich_spi_priv *priv, int reg)
 static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg)
 {
writeb(value, priv->base + reg);
-   debug("wrote %2.2x to %4.4x\n", value, reg);
+   debug_trace("wrote %2.2x to %4.4x\n", value, reg);
 }
 
 static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg)
 {
writew(value, priv->base + reg);
-   debug("wrote %4.4x to %4.4x\n", value, reg);
+   debug_trace("wrote %4.4x to %4.4x\n", value, reg);
 }
 
 static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg)
 {
writel(value, priv->base + reg);
-   debug("wrote %8.8x to %4.4x\n", value, reg);
+   debug_trace("wrote %8.8x to %4.4x\n", value, reg);
 }
 
 static void write_reg(struct ich_spi_priv *priv, const void *value,
@@ -447,7 +453,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int 
bitlen,
}
memcpy(trans->cmd, dout, bytes);
trans->cmd_len = bytes;
-   debug("ICH SPI: Saved %d bytes\n", bytes);
+   debug_trace("ICH SPI: Saved %d bytes\n", bytes);
return 0;
}
 
@@ -462,7 +468,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int 
bitlen,
trans->out = trans->cmd;
trans->bytesout = trans->cmd_len;
using_cmd = 1;
-   debug("ICH SPI: Using %d bytes\n", trans->cmd_len);
+   debug_trace("ICH SPI: Using %d bytes\n", trans->cmd_len);
} else {
trans->out = dout;
trans->bytesout = dout ? bytes : 0;
@@ -520,7 +526,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int 
bitlen,
if (using_cmd && dout && bytes) {
trans->out = dout;
trans->bytesout = bytes;
-   debug("ICH SPI: Moving to data, %d bytes\n", bytes);
+   debug_trace("ICH SPI: Moving to data, %d bytes\n", bytes);
}
 
/* Preset control fields */
-- 
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[U-Boot] [PATCH v4 0/8] dm: x86: Convert ICH driver fully to driver model PCI API

[Simon Glass]

This is a small series to move the ICH driver over to use the driver model
PCI API. It involves creating PCH drivers which the ICH driver can use to
find out its base address.

At present irq-router is the 'PCH' node in most device tree files. This is
not really correct since the router is just one of the functions of the PCH.
Another is the SPI bus. So this series also moves irq-router down a level.
This still works with the same irq-router driver, since it just searches for
the first compatible node it can find.

A driver-model-compatible irq-router driver should be written but that is
left for later.

This series unfortunately needs testing on each board since each has a
separate change. I have tested minnowmax and chromebook_link so far.

Changes in v4:
- Tidy up mentions on control bits in the header file
- Return -ENOSYS if the version is unknown
- Correct BIOS_CTRL address for PCH7
- Add BIOS_CTRL address for PCH9

Changes in v3:
- Add a PCH method to enable/disable SPI flash protection
- Drop the pch_init() call
- Add a new patch to separate out the read/write trace from normal debugging
- Use the set_spi_protect() PCH method

Changes in v2:
- Add more detail to the function comment
- Rename the last parameter to 'addr'
- Update the comment to explain usable of this function
- Update the commit message and header file comments
- Use an enum for the PCH version
- Replace SBASE with SPI base
- Add a TODO to check if the init() method can be removed later
- Rename the PCH functions
- Update the get_version() handle to use an enum
- Add a function to obtain the SPI base address
- Add enums for BIOS_CTRL register and bits
- Rename the PCH functions
- Update the get_version() handle to use an enum
- Adjust code for earlier commits
- Move the SPI base code into the PCH drivers

Simon Glass (8):
  dm: pci: Move pci_bus_to_hose() to compatibility
  dm: pci: Add a function to write a BAR
  dm: pci: Avoid using pci_bus_to_hose() in the uclass
  dm: Expand the uclass for Platform Controller Hubs (PCH)
  dm: x86: Add a driver for Intel PCH7
  dm: x86: Add a driver for Intel PCH9
  spi: ich: Separate out the read/write trace from normal debugging
  dm: x86: spi: Convert ICH SPI driver to driver model PCI API

 arch/x86/cpu/coreboot/pci.c|   3 +-
 arch/x86/cpu/irq.c |   7 +-
 arch/x86/cpu/ivybridge/bd82x6x.c   |  47 +++-
 arch/x86/dts/bayleybay.dts | 160 +-
 arch/x86/dts/broadwell_som-6896.dts|  23 ++--
 arch/x86/dts/chromebook_link.dts   |   5 +-
 arch/x86/dts/chromebox_panther.dts |  33 +++---
 arch/x86/dts/crownbay.dts  | 150 
 arch/x86/dts/galileo.dts   |  98 
 arch/x86/dts/minnowmax.dts | 158 ++
 arch/x86/dts/qemu-x86_i440fx.dts   |  26 +++--
 arch/x86/dts/qemu-x86_q35.dts  |  38 ---
 arch/x86/lib/Makefile  |   1 -
 drivers/Makefile   |   1 +
 drivers/pch/Makefile   |   7 ++
 {arch/x86/lib => drivers/pch}/pch-uclass.c |  32 ++
 drivers/pch/pch7.c |  61 ++
 drivers/pch/pch9.c |  43 +++
 drivers/pci/pci-uclass.c   |  24 ++--
 drivers/pci/pci_auto.c |  14 +--
 drivers/pci/pci_compat.c   |  15 +++
 drivers/pci/pci_internal.h |  12 ++
 drivers/spi/ich.c  | 176 +
 include/pch.h  |  82 ++
 include/pci.h  |  17 ++-
 25 files changed, 757 insertions(+), 476 deletions(-)
 create mode 100644 drivers/pch/Makefile
 rename {arch/x86/lib => drivers/pch}/pch-uclass.c (50%)
 create mode 100644 drivers/pch/pch7.c
 create mode 100644 drivers/pch/pch9.c
 create mode 100644 include/pch.h

-- 
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[U-Boot] [PATCH v4 4/8] dm: Expand the uclass for Platform Controller Hubs (PCH)

[Simon Glass]

A Platform Controller Hub is an Intel concept - it is like the peripherals
on an SoC and is often in a separate chip from the CPU. The chip is typically
found on the first PCI bus and integrates multiple devices.

We have a very simple uclass to support PCHs. Add a few operations, such as
setting up the devices on the PCH and finding the SPI controller base
address. Also move it into drivers/pch/ since we will be adding a few PCH
drivers.

Signed-off-by: Simon Glass 
---

Changes in v4:
- Return -ENOSYS if the version is unknown

Changes in v3:
- Add a PCH method to enable/disable SPI flash protection
- Drop the pch_init() call

Changes in v2:
- Update the commit message and header file comments
- Use an enum for the PCH version
- Replace SBASE with SPI base
- Add a TODO to check if the init() method can be removed later

 arch/x86/lib/Makefile  |  1 -
 drivers/Makefile   |  1 +
 drivers/pch/Makefile   |  5 ++
 {arch/x86/lib => drivers/pch}/pch-uclass.c | 32 +
 include/pch.h  | 74 ++
 5 files changed, 112 insertions(+), 1 deletion(-)
 create mode 100644 drivers/pch/Makefile
 rename {arch/x86/lib => drivers/pch}/pch-uclass.c (50%)
 create mode 100644 include/pch.h

diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index cd5ecb6..43792bc 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -24,7 +24,6 @@ obj-$(CONFIG_I8254_TIMER) += i8254.o
 ifndef CONFIG_DM_PCI
 obj-$(CONFIG_PCI) += pci_type1.o
 endif
-obj-y  += pch-uclass.o
 obj-y  += pirq_routing.o
 obj-y  += relocate.o
 obj-y += physmem.o
diff --git a/drivers/Makefile b/drivers/Makefile
index 00da40b..6294048 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -51,6 +51,7 @@ obj-y += hwmon/
 obj-y += misc/
 obj-y += pcmcia/
 obj-y += dfu/
+obj-$(CONFIG_X86) += pch/
 obj-y += rtc/
 obj-y += sound/
 obj-y += timer/
diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile
new file mode 100644
index 000..d69a99c
--- /dev/null
+++ b/drivers/pch/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += pch-uclass.o
diff --git a/arch/x86/lib/pch-uclass.c b/drivers/pch/pch-uclass.c
similarity index 50%
rename from arch/x86/lib/pch-uclass.c
rename to drivers/pch/pch-uclass.c
index 20dfa81..4579ed1 100644
--- a/arch/x86/lib/pch-uclass.c
+++ b/drivers/pch/pch-uclass.c
@@ -7,10 +7,42 @@
 
 #include 
 #include 
+#include 
 #include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int pch_get_sbase(struct udevice *dev, ulong *sbasep)
+{
+   struct pch_ops *ops = pch_get_ops(dev);
+
+   *sbasep = 0;
+   if (!ops->get_sbase)
+   return -ENOSYS;
+
+   return ops->get_sbase(dev, sbasep);
+}
+
+enum pch_version pch_get_version(struct udevice *dev)
+{
+   struct pch_ops *ops = pch_get_ops(dev);
+
+   if (!ops->get_version)
+   return -ENOSYS;
+
+   return ops->get_version(dev);
+}
+
+int pch_set_spi_protect(struct udevice *dev, bool protect)
+{
+   struct pch_ops *ops = pch_get_ops(dev);
+
+   if (!ops->set_spi_protect)
+   return -ENOSYS;
+
+   return ops->set_spi_protect(dev, protect);
+}
+
 static int pch_uclass_post_bind(struct udevice *bus)
 {
/*
diff --git a/include/pch.h b/include/pch.h
new file mode 100644
index 000..ff26865
--- /dev/null
+++ b/include/pch.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __pch_h
+#define __pch_h
+
+enum pch_version {
+   PCHV_UNKNOWN,
+   PCHV_7,
+   PCHV_9,
+};
+
+/* Operations for the Platform Controller Hub */
+struct pch_ops {
+   /**
+* get_sbase() - get the address of SPI base
+*
+* @dev:PCH device to check
+* @sbasep: Returns address of SPI base if available, else 0
+* @return 0 if OK, -ve on error (e.g. there is no SPI base)
+*/
+   int (*get_sbase)(struct udevice *dev, ulong *sbasep);
+
+   /**
+* get_version() - get the PCH version
+*
+* @return version, or -ENOSYS if unknown
+*/
+   enum pch_version (*get_version)(struct udevice *dev);
+
+   /**
+* set_spi_protect() - set whether SPI flash is protected or not
+*
+* @dev:PCH device to adjust
+* @protect:true to protect, false to unprotect
+*
+* @return 0 on success, -ENOSYS if not implemented
+*/
+   int (*set_spi_protect)(struct udevice *dev, bool protect);
+};
+
+#define pch_get_ops(dev)((struct pch_ops *)(dev)->driver->ops)
+
+/**
+ * pch_get_sbase() - get the address of SPI base
+ *
+ * @dev:   PCH device to check
+ * @sbasep:Returns address of SPI base if available, else 0
+ * @return 0 if OK, -ve on error (e.g. there is no SPI base)
+ */
+int pch_get_sbase(struct udevice 

Re: [U-Boot] [PATCH 00/23] dm: tegra: Convert tegra20 and tegra124 video drivers to driver model

[Marcel Ziswiler]

Hi Simon

On Sat, 2016-01-16 at 10:14 -0700, Simon Glass wrote:



> > I wanted to give that patch set a shot but could not figure out
> > against
> > what to get it cleanly applied. Could you reveal its baseline or
> > better
> > yet a git branch ready for testing?
> 
> Yes, this plus the next series is at u-boot-dm/rkf-working. Sorry I
> didn't point that out.

OK, that looks much better now. However I noticed a few things:

Apalis T30 has Ethernet broken but that's the same on master. Good news
your u-boot-dm/eth-working branch actually makes it work againTM (;-p). 
So I assume your just about to post some fixes in that regard.

Colibri T20 is completely broken. Bisecting it showed a simple
configuration issue which I will report ASAP on resp. patch.
Unfortunately with that Colibri T20 still does not show anything on the
screen anymore but rather reports the following:

stdio_add_devices: Video device failed (ret=-22)

Are you familiar with what could be the issue there?

Colibri T20/T30 have Ethernet broken as well but that's the same on
master. Unfortunately I don't think u-boot-dm/eth-working does anything
on that front I guess. I will report this ASAP in a separate email.

Thanks Simon.




Cheers

Marcel
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Re: [U-Boot] [PATCH 21/23] tegra: Convert CONFIG_PWM_TEGRA to Kconfig

[Marcel Ziswiler]

On Thu, 2016-01-14 at 11:28 -0700, Simon Glass wrote:
> Move this option to Kconfig and clean up the header files. Adjust the
> only
> user (the LCD driver) to work with the new driver.
> 
> Signed-off-by: Simon Glass 
> ---
> 
>  configs/colibri_t20_defconfig | 8 +---
>  configs/harmony_defconfig | 1 +
>  configs/medcom-wide_defconfig | 1 +
>  configs/nyan-big_defconfig| 1 +
>  configs/paz00_defconfig   | 1 +
>  configs/seaboard_defconfig| 1 +
>  configs/tec_defconfig | 1 +
>  configs/ventana_defconfig | 1 +
>  drivers/pwm/Kconfig   | 8 
>  include/configs/colibri_t20.h | 1 -
>  include/configs/harmony.h | 1 -
>  include/configs/medcom-wide.h | 1 -
>  include/configs/nyan-big.h| 1 -
>  include/configs/paz00.h   | 1 -
>  include/configs/seaboard.h| 1 -
>  include/configs/tec.h | 1 -
>  include/configs/ventana.h | 1 -
>  17 files changed, 20 insertions(+), 11 deletions(-)
> 
> diff --git a/configs/colibri_t20_defconfig
> b/configs/colibri_t20_defconfig
> index 84e5bc5..49687cf 100644
> --- a/configs/colibri_t20_defconfig
> +++ b/configs/colibri_t20_defconfig
> @@ -2,18 +2,20 @@ CONFIG_ARM=y
>  CONFIG_TEGRA=y
>  CONFIG_SPL_DM=y
>  CONFIG_TEGRA20=y
> -CONFIG_TARGET_COLIBRI_T20=y
> -CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri"
> -CONFIG_SYS_PROMPT="Colibri T20 # "
> +CONFIG_TARGET_MEDCOM_WIDE=y
> +CONFIG_DEFAULT_DEVICE_TREE="tegra20-medcom-wide"
> +CONFIG_SYS_PROMPT="Tegra20 (Medcom-Wide) # "

Hm, I don't think you do want to change our Colibri T20 to become a
Medcom Wide (;-p). Leaving that part off makes it at least boot again.

>  # CONFIG_CMD_IMI is not set
>  # CONFIG_CMD_IMLS is not set
>  # CONFIG_CMD_FLASH is not set
>  # CONFIG_CMD_FPGA is not set
>  CONFIG_CMD_GPIO=y
> +# CONFIG_CMD_SETEXPR is not set
>  # CONFIG_CMD_NFS is not set
>  CONFIG_DM_PMIC=y
>  CONFIG_DM_REGULATOR=y
>  CONFIG_DM_PWM=y
> +CONFIG_PWM_TEGRA=y
>  CONFIG_SYS_NS16550=y
>  CONFIG_USB=y
>  CONFIG_DM_USB=y


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Re: [U-Boot] [GIT PULL] u-boot-mips/master

[Tom Rini]

On Sat, Jan 16, 2016 at 09:45:19PM +0100, Daniel Schwierzeck wrote:

> Hi Tom,
> 
> please pull the first bunch of MIPS updates.
> 
> There is a possible merge conflict in dts/Makefile due to my patch [1]
> in this PR and Thomas' patch [2] waiting in u-boot-fdt tree.
> 
> [1] http://patchwork.ozlabs.org/patch/566695/
> [2] http://patchwork.ozlabs.org/patch/563669/
> 
> 
> The following changes since commit 782acf7b52db6bec1a796773e3033b4afcd6c9e2:
> 
>   Merge git://git.denx.de/u-boot-rockchip (2016-01-15 08:11:15 -0500)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-mips.git master
> 
> for you to fetch changes up to 0e0efb40b874633360967f532eb1ed59ad02adbe:
> 
>   MIPS: implement bit manipulating I/O accessors (2016-01-16 21:06:46 +0100)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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[U-Boot] [PATCH 6/6] usb: dwc2: Add SPLIT INTERRUPT transaction support

[Stefan Brüns]

CSPLITs for INTERRUPT transactions have to be scheduled in each microframe
following the SSPLIT. INTERRUPT transfers are executed in the next even/
odd microframe depending on the HCCHAR_ODDFRM flag.

As there are no handshakes for INTERRUPT SSPLITs the SSPLIT may have
failed (transport error) without the error being detected by the host
driver. If the last CSPLIT is not received within 4 microframes after the
SSPLIT there was a transaction error and the complete transaction has
to be restarted.

Signed-off-by: Stefan Brüns 
---
 drivers/usb/host/dwc2.c | 28 +++-
 drivers/usb/host/dwc2.h |  1 +
 2 files changed, 24 insertions(+), 5 deletions(-)

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 413845c..291e4a5 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -776,7 +776,7 @@ static int dwc2_eptype[] = {
 
 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
  int *pid, int in, void *buffer, int num_packets,
- int xfer_len, int *actual_len)
+ int xfer_len, int *actual_len, int odd_frame)
 {
int ret = 0;
uint32_t sub;
@@ -804,8 +804,10 @@ static int transfer_chunk(struct dwc2_hc_regs *hc_regs, 
void *aligned_buffer,
 
/* Set host channel enable after all other setup is complete. */
clrsetbits_le32(_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
-   DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
+   DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
+   DWC2_HCCHAR_ODDFRM,
(1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
+   (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
DWC2_HCCHAR_CHEN);
 
ret = wait_for_chhltd(hc_regs, , pid);
@@ -831,6 +833,7 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device 
*dev,
 {
struct dwc2_core_regs *regs = priv->regs;
struct dwc2_hc_regs *hc_regs = >hc_regs[DWC2_HC_CHANNEL];
+   struct dwc2_host_regs *host_regs = >host_regs;
int devnum = usb_pipedevice(pipe);
int ep = usb_pipeendpoint(pipe);
int max = usb_maxpacket(dev, pipe);
@@ -843,6 +846,7 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device 
*dev,
uint32_t num_packets;
int stop_transfer = 0;
uint32_t max_xfer_len;
+   int ssplit_frame_num = 0;
 
debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
  in, len);
@@ -881,6 +885,7 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device 
*dev,
do {
int actual_len = 0;
uint32_t hcint;
+   int odd_frame = 0;
xfer_len = len - done;
 
if (xfer_len > max_xfer_len)
@@ -895,19 +900,32 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device 
*dev,
else if (do_split)
clrbits_le32(_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
 
+   if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
+   int uframe_num = readl(_regs->hfnum);
+   if (!(uframe_num & 0x1))
+   odd_frame = 1;
+   }
+
ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
 in, (char *)buffer + done, num_packets,
-xfer_len, _len);
+xfer_len, _len, odd_frame);
 
hcint = readl(_regs->hcint);
if (complete_split) {
stop_transfer = 0;
-   if (hcint & DWC2_HCINT_NYET)
+   if (hcint & DWC2_HCINT_NYET) {
ret = 0;
-   else
+   int frame_num = DWC2_HFNUM_MAX_FRNUM &
+   readl(_regs->hfnum);
+   if (((frame_num - ssplit_frame_num) &
+   DWC2_HFNUM_MAX_FRNUM) > 4)
+   ret = -EAGAIN;
+   } else
complete_split = 0;
} else if (do_split) {
if (hcint & DWC2_HCINT_ACK) {
+   ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
+  readl(_regs->hfnum);
ret = 0;
complete_split = 1;
}
diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h
index f69372e..594757b 100644
--- a/drivers/usb/host/dwc2.h
+++ b/drivers/usb/host/dwc2.h
@@ -500,6 +500,7 @@ struct dwc2_core_regs {
 #define DWC2_HFNUM_FRNUM_OFFSET0
 #define DWC2_HFNUM_FRREM_MASK  (0x << 16)
 #define DWC2_HFNUM_FRREM_OFFSET 

[U-Boot] [PATCHv4 1/7] mtd: Sort subsystem directories aplhabeticaly in Makefile

[Ladislav Michl]

Signed-off-by: Ladislav Michl 
Reviewed-by: Tom Rini 
---
 drivers/Makefile | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/Makefile b/drivers/Makefile
index 00da40b..1b9f8d6 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -18,14 +18,14 @@ obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
 obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
 obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
 obj-$(CONFIG_SPL_SERIAL_SUPPORT) += serial/
-obj-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += mtd/spi/
 obj-$(CONFIG_SPL_SPI_SUPPORT) += spi/
 obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/
 obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/
+obj-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += misc/
 obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd/
 obj-$(CONFIG_SPL_NAND_SUPPORT) += mtd/nand/
-obj-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += misc/
 obj-$(CONFIG_SPL_ONENAND_SUPPORT) += mtd/onenand/
+obj-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += mtd/spi/
 obj-$(CONFIG_SPL_DMA_SUPPORT) += dma/
 obj-$(CONFIG_SPL_ETH_SUPPORT) += net/
 obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/
-- 
2.1.4

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[U-Boot] [PATCH 4/6] usb: dwc2: add helper function for setting SPLIT HC registers

[Stefan Brüns]

The split register setting is used for both SSPLIT and CSPLIT transactions,
the bit for CSPLIT has to be set seperately.

Signed-off-by: Stefan Brüns 
---
 drivers/usb/host/dwc2.c | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 0e710d9..7fbbc4b 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -432,10 +432,23 @@ static void dwc_otg_hc_init(struct dwc2_core_regs *regs, 
uint8_t hc_num,
 */
writel(hcchar, _regs->hcchar);
 
-   /* Program the HCSPLIT register for SPLITs */
+   /* Program the HCSPLIT register, default to no SPLIT */
writel(0, _regs->hcsplt);
 }
 
+static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
+ uint8_t hub_devnum, uint8_t hub_port)
+{
+   uint32_t hcsplt = 0;
+
+   hcsplt = DWC2_HCSPLT_SPLTENA;
+   hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
+   hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
+
+   /* Program the HCSPLIT register for SPLITs */
+   writel(hcsplt, _regs->hcsplt);
+}
+
 /*
  * DWC2 to USB API interface
  */
-- 
2.1.4

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[U-Boot] [PATCH 5/6] usb: dwc2: Implement SPLIT transaction support

[Stefan Brüns]

In contrast to non-SPLIT transfers each transaction has to be submitted
as an individual chunk.
The transaction state machine proceeds from SSPLIT to CSPLIT if the ACK
flag is set. CSPLIT has to be repeated while NYET is set.

Signed-off-by: Stefan Brüns 
---
 drivers/usb/host/dwc2.c | 81 -
 1 file changed, 66 insertions(+), 15 deletions(-)

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 7fbbc4b..413845c 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -837,6 +837,8 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device 
*dev,
int eptype = dwc2_eptype[usb_pipetype(pipe)];
int done = 0;
int ret = 0;
+   int do_split = 0;
+   int complete_split = 0;
uint32_t xfer_len;
uint32_t num_packets;
int stop_transfer = 0;
@@ -859,8 +861,26 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device 
*dev,
dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
eptype, max);
 
+   /* Check if the target is a FS/LS device behind a HS hub */
+   if (dev->speed != USB_SPEED_HIGH) {
+   uint8_t hub_addr;
+   uint8_t hub_port;
+   uint32_t hprt0 = readl(>hprt0);
+   if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
+DWC2_HPRT0_PRTSPD_HIGH) {
+   usb_find_usb2_hub_address_port(dev, _addr,
+  _port);
+   dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
+
+   do_split = 1;
+   num_packets = 1;
+   max_xfer_len = max;
+   }
+   }
+
do {
int actual_len = 0;
+   uint32_t hcint;
xfer_len = len - done;
 
if (xfer_len > max_xfer_len)
@@ -870,10 +890,29 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device 
*dev,
else
num_packets = 1;
 
+   if (complete_split)
+   setbits_le32(_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
+   else if (do_split)
+   clrbits_le32(_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
+
ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
 in, (char *)buffer + done, num_packets,
 xfer_len, _len);
 
+   hcint = readl(_regs->hcint);
+   if (complete_split) {
+   stop_transfer = 0;
+   if (hcint & DWC2_HCINT_NYET)
+   ret = 0;
+   else
+   complete_split = 0;
+   } else if (do_split) {
+   if (hcint & DWC2_HCINT_ACK) {
+   ret = 0;
+   complete_split = 1;
+   }
+   }
+
if (ret)
break;
 
@@ -882,7 +921,11 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device 
*dev,
 
done += actual_len;
 
-   } while ((done < len) && !stop_transfer);
+   /* Transactions are done when when either all data is transferred or
+* there is a short transfer. In case of a SPLIT make sure the CSPLIT
+* is executed.
+*/
+   } while (((done < len) && !stop_transfer) || complete_split);
 
writel(0, _regs->hcintmsk);
writel(0x, _regs->hcint);
@@ -925,31 +968,39 @@ static int _submit_control_msg(struct dwc2_priv *priv, 
struct usb_device *dev,
 setup);
}
 
+   /* SETUP stage */
pid = DWC2_HC_PID_SETUP;
-   ret = chunk_msg(priv, dev, pipe, , 0, setup, 8);
+   do {
+   ret = chunk_msg(priv, dev, pipe, , 0, setup, 8);
+   } while (ret == -EAGAIN);
if (ret)
return ret;
 
+   /* DATA stage */
+   act_len = 0;
if (buffer) {
pid = DWC2_HC_PID_DATA1;
-   ret = chunk_msg(priv, dev, pipe, , usb_pipein(pipe), buffer,
-   len);
+   do {
+   ret = chunk_msg(priv, dev, pipe, , usb_pipein(pipe),
+   buffer, len);
+   act_len += dev->act_len;
+   buffer += dev->act_len;
+   len -= dev->act_len;
+   } while (ret == -EAGAIN);
if (ret)
return ret;
-   act_len = dev->act_len;
-   } /* End of DATA stage */
-   else
-   act_len = 0;
-
-   /* STATUS stage */
-   if ((len == 0) || usb_pipeout(pipe))
+   status_direction = usb_pipeout(pipe);
+   } else {
+   /* No-data CONTROL 

[U-Boot] [PATCH 2/6] usb: dwc2: Simplify wait_for_chhltd(), remove ignore_ack

[Stefan Brüns]

A transfer is completed if the XFERCOMP flag is set, irrespective of the
ACK flag. BULK OUT transfers to some HS devices complete without having
the ACK flag set, which signal the devices has responded with an NYET
to the transfer (PING protocol).
The new behaviour matches the Linux kernel minus any PING protocol.

Also see 5966defabdcc (usb: dwc2: fix bulk transfers)

Signed-off-by: Stefan Brüns 
---
 drivers/usb/host/dwc2.c | 40 +---
 1 file changed, 17 insertions(+), 23 deletions(-)

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index d317104..ad097cb 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -729,10 +729,8 @@ static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, 
struct usb_device *dev,
return stat;
 }
 
-int wait_for_chhltd(struct dwc2_core_regs *regs, uint32_t *sub, int *toggle,
-   bool ignore_ack)
+int wait_for_chhltd(struct dwc2_core_regs *regs, uint32_t *sub, int *toggle)
 {
-   uint32_t hcint_comp_hlt_ack = DWC2_HCINT_XFERCOMP | DWC2_HCINT_CHHLTD;
struct dwc2_hc_regs *hc_regs = >hc_regs[DWC2_HC_CHANNEL];
int ret;
uint32_t hcint, hctsiz;
@@ -742,25 +740,22 @@ int wait_for_chhltd(struct dwc2_core_regs *regs, uint32_t 
*sub, int *toggle,
return ret;
 
hcint = readl(_regs->hcint);
-   if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
-   return -EAGAIN;
-   if (ignore_ack)
-   hcint &= ~DWC2_HCINT_ACK;
-   else
-   hcint_comp_hlt_ack |= DWC2_HCINT_ACK;
-   if (hcint != hcint_comp_hlt_ack) {
-   debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
-   return -EINVAL;
-   }
-
hctsiz = readl(_regs->hctsiz);
*sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
DWC2_HCTSIZ_XFERSIZE_OFFSET;
*toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
 
-   debug("%s: sub=%u toggle=%d\n", __func__, *sub, *toggle);
+   debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
+ *toggle);
 
-   return 0;
+   if (hcint & DWC2_HCINT_XFERCOMP)
+   return 0;
+
+   if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
+   return -EAGAIN;
+
+   debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
+   return -EINVAL;
 }
 
 static int dwc2_eptype[] = {
@@ -771,8 +766,7 @@ static int dwc2_eptype[] = {
 };
 
 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
- unsigned long pipe, int *pid, int in, void *buffer, int len,
- bool ignore_ack)
+ unsigned long pipe, int *pid, int in, void *buffer, int len)
 {
struct dwc2_core_regs *regs = priv->regs;
struct dwc2_hc_regs *hc_regs = >hc_regs[DWC2_HC_CHANNEL];
@@ -841,7 +835,7 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device 
*dev,
(1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
DWC2_HCCHAR_CHEN);
 
-   ret = wait_for_chhltd(regs, , pid, ignore_ack);
+   ret = wait_for_chhltd(regs, , pid);
if (ret)
break;
 
@@ -883,7 +877,7 @@ int _submit_bulk_msg(struct dwc2_priv *priv, struct 
usb_device *dev,
}
 
return chunk_msg(priv, dev, pipe, >bulk_data_toggle[devnum][ep],
-usb_pipein(pipe), buffer, len, true);
+usb_pipein(pipe), buffer, len);
 }
 
 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
@@ -903,14 +897,14 @@ static int _submit_control_msg(struct dwc2_priv *priv, 
struct usb_device *dev,
}
 
pid = DWC2_HC_PID_SETUP;
-   ret = chunk_msg(priv, dev, pipe, , 0, setup, 8, true);
+   ret = chunk_msg(priv, dev, pipe, , 0, setup, 8);
if (ret)
return ret;
 
if (buffer) {
pid = DWC2_HC_PID_DATA1;
ret = chunk_msg(priv, dev, pipe, , usb_pipein(pipe), buffer,
-   len, false);
+   len);
if (ret)
return ret;
act_len = dev->act_len;
@@ -926,7 +920,7 @@ static int _submit_control_msg(struct dwc2_priv *priv, 
struct usb_device *dev,
 
pid = DWC2_HC_PID_DATA1;
ret = chunk_msg(priv, dev, pipe, , status_direction,
-   priv->status_buffer, 0, false);
+   priv->status_buffer, 0);
if (ret)
return ret;
 
-- 
2.1.4

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[U-Boot] [PATCH 1/6] usb: dwc2: Fix out-of-bounds access, fix chunk size

[Stefan Brüns]

Fix two errors in transfer len calculation, move loop invariant code out
of loop.

If xfer_len is equal to CONFIG_DWC2_MAX_TRANSFER_SIZE (or slightly
smaller), the xfer_len will be to large, e.g.:
  xfer_len = MAX_TRANSFER_SIZE = 65535
  max packet size = 512
=> num_packets = 128
=> IN xfer_len = 65536

For OUT transactions larger than (65536 - mps) bytes, the xfer_len
determination is quite awkward, it is only correct due to:
- max_packet_size for control/bulk/interrupt is required to be
  power-of-two.
- (CONFIG_DWC2_MAX_TRANSFER_SIZE + 1) % max-packet-size is zero
  for all allowed (2^3 ... 2^9) packet sizes

As the max xfer len is loop invariant, it can be moved out of the loop.

Signed-off-by: Stefan Brüns 
---
 drivers/usb/host/dwc2.c | 30 +++---
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 5ef6deb..d317104 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -786,34 +786,34 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device 
*dev,
uint32_t xfer_len;
uint32_t num_packets;
int stop_transfer = 0;
+   uint32_t max_xfer_len;
 
debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
  in, len);
 
+   max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
+   if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
+   max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
+   if (max_xfer_len > DWC2_DATA_BUF_SIZE)
+   max_xfer_len = DWC2_DATA_BUF_SIZE;
+
+   /* Make sure that max_xfer_len is a multiple of max packet size. */
+   num_packets = max_xfer_len / max;
+   max_xfer_len = num_packets * max;
+
do {
/* Initialize channel */
dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
eptype, max);
 
xfer_len = len - done;
-   if (xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
-   xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1;
-   if (xfer_len > DWC2_DATA_BUF_SIZE)
-   xfer_len = DWC2_DATA_BUF_SIZE - max + 1;
 
-   /* Make sure that xfer_len is a multiple of max packet size. */
-   if (xfer_len > 0) {
+   if (xfer_len > max_xfer_len)
+   xfer_len = max_xfer_len;
+   else if (xfer_len > max)
num_packets = (xfer_len + max - 1) / max;
-   if (num_packets > CONFIG_DWC2_MAX_PACKET_COUNT) {
-   num_packets = CONFIG_DWC2_MAX_PACKET_COUNT;
-   xfer_len = num_packets * max;
-   }
-   } else {
+   else
num_packets = 1;
-   }
-
-   if (in)
-   xfer_len = num_packets * max;
 
debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
  *pid, xfer_len, num_packets);
-- 
2.1.4

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[U-Boot] [PATCH 0/4] ARM: uniphier: refactor and fix UniPhier outer cache

[Masahiro Yamada]

Masahiro Yamada (4):
  ARM: uniphier: refactor outer cache operation slightly
  ARM: uniphier: factor out outer cache sync as a helper function
  ARM: uniphier: fix range invalidate for outer cache
  ARM: uniphier: set active ways to really enable outer cache

 arch/arm/mach-uniphier/cache_uniphier.c | 43 -
 1 file changed, 37 insertions(+), 6 deletions(-)

-- 
1.9.1

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[U-Boot] [PATCH 3/4] ARM: uniphier: fix range invalidate for outer cache

[Masahiro Yamada]

If invalidate operation is invoked against a cache-unaliged region,
the both ends of the region should be flushed, not invalidated.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/cache_uniphier.c | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm/mach-uniphier/cache_uniphier.c 
b/arch/arm/mach-uniphier/cache_uniphier.c
index 6c77316..8435a33 100644
--- a/arch/arm/mach-uniphier/cache_uniphier.c
+++ b/arch/arm/mach-uniphier/cache_uniphier.c
@@ -105,6 +105,29 @@ void v7_outer_cache_flush_range(u32 start, u32 end)
 
 void v7_outer_cache_inval_range(u32 start, u32 end)
 {
+   if (start & (SSC_LINE_SIZE - 1)) {
+   start &= ~(SSC_LINE_SIZE - 1);
+   __uniphier_cache_maint_range(start, SSC_LINE_SIZE,
+SSCOQM_CM_WB_INV);
+   start += SSC_LINE_SIZE;
+   }
+
+   if (start >= end) {
+   uniphier_cache_sync();
+   return;
+   }
+
+   if (end & (SSC_LINE_SIZE - 1)) {
+   end &= ~(SSC_LINE_SIZE - 1);
+   __uniphier_cache_maint_range(end, SSC_LINE_SIZE,
+SSCOQM_CM_WB_INV);
+   }
+
+   if (start >= end) {
+   uniphier_cache_sync();
+   return;
+   }
+
uniphier_cache_maint_range(start, end, SSCOQM_CM_INV);
 }
 
-- 
1.9.1

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[U-Boot] [PATCH 1/4] ARM: uniphier: refactor outer cache operation slightly

[Masahiro Yamada]

Improve readability without changing the behavior.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/cache_uniphier.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-uniphier/cache_uniphier.c 
b/arch/arm/mach-uniphier/cache_uniphier.c
index b4ca8b6..4a79966 100644
--- a/arch/arm/mach-uniphier/cache_uniphier.c
+++ b/arch/arm/mach-uniphier/cache_uniphier.c
@@ -67,7 +67,9 @@ static void uniphier_cache_maint_range(u32 start, u32 end, 
u32 operation)
 */
start = start & ~(SSC_LINE_SIZE - 1);
 
-   if (start == 0 && end >= (u32)(-SSC_LINE_SIZE)) {
+   size = end - start;
+
+   if (unlikely(size >= (u32)(-SSC_LINE_SIZE))) {
/* this means cache operation for all range */
uniphier_cache_maint_all(operation);
return;
@@ -77,7 +79,7 @@ static void uniphier_cache_maint_range(u32 start, u32 end, 
u32 operation)
 * If end address is not aligned to cache-line,
 * do cache operation for the last cache-line
 */
-   size = (end - start + SSC_LINE_SIZE - 1) & ~(SSC_LINE_SIZE - 1);
+   size = ALIGN(size, SSC_LINE_SIZE);
 
while (size) {
u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ?
-- 
1.9.1

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[U-Boot] [PATCH 2/4] ARM: uniphier: factor out outer cache sync as a helper function

[Masahiro Yamada]

Avoid repeating the same code.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/cache_uniphier.c | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-uniphier/cache_uniphier.c 
b/arch/arm/mach-uniphier/cache_uniphier.c
index 4a79966..6c77316 100644
--- a/arch/arm/mach-uniphier/cache_uniphier.c
+++ b/arch/arm/mach-uniphier/cache_uniphier.c
@@ -11,6 +11,12 @@
 #include "ssc-regs.h"
 
 #ifdef CONFIG_UNIPHIER_L2CACHE_ON
+static void uniphier_cache_sync(void)
+{
+   writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
+   readl(SSCOPE); /* need a read back to confirm */
+}
+
 static void uniphier_cache_maint_all(u32 operation)
 {
/* try until the command is successfully set */
@@ -25,8 +31,7 @@ static void uniphier_cache_maint_all(u32 operation)
/* clear the complete notification flag */
writel(SSCOLPQS_EF, SSCOLPQS);
 
-   writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
-   readl(SSCOPE); /* need a read back to confirm */
+   uniphier_cache_sync();
 }
 
 void v7_outer_cache_flush_all(void)
@@ -90,8 +95,7 @@ static void uniphier_cache_maint_range(u32 start, u32 end, 
u32 operation)
size -= chunk_size;
}
 
-   writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
-   readl(SSCOPE); /* need a read back to confirm */
+   uniphier_cache_sync();
 }
 
 void v7_outer_cache_flush_range(u32 start, u32 end)
-- 
1.9.1

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[U-Boot] [PATCH 4/4] ARM: uniphier: set active ways to really enable outer cache

[Masahiro Yamada]

Each way must be unlocked to make it effective.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/cache_uniphier.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-uniphier/cache_uniphier.c 
b/arch/arm/mach-uniphier/cache_uniphier.c
index 8435a33..4398114 100644
--- a/arch/arm/mach-uniphier/cache_uniphier.c
+++ b/arch/arm/mach-uniphier/cache_uniphier.c
@@ -134,6 +134,8 @@ void v7_outer_cache_inval_range(u32 start, u32 end)
 void v7_outer_cache_enable(void)
 {
u32 tmp;
+
+   writel(U32_MAX, SSCLPDAWCR);/* activate all ways */
tmp = readl(SSCC);
tmp |= SSCC_ON;
writel(tmp, SSCC);
-- 
1.9.1

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Re: [U-Boot] x86: Bay Trail support with W83627DHG

[Stefan Roese]

Hi Bin,

On 16.01.2016 15:08, Bin Meng wrote:

On Fri, Jan 15, 2016 at 10:37 PM, Stefan Roese  wrote:

Hi Simon, Hi Bin!

I'm currently busy with porting U-Boot to a Bay Trail board.
Equipped with an Intel Atom E3845 and additionally the
Nuvoton / Winbond W83627DHG Super IO chip.

My staring point for this port is the Minnowboard MAX, which
works very well btw. I've used the same binaries as described
in the README.x86 as on the MinnowMAX for this new Bay Trail
board. But am not able yet to see any output on the DEBUG_UART.

Bin, you already mentioned in a previous mail, that I need to
enable the legacy UART in the Super IO chip for this. I've
started adding a small driver for this, similar to the one
you've introduced for the SMSC:


Ah, looks I delivered inaccurate information before! I just remember
BayTrail SoC integrates a legacy UART at I/O 0x3f8 and it is enabled
by FSP by default. If you use a debug version of FSP (only gold4
release provides a debug version FSP), you will se lots of useful
debug information printed on the serial port (the one connected to the
SoC legacy UART). But, why does your board have an additional Nuvoton
/ Winbond W83627DHG Super IO chip? I guess it's for other legacy
peripherals like 8042 KBC, etc? We need figure out the serial port you
are trying to enable is connected to which chip. If it is connected
directly to BayTrail SoC, then you don't need program this W83627DHG.


It is connected to the Winbond UART. So we need to enable and use it.
But how can I disable the BayTrail internal legacy UART? So that the
Winbond one is really used?



--<
#define WINBOND_ENTRY_KEY   0x87
#define WINBOND_EXIT_KEY0xAA

/* Enable configuration: pass entry key '0x87' into index port dev. */
static void pnp_enter_conf_state(u16 dev)
{
 u16 port = dev >> 8;

 outb(WINBOND_ENTRY_KEY, port);
 outb(WINBOND_ENTRY_KEY, port);
}

/* Disable configuration: pass exit key '0xAA' into index port dev. */
static void pnp_exit_conf_state(u16 dev)
{
 u16 port = dev >> 8;

 outb(WINBOND_EXIT_KEY, port);
}

/* Bring up early serial debugging output before the RAM is initialized. */
void winbond_enable_serial(uint dev, uint iobase, uint irq)
{
 pnp_enter_conf_state(dev);
 pnp_set_logical_device(dev);
 pnp_set_enable(dev, 0);
 pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
 pnp_set_irq(dev, PNP_IDX_IRQ0, irq);
 pnp_set_enable(dev, 1);
 pnp_exit_conf_state(dev);
}
--<

This is called via:
--<
/* I/O address of Winbond Super IO chip */
#define WINBOND_IO_PORT 0x2e



If the serial port is connected to winbond, we need make sure this I/O
port 0x2e is correct. Normally the chipset will have several optional
addresses, and which one is used is determined by some strap pins.


Let me double-check this.


/* Logical device number */
#define W83627DHG_SP1   2   /* Com1 */

 winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1),
   UART0_BASE, UART0_IRQ);
--<

As you may notice, this is ported from coreboot. But still, this
is not enough to get some output on the UART.

Debugging (without JTAG debugger and without DEBUG_UART but with
POST output) shows, that the board hangs somewhere in the FSP code.
When called via fsp_init(). POST shows 0x2A in this case. And
FSP does not return to fsp_continue() at all.



0x2A seems to be a U-Boot postcode.


Do you have any hints what could be missing for the DEBUG
UART to work on this board? Or what might cause the board
to hang in the FSP code? Or what the meaning of the FSP 0x2A
POST code is?



If the fsp_init() never returns, the most suspectable one is DDR
initialization failure. If it's a memory-down configuration, you may
need check the DDR chipset datasheet and fill in correct values in the
device tree file.


It looks like those 0x2A comes from the FSP to signal some DDR
issues. I've seen 0x2B as well. And have in the meantime been
able to boot further into U-Boot with some tuned settings.

But still, without any serial output this is hard to debug.

Thanks,
Stefan

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[U-Boot] [PATCH] ARM: uniphier: move UMC register macros to umc-regs.h

[Masahiro Yamada]

The umc-proxstream2.c defiens the same macros as in umc-regs.h.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/dram/umc-proxstream2.c | 49 +--
 arch/arm/mach-uniphier/dram/umc-regs.h| 26 ++
 2 files changed, 27 insertions(+), 48 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/umc-proxstream2.c 
b/arch/arm/mach-uniphier/dram/umc-proxstream2.c
index 63a84e6..bb7acde 100644
--- a/arch/arm/mach-uniphier/dram/umc-proxstream2.c
+++ b/arch/arm/mach-uniphier/dram/umc-proxstream2.c
@@ -16,54 +16,7 @@
 #include "../init.h"
 #include "../soc-info.h"
 #include "ddrmphy-regs.h"
-
-/* UM registers */
-#define UMC_MBUS0  0x00080004
-#define UMC_MBUS1  0x00081004
-#define UMC_MBUS2  0x00082004
-#define UMC_MBUS3  0x00083004
-
-/* UD registers */
-#define UMC_BITPERPIXELMODE_D0 0x010
-#define UMC_PAIR1DOFF_D0   0x054
-
-/* DC registers */
-#define UMC_INITSET0x014
-#define UMC_INITSTAT   0x018
-#define UMC_CMDCTLA0x000
-#define UMC_CMDCTLB0x004
-#define UMC_SPCCTLA0x030
-#define UMC_SPCCTLB0x034
-#define UMC_SPCSETB0x03c
-#define   UMC_SPCSETB_AREFMD_MASK  (0x3)   /* Auto Refresh Mode */
-#define   UMC_SPCSETB_AREFMD_ARB   (0x0)   /* control by arbitor */
-#define   UMC_SPCSETB_AREFMD_CONT  (0x1)   /* control by DRAMCONT */
-#define   UMC_SPCSETB_AREFMD_REG   (0x2)   /* control by register */
-#define UMC_ACSSETA0x060
-#define UMC_FLOWCTLA   0x400
-#define UMC_FLOWCTLB   0x404
-#define UMC_FLOWCTLC   0x408
-#define UMC_FLOWCTLG   0x508
-#define UMC_FLOWCTLOB0 0x520
-#define UMC_FLOWCTLOB1 0x524
-#define UMC_RDATACTL_D00x600
-#define   UMC_RDATACTL_RADLTY_SHIFT4
-#define   UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT))
-#define   UMC_RDATACTL_RAD2LTY_SHIFT   8
-#define   UMC_RDATACTL_RAD2LTY_MASK(0xf << (UMC_RDATACTL_RAD2LTY_SHIFT))
-#define UMC_WDATACTL_D00x604
-#define UMC_RDATACTL_D10x608
-#define UMC_WDATACTL_D10x60c
-#define UMC_DATASET0x610
-#define UMC_RESPCTL0x624
-#define UMC_DCCGCTL0x720
-#define UMC_ERRMASKA   0x958
-#define UMC_ERRMASKB   0x95c
-#define UMC_BSICMAPSET 0x988
-#define UMC_DIOCTLA0xc00
-#define   UMC_DIOCTLA_CTL_NRST BIT(8)  /* ctl_rst_n */
-#define   UMC_DIOCTLA_CFG_NRST BIT(0)  /* cfg_rst_n */
-#define UMC_DFICUPDCTLA0xc20
+#include "umc-regs.h"
 
 enum dram_freq {
FREQ_1866M,
diff --git a/arch/arm/mach-uniphier/dram/umc-regs.h 
b/arch/arm/mach-uniphier/dram/umc-regs.h
index 6159281..a6957a4 100644
--- a/arch/arm/mach-uniphier/dram/umc-regs.h
+++ b/arch/arm/mach-uniphier/dram/umc-regs.h
@@ -69,6 +69,10 @@
 #define UMC_SPCCTLB0x0034
 #define UMC_SPCSETA0x0038
 #define UMC_SPCSETB0x003C
+#define   UMC_SPCSETB_AREFMD_MASK  (0x3)   /* Auto Refresh Mode */
+#define   UMC_SPCSETB_AREFMD_ARB   (0x0)   /* control by arbitor */
+#define   UMC_SPCSETB_AREFMD_CONT  (0x1)   /* control by DRAMCONT */
+#define   UMC_SPCSETB_AREFMD_REG   (0x2)   /* control by register */
 #define UMC_SPCSETC0x0040
 #define UMC_SPCSETD0x0044
 #define UMC_SPCSTATA   0x0050
@@ -79,17 +83,39 @@
 #define UMC_FLOWCTLB   0x0404
 #define UMC_FLOWCTLC   0x0408
 #define UMC_FLOWCTLG   0x0508
+#define UMC_FLOWCTLOB0 0x0520
+#define UMC_FLOWCTLOB1 0x0524
 #define UMC_RDATACTL_D00x0600
+#define   UMC_RDATACTL_RADLTY_SHIFT4
+#define   UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT))
+#define   UMC_RDATACTL_RAD2LTY_SHIFT   8
+#define   UMC_RDATACTL_RAD2LTY_MASK(0xf << (UMC_RDATACTL_RAD2LTY_SHIFT))
 #define UMC_WDATACTL_D00x0604
 #define UMC_RDATACTL_D10x0608
 #define UMC_WDATACTL_D10x060C
 #define UMC_DATASET0x0610
+#define UMC_RESPCTL0x0624
 #define UMC_DCCGCTL0x0720
 #define UMC_DICGCTLA   0x0724
 #define UMC_DICGCTLB   0x0728
+#define UMC_ERRMASKA   0x0958
+#define UMC_ERRMASKB   0x095c
+#define UMC_BSICMAPSET 0x0988
 #define UMC_DIOCTLA0x0C00
+#define   UMC_DIOCTLA_CTL_NRST BIT(8)  /* ctl_rst_n */
+#define   UMC_DIOCTLA_CFG_NRST BIT(0)  /* cfg_rst_n */
 #define UMC_DFICUPDCTLA0x0C20
 
+/* UM registers */
+#define UMC_MBUS0  0x00080004
+#define UMC_MBUS1  0x00081004
+#define UMC_MBUS2  0x00082004
+#define UMC_MBUS3  0x00083004
+
+/* UD registers */
+#define 

[U-Boot] [PATCH v7 0/7] add support for atheros ath79 based SOCs

[Wills Wang]

These series of patch add support for atheros ath79 based SOCs in u-boot,
at the present moment it's just available for ar933x and qca953x chip.

This patch serises is based on mips_io_v4 branch on u-boot-mips repository 
[1] and tested on ar933x and qca953x board.

[1] 
http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads/mips_io_v4

Changes in v7:
- Use setbits_32
- Fix include path for SoC specific headers
- Use CKSEGxADDR instead of KSEGxADDR for ar933x
- Use CKSEGxADDR instead of KSEGxADDR for qca953x
- remove map_physmem for debug port
- Define spi_cs_activate/spi_cs_deactivate
- Rename MHZ to ATH79_SPI_MHZ
- Use clrsetbits_32
- Use KSEG1 address for debug port in ap121
- Use KSEG1 address for debug port in ap143

Changes in v6:
- Move ar933x as separate patch
- Add get_bootstrap in reset.c
- Use map_physmem instead of KSEG1ADDR
- Add arch_cpu_init for detect SOC type for early
- Remove board.c
- Define magic value in ddr.c
- Remove wait loop in putc and getc
- Use map_physmem instead of KSEG1ADDR
- Add rrw_delay in ath79_spi_priv for more accurate timing
- Remove ath79_spi_delay
- Calculate delay in ath79_spi_set_speed
- Convert SZ_XXX into hex in ap121.h
- Remove useless CONFIG_SYS_INIT_SP_OFFSET in ap121.h
- Add board_early_init_f for DDR and pin initialization
- Select UART and SPI in ap121_defconfig

Changes in v5:
- Add independent Kconfig
- Use SRAM for initial stack
- Move DDR initialization into board_early_init_f
- Convert DDR tap tunning code to C
- Save SOC's version into arch_global_data
- remove ar933x_serial_platdata
- Import document "qca,ar9330-uart.txt" from kernel
- Add support for debug UART
- remove ar933x_spi_platdata
- Import document "spi-ath79.txt" from kernel
- Add delay for bitbang operation
- Move CONFIG_SYS_TEXT_BASE into ap121.h, and remove config.mk
- Remove useless README file
- Remove useless checkboard function

Changes in v4:
- Use global_data to save CPU/DDR/AHB clock
- Use arch_global_data to save SOC's type, revison and id
- Auto calculate baudrate for serial driver
- Move pinctrl code in serial driver into arch/mips/mach-ath79
- Use get_serial_clock to serial clock source
- Use get_bus_freq instead of hardcode in SPI driver

Changes in v3:
- Move SoC specific header files into arch/mips/mach-ath79/include/mach
- Optimize assembly code
- Same code style convertion
- Convert serial driver to driver model
- Convert spi driver to driver model
- Add support for device tree

Changes in v2:
- Move all SoC specific header files into arch/mips/include/asm/arch-ath79
- Check SOC type and extract common code into arch/mips/mach-ath79
- Move serial driver code into drivers/serial
- Add a compatible spi driver
- Add a reference board implemention

Wills Wang (7):
  mips: add base support for QCA/Atheros ath79 SOCs
  mips: ath79: add support for AR933x SOCs
  mips: ath79: add support for QCA953x SOCs
  mips: ath79: add serial driver for ar933x SOC
  mips: ath79: add spi driver
  mips: ath79: add AP121 reference board
  mips: ath79: add AP143 reference board

 arch/mips/Kconfig  |6 +
 arch/mips/Makefile |1 +
 arch/mips/dts/Makefile |3 +-
 arch/mips/dts/ap121.dts|   43 +
 arch/mips/dts/ap143.dts|   43 +
 arch/mips/dts/ar933x.dtsi  |   70 ++
 arch/mips/dts/qca953x.dtsi |   72 ++
 arch/mips/include/asm/global_data.h|6 +
 arch/mips/mach-ath79/Kconfig   |   46 +
 arch/mips/mach-ath79/Makefile  |   10 +
 arch/mips/mach-ath79/ar933x/Makefile   |7 +
 arch/mips/mach-ath79/ar933x/clk.c  |   89 ++
 arch/mips/mach-ath79/ar933x/ddr.c  |  316 ++
 arch/mips/mach-ath79/ar933x/lowlevel_init.S|  279 +
 arch/mips/mach-ath79/cpu.c |  203 
 arch/mips/mach-ath79/dram.c|   16 +
 arch/mips/mach-ath79/include/mach/ar71xx_regs.h| 1187 
 arch/mips/mach-ath79/include/mach/ath79.h  |  143 +++
 arch/mips/mach-ath79/include/mach/ddr.h|   13 +
 arch/mips/mach-ath79/include/mach/reset.h  |   14 +
 arch/mips/mach-ath79/qca953x/Makefile  |7 +
 arch/mips/mach-ath79/qca953x/clk.c |  111 ++
 arch/mips/mach-ath79/qca953x/ddr.c |  462 
 arch/mips/mach-ath79/qca953x/lowlevel_init.S   |  185 +++
 arch/mips/mach-ath79/reset.c   |   71 ++
 board/ath79/ap121/Kconfig  |9 +
 board/ath79/ap121/MAINTAINERS  |6 +
 board/ath79/ap121/Makefile |5 +
 board/ath79/ap121/ap121.c  |   47 +
 board/ath79/ap143/Kconfig  |9 +
 board/ath79/ap143/MAINTAINERS  |6 +