[U-Boot] [PATCH] armv8/ls2080ardb: Update DDR timing to support more UDIMMs

[Shengzhou Liu]

Optimize DDR timing for good margins to support new Transcend
and Apacer DDR4 UDIMM besides current Micron UDIMM.

Verified 1866MT/s and 2133MT/s with following UDIMM on LS2080ARDB.
 - Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z
 - Apacer UDIMM: 78.C1GM4.AF10B
 - Transcend UDIMM: TS1GLH72V1H

Signed-off-by: Shengzhou Liu 
---
 board/freescale/ls2080ardb/ddr.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/freescale/ls2080ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h
index bda9d4a..7274778 100644
--- a/board/freescale/ls2080ardb/ddr.h
+++ b/board/freescale/ls2080ardb/ddr.h
@@ -30,8 +30,8 @@ static const struct board_specific_parameters udimm0[] = {
 */
{2,  1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{2,  1666, 0, 4, 8, 0x08090B0D, 0x0E10100C,},
-   {2,  1900, 0, 4, 8, 0x090A0C0E, 0x1012120D,},
-   {2,  2300, 0, 4, 9, 0x0A0B0C10, 0x1114140E,},
+   {2,  1900, 0, 6,   0xA, 0x0B0C0E11, 0x1214140F,},
+   {2,  2300, 0, 6,   0xB, 0x0C0D0F12, 0x14161610,},
{}
 };
 
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH 03/11] pxa_lcd: invert colors for Zipit Z2 to get white on black palette

[Marek Vasut]

On 03/21/2016 03:10 AM, Vasily Khoruzhick wrote:
> On Sun, Mar 20, 2016 at 6:48 PM, Marek Vasut  wrote:
>> On 03/21/2016 02:37 AM, Vasily Khoruzhick wrote:
>>> Signed-off-by: Vasily Khoruzhick 
>>
>> What happens if you display picture ? Will the colors be complete mess ?
> 
> Yes, inverted. Can be fixed by inverting colors in BMP. I didn't find
> another way to get white on black
> console in u-boot.

CONFIG_SYS_WHITE_ON_BLACK might help.

>>> ---
>>>  drivers/video/pxa_lcd.c | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c
>>> index 1809fc6..ba4f897 100644
>>> --- a/drivers/video/pxa_lcd.c
>>> +++ b/drivers/video/pxa_lcd.c
>>> @@ -166,7 +166,7 @@ vidinfo_t panel_info = {
>>>  #ifdef CONFIG_LMS283GF05
>>>
>>>  # define LCD_BPP LCD_COLOR8
>>> -/*# define LCD_INVERT_COLORS*/
>>> +# define LCD_INVERT_COLORS
>>>
>>>  /* you have to set lccr0 and lccr3 (including pcd) */
>>>  # define REG_LCCR0   0x043008f8
>>>
>>
>>
>> --
>> Best regards,
>> Marek Vasut


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Re: [U-Boot] [PATCH 03/11] pxa_lcd: invert colors for Zipit Z2 to get white on black palette

[Vasily Khoruzhick]

On Sun, Mar 20, 2016 at 6:48 PM, Marek Vasut  wrote:
> On 03/21/2016 02:37 AM, Vasily Khoruzhick wrote:
>> Signed-off-by: Vasily Khoruzhick 
>
> What happens if you display picture ? Will the colors be complete mess ?

Yes, inverted. Can be fixed by inverting colors in BMP. I didn't find
another way to get white on black
console in u-boot.

>> ---
>>  drivers/video/pxa_lcd.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c
>> index 1809fc6..ba4f897 100644
>> --- a/drivers/video/pxa_lcd.c
>> +++ b/drivers/video/pxa_lcd.c
>> @@ -166,7 +166,7 @@ vidinfo_t panel_info = {
>>  #ifdef CONFIG_LMS283GF05
>>
>>  # define LCD_BPP LCD_COLOR8
>> -/*# define LCD_INVERT_COLORS*/
>> +# define LCD_INVERT_COLORS
>>
>>  /* you have to set lccr0 and lccr3 (including pcd) */
>>  # define REG_LCCR0   0x043008f8
>>
>
>
> --
> Best regards,
> Marek Vasut
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Re: [U-Boot] [RFC V2 PATCH 0/3] Add cache for block devices

[Marek Vasut]

On 03/21/2016 02:45 AM, Eric Nelson wrote:
> Here's a more full-featured implementation of a cache for block devices
> that uses a small linked list of cache blocks.

Why do you use linked list ? You have four entries, you can as well use
fixed array. Maybe you should implement an adaptive cache would would
use the unpopulated malloc area and hash the sector number(s) into that
area ?

> Experimentation loading a 4.5 MiB kernel from the root directory of 
> a FAT filesystem shows that a single cache entry of a single block
> is the only 

only ... what ? This is where things started to be interesting, but you
leave us hanging :)

> Loading the same from the /boot directory of an ext4 filesystem
> shows a benefit with 4 cache entries, though the single biggest
> benefit is also with the first cache entry:
> 
> => for n in 0 1 2 4 8 ; do 
>>blkc 1 $n ; blkc c ; blkc i ; 
>>load mmc 0:2 10008000 /boot/zImage ; 
>> done
> changed to max of 0 entries of 1 blocks each
> 4955304 bytes read in 503 ms (9.4 MiB/s)
> changed to max of 1 entries of 1 blocks each
> 4955304 bytes read in 284 ms (16.6 MiB/s)
> changed to max of 2 entries of 1 blocks each
> 4955304 bytes read in 284 ms (16.6 MiB/s)
> changed to max of 4 entries of 1 blocks each
> 4955304 bytes read in 255 ms (18.5 MiB/s)
> changed to max of 8 entries of 1 blocks each
> 4955304 bytes read in 255 ms (18.5 MiB/s)
> 
> As mentioned earlier in this thread, the modification to the mmc
> layer should probably be simpler and easier to apply to other
> block subsystems.
> 
> Eric Nelson (3):
>   drivers: block: add block device cache
>   block: add Kconfig options for BLOCK_CACHE, CMD_BLOCK_CACHE
>   mmc: add support for block device cache
> 
>  drivers/block/Kconfig   |  19 
>  drivers/block/Makefile  |   1 +
>  drivers/block/cache_block.c | 240 
> 
>  drivers/mmc/mmc.c   |  10 +-
>  drivers/mmc/mmc_write.c |   7 ++
>  include/part.h  |  69 +
>  6 files changed, 345 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/block/cache_block.c
> 


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Re: [U-Boot] [PATCH 10/11] zipitz2: enable caches

[Marek Vasut]

On 03/21/2016 02:37 AM, Vasily Khoruzhick wrote:
> It speeds up loading kernel from SD or USB a lot.
> 
> Signed-off-by: Vasily Khoruzhick 
> ---

Acked-by: Marek Vasut 

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Re: [U-Boot] [PATCH 03/11] pxa_lcd: invert colors for Zipit Z2 to get white on black palette

[Marek Vasut]

On 03/21/2016 02:37 AM, Vasily Khoruzhick wrote:
> Signed-off-by: Vasily Khoruzhick 

What happens if you display picture ? Will the colors be complete mess ?

> ---
>  drivers/video/pxa_lcd.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c
> index 1809fc6..ba4f897 100644
> --- a/drivers/video/pxa_lcd.c
> +++ b/drivers/video/pxa_lcd.c
> @@ -166,7 +166,7 @@ vidinfo_t panel_info = {
>  #ifdef CONFIG_LMS283GF05
>  
>  # define LCD_BPP LCD_COLOR8
> -/*# define LCD_INVERT_COLORS*/
> +# define LCD_INVERT_COLORS
>  
>  /* you have to set lccr0 and lccr3 (including pcd) */
>  # define REG_LCCR0   0x043008f8
> 


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Re: [U-Boot] [PATCH 05/11] pxa-common: pxa27x has 3 OHCI ports

[Marek Vasut]

On 03/21/2016 02:37 AM, Vasily Khoruzhick wrote:
> 3rd port can be used as a device or host.
> 
> Signed-off-by: Vasily Khoruzhick 

Acked-by: Marek Vasut 

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Re: [U-Boot] [PATCH 04/11] zipitz2: enable libfdt

[Marek Vasut]

On 03/21/2016 02:37 AM, Vasily Khoruzhick wrote:
> zipitz2 supports DT boot since linux-4.4 (not mainlined yet)
> 
> Signed-off-by: Vasily Khoruzhick 
> ---
>  include/configs/zipitz2.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
> index 169eaf3..f69b52e 100644
> --- a/include/configs/zipitz2.h
> +++ b/include/configs/zipitz2.h
> @@ -47,6 +47,7 @@
>  #define  CONFIG_SETUP_MEMORY_TAGS
>  #define  CONFIG_SYS_TEXT_BASE0x0
>  #define  CONFIG_LZMA /* LZMA compression support */
> +#define  CONFIG_OF_LIBFDT

Also enable CONFIG_FIT and fold this into patch 01 .

>  /*
>   * Serial Console Configuration
> 


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Re: [U-Boot] [PATCH 06/11] zipitz2: enable USB host support

[Marek Vasut]

On 03/21/2016 02:37 AM, Vasily Khoruzhick wrote:

Commit message is missing, NAK

> Signed-off-by: Vasily Khoruzhick 
> ---
>  board/zipitz2/zipitz2.c   | 21 +
>  include/configs/zipitz2.h |  1 +
>  2 files changed, 22 insertions(+)
> 
> diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c
> index 8fa1261..aefbeee 100644
> --- a/board/zipitz2/zipitz2.c
> +++ b/board/zipitz2/zipitz2.c
> @@ -15,6 +15,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -52,6 +53,26 @@ int dram_init(void)
>   return 0;
>  }
>  
> +#ifdef   CONFIG_CMD_USB
> +int board_usb_init(int index, enum usb_init_type init)
> +{
> + /* enable port 2 */
> + writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
> + UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
> +
> + return 0;
> +}
> +
> +int board_usb_cleanup(int index, enum usb_init_type init)
> +{
> + return 0;
> +}
> +
> +void usb_board_stop(void)
> +{

Please stop the USB here, otherwise it can corrupt the memory when Linux
boots.

> +}
> +#endif
> +
>  void dram_init_banksize(void)
>  {
>   gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
> index f69b52e..52a36b7 100644
> --- a/include/configs/zipitz2.h
> +++ b/include/configs/zipitz2.h
> @@ -64,6 +64,7 @@
>  #define  CONFIG_CMD_ENV
>  #define  CONFIG_CMD_MMC
>  #define  CONFIG_CMD_SPI
> +#define  CONFIG_CMD_USB
>  
>  /*
>   * MMC Card Configuration
> 


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Re: [U-Boot] [PATCH 11/11] cfi_flash: return device into read array mode after reading status

[Marek Vasut]

On 03/21/2016 02:37 AM, Vasily Khoruzhick wrote:
> Otherwise flash remains in read status mode and it's not possible
> to access data on flash.
> 
> Signed-off-by: Vasily Khoruzhick 

CCing Stefan and Scott on this one.

> ---
>  drivers/mtd/cfi_flash.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
> index 39932f4..18831c6 100644
> --- a/drivers/mtd/cfi_flash.c
> +++ b/drivers/mtd/cfi_flash.c
> @@ -2203,6 +2203,8 @@ ulong flash_get_size (phys_addr_t base, int banknum)
>   flash_isset (info, sect_cnt,
>
> FLASH_OFFSET_PROTECT,
>
> FLASH_STATUS_PROTECT);
> + flash_write_cmd(info, sect_cnt, 0,
> + FLASH_CMD_RESET);
>   break;
>   case CFI_CMDSET_AMD_EXTENDED:
>   case CFI_CMDSET_AMD_STANDARD:
> 
s

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Re: [U-Boot] [PATCH 02/11] zipitz2: enable LCD rotation

[Marek Vasut]

On 03/21/2016 02:37 AM, Vasily Khoruzhick wrote:
> z2's screen is rotated by 270 degrees
> 
> Signed-off-by: Vasily Khoruzhick 
> ---
>  drivers/video/pxa_lcd.c   | 1 +
>  include/configs/zipitz2.h | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c
> index 2799425..1809fc6 100644
> --- a/drivers/video/pxa_lcd.c
> +++ b/drivers/video/pxa_lcd.c
> @@ -175,6 +175,7 @@ vidinfo_t panel_info = {
>  vidinfo_t panel_info = {
>   .vl_col = 240,
>   .vl_row = 320,
> + .vl_rot = 3,
>   .vl_width   = 240,
>   .vl_height  = 320,
>   .vl_clkp= CONFIG_SYS_HIGH,

Someone should rewrite the entire pxa_lcd driver to cfb-console API and
DM, but yeah:

Acked-by: Marek Vasut 

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Re: [U-Boot] [PATCH 07/11] pxa: start.S: enable SRAM clock

[Marek Vasut]

On 03/21/2016 02:37 AM, Vasily Khoruzhick wrote:
> SRAM is used for early stack, but kernel disables its clock on suspend.
> Re-enable SRAM clock on startup, otherwise u-boot crashes on resume from 
> suspend.
> 
> Signed-off-by: Vasily Khoruzhick 
> ---
>  arch/arm/cpu/pxa/start.S | 10 +-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
> index 24b6ad1..ce1181a 100644
> --- a/arch/arm/cpu/pxa/start.S
> +++ b/arch/arm/cpu/pxa/start.S
> @@ -53,7 +53,15 @@ reset:
>  #ifdef   CONFIG_CPU_PXA25X
>   bl  lock_cache_for_stack
>  #endif
> -
> +#ifdef   CONFIG_CPU_PXA27X
> + /*
> +  * enable clock for SRAM
> +  */
> + ldr r0,=CKEN
> + ldr r1,[r0]
> + orr r1,r1,#(1 << 20)

Don't we have a macro for this 1 << 20 already ?

> + str r1,[r0]
> +#endif
>   bl  _main
>  
>  
> /*--*/
> 


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Re: [U-Boot] [PATCH 01/11] zipitz2: restore board support

[Marek Vasut]

On 03/21/2016 02:37 AM, Vasily Khoruzhick wrote:
> zipitz2 was dropped in 49d8899ba9c26335e4a12e01c18028fc5e40c796

That's great to know. So what does this patch do ?

> Signed-off-by: Vasily Khoruzhick 

Hi!

> +int dram_init(void)
> +{
> + pxa2xx_dram_init();
> + gd->ram_size = PHYS_SDRAM_1_SIZE;
> + return 0;
> +}
> +
> +void dram_init_banksize(void)
> +{
> + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;

There should be a default function for this in common/board_*c

> +}
> +
> +#ifdef   CONFIG_CMD_MMC
> +int board_mmc_init(bd_t *bis)
> +{
> + pxa_mmc_register(0);
> + return 0;
> +}
> +#endif

[...]

> +void zipitz2_spi_sda(int set)
> +{
> + /* GPIO 13 */
> + if (set)
> + writel((1 << 13), GPSR0);
> + else
> + writel((1 << 13), GPCR0);

This could seriously use a conversion to GPIO driver, but this can be
done later. You can drop the excess parenthesis around 1 << 13 here and
all over the place. You can even convert it to BIT(13) .

> +}
> +
> +void zipitz2_spi_scl(int set)
> +{
> + /* GPIO 22 */
> + if (set)
> + writel((1 << 22), GPCR0);
> + else
> + writel((1 << 22), GPSR0);
> +}

[...]

> +void lcd_start(void)
> +{
> + int i;
> + unsigned char reg[3] = { 0x74, 0x00, 0 };
> + unsigned char data[3] = { 0x76, 0, 0 };
> + unsigned char dummy[3] = { 0, 0, 0 };

all should be const

> + /* PWM2 AF */
> + writel(readl(GAFR0_L) | 0x0080, GAFR0_L);
> + /* Enable clock to all PWM */
> + writel(readl(CKEN) | 0x3, CKEN);
> + /* Configure PWM2 */
> + writel(0x4f, PWM_CTRL2);
> + writel(0x2ff, PWM_PWDUTY2);
> + writel(792, PWM_PERVAL2);
> +
> + /* Toggle the reset pin to reset the LCD */
> + writel((1 << 19), GPSR0);
> + udelay(10);
> + writel((1 << 19), GPCR0);
> + udelay(2);
> + writel((1 << 19), GPSR0);

BIT()

> + udelay(2);
> +
> + /* Program the LCD init sequence */
> + for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) {
> + reg[0] = 0x74;
> + reg[1] = 0x0;
> + reg[2] = lcd_data[i].reg;
> + spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
> +
> + data[0] = 0x76;
> + data[1] = lcd_data[i].data >> 8;
> + data[2] = lcd_data[i].data & 0xff;
> + spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
> +
> + if (lcd_data[i].mdelay)
> + udelay(lcd_data[i].mdelay * 1000);

mdelay ;-)

> + }
> +
> + writel((1 << 11), GPSR0);
> +}
> +#endif

[...]

> diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
> new file mode 100644
> index 000..586a445
> --- /dev/null
> +++ b/include/configs/zipitz2.h
> @@ -0,0 +1,224 @@
> +/*
> + * Aeronix Zipit Z2 configuration file
> + *
> + * Copyright (C) 2009-2010 Marek Vasut 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/*
> + * High Level Board Configuration Options
> + */
> +#define  CONFIG_CPU_PXA27X   1   /* Marvell PXA270 CPU */
> +#define  CONFIG_SYS_TEXT_BASE0x0

use #define[SPACE] not #define[TAB] and please fix it all over the patch.

> +#undef   CONFIG_BOARD_LATE_INIT
> +#undef   CONFIG_SKIP_LOWLEVEL_INIT
> +#define  CONFIG_PREBOOT

[...]

Run checkpatch.pl on the patches please ;-)

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Re: [U-Boot] [PATCH 08/11] pxa: add support for D- and I- caches

[Marek Vasut]

On 03/21/2016 02:37 AM, Vasily Khoruzhick wrote:
> Tested with OHCI and pxafb drivers - no issues found
> 
> Signed-off-by: Vasily Khoruzhick 
> ---
>  arch/arm/cpu/pxa/Makefile|  1 +
>  arch/arm/cpu/pxa/cache.c | 62 
> 
>  arch/arm/cpu/pxa/pxa2xx.c| 10 +++
>  include/configs/pxa-common.h |  1 +
>  4 files changed, 74 insertions(+)
>  create mode 100644 arch/arm/cpu/pxa/cache.c
> 
> diff --git a/arch/arm/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile
> index 3ee08cd..79fcb73 100644
> --- a/arch/arm/cpu/pxa/Makefile
> +++ b/arch/arm/cpu/pxa/Makefile
> @@ -14,3 +14,4 @@ obj-y   += cpuinfo.o
>  obj-y+= timer.o
>  obj-y+= usb.o
>  obj-y+= relocate.o
> +obj-y+= cache.o
> diff --git a/arch/arm/cpu/pxa/cache.c b/arch/arm/cpu/pxa/cache.c
> new file mode 100644
> index 000..7aba112
> --- /dev/null
> +++ b/arch/arm/cpu/pxa/cache.c
> @@ -0,0 +1,62 @@
> +/*
> + * (C) Copyright 2016 Vasily Khoruzhick 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +
> +#ifndef CONFIG_SYS_CACHELINE_SIZE
> +#define CONFIG_SYS_CACHELINE_SIZE32

This condition where CONFIG_SYS_CACHELINE_SIZE is undefined must not
ever happen.

> +#endif
> +
> +void invalidate_dcache_all(void)
> +{
> + /* Flush/Invalidate I cache */
> + asm volatile("mcr p15, 0, %0, c7, c5, 0\n" : : "r"(0));
> + /* Flush/Invalidate D cache */
> + asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
> +}
> +
> +void flush_dcache_all(void)
> +{
> + return invalidate_dcache_all();
> +}
> +
> +void invalidate_dcache_range(unsigned long start, unsigned long stop)
> +{
> + start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
> + stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);

Apply same sanity check as armv7 does please.

> + while (start <= stop) {
> + asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
> + start += CONFIG_SYS_CACHELINE_SIZE;
> + }
> +}
> +
> +void flush_dcache_range(unsigned long start, unsigned long stop)
> +{
> + return invalidate_dcache_range(start, stop);
> +}
> +#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
> +void invalidate_dcache_all(void)
> +{
> +}
> +
> +void flush_dcache_all(void)
> +{
> +}
> +#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
> +
> +/*
> + * Stub implementations for l2 cache operations
> + */
> +
> +__weak void l2_cache_disable(void) {}
> +
> +#if defined CONFIG_SYS_THUMB_BUILD
> +__weak void invalidate_l2_cache(void) {}
> +#endif
> diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c
> index 2f12fb9..77f0ef2 100644
> --- a/arch/arm/cpu/pxa/pxa2xx.c
> +++ b/arch/arm/cpu/pxa/pxa2xx.c
> @@ -284,3 +284,13 @@ void reset_cpu(ulong ignored)
>   for (;;)
>   ;
>  }
> +
> +void enable_caches(void)
> +{
> +#ifndef CONFIG_SYS_ICACHE_OFF
> + icache_enable();
> +#endif
> +#ifndef CONFIG_SYS_DCACHE_OFF
> + dcache_enable();
> +#endif
> +}
> diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h
> index 4c1c2c7..7295687 100644
> --- a/include/configs/pxa-common.h
> +++ b/include/configs/pxa-common.h
> @@ -10,6 +10,7 @@
>  #define  __CONFIG_PXA_COMMON_H__
>  
>  #define  CONFIG_DISPLAY_CPUINFO
> +#define  CONFIG_SYS_ARM_CACHE_WRITETHROUGH
>  
>  /*
>   * KGDB
> 


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 09/11] pxa_lcd: make driver cache-aware

[Marek Vasut]

On 03/21/2016 02:37 AM, Vasily Khoruzhick wrote:
> Signed-off-by: Vasily Khoruzhick 
> ---
>  drivers/video/pxa_lcd.c | 16 
>  1 file changed, 16 insertions(+)

Why don't you just allocate the piece of LCD memory as non-cachable ?

-- 
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[U-Boot] [RFC V2 PATCH 3/3] mmc: add support for block device cache

[Eric Nelson]

Signed-off-by: Eric Nelson 
---
 drivers/mmc/mmc.c   | 10 +-
 drivers/mmc/mmc_write.c |  7 +++
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 8b2e606..956f4e1 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -6,7 +6,6 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
-
 #include 
 #include 
 #include 
@@ -240,6 +239,8 @@ static ulong mmc_bread(struct blk_desc *block_dev, lbaint_t 
start,
int dev_num = block_dev->devnum;
int err;
lbaint_t cur, blocks_todo = blkcnt;
+   void *outbuf = dst;
+   lbaint_t outblk = start;
 
if (blkcnt == 0)
return 0;
@@ -260,6 +261,10 @@ static ulong mmc_bread(struct blk_desc *block_dev, 
lbaint_t start,
return 0;
}
 
+   if (cache_block_read(IF_TYPE_MMC, dev_num, start, blkcnt,
+mmc->read_bl_len, dst))
+   return blkcnt;
+
if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
debug("%s: Failed to set blocklen\n", __func__);
return 0;
@@ -277,6 +282,9 @@ static ulong mmc_bread(struct blk_desc *block_dev, lbaint_t 
start,
dst += cur * mmc->read_bl_len;
} while (blocks_todo > 0);
 
+   cache_block_fill(IF_TYPE_MMC, dev_num, outblk, blkcnt,
+mmc->read_bl_len, outbuf);
+
return blkcnt;
 }
 
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index 7b186f8..1c96d29 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "mmc_private.h"
 
 static ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt)
@@ -20,6 +21,8 @@ static ulong mmc_erase_t(struct mmc *mmc, ulong start, 
lbaint_t blkcnt)
ulong end;
int err, start_cmd, end_cmd;
 
+   cache_block_invalidate(IF_TYPE_MMC, mmc->block_dev.devnum);
+
if (mmc->high_capacity) {
end = start + blkcnt - 1;
} else {
@@ -82,6 +85,8 @@ unsigned long mmc_berase(struct blk_desc *block_dev, lbaint_t 
start,
if (err < 0)
return -1;
 
+   cache_block_invalidate(IF_TYPE_MMC, dev_num);
+
/*
 * We want to see if the requested start or total block count are
 * unaligned.  We discard the whole numbers and only care about the
@@ -186,6 +191,8 @@ ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t 
start, lbaint_t blkcnt,
if (err < 0)
return 0;
 
+   cache_block_invalidate(IF_TYPE_MMC, dev_num);
+
if (mmc_set_blocklen(mmc, mmc->write_bl_len))
return 0;
 
-- 
2.6.2

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[U-Boot] [RFC V2 PATCH 1/3] drivers: block: add block device cache

[Eric Nelson]

Add a block device cache to speed up repeated reads of block devices by 
various filesystems.

This small amount of cache can dramatically speed up filesystem
operations by skipping repeated reads of common areas of a block
device (typically directory structures).

This has shown to have some benefit on FAT filesystem operations of
loading a kernel and RAM disk, but more dramatic benefits on ext4
filesystems when the kernel and/or RAM disk are spread across 
multiple extent header structures as described in commit fc0fc50.

The cache is implemented through a minimal list (block_cache) maintained
in most-recently-used order and count of the current number of entries
(cache_count). It uses a maximum block count setting to prevent copies
of large block reads and an upper bound on the number of cached areas.

The maximum number of entries in the cache defaults to 4 and the maximum
number of blocks per cache entry has a default of 1, which matches the
current implementation of at least FAT and ext4 that only read a single
block at a time.

The 'blkcache' command (enabled through CONFIG_CMD_BLOCK_CACHE) allows
changing these values and can be used to tune for a particular filesystem
layout.

Signed-off-by: Eric Nelson 
---
 drivers/block/Makefile  |   1 +
 drivers/block/cache_block.c | 240 
 include/part.h  |  69 +
 3 files changed, 310 insertions(+)
 create mode 100644 drivers/block/cache_block.c

diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index b5c7ae1..056a48b 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_IDE_SIL680) += sil680.o
 obj-$(CONFIG_SANDBOX) += sandbox.o
 obj-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
 obj-$(CONFIG_SYSTEMACE) += systemace.o
+obj-$(CONFIG_BLOCK_CACHE) += cache_block.o
diff --git a/drivers/block/cache_block.c b/drivers/block/cache_block.c
new file mode 100644
index 000..e4ebeda
--- /dev/null
+++ b/drivers/block/cache_block.c
@@ -0,0 +1,240 @@
+/*
+ * Copyright (C) Nelson Integration, LLC 2016
+ * Author: Eric Nelson
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct block_cache_node {
+   struct list_head lh;
+   int iftype;
+   int devnum;
+   lbaint_t start;
+   lbaint_t blkcnt;
+   unsigned long blksz;
+   char *cache;
+};
+
+static LIST_HEAD(block_cache);
+static unsigned cache_count;
+
+static unsigned long max_blocks_per_entry = 1;
+static unsigned long max_cache_entries = 4;
+
+static unsigned block_cache_misses;
+static unsigned block_cache_hits;
+
+static int trace;
+
+/*
+ * search for a set of blocks in the cache
+ *
+ * remove and return the node if found so it can be
+ * added back at the start of the list and maintain MRU order)
+ */
+static struct block_cache_node *cache_find
+   (int iftype, int devnum,
+lbaint_t start, lbaint_t blkcnt,
+unsigned long blksz)
+{
+   struct block_cache_node *node;
+
+   list_for_each_entry(node, _cache, lh)
+   if ((node->iftype == iftype) &&
+   (node->devnum == devnum) &&
+   (node->blksz == blksz) &&
+   (node->start <= start) &&
+   (node->start + node->blkcnt >= start + blkcnt)) {
+   list_del(>lh);
+   return node;
+   }
+   return 0;
+}
+
+int cache_block_read(int iftype, int devnum,
+lbaint_t start, lbaint_t blkcnt,
+unsigned long blksz, void *buffer)
+{
+   struct block_cache_node *node = cache_find(iftype, devnum, start,
+  blkcnt, blksz);
+   if (node) {
+   const char *src = node->cache + (start - node->start) * blksz;
+   list_add(>lh, _cache);
+   memcpy(buffer, src, blksz*blkcnt);
+   if (trace)
+   printf("hit: start " LBAF ", count " LBAFU "\n",
+  start, blkcnt);
+   ++block_cache_hits;
+   return 1;
+   }
+
+   if (trace)
+   printf("miss: start " LBAF ", count " LBAFU "\n",
+  start, blkcnt);
+   ++block_cache_misses;
+   return 0;
+}
+
+void cache_block_fill(int iftype, int devnum,
+ lbaint_t start, lbaint_t blkcnt,
+ unsigned long blksz, void const *buffer)
+{
+   lbaint_t bytes;
+   struct block_cache_node *node;
+
+   /* don't cache big stuff */
+   if (blkcnt > max_blocks_per_entry)
+   return;
+
+   if (max_cache_entries == 0)
+   return;
+
+   bytes = blksz * blkcnt;
+   if (max_cache_entries <= cache_count) {
+   /* pop LRU */
+   node = (struct block_cache_node *)block_cache.prev;
+   

[U-Boot] [RFC V2 PATCH 2/3] block: add Kconfig options for [CMD_]BLOCK_CACHE

[Eric Nelson]

Allow the selection of CONFIG_BLOCK_CACHE, CONFIG_CMD_BLOCK_CACHE
using menuconfig.

Signed-off-by: Eric Nelson 
---
 drivers/block/Kconfig | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index f35c4d4..6529efb 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -18,3 +18,22 @@ config DISK
  types can use this, such as AHCI/SATA. It does not provide any 
standard
  operations at present. The block device interface has not been 
converted
  to driver model.
+
+config BLOCK_CACHE
+   bool "Use block device cache"
+   default n
+   help
+ This option enables a disk-block cache for all block devices.
+ This is most useful when accessing filesystems under U-Boot since
+ it will prevent repeated reads from directory structures.
+
+config CMD_BLOCK_CACHE
+   bool "Include block device cache control command (blkcache)"
+   depends on BLOCK_CACHE
+   default y if BLOCK_CACHE
+   help
+ Enable the blkcache command, which can be used to control the
+ operation of the cache functions.
+ This is most useful when fine-tuning the operation of the cache
+ during development, but also allows the cache to be disabled when
+ it might hurt performance (e.g. when using the ums command).
-- 
2.6.2

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[U-Boot] [RFC V2 PATCH 0/3] Add cache for block devices

[Eric Nelson]

Here's a more full-featured implementation of a cache for block devices
that uses a small linked list of cache blocks.

Experimentation loading a 4.5 MiB kernel from the root directory of 
a FAT filesystem shows that a single cache entry of a single block
is the only 

Loading the same from the /boot directory of an ext4 filesystem
shows a benefit with 4 cache entries, though the single biggest
benefit is also with the first cache entry:

=> for n in 0 1 2 4 8 ; do 
>blkc 1 $n ; blkc c ; blkc i ; 
>load mmc 0:2 10008000 /boot/zImage ; 
> done
changed to max of 0 entries of 1 blocks each
4955304 bytes read in 503 ms (9.4 MiB/s)
changed to max of 1 entries of 1 blocks each
4955304 bytes read in 284 ms (16.6 MiB/s)
changed to max of 2 entries of 1 blocks each
4955304 bytes read in 284 ms (16.6 MiB/s)
changed to max of 4 entries of 1 blocks each
4955304 bytes read in 255 ms (18.5 MiB/s)
changed to max of 8 entries of 1 blocks each
4955304 bytes read in 255 ms (18.5 MiB/s)

As mentioned earlier in this thread, the modification to the mmc
layer should probably be simpler and easier to apply to other
block subsystems.

Eric Nelson (3):
  drivers: block: add block device cache
  block: add Kconfig options for BLOCK_CACHE, CMD_BLOCK_CACHE
  mmc: add support for block device cache

 drivers/block/Kconfig   |  19 
 drivers/block/Makefile  |   1 +
 drivers/block/cache_block.c | 240 
 drivers/mmc/mmc.c   |  10 +-
 drivers/mmc/mmc_write.c |   7 ++
 include/part.h  |  69 +
 6 files changed, 345 insertions(+), 1 deletion(-)
 create mode 100644 drivers/block/cache_block.c

-- 
2.6.2

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[U-Boot] [PATCH 06/11] zipitz2: enable USB host support

[Vasily Khoruzhick]

Signed-off-by: Vasily Khoruzhick 
---
 board/zipitz2/zipitz2.c   | 21 +
 include/configs/zipitz2.h |  1 +
 2 files changed, 22 insertions(+)

diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c
index 8fa1261..aefbeee 100644
--- a/board/zipitz2/zipitz2.c
+++ b/board/zipitz2/zipitz2.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -52,6 +53,26 @@ int dram_init(void)
return 0;
 }
 
+#ifdef CONFIG_CMD_USB
+int board_usb_init(int index, enum usb_init_type init)
+{
+   /* enable port 2 */
+   writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+   UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
+
+   return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+   return 0;
+}
+
+void usb_board_stop(void)
+{
+}
+#endif
+
 void dram_init_banksize(void)
 {
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index f69b52e..52a36b7 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -64,6 +64,7 @@
 #defineCONFIG_CMD_ENV
 #defineCONFIG_CMD_MMC
 #defineCONFIG_CMD_SPI
+#defineCONFIG_CMD_USB
 
 /*
  * MMC Card Configuration
-- 
2.7.2

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[U-Boot] [PATCH 09/11] pxa_lcd: make driver cache-aware

[Vasily Khoruzhick]

Signed-off-by: Vasily Khoruzhick 
---
 drivers/video/pxa_lcd.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c
index ba4f897..d64c25b 100644
--- a/drivers/video/pxa_lcd.c
+++ b/drivers/video/pxa_lcd.c
@@ -353,6 +353,9 @@ void lcd_ctrl_init (void *lcdbase)
pxafb_init(_info);
pxafb_setup_gpio(_info);
pxafb_enable_controller(_info);
+
+   /* Enable flushing if we enabled dcache */
+   lcd_set_flush_dcache(1);
 }
 
 /*--*/
@@ -565,6 +568,10 @@ static int pxafb_init (vidinfo_t *vid)
fbi->dmadesc_fblow->fidr  = 0;
fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
 
+   flush_dcache_range((u32)fbi->dmadesc_fblow,
+  (u32)fbi->dmadesc_fblow +
+  sizeof(*fbi->dmadesc_fblow));
+
fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel 
mode */
 
fbi->dmadesc_fbhigh->fsadr = fbi->screen;
@@ -580,11 +587,20 @@ static int pxafb_init (vidinfo_t *vid)
/* assume any mode with <12 bpp is palette driven */
fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
+   flush_dcache_range((u32)fbi->dmadesc_fbhigh,
+  (u32)fbi->dmadesc_fbhigh +
+  sizeof(*fbi->dmadesc_fbhigh));
+   flush_dcache_range((u32)fbi->dmadesc_palette,
+  (u32)fbi->dmadesc_palette +
+  sizeof(*fbi->dmadesc_palette));
/* flips back and forth between pal and fbhigh */
fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
}
else
{
+   flush_dcache_range((u32)fbi->dmadesc_fbhigh,
+  (u32)fbi->dmadesc_fbhigh +
+  sizeof(*fbi->dmadesc_fbhigh));
/* palette shouldn't be loaded in true-color mode */
fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just 
fbhigh */
-- 
2.7.2

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[U-Boot] [PATCH 10/11] zipitz2: enable caches

[Vasily Khoruzhick]

It speeds up loading kernel from SD or USB a lot.

Signed-off-by: Vasily Khoruzhick 
---
 board/zipitz2/zipitz2.c   | 4 
 include/configs/zipitz2.h | 3 +--
 2 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c
index aefbeee..d3ca939 100644
--- a/board/zipitz2/zipitz2.c
+++ b/board/zipitz2/zipitz2.c
@@ -30,10 +30,6 @@ inline void lcd_start(void) {};
  */
 int board_init(void)
 {
-   /* We have RAM, disable cache */
-   dcache_disable();
-   icache_disable();
-
/* arch number of Z2 */
gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2;
 
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index 52a36b7..5200e02 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -27,8 +27,6 @@
 #define CONFIG_ENV_ADDR0x4
 #define CONFIG_ENV_SIZE0x1
 
-#define CONFIG_SYS_DCACHE_OFF
-
 #defineCONFIG_SYS_MALLOC_LEN   (128*1024)
 #defineCONFIG_ARCH_CPU_INIT
 
@@ -65,6 +63,7 @@
 #defineCONFIG_CMD_MMC
 #defineCONFIG_CMD_SPI
 #defineCONFIG_CMD_USB
+#defineCONFIG_CMD_CACHE
 
 /*
  * MMC Card Configuration
-- 
2.7.2

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[U-Boot] [PATCH 11/11] cfi_flash: return device into read array mode after reading status

[Vasily Khoruzhick]

Otherwise flash remains in read status mode and it's not possible
to access data on flash.

Signed-off-by: Vasily Khoruzhick 
---
 drivers/mtd/cfi_flash.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 39932f4..18831c6 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -2203,6 +2203,8 @@ ulong flash_get_size (phys_addr_t base, int banknum)
flash_isset (info, sect_cnt,
 
FLASH_OFFSET_PROTECT,
 
FLASH_STATUS_PROTECT);
+   flash_write_cmd(info, sect_cnt, 0,
+   FLASH_CMD_RESET);
break;
case CFI_CMDSET_AMD_EXTENDED:
case CFI_CMDSET_AMD_STANDARD:
-- 
2.7.2

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[U-Boot] [PATCH 04/11] zipitz2: enable libfdt

[Vasily Khoruzhick]

zipitz2 supports DT boot since linux-4.4 (not mainlined yet)

Signed-off-by: Vasily Khoruzhick 
---
 include/configs/zipitz2.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index 169eaf3..f69b52e 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -47,6 +47,7 @@
 #defineCONFIG_SETUP_MEMORY_TAGS
 #defineCONFIG_SYS_TEXT_BASE0x0
 #defineCONFIG_LZMA /* LZMA compression support */
+#defineCONFIG_OF_LIBFDT
 
 /*
  * Serial Console Configuration
-- 
2.7.2

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[U-Boot] [PATCH 07/11] pxa: start.S: enable SRAM clock

[Vasily Khoruzhick]

SRAM is used for early stack, but kernel disables its clock on suspend.
Re-enable SRAM clock on startup, otherwise u-boot crashes on resume from 
suspend.

Signed-off-by: Vasily Khoruzhick 
---
 arch/arm/cpu/pxa/start.S | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index 24b6ad1..ce1181a 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -53,7 +53,15 @@ reset:
 #ifdef CONFIG_CPU_PXA25X
bl  lock_cache_for_stack
 #endif
-
+#ifdef CONFIG_CPU_PXA27X
+   /*
+* enable clock for SRAM
+*/
+   ldr r0,=CKEN
+   ldr r1,[r0]
+   orr r1,r1,#(1 << 20)
+   str r1,[r0]
+#endif
bl  _main
 
 
/*--*/
-- 
2.7.2

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[U-Boot] [PATCH 08/11] pxa: add support for D- and I- caches

[Vasily Khoruzhick]

Tested with OHCI and pxafb drivers - no issues found

Signed-off-by: Vasily Khoruzhick 
---
 arch/arm/cpu/pxa/Makefile|  1 +
 arch/arm/cpu/pxa/cache.c | 62 
 arch/arm/cpu/pxa/pxa2xx.c| 10 +++
 include/configs/pxa-common.h |  1 +
 4 files changed, 74 insertions(+)
 create mode 100644 arch/arm/cpu/pxa/cache.c

diff --git a/arch/arm/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile
index 3ee08cd..79fcb73 100644
--- a/arch/arm/cpu/pxa/Makefile
+++ b/arch/arm/cpu/pxa/Makefile
@@ -14,3 +14,4 @@ obj-y += cpuinfo.o
 obj-y  += timer.o
 obj-y  += usb.o
 obj-y  += relocate.o
+obj-y  += cache.o
diff --git a/arch/arm/cpu/pxa/cache.c b/arch/arm/cpu/pxa/cache.c
new file mode 100644
index 000..7aba112
--- /dev/null
+++ b/arch/arm/cpu/pxa/cache.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2016 Vasily Khoruzhick 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE  32
+#endif
+
+void invalidate_dcache_all(void)
+{
+   /* Flush/Invalidate I cache */
+   asm volatile("mcr p15, 0, %0, c7, c5, 0\n" : : "r"(0));
+   /* Flush/Invalidate D cache */
+   asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
+}
+
+void flush_dcache_all(void)
+{
+   return invalidate_dcache_all();
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+   start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+   stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+
+   while (start <= stop) {
+   asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
+   start += CONFIG_SYS_CACHELINE_SIZE;
+   }
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+   return invalidate_dcache_range(start, stop);
+}
+#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+/*
+ * Stub implementations for l2 cache operations
+ */
+
+__weak void l2_cache_disable(void) {}
+
+#if defined CONFIG_SYS_THUMB_BUILD
+__weak void invalidate_l2_cache(void) {}
+#endif
diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c
index 2f12fb9..77f0ef2 100644
--- a/arch/arm/cpu/pxa/pxa2xx.c
+++ b/arch/arm/cpu/pxa/pxa2xx.c
@@ -284,3 +284,13 @@ void reset_cpu(ulong ignored)
for (;;)
;
 }
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+   icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+   dcache_enable();
+#endif
+}
diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h
index 4c1c2c7..7295687 100644
--- a/include/configs/pxa-common.h
+++ b/include/configs/pxa-common.h
@@ -10,6 +10,7 @@
 #define__CONFIG_PXA_COMMON_H__
 
 #defineCONFIG_DISPLAY_CPUINFO
+#defineCONFIG_SYS_ARM_CACHE_WRITETHROUGH
 
 /*
  * KGDB
-- 
2.7.2

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[U-Boot] [PATCH 05/11] pxa-common: pxa27x has 3 OHCI ports

[Vasily Khoruzhick]

3rd port can be used as a device or host.

Signed-off-by: Vasily Khoruzhick 
---
 include/configs/pxa-common.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h
index f0ecc34..4c1c2c7 100644
--- a/include/configs/pxa-common.h
+++ b/include/configs/pxa-common.h
@@ -37,7 +37,11 @@
 #defineCONFIG_USB_OHCI_NEW
 #defineCONFIG_SYS_USB_OHCI_CPU_INIT
 #defineCONFIG_SYS_USB_OHCI_BOARD_INIT
+#ifdef CONFIG_CPU_PXA27X
+#defineCONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS  3
+#else
 #defineCONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS  2
+#endif
 #defineCONFIG_SYS_USB_OHCI_REGS_BASE   0x4c00
 #defineCONFIG_SYS_USB_OHCI_SLOT_NAME   "pxa-ohci"
 #defineCONFIG_USB_STORAGE
-- 
2.7.2

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[U-Boot] [PATCH 01/11] zipitz2: restore board support

[Vasily Khoruzhick]

zipitz2 was dropped in 49d8899ba9c26335e4a12e01c18028fc5e40c796

Signed-off-by: Vasily Khoruzhick 
---
 arch/arm/Kconfig  |   5 ++
 board/zipitz2/Kconfig |   9 ++
 board/zipitz2/MAINTAINERS |   6 ++
 board/zipitz2/Makefile|  10 +++
 board/zipitz2/zipitz2.c   | 200 +
 configs/zipitz2_defconfig |   7 ++
 include/configs/zipitz2.h | 224 ++
 7 files changed, 461 insertions(+)
 create mode 100644 board/zipitz2/Kconfig
 create mode 100644 board/zipitz2/MAINTAINERS
 create mode 100644 board/zipitz2/Makefile
 create mode 100644 board/zipitz2/zipitz2.c
 create mode 100644 configs/zipitz2_defconfig
 create mode 100644 include/configs/zipitz2.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e5f57ef..882a818 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -686,6 +686,10 @@ config TARGET_H2200
bool "Support h2200"
select CPU_PXA
 
+config TARGET_ZIPITZ2
+   bool "Support zipitz2"
+   select CPU_PXA
+
 config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
select CPU_PXA
@@ -859,6 +863,7 @@ source "board/technologic/ts4800/Kconfig"
 source "board/vscom/baltos/Kconfig"
 source "board/woodburn/Kconfig"
 source "board/work-microwave/work_92105/Kconfig"
+source "board/zipitz2/Kconfig"
 
 source "arch/arm/Kconfig.debug"
 
diff --git a/board/zipitz2/Kconfig b/board/zipitz2/Kconfig
new file mode 100644
index 000..c663504
--- /dev/null
+++ b/board/zipitz2/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_ZIPITZ2
+
+config SYS_BOARD
+   default "zipitz2"
+
+config SYS_CONFIG_NAME
+   default "zipitz2"
+
+endif
diff --git a/board/zipitz2/MAINTAINERS b/board/zipitz2/MAINTAINERS
new file mode 100644
index 000..e027cd3
--- /dev/null
+++ b/board/zipitz2/MAINTAINERS
@@ -0,0 +1,6 @@
+ZIPITZ2 BOARD
+M: Vasily Khoruzhick 
+S: Maintained
+F: board/zipitz2/
+F: include/configs/zipitz2.h
+F: configs/zipitz2_defconfig
diff --git a/board/zipitz2/Makefile b/board/zipitz2/Makefile
new file mode 100644
index 000..855f6bc
--- /dev/null
+++ b/board/zipitz2/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2009
+# Marek Vasut 
+#
+# Heavily based on pxa255_idp platform
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := zipitz2.o
diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c
new file mode 100644
index 000..8fa1261
--- /dev/null
+++ b/board/zipitz2/zipitz2.c
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2009
+ * Marek Vasut 
+ *
+ * Heavily based on pxa255_idp platform
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_SPI
+void lcd_start(void);
+#else
+inline void lcd_start(void) {};
+#endif
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+   /* We have RAM, disable cache */
+   dcache_disable();
+   icache_disable();
+
+   /* arch number of Z2 */
+   gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2;
+
+   /* adress of boot parameters */
+   gd->bd->bi_boot_params = 0xa100;
+
+   /* Enable LCD */
+   lcd_start();
+
+   return 0;
+}
+
+int dram_init(void)
+{
+   pxa2xx_dram_init();
+   gd->ram_size = PHYS_SDRAM_1_SIZE;
+   return 0;
+}
+
+void dram_init_banksize(void)
+{
+   gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+   gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+   pxa_mmc_register(0);
+   return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_SPI
+
+struct {
+   unsigned char   reg;
+   unsigned short  data;
+   unsigned char   mdelay;
+} lcd_data[] = {
+   { 0x07, 0x, 0 },
+   { 0x13, 0x, 10 },
+   { 0x11, 0x3004, 0 },
+   { 0x14, 0x200F, 0 },
+   { 0x10, 0x1a20, 0 },
+   { 0x13, 0x0040, 50 },
+   { 0x13, 0x0060, 0 },
+   { 0x13, 0x0070, 200 },
+   { 0x01, 0x0127, 0 },
+   { 0x02, 0x0700, 0 },
+   { 0x03, 0x1030, 0 },
+   { 0x08, 0x0208, 0 },
+   { 0x0B, 0x0620, 0 },
+   { 0x0C, 0x0110, 0 },
+   { 0x30, 0x0120, 0 },
+   { 0x31, 0x0127, 0 },
+   { 0x32, 0x, 0 },
+   { 0x33, 0x0503, 0 },
+   { 0x34, 0x0727, 0 },
+   { 0x35, 0x0124, 0 },
+   { 0x36, 0x0706, 0 },
+   { 0x37, 0x0701, 0 },
+   { 0x38, 0x0F00, 0 },
+   { 0x39, 0x0F00, 0 },
+   { 0x40, 0x, 0 },
+   { 0x41, 0x, 0 },
+   { 0x42, 0x013f, 0 },
+   { 0x43, 0x, 0 },
+   { 0x44, 0x013f, 0 },
+   { 0x45, 0x, 0 },
+   { 0x46, 0xef00, 0 },
+   { 0x47, 0x013f, 0 },
+   { 0x48, 0x, 0 },
+   { 0x07, 0x0015, 30 },
+   { 0x07, 0x0017, 0 },
+   { 0x20, 0x, 0 },
+   { 0x21, 0x, 0 },
+   { 0x22, 0x, 0 },
+};
+
+void 

[U-Boot] [PATCH 03/11] pxa_lcd: invert colors for Zipit Z2 to get white on black palette

[Vasily Khoruzhick]

Signed-off-by: Vasily Khoruzhick 
---
 drivers/video/pxa_lcd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c
index 1809fc6..ba4f897 100644
--- a/drivers/video/pxa_lcd.c
+++ b/drivers/video/pxa_lcd.c
@@ -166,7 +166,7 @@ vidinfo_t panel_info = {
 #ifdef CONFIG_LMS283GF05
 
 # define LCD_BPP   LCD_COLOR8
-/*# define LCD_INVERT_COLORS*/
+# define LCD_INVERT_COLORS
 
 /* you have to set lccr0 and lccr3 (including pcd) */
 # define REG_LCCR0 0x043008f8
-- 
2.7.2

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[U-Boot] [PATCH 02/11] zipitz2: enable LCD rotation

[Vasily Khoruzhick]

z2's screen is rotated by 270 degrees

Signed-off-by: Vasily Khoruzhick 
---
 drivers/video/pxa_lcd.c   | 1 +
 include/configs/zipitz2.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c
index 2799425..1809fc6 100644
--- a/drivers/video/pxa_lcd.c
+++ b/drivers/video/pxa_lcd.c
@@ -175,6 +175,7 @@ vidinfo_t panel_info = {
 vidinfo_t panel_info = {
.vl_col = 240,
.vl_row = 320,
+   .vl_rot = 3,
.vl_width   = 240,
.vl_height  = 320,
.vl_clkp= CONFIG_SYS_HIGH,
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index 586a445..169eaf3 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -83,6 +83,7 @@
 #ifdef CONFIG_CMD_SPI
 #defineCONFIG_SOFT_SPI
 #defineCONFIG_LCD
+#defineCONFIG_LCD_ROTATION
 #defineCONFIG_PXA_LCD
 #defineCONFIG_LMS283GF05
 
-- 
2.7.2

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Re: [U-Boot] [PULL] u-boot-socfpga/master

[Tom Rini]

On Sun, Mar 20, 2016 at 09:41:47PM +0100, Marek Vasut wrote:

> The following changes since commit e4fb863f6dec0002069d57422ebe3ce3af69a273:
> 
>   dm: blk: Add tests for block devices (2016-03-17 21:27:39 -0600)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-socfpga.git master
> 
> for you to fetch changes up to 93d9fc26cb7b4fcbb849e79d21d16b114e4501a9:
> 
>   arm: socfpga: sr1500: Misc updates (SPI speed, env location)
> (2016-03-20 18:01:11 +0100)
> 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [PULL] u-boot-usb/master

[Tom Rini]

On Sun, Mar 20, 2016 at 09:40:51PM +0100, Marek Vasut wrote:

> The following changes since commit e4fb863f6dec0002069d57422ebe3ce3af69a273:
> 
>   dm: blk: Add tests for block devices (2016-03-17 21:27:39 -0600)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-usb.git master
> 
> for you to fetch changes up to 1b108880e6433e398681785f51b2a2dca983cd1b:
> 
>   usb: xhci: Fix vendor command error if the request type is
> USB_REQ_SET_ADDRESS or USB_REQ_SET_CONFIGURATION. (2016-03-20 18:00:45
> +0100)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH] mx27: 16-bit wide watchdog registers

[Fabio Estevam]

On Sun, Mar 20, 2016 at 10:10 AM, Leonid Iziumtsev
 wrote:
> From: Leonid Iziumtsev 
>
> Make the watchdog registers 16-bit wide, as they are according to TRM.
>
> Signed-off-by: Leonid Iziumtsev 

Reviewed-by: Fabio Estevam 
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Re: [U-Boot] [RFC PATCH 2/2] mmc: add support for block device cache

[Eric Nelson]

Hi Tom,

On 03/20/2016 03:13 PM, Tom Rini wrote:
> On Sun, Mar 20, 2016 at 12:35:53PM -0700, Eric Nelson wrote:
>> Hi Stephen,
>>
>> On 03/17/2016 02:23 PM, Stephen Warren wrote:
>>> On 03/16/2016 03:40 PM, Eric Nelson wrote:
 Signed-off-by: Eric Nelson 
>>>
>>> Patch description.
>>>
 ---
   drivers/mmc/mmc.c   | 10 +-
   drivers/mmc/mmc_write.c |  7 +++
>>>
>>> Presumably it makes sense for the cache to work for IDE, SATA, USB,
>>> SCSI, ... too. I wonder if it's possible to put this code somewhere more
>>> central than mmc*.c so it automatically applies to
>>> dev_desc->block_read() (see include/part.h). Perhaps not since each
>>> implementation supplies its own block_read function directly, so the
>>> cache calls do need to be duplicated everywhere.
>>>
>>
>> Yeah. I haven't found a spot that would allow interception of
>> the various block_read/write functions.
> 
> Shouldn't DM also help here?
> 

I haven't yet looked, but this may be true.

I'm seeing some build breakage on master surrounding the use
of DM though.

If I select DM and BLK on top of nitrogen6q_defconfig, I get
lots of build errors.

I want to get a V2 RFC patch out before digging through the
details of that.

Regards,


Eric
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[U-Boot] How to run a new instance of u-boot from u-boot shell prompt

[Woody Wu]

Hi list,

in a running version of u-boot, assume i downloaded another version of
u-boot into my RAM, then how can i jump to this new u-boot and run?  I want
to do this because the new version of u-boot that i hacked not yet stable
so I don't want to actually flash it to my nand.

BTW: my current u-boot version is quite old: 2009-11.


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[U-Boot] [PATCH] mx27: 16-bit wide watchdog registers

[Leonid Iziumtsev]

From: Leonid Iziumtsev 

Make the watchdog registers 16-bit wide, as they are according to TRM.

Signed-off-by: Leonid Iziumtsev 
---
 arch/arm/cpu/arm926ejs/mx27/reset.c   | 8 
 arch/arm/include/asm/arch-mx27/imx-regs.h | 6 +++---
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/mx27/reset.c 
b/arch/arm/cpu/arm926ejs/mx27/reset.c
index f7b4a1c..e764986 100644
--- a/arch/arm/cpu/arm926ejs/mx27/reset.c
+++ b/arch/arm/cpu/arm926ejs/mx27/reset.c
@@ -27,14 +27,14 @@ void reset_cpu(ulong ignored)
 {
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */
-   writel(0x, >wcr);
+   writew(0x, >wcr);
 
/* Write Service Sequence */
-   writel(0x, >wsr);
-   writel(0x, >wsr);
+   writew(0x, >wsr);
+   writew(0x, >wsr);
 
/* Enable watchdog */
-   writel(WCR_WDE, >wcr);
+   writew(WCR_WDE, >wcr);
 
while (1);
/*NOTREACHED*/
diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h 
b/arch/arm/include/asm/arch-mx27/imx-regs.h
index baf1d29..40b76d2 100644
--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
@@ -106,9 +106,9 @@ struct esdramc_regs {
 
 /* Watchdog Registers*/
 struct wdog_regs {
-   u32 wcr;
-   u32 wsr;
-   u32 wstr;
+   u16 wcr;
+   u16 wsr;
+   u16 wstr;
 };
 
 /* PLL registers */
-- 
1.9.1

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Re: [U-Boot] [RFC PATCH 1/2] add block device cache

[Eric Nelson]

Thanks for the feedback Tom,

On 03/20/2016 03:13 PM, Tom Rini wrote:
> On Thu, Mar 17, 2016 at 02:33:04PM -0700, Eric Nelson wrote:
>> Thanks for the review(s) Stephen.
>>
>> On 03/17/2016 02:16 PM, Stephen Warren wrote:
>>> On 03/16/2016 03:40 PM, Eric Nelson wrote:
 Signed-off-by: Eric Nelson 
>>>
>>> A patch description would be useful here; the cover letter wouldn't be
>>> checked in.
>>>
>>
>> Yeah. Please hote the RFC.
>>
>> I was really hoping for some broader feedback about whether this
>> is a better approach than the more specialized ext4 extent cache.
> 
> Well, I guess it comes down to how hard it is to also re-use this on say
> USB (another common case and one I assume you can test on your HW) since
> all of EXT4 and FAT and MMC and USB are fairly common and we should be
> able to address these with your approach, or at least be within "rework
> some other stuff and then.." distance.
> 

It should be trivial to include this support for USB, SATA, IDE, or
any other block device, but not transparent.

I'm close to a V2 RFC patch so people can throw stones at an actual
implementation.

Regards,


Eric
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Re: [U-Boot] [RFC PATCH 2/2] mmc: add support for block device cache

[Tom Rini]

On Sun, Mar 20, 2016 at 12:35:53PM -0700, Eric Nelson wrote:
> Hi Stephen,
> 
> On 03/17/2016 02:23 PM, Stephen Warren wrote:
> > On 03/16/2016 03:40 PM, Eric Nelson wrote:
> >> Signed-off-by: Eric Nelson 
> > 
> > Patch description.
> > 
> >> ---
> >>   drivers/mmc/mmc.c   | 10 +-
> >>   drivers/mmc/mmc_write.c |  7 +++
> > 
> > Presumably it makes sense for the cache to work for IDE, SATA, USB,
> > SCSI, ... too. I wonder if it's possible to put this code somewhere more
> > central than mmc*.c so it automatically applies to
> > dev_desc->block_read() (see include/part.h). Perhaps not since each
> > implementation supplies its own block_read function directly, so the
> > cache calls do need to be duplicated everywhere.
> > 
> 
> Yeah. I haven't found a spot that would allow interception of
> the various block_read/write functions.

Shouldn't DM also help here?

-- 
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Re: [U-Boot] [RFC PATCH 1/2] add block device cache

[Tom Rini]

On Thu, Mar 17, 2016 at 02:33:04PM -0700, Eric Nelson wrote:
> Thanks for the review(s) Stephen.
> 
> On 03/17/2016 02:16 PM, Stephen Warren wrote:
> > On 03/16/2016 03:40 PM, Eric Nelson wrote:
> >> Signed-off-by: Eric Nelson 
> > 
> > A patch description would be useful here; the cover letter wouldn't be
> > checked in.
> > 
> 
> Yeah. Please hote the RFC.
> 
> I was really hoping for some broader feedback about whether this
> is a better approach than the more specialized ext4 extent cache.

Well, I guess it comes down to how hard it is to also re-use this on say
USB (another common case and one I assume you can test on your HW) since
all of EXT4 and FAT and MMC and USB are fairly common and we should be
able to address these with your approach, or at least be within "rework
some other stuff and then.." distance.

-- 
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[U-Boot] [PULL] u-boot-usb/master

[Marek Vasut]

The following changes since commit e4fb863f6dec0002069d57422ebe3ce3af69a273:

  dm: blk: Add tests for block devices (2016-03-17 21:27:39 -0600)

are available in the git repository at:

  git://git.denx.de/u-boot-usb.git master

for you to fetch changes up to 1b108880e6433e398681785f51b2a2dca983cd1b:

  usb: xhci: Fix vendor command error if the request type is
USB_REQ_SET_ADDRESS or USB_REQ_SET_CONFIGURATION. (2016-03-20 18:00:45
+0100)


Stefan Roese (4):
  usb: legacy_hub_port_reset(): Speedup hub reset handling
  usb: Remove 200 ms delay in usb_hub_port_connect_change()
  usb: Don't reset the USB hub a 2nd time
  usb: Change power-on / scanning timeout handling

Ted Chen (1):
  usb: xhci: Fix vendor command error if the request type is
USB_REQ_SET_ADDRESS or USB_REQ_SET_CONFIGURATION.

 common/usb.c|  13 +
 common/usb_hub.c| 329
+++---
 drivers/usb/host/xhci.c |   6 ++-
 include/usb.h   |   4 ++
 4 files changed, 239 insertions(+), 113 deletions(-)
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[U-Boot] [PULL] u-boot-socfpga/master

[Marek Vasut]

The following changes since commit e4fb863f6dec0002069d57422ebe3ce3af69a273:

  dm: blk: Add tests for block devices (2016-03-17 21:27:39 -0600)

are available in the git repository at:

  git://git.denx.de/u-boot-socfpga.git master

for you to fetch changes up to 93d9fc26cb7b4fcbb849e79d21d16b114e4501a9:

  arm: socfpga: sr1500: Misc updates (SPI speed, env location)
(2016-03-20 18:01:11 +0100)


Chin Liang See (1):
  arm: socfpga: Enabling U-Boot environment support in QSPI

Marek Vasut (1):
  arm: socfpga: Fix SR1500 env position

Stefan Roese (2):
  arm: socfpga: Allow boards to define a custom environment size
  arm: socfpga: sr1500: Misc updates (SPI speed, env location)

 arch/arm/dts/socfpga_cyclone5_sr1500.dts |  2 +-
 configs/socfpga_sr1500_defconfig |  2 ++
 include/configs/socfpga_common.h |  8 
 include/configs/socfpga_sr1500.h | 25 +++--
 4 files changed, 26 insertions(+), 11 deletions(-)
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Re: [U-Boot] [RFC PATCH 2/2] mmc: add support for block device cache

[Eric Nelson]

Hi Stephen,

On 03/17/2016 02:23 PM, Stephen Warren wrote:
> On 03/16/2016 03:40 PM, Eric Nelson wrote:
>> Signed-off-by: Eric Nelson 
> 
> Patch description.
> 
>> ---
>>   drivers/mmc/mmc.c   | 10 +-
>>   drivers/mmc/mmc_write.c |  7 +++
> 
> Presumably it makes sense for the cache to work for IDE, SATA, USB,
> SCSI, ... too. I wonder if it's possible to put this code somewhere more
> central than mmc*.c so it automatically applies to
> dev_desc->block_read() (see include/part.h). Perhaps not since each
> implementation supplies its own block_read function directly, so the
> cache calls do need to be duplicated everywhere.
> 

Yeah. I haven't found a spot that would allow interception of
the various block_read/write functions.

The get_dev_hwpart() routine in disk/part.c is close, but it seems
to be bypassed by cmd_mmc, cmd_sata, et cetera.

I think the best that can be done is to provide a common shim that can
easily be inserted from within the various block driver code.

>> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
>>*
>>* SPDX-License-Identifier:GPL-2.0+
>>*/
>> -
>>   #include 
> 
> Nit: unrelated change.
> 
> I think there is a missing call to cache_block_invalidate() when the MMC
> device gets re-enumerated/re-initialized. The user would do something to
> trigger this (e.g. mmc rescan) when they'd swapped an SD card out for
> example.
> 

Good catch.

> Do you have any stats on how many operations this saves for typical FS
> operations such as:
> 
> - Partition table type identification (with various types such as
> MBR/DOS, GPT, ...)
> - Partition enumeration
> - Filesystem identification (with various filesystems such as FAT, ext,
> ...)
> - File reads
> 

Not yet, but I'm working something up that will allow this to be
gathered easily. As soon as we implement a cache, it provides a nice
spot for tracing operations.

Regards,


Eric
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Re: [U-Boot] Linux hangs due to commit v2015.10-15-g02cc27c on loading i2c-mv64xx

[Hans de Goede]

Hi All,

Sun Mar 20 16:56:32 CET 2016, Michael Haas wrote:

> I'm running Debian Jessie with Linux 4.3.0-0.bpo.1-armmp-lpae on my
> a20-olinuxino-lime2.
> I have noticed that my board hangs with my recent u-boot versions when I
> load the i2c module.
>
> git-bisect narrowed the problem down to the following commit:
>
> 02cc27c74f9b884b538bcd1b93342a4c05b5d608 is the first bad commit
> commit 02cc27c74f9b884b538bcd1b93342a4c05b5d608
> Author: Hans de Goede 
> Date:   Sat Oct 3 15:29:24 2015 +0200
>
>sunxi: power: Change axp209 LDO3 and LDO4 default to disabled



> The axp209 is attached to the i2c bus, so that is likely the real
> culprit. In my setup, the axp209 drivers are loaded before I insert
> i2c-mv64xxx.
>
> What would be the best course of action here?
>
> * Revert the commit
> * Enable LDO3 and LDO4 for the a20-olinuxino-lime2 only?
> * Fix linux

I would go for option 3: "Fix linux", looking at the lime2 dts I see:

vcc_csi0: ldo3 {
regulator-min-microvolt = <70>;
regulator-max-microvolt = <350>;
regulator-always-on;
};

vcc_csi1: ldo4 {
regulator-min-microvolt = <125>;
regulator-max-microvolt = <330>;
regulator-always-on;
};

The regulator-always-on will cause both regulators to get turned on,
but the min / max constraints match the datasheet constrains / the
absolute min / max values these ldo-s can deliver, not the constraints
which the board design puts on these.

So now these ldo-s end up getting turned on at whatever voltage
is the default (which according to the datasheet is unknown),
where as the schematic says that if these get turned on (which
is not necessary) they should be run at 2.8V.

This dts file is the only axp209 using dts file which:

1) Does not have proper constraints for LDO3 / LDO4
2) Uses regulator-always-on; for these

I would suggest fixing both, first you can try making min = max =
280. And if that fixes things, which I expect it will, I would
also drop the regulator-always-on from the dts, since we really
only need to turn these on when using the csi interface in which
case it would be up to the csi driver to explicitly turn them on.

Regards,

Hans






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Re: [U-Boot] [PATCH] Add CONFIG_GMAC_TX_DELAY=4 for OlinuXino Lime2

[Hans de Goede]

Hi,

On 20-03-16 16:28, Michael Haas wrote:

On 03/20/2016 02:45 PM, Hans de Goede wrote:

Hi,

On 19-03-16 14:40, Michael Haas wrote:

On 03/19/2016 10:32 AM, Hans de Goede wrote:

Hi,

On 19-03-16 09:39, François-David Collin wrote:

Hi,

As I’m banging my head on this too, please allow me to provide some
details
I got two stable situations :
The Lime2 is connected directly to the Gbit interface of my laptop,
speed are OK:


Michael Haas' work to debug this by looking at the phy registers
seems to be the most promising so-far, the clk reg and axp209
registers all seem to be identical between good and bad setups.

Can you try to:

1) Stop the boot in u-boot (press a key on the serial console)
2) Bring up the network, e.g. type "dhcp" then ctrl+c when it tries
to tftp
3) Do: "mii read 1 0x11" in u-boot and record the output ?

Regards,

Hans


Hi all,

i have diffed and cross-compared logs of several working and broken tftp
downloads. The most significant
difference between working and broken was registers 0xa, 0x1c and 0x2a
in the first MII page.

These registers started making sense when I looked at the datasheet for
the RTL8211CL. Previously, I was looking at the RTL8211E.

0xA was set to 7800 for working runs and 3800 for broken runs. The
difference is bit 14 in the GBSR: 'MASTER/SLAVE Configuration
Resolution'. In the broken runs, the autonegotation configured the
OlinuXino to 'slave'. I have whipped up a quick patch which disable the
master/slave part of the autonegotiation and force master mode.

The patch itself is quite terrible as it's forcing the master mode bits
for every phy, not just for the RTL8211CL. It's good enough for testing,
however, and I seem to be getting consistent download speeds. There are
occasional hangs when booting the downloaded kernel, but that is
probably a different issue.

diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 51b5746..484b2be 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -170,6 +170,7 @@ int genphy_restart_aneg(struct phy_device *phydev)
   int genphy_config_aneg(struct phy_device *phydev)
   {
  int result;
+   phy_write(phydev, MDIO_DEVAD_NONE, 0x09, 0x1A00);

  if (AUTONEG_ENABLE != phydev->autoneg)
  return genphy_setup_forced(phydev);

Please test this change and let me know. If it's successful, I will
submit a proper version.


Good catch, I wonder why we need this. I believe that the proper version
should probably be wrapped in a #ifdef CONFIG_REALTEK_PHY_FORCE_MASTER
and then add a Kconfig option for this (and enable it in the lime2
defconfig), forcing this on all rtl8211cl phy-s seems wrong, unless
someone can dig up an errata from realtek which said we should.


I was going to add that in realtek.c, not in phy.c - as soon as I figure
out which section there is applicable.


Ack, I already understood that. What I mean is that even if you limit
the fix to just apply to rtl8211cl phys, that that is still a somewhat
big hammer if the problem only happens on the lime2. Always applying
the workaround if the phy is a rtl8211cl means also applying it on
other sunxi boards and likely also on boards with a completely different
soc which also happen to use the rtl8211cl, which is why I suggest that
you wrap it in #ifdef CONFIG_REALTEK_PHY_FORCE_MASTER and a matching
Kconfig bool, which defaults to false.


I have started a new thread
asking about that.


Ack I've seen that.


Are any other sunxi boards impacted by the same problem that you know ?



No, I don't know of any other boards, but I have not looked very hard :)


Ok, so for now lets put this fix / workaround behind a #ifdef then, and
enable it only on the lime2

Regards,

Hans
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[U-Boot] [PATCH] arm: socfpga: sockit: Use more relaxed DRAM timings

[Marek Vasut]

The currently present DRAM timings generated from GHRD 14.0 did
not work on SoCkit rev. D because they were too tight. Load the
DRAM timings from GHRD 13.0 which are more relaxed and work with
SoCkit rev. D.

Signed-off-by: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
---
 board/terasic/sockit/qts/iocsr_config.h | 116 
 board/terasic/sockit/qts/pll_config.h   |  14 ++--
 board/terasic/sockit/qts/sdram_config.h |  30 -
 3 files changed, 80 insertions(+), 80 deletions(-)

diff --git a/board/terasic/sockit/qts/iocsr_config.h 
b/board/terasic/sockit/qts/iocsr_config.h
index 83b1093..51b262b 100644
--- a/board/terasic/sockit/qts/iocsr_config.h
+++ b/board/terasic/sockit/qts/iocsr_config.h
@@ -181,17 +181,17 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x1000,
0xA034,
0x0D01,
-   0x40680208,
-   0x41034051,
-   0x12481A00,
-   0x802080D0,
-   0x34051406,
-   0x01A02490,
-   0x080D,
-   0x51406802,
-   0x02490340,
+   0xE0680B2C,
+   0x20834038,
+   0x11441A00,
+   0x80B2C0D0,
+   0x34038E06,
+   0x01A00208,
+   0x2C0D,
+   0x38E0680B,
+   0x00208340,
0xD01A,
-   0x0680A280,
+   0x0680B2C0,
0x1004,
0x0020,
0x1004,
@@ -255,17 +255,17 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x1000,
0xA034,
0x0D01,
-   0x40680208,
-   0x49034051,
-   0x12481A02,
-   0x80A280D0,
-   0x34030C06,
+   0xE0680B2C,
+   0x20834038,
+   0x11441A00,
+   0x80B2C0D0,
+   0x34038E06,
0x01A00040,
-   0x280D0002,
-   0x5140680A,
-   0x02490340,
-   0xD012481A,
-   0x0680A280,
+   0x2C0D0002,
+   0x38E0680B,
+   0x00208340,
+   0xD001041A,
+   0x0680B2C0,
0x1004,
0x0020,
0x1004,
@@ -330,18 +330,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x14F3690D,
0x1A041414,
0x00D0,
-   0x04864000,
-   0x59647A01,
-   0xD32CA3DE,
-   0xF551451E,
-   0x034CD348,
+   0x18864000,
+   0x49247A06,
+   0xABCF23D7,
+   0xF7DE791E,
+   0x0356E388,
0x821A,
0xD000,
-   0x05140680,
-   0xD669A47A,
-   0x1ED32CA3,
-   0x48F55E79,
-   0x00034C92,
+   0x05960680,
+   0xD749247A,
+   0x1EABCF23,
+   0x88F7DE79,
+   0x000356E3,
0x00080200,
0x1000,
0x00080200,
@@ -404,18 +404,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x14F3690D,
0x1A041414,
0x00D0,
-   0x14864000,
-   0x59647A05,
-   0x9228A3DE,
-   0xF65E791E,
-   0x034CD348,
-   0x821A0186,
+   0x18864000,
+   0x49247A06,
+   0xABCF23D7,
+   0xF7DE791E,
+   0x0356E388,
+   0x821A01C7,
0xD000,
0x0680,
-   0xD669A47A,
-   0x1E9228A3,
-   0x48F65E79,
-   0x00034CD3,
+   0xD749247A,
+   0x1EABCF23,
+   0x88F7DE79,
+   0x000356E3,
0x00080200,
0x1000,
0x00080200,
@@ -478,18 +478,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x14F3690D,
0x1A041414,
0x00D0,
-   0x0C864000,
-   0x79E47A03,
-   0xB2AAA3D1,
-   0xF551451E,
-   0x035CD348,
+   0x18864000,
+   0x49247A06,
+   0xABCF23D7,
+   0xF7DE791E,
+   0x0356E388,
0x821A,
0xD000,
0x0680,
-   0xD159647A,
-   0x1ED32CA3,
-   0x48F55145,
-   0x00035CD3,
+   0xD749247A,
+   0x1EABCF23,
+   0x88F7DE79,
+   0x000356E3,
0x00080200,
0x1000,
0x00080200,
@@ -552,18 +552,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x14F1690D,
0x1A041414,
0x00D0,
-   0x04864000,
-   0x69A47A01,
-   0x9228A3D6,
-   0xF65E791E,
-   0x034C9248,
+   0x18864000,
+   0x49247A06,
+   0xABCF23D7,
+   0xF7DE791E,
+   0x0356E388,
0x821A,
0xD000,
0x0680,
-   0xDE59647A,
-   0x1ED32CA3,
-   0x48F55E79,
-   0x00034CD3,
+   0xD749247A,
+   0x1EABCF23,
+   0x88F7DE79,
+   0x000356E3,
0x00080200,
0x1000,
0x00080200,
diff --git a/board/terasic/sockit/qts/pll_config.h 
b/board/terasic/sockit/qts/pll_config.h
index 0ecccbf..820b9ff 100644
--- a/board/terasic/sockit/qts/pll_config.h
+++ b/board/terasic/sockit/qts/pll_config.h
@@ -10,13 +10,13 @@
 #define CONFIG_HPS_DBCTRL_STAYOSC1 1
 
 #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
 #define 

[U-Boot] [PATCH] arm: mx5: Enable NAND TrimFFS on M53EVK

[Marek Vasut]

Enable NAND TrimFFS support in M53EVK, since it is convenient when
installing UBI images to NAND.

Signed-off-by: Marek Vasut 
Cc: Stefano Babic 
---
 include/configs/m53evk.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index fbaa600..c247c2a 100644
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -43,6 +43,7 @@
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SATA
 #define CONFIG_CMD_USB
-- 
2.7.0

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Re: [U-Boot] Newbie SPL question for socfpga_sockit

[Marek Vasut]

On 03/19/2016 12:10 PM, Phil Reid wrote:
> On 19/03/2016 5:22 AM, George Broz wrote:
>> On 18 March 2016 at 12:32, Marek Vasut  wrote:
>>> On 03/18/2016 07:59 PM, George Broz wrote:
 On 16 March 2016 at 18:35, Marek Vasut  wrote:
> On 03/16/2016 05:17 PM, George Broz wrote:
>> On 15 March 2016 at 18:29, George Broz  wrote:
>>
>>>
>>> Hello again -
>>>
>>> So under the assumption my SoCKit h/w was broken, I bought a new
>>> board.
>>> They are back ordered on SoCKit boards, so I got a DE0-Nano-SoC
>>> instead.
>>>
>>> I build the v2016.03 (release) version of u-boot-with-spl.sfp.
>>>
>>> I power-up the (brand new) board and get:
>>>
>>> U-Boot SPL 2016.03 (Mar 15 2016 - 14:52:42)
>>> drivers/ddr/altera/sequencer.c: Preparing to start memory
>>> calibration
>>> drivers/ddr/altera/sequencer.c: CALIBRATION FAILED
>>> drivers/ddr/altera/sequencer.c: Calibration complete
>>> SDRAM calibration failed.
>>> ### ERROR ### Please RESET the board ###
>>>
>>> U-Boot SPL 2016.03 (Mar 15 2016 - 14:52:42)
>>> drivers/ddr/altera/sequencer.c: Preparing to start memory
>>> calibration
>>> drivers/ddr/altera/sequencer.c: CALIBRATION FAILED
>>> drivers/ddr/altera/sequencer.c: Calibration complete
>>> SDRAM calibration failed.
>>> ### ERROR ### Please RESET the board ###
>>>
>>> U-Boot SPL 2016.03 (Mar 15 2016 - 14:52:42)
>>> drivers/ddr/altera/sequencer.c: Preparing to start memory
>>> calibration
>>> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
>>> drivers/ddr/altera/sequencer.c: Calibration complete
>>> Trying to boot from MMC
>>>
>>> U-Boot 2016.03 (Mar 15 2016 - 14:52:42 -0700)
>>>
>>> CPU:   Altera SoCFPGA Platform
>>> FPGA:  Altera Cyclone V, SE/A4 or SX/C4, version 0x0
>>> BOOT:  SD/MMC Internal Transceiver (3.0V)
>>> Watchdog enabled
>>> I2C:   ready
>>> DRAM:  1 GiB
>>> MMC:   dwmmc0@ff704000: 0
>>> In:serial
>>> Out:   serial
>>> Err:   serial
>>> Model: Terasic DE0-Nano(Atlas)
>>> Net:
>>> Error: ethernet@ff702000 address not set.
>>> No ethernet found.
>>> Hit any key to stop autoboot:  0
>>> =>
>>>
>>> And this is a good case... usually it doesn't succeed after the
>>> fourth try
>>> and I have to cycle power 4 or 5 times before I get lucky.
>>>
>>> If I do get lucky and then try to see a USB storage device, then
>>> I get:
>>>
>>> =>
>>> => usb start
>>> starting USB...
>>> USB0:   Core Release: 2.93a
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> dwc_otg_core_host_init: Timeout!
>>> scanning bus 0 for devices... 1 USB Device(s) found
>>> =>
>>>
>>> (Every time)
>>>
>>> The version of u-boot SPL that ships with the board:
>>> U-Boot SPL 2013.01.01 (Dec 29 2014 - 15:29:15)
>>>
>>> boots every time and has limited USB capability as
>>> it can see some USB sticks, but not others.
>>>
>>>
>>> Anyway - brand new board - same old symptoms.
>>>
>>> Is it perhaps a toolchain problem?? I'm using:
>>>
>>> Thread model: posix
>>> gcc version 4.9.3 20141031 (prerelease) (Linaro GCC 4.9-2014.11)
>>>
>>> COLLECT_GCC=arm-poky-linux-gnueabi-gcc
>>> COLLECT_LTO_WRAPPER=/opt/poky/1.7.1/sysroots/x86_64-pokysdk-linux/usr/libexec/arm-poky-linux-gnueabi/gcc/arm-poky-linux-gnueabi/4.9.3/lto-wrapper
>>>
>>> < snip >
>>>
>>> Any advice greatly appreciated.
>>>
>>>
>>> Regards,
>>> --George Broz
>>
>> Rebuilt using the Altera EDS15.0 toolchain:
>>
>>arm-altera-eabi-gcc --version
>>arm-altera-eabi-gcc (Sourcery CodeBench Lite 2014.11-13) 4.9.1
>>Copyright (C) 2014 Free Software Foundation, Inc.
>>This is free software; see the source for copying conditions. 
>> There is NO
>>warranty; not even for MERCHANTABILITY or FITNESS FOR A
>> PARTICULAR PURPOSE.
>>
>>
>> Get same result ... mostly failing calibration, non-working USB
>>
>> U-Boot SPL 2016.03 (Mar 16 2016 - 08:27:20)
>> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
>> drivers/ddr/altera/sequencer.c: CALIBRATION FAILED
>> drivers/ddr/altera/sequencer.c: Calibration complete
>> SDRAM 

Re: [U-Boot] Newbie SPL question for socfpga_sockit

[Marek Vasut]

On 03/20/2016 04:55 PM, Dinh Nguyen wrote:
> 
> 
> On 03/16/2016 08:35 PM, Marek Vasut wrote:
>>>
>>> Does this work for anybody else?
>>> Is it in anyone's experience that these (cheaper) Terasic
>>> eval boards are generally out of spec?
>>>
>>> Is there a way to relax the calibration parameters? the USB parameters?
>>>
>>> Would it help if I posted debug output?
>>
>> Sorry for the late reply, I am horribly overloaded now. I asked someone
>> in #u-boot who has the DE0-NANO-SOC board to test latest u-boot/master
>> on it and it apparently worked for him. I should get some more feedback
>> in the morning [ see http://pastebin.com/CM1QJGnh ] .
>>
>> Still, this is getting real creepy. You are the second person who is
>> complaining about misbehavior of terasic boards with mainline u-boot
>> and whatever I do, I cannot replicate this.
>>
>> I am at least CCing the Altera guys. Sorry I have no better suggestion
>> for you :(
> 
> I don't have any problems with mainline U-Boot and SPL on my DE0-NANO-BOARD:
> 
> U-Boot SPL 2016.03-00307-ge4fb863 (Mar 20 2016 - 10:37:13)
> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
> drivers/ddr/altera/sequencer.c: Calibration complete
> Trying to boot from MMC
> 
> 
> U-Boot 2016.03-00307-ge4fb863 (Mar 20 2016 - 10:37:13 -0500)
> 
> CPU:   Altera SoCFPGA Platform
> FPGA:  Altera Cyclone V, SE/A4 or SX/C4, version 0x0
> BOOT:  SD/MMC Internal Transceiver (3.0V)
>Watchdog enabled
> I2C:   ready
> DRAM:  1 GiB
> MMC:   dwmmc0@ff704000: 0
> In:serial
> Out:   serial
> Err:   serial
> Model: Terasic DE0-Nano(Atlas)
> Net:   eth0: ethernet@ff702000
> Hit any key to stop autoboot:  0
> =>
> 
> Sorry, I know that doesn't help. So let's walk through my workflow. I am
> not using any Altera tools when I build.
> 
> $make socfpga_de0_nano_soc_defconfig
> $make u-boot-with-spl.sfp
> $dd if=u-boot-with-spl.sfp of=/dev/sdb3
> 
> My gcc is: arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.7.3-12ubuntu1) 4.7.3
> 
> Has the board ever worked for you at all? Can you try this image:
> 
> https://rocketboards.org/foswiki/view/Documentation/AtlasSoCSdCardImage
> 
> Dinh

I just ported U-Boot to another customer board. I noticed QSPI has
problems and USB can be flaky. That's the standard cache issue we
have, disabling dcache fixed that.

I am starting to wonder whether we're hitting some corner case here.
Maybe we should eventually try and trace all the register reads and
writes generated by the DDR calibration code both in old and new SPL
and make a diff to see if something really did change.

Dinh, can you share the marking on the SoC and the DRAMs on your board?

Thanks!

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] Newbie SPL question for socfpga_sockit

[Marek Vasut]

On 03/18/2016 10:22 PM, George Broz wrote:
> On 18 March 2016 at 12:32, Marek Vasut  wrote:
>> On 03/18/2016 07:59 PM, George Broz wrote:
>>> On 16 March 2016 at 18:35, Marek Vasut  wrote:
 On 03/16/2016 05:17 PM, George Broz wrote:
> On 15 March 2016 at 18:29, George Broz  wrote:
>
>>
>> Hello again -
>>
>> So under the assumption my SoCKit h/w was broken, I bought a new board.
>> They are back ordered on SoCKit boards, so I got a DE0-Nano-SoC instead.
>>
>> I build the v2016.03 (release) version of u-boot-with-spl.sfp.
>>
>> I power-up the (brand new) board and get:
>>
>> U-Boot SPL 2016.03 (Mar 15 2016 - 14:52:42)
>> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
>> drivers/ddr/altera/sequencer.c: CALIBRATION FAILED
>> drivers/ddr/altera/sequencer.c: Calibration complete
>> SDRAM calibration failed.
>> ### ERROR ### Please RESET the board ###
>>
>> U-Boot SPL 2016.03 (Mar 15 2016 - 14:52:42)
>> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
>> drivers/ddr/altera/sequencer.c: CALIBRATION FAILED
>> drivers/ddr/altera/sequencer.c: Calibration complete
>> SDRAM calibration failed.
>> ### ERROR ### Please RESET the board ###
>>
>> U-Boot SPL 2016.03 (Mar 15 2016 - 14:52:42)
>> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
>> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
>> drivers/ddr/altera/sequencer.c: Calibration complete
>> Trying to boot from MMC
>>
>> U-Boot 2016.03 (Mar 15 2016 - 14:52:42 -0700)
>>
>> CPU:   Altera SoCFPGA Platform
>> FPGA:  Altera Cyclone V, SE/A4 or SX/C4, version 0x0
>> BOOT:  SD/MMC Internal Transceiver (3.0V)
>>Watchdog enabled
>> I2C:   ready
>> DRAM:  1 GiB
>> MMC:   dwmmc0@ff704000: 0
>> In:serial
>> Out:   serial
>> Err:   serial
>> Model: Terasic DE0-Nano(Atlas)
>> Net:
>> Error: ethernet@ff702000 address not set.
>> No ethernet found.
>> Hit any key to stop autoboot:  0
>> =>
>>
>> And this is a good case... usually it doesn't succeed after the fourth 
>> try
>> and I have to cycle power 4 or 5 times before I get lucky.
>>
>> If I do get lucky and then try to see a USB storage device, then I get:
>>
>> =>
>> => usb start
>> starting USB...
>> USB0:   Core Release: 2.93a
>> dwc_otg_core_host_init: Timeout!
>> dwc_otg_core_host_init: Timeout!
>> dwc_otg_core_host_init: Timeout!
>> dwc_otg_core_host_init: Timeout!
>> dwc_otg_core_host_init: Timeout!
>> dwc_otg_core_host_init: Timeout!
>> dwc_otg_core_host_init: Timeout!
>> dwc_otg_core_host_init: Timeout!
>> dwc_otg_core_host_init: Timeout!
>> dwc_otg_core_host_init: Timeout!
>> dwc_otg_core_host_init: Timeout!
>> dwc_otg_core_host_init: Timeout!
>> dwc_otg_core_host_init: Timeout!
>> dwc_otg_core_host_init: Timeout!
>> dwc_otg_core_host_init: Timeout!
>> scanning bus 0 for devices... 1 USB Device(s) found
>> =>
>>
>> (Every time)
>>
>> The version of u-boot SPL that ships with the board:
>> U-Boot SPL 2013.01.01 (Dec 29 2014 - 15:29:15)
>>
>> boots every time and has limited USB capability as
>> it can see some USB sticks, but not others.
>>
>>
>> Anyway - brand new board - same old symptoms.
>>
>> Is it perhaps a toolchain problem?? I'm using:
>>
>> Thread model: posix
>> gcc version 4.9.3 20141031 (prerelease) (Linaro GCC 4.9-2014.11)
>>
>> COLLECT_GCC=arm-poky-linux-gnueabi-gcc
>> COLLECT_LTO_WRAPPER=/opt/poky/1.7.1/sysroots/x86_64-pokysdk-linux/usr/libexec/arm-poky-linux-gnueabi/gcc/arm-poky-linux-gnueabi/4.9.3/lto-wrapper
>> < snip >
>>
>> Any advice greatly appreciated.
>>
>>
>> Regards,
>> --George Broz
>
> Rebuilt using the Altera EDS15.0 toolchain:
>
>   arm-altera-eabi-gcc --version
>   arm-altera-eabi-gcc (Sourcery CodeBench Lite 2014.11-13) 4.9.1
>   Copyright (C) 2014 Free Software Foundation, Inc.
>   This is free software; see the source for copying conditions.  There is 
> NO
>   warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR 
> PURPOSE.
>
>
> Get same result ... mostly failing calibration, non-working USB
>
> U-Boot SPL 2016.03 (Mar 16 2016 - 08:27:20)
> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> drivers/ddr/altera/sequencer.c: CALIBRATION FAILED
> drivers/ddr/altera/sequencer.c: Calibration complete
> SDRAM calibration failed.
> ### ERROR ### Please RESET the board ###
>
> U-Boot SPL 2016.03 (Mar 16 2016 - 08:27:20)
> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> 

[U-Boot] [PATCH 4/5] arm: lib: Sync libgcc 32b division/modulo operations

[Marek Vasut]

Sync the libgcc 32bit division and modulo operations with Linux 4.4.6 ,
commit 0d1912303e54ed1b2a371be0bba51c384dd57326 . The functions in these
four files are present in lib1funcs.S in Linux, so replace these files
with lib1funcs.S from Linux.

Since we do not support stack unwinding, instead of importing the whole
asm/unwind.h and all the baggage, this patch defines empty UNWIND() macro
in lib1funcs.S . Moreover, to make all of the functions available, define
CONFIG_AEABI , which is safe, because U-Boot is always compiled with ARM
EABI.

Signed-off-by: Marek Vasut 
Cc: Albert Aribaud 
Cc: Masahiro Yamada 
Cc: Simon Glass 
Cc: Tom Rini 
---
 arch/arm/lib/Makefile|   5 +-
 arch/arm/lib/divsi3.S| 143 ---
 arch/arm/lib/lib1funcs.S | 351 +++
 arch/arm/lib/modsi3.S|  99 -
 arch/arm/lib/udivsi3.S   |  95 -
 arch/arm/lib/umodsi3.S   |  90 
 6 files changed, 353 insertions(+), 430 deletions(-)
 delete mode 100644 arch/arm/lib/divsi3.S
 create mode 100644 arch/arm/lib/lib1funcs.S
 delete mode 100644 arch/arm/lib/modsi3.S
 delete mode 100644 arch/arm/lib/udivsi3.S
 delete mode 100644 arch/arm/lib/umodsi3.S

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 7cfe5ab..dce6ff9 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -5,9 +5,8 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o divsi3.o \
-   lshrdi3.o modsi3.o udivsi3.o umodsi3.o div0.o \
-   uldivmod.o
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o \
+   lib1funcs.o uldivmod.o div0.o
 
 ifdef CONFIG_CPU_V7M
 obj-y  += vectors_m.o crt0.o
diff --git a/arch/arm/lib/divsi3.S b/arch/arm/lib/divsi3.S
deleted file mode 100644
index c463c68..000
--- a/arch/arm/lib/divsi3.S
+++ /dev/null
@@ -1,143 +0,0 @@
-#include 
-
-.macro ARM_DIV_BODY dividend, divisor, result, curbit
-
-#if __LINUX_ARM_ARCH__ >= 5
-
-   clz \curbit, \divisor
-   clz \result, \dividend
-   sub \result, \curbit, \result
-   mov \curbit, #1
-   mov \divisor, \divisor, lsl \result
-   mov \curbit, \curbit, lsl \result
-   mov \result, #0
-
-#else
-
-   @ Initially shift the divisor left 3 bits if possible,
-   @ set curbit accordingly.  This allows for curbit to be located
-   @ at the left end of each 4 bit nibbles in the division loop
-   @ to save one loop in most cases.
-   tst \divisor, #0xe000
-   moveq   \divisor, \divisor, lsl #3
-   moveq   \curbit, #8
-   movne   \curbit, #1
-
-   @ Unless the divisor is very big, shift it up in multiples of
-   @ four bits, since this is the amount of unwinding in the main
-   @ division loop.  Continue shifting until the divisor is
-   @ larger than the dividend.
-1: cmp \divisor, #0x1000
-   cmplo   \divisor, \dividend
-   movlo   \divisor, \divisor, lsl #4
-   movlo   \curbit, \curbit, lsl #4
-   blo 1b
-
-   @ For very big divisors, we must shift it a bit at a time, or
-   @ we will be in danger of overflowing.
-1: cmp \divisor, #0x8000
-   cmplo   \divisor, \dividend
-   movlo   \divisor, \divisor, lsl #1
-   movlo   \curbit, \curbit, lsl #1
-   blo 1b
-
-   mov \result, #0
-
-#endif
-
-   @ Division loop
-1: cmp \dividend, \divisor
-   subhs   \dividend, \dividend, \divisor
-   orrhs   \result,   \result,   \curbit
-   cmp \dividend, \divisor,  lsr #1
-   subhs   \dividend, \dividend, \divisor, lsr #1
-   orrhs   \result,   \result,   \curbit,  lsr #1
-   cmp \dividend, \divisor,  lsr #2
-   subhs   \dividend, \dividend, \divisor, lsr #2
-   orrhs   \result,   \result,   \curbit,  lsr #2
-   cmp \dividend, \divisor,  lsr #3
-   subhs   \dividend, \dividend, \divisor, lsr #3
-   orrhs   \result,   \result,   \curbit,  lsr #3
-   cmp \dividend, #0   @ Early termination?
-   movnes  \curbit,   \curbit,  lsr #4 @ No, any more bits to do?
-   movne   \divisor,  \divisor, lsr #4
-   bne 1b
-
-.endm
-
-.macro ARM_DIV2_ORDER divisor, order
-
-#if __LINUX_ARM_ARCH__ >= 5
-
-   clz \order, \divisor
-   rsb \order, \order, #31
-
-#else
-
-   cmp \divisor, #(1 << 16)
-   movhs   \divisor, \divisor, lsr #16
-   movhs   \order, #16
-   movlo   \order, #0
-
-   cmp \divisor, #(1 << 8)
-   movhs   \divisor, \divisor, lsr #8
-   addhs   \order, \order, #8
-
-   cmp \divisor, #(1 << 4)
-   movhs   \divisor, \divisor, lsr #4
-   addhs   \order, \order, #4
-
-   cmp \divisor, #(1 << 2)
-   addhi   

[U-Boot] [PATCH 5/5] lib: Enable private libgcc by default

[Marek Vasut]

This patch decouples U-Boot binary from the toolchain on systems where
private libgcc is available. Instead of pulling in functions provided
by the libgcc from the toolchain, U-Boot will use it's own set of libgcc
functions. These functions are usually imported from Linux kernel, which
also uses it's own libgcc functions instead of the ones provided by the
toolchain.

This patch solves a rather common problem. The toolchain can usually
generate code for many variants of target architecture and often even
different endianness. The libgcc on the other hand is usually compiled
for one particular configuration and the functions provided by it may
or may not be suited for use in U-Boot. This can manifest in two ways,
either the U-Boot fails to compile altogether and linker will complain
or, in the much worse case, the resulting U-Boot will build, but will
misbehave in very subtle and hard to debug ways.

Signed-off-by: Marek Vasut 
Cc: Albert Aribaud 
Cc: Masahiro Yamada 
Cc: Simon Glass 
Cc: Tom Rini 
---
 lib/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/Kconfig b/lib/Kconfig
index 7a45336..2b911bc 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -14,6 +14,7 @@ config HAVE_PRIVATE_LIBGCC
 config USE_PRIVATE_LIBGCC
bool "Use private libgcc"
depends on HAVE_PRIVATE_LIBGCC
+   default y if HAVE_PRIVATE_LIBGCC
help
  This option allows you to use the built-in libgcc implementation
  of U-Boot instead of the one privided by the compiler.
-- 
2.7.0

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[U-Boot] [PATCH 1/5] arm: include: Import unified.h from Linux kernel

[Marek Vasut]

Import unified.h from Linux kernel 4.4.6 , commit
0d1912303e54ed1b2a371be0bba51c384dd57326 . This header file contains
macros used in libgcc functions in Linux kernel on ARM and will be
needed for the libgcc sync.

Since unified.h defines the W(instr) macro, we must drop this from
the macro from memcpy.S , otherwise this triggers a warning about
symbol redefinition. In order to keep the changes to unified.h to
the minimum, tweak arch/arm/lib/Makefile such that it defines new
CONFIG_THUMB2_KERNEL macro, which is already checked by unified.h,
only if Thumb build is enabled, but the target does not support
Thumb2 . This way we can remove ad-hoc -DMEMSET_NO_THUMB_BUILD and
-DMEMCPY_NO_THUMB_BUILD and we do not change the logic.

Signed-off-by: Marek Vasut 
Cc: Albert Aribaud 
Cc: Masahiro Yamada 
Cc: Simon Glass 
Cc: Tom Rini 
---
 arch/arm/include/asm/assembler.h |   1 +
 arch/arm/include/asm/unified.h   | 140 +++
 arch/arm/lib/Makefile|   6 +-
 arch/arm/lib/memcpy.S|   6 --
 4 files changed, 144 insertions(+), 9 deletions(-)
 create mode 100644 arch/arm/include/asm/unified.h

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 11b80fb..ae1e42f 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -15,6 +15,7 @@
  */
 
 #include 
+#include 
 
 /*
  * Endian independent macros for shifting bytes within registers.
diff --git a/arch/arm/include/asm/unified.h b/arch/arm/include/asm/unified.h
new file mode 100644
index 000..a91ae49
--- /dev/null
+++ b/arch/arm/include/asm/unified.h
@@ -0,0 +1,140 @@
+/*
+ * include/asm-arm/unified.h - Unified Assembler Syntax helper macros
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_UNIFIED_H
+#define __ASM_UNIFIED_H
+
+#if defined(__ASSEMBLY__) && defined(CONFIG_ARM_ASM_UNIFIED)
+   .syntax unified
+#endif
+
+#ifdef CONFIG_CPU_V7M
+#define AR_CLASS(x...)
+#define M_CLASS(x...)  x
+#else
+#define AR_CLASS(x...) x
+#define M_CLASS(x...)
+#endif
+
+#ifdef CONFIG_THUMB2_KERNEL
+
+#if __GNUC__ < 4
+#error Thumb-2 kernel requires gcc >= 4
+#endif
+
+/* The CPSR bit describing the instruction set (Thumb) */
+#define PSR_ISETSTATE  PSR_T_BIT
+
+#define ARM(x...)
+#define THUMB(x...)x
+#ifdef __ASSEMBLY__
+#define W(instr)   instr.w
+#else
+#define WASM(instr)#instr ".w"
+#endif
+
+#else  /* !CONFIG_THUMB2_KERNEL */
+
+/* The CPSR bit describing the instruction set (ARM) */
+#define PSR_ISETSTATE  0
+
+#define ARM(x...)  x
+#define THUMB(x...)
+#ifdef __ASSEMBLY__
+#define W(instr)   instr
+#else
+#define WASM(instr)#instr
+#endif
+
+#endif /* CONFIG_THUMB2_KERNEL */
+
+#ifndef CONFIG_ARM_ASM_UNIFIED
+
+/*
+ * If the unified assembly syntax isn't used (in ARM mode), these
+ * macros expand to an empty string
+ */
+#ifdef __ASSEMBLY__
+   .macro  it, cond
+   .endm
+   .macro  itt, cond
+   .endm
+   .macro  ite, cond
+   .endm
+   .macro  ittt, cond
+   .endm
+   .macro  itte, cond
+   .endm
+   .macro  itet, cond
+   .endm
+   .macro  itee, cond
+   .endm
+   .macro  i, cond
+   .endm
+   .macro  ittte, cond
+   .endm
+   .macro  ittet, cond
+   .endm
+   .macro  ittee, cond
+   .endm
+   .macro  itett, cond
+   .endm
+   .macro  itete, cond
+   .endm
+   .macro  iteet, cond
+   .endm
+   .macro  iteee, cond
+   .endm
+#else  /* !__ASSEMBLY__ */
+__asm__(
+"  .macro  it, cond\n"
+"  .endm\n"
+"  .macro  itt, cond\n"
+"  .endm\n"
+"  .macro  ite, cond\n"
+"  .endm\n"
+"  .macro  ittt, cond\n"
+"  .endm\n"
+"  .macro  itte, cond\n"
+"  .endm\n"
+"  .macro  itet, cond\n"
+"  .endm\n"
+"  .macro  itee, cond\n"
+"  .endm\n"
+"  .macro  i, cond\n"
+"  .endm\n"
+"  .macro  ittte, cond\n"
+"  .endm\n"
+"  .macro  ittet, cond\n"
+"  .endm\n"
+"  .macro  ittee, cond\n"
+"  .endm\n"
+"  .macro  itett, cond\n"
+"  .endm\n"
+"  .macro  itete, cond\n"
+"  .endm\n"
+"  .macro  iteet, cond\n"
+"  .endm\n"
+"  .macro  iteee, 

[U-Boot] [PATCH 2/5] arm: lib: Drop underscore from private libgcc filenames

[Marek Vasut]

Drop the underscore from the filenames of files implementing libgcc
routines. There is no functional change. This change is done to make
sync with Linux kernel easier.

Signed-off-by: Marek Vasut 
Cc: Albert Aribaud 
Cc: Masahiro Yamada 
Cc: Simon Glass 
Cc: Tom Rini 
---
 arch/arm/lib/Makefile| 6 +++---
 arch/arm/lib/{_ashldi3.S => ashldi3.S}   | 0
 arch/arm/lib/{_ashrdi3.S => ashrdi3.S}   | 0
 arch/arm/lib/{_divsi3.S => divsi3.S} | 0
 arch/arm/lib/{_lshrdi3.S => lshrdi3.S}   | 0
 arch/arm/lib/{_modsi3.S => modsi3.S} | 0
 arch/arm/lib/{_udivsi3.S => udivsi3.S}   | 0
 arch/arm/lib/{_uldivmod.S => uldivmod.S} | 0
 arch/arm/lib/{_umodsi3.S => umodsi3.S}   | 0
 9 files changed, 3 insertions(+), 3 deletions(-)
 rename arch/arm/lib/{_ashldi3.S => ashldi3.S} (100%)
 rename arch/arm/lib/{_ashrdi3.S => ashrdi3.S} (100%)
 rename arch/arm/lib/{_divsi3.S => divsi3.S} (100%)
 rename arch/arm/lib/{_lshrdi3.S => lshrdi3.S} (100%)
 rename arch/arm/lib/{_modsi3.S => modsi3.S} (100%)
 rename arch/arm/lib/{_udivsi3.S => udivsi3.S} (100%)
 rename arch/arm/lib/{_uldivmod.S => uldivmod.S} (100%)
 rename arch/arm/lib/{_umodsi3.S => umodsi3.S} (100%)

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index a930744..7cfe5ab 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -5,9 +5,9 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \
-   _lshrdi3.o _modsi3.o _udivsi3.o _umodsi3.o div0.o \
-   _uldivmod.o
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o divsi3.o \
+   lshrdi3.o modsi3.o udivsi3.o umodsi3.o div0.o \
+   uldivmod.o
 
 ifdef CONFIG_CPU_V7M
 obj-y  += vectors_m.o crt0.o
diff --git a/arch/arm/lib/_ashldi3.S b/arch/arm/lib/ashldi3.S
similarity index 100%
rename from arch/arm/lib/_ashldi3.S
rename to arch/arm/lib/ashldi3.S
diff --git a/arch/arm/lib/_ashrdi3.S b/arch/arm/lib/ashrdi3.S
similarity index 100%
rename from arch/arm/lib/_ashrdi3.S
rename to arch/arm/lib/ashrdi3.S
diff --git a/arch/arm/lib/_divsi3.S b/arch/arm/lib/divsi3.S
similarity index 100%
rename from arch/arm/lib/_divsi3.S
rename to arch/arm/lib/divsi3.S
diff --git a/arch/arm/lib/_lshrdi3.S b/arch/arm/lib/lshrdi3.S
similarity index 100%
rename from arch/arm/lib/_lshrdi3.S
rename to arch/arm/lib/lshrdi3.S
diff --git a/arch/arm/lib/_modsi3.S b/arch/arm/lib/modsi3.S
similarity index 100%
rename from arch/arm/lib/_modsi3.S
rename to arch/arm/lib/modsi3.S
diff --git a/arch/arm/lib/_udivsi3.S b/arch/arm/lib/udivsi3.S
similarity index 100%
rename from arch/arm/lib/_udivsi3.S
rename to arch/arm/lib/udivsi3.S
diff --git a/arch/arm/lib/_uldivmod.S b/arch/arm/lib/uldivmod.S
similarity index 100%
rename from arch/arm/lib/_uldivmod.S
rename to arch/arm/lib/uldivmod.S
diff --git a/arch/arm/lib/_umodsi3.S b/arch/arm/lib/umodsi3.S
similarity index 100%
rename from arch/arm/lib/_umodsi3.S
rename to arch/arm/lib/umodsi3.S
-- 
2.7.0

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[U-Boot] [PATCH 3/5] arm: lib: Sync libgcc shift operations

[Marek Vasut]

Sync the libgcc shift operations with Linux kernel 4.4.6 , commit
0d1912303e54ed1b2a371be0bba51c384dd57326 . Syncing these three
files is easy, as there is almost no change in them, except the
addition of Thumb support.

Signed-off-by: Marek Vasut 
Cc: Albert Aribaud 
Cc: Masahiro Yamada 
Cc: Simon Glass 
Cc: Tom Rini 
---
 arch/arm/lib/ashldi3.S | 12 
 arch/arm/lib/ashrdi3.S | 12 
 arch/arm/lib/lshrdi3.S | 12 
 3 files changed, 24 insertions(+), 12 deletions(-)

diff --git a/arch/arm/lib/ashldi3.S b/arch/arm/lib/ashldi3.S
index 9c34c21..a4f5ebb 100644
--- a/arch/arm/lib/ashldi3.S
+++ b/arch/arm/lib/ashldi3.S
@@ -5,6 +5,7 @@
  */
 
 #include 
+#include 
 
 #ifdef __ARMEB__
 #define al r1
@@ -14,15 +15,18 @@
 #define ah r1
 #endif
 
-.globl __ashldi3
-__ashldi3:
+ENTRY(__ashldi3)
 ENTRY(__aeabi_llsl)
 
subsr3, r2, #32
rsb ip, r2, #32
movmi   ah, ah, lsl r2
movpl   ah, al, lsl r3
-   orrmi   ah, ah, al, lsr ip
+ ARM(  orrmi   ah, ah, al, lsr ip  )
+ THUMB(lsrmi   r3, al, ip  )
+ THUMB(orrmi   ah, ah, r3  )
mov al, al, lsl r2
-   mov pc, lr
+   ret lr
+
+ENDPROC(__ashldi3)
 ENDPROC(__aeabi_llsl)
diff --git a/arch/arm/lib/ashrdi3.S b/arch/arm/lib/ashrdi3.S
index c74fd64..c6e1ed3 100644
--- a/arch/arm/lib/ashrdi3.S
+++ b/arch/arm/lib/ashrdi3.S
@@ -5,6 +5,7 @@
  */
 
 #include 
+#include 
 
 #ifdef __ARMEB__
 #define al r1
@@ -14,15 +15,18 @@
 #define ah r1
 #endif
 
-.globl __ashrdi3
-__ashrdi3:
+ENTRY(__ashrdi3)
 ENTRY(__aeabi_lasr)
 
subsr3, r2, #32
rsb ip, r2, #32
movmi   al, al, lsr r2
movpl   al, ah, asr r3
-   orrmi   al, al, ah, lsl ip
+ ARM(  orrmi   al, al, ah, lsl ip  )
+ THUMB(lslmi   r3, ah, ip  )
+ THUMB(orrmi   al, al, r3  )
mov ah, ah, asr r2
-   mov pc, lr
+   ret lr
+
+ENDPROC(__ashrdi3)
 ENDPROC(__aeabi_lasr)
diff --git a/arch/arm/lib/lshrdi3.S b/arch/arm/lib/lshrdi3.S
index 1f9b916..9c51141 100644
--- a/arch/arm/lib/lshrdi3.S
+++ b/arch/arm/lib/lshrdi3.S
@@ -5,6 +5,7 @@
  */
 
 #include 
+#include 
 
 #ifdef __ARMEB__
 #define al r1
@@ -14,15 +15,18 @@
 #define ah r1
 #endif
 
-.globl __lshrdi3
-__lshrdi3:
+ENTRY(__lshrdi3)
 ENTRY(__aeabi_llsr)
 
subsr3, r2, #32
rsb ip, r2, #32
movmi   al, al, lsr r2
movpl   al, ah, lsr r3
-   orrmi   al, al, ah, lsl ip
+ ARM(  orrmi   al, al, ah, lsl ip  )
+ THUMB(lslmi   r3, ah, ip  )
+ THUMB(orrmi   al, al, r3  )
mov ah, ah, lsr r2
-   mov pc, lr
+   ret lr
+
+ENDPROC(__lshrdi3)
 ENDPROC(__aeabi_llsr)
-- 
2.7.0

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[U-Boot] [PATCH 5/6] lpc32xx: work_92105: Rework Makefile

[Tom Rini]

When we switch to including all linker lists in U-Boot it is important
to not include commands as that may lead to link errors due to other
things we have already discarded.  In this case change things so that we
only build the right objects for SPL or non-SPL

Cc: Albert ARIBAUD (3ADEV) 
Signed-off-by: Tom Rini 
---
 board/work-microwave/work_92105/Makefile |8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/board/work-microwave/work_92105/Makefile 
b/board/work-microwave/work_92105/Makefile
index ba31c8e..e26c673 100644
--- a/board/work-microwave/work_92105/Makefile
+++ b/board/work-microwave/work_92105/Makefile
@@ -5,6 +5,8 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  := work_92105.o work_92105_display.o
-
-obj-$(CONFIG_SPL_BUILD) += work_92105_spl.o
+ifdef CONFIG_SPL_BUILD
+obj-y  += work_92105_spl.o
+else
+obj-y  += work_92105.o work_92105_display.o
+endif
-- 
1.7.9.5

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[U-Boot] Linux hangs due to commit v2015.10-15-g02cc27c on loading i2c-mv64xx

[Michael Haas]

Hello all,

I'm running Debian Jessie with Linux 4.3.0-0.bpo.1-armmp-lpae on my
a20-olinuxino-lime2.
I have noticed that my board hangs with my recent u-boot versions when I
load the i2c module.

git-bisect narrowed the problem down to the following commit:

02cc27c74f9b884b538bcd1b93342a4c05b5d608 is the first bad commit
commit 02cc27c74f9b884b538bcd1b93342a4c05b5d608
Author: Hans de Goede 
Date:   Sat Oct 3 15:29:24 2015 +0200

sunxi: power: Change axp209 LDO3 and LDO4 default to disabled
   
LDO3 and LDO4 are normally either unused, or used to power csi
attached camera sensors, and as such do not need to be enabled at
boot time.
   
Signed-off-by: Hans de Goede 
Acked-by: Ian Campbell 

:04 04 9ff2e54e613a4386473cdf66c3bc5dc830a31bc7
d5330c13ef2c86643499f476b7042748969fd523 MT>drivers


The axp209 is attached to the i2c bus, so that is likely the real
culprit. In my setup, the axp209 drivers are loaded before I insert
i2c-mv64xxx.

What would be the best course of action here?

* Revert the commit
* Enable LDO3 and LDO4 for the a20-olinuxino-lime2 only?
* Fix linux

Best,

Michael

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Re: [U-Boot] Newbie SPL question for socfpga_sockit

[Dinh Nguyen]

On 03/16/2016 08:35 PM, Marek Vasut wrote:
>>
>> Does this work for anybody else?
>> Is it in anyone's experience that these (cheaper) Terasic
>> eval boards are generally out of spec?
>>
>> Is there a way to relax the calibration parameters? the USB parameters?
>>
>> Would it help if I posted debug output?
> 
> Sorry for the late reply, I am horribly overloaded now. I asked someone
> in #u-boot who has the DE0-NANO-SOC board to test latest u-boot/master
> on it and it apparently worked for him. I should get some more feedback
> in the morning [ see http://pastebin.com/CM1QJGnh ] .
> 
> Still, this is getting real creepy. You are the second person who is
> complaining about misbehavior of terasic boards with mainline u-boot
> and whatever I do, I cannot replicate this.
> 
> I am at least CCing the Altera guys. Sorry I have no better suggestion
> for you :(

I don't have any problems with mainline U-Boot and SPL on my DE0-NANO-BOARD:

U-Boot SPL 2016.03-00307-ge4fb863 (Mar 20 2016 - 10:37:13)
drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
drivers/ddr/altera/sequencer.c: Calibration complete
Trying to boot from MMC


U-Boot 2016.03-00307-ge4fb863 (Mar 20 2016 - 10:37:13 -0500)

CPU:   Altera SoCFPGA Platform
FPGA:  Altera Cyclone V, SE/A4 or SX/C4, version 0x0
BOOT:  SD/MMC Internal Transceiver (3.0V)
   Watchdog enabled
I2C:   ready
DRAM:  1 GiB
MMC:   dwmmc0@ff704000: 0
In:serial
Out:   serial
Err:   serial
Model: Terasic DE0-Nano(Atlas)
Net:   eth0: ethernet@ff702000
Hit any key to stop autoboot:  0
=>

Sorry, I know that doesn't help. So let's walk through my workflow. I am
not using any Altera tools when I build.

$make socfpga_de0_nano_soc_defconfig
$make u-boot-with-spl.sfp
$dd if=u-boot-with-spl.sfp of=/dev/sdb3

My gcc is: arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.7.3-12ubuntu1) 4.7.3

Has the board ever worked for you at all? Can you try this image:

https://rocketboards.org/foswiki/view/Documentation/AtlasSoCSdCardImage

Dinh


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Re: [U-Boot] [PATCH] Add CONFIG_GMAC_TX_DELAY=4 for OlinuXino Lime2

[Michael Haas]

On 03/20/2016 02:45 PM, Hans de Goede wrote:
> Hi,
>
> On 19-03-16 14:40, Michael Haas wrote:
>> On 03/19/2016 10:32 AM, Hans de Goede wrote:
>>> Hi,
>>>
>>> On 19-03-16 09:39, François-David Collin wrote:
 Hi,

 As I’m banging my head on this too, please allow me to provide some
 details
 I got two stable situations :
 The Lime2 is connected directly to the Gbit interface of my laptop,
 speed are OK:
>>>
>>> Michael Haas' work to debug this by looking at the phy registers
>>> seems to be the most promising so-far, the clk reg and axp209
>>> registers all seem to be identical between good and bad setups.
>>>
>>> Can you try to:
>>>
>>> 1) Stop the boot in u-boot (press a key on the serial console)
>>> 2) Bring up the network, e.g. type "dhcp" then ctrl+c when it tries
>>> to tftp
>>> 3) Do: "mii read 1 0x11" in u-boot and record the output ?
>>>
>>> Regards,
>>>
>>> Hans
>>
>> Hi all,
>>
>> i have diffed and cross-compared logs of several working and broken tftp
>> downloads. The most significant
>> difference between working and broken was registers 0xa, 0x1c and 0x2a
>> in the first MII page.
>>
>> These registers started making sense when I looked at the datasheet for
>> the RTL8211CL. Previously, I was looking at the RTL8211E.
>>
>> 0xA was set to 7800 for working runs and 3800 for broken runs. The
>> difference is bit 14 in the GBSR: 'MASTER/SLAVE Configuration
>> Resolution'. In the broken runs, the autonegotation configured the
>> OlinuXino to 'slave'. I have whipped up a quick patch which disable the
>> master/slave part of the autonegotiation and force master mode.
>>
>> The patch itself is quite terrible as it's forcing the master mode bits
>> for every phy, not just for the RTL8211CL. It's good enough for testing,
>> however, and I seem to be getting consistent download speeds. There are
>> occasional hangs when booting the downloaded kernel, but that is
>> probably a different issue.
>>
>> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
>> index 51b5746..484b2be 100644
>> --- a/drivers/net/phy/phy.c
>> +++ b/drivers/net/phy/phy.c
>> @@ -170,6 +170,7 @@ int genphy_restart_aneg(struct phy_device *phydev)
>>   int genphy_config_aneg(struct phy_device *phydev)
>>   {
>>  int result;
>> +   phy_write(phydev, MDIO_DEVAD_NONE, 0x09, 0x1A00);
>>
>>  if (AUTONEG_ENABLE != phydev->autoneg)
>>  return genphy_setup_forced(phydev);
>>
>> Please test this change and let me know. If it's successful, I will
>> submit a proper version.
>
> Good catch, I wonder why we need this. I believe that the proper version
> should probably be wrapped in a #ifdef CONFIG_REALTEK_PHY_FORCE_MASTER
> and then add a Kconfig option for this (and enable it in the lime2
> defconfig), forcing this on all rtl8211cl phy-s seems wrong, unless
> someone can dig up an errata from realtek which said we should.

I was going to add that in realtek.c, not in phy.c - as soon as I figure
out which section there is applicable. I have started a new thread
asking about that.
>
> Are any other sunxi boards impacted by the same problem that you know ?
>

No, I don't know of any other boards, but I have not looked very hard :)

Michael
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Re: [U-Boot] ext4 and caching

[Eric Nelson]

Thanks Ioan,

On 03/19/2016 08:42 AM, Ioan Nicu wrote:
> Hi Eric,
> 
> On Wed, Mar 16, 2016 at 11:42:55AM -0700, EXT Eric Nelson wrote:
>>  Hi all,
>>
>> I've been seeing the same sort of issues repoted by Ionut
>> and as addressed by this patch:
>>  http://lists.denx.de/pipermail/u-boot/2014-January/171459.html
>>
>> That patch was added in commit fc0fc50 and reverted in commit 715b56f.
>>
>> It no longer applies cleanly, and when I tried to resurrect it,
>> I saw errors traversing directories and perhaps something went
>> wrong with my merge.
>>
>> Ionut, do you have a current version of this patch?
>>
> 
> We reverted that patch because it was breaking ext4 write support. I initially
> developed the patch on top of an older u-boot which didn't have write supoort
> at all.
> 
> I have tried to refactor my patch to work with both read/write, but I gave up
> when I saw that the ext4 write code relied on the old behavior of
> read_allocated_block/ext4fs_get_extent_block. I could have worked around that,
> but then the whole thing would have looked like hack, so I didn't like it ...
> 
> If you are interested in a current version of this patch, I could try to
> revive it. But it has the limitation I mentioned above, so I guess you could
> use it just for some ext4 read performance measurement test.
> 

I do want to get rid of the performance problem, but as I suggested
by my patch set, I think that a more general-purpose cache is a better
approach.

Regards,


Eric

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Re: [U-Boot] [PATCH 00/18] sf: fix support of QSPI memories and controllers

[Stefan Roese]

Hi All,

please excuse the late reply to this thread. But I'm very interested
in QSPI, as one of my customers uses Micron QSPI NOR and really wants
to take full advantage of the device (quad access) to speed up the
overall boot process. This is on SoCFPGA btw.

Please allow me a few comments below.

On 16.03.2016 15:14, Jagan Teki wrote:

On Wednesday 16 March 2016 07:00 PM, Cyrille Pitchen wrote:

Le 15/03/2016 19:21, Jagan Teki a écrit :

On Tuesday 15 March 2016 11:42 PM, Cyrille Pitchen wrote:

Hi all,

This series of patches fixes and extend the support of QSPI memories
in the SPI flash framework. The updates are split into many parts to
make it easier to understand and review but they should be considered
as a whole.

This was tested on a Atmel sama5d2 xplained board with a Micron
n25q128a
memory.

Best regards,

Cyrille

Cyrille Pitchen (18):
Revert "sf: Fix quad bit set for micron devices"
sf: call spi_claim_bus() and spi_release_bus() only once per read,
  write or erase
sf: replace spi_flash_read_common() calls by spi_flash_cmd_read()
sf: remove spi_flash_write_common()
sf: export spi_flash_wait_ready() function
sf: share erase generic algorithm
sf: share write generic algorithm
sf: share read generic algorithm
sf: add hooks to handle register read and write operations
sf: move support of SST flash into generic spi_flash_write_alg()
sf: fix selection of supported READ commands for QSPI memories
sf: fix detection of QSPI memories when they boot in Quad or
Dual mode
sf: add helper function to set the number of dummy bytes
sf: add 4byte address opcodes
sf: prepare next fixes to support of QSPI memories by manufacturer
sf: fix support of Micron memories
ARM: at91: clock: add function to get QSPI clocks
sf: add driver for Atmel QSPI controller


Appreciate for the work, we're working on spi-nor framework[1]
planning to push in couple of weeks. Will let you know once it merged
so that you can add your changes on top of that.

[1]
http://git.denx.de/?p=u-boot/u-boot-spi.git;a=shortlog;h=refs/heads/spi-nor-next




Hi Jagan,

I've started to have a look on your branch. I hope it's not to late
for few
comments:

Globally I see the new code attend to match the spi-nor framework from
Linux.
OK that's fine but please note the current spi-nor framework in Linux has
incomplete and sometime not working support of QSPI memories.

First, after a discussion with Brian and Bean on linux-mtd [1], Bean's
commit
to add support to Micron QSPI memories was reverted since it didn't
work alone.
In his reply, Brian agreed the code was not tested and should not have
been
merged.

This highlights a more general issue: currently, there is no mean for the
spi-nor framework to notify the SPI controller driver about a SPI
protocol
change at the QSPI memory side. This applies to Micron memories when
they enter
their Quad I/O mode. If so, ALL commands, even JEDEC Read ID, Read Status
Register, ..., MUST use the SPI 4-4-4 protocol. Commands sent using
SPI 1-x-y
protocols are no longer decoded properly.
This also applies to Macronix and Winbond memories if they enter their
QPI
mode, which is the equivalent of Micron Quad I/O mode.
This is why I've suggested to add 4 new fields in the struct spi_nor:
- .reg_proto: the SPI protocol to be used by .read_reg() and .write_reg()
   hooks.
- .read_proto: the SPI protocol to be used by the .read() hooks, maybe
by the
   .read_mmap() also.
- .write_proto: the SPI protocol to be used by the .write() hooks
- .erase_proto: the SPI protocol to be used by the .erase() hooks.

(Q)SPI controller drivers cannot guess the protocol to be used from
the command
op code. Indeed, taking the Micron case as un example, the very same
0xeb op
code may be used with the SPI 1-4-4 protocol (Micron Extended SPI
mode) or
with the SPI 4-4-4 protocol (Micron Quad I/O mode).


Also just some words about the naming of SPI x-y-z protocols:
- x refers to the number of I/O lines used to send the op code byte
- y is the number of I/O lines used to send the address, mode/dummy
cycles
   (if these cycles exist for the command op code)
- z is the number of I/O lines used to send/receive data (if needed)

So the SNOR_OP_READ_1_1_2_IO macro for the Fast Read Dual I/O command (as
opposed to the macro SNOR_OP_READ_1_1_2 macro for the Fast Read Dual
Output
command) doesn't make sense: it should be named SNOR_OP_READ_1_2_2.


Then about the value used for the dummy cycles, it's not always true
that we
don't care about initializing them. Depending on the configuration of the
memory, some special dummy cycles, sometime called mode cycles, are
used to
during Fast Read operations to make the memory enter/leaver its
Continuous Read
mode. Once is Continuous Read mode, the op code byte is no longer
sent, it is
implicit and the command actually starts from the address cycles. This
mode
is mostly used for XIP applications hence is not relevant for mtd usage.

[U-Boot] [PATCH] test/dm/core.c: Make pre-reloc test use pre-reloc struct

[Tom Rini]

LLVM 3.5 noted:
test/dm/core.c:41:35: warning: unused variable 'test_pdata_pre_reloc' 
[-Wunused-const-variable]
static const struct dm_test_pdata test_pdata_pre_reloc = {

And the correct fix here is that the driver_info_pre_reloc test should
use the test_pdata_pre_reloc not test_pdata_manual variable

Cc: Simon Glass 
Signed-off-by: Tom Rini 
---
 test/dm/core.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/test/dm/core.c b/test/dm/core.c
index 9fbc70d..70bf4d0 100644
--- a/test/dm/core.c
+++ b/test/dm/core.c
@@ -64,7 +64,7 @@ static struct driver_info driver_info_manual = {
 
 static struct driver_info driver_info_pre_reloc = {
.name = "test_pre_reloc_drv",
-   .platdata = _pdata_manual,
+   .platdata = _pdata_pre_reloc,
 };
 
 void dm_leak_check_start(struct unit_test_state *uts)
-- 
1.7.9.5

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Re: [U-Boot] [linux-sunxi] Re: [PATCH] sunxi: Add support for Cubietruck Plus

[Hans de Goede]

hI,

On 19-03-16 23:43, Dennis Gilmore wrote:

Hans,

What is the status of this patch?


I added this to my sunxi-wip tree (including a fix for the build error)
a couple of days ago. I will send a pull-req for various u-boot sunxi
patch soonish and then it will hit mainline.

Regards,

Hans




Dennis

On Wednesday, January 27, 2016 4:34:44 PM CDT Chen-Yu Tsai wrote:

Cubietruck Plus is a A83T/H8 based development board. The board has
standard DDR3 SDRAM, AXP818 PMIC/codec, SD/MMC, eMMC, USB 2.0 host
via HSIC USB Hub, USB OTG, SATA via USB bridge, gigabit ethernet,
WiFi, headphone out / mic in, and various GPIO headers.

The board also has an EEPROM on i2c0 which holds the MAC address.

DLDO3 and DLDO4 provide power to the EMAC pins and PHY. Pin PA20
is connected to the reset control of the PHY. EMAC is not actually
supported yet.

The DTS is the same as the one already in the kernel.

Signed-off-by: Chen-Yu Tsai 
---
  arch/arm/dts/Makefile   |  1 +
  arch/arm/dts/sun8i-a83t-cubietruck-plus.dts | 65
+ configs/Cubietruck_plus_defconfig   |
18 
  3 files changed, 84 insertions(+)
  create mode 100644 arch/arm/dts/sun8i-a83t-cubietruck-plus.dts
  create mode 100644 configs/Cubietruck_plus_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1c7d359..e338db5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -184,6 +184,7 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
sun8i-a33-sinlinx-sina33.dtb
  dtb-$(CONFIG_MACH_SUN8I_A83T) += \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
+   sun8i-a83t-cubietruck-plus.dtb \
sun8i-a83t-sinovoip-bpi-m3.dtb
  dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-orangepi-pc.dtb \
diff --git a/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts
b/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts new file mode 100644
index 000..88b1e09
--- /dev/null
+++ b/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2015 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a83t.dtsi"
+
+/ {
+   model = "Cubietech Cubietruck Plus";
+   compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_b>;
+   status = "okay";
+};
diff --git a/configs/Cubietruck_plus_defconfig
b/configs/Cubietruck_plus_defconfig new file mode 100644
index 000..bb0b336
--- /dev/null
+++ b/configs/Cubietruck_plus_defconfig
@@ -0,0 +1,18 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_A83T=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=15355
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
+CONFIG_I2C0_ENABLE=y
+CONFIG_AXP_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y

Re: [U-Boot] [PATCH] Add CONFIG_GMAC_TX_DELAY=4 for OlinuXino Lime2

[Hans de Goede]

Hi,

On 19-03-16 14:40, Michael Haas wrote:

On 03/19/2016 10:32 AM, Hans de Goede wrote:

Hi,

On 19-03-16 09:39, François-David Collin wrote:

Hi,

As I’m banging my head on this too, please allow me to provide some
details
I got two stable situations :
The Lime2 is connected directly to the Gbit interface of my laptop,
speed are OK:


Michael Haas' work to debug this by looking at the phy registers
seems to be the most promising so-far, the clk reg and axp209
registers all seem to be identical between good and bad setups.

Can you try to:

1) Stop the boot in u-boot (press a key on the serial console)
2) Bring up the network, e.g. type "dhcp" then ctrl+c when it tries
to tftp
3) Do: "mii read 1 0x11" in u-boot and record the output ?

Regards,

Hans


Hi all,

i have diffed and cross-compared logs of several working and broken tftp
downloads. The most significant
difference between working and broken was registers 0xa, 0x1c and 0x2a
in the first MII page.

These registers started making sense when I looked at the datasheet for
the RTL8211CL. Previously, I was looking at the RTL8211E.

0xA was set to 7800 for working runs and 3800 for broken runs. The
difference is bit 14 in the GBSR: 'MASTER/SLAVE Configuration
Resolution'. In the broken runs, the autonegotation configured the
OlinuXino to 'slave'. I have whipped up a quick patch which disable the
master/slave part of the autonegotiation and force master mode.

The patch itself is quite terrible as it's forcing the master mode bits
for every phy, not just for the RTL8211CL. It's good enough for testing,
however, and I seem to be getting consistent download speeds. There are
occasional hangs when booting the downloaded kernel, but that is
probably a different issue.

diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 51b5746..484b2be 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -170,6 +170,7 @@ int genphy_restart_aneg(struct phy_device *phydev)
  int genphy_config_aneg(struct phy_device *phydev)
  {
 int result;
+   phy_write(phydev, MDIO_DEVAD_NONE, 0x09, 0x1A00);

 if (AUTONEG_ENABLE != phydev->autoneg)
 return genphy_setup_forced(phydev);

Please test this change and let me know. If it's successful, I will
submit a proper version.


Good catch, I wonder why we need this. I believe that the proper version
should probably be wrapped in a #ifdef CONFIG_REALTEK_PHY_FORCE_MASTER
and then add a Kconfig option for this (and enable it in the lime2
defconfig), forcing this on all rtl8211cl phy-s seems wrong, unless
someone can dig up an errata from realtek which said we should.

Are any other sunxi boards impacted by the same problem that you know ?

Regards,

Hans
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Re: [U-Boot] Please pull u-boot-dm

[Tom Rini]

On Sat, Mar 19, 2016 at 06:35:24PM -0600, Simon Glass wrote:

> Hi Tom,
> 
> Here is the rest of the block device stuff as well as a few buildman
> improvements and a few other things.
> 
> The following changes since commit f23baa572f96e1e13d7f1a3c8addb61b5d0dbd29:
> 
>   cmd_dhry.c: Use lldiv for vax_mips calculation as well (2016-03-17
> 10:14:25 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-dm.git
> 
> for you to fetch changes up to e4fb863f6dec0002069d57422ebe3ce3af69a273:
> 
>   dm: blk: Add tests for block devices (2016-03-17 21:27:39 -0600)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH] spl: Print from which mmc slot spl is trying to boot

[Tom Rini]

On Sun, Mar 20, 2016 at 02:19:19PM +0100, Hans de Goede wrote:

> On some sunxi boards (and presumably also non sunxi boards) u-boot can
> be either loaded from a sdcard in a micro-sd slot, or from eMMC.
> 
> Print which MMC spl tries to boot from, to help debugging.
> 
> Signed-off-by: Hans de Goede 

Reviewed-by: Tom Rini 

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[U-Boot] [PATCH] cmd: spi: check return value of strdup

[Peng Fan]

Check return value of strdup.

Signed-off-by: Peng Fan 
Cc: Przemyslaw Marczak 
Cc: Bin Meng 
Cc: Heiko Schocher 
Cc: Simon Glass 
Cc: Stefan Roese 
Cc: Tom Rini 
---
 cmd/spi.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/cmd/spi.c b/cmd/spi.c
index 64c3ffc..f16ef9a 100644
--- a/cmd/spi.c
+++ b/cmd/spi.c
@@ -51,6 +51,8 @@ static int do_spi_xfer(int bus, int cs)
 
snprintf(name, sizeof(name), "generic_%d:%d", bus, cs);
str = strdup(name);
+   if (!str)
+   return -ENOMEM;
ret = spi_get_bus_and_cs(bus, cs, 100, mode, "spi_generic_drv",
 str, , );
if (ret)
-- 
2.6.2

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[U-Boot] [PATCH] sunxi: Enable support for the eMMC found on the orangepi plus

[Hans de Goede]

This enables support for the eMMC found on the orangepi plus.

Signed-off-by: Hans de Goede 
---
 configs/orangepi_plus_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index c4885f4..770bd98 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -4,6 +4,8 @@ CONFIG_MACH_SUN8I_H3=y
 CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 # CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-- 
2.7.3

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[U-Boot] [PATCH] spl: Print from which mmc slot spl is trying to boot

[Hans de Goede]

On some sunxi boards (and presumably also non sunxi boards) u-boot can
be either loaded from a sdcard in a micro-sd slot, or from eMMC.

Print which MMC spl tries to boot from, to help debugging.

Signed-off-by: Hans de Goede 
---
 common/spl/spl.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index e5167bf..82e7f58 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -210,9 +210,9 @@ struct boot_device_name boot_name_table[] = {
{ BOOT_DEVICE_RAM, "RAM" },
 #endif
 #ifdef CONFIG_SPL_MMC_SUPPORT
-   { BOOT_DEVICE_MMC1, "MMC" },
-   { BOOT_DEVICE_MMC2, "MMC" },
-   { BOOT_DEVICE_MMC2_2, "MMC" },
+   { BOOT_DEVICE_MMC1, "MMC1" },
+   { BOOT_DEVICE_MMC2, "MMC2" },
+   { BOOT_DEVICE_MMC2_2, "MMC2_2" },
 #endif
 #ifdef CONFIG_SPL_NAND_SUPPORT
{ BOOT_DEVICE_NAND, "NAND" },
-- 
2.7.3

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[U-Boot] [PATCH 3/3] Fix typo choosen in comments and printf logs

[Alexander Merkle]

Minor change: chosen is written with one "o".
No code change here, only comment & printf.

Signed-off-by: Alexander Merkle 
---

 common/menu.c   | 2 +-
 drivers/ddr/fsl/lc_common_dimm_params.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/common/menu.c b/common/menu.c
index eda96d6..c53030f 100644
--- a/common/menu.c
+++ b/common/menu.c
@@ -350,7 +350,7 @@ int menu_item_add(struct menu *m, char *item_key, void 
*item_data)
  * make it obvious what the key for each entry is.
  *
  * item_choice - If not NULL, will be called when asking the user to choose an
- * item. Returns a key string corresponding to the choosen item or NULL if
+ * item. Returns a key string corresponding to the chosen item or NULL if
  * no item has been selected.
  *
  * item_choice_data - Will be passed as the argument to the item_choice 
function
diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c 
b/drivers/ddr/fsl/lc_common_dimm_params.c
index 47ad4e5..850c8f6 100644
--- a/drivers/ddr/fsl/lc_common_dimm_params.c
+++ b/drivers/ddr/fsl/lc_common_dimm_params.c
@@ -60,8 +60,8 @@ compute_cas_latency(const unsigned int ctrl_num,
 * 18ns for all DDR4 speed grades.
 */
if (caslat_actual * mclk_ps > taamax) {
-   printf("The choosen cas latency %d is too large\n",
-   caslat_actual);
+   printf("The chosen cas latency %d is too large\n",
+  caslat_actual);
}
outpdimm->lowest_common_spd_caslat = caslat_actual;
debug("lowest_common_spd_caslat is 0x%x\n", caslat_actual);
-- 
2.7.0

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[U-Boot] [PATCH] driver: net: fsl-mc: Return from DPAA_exit if boot_status !=0

[Prabhakar Kushwaha]

return value of get_mc_boot_status() in case of failure is not necessary
to be -1.

So update the error condition check.

Signed-off-by: Prabhakar Kushwaha 
Reported-by: Yao Yuan 
---
 drivers/net/fsl-mc/mc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 53c4966..7ae619d 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -1147,7 +1147,7 @@ int fsl_mc_ldpaa_exit(bd_t *bd)
 {
int err = 0;
 
-   if (bd && get_mc_boot_status() == -1)
+   if (bd && get_mc_boot_status() != 0)
return 0;
 
if (bd && !get_mc_boot_status() && get_dpl_apply_status() == -1) {
-- 
1.9.1


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Re: [U-Boot] [PATCH 1/2] efi_stub: Move carriage return before line feed in putc()

[Tom Rini]

On Thu, Mar 17, 2016 at 11:59:03PM -0700, Bin Meng wrote:

> A carriage return needs to execute before a line feed.
> 
> Signed-off-by: Bin Meng 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [U-Boot, v5, 25/30] efi_loader: Add README section in README.efi

[Tom Rini]

On Fri, Mar 04, 2016 at 01:10:09AM +0100, Alexander Graf wrote:

> To preserve all cover letter knowledge of the status on UEFI payload
> support, let's add some sections to README.efi.
> 
> Signed-off-by: Alexander Graf 
> 
> v3 -> v4:
> 
>   - Add section about config options
>   - s/10kb/10KB/

Applied to u-boot/master, thanks!

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Re: [U-Boot] sunxi: video: Configure only LVDS pins instead of all LCD pins when LVDS interface selected

[Hans de Goede]

Hi,

On 04-03-16 18:08, Lawrence Yu wrote:

The behavior before this patch would attempt to configure the mux
setting for pins 0 to 27 on PORTD to all be setting 3 for LVDS.  The
LVDS interface actually only uses pins 18 to 27 and not pins 0 to 27
as in the parallel LCD interface.  This patch restricts the
configuration to only the relevant pins 18 to 27 on PORTD.

This was tested on a sun8i A33 tablet with an LVDS screen.  MMC1 has
the capability to use pins 2 to 7 on PORTD and the mux on those pins
was being inadvertently set to setting 3 for MMC functionality which
this patch corrects.

Signed-off-by: Lawrence Yu 


Thanks for the patch, the lvds using pins 18 - 27 is only true
on A23/A33 on e.g. A10 it uses pins 0-19. So I've changed the
condition to:

#if defined CONFIG_MACH_SUN8I && defined CONFIG_VIDEO_LCD_IF_LVDS

and merged the patch with that change.

Regards,

Hans



---

  drivers/video/sunxi_display.c | 4 
  1 file changed, 4 insertions(+)

diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c
index 9fee66a..3674ae1 100644
--- a/drivers/video/sunxi_display.c
+++ b/drivers/video/sunxi_display.c
@@ -767,7 +767,11 @@ static void sunxi_lcdc_tcon0_mode_set(const struct 
ctfb_res_modes *mode,
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
int bp, clk_delay, clk_div, clk_double, pin, total, val;

+#ifdef CONFIG_VIDEO_LCD_IF_LVDS
+   for (pin = SUNXI_GPD(18); pin <= SUNXI_GPD(27); pin++) {
+#else
for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++) {
+#endif
  #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
  #endif


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[U-Boot] [PATCH 2/4] driver: net: fsl-mc: Check NULL before pointer dereference

[Prabhakar Kushwaha]

NULL pointer should be checked before any dereference.  This patch
move memest after the NULL pointer check.

Signed-off-by: Prabhakar Kushwaha 
Reported-by: Jose Rivera 
---
 drivers/net/fsl-mc/dpio/qbman_sys.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/fsl-mc/dpio/qbman_sys.h 
b/drivers/net/fsl-mc/dpio/qbman_sys.h
index 235d641..7a537fb 100644
--- a/drivers/net/fsl-mc/dpio/qbman_sys.h
+++ b/drivers/net/fsl-mc/dpio/qbman_sys.h
@@ -255,11 +255,11 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys 
*s,
s->addr_cena = d->cena_bar;
s->addr_cinh = d->cinh_bar;
s->cena = (void *)valloc(CONFIG_SYS_PAGE_SIZE);
-   memset((void *)s->cena, 0x00, CONFIG_SYS_PAGE_SIZE);
if (!s->cena) {
printf("Could not allocate page for cena shadow\n");
return -1;
}
+   memset((void *)s->cena, 0x00, CONFIG_SYS_PAGE_SIZE);
 
 #ifdef QBMAN_CHECKING
/* We should never be asked to initialise for a portal that isn't in
-- 
1.9.1


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[U-Boot] [PATCH 01/13] ARM: dts: uniphier: add device tree for Micro Support Card

[Masahiro Yamada]

Import uniphier-support-card.dtsi from Linux Kernel and make it
available on the UniPhier reference boards.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/dts/uniphier-ph1-ld4-ref.dts   |  5 +
 arch/arm/dts/uniphier-ph1-ld6b-ref.dts  |  5 +
 arch/arm/dts/uniphier-ph1-pro4-ref.dts  |  5 +
 arch/arm/dts/uniphier-ph1-sld3-ref.dts  |  5 +
 arch/arm/dts/uniphier-ph1-sld8-ref.dts  |  5 +
 arch/arm/dts/uniphier-support-card.dtsi | 33 +
 6 files changed, 58 insertions(+)
 create mode 100644 arch/arm/dts/uniphier-support-card.dtsi

diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts 
b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
index d7b0007..6cae452 100644
--- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
@@ -9,6 +9,7 @@
 /dts-v1/;
 /include/ "uniphier-ph1-ld4.dtsi"
 /include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
 
 / {
model = "UniPhier PH1-LD4 Reference Board";
@@ -35,6 +36,10 @@
};
 };
 
+ {
+   interrupts = <0 49 4>;
+};
+
  {
status = "okay";
 };
diff --git a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts 
b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
index 13a29fd..e2a2a8c 100644
--- a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
@@ -9,6 +9,7 @@
 /dts-v1/;
 /include/ "uniphier-ph1-ld6b.dtsi"
 /include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
 
 / {
model = "UniPhier PH1-LD6b Reference Board";
@@ -37,6 +38,10 @@
};
 };
 
+ {
+   interrupts = <0 52 4>;
+};
+
  {
status = "okay";
 };
diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts 
b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
index 07a9783..5be76e2 100644
--- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
@@ -9,6 +9,7 @@
 /dts-v1/;
 /include/ "uniphier-ph1-pro4.dtsi"
 /include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
 
 / {
model = "UniPhier PH1-Pro4 Reference Board";
@@ -38,6 +39,10 @@
};
 };
 
+ {
+   interrupts = <0 50 4>;
+};
+
  {
status = "okay";
 };
diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts 
b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
index c7213c9..c4601cf 100644
--- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
@@ -9,6 +9,7 @@
 /dts-v1/;
 /include/ "uniphier-ph1-sld3.dtsi"
 /include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
 
 / {
model = "UniPhier PH1-sLD3 Reference Board";
@@ -36,6 +37,10 @@
};
 };
 
+ {
+   interrupts = <0 49 4>;
+};
+
  {
status = "okay";
 };
diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts 
b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
index ec5c5bd..8ceb93e 100644
--- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
@@ -9,6 +9,7 @@
 /dts-v1/;
 /include/ "uniphier-ph1-sld8.dtsi"
 /include/ "uniphier-ref-daughter.dtsi"
+/include/ "uniphier-support-card.dtsi"
 
 / {
model = "UniPhier PH1-sLD8 Reference Board";
@@ -35,6 +36,10 @@
};
 };
 
+ {
+   interrupts = <0 48 4>;
+};
+
  {
status = "okay";
 };
diff --git a/arch/arm/dts/uniphier-support-card.dtsi 
b/arch/arm/dts/uniphier-support-card.dtsi
new file mode 100644
index 000..be0f1d6
--- /dev/null
+++ b/arch/arm/dts/uniphier-support-card.dtsi
@@ -0,0 +1,33 @@
+/*
+ * Device Tree Source for UniPhier Support Card (Expansion Board)
+ *
+ * Copyright (C) 2015 Masahiro Yamada 
+ *
+ * SPDX-License-Identifier:GPL-2.0+X11
+ */
+
+_bus {
+   status = "okay";
+   ranges = <1 0x 0x4200 0x0200>;
+
+   support_card: support_card {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0x 1 0x01f0 0x0010>;
+
+   ethsc: ethernet@ {
+   compatible = "smsc,lan9118", "smsc,lan9115";
+   reg = <0x 0x1000>;
+   phy-mode = "mii";
+   reg-io-width = <4>;
+   };
+
+   serialsc: uart@000b {
+   compatible = "ns16550a";
+   reg = <0x000b 0x20>;
+   clock-frequency = <12288000>;
+   reg-shift = <1>;
+   };
+   };
+};
-- 
1.9.1

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[U-Boot] [PATCH] MAINTAINERS : Add entry for ls2080/5 SECURE BOOT defconfigs

[Saksham Jain]

Added myself as maintainers for the following:
1) configs/ls2080aqds_SECURE_BOOT_defconfig
2) configs/ls2085aqds_SECURE_BOOT_defconfig
3) configs/ls2080ardb_SECURE_BOOT_defconfig
4) configs/ls2085ardb_SECURE_BOOT_defconfig

Signed-off-by: Saksham Jain 
---
 This patch depends on patch which adds these defconfigs:
 http://patchwork.ozlabs.org/patch/580644/
 board/freescale/ls2080aqds/MAINTAINERS | 6 ++
 board/freescale/ls2080ardb/MAINTAINERS | 6 ++
 2 files changed, 12 insertions(+)

diff --git a/board/freescale/ls2080aqds/MAINTAINERS 
b/board/freescale/ls2080aqds/MAINTAINERS
index 6f99ad0..aacd134 100644
--- a/board/freescale/ls2080aqds/MAINTAINERS
+++ b/board/freescale/ls2080aqds/MAINTAINERS
@@ -8,3 +8,9 @@ F:  configs/ls2080aqds_defconfig
 F: configs/ls2080aqds_nand_defconfig
 F: configs/ls2085aqds_defconfig
 F: configs/ls2085aqds_nand_defconfig
+
+LS2080A_SECURE_BOOT BOARD
+M: Saksham Jain 
+S: Maintained
+F: configs/ls2080aqds_SECURE_BOOT_defconfig
+F: configs/ls2085aqds_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls2080ardb/MAINTAINERS 
b/board/freescale/ls2080ardb/MAINTAINERS
index c9f3459..4356637 100644
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -8,3 +8,9 @@ F:  configs/ls2080ardb_defconfig
 F: configs/ls2080ardb_nand_defconfig
 F: configs/ls2085ardb_defconfig
 F: configs/ls2085ardb_nand_defconfig
+
+LS2080A_SECURE_BOOT BOARD
+M: Saksham Jain 
+S: Maintained
+F: configs/ls2080ardb_SECURE_BOOT_defconfig
+F: configs/ls2085ardb_SECURE_BOOT_defconfig
-- 
1.8.1.4

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Re: [U-Boot] [PATCH v4 09/14] armv8: fsl-lsch3: Disable SMMU during Secure Boot

[york sun]

On 02/08/2016 09:27 PM, Saksham Jain wrote:
> During secure boot, SMMU is enabled on POR by SP bootrom.
> SMMU needs to be put in Bypass mode in uboot to
> enable CAAM transcations to pass through.
> 
> During Nonsecure Boot, SP BootROM doesn't enable SMMU and
> at reset SMMU is in bypass mode.
> 

Please keep your line wrap consistent.

York


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[U-Boot] [PATCH 2/3] sunxi: Fix clock_twi_onoff for sun8i-a83

[Hans de Goede]

clock_sun8i_a83.c did not contain a clock_twi_onoff implementation
at all, this is fixed by moving the clock_sun6i.c implementation,
which is correct for the a83 too, to a shared location.

Signed-off-by: Hans de Goede 
---
 arch/arm/cpu/armv7/sunxi/clock.c   | 35 ++
 arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 31 --
 2 files changed, 35 insertions(+), 31 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index 5cc5d25..0b8fc94 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 __weak void clock_init_sec(void)
@@ -28,3 +29,37 @@ int clock_init(void)
 
return 0;
 }
+
+/* These functions are shared between various SoCs so put them here. */
+#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I
+int clock_twi_onoff(int port, int state)
+{
+   struct sunxi_ccm_reg *const ccm =
+   (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+   if (port == 5) {
+   if (state)
+   prcm_apb0_enable(
+   PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
+   else
+   prcm_apb0_disable(
+   PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
+   return 0;
+   }
+
+   /* set the apb clock gate and reset for twi */
+   if (state) {
+   setbits_le32(>apb2_gate,
+CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port));
+   setbits_le32(>apb2_reset_cfg,
+1 << (APB2_RESET_TWI_SHIFT + port));
+   } else {
+   clrbits_le32(>apb2_reset_cfg,
+1 << (APB2_RESET_TWI_SHIFT + port));
+   clrbits_le32(>apb2_gate,
+CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port));
+   }
+
+   return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c 
b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 4e1e1a4..15272c9 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -85,37 +85,6 @@ void clock_init_uart(void)
 #endif
 }
 
-int clock_twi_onoff(int port, int state)
-{
-   struct sunxi_ccm_reg *const ccm =
-   (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
-   if (port == 5) {
-   if (state)
-   prcm_apb0_enable(
-   PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
-   else
-   prcm_apb0_disable(
-   PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
-   return 0;
-   }
-
-   /* set the apb clock gate and reset for twi */
-   if (state) {
-   setbits_le32(>apb2_gate,
-CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
-   setbits_le32(>apb2_reset_cfg,
-1 << (APB2_RESET_TWI_SHIFT + port));
-   } else {
-   clrbits_le32(>apb2_reset_cfg,
-1 << (APB2_RESET_TWI_SHIFT + port));
-   clrbits_le32(>apb2_gate,
-CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
-   }
-
-   return 0;
-}
-
 #ifdef CONFIG_SPL_BUILD
 void clock_set_pll1(unsigned int clk)
 {
-- 
2.7.2

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Re: [U-Boot] [U-Boot, v5, 27/30] arm64: Replace fdt_name env variables with fdtfile

[Tom Rini]

On Fri, Mar 04, 2016 at 01:10:11AM +0100, Alexander Graf wrote:

> The commonly defined environment variable to determine the device tree
> file name is called fdtfile rather than fdt_name. Replace all occurences
> of fdt_name with fdtfile.
> 
> Signed-off-by: Alexander Graf 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] fdt: Try to read #address-cells/size-cells from parent

[David Gibson]

On Wed, Mar 16, 2016 at 05:18:25PM +0100, Michal Simek wrote:
> Hi David,
> 
> On 15.3.2016 01:27, David Gibson wrote:
> > On Mon, Mar 14, 2016 at 10:10:58PM +0100, Michal Simek wrote:
> >> On 13.3.2016 02:54, Simon Glass wrote:
> >>> Hi Michal,
> >>>
> >>> On 16 February 2016 at 09:10, Michal Simek  
> >>> wrote:
>  Hi Simon,
> 
>  On 16.2.2016 17:00, Simon Glass wrote:
> > Hi Michal,
> >
> > On 15 February 2016 at 02:58, Michal Simek  
> > wrote:
> >> Hi Simon,
> >>
> >> On 10.2.2016 13:04, Michal Simek wrote:
> >>> Read #address-cells and #size-cells from parent if they are not 
> >>> present in
> >>> current node.
> >>>
> >>> Signed-off-by: Michal Simek 
> >>> ---
> >>>
> >>> I have code which read information about memory for zynqmp but memory
> >>> node most of the time doesn't contain #address/size-cells which are
> >>> present in parent node.
> >>> That's why let's try to read it from parent.
> >>>
> >>> Also I think that we shouldn't return 2 if property is not found 
> >>> because
> >>> it has side effect on 32bit systems with #address/size-cells = <1>;
> >>>
> >>> ---
> >>>  lib/libfdt/fdt_addresses.c | 18 ++
> >>>  1 file changed, 14 insertions(+), 4 deletions(-)
> >>>
> >>> diff --git a/lib/libfdt/fdt_addresses.c b/lib/libfdt/fdt_addresses.c
> >>> index 76054d98e5fd..b164d0988079 100644
> >>> --- a/lib/libfdt/fdt_addresses.c
> >>> +++ b/lib/libfdt/fdt_addresses.c
> >>> @@ -19,10 +19,15 @@ int fdt_address_cells(const void *fdt, int 
> >>> nodeoffset)
> >>>   const fdt32_t *ac;
> >>>   int val;
> >>>   int len;
> >>> + int parent;
> >>>
> >>>   ac = fdt_getprop(fdt, nodeoffset, "#address-cells", );
> >>> - if (!ac)
> >>> - return 2;
> >>> + if (!ac) {
> >>> + parent = fdt_parent_offset(fdt, nodeoffset);
> >>> + ac = fdt_getprop(fdt, parent, "#address-cells", );
> >>> + if (!ac)
> >>> + return 2;
> >>> + }
> >>>
> >>>   if (len != sizeof(*ac))
> >>>   return -FDT_ERR_BADNCELLS;
> >>> @@ -39,10 +44,15 @@ int fdt_size_cells(const void *fdt, int 
> >>> nodeoffset)
> >>>   const fdt32_t *sc;
> >>>   int val;
> >>>   int len;
> >>> + int parent;
> >>>
> >>>   sc = fdt_getprop(fdt, nodeoffset, "#size-cells", );
> >>> - if (!sc)
> >>> - return 2;
> >>> + if (!sc) {
> >>> + parent = fdt_parent_offset(fdt, nodeoffset);
> >>> + sc = fdt_getprop(fdt, parent, "#size-cells", );
> >>> + if (!sc)
> >>> + return 2;
> >>> + }
> >>>
> >>>   if (len != sizeof(*sc))
> >>>   return -FDT_ERR_BADNCELLS;
> >>>
> >>
> >> Simon: Any comment?
> >
> > It seems risky to change the behaviour here. Also fdt_parent_offset() 
> > is slow.
> >
> > Can you point me to the binding / example DT that you are trying to 
> > parse?
> 
>  Look at dram_init(), etc.
>  https://github.com/Xilinx/u-boot-xlnx/blob/master/board/xilinx/zynqmp/zynqmp.c
> 
>  fdt_get_reg() is calling fdt_size_cells()
> 
> 
>  And this is DTS fragment.
>  #address-cells = <2>;
>  #size-cells = <1>;
> 
>  memory {
>  device_type = "memory";
>  reg = <0x0 0x0 0x8000>, <0x8 0x 0x8000>;
>  };
> 
>  Code is in memory node I need to work with and asking for size-cells.
>  Current code returns 2 instead of error and the rest of code just works
>  with size = 2 which is incorrect for this setup.
> 
>  I have already changed size-cells = 2 in our repo because I need to
>  support for more than 4GB memory anyway but this should point to the
>  problem in that generic functions.
> >>>
> >>> I think this should go in a higher-level function. I very much doubt
> >>> that this patch would be accepted upstream.
> >>>
> >>> Can you find the caller and make it call this function again (for the
> >>> parent) when no nothing is found on the first call? Hopefully this
> >>> caller will have access to the parent node and will not need to call
> >>> fdt_parent_offset().
> >>
> >> The funny part is that nothing is found means return 2. If this returns
> >> something <0 then there is not a problem to try it with parents.
> > 
> > I don't have the full context of this thread, so it's a bit hard to be
> > sure, but this doesn't look right from what I can see.  Two things to
> > remember here:
> > 
> >   * #address-cells and #size-cells describe the format of addresses
> > for 

[U-Boot] [PATCH v2 2/5] arm: Add support for HYP mode and LPAE page tables

[Alexander Graf]

We currently always modify the SVC versions of registers and only support
the short descriptor PTE format.

Some boards however (like the RPi2) run in HYP mode. There, we need to modify
the HYP version of system registers and HYP mode only supports the long
descriptor PTE format.

So this patch introduces support for both long descriptor PTEs and HYP mode
registers.

Signed-off-by: Alexander Graf 

---

v1 -> v2:

  - Switch to KConfig
  - Rename config define to CONFIG_ARMV7_LPAE
---
 arch/arm/cpu/armv7/Kconfig|  8 
 arch/arm/include/asm/system.h | 99 ---
 arch/arm/lib/cache-cp15.c | 66 ++---
 3 files changed, 161 insertions(+), 12 deletions(-)

diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index 6c5d5dd..afeaac8 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -31,4 +31,12 @@ config ARMV7_VIRT
---help---
Say Y here to boot in hypervisor (HYP) mode when booting non-secure.
 
+config ARMV7_LPAE
+   boolean "Use LPAE page table format" if EXPERT
+   depends on CPU_V7
+   default n
+   ---help---
+   Say Y here to use the long descriptor page table format. This is
+   required if U-Boot runs in HYP mode.
+
 endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 832c1db..9ae890a 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -176,7 +176,9 @@ void smc_call(struct pt_regs *args);
 #define CR_AFE (1 << 29)   /* Access flag enable   */
 #define CR_TE  (1 << 30)   /* Thumb exception enable   */
 
-#ifndef PGTABLE_SIZE
+#if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE)
+#define PGTABLE_SIZE   (4096 * 5)
+#elif !defined(PGTABLE_SIZE)
 #define PGTABLE_SIZE   (4096 * 4)
 #endif
 
@@ -233,17 +235,50 @@ void save_boot_params_ret(void);
 #define wfi()
 #endif
 
+static inline unsigned long get_cpsr(void)
+{
+   unsigned long cpsr;
+
+   asm volatile("mrs %0, cpsr" : "=r"(cpsr): );
+   return cpsr;
+}
+
+static inline int is_hyp(void)
+{
+#ifdef CONFIG_ARMV7_LPAE
+   /* HYP mode requires LPAE ... */
+   return ((get_cpsr() & 0x1f) == 0x1a);
+#else
+   /* ... so without LPAE support we can optimize all hyp code away */
+   return 0;
+#endif
+}
+
 static inline unsigned int get_cr(void)
 {
unsigned int val;
-   asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : 
"cc");
+
+   if (is_hyp())
+   asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val)
+ :
+ : "cc");
+   else
+   asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val)
+ :
+ : "cc");
return val;
 }
 
 static inline void set_cr(unsigned int val)
 {
-   asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
- : : "r" (val) : "cc");
+   if (is_hyp())
+   asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" :
+ : "r" (val)
+ : "cc");
+   else
+   asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" :
+ : "r" (val)
+ : "cc");
isb();
 }
 
@@ -261,12 +296,59 @@ static inline void set_dacr(unsigned int val)
isb();
 }
 
-#ifdef CONFIG_CPU_V7
+#ifdef CONFIG_ARMV7_LPAE
+/* Long-Descriptor Translation Table Level 1/2 Bits */
+#define TTB_SECT_XN_MASK   (1ULL << 54)
+#define TTB_SECT_NG_MASK   (1 << 11)
+#define TTB_SECT_AF(1 << 10)
+#define TTB_SECT_SH_MASK   (3 << 8)
+#define TTB_SECT_NS_MASK   (1 << 5)
+#define TTB_SECT_AP(1 << 6)
+/* Note: TTB AP bits are set elsewhere */
+#define TTB_SECT_MAIR(x)   ((x & 0x7) << 2) /* Index into MAIR */
+#define TTB_SECT   (1 << 0)
+#define TTB_PAGETABLE  (3 << 0)
+
+/* TTBCR flags */
+#define TTBCR_EAE  (1 << 31)
+#define TTBCR_T0SZ(x)  ((x) << 0)
+#define TTBCR_T1SZ(x)  ((x) << 16)
+#define TTBCR_USING_TTBR0  (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
+#define TTBCR_IRGN0_NC (0 << 8)
+#define TTBCR_IRGN0_WBWA   (1 << 8)
+#define TTBCR_IRGN0_WT (2 << 8)
+#define TTBCR_IRGN0_WBNWA  (3 << 8)
+#define TTBCR_IRGN0_MASK   (3 << 8)
+#define TTBCR_ORGN0_NC (0 << 10)
+#define TTBCR_ORGN0_WBWA   (1 << 10)
+#define TTBCR_ORGN0_WT (2 << 10)
+#define TTBCR_ORGN0_WBNWA  (3 << 10)
+#define TTBCR_ORGN0_MASK   (3 << 10)
+#define TTBCR_SHARED_NON   (0 

Re: [U-Boot] [PATCH] Add CONFIG_GMAC_TX_DELAY=4 for OlinuXino Lime2

[François-David Collin]

Hi,

I am not 100% sure, but I remember trying first to disable the PMIC in uboot to 
cure this problem, see my post on archlinux arm forum there : 
https://archlinuxarm.org/forum/viewtopic.php?f=33=9911#p50946
But eventually I think this is this patch 
http://lists.denx.de/pipermail/u-boot/2016-March/248923.html
which got it right (no need of disabling pmic). My guess is the board failed to 
activate the Ethernet PHY via pmic due to incompatible config (the failure was 
just after the pmic i2c registering by the kernel).

Regards,
-- 
François-David Collin

De : Michael Haas
Envoyé le :dimanche 20 mars 2016 09:52
À : u-boot@lists.denx.de
Objet :Re: [U-Boot] [PATCH] Add CONFIG_GMAC_TX_DELAY=4 for OlinuXino Lime2

On 03/18/2016 08:06 PM, Michael Haas wrote:
> On 03/18/2016 08:02 PM, Karsten Merker wrote:
>> The installer supports a number of systems that can only load images
>> of limited size, therefore the installer includes only an
>> installation-related subset of all the kernel modules and i2c-mv64xxx
>> currently isn't among those. This hasn't been a practical problem up
>> to now, but being able to talk to the pmic is indeed something that
>> should be possible even in the installer. I'll try to address that in
>> the next days. Regards, Karsten 
> Just an anecdote: I loaded i2c-mv64xx.ko which I had extracted from the
> deb and the olinuxino locked up.

Just for the record: loading i2c-mv64xx.ko reproducibly hangs my Debian
Jessie install with the 4.3.0-0.bpo.1-armmp-lpae kernel.
This happens only on u-boot 2016.01; both Debian stable 2014.10 and my
own build of 2016.03 + patches work fine!


So no problem since it's fixed on newer builds.
Just a note for those playing along at home and wondering why their
olinuxino does not come up anymore with 2016.01.
>
> So now I'm trying to reproduce broken GBit, which is harder than
> expected. I managed to do it once right after the lockup in u-boot: tftp
> was slow and ran into timeouts. Then I typed 'reset' in the u-boot
> shell. u-boot started again and GBit was working again.
>
> Weird.
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Re: [U-Boot] [PATCH v6 00/76] mtd: Add SPI-NOR core support

[Huan Wang]

Hi, Jagan,

> On 9 March 2016 at 13:37, Qianyu Gong  wrote:
> > Hi Jagan,
> >
> >> -Original Message-
> >> From: york sun
> >> Sent: Tuesday, March 08, 2016 12:46 AM
> >> To: Jagan Teki ; Huan Wang ;
> >> Qianyu Gong 
> >> Cc: u-boot@lists.denx.de; Siva Durga Prasad Paladugu
> >> ; Stefan Roese ; Michal Simek
> >> ; Tom Rini 
> >> Subject: Re: [U-Boot] [PATCH v6 00/76] mtd: Add SPI-NOR core support
> >>
> >> On 03/03/2016 01:06 PM, york sun wrote:
> >> > On 02/29/2016 04:26 AM, Jagan Teki wrote:
> >> >> Hi York,
> >> >>
> >> >> On 27 February 2016 at 02:14, york sun  wrote:
> >> >>> On 02/22/2016 10:18 AM, Jagan Teki wrote:
> >>
> >> 
> >>
> >> 
> >>  Can you pls- test the dataflash changes? use u-boot-spi/spi-nor
> >> 
> >> >>> Jagan,
> >> >>>
> >> >>> I am getting there. Will test sf probe/read/write and probably
> >> >>> boot on selected platforms. Is there any specific platform/test
> in your mind?
> >> >>
> >> >> Yes, these tests OK. and if possible please verify 'sf protect' as
> well.
> >> >>
> >> >
> >> > Jagan,
> >> >
> >> > Sorry for the delay. I am having issue with both ls1021aqds and
> >> > ls1043aqds. Need to work with internal team to sort it out.
> >> >
> >> > My understanding the tests you need are for spi-nor, in my case,
> >> > fsl-qspi, right? This is not for fsl-dspi or fsl-espi driver. I
> >> > only have ls1021aqds and ls1043aqds with such support.
> >> >
> >>
> >> Jagan,
> >>
> >> Alison and Qianyu have tested on LS1021AQDS and LS1043AQDS. There
> >> were some issues. They will post their findings (and possible fix) to
> this thread.
> >>
> >> York
> >
> > I tested on LS1043AQDS board based on your spi-nor branch. The
> 'spi_flash_probe'
> > failed during QSPI boot. Then I found that CONFIG_DM_MTD_SPI_NOR is
> > not defined for the board but it could be selected if CONFIG_MTD &&
> CONFIG_DM_SPI, correct?
> >
> > So after I moved CONFIG_MTD to the defconfig file, the probing could
> work now.
> >
> > And there is another small effect on our Fman driver. It would like to
> > read ucode blob from the QSPI flash. As the 'spi_flash_read' interface
> > is changed, I've modified the address value to an offset value in
> flash.
> 
> Qianyu,
> 
> > Here are my patches:
> > http://patchwork.ozlabs.org/patch/594872/
> > http://patchwork.ozlabs.org/patch/594873/
> > http://patchwork.ozlabs.org/patch/594874/
> 
> I have applied 3rd patch on my test branch, and remaining two will go in
> another time like once spi-nor got merged.
> 
> Qianyu/Alison Wang,
> 
> Please test this[1] branch for your new changes and let me know for any
> issues.
> 
> [1] http://git.denx.de/?p=u-boot/u-boot-
> spi.git;a=shortlog;h=refs/heads/spi-nor-next
> 
> 
[Alison Wang] No problem on LS1021AQDS and LS1021ATWR.

Thanks.

Best Regards,
Alison Wang
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Re: [U-Boot] [PATCH] Add CONFIG_GMAC_TX_DELAY=4 for OlinuXino Lime2

[Michael Haas]

On 03/18/2016 08:06 PM, Michael Haas wrote:
> On 03/18/2016 08:02 PM, Karsten Merker wrote:
>> The installer supports a number of systems that can only load images
>> of limited size, therefore the installer includes only an
>> installation-related subset of all the kernel modules and i2c-mv64xxx
>> currently isn't among those. This hasn't been a practical problem up
>> to now, but being able to talk to the pmic is indeed something that
>> should be possible even in the installer. I'll try to address that in
>> the next days. Regards, Karsten 
> Just an anecdote: I loaded i2c-mv64xx.ko which I had extracted from the
> deb and the olinuxino locked up.

Just for the record: loading i2c-mv64xx.ko reproducibly hangs my Debian
Jessie install with the 4.3.0-0.bpo.1-armmp-lpae kernel.
This happens only on u-boot 2016.01; both Debian stable 2014.10 and my
own build of 2016.03 + patches work fine!


So no problem since it's fixed on newer builds.
Just a note for those playing along at home and wondering why their
olinuxino does not come up anymore with 2016.01.
>
> So now I'm trying to reproduce broken GBit, which is harder than
> expected. I managed to do it once right after the lockup in u-boot: tftp
> was slow and ran into timeouts. Then I typed 'reset' in the u-boot
> shell. u-boot started again and GBit was working again.
>
> Weird.
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Re: [U-Boot] [PATCH] Add CONFIG_GMAC_TX_DELAY=4 for OlinuXino Lime2

[Michael Haas]

On 03/17/2016 11:52 AM, Hans de Goede wrote:
>
> 3) The phy settings, unfortunately I do not know of
> a way to dump these, so lets just forget about these
> and focus on the other 2.
>

You can dump these with 'mii read' in u-boot. I sat down with the
rtl8211eg data sheet and decided to look at 'PHYCR (PHY Specific Control
Register, Address 0x10)' and
'PHYSR (PHY Specific Status Register, Address 0x11)'.

There is no difference at 0x10 between working and broken. There are
some changed bits in  reserved areas in 0x11:

Bad:
=> mii read 1 0x10
01EE
=> mii read 1 0x11
AD5C
# 1010 1101 0101 1100


Good:
=> mii read 1 0x10
01EE
=> mii read 1 0x11
BDDC
# 1011 1101 1101 1100

Good #2:
=> mii read 1 0x11
BD5C
# 1011 1101 0101 1100


I haven't yet looked at other registers.

Michael

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[U-Boot] [PATCH 00/14] dm: Fix various issues reported by coverity

[Simon Glass]

A lot of issues have been found in the error handling with recent additions
to the FIT handling code in mkimage. In some cases buffers are not freed or
files are not closed. Fix these problems and a few others in existing code
that coverity noticed due to recent patches.


Simon Glass (14):
  mkimage: Fix munmap() call when importing data
  mkimage: Correct file being closed twice in fit_import_data()
  mkimage: Correct file being closed twice in fit_extract_data()
  part_iso: Drop the customer unaligned access functions
  part_efi: Drop the NULL check on dev_desc in part_print_efi()
  part_efi: Drop NULL check in part_get_info_efi()
  mkimage: Close the file when unable to get its size
  mkimage: Add a missing free() to fit_import_data()
  mkimage: Fix error path in fit_extract_data()
  mkimage: Fix missing free() in fit_extract_data()
  mkimage: Fix missing free() and close() in fit_build()
  mkimage: Ensure file is closed in fdt_property_file()
  mkimage: Don't close the file if it wasn't opened
  usb: Correct return value in usb_stor_info()

 common/usb_storage.c |  2 +-
 disk/part_efi.c  |  6 +-
 disk/part_iso.c  | 27 ---
 tools/fit_image.c| 28 ++--
 tools/imagetool.c|  1 +
 5 files changed, 25 insertions(+), 39 deletions(-)

-- 
2.7.0.rc3.207.g0ac5344

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Re: [U-Boot] [PATCH 14/14] usb: Correct return value in usb_stor_info()

[Tom Rini]

On Wed, Mar 16, 2016 at 07:45:44AM -0600, Simon Glass wrote:

> This should return 0 on success, not 1. Fix it.
> 
> Signed-off-by: Simon Glass 

Reviewed-by: Tom Rini 

-- 
Tom


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[U-Boot] [PATCH] cmd_dhry.c: Use lldiv for vax_mips calculation as well

[Tom Rini]

Since dhry_per_sec is a u64 we must also use lldiv here when working
with it.  Otherwise:
../lib/dhry/cmd_dhry.c:(.text.do_dhry+0xd8): undefined reference to `__udivdi3'

On some platforms.

Signed-off-by: Tom Rini 
---
 lib/dhry/cmd_dhry.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/dhry/cmd_dhry.c b/lib/dhry/cmd_dhry.c
index d7e1e6a..f44305b 100644
--- a/lib/dhry/cmd_dhry.c
+++ b/lib/dhry/cmd_dhry.c
@@ -22,7 +22,7 @@ static int do_dhry(cmd_tbl_t *cmdtp, int flag, int argc, char 
* const argv[])
dhry(iterations);
duration = get_timer(start);
dhry_per_sec = lldiv(iterations * 1000ULL, duration);
-   vax_mips = dhry_per_sec / 1757;
+   vax_mips = lldiv(dhry_per_sec, 1757);
printf("%d iterations in %lu ms: %lu/s, %lu DMIPS\n", iterations,
   duration, (ulong)dhry_per_sec, vax_mips);
 
-- 
1.7.9.5

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[U-Boot] Which entry in drivers/net/phy/realtek.c matches my device?

[Michael Haas]

Hello all,

I'd like to add some device-specific hacks to realtek.c. I'm using the
Olimex A20-OlinuXino-Lime2 which uses the RTL8211CL PHY.

Which of the various phy_driver structs is responsible for that device?
I presume it's keyed off the .uid, but I'm not sure how to find the ID
of the specific PHY used on my device.

Thanks!

Michael
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Re: [U-Boot] [PATCH v2] serial: pl01x: Add support for devices with the rate pre-configured.

[Stephen Warren]

On 03/15/2016 08:36 PM, Stephen Warren wrote:

On 03/13/2016 07:16 PM, Eric Anholt wrote:

For Raspberry Pi, we had the input clock rate to the pl011 fixed in
the rpi.c file, but it may be changed by firmware due to user changes
to config.txt.  Since the firmware always sets up the uart (default
115200 output unless the user changes it), we can just skip our own
uart init to simplify the boot process and more reliably get serial
output.


Tested-by: Stephen Warren 
# on RPi B+ and RPi 2


Sorry, I take this Tested-by back. With the latest firmware (which has 
some modifications intended to initialize either the PL01x or the mini 
UART depending on which the kernel will actually use), this patch causes 
U-Boot not to boot at all. I'm pretty sure this is a FW bug (since even 
without this patch the UART doesn't work, but U-Boot does at least boot 
and can be used over HDMI/usbkbd), but I'd still prefer not to apply 
this until the FW is working again and we can double-check everything.


Hopefully this will be resolved in 
https://github.com/raspberrypi/firmware/issues/553 soon.

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[U-Boot] [PATCH 11/13] ARM: uniphier: add sg_set_iectrl() function

[Masahiro Yamada]

This helper function would be useful for new SoCs with per-pin
input enable controlling, such as PH1-LD20, PH1-LD11, etc.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/sg-regs.h | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h
index 3a535c7..2cdc2db 100644
--- a/arch/arm/mach-uniphier/sg-regs.h
+++ b/arch/arm/mach-uniphier/sg-regs.h
@@ -115,6 +115,17 @@ static inline void sg_set_pinsel(unsigned pin, unsigned 
muxval,
writel(tmp, reg);
 }
 
+static inline void sg_set_iectrl(unsigned pin)
+{
+   unsigned bit = pin % 32;
+   unsigned long reg = SG_IECTRL + pin / 32 * 4;
+   u32 tmp;
+
+   tmp = readl(reg);
+   tmp |= 1 << bit;
+   writel(tmp, reg);
+}
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* ARCH_SG_REGS_H */
-- 
1.9.1

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[U-Boot] [PATCH] driver: net: fsl-mc: Check NULL before pointer dereference

[Prabhakar Kushwaha]

NULL pointer should be checked before any dereference.  This patch
move memest after the NULL pointer check.

Signed-off-by: Prabhakar Kushwaha 
Reported-by: Jose Rivera 
---
 drivers/net/fsl-mc/dpio/qbman_sys.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/fsl-mc/dpio/qbman_sys.h 
b/drivers/net/fsl-mc/dpio/qbman_sys.h
index 235d641..7a537fb 100644
--- a/drivers/net/fsl-mc/dpio/qbman_sys.h
+++ b/drivers/net/fsl-mc/dpio/qbman_sys.h
@@ -255,11 +255,11 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys 
*s,
s->addr_cena = d->cena_bar;
s->addr_cinh = d->cinh_bar;
s->cena = (void *)valloc(CONFIG_SYS_PAGE_SIZE);
-   memset((void *)s->cena, 0x00, CONFIG_SYS_PAGE_SIZE);
if (!s->cena) {
printf("Could not allocate page for cena shadow\n");
return -1;
}
+   memset((void *)s->cena, 0x00, CONFIG_SYS_PAGE_SIZE);
 
 #ifdef QBMAN_CHECKING
/* We should never be asked to initialise for a portal that isn't in
-- 
1.9.1


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