[U-Boot] [PATCH] malloc_simple: Add simple malloc free function

[Chin Liang See]

Enable a simple malloc implementation which will minimize
memory usage prior relocation. This is essential as memory
available prior location is internal memory and limited in
size.

This implementation will stored last 2 usage of malloc. When
free is invoked and the free address matched, we shall revert
to previous value of gd->malloc_ptr that we stored.

Signed-off-by: Chin Liang See 
Cc: Marek Vasut 
Cc: Simon Glass 
Cc: Tom Rini 
Cc: Dinh Nguyen 
Cc: Tien Fong Chee 
---
 common/dlmalloc.c |  6 --
 common/malloc_simple.c| 34 ++
 include/asm-generic/global_data.h |  2 ++
 include/malloc.h  |  3 ++-
 4 files changed, 42 insertions(+), 3 deletions(-)

diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index adc680e..ba42d0d 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -1523,9 +1523,11 @@ void fREe(mem) Void_t* mem;
   int   islr;  /* track whether merging with last_remainder */
 
 #ifdef CONFIG_SYS_MALLOC_F_LEN
-   /* free() is a no-op - all the memory will be freed on relocation */
-   if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT))
+   /* Invoke free_simple. All the memory will be freed on relocation */
+   if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) {
+   free_simple(mem);
return;
+   }
 #endif
 
   if (mem == NULL)  /* free(0) has no effect */
diff --git a/common/malloc_simple.c b/common/malloc_simple.c
index 0f6bcbc..383a546 100644
--- a/common/malloc_simple.c
+++ b/common/malloc_simple.c
@@ -26,6 +26,18 @@ void *malloc_simple(size_t bytes)
return NULL;
}
ptr = map_sysmem(gd->malloc_base + gd->malloc_ptr, bytes);
+
+   /* implement a simple free mechanism which stored last 2 usage */
+   if (gd->malloc_free_addr[0] != 0) {
+   /* shifting as we are storing depth of 2 */
+   gd->malloc_free_addr[1] = gd->malloc_free_addr[0];
+   gd->malloc_free_ptr[1] = gd->malloc_free_ptr[0];
+   }
+   /* saving last malloc address for malloc free */
+   gd->malloc_free_addr[0] = ptr;
+   /* saving last malloc_ptr prior allocation for malloc free */
+   gd->malloc_free_ptr[0] = gd->malloc_ptr;
+
gd->malloc_ptr = ALIGN(new_ptr, sizeof(new_ptr));
debug("%lx\n", (ulong)ptr);
 
@@ -42,6 +54,18 @@ void *memalign_simple(size_t align, size_t bytes)
if (new_ptr > gd->malloc_limit)
return NULL;
ptr = map_sysmem(addr, bytes);
+
+   /* implement a simple free mechanism which stored last 2 usage */
+   if (gd->malloc_free_addr[0] != 0) {
+   /* shifting as we are storing depth of 2 */
+   gd->malloc_free_addr[1] = gd->malloc_free_addr[0];
+   gd->malloc_free_ptr[1] = gd->malloc_free_ptr[0];
+   }
+   /* saving last malloc address for malloc free */
+   gd->malloc_free_addr[0] = ptr;
+   /* saving last malloc_ptr prior allocation for malloc free */
+   gd->malloc_free_ptr[0] = gd->malloc_ptr;
+
gd->malloc_ptr = ALIGN(new_ptr, sizeof(new_ptr));
 
return ptr;
@@ -59,3 +83,13 @@ void *calloc(size_t nmemb, size_t elem_size)
return ptr;
 }
 #endif
+
+void free_simple(Void_t* mem)
+{
+   if (mem == gd->malloc_free_addr[0]) {
+   gd->malloc_ptr = gd->malloc_free_ptr[0];
+   /* shifting as we are storing depth of 2 */
+   gd->malloc_free_addr[0] = gd->malloc_free_addr[1];
+   gd->malloc_free_ptr[0] = gd->malloc_free_ptr[1];
+   }
+}
diff --git a/include/asm-generic/global_data.h 
b/include/asm-generic/global_data.h
index a6d1d2a..9380772 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -90,6 +90,8 @@ typedef struct global_data {
unsigned long malloc_base;  /* base address of early malloc() */
unsigned long malloc_limit; /* limit address */
unsigned long malloc_ptr;   /* current address */
+   void *malloc_free_addr[2];  /* Last malloc pointer address*/
+   unsigned long malloc_free_ptr[2];   /* Last malloc_ptr */
 #endif
 #ifdef CONFIG_PCI
struct pci_controller *hose;/* PCI hose for early use */
diff --git a/include/malloc.h b/include/malloc.h
index 8175c75..02651aa 100644
--- a/include/malloc.h
+++ b/include/malloc.h
@@ -876,7 +876,7 @@ extern Void_t* sbrk();
 #define malloc malloc_simple
 #define realloc realloc_simple
 #define memalign memalign_simple
-static inline void free(void *ptr) {}
+#define free free_simple
 void *calloc(size_t nmemb, size_t size);
 void *memalign_simple(size_t alignment, size_t bytes);
 void *realloc_simple(void *ptr, size_t size);
@@ -913,6 +913,7 @@ int initf_malloc(void);
 
 /* Simple versions which can be used when space is 

[U-Boot] [PATCH] net: asix: Fix ASIX 88772B with driver model

[Alban Bedel]

Commit 147271209a9d ("net: asix: fix operation without eeprom")
added a special handling for ASIX 88772B that enable another
type of header. This break the driver in DM mode as the extra handling
needed in the receive path is missing.

However this new header mode is not required and only seems to
increase the code complexity, so this patch revert this part of
commit 147271209a9d.

Change-Id: I7edc89f5714ead60e5204340ba05caf21b155593
Fixes: 147271209a9d ("net: asix: fix operation without eeprom")
Signed-off-by: Alban Bedel 
---
 drivers/usb/eth/asix.c | 22 +++---
 1 file changed, 3 insertions(+), 19 deletions(-)

diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c
index ad083cf8ae4a..1c6e967db1a0 100644
--- a/drivers/usb/eth/asix.c
+++ b/drivers/usb/eth/asix.c
@@ -67,11 +67,8 @@
 AX_MEDIUM_AC | AX_MEDIUM_RE)
 
 /* AX88772 & AX88178 RX_CTL values */
-#define AX_RX_CTL_RH2M 0x0200  /* 32-bit aligned RX IP header */
-#define AX_RX_CTL_RH1M 0x0100  /* Enable RX header format type 1 */
-#define AX_RX_CTL_SO   0x0080
-#define AX_RX_CTL_AB   0x0008
-#define AX_RX_HEADER_DEFAULT   (AX_RX_CTL_RH1M | AX_RX_CTL_RH2M)
+#define AX_RX_CTL_SO   0x0080
+#define AX_RX_CTL_AB   0x0008
 
 #define AX_DEFAULT_RX_CTL  \
(AX_RX_CTL_SO | AX_RX_CTL_AB)
@@ -98,8 +95,6 @@
 #define FLAG_TYPE_AX88772B (1U << 2)
 #define FLAG_EEPROM_MAC(1U << 3) /* initial mac address in 
eeprom */
 
-#define ASIX_USB_VENDOR_ID 0x0b95
-#define AX88772B_USB_PRODUCT_ID0x772b
 
 /* driver private */
 struct asix_private {
@@ -431,15 +426,10 @@ static int asix_init_common(struct ueth_data *dev, 
uint8_t *enetaddr)
int timeout = 0;
 #define TIMEOUT_RESOLUTION 50  /* ms */
int link_detected;
-   u32 ctl = AX_DEFAULT_RX_CTL;
 
debug("** %s()\n", __func__);
 
-   if ((dev->pusb_dev->descriptor.idVendor == ASIX_USB_VENDOR_ID) &&
-   (dev->pusb_dev->descriptor.idProduct == AX88772B_USB_PRODUCT_ID))
-   ctl |= AX_RX_HEADER_DEFAULT;
-
-   if (asix_write_rx_ctl(dev, ctl) < 0)
+   if (asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL) < 0)
goto out_err;
 
if (asix_write_hwaddr_common(dev, enetaddr) < 0)
@@ -572,12 +562,6 @@ static int asix_recv(struct eth_device *eth)
return -1;
}
 
-   if ((dev->pusb_dev->descriptor.idVendor ==
-ASIX_USB_VENDOR_ID) &&
-   (dev->pusb_dev->descriptor.idProduct ==
-AX88772B_USB_PRODUCT_ID))
-   buf_ptr += 2;
-
/* Notify net stack */
net_process_received_packet(buf_ptr + sizeof(packet_len),
packet_len);
-- 
2.9.2

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[U-Boot] [RESEND PATCH 1/2] rockchip: add basic partitions support for rk3288

[Ziyuan Xu]

For compatibility with distro boot, fastboot, and mount the mmc deivce
to PC via usb mass storage feature, GPT partitions are essential.

You should write the partitions to mmc device prior to use above
feature.

=> gpt write mmc 1 $partitions
GPT successfully written to block device!
success!

Signed-off-by: Ziyuan Xu 
---

 include/configs/rk3288_common.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 814116c..fa37335 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -113,6 +113,12 @@
"kernel_addr_r=0x0200\0" \
"ramdisk_addr_r=0x0400\0"
 
+#define CONFIG_RANDOM_UUID
+#define PARTS_DEFAULT \
+   "uuid_disk=${uuid_gpt_disk};" \
+   "name=boot,start=8M,size=64M,bootable,uuid=${uuid_gpt_boot};" \
+   "name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \
+
 /* First try to boot from SD (index 0), then eMMC (index 1 */
 #define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
@@ -125,6 +131,7 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x1fff\0" \
"initrd_high=0x1fff\0" \
+   "partitions=" PARTS_DEFAULT \
ENV_MEM_LAYOUT_SETTINGS \
ROCKCHIP_DEVICE_SETTINGS \
BOOTENV
-- 
2.9.2


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[U-Boot] [RESEND PATCH 2/2] rockchip: add usb mass storage feature support for rk3288

[Ziyuan Xu]

Enable ums feature for rk3288 boards, so that we can mount the mmc
device to PC.

Signed-off-by: Ziyuan Xu 
---

 include/configs/rk3288_common.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index fa37335..d3d4c68 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -96,6 +96,10 @@
 #define CONFIG_FASTBOOT_BUF_ADDR   CONFIG_SYS_LOAD_ADDR
 #define CONFIG_FASTBOOT_BUF_SIZE   0x0800
 
+/* usb mass storage */
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_CMD_USB_MASS_STORAGE
+
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_G_DNL_MANUFACTURER  "Rockchip"
 #define CONFIG_G_DNL_VENDOR_NUM0x2207
-- 
2.9.2


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[U-Boot] [PATCH 2/2] rockchip: add usb mass storage feature support for rk3288

[Ziyuan Xu]

Enable ums feature for rk3288 boards, so that we can mount the mmc
device to PC.

Signed-off-by: Ziyuan Xu 
---

 include/common.h| 4 +++-
 include/configs/rk3288_common.h | 4 
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/include/common.h b/include/common.h
index e9f0dea..1866cf3 100644
--- a/include/common.h
+++ b/include/common.h
@@ -9,7 +9,9 @@
 #define __COMMON_H_1
 
 #ifndef __ASSEMBLY__   /* put C only stuff in this section */
-
+#ifndef CONFIG_SPL_BUILD
+#define DEBUG
+#endif
 typedef unsigned char  uchar;
 typedef volatile unsigned long vu_long;
 typedef volatile unsigned short vu_short;
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index fa37335..d3d4c68 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -96,6 +96,10 @@
 #define CONFIG_FASTBOOT_BUF_ADDR   CONFIG_SYS_LOAD_ADDR
 #define CONFIG_FASTBOOT_BUF_SIZE   0x0800
 
+/* usb mass storage */
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_CMD_USB_MASS_STORAGE
+
 #define CONFIG_USB_GADGET_DOWNLOAD
 #define CONFIG_G_DNL_MANUFACTURER  "Rockchip"
 #define CONFIG_G_DNL_VENDOR_NUM0x2207
-- 
2.9.2


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[U-Boot] [PATCH 1/2] rockchip: add basic partitions support for rk3288

[Ziyuan Xu]

For compatibility with distro boot, fastboot, and mount the mmc deivce
to PC via usb mass storage feature, GPT partitions are essential.

You should write the partitions to mmc device prior to use above
feature.

=> gpt write mmc 1 $partitions
GPT successfully written to block device!
success!

Signed-off-by: Ziyuan Xu 
---

 include/configs/rk3288_common.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 814116c..fa37335 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -113,6 +113,12 @@
"kernel_addr_r=0x0200\0" \
"ramdisk_addr_r=0x0400\0"
 
+#define CONFIG_RANDOM_UUID
+#define PARTS_DEFAULT \
+   "uuid_disk=${uuid_gpt_disk};" \
+   "name=boot,start=8M,size=64M,bootable,uuid=${uuid_gpt_boot};" \
+   "name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \
+
 /* First try to boot from SD (index 0), then eMMC (index 1 */
 #define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
@@ -125,6 +131,7 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x1fff\0" \
"initrd_high=0x1fff\0" \
+   "partitions=" PARTS_DEFAULT \
ENV_MEM_LAYOUT_SETTINGS \
ROCKCHIP_DEVICE_SETTINGS \
BOOTENV
-- 
2.9.2


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Re: [U-Boot] A command to discard saved environments?

[Masahiro Yamada]

Hi Fabio,


2016-08-03 12:34 GMT+09:00 Fabio Estevam :
> On Wed, Aug 3, 2016 at 12:31 AM, Masahiro Yamada
>  wrote:
>> Hi.
>>
>>
>> I am looking for a command
>> that discards the saved environments,
>
> Does this command help?
>
> => env default -f -a
>


I know this command, but it is the manupulation
of working RAM in U-Boot.

If I reset my board,
it will load the saved environment again.



I want the environment data in a non-volatile device to go away.




-- 
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Masahiro Yamada
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Re: [U-Boot] A command to discard saved environments?

[Fabio Estevam]

On Wed, Aug 3, 2016 at 12:31 AM, Masahiro Yamada
 wrote:
> Hi.
>
>
> I am looking for a command
> that discards the saved environments,

Does this command help?

=> env default -f -a

Regards,

Fabio Estevam
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[U-Boot] A command to discard saved environments?

[Masahiro Yamada]

Hi.


I am looking for a command
that discards the saved environments,
and takes me back to the
"*** Warning - bad CRC, using default environment" state.


In my case, the environment data is saved
at sector 0x400 of the MMC device on my board.


So, I can just do

 > mmc erase 400 10


But, beforehand, I need to know

CONFIG_ENV_IS_IN_MMC
CONFIG_ENV_OFFSET 0x8

in order to confirm if the above command is doing the right thing.
(If I make a mistake in calculating the offset value,
other data would be damaged.)



Is there a nice command to do that?



-- 
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[U-Boot] [Patch v2] net: fm: fix spi flash probe for using driver model

[Gong Qianyu]

The current code would always use the speed and mode set by
CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. But if using
SPI driver model it should get the values from DT.

Signed-off-by: Gong Qianyu 
Reviewed-by: Jagan Teki 
---
v2:
 - Revised the comments as per Jagan's advice.

 drivers/net/fm/fm.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 00cdfd4..4a3e463 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -371,8 +371,18 @@ int fm_init_common(int index, struct ccsr_fman *reg)
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
int ret = 0;
 
+#ifdef CONFIG_DM_SPI_FLASH
+   struct udevice *new;
+
+   /* speed and mode will be read from DT */
+   ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+0, 0, );
+
+   ucode_flash = dev_get_uclass_priv(new);
+#else
ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+#endif
if (!ucode_flash)
printf("SF: probe for ucode failed\n");
else {
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH] crypto/fsl: Update blob cmd to accept 64bit addresses

[york sun]

On 07/14/2016 04:09 AM, Sumit Garg wrote:
> Update blob cmd to accept 64bit source, key modifier and destination
> addresses. Also correct output result print format for fsl specific
> implementation of blob cmd.
>
> Signed-off-by: Sumit Garg 
> ---
>  cmd/blob.c|  2 +-
>  drivers/crypto/fsl/fsl_blob.c | 13 ++---
>  2 files changed, 11 insertions(+), 4 deletions(-)

Applied to fsl-qoriq master, awaiting upstream.
Thanks.

York


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Re: [U-Boot] [PATCH v2] driver: spi: fsl-qspi: remove compile Warnings

[york sun]

On 07/12/2016 07:57 PM, Yunhui Cui wrote:
> From: Yunhui Cui 
>
> Warnins log:
> drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’:
> drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of 
> different size [-Wint-to-pointer-cast]
>   memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);
>
> Signed-off-by: Yunhui Cui 
> ---
>  drivers/spi/fsl_qspi.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>

Applied to fsl-qoriq master, awaiting upstream.
Thanks.

York


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Re: [U-Boot] [PATCH] powerpc/mpc85xx: Update erratum workaround for A006379

[york sun]

On 08/01/2016 09:04 AM, York Sun wrote:
> Update erratum workaround for A006379 to set register CPCHDBCR0
> with value 0x001e, replacing the old value 0x003c.
>
> Signed-off-by: York Sun 
> Reported-by: Dave Liu 
> ---
>  arch/powerpc/include/asm/immap_85xx.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Applied to fsl-qoriq master, awaiting upstream.

York

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Re: [U-Boot] [PATCH] board: ls1012aqds: Update LBMAP_MASK and RST_CTL_RESET

[york sun]

On 07/19/2016 01:36 AM, Prabhakar Kushwaha wrote:
> qixis_reset altbank usagge ~QIXIS_LBMAP_MASK in code. So define
> inverse value QIXIS_LBMAP_MASK.
>
> Also, update QIXIS_RST_CTL_RESET value to keep RST_CTL[REQ_MOD]
> as 0b11 i.e. PORESET during qixis_reset
>
> Signed-off-by: Prabhakar Kushwaha 
> ---
>  include/configs/ls1012aqds.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>

Applied to fsl-qoriq master, awaiting upstream.
Thanks.

York


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Re: [U-Boot] [PATCH] board/freescale: Update MAINTAINERS files

[york sun]

On 07/29/2016 08:47 AM, York Sun wrote:
> Update maintainers for secure boot targets.
>
> Signed-off-by: York Sun 
> ---
>
>  board/freescale/b4860qds/MAINTAINERS   | 2 +-
>  board/freescale/bsc9132qds/MAINTAINERS | 2 +-
>  board/freescale/corenet_ds/MAINTAINERS | 2 +-
>  board/freescale/ls1021atwr/MAINTAINERS | 4 
>  board/freescale/ls1043ardb/MAINTAINERS | 2 +-
>  board/freescale/t1040qds/MAINTAINERS   | 2 +-
>  board/freescale/t104xrdb/MAINTAINERS   | 6 +-
>  board/freescale/t208xqds/MAINTAINERS   | 2 +-
>  board/freescale/t208xrdb/MAINTAINERS   | 2 +-
>  board/freescale/t4qds/MAINTAINERS  | 2 +-
>  10 files changed, 17 insertions(+), 9 deletions(-)
>


Applied to fsl-qoriq master, awaiting upstream.

York


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[U-Boot] Please pull u-boot-fsl-qoriq master

[york sun]

Tom,

The following changes since commit 26fb8db0f4d1e7c118b5e8f3a8849f359b91c166:

   Merge git://git.denx.de/u-boot-rockchip (2016-07-31 20:31:13 -0400)

are available in the git repository at:

   git://git.denx.de/u-boot-fsl-qoriq.git

for you to fetch changes up to ab01ef5fa617444fd95543ee04ea53ccda273269:

   ARMv8/fsl-ppa: Consolidate PPA image stored-media flag for XIP 
(2016-08-02 09:51:29 -0700)


Hou Zhiqiang (4):
   arm/PSCI: Removed unused code
   arm/PSCI: Fixed the backward compatiblity issue
   arm/PSCI: Add support for creating ARMv7 PSCI version 1.0 DT node
   ARMv8/fsl-ppa: Consolidate PPA image stored-media flag for XIP

Prabhakar Kushwaha (3):
   board: ls1012aqds: Update LBMAP_MASK and RST_CTL_RESET
   armv8: ls1012a: Enable DDR row-bank-column decoding
   armv8: ls1012a: Update Refresh cycle for DDR

Sumit Garg (1):
   crypto/fsl: Update blob cmd to accept 64bit addresses

Wenbin Song (1):
   armv8: ls1043a: enable pxe commands

York Sun (3):
   powerpc/mpc85xx: Update erratum workaround for A006379
   board/freescale: Update MAINTAINERS files
   driver/ddr/fsl: Fix timing_cfg_2

Yunhui Cui (1):
   driver: spi: fsl-qspi: remove compile Warnings

  arch/arm/cpu/armv8/fsl-layerscape/ppa.c |  2 +-
  arch/arm/include/asm/psci.h |  3 ++
  arch/arm/lib/psci-dt.c  | 80 
+++--
  arch/powerpc/include/asm/immap_85xx.h   |  2 +-
  board/freescale/b4860qds/MAINTAINERS|  2 +-
  board/freescale/bsc9132qds/MAINTAINERS  |  2 +-
  board/freescale/corenet_ds/MAINTAINERS  |  2 +-
  board/freescale/ls1021atwr/MAINTAINERS  |  4 ++
  board/freescale/ls1043ardb/MAINTAINERS  |  2 +-
  board/freescale/t1040qds/MAINTAINERS|  2 +-
  board/freescale/t104xrdb/MAINTAINERS|  6 ++-
  board/freescale/t208xqds/MAINTAINERS|  2 +-
  board/freescale/t208xrdb/MAINTAINERS|  2 +-
  board/freescale/t4qds/MAINTAINERS   |  2 +-
  cmd/blob.c  |  2 +-
  drivers/crypto/fsl/fsl_blob.c   | 13 --
  drivers/ddr/fsl/ctrl_regs.c |  2 +-
  drivers/spi/fsl_qspi.c  |  4 +-
  include/configs/ls1012aqds.h|  4 +-
  include/configs/ls1043a_common.h|  2 +
  include/configs/ls1043ardb.h|  4 +-
  include/fsl_mmdc.h  |  4 +-
  22 files changed, 82 insertions(+), 66 deletions(-)

Thanks.

York
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Re: [U-Boot] [PATCH] armv8: ls1043a: add pxe commands

[york sun]

On 07/15/2016 02:28 AM, Wenbin Song wrote:
> Configure to support U-boot's pxe.
>
> Signed-off-by: Wenbin Song 
> ---
>  include/configs/ls1043a_common.h | 2 ++
>  1 file changed, 2 insertions(+)

Minor change to subject.
Applied to fsl-qoriq master, awaiting upstream.
Thanks.

York


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Re: [U-Boot] [PATCH] ARMv8/fsl-ppa: Consolidate PPA image stored-media flag for XIP

[york sun]

On 07/29/2016 04:37 AM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang 
>
> The PPA binary may be stored on QSPI flash instead of NOR.
> So, deprecated CONFIG_SYS_LS_PPA_FW_IN_NOR in favour of
> CONFIG_SYS_LS_PPA_FW_IN_XIP to prevent fragmentation of code
> by addition of a new QSPI specific flag.
>
> Signed-off-by: Hou Zhiqiang 
> Signed-off-by: Abhimanyu Saini 
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 2 +-
>  include/configs/ls1043ardb.h| 4 ++--
>  2 files changed, 3 insertions(+), 3 deletions(-)
>

Applied to fsl-qoriq master, awaiting upstream.
Thanks.

York


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Re: [U-Boot] [PATCH 2/3] arm/PSCI: Fixed the backward compatiblity issue

[york sun]

On 07/29/2016 03:37 AM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang 
>
> Appended the compatible strings of old version PSCI to the latest version
> supported. And there are some psci functions' property must be added to DT
> only for psci version 0.1, such as 'cpu_on' 'cpu_off' etc.
>
> Note:
> The PSCI version 0.1 isn't supported by ARMv8 Secure Firmware Framework.
>
> Signed-off-by: Hou Zhiqiang 
> ---
>  arch/arm/include/asm/psci.h |  3 +++
>  arch/arm/lib/psci-dt.c  | 61 
> ++---
>  2 files changed, 38 insertions(+), 26 deletions(-)

Applied to fsl-qoriq master, awaiting upstream.
Thanks.

York


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Re: [U-Boot] [PATCH 3/3] arm/PSCI: Added support for creating ARMv7 PSCI version 1.0 DT node

[york sun]

On 07/29/2016 03:37 AM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang 
>
> Signed-off-by: Hou Zhiqiang 
> ---
>  arch/arm/lib/psci-dt.c | 2 ++
>  1 file changed, 2 insertions(+)

Applied to fsl-qoriq master, awaiting upstream.
Thanks.

York


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Re: [U-Boot] [PATCH 1/2] armv8: ls1012a: Enable DDR row-bank-column decoding

[york sun]

On 07/19/2016 03:24 AM, Prabhakar Kushwaha wrote:
> Enable DDR row-bank-column decoding to decode DDR address as
> row-bank-column instead of bank-row-column for improving
> performance of serial data transfers.
>
> Signed-off-by: Calvin Johnson 
> Signed-off-by: Prabhakar Kushwaha 
> ---
>  include/fsl_mmdc.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Applied to fsl-qoriq master, awaiting upstream.
Thanks.

York


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Re: [U-Boot] [PATCH 2/2] armv8: ls1012a: Update Refresh cycle for DDR

[york sun]

On 07/19/2016 03:24 AM, Prabhakar Kushwaha wrote:
> Refresh cycle value must be selected based on the frequency
> of DDR. tREFI = 7.8 us as per JEDEC. The value for MDREF[REF_CNT]
> should be based on round up (tREFI/tCK) formula. For 500MHz, mdref
> value should be 0x0f3c8000.
>
> Signed-off-by: Calvin Johnson 
> Signed-off-by: Prabhakar Kushwaha 
> ---
>  include/fsl_mmdc.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Applied to fsl-qoriq master, awaiting upstream.
Thanks.

York


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Re: [U-Boot] [PATCH 1/3] arm/PSCI: Removed unused code

[york sun]

On 07/29/2016 03:37 AM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang 
>
> Identify the PSCI node only by its name, so removed the code finding
> it by compatible string.
>
> Signed-off-by: Hou Zhiqiang 
> ---
>  arch/arm/lib/psci-dt.c | 17 -
>  1 file changed, 17 deletions(-)

Applied to fsl-qoriq master, awaiting upstream.
Thanks.

York


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Re: [U-Boot] [PATCH] driver/ddr/fsl: Fix timing_cfg_2

[york sun]

On 07/29/2016 09:02 AM, York Sun wrote:
> Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the
> change was wrong. wr_lat has 5 bits with MSB at [13] and lower
> 4 bits at [9:12], in big-endian convention.
>
> Signed-off-by: York Sun 
> Reported-by: Thomas Schaefer 
> ---
>
>  drivers/ddr/fsl/ctrl_regs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Applied to fsl-qoriq master, awaiting upstream.
Thanks.

York


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[U-Boot] 2016.07 regression: kwboot does not work on Kirkwood

[Simon Baatz]

Hi,

I just tried to boot a freshly built u-boot.kwb using UART boot on a
Kirkwood box (IB-NAS6210), but to no avail.  An old backup image does
not boot either.

After scratching my head for quite some time, I found this change in
commit f4db6c976cf ("arm: mvebu: Add runtime detection of UART
(xmodem) boot-mode") to kwboot.c:

@@ -652,6 +654,14 @@ kwboot_img_patch_hdr(void *img, size_t size)
 
hdr->blockid = IBR_HDR_UART_ID;
 
+   /*
+* Subtract mkimage header size from destination address
+* as this header is not expected by the Marvell BootROM.
+* This way, the execution address is identical to the
+* one the image is compiled for (TEXT_BASE).
+*/
+   hdr->destaddr = hdr->destaddr - sizeof(struct image_header);
+
if (image_ver == 0) {
struct main_hdr_v0 *hdr_v0 = img;


Reverting this change makes kwboot work again for me.

I don't know what the correct fix is. Should we change hdr->destaddr
only for header version 1? (Orion and Kirkwood use header version 0,
right?)
 

- Simon
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Re: [U-Boot] [PATCH] arm: cache: always flush cache line size for page table

[Stefan Agner]

On 2016-08-02 10:55, Marek Vasut wrote:
> On 08/02/2016 07:01 PM, Stefan Agner wrote:
>> On 2016-08-02 08:56, Marek Vasut wrote:
>>> On 08/02/2016 05:47 PM, Stefan Agner wrote:
 On 2016-08-02 02:38, Marek Vasut wrote:
> On 08/02/2016 09:07 AM, Stefan Agner wrote:
>> From: Stefan Agner 
>>
>> The page table is maintained by the CPU, hence it is safe to always
>> align cache flush to a whole cache line size. This allows to use
>> mmu_page_table_flush for a single page table, e.g. when configure
>> only small regions through mmu_set_region_dcache_behaviour.
>>
>> Signed-off-by: Stefan Agner 
>> ---
>> This avoids two messages observed on a i.MX 7 based system:
>> CACHE: Misaligned operation at range [9fff, 9fff0004]
>> CACHE: Misaligned operation at range [9fff0024, 9fff0028]
>>
>> Those were caused by two calls to mmu_set_region_dcache_behaviour
>> in arch/arm/imx-common/cache.c (enable_caches).
>>
>> Not sure if this is the right way to fix this... Also, we could
>> do the alignment in mmu_set_region_dcache_behaviour.
>
> This should be fixed on the driver level indeed, not in cache_v7.c

 Fixing it in enable_caches in arch/arm/imx-common/cache.c is definitely
 unpractical...

 So I guess by driver level you mean in
 arch/arm/lib/cache-cp15.c:mmu_set_region_dcache_behaviour
 correct?

 It has the potential to code duplication in case other users of
 mmu_page_table_flush need to flush page tables less than cache line
 size...
>>>
>>> Isn't the function supposed to flush the whole MMU table ? Or is the
>>> idea here to really flush separate entries ?
>>
>> It has a start/stop argument, so I guess it is supposed to flush
>> separate
>> entries...
> 
> The cache ops also have start/stop argument, but they explicitly cannot
> be used on non-cache-aligned addresses, so the start/stop argument does
> not imply anything.

mmu_set_region_dcache_behaviour and mmu_page_table_flush have been added
by
Simon in one commit, and since mmu_set_region_dcache_behaviour uses it
to
flush only parts of the page table I assume it was ment to be used to
flush
(a range of) separate entries...

In the end it really depends on how we define the semantics of those two
functions... However, we need to take care of alignment in one of those
two,
it is almost impossible on the caller site of
mmu_set_region_dcache_behaviour.

Opinions?

--
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Re: [U-Boot] [PATCH 2/2] fs/fat: Optimizes memory size with single global variable instead of 3

[Benoît Thébaudeau]

Hi,

On Tue, Aug 2, 2016 at 8:53 PM, Stephen Warren  wrote:
> On 07/28/2016 12:11 AM, Tien Fong Chee wrote:
>>
>> Single 64KB get_contents_vfatname_block global variable would be used for
>> all FAT implementation instead of allocating additional two global
>> variables
>> which are get_denfromdir_block and do_fat_read_at_block. This
>> implementation
>> can help in saving up 128KB memory space.
>
>
> The series,
>
> Tested-by: Stephen Warren 
> (via DFU's FAT reading/writing on various Tegra; likely primarily FAT rather
> than VFAT though)
>
> Reviewed-by: Stephen Warren 

I suspect that reading a filename with VFAT entries crossing a cluster
boundary in a FAT32 root directory will be broken by this series. I do
not have time to test this and other corner cases right now though,
but it will be possible in the next few weeks.

Best regards,
Benoît
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Re: [U-Boot] [PATCH v2] mkimage: Fix argument parsing with signature comment

[Tom Rini]

On Tue, Aug 02, 2016 at 06:57:14PM +, Karl Beldan wrote:

> Inform getopt that '-c' requires a parameter.
> 
> Fixes: a02221f29deb ("mkimage: Convert to use getopt()")
> Signed-off-by: Karl Beldan 

Reviewed-by: Tom Rini 

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[U-Boot] [PATCH v2] mkimage: Fix argument parsing with signature comment

[Karl Beldan]

Inform getopt that '-c' requires a parameter.

Fixes: a02221f29deb ("mkimage: Convert to use getopt()")
Signed-off-by: Karl Beldan 
---
 tools/mkimage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/mkimage.c b/tools/mkimage.c
index d993958..3c594a0 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -140,7 +140,7 @@ static void process_args(int argc, char **argv)
int opt;
 
while ((opt = getopt(argc, argv,
-"a:A:b:cC:d:D:e:Ef:Fk:K:ln:p:O:rR:qsT:vVx")) != 
-1) {
+"a:A:b:c:C:d:D:e:Ef:Fk:K:ln:p:O:rR:qsT:vVx")) != 
-1) {
switch (opt) {
case 'a':
params.addr = strtoull(optarg, , 16);
-- 
2.9.0.rc1

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Re: [U-Boot] [PATCH 2/2] fs/fat: Optimizes memory size with single global variable instead of 3

[Stephen Warren]

On 07/28/2016 12:11 AM, Tien Fong Chee wrote:

Single 64KB get_contents_vfatname_block global variable would be used for
all FAT implementation instead of allocating additional two global variables
which are get_denfromdir_block and do_fat_read_at_block. This implementation
can help in saving up 128KB memory space.


The series,

Tested-by: Stephen Warren 
(via DFU's FAT reading/writing on various Tegra; likely primarily FAT 
rather than VFAT though)


Reviewed-by: Stephen Warren 

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Re: [U-Boot] [PATCH 1/2] net: fm: fix spi flash probe for using driver model

[york sun]

On 07/29/2016 04:00 AM, Qianyu Gong wrote:
> Hi Jagan,
>
> Thanks. I'll fix it in the next version.
>

Qianyu,

Is there anything you need to fix?

York
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Re: [U-Boot] [PATCH] ARM: Rework and correct barrier definitions

[Stephen Warren]

On 08/01/2016 04:54 PM, Tom Rini wrote:

As part of testing booting Linux kernels on Rockchip devices, it was
discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for
some cases incomplete isb definitions.  This was causing a failure to
boot of the Linux kernel.

In order to solve this problem as well as cover any corner cases that we
may also have had a number of changes are made in order to consolidate
things.  First,  now becomes the source of isb/dsb/dmb
definitions.  This however introduces another complexity.  Due to
needing to build SPL for 32bit tegra with -march=armv4 we need to borrow
the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete
form.  Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add
a comment about it.  Now that we can always know what the target CPU is
capable off we can get always do the correct thing for the barrier.  The
final part of this is that need to be consistent everywhere and call
isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the
function names in others.


Reviewed-by: Stephen Warren 
Tested-by: Stephen Warren 

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Re: [U-Boot] [PATCH] arm: cache: always flush cache line size for page table

[Marek Vasut]

On 08/02/2016 07:01 PM, Stefan Agner wrote:
> On 2016-08-02 08:56, Marek Vasut wrote:
>> On 08/02/2016 05:47 PM, Stefan Agner wrote:
>>> On 2016-08-02 02:38, Marek Vasut wrote:
 On 08/02/2016 09:07 AM, Stefan Agner wrote:
> From: Stefan Agner 
>
> The page table is maintained by the CPU, hence it is safe to always
> align cache flush to a whole cache line size. This allows to use
> mmu_page_table_flush for a single page table, e.g. when configure
> only small regions through mmu_set_region_dcache_behaviour.
>
> Signed-off-by: Stefan Agner 
> ---
> This avoids two messages observed on a i.MX 7 based system:
> CACHE: Misaligned operation at range [9fff, 9fff0004]
> CACHE: Misaligned operation at range [9fff0024, 9fff0028]
>
> Those were caused by two calls to mmu_set_region_dcache_behaviour
> in arch/arm/imx-common/cache.c (enable_caches).
>
> Not sure if this is the right way to fix this... Also, we could
> do the alignment in mmu_set_region_dcache_behaviour.

 This should be fixed on the driver level indeed, not in cache_v7.c
>>>
>>> Fixing it in enable_caches in arch/arm/imx-common/cache.c is definitely
>>> unpractical...
>>>
>>> So I guess by driver level you mean in
>>> arch/arm/lib/cache-cp15.c:mmu_set_region_dcache_behaviour
>>> correct?
>>>
>>> It has the potential to code duplication in case other users of
>>> mmu_page_table_flush need to flush page tables less than cache line
>>> size...
>>
>> Isn't the function supposed to flush the whole MMU table ? Or is the
>> idea here to really flush separate entries ?
> 
> It has a start/stop argument, so I guess it is supposed to flush
> separate
> entries...

The cache ops also have start/stop argument, but they explicitly cannot
be used on non-cache-aligned addresses, so the start/stop argument does
not imply anything.

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] configs: Fix mmc rescan misuses

[Tom Rini]

On Tue, Aug 02, 2016 at 10:36:17AM +, Karl Beldan wrote:

> This follows 9fd383724cf4 ("mmc: don't allow extra cmdline arguments"),
> and affects omapl138_lcdk and omap3_evm_quick_mmc.
> 
> Signed-off-by: Karl Beldan 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [PATCH] mkimage: Fix argument parsing with signature comment

[Tom Rini]

On Tue, Aug 02, 2016 at 08:49:55AM +, Karl Beldan wrote:

> From: Karl Beldan 
> 
> Signed-off-by: Karl Beldan 
> ---
>  tools/mkimage.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/tools/mkimage.c b/tools/mkimage.c
> index d993958..3c594a0 100644
> --- a/tools/mkimage.c
> +++ b/tools/mkimage.c
> @@ -140,7 +140,7 @@ static void process_args(int argc, char **argv)
>   int opt;
>  
>   while ((opt = getopt(argc, argv,
> -  "a:A:b:cC:d:D:e:Ef:Fk:K:ln:p:O:rR:qsT:vVx")) != 
> -1) {
> +  "a:A:b:c:C:d:D:e:Ef:Fk:K:ln:p:O:rR:qsT:vVx")) != 
> -1) {

Can you please add in a message and perhaps a Fixes: ... ?  Thanks!

-- 
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Re: [U-Boot] [PATCH v3 3/5] ARM: dts: dra7xx: Add u-boot specific property for PCF8575 nodes

[Tom Rini]

On Tue, Aug 02, 2016 at 10:14:26AM +0530, Vignesh R wrote:

> PCF8575 does not have any registers hence, offset field needs to be
> ignored for i2c read/write. Therefore populate u-boot,i2c-offset-len
> with 0 in PCF8575 DT nodes.
> 
> Signed-off-by: Vignesh R 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [PATCH v3 2/5] ARM: dra7xx_evm: Enable support for TI PCF8575

[Tom Rini]

On Tue, Aug 02, 2016 at 10:14:25AM +0530, Vignesh R wrote:

> On DRA7, pcf chip present at address 0x21 on i2c1, is used to
> switch between cpsw slave0 and slave1. Hence, enable PCF
> driver for the same.
> 
> Signed-off-by: Vignesh R 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH 5/5] configs: k2l_evm: add random eth address support

[Tom Rini]

On Tue, Aug 02, 2016 at 12:01:15PM +0530, Mugunthan V N wrote:

> There is only one ethernet mac address in e-fuse, but there are
> multiple slaves in keystone net, so enable random mac address
> support.
> 
> Signed-off-by: Mugunthan V N 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [PATCH 4/5] configs: k2e_evm: add random eth address support

[Tom Rini]

On Tue, Aug 02, 2016 at 12:01:14PM +0530, Mugunthan V N wrote:

> There is only one ethernet mac address in e-fuse, but there are
> multiple slaves in keystone net, so enable random mac address
> support.
> 
> Signed-off-by: Mugunthan V N 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [PATCH 2/5] drivers: net: keystone_net: add support for multi slave ethernet

[Tom Rini]

On Tue, Aug 02, 2016 at 12:01:12PM +0530, Mugunthan V N wrote:

> Keystone net can have multiple ethernet slaves, currently only
> slave 1 is supported by the driver. Register multiple slaves as
> individual ethernets to network framework.
> 
> Signed-off-by: Mugunthan V N 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [PATCH 1/5] drivers: net: keystone_net: fix line termination with semi-colon

[Tom Rini]

On Tue, Aug 02, 2016 at 12:01:11PM +0530, Mugunthan V N wrote:

> Each line should be terminated by semi-colon. It was not caught
> earlier as there is a proper statement. Fix it by changing the
> comma with semi-colon.
> 
> Signed-off-by: Mugunthan V N 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH 3/5] configs: k2hk_evm: add random eth address support

[Tom Rini]

On Tue, Aug 02, 2016 at 12:01:13PM +0530, Mugunthan V N wrote:

> There is only one ethernet mac address in e-fuse, but there are
> multiple slaves in keystone net, so enable random mac address
> support.
> 
> Signed-off-by: Mugunthan V N 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [GIT PULL] Xilinx changes

[Tom Rini]

On Tue, Aug 02, 2016 at 08:25:04AM +0200, Michal Simek wrote:

> Hi Tom,
> 
> please pull these patches to your tree. There are two critical
> patches. One dm-pre-reloc which get ZynqMP boards back to live.
> And the second about stack pointer init.
> 
> Thanks,
> Michal
> 
> 
> The following changes since commit 26fb8db0f4d1e7c118b5e8f3a8849f359b91c166:
> 
>   Merge git://git.denx.de/u-boot-rockchip (2016-07-31 20:31:13 -0400)
> 
> are available in the git repository at:
> 
> 
>   git://www.denx.de/git/u-boot-microblaze.git master
> 
> for you to fetch changes up to 28559d4c93de5039f851eea6d1404305d3ad0825:
> 
>   ARM64: zynqmp: Do not enable DM_MMC by default (2016-08-02 07:19:09 +0200)
> 

Applied to u-boot/master, thanks!




-- 
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Re: [U-Boot] Please pull u-boot-dm

[Tom Rini]

On Mon, Aug 01, 2016 at 12:24:18PM -0600, Simon Glass wrote:

> Hi Tom,
> 
> Here's the buildman updates and an fdt patch. If you end up dropping
> the last two patches (MAKEALL removal) that's fine. But I've included
> them for now.
> 
> 
> The following changes since commit 26fb8db0f4d1e7c118b5e8f3a8849f359b91c166:
> 
>   Merge git://git.denx.de/u-boot-rockchip (2016-07-31 20:31:13 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-dm.git
> 
> for you to fetch changes up to 6de80f2196cb7b7a2c550a636404c54cf532fc17:
> 
>   Drop references to MAKEALL in the documentation (2016-07-31 19:37:08 -0600)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH] MAINTAINERS, git-mailrc: Update the mmc maintainer

[Tom Rini]

On Mon, Aug 01, 2016 at 12:35:20PM +0900, Jaehoon Chung wrote:

> Update the mmc maintainer from Pantelis to me.
> 
> Acked-by: Pantelis Antoniou 
> Signed-off-by: Jaehoon Chung 

Thanks a lot Pantelis and welcome aboard Jaehoon!

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH 9/9] test: Adjust run_command_list() to return a list of strings

[Stephen Warren]

On 07/31/2016 05:35 PM, Simon Glass wrote:

Return one string for each command that was executed. This seems cleaner.


The series,
Reviewed-by: Stephen Warren 

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Re: [U-Boot] [PATCH 7/9] test: vboot: Put each test variant in its own section

[Stephen Warren]

On 07/31/2016 05:35 PM, Simon Glass wrote:

Use 'cons.log.section' feature to split up the test output. This makes it
easier to read.

Suggested-by: Stephen Warren 

Signed-off-by: Simon Glass 


The same nit I mentioned before applies to a few other commits too, such 
as this one.



diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py



-cons.log.action('%s: Test Verified Boot Run: %s' % (sha_algo, 
test_type))
-output = cons.run_command_list(
-['sb load hostfs - 100 %stest.fit' % tmpdir,
- 'fdt addr 100',
- 'bootm 100'])
+with cons.log.section('Verified boot %s %s' % (sha_algo, test_type)):
+output = cons.run_command_list(
+['sb load hostfs - 100 %stest.fit' % tmpdir,
+'fdt addr 100',
+'bootm 100'])
 assert(expect_string in output)


I'd suggest putting the assert inside the "with" block too, so that any 
error messages it raises are part of that block.


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Re: [U-Boot] [PATCH 5/9] test: Drop the cmd() function

[Stephen Warren]

On 07/31/2016 05:35 PM, Simon Glass wrote:

Instead of this, use the existing run_and_log() function, enhanced to
support a command string as well as a list of arguments.

Suggested-by: Stephen Warren 

Signed-off-by: Simon Glass 


Nit: Drop the blank line between those two tags.

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Re: [U-Boot] [PATCH] arm: cache: always flush cache line size for page table

[Stefan Agner]

On 2016-08-02 08:56, Marek Vasut wrote:
> On 08/02/2016 05:47 PM, Stefan Agner wrote:
>> On 2016-08-02 02:38, Marek Vasut wrote:
>>> On 08/02/2016 09:07 AM, Stefan Agner wrote:
 From: Stefan Agner 

 The page table is maintained by the CPU, hence it is safe to always
 align cache flush to a whole cache line size. This allows to use
 mmu_page_table_flush for a single page table, e.g. when configure
 only small regions through mmu_set_region_dcache_behaviour.

 Signed-off-by: Stefan Agner 
 ---
 This avoids two messages observed on a i.MX 7 based system:
 CACHE: Misaligned operation at range [9fff, 9fff0004]
 CACHE: Misaligned operation at range [9fff0024, 9fff0028]

 Those were caused by two calls to mmu_set_region_dcache_behaviour
 in arch/arm/imx-common/cache.c (enable_caches).

 Not sure if this is the right way to fix this... Also, we could
 do the alignment in mmu_set_region_dcache_behaviour.
>>>
>>> This should be fixed on the driver level indeed, not in cache_v7.c
>>
>> Fixing it in enable_caches in arch/arm/imx-common/cache.c is definitely
>> unpractical...
>>
>> So I guess by driver level you mean in
>> arch/arm/lib/cache-cp15.c:mmu_set_region_dcache_behaviour
>> correct?
>>
>> It has the potential to code duplication in case other users of
>> mmu_page_table_flush need to flush page tables less than cache line
>> size...
> 
> Isn't the function supposed to flush the whole MMU table ? Or is the
> idea here to really flush separate entries ?

It has a start/stop argument, so I guess it is supposed to flush
separate
entries...

--
Stefan

> 
>> I felt that mmu_page_table_flush is a convenience function and should
>> take care of that issue.
>>
>> --
>> Stefan
>>
>>
>>
>>>
 --
 Stefan

  arch/arm/cpu/armv7/cache_v7.c | 7 +++
  1 file changed, 7 insertions(+)

 diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
 index 52f1856..71787fc 100644
 --- a/arch/arm/cpu/armv7/cache_v7.c
 +++ b/arch/arm/cpu/armv7/cache_v7.c
 @@ -147,6 +147,13 @@ void arm_init_before_mmu(void)

  void mmu_page_table_flush(unsigned long start, unsigned long stop)
  {
 +  /*
 +   * Make sure range is cache line aligned
 +   * Only CPU maintains page tables, hence it is save to always
 +   * flush the complete cache line...
 +   */
 +  start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
 +  stop = ALIGN(stop, CONFIG_SYS_CACHELINE_SIZE);
flush_dcache_range(start, stop);
v7_inval_tlb();
  }

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Re: [U-Boot] tegra124 jetson-tk1 ethernet problems.

[Stephen Warren]

On 08/01/2016 09:20 PM, Peter Chubb wrote:


Hi Folks,
   Since patch 96350f729c42 "dm: tegra: net: Convert tegra boards to
   driver model for Ethernet" booting via dhcp has been broken on the
   Jetson TK1.


Best to Cc the net and DM maintainers (Joe Hershberger and Simon Glass) 
on this to make sure they see the issue. I've done so here.



   I tried applying "net: Probe PCI before looking for ethernet
   devices"; this `works' in that the ethernet device is detected and
   works,  but I end up with huge numbers of
  CACHE: Misaligned operation at range [fffb8c00, fffb8c2e]
   messages on the serial console.

>

   These come from the flush_cache() calls in net/rtl8169.c.  I
   suggest the attached patch (or something like it):


Interesting; in my automated testing system, I do see these cache error 
messages, yet ping and TFTP work for me. Admittedly my test setup uses a 
static IP configuration rather than DHCP.



diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c



 static void rtl_flush_rx_desc(struct RxDesc *desc)
 {
 #ifndef CONFIG_SYS_NONCACHED_MEMORY
-   flush_cache((unsigned long)desc, sizeof(*desc));
+   unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
+   unsigned long size = ALIGN(sizeof(*desc), ARCH_DMA_MINALIGN);
+
+   flush_cache(start, size);
 #endif
 }

@@ -493,21 +496,28 @@ static void rtl_inval_tx_desc(struct TxDesc *desc)
 static void rtl_flush_tx_desc(struct TxDesc *desc)
 {
 #ifndef CONFIG_SYS_NONCACHED_MEMORY
-   flush_cache((unsigned long)desc, sizeof(*desc));
+   unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
+   unsigned long sz = ALIGN(sizeof *desc, ARCH_DMA_MINALIGN);
+
+   flush_cache(start, sz);
 #endif
 }


Those two are wrong. Hopefully neither of those changes do anything on 
Jetson TK1, since CONFIG_SYS_NONCACHED_MEMORY is enabled there.


The cache line is likely larger than the individual descriptor size, so 
rounding up the flush length to a whole cache line will likely end up 
flushing more descriptors than you want. This will eventually result in 
SW over-writing a HW update to another descriptor, and so at least lose 
packets. For this reason, CONFIG_SYS_NONCACHED_MEMORY must be set if the 
descriptor and cache line sizes don't match, except for systems where IO 
is fully cache-coherent and hence the cache operations are no-ops.



 static void rtl_inval_buffer(void *buf, size_t size)
 {
-   unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
-   unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
+   unsigned long end = ALIGN((unsigned long)buf + size, ARCH_DMA_MINALIGN);

-   invalidate_dcache_range(start, end);
+/* buf is aligned to RTL8169_ALIGN,
+ * which is a multiple of ARCH_DMA_ALIGN
+ */
+   invalidate_dcache_range((unsigned long)buf, end);
 }

 static void rtl_flush_buffer(void *buf, size_t size)
 {
-   flush_cache((unsigned long)buf, size);
+   unsigned long sz = ALIGN(size, ARCH_DMA_MINALIGN);
+
+   flush_cache((unsigned long)buf, sz);
 }


I believe the correct approach is for the caller (network core code) to 
provide cache-aligned buffers, rather than for each driver to align the 
start/size when performing cache operations. Again, this is to ensure 
that cache operations don't affect any other data adjacent to the 
buffer. Can you see why the network core code isn't using cache-aligned 
buffers when DM_ETH is enabled? Perhaps DM_ETH isn't the trigger, but 
just changed something about the memory layout that exposed some other 
pre-existing issue.

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Re: [U-Boot] [PATCH] arm: cache: always flush cache line size for page table

[Marek Vasut]

On 08/02/2016 05:47 PM, Stefan Agner wrote:
> On 2016-08-02 02:38, Marek Vasut wrote:
>> On 08/02/2016 09:07 AM, Stefan Agner wrote:
>>> From: Stefan Agner 
>>>
>>> The page table is maintained by the CPU, hence it is safe to always
>>> align cache flush to a whole cache line size. This allows to use
>>> mmu_page_table_flush for a single page table, e.g. when configure
>>> only small regions through mmu_set_region_dcache_behaviour.
>>>
>>> Signed-off-by: Stefan Agner 
>>> ---
>>> This avoids two messages observed on a i.MX 7 based system:
>>> CACHE: Misaligned operation at range [9fff, 9fff0004]
>>> CACHE: Misaligned operation at range [9fff0024, 9fff0028]
>>>
>>> Those were caused by two calls to mmu_set_region_dcache_behaviour
>>> in arch/arm/imx-common/cache.c (enable_caches).
>>>
>>> Not sure if this is the right way to fix this... Also, we could
>>> do the alignment in mmu_set_region_dcache_behaviour.
>>
>> This should be fixed on the driver level indeed, not in cache_v7.c
> 
> Fixing it in enable_caches in arch/arm/imx-common/cache.c is definitely
> unpractical...
> 
> So I guess by driver level you mean in 
> arch/arm/lib/cache-cp15.c:mmu_set_region_dcache_behaviour
> correct?
> 
> It has the potential to code duplication in case other users of
> mmu_page_table_flush need to flush page tables less than cache line
> size...

Isn't the function supposed to flush the whole MMU table ? Or is the
idea here to really flush separate entries ?

> I felt that mmu_page_table_flush is a convenience function and should
> take care of that issue.
> 
> --
> Stefan
> 
> 
> 
>>
>>> --
>>> Stefan
>>>
>>>  arch/arm/cpu/armv7/cache_v7.c | 7 +++
>>>  1 file changed, 7 insertions(+)
>>>
>>> diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
>>> index 52f1856..71787fc 100644
>>> --- a/arch/arm/cpu/armv7/cache_v7.c
>>> +++ b/arch/arm/cpu/armv7/cache_v7.c
>>> @@ -147,6 +147,13 @@ void arm_init_before_mmu(void)
>>>
>>>  void mmu_page_table_flush(unsigned long start, unsigned long stop)
>>>  {
>>> +   /*
>>> +* Make sure range is cache line aligned
>>> +* Only CPU maintains page tables, hence it is save to always
>>> +* flush the complete cache line...
>>> +*/
>>> +   start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
>>> +   stop = ALIGN(stop, CONFIG_SYS_CACHELINE_SIZE);
>>> flush_dcache_range(start, stop);
>>> v7_inval_tlb();
>>>  }
>>>


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] arm: cache: always flush cache line size for page table

[Stefan Agner]

On 2016-08-02 02:38, Marek Vasut wrote:
> On 08/02/2016 09:07 AM, Stefan Agner wrote:
>> From: Stefan Agner 
>>
>> The page table is maintained by the CPU, hence it is safe to always
>> align cache flush to a whole cache line size. This allows to use
>> mmu_page_table_flush for a single page table, e.g. when configure
>> only small regions through mmu_set_region_dcache_behaviour.
>>
>> Signed-off-by: Stefan Agner 
>> ---
>> This avoids two messages observed on a i.MX 7 based system:
>> CACHE: Misaligned operation at range [9fff, 9fff0004]
>> CACHE: Misaligned operation at range [9fff0024, 9fff0028]
>>
>> Those were caused by two calls to mmu_set_region_dcache_behaviour
>> in arch/arm/imx-common/cache.c (enable_caches).
>>
>> Not sure if this is the right way to fix this... Also, we could
>> do the alignment in mmu_set_region_dcache_behaviour.
> 
> This should be fixed on the driver level indeed, not in cache_v7.c

Fixing it in enable_caches in arch/arm/imx-common/cache.c is definitely
unpractical...

So I guess by driver level you mean in 
arch/arm/lib/cache-cp15.c:mmu_set_region_dcache_behaviour
correct?

It has the potential to code duplication in case other users of
mmu_page_table_flush need to flush page tables less than cache line
size...

I felt that mmu_page_table_flush is a convenience function and should
take care of that issue.

--
Stefan



> 
>> --
>> Stefan
>>
>>  arch/arm/cpu/armv7/cache_v7.c | 7 +++
>>  1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
>> index 52f1856..71787fc 100644
>> --- a/arch/arm/cpu/armv7/cache_v7.c
>> +++ b/arch/arm/cpu/armv7/cache_v7.c
>> @@ -147,6 +147,13 @@ void arm_init_before_mmu(void)
>>
>>  void mmu_page_table_flush(unsigned long start, unsigned long stop)
>>  {
>> +/*
>> + * Make sure range is cache line aligned
>> + * Only CPU maintains page tables, hence it is save to always
>> + * flush the complete cache line...
>> + */
>> +start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
>> +stop = ALIGN(stop, CONFIG_SYS_CACHELINE_SIZE);
>>  flush_dcache_range(start, stop);
>>  v7_inval_tlb();
>>  }
>>
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Re: [U-Boot] [PATCH v2 10/10] boston: Introduce support for the MIPS Boston development board

[Marek Vasut]

On 08/02/2016 03:12 PM, Paul Burton wrote:
> On 01/08/16 19:36, Marek Vasut wrote:
>> On 07/31/2016 07:32 PM, Paul Burton wrote:
>>> On 31/07/16 16:56, Marek Vasut wrote:
 On 07/29/2016 10:36 AM, Paul Burton wrote:
 [...]
>>> +#ifndef __ASSEMBLY__
>>> +
>>> +#include 
>>> +
>>> +#define BUILD_PLAT_ACCESSORS(offset, name)\
>>> +static inline uint32_t read_boston_##name(void)\
>>> +{\
>>> +uint32_t *reg = (void *)CKSEG1ADDR(BOSTON_PLAT_BASE) +
>>> (offset);\
>>> +return __raw_readl(reg);\
>>> +}
>>
>> Don't we have enough standard accessors to confuse people ?
>> Why do you add another custom ones ? Remove this and just use
>> standard accessors throughout the code.
>
> Hi Marek,
>
> These accessors are simple wrappers around __raw_readl, I'd hardly say
> they can be considered confusing. The alternative is lots of:
>
> val = __raw_readl((void *)CKSEG1ADDR(BOSTON_PLAT_BASE) + OFFSET);
>
> ...and that is just plain ugly.

 This should be map_physmem() + readl(), see ie. the ag7xxx.c driver or
 whatever other stuff from the atheros ath79 port. Does this work ?
>>>
>>> Yes this works. I suggest you read about the MIPS memory map if you wish
>>> to critique this code.
>>
>> What am I missing ?
> 
> Hi Marek,
> 
> You're missing that in MIPS the virtual address space includes the
> unmapped regions kseg0 & kseg1. To perform uncached access to a physical
> address beneath 512MB one can simply use it as an offset into kseg1,
> with no need to perform any mapping.

The map_physmem() does this translation, no ?

> Invoking readl on a field of a struct
> representing these registers would be nice, but some of them need
> to be
> accessed from assembly so that would involve duplication which isn't
> nice.

 The struct based access is deprecated, don't bother with it.

> I think this way is the best option, where if you want to read the
> Boston core_cl register you call read_boston_core_cl() - it's hardly
> confusing what that does.

 Now imagine what would happen if everyone introduced his own
 my_platform_read_random_register() accessor(s) . This would be utter
 chaos.
>>>
>>> You speak as though this patch introduces new general purpose accessor
>>> functions that perform some arbitrary memory read. It does not.
>>
>> Yes it does, the accessor is globally available.
> 
> They're only available if you include boston-regs.h which lives inside
> board/imgtec/boston/, and regardless their availability does not make
> them general purpose. Each accesses only a single register in a single
> way. That is not a general purpose accessor like readl, __raw_readl, inl
> or whatever else - indeed it's built using the standard __raw_readl.

OK, I see we have two stubborn people bashing heads against one another.
I'll leave this decision about this accessor thing to Dan if you don't mind.

>>> It
>>> introduces functions each of which reads a single register in the only
>>> sane way to read that register, via the standard __raw_readl. It does so
>>> in a pretty well namespaced manner & with names that match the register
>>> names of the platform. If everyone were to do that I fail to see what
>>> the problem would be.
>>
>> Say you want to find all register accesses -- with random functions with
>> ad-hoc names, you cannot do simple git grep, you need to grep for these
>> ad-hoc functions as well ... but they won't show up, since there
>> is also preprocessor string concatenation, which further obfuscates
>> things and makes it unpleasant to work with.
>>
>> In my opinion, this macro has no value.
> 
> I disagree & find it rather pleasant to use with minimal costs, but
> given that there are only 2 such register accesses left since the clock
> changes in v2 I've removed it.
> 
>>> +BUILD_PLAT_ACCESSORS(BOSTON_PLAT_CORE_CL, core_cl)
>>> +BUILD_PLAT_ACCESSORS(BOSTON_PLAT_MMCMDIV, mmcmdiv)
>>> +BUILD_PLAT_ACCESSORS(BOSTON_PLAT_DDRCONF0, ddrconf0)
>>> +
>>> +#endif /* !__ASSEMBLY__ */
>>> +
>>> +#endif /* __BOARD_BOSTON_REGS_H__ */
>>> diff --git a/board/imgtec/boston/checkboard.c
>>> b/board/imgtec/boston/checkboard.c
>>> new file mode 100644
>>> index 000..417ac4e
>>> --- /dev/null
>>> +++ b/board/imgtec/boston/checkboard.c
>>> @@ -0,0 +1,29 @@
>>> +/*
>>> + * Copyright (C) 2016 Imagination Technologies
>>> + *
>>> + * SPDX-License-Identifier:GPL-2.0
>>> + */
>>> +
>>> +#include 
>>> +
>>> +#include 
>>> +
>>> +#include "boston-lcd.h"
>>> +#include "boston-regs.h"
>>>
>>> +int checkboard(void)
>>> +{
>>> +u32 changelist;
>>> +
>>> +lowlevel_display("U-boot  ");
>>> +
>>> +printf("Board: MIPS Boston\n");

[U-Boot] [PATCH v5 11/11] boston: Introduce support for the MIPS Boston development board

[Paul Burton]

This patch introduces support for building U-Boot to run on the MIPS
Boston development board. This is a board built around an FPGA & an
Intel EG20T Platform Controller Hub, used largely as part of the
development of new CPUs and their software support. It is essentially
the successor to the older MIPS Malta board.

Signed-off-by: Paul Burton 

---

Changes in v5:
- Mention arch revision & toolchain in README.boston
- Drop platform register access now only 2 are used since clock changes

Changes in v4:
- Add README.boston

Changes in v3:
- Add defconfigs for 32b & 64b, big & little endian, switch to MIPSr2

Changes in v2:
- Use AT instead of $1
- Use a clock driver instead of patching the DT

 arch/mips/Kconfig   |  16 +++
 arch/mips/dts/Makefile  |   1 +
 arch/mips/dts/img,boston.dts| 216 
 board/imgtec/boston/Kconfig |  16 +++
 board/imgtec/boston/MAINTAINERS |   6 +
 board/imgtec/boston/Makefile|   9 ++
 board/imgtec/boston/boston-lcd.h|  21 
 board/imgtec/boston/boston-regs.h   |  26 +
 board/imgtec/boston/checkboard.c|  30 +
 board/imgtec/boston/ddr.c   |  30 +
 board/imgtec/boston/lowlevel_init.S |  56 ++
 configs/boston32r2_defconfig|  40 +++
 configs/boston32r2el_defconfig  |  41 +++
 configs/boston64r2_defconfig|  40 +++
 configs/boston64r2el_defconfig  |  41 +++
 doc/README.boston   |  58 ++
 include/configs/boston.h|  68 
 17 files changed, 715 insertions(+)
 create mode 100644 arch/mips/dts/img,boston.dts
 create mode 100644 board/imgtec/boston/Kconfig
 create mode 100644 board/imgtec/boston/MAINTAINERS
 create mode 100644 board/imgtec/boston/Makefile
 create mode 100644 board/imgtec/boston/boston-lcd.h
 create mode 100644 board/imgtec/boston/boston-regs.h
 create mode 100644 board/imgtec/boston/checkboard.c
 create mode 100644 board/imgtec/boston/ddr.c
 create mode 100644 board/imgtec/boston/lowlevel_init.S
 create mode 100644 configs/boston32r2_defconfig
 create mode 100644 configs/boston32r2el_defconfig
 create mode 100644 configs/boston64r2_defconfig
 create mode 100644 configs/boston64r2el_defconfig
 create mode 100644 doc/README.boston
 create mode 100644 include/configs/boston.h

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 21066f0..7ba0ef2 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -73,9 +73,25 @@ config MACH_PIC32
select OF_CONTROL
select DM
 
+config TARGET_BOSTON
+   bool "Support Boston"
+   select DM
+   select DM_SERIAL
+   select OF_CONTROL
+   select MIPS_L1_CACHE_SHIFT_6
+   select SUPPORTS_BIG_ENDIAN
+   select SUPPORTS_LITTLE_ENDIAN
+   select SUPPORTS_CPU_MIPS32_R1
+   select SUPPORTS_CPU_MIPS32_R2
+   select SUPPORTS_CPU_MIPS32_R6
+   select SUPPORTS_CPU_MIPS64_R1
+   select SUPPORTS_CPU_MIPS64_R2
+   select SUPPORTS_CPU_MIPS64_R6
+
 endchoice
 
 source "board/dbau1x00/Kconfig"
+source "board/imgtec/boston/Kconfig"
 source "board/imgtec/malta/Kconfig"
 source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 2f04d73..6a5e43e 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -4,6 +4,7 @@
 
 dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
 dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
+dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb
 dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
diff --git a/arch/mips/dts/img,boston.dts b/arch/mips/dts/img,boston.dts
new file mode 100644
index 000..2fbcb93
--- /dev/null
+++ b/arch/mips/dts/img,boston.dts
@@ -0,0 +1,216 @@
+/dts-v1/;
+
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "img,boston";
+
+   chosen {
+   stdout-path = 
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "img,mips";
+   reg = <0>;
+   clocks = <_boston BOSTON_CLK_CPU>;
+   };
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x 0x1000>;
+   };
+
+   gic: interrupt-controller {
+   compatible = "mti,gic";
+
+   interrupt-controller;
+   #interrupt-cells = <3>;
+
+   timer {
+   compatible = "mti,gic-timer";
+   interrupts = ;
+   clocks = <_boston BOSTON_CLK_CPU>;
+   };
+   };
+
+   pci0: pci@1000 {
+   status = "disabled";
+   

Re: [U-Boot] [PATCH v2 10/10] boston: Introduce support for the MIPS Boston development board

[Paul Burton]

On 01/08/16 19:36, Marek Vasut wrote:

On 07/31/2016 07:32 PM, Paul Burton wrote:

On 31/07/16 16:56, Marek Vasut wrote:

On 07/29/2016 10:36 AM, Paul Burton wrote:
[...]

+#ifndef __ASSEMBLY__
+
+#include 
+
+#define BUILD_PLAT_ACCESSORS(offset, name)\
+static inline uint32_t read_boston_##name(void)\
+{\
+uint32_t *reg = (void *)CKSEG1ADDR(BOSTON_PLAT_BASE) + (offset);\
+return __raw_readl(reg);\
+}


Don't we have enough standard accessors to confuse people ?
Why do you add another custom ones ? Remove this and just use
standard accessors throughout the code.


Hi Marek,

These accessors are simple wrappers around __raw_readl, I'd hardly say
they can be considered confusing. The alternative is lots of:

val = __raw_readl((void *)CKSEG1ADDR(BOSTON_PLAT_BASE) + OFFSET);

...and that is just plain ugly.


This should be map_physmem() + readl(), see ie. the ag7xxx.c driver or
whatever other stuff from the atheros ath79 port. Does this work ?


Yes this works. I suggest you read about the MIPS memory map if you wish
to critique this code.


What am I missing ?


Hi Marek,

You're missing that in MIPS the virtual address space includes the 
unmapped regions kseg0 & kseg1. To perform uncached access to a physical 
address beneath 512MB one can simply use it as an offset into kseg1, 
with no need to perform any mapping.



Invoking readl on a field of a struct
representing these registers would be nice, but some of them need to be
accessed from assembly so that would involve duplication which isn't
nice.


The struct based access is deprecated, don't bother with it.


I think this way is the best option, where if you want to read the
Boston core_cl register you call read_boston_core_cl() - it's hardly
confusing what that does.


Now imagine what would happen if everyone introduced his own
my_platform_read_random_register() accessor(s) . This would be utter
chaos.


You speak as though this patch introduces new general purpose accessor
functions that perform some arbitrary memory read. It does not.


Yes it does, the accessor is globally available.


They're only available if you include boston-regs.h which lives inside 
board/imgtec/boston/, and regardless their availability does not make 
them general purpose. Each accesses only a single register in a single 
way. That is not a general purpose accessor like readl, __raw_readl, inl 
or whatever else - indeed it's built using the standard __raw_readl.



It
introduces functions each of which reads a single register in the only
sane way to read that register, via the standard __raw_readl. It does so
in a pretty well namespaced manner & with names that match the register
names of the platform. If everyone were to do that I fail to see what
the problem would be.


Say you want to find all register accesses -- with random functions with
ad-hoc names, you cannot do simple git grep, you need to grep for these
ad-hoc functions as well ... but they won't show up, since there
is also preprocessor string concatenation, which further obfuscates
things and makes it unpleasant to work with.

In my opinion, this macro has no value.


I disagree & find it rather pleasant to use with minimal costs, but 
given that there are only 2 such register accesses left since the clock 
changes in v2 I've removed it.



+BUILD_PLAT_ACCESSORS(BOSTON_PLAT_CORE_CL, core_cl)
+BUILD_PLAT_ACCESSORS(BOSTON_PLAT_MMCMDIV, mmcmdiv)
+BUILD_PLAT_ACCESSORS(BOSTON_PLAT_DDRCONF0, ddrconf0)
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __BOARD_BOSTON_REGS_H__ */
diff --git a/board/imgtec/boston/checkboard.c
b/board/imgtec/boston/checkboard.c
new file mode 100644
index 000..417ac4e
--- /dev/null
+++ b/board/imgtec/boston/checkboard.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+
+#include 
+
+#include "boston-lcd.h"
+#include "boston-regs.h"

+int checkboard(void)
+{
+u32 changelist;
+
+lowlevel_display("U-boot  ");
+
+printf("Board: MIPS Boston\n");
+
+printf("CPU:   0x%08x", read_c0_prid());


This should be in print_cpuinfo()


I don't agree. This goes on to read a board-specific register to
determine information about the CPU (the revision of its RTL) and that
should not be done in arch-level code, which is what every other
implementation of print_cpuinfo is.


Ah, so the register used to determine CPU info is board-specific ? That
is utterly braindead design in my mind. The read_c0_prid() looked like
it is reading some standard register, maybe that's not true ...


read_c0_prid() is generic, it's the read_boston_core_cl() that is
board-specific & used to print the CPU's RTL revision, as I described
with "goes on to...".


So this stuff should be in print_cpuinfo() if it's generic.


I disagree that this is a bad design. It's pretty
logical that an FPGA based development platform might wish to expose

Re: [U-Boot] [PATCH] serial: Enable checking UART is ready for console based on device tree

[Marek Vasut]

On 08/01/2016 03:01 AM, Simon Glass wrote:
> Hi,
> 
> On 26 July 2016 at 04:55, Tien Fong Chee  wrote:
>> This patch would do checking on device tree to ensure the UART exist
>> in the system and ready for console before setting have_console to true.
>> This is required to avoid unexpected behavior such as hang during UART
>> initialization.
>>
>> Signed-off-by: Tien Fong Chee 
>> Cc: Dinh Nguyen 
>> Cc: Dinh Nguyen 
>> Cc: ChinLiang 
>> Cc: Thomas Chou 
>> Cc: Simon Glass 
>> Cc: Marek Vasut 
>> ---
>>  common/console.c  |   11 ---
>>  common/spl/spl.c  |3 +-
>>  drivers/serial/serial.c   |   58 
>> +++-
>>  include/asm-generic/global_data.h |1 +
>>  include/serial.h  |1 +
>>  5 files changed, 66 insertions(+), 8 deletions(-)
> 
> Another way to deal with this would be to have the driver return
> -EBUSY (or perhaps -EAGAIN) and set this flag in
> serial_find_console_or_panic(). After all, the unavailability of
> serial is a driver-specific thing, right?

I think the -EAGAIN makes sense -- use default null console and probe
the UART when it's ready.

> How / when does the FPGA get programmed on your system?

On CV/AV, the FPGA is loaded via the fpga command .


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] ARM: Rework and correct barrier definitions

[Sandy Patterson]

Works for me on rock2. Thanks for the fix.

Acked-by: Sandy Patterson 

On Mon, Aug 1, 2016 at 8:39 PM, Tom Rini  wrote:

> On Tue, Aug 02, 2016 at 08:37:19AM +0800, Ziyuan Xu wrote:
> > Hi Tom,
> >
> >
> > On 2016年08月02日 06:54, Tom Rini wrote:
> > >As part of testing booting Linux kernels on Rockchip devices, it was
> > >discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for
> > >some cases incomplete isb definitions.  This was causing a failure to
> > >boot of the Linux kernel.
> > >
> > >In order to solve this problem as well as cover any corner cases that we
> > >may also have had a number of changes are made in order to consolidate
> > >things.  First,  now becomes the source of isb/dsb/dmb
> > >definitions.  This however introduces another complexity.  Due to
> > >needing to build SPL for 32bit tegra with -march=armv4 we need to borrow
> > >the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete
> > >form.  Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add
> > >a comment about it.  Now that we can always know what the target CPU is
> > >capable off we can get always do the correct thing for the barrier.  The
> > >final part of this is that need to be consistent everywhere and call
> > >isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the
> > >function names in others.
> > >
> > >Reported-by: Ziyuan Xu 
> > >Reported-by: Sandy Patterson 
> > >Signed-off-by: Tom Rini 
> > Great, this rework is similar to linux kernel, and it's better than
> > what I did.  Moreover, it works for my rk3288 boards.
> > Tested-by: Ziyuan Xu 
> >
> > But please can you keep things in alpha order? See below.
>
> Sure, I'll re-work when applying or reposting if there's any other
> comments.  Thanks!
>
> --
> Tom
>
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Re: [U-Boot] [PATCH v2 0/3] Add USB EHCI support for ls1012aqds

[Rajesh Bhagat]

> 
> > -Original Message-
> > From: Marek Vasut [mailto:ma...@denx.de]
> > Sent: Friday, June 10, 2016 9:40 AM
> > To: Rajesh Bhagat ; u-boot@lists.denx.de
> > Cc: Sriram Dash ; albert.u.b...@aribaud.net;
> > prabha...@freescale.com; york sun ; Rajat Srivastava
> > 
> > Subject: Re: [PATCH v2 0/3] Add USB EHCI support for ls1012aqds
> >
> > On 06/10/2016 05:41 AM, Rajesh Bhagat wrote:
> > >
> > >
> > >> -Original Message-
> > >> From: Marek Vasut [mailto:ma...@denx.de]
> > >> Sent: Thursday, June 09, 2016 7:12 PM
> > >> To: Rajesh Bhagat ; u-boot@lists.denx.de
> > >> Cc: Sriram Dash ; albert.u.b...@aribaud.net;
> > >> prabha...@freescale.com; york sun ; Rajat
> > >> Srivastava 
> > >> Subject: Re: [PATCH v2 0/3] Add USB EHCI support for ls1012aqds
> > >>
> > >> On 06/09/2016 08:57 AM, Rajesh Bhagat wrote:
> > >>> Adds USB EHCI support for ls1012qds by adding the support for NXP
> > >>> ULPI PHY and adding the support it configuration files. Also
> > >>> enables, USB2 IP in ns access defines.
> > >>>
> > >>> Rajesh Bhagat (3):
> > >>>   drivers: usb: fsl: add USB ULPI init code
> > >>>   config: ls1012aqds: Add USB EHCI support for ls1012aqds
> > >>>   armv8: ls1012a: Added CSU assignment for USB2
> > >>>
> > >>>  .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |1 +
> > >>>  .../include/asm/arch-fsl-layerscape/ns_access.h|2 +
> > >>>  drivers/usb/host/ehci-fsl.c|   21
> > 
> > >>>  include/configs/ls1012aqds.h   |5 
> > >>>  include/usb/ehci-ci.h  |2 +-
> > >>>  5 files changed, 30 insertions(+), 1 deletions(-)
> > >>>
> > >
> > > Hello Marek,
> > >
> > >> I wanted to apply these on u-boot-usb/master , but patch 2 fails to
> > >> apply. Please rebase and repose.
> > >>
> > >
> > > Can you apply below patch for Layerscape USB macro cleanup for
> > > various Soc to apply above patch:
> > >
> > > https://patchwork.ozlabs.org/patch/631595/

Hello Marek, 

> >
> > This has to go through soc tree, so I will have to wait for it to be
> > applied. Let me know when it's in, then I can pick these patches.
> >

The dependency patch has made it to uboot master, Please apply the 
EHCI support patches.

Commit: 9729dc9565c9c1812efbb630e1db4d54f580363c
include: usb: Rename USB controller base address mapping

Best Regards,
Rajesh Bhagat 

> > > [root@phoenix u-boot-usb]$ pw-am.sh 631595
> > > 2016-06-10 09:02:02
> > > URL:https://patchwork.ozlabs.org/patch/631595/mbox/ [6138] ->
> > > "pw-am-631595.patch" [1]
> > > Applying: include: usb: Rename USB controller base address mapping
> > > [root@phoenix u-boot-usb]$ pw-am.sh 632644
> > > 2016-06-10 09:02:18
> > > URL:https://patchwork.ozlabs.org/patch/632644/mbox/ [2104] ->
> > > "pw-am-632644.patch" [1]
> > > Applying: drivers: usb: fsl: add USB ULPI init code [root@phoenix
> > > u-boot-usb]$ pw-am.sh 632646
> > > 2016-06-10 09:02:28
> > > URL:https://patchwork.ozlabs.org/patch/632646/mbox/ [2819] ->
> > > "pw-am-632646.patch" [1]
> > > Applying: config: ls1012aqds: Add USB EHCI support for ls1012aqds
> > > [root@phoenix u-boot-usb]$ pw-am.sh 632645
> > > 2016-06-10 09:02:36
> > > URL:https://patchwork.ozlabs.org/patch/632645/mbox/ [1501] ->
> > > "pw-am-632645.patch" [1]
> > > Applying: armv8: ls1012a: Added CSU assignment for USB2
> > >
> > > OR
> > >
> > > Please share if there is a need to rebase them.
> > >
> > > Best Regards,
> > > Rajesh Bhagat
> > >
> > >> --
> > >> Best regards,
> > >> Marek Vasut
> >
> >
> > --
> > Best regards,
> > Marek Vasut
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Re: [U-Boot] Question on Enabling hypervisor mode in u-boot

[Keerthy]

Hi Alex,


On Tuesday 02 August 2016 07:24 AM, Keerthy wrote:



On Tuesday 02 August 2016 03:16 AM, Alexander Graf wrote:



On 01 Aug 2016, at 11:07, Keerthy  wrote:

Hi Alexander,

I am trying to enable hypervisor in u-boot for DRA7(A15 based) family
of SoCs which does not have LPAE support yet.

Is it mandatory for LPAE to be enabled before enabling hypervisor for
A15?


HYP mode shares the same page table layout as the LPAE one. I’m
actually surprised you managed to configure an A15 without LPAE. Are
you sure it doesn’t support it?


I meant CONFIG_LPAE not enabled yet in our defconfig. I was trying to
get hyp mode enabled and saw that enabling LPAE config seemed mandatory
as per your commit.


I am referring 
http://liris.cnrs.fr/~mmrissa/lib/exe/fetch.php?media=armv7-a-r-manual.pdf.


Attrm[3:0] bits for DCACHE_WRITEALLOC, DCACHE_WRITEBACK, 
DCACHE_WRITETHROUGH definitions.


DCACHE_WRITEBACK should have 0x3 << 2 to get 11RW for MAIRn.Attrm[3:0] 
encoding.


Correct me if i am wrong of referring a wrong document.


Regards,
Keerthy






Alex


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Re: [U-Boot] [PATCH 4/5] fsl: csu: add an API to set R/W permission to PCIe

[Zhiqiang Hou]

Hi All,

Drop this patch.

> -Original Message-
> From: Zhiqiang Hou [mailto:zhiqiang@nxp.com]
> Sent: 2016年8月2日 19:03
> To: u-boot@lists.denx.de; albert.u.b...@aribaud.net; york sun
> ; w...@denx.de; Prabhakar Kushwaha
> ; Huan Wang ;
> Mingkai Hu 
> Cc: Yao Yuan ; Qianyu Gong ;
> bmeng...@gmail.com; Shengzhou Liu ; Zhiqiang
> Hou 
> Subject: [PATCH 4/5] fsl: csu: add an API to set R/W permission to PCIe
> 
> From: Hou Zhiqiang 
> 
> Signed-off-by: Hou Zhiqiang 
> ---
> V2
>  - mv disable_pcie_ns_access() to set_pcie_ns_access().
> 
>  .../include/asm/arch-fsl-layerscape/ns_access.h|  1 +
>  board/freescale/common/ns_access.c | 28
> ++
>  include/fsl_csu.h  |  1 +
>  3 files changed, 30 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
> b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
> index db76066..f46f1d8 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
> @@ -6,6 +6,7 @@
> 
>  #ifndef __FSL_NS_ACCESS_H_
>  #define __FSL_NS_ACCESS_H_
> +#include 
> 
>  enum csu_cslx_ind {
>   CSU_CSLX_PCIE2_IO = 0,
> diff --git a/board/freescale/common/ns_access.c
> b/board/freescale/common/ns_access.c
> index c3d7a5e..6d547fa 100644
> --- a/board/freescale/common/ns_access.c
> +++ b/board/freescale/common/ns_access.c
> @@ -8,6 +8,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
> 
>  void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val)  { @@
> -40,3 +41,30 @@ void enable_layerscape_ns_access(void)  {
>   enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));  }
> +
> +void set_pcie_ns_access(int pcie, u16 val) {
> + switch (pcie) {
> +#ifdef CONFIG_PCIE1
> + case PCIE1:
> + set_devices_ns_access(_dev[CSU_CSLX_PCIE1], val);
> + set_devices_ns_access(_dev[CSU_CSLX_PCIE1_IO], val);
> + return;
> +#endif
> +#ifdef CONFIG_PCIE2
> + case PCIE2:
> + set_devices_ns_access(_dev[CSU_CSLX_PCIE2], val);
> + set_devices_ns_access(_dev[CSU_CSLX_PCIE2_IO], val);
> + return;
> +#endif
> +#ifdef CONFIG_PCIE3
> + case PCIE3:
> + set_devices_ns_access(_dev[CSU_CSLX_PCIE3], val);
> + set_devices_ns_access(_dev[CSU_CSLX_PCIE3_IO], val);
> + return;
> +#endif
> + default:
> + debug("The PCIE%d doesn't exist!\n", pcie);
> + return;
> + }
> +}
> diff --git a/include/fsl_csu.h b/include/fsl_csu.h index 57a9985..42ca433
> 100644
> --- a/include/fsl_csu.h
> +++ b/include/fsl_csu.h
> @@ -31,5 +31,6 @@ struct csu_ns_dev {
> 
>  void enable_layerscape_ns_access(void);
>  void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val);
> +void set_pcie_ns_access(int pcie, u16 val);
> 
>  #endif
> --
> 2.1.0.27.g96db324

Thanks,
Zhiqiang
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Re: [U-Boot] [PATCH] mmc: send CMD0 before CMD1 for some MMC cards

[Yangbo Lu]

Thank you, Jaehoon.
So I will send the new version later :)


Best regards,
Yangbo Lu


> -Original Message-
> From: Jaehoon Chung [mailto:jh80.ch...@samsung.com]
> Sent: Tuesday, August 02, 2016 3:13 PM
> To: Yangbo Lu; Ziyuan Xu; u-boot@lists.denx.de; Tom Rini
> Cc: Pantelis Antoniou
> Subject: Re: [U-Boot] [PATCH] mmc: send CMD0 before CMD1 for some MMC
> cards
> 
> On 08/02/2016 04:03 PM, Yangbo Lu wrote:
> > Hi Jaehoon,
> >
> >
> >> -Original Message-
> >> From: Jaehoon Chung [mailto:jh80.ch...@samsung.com]
> >> Sent: Thursday, July 28, 2016 4:40 PM
> >> To: Yangbo Lu; Ziyuan Xu; u-boot@lists.denx.de; Tom Rini
> >> Cc: Pantelis Antoniou
> >> Subject: Re: [U-Boot] [PATCH] mmc: send CMD0 before CMD1 for some MMC
> >> cards
> >>
> >> Hi Yangbo,
> >>
> >> On 07/28/2016 11:45 AM, Yangbo Lu wrote:
> >>> Hi Ziyuan and Jaehoon,
> >>>
> >>>
>  -Original Message-
>  From: Ziyuan Xu [mailto:xzy...@rock-chips.com]
>  Sent: Wednesday, July 27, 2016 9:37 PM
>  To: Jaehoon Chung; Yangbo Lu; u-boot@lists.denx.de; Tom Rini
>  Cc: Pantelis Antoniou
>  Subject: Re: [U-Boot] [PATCH] mmc: send CMD0 before CMD1 for some
>  MMC cards
> 
> 
> 
>  On 2016年07月27日 19:15, Jaehoon Chung wrote:
> > On 07/27/2016 04:28 PM, Yangbo Lu wrote:
> >> Hi Tom,
> >>
> >> Could you help to assign this mmc patch reviewing to right person?
> >> It seems no one had reviewed it for almost half year.
> >>
> >> And another my mmc patch also needs to be reviewed.
> >> I submitted in May. Please help.
> >> http://patchwork.ozlabs.org/patch/624448/
> >>
> >>
> >> Thank you very much.
> >>
> >>
> >> Best regards,
> >> Yangbo Lu
> >>
> >>> -Original Message-
> >>> From: Yangbo Lu [mailto:yangbo...@nxp.com]
> >>> Sent: Wednesday, March 09, 2016 11:00 AM
> >>> To: u-boot@lists.denx.de
> >>> Cc: Pantelis Antoniou; Yangbo Lu
> >>> Subject: [PATCH] mmc: send CMD0 before CMD1 for some MMC cards
> >>>
> >>> When the MMC framework was added in u-boot, the mmc_go_idle was
> >>> added before mmc_send_op_cond_iter in function mmc_send_op_cond
> >>> annotating that some cards seemed to need this. Actually, we
> >>> still need to do this in function mmc_complete_op_cond for those
> cards.
> >>> This has been verified on Micron MTFC4GACAECN eMMC chip.
> > If there is no go_idle(), then what happen?
> > If you share the information more, i can check the more..
>  Sounds interesting, I also want want to know what happen?
>  It seems like you failed in CMD1? The eMMC device was always in
>  busy device within 1 second?
> >>>
> >>> [Lu Yangbo-B47093] This was an issue which our customer reported and
> >> required us to fix in March.
> >>> They used NXP LS1020A platform and Micron MTFC4GACAECN eMMC, and
> >> reported they had to add CMD0 as below.
> >>> Otherwise it couldn’t read OCR.
> >>>
> >>> static int mmc_complete_op_cond(struct mmc *mmc) {
> >>>   struct mmc_cmd cmd;
> >>>   int timeout = 1000;
> >>>   uint start;
> >>>   int err;
> >>>
> >>> #if defined (XXX_CHANGED)
> >>>   // our eMMC chip (Micron MTFC4GACAECN) requires that it be put in
> >> idle mode before
> >>>   // negociating the operating voltage levels.
> >>>   mmc_go_idle(mmc);
> >>> #endif
> >>
> >> Well, it seems to fix workaround. mmc_go_idle() means Device Reset.
> >>
> >> mmc_complete_op_cond() function has added for reducing the booting
> time.
> >> If mmc_go_idle() is added at here, there is no benefit, and it should
> >> be back to old concept.
> >>
> >> I don't agree this patch..now.
> >>
> >
> > [Lu Yangbo-B47093] Did you notice mmc_send_op_cond function? Before
> mmc_send_op_cond_iter sending CMD1, there always was mmc_go_idle.
> > I don’t know why said 'Some cards seem to need this', but it must fix
> some issue.
> >
> > static int mmc_send_op_cond(struct mmc *mmc) {
> > int err, i;
> >
> > /* Some cards seem to need this */
> > mmc_go_idle(mmc);
> >
> > /* Asking to the card its capabilities */
> > for (i = 0; i < 2; i++) {
> > err = mmc_send_op_cond_iter(mmc, i != 0);
> > if (err)
> > return err;
> >
> > /* exit if not busy (flag seems to be inverted) */
> > if (mmc->ocr & OCR_BUSY)
> > break;
> > }
> > mmc->op_cond_pending = 1;
> > return 0;
> > }
> >
> > Now in mmc_complete_op_cond function, there may be the same issue.
> Without the mmc_go_idle, mmc_send_op_cond_iter failed to get ocr.
> > Maybe I should move mmc_go_idle just before mmc_send_op_cond_iter, like
> this.
> >
> > static int mmc_complete_op_cond(struct mmc *mmc) {
> > struct mmc_cmd cmd;
> > int timeout = 1000;
> > uint start;
> > int err;
> >
> > mmc->op_cond_pending = 0;
> > if (!(mmc->ocr & 

Re: [U-Boot] [PATCH] mmc: send CMD0 before CMD1 for some MMC cards

[Yangbo Lu]

Hi Jaehoon,


> -Original Message-
> From: Jaehoon Chung [mailto:jh80.ch...@samsung.com]
> Sent: Thursday, July 28, 2016 4:40 PM
> To: Yangbo Lu; Ziyuan Xu; u-boot@lists.denx.de; Tom Rini
> Cc: Pantelis Antoniou
> Subject: Re: [U-Boot] [PATCH] mmc: send CMD0 before CMD1 for some MMC
> cards
> 
> Hi Yangbo,
> 
> On 07/28/2016 11:45 AM, Yangbo Lu wrote:
> > Hi Ziyuan and Jaehoon,
> >
> >
> >> -Original Message-
> >> From: Ziyuan Xu [mailto:xzy...@rock-chips.com]
> >> Sent: Wednesday, July 27, 2016 9:37 PM
> >> To: Jaehoon Chung; Yangbo Lu; u-boot@lists.denx.de; Tom Rini
> >> Cc: Pantelis Antoniou
> >> Subject: Re: [U-Boot] [PATCH] mmc: send CMD0 before CMD1 for some MMC
> >> cards
> >>
> >>
> >>
> >> On 2016年07月27日 19:15, Jaehoon Chung wrote:
> >>> On 07/27/2016 04:28 PM, Yangbo Lu wrote:
>  Hi Tom,
> 
>  Could you help to assign this mmc patch reviewing to right person?
>  It seems no one had reviewed it for almost half year.
> 
>  And another my mmc patch also needs to be reviewed.
>  I submitted in May. Please help.
>  http://patchwork.ozlabs.org/patch/624448/
> 
> 
>  Thank you very much.
> 
> 
>  Best regards,
>  Yangbo Lu
> 
> > -Original Message-
> > From: Yangbo Lu [mailto:yangbo...@nxp.com]
> > Sent: Wednesday, March 09, 2016 11:00 AM
> > To: u-boot@lists.denx.de
> > Cc: Pantelis Antoniou; Yangbo Lu
> > Subject: [PATCH] mmc: send CMD0 before CMD1 for some MMC cards
> >
> > When the MMC framework was added in u-boot, the mmc_go_idle was
> > added before mmc_send_op_cond_iter in function mmc_send_op_cond
> > annotating that some cards seemed to need this. Actually, we still
> > need to do this in function mmc_complete_op_cond for those cards.
> > This has been verified on Micron MTFC4GACAECN eMMC chip.
> >>> If there is no go_idle(), then what happen?
> >>> If you share the information more, i can check the more..
> >> Sounds interesting, I also want want to know what happen?
> >> It seems like you failed in CMD1? The eMMC device was always in busy
> >> device within 1 second?
> >
> > [Lu Yangbo-B47093] This was an issue which our customer reported and
> required us to fix in March.
> > They used NXP LS1020A platform and Micron MTFC4GACAECN eMMC, and
> reported they had to add CMD0 as below.
> > Otherwise it couldn’t read OCR.
> >
> > static int mmc_complete_op_cond(struct mmc *mmc) {
> > struct mmc_cmd cmd;
> > int timeout = 1000;
> > uint start;
> > int err;
> >
> > #if defined (XXX_CHANGED)
> > // our eMMC chip (Micron MTFC4GACAECN) requires that it be put in
> idle mode before
> > // negociating the operating voltage levels.
> > mmc_go_idle(mmc);
> > #endif
> 
> Well, it seems to fix workaround. mmc_go_idle() means Device Reset.
> 
> mmc_complete_op_cond() function has added for reducing the booting time.
> If mmc_go_idle() is added at here, there is no benefit, and it should be
> back to old concept.
> 
> I don't agree this patch..now.
> 

[Lu Yangbo-B47093] Did you notice mmc_send_op_cond function? Before 
mmc_send_op_cond_iter sending CMD1, there always was mmc_go_idle.
I don’t know why said 'Some cards seem to need this', but it must fix some 
issue.

static int mmc_send_op_cond(struct mmc *mmc)
{
int err, i;

/* Some cards seem to need this */
mmc_go_idle(mmc);

/* Asking to the card its capabilities */
for (i = 0; i < 2; i++) {
err = mmc_send_op_cond_iter(mmc, i != 0);
if (err)
return err;

/* exit if not busy (flag seems to be inverted) */
if (mmc->ocr & OCR_BUSY)
break;
}
mmc->op_cond_pending = 1;
return 0;
}

Now in mmc_complete_op_cond function, there may be the same issue. Without the 
mmc_go_idle, mmc_send_op_cond_iter failed to get ocr.
Maybe I should move mmc_go_idle just before mmc_send_op_cond_iter, like this.

static int mmc_complete_op_cond(struct mmc *mmc)
{
struct mmc_cmd cmd;
int timeout = 1000;
uint start;
int err;

mmc->op_cond_pending = 0;
if (!(mmc->ocr & OCR_BUSY)) {
start = get_timer(0);
while (1) {
/* Some cards seem to need this */
mmc_go_idle(mmc);
err = mmc_send_op_cond_iter(mmc, 1);

If you think it's not proper, do you have any suggestion?
:)

Thanks a lot.

> Best Regards,
> Jaehoon Chung
> 
> >
> >
> > I hadn’t reproduce this to get more details about this issue since I
> didn’t have one this kind eMMC card that time.
> > Thanks.
> >
> >>>
> >>> Best Regards,
> >>> Jaehoon Chung
> >>>
> > Signed-off-by: Yangbo Lu 
> > ---
> >   drivers/mmc/mmc.c | 3 +++
> >   1 file changed, 3 insertions(+)
> >
> > diff --git 

[U-Boot] [PATCH 7/7] net/ethoc: implement MDIO bus and support phylib

[Max Filippov]

Implement MDIO bus read/write functions, initialize the bus and scan for
the PHY when phylib is enabled. Limit PHY speeds to 10/100 Mbps.

Cc: Michal Simek 
Signed-off-by: Max Filippov 
---
 drivers/net/ethoc.c | 152 +---
 1 file changed, 146 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index fa623d5..fe04396 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -181,6 +181,11 @@ struct ethoc {
void __iomem *iobase;
void __iomem *packet;
phys_addr_t packet_phys;
+
+#ifdef CONFIG_PHYLIB
+   struct mii_dev *bus;
+   struct phy_device *phydev;
+#endif
 };
 
 /**
@@ -319,13 +324,31 @@ static int ethoc_reset(struct ethoc *priv)
 
 static int ethoc_init_common(struct ethoc *priv)
 {
+   int ret = 0;
+
priv->num_tx = 1;
priv->num_rx = PKTBUFSRX;
ethoc_write(priv, TX_BD_NUM, priv->num_tx);
ethoc_init_ring(priv);
ethoc_reset(priv);
 
-   return 0;
+#ifdef CONFIG_PHYLIB
+   ret = phy_startup(priv->phydev);
+   if (ret) {
+   printf("Could not initialize PHY %s\n",
+  priv->phydev->dev->name);
+   return ret;
+   }
+#endif
+   return ret;
+}
+
+static void ethoc_stop_common(struct ethoc *priv)
+{
+   ethoc_disable_rx_and_tx(priv);
+#ifdef CONFIG_PHYLIB
+   phy_shutdown(priv->phydev);
+#endif
 }
 
 static int ethoc_update_rx_stats(struct ethoc_bd *bd)
@@ -509,13 +532,119 @@ static int ethoc_free_pkt_common(struct ethoc *priv)
return 0;
 }
 
+#ifdef CONFIG_PHYLIB
+
+static int ethoc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+   struct ethoc *priv = bus->priv;
+   ulong tmo = get_timer(0);
+
+   ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(addr, reg));
+   ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
+
+   while (get_timer(tmo) < CONFIG_SYS_HZ) {
+   u32 status = ethoc_read(priv, MIISTATUS);
+
+   if (!(status & MIISTATUS_BUSY)) {
+   u32 data = ethoc_read(priv, MIIRX_DATA);
+
+   /* reset MII command register */
+   ethoc_write(priv, MIICOMMAND, 0);
+   return data;
+   }
+   }
+   return -ETIMEDOUT;
+}
+
+static int ethoc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+   u16 val)
+{
+   struct ethoc *priv = bus->priv;
+   ulong tmo = get_timer(0);
+
+   ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(addr, reg));
+   ethoc_write(priv, MIITX_DATA, val);
+   ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
+
+   while (get_timer(tmo) < CONFIG_SYS_HZ) {
+   u32 stat = ethoc_read(priv, MIISTATUS);
+
+   if (!(stat & MIISTATUS_BUSY)) {
+   /* reset MII command register */
+   ethoc_write(priv, MIICOMMAND, 0);
+   return 0;
+   }
+   }
+   return -ETIMEDOUT;
+}
+
+static int ethoc_mdio_init(const char *name, struct ethoc *priv)
+{
+   struct mii_dev *bus = mdio_alloc();
+   int ret;
+
+   if (!bus) {
+   printf("Failed to allocate MDIO bus\n");
+   return -ENOMEM;
+   }
+
+   bus->read = ethoc_mdio_read;
+   bus->write = ethoc_mdio_write;
+   snprintf(bus->name, sizeof(bus->name), "%s", name);
+   bus->priv = priv;
+
+   ret = mdio_register(bus);
+   if (ret < 0)
+   return ret;
+
+   priv->bus = miiphy_get_dev_by_name(name);
+   return 0;
+}
+
+static int ethoc_phy_init(struct ethoc *priv, void *dev)
+{
+   struct phy_device *phydev;
+   int mask = 0x;
+
+#ifdef CONFIG_PHY_ADDR
+   mask = 1 << CONFIG_PHY_ADDR;
+#endif
+
+   phydev = phy_find_by_mask(priv->bus, mask, PHY_INTERFACE_MODE_MII);
+   if (!phydev)
+   return -ENODEV;
+
+   phy_connect_dev(phydev, dev);
+
+   phydev->supported &= PHY_BASIC_FEATURES;
+   phydev->advertising = phydev->supported;
+
+   priv->phydev = phydev;
+   phy_config(phydev);
+
+   return 0;
+}
+
+#else
+
+static inline int ethoc_mdio_init(const char *name, struct ethoc *priv)
+{
+   return 0;
+}
+
+static inline int ethoc_phy_init(struct ethoc *priv, void *dev)
+{
+   return 0;
+}
+
+#endif
+
 #ifndef CONFIG_DM_ETH
 
 static int ethoc_init(struct eth_device *dev, bd_t *bd)
 {
struct ethoc *priv = (struct ethoc *)dev->priv;
 
-   priv->iobase = ioremap(dev->iobase, ETHOC_IOSIZE);
return ethoc_init_common(priv);
 }
 
@@ -534,7 +663,7 @@ static int ethoc_send(struct eth_device *dev, void *packet, 
int length)
 
 static void ethoc_halt(struct eth_device *dev)
 {
-   ethoc_disable_rx_and_tx(dev->priv);
+   ethoc_stop_common(dev->priv);
 }
 
 static int ethoc_recv(struct eth_device *dev)
@@ -584,6 

[U-Boot] [PATCH 1/7] net/ethoc: add Kconfig entry for the driver

[Max Filippov]

Add Kconfig entry for the driver, remove #define CONFIG_ETHOC from the
only board configuration that uses it and put it into that board's
defconfig.

Cc: Stefan Kristiansson 
Signed-off-by: Max Filippov 
---
 configs/openrisc-generic_defconfig | 2 ++
 drivers/net/Kconfig| 5 +
 include/configs/openrisc-generic.h | 1 -
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/configs/openrisc-generic_defconfig 
b/configs/openrisc-generic_defconfig
index 14923c0..5bc81cc 100644
--- a/configs/openrisc-generic_defconfig
+++ b/configs/openrisc-generic_defconfig
@@ -6,5 +6,7 @@ CONFIG_TARGET_OPENRISC_GENERIC=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_NETDEVICES=y
+CONFIG_ETHOC=y
 CONFIG_SYS_NS16550=y
 # CONFIG_AUTOBOOT is not set
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 88d8e83..be3ed73 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -124,6 +124,11 @@ config ETH_DESIGNWARE
  100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to
  provide the PHY (physical media interface).
 
+config ETHOC
+   bool "OpenCores 10/100 Mbps Ethernet MAC"
+   help
+ This MAC is present in OpenRISC and Xtensa XTFPGA boards.
+
 config MVPP2
bool "Marvell Armada 375 network interface support"
depends on ARMADA_375
diff --git a/include/configs/openrisc-generic.h 
b/include/configs/openrisc-generic.h
index 913256a..227c0ca 100644
--- a/include/configs/openrisc-generic.h
+++ b/include/configs/openrisc-generic.h
@@ -44,7 +44,6 @@
 /*
  * Ethernet
  */
-#define CONFIG_ETHOC
 #define CONFIG_SYS_ETHOC_BASE  0x9200
 
 #define CONFIG_BOOTFILE"boot.img"
-- 
2.1.4

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[U-Boot] [PATCH 5/7] net/ethoc: don't mix virtual and physical addresses

[Max Filippov]

Addresses used in buffer descriptors and passed in platform data or
device tree are physical. Addresses used by CPU to access packet data
and registers are virtual. Don't mix these addresses and use virt_to_phys
for translation.

Signed-off-by: Max Filippov 
---
 drivers/net/ethoc.c | 23 +--
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index 8cb15c7..e25dd1b 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -255,6 +255,7 @@ static int ethoc_init_ring(struct ethoc *priv)
 
/* setup transmission buffers */
bd.stat = TX_BD_IRQ | TX_BD_CRC;
+   bd.addr = 0;
 
for (i = 0; i < priv->num_tx; i++) {
if (i == priv->num_tx - 1)
@@ -266,11 +267,12 @@ static int ethoc_init_ring(struct ethoc *priv)
bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
 
for (i = 0; i < priv->num_rx; i++) {
-   bd.addr = (u32)net_rx_packets[i];
+   bd.addr = virt_to_phys(net_rx_packets[i]);
if (i == priv->num_rx - 1)
bd.stat |= RX_BD_WRAP;
 
-   flush_dcache_range(bd.addr, bd.addr + PKTSIZE_ALIGN);
+   flush_dcache_range((ulong)net_rx_packets[i],
+  (ulong)net_rx_packets[i] + PKTSIZE_ALIGN);
ethoc_write_bd(priv, priv->num_tx + i, );
}
 
@@ -351,10 +353,10 @@ static int ethoc_update_rx_stats(struct ethoc_bd *bd)
 
 static int ethoc_rx_common(struct ethoc *priv, uchar **packetp)
 {
-   u32 entry;
struct ethoc_bd bd;
+   u32 i = priv->cur_rx % priv->num_rx;
+   u32 entry = priv->num_tx + i;
 
-   entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
ethoc_read_bd(priv, entry, );
if (bd.stat & RX_BD_EMPTY)
return -EAGAIN;
@@ -365,7 +367,7 @@ static int ethoc_rx_common(struct ethoc *priv, uchar 
**packetp)
int size = bd.stat >> 16;
 
size -= 4;  /* strip the CRC */
-   *packetp = (void *)bd.addr;
+   *packetp = net_rx_packets[i];
return size;
} else {
return 0;
@@ -428,9 +430,9 @@ static int ethoc_send_common(struct ethoc *priv, void 
*packet, int length)
bd.stat |= TX_BD_PAD;
else
bd.stat &= ~TX_BD_PAD;
-   bd.addr = (u32)packet;
+   bd.addr = virt_to_phys(packet);
 
-   flush_dcache_range(bd.addr, bd.addr + length);
+   flush_dcache_range((ulong)packet, (ulong)packet + length);
bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
bd.stat |= TX_BD_LEN(length);
ethoc_write_bd(priv, entry, );
@@ -463,14 +465,15 @@ static int ethoc_send_common(struct ethoc *priv, void 
*packet, int length)
 
 static int ethoc_free_pkt_common(struct ethoc *priv)
 {
-   u32 entry;
struct ethoc_bd bd;
+   u32 i = priv->cur_rx % priv->num_rx;
+   u32 entry = priv->num_tx + i;
 
-   entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
ethoc_read_bd(priv, entry, );
 
/* clear the buffer descriptor so it can be reused */
-   flush_dcache_range(bd.addr, bd.addr + PKTSIZE_ALIGN);
+   flush_dcache_range((ulong)net_rx_packets[i],
+  (ulong)net_rx_packets[i] + PKTSIZE_ALIGN);
bd.stat &= ~RX_BD_STATS;
bd.stat |= RX_BD_EMPTY;
ethoc_write_bd(priv, entry, );
-- 
2.1.4

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[U-Boot] [PATCH 6/7] net/ethoc: support private memory configurations

[Max Filippov]

The ethoc device can be configured to have a private memory region
instead of having access to the main memory. In that case egress packets
must be copied into that memory for transmission and pointers to that
memory need to be passed to net_process_received_packet or returned from
the recv callback.

Signed-off-by: Max Filippov 
---
 drivers/net/ethoc.c  | 46 
 include/dm/platform_data/net_ethoc.h |  1 +
 2 files changed, 42 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index e25dd1b..fa623d5 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -179,6 +179,8 @@ struct ethoc {
u32 num_rx;
u32 cur_rx;
void __iomem *iobase;
+   void __iomem *packet;
+   phys_addr_t packet_phys;
 };
 
 /**
@@ -247,6 +249,7 @@ static inline void ethoc_disable_rx_and_tx(struct ethoc 
*priv)
 static int ethoc_init_ring(struct ethoc *priv)
 {
struct ethoc_bd bd;
+   phys_addr_t addr = priv->packet_phys;
int i;
 
priv->cur_tx = 0;
@@ -258,6 +261,10 @@ static int ethoc_init_ring(struct ethoc *priv)
bd.addr = 0;
 
for (i = 0; i < priv->num_tx; i++) {
+   if (addr) {
+   bd.addr = addr;
+   addr += PKTSIZE_ALIGN;
+   }
if (i == priv->num_tx - 1)
bd.stat |= TX_BD_WRAP;
 
@@ -267,7 +274,12 @@ static int ethoc_init_ring(struct ethoc *priv)
bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
 
for (i = 0; i < priv->num_rx; i++) {
-   bd.addr = virt_to_phys(net_rx_packets[i]);
+   if (addr) {
+   bd.addr = addr;
+   addr += PKTSIZE_ALIGN;
+   } else {
+   bd.addr = virt_to_phys(net_rx_packets[i]);
+   }
if (i == priv->num_rx - 1)
bd.stat |= RX_BD_WRAP;
 
@@ -367,7 +379,10 @@ static int ethoc_rx_common(struct ethoc *priv, uchar 
**packetp)
int size = bd.stat >> 16;
 
size -= 4;  /* strip the CRC */
-   *packetp = net_rx_packets[i];
+   if (priv->packet)
+   *packetp = priv->packet + entry * PKTSIZE_ALIGN;
+   else
+   *packetp = net_rx_packets[i];
return size;
} else {
return 0;
@@ -430,8 +445,15 @@ static int ethoc_send_common(struct ethoc *priv, void 
*packet, int length)
bd.stat |= TX_BD_PAD;
else
bd.stat &= ~TX_BD_PAD;
-   bd.addr = virt_to_phys(packet);
 
+   if (priv->packet) {
+   void *p = priv->packet + entry * PKTSIZE_ALIGN;
+
+   memcpy(p, packet, length);
+   packet = p;
+   } else {
+   bd.addr = virt_to_phys(packet);
+   }
flush_dcache_range((ulong)packet, (ulong)packet + length);
bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
bd.stat |= TX_BD_LEN(length);
@@ -468,12 +490,17 @@ static int ethoc_free_pkt_common(struct ethoc *priv)
struct ethoc_bd bd;
u32 i = priv->cur_rx % priv->num_rx;
u32 entry = priv->num_tx + i;
+   void *src;
 
ethoc_read_bd(priv, entry, );
 
+   if (priv->packet)
+   src = priv->packet + entry * PKTSIZE_ALIGN;
+   else
+   src = net_rx_packets[i];
/* clear the buffer descriptor so it can be reused */
-   flush_dcache_range((ulong)net_rx_packets[i],
-  (ulong)net_rx_packets[i] + PKTSIZE_ALIGN);
+   flush_dcache_range((ulong)src,
+  (ulong)src + PKTSIZE_ALIGN);
bd.stat &= ~RX_BD_STATS;
bd.stat |= RX_BD_EMPTY;
ethoc_write_bd(priv, entry, );
@@ -606,8 +633,12 @@ static void ethoc_stop(struct udevice *dev)
 static int ethoc_ofdata_to_platdata(struct udevice *dev)
 {
struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
+   fdt_addr_t addr;
 
pdata->eth_pdata.iobase = dev_get_addr(dev);
+   addr = dev_get_addr_index(dev, 1);
+   if (addr != FDT_ADDR_T_NONE)
+   pdata->packet_base = addr;
return 0;
 }
 
@@ -617,6 +648,11 @@ static int ethoc_probe(struct udevice *dev)
struct ethoc *priv = dev_get_priv(dev);
 
priv->iobase = ioremap(pdata->eth_pdata.iobase, ETHOC_IOSIZE);
+   if (pdata->packet_base) {
+   priv->packet_phys = pdata->packet_base;
+   priv->packet = ioremap(pdata->packet_base,
+  (1 + PKTBUFSRX) * PKTSIZE_ALIGN);
+   }
return 0;
 }
 
diff --git a/include/dm/platform_data/net_ethoc.h 
b/include/dm/platform_data/net_ethoc.h
index 1d8c73c..3f94bde 100644
--- a/include/dm/platform_data/net_ethoc.h
+++ b/include/dm/platform_data/net_ethoc.h
@@ -13,6 +13,7 @@
 
 struct ethoc_eth_pdata {
struct 

[U-Boot] [PATCH 4/7] net/ethoc: support device tree

[Max Filippov]

Add .of_match table and .ofdata_to_platdata callback to allow for ethoc
device configuration from the device tree.

Signed-off-by: Max Filippov 
---
 drivers/net/ethoc.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index 0225595..8cb15c7 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -600,6 +600,14 @@ static void ethoc_stop(struct udevice *dev)
ethoc_disable_rx_and_tx(priv);
 }
 
+static int ethoc_ofdata_to_platdata(struct udevice *dev)
+{
+   struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
+
+   pdata->eth_pdata.iobase = dev_get_addr(dev);
+   return 0;
+}
+
 static int ethoc_probe(struct udevice *dev)
 {
struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
@@ -626,9 +634,16 @@ static const struct eth_ops ethoc_ops = {
.write_hwaddr   = ethoc_write_hwaddr,
 };
 
+static const struct udevice_id ethoc_ids[] = {
+   { .compatible = "opencores,ethoc" },
+   { }
+};
+
 U_BOOT_DRIVER(ethoc) = {
.name   = "ethoc",
.id = UCLASS_ETH,
+   .of_match   = ethoc_ids,
+   .ofdata_to_platdata = ethoc_ofdata_to_platdata,
.probe  = ethoc_probe,
.remove = ethoc_remove,
.ops= _ops,
-- 
2.1.4

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[U-Boot] [PATCH 3/7] net/ethoc: add CONFIG_DM_ETH support

[Max Filippov]

Extract reusable parts from ethoc_init, ethoc_set_mac_address,
ethoc_send and ethoc_receive, move the rest under #ifdef CONFIG_DM_ETH.
Add U_BOOT_DRIVER, eth_ops structure and implement required methods.

Signed-off-by: Max Filippov 
---
 drivers/net/ethoc.c  | 221 +++
 include/dm/platform_data/net_ethoc.h |  20 
 2 files changed, 194 insertions(+), 47 deletions(-)
 create mode 100644 include/dm/platform_data/net_ethoc.h

diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index f5bd1ab..0225595 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -5,13 +5,14 @@
  * Copyright (C) 2008-2009 Avionic Design GmbH
  *   Thierry Reding 
  * Copyright (C) 2010 Thomas Chou 
+ * Copyright (C) 2016 Cadence Design Systems Inc.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * SPDX-License-Identifier:GPL-2.0
  */
 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -216,11 +217,8 @@ static inline void ethoc_write_bd(struct ethoc *priv, int 
index,
ethoc_write(priv, offset + 4, bd->addr);
 }
 
-static int ethoc_set_mac_address(struct eth_device *dev)
+static int ethoc_set_mac_address(struct ethoc *priv, u8 *mac)
 {
-   struct ethoc *priv = (struct ethoc *)dev->priv;
-   u8 *mac = dev->enetaddr;
-
ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
(mac[4] << 8) | (mac[5] << 0));
ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
@@ -305,11 +303,8 @@ static int ethoc_reset(struct ethoc *priv)
return 0;
 }
 
-static int ethoc_init(struct eth_device *dev, bd_t * bd)
+static int ethoc_init_common(struct ethoc *priv)
 {
-   struct ethoc *priv = (struct ethoc *)dev->priv;
-   printf("ethoc\n");
-
priv->num_tx = 1;
priv->num_rx = PKTBUFSRX;
ethoc_write(priv, TX_BD_NUM, priv->num_tx);
@@ -354,36 +349,43 @@ static int ethoc_update_rx_stats(struct ethoc_bd *bd)
return ret;
 }
 
-static int ethoc_rx(struct ethoc *priv, int limit)
+static int ethoc_rx_common(struct ethoc *priv, uchar **packetp)
 {
-   int count;
-
-   for (count = 0; count < limit; ++count) {
-   u32 entry;
-   struct ethoc_bd bd;
+   u32 entry;
+   struct ethoc_bd bd;
 
-   entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
-   ethoc_read_bd(priv, entry, );
-   if (bd.stat & RX_BD_EMPTY)
-   break;
+   entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
+   ethoc_read_bd(priv, entry, );
+   if (bd.stat & RX_BD_EMPTY)
+   return -EAGAIN;
+
+   debug("%s(): RX buffer %d, %x received\n",
+ __func__, priv->cur_rx, bd.stat);
+   if (ethoc_update_rx_stats() == 0) {
+   int size = bd.stat >> 16;
+
+   size -= 4;  /* strip the CRC */
+   *packetp = (void *)bd.addr;
+   return size;
+   } else {
+   return 0;
+   }
+}
 
-   debug("%s(): RX buffer %d, %x received\n",
- __func__, priv->cur_rx, bd.stat);
-   if (ethoc_update_rx_stats() == 0) {
-   int size = bd.stat >> 16;
-   size -= 4;  /* strip the CRC */
-   net_process_received_packet((void *)bd.addr, size);
-   }
+static int ethoc_recv_common(struct ethoc *priv)
+{
+   u32 pending;
 
-   /* clear the buffer descriptor so it can be reused */
-   flush_dcache_range(bd.addr, bd.addr + PKTSIZE_ALIGN);
-   bd.stat &= ~RX_BD_STATS;
-   bd.stat |= RX_BD_EMPTY;
-   ethoc_write_bd(priv, entry, );
-   priv->cur_rx++;
+   pending = ethoc_read(priv, INT_SOURCE);
+   ethoc_ack_irq(priv, pending);
+   if (pending & INT_MASK_BUSY)
+   debug("%s(): packet dropped\n", __func__);
+   if (pending & INT_MASK_RX) {
+   debug("%s(): rx irq\n", __func__);
+   return 1;
}
 
-   return count;
+   return 0;
 }
 
 static int ethoc_update_tx_stats(struct ethoc_bd *bd)
@@ -413,9 +415,8 @@ static void ethoc_tx(struct ethoc *priv)
(void)ethoc_update_tx_stats();
 }
 
-static int ethoc_send(struct eth_device *dev, void *packet, int length)
+static int ethoc_send_common(struct ethoc *priv, void *packet, int length)
 {
-   struct ethoc *priv = (struct ethoc *)dev->priv;
struct ethoc_bd bd;
u32 entry;
u32 pending;
@@ -460,6 +461,47 @@ static int ethoc_send(struct eth_device *dev, void 
*packet, int length)
return 0;
 }
 
+static int ethoc_free_pkt_common(struct ethoc *priv)
+{
+   u32 entry;
+   

[U-Boot] [PATCH 0/7] net/ethoc improvements

[Max Filippov]

Hello,

this series does the following improvements to the OpenCores 10/100 Mbps
driver:
- add Kconfig symbol for the driver;
- add DM_ETH support;
- add device tree support;
- add optional phylib support;
- add support for configurations with private packet memory;
- clean up virtual/physical address usage.

Please review.

Max Filippov (7):
  net/ethoc: add Kconfig entry for the driver
  net/ethoc: use priv instead of dev internally
  net/ethoc: add CONFIG_DM_ETH support
  net/ethoc: support device tree
  net/ethoc: don't mix virtual and physical addresses
  net/ethoc: support private memory configurations
  net/ethoc: implement MDIO bus and support phylib

 configs/openrisc-generic_defconfig   |   2 +
 drivers/net/Kconfig  |   5 +
 drivers/net/ethoc.c  | 522 ---
 include/configs/openrisc-generic.h   |   1 -
 include/dm/platform_data/net_ethoc.h |  21 ++
 5 files changed, 450 insertions(+), 101 deletions(-)
 create mode 100644 include/dm/platform_data/net_ethoc.h

-- 
2.1.4

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[U-Boot] [PATCH 2/7] net/ethoc: use priv instead of dev internally

[Max Filippov]

Don't use physical base address of registers directly, ioremap it first.
Save pointer in private struct ethoc and use that struct in all internal
functions.

Signed-off-by: Max Filippov 
---
 drivers/net/ethoc.c | 111 ++--
 1 file changed, 56 insertions(+), 55 deletions(-)

diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index edb3c80..f5bd1ab 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -12,11 +12,10 @@
  */
 
 #include 
-#include 
+#include 
 #include 
 #include 
 #include 
-#include 
 #include 
 
 /* register offsets */
@@ -162,6 +161,7 @@
 #defineETHOC_BD_BASE   0x400
 #defineETHOC_TIMEOUT   (HZ / 2)
 #defineETHOC_MII_TIMEOUT   (1 + (HZ / 5))
+#defineETHOC_IOSIZE0x54
 
 /**
  * struct ethoc - driver-private device structure
@@ -177,6 +177,7 @@ struct ethoc {
u32 dty_tx;
u32 num_rx;
u32 cur_rx;
+   void __iomem *iobase;
 };
 
 /**
@@ -189,64 +190,64 @@ struct ethoc_bd {
u32 addr;
 };
 
-static inline u32 ethoc_read(struct eth_device *dev, size_t offset)
+static inline u32 ethoc_read(struct ethoc *priv, size_t offset)
 {
-   return readl(dev->iobase + offset);
+   return readl(priv->iobase + offset);
 }
 
-static inline void ethoc_write(struct eth_device *dev, size_t offset, u32 data)
+static inline void ethoc_write(struct ethoc *priv, size_t offset, u32 data)
 {
-   writel(data, dev->iobase + offset);
+   writel(data, priv->iobase + offset);
 }
 
-static inline void ethoc_read_bd(struct eth_device *dev, int index,
+static inline void ethoc_read_bd(struct ethoc *priv, int index,
 struct ethoc_bd *bd)
 {
size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
-   bd->stat = ethoc_read(dev, offset + 0);
-   bd->addr = ethoc_read(dev, offset + 4);
+   bd->stat = ethoc_read(priv, offset + 0);
+   bd->addr = ethoc_read(priv, offset + 4);
 }
 
-static inline void ethoc_write_bd(struct eth_device *dev, int index,
+static inline void ethoc_write_bd(struct ethoc *priv, int index,
  const struct ethoc_bd *bd)
 {
size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
-   ethoc_write(dev, offset + 0, bd->stat);
-   ethoc_write(dev, offset + 4, bd->addr);
+   ethoc_write(priv, offset + 0, bd->stat);
+   ethoc_write(priv, offset + 4, bd->addr);
 }
 
 static int ethoc_set_mac_address(struct eth_device *dev)
 {
+   struct ethoc *priv = (struct ethoc *)dev->priv;
u8 *mac = dev->enetaddr;
 
-   ethoc_write(dev, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
+   ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
(mac[4] << 8) | (mac[5] << 0));
-   ethoc_write(dev, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
+   ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
return 0;
 }
 
-static inline void ethoc_ack_irq(struct eth_device *dev, u32 mask)
+static inline void ethoc_ack_irq(struct ethoc *priv, u32 mask)
 {
-   ethoc_write(dev, INT_SOURCE, mask);
+   ethoc_write(priv, INT_SOURCE, mask);
 }
 
-static inline void ethoc_enable_rx_and_tx(struct eth_device *dev)
+static inline void ethoc_enable_rx_and_tx(struct ethoc *priv)
 {
-   u32 mode = ethoc_read(dev, MODER);
+   u32 mode = ethoc_read(priv, MODER);
mode |= MODER_RXEN | MODER_TXEN;
-   ethoc_write(dev, MODER, mode);
+   ethoc_write(priv, MODER, mode);
 }
 
-static inline void ethoc_disable_rx_and_tx(struct eth_device *dev)
+static inline void ethoc_disable_rx_and_tx(struct ethoc *priv)
 {
-   u32 mode = ethoc_read(dev, MODER);
+   u32 mode = ethoc_read(priv, MODER);
mode &= ~(MODER_RXEN | MODER_TXEN);
-   ethoc_write(dev, MODER, mode);
+   ethoc_write(priv, MODER, mode);
 }
 
-static int ethoc_init_ring(struct eth_device *dev)
+static int ethoc_init_ring(struct ethoc *priv)
 {
-   struct ethoc *priv = (struct ethoc *)dev->priv;
struct ethoc_bd bd;
int i;
 
@@ -261,7 +262,7 @@ static int ethoc_init_ring(struct eth_device *dev)
if (i == priv->num_tx - 1)
bd.stat |= TX_BD_WRAP;
 
-   ethoc_write_bd(dev, i, );
+   ethoc_write_bd(priv, i, );
}
 
bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
@@ -272,35 +273,35 @@ static int ethoc_init_ring(struct eth_device *dev)
bd.stat |= RX_BD_WRAP;
 
flush_dcache_range(bd.addr, bd.addr + PKTSIZE_ALIGN);
-   ethoc_write_bd(dev, priv->num_tx + i, );
+   ethoc_write_bd(priv, priv->num_tx + i, );
}
 
return 0;
 }
 
-static int ethoc_reset(struct eth_device *dev)
+static int ethoc_reset(struct ethoc *priv)
 {
u32 mode;
 
/* TODO: reset controller? */
 
-   ethoc_disable_rx_and_tx(dev);
+   

[U-Boot] [PATCHv2 3/5] fsl: csu: add an API to set individual device access permission

[Zhiqiang Hou]

From: Hou Zhiqiang 

Add this API to make the individual device is able to be set to
the specified permission.

Signed-off-by: Hou Zhiqiang 
---
V2
 - no change

 board/freescale/common/ns_access.c | 34 --
 include/fsl_csu.h  |  1 +
 2 files changed, 21 insertions(+), 14 deletions(-)

diff --git a/board/freescale/common/ns_access.c 
b/board/freescale/common/ns_access.c
index d8d16c5..c3d7a5e 100644
--- a/board/freescale/common/ns_access.c
+++ b/board/freescale/common/ns_access.c
@@ -9,25 +9,31 @@
 #include 
 #include 
 
-static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
+void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val)
 {
u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
u32 *reg;
-   uint32_t val;
-   int i;
+   uint32_t tmp;
 
-   for (i = 0; i < num; i++) {
-   reg = base + ns_dev[i].ind / 2;
-   val = in_be32(reg);
-   if (ns_dev[i].ind % 2 == 0) {
-   val &= 0x;
-   val |= ns_dev[i].val << 16;
-   } else {
-   val &= 0x;
-   val |= ns_dev[i].val;
-   }
-   out_be32(reg, val);
+   reg = base + ns_dev->ind / 2;
+   tmp = in_be32(reg);
+   if (ns_dev->ind % 2 == 0) {
+   tmp &= 0x;
+   tmp |= val << 16;
+   } else {
+   tmp &= 0x;
+   tmp |= val;
}
+
+   out_be32(reg, tmp);
+}
+
+static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
+{
+   int i;
+
+   for (i = 0; i < num; i++)
+   set_devices_ns_access(ns_dev + i, ns_dev[i].val);
 }
 
 void enable_layerscape_ns_access(void)
diff --git a/include/fsl_csu.h b/include/fsl_csu.h
index f4d97fb..57a9985 100644
--- a/include/fsl_csu.h
+++ b/include/fsl_csu.h
@@ -30,5 +30,6 @@ struct csu_ns_dev {
 };
 
 void enable_layerscape_ns_access(void);
+void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val);
 
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 4/5] fsl: csu: add an API to set R/W permission to PCIe

[Zhiqiang Hou]

From: Hou Zhiqiang 

Signed-off-by: Hou Zhiqiang 
---
V2
 - mv disable_pcie_ns_access() to set_pcie_ns_access().

 .../include/asm/arch-fsl-layerscape/ns_access.h|  1 +
 board/freescale/common/ns_access.c | 28 ++
 include/fsl_csu.h  |  1 +
 3 files changed, 30 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h 
b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index db76066..f46f1d8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -6,6 +6,7 @@
 
 #ifndef __FSL_NS_ACCESS_H_
 #define __FSL_NS_ACCESS_H_
+#include 
 
 enum csu_cslx_ind {
CSU_CSLX_PCIE2_IO = 0,
diff --git a/board/freescale/common/ns_access.c 
b/board/freescale/common/ns_access.c
index c3d7a5e..6d547fa 100644
--- a/board/freescale/common/ns_access.c
+++ b/board/freescale/common/ns_access.c
@@ -8,6 +8,7 @@
 #include 
 #include 
 #include 
+#include 
 
 void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val)
 {
@@ -40,3 +41,30 @@ void enable_layerscape_ns_access(void)
 {
enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
 }
+
+void set_pcie_ns_access(int pcie, u16 val)
+{
+   switch (pcie) {
+#ifdef CONFIG_PCIE1
+   case PCIE1:
+   set_devices_ns_access(_dev[CSU_CSLX_PCIE1], val);
+   set_devices_ns_access(_dev[CSU_CSLX_PCIE1_IO], val);
+   return;
+#endif
+#ifdef CONFIG_PCIE2
+   case PCIE2:
+   set_devices_ns_access(_dev[CSU_CSLX_PCIE2], val);
+   set_devices_ns_access(_dev[CSU_CSLX_PCIE2_IO], val);
+   return;
+#endif
+#ifdef CONFIG_PCIE3
+   case PCIE3:
+   set_devices_ns_access(_dev[CSU_CSLX_PCIE3], val);
+   set_devices_ns_access(_dev[CSU_CSLX_PCIE3_IO], val);
+   return;
+#endif
+   default:
+   debug("The PCIE%d doesn't exist!\n", pcie);
+   return;
+   }
+}
diff --git a/include/fsl_csu.h b/include/fsl_csu.h
index 57a9985..42ca433 100644
--- a/include/fsl_csu.h
+++ b/include/fsl_csu.h
@@ -31,5 +31,6 @@ struct csu_ns_dev {
 
 void enable_layerscape_ns_access(void);
 void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val);
+void set_pcie_ns_access(int pcie, u16 val);
 
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCHv2 4/5] fsl: csu: add an API to set R/W permission to PCIe

[Zhiqiang Hou]

From: Hou Zhiqiang 

Signed-off-by: Hou Zhiqiang 
---
 .../include/asm/arch-fsl-layerscape/ns_access.h|  1 +
 board/freescale/common/ns_access.c | 28 ++
 include/fsl_csu.h  |  1 +
 3 files changed, 30 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h 
b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index db76066..f46f1d8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -6,6 +6,7 @@
 
 #ifndef __FSL_NS_ACCESS_H_
 #define __FSL_NS_ACCESS_H_
+#include 
 
 enum csu_cslx_ind {
CSU_CSLX_PCIE2_IO = 0,
diff --git a/board/freescale/common/ns_access.c 
b/board/freescale/common/ns_access.c
index c3d7a5e..81c9211 100644
--- a/board/freescale/common/ns_access.c
+++ b/board/freescale/common/ns_access.c
@@ -8,6 +8,7 @@
 #include 
 #include 
 #include 
+#include 
 
 void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val)
 {
@@ -40,3 +41,30 @@ void enable_layerscape_ns_access(void)
 {
enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
 }
+
+void set_pcie_ns_access(int pcie, u16 val)
+{
+   switch (pcie) {
+#ifdef CONFIG_PCIE1
+   case PCIE1:
+   set_devices_ns_access(_dev[CSU_CSLX_PCIE1], val);
+   set_devices_ns_access(_dev[CSU_CSLX_PCIE1_IO], val);
+   return;
+#endif
+#ifdef CONFIG_PCIE2
+   case PCIE2:
+   set_devices_ns_access(_dev[CSU_CSLX_PCIE2], val);
+   set_devices_ns_access(_dev[CSU_CSLX_PCIE2_IO], val);
+   return;
+#endif
+#ifdef CONFIG_PCIE3
+   case PCIE3:
+   set_devices_ns_access(_dev[CSU_CSLX_PCIE3], val);
+   set_devices_ns_access(_dev[CSU_CSLX_PCIE3_IO], val);
+   return;
+#endif
+   default:
+   debug("The PCIE%d doesn't exist!\n", pcie);
+   return;
+   }
+}
diff --git a/include/fsl_csu.h b/include/fsl_csu.h
index 57a9985..8582ac0 100644
--- a/include/fsl_csu.h
+++ b/include/fsl_csu.h
@@ -31,5 +31,6 @@ struct csu_ns_dev {
 
 void enable_layerscape_ns_access(void);
 void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val);
+void set_pcie_ns_access(int pcie, u16 val);
 
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCHv2 5/5] fsl-layerscape: Add workaround for PCIe erratum A010315

[Zhiqiang Hou]

From: Hou Zhiqiang 

As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including its CCSR, IO space and memory space according to the
serders protocol field of RCW.

Signed-off-by: Hou Zhiqiang 
---
Tested on LS1043A RDB board.

V2
 - no change

 arch/arm/cpu/armv7/ls102xa/soc.c  | 14 ++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c   | 16 
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  2 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h|  4 
 arch/arm/include/asm/arch-ls102xa/config.h|  1 +
 arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h   |  4 
 board/freescale/ls1012aqds/ls1012aqds.c   |  4 
 board/freescale/ls1012ardb/ls1012ardb.c   |  4 
 board/freescale/ls1021aqds/ls1021aqds.c   |  4 
 board/freescale/ls1021atwr/ls1021atwr.c   |  4 
 board/freescale/ls1043aqds/ls1043aqds.c   |  4 
 board/freescale/ls1043ardb/ls1043ardb.c   |  4 
 12 files changed, 65 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 4c93ab7..31f00cb 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -59,6 +60,19 @@ unsigned int get_soc_major_rev(void)
return major;
 }
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+void erratum_a010315(void)
+{
+   int i;
+
+   for (i = PCIE1; i <= PCIE2; i++)
+   if (!is_serdes_configured(i)) {
+   debug("PCIe%d: disabled all R/W permission!\n", i);
+   set_pcie_ns_access(i, 0);
+   }
+}
+#endif
+
 int arch_soc_init(void)
 {
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index fac539d..c0d2610 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -8,11 +8,14 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 #include 
+#endif
 #ifdef CONFIG_SYS_FSL_DDR
 #include 
 #include 
@@ -299,6 +302,19 @@ void erratum_a008850_post(void)
 #endif
 }
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+void erratum_a010315(void)
+{
+   int i;
+
+   for (i = PCIE1; i <= PCIE4; i++)
+   if (!is_serdes_configured(i)) {
+   debug("PCIe%d: disabled all R/W permission!\n", i);
+   set_pcie_ns_access(i, 0);
+   }
+}
+#endif
+
 void fsl_lsch2_early_init_f(void)
 {
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index b0ad4b4..159c25d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -167,6 +167,8 @@
 #define CONFIG_SYS_FSL_SEC_BE
 
 #define CONFIG_SYS_FSL_SRDS_1
+
+#define CONFIG_SYS_FSL_ERRATUM_A010315
 /* SoC related */
 #ifdef CONFIG_LS1043A
 #define CONFIG_MAX_CPUS4
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h 
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 8d4a7ad..4512732 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -100,6 +100,10 @@ void cpu_name(char *name);
 void erratum_a009635(void);
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+void erratum_a010315(void);
+#endif
+
 bool soc_has_dp_ddr(void);
 bool soc_has_aiop(void);
 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index d408fe4..a16d980 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -131,6 +131,7 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT1
 #define CONFIG_SYS_FSL_ERRATUM_A008378
 #define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_ERRATUM_A010315
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 #else
 #error SoC not defined
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h 
b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
index a354684..9c91354 100644
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
@@ -11,4 +11,8 @@ unsigned int get_soc_major_rev(void);
 int arch_soc_init(void);
 int ls102xa_smmu_stream_id_init(void);
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+void erratum_a010315(void);
+#endif
+
 #endif /* __FSL_LS102XA_SOC_H */
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c 
b/board/freescale/ls1012aqds/ls1012aqds.c

[U-Boot] [PATCHv2 1/5] fsl: serdes: ensure accessing the initialized maps of serdes protocol

[Zhiqiang Hou]

From: Hou Zhiqiang 

Up to now, the function is_serdes_configed() doesn't check if the map
of serdes protocol is initialized before accessing it. The function
is_serdes_configed() will get wrong result when it was called before
the serdes protocol maps initialized. As the first element of the map
isn't used for any device, so use it as the flag to indicate if the
map has been initialized.

Signed-off-by: Hou Zhiqiang 
---
V2:
 - Check initialization-state of the serdes protocol map before serdes init.
 - Comment the element 'NONE' used as a initialization-state flag.

 arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c  | 15 +--
 arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c | 12 
 arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 12 
 .../arm/include/asm/arch-fsl-layerscape/fsl_serdes.h |  8 
 arch/arm/include/asm/arch-ls102xa/fsl_serdes.h   |  4 
 arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c|  9 +
 arch/powerpc/cpu/mpc85xx/c29x_serdes.c   |  9 +
 arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c   | 18 ++
 arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c|  8 
 arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c| 20 +++-
 arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c| 20 +++-
 arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c|  9 +
 arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c|  9 +
 arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c|  9 +
 arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c|  9 +
 arch/powerpc/cpu/mpc85xx/p1010_serdes.c  | 20 +++-
 arch/powerpc/cpu/mpc85xx/p1021_serdes.c  |  9 +
 arch/powerpc/cpu/mpc85xx/p1022_serdes.c  | 20 +++-
 arch/powerpc/cpu/mpc85xx/p1023_serdes.c  | 12 +++-
 arch/powerpc/cpu/mpc85xx/p2020_serdes.c  |  9 +
 arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c| 20 +++-
 arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c| 20 +++-
 arch/powerpc/include/asm/fsl_serdes.h|  4 
 23 files changed, 276 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c 
b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
index 9b78acb..86ace90 100644
--- a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
+++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
@@ -23,9 +23,15 @@ int is_serdes_configured(enum srds_prtcl device)
u64 ret = 0;
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
+   if (!(serdes1_prtcl_map & (1ULL << NONE)))
+   fsl_serdes_init();
+
ret |= (1ULL << device) & serdes1_prtcl_map;
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
+   if (!(serdes2_prtcl_map & (1ULL << NONE)))
+   fsl_serdes_init();
+
ret |= (1ULL << device) & serdes2_prtcl_map;
 #endif
 
@@ -87,19 +93,24 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 
sd_prctl_shift)
serdes_prtcl_map |= (1ULL << lane_prtcl);
}
 
+   /* Set the first bit to indicate serdes has been initialized */
+   serdes_prtcl_map |= (1ULL << NONE);
+
return serdes_prtcl_map;
 }
 
 void fsl_serdes_init(void)
 {
 #ifdef CONFIG_SYS_FSL_SRDS_1
-   serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
+   if (!(serdes1_prtcl_map & (1ULL << NONE)))
+   serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_SERDES_ADDR,
RCWSR4_SRDS1_PRTCL_MASK,
RCWSR4_SRDS1_PRTCL_SHIFT);
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
-   serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
+   if (!(serdes2_prtcl_map & (1ULL << NONE)))
+   serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
CONFIG_SYS_FSL_SERDES_ADDR +
FSL_SRDS_2 * 0x1000,
RCWSR4_SRDS2_PRTCL_MASK,
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
index f73092a..29cd28e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
@@ -22,9 +22,15 @@ int is_serdes_configured(enum srds_prtcl device)
int ret = 0;
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
+   if (!serdes1_prtcl_map[NONE])
+   fsl_serdes_init();
+
ret |= serdes1_prtcl_map[device];
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
+   if (!serdes2_prtcl_map[NONE])
+   fsl_serdes_init();
+
ret |= serdes2_prtcl_map[device];
 #endif
 
@@ -98,6 +104,9 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 
sd_prctl_shift,
u32 cfg;
int lane;
 
+   if 

[U-Boot] [PATCHv2 2/5] arm: fsl-layerscape: move forward the non-secure access permission setup

[Zhiqiang Hou]

From: Hou Zhiqiang 

Move forward the basic non-secure access enable operation, so the
subsequent individual device access permission can override it.
And collect the dispersed callers in board level, and then move
them to SoC level.

Signed-off-by: Hou Zhiqiang 
---
V2
 - no change

 arch/arm/cpu/armv7/ls102xa/soc.c  | 5 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c   | 5 +
 arch/arm/cpu/armv8/fsl-layerscape/spl.c   | 4 
 board/freescale/ls1012afrdm/ls1012afrdm.c | 5 -
 board/freescale/ls1012aqds/ls1012aqds.c   | 5 -
 board/freescale/ls1012ardb/ls1012ardb.c   | 5 -
 board/freescale/ls1021aqds/ls1021aqds.c   | 4 
 board/freescale/ls1021atwr/ls1021atwr.c   | 4 
 board/freescale/ls1043aqds/ls1043aqds.c   | 4 
 board/freescale/ls1043ardb/ls1043ardb.c   | 5 -
 10 files changed, 10 insertions(+), 36 deletions(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index b1b0c71..4c93ab7 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 
 struct liodn_id_table sec_liodn_tbl[] = {
SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
@@ -64,6 +65,10 @@ int arch_soc_init(void)
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
unsigned int major;
 
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+   enable_layerscape_ns_access();
+#endif
+
 #ifdef CONFIG_FSL_QSPI
out_be32(>qspi_cfg, SCFG_QSPI_CLKSEL);
 #endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index f62b78d..fac539d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #ifdef CONFIG_SYS_FSL_DDR
 #include 
 #include 
@@ -303,6 +304,10 @@ void fsl_lsch2_early_init_f(void)
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+   enable_layerscape_ns_access();
+#endif
+
 #ifdef CONFIG_FSL_IFC
init_early_memctl_regs();   /* tighten IFC timing */
 #endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c 
b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 19e34fa..b75547d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -8,7 +8,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -66,9 +65,6 @@ void board_init_f(ulong dummy)
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
 
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-   enable_layerscape_ns_access();
-#endif
board_init_r(NULL, 0);
 }
 #endif
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c 
b/board/freescale/ls1012afrdm/ls1012afrdm.c
index a94a458..5a2b1f4 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -11,7 +11,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -175,10 +174,6 @@ int board_init(void)
gd->env_addr = (ulong)_environment[0];
 #endif
 
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-   enable_layerscape_ns_access();
-#endif
-
return 0;
 }
 
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c 
b/board/freescale/ls1012aqds/ls1012aqds.c
index 71eea82..852d683 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -17,7 +17,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -207,10 +206,6 @@ int board_init(void)
out_le32(>ctrl_ord,
 CCI400_CTRLORD_EN_BARRIER);
 
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-   enable_layerscape_ns_access();
-#endif
-
 #ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)_environment[0];
 #endif
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c 
b/board/freescale/ls1012ardb/ls1012ardb.c
index f69768d..a3748de 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -14,7 +14,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -207,10 +206,6 @@ int board_init(void)
gd->env_addr = (ulong)_environment[0];
 #endif
 
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-   enable_layerscape_ns_access();
-#endif
-
return 0;
 }
 
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c 
b/board/freescale/ls1021aqds/ls1021aqds.c
index dbea0bf..291b0f4 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -446,10 +446,6 @@ int board_init(void)
 
ls102xa_smmu_stream_id_init();
 
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-   enable_layerscape_ns_access();
-#endif
-
 #ifdef CONFIG_U_QE
u_qe_init();
 #endif
diff --git 

[U-Boot] [PATCH] configs: Fix mmc rescan misuses

[Karl Beldan]

This follows 9fd383724cf4 ("mmc: don't allow extra cmdline arguments"),
and affects omapl138_lcdk and omap3_evm_quick_mmc.

Signed-off-by: Karl Beldan 
---
 include/configs/omap3_evm_quick_mmc.h | 2 +-
 include/configs/omapl138_lcdk.h   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/omap3_evm_quick_mmc.h 
b/include/configs/omap3_evm_quick_mmc.h
index b7d8765..867856f 100644
--- a/include/configs/omap3_evm_quick_mmc.h
+++ b/include/configs/omap3_evm_quick_mmc.h
@@ -61,7 +61,7 @@
"silent=1"
 
 #define CONFIG_BOOTCOMMAND \
-   "mmc rescan 0; "\
+   "mmc rescan; "  \
"fatload mmc 0 0x8200 uImage; " \
"bootm 0x8200;"
 
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 1f36d36..d00cf50 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -203,7 +203,7 @@
 #define CONFIG_REVISION_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_BOOTARGS"console=ttyS2,115200n8 
root=/dev/mmcblk0p2 rw rootwait ip=off"
-#define CONFIG_BOOTCOMMAND "if mmc rescan 0; then if fatload mmc 0 
0xc060 boot.scr; then source 0xc060; else fatload mmc 0 0xc070 
uImage; bootm c070; fi; else sf probe 0; sf read 0xc070 0x8 
0x22; bootm 0xc070; fi"
+#define CONFIG_BOOTCOMMAND "if mmc rescan; then if fatload mmc 0 
0xc060 boot.scr; then source 0xc060; else fatload mmc 0 0xc070 
uImage; bootm c070; fi; else sf probe 0; sf read 0xc070 0x8 
0x22; bootm 0xc070; fi"
 
 /*
  * U-Boot commands
-- 
2.9.0.rc1

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[U-Boot] [PATCH] mkimage: Fix argument parsing with signature comment

[Karl Beldan]

From: Karl Beldan 

Signed-off-by: Karl Beldan 
---
 tools/mkimage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/mkimage.c b/tools/mkimage.c
index d993958..3c594a0 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -140,7 +140,7 @@ static void process_args(int argc, char **argv)
int opt;
 
while ((opt = getopt(argc, argv,
-"a:A:b:cC:d:D:e:Ef:Fk:K:ln:p:O:rR:qsT:vVx")) != 
-1) {
+"a:A:b:c:C:d:D:e:Ef:Fk:K:ln:p:O:rR:qsT:vVx")) != 
-1) {
switch (opt) {
case 'a':
params.addr = strtoull(optarg, , 16);
-- 
2.9.0.rc1

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[U-Boot] [PATCH] mkimage: Fix argument parsing with signature comment

[Karl Beldan]

Signed-off-by: Karl Beldan 
---
 tools/mkimage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/mkimage.c b/tools/mkimage.c
index d993958..3c594a0 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -140,7 +140,7 @@ static void process_args(int argc, char **argv)
int opt;
 
while ((opt = getopt(argc, argv,
-"a:A:b:cC:d:D:e:Ef:Fk:K:ln:p:O:rR:qsT:vVx")) != 
-1) {
+"a:A:b:c:C:d:D:e:Ef:Fk:K:ln:p:O:rR:qsT:vVx")) != 
-1) {
switch (opt) {
case 'a':
params.addr = strtoull(optarg, , 16);
-- 
2.9.0.rc1

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[U-Boot] Regarding source code of u-boot

[kirti kumbhar]

Sir,
 I have download the source of  u-boot,but there is one problem when I
installing   cross complier there are many dependency of assembly code I
try to remove it but not working correctly  so,sir please send some command
or source code.


Thanks & Regards
Kirti D Kumbhar.
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Re: [U-Boot] [PATCH 0/5] usb: fsl: Add code to use CONFIG_DM_USB

[Marek Vasut]

On 07/28/2016 06:01 PM, york sun wrote:
> On 07/28/2016 04:34 AM, Marek Vasut wrote:
>> On 07/27/2016 08:00 PM, york sun wrote:
>>> On 07/21/2016 04:45 AM, Marek Vasut wrote:
 On 07/21/2016 10:02 AM, Rajesh Bhagat wrote:
> Hi All,
>
> Any Comments?

 York, please check this.
>>>
>>> Passed compiling tests on powerpc and arm platforms.
>>
>> And the patches are OK ?
>>
> 
> They look OK to me. But I have to admit I am not an expert on USB.

OK


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Re: [U-Boot] [PATCH v2 0/3] usb: arrange Kconfig entries for USB host support

[Marek Vasut]

On 07/31/2016 05:16 PM, Masahiro Yamada wrote:
> We have CONFIG_USB_GADGET, while we do not have an option to
> turn on/off USB host support.
> 
> In Linux, CONFIG_USB is used to enable the USB host support,
> but it is used in U-Boot to enable the whole USB sub-system.
> So, as an alternative, this commit adds CONFIG_USB_HOST
> and I think it makes sense enough.

Hi, I applied all three, but please address the CONFIG_USB_OHCI_NEW from
Alexey in a separate patch.

> Changes in v2:
>   - Fix a typo  CONIFG_ -> CONFIG_
> 
> Masahiro Yamada (3):
>   usb: add CONFIG_USB_OHCI_HCD in Kconfig
>   usb: add CONFIG_USB_UHCI_HCD in Kconfig
>   usb: add (move) CONFIG_USB_HOST to Kconfig
> 
>  configs/axs103_defconfig  |  1 +
>  drivers/usb/host/Kconfig  | 59 
> +++
>  include/configs/am43xx_evm.h  |  1 -
>  include/configs/am57xx_evm.h  |  1 -
>  include/configs/cm_t43.h  |  1 -
>  include/configs/cm_t54.h  |  1 -
>  include/configs/dra7xx_evm.h  |  1 -
>  include/configs/duovero.h |  1 -
>  include/configs/omap4_panda.h |  1 -
>  include/configs/omap5_uevm.h  |  1 -
>  10 files changed, 50 insertions(+), 18 deletions(-)
> 


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Re: [U-Boot] [PATCH 2/3] arm/PSCI: Fixed the backward compatiblity issue

[Zhiqiang Hou]

Hi York,

Thanks for your comments!

> -Original Message-
> From: york sun
> Sent: 2016年8月2日 0:10
> To: Zhiqiang Hou ; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; hdego...@redhat.com; w...@csie.org; Hongbo
> Zhang ; b.galv...@gmail.com
> Subject: Re: [PATCH 2/3] arm/PSCI: Fixed the backward compatiblity issue
> 
> On 07/31/2016 08:20 PM, Zhiqiang Hou wrote:
> > Hi York,
> >
> > Thanks for your comments!
> >
> >> -Original Message-
> >> From: york sun
> >> Sent: 2016年7月29日 23:37
> >> To: Zhiqiang Hou ; u-boot@lists.denx.de;
> >> albert.u.b...@aribaud.net; hdego...@redhat.com; w...@csie.org;
> Hongbo
> >> Zhang ; b.galv...@gmail.com
> >> Subject: Re: [PATCH 2/3] arm/PSCI: Fixed the backward compatiblity
> >> issue
> >>
> >> On 07/29/2016 03:37 AM, Zhiqiang Hou wrote:
> >>> From: Hou Zhiqiang 
> >>>
> >>> Appended the compatible strings of old version PSCI to the latest
> >>> version supported. And there are some psci functions' property must
> >>> be added to DT only for psci version 0.1, such as 'cpu_on' 'cpu_off' etc.
> >>>
> >>> Note:
> >>> The PSCI version 0.1 isn't supported by ARMv8 Secure Firmware
> Framework.
> >>>
> >>> Signed-off-by: Hou Zhiqiang 
> >>> ---
> >>
> >> You missed version number and change log.
> >
> > Should the previous Secure Firmware Framework patchset need to be
> resubmitted? And the version number follow the that patchset?
> 
> Zhiqiang,
> 
> When you send a new version, reviewers are expecting updated version
> number and a change log. This helps us tracking what has been changed.
> All patches in the same set should be updated. If a patch has not change, a
> simple "no change" helps. If any dependency has changed/updated, please
> update the note as well.
> 

I know what do you mean, this 3 patch was sent to u-boot@lists.denx.de the 
first time, please forget the versions for internal review. So I am confusing 
if you mean this 3 patches should be merged into the patchset '[PATCHv7 1/6] 
armv8: fsl-layerscape: add i/d-cache enable function to enable_caches' and then 
resubmit all the patches? I don't know if that is legal, because the state of 
that patchset has been applied to u-boot-fsl-qoriq master and awaiting 
upstream. 

> >
> >>>  arch/arm/include/asm/psci.h |  3 +++
> >>>  arch/arm/lib/psci-dt.c  | 61
> >> ++---
> >>>  2 files changed, 38 insertions(+), 26 deletions(-)
> >>>
> >>> diff --git a/arch/arm/include/asm/psci.h
> >>> b/arch/arm/include/asm/psci.h index 8aefaa7..5b8ce4d 100644
> >>> --- a/arch/arm/include/asm/psci.h
> >>> +++ b/arch/arm/include/asm/psci.h
> >>> @@ -18,6 +18,9 @@
> >>>  #ifndef __ARM_PSCI_H__
> >>>  #define __ARM_PSCI_H__
> >>>
> >>> +#define ARM_PSCI_VER_1_0 (0x0001)
> >>> +#define ARM_PSCI_VER_0_2 (0x0002)
> >>> +
> >>>  /* PSCI 0.1 interface */
> >>>  #define ARM_PSCI_FN_BASE 0x95c1ba5e
> >>>  #define ARM_PSCI_FN(n)   (ARM_PSCI_FN_BASE + (n))
> >>> diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c index
> >>> bcd92e7..af49c24 100644
> >>> --- a/arch/arm/lib/psci-dt.c
> >>> +++ b/arch/arm/lib/psci-dt.c
> >>> @@ -19,7 +19,6 @@ int fdt_psci(void *fdt)  #if
> >>> defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI)
> >>>   int nodeoff;
> >>>   unsigned int psci_ver = 0;
> >>> - char *psci_compt;
> >>>   int tmp;
> >>>
> >>>   nodeoff = fdt_path_offset(fdt, "/cpus"); @@ -68,39 +67,49 @@
> >>> init_psci_node:
> >>>   psci_ver = sec_firmware_support_psci_version();
> >>>  #endif
> >>>   switch (psci_ver) {
> >>> - case 0x0001:
> >>> - psci_compt = "arm,psci-1.0";
> >>> - break;
> >>> - case 0x0002:
> >>> - psci_compt = "arm,psci-0.2";
> >>> - break;
> >>> + case ARM_PSCI_VER_1_0:
> >>> + tmp = fdt_setprop_string(fdt, nodeoff,
> >>> + "compatible", "arm,psci-1.0");
> >>> + if (tmp)
> >>> + return tmp;
> >>
> >> Add a comment "fall through".
> >>
> >
> > Yes, will add the comment.
> > []
> >>> + case ARM_PSCI_VER_0_2:
> >>> + tmp = fdt_appendprop_string(fdt, nodeoff,
> >>> + "compatible", "arm,psci-0.2");
> >>> + if (tmp)
> >>> + return tmp;
> >>
> >> Add a comment "fall through".
> >>
> >>>   default:
> >>> - psci_compt = "arm,psci";
> >>> + /*
> >>> +  * The Secure firmware framework isn't able to support PSCI version
> 0.1.
> >>> +  */
> >>> +#ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
> >>> + tmp = fdt_appendprop_string(fdt, nodeoff,
> >>> + "compatible", "arm,psci");
> >>> + if (tmp)
> >>> + return tmp;
> >>> + tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend",
> >>> + ARM_PSCI_FN_CPU_SUSPEND);
> >>> + if (tmp)
> >>> + 

[U-Boot] [v2, 5/5] arch/arm, arch/powerpc: enable workaround for eSDHC erratum A009620

[Yangbo Lu]

This patch is to enable workaround for eSDHC erratum A009620. All the
affected platforms include PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/
T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A).

Signed-off-by: Yangbo Lu 
---
Changes for v2:
- Added this patch
- Moved definition out of board files
---
 arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++
 arch/arm/include/asm/arch-ls102xa/config.h| 1 +
 arch/powerpc/include/asm/config_mpc85xx.h | 8 
 3 files changed, 11 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index b0ad4b4..7f31fcd 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -32,6 +32,7 @@
 #define CONFIG_NUM_DDR_CONTROLLERS 3
 #define CONFIG_SYS_FSL_HAS_DP_DDR  /* Runtime check to confirm */
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 1, 4, 4 }
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #defineSRDS_MAX_LANES  8
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_SRDS_2
@@ -175,6 +176,7 @@
 #define CONFIG_SYS_NUM_FM1_DTSEC   7
 #define CONFIG_SYS_NUM_FM1_10GEC   1
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  4
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #define CONFIG_SYS_FSL_DDR_BE
 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED  CONFIG_SYS_DDR_BLOCK1_SIZE
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index d408fe4..054f05d 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -131,6 +131,7 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT1
 #define CONFIG_SYS_FSL_ERRATUM_A008378
 #define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 #else
 #error SoC not defined
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 505d355..b3d8fe8 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -148,6 +148,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT  4
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #define CONFIG_NUM_DDR_CONTROLLERS 1
 #define CONFIG_USB_MAX_CONTROLLER_COUNT1
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  4
@@ -369,6 +370,7 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -530,6 +532,7 @@
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #define CONFIG_SYS_FSL_ERRATUM_USB14
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
@@ -568,6 +571,7 @@
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #define CONFIG_SYS_FSL_ERRATUM_USB14
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
@@ -686,6 +690,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A007186
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_FSL_ERRATUM_A007798
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe00
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 #define CONFIG_SYS_FSL_PCI_VER_3_X
@@ -802,6 +807,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe00
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define QE_MURAM_SIZE  0x6000UL
 #define MAX_QE_RISC1
@@ -823,6 +829,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #endif
 #if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
 #define CONFIG_MAX_CPUS2
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_MAX_CPUS1
 #endif
@@ -882,6 +889,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #elif defined(CONFIG_PPC_T2081)
 #define CONFIG_SYS_NUM_FM1_DTSEC   6
 #define CONFIG_SYS_NUM_FM1_10GEC   2
-- 
2.1.0.27.g96db324

[U-Boot] [v2, 2/5] mmc: send STOP command when the READ/WRITE commands fail

[Yangbo Lu]

The STOP command should be sent to stop data transfer when the
READ/WRITE commands fail. Otherwise, any subsequent command will
fail to be sent.

Signed-off-by: Yangbo Lu 
---
Changes for v2:
- None
---
 drivers/mmc/mmc.c | 28 +++-
 drivers/mmc/mmc_private.h |  1 +
 drivers/mmc/mmc_write.c   |  8 ++--
 3 files changed, 22 insertions(+), 15 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index f8e5f7a..85d1e18 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -188,6 +188,21 @@ int mmc_set_blocklen(struct mmc *mmc, int len)
return mmc_send_cmd(mmc, , NULL);
 }
 
+int mmc_send_stop(struct mmc *mmc)
+{
+   struct mmc_cmd cmd;
+   int err;
+
+   cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
+   cmd.cmdarg = 0;
+   cmd.resp_type = MMC_RSP_R1b;
+
+   err = mmc_send_cmd(mmc, , NULL);
+   if (err)
+   printf("mmc fail to send stop cmd\n");
+   return err;
+}
+
 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
   lbaint_t blkcnt)
 {
@@ -211,19 +226,14 @@ static int mmc_read_blocks(struct mmc *mmc, void *dst, 
lbaint_t start,
data.blocksize = mmc->read_bl_len;
data.flags = MMC_DATA_READ;
 
-   if (mmc_send_cmd(mmc, , ))
+   if (mmc_send_cmd(mmc, , )) {
+   mmc_send_stop(mmc);
return 0;
+   }
 
if (blkcnt > 1) {
-   cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
-   cmd.cmdarg = 0;
-   cmd.resp_type = MMC_RSP_R1b;
-   if (mmc_send_cmd(mmc, , NULL)) {
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
-   printf("mmc fail to send stop cmd\n");
-#endif
+   if (mmc_send_stop(mmc))
return 0;
-   }
}
 
return blkcnt;
diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h
index 49ec022..2791125 100644
--- a/drivers/mmc/mmc_private.h
+++ b/drivers/mmc/mmc_private.h
@@ -16,6 +16,7 @@ extern int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data);
 extern int mmc_send_status(struct mmc *mmc, int timeout);
 extern int mmc_set_blocklen(struct mmc *mmc, int len);
+int mmc_send_stop(struct mmc *mmc);
 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
 void mmc_adapter_card_type_ident(void);
 #endif
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index 0f8b5c7..fb8488c 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -150,6 +150,7 @@ static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t 
start,
 
if (mmc_send_cmd(mmc, , )) {
printf("mmc write failed\n");
+   mmc_send_stop(mmc);
return 0;
}
 
@@ -157,13 +158,8 @@ static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t 
start,
 * token, not a STOP_TRANSMISSION request.
 */
if (!mmc_host_is_spi(mmc) && blkcnt > 1) {
-   cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
-   cmd.cmdarg = 0;
-   cmd.resp_type = MMC_RSP_R1b;
-   if (mmc_send_cmd(mmc, , NULL)) {
-   printf("mmc fail to send stop cmd\n");
+   if (mmc_send_stop(mmc))
return 0;
-   }
}
 
/* Waiting for the ready status */
-- 
2.1.0.27.g96db324

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[U-Boot] [v2, 4/5] mmc: add workaround for eSDHC erratum A009620

[Yangbo Lu]

Erratum Title:
Data timeout error not getting set in case of command with busy
response (R1b) as well as for busy period after last write block
transfer.

Description:
In the event that a busy timeout occurs for a command with a busy
response (e.g. R1b response) as well as busy period after the last
write block, the eSDHC does not set the IRQSTAT[DTOE] bit or the
IRQSTAT[TC]. Therefore, the current command transfer is never completed.

Workaround:
Workaround for CMD with busy:
Don't set the XFRTYP[RSP]=2'b11 for commands with busy response and
poll the busy status of the card from the PRSSTAT[DLSL]

Workaround for busy period after last write block:
1. After the command completion interrupt (IRQSTAT[CC]), wait for
   de-assertion of PRSTAT[WTA].
2. Once PRSTAT[WTA] is de-asserted, start the software timer and poll
   the busy signal (DAT0) using PRSTAT[DLSL[0]].
3. Wait for DAT0 signal to go high (which indicate transfer complete)
   or software timer expiry (which indicate data timeout error).
4. Issue soft reset for data (SYSCTL[RSTD]).
5. In case of data timeout error (detected in step 3) perform the
   error recovery.

The workaround for CMD with busy has already been applied in eSDHC
driver. This patch is to add workaround for the 2nd issue.

Signed-off-by: Yangbo Lu 
---
Changes for v2:
- Split original patch into config part and mmc part
---
 drivers/mmc/fsl_esdhc.c | 26 ++
 include/fsl_esdhc.h |  1 +
 2 files changed, 27 insertions(+)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 80bc177..99cadae 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -482,6 +482,32 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 
struct mmc_data *data)
 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
esdhc_pio_read_write(mmc, data);
 #else
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
+   int timeout = 5000;
+   if (data->flags & MMC_DATA_WRITE) {
+   while (esdhc_read32(>prsstat) & PRSSTAT_WTA)
+   ;
+
+   /* Poll on DATA0 line for 500 ms */
+   while (!(esdhc_read32(>prsstat) & PRSSTAT_DAT0)) {
+   udelay(100);
+   timeout--;
+   if (timeout <= 0) {
+   err = TIMEOUT;
+   break;
+   }
+   }
+   if (!err) {
+   esdhc_write32(>sysctl,
+ esdhc_read32(>sysctl) |
+ SYSCTL_RSTD);
+   while ((esdhc_read32(>sysctl) &
+   SYSCTL_RSTD))
+   ;
+   }
+   goto out;
+   }
+#endif
do {
irqstat = esdhc_read32(>irqstat);
 
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index c6f4666..3f146f7 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -97,6 +97,7 @@
 #define PRSSTAT_CINS   (0x0001)
 #define PRSSTAT_BREN   (0x0800)
 #define PRSSTAT_BWEN   (0x0400)
+#define PRSSTAT_WTA(0x0100)
 #define PRSSTAT_SDSTB  (0X0008)
 #define PRSSTAT_DLA(0x0004)
 #define PRSSTAT_CICHB  (0x0002)
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH] arm: cache: always flush cache line size for page table

[Marek Vasut]

On 08/02/2016 09:07 AM, Stefan Agner wrote:
> From: Stefan Agner 
> 
> The page table is maintained by the CPU, hence it is safe to always
> align cache flush to a whole cache line size. This allows to use
> mmu_page_table_flush for a single page table, e.g. when configure
> only small regions through mmu_set_region_dcache_behaviour.
> 
> Signed-off-by: Stefan Agner 
> ---
> This avoids two messages observed on a i.MX 7 based system:
> CACHE: Misaligned operation at range [9fff, 9fff0004]
> CACHE: Misaligned operation at range [9fff0024, 9fff0028]
> 
> Those were caused by two calls to mmu_set_region_dcache_behaviour
> in arch/arm/imx-common/cache.c (enable_caches).
> 
> Not sure if this is the right way to fix this... Also, we could
> do the alignment in mmu_set_region_dcache_behaviour.

This should be fixed on the driver level indeed, not in cache_v7.c

> --
> Stefan
> 
>  arch/arm/cpu/armv7/cache_v7.c | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
> index 52f1856..71787fc 100644
> --- a/arch/arm/cpu/armv7/cache_v7.c
> +++ b/arch/arm/cpu/armv7/cache_v7.c
> @@ -147,6 +147,13 @@ void arm_init_before_mmu(void)
>  
>  void mmu_page_table_flush(unsigned long start, unsigned long stop)
>  {
> + /*
> +  * Make sure range is cache line aligned
> +  * Only CPU maintains page tables, hence it is save to always
> +  * flush the complete cache line...
> +  */
> + start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
> + stop = ALIGN(stop, CONFIG_SYS_CACHELINE_SIZE);
>   flush_dcache_range(start, stop);
>   v7_inval_tlb();
>  }
> 


-- 
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Marek Vasut
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[U-Boot] [v2, 3/5] mmc: fsl_esdhc: add error recovery for data transfer with Auto CMD12

[Yangbo Lu]

For data transfer with Auto CMD12, the host will not send an Auto
CMD12 to stop when the transfer fails. So this patch adds a flag
to indicate the READ/WRITE command error, and makes the driver
continue to send a CMD12 manually.

Signed-off-by: Yangbo Lu 
---
Changes for v2:
- None
---
 drivers/mmc/fsl_esdhc.c | 22 --
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index b23845d..80bc177 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -106,6 +106,9 @@ struct fsl_esdhc_priv {
int wp_enable;
struct gpio_desc cd_gpio;
struct gpio_desc wp_gpio;
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
+   int rw_err;
+#endif
 };
 
 /* Return the XFERTYP flags for a given command and data packet */
@@ -362,8 +365,12 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 
struct mmc_data *data)
struct fsl_esdhc *regs = priv->esdhc_regs;
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
-   if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
-   return 0;
+   if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) {
+   if (priv->rw_err)
+   priv->rw_err = 0;
+   else
+   return 0;
+   }
 #endif
 
esdhc_write32(>irqstat, -1);
@@ -518,6 +525,13 @@ out:
/* If this was CMD11, then notify that power cycle is needed */
if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
printf("CMD11 to switch to 1.8V mode failed, card 
requires power cycle.\n");
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
+   if (cmd->cmdidx == MMC_CMD_READ_SINGLE_BLOCK ||
+   cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK ||
+   cmd->cmdidx == MMC_CMD_WRITE_SINGLE_BLOCK ||
+   cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)
+   priv->rw_err = 1;
+#endif
}
 
esdhc_write32(>irqstat, -1);
@@ -828,6 +842,10 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
 
priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
+   priv->rw_err = 0;
+#endif
+
mmc = mmc_create(>cfg, priv);
if (mmc == NULL)
return -1;
-- 
2.1.0.27.g96db324

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[U-Boot] [v2, 1/5] mmc: fsl_esdhc: don't set XFERTYP_RSPTYP_48_BUSY for CMD with busy response

[Yangbo Lu]

For CMD with busy response, the eSDHC driver would poll DAT0 until
CMD completion rather than polling IRQSTAT. So, don't set
XFERTYP_RSPTYP_48_BUSY to avoid interrupts (DTOE or TC) in IRQSTAT.

Signed-off-by: Yangbo Lu 
---
Changes for v2:
- None
---
 drivers/mmc/fsl_esdhc.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index a865c7b..b23845d 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -136,8 +136,16 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct 
mmc_data *data)
xfertyp |= XFERTYP_CICEN;
if (cmd->resp_type & MMC_RSP_136)
xfertyp |= XFERTYP_RSPTYP_136;
-   else if (cmd->resp_type & MMC_RSP_BUSY)
-   xfertyp |= XFERTYP_RSPTYP_48_BUSY;
+   /*
+* For CMD with busy response, the eSDHC driver would poll DAT0
+* until CMD completion rather than polling IRQSTAT. So, don't
+* set XFERTYP_RSPTYP_48_BUSY to avoid interrupts (DTOE or TC)
+* in IRQSTAT.
+*
+* Remove:
+* else if (cmd->resp_type & MMC_RSP_BUSY)
+*  xfertyp |= XFERTYP_RSPTYP_48_BUSY;
+*/
else if (cmd->resp_type & MMC_RSP_PRESENT)
xfertyp |= XFERTYP_RSPTYP_48;
 
-- 
2.1.0.27.g96db324

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[U-Boot] [v2] mmc: send CMD0 before CMD1 for some MMC cards

[Yangbo Lu]

When the MMC framework was added in u-boot, the mmc_go_idle was
added before mmc_send_op_cond_iter in function mmc_send_op_cond
annotating that some cards seemed to need this. Actually, we still
need to do this in function mmc_complete_op_cond for those cards.
This has been verified on Micron MTFC4GACAECN eMMC chip.

Signed-off-by: Yangbo Lu 
---
 drivers/mmc/mmc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index f8e5f7a..d4e96bc 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -422,6 +422,9 @@ static int mmc_complete_op_cond(struct mmc *mmc)
 
mmc->op_cond_pending = 0;
if (!(mmc->ocr & OCR_BUSY)) {
+   /* Some cards seem to need this */
+   mmc_go_idle(mmc);
+
start = get_timer(0);
while (1) {
err = mmc_send_op_cond_iter(mmc, 1);
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] imx_watchdog: Do not assert WDOG_B on watchdog init

[Ross Parker]

Currently the driver asserts WDOG_B by clearing WCR_WDA bit when
enabling the watchdog. Do not clear WCR_WDA.

Signed-off-by: Ross Parker 
Cc: Stefano Babic 

---
 drivers/watchdog/imx_watchdog.c | 2 +-
 include/fsl_wdog.h  | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/watchdog/imx_watchdog.c
b/drivers/watchdog/imx_watchdog.c
index 2938d9f..3f826d1 100644
--- a/drivers/watchdog/imx_watchdog.c
+++ b/drivers/watchdog/imx_watchdog.c
@@ -34,7 +34,7 @@ void hw_watchdog_init(void)
 #endif
  timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
  writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS |
- SET_WCR_WT(timeout), >wcr);
+ WCR_WDA | SET_WCR_WT(timeout), >wcr);
  hw_watchdog_reset();
 }
 #endif
diff --git a/include/fsl_wdog.h b/include/fsl_wdog.h
index f698d4d..7818f78 100644
--- a/include/fsl_wdog.h
+++ b/include/fsl_wdog.h
@@ -15,5 +15,6 @@ struct watchdog_regs {
 #define WCR_WDE 0x04
 #define WCR_WDT 0x08
 #define WCR_SRS 0x10
+#define WCR_WDA 0x20
 #define SET_WCR_WT(x) (x << 8)
 #define WCR_WT_MSK SET_WCR_WT(0xFF)
-- 
1.9.1
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Re: [U-Boot] Disable command at runtime

[Petr Kubizňák]

Dear Wolfgang,

On 08/01/2016 10:05 PM, Wolfgang Denk wrote:

How could that ever be "safe" - in the sense of protecting against an
attacker?  How could you perform such a "switch" between modes?  By
setting some bit somewhere.  And it has to be in some persistent
storage.  And the source code of your image is available to the
public.  What should prevent an attacker from undoing your bit
setting and switching back to "full" mode?
If it was to be an irreversible switch, a reliable way might be to 
effectively remove some parts of the program by overwriting them. Not 
that I ever have done that, perhaps it's not that easy as I imagine, but 
I believe it's possible.

U-Boot is a boot loader, not a high security environment.  If you
grand somebody access to the U-Boot command line interface, he owns
the system.  If not directly, so by just pulling a few simple tricks.
You are absolutely right, whoever has access to U-Boot, can easily 
destroy the system. The main problem is perhaps in my understanding of 
the concept. I'm always tempted to keep access to U-Boot "for future 
sakes", but have not found a reliable way to deny the access to the 
others. Is there a "correct approach"?


By the way, once I read in some conversation that bad security is no 
security, so that's why U-Boot does not implement bad security. From my 
point of view, bad security (e.g. password stored in env) is strong 
enough to keep away the amateurs who just want to play with it and don't 
really know they might destroy the system. Of course it does not secure 
the system from the really evil attackers, but what does?


Best Regards,
Petr
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Re: [U-Boot] Disable command at runtime

[Petr Kubizňák]

Dear ladis,

Thanks for your comment, I didn't really know about the standalone 
applications mechanism, it might surely be useful.


Best Regards,
Petr


On 08/01/2016 10:38 PM, Ladislav Michl wrote:

You can still download U-Boot standalone application implementing whatever
you need to do in production, so in "normal mode" your manufacturing secrets
are not even part of your product.

Best regards,
ladis


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Re: [U-Boot] [PATCH v2 0/4] Add support for TI PCF8575 I2C GPIO expander

[Vignesh R]

On Friday 29 July 2016 04:50 PM, Vignesh R wrote:
> This series adds support for TI's PCF8575 I2C GPIO expander[1] based on
> Linux Kernel driver for the same.  Also adds support for ethernet to use
> new PCF8575 driver to select appropriate cpsw slaves on dra72.
> 
> Depends on I2C DM support [2]
> 
> Tested on DRA72 EVM.
> 
> [1]http://www.ti.com/lit/ds/symlink/pcf8575.pdf
> [2]https://www.mail-archive.com/u-boot@lists.denx.de/msg218923.html

I have posted v3 of this series after addressing the additional comments
that I got for older version.

> 
> Vignesh R (4):
>   gpio: Add driver for TI PCF8575 I2C GPIO expander
>   ARM: dra7xx_evm: Enable support for TI PCF8575
>   net: cpsw: Add support to drive gpios for ethernet to be functional
>   ARM: dts: dra72-evm: Add mode-gpios entry for mac node
> 
>  arch/arm/dts/dra72-evm.dts |   2 +-
>  doc/device-tree-bindings/gpio/gpio-pcf857x.txt |  71 +
>  drivers/gpio/Kconfig   |   7 +
>  drivers/gpio/Makefile  |   1 +
>  drivers/gpio/pcf8575_gpio.c| 190 
> +
>  drivers/net/cpsw.c |  12 ++
>  include/configs/dra7xx_evm.h   |   5 +
>  7 files changed, 287 insertions(+), 1 deletion(-)
>  create mode 100644 doc/device-tree-bindings/gpio/gpio-pcf857x.txt
>  create mode 100644 drivers/gpio/pcf8575_gpio.c
> 

-- 
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Vignesh
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Re: [U-Boot] [PATCH] mtd: nand: mxs: fix cache alignment for cache lines >32

[Stefano Babic]

Hi Stefan,

On 02/08/2016 08:55, Stefan Agner wrote:
> From: Stefan Agner 
> 
> Currently the command buffer gets allocated with a size of 32 bytes.
> This causes warning messages on systems with cache lines bigger than
> 32 bytes:
> CACHE: Misaligned operation at range [9df17a00, 9df17a20]
> 

I've never seen this on NAND

> Define command buffer to be at least 32 bytes, but more if cache
> line is bigger.
> 
> Signed-off-by: Stefan Agner 
> ---
> This appeared after Simon enable the message in check_cache_range
> by default...

ok, this explains why !

> 
>  drivers/mtd/nand/mxs_nand.c | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
> index 94fc5c1..4bf564e 100644
> --- a/drivers/mtd/nand/mxs_nand.c
> +++ b/drivers/mtd/nand/mxs_nand.c
> @@ -37,7 +37,12 @@
>  #endif
>  #define  MXS_NAND_METADATA_SIZE  10
>  #define  MXS_NAND_BITS_PER_ECC_LEVEL 13
> +
> +#if !defined(CONFIG_SYS_CACHELINE_SIZE) || CONFIG_SYS_CACHELINE_SIZE < 32
>  #define  MXS_NAND_COMMAND_BUFFER_SIZE32
> +#else
> +#define  MXS_NAND_COMMAND_BUFFER_SIZE
> CONFIG_SYS_CACHELINE_SIZE
> +#endif
>  
>  #define  MXS_NAND_BCH_TIMEOUT1
>  
> 

Reviewed-by: Stefano Babic 

Best regards,
Stefano Babic

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[U-Boot] [PATCH v4] nitrogen6x : Use generic distro configuration

[Fabien Lahoudere]

In order to simplify the use of various images on various media
for nitrogen6x, the configuration of the board must follow the
generic distro configuration (doc/README.distro).

In order to boot your old rootfs, move your kernel and your device
tree in /boot/. Then create /boot/extlinux/extlinux.conf with for
example:

default Buildroot

label Buildroot
kernel /boot/zImage
append console=ttymxc1,115200 root=/dev/mmcblk0p1 rootwait rw
fdtdir /boot

Signed-off-by: Fabien Lahoudere 
---
Changes for V2:
- reintegration of deleted env
- changes are applied only if CONFIG_DISTRO_DEFAULTS=y

Changes for V3:
- remove undefined device tree

Changes for v4:
- remove default definition of CONFIG_FDTADDR in mx6_common.h

 configs/mx6qsabrelite_defconfig |  1 +
 configs/nitrogen6dl2g_defconfig |  1 +
 configs/nitrogen6dl_defconfig   |  1 +
 configs/nitrogen6q2g_defconfig  |  1 +
 configs/nitrogen6q_defconfig|  1 +
 configs/nitrogen6s1g_defconfig  |  1 +
 configs/nitrogen6s_defconfig|  1 +
 doc/README.imx6 | 47 
+

 include/configs/mx6_common.h| 22 +++
 include/configs/nitrogen6x.h| 38 +++--
 10 files changed, 108 insertions(+), 6 deletions(-)

diff --git a/configs/mx6qsabrelite_defconfig 
b/configs/mx6qsabrelite_defconfig

index fa6139a..27b64c4 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -36,3 +36,4 @@ CONFIG_G_DNL_MANUFACTURER="Boundary"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
+CONFIG_DISTRO_DEFAULTS=y
\ No newline at end of file
diff --git a/configs/nitrogen6dl2g_defconfig 
b/configs/nitrogen6dl2g_defconfig

index 02b2462..b1344c6 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -34,3 +34,4 @@ CONFIG_G_DNL_MANUFACTURER="Boundary"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
+CONFIG_DISTRO_DEFAULTS=y
\ No newline at end of file
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index 52553f6..f794c08 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -34,3 +34,4 @@ CONFIG_G_DNL_MANUFACTURER="Boundary"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
+CONFIG_DISTRO_DEFAULTS=y
\ No newline at end of file
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index 11188b7..56cebe0 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -34,3 +34,4 @@ CONFIG_G_DNL_MANUFACTURER="Boundary"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
+CONFIG_DISTRO_DEFAULTS=y
\ No newline at end of file
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index 05bf140..c150b97 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -34,3 +34,4 @@ CONFIG_G_DNL_MANUFACTURER="Boundary"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
+CONFIG_DISTRO_DEFAULTS=y
\ No newline at end of file
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index bb081a2..dfd096d 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -34,3 +34,4 @@ CONFIG_G_DNL_MANUFACTURER="Boundary"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
+CONFIG_DISTRO_DEFAULTS=y
\ No newline at end of file
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index 08e91c9..5e2e693 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -34,3 +34,4 @@ CONFIG_G_DNL_MANUFACTURER="Boundary"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
+CONFIG_DISTRO_DEFAULTS=y
\ No newline at end of file
diff --git a/doc/README.imx6 b/doc/README.imx6
index 1823fb2..36452f6 100644
--- a/doc/README.imx6
+++ b/doc/README.imx6
@@ -138,3 +138,50 @@ c
 The last "c" command tells kermit (from ckermit package in most distros)
 to switch from command line mode to communication mode, and when the
 script is finished, the U-Boot prompt is shown in the same shell.
+
+3. Using generic distro configuration
+-
+
+In order to simplify the use of various images on various media
+for imx6 boards, the configuration of the board must follow the
+generic distro configuration (doc/README.distro).
+
+3.1. Setup uboot configuration for your board
+-
+
+First, you have to set 'CONFIG_DISTRO_DEFAULTS=y' in your board defconfig
+
+Some mandatory variable are set in mx6_common.h but can be overwritten 
like:

+  - fdtfile with CONFIG_FDTFILE
+  - fdt_addr_r and fdt_addr with CONFIG_FDTADDR
+  - ramdisk_addr_r, ramdiskaddr CONFIG_RAMDISKADDR
+
+You also have to 

Re: [U-Boot] [PATCH] mmc: send CMD0 before CMD1 for some MMC cards

[Yangbo Lu]

> -Original Message-
> From: Jaehoon Chung [mailto:jh80.ch...@samsung.com]
> Sent: Tuesday, August 02, 2016 3:18 PM
> To: Yangbo Lu; Ziyuan Xu; u-boot@lists.denx.de; Tom Rini
> Cc: Pantelis Antoniou
> Subject: Re: [U-Boot] [PATCH] mmc: send CMD0 before CMD1 for some MMC
> cards
> 
> On 08/02/2016 04:13 PM, Jaehoon Chung wrote:
> > On 08/02/2016 04:03 PM, Yangbo Lu wrote:
> >> Hi Jaehoon,
> >>
> >>
> >>> -Original Message-
> >>> From: Jaehoon Chung [mailto:jh80.ch...@samsung.com]
> >>> Sent: Thursday, July 28, 2016 4:40 PM
> >>> To: Yangbo Lu; Ziyuan Xu; u-boot@lists.denx.de; Tom Rini
> >>> Cc: Pantelis Antoniou
> >>> Subject: Re: [U-Boot] [PATCH] mmc: send CMD0 before CMD1 for some
> >>> MMC cards
> >>>
> >>> Hi Yangbo,
> >>>
> >>> On 07/28/2016 11:45 AM, Yangbo Lu wrote:
>  Hi Ziyuan and Jaehoon,
> 
> 
> > -Original Message-
> > From: Ziyuan Xu [mailto:xzy...@rock-chips.com]
> > Sent: Wednesday, July 27, 2016 9:37 PM
> > To: Jaehoon Chung; Yangbo Lu; u-boot@lists.denx.de; Tom Rini
> > Cc: Pantelis Antoniou
> > Subject: Re: [U-Boot] [PATCH] mmc: send CMD0 before CMD1 for some
> > MMC cards
> >
> >
> >
> > On 2016年07月27日 19:15, Jaehoon Chung wrote:
> >> On 07/27/2016 04:28 PM, Yangbo Lu wrote:
> >>> Hi Tom,
> >>>
> >>> Could you help to assign this mmc patch reviewing to right person?
> >>> It seems no one had reviewed it for almost half year.
> >>>
> >>> And another my mmc patch also needs to be reviewed.
> >>> I submitted in May. Please help.
> >>> http://patchwork.ozlabs.org/patch/624448/
> >>>
> >>>
> >>> Thank you very much.
> >>>
> >>>
> >>> Best regards,
> >>> Yangbo Lu
> >>>
>  -Original Message-
>  From: Yangbo Lu [mailto:yangbo...@nxp.com]
>  Sent: Wednesday, March 09, 2016 11:00 AM
>  To: u-boot@lists.denx.de
>  Cc: Pantelis Antoniou; Yangbo Lu
>  Subject: [PATCH] mmc: send CMD0 before CMD1 for some MMC cards
> 
>  When the MMC framework was added in u-boot, the mmc_go_idle was
>  added before mmc_send_op_cond_iter in function mmc_send_op_cond
>  annotating that some cards seemed to need this. Actually, we
>  still need to do this in function mmc_complete_op_cond for those
> cards.
>  This has been verified on Micron MTFC4GACAECN eMMC chip.
> >> If there is no go_idle(), then what happen?
> >> If you share the information more, i can check the more..
> > Sounds interesting, I also want want to know what happen?
> > It seems like you failed in CMD1? The eMMC device was always in
> > busy device within 1 second?
> 
>  [Lu Yangbo-B47093] This was an issue which our customer reported
>  and
> >>> required us to fix in March.
>  They used NXP LS1020A platform and Micron MTFC4GACAECN eMMC, and
> >>> reported they had to add CMD0 as below.
>  Otherwise it couldn’t read OCR.
> 
>  static int mmc_complete_op_cond(struct mmc *mmc) {
>   struct mmc_cmd cmd;
>   int timeout = 1000;
>   uint start;
>   int err;
> 
>  #if defined (XXX_CHANGED)
>   // our eMMC chip (Micron MTFC4GACAECN) requires that it be put in
> >>> idle mode before
>   // negociating the operating voltage levels.
>   mmc_go_idle(mmc);
>  #endif
> >>>
> >>> Well, it seems to fix workaround. mmc_go_idle() means Device Reset.
> >>>
> >>> mmc_complete_op_cond() function has added for reducing the booting
> time.
> >>> If mmc_go_idle() is added at here, there is no benefit, and it
> >>> should be back to old concept.
> >>>
> >>> I don't agree this patch..now.
> >>>
> >>
> >> [Lu Yangbo-B47093] Did you notice mmc_send_op_cond function? Before
> mmc_send_op_cond_iter sending CMD1, there always was mmc_go_idle.
> >> I don’t know why said 'Some cards seem to need this', but it must fix
> some issue.
> >>
> >> static int mmc_send_op_cond(struct mmc *mmc) {
> >> int err, i;
> >>
> >> /* Some cards seem to need this */
> >> mmc_go_idle(mmc);
> >>
> >> /* Asking to the card its capabilities */
> >> for (i = 0; i < 2; i++) {
> >> err = mmc_send_op_cond_iter(mmc, i != 0);
> >> if (err)
> >> return err;
> >>
> >> /* exit if not busy (flag seems to be inverted) */
> >> if (mmc->ocr & OCR_BUSY)
> >> break;
> >> }
> >> mmc->op_cond_pending = 1;
> >> return 0;
> >> }
> >>
> >> Now in mmc_complete_op_cond function, there may be the same issue.
> Without the mmc_go_idle, mmc_send_op_cond_iter failed to get ocr.
> >> Maybe I should move mmc_go_idle just before mmc_send_op_cond_iter,
> like this.
> >>
> >> static int mmc_complete_op_cond(struct mmc *mmc) {
> >> struct mmc_cmd cmd;
> >> int timeout = 1000;
> >> uint start;
> >>

[U-Boot] [PATCH] cmd: net: flush cache cacheline aligned

[Stefan Agner]

From: Stefan Agner 

Flush loaded data cacheline aligned. This avoids warnings such as
CACHE: Misaligned operation at range [8100, 816d0fa8]

Signed-off-by: Stefan Agner 
---
Why do we actually have to flush caches after load? It seems to
have worked so far despite the caches did not get flushed (due to
missalignment).

--
Stefan

 cmd/net.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cmd/net.c b/cmd/net.c
index b2f3c7b..540daeb 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -244,7 +244,7 @@ static int netboot_common(enum proto_t proto, cmd_tbl_t 
*cmdtp, int argc,
}
 
/* flush cache */
-   flush_cache(load_addr, size);
+   flush_cache(load_addr, ALIGN(size, CONFIG_SYS_CACHELINE_SIZE));
 
bootstage_mark(BOOTSTAGE_ID_NET_LOADED);
 
-- 
2.9.0

___
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Re: [U-Boot] [PATCH] mmc: send CMD0 before CMD1 for some MMC cards

[Jaehoon Chung]

On 08/02/2016 04:13 PM, Jaehoon Chung wrote:
> On 08/02/2016 04:03 PM, Yangbo Lu wrote:
>> Hi Jaehoon,
>>
>>
>>> -Original Message-
>>> From: Jaehoon Chung [mailto:jh80.ch...@samsung.com]
>>> Sent: Thursday, July 28, 2016 4:40 PM
>>> To: Yangbo Lu; Ziyuan Xu; u-boot@lists.denx.de; Tom Rini
>>> Cc: Pantelis Antoniou
>>> Subject: Re: [U-Boot] [PATCH] mmc: send CMD0 before CMD1 for some MMC
>>> cards
>>>
>>> Hi Yangbo,
>>>
>>> On 07/28/2016 11:45 AM, Yangbo Lu wrote:
 Hi Ziyuan and Jaehoon,


> -Original Message-
> From: Ziyuan Xu [mailto:xzy...@rock-chips.com]
> Sent: Wednesday, July 27, 2016 9:37 PM
> To: Jaehoon Chung; Yangbo Lu; u-boot@lists.denx.de; Tom Rini
> Cc: Pantelis Antoniou
> Subject: Re: [U-Boot] [PATCH] mmc: send CMD0 before CMD1 for some MMC
> cards
>
>
>
> On 2016年07月27日 19:15, Jaehoon Chung wrote:
>> On 07/27/2016 04:28 PM, Yangbo Lu wrote:
>>> Hi Tom,
>>>
>>> Could you help to assign this mmc patch reviewing to right person?
>>> It seems no one had reviewed it for almost half year.
>>>
>>> And another my mmc patch also needs to be reviewed.
>>> I submitted in May. Please help.
>>> http://patchwork.ozlabs.org/patch/624448/
>>>
>>>
>>> Thank you very much.
>>>
>>>
>>> Best regards,
>>> Yangbo Lu
>>>
 -Original Message-
 From: Yangbo Lu [mailto:yangbo...@nxp.com]
 Sent: Wednesday, March 09, 2016 11:00 AM
 To: u-boot@lists.denx.de
 Cc: Pantelis Antoniou; Yangbo Lu
 Subject: [PATCH] mmc: send CMD0 before CMD1 for some MMC cards

 When the MMC framework was added in u-boot, the mmc_go_idle was
 added before mmc_send_op_cond_iter in function mmc_send_op_cond
 annotating that some cards seemed to need this. Actually, we still
 need to do this in function mmc_complete_op_cond for those cards.
 This has been verified on Micron MTFC4GACAECN eMMC chip.
>> If there is no go_idle(), then what happen?
>> If you share the information more, i can check the more..
> Sounds interesting, I also want want to know what happen?
> It seems like you failed in CMD1? The eMMC device was always in busy
> device within 1 second?

 [Lu Yangbo-B47093] This was an issue which our customer reported and
>>> required us to fix in March.
 They used NXP LS1020A platform and Micron MTFC4GACAECN eMMC, and
>>> reported they had to add CMD0 as below.
 Otherwise it couldn’t read OCR.

 static int mmc_complete_op_cond(struct mmc *mmc) {
struct mmc_cmd cmd;
int timeout = 1000;
uint start;
int err;

 #if defined (XXX_CHANGED)
// our eMMC chip (Micron MTFC4GACAECN) requires that it be put in
>>> idle mode before
// negociating the operating voltage levels.
mmc_go_idle(mmc);
 #endif
>>>
>>> Well, it seems to fix workaround. mmc_go_idle() means Device Reset.
>>>
>>> mmc_complete_op_cond() function has added for reducing the booting time.
>>> If mmc_go_idle() is added at here, there is no benefit, and it should be
>>> back to old concept.
>>>
>>> I don't agree this patch..now.
>>>
>>
>> [Lu Yangbo-B47093] Did you notice mmc_send_op_cond function? Before 
>> mmc_send_op_cond_iter sending CMD1, there always was mmc_go_idle.
>> I don’t know why said 'Some cards seem to need this', but it must fix some 
>> issue.
>>
>> static int mmc_send_op_cond(struct mmc *mmc)
>> {
>> int err, i;
>>
>> /* Some cards seem to need this */
>> mmc_go_idle(mmc);
>>
>> /* Asking to the card its capabilities */
>> for (i = 0; i < 2; i++) {
>> err = mmc_send_op_cond_iter(mmc, i != 0);
>> if (err)
>> return err;
>>
>> /* exit if not busy (flag seems to be inverted) */
>> if (mmc->ocr & OCR_BUSY)
>> break;
>> }
>> mmc->op_cond_pending = 1;
>> return 0;
>> }
>>
>> Now in mmc_complete_op_cond function, there may be the same issue. Without 
>> the mmc_go_idle, mmc_send_op_cond_iter failed to get ocr.
>> Maybe I should move mmc_go_idle just before mmc_send_op_cond_iter, like this.
>>
>> static int mmc_complete_op_cond(struct mmc *mmc)
>> {
>> struct mmc_cmd cmd;
>> int timeout = 1000;
>> uint start;
>> int err;
>>
>> mmc->op_cond_pending = 0;
>> if (!(mmc->ocr & OCR_BUSY)) {
>> start = get_timer(0);
>> while (1) {
>>  /* Some cards seem to need this */
>>  mmc_go_idle(mmc);
>> err = mmc_send_op_cond_iter(mmc, 1);
> 
> If you need to add the mmc_go_idle(), then I think this point is right. :)

One more..i don't check in more detail.
Could you consider the below things?

1. located 

Re: [U-Boot] [PATCH] mmc: send CMD0 before CMD1 for some MMC cards

[Jaehoon Chung]

On 08/02/2016 04:03 PM, Yangbo Lu wrote:
> Hi Jaehoon,
> 
> 
>> -Original Message-
>> From: Jaehoon Chung [mailto:jh80.ch...@samsung.com]
>> Sent: Thursday, July 28, 2016 4:40 PM
>> To: Yangbo Lu; Ziyuan Xu; u-boot@lists.denx.de; Tom Rini
>> Cc: Pantelis Antoniou
>> Subject: Re: [U-Boot] [PATCH] mmc: send CMD0 before CMD1 for some MMC
>> cards
>>
>> Hi Yangbo,
>>
>> On 07/28/2016 11:45 AM, Yangbo Lu wrote:
>>> Hi Ziyuan and Jaehoon,
>>>
>>>
 -Original Message-
 From: Ziyuan Xu [mailto:xzy...@rock-chips.com]
 Sent: Wednesday, July 27, 2016 9:37 PM
 To: Jaehoon Chung; Yangbo Lu; u-boot@lists.denx.de; Tom Rini
 Cc: Pantelis Antoniou
 Subject: Re: [U-Boot] [PATCH] mmc: send CMD0 before CMD1 for some MMC
 cards



 On 2016年07月27日 19:15, Jaehoon Chung wrote:
> On 07/27/2016 04:28 PM, Yangbo Lu wrote:
>> Hi Tom,
>>
>> Could you help to assign this mmc patch reviewing to right person?
>> It seems no one had reviewed it for almost half year.
>>
>> And another my mmc patch also needs to be reviewed.
>> I submitted in May. Please help.
>> http://patchwork.ozlabs.org/patch/624448/
>>
>>
>> Thank you very much.
>>
>>
>> Best regards,
>> Yangbo Lu
>>
>>> -Original Message-
>>> From: Yangbo Lu [mailto:yangbo...@nxp.com]
>>> Sent: Wednesday, March 09, 2016 11:00 AM
>>> To: u-boot@lists.denx.de
>>> Cc: Pantelis Antoniou; Yangbo Lu
>>> Subject: [PATCH] mmc: send CMD0 before CMD1 for some MMC cards
>>>
>>> When the MMC framework was added in u-boot, the mmc_go_idle was
>>> added before mmc_send_op_cond_iter in function mmc_send_op_cond
>>> annotating that some cards seemed to need this. Actually, we still
>>> need to do this in function mmc_complete_op_cond for those cards.
>>> This has been verified on Micron MTFC4GACAECN eMMC chip.
> If there is no go_idle(), then what happen?
> If you share the information more, i can check the more..
 Sounds interesting, I also want want to know what happen?
 It seems like you failed in CMD1? The eMMC device was always in busy
 device within 1 second?
>>>
>>> [Lu Yangbo-B47093] This was an issue which our customer reported and
>> required us to fix in March.
>>> They used NXP LS1020A platform and Micron MTFC4GACAECN eMMC, and
>> reported they had to add CMD0 as below.
>>> Otherwise it couldn’t read OCR.
>>>
>>> static int mmc_complete_op_cond(struct mmc *mmc) {
>>> struct mmc_cmd cmd;
>>> int timeout = 1000;
>>> uint start;
>>> int err;
>>>
>>> #if defined (XXX_CHANGED)
>>> // our eMMC chip (Micron MTFC4GACAECN) requires that it be put in
>> idle mode before
>>> // negociating the operating voltage levels.
>>> mmc_go_idle(mmc);
>>> #endif
>>
>> Well, it seems to fix workaround. mmc_go_idle() means Device Reset.
>>
>> mmc_complete_op_cond() function has added for reducing the booting time.
>> If mmc_go_idle() is added at here, there is no benefit, and it should be
>> back to old concept.
>>
>> I don't agree this patch..now.
>>
> 
> [Lu Yangbo-B47093] Did you notice mmc_send_op_cond function? Before 
> mmc_send_op_cond_iter sending CMD1, there always was mmc_go_idle.
> I don’t know why said 'Some cards seem to need this', but it must fix some 
> issue.
> 
> static int mmc_send_op_cond(struct mmc *mmc)
> {
> int err, i;
> 
> /* Some cards seem to need this */
> mmc_go_idle(mmc);
> 
> /* Asking to the card its capabilities */
> for (i = 0; i < 2; i++) {
> err = mmc_send_op_cond_iter(mmc, i != 0);
> if (err)
> return err;
> 
> /* exit if not busy (flag seems to be inverted) */
> if (mmc->ocr & OCR_BUSY)
> break;
> }
> mmc->op_cond_pending = 1;
> return 0;
> }
> 
> Now in mmc_complete_op_cond function, there may be the same issue. Without 
> the mmc_go_idle, mmc_send_op_cond_iter failed to get ocr.
> Maybe I should move mmc_go_idle just before mmc_send_op_cond_iter, like this.
> 
> static int mmc_complete_op_cond(struct mmc *mmc)
> {
> struct mmc_cmd cmd;
> int timeout = 1000;
> uint start;
> int err;
> 
> mmc->op_cond_pending = 0;
> if (!(mmc->ocr & OCR_BUSY)) {
> start = get_timer(0);
> while (1) {
>   /* Some cards seem to need this */
>   mmc_go_idle(mmc);
> err = mmc_send_op_cond_iter(mmc, 1);

If you need to add the mmc_go_idle(), then I think this point is right. :)

Best Regards,
Jaehoon Chung

> 
> If you think it's not proper, do you have any suggestion?
> :)
> 
> Thanks a lot.
> 
>> Best Regards,
>> Jaehoon Chung
>>
>>>
>>>
>>> I hadn’t reproduce this to get more details about this issue since I
>> didn’t have one this kind