[U-Boot] [PATCH v1] ARM: at91: add default config file for sama5d36ek CMP board

[Wenyou Yang]

The sama5d36ek CMP board is the variant of sama5d3xek board.
It is equipped with the low-power DDR2 SDRAM, PMIC ACT8865, and
some power rail. Its main purpose is used to measure the power
consumption. As those changes are done in at91bootstrap,
in U-Boot, use another device tree file, no code to change.

As there is additional power consumption due to the USB Host
and USB Device enabled, for the power consumption measurement,
disable the USB host and device.

Signed-off-by: Wenyou Yang 
This patch is based on
[PATCH v1 0/7] board: sama5d3: convert boards to support DM/DT
http://lists.denx.de/pipermail/u-boot/2016-October/271253.html

---

 configs/sama5d36ek_cmp_mmc_defconfig   | 58 ++
 configs/sama5d36ek_cmp_nandflash_defconfig | 57 +
 configs/sama5d36ek_cmp_spiflash_defconfig  | 57 +
 include/configs/sama5d3xek.h   |  2 +-
 4 files changed, 173 insertions(+), 1 deletion(-)
 create mode 100644 configs/sama5d36ek_cmp_mmc_defconfig
 create mode 100644 configs/sama5d36ek_cmp_nandflash_defconfig
 create mode 100644 configs/sama5d36ek_cmp_spiflash_defconfig

diff --git a/configs/sama5d36ek_cmp_mmc_defconfig 
b/configs/sama5d36ek_cmp_mmc_defconfig
new file mode 100644
index 000..ee72c59
--- /dev/null
+++ b/configs/sama5d36ek_cmp_mmc_defconfig
@@ -0,0 +1,58 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3XEK=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xee00
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
+CONFIG_LCD=y
diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig 
b/configs/sama5d36ek_cmp_nandflash_defconfig
new file mode 100644
index 000..aabbf4a
--- /dev/null
+++ b/configs/sama5d36ek_cmp_nandflash_defconfig
@@ -0,0 +1,57 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3XEK=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names 
interrupt-parent"
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xee00
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
+CONFIG_LCD=y
diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig 
b/configs/sama5d36ek_cmp_spiflash_defconfig
new file mode 100644
index 000..e4131d9
--- /dev/null
+++ b/configs/sama5d36ek_cmp_spiflash_defconfig
@@ -0,0 +1,57 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3XEK=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
+CONFIG_FIT=y

[U-Boot] [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC node

[Wenbin song]

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment
and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose
which offset will be used. If GIC_ADDR_BIT bit is set, 4K alignment is used,
or else 64K alignment is used. The rev1.0 silicon only supports the CIG offset
with 4K alignment.

GIC offset is decided by SVR and GIC_ADDR_BIT bit.

Overriding the weak smp_kick_all_cpus, the new impletment is able to detect
GIC offset.

Signed-off-by: Wenbin Song 
Signed-off-by: Mingkai Hu 
---
Changes in v6:
Add comments around checking the revision. 
Changes in v5:
Replace fix_gic_off with get_gic_off.
Add #if condition to check CONFIG_GICV2 and CONFIG_GICV3 on 
smp_kick_all_cpus.
Fixup gic node with 64K alignment when running on rev1.1 with 
GIC_ADDR_BIT cleared. 
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  4 ++
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c| 71 ++
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   | 57 +++--
 arch/arm/include/asm/arch-fsl-layerscape/config.h  | 26 +++-
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  3 +-
 5 files changed, 154 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 94ec8d5..f415868 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -135,4 +135,8 @@ config SYS_FSL_DDR4
help
  Enable Freescale DDR4 controller.
 
+config HAS_FEATURE_GIC4K_ALIGN
+   bool
+   default y if ARCH_LS1043A
+
 endmenu
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 1a8321b..9936be1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -126,6 +126,74 @@ void fsl_fdt_disable_usb(void *blob)
}
 }
 
+#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
+static void fdt_fixup_gic(void *blob)
+{
+   int offset, err;
+   u64 reg[8];
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   unsigned int rev;
+   struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+   int align_4k = 1;
+
+   rev = gur_in32(>svr) & 0xff;
+   /*
+* For ls1043a rev1.0, the GIC offset aligns with 4K.
+* For ls1043a rev1.1 or more higher, the GIC offset
+* is decided by gic_align register.
+*/
+
+   if (rev > REV1_0) {
+   /*
+* The GIC_ADDR_BIT on gic_align was set by
+* PBI to select GIC offset.
+*/
+   rev = scfg_in32(>gic_align) & (0x01 << GIC_ADDR_BIT);
+   if (!rev)
+   align_4k = 0;
+   }
+
+   offset = fdt_subnode_offset(blob, 0, "interrupt-controller@140");
+   if (offset < 0) {
+   printf("WARNING: fdt_subnode_offset can't find node %s: %s\n",
+  "interrupt-controller@140", fdt_strerror(offset));
+   return;
+   }
+
+   /* Fixup gic node align with 4K */
+   if (align_4k) {
+   reg[0] = cpu_to_fdt64(GICD_BASE_4K);
+   reg[1] = cpu_to_fdt64(GICD_SIZE_4K);
+   reg[2] = cpu_to_fdt64(GICC_BASE_4K);
+   reg[3] = cpu_to_fdt64(GICC_SIZE_4K);
+   reg[4] = cpu_to_fdt64(GICH_BASE_4K);
+   reg[5] = cpu_to_fdt64(GICH_SIZE_4K);
+   reg[6] = cpu_to_fdt64(GICV_BASE_4K);
+   reg[7] = cpu_to_fdt64(GICV_SIZE_4K);
+   } else {
+   /* Fixup gic node align with 64K */
+   reg[0] = cpu_to_fdt64(GICD_BASE);
+   reg[1] = cpu_to_fdt64(GICD_SIZE);
+   reg[2] = cpu_to_fdt64(GICC_BASE);
+   reg[3] = cpu_to_fdt64(GICC_SIZE);
+   reg[4] = cpu_to_fdt64(GICH_BASE);
+   reg[5] = cpu_to_fdt64(GICH_SIZE);
+   reg[6] = cpu_to_fdt64(GICV_BASE);
+   reg[7] = cpu_to_fdt64(GICV_SIZE);
+   }
+
+   err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg));
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
+  "reg", "interrupt-controller@140",
+  fdt_strerror(err));
+   return;
+   }
+
+   return;
+}
+#endif
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 #ifdef CONFIG_FSL_LSCH2
@@ -170,4 +238,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #endif
fsl_fdt_disable_usb(blob);
 
+#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
+   fdt_fixup_gic(blob);
+#endif
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5d0b7a4..d50096c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -14,6 +14,55 @@
 #include 
 #endif
 
+
+/* 

[U-Boot] Device tree & PCI/ECAM questions

[Aaron Williams]

Hi all,

I am working on several drivers for our Octeon-TX/Thunder chips which 
talk to devices connected to the ECAM bus through another sub-bus and am 
having issues regarding the device tree.


We have a "PCI" driver to handle the ECAM and I created a simple-bus 
stub for our MRML bus which connects low-speed devices to the ECAM bus 
and all of the devices show up in the device tree.


My problem is that the devices also enumerated via PCI.

I have something like the following:

static int cavium_pci_mmc_probe(struct udevice *dev)
{
debug("%s: Entry\n", __func__);
pci_dev_t bdf = dm_pci_get_bdf(dev);
struct cavium_mmc_host *host = dev_get_priv(dev);
size_t size;
uint64_t base_addr = dm_pci_map_bar(dev, 0, , PCI_REGION_MEM);
int rc = 0;

host->base_addr = base_addr;
dev->req_seq = PCI_FUNC(bdf);

debug("%s(%s): ", __func__, dev->name);
debug("  platdata:%p\n"
  "  parent platdata: %p\n"
  "  uclass platdata: %p\n"
  "  base address:%lx\n"
  "  of_offset:   %d\n"
  "  parent:  %p\n"
  "  priv:%p\n"
  "  uclass:  %p\n"
  "  req_seq: %d\n"
  "  seq: %d\n",
  dev->platdata, dev->parent_platdata,
  dev->uclass_platdata, base_addr,
  dev->of_offset, dev->parent, dev->priv,
  dev->uclass, dev->req_seq, dev->seq);

if (dev->of_offset >= 0)
rc = process_node(dev, gd->fdt_blob, dev->of_offset);

return rc;
}

static const struct udevice_id cavium_mmc_ids[] = {
{ .compatible = "cavium,thunder-8890-mmc" },
{ .compatible = "cavium,mmc" },
{ },
};

static const struct udevice_id cavium_mmc_slot_ids[] = {
{ .compatible = "cavium,thunder-8890-mmc-slot" },
{ },
};

U_BOOT_DRIVER(cavium_pci_mmc) = {
.name= "mmc_cavium",
.id= UCLASS_MMC,
.of_match = of_match_ptr(cavium_mmc_ids),
.ofdata_to_platdata = cavium_mmc_ofdata_to_platdata,
.probe= cavium_pci_mmc_probe,
.priv_auto_alloc_size = sizeof(struct cavium_mmc_host),
.ops = NULL,
};

static struct pci_device_id cavium_pci_mmc_supported[] = {
{ PCI_VDEVICE(CAVIUM, PCI_DEVICE_ID_THUNDER_MMC) },
{},
};

U_BOOT_PCI_DEVICE(cavium_pci_mmc, cavium_pci_mmc_supported);

The problem I'm seeing is that in the probe function the of_offset field 
is always -1. Shouldn't it resolve this information via the compatible 
string in the device tree? How should I go about setting it up so that 
not only things like the base address get resolved but also the 
of_offset field since all of the slot configuration comes from the 
device tree.


In our case we have a single MMC device on the MRML bus connected to the 
ECAM bus (which looks like a PCI bus) which supports multiple slots with 
one set of registers.


-Aaron

--
Aaron Williams
Software Engineer
Cavium, Inc.
(408) 943-7198  (510) 789-8988 (cell)

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[U-Boot] [PATCH v6 2/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 MSI node

[Wenbin song]

There are two types of msi node in kernel device tree, one is for
LS1043A rev1.1 silicon, the other is for rev1.0.

According to revision number, fixup the msi node.

Signed-off-by: Wenbin Song 
Signed-off-by: Mingkai Hu 
---
Change in v6:
None
Change in v5:
Fixup the msi node used on rev1.0 when running on rev1.1.   
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |   3 +
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c   | 115 ++
 2 files changed, 118 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index f415868..34ac867 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -139,4 +139,7 @@ config HAS_FEATURE_GIC4K_ALIGN
bool
default y if ARCH_LS1043A
 
+config HAS_FEATURE_ENHANCED_MSI
+   bool
+   default y if ARCH_LS1043A
 endmenu
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 9936be1..e87ba19 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -194,6 +194,118 @@ static void fdt_fixup_gic(void *blob)
 }
 #endif
 
+#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
+static int _fdt_fixup_msi_subnode(void *blob, int offset, const char *name,
+ int irq_0, int irq_1, int rev)
+{
+   int err, sub_offset, len;
+   u32 tmp[4][3];
+
+   sub_offset = fdt_subnode_offset(blob, offset, name);
+   if (offset < 0) {
+   printf("WARNING: fdt_subnode_offset can't find %s: %s\n",
+  name, fdt_strerror(sub_offset));
+   return 0;
+   }
+
+   tmp[0][0] = cpu_to_fdt32(0x0);
+   tmp[0][1] = cpu_to_fdt32(irq_0);
+   tmp[0][2] = cpu_to_fdt32(0x4);
+
+   if (rev > REV1_0) {
+   tmp[1][0] = cpu_to_fdt32(0x0);
+   tmp[1][1] = cpu_to_fdt32(irq_1);
+   tmp[1][2] = cpu_to_fdt32(0x4);
+   tmp[2][0] = cpu_to_fdt32(0x0);
+   tmp[2][1] = cpu_to_fdt32(irq_1 + 1);
+   tmp[2][2] = cpu_to_fdt32(0x4);
+   tmp[3][0] = cpu_to_fdt32(0x0);
+   tmp[3][1] = cpu_to_fdt32(irq_1 + 2);
+   tmp[3][2] = cpu_to_fdt32(0x4);
+   len = sizeof(tmp);
+   } else {
+   len = sizeof(tmp[0]);
+   }
+
+   err = fdt_setprop(blob, sub_offset, "interrupts", tmp, len);
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
+  "interrupts", name, fdt_strerror(err));
+   return 0;
+   }
+
+   return 1;
+}
+
+static int _fdt_fixup_pci_msi(void *blob, const char *name, int rev)
+{
+   int offset, len, err;
+   void *p;
+   int val;
+   u32 tmp[4][8];
+
+   offset = fdt_path_offset(blob, name);
+   if (offset < 0) {
+   printf("WARNING: fdt_path_offset can't find path %s: %s\n",
+  name, fdt_strerror(offset));
+   return 0;
+   }
+
+   p = (char *)fdt_getprop(blob, offset, "interrupt-map", );
+   if (!p || len != sizeof(tmp)) {
+   printf("WARNING: fdt_getprop can't get %s from node %s\n",
+  "interrupt-map", name);
+   return 0;
+   }
+
+   memcpy((char *)tmp, p, len);
+
+   val = fdt32_to_cpu(tmp[0][6]);
+   if (rev > REV1_0) {
+   tmp[1][6] = cpu_to_fdt32(val + 1);
+   tmp[2][6] = cpu_to_fdt32(val + 2);
+   tmp[3][6] = cpu_to_fdt32(val + 3);
+   } else {
+   tmp[1][6] = cpu_to_fdt32(val);
+   tmp[2][6] = cpu_to_fdt32(val);
+   tmp[3][6] = cpu_to_fdt32(val);
+   }
+
+   err = fdt_setprop(blob, offset, "interrupt-map", tmp, sizeof(tmp));
+   if (err < 0) {
+   printf("WARNING: fdt_setprop can't set %s from node %s: %s.\n",
+  "interrupt-map", name, fdt_strerror(err));
+   return 0;
+   }
+   return 1;
+}
+
+/* Fixup msi to v1_0*/
+
+static void fdt_fixup_msi(void *blob)
+{
+   int nodeoffset;
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   unsigned int rev;
+
+   rev = gur_in32(>svr) & 0xff;
+
+   nodeoffset = fdt_path_offset(blob, "/soc/msi-controller");
+   if (nodeoffset < 0) {
+   printf("WARNING: fdt_path_offset can't find path %s: %s\n",
+  "/soc/msi-controller", fdt_strerror(nodeoffset));
+   return;
+   }
+   _fdt_fixup_msi_subnode(blob, nodeoffset, "msi0@1571000", 116, 111, rev);
+   _fdt_fixup_msi_subnode(blob, nodeoffset, "msi1@1572000", 126, 121, rev);
+   _fdt_fixup_msi_subnode(blob, nodeoffset, "msi2@1573000", 160, 155, rev);
+
+   _fdt_fixup_pci_msi(blob, "/soc/pcie@340", rev);
+   _fdt_fixup_pci_msi(blob, 

Re: [U-Boot] OMAP3630 Falcon Mode Questions

[Adam Ford]

On Mon, Oct 31, 2016 at 6:57 AM, Tom Rini  wrote:
> On Sat, Oct 29, 2016 at 12:53:27PM -0500, Adam Ford wrote:
>> I am trying to utilize Falcon mode on an OMAP3630 (DM3730), but it
>> just hangs, and I was hoping someone might find something obvious that
>> I missed.  I am able to boot from NAND through U-boot, so I know my
>> kernel and device tree are OK as are the boot parameters, MLO and
>> U-boot.
>>
>> I have read through the ./doc/README.falcon, and I read through some
>> of the am33 docs regarding this, and I think I'm doing it right, but
>> I'm obviously missing something.
>>
>> I have reset my partition structure to:
>> device nand0 , # parts = 6
>>  #: namesizeoffset  mask_flags
>>  0: MLO 0x0008  0x  0
>>  1: u-boot  0x001c  0x0008  0
>>  2: spl-os  0x0002  0x0024  0
>>  3: u-boot-env  0x0002  0x0026  0
>>  4: kernel  0x0080  0x0028  0
>>  5: fs  0x1f58  0x00a8  0
>>
>> My defines in the header file are set as follows:
>>
>> #define CONFIG_CMD_SPL_NAND_OFS 0x24
>> (matches spl-os offset)
>>
>> #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x28
>> (matches kernel offset)
>>
>> #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
>>
>>
>> #define CONFIG_SYS_TEXT_BASE 0x8010
>> #define CONFIG_SPL_BSS_START_ADDR 0x8000
>> #define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
>> #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
>> #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10
>>
>>
>> I build my uImage with LOADADDR=0x80008000
>>
>> My bootargs are as follows:
>> console=ttyO0,115200n8 ignore_loglevel early_printk no_console_suspend
>> root=ubi0:rootfs rw ubi.mtd=fs noinitrd rootfstype=ubifs rootwait
>> display=15 ignore_loglevel early_printk no_console_suspend
>> mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),8m(kernel),-(fs)
>>
>>
>> I can load uImage and fdtimage, then with the bootargs set, I run
>>
>> spl export fdt $loadaddr - $fdtaddr
>>
>> ## Booting kernel from Legacy Image at 8100 ...
>>Image Name:   Linux-4.9.0-rc2-00040-g9fe68ca-d
>>Image Type:   ARM Linux Kernel Image (uncompressed)
>>Data Size:3869952 Bytes = 3.7 MiB
>>Load Address: 80008000
>>Entry Point:  80008000
>>Verifying Checksum ... OK
>> ## Flattened Device Tree blob at 8600
>>Booting using the fdt blob at 0x8600
>>Loading Kernel Image ... OK
>>Loading Device Tree to 8df1f000, end 8df33114 ... OK
>> subcommand not supported
>> subcommand not supported
>>Loading Device Tree to 8df07000, end 8df1e114 ... OK
>> Argument image is now in RAM: 0x8df07000
>>
>> I then write this blob to my spl-os partition with the following:
>>
>> nand write 0x8df07000 spl-os 0x2
>>
>> When I eject the SD card and I boot from NAND (attempting) with Falcon
>> it just hangs:
>>
>> U-Boot SPL 2016.11-rc2-00164-g7904673-dirty (Oct 29 2016 - 10:28:32)
>> Trying to boot from NAND
>>
>> Does anyone know if I missed a step somewhere, or do I have something
>> configured incorrectly?
>
> OK, just to be clear, did you test reading the uImage and spl-os back in
> U-Boot and booting those?  If so and it works, try enabling DEBUG for
> SPL and seeing if you get more output.

I can load the uImage and the created spl-os back and it boots fine. I
enabled DEBUG, but I had to make a tweak to the printf statement to
get the name of Linux to display correctly.

Here is my dump:

U-Boot SPL 2016.11-rc3-9-g050adda-dirty (Oct 31 2016 - 18:29:40)
Trying to boot from NAND
spl: nand - using hw ecc
spl: payload image: Linux-4.9.0-rc2-00040-g9fe68ca-d load addr: 0x80007fc0 si
ze: 3869936
Jumping to Linux


In order to get to "Jumping to Linux"  I removed some of the default
memory overrides:

>From 050addab9986c35822bbe8f677fb8e7b2c4cb2f6 Mon Sep 17 00:00:00 2001
From: Adam Ford 
Date: Mon, 31 Oct 2016 18:19:39 -0500
Subject: [PATCH] OMAP3: omap3_logic_defconfig

Use the SPL info inherited from the common TI files.

diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 2dcc729..0bff817 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -19,14 +19,10 @@
  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  * 64 bytes before this address should be set aside for u-boot.img's
  * header. That is 0x800FFFC0--0x8010 should not be used for any
- * other needs.  We use this rather than the inherited defines from
- * ti_armv7_common.h for backwards compatibility.
+ * other needs.
  */
-#define CONFIG_SYS_TEXT_BASE   0x8010
-#define CONFIG_SPL_BSS_START_ADDR  0x8000
-#define CONFIG_SPL_BSS_MAX_SIZE(512 << 10) /* 512 KB */
-#define CONFIG_SYS_SPL_MALLOC_START0x80208000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10
+/* 

[U-Boot] [PATCH] net: mvgbe: Fix build error with CONFIG_PHYLIB

[Chris Packham]

Commit 5a49f17481bb ("net: mii: Use spatch to update miiphy_register")
updated the mvgbe implementation of smi_reg_read/smi_reg_write. Prior to
that change mvgbe_phy_read and mvgbe_phy_write where used as wrappers to
satisfy the phylib APIs. Because these functions weren't updated in that
commit build errors where triggered when CONFIG_PHYLIB was enabled.

Fix these build errors by removing mvgbe_phy_read and mvgbe_phy_write
and using smi_reg_read/smi_reg_write directly.

Signed-off-by: Chris Packham 
---
Looking at this closer it actually appears that the mvgbe driver has 2
places where a mii_dev is created. The first in mvgbe_phylib_init()
which is triggered when CONFIG_PHYLIB is enabled (this is where I
first noticed the build error), the second in mvgbe_initialize() which
is triggered when CONFIG_MII or CONFIG_CMD_MII is enabled.

I think this could do with some more cleaning up. But perhaps the build
error should be fixed first and then we can tackle the cleanup.

 drivers/net/mvgbe.c | 25 +++--
 1 file changed, 3 insertions(+), 22 deletions(-)

diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index c784cdcae265..f833efbe6779 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -177,25 +177,6 @@ static int smi_reg_write(struct mii_dev *bus, int phy_adr, 
int devad,
 }
 #endif
 
-#if defined(CONFIG_PHYLIB)
-int mvgbe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
-  int reg_addr)
-{
-   u16 data;
-   int ret;
-   ret = smi_reg_read(bus->name, phy_addr, reg_addr, );
-   if (ret)
-   return ret;
-   return data;
-}
-
-int mvgbe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
-   int reg_addr, u16 data)
-{
-   return smi_reg_write(bus->name, phy_addr, reg_addr, data);
-}
-#endif
-
 /* Stop and checks all queues */
 static void stop_queue(u32 * qreg)
 {
@@ -676,8 +657,8 @@ int mvgbe_phylib_init(struct eth_device *dev, int phyid)
printf("mdio_alloc failed\n");
return -ENOMEM;
}
-   bus->read = mvgbe_phy_read;
-   bus->write = mvgbe_phy_write;
+   bus->read = smi_reg_read;
+   bus->write = smi_reg_write;
strcpy(bus->name, dev->name);
 
ret = mdio_register(bus);
@@ -688,7 +669,7 @@ int mvgbe_phylib_init(struct eth_device *dev, int phyid)
}
 
/* Set phy address of the port */
-   mvgbe_phy_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid);
+   smi_reg_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid);
 
phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
-- 
2.10.2

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[U-Boot] [ANN] U-Boot v2016.11-rc3 released

[Tom Rini]

Hey all,

It's release day and v2016.11-rc3 is out.  I've just about cleaned out
my queue of stuff I want to take for this release.  What's outstanding
is perhaps another Kconfig migration or two, and whatever critical fixes
people point out.

While there's a few important things that've come in here what I really
want to call out is fixed (it was broken for a few weeks) and much
improved travis-ci support.  All of the qemu targets that I have made
work with test.py locally (upstream qemu, no defconfig mods) are now
also enabled and tested by travis-ci.  So all it takes now if you want
to replicate this level of testing yourself is to let travis-ci.org have
permission to your github.  All of the tests take a bit less than 2
hours wall-clock right now to run and covers most machines and
architectures.

As it stands now, I plan on doing the final release on November 14th as
scheduled.

Thanks all!

-- 
Tom


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Re: [U-Boot] [PATCH 01/20] rockchip: video: Correct HDMI data source selection

[Andrew F. Davis]

On 10/31/2016 03:39 PM, Simon Glass wrote:
> This code currently always selects the second source. It only worked
> because both sources are set up.
> 
> With the change to only init video devices that are present in the stdout
> environment variable, this fails. Fix it.
> 
> Signed-off-by: Simon Glass 
> ---
> 
>  drivers/video/rockchip/rk_hdmi.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/video/rockchip/rk_hdmi.c 
> b/drivers/video/rockchip/rk_hdmi.c
> index 7976c5e..72142dc 100644
> --- a/drivers/video/rockchip/rk_hdmi.c
> +++ b/drivers/video/rockchip/rk_hdmi.c
> @@ -899,7 +899,8 @@ static int rk_hdmi_probe(struct udevice *dev)
>   rk_setreg(>grf->soc_con6, 1 << 15);
>  
>   /* hdmi data from vop id */
> - rk_setreg(>grf->soc_con6, (vop_id == 1) ? (1 << 4) : (1 << 4));
> + rk_clrsetreg(>grf->soc_con6, 1 << 4,
> +  (vop_id == 1) ? (1 << 4) : 0);

Magic numbers, could this get fixed to:

#define CON6_SOMETHING bit(4)

same for other bits if anyone knows what they do.

>  
>   ret = hdmi_wait_for_hpd(priv->regs);
>   if (ret < 0) {
> 
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Re: [U-Boot] [PATCH v5 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC node

[york sun]

On 10/30/2016 07:10 PM, Wenbin Song wrote:
> Hi york:
>
>
> Best Regards
> Wenbin Song
>
>> -Original Message-
>> From: york sun
>> Sent: Friday, October 28, 2016 11:40 PM
>> To: Wenbin Song ; albert.u.b...@aribaud.net;
>> Mingkai Hu ; u-boot@lists.denx.de
>> Subject: Re: [PATCH v5 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC
>> node
>>
>> On 10/27/2016 02:06 AM, Wenbin song wrote:
>>> The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
>>> alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
>>> is used to choose which offset will be used. If GIC_ADDR_BIT bit is
>>> set, 4K alignment is used, or else 64K alignment is used. The rev1.0
>>> silicon only supports the CIG offset with 4K alignment.
>>>
>>> GIC offset is decided by SVR and GIC_ADDR_BIT bit.
>>>
>>> Overriding the weak smp_kick_all_cpus, the new impletment is able to
>>> detect GIC offset.
>>>
>>> Signed-off-by: Wenbin Song 
>>> Signed-off-by: Mingkai Hu 
>>> ---
>>> Changes in v5:
>>> Replace fix_gic_off with get_gic_off.
>>> Add #if condition to check CONFIG_GICV2 and CONFIG_GICV3 on
>> smp_kick_all_cpus.
>>> Fixup gic node with 64K alignment when running on rev1.1 with
>> GIC_ADDR_BIT cleared.
>>> ---
>>
>> 
>>
>>>
>>> +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN static void fdt_fixup_gic(void
>>> +*blob) {
>>> +   int offset, err;
>>> +   u64 reg[8];
>>> +   struct ccsr_gur __iomem *gur = (void
>> *)(CONFIG_SYS_FSL_GUTS_ADDR);
>>> +   unsigned int rev;
>>> +   struct ccsr_scfg __iomem *scfg = (void
>> *)CONFIG_SYS_FSL_SCFG_ADDR;
>>> +   int align_4k = 1;
>>> +
>>> +   rev = gur_in32(>svr) & 0xff;
>>> +
>>> +   if (rev > REV1_0) {
>>> +   rev = scfg_in32(>gic_align) & (0x01 << GIC_ADDR_BIT);
>>> +   if (!rev)
>>> +   align_4k = 0;
>>> +   }
>>> +
>>
>> Does this register scfg->gic_align exist for other SoCs? Can you get a 
>> consistent
>> reading from this register if not set by PBI? If yes, can you revert the 
>> logic in PBI
>> command to set this bit in backward compatible way?
>
>
> []  scfg->gic_align  is a new added  register on ls1043a rev1.1 or more 
> higher  to select the GIC offset by PBI.
> If it is set by PBI,  GIC offset is 4K alignment.
> If it is cleared by PBI, GIC offset is 64K alignment.
> The reset value is cleared.
>
> So for ls1043a rev1.1 or more higher , we are be able to select the GIC 
> offset  by using different rcw.
> If  not set by PBI, reading from it always gets  0.
>
>  And the scfg->gic_align is reserved for other SoCs.

So it is hard-wired to 0 for 64K. Keep you code to check the revision 
then. Maybe put a comment around checking the revision to warn later use 
for other SoCs?

York

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[U-Boot] [PATCH 20/20] rockchip: Add support for veyron-mickey (Chromebit)

[Simon Glass]

This adds support for the Asus Chromebit, and RK3288-based device designed
to plug directly into an HDMI monitor. The device tree file comes from
Linux v4.8.

Signed-off-by: Simon Glass 
---

 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/rk3288-veyron-mickey.dts | 265 ++
 arch/arm/mach-rockchip/rk3288-board-spl.c |   3 +-
 arch/arm/mach-rockchip/rk3288/Kconfig |   9 +
 board/google/veyron/Kconfig   |  16 ++
 board/google/veyron/MAINTAINERS   |   7 +
 configs/chromebit_mickey_defconfig|  84 ++
 7 files changed, 384 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/rk3288-veyron-mickey.dts
 create mode 100644 configs/chromebit_mickey_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index af8b0de..5723c1b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -30,6 +30,7 @@ dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-firefly.dtb \
rk3288-veyron-jerry.dtb \
+   rk3288-veyron-mickey.dtb \
rk3288-rock2-square.dtb \
rk3288-evb.dtb \
rk3288-fennec.dtb \
diff --git a/arch/arm/dts/rk3288-veyron-mickey.dts 
b/arch/arm/dts/rk3288-veyron-mickey.dts
new file mode 100644
index 000..3da5038
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-mickey.dts
@@ -0,0 +1,265 @@
+/*
+ * Google Veyron Mickey Rev 0 board device tree source
+ *
+ * Copyright 2015 Google, Inc
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "rk3288-veyron-chromebook.dtsi"
+
+/ {
+   model = "Google Mickey";
+   compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7",
+"google,veyron-mickey-rev6", "google,veyron-mickey-rev5",
+"google,veyron-mickey-rev4", "google,veyron-mickey-rev3",
+"google,veyron-mickey-rev2", "google,veyron-mickey-rev1",
+"google,veyron-mickey-rev0", "google,veyron-mickey",
+"google,veyron", "rockchip,rk3288";
+
+   vcc_5v: vcc-5v {
+   vin-supply = <_sys>;
+   };
+
+   vcc33_io: vcc33_io {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc33_io";
+   regulator-always-on;
+   regulator-boot-on;
+   vin-supply = <_sys>;
+   };
+};
+
+_thermal {
+   /delete-node/ trips;
+   /delete-node/ cooling-maps;
+
+   trips {
+   cpu_alert_almost_warm: cpu_alert_almost_warm {
+   temperature = <63000>; /* millicelsius */
+   hysteresis = <2000>; /* millicelsius */
+   type = "passive";
+   };
+   cpu_alert_warm: cpu_alert_warm {
+   temperature = <65000>; /* millicelsius */
+   hysteresis = <2000>; /* millicelsius */
+   type = "passive";
+   };
+   cpu_alert_almost_hot: 

[U-Boot] [PATCH 04/20] dm: core: Handle global_data moving in SPL

[Simon Glass]

When CONFIG_SPL_STACK_R is enabled, and spl_init() is called before
board_init_r(), spl_relocate_stack_gd() will move global_data to a new
place in memory. This affects driver model since it uses a list for the
uclasses. Unless this is updated the list will become invalid. When
looking for a non-existent uclass, such as when adding a new one, the loop
in uclass_find() may continue forever, thus causing a hang.

Add a function to correct this rather obscure bug.

Signed-off-by: Simon Glass 
---

 common/spl/spl.c|  3 +++
 drivers/core/root.c |  7 +++
 include/dm/root.h   | 10 ++
 3 files changed, 20 insertions(+)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index bdb165a..9dc9e22 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -511,6 +511,9 @@ ulong spl_relocate_stack_gd(void)
ptr = CONFIG_SPL_STACK_R_ADDR - roundup(sizeof(gd_t),16);
new_gd = (gd_t *)ptr;
memcpy(new_gd, (void *)gd, sizeof(gd_t));
+#if CONFIG_IS_ENABLED(CONFIG_DM)
+   dm_fixup_for_gd_move(new_gd);
+#endif
 #if !defined(CONFIG_ARM)
gd = new_gd;
 #endif
diff --git a/drivers/core/root.c b/drivers/core/root.c
index 33dc9c0..9edfc1e 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -41,6 +41,13 @@ struct udevice *dm_root(void)
return gd->dm_root;
 }
 
+void dm_fixup_for_gd_move(struct global_data *new_gd)
+{
+   /* The sentinel node has moved, so update things that point to it */
+   new_gd->uclass_root.next->prev = _gd->uclass_root;
+   new_gd->uclass_root.prev->next = _gd->uclass_root;
+}
+
 fdt_addr_t dm_get_translation_offset(void)
 {
struct udevice *root = dm_root();
diff --git a/include/dm/root.h b/include/dm/root.h
index c7f0c1d..3cf730d 100644
--- a/include/dm/root.h
+++ b/include/dm/root.h
@@ -21,6 +21,16 @@ struct udevice;
  */
 struct udevice *dm_root(void);
 
+struct global_data;
+/**
+ * dm_fixup_for_gd_move() - Handle global_data moving to a new place
+ *
+ * The uclass list is part of global_data. Due to the way lists work, moving
+ * the list will cause it to become invalid. This function fixes that up so
+ * that the uclass list will work correctly.
+ */
+void dm_fixup_for_gd_move(struct global_data *new_gd);
+
 /**
  * dm_scan_platdata() - Scan all platform data and bind drivers
  *
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH 19/20] rockchip: veyron: Adjust ARM clock after relocation

[Simon Glass]

Update board_init() to increase the ARM clock to the maximum speed on
veyron boards. This makes quite a large difference in performance. With
this change, speed goes from about 750 DMIPS to 2720 DMIPs.

Signed-off-by: Simon Glass 
---

 arch/arm/mach-rockchip/rk3288-board.c | 44 +++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3288-board.c 
b/arch/arm/mach-rockchip/rk3288-board.c
index baf9522..bca6075 100644
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -16,6 +16,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -56,6 +58,39 @@ int board_late_init(void)
return rk_board_late_init();
 }
 
+#ifndef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+static int veyron_init(void)
+{
+   struct udevice *dev;
+   struct clk clk;
+   int ret;
+
+   ret = regulator_get_by_platname("vdd_arm", );
+   if (ret)
+   return ret;
+
+   /* Slowly raise to max CPU voltage to prevent overshoot */
+   ret = regulator_set_value(dev, 120);
+   if (ret)
+   return ret;
+   udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
+   ret = regulator_set_value(dev, 140);
+   if (ret)
+   return ret;
+   udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
+
+   ret = rockchip_get_clk();
+   if (ret)
+   return ret;
+   clk.id = PLL_APLL;
+   ret = clk_set_rate(, 18);
+   if (IS_ERR_VALUE(ret))
+   return ret;
+
+   return 0;
+}
+#endif
+
 int board_init(void)
 {
 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
@@ -87,6 +122,15 @@ err:
 
return -1;
 #else
+   int ret;
+
+   /* We do some SoC one time setting here */
+   if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
+   ret = veyron_init();
+   if (ret)
+   return ret;
+   }
+
return 0;
 #endif
 }
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH 03/20] rockchip: Allow jerry to use of-platdata

[Simon Glass]

This board always boots from SPI, so update the code to support that with
of-platdata. The boot source is not currently available with of-platdata.

Signed-off-by: Simon Glass 
---

 arch/arm/mach-rockchip/rk3288-board-spl.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c 
b/arch/arm/mach-rockchip/rk3288-board-spl.c
index 0f40351..185b5fd 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -64,6 +64,8 @@ u32 spl_boot_device(void)
}
 
 fallback:
+#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
+   return BOOT_DEVICE_SPI;
 #endif
return BOOT_DEVICE_MMC1;
 }
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH 02/20] rockchip: video: Correct VOP clock selection

[Simon Glass]

This code incorrectly uses the oscillator. It should use the clock
selected in the device tree.

Signed-off-by: Simon Glass 
Fixes: 135aa95 (clk: convert API to match reset/mailbox style)
---

 drivers/video/rockchip/rk_vop.c | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index c6d88d9..130dace 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -195,7 +195,6 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
struct udevice *disp;
int ret, remote, i, offset;
struct display_plat *disp_uc_plat;
-   struct udevice *dev_clk;
struct clk clk;
 
vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
@@ -238,11 +237,7 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
return ret;
}
 
-   ret = rockchip_get_clk(_clk);
-   if (!ret) {
-   clk.id = DCLK_VOP0 + remote_vop_id;
-   ret = clk_request(dev_clk, );
-   }
+   ret = clk_get_by_index(dev, 1, );
if (!ret)
ret = clk_set_rate(, timing.pixelclock.typ);
if (ret) {
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH 16/20] rockchip: Rename jerry files to veyron

[Simon Glass]

At present we have a single rk3288-based Chromebook: chromebook_jerry. But
all such Chromebooks can use the same binary with only device-tree
differences. The family name is 'veyron', so rename the files accordingly.

Also update the device-tree filename since this currently differs from
Linux.

Signed-off-by: Simon Glass 
---

 arch/arm/dts/Makefile  | 2 +-
 arch/arm/dts/{rk3288-jerry.dts => rk3288-veyron-jerry.dts} | 0
 arch/arm/mach-rockchip/rk3288/Kconfig  | 2 +-
 board/google/{chromebook_jerry => veyron}/Kconfig  | 4 ++--
 board/google/{chromebook_jerry => veyron}/MAINTAINERS  | 4 ++--
 board/google/{chromebook_jerry => veyron}/Makefile | 2 +-
 board/google/{chromebook_jerry/jerry.c => veyron/veyron.c} | 0
 configs/chromebook_jerry_defconfig | 2 +-
 include/configs/{chromebook_jerry.h => veyron.h}   | 0
 9 files changed, 8 insertions(+), 8 deletions(-)
 rename arch/arm/dts/{rk3288-jerry.dts => rk3288-veyron-jerry.dts} (100%)
 rename board/google/{chromebook_jerry => veyron}/Kconfig (74%)
 rename board/google/{chromebook_jerry => veyron}/MAINTAINERS (60%)
 rename board/google/{chromebook_jerry => veyron}/Makefile (81%)
 rename board/google/{chromebook_jerry/jerry.c => veyron/veyron.c} (100%)
 rename include/configs/{chromebook_jerry.h => veyron.h} (100%)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 836a8c4..af8b0de 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -29,7 +29,7 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-firefly.dtb \
-   rk3288-jerry.dtb \
+   rk3288-veyron-jerry.dtb \
rk3288-rock2-square.dtb \
rk3288-evb.dtb \
rk3288-fennec.dtb \
diff --git a/arch/arm/dts/rk3288-jerry.dts 
b/arch/arm/dts/rk3288-veyron-jerry.dts
similarity index 100%
rename from arch/arm/dts/rk3288-jerry.dts
rename to arch/arm/dts/rk3288-veyron-jerry.dts
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig 
b/arch/arm/mach-rockchip/rk3288/Kconfig
index c53d2e2..30c557b 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -88,7 +88,7 @@ source "board/chipspark/popmetal_rk3288/Kconfig"
 
 source "board/firefly/firefly-rk3288/Kconfig"
 
-source "board/google/chromebook_jerry/Kconfig"
+source "board/google/veyron/Kconfig"
 
 source "board/radxa/rock2/Kconfig"
 
diff --git a/board/google/chromebook_jerry/Kconfig b/board/google/veyron/Kconfig
similarity index 74%
rename from board/google/chromebook_jerry/Kconfig
rename to board/google/veyron/Kconfig
index 3640513..b1f51ce 100644
--- a/board/google/chromebook_jerry/Kconfig
+++ b/board/google/veyron/Kconfig
@@ -1,13 +1,13 @@
 if TARGET_CHROMEBOOK_JERRY
 
 config SYS_BOARD
-   default "chromebook_jerry"
+   default "veyron"
 
 config SYS_VENDOR
default "google"
 
 config SYS_CONFIG_NAME
-   default "chromebook_jerry"
+   default "veyron"
 
 config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
diff --git a/board/google/chromebook_jerry/MAINTAINERS 
b/board/google/veyron/MAINTAINERS
similarity index 60%
rename from board/google/chromebook_jerry/MAINTAINERS
rename to board/google/veyron/MAINTAINERS
index b01b6cd..d641eed 100644
--- a/board/google/chromebook_jerry/MAINTAINERS
+++ b/board/google/veyron/MAINTAINERS
@@ -1,6 +1,6 @@
 CHROMEBOOK JERRY BOARD
 M: Simon Glass 
 S: Maintained
-F: board/google/chromebook_jerry/
-F: include/configs/chromebook_jerry.h
+F: board/google/veyron/
+F: include/configs/veyron.h
 F: configs/chromebook_jerry_defconfig
diff --git a/board/google/chromebook_jerry/Makefile 
b/board/google/veyron/Makefile
similarity index 81%
rename from board/google/chromebook_jerry/Makefile
rename to board/google/veyron/Makefile
index d29a063..9868357 100644
--- a/board/google/chromebook_jerry/Makefile
+++ b/board/google/veyron/Makefile
@@ -4,4 +4,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  += jerry.o
+obj-y  += veyron.o
diff --git a/board/google/chromebook_jerry/jerry.c 
b/board/google/veyron/veyron.c
similarity index 100%
rename from board/google/chromebook_jerry/jerry.c
rename to board/google/veyron/veyron.c
diff --git a/configs/chromebook_jerry_defconfig 
b/configs/chromebook_jerry_defconfig
index 6f4ae18..46df1a6 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -7,7 +7,7 @@ CONFIG_TARGET_CHROMEBOOK_JERRY=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SPL_STACK_R_ADDR=0x8
-CONFIG_DEFAULT_DEVICE_TREE="rk3288-jerry"
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry"
 CONFIG_SILENT_CONSOLE=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_STACK_R=y
diff --git a/include/configs/chromebook_jerry.h b/include/configs/veyron.h
similarity index 100%
rename from 

[U-Boot] [PATCH 18/20] rockchip: clk: Support setting ACLK

[Simon Glass]

Add basic support for setting the ARM clock, since this allows us to run
at maximum speed in U-Boot. Currently only a single speed is supported
(1.8GHz).

Signed-off-by: Simon Glass 
---

 drivers/clk/rockchip/clk_rk3288.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3288.c 
b/drivers/clk/rockchip/clk_rk3288.c
index ed97e87..d15504c 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -691,6 +691,13 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong 
rate)
 
gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
switch (clk->id) {
+   case PLL_APLL:
+   /* We only support a fixed rate here */
+   if (rate != 18)
+   return -EINVAL;
+   rk3288_clk_configure_cpu(priv->cru, priv->grf);
+   new_rate = rate;
+   break;
case CLK_DDR:
new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
break;
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH 17/20] rockchip: Move jerry SDRAM settings into its own .dts file

[Simon Glass]

The SDRAM settings are not common across all veyron models. Move the
current settings into Jerry's file.

Signed-off-by: Simon Glass 
---

 arch/arm/dts/rk3288-veyron-jerry.dts | 11 +++
 arch/arm/dts/rk3288-veyron.dtsi  |  8 
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts 
b/arch/arm/dts/rk3288-veyron-jerry.dts
index da37ea8..8aab607 100644
--- a/arch/arm/dts/rk3288-veyron-jerry.dts
+++ b/arch/arm/dts/rk3288-veyron-jerry.dts
@@ -55,6 +55,17 @@
};
 };
 
+ {
+   rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
+   0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+   0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+   0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+   0x5 0x0>;
+   rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+   0xa60 0x40 0x10 0x0>;
+   rockchip,sdram-params = <0x30B25564 0x627 3 66600 3 9 1>;
+};
+
 _keys {
power {
gpios = < 5 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index 2ffe39c..a314058 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -245,14 +245,6 @@
533000 115
666000 120
>;
-   rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
-   0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
-   0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
-   0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
-   0x5 0x0>;
-   rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
-   0xa60 0x40 0x10 0x0>;
-   rockchip,sdram-params = <0x30B25564 0x627 3 66600 3 9 1>;
 };
 
  {
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH 15/20] rockchip: Move jerry to use of-platdata

[Simon Glass]

Adjust jerry to use of-platdata like other rk3288 boards. This reduces the
SPL size enough that it boots again.

Signed-off-by: Simon Glass 
---

 configs/chromebook_jerry_defconfig | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/configs/chromebook_jerry_defconfig 
b/configs/chromebook_jerry_defconfig
index 876adc4..6f4ae18 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -1,12 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_MMC_SUPPORT is not set
-CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_ROCKCHIP_RK3288=y
 CONFIG_TARGET_CHROMEBOOK_JERRY=y
-CONFIG_ROCKCHIP_FAST_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SPL_STACK_R_ADDR=0x8
@@ -36,7 +33,7 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
@@ -71,6 +68,7 @@ CONFIG_DEBUG_UART_BASE=0xff69
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
+CONFIG_ROCKCHIP_SERIAL=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_DM_VIDEO=y
@@ -80,3 +78,5 @@ CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
+CONFIG_SPL_OF_PLATDATA=y
+# CONFIG_SPL_OF_LIBFDT is not set
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH 14/20] rockchip: video: Check for device in use

[Simon Glass]

Check whether a display device is in use before using it. Add a comment as
to why two displays cannot currently be used at the same time.

This allows us to remove the device-tree change that disables vopb on
jerry.

Signed-off-by: Simon Glass 
---

 arch/arm/dts/rk3288-jerry.dts  | 5 -
 arch/arm/dts/rk3288-veyron-chromebook.dtsi | 2 ++
 drivers/video/rockchip/rk_vop.c| 9 +
 3 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/rk3288-jerry.dts b/arch/arm/dts/rk3288-jerry.dts
index 2aa3b9f..da37ea8 100644
--- a/arch/arm/dts/rk3288-jerry.dts
+++ b/arch/arm/dts/rk3288-jerry.dts
@@ -108,11 +108,6 @@
pinctrl-0 = <_hdmi_en>;
 };
 
- {
-   /* Disable this so that we use vopl */
-   status = "disabled";
-};
-
  {
pinctrl-names = "default";
pinctrl-0 = <_hpd>;
diff --git a/arch/arm/dts/rk3288-veyron-chromebook.dtsi 
b/arch/arm/dts/rk3288-veyron-chromebook.dtsi
index bbbc2f4..f88a868 100644
--- a/arch/arm/dts/rk3288-veyron-chromebook.dtsi
+++ b/arch/arm/dts/rk3288-veyron-chromebook.dtsi
@@ -13,6 +13,8 @@
 / {
aliases {
i2c20 = _tunnel;
+   video0 = 
+   video1 = 
};
 
gpio_keys: gpio-keys {
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index 130dace..eab5486 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -221,6 +221,11 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
 
disp_uc_plat = dev_get_uclass_platdata(disp);
debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
+   if (display_in_use(disp)) {
+   debug("   - device in use\n");
+   return -EBUSY;
+   }
+
disp_uc_plat->source_id = remote_vop_id;
disp_uc_plat->src_dev = dev;
 
@@ -311,6 +316,10 @@ static int rk_vop_probe(struct udevice *dev)
/*
 * Try all the ports until we find one that works. In practice this
 * tries EDP first if available, then HDMI.
+*
+* Note that rockchip_vop_set_clk() always uses NPLL as the source
+* clock so it is currently not possible to use more than one display
+* device simultaneously.
 */
port = fdt_subnode_offset(blob, dev->of_offset, "port");
if (port < 0)
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH 13/20] video: Track whether a display is in use

[Simon Glass]

Mark a display as in use when display_enable() is called. This can avoid
a display being used by multiple video-output devices.

Signed-off-by: Simon Glass 
---

 drivers/video/display-uclass.c | 18 +-
 include/display.h  | 10 ++
 2 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/video/display-uclass.c b/drivers/video/display-uclass.c
index e4763de..e752eb0 100644
--- a/drivers/video/display-uclass.c
+++ b/drivers/video/display-uclass.c
@@ -23,10 +23,19 @@ int display_enable(struct udevice *dev, int panel_bpp,
const struct display_timing *timing)
 {
struct dm_display_ops *ops = display_get_ops(dev);
+   struct display_plat *disp_uc_plat;
+   int ret;
 
if (!ops || !ops->enable)
return -ENOSYS;
-   return ops->enable(dev, panel_bpp, timing);
+   ret = ops->enable(dev, panel_bpp, timing);
+   if (ret)
+   return ret;
+
+   disp_uc_plat = dev_get_uclass_platdata(dev);
+   disp_uc_plat->in_use = true;
+
+   return 0;
 }
 
 int display_read_timing(struct udevice *dev, struct display_timing *timing)
@@ -48,6 +57,13 @@ int display_read_timing(struct udevice *dev, struct 
display_timing *timing)
return edid_get_timing(buf, ret, timing, _bits_per_colour);
 }
 
+bool display_in_use(struct udevice *dev)
+{
+   struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
+
+   return disp_uc_plat->in_use;
+}
+
 UCLASS_DRIVER(display) = {
.id = UCLASS_DISPLAY,
.name   = "display",
diff --git a/include/display.h b/include/display.h
index b1c4766..d0a08d4 100644
--- a/include/display.h
+++ b/include/display.h
@@ -16,10 +16,12 @@ struct display_timing;
  * @source_id: ID for the source of the display data, typically a video
  * controller
  * @src_dev:   Source device providing the video
+ * @in_use:Display is being used
  */
 struct display_plat {
int source_id;
struct udevice *src_dev;
+   bool in_use;
 };
 
 /**
@@ -41,6 +43,14 @@ int display_read_timing(struct udevice *dev, struct 
display_timing *timing);
 int display_enable(struct udevice *dev, int panel_bpp,
   const struct display_timing *timing);
 
+/**
+ * display_in_use() - Check if a display is in use by any device
+ *
+ * @return true if the device is in use (display_enable() has been called
+ * successfully), else false
+ */
+bool display_in_use(struct udevice *dev);
+
 struct dm_display_ops {
/**
 * read_timing() - Read information directly
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH 11/20] spi: Add a debug() on bind failure

[Simon Glass]

This is an uncommon error but we may as well have a debug() message when
it happens.

Signed-off-by: Simon Glass 
---

 drivers/spi/spi-uclass.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 358e229..b251442 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -297,8 +297,11 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int 
mode,
debug("%s: Binding new device '%s', busnum=%d, cs=%d, 
driver=%s\n",
  __func__, dev_name, busnum, cs, drv_name);
ret = device_bind_driver(bus, drv_name, dev_name, );
-   if (ret)
+   if (ret) {
+   debug("%s: Unable to bind driver (ret=%d)\n", __func__,
+ ret);
return ret;
+   }
plat = dev_get_parent_platdata(dev);
plat->cs = cs;
plat->max_hz = speed;
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH 10/20] spi: Add error checking for invalid bus widths

[Simon Glass]

At present an invalid bus width prints a message but does not return an
error. This is the opposite of the correct behaviour. Adjust it to avoid
code bloat in the common case, and avoid hard-to-debug failure in the
uncommon case.

Signed-off-by: Simon Glass 
---

 drivers/spi/spi-uclass.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 26eada2..358e229 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -415,8 +415,8 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node,
mode |= SPI_TX_QUAD;
break;
default:
-   error("spi-tx-bus-width %d not supported\n", value);
-   break;
+   debug("spi-tx-bus-width %d not supported\n", value);
+   return -EPROTONOSUPPORT;
}
 
value = fdtdec_get_uint(blob, node, "spi-rx-bus-width", 1);
@@ -430,8 +430,8 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node,
mode |= SPI_RX_QUAD;
break;
default:
-   error("spi-rx-bus-width %d not supported\n", value);
-   break;
+   debug("spi-rx-bus-width %d not supported\n", value);
+   return -EPROTONOSUPPORT;
}
 
plat->mode = mode;
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH 12/20] video: Use cache-alignment in video_sync()

[Simon Glass]

Sometimes the frame buffer is not a multiple of the cache line size.
Adjust the cache-flushing code to avoid cache warnings/errors in this
case.

Signed-off-by: Simon Glass 
---

 drivers/video/video-uclass.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index 11ca793..3036e3a 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -117,7 +117,8 @@ void video_sync(struct udevice *vid)
 
if (priv->flush_dcache) {
flush_dcache_range((ulong)priv->fb,
-  (ulong)priv->fb + priv->fb_size);
+  ALIGN((ulong)priv->fb + priv->fb_size,
+CONFIG_SYS_CACHELINE_SIZE));
}
 #elif defined(CONFIG_VIDEO_SANDBOX_SDL)
struct video_priv *priv = dev_get_uclass_priv(vid);
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH 09/20] rockchip: spi: Honour the deactivation delay

[Simon Glass]

This is not currently implemented. Add support for this so that the Chrome
OS EC can be used on jerry.

Signed-off-by: Simon Glass 
---

 drivers/spi/rk_spi.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 8d64249..15cf0bd 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -110,6 +110,14 @@ static void spi_cs_activate(struct udevice *dev, uint cs)
struct rockchip_spi_priv *priv = dev_get_priv(bus);
struct rockchip_spi *regs = priv->regs;
 
+   /* If it's too soon to do another transaction, wait */
+   if (plat->deactivate_delay_us && priv->last_transaction_us) {
+   ulong delay_us; /* The delay completed so far */
+   delay_us = timer_get_us() - priv->last_transaction_us;
+   if (delay_us < plat->deactivate_delay_us)
+   udelay(plat->deactivate_delay_us - delay_us);
+   }
+
debug("activate cs%u\n", cs);
writel(1 << cs, >ser);
if (plat->activate_delay_us)
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH 08/20] rockchip: spi: Add support for of-platdata

[Simon Glass]

Allow this driver to be used with of-platdata on rk3288.

Signed-off-by: Simon Glass 
---

 drivers/spi/rk_spi.c | 36 +++-
 1 file changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 105ee4a..8d64249 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -27,6 +28,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DEBUG_RK_SPI   0
 
 struct rockchip_spi_platdata {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+   struct dtd_rockchip_rk3288_spi of_plat;
+#endif
s32 frequency;  /* Default clock frequency, -1 for none */
fdt_addr_t base;
uint deactivate_delay_us;   /* Delay to wait after deactivate */
@@ -127,9 +131,29 @@ static void spi_cs_deactivate(struct udevice *dev, uint cs)
priv->last_transaction_us = timer_get_us();
 }
 
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int conv_of_platdata(struct udevice *dev)
+{
+   struct rockchip_spi_platdata *plat = dev->platdata;
+   struct dtd_rockchip_rk3288_spi *dtplat = >of_plat;
+   struct rockchip_spi_priv *priv = dev_get_priv(dev);
+   int ret;
+
+   plat->base = dtplat->reg[0];
+   plat->frequency = 2000;
+   ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, >clk);
+   if (ret < 0)
+   return ret;
+   dev->req_seq = 0;
+
+   return 0;
+}
+#endif
+
 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
 {
-   struct rockchip_spi_platdata *plat = bus->platdata;
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+   struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
struct rockchip_spi_priv *priv = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
@@ -153,6 +177,7 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice 
*bus)
debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
  __func__, (uint)plat->base, plat->frequency,
  plat->deactivate_delay_us);
+#endif
 
return 0;
 }
@@ -164,6 +189,11 @@ static int rockchip_spi_probe(struct udevice *bus)
int ret;
 
debug("%s: probe\n", __func__);
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+   ret = conv_of_platdata(bus);
+   if (ret)
+   return ret;
+#endif
priv->regs = (struct rockchip_spi *)plat->base;
 
priv->last_transaction_us = timer_get_us();
@@ -369,7 +399,11 @@ static const struct udevice_id rockchip_spi_ids[] = {
 };
 
 U_BOOT_DRIVER(rockchip_spi) = {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+   .name   = "rockchip_rk3288_spi",
+#else
.name   = "rockchip_spi",
+#endif
.id = UCLASS_SPI,
.of_match = rockchip_spi_ids,
.ops= _spi_ops,
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH 07/20] spi: Add of-platdata support to SPI and SPI flash

[Simon Glass]

Some boards may want to use these subsystems with of-platdata in SPL. Add
support for this by avoiding any device tree access in this case.

Signed-off-by: Simon Glass 
---

 drivers/mtd/spi/spi_flash.c |  2 +-
 drivers/spi/spi-uclass.c| 13 -
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 7f6e9ae..6571f86 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1228,7 +1228,7 @@ int spi_flash_scan(struct spi_flash *flash)
return ret;
 #endif
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
ret = spi_flash_decode_fdt(gd->fdt_blob, flash);
if (ret) {
debug("SF: FDT decode error\n");
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index d9c49e4..26eada2 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -108,6 +108,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
return dm_spi_xfer(slave->dev, bitlen, dout, din, flags);
 }
 
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
 static int spi_child_post_bind(struct udevice *dev)
 {
struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
@@ -117,14 +118,16 @@ static int spi_child_post_bind(struct udevice *dev)
 
return spi_slave_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, plat);
 }
+#endif
 
 static int spi_post_probe(struct udevice *bus)
 {
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
 
spi->max_hz = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
 "spi-max-frequency", 0);
-
+#endif
 #if defined(CONFIG_NEEDS_MANUAL_RELOC)
struct dm_spi_ops *ops = spi_get_ops(bus);
 
@@ -274,7 +277,11 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int 
mode,
bool created = false;
int ret;
 
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+   ret = uclass_first_device_err(UCLASS_SPI, );
+#else
ret = uclass_get_device_by_seq(UCLASS_SPI, busnum, );
+#endif
if (ret) {
printf("Invalid bus %d (err=%d)\n", busnum, ret);
return ret;
@@ -436,14 +443,18 @@ UCLASS_DRIVER(spi) = {
.id = UCLASS_SPI,
.name   = "spi",
.flags  = DM_UC_FLAG_SEQ_ALIAS,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.post_bind  = dm_scan_fdt_dev,
+#endif
.post_probe = spi_post_probe,
.child_pre_probe = spi_child_pre_probe,
.per_device_auto_alloc_size = sizeof(struct dm_spi_bus),
.per_child_auto_alloc_size = sizeof(struct spi_slave),
.per_child_platdata_auto_alloc_size =
sizeof(struct dm_spi_slave_platdata),
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.child_post_bind = spi_child_post_bind,
+#endif
 };
 
 UCLASS_DRIVER(spi_generic) = {
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH 05/20] stdio: Correct code style nits

[Simon Glass]

Fix a few code style nits in stdio_get_by_name().

Signed-off-by: Simon Glass 
---

 common/stdio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/stdio.c b/common/stdio.c
index 8e4a9be..a7d016b 100644
--- a/common/stdio.c
+++ b/common/stdio.c
@@ -173,12 +173,12 @@ static int stdio_probe_device(const char *name, enum 
uclass_id id,
 }
 #endif
 
-struct stdio_dev* stdio_get_by_name(const char *name)
+struct stdio_dev *stdio_get_by_name(const char *name)
 {
struct list_head *pos;
struct stdio_dev *sdev;
 
-   if(!name)
+   if (!name)
return NULL;
 
list_for_each(pos, &(devs.list)) {
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH 06/20] stdio: Correct numbering logic in stdio_probe_device()

[Simon Glass]

The current code assumes that the devices are ordered corresponding to
their alias value. But (for example) video1 can come before video0 in the
device tree.

Correct this, by always looking for device 0 first. After that we can fall
back to finding the first available device.

Signed-off-by: Simon Glass 
---

 common/stdio.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/common/stdio.c b/common/stdio.c
index a7d016b..4d30017 100644
--- a/common/stdio.c
+++ b/common/stdio.c
@@ -151,9 +151,10 @@ static int stdio_probe_device(const char *name, enum 
uclass_id id,
*sdevp = NULL;
seq = trailing_strtoln(name, NULL);
if (seq == -1)
+   seq = 0;
+   ret = uclass_get_device_by_seq(id, seq, );
+   if (ret == -ENODEV)
ret = uclass_first_device_err(id, );
-   else
-   ret = uclass_get_device_by_seq(id, seq, );
if (ret) {
debug("No %s device for seq %d (%s)\n", uclass_get_name(id),
  seq, name);
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH 01/20] rockchip: video: Correct HDMI data source selection

[Simon Glass]

This code currently always selects the second source. It only worked
because both sources are set up.

With the change to only init video devices that are present in the stdout
environment variable, this fails. Fix it.

Signed-off-by: Simon Glass 
---

 drivers/video/rockchip/rk_hdmi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index 7976c5e..72142dc 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -899,7 +899,8 @@ static int rk_hdmi_probe(struct udevice *dev)
rk_setreg(>grf->soc_con6, 1 << 15);
 
/* hdmi data from vop id */
-   rk_setreg(>grf->soc_con6, (vop_id == 1) ? (1 << 4) : (1 << 4));
+   rk_clrsetreg(>grf->soc_con6, 1 << 4,
+(vop_id == 1) ? (1 << 4) : 0);
 
ret = hdmi_wait_for_hpd(priv->regs);
if (ret < 0) {
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH] sunxi: Use the available Kconfig option for AHCI

[Jelle van der Waa]

Use the already available Kconfig option for AHCI. Tested on the
BananaPi.

Signed-off-by: Jelle van der Waa 
---
 configs/A10-OLinuXino-Lime_defconfig   | 3 ++-
 configs/A20-OLinuXino-Lime2_defconfig  | 3 ++-
 configs/A20-OLinuXino-Lime_defconfig   | 3 ++-
 configs/A20-OLinuXino_MICRO_defconfig  | 3 ++-
 configs/A20-Olimex-SOM-EVB_defconfig   | 3 ++-
 configs/Bananapi_defconfig | 3 ++-
 configs/Bananapro_defconfig| 3 ++-
 configs/Cubieboard2_defconfig  | 3 ++-
 configs/Cubieboard_defconfig   | 3 ++-
 configs/Cubietruck_defconfig   | 3 ++-
 configs/Itead_Ibox_A20_defconfig   | 3 ++-
 configs/Lamobo_R1_defconfig| 3 ++-
 configs/Linksprite_pcDuino3_Nano_defconfig | 3 ++-
 configs/Linksprite_pcDuino3_defconfig  | 3 ++-
 configs/Marsboard_A10_defconfig| 3 ++-
 configs/Mele_A1000_defconfig   | 3 ++-
 configs/Mele_M5_defconfig  | 3 ++-
 configs/Orangepi_defconfig | 3 ++-
 configs/Orangepi_mini_defconfig| 3 ++-
 configs/Wits_Pro_A20_DKT_defconfig | 3 ++-
 20 files changed, 40 insertions(+), 20 deletions(-)

diff --git a/configs/A10-OLinuXino-Lime_defconfig 
b/configs/A10-OLinuXino-Lime_defconfig
index 04b720d..bb7eaf8 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -8,7 +8,8 @@ CONFIG_SYS_CLK_FREQ=91200
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
+CONFIG_AHCI=y
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,SATAPWR=SUNXI_GPC(3)"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-OLinuXino-Lime2_defconfig 
b/configs/A20-OLinuXino-Lime2_defconfig
index 4751fe0..d48e35d 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -8,7 +8,8 @@ CONFIG_USB0_VBUS_PIN="PC17"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
+CONFIG_AHCI=y
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,SATAPWR=SUNXI_GPC(3)"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-OLinuXino-Lime_defconfig 
b/configs/A20-OLinuXino-Lime_defconfig
index 024dc2d..7c5d84d 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -6,7 +6,8 @@ CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
+CONFIG_AHCI=y
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPC(3)"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-OLinuXino_MICRO_defconfig 
b/configs/A20-OLinuXino_MICRO_defconfig
index 5809345..9eb5f1b 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -9,7 +9,8 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=3
 CONFIG_VIDEO_VGA=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
+CONFIG_AHCI=y
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPB(8)"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig 
b/configs/A20-Olimex-SOM-EVB_defconfig
index 7a14a7b..a6bf45f 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -11,7 +11,8 @@ CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
+CONFIG_AHCI=y
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,SATAPWR=SUNXI_GPC(3)"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index 366ef24..3da1cf7 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -7,7 +7,8 @@ CONFIG_VIDEO_COMPOSITE=y
 CONFIG_GMAC_TX_DELAY=3
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
+CONFIG_AHCI=y
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23)"
 CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index 9b39124..2b9c865 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -9,7 +9,8 @@ CONFIG_VIDEO_COMPOSITE=y
 CONFIG_GMAC_TX_DELAY=3

Re: [U-Boot] [PATCH v1] arm: Add support for PDU001

[Simon Glass]

Hi Felix,

On 31 October 2016 at 08:54, Felix Brack  wrote:
>
> Hello Simon,
>
> On 26.10.2016 18:30, Simon Glass wrote:
> > Hi Felix,
> >
> > On 19 October 2016 at 04:12, Felix Brack  wrote:
> >> This patch adds support for the PDU001 board.
> >>
> >> Signed-off-by: Felix Brack 
> >> ---
> >>
> >>  arch/arm/Kconfig  |   1 +
> >>  arch/arm/cpu/armv7/am33xx/Kconfig |   9 ++
> >>  board/eets/pdu001/Kconfig |  66 ++
> >>  board/eets/pdu001/MAINTAINERS |   6 +
> >>  board/eets/pdu001/Makefile|  13 ++
> >>  board/eets/pdu001/README  |  35 +
> >>  board/eets/pdu001/board.c | 263 
> >> ++
> >>  board/eets/pdu001/board.h |  30 +
> >>  board/eets/pdu001/mux.c   | 146 +
> >>  configs/pdu001_defconfig  |  33 +
> >>  include/configs/pdu001.h  | 117 +
> >>  11 files changed, 719 insertions(+)
> >>  create mode 100644 board/eets/pdu001/Kconfig
> >>  create mode 100644 board/eets/pdu001/MAINTAINERS
> >>  create mode 100644 board/eets/pdu001/Makefile
> >>  create mode 100644 board/eets/pdu001/README
> >>  create mode 100644 board/eets/pdu001/board.c
> >>  create mode 100644 board/eets/pdu001/board.h
> >>  create mode 100644 board/eets/pdu001/mux.c
> >>  create mode 100644 configs/pdu001_defconfig
> >>  create mode 100644 include/configs/pdu001.h
[...]
> >> +
> >> +static struct module_pin_mux uart0_pin_mux[] = {
> >> +   {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},  /* 
> >> UART0_RXD */
> >> +   {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},  /* 
> >> UART0_TXD */
> >> +   {-1},
> >
> > Really this should go in a pinctrl driver.
> >
>
> Agreed. A pinctrl driver for the TI AM335X SOC doesn't exist yet, correct?
>

I'm not sure, but it seems like we should get one sometime!

Regards,
Simon
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[U-Boot] [PATCH v2 2/3] arm: am57xx: Enable 8-bit eMMC access

[Sam Protsenko]

Signed-off-by: Sam Protsenko 
---
Changes in v2: None

 include/configs/am57xx_evm.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index bcbe3cd..d009900 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -65,6 +65,7 @@
 #define CONFIG_CMD_GPT
 #define CONFIG_EFI_PARTITION
 #define CONFIG_RANDOM_UUID
+#define CONFIG_HSMMC2_8BIT
 
 /* CPSW Ethernet */
 #define CONFIG_BOOTP_DNS   /* Configurable parts of CMD_DHCP */
-- 
2.9.3

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[U-Boot] [PATCH v2 3/3] arm: dra7xx: Unify Android partition table

[Sam Protsenko]

Make Android partition table the same as for AM57x EVM.

  1. Make "bootloader" partition start from 0x300 sectors offset, so
 DRA7 is bootable in Android mode (see
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR option).
  2. Increase "bootloader" partition size, because size of u-boot.img is
 about 632 KiB (when building DT defconfig, with FIT image enabled).
  3. Specify "reserved" partition explicitly, rather than specifying
 "efs" partition start. Reserved area will be used to store U-Boot
 environment on eMMC. It's convenient to have it exposed explicitly
 so we can read/write U-Boot environment.
  4. Keep all Android partitions locations intact, by reducing
 "reserved" partition size. CONFIG_ENV_SIZE is considered.

Signed-off-by: Sam Protsenko 
---
Changes in v2: None

 include/configs/dra7xx_evm.h | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 798002d..1834d04 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -54,11 +54,12 @@
/* Android partitions */ \
"partitions_android=" \
"uuid_disk=${uuid_gpt_disk};" \
-   "name=xloader,start=128K,size=128K,uuid=${uuid_gpt_xloader};" \
-   "name=bootloader,size=384K,uuid=${uuid_gpt_bootloader};" \
+   "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \
+   "name=bootloader,size=768K,uuid=${uuid_gpt_bootloader};" \
"name=environment,size=128K,uuid=${uuid_gpt_environment};" \
"name=misc,size=128K,uuid=${uuid_gpt_misc};" \
-   "name=efs,start=1280K,size=16M,uuid=${uuid_gpt_efs};" \
+   "name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \
+   "name=efs,size=16M,uuid=${uuid_gpt_efs};" \
"name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \
"name=recovery,size=10M,uuid=${uuid_gpt_recovery};" \
"name=boot,size=10M,uuid=${uuid_gpt_boot};" \
-- 
2.9.3

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[U-Boot] [PATCH v2 1/3] arm: am57xx: Define Android partition table

[Sam Protsenko]

"fastboot oem format" command reuses "gpt write" command, which in turn
requires correct partitions defined in $partitions variable. This patch
adds such definition of Android partitions for DRA7XX EVM board.

By default $partitions variable contains Linux partition table. In order
to prepare Android environment one can run next commands from U-Boot
shell:

=> env set partitions $partitions_android
=> env save

After those operations one can go to fastboot mode and perform
"fastboot oem format" to create Android partition table.

While at it, enable CONFIG_RANDOM_UUID to spare user from providing
UUIDs for each partition manually.

Signed-off-by: Sam Protsenko 
---
Changes in v2:
  - do not wrap PARTS_DEFAULT in #ifndef CONFIG_SPL_BUILD

 include/configs/am57xx_evm.h | 21 -
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index d865f41..bcbe3cd 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -38,14 +38,33 @@
 
 /* Define the default GPT table for eMMC */
 #define PARTS_DEFAULT \
+   /* Linux partitions */ \
"uuid_disk=${uuid_gpt_disk};" \
-   "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
+   "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
+   /* Android partitions */ \
+   "partitions_android=" \
+   "uuid_disk=${uuid_gpt_disk};" \
+   "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \
+   "name=bootloader,size=768K,uuid=${uuid_gpt_bootloader};" \
+   "name=environment,size=128K,uuid=${uuid_gpt_environment};" \
+   "name=misc,size=128K,uuid=${uuid_gpt_misc};" \
+   "name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \
+   "name=efs,size=16M,uuid=${uuid_gpt_efs};" \
+   "name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \
+   "name=recovery,size=10M,uuid=${uuid_gpt_recovery};" \
+   "name=boot,size=10M,uuid=${uuid_gpt_boot};" \
+   "name=system,size=768M,uuid=${uuid_gpt_system};" \
+   "name=cache,size=256M,uuid=${uuid_gpt_cache};" \
+   "name=ipu1,size=1M,uuid=${uuid_gpt_ipu1};" \
+   "name=ipu2,size=1M,uuid=${uuid_gpt_ipu2};" \
+   "name=userdata,size=-,uuid=${uuid_gpt_userdata}"
 
 #include 
 
 /* Enhance our eMMC support / experience. */
 #define CONFIG_CMD_GPT
 #define CONFIG_EFI_PARTITION
+#define CONFIG_RANDOM_UUID
 
 /* CPSW Ethernet */
 #define CONFIG_BOOTP_DNS   /* Configurable parts of CMD_DHCP */
-- 
2.9.3

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[U-Boot] Please pull u-boot-rockchip

[Simon Glass]

Hi Tom,

This includes various minor tweaks for rockchip.


The following changes since commit 48d2fc47c9feac54fdc0e2e0462f13b1a8689ece:

  Merge branch 'sun9i-a80-spl' of http://git.denx.de/u-boot-sunxi
(2016-10-30 08:12:00 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-rockchip.git

for you to fetch changes up to 4594ac07847f5c7fe7294ce6c71849fea0a431e0:

  rk3288: kconfig: remove duplicate definition of SPL_MMC_SUPPORT
(2016-10-30 13:29:06 -0600)


Jacob Chen (3):
  clk: rk3399: fix rockchip_get_cru
  rockchip: use rockchip linux partitions layout
  rockchip: doc: add GPT partition layout

Kever Yang (7):
  rk3399: disable the clock multiplier support when SoC init
  rk3288: fix reg address for GRF_SOC_CON2
  evb-rk3399: config: set emmc as default boot dev
  rk3288: config change for enable dram capacity auto-detect.
  rk3288: sdram: auto-detect the capacity
  dts: rk3288: remove node in dmc which not need anymore
  rk3288: kconfig: remove duplicate definition of SPL_MMC_SUPPORT

Sandy Patterson (1):
  rockchip: RK3288 needs fdt and initrd below 256M now

Simon Glass (3):
  rockchip: rk3036: Move rockchip_get_cru() out of the driver
  rockchip: rk3399: Move rockchip_get_cru() out of the driver
  rockchip: rk3288: Move rockchip_get_cru() out of the driver

 arch/arm/dts/rk3288-evb.dts |   3 -
 arch/arm/dts/rk3288-fennec.dts  |   3 -
 arch/arm/dts/rk3288-firefly.dts |   2 -
 arch/arm/dts/rk3288-miniarm.dts |   3 -
 arch/arm/dts/rk3288-popmetal.dts|   3 -
 arch/arm/dts/rk3288-rock2-square.dts|   2 -
 arch/arm/dts/rk3288-veyron.dtsi |   2 -
 arch/arm/include/asm/arch-rockchip/cru_rk3036.h |   6 ++
 arch/arm/include/asm/arch-rockchip/cru_rk3288.h |   7 +++
 arch/arm/include/asm/arch-rockchip/cru_rk3399.h |   6 ++
 arch/arm/include/asm/arch-rockchip/sdram.h  |  15 +
 arch/arm/mach-rockchip/rk3036/Makefile  |   2 +
 arch/arm/mach-rockchip/rk3036/clk_rk3036.c  |  33 +++
 arch/arm/mach-rockchip/rk3288/Kconfig   |   3 -
 arch/arm/mach-rockchip/rk3288/clk_rk3288.c  |  16 ++
 arch/arm/mach-rockchip/rk3288/rk3288.c  |   2 +-
 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c| 272
+++--
 arch/arm/mach-rockchip/rk3399/Makefile  |   1 +
 arch/arm/mach-rockchip/rk3399/clk_rk3399.c  |  33 +++
 arch/arm/mach-rockchip/rk3399/rk3399.c  |  14 +
 configs/evb-rk3288_defconfig|   1 +
 configs/fennec-rk3288_defconfig |   1 +
 configs/miniarm-rk3288_defconfig|   1 +
 configs/popmetal-rk3288_defconfig   |   1 +
 doc/README.rockchip |  11 +++-
 drivers/clk/rockchip/clk_rk3036.c   |  24 +---
 drivers/clk/rockchip/clk_rk3288.c   |  21 ---
 drivers/clk/rockchip/clk_rk3399.c   |  24 +---
 include/configs/evb_rk3399.h|   2 +-
 include/configs/rk3036_common.h |  17 +-
 include/configs/rk3288_common.h |  23 ++--
 include/configs/rk3399_common.h |  16 +-
 include/configs/rockchip-common.h   |  35 
 33 files changed, 422 insertions(+), 183 deletions(-)
 create mode 100644 arch/arm/mach-rockchip/rk3036/clk_rk3036.c
 create mode 100644 arch/arm/mach-rockchip/rk3399/clk_rk3399.c
 create mode 100644 include/configs/rockchip-common.h

Regards,
Simon
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[U-Boot] [PATCH v2 2/2] spl: Remove CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS

[Sam Protsenko]

This option isn't used for anything, so get rid of it.

Signed-off-by: Sam Protsenko 
---
Changes in v2: None

 README | 4 
 include/configs/am3517_crane.h | 1 -
 include/configs/am3517_evm.h   | 1 -
 include/configs/at91sam9m10g45ek.h | 1 -
 include/configs/at91sam9n12ek.h| 1 -
 include/configs/at91sam9x5ek.h | 1 -
 include/configs/brppt1.h   | 2 --
 include/configs/brxre1.h   | 2 --
 include/configs/clearfog.h | 1 -
 include/configs/cm_fx6.h   | 1 -
 include/configs/cm_t35.h   | 1 -
 include/configs/cm_t54.h   | 5 -
 include/configs/db-88f6820-gp.h| 1 -
 include/configs/draco.h| 2 --
 include/configs/etamin.h   | 2 --
 include/configs/imx6_spl.h | 3 +--
 include/configs/ls1021aqds.h   | 1 -
 include/configs/ls1021atwr.h   | 6 +-
 include/configs/ls1043a_common.h   | 1 -
 include/configs/ls1046a_common.h   | 1 -
 include/configs/omap3_evm.h| 1 -
 include/configs/picosam9g45.h  | 1 -
 include/configs/pxm2.h | 2 --
 include/configs/rastaban.h | 2 --
 include/configs/rut.h  | 2 --
 include/configs/sama5d2_xplained.h | 1 -
 include/configs/sama5d3_xplained.h | 1 -
 include/configs/sama5d3xek.h   | 1 -
 include/configs/sama5d4_xplained.h | 1 -
 include/configs/sama5d4ek.h| 1 -
 include/configs/tao3530.h  | 1 -
 include/configs/thuban.h   | 2 --
 include/configs/ti814x_evm.h   | 1 -
 include/configs/ti816x_evm.h   | 1 -
 include/configs/ti_armv7_common.h  | 3 ---
 include/configs/woodburn_sd.h  | 1 -
 include/configs/zynq-common.h  | 1 -
 scripts/config_whitelist.txt   | 1 -
 38 files changed, 2 insertions(+), 60 deletions(-)

diff --git a/README b/README
index d838b9e..c186707 100644
--- a/README
+++ b/README
@@ -3338,10 +3338,6 @@ FIT uImage format:
CONFIG_SPL_INIT_MINIMAL
Arch init code should be built for a very small image
 
-   CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS
-   Size of partition on the MMC to load U-Boot from
-   when the MMC is being used in raw mode.
-
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
Partition on the MMC to load U-Boot from when the MMC is being
used in raw mode
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 943ab3a..2f20e10 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -275,7 +275,6 @@
 #define CONFIG_SPL_BSS_START_ADDR  0x8000
 #define CONFIG_SPL_BSS_MAX_SIZE0x8 /* 512 KB */
 
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img"
 
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index deb1bab..a4ae545 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -335,7 +335,6 @@
 #define CONFIG_SPL_BSS_START_ADDR  0x8000
 #define CONFIG_SPL_BSS_MAX_SIZE0x8 /* 512 KB */
 
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img"
 
diff --git a/include/configs/at91sam9m10g45ek.h 
b/include/configs/at91sam9m10g45ek.h
index cb066ac..fd0504d 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -193,7 +193,6 @@
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0008
 
 #define CONFIG_SPL_LDSCRIPT
arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img"
 
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index faa232c..b825464 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -237,7 +237,6 @@
 
 #ifdef CONFIG_SYS_USE_MMC
 #define CONFIG_SPL_LDSCRIPT
arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img"
 
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index efdf88d..843f03a 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -236,7 +236,6 @@
 
 #ifdef CONFIG_SYS_USE_MMC
 #define CONFIG_SPL_LDSCRIPT
arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img"
 
diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h

[U-Boot] [PATCH v2 0/2] spl: Convert MMC raw mode sector options to Kconfig

[Sam Protsenko]

This series accomplishes next:

  1. Convert CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR option to Kconfig
  2. Remove CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR from boards that
 don't build SPL
  3. Add CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR bool option, which
 can be tested with #ifdef
  4. Remove CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS option, as it's not used

All patches were tested with buildman tool. This command:

$ ./tools/buildman/buildman -b master -sSdB

results in:

Summary of 3 commits for 622 boards (4 threads, 1 job per thread)
01: travis-ci: Add test.py for various qemu platforms
   arm:  +   colibri_pxa270 snow smdk5250 spring
02: spl: Convert CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to Kconfig
03: spl: Remove CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS

So patchset doesn't break or alter any board.

Changes in v2:
  - PATCH 1/2: merge "SPL dependency" patch
  - PATCH 1/2: add defaults for common architectures/targets

Sam Protsenko (2):
  spl: Convert CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to Kconfig
  spl: Remove CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS

 README |  5 
 common/spl/Kconfig | 30 ++
 common/spl/spl_mmc.c   |  4 +--
 configs/A10-OLinuXino-Lime_defconfig   |  1 +
 configs/A10s-OLinuXino-M_defconfig |  1 +
 configs/A13-OLinuXinoM_defconfig   |  1 +
 configs/A13-OLinuXino_defconfig|  1 +
 configs/A20-OLinuXino-Lime2_defconfig  |  1 +
 configs/A20-OLinuXino-Lime_defconfig   |  1 +
 configs/A20-OLinuXino_MICRO_defconfig  |  1 +
 configs/A20-Olimex-SOM-EVB_defconfig   |  1 +
 configs/A33-OLinuXino_defconfig|  1 +
 configs/Ainol_AW1_defconfig|  1 +
 configs/Ampe_A76_defconfig |  1 +
 configs/Auxtek-T003_defconfig  |  1 +
 configs/Auxtek-T004_defconfig  |  1 +
 configs/Bananapi_defconfig |  1 +
 configs/Bananapro_defconfig|  1 +
 configs/CHIP_defconfig |  1 +
 configs/CSQ_CS908_defconfig|  1 +
 configs/Chuwi_V7_CW0825_defconfig  |  2 +-
 configs/Colombus_defconfig |  1 +
 configs/Cubieboard2_defconfig  |  1 +
 configs/Cubieboard_defconfig   |  1 +
 configs/Cubietruck_defconfig   |  1 +
 configs/Cubietruck_plus_defconfig  |  1 +
 configs/Empire_electronix_d709_defconfig   |  1 +
 configs/Empire_electronix_m712_defconfig   |  1 +
 configs/Hummingbird_A31_defconfig  |  1 +
 configs/Hyundai_A7HD_defconfig |  1 +
 configs/Itead_Ibox_A20_defconfig   |  1 +
 configs/Lamobo_R1_defconfig|  1 +
 configs/Linksprite_pcDuino3_Nano_defconfig |  1 +
 configs/Linksprite_pcDuino3_defconfig  |  1 +
 configs/Linksprite_pcDuino_defconfig   |  1 +
 configs/MK808C_defconfig   |  1 +
 configs/MSI_Primo73_defconfig  |  1 +
 configs/MSI_Primo81_defconfig  |  2 +-
 configs/Marsboard_A10_defconfig|  1 +
 configs/Mele_A1000G_quad_defconfig |  1 +
 configs/Mele_A1000_defconfig   |  1 +
 configs/Mele_I7_defconfig  |  1 +
 configs/Mele_M3_defconfig  |  1 +
 configs/Mele_M5_defconfig  |  1 +
 configs/Mele_M9_defconfig  |  1 +
 configs/Mini-X_defconfig   |  1 +
 configs/Orangepi_defconfig |  1 +
 configs/Orangepi_mini_defconfig|  1 +
 configs/Sinlinx_SinA31s_defconfig  |  1 +
 configs/Sinlinx_SinA33_defconfig   |  1 +
 configs/Sinovoip_BPI_M2_defconfig  |  1 +
 configs/Sinovoip_BPI_M3_defconfig  |  1 +
 configs/UTOO_P66_defconfig |  1 +
 configs/Wexler_TAB7200_defconfig   |  1 +
 configs/Wits_Pro_A20_DKT_defconfig |  1 +
 configs/Wobo_i5_defconfig  |  1 +
 configs/Yones_Toptech_BD1078_defconfig |  1 +
 configs/Yones_Toptech_BS1078_V2_defconfig  |  1 +
 configs/am335x_baltos_defconfig|  1 +
 configs/am335x_boneblack_defconfig |  1 +
 configs/am335x_boneblack_vboot_defconfig   |  1 +
 configs/am335x_evm_defconfig   |  1 +
 configs/am335x_evm_nor_defconfig   |  1 +
 configs/am335x_evm_spiboot_defconfig   |  1 +
 configs/am335x_evm_usbspl_defconfig|  1 +
 

Re: [U-Boot] [PATCH] tools: Makefile: improve cross_tools target usability

[Marek Vasut]

On 10/31/2016 02:15 PM, Stefan Müller-Klieser wrote:
> When building the cross_tools target, HOSTCFLAGS and HOSTLDFLAGS will
> propagate to the target build. This should not happen and is easy to
> prevent.
> 
> Signed-off-by: Stefan Müller-Klieser 

+CC Masahiro Yamada-san .

> ---
>  tools/Makefile | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/tools/Makefile b/tools/Makefile
> index 400588c..305336c 100644
> --- a/tools/Makefile
> +++ b/tools/Makefile
> @@ -263,6 +263,8 @@ subdir- += env
>  
>  ifneq ($(CROSS_BUILD_TOOLS),)
>  HOSTCC = $(CC)
> +HOSTCFLAGS = $(CFLAGS)
> +HOSTLDFLAGS = $(LDFLAGS)
>  
>  quiet_cmd_crosstools_strip = STRIP   $^
>cmd_crosstools_strip = $(STRIP) $^; touch $@
> 


-- 
Best regards,
Marek Vasut
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[U-Boot] [PATCH v4 2/2] image: Protect against overflow in unknown_msg()

[Simon Glass]

Coverity complains that this can overflow. If we later increase the size
of one of the strings in the table, it could happen.

Adjust the code to protect against this.

Signed-off-by: Simon Glass 
Reported-by: Coverity (CID: 150964)
---

Changes in v4:
- Add missing [] (tested)

Changes in v3:
- Adjust to deal with what strncpy() actually does (I think)

Changes in v2:
- Drop unwanted #include

 common/image.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/common/image.c b/common/image.c
index 0e86c13..7604494 100644
--- a/common/image.c
+++ b/common/image.c
@@ -587,10 +587,12 @@ const table_entry_t *get_table_entry(const table_entry_t 
*table, int id)
 
 static const char *unknown_msg(enum ih_category category)
 {
+   static const char unknown_str[] = "Unknown ";
static char msg[30];
 
-   strcpy(msg, "Unknown ");
-   strcat(msg, table_info[category].desc);
+   strcpy(msg, unknown_str);
+   strncat(msg, table_info[category].desc,
+   sizeof(msg) - sizeof(unknown_str));
 
return msg;
 }
-- 
2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v4 2/2] image: Protect against overflow in unknown_msg()

[Simon Glass]

Coverity complains that this can overflow. If we later increase the size
of one of the strings in the table, it could happen.

Adjust the code to protect against this.

Signed-off-by: Simon Glass 
Reported-by: Coverity (CID: 150964)
---

Changes in v4:
- Add missing [] (tested)

Changes in v3:
- Adjust to deal with what strncpy() actually does (I think)

Changes in v2:
- Drop unwanted #include

 common/image.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/common/image.c b/common/image.c
index 0e86c13..7604494 100644
--- a/common/image.c
+++ b/common/image.c
@@ -587,10 +587,12 @@ const table_entry_t *get_table_entry(const table_entry_t 
*table, int id)
 
 static const char *unknown_msg(enum ih_category category)
 {
+   static const char unknown_str[] = "Unknown ";
static char msg[30];
 
-   strcpy(msg, "Unknown ");
-   strcat(msg, table_info[category].desc);
+   strcpy(msg, unknown_str);
+   strncat(msg, table_info[category].desc,
+   sizeof(msg) - sizeof(unknown_str));
 
return msg;
 }
-- 
2.8.0.rc3.226.g39d4020

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Re: [U-Boot] [PATCH v3 2/2] image: Protect against overflow in unknown_msg()

[Simon Glass]

Hi Tom,

On 28 October 2016 at 14:04, Tom Rini  wrote:
> On Fri, Oct 28, 2016 at 12:41:05PM -0700, Simon Glass wrote:
>> Hi Tom,
>>
>> On 28 October 2016 at 11:59, Tom Rini  wrote:
>> > On Thu, Oct 27, 2016 at 08:18:39PM -0600, Simon Glass wrote:
>> >> Coverity complains that this can overflow. If we later increase the size
>> >> of one of the strings in the table, it could happen.
>> >>
>> >> Adjust the code to protect against this.
>> >>
>> >> Signed-off-by: Simon Glass 
>> >> Reported-by: Coverity (CID: 150964)
>> >> ---
>> >>
>> >> Changes in v3:
>> >> - Adjust to deal with what strncpy() actually does (I think)
>> >>
>> >> Changes in v2:
>> >> - Drop unwanted #include
>> >>
>> >>  common/image.c | 6 --
>> >>  1 file changed, 4 insertions(+), 2 deletions(-)
>> >>
>> >> diff --git a/common/image.c b/common/image.c
>> >> index 0e86c13..016f263 100644
>> >> --- a/common/image.c
>> >> +++ b/common/image.c
>> >> @@ -588,9 +588,11 @@ const table_entry_t *get_table_entry(const 
>> >> table_entry_t *table, int id)
>> >>  static const char *unknown_msg(enum ih_category category)
>> >>  {
>> >>   static char msg[30];
>> >> + static char unknown_str = "Unknown ";
>> >>
>> >> - strcpy(msg, "Unknown ");
>> >> - strcat(msg, table_info[category].desc);
>> >> + strcpy(msg, unknown_str);
>> >> + strncat(msg, table_info[category].desc,
>> >> + sizeof(msg) - sizeof(unknown_str));
>> >
>> > We still need to subtract 1 more here at the end, for the NUL don't we?
>>
>> I was hoping that the sizeof(msg) would take care of that?
>
> No, and you didn't compile test this did you? ;)  I was trying to throw
> up a stupid test to confirm what all everything would be.
> test.c:6:28: warning: initialization makes integer from pointer without a 
> cast [-Wint-conversion]
>   static char unknown_str = "Unknown ";
> ^~
> test.c:6:28: error: initializer element is not computable at load time
>
> Correcting that to be *unknown_str gives us back the sizeof(char *) not
> the string in question.  So we need to use strlen(unknown_str), and
> strlen does not include the NUL, so we would need to still add in the -
> 1 after all of the above.

Sorry I was travelling last week and not really focussed on this. I
meant to use [].

>
> And I'm being verbose above because string handling can be annoying and
> I didn't get it 100% right in my head so I figured it's worth showing
> the work.  And since we're going with "Coverity says we've got string
> problems" we should really correct it, and not just be wrong in a
> different way :)

I think I can use sizeof() and this time I've tested that it does the
right thing, by adding a test function to call it.

Regards,
Simon
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[U-Boot] [PATCH v4 1/2] mkimage: Fix missing free() in show_valid_options()

[Simon Glass]

The allocated memory should be freed. Fix it.

Signed-off-by: Simon Glass 
Reported-by: Coverity (CID: 150963)
Reviewed-by: Tom Rini 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 tools/mkimage.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/mkimage.c b/tools/mkimage.c
index 3c594a0..521fa80 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -64,6 +64,7 @@ static int show_valid_options(enum ih_category category)
genimg_get_cat_name(category, item));
}
fprintf(stderr, "\n");
+   free(order);
 
return 0;
 }
-- 
2.8.0.rc3.226.g39d4020

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Re: [U-Boot] [PATCH V3 2/2] net: add driver for Synopsys Ethernet QoS device

[Stephen Warren]

On 10/21/2016 02:46 PM, Stephen Warren wrote:

From: Stephen Warren 

This driver supports the Synopsys Designware Ethernet QoS (Quality of
Service) a/k/a eqos IP block, which is a different design than the HW
supported by the existing designware.c driver. The IP supports many
options for bus type, clocking/reset structure, and feature list. This
driver currently supports the specific configuration used in NVIDIA's
Tegra186 chip, but should be extensible to other combinations quite
easily, as explained in the source.

Signed-off-by: Stephen Warren 
Reviewed-by: Simon Glass  # V1
---
v3:
* Use structs to describe register layout.
* Implement write_hwaddr(). This requires tracking whether registers are
  accessible and knowing for which configurations this matters.
* Add full description of Tegra186 HW block configuration.
* s/tegra/tegra186/ in symbol names.
* Use a single struct type for all descriptors, with field names that
  match the HW documentation.


Joe, does this new version look good? I believe it addresses all your 
previous comments. Thanks.

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Re: [U-Boot] [PATCH RESEND v2 1/2] ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node

[R, Vignesh]

On 10/31/2016 5:24 PM, Tom Rini wrote:
> On Mon, Oct 31, 2016 at 09:40:34AM +0530, Vignesh R wrote:
> 
>> Update the spi-max-frequency property of m25p80 flash slave to match
>> that of TI QSPI controller node, so that QSPI operations happen at
>> maximum supported frequency of 76.8MHz.
>>
>> Signed-off-by: Vignesh R 
>> Reviewed-by: Jagan Teki 
> 
> And this is also done in the kernel right?  Thanks!
> 

Yes, the kernel patch is merged.

-- 
Regards
Vignesh
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Re: [U-Boot] [PATCH v1] arm: Add support for PDU001

[Felix Brack]

Hello Simon,

On 26.10.2016 18:30, Simon Glass wrote:
> Hi Felix,
> 
> On 19 October 2016 at 04:12, Felix Brack  wrote:
>> This patch adds support for the PDU001 board.
>>
>> Signed-off-by: Felix Brack 
>> ---
>>
>>  arch/arm/Kconfig  |   1 +
>>  arch/arm/cpu/armv7/am33xx/Kconfig |   9 ++
>>  board/eets/pdu001/Kconfig |  66 ++
>>  board/eets/pdu001/MAINTAINERS |   6 +
>>  board/eets/pdu001/Makefile|  13 ++
>>  board/eets/pdu001/README  |  35 +
>>  board/eets/pdu001/board.c | 263 
>> ++
>>  board/eets/pdu001/board.h |  30 +
>>  board/eets/pdu001/mux.c   | 146 +
>>  configs/pdu001_defconfig  |  33 +
>>  include/configs/pdu001.h  | 117 +
>>  11 files changed, 719 insertions(+)
>>  create mode 100644 board/eets/pdu001/Kconfig
>>  create mode 100644 board/eets/pdu001/MAINTAINERS
>>  create mode 100644 board/eets/pdu001/Makefile
>>  create mode 100644 board/eets/pdu001/README
>>  create mode 100644 board/eets/pdu001/board.c
>>  create mode 100644 board/eets/pdu001/board.h
>>  create mode 100644 board/eets/pdu001/mux.c
>>  create mode 100644 configs/pdu001_defconfig
>>  create mode 100644 include/configs/pdu001.h
>>
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>> index d7a9b11..7ab966b 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -1020,6 +1020,7 @@ source "board/vscom/baltos/Kconfig"
>>  source "board/woodburn/Kconfig"
>>  source "board/work-microwave/work_92105/Kconfig"
>>  source "board/zipitz2/Kconfig"
>> +source "board/eets/pdu001/Kconfig"
>>
>>  source "arch/arm/Kconfig.debug"
>>
>> diff --git a/arch/arm/cpu/armv7/am33xx/Kconfig 
>> b/arch/arm/cpu/armv7/am33xx/Kconfig
>> index 8fd32c2..d5217b1 100644
>> --- a/arch/arm/cpu/armv7/am33xx/Kconfig
>> +++ b/arch/arm/cpu/armv7/am33xx/Kconfig
>> @@ -79,6 +79,15 @@ config TARGET_PEPPER
>> select DM_SERIAL
>> select DM_GPIO
>>
>> +config TARGET_PDU001
>> +   bool "Support PDU001"
>> +   select DM
>> +   select DM_SERIAL
>> +   help
>> + Support for PDU001 platform developed by EETS GmbH.
>> + The PDU001 is a processor and display unit developed around
>> + the Computing-Module m2 from bytes at work AG.
>> +
>>  endchoice
>>
>>  endif
>> diff --git a/board/eets/pdu001/Kconfig b/board/eets/pdu001/Kconfig
>> new file mode 100644
>> index 000..fe5f520
>> --- /dev/null
>> +++ b/board/eets/pdu001/Kconfig
>> @@ -0,0 +1,66 @@
>> +# Copyright (c) 2016, EETS GmbH
>> +#
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +
>> +if TARGET_PDU001
>> +
>> +config SYS_BOARD
>> +   default "pdu001"
>> +
>> +config SYS_VENDOR
>> +   default "eets"
>> +
>> +config SYS_SOC
>> +   default "am33xx"
>> +
>> +config SYS_CONFIG_NAME
>> +   default "pdu001"
>> +
>> +config CONS_INDEX
>> +   int "UART used for console"
>> +   range 1 6
>> +   default 4
>> +   help
>> + The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
>> + in documentation, etc) available to it.  The best choice for the
>> + PDU001 is UART3 as it is wired to the header K2; enter 4 here to
>> + use UART3. UART0 is connected to the EIA-485 transceiver. If you
>> + really need to use it, you are advised to remove the transceiver 
>> U14
>> + from the board. UART1 is wired to the backplane and therefore
>> + accessible from there or by the backplane connector K1 of the PDU.
>> + Any other UART then UART3 (enter 4 here), UART1 (enter 2 here) or
>> + UART0 (enter 1 here) are not sensible since they are not sired to
>> + any connector and therefore difficult to access.
>> +
>> +choice
>> +   prompt "State of Run LED"
>> +   default PDU001_RUN_LED_RED
>> +   help
>> + The PDU001 has a bi-color (red/green) LED labeled 'Run' which
>> + can be used to indicate the operating state of the board. By
>> + default it will be lit red by U-Boot. Later in the start-up
>> + process it can be changed to green (or heartbeat or anything else)
>> + by the kernel or some other software.
>> +
>> +config RUN_LED_RED
>> +   bool
>> +   prompt "Red"
>> +   help
>> + Lit Run LED red.
> 
> What does this mean? Can you expand the help a bit?

Sorry, the extended help text is 'one level higher' at the 'choice' tag.
I will move it to the corresponding 'config' tags. 

> 
>> +
>> +config RUN_LED_GREEN
>> +   bool
>> +   prompt "Green"
>> +   help
>> + Lit Run LED green.
>> +
>> +config RUN_LED_OFF
>> +   bool
>> +   prompt "Off"
>> +   help
>> + Do not lit Run LED.
>> +
>> +endchoice
>> +
>> +endif
>> diff --git a/board/eets/pdu001/MAINTAINERS b/board/eets/pdu001/MAINTAINERS
>> new file mode 100644
>> index 000..b5edc4d
>> --- 

Re: [U-Boot] [PATCH v3] arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC

[linux-kernel-dev]

Hi Jagan,
>From: Jagan Teki [mailto:ja...@openedev.com]
>Sent: Donnerstag, 20. Oktober 2016 12:52
>Subject: Re: [U-Boot] [PATCH v3] arm: imx: add i.MX53 Beckhoff CX9020
>Embedded PC
>
>On Mon, Oct 17, 2016 at 5:57 PM,   wrote:
>> From: Patrick Bruenn 
>>...
>> diff --git a/board/beckhoff/mx53cx9020/imximage.cfg
>b/board/beckhoff/mx53cx9020/imximage.cfg
>> new file mode 100644
>> index 000..c6bdc72
>> --- /dev/null
>> +++ b/board/beckhoff/mx53cx9020/imximage.cfg
>> @@ -0,0 +1,82 @@
>> +/*
>> + * Copyright (C) 2015  Beckhoff Automation GmbH
>> + * Patrick Bruenn 
>> + *
>> + * Based on Freescale's Linux i.MX mx53loco/imximage.cfg file:
>
>Is this Linux refenace file? I saw similar one at ./board/freescale/mx53loco.
It's from /board/freescale/mx53loco, I will make that more clear in the 
comment
>>...
>> diff --git a/board/beckhoff/mx53cx9020/mx53cx9020.c
>b/board/beckhoff/mx53cx9020/mx53cx9020.c
>> new file mode 100644
>> index 000..c92ec15
>> --- /dev/null
>> +++ b/board/beckhoff/mx53cx9020/mx53cx9020.c
>> @@ -0,0 +1,563 @@
>> +/*
>> + * Copyright (C) 2015  Beckhoff Automation GmbH & Co. KG
>> + * Patrick Bruenn 
>> + *
>> + * Based on Freescale's Linux i.MX mx53loco.c file:
>
>Same as above
>
yes, same here.
>>...
>> +static void clock_1GHz(void)
>> +{
>> +   int ret;
>> +   u32 ref_clk = MXC_HCLK;
>> +   /*
>> +* After increasing voltage to 1.25V, we can switch
>> +* CPU clock to 1GHz and DDR to 400MHz safely
>> +*/
>> +   ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
>> +   if (ret)
>> +   printf("CPU:   Switch CPU clock to 1GHZ failed\n");
>> +
>> +   ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
>> +   ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
>
>Why we need to | the previous ret?
>
To keep it the same as in mx53loco.c. Besides it sounds reasonable to me the 
check both functions for success.
>>...
>> +U_BOOT_CMD(loadccat, 5, 1, do_load_ccat,
>> +  "loads ccat firmware",
>> +  "   \n"
>> +  "- write FPGA firmware from 'dev' on 'interface' in 
>> 'filename' to
>CCAT using 'addr' as a buffer");
>
>Can't we achieve this through cmd/fpga* ?
>
Maybe, but I didn't find a working solution. From your experience should the 
cyclone2 driver work for cyclon3 as well?
>> ...
>> diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h
>> new file mode 100644
>> index 000..b90e076
>> --- /dev/null
>> +++ b/include/configs/mx53cx9020.h
>> @@ -0,0 +1,206 @@
>> +/*
>> + * Copyright (C) 2015  Beckhoff Automation GmbH & Co. KG
>> + * Patrick Bruenn 
>> + *
>> + * Configuration settings for Beckhoff CX9020.
>> + *
>> + * Based on Freescale's Linux i.MX mx53loco.h file:
>> + * Copyright (C) 2010-2011 Freescale Semiconductor.
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#ifndef __CONFIG_H
>> +#define __CONFIG_H
>> +
>> +#define CONFIG_MX53
>
>Move to defconfig
>
If I move that, mx53cx9020 would be different from all other mx53 boards.
Despite from that I tried to, but compiling will fail, because CPU_TYPE, 
required by imx-regs.h, is not set.
>> +
>> +#define CONFIG_MACH_TYPE   MACH_TYPE_MX53_LOCO
>
>What is the need for this?
>
I will remove it.
>> +
>> +#include 
>> +
>> +#define CONFIG_CMDLINE_TAG
>> +#define CONFIG_SETUP_MEMORY_TAGS
>> +#define CONFIG_INITRD_TAG
>> +
>> +#define CONFIG_SYS_FSL_CLK
>> +
>> +/* Size of malloc() pool */
>> +#define CONFIG_SYS_MALLOC_LEN  (10 * 1024 * 1024)
>> +
>> +#define CONFIG_BOARD_EARLY_INIT_F
>> +#define CONFIG_BOARD_LATE_INIT
>> +#define CONFIG_MXC_GPIO
>> +#define CONFIG_REVISION_TAG
>> +
>> +#define CONFIG_MXC_UART
>
>Move to defconfig
>
Again, mx53cx9020 would be different form all remaining mx53 boards. But at 
least this one seems to work.
>> +
>> +/* MMC Configs */
>> +#define CONFIG_FSL_ESDHC
>
>Move to defconfig
>
Again, mx53cx9020 would be different form all remaining mx53 boards. This one 
seems to work, too.
>> +#define CONFIG_SYS_FSL_ESDHC_ADDR  0
>> +#define CONFIG_SYS_FSL_ESDHC_NUM   2
>> +
>> +#define CONFIG_MMC
>> +#define CONFIG_GENERIC_MMC
>> +
>> +/* bootz: zImage/initrd.img support */
>> +#define CONFIG_DOS_PARTITION
>> +
>> +/* Eth Configs */
>> +#define CONFIG_MII
>> +
>> +#define CONFIG_FEC_MXC
>
>Move to defconfig
>
Again, mx53cx9020 would be different form all remaining mx53 boards. This one 
seems to work, too.
>> +#define IMX_FEC_BASE   FEC_BASE_ADDR
>> +#define CONFIG_FEC_MXC_PHYADDR 0x1F
>> +
>> +/* USB Configs */
>> +#define CONFIG_USB_EHCI
>> +#define CONFIG_USB_EHCI_MX5
>> +#define CONFIG_USB_STORAGE
>> +#define CONFIG_USB_HOST_ETHER
>> +#define CONFIG_USB_ETHER_ASIX
>> +#define CONFIG_USB_ETHER_MCS7830
>> +#define CONFIG_USB_ETHER_SMSC95XX
>> +#define CONFIG_MXC_USB_PORT1
>> +#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI |
>PORT_PTS_PTW)

Re: [U-Boot] [PATCH v4] efi_loader: console: Correctly report modes

[Alexander Graf]

On 28/10/2016 17:35, Emmanuel Vadot wrote:

Add support for EFI console modes.
Mode 0 is always 80x25 and present by EFI specification.
Mode 1 is always 80x50 and not mandatory.
Mode 2 and above is freely usable.

If the terminal can handle mode 1, we mark it as supported.
If the terminal size is greater than mode 0 and different than mode 1,
we install it as mode 2.

Modes can be switch with cout_set_mode.

Changes in V4:
 Reset cursor positon on mode switch
 Use local variables in console query code

Changes in V3:
 Valid mode are 0 to EFIMode-1
 Fix style

Changes in V2:
 Add mode switch
 Report only the modes that we support

Signed-off-by: Emmanuel Vadot 
---
 lib/efi_loader/efi_console.c | 90 
 1 file changed, 74 insertions(+), 16 deletions(-)

diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c
index 2e0228c..c22eb3e 100644
--- a/lib/efi_loader/efi_console.c
+++ b/lib/efi_loader/efi_console.c
@@ -9,11 +9,38 @@
 #include 
 #include 

-/* If we can't determine the console size, default to 80x24 */
-static int console_columns = 80;
-static int console_rows = 24;
 static bool console_size_queried;

+#define EFI_COUT_MODE_2 2
+#define EFI_MAX_COUT_MODE 3
+
+struct cout_mode {
+   unsigned long columns;
+   unsigned long rows;
+   int present;
+};
+
+static struct cout_mode efi_cout_modes[] = {
+   /* EFI Mode 0 is 80x25 and always present */
+   {
+   .columns = 80,
+   .rows = 25,
+   .present = 1,
+   },
+   /* EFI Mode 1 is always 80x50 */
+   {
+   .columns = 80,
+   .rows = 50,
+   .present = 0,
+   },
+   /* Value are unknown until we query the console */
+   {
+   .columns = 0,
+   .rows = 0,
+   .present = 0,
+   },
+};
+
 const efi_guid_t efi_guid_console_control = CONSOLE_CONTROL_GUID;

 #define cESC '\x1b'
@@ -56,8 +83,9 @@ const struct efi_console_control_protocol efi_console_control 
= {
.lock_std_in = efi_cin_lock_std_in,
 };

+/* Default to mode 0 */
 static struct simple_text_output_mode efi_con_mode = {
-   .max_mode = 0,
+   .max_mode = 1,
.mode = 0,
.attribute = 0,
.cursor_column = 0,
@@ -131,8 +159,10 @@ static efi_status_t EFIAPI efi_cout_output_string(
struct efi_simple_text_output_protocol *this,
const unsigned short *string)
 {
+   struct cout_mode *mode;
u16 ch;

+   mode = _cout_modes[efi_con_mode.mode];
EFI_ENTRY("%p, %p", this, string);
for (;(ch = *string); string++) {
print_unicode_in_utf8(ch);
@@ -140,13 +170,12 @@ static efi_status_t EFIAPI efi_cout_output_string(
if (ch == '\n') {
efi_con_mode.cursor_column = 1;
efi_con_mode.cursor_row++;
-   } else if (efi_con_mode.cursor_column > console_columns) {
+   } else if (efi_con_mode.cursor_column > mode->columns) {
efi_con_mode.cursor_column = 1;
efi_con_mode.cursor_row++;
}
-   if (efi_con_mode.cursor_row > console_rows) {
-   efi_con_mode.cursor_row = console_rows;
-   }
+   if (efi_con_mode.cursor_row > mode->rows)
+   efi_con_mode.cursor_row = mode->rows;
}

return EFI_EXIT(EFI_SUCCESS);
@@ -170,6 +199,8 @@ static efi_status_t EFIAPI efi_cout_query_mode(
if (!console_size_queried) {
/* Ask the terminal about its size */
int n[3];
+   int cols;
+   int rows;
u64 timeout;

console_size_queried = true;
@@ -191,15 +222,38 @@ static efi_status_t EFIAPI efi_cout_query_mode(
goto out;
}

-   console_columns = n[2];
-   console_rows = n[1];
+   cols = n[2];
+   rows = n[1];


Please add a new line here :).


+   /* Test if we can have Mode 1 */
+   if (cols >= 80 && rows >= 50) {
+   efi_cout_modes[1].present = 1;
+   efi_con_mode.max_mode = 2;
+   }
+
+   /*
+* Install our mode as mode 2 if it is different
+* than mode 0 or 1 and set it  as the currently selected mode
+*/
+   if ((cols != 80 && rows != 25) || (cols != 80 && rows != 50)) {


This equation is always true, no?

cols = 80, rows = 25:

  if (true || false) -> true

cols = 80, rows = 50:

  if (false || true) -> true

cols = 10 rows = 10:

  if (true || true) -> true

Basically what you want is

  if (cols != 80) && (rows != 25) && (rows != 50))

or if you want extra readability points, something like

  static bool 

Re: [U-Boot] OMAP3630 Falcon Mode Questions

[Tom Rini]

On Sat, Oct 29, 2016 at 12:53:27PM -0500, Adam Ford wrote:
> I am trying to utilize Falcon mode on an OMAP3630 (DM3730), but it
> just hangs, and I was hoping someone might find something obvious that
> I missed.  I am able to boot from NAND through U-boot, so I know my
> kernel and device tree are OK as are the boot parameters, MLO and
> U-boot.
> 
> I have read through the ./doc/README.falcon, and I read through some
> of the am33 docs regarding this, and I think I'm doing it right, but
> I'm obviously missing something.
> 
> I have reset my partition structure to:
> device nand0 , # parts = 6
>  #: namesizeoffset  mask_flags
>  0: MLO 0x0008  0x  0
>  1: u-boot  0x001c  0x0008  0
>  2: spl-os  0x0002  0x0024  0
>  3: u-boot-env  0x0002  0x0026  0
>  4: kernel  0x0080  0x0028  0
>  5: fs  0x1f58  0x00a8  0
> 
> My defines in the header file are set as follows:
> 
> #define CONFIG_CMD_SPL_NAND_OFS 0x24
> (matches spl-os offset)
> 
> #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x28
> (matches kernel offset)
> 
> #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
> 
> 
> #define CONFIG_SYS_TEXT_BASE 0x8010
> #define CONFIG_SPL_BSS_START_ADDR 0x8000
> #define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
> #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
> #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10
> 
> 
> I build my uImage with LOADADDR=0x80008000
> 
> My bootargs are as follows:
> console=ttyO0,115200n8 ignore_loglevel early_printk no_console_suspend
> root=ubi0:rootfs rw ubi.mtd=fs noinitrd rootfstype=ubifs rootwait
> display=15 ignore_loglevel early_printk no_console_suspend
> mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),8m(kernel),-(fs)
> 
> 
> I can load uImage and fdtimage, then with the bootargs set, I run
> 
> spl export fdt $loadaddr - $fdtaddr
> 
> ## Booting kernel from Legacy Image at 8100 ...
>Image Name:   Linux-4.9.0-rc2-00040-g9fe68ca-d
>Image Type:   ARM Linux Kernel Image (uncompressed)
>Data Size:3869952 Bytes = 3.7 MiB
>Load Address: 80008000
>Entry Point:  80008000
>Verifying Checksum ... OK
> ## Flattened Device Tree blob at 8600
>Booting using the fdt blob at 0x8600
>Loading Kernel Image ... OK
>Loading Device Tree to 8df1f000, end 8df33114 ... OK
> subcommand not supported
> subcommand not supported
>Loading Device Tree to 8df07000, end 8df1e114 ... OK
> Argument image is now in RAM: 0x8df07000
> 
> I then write this blob to my spl-os partition with the following:
> 
> nand write 0x8df07000 spl-os 0x2
> 
> When I eject the SD card and I boot from NAND (attempting) with Falcon
> it just hangs:
> 
> U-Boot SPL 2016.11-rc2-00164-g7904673-dirty (Oct 29 2016 - 10:28:32)
> Trying to boot from NAND
> 
> Does anyone know if I missed a step somewhere, or do I have something
> configured incorrectly?

OK, just to be clear, did you test reading the uImage and spl-os back in
U-Boot and booting those?  If so and it works, try enabling DEBUG for
SPL and seeing if you get more output.

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Re: [U-Boot] [PATCH RESEND v2 1/2] ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node

[Tom Rini]

On Mon, Oct 31, 2016 at 09:40:34AM +0530, Vignesh R wrote:

> Update the spi-max-frequency property of m25p80 flash slave to match
> that of TI QSPI controller node, so that QSPI operations happen at
> maximum supported frequency of 76.8MHz.
> 
> Signed-off-by: Vignesh R 
> Reviewed-by: Jagan Teki 

And this is also done in the kernel right?  Thanks!

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Re: [U-Boot] [PATCH v5 01/21] sf: Adopt flash table INFO macro from Linux

[Jagan Teki]

On Mon, Oct 31, 2016 at 3:13 PM, Vignesh R  wrote:
>
>
> On Monday 31 October 2016 03:05 PM, Jagan Teki wrote:
>> On Mon, Oct 31, 2016 at 3:02 PM, Vignesh R  wrote:
>>>
>>>
>>> On Monday 31 October 2016 02:50 PM, Jagan Teki wrote:
 On Mon, Oct 31, 2016 at 2:24 PM, Jagan Teki  wrote:
> On Mon, Oct 31, 2016 at 8:48 AM, Vignesh R  wrote:
>>
>>
>> On Sunday 30 October 2016 11:16 PM, Jagan Teki wrote:
>> [...]
>>> + {"S25FL128P_64K",  INFO(0x012018, 0x0301,  64 * 1024,   256, 
>>> RD_FULL | WR_QPP) },
>>> + {"S25FL032P",  INFO(0x010215, 0x4d00,  64 * 1024,64, 
>>> RD_FULL | WR_QPP) },
>>> + {"S25FL064P",  INFO(0x010216, 0x4d00,  64 * 1024,   128, 
>>> RD_FULL | WR_QPP) },
>>> + {"S25FL128S_256K", INFO(0x012018, 0x4d00, 256 * 1024,64, 
>>> RD_FULL | WR_QPP) },
>>> + {"S25FL128S_64K",  INFO(0x012018, 0x4d01,  64 * 1024,   256, 
>>> RD_FULL | WR_QPP) },
>>> + {"S25FL256S_256K", INFO(0x010219, 0x4d00, 256 * 1024,   128, 
>>> RD_FULL | WR_QPP) },
>>> + {"S25FL256S_64K",  INFO(0x010219, 0x4d01,  64 * 1024,   512, 
>>> RD_FULL | WR_QPP) },
>>> + {"S25FS512S",  INFO(0x010220, 0x4D00, 128 * 1024,   512, 
>>> RD_FULL | WR_QPP) },
>>> + {"S25FL512S_256K", INFO(0x010220, 0x4d00, 256 * 1024,   256, 
>>> RD_FULL | WR_QPP) },
>>
>> Could you change above S25FS512S and S25FL512S_256K to use INFO6 macro?
>> Right now, S25FL512S_256K gets detected as S25FS512S and sf update fails
>> due as erasesizes are different.
>
> I think this seems to be an existing issue, even before these changes.
> after this [1] I will prepare a patch to use INFO6 for S25FS512S.
>
> [1] 
> http://git.denx.de/?p=u-boot-spi.git;a=commitdiff;h=13c17cad45ad9040fd0f6ebadf76554eb6353381

 Try u-boot-spi/next?

>>>
>>> Yes, that works. sf probe correctly detects S25FL512S_256K. Thanks!
>>
>> Now it's s25fl512s_256k changed to lower-case hope you detect the same?
>>
>
> Yes here is the log :
>
> U-Boot 2016.11-rc2-00220-g53b750eed351 (Oct 31 2016 - 14:57:11 +0530)
>
> CPU: 66AK2Gx SR1.0
> Model: Texas Instruments Keystone 2 Galileo EVM
> I2C:   ready
> DRAM:
> Clear entire DDR3 memory to enable ECC
> 2 GiB
> MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
> reading uboot.env
>
> ** Unable to read "uboot.env" from mmc0:1 **
> Using default environment
>
> Net:
> Warning: netcp@400 using MAC address from ROM
> eth0: netcp@400
> Hit any key to stop autoboot:  0
> => sf probe 4:0
> SF: Detected s25fl512s_256k with page size 512 Bytes, erase size 256
> KiB, total 64 MiB
> =>

Perfect, thanks!

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Re: [U-Boot] [PATCH v5 01/21] sf: Adopt flash table INFO macro from Linux

[Vignesh R]

On Monday 31 October 2016 03:05 PM, Jagan Teki wrote:
> On Mon, Oct 31, 2016 at 3:02 PM, Vignesh R  wrote:
>>
>>
>> On Monday 31 October 2016 02:50 PM, Jagan Teki wrote:
>>> On Mon, Oct 31, 2016 at 2:24 PM, Jagan Teki  wrote:
 On Mon, Oct 31, 2016 at 8:48 AM, Vignesh R  wrote:
>
>
> On Sunday 30 October 2016 11:16 PM, Jagan Teki wrote:
> [...]
>> + {"S25FL128P_64K",  INFO(0x012018, 0x0301,  64 * 1024,   256, 
>> RD_FULL | WR_QPP) },
>> + {"S25FL032P",  INFO(0x010215, 0x4d00,  64 * 1024,64, 
>> RD_FULL | WR_QPP) },
>> + {"S25FL064P",  INFO(0x010216, 0x4d00,  64 * 1024,   128, 
>> RD_FULL | WR_QPP) },
>> + {"S25FL128S_256K", INFO(0x012018, 0x4d00, 256 * 1024,64, 
>> RD_FULL | WR_QPP) },
>> + {"S25FL128S_64K",  INFO(0x012018, 0x4d01,  64 * 1024,   256, 
>> RD_FULL | WR_QPP) },
>> + {"S25FL256S_256K", INFO(0x010219, 0x4d00, 256 * 1024,   128, 
>> RD_FULL | WR_QPP) },
>> + {"S25FL256S_64K",  INFO(0x010219, 0x4d01,  64 * 1024,   512, 
>> RD_FULL | WR_QPP) },
>> + {"S25FS512S",  INFO(0x010220, 0x4D00, 128 * 1024,   512, 
>> RD_FULL | WR_QPP) },
>> + {"S25FL512S_256K", INFO(0x010220, 0x4d00, 256 * 1024,   256, 
>> RD_FULL | WR_QPP) },
>
> Could you change above S25FS512S and S25FL512S_256K to use INFO6 macro?
> Right now, S25FL512S_256K gets detected as S25FS512S and sf update fails
> due as erasesizes are different.

 I think this seems to be an existing issue, even before these changes.
 after this [1] I will prepare a patch to use INFO6 for S25FS512S.

 [1] 
 http://git.denx.de/?p=u-boot-spi.git;a=commitdiff;h=13c17cad45ad9040fd0f6ebadf76554eb6353381
>>>
>>> Try u-boot-spi/next?
>>>
>>
>> Yes, that works. sf probe correctly detects S25FL512S_256K. Thanks!
> 
> Now it's s25fl512s_256k changed to lower-case hope you detect the same?
> 

Yes here is the log :

U-Boot 2016.11-rc2-00220-g53b750eed351 (Oct 31 2016 - 14:57:11 +0530)

CPU: 66AK2Gx SR1.0
Model: Texas Instruments Keystone 2 Galileo EVM
I2C:   ready
DRAM:
Clear entire DDR3 memory to enable ECC
2 GiB
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
reading uboot.env

** Unable to read "uboot.env" from mmc0:1 **
Using default environment

Net:
Warning: netcp@400 using MAC address from ROM
eth0: netcp@400
Hit any key to stop autoboot:  0
=> sf probe 4:0
SF: Detected s25fl512s_256k with page size 512 Bytes, erase size 256
KiB, total 64 MiB
=>


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Vignesh
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Re: [U-Boot] [PATCH v5 01/21] sf: Adopt flash table INFO macro from Linux

[Jagan Teki]

On Mon, Oct 31, 2016 at 3:02 PM, Vignesh R  wrote:
>
>
> On Monday 31 October 2016 02:50 PM, Jagan Teki wrote:
>> On Mon, Oct 31, 2016 at 2:24 PM, Jagan Teki  wrote:
>>> On Mon, Oct 31, 2016 at 8:48 AM, Vignesh R  wrote:


 On Sunday 30 October 2016 11:16 PM, Jagan Teki wrote:
 [...]
> + {"S25FL128P_64K",  INFO(0x012018, 0x0301,  64 * 1024,   256, 
> RD_FULL | WR_QPP) },
> + {"S25FL032P",  INFO(0x010215, 0x4d00,  64 * 1024,64, 
> RD_FULL | WR_QPP) },
> + {"S25FL064P",  INFO(0x010216, 0x4d00,  64 * 1024,   128, 
> RD_FULL | WR_QPP) },
> + {"S25FL128S_256K", INFO(0x012018, 0x4d00, 256 * 1024,64, 
> RD_FULL | WR_QPP) },
> + {"S25FL128S_64K",  INFO(0x012018, 0x4d01,  64 * 1024,   256, 
> RD_FULL | WR_QPP) },
> + {"S25FL256S_256K", INFO(0x010219, 0x4d00, 256 * 1024,   128, 
> RD_FULL | WR_QPP) },
> + {"S25FL256S_64K",  INFO(0x010219, 0x4d01,  64 * 1024,   512, 
> RD_FULL | WR_QPP) },
> + {"S25FS512S",  INFO(0x010220, 0x4D00, 128 * 1024,   512, 
> RD_FULL | WR_QPP) },
> + {"S25FL512S_256K", INFO(0x010220, 0x4d00, 256 * 1024,   256, 
> RD_FULL | WR_QPP) },

 Could you change above S25FS512S and S25FL512S_256K to use INFO6 macro?
 Right now, S25FL512S_256K gets detected as S25FS512S and sf update fails
 due as erasesizes are different.
>>>
>>> I think this seems to be an existing issue, even before these changes.
>>> after this [1] I will prepare a patch to use INFO6 for S25FS512S.
>>>
>>> [1] 
>>> http://git.denx.de/?p=u-boot-spi.git;a=commitdiff;h=13c17cad45ad9040fd0f6ebadf76554eb6353381
>>
>> Try u-boot-spi/next?
>>
>
> Yes, that works. sf probe correctly detects S25FL512S_256K. Thanks!

Now it's s25fl512s_256k changed to lower-case hope you detect the same?

thanks!
-- 
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Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH v5 01/21] sf: Adopt flash table INFO macro from Linux

[Vignesh R]

On Monday 31 October 2016 02:50 PM, Jagan Teki wrote:
> On Mon, Oct 31, 2016 at 2:24 PM, Jagan Teki  wrote:
>> On Mon, Oct 31, 2016 at 8:48 AM, Vignesh R  wrote:
>>>
>>>
>>> On Sunday 30 October 2016 11:16 PM, Jagan Teki wrote:
>>> [...]
 + {"S25FL128P_64K",  INFO(0x012018, 0x0301,  64 * 1024,   256, RD_FULL 
 | WR_QPP) },
 + {"S25FL032P",  INFO(0x010215, 0x4d00,  64 * 1024,64, RD_FULL 
 | WR_QPP) },
 + {"S25FL064P",  INFO(0x010216, 0x4d00,  64 * 1024,   128, RD_FULL 
 | WR_QPP) },
 + {"S25FL128S_256K", INFO(0x012018, 0x4d00, 256 * 1024,64, RD_FULL 
 | WR_QPP) },
 + {"S25FL128S_64K",  INFO(0x012018, 0x4d01,  64 * 1024,   256, RD_FULL 
 | WR_QPP) },
 + {"S25FL256S_256K", INFO(0x010219, 0x4d00, 256 * 1024,   128, RD_FULL 
 | WR_QPP) },
 + {"S25FL256S_64K",  INFO(0x010219, 0x4d01,  64 * 1024,   512, RD_FULL 
 | WR_QPP) },
 + {"S25FS512S",  INFO(0x010220, 0x4D00, 128 * 1024,   512, RD_FULL 
 | WR_QPP) },
 + {"S25FL512S_256K", INFO(0x010220, 0x4d00, 256 * 1024,   256, RD_FULL 
 | WR_QPP) },
>>>
>>> Could you change above S25FS512S and S25FL512S_256K to use INFO6 macro?
>>> Right now, S25FL512S_256K gets detected as S25FS512S and sf update fails
>>> due as erasesizes are different.
>>
>> I think this seems to be an existing issue, even before these changes.
>> after this [1] I will prepare a patch to use INFO6 for S25FS512S.
>>
>> [1] 
>> http://git.denx.de/?p=u-boot-spi.git;a=commitdiff;h=13c17cad45ad9040fd0f6ebadf76554eb6353381
> 
> Try u-boot-spi/next?
> 

Yes, that works. sf probe correctly detects S25FL512S_256K. Thanks!


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Vignesh
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Re: [U-Boot] [PATCH RESEND v2 2/2] spi: ti_qspi: Fix baudrate divider calculation

[Jagan Teki]

On Mon, Oct 31, 2016 at 9:40 AM, Vignesh R  wrote:
> Fix the divider calculation logic to choose a value so that the
> resulting baudrate is either equal to or closest possible baudrate less
> than the requested value. While at that, cleanup ti_spi_set_speed().
>
> Signed-off-by: Vignesh R 
> ---
>
> v2: cleanup ti_spi_set_speed() a bit.
>
>  drivers/spi/ti_qspi.c | 15 +++
>  1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
> index 52520dff6325..b5de70bf40e3 100644
> --- a/drivers/spi/ti_qspi.c
> +++ b/drivers/spi/ti_qspi.c
> @@ -16,6 +16,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> @@ -118,21 +119,19 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, 
> uint hz)
> if (!hz)
> clk_div = 0;
> else
> -   clk_div = (priv->fclk / hz) - 1;
> -
> -   debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
> +   clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
>
> /* disable SCLK */
> writel(readl(>base->clk_ctrl) & ~QSPI_CLK_EN,
>>base->clk_ctrl);

Move this before enable SCLK.

>
> -   /* assign clk_div values */
> -   if (clk_div < 0)
> -   clk_div = 0;
> -   else if (clk_div > QSPI_CLK_DIV_MAX)
> +   /* truncate clk_div value to QSPI_CLK_DIV_MAX */
> +   if (clk_div > QSPI_CLK_DIV_MAX)
> clk_div = QSPI_CLK_DIV_MAX;
>
> -   /* enable SCLK */
> +   debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
> +
> +   /* enable SCLK and program the clk divider */
> writel(QSPI_CLK_EN | clk_div, >base->clk_ctrl);
>  }

thanks!
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Re: [U-Boot] [PATCH v5 01/21] sf: Adopt flash table INFO macro from Linux

[Jagan Teki]

On Mon, Oct 31, 2016 at 2:24 PM, Jagan Teki  wrote:
> On Mon, Oct 31, 2016 at 8:48 AM, Vignesh R  wrote:
>>
>>
>> On Sunday 30 October 2016 11:16 PM, Jagan Teki wrote:
>> [...]
>>> + {"S25FL128P_64K",  INFO(0x012018, 0x0301,  64 * 1024,   256, RD_FULL 
>>> | WR_QPP) },
>>> + {"S25FL032P",  INFO(0x010215, 0x4d00,  64 * 1024,64, RD_FULL 
>>> | WR_QPP) },
>>> + {"S25FL064P",  INFO(0x010216, 0x4d00,  64 * 1024,   128, RD_FULL 
>>> | WR_QPP) },
>>> + {"S25FL128S_256K", INFO(0x012018, 0x4d00, 256 * 1024,64, RD_FULL 
>>> | WR_QPP) },
>>> + {"S25FL128S_64K",  INFO(0x012018, 0x4d01,  64 * 1024,   256, RD_FULL 
>>> | WR_QPP) },
>>> + {"S25FL256S_256K", INFO(0x010219, 0x4d00, 256 * 1024,   128, RD_FULL 
>>> | WR_QPP) },
>>> + {"S25FL256S_64K",  INFO(0x010219, 0x4d01,  64 * 1024,   512, RD_FULL 
>>> | WR_QPP) },
>>> + {"S25FS512S",  INFO(0x010220, 0x4D00, 128 * 1024,   512, RD_FULL 
>>> | WR_QPP) },
>>> + {"S25FL512S_256K", INFO(0x010220, 0x4d00, 256 * 1024,   256, RD_FULL 
>>> | WR_QPP) },
>>
>> Could you change above S25FS512S and S25FL512S_256K to use INFO6 macro?
>> Right now, S25FL512S_256K gets detected as S25FS512S and sf update fails
>> due as erasesizes are different.
>
> I think this seems to be an existing issue, even before these changes.
> after this [1] I will prepare a patch to use INFO6 for S25FS512S.
>
> [1] 
> http://git.denx.de/?p=u-boot-spi.git;a=commitdiff;h=13c17cad45ad9040fd0f6ebadf76554eb6353381

Try u-boot-spi/next?

thanks!
-- 
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U-Boot, Linux | Upstream Maintainer
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Re: [U-Boot] [PATCH v5 01/21] sf: Adopt flash table INFO macro from Linux

[Jagan Teki]

On Mon, Oct 31, 2016 at 8:48 AM, Vignesh R  wrote:
>
>
> On Sunday 30 October 2016 11:16 PM, Jagan Teki wrote:
> [...]
>> + {"S25FL128P_64K",  INFO(0x012018, 0x0301,  64 * 1024,   256, RD_FULL | 
>> WR_QPP) },
>> + {"S25FL032P",  INFO(0x010215, 0x4d00,  64 * 1024,64, RD_FULL | 
>> WR_QPP) },
>> + {"S25FL064P",  INFO(0x010216, 0x4d00,  64 * 1024,   128, RD_FULL | 
>> WR_QPP) },
>> + {"S25FL128S_256K", INFO(0x012018, 0x4d00, 256 * 1024,64, RD_FULL | 
>> WR_QPP) },
>> + {"S25FL128S_64K",  INFO(0x012018, 0x4d01,  64 * 1024,   256, RD_FULL | 
>> WR_QPP) },
>> + {"S25FL256S_256K", INFO(0x010219, 0x4d00, 256 * 1024,   128, RD_FULL | 
>> WR_QPP) },
>> + {"S25FL256S_64K",  INFO(0x010219, 0x4d01,  64 * 1024,   512, RD_FULL | 
>> WR_QPP) },
>> + {"S25FS512S",  INFO(0x010220, 0x4D00, 128 * 1024,   512, RD_FULL | 
>> WR_QPP) },
>> + {"S25FL512S_256K", INFO(0x010220, 0x4d00, 256 * 1024,   256, RD_FULL | 
>> WR_QPP) },
>
> Could you change above S25FS512S and S25FL512S_256K to use INFO6 macro?
> Right now, S25FL512S_256K gets detected as S25FS512S and sf update fails
> due as erasesizes are different.

I think this seems to be an existing issue, even before these changes.
after this [1] I will prepare a patch to use INFO6 for S25FS512S.

[1] 
http://git.denx.de/?p=u-boot-spi.git;a=commitdiff;h=13c17cad45ad9040fd0f6ebadf76554eb6353381

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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