[U-Boot] [PATCH] spl: don't use %.*s with CONFIG_USE_TINY_PRINTF

[Oded Gabbay]

In the tiny-printf implementation, there is no support for %.*s. This patch
checks if CONFIG_USE_TINY_PRINTF is defined and if so, prints a different
debug statement which doesn't use %.*s

Signed-off-by: Oded Gabbay 
Cc: Simon Glass 
---
 common/spl/spl.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index f7df834..7c4744d 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -115,9 +115,14 @@ int spl_parse_image_header(struct spl_image_info 
*spl_image,
}
spl_image->os = image_get_os(header);
spl_image->name = image_get_name(header);
+#ifdef CONFIG_USE_TINY_PRINTF
+   debug("spl: payload image: %s load addr: 0x%x size: %d\n",
+   spl_image->name, spl_image->load_addr, spl_image->size);
+#else
debug("spl: payload image: %.*s load addr: 0x%x size: %d\n",
(int)sizeof(spl_image->name), spl_image->name,
spl_image->load_addr, spl_image->size);
+#endif
} else {
 #ifdef CONFIG_SPL_PANIC_ON_RAW_IMAGE
/*
-- 
2.7.4

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Re: [U-Boot] [PATCHv3 2/2] armv8/fsl-lsch3: consolidate the clock system initialization

[Z.Q. Hou]

Hi,

Please ignore this patch!

Thanks,
Zhiqiang


> -Original Message-
> From: Zhiqiang Hou [mailto:zhiqiang@nxp.com]
> Sent: 2016年12月28日 14:48
> To: u-boot@lists.denx.de; albert.u.b...@aribaud.net; york sun
> ; Mingkai Hu ; Prabhakar
> Kushwaha ; Calvin Johnson
> 
> Cc: Z.Q. Hou 
> Subject: [PATCHv3 2/2] armv8/fsl-lsch3: consolidate the clock system
> initialization
> 
> From: Hou Zhiqiang 
> 
> This patch binds the sys_info->freq_systembus to Platform PLL, and
> implements the IPs' clock function individually.
> 
> Signed-off-by: Hou Zhiqiang 
> ---
> V3:
>  - No change
> 
>  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 28
> --  .../include/asm/arch-fsl-layerscape/immap_lsch3.h
> |  1 +
>  include/configs/ls2080a_common.h   |  2 +-
>  3 files changed, 23 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> index a9b12a4..f8fefc7 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> @@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info)  #endif
> #endif
> 
> + /* The freq_systembus is used to record frequency of platform PLL */
>   sys_info->freq_systembus *= (gur_in32(>rcwsr[0]) >>
>   FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
>   FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
> - /* Platform clock is half of platform PLL */
> - sys_info->freq_systembus /= 2;
>   sys_info->freq_ddrbus *= (gur_in32(>rcwsr[0]) >>
>   FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
>   FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
> @@ -142,13 +141,13 @@ int get_clocks(void)
>   struct sys_info sys_info;
>   get_sys_info(_info);
>   gd->cpu_clk = sys_info.freq_processor[0];
> - gd->bus_clk = sys_info.freq_systembus;
> + gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
>   gd->mem_clk = sys_info.freq_ddrbus;
>  #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
>   gd->arch.mem2_clk = sys_info.freq_ddrbus2;  #endif  #if
> defined(CONFIG_FSL_ESDHC)
> - gd->arch.sdhc_clk = gd->bus_clk / 2;
> + gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
>  #endif /* defined(CONFIG_FSL_ESDHC) */
> 
>   if (gd->cpu_clk != 0)
> @@ -159,7 +158,7 @@ int get_clocks(void)
> 
>  /
>   * get_bus_freq
> - * return system bus freq in Hz
> + * return platform clock in Hz
>   */
>  ulong get_bus_freq(ulong dummy)
>  {
> @@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num)
>   return gd->mem_clk;
>  }
> 
> +int get_i2c_freq(ulong dummy)
> +{
> + return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV; }
> +
> +int get_dspi_freq(ulong dummy)
> +{
> + return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV; }
> +
> +int get_serial_clock(void)
> +{
> + return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV; }
> +
>  unsigned int mxc_get_clock(enum mxc_clock clk)  {
>   switch (clk) {
>   case MXC_I2C_CLK:
> - return get_bus_freq(0) / 2;
> + return get_i2c_freq(0);
>   case MXC_DSPI_CLK:
> - return get_bus_freq(0) / 2;
> + return get_dspi_freq(0);
>   default:
>   printf("Unsupported clock\n");
>   }
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> index e18dcbd..cd25b48 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> @@ -159,6 +159,7 @@
>  #ifndef __ASSEMBLY__
>  struct sys_info {
>   unsigned long freq_processor[CONFIG_MAX_CPUS];
> + /* frequency of platform PLL */
>   unsigned long freq_systembus;
>   unsigned long freq_ddrbus;
>  #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
> diff --git a/include/configs/ls2080a_common.h
> b/include/configs/ls2080a_common.h
> index 2cae966..cf1185c 100644
> --- a/include/configs/ls2080a_common.h
> +++ b/include/configs/ls2080a_common.h
> @@ -97,7 +97,7 @@
>  #define CONFIG_CONS_INDEX   1
>  #define CONFIG_SYS_NS16550_SERIAL
>  #define CONFIG_SYS_NS16550_REG_SIZE 1
> -#define CONFIG_SYS_NS16550_CLK  (get_bus_freq(0)/2)
> +#define CONFIG_SYS_NS16550_CLK  (get_serial_clock())
> 
>  #define CONFIG_BAUDRATE  115200
>  #define CONFIG_SYS_BAUDRATE_TABLE{ 9600, 19200, 38400, 57600,
> 115200 }
> --
> 2.1.0.27.g96db324

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Re: [U-Boot] [PATCHv4 1/2] armv8/fsl-lsch2: refactor the clock system initialization

[Z.Q. Hou]

Hi,

Please ignore this patch!

Thanks,
Zhiqiang

> -Original Message-
> From: Zhiqiang Hou [mailto:zhiqiang@nxp.com]
> Sent: 2016年12月28日 14:48
> To: u-boot@lists.denx.de; albert.u.b...@aribaud.net; york sun
> ; Mingkai Hu ; Prabhakar
> Kushwaha ; Calvin Johnson
> 
> Cc: Z.Q. Hou 
> Subject: [PATCHv4 1/2] armv8/fsl-lsch2: refactor the clock system 
> initialization
> 
> From: Hou Zhiqiang 
> 
> Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A,
> LS1046A and LS1012A. But the clocks tree has a lot of differences, for 
> instance,
> the IP modules have different dividers to derive its clock from Platform PLL.
> And the core cluster PLL and platform PLL maybe have different reference
> clocks, such as LS1012A. Another problem is which clock/PLL should be
> described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2.
> 
> This patch is to bind the sys_info->freq_systembus to the Platform PLL, and
> handle the different divider of IP modules separately between different SoCs,
> and separate reference clocks of core cluster PLL and platform PLL.
> 
> Signed-off-by: Hou Zhiqiang 
> ---
> V4:
>  - Generate the patch set base on the latest
> git://git.denx.de/u-boot-fsl-qoriq.git.
>  - Correct the description of the IP modules' divider.
> 
>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig  | 76
> ++
>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c|  3 +-
>  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 68
> ++-  .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |
> 1 +
>  include/configs/ls1012a_common.h   |  6 +-
>  include/configs/ls1043a_common.h   |  3 +-
>  include/configs/ls1046a_common.h   |  3 +-
>  include/configs/ls2080aqds.h   |  2 -
>  include/configs/ls2080ardb.h   |  1 -
>  9 files changed, 134 insertions(+), 29 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index cc0dc88..de1e5a4 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -87,6 +87,82 @@ config MAX_CPUS
> cores, count the reserved ports. This will allocate enough memory
> in spin table to properly handle all cores.
> 
> +menu "Layerscape clock tree configuration"
> + depends on FSL_LSCH2 || FSL_LSCH3
> +
> +config SYS_FSL_CLK
> + bool "Enable clock tree initialization"
> + default y
> +
> +config CLUSTER_CLK_FREQ
> + int "Reference clock of core cluster"
> + depends on ARCH_LS1012A
> + default 1
> + help
> +   This number is the reference clock frequency of core PLL.
> +   For most platforms, the core PLL and Platform PLL have the same
> +   reference clock, but for some platforms, LS1012A for instance,
> +   they are provided sepatately.
> +
> +config SYS_FSL_PCLK_DIV
> + int "Platform clock divider"
> + default 1 if ARCH_LS1043A
> + default 1 if ARCH_LS1046A
> + default 2
> + help
> +   This is the divider that is used to derive Platform clock from
> +   Platform PLL, in another word:
> + Platform_clk = Platform_PLL_freq / this_divider
> +
> +config SYS_FSL_DSPI_CLK_DIV
> + int "DSPI clock divider"
> + default 1 if ARCH_LS1043A
> + default 2
> + help
> +   This is the divider that is used to derive DSPI clock from Platform
> +   PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
> +
> +config SYS_FSL_DUART_CLK_DIV
> + int "DUART clock divider"
> + default 1 if ARCH_LS1043A
> + default 2
> + help
> +   This is the divider that is used to derive DUART clock from Platform
> +   clock, in another word DUART_clk = Platform_clk / this_divider.
> +
> +config SYS_FSL_I2C_CLK_DIV
> + int "I2C clock divider"
> + default 1 if ARCH_LS1043A
> + default 2
> + help
> +   This is the divider that is used to derive I2C clock from Platform
> +   clock, in another word I2C_clk = Platform_clk / this_divider.
> +
> +config SYS_FSL_IFC_CLK_DIV
> + int "IFC clock divider"
> + default 1 if ARCH_LS1043A
> + default 2
> + help
> +   This is the divider that is used to derive IFC clock from Platform
> +   clock, in another word IFC_clk = Platform_clk / this_divider.
> +
> +config SYS_FSL_LPUART_CLK_DIV
> + int "LPUART clock divider"
> + default 1 if ARCH_LS1043A
> + default 2
> + help
> +   This is the divider that is used to derive LPUART clock from Platform
> +   clock, in another word LPUART_clk = Platform_clk / this_divider.
> +
> +config SYS_FSL_SDHC_CLK_DIV
> + int "SDHC clock divider"
> + default 1 if ARCH_LS1043A
> + default 2
> 

[U-Boot] [PATCHv3 2/2] armv8/fsl-lsch3: consolidate the clock system initialization

[Zhiqiang Hou]

From: Hou Zhiqiang 

This patch binds the sys_info->freq_systembus to Platform PLL, and
implements the IPs' clock function individually.

Signed-off-by: Hou Zhiqiang 
---
V3:
 - No change

 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 28 --
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
 include/configs/ls2080a_common.h   |  2 +-
 3 files changed, 23 insertions(+), 8 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index a9b12a4..f8fefc7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info)
 #endif
 #endif
 
+   /* The freq_systembus is used to record frequency of platform PLL */
sys_info->freq_systembus *= (gur_in32(>rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
-   /* Platform clock is half of platform PLL */
-   sys_info->freq_systembus /= 2;
sys_info->freq_ddrbus *= (gur_in32(>rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
@@ -142,13 +141,13 @@ int get_clocks(void)
struct sys_info sys_info;
get_sys_info(_info);
gd->cpu_clk = sys_info.freq_processor[0];
-   gd->bus_clk = sys_info.freq_systembus;
+   gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
gd->mem_clk = sys_info.freq_ddrbus;
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
gd->arch.mem2_clk = sys_info.freq_ddrbus2;
 #endif
 #if defined(CONFIG_FSL_ESDHC)
-   gd->arch.sdhc_clk = gd->bus_clk / 2;
+   gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
 #endif /* defined(CONFIG_FSL_ESDHC) */
 
if (gd->cpu_clk != 0)
@@ -159,7 +158,7 @@ int get_clocks(void)
 
 /
  * get_bus_freq
- * return system bus freq in Hz
+ * return platform clock in Hz
  */
 ulong get_bus_freq(ulong dummy)
 {
@@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num)
return gd->mem_clk;
 }
 
+int get_i2c_freq(ulong dummy)
+{
+   return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV;
+}
+
+int get_dspi_freq(ulong dummy)
+{
+   return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
+}
+
+int get_serial_clock(void)
+{
+   return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
+}
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
switch (clk) {
case MXC_I2C_CLK:
-   return get_bus_freq(0) / 2;
+   return get_i2c_freq(0);
case MXC_DSPI_CLK:
-   return get_bus_freq(0) / 2;
+   return get_dspi_freq(0);
default:
printf("Unsupported clock\n");
}
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index e18dcbd..cd25b48 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -159,6 +159,7 @@
 #ifndef __ASSEMBLY__
 struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];
+   /* frequency of platform PLL */
unsigned long freq_systembus;
unsigned long freq_ddrbus;
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 2cae966..cf1185c 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -97,7 +97,7 @@
 #define CONFIG_CONS_INDEX   1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK  (get_bus_freq(0)/2)
+#define CONFIG_SYS_NS16550_CLK  (get_serial_clock())
 
 #define CONFIG_BAUDRATE115200
 #define CONFIG_SYS_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCHv4 2/2] armv8/fsl-lsch3: consolidate the clock system initialization

[Zhiqiang Hou]

From: Hou Zhiqiang 

This patch binds the sys_info->freq_systembus to Platform PLL, and
implements the IPs' clock function individually.

Signed-off-by: Hou Zhiqiang 
---
V4:
 - No change

 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 28 --
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
 include/configs/ls2080a_common.h   |  2 +-
 3 files changed, 23 insertions(+), 8 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index a9b12a4..f8fefc7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info)
 #endif
 #endif
 
+   /* The freq_systembus is used to record frequency of platform PLL */
sys_info->freq_systembus *= (gur_in32(>rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
-   /* Platform clock is half of platform PLL */
-   sys_info->freq_systembus /= 2;
sys_info->freq_ddrbus *= (gur_in32(>rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
@@ -142,13 +141,13 @@ int get_clocks(void)
struct sys_info sys_info;
get_sys_info(_info);
gd->cpu_clk = sys_info.freq_processor[0];
-   gd->bus_clk = sys_info.freq_systembus;
+   gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
gd->mem_clk = sys_info.freq_ddrbus;
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
gd->arch.mem2_clk = sys_info.freq_ddrbus2;
 #endif
 #if defined(CONFIG_FSL_ESDHC)
-   gd->arch.sdhc_clk = gd->bus_clk / 2;
+   gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
 #endif /* defined(CONFIG_FSL_ESDHC) */
 
if (gd->cpu_clk != 0)
@@ -159,7 +158,7 @@ int get_clocks(void)
 
 /
  * get_bus_freq
- * return system bus freq in Hz
+ * return platform clock in Hz
  */
 ulong get_bus_freq(ulong dummy)
 {
@@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num)
return gd->mem_clk;
 }
 
+int get_i2c_freq(ulong dummy)
+{
+   return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV;
+}
+
+int get_dspi_freq(ulong dummy)
+{
+   return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
+}
+
+int get_serial_clock(void)
+{
+   return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
+}
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
switch (clk) {
case MXC_I2C_CLK:
-   return get_bus_freq(0) / 2;
+   return get_i2c_freq(0);
case MXC_DSPI_CLK:
-   return get_bus_freq(0) / 2;
+   return get_dspi_freq(0);
default:
printf("Unsupported clock\n");
}
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index e18dcbd..cd25b48 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -159,6 +159,7 @@
 #ifndef __ASSEMBLY__
 struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];
+   /* frequency of platform PLL */
unsigned long freq_systembus;
unsigned long freq_ddrbus;
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 2cae966..cf1185c 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -97,7 +97,7 @@
 #define CONFIG_CONS_INDEX   1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK  (get_bus_freq(0)/2)
+#define CONFIG_SYS_NS16550_CLK  (get_serial_clock())
 
 #define CONFIG_BAUDRATE115200
 #define CONFIG_SYS_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCHv4 1/2] armv8/fsl-lsch2: refactor the clock system initialization

[Zhiqiang Hou]

From: Hou Zhiqiang 

Up to now, there are 3 kind of SoCs under Layerscape Chassis 2,
like LS1043A, LS1046A and LS1012A. But the clocks tree has a
lot of differences, for instance, the IP modules have different
dividers to derive its clock from Platform PLL. And the core
cluster PLL and platform PLL maybe have different reference
clocks, such as LS1012A. Another problem is which clock/PLL
should be described by sys_info->freq_systembus, it is confused
in Layerscape Chissis 2.

This patch is to bind the sys_info->freq_systembus to the Platform
PLL, and handle the different divider of IP modules separately
between different SoCs, and separate reference clocks of core
cluster PLL and platform PLL.

Signed-off-by: Hou Zhiqiang 
---
V4:
 - Generate the patch set base on the latest 
git://git.denx.de/u-boot-fsl-qoriq.git.
 - Correct the description of the IP modules' divider.

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  | 76 ++
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c|  3 +-
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 68 ++-
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  1 +
 include/configs/ls1012a_common.h   |  6 +-
 include/configs/ls1043a_common.h   |  3 +-
 include/configs/ls1046a_common.h   |  3 +-
 include/configs/ls2080aqds.h   |  2 -
 include/configs/ls2080ardb.h   |  1 -
 9 files changed, 134 insertions(+), 29 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index cc0dc88..de1e5a4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -87,6 +87,82 @@ config MAX_CPUS
  cores, count the reserved ports. This will allocate enough memory
  in spin table to properly handle all cores.
 
+menu "Layerscape clock tree configuration"
+   depends on FSL_LSCH2 || FSL_LSCH3
+
+config SYS_FSL_CLK
+   bool "Enable clock tree initialization"
+   default y
+
+config CLUSTER_CLK_FREQ
+   int "Reference clock of core cluster"
+   depends on ARCH_LS1012A
+   default 1
+   help
+ This number is the reference clock frequency of core PLL.
+ For most platforms, the core PLL and Platform PLL have the same
+ reference clock, but for some platforms, LS1012A for instance,
+ they are provided sepatately.
+
+config SYS_FSL_PCLK_DIV
+   int "Platform clock divider"
+   default 1 if ARCH_LS1043A
+   default 1 if ARCH_LS1046A
+   default 2
+   help
+ This is the divider that is used to derive Platform clock from
+ Platform PLL, in another word:
+   Platform_clk = Platform_PLL_freq / this_divider
+
+config SYS_FSL_DSPI_CLK_DIV
+   int "DSPI clock divider"
+   default 1 if ARCH_LS1043A
+   default 2
+   help
+ This is the divider that is used to derive DSPI clock from Platform
+ PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
+
+config SYS_FSL_DUART_CLK_DIV
+   int "DUART clock divider"
+   default 1 if ARCH_LS1043A
+   default 2
+   help
+ This is the divider that is used to derive DUART clock from Platform
+ clock, in another word DUART_clk = Platform_clk / this_divider.
+
+config SYS_FSL_I2C_CLK_DIV
+   int "I2C clock divider"
+   default 1 if ARCH_LS1043A
+   default 2
+   help
+ This is the divider that is used to derive I2C clock from Platform
+ clock, in another word I2C_clk = Platform_clk / this_divider.
+
+config SYS_FSL_IFC_CLK_DIV
+   int "IFC clock divider"
+   default 1 if ARCH_LS1043A
+   default 2
+   help
+ This is the divider that is used to derive IFC clock from Platform
+ clock, in another word IFC_clk = Platform_clk / this_divider.
+
+config SYS_FSL_LPUART_CLK_DIV
+   int "LPUART clock divider"
+   default 1 if ARCH_LS1043A
+   default 2
+   help
+ This is the divider that is used to derive LPUART clock from Platform
+ clock, in another word LPUART_clk = Platform_clk / this_divider.
+
+config SYS_FSL_SDHC_CLK_DIV
+   int "SDHC clock divider"
+   default 1 if ARCH_LS1043A
+   default 2
+   help
+ This is the divider that is used to derive SDHC clock from Platform
+ clock, in another word SDHC_clk = Platform_clk / this_divider.
+endmenu
+
 config NUM_DDR_CONTROLLERS
int "Maximum DDR controllers"
default 3 if ARCH_LS2080A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 467d9af..3bdeb0e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -345,8 +345,9 @@ int print_cpuinfo(void)
   (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
 

[U-Boot] [PATCHv4 1/2] armv8/fsl-lsch2: refactor the clock system initialization

[Zhiqiang Hou]

From: Hou Zhiqiang 

Up to now, there are 3 kind of SoCs under Layerscape Chassis 2,
like LS1043A, LS1046A and LS1012A. But the clocks tree has a
lot of differences, for instance, the IP modules have different
dividers to derive its clock from Platform PLL. And the core
cluster PLL and platform PLL maybe have different reference
clocks, such as LS1012A. Another problem is which clock/PLL
should be described by sys_info->freq_systembus, it is confused
in Layerscape Chissis 2.

This patch is to bind the sys_info->freq_systembus to the Platform
PLL, and handle the different divider of IP modules separately
between different SoCs, and separate reference clocks of core
cluster PLL and platform PLL.

Signed-off-by: Hou Zhiqiang 
---
V4:
 - Correct the description of the IP modules' divider.

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  | 76 ++
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c|  3 +-
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 68 ++-
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  1 +
 include/configs/ls1012a_common.h   |  6 +-
 include/configs/ls1043a_common.h   |  3 +-
 include/configs/ls1046a_common.h   |  3 +-
 include/configs/ls2080aqds.h   |  2 -
 include/configs/ls2080ardb.h   |  1 -
 9 files changed, 134 insertions(+), 29 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index cc0dc88..469886f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -87,6 +87,82 @@ config MAX_CPUS
  cores, count the reserved ports. This will allocate enough memory
  in spin table to properly handle all cores.
 
+menu "Layerscape clock tree configuration"
+   depends on FSL_LSCH2 || FSL_LSCH3
+
+config SYS_FSL_CLK
+   bool "Enable clock tree initialization"
+   default y
+
+config CLUSTER_CLK_FREQ
+   int "Reference clock of core cluster"
+   depends on ARCH_LS1012A
+   default 1
+   help
+ This number is the reference clock frequency of core PLL.
+ For most platforms, the core PLL and Platform PLL have the same
+ reference clock, but for some platforms, LS1012A for instance,
+ they are provided sepatately.
+
+config SYS_FSL_PCLK_DIV
+   int "Platform clock divider"
+   default 1 if ARCH_LS1043A
+   default 1 if ARCH_LS1046A
+   default 2
+   help
+ This is the divider that is used to derive Platform clock from
+ Platform PLL, in another word:
+   Platform_clk = Platform_PLL_freq / this_divider
+
+config SYS_FSL_DSPI_CLK_DIV
+   int "DSPI clock divider"
+   default 1 if ARCH_LS1043A
+   default 2
+   help
+ This is the divider that is used to derive DSPI clock from Platform
+ PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
+
+config SYS_FSL_DUART_CLK_DIV
+   int "DUART clock divider"
+   default 1 if ARCH_LS1043A
+   default 2
+   help
+ This is the divider that is used to derive DUART clock from Platform
+ clock, in another word DUART_clk = Platform_clk / this_divider.
+
+config SYS_FSL_I2C_CLK_DIV
+   int "I2C clock divider"
+   default 1 if ARCH_LS1043A
+   default 2
+   help
+ This is the divider that is used to derive I2C clock from Platform
+ clock, in another word I2C_clk = Platform_clk / this_divider.
+
+config SYS_FSL_IFC_CLK_DIV
+   int "IFC clock divider"
+   default 1 if ARCH_LS1043A
+   default 2
+   help
+ This is the divider that is used to derive IFC clock from Platform
+ clock, in another word IFC_clk = Platform_clk / this_divider.
+
+config SYS_FSL_LPUART_CLK_DIV
+   int "LPUART clock divider"
+   default 1 if ARCH_LS1043A
+   default 2
+   help
+ This is the divider that is used to derive LPUART clock from Platform
+ clock, in another word LPUART_clk = Platform_clk / this_divider.
+
+config SYS_FSL_SDHC_CLK_DIV
+   int "SDHC clock divider"
+   default 1 if ARCH_LS1043A
+   default 2
+   help
+ This is the divider that is used to derive SDHC clock from Platform
+ clock, in another word SDHC_clk = Platform_clk / this_divider.
+endmenu
+
 config NUM_DDR_CONTROLLERS
int "Maximum DDR controllers"
default 3 if ARCH_LS2080A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 467d9af..3bdeb0e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -345,8 +345,9 @@ int print_cpuinfo(void)
   (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
   strmhz(buf, sysinfo.freq_processor[core]));
}
+   /* 

[U-Boot] [PATCH v2 29/30] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

[Chee Tien Fong]

From: Tien Fong Chee 

This patch adding the Arria10 critical hardware initialization before
enabling console print out in spl.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V2
- Release UART from reset before enalbing console, and reverting license
  changes.
---
 arch/arm/mach-socfpga/spl.c | 84 +++--
 1 file changed, 82 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index fec4c7a..9e27f82 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -19,22 +19,32 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
const u32 bsel = readl(_regs->bootinfo);
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
switch (bsel & 0x7) {
case 0x1:   /* FPGA (HPS2FPGA Bridge) */
return BOOT_DEVICE_RAM;
@@ -55,6 +65,24 @@ u32 spl_boot_device(void)
printf("Invalid boot device (bsel=%08x)!\n", bsel);
hang();
}
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   switch ((bsel>>12) & 0x7) {
+   case 0x1:   /* FPGA (HPS2FPGA Bridge) */
+   return BOOT_DEVICE_RAM;
+   case 0x2:   /* NAND Flash (1.8V) */
+   case 0x3:   /* NAND Flash (3.0V) */
+   return BOOT_DEVICE_NAND;
+   case 0x4:   /* SD/MMC External Transceiver (1.8V) */
+   case 0x5:   /* SD/MMC Internal Transceiver (3.0V) */
+   return BOOT_DEVICE_MMC1;
+   case 0x6:   /* QSPI Flash (1.8V) */
+   case 0x7:   /* QSPI Flash (3.0V) */
+   return BOOT_DEVICE_SPI;
+   default:
+   printf("Invalid boot device (bsel=%08x)!\n", bsel);
+   hang();
+   }
+#endif
 }
 
 #ifdef CONFIG_SPL_MMC_SUPPORT
@@ -68,6 +96,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
writel(0x1, _regs->lwhps2fpgaregs);
@@ -182,3 +211,54 @@ void board_init_f(ulong dummy)
/* Configure simple malloc base pointer into RAM. */
gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
 }
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void board_init_f(ulong dummy)
+{
+   memset(__bss_start, 0, __bss_end - __bss_start);
+   /*
+* Configure Clock Manager to use intosc clock instead external osc to
+* ensure success watchdog operation. We do it as early as possible.
+*/
+   cm_use_intosc();
+
+   watchdog_disable();
+
+   arch_early_init_r();
+
+#ifdef CONFIG_HW_WATCHDOG
+   /* release osc1 watchdog timer 0 from reset */
+   reset_deassert_osc1wd0();
+
+   /* reconfigure and enable the watchdog */
+   hw_watchdog_init();
+   WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
+
+#ifdef CONFIG_OF_CONTROL
+   /* We need to access to FDT as this stage */
+   /* FDT is at end of image */
+   gd->fdt_blob = (void *)(__bss_end);
+   /* Check whether we have a valid FDT or not. */
+   if (fdtdec_prepare_fdt()) {
+   panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
+   "doc/README.fdt-control");
+   }
+#endif /* CONFIG_OF_CONTROL */
+
+   /* Initialize the timer */
+   timer_init();
+
+   /* configuring the clock based on handoff */
+   cm_basic_init(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   config_dedicated_pins(gd->fdt_blob);
+   WATCHDOG_RESET();
+
+   /* Release UART from reset */
+   reset_deassert_uart();
+
+   /* enable console uart printing */
+   preloader_console_init();
+}
+#endif
-- 
2.2.2

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[U-Boot] [PATCH v2 30/30] arm: socfpga: arria10: Enable fpga driver build for SPL.

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V2
- resolved build error of undefined some functions in fpga driver for SPL
  build
---
 drivers/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/Makefile b/drivers/Makefile
index c19fa14..c15796b 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_$(SPL_)PINCTRL)+= pinctrl/
 obj-$(CONFIG_$(SPL_)RAM)   += ram/
 
 ifdef CONFIG_SPL_BUILD
-
+obj-$(CONFIG_FPGA) += fpga/
 obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
 obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/
 obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
-- 
2.2.2

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[U-Boot] [PATCH v2 28/30] arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins configuration

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V2
- Removed extern declaration.
---
 arch/arm/mach-socfpga/include/mach/pinmux.h |  17 +
 arch/arm/mach-socfpga/pinmux.c  | 104 
 2 files changed, 121 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/pinmux.h
 create mode 100644 arch/arm/mach-socfpga/pinmux.c

diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h 
b/arch/arm/mach-socfpga/include/mach/pinmux.h
new file mode 100644
index 000..ff54caa
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/pinmux.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_PINMUX_H_
+#define_PINMUX_H_
+
+#ifndef __ASSEMBLY__
+int config_dedicated_pins(const void *blob);
+int config_pins(const void *blob, const char *pin_grp);
+#endif
+
+
+
+#endif /* _PINMUX_H_ */
diff --git a/arch/arm/mach-socfpga/pinmux.c b/arch/arm/mach-socfpga/pinmux.c
new file mode 100644
index 000..d45722f
--- /dev/null
+++ b/arch/arm/mach-socfpga/pinmux.c
@@ -0,0 +1,104 @@
+/*
+ *  Copyright (C) 2016 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+int config_dedicated_pins(const void *blob);
+int config_pins(const void *blob, const char *pin_grp);
+static int __do_pinctr_pins(const void *blob, int child, const char 
*node_name);
+static int do_pinctrl_pins(const void *blob, int node, const char *child_name);
+
+static int __do_pinctr_pins(const void *blob, int child, const char *node_name)
+{
+   int len;
+   fdt_addr_t base_addr;
+   fdt_size_t size;
+   const u32 *cell;
+   u32 offset, value;
+
+   base_addr = fdtdec_get_addr_size(blob, child, "reg", );
+   if (base_addr != FDT_ADDR_T_NONE) {
+   cell = fdt_getprop(blob, child, "pinctrl-single,pins",
+   );
+   if (cell != NULL) {
+   debug("%p %d\n", cell, len);
+   for (;len > 0; len -= (2*sizeof(u32))) {
+   offset = fdt32_to_cpu(*cell++);
+   value = fdt32_to_cpu(*cell++);
+   debug("<0x%x 0x%x>\n", offset, value);
+   writel(value, base_addr + offset);
+   }
+   return 0;
+   }
+   }
+   return 1;
+}
+
+static int do_pinctrl_pins(const void *blob, int node, const char *child_name)
+{
+   int child, len;
+   const char *node_name;
+
+   child = fdt_first_subnode(blob, node);
+
+   if (child < 0)
+   return 2;
+
+   node_name = fdt_get_name(blob, child, );
+
+   while (node_name) {
+   if (!strcmp(child_name, node_name)) {
+   __do_pinctr_pins(blob, child, node_name);
+   return(0);
+   }
+   child = fdt_next_subnode(blob, child);
+
+   if (child < 0)
+   break;
+
+   node_name = fdt_get_name(blob, child, );
+   }
+
+   return 1;
+}
+
+int config_dedicated_pins(const void *blob)
+{
+   int node;
+
+   node = fdtdec_next_compatible(blob, 0,
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+
+   if (node < 0)
+   return 1;
+
+   if (do_pinctrl_pins(blob, node, "dedicated_cfg"))
+   return 2;
+
+   if (do_pinctrl_pins(blob, node, "dedicated"))
+   return 3;
+
+   return 0;
+}
+
+int config_pins(const void *blob, const char *pin_grp)
+{
+   int node;
+
+   node = fdtdec_next_compatible(blob, 0,
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+
+   if (node < 0)
+   return 1;
+
+   if (do_pinctrl_pins(blob, node, pin_grp))
+   return 2;
+
+   return 0;
+}
-- 
2.2.2

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[U-Boot] [PATCH v2 26/30] arm: socfpga: arria10: Added miscellaneous drivers for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

The drivers is restructured such common functions, gen5 functions. and
arria10 functions are moved to misc.c, misc_gen5 and misc_arria10
respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Tien Fong 
---
Changes for V2
- Populating base address of UART based on handoff setting.
---
 arch/arm/mach-socfpga/Makefile|   6 +-
 arch/arm/mach-socfpga/include/mach/misc.h |  32 ++
 arch/arm/mach-socfpga/misc.c  | 427 +-
 arch/arm/mach-socfpga/misc_arria10.c  | 255 +++
 arch/arm/mach-socfpga/{misc.c => misc_gen5.c} | 232 ++
 5 files changed, 337 insertions(+), 615 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/misc.h
 create mode 100644 arch/arm/mach-socfpga/misc_arria10.c
 copy arch/arm/mach-socfpga/{misc.c => misc_gen5.c} (66%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b8fcf6e..1ab68be 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -9,9 +9,11 @@
 
 obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
   fpga_manager.o board.o
-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o misc_arria10.o 
\
+   clock_manager_arria10.o pinmux.o
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
-   reset_manager_gen5.o
+   reset_manager_gen5.o misc_gen5.o \
+   clock_manager_gen5.o
 
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h 
b/arch/arm/mach-socfpga/include/mach/misc.h
new file mode 100644
index 000..045268d
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _MISC_H_
+#define_MISC_H_
+
+extern void dwmac_deassert_reset(const unsigned int of_reset_id,
+const u32 phymode);
+
+struct bsel{
+   const char  *mode;
+   const char  *name;
+};
+
+extern struct bsel bsel_str[];
+
+#ifdef CONFIG_FPGA
+extern void socfpga_fpga_add(void);
+#else
+inline void socfpga_fpga_add(void) {}
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+unsigned int dedicated_uart_com_port(const void *blob);
+unsigned int shared_uart_com_port(const void *blob);
+unsigned int uart_com_port(const void *blob);
+#endif
+
+#endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 510aa1d..7fd5c0e 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,45 +7,33 @@
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
-#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#include 
-#else
-#include 
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pl310_regs *const pl310 =
+static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-static struct socfpga_system_manager *sysmgr_regs =
-   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-static struct socfpga_reset_manager *reset_manager_base =
-   (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-static struct nic301_registers *nic301_regs =
-   (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-#else
-static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
-   (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
-static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
-   (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
-#endif
-static struct scu_registers *scu_regs =
-   (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
+
+struct bselbsel_str[] = {
+   { "rsvd", "Reserved", },
+   { "fpga", "FPGA (HPS2FPGA Bridge)", },
+   { "nand", "NAND Flash (1.8V)", },
+   { "nand", "NAND Flash (3.0V)", },
+   { "sd", "SD/MMC External Transceiver (1.8V)", },
+   { "sd", "SD/MMC Internal Transceiver (3.0V)", },
+   { "qspi", "QSPI Flash (1.8V)", },
+   { "qspi", "QSPI Flash (3.0V)", },
+};
 
 int dram_init(void)
 {
@@ -84,219 +72,6 @@ void v7_outer_cache_disable(void)
clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
 }
 
-/*
- * DesignWare Ethernet initialization
- */
-#ifdef CONFIG_ETH_DESIGNWARE
-static void dwmac_deassert_reset(const unsigned 

[U-Boot] [PATCH v2 25/30] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

[Chee Tien Fong]

From: Tien Fong Chee 

Drivers for reset manager is restructured such that common functions,
gen5 drivers and Arria10 drivers are moved to reset_manager.c,
reset_manager_gen5.c and reset_manager_arria10.c respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V2
- Reverted license changes, removing extern and volatile declaration
---
 arch/arm/mach-socfpga/Makefile |  16 +-
 arch/arm/mach-socfpga/include/mach/reset_manager.h | 155 ++--
 arch/arm/mach-socfpga/reset_manager.c  | 112 +-
 arch/arm/mach-socfpga/reset_manager_arria10.c  | 407 +
 .../{reset_manager.c => reset_manager_gen5.c}  |  94 ++---
 5 files changed, 570 insertions(+), 214 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
 copy arch/arm/mach-socfpga/{reset_manager.c => reset_manager_gen5.c} (58%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 809cd47..b8fcf6e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -2,21 +2,27 @@
 # (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 #
-# Copyright (C) 2012 Altera Corporation 
+# Copyright (C) 2012-2016 Altera Corporation 
 #
 # SPDX-License-Identifier: GPL-2.0+
 #
 
 obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
   fpga_manager.o board.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
+   reset_manager_gen5.o
 
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o wrap_iocsr_config.o \
+   wrap_pinmux_config.o wrap_sdram_config.o
+endif
 
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
 # QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5)  += scan_manager.o wrap_pll_config.o
-obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o\
-  wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pinmux_config.o+= -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pll_config.o   += -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
+endif
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6225118..13f9731 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation 
+ *  Copyright (C) 2012-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,15 +7,27 @@
 #ifndef_RESET_MANAGER_H_
 #define_RESET_MANAGER_H_
 
+/* Common function prototypes */
 void reset_cpu(ulong addr);
-void reset_deassert_peripherals_handoff(void);
-
 void socfpga_bridges_reset(int enable);
-
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+void reset_deassert_peripherals_handoff(void);
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void watchdog_disable(void);
+void reset_deassert_noc_ddr_scheduler(void);
+int is_wdt_in_reset(void);
+void emac_manage_reset(ulong emacbase, uint state);
+int reset_deassert_bridges_handoff(void);
+void reset_assert_fpga_connected_peripherals(void);
+void reset_deassert_osc1wd0(void);
+void reset_assert_uart(void);
+void reset_deassert_uart(void);
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -29,40 +41,40 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
 };
-#else
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 struct socfpga_reset_manager {
-   u32 stat;
-   u32 ramstat;
-   u32 miscstat;
-   u32 ctrl;
-   u32 hdsken;
-   u32 hdskreq;
-   u32 hdskack;
-   u32 counts;
-   u32 mpu_mod_reset;
-   u32 per_mod_reset;  /* stated as per0_mod_reset in A10 datasheet */
-   u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */
-   u32 brg_mod_reset;
-   u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */
-   u32 coldmodrst;
-   u32 nrstmodrst;
-   u32 dbgmodrst;
-   u32 mpuwarmmask;
-   u32 per0warmmask;
-   u32 per1warmmask;
-   u32 brgwarmmask;
-   u32 syswarmmask;
-   u32 nrstwarmmask;
-   u32 l3warmmask;
-   u32 tststa;
-   u32 

[U-Boot] [PATCH v2 27/30] arm: socfpga: arria10: Added drivers for Arria10 clock manager

[Chee Tien Fong]

From: Tien Fong Chee 

The drivers is restructured such common functions, gen5 functions, and
arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
clock_manager_arria10 respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ching Liang See 
Cc: Tien Fong 
---
Changes for V2
- Reverted license changes, removing extern and volatile declaration.
---
 arch/arm/mach-socfpga/clock_manager.c  | 752 +++-
 arch/arm/mach-socfpga/clock_manager_arria10.c  | 954 +
 .../{clock_manager.c => clock_manager_gen5.c}  | 240 +-
 arch/arm/mach-socfpga/include/mach/clock_manager.h | 356 ++--
 4 files changed, 1573 insertions(+), 729 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
 copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (62%)

diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index aa71636..d209f7d 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2013 Altera Corporation 
+ *  Copyright (C) 2013-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,416 +7,287 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* Function prototypes */
+/* Common prototypes */
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+static void cm_print_clock_quick_summary(void);
+int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+void cm_wait_for_lock(uint32_t mask);
+void cm_wait_for_fsm(void);
+unsigned int cm_get_main_vco_clk_hz(void);
+unsigned int cm_get_per_vco_clk_hz(void);
+unsigned long cm_get_mpu_clk_hz(void);
+
 static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
-static void cm_wait_for_lock(uint32_t mask)
+/* Common functions */
+int set_cpu_clk_info(void)
 {
-   register uint32_t inter_val;
-   uint32_t retry = 0;
-   do {
-   inter_val = readl(_manager_base->inter) & mask;
-   if (inter_val == mask)
-   retry++;
-   else
-   retry = 0;
-   if (retry >= 10)
-   break;
-   } while (1);
-}
+   /* Calculate the clock frequencies required for drivers */
+   cm_get_l4_sp_clk_hz();
+   cm_get_mmc_controller_clk_hz();
 
-/* function to poll in the fsm busy bit */
-static void cm_wait_for_fsm(void)
-{
-   while (readl(_manager_base->stat) & CLKMGR_STAT_BUSY)
-   ;
-}
+   gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 100;
+   gd->bd->bi_dsp_freq = 0;
 
-/*
- * function to write the bypass register which requires a poll of the
- * busy bit
- */
-static void cm_write_bypass(uint32_t val)
-{
-   writel(val, _manager_base->bypass);
-   cm_wait_for_fsm();
-}
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   gd->bd->bi_ddr_freq = 0;
+#endif
 
-/* function to write the ctrl register which requires a poll of the busy bit */
-static void cm_write_ctrl(uint32_t val)
-{
-   writel(val, _manager_base->ctrl);
-   cm_wait_for_fsm();
+   return 0;
 }
 
-/* function to write a clock register that has phase information */
-static void cm_write_with_phase(uint32_t value,
-   uint32_t reg_address, uint32_t mask)
+unsigned int cm_get_spi_controller_clk_hz(void)
 {
-   /* poll until phase is zero */
-   while (readl(reg_address) & mask)
-   ;
+   uint32_t clock = 0;
 
-   writel(value, reg_address);
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   uint32_t reg;
+   clock = cm_get_per_vco_clk_hz();
 
-   while (readl(reg_address) & mask)
-   ;
-}
+   /* get the clock prior L4 SP divider (periph_base_clk) */
+   reg = readl(_manager_base->per_pll.perbaseclk);
+   clock /= (reg + 1);
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   clock = cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);
+#endif
 
-/*
- * Setup clocks while making no assumptions about previous state of the clocks.
- *
- * Start by being paranoid and gate all sw managed clocks
- * Put all plls in bypass
- * Put all plls VCO registers back to reset value (bandgap power down).
- * Put peripheral and main pll src to reset value to avoid glitch.
- * Delay 5 us.
- * Deassert bandgap power down and set numerator and denominator
- * Start 7 us timer.
- * set internal dividers
- * Wait for 7 us timer.
- * Enable 

[U-Boot] [PATCH v2 22/30] arm: socfpga: arria10: Added clock manager and pin mux compat macro

[Chee Tien Fong]

From: Tien Fong Chee 

These compat macros would be used by clock manager and pin mux drivers
to look the required HW info from DTS for hardware initialization.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V2
- Added only compat strings with matching drivers in this series patches
---
 include/fdtdec.h | 8 
 lib/fdtdec.c | 8 
 2 files changed, 16 insertions(+)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index d074478..73e3a46 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -155,6 +155,14 @@ enum fdt_compat_id {
COMPAT_INTEL_BAYTRAIL_FSP_MDP,  /* Intel FSP memory-down params */
COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */
COMPAT_SUNXI_NAND,  /* SUNXI NAND controller */
+   COMPAT_ALTERA_SOCFPGA_CLK,  /* SoCFPGA Clock initialization */
+   COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,   /* pinctrl-single */
+   COMPAT_ALTERA_SOCFPGA_H2F_BRG,  /* Arria10 hps2fpga bridge */
+   COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,/* Arria10 lwhps2fpga bridge */
+   COMPAT_ALTERA_SOCFPGA_F2H_BRG,  /* Arria10 fpga2hps bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR0,   /* Arria10 fpga2SDRAM0 bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR1,   /* Arria10 fpga2SDRAM1 bridge */
+   COMPAT_ALTERA_SOCFPGA_F2SDR2,   /* Arria10 fpga2SDRAM2 bridge */
 
COMPAT_COUNT,
 };
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 81f47ef..ebe4a9a 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -66,6 +66,14 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
+   COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
+   COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
+   COMPAT(ALTERA_SOCFPGA_H2F_BRG, "altr,socfpga-hps2fpga-bridge"),
+   COMPAT(ALTERA_SOCFPGA_LWH2F_BRG, "altr,socfpga-lwhps2fpga-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2H_BRG, "altr,socfpga-fpga2hps-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
+   COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
-- 
2.2.2

___
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U-Boot@lists.denx.de
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[U-Boot] [PATCH v2 24/30] arm: socfpga: arria10: Added support for Arria 10 socdk

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V2
- Separate patch, reuse socfpga_common.h
---
 arch/arm/mach-socfpga/system_manager.c  |  4 ++-
 drivers/fpga/socfpga.c  |  7 +++--
 include/configs/socfpga_arria10_socdk.h | 56 -
 include/configs/socfpga_common.h| 33 ---
 4 files changed, 71 insertions(+), 29 deletions(-)

diff --git a/arch/arm/mach-socfpga/system_manager.c 
b/arch/arm/mach-socfpga/system_manager.c
index 9e1c3fd..e1f0082 100644
--- a/arch/arm/mach-socfpga/system_manager.c
+++ b/arch/arm/mach-socfpga/system_manager.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013 Altera Corporation 
+ * Copyright (C) 2013-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -11,8 +11,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 /*
  * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index bfefafd..7fd922e 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 Altera Corporation 
+ * Copyright (C) 2012-2016 Altera Corporation 
  * All rights reserved.
  *
  * SPDX-License-Identifier:BSD-3-Clause
@@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static struct socfpga_fpga_manager *fpgamgr_regs =
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 /* Set CD ratio */
 static void fpgamgr_set_cd_ratio(unsigned long ratio)
@@ -267,9 +269,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
}
 
/* Prior programming the FPGA, all bridges need to be shut off */
-
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* Disable all signals from hps peripheral controller to fpga */
writel(0, _regs->fpgaintfgrp_module);
+#endif
 
/* Disable all signals from FPGA to HPS SDRAM */
 #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS0x5080
diff --git a/include/configs/socfpga_arria10_socdk.h 
b/include/configs/socfpga_arria10_socdk.h
index 577f60f..105c4c0 100644
--- a/include/configs/socfpga_arria10_socdk.h
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2015 Altera Corporation 
+ *  Copyright (C) 2015-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0
  */
@@ -8,31 +8,20 @@
 #define __CONFIG_SOCFGPA_ARRIA10_H__
 
 #include 
+
 /* U-Boot Commands */
-#define CONFIG_SYS_NO_FLASH
 #define CONFIG_DOS_PARTITION
 #define CONFIG_FAT_WRITE
 #define CONFIG_HW_WATCHDOG
 
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_PING
 
-/*
- * Memory configurations
- */
-#define PHYS_SDRAM_1_SIZE  0x200
-
 /* Booting Linux */
-#define CONFIG_BOOTDELAY   3
 #define CONFIG_BOOTFILE"zImage"
 #define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
 #define CONFIG_BOOTCOMMAND  "run mmcload; run mmcboot"
@@ -40,24 +29,30 @@
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
 /*
- * Display CPU and Board Info
+ * U-Boot general configurations
+ */
+/* Cache options */
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+
+/*
+ * U-Boot console configurations
  */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_DOS_PARTITION
+
+/* Memory configurations  */
+#define PHYS_SDRAM_1_SIZE  0x8000
 
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)
-
-/* PHY */
 #define CONFIG_PHY_MICREL
 #define CONFIG_PHY_MICREL_KSZ9031
-
 #endif
 
+/*
+ * U-Boot environment configurations
+ */
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */
-#define CONFIG_ENV_OFFSET  512/* just after the MBR */
 
 /*
  * arguments passed to the bootz command. The value of
@@ -89,6 +84,23 @@
" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
"bootm ${loadaddr} - ${fdt_addr}\0"
 
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* reload value when timer count to zero */

[U-Boot] [PATCH v2 21/30] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

[Chee Tien Fong]

From: Tien Fong Chee 

Enhanced defconfig file for Arria10 to enable SPL build and supporting
device tree build for SDMMC.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V2
- Removed boot header info setup since it already fixed in mainline
---
 configs/socfpga_arria10_defconfig | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/configs/socfpga_arria10_defconfig 
b/configs/socfpga_arria10_defconfig
index 422261b..755bb66 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -3,14 +3,22 @@ CONFIG_ARCH_SOCFPGA=y
 CONFIG_TARGET_SOCFPGA_ARRIA10=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk"
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
+CONFIG_IDENT_STRING="socfpga_arria10"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_DWAPB_GPIO=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_DESIGNWARE_SPI=y
 CONFIG_DM_MMC=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_CMD_MMC=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
-- 
2.2.2

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[U-Boot] [PATCH v2 20/30] arm: socfpga: arria10: Enable SPL for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

This patch enables SPL build and implementation for Arria 10.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V2
- Commit messages changed.
---
 arch/arm/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 74b769f..d871a45 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -554,9 +554,9 @@ config ARCH_SNAPDRAGON
 config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select CPU_V7
-   select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
+   select SUPPORT_SPL
select OF_CONTROL
-   select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
+   select SPL_OF_CONTROL
select DM
select DM_SPI_FLASH
select DM_SPI
-- 
2.2.2

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[U-Boot] [PATCH v2 23/30] arm: socfpga: arria10: Added some hardware base address for Arria 10

[Chee Tien Fong]

From: Tien Fong Chee 

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
changes for v2
- Separate patch for adding some HW base address for Arria 10.
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index 902c321..2d66580 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Altera Corporation 
+ * Copyright (C) 2014-2016 Altera Corporation 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -36,10 +36,13 @@
 #define SOCFPGA_ECC_OCRAM_ADDRESS  0xff8c3000
 #define SOCFPGA_UART0_ADDRESS  0xffc02000
 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0
+#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100
 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
 
 #define SOCFPGA_SDR_ADDRESS0xffcfb000
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST   0xffd11000
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST0xffd13500
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS  0xffd12400
 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200
 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS  0xffd13300
-- 
2.2.2

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[U-Boot] [PATCH v2 19/30] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc

[Chee Tien Fong]

From: Tien Fong Chee 

This is initial version of device tree for the Intel socfpga arria10
development kit with sdmmc.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
Changes for V2
- modified the handoff.dtsi to board specific, and moving some chosen
  config to handoff.dtsi because these config would be generated by tool
---
 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/socfpga_arria10.dtsi  | 859 +
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts   |  30 +
 .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi   | 479 
 4 files changed, 1370 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/socfpga_arria10.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3ee608b..024aa5f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -137,7 +137,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=   
\
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb   \
socfpga_cyclone5_sr1500.dtb \
-   socfpga_cyclone5_vining_fpga.dtb
+   socfpga_cyclone5_vining_fpga.dtb\
+   socfpga_arria10_socdk_sdmmc.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \
dra72-evm-revc.dtb dra71-evm.dtb
diff --git a/arch/arm/dts/socfpga_arria10.dtsi 
b/arch/arm/dts/socfpga_arria10.dtsi
new file mode 100644
index 000..f63c4b4
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -0,0 +1,859 @@
+/*
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include "skeleton.dtsi"
+#include 
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   aliases {
+   ethernet0 = 
+   ethernet1 = 
+   ethernet2 = 
+   serial0 = 
+   serial1 = 
+   timer0 = 
+   timer1 = 
+   timer2 = 
+   timer3 = 
+   spi0 = 
+   spi1 = 
+   };
+
+   memory {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x4000>; /* 1GB */
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0>;
+   next-level-cache = <>;
+   };
+   cpu@1 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <1>;
+   next-level-cache = <>;
+   };
+   };
+
+   intc: intc@d000 {
+   compatible = "arm,cortex-a9-gic";
+   #interrupt-cells = <3>;
+   interrupt-controller;
+   reg = <0xd000 0x1000>,
+ <0xc100 0x100>;
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "simple-bus";
+   device_type = "soc";
+   interrupt-parent = <>;
+   ranges;
+
+   amba {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   pdma: pdma@ffda1000 {
+   compatible = "arm,pl330", "arm,primecell";
+   reg = <0xffda1000 0x1000>;
+   interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
+<0 84 IRQ_TYPE_LEVEL_HIGH>,
+<0 85 IRQ_TYPE_LEVEL_HIGH>,
+<0 86 IRQ_TYPE_LEVEL_HIGH>,
+<0 87 IRQ_TYPE_LEVEL_HIGH>,
+<0 88 IRQ_TYPE_LEVEL_HIGH>,
+<0 89 IRQ_TYPE_LEVEL_HIGH>,
+<0 90 IRQ_TYPE_LEVEL_HIGH>,
+<0 91 IRQ_TYPE_LEVEL_HIGH>;
+   #dma-cells = <1>;
+   #dma-channels = <8>;
+   #dma-requests = <32>;
+   clocks = <_main_clk>;
+   clock-names = "apb_pclk";
+   };
+   };
+
+   

[U-Boot] [PATCH v2 18/30] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

[Chee Tien Fong]

From: Chin Liang See 

Add base address header file for Stratix10 SoC

Signed-off-by: Chin Liang See 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Ley Foon Tan 
---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 48 ++
 1 file changed, 48 insertions(+)
 create mode 100755 arch/arm/mach-socfpga/include/mach/base_addr_s10.h

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
new file mode 100755
index 000..411518d
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SMMU_ADDRESS   0xfa00
+#define SOCFPGA_EMAC0_ADDRESS  0xff80
+#define SOCFPGA_EMAC1_ADDRESS  0xff802000
+#define SOCFPGA_EMAC2_ADDRESS  0xff804000
+#define SOCFPGA_SDMMC_ADDRESS  0xff808000
+#define SOCFPGA_USB0_ADDRESS   0xffb0
+#define SOCFPGA_USB1_ADDRESS   0xffb4
+#define SOCFPGA_NANDREGS_ADDRESS   0xffb8
+#define SOCFPGA_NANDDATA_ADDRESS   0xffb9
+#define SOCFPGA_UART0_ADDRESS  0xffc02000
+#define SOCFPGA_UART1_ADDRESS  0xffc02100
+#define SOCFPGA_I2C0_ADDRESS   0xffc02800
+#define SOCFPGA_I2C1_ADDRESS   0xffc02900
+#define SOCFPGA_I2C2_ADDRESS   0xffc02a00
+#define SOCFPGA_I2C3_ADDRESS   0xffc02b00
+#define SOCFPGA_I2C4_ADDRESS   0xffc02c00
+#define SOCFPGA_SPTIMER0_ADDRESS   0xffc03000
+#define SOCFPGA_SPTIMER1_ADDRESS   0xffc03100
+#define SOCFPGA_GPIO0_ADDRESS  0xffc03200
+#define SOCFPGA_GPIO1_ADDRESS  0xffc03300
+#define SOCFPGA_SYSTIMER0_ADDRESS  0xffd0
+#define SOCFPGA_SYSTIMER0_ADDRESS  0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00200
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00300
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00400
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00500
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd1
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS0xffd13000
+#define SOCFPGA_DMANONSECURE_ADDRESS   0xffda
+#define SOCFPGA_DMASECURE_ADDRESS  0xffda1000
+#define SOCFPGA_SPIS0_ADDRESS  0xffda2000
+#define SOCFPGA_SPIS1_ADDRESS  0xffda3000
+#define SOCFPGA_SPIM0_ADDRESS  0xffda4000
+#define SOCFPGA_SPIM1_ADDRESS  0xffda5000
+#define SOCFPGA_OCRAM_ADDRESS  0xffe0
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
-- 
2.2.2

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[U-Boot] [PATCH v2 17/30] arm: socfpga: arria10: update dwmac reset function to support Arria10

[Chee Tien Fong]

From: Dinh Nguyen 

On the Arria10, the EMAC phy mode configuration for each EMACs is located
in separate registers versus being in 1 register for the GEN5 devices. The
Arria10 also has 3 EMACs compared to 2 for the GEN5 devices.

Update the dwmac_deassert_reset function to support both GEN5 and Arria10
devices.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/include/mach/system_manager.h |  4 +---
 arch/arm/mach-socfpga/misc.c| 14 ++
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 9ca889a..831ba4a 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -133,9 +133,7 @@ struct socfpga_system_manager {
u32  usb0_l3master;
u32  usb1_l3master;
u32  emac_global;
-   u32  emac0;
-   u32  emac1;
-   u32  emac2;
+   u32  emac[3];
u32  _pad_0x50_0x5f[4];
u32  fpgaintf_en_global;
u32  fpgaintf_en_0;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index c97caea..510aa1d 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -21,7 +21,11 @@
 #include 
 #include 
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
+#else
+#include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -95,15 +99,25 @@ static void dwmac_deassert_reset(const unsigned int 
of_reset_id,
} else if (of_reset_id == EMAC1_RESET) {
physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
reset = SOCFPGA_RESET(EMAC1);
+#ifndef CONFIG_TARGET_SOCFPGA_GEN5
+   } else if (of_reset_id == EMAC2_RESET) {
+   reset = SOCFPGA_RESET(EMAC2);
+#endif
} else {
printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
return;
}
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* configure to PHY interface select choosed */
clrsetbits_le32(_regs->emacgrp_ctrl,
SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
phymode << physhift);
+#else
+   clrsetbits_le32(_regs->emac[of_reset_id - EMAC0_RESET],
+   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
+   phymode);
+#endif
 
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
-- 
2.2.2

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[U-Boot] [PATCH v2 16/30] arm: socfpga: add reset manager defines for Arria10

[Chee Tien Fong]

From: Dinh Nguyen 

Add the Arria10 reset manager defines that is used in Linux. Change the
license to SPDX.

[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]

Signed-off-by: Dinh Nguyen 
---
 include/dt-bindings/reset/altr,rst-mgr-a10.h | 103 +++
 1 file changed, 103 insertions(+)
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h

diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h 
b/include/dt-bindings/reset/altr,rst-mgr-a10.h
new file mode 100644
index 000..7619ca2
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-a10.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Steffen Trumtrar 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+
+/* MPUMODRST */
+#define CPU0_RESET 0
+#define CPU1_RESET 1
+#define WDS_RESET  2
+#define SCUPER_RESET   3
+
+/* PER0MODRST */
+#define EMAC0_RESET32
+#define EMAC1_RESET33
+#define EMAC2_RESET34
+#define USB0_RESET 35
+#define USB1_RESET 36
+#define NAND_RESET 37
+#define QSPI_RESET 38
+#define SDMMC_RESET39
+#define EMAC0_OCP_RESET40
+#define EMAC1_OCP_RESET41
+#define EMAC2_OCP_RESET42
+#define USB0_OCP_RESET 43
+#define USB1_OCP_RESET 44
+#define NAND_OCP_RESET 45
+#define QSPI_OCP_RESET 46
+#define SDMMC_OCP_RESET47
+#define DMA_RESET  48
+#define SPIM0_RESET49
+#define SPIM1_RESET50
+#define SPIS0_RESET51
+#define SPIS1_RESET52
+#define DMA_OCP_RESET  53
+#define EMAC_PTP_RESET 54
+/* 55 is empty*/
+#define DMAIF0_RESET   56
+#define DMAIF1_RESET   57
+#define DMAIF2_RESET   58
+#define DMAIF3_RESET   59
+#define DMAIF4_RESET   60
+#define DMAIF5_RESET   61
+#define DMAIF6_RESET   62
+#define DMAIF7_RESET   63
+
+/* PER1MODRST */
+#define L4WD0_RESET64
+#define L4WD1_RESET65
+#define L4SYSTIMER0_RESET  66
+#define L4SYSTIMER1_RESET  67
+#define SPTIMER0_RESET 68
+#define SPTIMER1_RESET 69
+/* 70-71 is reserved */
+#define I2C0_RESET 72
+#define I2C1_RESET 73
+#define I2C2_RESET 74
+#define I2C3_RESET 75
+#define I2C4_RESET 76
+/* 77-79 is reserved */
+#define UART0_RESET80
+#define UART1_RESET81
+/* 82-87 is reserved */
+#define GPIO0_RESET88
+#define GPIO1_RESET89
+#define GPIO2_RESET90
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET 96
+#define LWHPS2FPGA_RESET   97
+#define FPGA2HPS_RESET 98
+#define F2SSDRAM0_RESET99
+#define F2SSDRAM1_RESET100
+#define F2SSDRAM2_RESET101
+#define DDRSCH_RESET   102
+
+/* SYSMODRST*/
+#define ROM_RESET  128
+#define OCRAM_RESET129
+/* 130 is reserved */
+#define FPGAMGR_RESET  131
+#define S2F_RESET  132
+#define SYSDBG_RESET   133
+#define OCRAM_OCP_RESET134
+
+/* COLDMODRST */
+#define CLKMGRCOLD_RESET   160
+/* 161-162 is reserved */
+#define S2FCOLD_RESET  163
+#define TIMESTAMPCOLD_RESET164
+#define TAPCOLD_RESET  165
+#define HMCCOLD_RESET  166
+#define IOMGRCOLD_RESET167
+
+/* NRSTMODRST */
+#define NRSTPINOE_RESET192
+
+/* DBGMODRST */
+#define DBG_RESET  224
+#endif
-- 
2.2.2

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[U-Boot] [PATCH v2 15/30] arm: socfpga: combine clrbits/setbits into a single clrsetbits

[Chee Tien Fong]

From: Dinh Nguyen 

There is no dependency on doing a separate clrbits first in the
dwmac_deassert_reset function. Combine them into a single
clrsetbits call.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/misc.c | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 2645129..c97caea 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -100,13 +100,10 @@ static void dwmac_deassert_reset(const unsigned int 
of_reset_id,
return;
}
 
-   /* Clearing emac0 PHY interface select to 0 */
-   clrbits_le32(_regs->emacgrp_ctrl,
-SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
-
/* configure to PHY interface select choosed */
-   setbits_le32(_regs->emacgrp_ctrl,
-phymode << physhift);
+   clrsetbits_le32(_regs->emacgrp_ctrl,
+   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
+   phymode << physhift);
 
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
-- 
2.2.2

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[U-Boot] [PATCH v2 11/30] arm: socfpga: wrap system manager functions for A5/C5 devices

[Chee Tien Fong]

From: Dinh Nguyen 

The system manager on Arria10 is not used for pin muxing duties, so wrap
these functions for GEN5 devices only.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/system_manager.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-socfpga/system_manager.c 
b/arch/arm/mach-socfpga/system_manager.c
index 75a65f3..9e1c3fd 100644
--- a/arch/arm/mach-socfpga/system_manager.c
+++ b/arch/arm/mach-socfpga/system_manager.c
@@ -19,6 +19,7 @@ static struct socfpga_system_manager *sysmgr_regs =
  * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
  * CONFIG_SYSMGR_ISWGRP_HANDOFF.
  */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void populate_sysmgr_fpgaintf_module(void)
 {
uint32_t handoff_val = 0;
@@ -83,3 +84,4 @@ void sysmgr_config_warmrstcfgio(int enable)
clrbits_le32(_regs->romcodegrp_ctrl,
 SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
 }
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
-- 
2.2.2

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[U-Boot] [PATCH v2 14/30] arm: socfpga: arria10: remove board_init and s_init

[Chee Tien Fong]

From: Dinh Nguyen 

These functions are already in arch/arm/mach-socfpga/board.c

Signed-off-by: Dinh Nguyen 
---
 board/altera/arria10-socdk/socfpga.c | 17 -
 1 file changed, 17 deletions(-)

diff --git a/board/altera/arria10-socdk/socfpga.c 
b/board/altera/arria10-socdk/socfpga.c
index abedc22..8516633 100644
--- a/board/altera/arria10-socdk/socfpga.c
+++ b/board/altera/arria10-socdk/socfpga.c
@@ -5,20 +5,3 @@
  */
 
 #include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void)
-{
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
-   /* Address of boot parameters for ATAG (if ATAG is used) */
-   gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-   return 0;
-}
-- 
2.2.2

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[U-Boot] [PATCH v2 13/30] arm: socfpga: arria10 fpga does not have bridges mapped

[Chee Tien Fong]

From: Dinh Nguyen 

On the Arria10 device, the bridges are not mapped through the interconnect.

Signed-off-by: Dinh Nguyen 
---
 drivers/fpga/socfpga.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index f1b2f2c..bfefafd 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -278,8 +278,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
socfpga_bridges_reset(1);
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* Unmap the bridges from NIC-301 */
writel(0x1, SOCFPGA_L3REGS_ADDRESS);
+#endif
 
/* Initialize the FPGA Manager */
status = fpgamgr_program_init();
-- 
2.2.2

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[U-Boot] [PATCH v2 12/30] arm: socfpga: arria10: don't build GEN5 sdram for arria10

[Chee Tien Fong]

From: Dinh Nguyen 

The Arria10 device will not be able to re-use the GEN5 SDRAM controller,
so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig
option in drivers/ddr/altera/Kconfig.

Signed-off-by: Dinh Nguyen 
---
 drivers/Kconfig  | 2 ++
 drivers/ddr/Kconfig  | 1 +
 drivers/ddr/altera/Kconfig   | 6 ++
 include/configs/socfpga_common.h | 5 -
 4 files changed, 9 insertions(+), 5 deletions(-)
 create mode 100644 drivers/ddr/Kconfig
 create mode 100644 drivers/ddr/altera/Kconfig

diff --git a/drivers/Kconfig b/drivers/Kconfig
index e8c9e0a..0178498 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/cpu/Kconfig"
 
 source "drivers/crypto/Kconfig"
 
+source "drivers/ddr/Kconfig"
+
 source "drivers/demo/Kconfig"
 
 source "drivers/dfu/Kconfig"
diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig
new file mode 100644
index 000..b764add
--- /dev/null
+++ b/drivers/ddr/Kconfig
@@ -0,0 +1 @@
+source "drivers/ddr/altera/Kconfig"
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
new file mode 100644
index 000..9554da7
--- /dev/null
+++ b/drivers/ddr/altera/Kconfig
@@ -0,0 +1,6 @@
+config ALTERA_SDRAM
+   bool "SoCFPGA SDRAM for Arria5/Cyclone5 devices"
+   default y if TARGET_SOCFPGA_GEN5
+   help
+ This is for building the SDRAM controller for the Arria5/Cyclone5
+ devices.
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 58a6550..f6a2f8d 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -77,11 +77,6 @@
 #define CONFIG_SYS_PL310_BASE  SOCFPGA_MPUL2_ADDRESS
 
 /*
- * SDRAM controller
- */
-#define CONFIG_ALTERA_SDRAM
-
-/*
  * EPCS/EPCQx1 Serial Flash Controller
  */
 #ifdef CONFIG_ALTERA_SPI
-- 
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[U-Boot] [PATCH v2 10/30] arm: socfpga: arria10: add reset manager for Arria10

[Chee Tien Fong]

From: Dinh Nguyen 

Add the defines for the reset manager and some basic reset functionality.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/include/mach/reset_manager.h | 65 ++
 arch/arm/mach-socfpga/reset_manager.c  | 24 +++-
 2 files changed, 88 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 2f070f2..6225118 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -15,6 +15,7 @@ void socfpga_bridges_reset(int enable);
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -28,6 +29,42 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
 };
+#else
+struct socfpga_reset_manager {
+   u32 stat;
+   u32 ramstat;
+   u32 miscstat;
+   u32 ctrl;
+   u32 hdsken;
+   u32 hdskreq;
+   u32 hdskack;
+   u32 counts;
+   u32 mpu_mod_reset;
+   u32 per_mod_reset;  /* stated as per0_mod_reset in A10 datasheet */
+   u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */
+   u32 brg_mod_reset;
+   u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */
+   u32 coldmodrst;
+   u32 nrstmodrst;
+   u32 dbgmodrst;
+   u32 mpuwarmmask;
+   u32 per0warmmask;
+   u32 per1warmmask;
+   u32 brgwarmmask;
+   u32 syswarmmask;
+   u32 nrstwarmmask;
+   u32 l3warmmask;
+   u32 tststa;
+   u32 tstscratch;
+   u32 hdsktimeout;
+   u32 hmcintr;
+   u32 hmcintren;
+   u32 hmcintrens;
+   u32 hmcintrenr;
+   u32 hmcgpout;
+   u32 hmcgpin;
+};
+#endif
 
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
@@ -55,6 +92,7 @@ struct socfpga_reset_manager {
 #define RSTMGR_BANK(_reset)\
(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 /*
  * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
  * 0 ... mpumodrst
@@ -75,6 +113,33 @@ struct socfpga_reset_manager {
 #define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 22)
 #define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
 #define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
+#else
+/*
+ * SocFPGA Arria10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ * 4 ... sysmodrst
+ */
+#define RSTMGR_EMAC0   RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1   RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2   RSTMGR_DEFINE(1, 2)
+#define RSTMGR_L4WD0   RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1   RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
+#define RSTMGR_SPTIMER0RSTMGR_DEFINE(2, 4)
+#define RSTMGR_SPTIMER1RSTMGR_DEFINE(2, 5)
+#define RSTMGR_UART0   RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1   RSTMGR_DEFINE(2, 17)
+#define RSTMGR_SPIM0   RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1   RSTMGR_DEFINE(1, 18)
+#define RSTMGR_QSPIRSTMGR_DEFINE(1, 6)
+#define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 7)
+#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
+#define RSTMGR_DDRSCH  RSTMGR_DEFINE(3, 6)
+#endif
 
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)   RSTMGR_##_name
diff --git a/arch/arm/mach-socfpga/reset_manager.c 
b/arch/arm/mach-socfpga/reset_manager.c
index b6beaa2..d0ff6c4 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -18,7 +18,9 @@ static const struct socfpga_reset_manager *reset_manager_base 
=
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
-/* Assert or de-assert SoCFPGA reset manager reset. */
+/*
+ * Assert or de-assert SoCFPGA reset manager reset.
+ */
 void socfpga_per_reset(u32 reset, int set)
 {
const void *reg;
@@ -46,13 +48,29 @@ void socfpga_per_reset(u32 reset, int set)
  * Assert reset on every peripheral but L4WD0.
  * Watchdog must be kept intact to prevent glitches
  * and/or hangs.
+ * For the Arria10, we disable all the peripherals except L4 watchdog0,
+ * L4 Timer 0, and ECC.
  */
 void socfpga_per_reset_all(void)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
 
writel(~l4wd0, _manager_base->per_mod_reset);

[U-Boot] [PATCH v2 08/30] arm: socfpga: arria10: add config option build for arria10

[Chee Tien Fong]

From: Dinh Nguyen 

Signed-off-by: Dinh Nguyen 
---
 arch/arm/Kconfig  |  4 ++--
 arch/arm/mach-socfpga/Kconfig | 10 ++
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d871a45..74b769f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -554,9 +554,9 @@ config ARCH_SNAPDRAGON
 config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select CPU_V7
-   select SUPPORT_SPL
+   select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
select OF_CONTROL
-   select SPL_OF_CONTROL
+   select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
select DM
select DM_SPI_FLASH
select DM_SPI
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 6991af8..d9a5178 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -31,6 +31,9 @@ config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
 
+config TARGET_SOCFPGA_ARRIA10
+   bool
+
 config TARGET_SOCFPGA_CYCLONE5
bool
select TARGET_SOCFPGA_GEN5
@@ -50,6 +53,10 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_ARRIA10_SOCDK
+   bool "Altera SOCFPGA SoCDK (Arria 10)"
+   select TARGET_SOCFPGA_ARRIA10
+
 config TARGET_SOCFPGA_DENX_MCVEVK
bool "DENX MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -86,6 +93,7 @@ endchoice
 
 config SYS_BOARD
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
@@ -98,6 +106,7 @@ config SYS_BOARD
 
 config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -111,6 +120,7 @@ config SYS_SOC
 
 config SYS_CONFIG_NAME
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
-- 
2.2.2

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[U-Boot] [PATCH v2 09/30] arm: socfpga: add define for bootinfo bsel bit shift

[Chee Tien Fong]

From: Dinh Nguyen 

On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10,
the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that
the reading the bsel can generic.

Suggested-by: Marek Vasut 
Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/include/mach/system_manager.h | 2 ++
 arch/arm/mach-socfpga/misc.c| 4 ++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index e688c50..9ca889a 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -203,8 +203,10 @@ struct socfpga_system_manager {
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define SYSMGR_SDMMC_SMPLSEL_SHIFT 3
+#define SYSMGR_BOOTINFO_BSEL_SHIFT 0
 #else
 #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
+#define SYSMGR_BOOTINFO_BSEL_SHIFT 12
 #endif
 
 #define SYSMGR_SDMMC_DRVSEL_SHIFT  0
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index c1e5969..2645129 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -261,12 +261,12 @@ static int socfpga_fpga_id(const bool print_id)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
+   const u32 bsel = (readl(_regs->bootinfo) >>
+ SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7;
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-   const u32 bsel = readl(_regs->bootinfo) & 0x7;
puts("CPU:   Altera SoCFPGA Platform\n");
socfpga_fpga_id(1);
 #else
-   const u32 bsel = (readl(_regs->bootinfo) >> 12) & 0x7;
puts("CPU:   Altera SoCFPGA Arria 10\n");
 #endif
printf("BOOT:  %s\n", bsel_str[bsel].name);
-- 
2.2.2

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[U-Boot] [PATCH v2 06/30] arm: socfpga: arria10: add socfpga_arria10_socdk config

[Chee Tien Fong]

From: Dinh Nguyen 

Add config for the Arria10 SoC Development Kit.

Signed-off-by: Dinh Nguyen 
Acked-by: Marek Vasut 
---
 include/configs/socfpga_arria10_socdk.h | 94 +
 1 file changed, 94 insertions(+)
 create mode 100644 include/configs/socfpga_arria10_socdk.h

diff --git a/include/configs/socfpga_arria10_socdk.h 
b/include/configs/socfpga_arria10_socdk.h
new file mode 100644
index 000..577f60f
--- /dev/null
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -0,0 +1,94 @@
+/*
+ *  Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
+#define __CONFIG_SOCFGPA_ARRIA10_H__
+
+#include 
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+
+/*
+ * Memory configurations
+ */
+#define PHYS_SDRAM_1_SIZE  0x200
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY   3
+#define CONFIG_BOOTFILE"zImage"
+#define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND  "run mmcload; run mmcboot"
+#define CONFIG_LOADADDR0x0100
+#define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
+
+/*
+ * Display CPU and Board Info
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+
+#endif
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */
+#define CONFIG_ENV_OFFSET  512/* just after the MBR */
+
+/*
+ * arguments passed to the bootz command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+   "verify=n\0" \
+   "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+   "bootm ${loadaddr} - ${fdt_addr}\0" \
+   "bootimage=zImage\0" \
+   "fdt_addr=100\0" \
+   "fdtimage=socfpga.dtb\0" \
+   "fsloadcmd=ext2load\0" \
+   "bootm ${loadaddr} - ${fdt_addr}\0" \
+   "mmcroot=/dev/mmcblk0p2\0" \
+   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+   " root=${mmcroot} rw rootwait;" \
+   "bootz ${loadaddr} - ${fdt_addr}\0" \
+   "mmcload=mmc rescan;" \
+   "load mmc 0:1 ${loadaddr} ${bootimage};" \
+   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+   "qspiroot=/dev/mtdblock0\0" \
+   "qspirootfstype=jffs2\0" \
+   "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+   " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+   "bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* The rest of the configuration is shared */
+#include 
+#endif /* __CONFIG_H */
-- 
2.2.2

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[U-Boot] [PATCH v2 07/30] arm: socfpga: arria10: add socfpga_arria10_defconfig

[Chee Tien Fong]

From: Dinh Nguyen 

Add a defconfig file for Arria10, which does not include enabling SPL.

Signed-off-by: Dinh Nguyen 
Acked-by: Marek Vasut 
---
 configs/socfpga_arria10_defconfig | 16 
 1 file changed, 16 insertions(+)
 create mode 100644 configs/socfpga_arria10_defconfig

diff --git a/configs/socfpga_arria10_defconfig 
b/configs/socfpga_arria10_defconfig
new file mode 100644
index 000..422261b
--- /dev/null
+++ b/configs/socfpga_arria10_defconfig
@@ -0,0 +1,16 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_ARRIA10=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DM_MMC=y
-- 
2.2.2

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[U-Boot] [PATCH v2 03/30] arm: socfpga: arria10: add board files for the Arria10 SoCDK

[Chee Tien Fong]

From: Dinh Nguyen 

Add minimal support for the Arria10 SoCDK.

Signed-off-by: Dinh Nguyen 
---
 board/altera/arria10-socdk/Kconfig   | 18 ++
 board/altera/arria10-socdk/Makefile  |  7 +++
 board/altera/arria10-socdk/socfpga.c | 24 
 3 files changed, 49 insertions(+)
 create mode 100644 board/altera/arria10-socdk/Kconfig
 create mode 100644 board/altera/arria10-socdk/Makefile
 create mode 100644 board/altera/arria10-socdk/socfpga.c

diff --git a/board/altera/arria10-socdk/Kconfig 
b/board/altera/arria10-socdk/Kconfig
new file mode 100644
index 000..b80cc6d
--- /dev/null
+++ b/board/altera/arria10-socdk/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_SOCFPGA_ARRIA10
+
+config SYS_CPU
+   default "armv7"
+
+config SYS_BOARD
+   default "socfpga_arria10"
+
+config SYS_VENDOR
+   default "altera"
+
+config SYS_SOC
+   default "socfpga_arria10"
+
+config SYS_CONFIG_NAME
+   default "socfpga_arria10"
+
+endif
diff --git a/board/altera/arria10-socdk/Makefile 
b/board/altera/arria10-socdk/Makefile
new file mode 100644
index 000..1d885ce
--- /dev/null
+++ b/board/altera/arria10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Altera Corporation 
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y  := socfpga.o
diff --git a/board/altera/arria10-socdk/socfpga.c 
b/board/altera/arria10-socdk/socfpga.c
new file mode 100644
index 000..abedc22
--- /dev/null
+++ b/board/altera/arria10-socdk/socfpga.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void)
+{
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+   /* Address of boot parameters for ATAG (if ATAG is used) */
+   gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+   return 0;
+}
-- 
2.2.2

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[U-Boot] [PATCH v2 05/30] arm: socfpga: arria10: add misc functions for Arria10

[Chee Tien Fong]

From: Dinh Nguyen 

Add arch_early_init_r function. The Arria10 has a firewall protection
around the SDRAM and OCRAM. These firewalls are to be disabled in order
for U-Boot to function.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/misc.c | 51 
 1 file changed, 51 insertions(+)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index dd6b53b..c1e5969 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -30,8 +31,15 @@ static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 static struct socfpga_reset_manager *reset_manager_base =
(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
+#else
+static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
+   (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
+static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
+   (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
+#endif
 static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 
@@ -253,9 +261,14 @@ static int socfpga_fpga_id(const bool print_id)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
const u32 bsel = readl(_regs->bootinfo) & 0x7;
puts("CPU:   Altera SoCFPGA Platform\n");
socfpga_fpga_id(1);
+#else
+   const u32 bsel = (readl(_regs->bootinfo) >> 12) & 0x7;
+   puts("CPU:   Altera SoCFPGA Arria 10\n");
+#endif
printf("BOOT:  %s\n", bsel_str[bsel].name);
return 0;
 }
@@ -338,6 +351,7 @@ int arch_cpu_init(void)
return 0;
 }
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 /*
  * Convert all NIC-301 AMBA slaves from secure to non-secure
  */
@@ -461,6 +475,43 @@ int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
 
return 0;
 }
+#else
+/*
++ * This function initializes security policies to be consistent across
++ * all logic units in the Arria 10.
++ *
++ * The idea is to set all security policies to be normal, nonsecure
++ * for all units.
++ */
+static void initialize_security_policies(void)
+{
+   /* Put OCRAM in non-secure */
+   writel(0x003f, _fw_ocram_base->region0);
+   writel(0x1, _fw_ocram_base->enable);
+
+   /* Put DDR in non-secure */
+   writel(0x, _fw_ddr_l3_base->hpsregion0addr);
+   writel(0x1, _fw_ddr_l3_base->enable);
+}
+
+int arch_early_init_r(void)
+{
+   initialize_security_policies();
+
+   /* Configure the L2 controller to make SDRAM start at 0 */
+   writel(0x1, >pl310_addr_filter_start);
+
+   /* assert reset to all except L4WD0 and L4TIMER0 */
+   socfpga_per_reset_all();
+
+   /* configuring the clock based on handoff */
+   /* TODO: Add call to cm_basic_init() */
+
+   /* Add device descriptor to FPGA device table */
+   socfpga_fpga_add();
+   return 0;
+}
+#endif
 
 U_BOOT_CMD(
bridge, 2, 1, do_bridge,
-- 
2.2.2

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[U-Boot] [PATCH v2 04/30] arm: socfpga: arria10: add system manager defines

[Chee Tien Fong]

From: Tien Fong Chee 

Add system manager defines for Arria10.

Signed-off-by: Dinh Nguyen 
---
 .../arm/mach-socfpga/include/mach/system_manager.h | 122 +
 1 file changed, 122 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index c45edea..e688c50 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -15,6 +15,7 @@ void sysmgr_config_warmrstcfgio(int enable);
 void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_system_manager {
/* System Manager Module */
u32 siliconid1; /* 0x00 */
@@ -115,6 +116,77 @@ struct socfpga_system_manager {
u32 _pad_0x734;
u32 spim0usefpga;   /* 0x738 */
 };
+#else /* Arria10 System Manager */
+struct socfpga_system_manager {
+   u32  siliconid1;
+   u32  siliconid2;
+   u32  wddbg;
+   u32  bootinfo;
+   u32  mpu_ctrl_l2_ecc;
+   u32  _pad_0x14_0x1f[3];
+   u32  dma;
+   u32  dma_periph;
+   u32  sdmmcgrp_ctrl;
+   u32  sdmmc_l3master;
+   u32  nand_bootstrap;
+   u32  nand_l3master;
+   u32  usb0_l3master;
+   u32  usb1_l3master;
+   u32  emac_global;
+   u32  emac0;
+   u32  emac1;
+   u32  emac2;
+   u32  _pad_0x50_0x5f[4];
+   u32  fpgaintf_en_global;
+   u32  fpgaintf_en_0;
+   u32  fpgaintf_en_1;
+   u32  fpgaintf_en_2;
+   u32  fpgaintf_en_3;
+   u32  _pad_0x74_0x7f[3];
+   u32  noc_addr_remap_value;
+   u32  noc_addr_remap_set;
+   u32  noc_addr_remap_clear;
+   u32  _pad_0x8c_0x8f;
+   u32  ecc_intmask_value;
+   u32  ecc_intmask_set;
+   u32  ecc_intmask_clr;
+   u32  ecc_intstatus_serr;
+   u32  ecc_intstatus_derr;
+   u32  mpu_status_l2_ecc;
+   u32  mpu_clear_l2_ecc;
+   u32  mpu_status_l1_parity;
+   u32  mpu_clear_l1_parity;
+   u32  mpu_set_l1_parity;
+   u32  _pad_0xb8_0xbf[2];
+   u32  noc_timeout;
+   u32  noc_idlereq_set;
+   u32  noc_idlereq_clr;
+   u32  noc_idlereq_value;
+   u32  noc_idleack;
+   u32  noc_idlestatus;
+   u32  fpga2soc_ctrl;
+   u32  _pad_0xdc_0xff[9];
+   u32  tsmc_tsel_0;
+   u32  tsmc_tsel_1;
+   u32  tsmc_tsel_2;
+   u32  tsmc_tsel_3;
+   u32  _pad_0x110_0x200[60];
+   u32  romhw_ctrl;
+   u32  romcode_ctrl;
+   u32  romcode_cpu1startaddr;
+   u32  romcode_initswstate;
+   u32  romcode_initswlastld;
+   u32  _pad_0x214_0x217;
+   u32  warmram_enable;
+   u32  warmram_datastart;
+   u32  warmram_length;
+   u32  warmram_execution;
+   u32  warmram_crc;
+   u32  _pad_0x22c_0x22f;
+   u32  isw_handoff[8];
+   u32  romcode_bootromswstate[8];
+};
+#endif
 
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX(1 << 0)
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO(1 << 1)
@@ -146,4 +218,54 @@ struct socfpga_system_manager {
 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB2
 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK0x3
 
+/* For dedicated IO configuration */
+/* Voltage select enums */
+#define VOLTAGE_SEL_3V 0x0
+#define VOLTAGE_SEL_1P8V   0x1
+#define VOLTAGE_SEL_2P5V   0x2
+
+/* Input buffer enable */
+#define INPUT_BUF_DISABLE  0
+#define INPUT_BUF_1P8V 1
+#define INPUT_BUF_2P5V3V   2
+
+/* Weak pull up enable */
+#define WK_PU_DISABLE  0
+#define WK_PU_ENABLE   1
+
+/* Pull up slew rate control */
+#define PU_SLW_RT_SLOW 0
+#define PU_SLW_RT_FAST 1
+#define PU_SLW_RT_DEFAULT  PU_SLW_RT_SLOW
+
+/* Pull down slew rate control */
+#define PD_SLW_RT_SLOW 0
+#define PD_SLW_RT_FAST 1
+#define PD_SLW_RT_DEFAULT  PD_SLW_RT_SLOW
+
+/* Drive strength control */
+#define PU_DRV_STRG_DEFAULT0x10
+#define PD_DRV_STRG_DEFAULT0x10
+
+/* bit position */
+#define PD_DRV_STRG_LSB0
+#define PD_SLW_RT_LSB  5
+#define PU_DRV_STRG_LSB8
+#define PU_SLW_RT_LSB  13
+#define WK_PU_LSB  16
+#define INPUT_BUF_LSB  17
+#define BIAS_TRIM_LSB  19
+#define VOLTAGE_SEL_LSB0
+
+#define ALT_SYSMGR_NOC_H2F_SET_MSK 0x0001
+#define ALT_SYSMGR_NOC_LWH2F_SET_MSK   0x0010
+#define ALT_SYSMGR_NOC_F2H_SET_MSK 0x0100
+#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK  0x0001
+#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK  0x0010
+#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK  0x0100
+#define ALT_SYSMGR_NOC_TMO_EN_SET_MSK  0x0001
+
+#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK  0x0002
+#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK  0x0002
+
 #endif /* 

[U-Boot] [PATCH v2 02/30] arm: socfpga: arria10: add sdram defines for Arria10

[Chee Tien Fong]

From: Dinh Nguyen 

Add the structures for the SDRAM controller on Arria10.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 +
 1 file changed, 380 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_a10.h

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_a10.h 
b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
new file mode 100644
index 000..0403531
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_SOCFPGA_SDRAM_A10_H_
+#define_SOCFPGA_SDRAM_A10_H_
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_ecc_hmc {
+   u32 ip_rev_id;
+   u32 _pad_0x4_0x7;
+   u32 ddrioctrl;
+   u32 ddrcalstat;
+   u32 mpr_0beat1;
+   u32 mpr_1beat1;
+   u32 mpr_2beat1;
+   u32 mpr_3beat1;
+   u32 mpr_4beat1;
+   u32 mpr_5beat1;
+   u32 mpr_6beat1;
+   u32 mpr_7beat1;
+   u32 mpr_8beat1;
+   u32 mpr_0beat2;
+   u32 mpr_1beat2;
+   u32 mpr_2beat2;
+   u32 mpr_3beat2;
+   u32 mpr_4beat2;
+   u32 mpr_5beat2;
+   u32 mpr_6beat2;
+   u32 mpr_7beat2;
+   u32 mpr_8beat2;
+   u32 _pad_0x58_0x5f[2];
+   u32 auto_precharge;
+   u32 _pad_0x64_0xff[39];
+   u32 eccctrl;
+   u32 eccctrl2;
+   u32 _pad_0x108_0x10f[2];
+   u32 errinten;
+   u32 errintens;
+   u32 errintenr;
+   u32 intmode;
+   u32 intstat;
+   u32 diaginttest;
+   u32 modstat;
+   u32 derraddra;
+   u32 serraddra;
+   u32 _pad_0x134_0x137;
+   u32 autowb_corraddr;
+   u32 serrcntreg;
+   u32 autowb_drop_cntreg;
+   u32 _pad_0x144_0x147;
+   u32 ecc_reg2wreccdatabus;
+   u32 ecc_rdeccdata2regbus;
+   u32 ecc_reg2rdeccdatabus;
+   u32 _pad_0x154_0x15f[3];
+   u32 ecc_diagon;
+   u32 ecc_decstat;
+   u32 _pad_0x168_0x16f[2];
+   u32 ecc_errgenaddr_0;
+   u32 ecc_errgenaddr_1;
+   u32 ecc_errgenaddr_2;
+   u32 ecc_errgenaddr_3;
+};
+
+struct socfpga_noc_ddr_scheduler {
+   u32 ddr_t_main_scheduler_id_coreid;
+   u32 ddr_t_main_scheduler_id_revisionid;
+   u32 ddr_t_main_scheduler_ddrconf;
+   u32 ddr_t_main_scheduler_ddrtiming;
+   u32 ddr_t_main_scheduler_ddrmode;
+   u32 ddr_t_main_scheduler_readlatency;
+   u32 _pad_0x20_0x34[8];
+   u32 ddr_t_main_scheduler_activate;
+   u32 ddr_t_main_scheduler_devtodev;
+};
+
+/*
+ * OCRAM firewall
+ */
+struct socfpga_noc_fw_ocram {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 region0;
+   u32 region1;
+   u32 region2;
+   u32 region3;
+   u32 region4;
+   u32 region5;
+};
+
+/* for master such as MPU and FPGA */
+struct socfpga_noc_fw_ddr_mpu_fpga2sdram {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 _pad_0xc_0xf;
+   u32 mpuregion0addr;
+   u32 mpuregion1addr;
+   u32 mpuregion2addr;
+   u32 mpuregion3addr;
+   u32 fpga2sdram0region0addr;
+   u32 fpga2sdram0region1addr;
+   u32 fpga2sdram0region2addr;
+   u32 fpga2sdram0region3addr;
+   u32 fpga2sdram1region0addr;
+   u32 fpga2sdram1region1addr;
+   u32 fpga2sdram1region2addr;
+   u32 fpga2sdram1region3addr;
+   u32 fpga2sdram2region0addr;
+   u32 fpga2sdram2region1addr;
+   u32 fpga2sdram2region2addr;
+   u32 fpga2sdram2region3addr;
+};
+
+/* for L3 master */
+struct socfpga_noc_fw_ddr_l3 {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 hpsregion0addr;
+   u32 hpsregion1addr;
+   u32 hpsregion2addr;
+   u32 hpsregion3addr;
+   u32 hpsregion4addr;
+   u32 hpsregion5addr;
+   u32 hpsregion6addr;
+   u32 hpsregion7addr;
+};
+
+struct socfpga_io48_mmr {
+   u32 dbgcfg0;
+   u32 dbgcfg1;
+   u32 dbgcfg2;
+   u32 dbgcfg3;
+   u32 dbgcfg4;
+   u32 dbgcfg5;
+   u32 dbgcfg6;
+   u32 reserve0;
+   u32 reserve1;
+   u32 reserve2;
+   u32 ctrlcfg0;
+   u32 ctrlcfg1;
+   u32 ctrlcfg2;
+   u32 ctrlcfg3;
+   u32 ctrlcfg4;
+   u32 ctrlcfg5;
+   u32 ctrlcfg6;
+   u32 ctrlcfg7;
+   u32 ctrlcfg8;
+   u32 ctrlcfg9;
+   u32 dramtiming0;
+   u32 dramodt0;
+   u32 dramodt1;
+   u32 sbcfg0;
+   u32 sbcfg1;
+   u32 sbcfg2;
+   u32 sbcfg3;
+   u32 sbcfg4;
+   u32 sbcfg5;
+   u32 sbcfg6;
+   u32 sbcfg7;
+   u32 caltiming0;
+   u32 caltiming1;
+   u32 caltiming2;
+   u32 caltiming3;
+   u32 caltiming4;
+   u32 caltiming5;
+   u32 caltiming6;
+   u32 caltiming7;
+   u32 caltiming8;
+   u32 caltiming9;
+   u32 caltiming10;
+   u32 dramaddrw;
+   u32 sideband0;
+   u32 sideband1;
+ 

[U-Boot] [PATCH v2 01/30] arm: socfpga: arria10: add additional i2c nodes for Arria10

[Chee Tien Fong]

From: Dinh Nguyen 

Add remaining 3 I2C base addresses for the Arria10.

Signed-off-by: Dinh Nguyen 
Reviewed-by: Stefan Roese 
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index a7056d4..902c321 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -29,6 +29,9 @@
 #define SOCFPGA_MPUL2_ADDRESS  0xf000
 #define SOCFPGA_I2C0_ADDRESS   0xffc02200
 #define SOCFPGA_I2C1_ADDRESS   0xffc02300
+#define SOCFPGA_I2C2_ADDRESS   0xffc02400
+#define SOCFPGA_I2C3_ADDRESS   0xffc02500
+#define SOCFPGA_I2C4_ADDRESS   0xffc02600
 
 #define SOCFPGA_ECC_OCRAM_ADDRESS  0xff8c3000
 #define SOCFPGA_UART0_ADDRESS  0xffc02000
-- 
2.2.2

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Re: [U-Boot] [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system initialization

[Z.Q. Hou]

Hi Prabhakar,

Thanks a lot for your comments!

> -Original Message-
> From: Prabhakar Kushwaha
> Sent: 2016年12月28日 12:06
> To: Z.Q. Hou ; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; york sun ; Mingkai Hu
> ; Calvin Johnson 
> Subject: RE: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system
> initialization
> 
> 
> > -Original Message-
> > From: Z.Q. Hou
> > Sent: Tuesday, December 27, 2016 3:58 PM
> > To: Prabhakar Kushwaha ; u-
> > b...@lists.denx.de; albert.u.b...@aribaud.net; york sun
> > ; Mingkai Hu ; Calvin Johnson
> > 
> > Subject: RE: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system
> > initialization
> >
> > Hi Prabhakar,
> >
> > Thanks a lot for your comments!
> >
> > > -Original Message-
> > > From: Prabhakar Kushwaha
> > > Sent: 2016年12月27日 16:59
> > > To: Z.Q. Hou ; u-boot@lists.denx.de;
> > > albert.u.b...@aribaud.net; york sun ; Mingkai Hu
> > > ; Calvin Johnson 
> > > Cc: Z.Q. Hou 
> > > Subject: RE: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock
> > > system initialization
> > >
> > >
> > > > -Original Message-
> > > > From: Zhiqiang Hou [mailto:zhiqiang@nxp.com]
> > > > Sent: Tuesday, December 27, 2016 1:06 PM
> > > > To: u-boot@lists.denx.de; albert.u.b...@aribaud.net; york sun
> > > > ; Mingkai Hu ; Prabhakar
> > > > Kushwaha ; Calvin Johnson
> > > > 
> > > > Cc: Z.Q. Hou 
> > > > Subject: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system
> > > > initialization
> > > >
> > > > From: Hou Zhiqiang 
> > > >
> > > > Up to now, there are 3 kind of SoCs under Layerscape Chassis 2,
> > > > like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot
> > > > of differences, for instance, the IP modules have different
> > > > dividers to derive its clock from Platform PLL. And the core
> > > > cluster PLL and platform PLL maybe have different reference clocks, such
> as LS1012A.
> > > > Another problem is which clock/PLL should be described by
> > > > sys_info->freq_systembus, it is confused in Layerscape Chissis 2.
> > > >
> > > > This patch is to bind the sys_info->freq_systembus to the Platform
> > > > PLL, and handle the different divider of IP modules separately
> > > > between different SoCs, and separate reference clocks of core
> > > > cluster PLL and platform PLL.
> > > >
> > > > Signed-off-by: Hou Zhiqiang 
> > > > ---
> > > > V3:
> > > >  - Generate the patch set base on the latest
> > > > git://git.denx.de/u-boot-fsl- qoriq.git.
> > > >  - Use the Kconfig instead of header file to add CONFIG_*
> > > >
> > > >  arch/arm/cpu/armv8/fsl-layerscape/Kconfig  | 76
> > > > ++
> > > >  arch/arm/cpu/armv8/fsl-layerscape/cpu.c|  3 +-
> > > >  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 68
> > > > ++-
> > > > ++.../include/asm/arch-fsl-layerscape/immap_lsch2.h
> > > |  1 +
> > > >  include/configs/ls1012a_common.h   |  6 +-
> > > >  include/configs/ls1043a_common.h   |  3 +-
> > > >  include/configs/ls1046a_common.h   |  3 +-
> > > >  include/configs/ls2080aqds.h   |  2 -
> > > >  include/configs/ls2080ardb.h   |  1 -
> > > >  9 files changed, 134 insertions(+), 29 deletions(-)
> > > >
> > > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > > > b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > > > index cc0dc88..de1e5a4 100644
> > > > --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > > > @@ -87,6 +87,82 @@ config MAX_CPUS
> > > >   cores, count the reserved ports. This will allocate enough 
> > > > memory
> > > >   in spin table to properly handle all cores.
> > > >
> > > > +menu "Layerscape clock tree configuration"
> > > > +   depends on FSL_LSCH2 || FSL_LSCH3
> > > > +
> > > > +config SYS_FSL_CLK
> > > > +   bool "Enable clock tree initialization"
> > > > +   default y
> > > > +
> > > > +config CLUSTER_CLK_FREQ
> > > > +   int "Reference clock of core cluster"
> > > > +   depends on ARCH_LS1012A
> > > > +   default 1
> > > > +   help
> > > > + This number is the reference clock frequency of core PLL.
> > > > + For most platforms, the core PLL and Platform PLL have the 
> > > > same
> > > > + reference clock, but for some platforms, LS1012A for instance,
> > > > + they are provided sepatately.
> > > > +
> > > > +config SYS_FSL_PCLK_DIV
> > > > +   int "Platform clock divider"
> > > 

Re: [U-Boot] [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system initialization

[Prabhakar Kushwaha]

> -Original Message-
> From: Z.Q. Hou
> Sent: Tuesday, December 27, 2016 3:58 PM
> To: Prabhakar Kushwaha ; u-
> b...@lists.denx.de; albert.u.b...@aribaud.net; york sun ;
> Mingkai Hu ; Calvin Johnson 
> Subject: RE: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system
> initialization
> 
> Hi Prabhakar,
> 
> Thanks a lot for your comments!
> 
> > -Original Message-
> > From: Prabhakar Kushwaha
> > Sent: 2016年12月27日 16:59
> > To: Z.Q. Hou ; u-boot@lists.denx.de;
> > albert.u.b...@aribaud.net; york sun ; Mingkai Hu
> > ; Calvin Johnson 
> > Cc: Z.Q. Hou 
> > Subject: RE: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system
> > initialization
> >
> >
> > > -Original Message-
> > > From: Zhiqiang Hou [mailto:zhiqiang@nxp.com]
> > > Sent: Tuesday, December 27, 2016 1:06 PM
> > > To: u-boot@lists.denx.de; albert.u.b...@aribaud.net; york sun
> > > ; Mingkai Hu ; Prabhakar
> > > Kushwaha ; Calvin Johnson
> > > 
> > > Cc: Z.Q. Hou 
> > > Subject: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system
> > > initialization
> > >
> > > From: Hou Zhiqiang 
> > >
> > > Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like
> > > LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of
> > > differences, for instance, the IP modules have different dividers to
> > > derive its clock from Platform PLL. And the core cluster PLL and
> > > platform PLL maybe have different reference clocks, such as LS1012A.
> > > Another problem is which clock/PLL should be described by
> > > sys_info->freq_systembus, it is confused in Layerscape Chissis 2.
> > >
> > > This patch is to bind the sys_info->freq_systembus to the Platform
> > > PLL, and handle the different divider of IP modules separately between
> > > different SoCs, and separate reference clocks of core cluster PLL and
> > > platform PLL.
> > >
> > > Signed-off-by: Hou Zhiqiang 
> > > ---
> > > V3:
> > >  - Generate the patch set base on the latest
> > > git://git.denx.de/u-boot-fsl- qoriq.git.
> > >  - Use the Kconfig instead of header file to add CONFIG_*
> > >
> > >  arch/arm/cpu/armv8/fsl-layerscape/Kconfig  | 76
> > > ++
> > >  arch/arm/cpu/armv8/fsl-layerscape/cpu.c|  3 +-
> > >  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 68
> > > ++-  .../include/asm/arch-fsl-layerscape/immap_lsch2.h
> > |  1 +
> > >  include/configs/ls1012a_common.h   |  6 +-
> > >  include/configs/ls1043a_common.h   |  3 +-
> > >  include/configs/ls1046a_common.h   |  3 +-
> > >  include/configs/ls2080aqds.h   |  2 -
> > >  include/configs/ls2080ardb.h   |  1 -
> > >  9 files changed, 134 insertions(+), 29 deletions(-)
> > >
> > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > > b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > > index cc0dc88..de1e5a4 100644
> > > --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > > @@ -87,6 +87,82 @@ config MAX_CPUS
> > > cores, count the reserved ports. This will allocate enough memory
> > > in spin table to properly handle all cores.
> > >
> > > +menu "Layerscape clock tree configuration"
> > > + depends on FSL_LSCH2 || FSL_LSCH3
> > > +
> > > +config SYS_FSL_CLK
> > > + bool "Enable clock tree initialization"
> > > + default y
> > > +
> > > +config CLUSTER_CLK_FREQ
> > > + int "Reference clock of core cluster"
> > > + depends on ARCH_LS1012A
> > > + default 1
> > > + help
> > > +   This number is the reference clock frequency of core PLL.
> > > +   For most platforms, the core PLL and Platform PLL have the same
> > > +   reference clock, but for some platforms, LS1012A for instance,
> > > +   they are provided sepatately.
> > > +
> > > +config SYS_FSL_PCLK_DIV
> > > + int "Platform clock divider"
> > > + default 1 if ARCH_LS1043A
> > > + default 1 if ARCH_LS1046A
> > > + default 2
> >
> > Only LS2080A and LS2088A requires Platform_PLL_freq / 2. So make 1 as
> > default and exception for LS2080A and LS2088A
> >
> The LS1012A also requires Platform_PLL_freq / 2 to derive Platform clock,
> referring to LS1012A Reference Manual, Rev. C.
> Isn't it better to make 2 the default value?
> 
> >
> > > + help
> > > +   This is the divider that is used to derive Platform clock from
> > > +   Platform PLL, in another word:
> > > + Platform_clk = Platform_PLL_freq / this_divider
> > > +
> >
> > 
> >
> > > +#endif
> > > + cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
> > > +
> > >  #ifdef CONFIG_DDR_CLK_FREQ
> > >   sys_info->freq_ddrbus = 

Re: [U-Boot] [PATCH v2 27/63] x86: Do relocation before clearing BSS

[Bin Meng]

On Sun, Nov 20, 2016 at 4:25 AM, Simon Glass  wrote:
> The BSS region may overlap with relocations. If we clear BSS we will
> overwrite the start of the relocation area. This doesn't matter when running
> from SPI flash, since it is read-only. But when relocating 64-bit U-Boot
> from one place in RAM to another, relocation will fail because some of its
> relocations have been zeroed.
>
> To fix this, put the ELF fixup call before the BSS clearing call.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  common/board_f.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Bin Meng 
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[U-Boot] [RESEND PATCH v3 2/2] dts: arm64: rk3399: add max-frequency for sdhci

[Kever Yang]

Add 'max-frequency' for sdhci node for clock init.

Signed-off-by: Kever Yang 
---

Changes in v3: None

 arch/arm/dts/rk3399.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 179860c..22277ff 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -188,6 +188,7 @@
interrupts = ;
assigned-clocks = < SCLK_EMMC>;
assigned-clock-rates = <2>;
+   max-frequency = <2>;
clocks = < SCLK_EMMC>, < ACLK_EMMC>;
clock-names = "clk_xin", "clk_ahb";
phys = <_phy>;
-- 
1.9.1

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[U-Boot] [RESEND PATCH v3 1/2] mmc: rockchip_sdhci: add clock init for mmc

[Kever Yang]

Init the clock rate to max-frequency from dts with clock driver api.

Signed-off-by: Kever Yang 
---

Changes in v3:
- using dt for max-frequency
Series-changes: 2
- using the return value

 drivers/mmc/rockchip_sdhci.c | 19 +--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index c56e1a3..e33e35e 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -12,7 +12,9 @@
 #include 
 #include 
 #include 
+#include 
 
+DECLARE_GLOBAL_DATA_PTR;
 /* 400KHz is max freq for card ID etc. Use that as min */
 #define EMMC_MIN_FREQ  40
 
@@ -32,11 +34,24 @@ static int arasan_sdhci_probe(struct udevice *dev)
struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
struct rockchip_sdhc *prv = dev_get_priv(dev);
struct sdhci_host *host = >host;
-   int ret;
+   int max_frequency, ret;
+   struct clk clk;
+
+
+   max_frequency = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+   "max-frequency", 0);
+   ret = clk_get_by_index(dev, 0, );
+   if (!ret) {
+   ret = clk_set_rate(, max_frequency);
+   if (IS_ERR_VALUE(ret))
+   printf("%s clk set rate fail!\n", __func__);
+   } else {
+   printf("%s fail to get clk\n", __func__);
+   }
 
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
 
-   ret = sdhci_setup_cfg(>cfg, host, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ,
+   ret = sdhci_setup_cfg(>cfg, host, max_frequency,
EMMC_MIN_FREQ);
 
host->mmc = >mmc;
-- 
1.9.1

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Re: [U-Boot] [PATCH v2 26/63] x86: board_r: Set the global data pointer after relocation

[Bin Meng]

Hi Simon,

On Sun, Nov 20, 2016 at 4:25 AM, Simon Glass  wrote:
> Since 'gd' is just a normal variable on 64-bit x86, it is relocated by the
> time we get to board_init_r(). The old 'gd' variable is passed in as
> parameter to board_init_r(), presumably for this situation.
>
> Assign it on 64-bit x86 so that gd points to the correct data.
>
> Options to improve this:
> - Make gd a fixed register and remove the board_init_r() parameter
> - Make all archs use this board_init_r() parameter

Can you move these from commit message to a "TODO" part in the codes?

>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  common/board_r.c | 5 +
>  1 file changed, 5 insertions(+)
>
> diff --git a/common/board_r.c b/common/board_r.c
> index d959ad3..02800ca 100644
> --- a/common/board_r.c
> +++ b/common/board_r.c
> @@ -974,6 +974,11 @@ init_fnc_t init_sequence_r[] = {
>
>  void board_init_r(gd_t *new_gd, ulong dest_addr)
>  {
> +   /* Set up the new global data pointer */
> +#if CONFIG_IS_ENABLED(X86_64)
> +   arch_setup_gd(new_gd);
> +#endif
> +
>  #ifdef CONFIG_NEEDS_MANUAL_RELOC
> int i;
>  #endif
> --

Reviewed-by: Bin Meng 

Regards,
Bin
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Re: [U-Boot] [PATCH v2 25/63] x86: board_f: Update init sequence for 64-bit startup

[Bin Meng]

Hi Simon,

On Sun, Nov 20, 2016 at 4:25 AM, Simon Glass  wrote:
> Adjust the code so that 64-bit startup works. Since we don't need to do CAR
> changes in U-Boot proper anymore (they are done in SPL) we can simplify the
> flow and return normally from board_init_f().
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  common/board_f.c | 12 
>  1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/common/board_f.c b/common/board_f.c
> index 4b74835..f19f998 100644
> --- a/common/board_f.c
> +++ b/common/board_f.c
> @@ -767,7 +767,8 @@ static int setup_reloc(void)
>  }
>
>  /* ARM calls relocate_code from its crt0.S */
> -#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
> +#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
> +   !CONFIG_IS_ENABLED(X86_64)
>
>  static int jump_to_copy(void)
>  {
> @@ -1045,7 +1046,8 @@ static init_fnc_t init_sequence_f[] = {
>  #if defined(CONFIG_XTENSA)
> clear_bss,
>  #endif
> -#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
> +#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
> +   !CONFIG_IS_ENABLED(X86_64)
> jump_to_copy,
>  #endif
> NULL,
> @@ -1079,7 +1081,7 @@ void board_init_f(ulong boot_flags)
> hang();
>
>  #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
> -   !defined(CONFIG_EFI_APP)
> +   !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64)
> /* NOTREACHED - jump_to_copy() does not return */
> hang();
>  #endif
> @@ -1103,8 +1105,10 @@ void board_init_f(ulong boot_flags)
>   * NOTE: At present only x86 uses this route, but it is intended that
>   * all archs will move to this when generic relocation is implemented.
>   */
> -static init_fnc_t init_sequence_f_r[] = {
> +static const init_fnc_t init_sequence_f_r[] = {

nits: adding "const" is irrelevant to this patch.

> +#if !CONFIG_IS_ENABLED(X86_64)
> init_cache_f_r,
> +#endif
>
> NULL,
>  };
> --

Reviewed-by: Bin Meng 

Regards,
Bin
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Re: [U-Boot] [PATCH v2 24/63] x86: Add 64-bit start-up code

[Bin Meng]

Hi Simon,

On Sun, Nov 20, 2016 at 4:25 AM, Simon Glass  wrote:
> Add code to start up U-Boot in 64-bit mode. It is fairly simple since we are
> running from RAM and SPL has done the low-level init.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  arch/x86/Makefile  |  5 +
>  arch/x86/cpu/Makefile  |  4 
>  arch/x86/cpu/start64.S | 39 +++
>  3 files changed, 48 insertions(+)
>  create mode 100644 arch/x86/cpu/start64.S
>
> diff --git a/arch/x86/Makefile b/arch/x86/Makefile
> index dd0e22f..4be1c35 100644
> --- a/arch/x86/Makefile
> +++ b/arch/x86/Makefile
> @@ -3,8 +3,13 @@
>  #
>
>  ifeq ($(CONFIG_EFI_APP),)
> +ifdef CONFIG_$(SPL_)X86_64
> +head-y := arch/x86/cpu/start64.o
> +else
>  head-y := arch/x86/cpu/start.o
>  endif
> +endif
> +
>  head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/start16.o
>  head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/resetvec.o
>
> diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
> index fd81310..97b26b0 100644
> --- a/arch/x86/cpu/Makefile
> +++ b/arch/x86/cpu/Makefile
> @@ -8,7 +8,11 @@
>  # SPDX-License-Identifier: GPL-2.0+
>  #
>
> +ifeq ($(CONFIG_$(SPL_)X86_64),y)
> +extra-y= start64.o
> +else
>  extra-y= start.o
> +endif
>  extra-$(CONFIG_$(SPL_)X86_16BIT_INIT) += resetvec.o start16.o
>  obj-y  += interrupts.o cpu.o cpu_x86.o call64.o setjmp.o
>
> diff --git a/arch/x86/cpu/start64.S b/arch/x86/cpu/start64.S
> new file mode 100644
> index 000..9eadc35
> --- /dev/null
> +++ b/arch/x86/cpu/start64.S
> @@ -0,0 +1,39 @@
> +/*
> + * 64-bit x86 Startup Code
> + *
> + * (C) Copyright 216 Google, Inc
> + * Written by Simon Glass 
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 

I guess not every header file above is being used, can you double
check and remove useless includes?

> +
> +.section .text
> +.code64
> +.globl _start
> +.type _start, @function
> +_start:
> +   /* Set up memory using the existing stack */
> +   mov %rsp, %rdi
> +   callboard_init_f_alloc_reserve
> +   mov %rax, %rsp
> +
> +   callboard_init_f_init_reserve
> +
> +   callq   board_init_f
> +   callq   board_init_f_r
> +

for consistency, can we just use "call"

> +   /* Should not return here */
> +   jmp .
> +
> +   /* If the debug UART is being used, it is already set up by SPL */
> +   .globl board_debug_uart_init

This function looks useless, is it a must?

> +board_debug_uart_init:
> +   ret
> --

Regards,
Bin
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Re: [U-Boot] [RESEND PATCH v2] mmc: rockchip_sdhci: add clock init for mmc

[Jaehoon Chung]

On 12/28/2016 10:45 AM, Kever Yang wrote:
> Hi Jaehoon,
> 
> On 12/28/2016 09:34 AM, Jaehoon Chung wrote:
>> Hi Kever,
>>
>> On 12/28/2016 10:12 AM, Kever Yang wrote:
>>> Hi Jaehoon,
>>>
>>> On 12/28/2016 06:08 AM, Jaehoon Chung wrote:
 Hi Kever,

 On 12/27/2016 10:09 PM, Kever Yang wrote:
> Init the clock rate to CONFIG_ROCKCHIP_SDHCI_MAX_FREQ with clock driver
> api.
>
> Signed-off-by: Kever Yang 
> ---
>
> Changes in v2:
> - using the return value
>
>drivers/mmc/rockchip_sdhci.c | 11 +++
>1 file changed, 11 insertions(+)
>
> diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
> index c56e1a3..96049f3 100644
> --- a/drivers/mmc/rockchip_sdhci.c
> +++ b/drivers/mmc/rockchip_sdhci.c
> @@ -12,6 +12,7 @@
>#include 
>#include 
>#include 
> +#include 
>  /* 400KHz is max freq for card ID etc. Use that as min */
>#define EMMC_MIN_FREQ40
> @@ -33,6 +34,16 @@ static int arasan_sdhci_probe(struct udevice *dev)
>struct rockchip_sdhc *prv = dev_get_priv(dev);
>struct sdhci_host *host = >host;
>int ret;
> +struct clk clk;
> +
> +ret = clk_get_by_index(dev, 0, );
> +if (!ret) {
> +ret = clk_set_rate(, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ);
 How about getting clock value from dt?
>>> SDHCI dts node is like below:
>>>  sdhci: sdhci@fe33 {
>>>  u-boot,dm-pre-reloc;
>>>  compatible = "rockchip,rk3399-sdhci-5.1", 
>>> "arasan,sdhci-5.1";
>>>  reg = <0x0 0xfe33 0x0 0x1>;
>>>  interrupts = ;
>>>  assigned-clocks = < SCLK_EMMC>;
>>>  assigned-clock-rates = <2>;
>>>  clocks = < SCLK_EMMC>, < ACLK_EMMC>;
>>>  clock-names = "clk_xin", "clk_ahb";
>>>  phys = <_phy>;
>>>  phy-names = "phy_arasan";
>>>  status = "disabled";
>>>  };
>>>
>>> There is an assigned-clock-rates, which is parsed by clock driver in kernel,
>>> but the U-Boot clk driver do not have this feature, is it OK for us to 
>>> parse it in sdhci driver?
>> Yes, Maybe it's possible to parse it in sdhci driver.
>> (assigned-clock-rate might be for assigning to initial source clock value.)
>> In Linux kernel, there is also similar property like "max-frequency".
>> MMC can have the difference maximum frequency for each SoC.
>>
>> I'm considering that implement the generic mmc parsing function.
>> Because some property can be used commonly.
>>
>> If you put the parser in sdhci driver, i will rework it into generic parsing 
>> function in future.
>> How about? :)
> 
> Look into another sdmmc dts node(dwmmc), I can found clk-freq-min-max, I 
> think this is more generic for add the SDHCI driver, right?

Yes, likes them.

> sdmmc: dwmmc@fe32 {
> compatible = "rockchip,rk3399-dw-mshc",
>  "rockchip,rk3288-dw-mshc";
> reg = <0x0 0xfe32 0x0 0x4000>;
> interrupts = ;
> clock-freq-min-max = <40 15000>;
> clocks = < SCLK_SDMMC>, < HCLK_SDMMC>,
>  < SCLK_SDMMC_DRV>, < SCLK_SDMMC_SAMPLE>;
> clock-names = "ciu", "biu", "ciu-drive", "ciu-sample";
> pinctrl-names = "default";
> pinctrl-0 = <_clk>;
> fifo-depth = <0x100>;
> status = "disabled";
> };
> 
> The U-Boot dwmmc driver will set the clock via system clock API, but SDHCI 
> driver do not do that,
> that's why I have to init the clock in rockchip_sdhci.

Now, I think that it's enough to put the parsing code in your rockchip_sdhci.c, 
isn't?

arasan_sdhci_probe() {
..
parsing "max-frequency"
clk_get_by_index();
clk_set_rate();
..

}

Is it working?

> 
> I hope everything are working like kernel, you also working on kernel mmc 
> driver, right?

Yes, i'm working on also kernel side. I also hope so. :)

Best Regards,
Jaehoon Chung

> 
> Thanks,
> - Kever
> 
>>
>> Best Regards,
>> Jaehoon Chung
>>
>>> Thanks,
>>> - Kever
>>>
 Best Regards,
 Jaehoon Chung

> +if (IS_ERR_VALUE(ret))
> +printf("%s clk set rate fail!\n", __func__);
> +} else {
> +printf("%s fail to get clk\n", __func__);
> +}
>  host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
>   


>>>
>>
>>
>>
> 
> 
> 
> 
> 

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Re: [U-Boot] [RESEND PATCH v2] mmc: rockchip_sdhci: add clock init for mmc

[Kever Yang]

Hi Jaehoon,

On 12/28/2016 09:34 AM, Jaehoon Chung wrote:

Hi Kever,

On 12/28/2016 10:12 AM, Kever Yang wrote:

Hi Jaehoon,

On 12/28/2016 06:08 AM, Jaehoon Chung wrote:

Hi Kever,

On 12/27/2016 10:09 PM, Kever Yang wrote:

Init the clock rate to CONFIG_ROCKCHIP_SDHCI_MAX_FREQ with clock driver
api.

Signed-off-by: Kever Yang 
---

Changes in v2:
- using the return value

   drivers/mmc/rockchip_sdhci.c | 11 +++
   1 file changed, 11 insertions(+)

diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index c56e1a3..96049f3 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -12,6 +12,7 @@
   #include 
   #include 
   #include 
+#include 
 /* 400KHz is max freq for card ID etc. Use that as min */
   #define EMMC_MIN_FREQ40
@@ -33,6 +34,16 @@ static int arasan_sdhci_probe(struct udevice *dev)
   struct rockchip_sdhc *prv = dev_get_priv(dev);
   struct sdhci_host *host = >host;
   int ret;
+struct clk clk;
+
+ret = clk_get_by_index(dev, 0, );
+if (!ret) {
+ret = clk_set_rate(, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ);

How about getting clock value from dt?

SDHCI dts node is like below:
 sdhci: sdhci@fe33 {
 u-boot,dm-pre-reloc;
 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 reg = <0x0 0xfe33 0x0 0x1>;
 interrupts = ;
 assigned-clocks = < SCLK_EMMC>;
 assigned-clock-rates = <2>;
 clocks = < SCLK_EMMC>, < ACLK_EMMC>;
 clock-names = "clk_xin", "clk_ahb";
 phys = <_phy>;
 phy-names = "phy_arasan";
 status = "disabled";
 };

There is an assigned-clock-rates, which is parsed by clock driver in kernel,
but the U-Boot clk driver do not have this feature, is it OK for us to parse it 
in sdhci driver?

Yes, Maybe it's possible to parse it in sdhci driver.
(assigned-clock-rate might be for assigning to initial source clock value.)
In Linux kernel, there is also similar property like "max-frequency".
MMC can have the difference maximum frequency for each SoC.

I'm considering that implement the generic mmc parsing function.
Because some property can be used commonly.

If you put the parser in sdhci driver, i will rework it into generic parsing 
function in future.
How about? :)


Look into another sdmmc dts node(dwmmc), I can found clk-freq-min-max, I 
think this is more generic for add the SDHCI driver, right?

sdmmc: dwmmc@fe32 {
compatible = "rockchip,rk3399-dw-mshc",
 "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe32 0x0 0x4000>;
interrupts = ;
clock-freq-min-max = <40 15000>;
clocks = < SCLK_SDMMC>, < HCLK_SDMMC>,
 < SCLK_SDMMC_DRV>, < SCLK_SDMMC_SAMPLE>;
clock-names = "ciu", "biu", "ciu-drive", "ciu-sample";
pinctrl-names = "default";
pinctrl-0 = <_clk>;
fifo-depth = <0x100>;
status = "disabled";
};

The U-Boot dwmmc driver will set the clock via system clock API, but 
SDHCI driver do not do that,

that's why I have to init the clock in rockchip_sdhci.

I hope everything are working like kernel, you also working on kernel 
mmc driver, right?


Thanks,
- Kever



Best Regards,
Jaehoon Chung


Thanks,
- Kever


Best Regards,
Jaehoon Chung


+if (IS_ERR_VALUE(ret))
+printf("%s clk set rate fail!\n", __func__);
+} else {
+printf("%s fail to get clk\n", __func__);
+}
 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
  












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Re: [U-Boot] [RESEND PATCH v2] mmc: rockchip_sdhci: add clock init for mmc

[Jaehoon Chung]

Hi Kever,

On 12/28/2016 10:12 AM, Kever Yang wrote:
> Hi Jaehoon,
> 
> On 12/28/2016 06:08 AM, Jaehoon Chung wrote:
>> Hi Kever,
>>
>> On 12/27/2016 10:09 PM, Kever Yang wrote:
>>> Init the clock rate to CONFIG_ROCKCHIP_SDHCI_MAX_FREQ with clock driver
>>> api.
>>>
>>> Signed-off-by: Kever Yang 
>>> ---
>>>
>>> Changes in v2:
>>> - using the return value
>>>
>>>   drivers/mmc/rockchip_sdhci.c | 11 +++
>>>   1 file changed, 11 insertions(+)
>>>
>>> diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
>>> index c56e1a3..96049f3 100644
>>> --- a/drivers/mmc/rockchip_sdhci.c
>>> +++ b/drivers/mmc/rockchip_sdhci.c
>>> @@ -12,6 +12,7 @@
>>>   #include 
>>>   #include 
>>>   #include 
>>> +#include 
>>> /* 400KHz is max freq for card ID etc. Use that as min */
>>>   #define EMMC_MIN_FREQ40
>>> @@ -33,6 +34,16 @@ static int arasan_sdhci_probe(struct udevice *dev)
>>>   struct rockchip_sdhc *prv = dev_get_priv(dev);
>>>   struct sdhci_host *host = >host;
>>>   int ret;
>>> +struct clk clk;
>>> +
>>> +ret = clk_get_by_index(dev, 0, );
>>> +if (!ret) {
>>> +ret = clk_set_rate(, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ);
>> How about getting clock value from dt?
> 
> SDHCI dts node is like below:
> sdhci: sdhci@fe33 {
> u-boot,dm-pre-reloc;
> compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
> reg = <0x0 0xfe33 0x0 0x1>;
> interrupts = ;
> assigned-clocks = < SCLK_EMMC>;
> assigned-clock-rates = <2>;
> clocks = < SCLK_EMMC>, < ACLK_EMMC>;
> clock-names = "clk_xin", "clk_ahb";
> phys = <_phy>;
> phy-names = "phy_arasan";
> status = "disabled";
> };
> 
> There is an assigned-clock-rates, which is parsed by clock driver in kernel,
> but the U-Boot clk driver do not have this feature, is it OK for us to parse 
> it in sdhci driver?

Yes, Maybe it's possible to parse it in sdhci driver.
(assigned-clock-rate might be for assigning to initial source clock value.)
In Linux kernel, there is also similar property like "max-frequency".
MMC can have the difference maximum frequency for each SoC.

I'm considering that implement the generic mmc parsing function.
Because some property can be used commonly.

If you put the parser in sdhci driver, i will rework it into generic parsing 
function in future.
How about? :)

Best Regards,
Jaehoon Chung

> 
> Thanks,
> - Kever
> 
>>
>> Best Regards,
>> Jaehoon Chung
>>
>>> +if (IS_ERR_VALUE(ret))
>>> +printf("%s clk set rate fail!\n", __func__);
>>> +} else {
>>> +printf("%s fail to get clk\n", __func__);
>>> +}
>>> host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
>>>  
>>
>>
>>
> 
> 

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Re: [U-Boot] [RESEND PATCH v2] mmc: rockchip_sdhci: add clock init for mmc

[Kever Yang]

Hi Jaehoon,

On 12/28/2016 06:08 AM, Jaehoon Chung wrote:

Hi Kever,

On 12/27/2016 10:09 PM, Kever Yang wrote:

Init the clock rate to CONFIG_ROCKCHIP_SDHCI_MAX_FREQ with clock driver
api.

Signed-off-by: Kever Yang 
---

Changes in v2:
- using the return value

  drivers/mmc/rockchip_sdhci.c | 11 +++
  1 file changed, 11 insertions(+)

diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index c56e1a3..96049f3 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -12,6 +12,7 @@
  #include 
  #include 
  #include 
+#include 
  
  /* 400KHz is max freq for card ID etc. Use that as min */

  #define EMMC_MIN_FREQ 40
@@ -33,6 +34,16 @@ static int arasan_sdhci_probe(struct udevice *dev)
struct rockchip_sdhc *prv = dev_get_priv(dev);
struct sdhci_host *host = >host;
int ret;
+   struct clk clk;
+
+   ret = clk_get_by_index(dev, 0, );
+   if (!ret) {
+   ret = clk_set_rate(, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ);

How about getting clock value from dt?


SDHCI dts node is like below:
sdhci: sdhci@fe33 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-sdhci-5.1", 
"arasan,sdhci-5.1";

reg = <0x0 0xfe33 0x0 0x1>;
interrupts = ;
assigned-clocks = < SCLK_EMMC>;
assigned-clock-rates = <2>;
clocks = < SCLK_EMMC>, < ACLK_EMMC>;
clock-names = "clk_xin", "clk_ahb";
phys = <_phy>;
phy-names = "phy_arasan";
status = "disabled";
};

There is an assigned-clock-rates, which is parsed by clock driver in 
kernel,
but the U-Boot clk driver do not have this feature, is it OK for us to 
parse it in sdhci driver?


Thanks,
- Kever



Best Regards,
Jaehoon Chung


+   if (IS_ERR_VALUE(ret))
+   printf("%s clk set rate fail!\n", __func__);
+   } else {
+   printf("%s fail to get clk\n", __func__);
+   }
  
  	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
  







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Re: [U-Boot] [PATCH] SPL: NOR: Add CONFIG_SPL_NOR_COPY_ENTIRE_IMAGE define to enable whole image copy from NOR

[Marek Vasut]

On 12/26/2016 05:36 PM, Lukasz Majewski wrote:
> Hi Marek,
> 
>> On 11/29/2016 07:18 PM, Tom Rini wrote:
>>> On Tue, Nov 29, 2016 at 11:50:34AM +0100, Marek Vasut wrote:
 On 11/29/2016 10:11 AM, Lukasz Majewski wrote:
> Hi Marek,
>
>> On 11/28/2016 10:09 PM, Lukasz Majewski wrote:
>>> This define gives the possibility to copy entire image
>>> (including header - e.g. u-boot.img) from NOR parallel memory
>>> to e.g. SDRAM. The current code only supports loading the raw
>>> binary image (the u-boot.bin).
>>>
>>> The legacy behavior is preserved, since other board don't
>>> enabled this option.
>>
>> So, what's the usecase again ? ;-) 
>
> :-)
>
> The use case is to allow u-boot.img being loaded from Parallel
> NOR. The current code only supports u-boot.bin.

 Why is u-boot.bin (or the payload) not sufficient ? Why do you
 need the header ?
>>>
>>> Well, the general use-case and code flow is that we load u-boot.img
>>> (or a FIT image) and if all else fails, fall back to assuming
>>> a .bin and a known address).
>>>
>> And exactly how is that whole image useful in RAM ? Sorry, I still do
>> not see it, usually you just need the executable payload, although
>> even that can be left in flash most of the time.
> 
> The use case is that I do want to boot from SD card/eMMC and NOR with
> using u-boot.img.
> 
> I would like to avoid situation when for NOR I must use u-boot.bin and
> for eMMC u-boot.img.
> 
> Such approach keeps things as simple as possible :-)

Oh, so it allows you to detect bitrot for the content in SPI NOR ?
It's a bit strange we had to use u-boot.bin with SPL there.

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [U-Boot, 1/3] ARM: revive CONFIG_USE_ARCH_MEMCPY/MEMSET for UniPhier and Tegra

[Tom Rini]

On Mon, Dec 19, 2016 at 07:31:02PM +0900, Masahiro Yamada wrote:

> Commit be72591bcd64 ("Kconfig: Move USE_ARCH_MEMCPY/MEMSET to
> Kconfig") is misconversion.
> 
> The original logic in include/configs/uniphier.h was as follows:
> 
>   #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64)
>   #define CONFIG_USE_ARCH_MEMSET
>   #define CONFIG_USE_ARCH_MEMCPY
>   #endif
> 
> This means those configs were enabled when building U-Boot proper,
> but disabled when building SPL.  Likewise for Tegra.
> 
> Now "depends on !SPL" prevents any boards with SPL support
> from reaching these options.  This changed the behavior for
> UniPhier and Tegra SoC family.
> 
> Please notice these two options only control the U-Boot proper
> build.  As you see arch/arm/Makefile, ARM-specific memset/memcpy
> are never compiled for SPL.  So, __HAVE_ARCH_MEMCPY/MEMSET should
> not set for SPL.
> 
> Fixes: be72591bcd64 ("Kconfig: Move USE_ARCH_MEMCPY/MEMSET to Kconfig")
> Signed-off-by: Masahiro Yamada 
> Reviewed-by: Fabio Estevam 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] MAINTAINERS, git-mailrc: update the Power maintainer

[Tom Rini]

On Mon, Dec 19, 2016 at 01:36:01PM +0900, Jaehoon Chung wrote:

> Przemyslaw didn't maintain the PMIC anymore.
> Update the pmic maintainer from Przeymyslaw to me.
> 
> Signed-off-by: Jaehoon Chung 
> Reviewed-by: Simon Glass 

Applied to u-boot/master, thanks!

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Re: [U-Boot] fs/fat: simplify get_fatent for FAT12

[Tom Rini]

On Sat, Dec 17, 2016 at 03:55:10AM +0100, Stefan Brüns wrote:

> From: Stefan Brüns 
> 
> Instead of shuffling bits from two adjacent 16 bit words, use one 16 bit
> word with the appropriate byte offset in the buffer.
> 
> Signed-off-by: Stefan Brüns 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [U-Boot, v2, 2/2] fs/fat: merge readwrite get_fatent_value() with readonly get_fatent()

[Tom Rini]

On Sat, Dec 17, 2016 at 12:27:51AM +0100, Stefan Brüns wrote:

> get_fatent_value(...) flushes changed FAT entries to disk when fetching
> the next FAT blocks, in every other aspect it is identical to
> get_fatent(...).
> 
> Provide a stub implementation for flush_dirty_fat_buffer if
> CONFIG_FAT_WRITE is not set. Calling flush_dirty_fat_buffer during read
> only operation is fine as it checks if any buffers needs flushing.
> 
> Signed-off-by: Stefan Brüns 
> Reviewed-by: Benoît Thébaudeau 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [U-Boot, v2, 1/2] fs/fat: Avoid corruption of sectors following the FAT

[Tom Rini]

On Sat, Dec 17, 2016 at 12:27:50AM +0100, Stefan Brüns wrote:

> The FAT is read/flushed in segments of 6 (FATBUFBLOCKS) disk sectors. The
> last segment may be less than 6 sectors, cap the length.
> 
> Signed-off-by: Stefan Brüns 
> Reviewed-by: Benoît Thébaudeau 

Applied to u-boot/master, thanks!

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Re: [U-Boot] cmd/Kconfig: Fix typo in CMD_MEMORY help text

[Tom Rini]

On Thu, Dec 15, 2016 at 08:02:19PM -0200, Fabio Estevam wrote:

> From: Fabio Estevam 
> 
> Fix "Memory" and "initialize" typos in the CMD_MEMORY help text.
> 
> Signed-off-by: Fabio Estevam 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot,v2] fat: fatwrite: fix the command for FAT12

[Tom Rini]

On Thu, Dec 15, 2016 at 03:52:53PM -0500, Philipp Skadorov wrote:

> The u-boot command fatwrite empties FAT clusters from the beginning
> till the end of the file.
> Specifically for FAT12 it fails to detect the end of the file and goes
> beyond the file bounds thus corrupting the file system.
> 
> Additionally, FAT entry chaining-up into a file is not implemented
> for FAT12.
> 
> The users normally workaround this by re-formatting the partition as
> FAT16/FAT32, like here:
> https://github.com/FEDEVEL/openrex-uboot-v2015.10/issues/1
> 
> The patch fixes the bounds of a file and FAT12 entries chaining into
> a file, including EOF markup.
> 
> Signed-off-by: Philipp Skadorov 

Applied to u-boot/master, thanks!

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Re: [U-Boot] relocate-rela: use compiler.h endian macros

[Tom Rini]

On Sun, Dec 11, 2016 at 02:51:13PM +1100, Jonathan Gray wrote:

> Use the endian macros from u-boot's compiler.h instead of duplicating
> the definitions.
> 
> This also avoids a build error on OpenBSD by removing swap64 which
> collides with a system definition in endian.h pulled in by inttypes.h.
> 
> Signed-off-by: Jonathan Gray 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot,v3] timer: Support clocks via phandle

[Tom Rini]

On Fri, Dec 09, 2016 at 05:18:32PM +0300, Zakharov Vlad wrote:

> Earlier timer driver needed a clock-frequency property in compatible
> device-tree nodes. Another way is to reference a clock via a phandle.
> 
> So now timer_pre_probe tries to get clock by reference through device
> tree. In case it is impossible to get clock device through the
> reference, clock-frequency property of the timer node is read to provide
> backward compatibility.
> 
> Signed-off-by: Vlad Zakharov 
> Reviewed-by: Simon Glass 

Applied to u-boot/master, thanks!

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Re: [U-Boot] regulator: fixed: Add support to handle enable-active-high DT property

[Tom Rini]

On Wed, Dec 07, 2016 at 04:55:06PM +0530, Vignesh R wrote:

> Add support to handle enable-active-high DT property. This property is
> used to drive the gpio controlling fixed regulator as active high when
> claiming gpio line.
> 
> Signed-off-by: Vignesh R 
> Acked-by: Simon Glass 

Applied to u-boot/master, thanks!

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Re: [U-Boot] Pull request: u-boot-sunxi/master

[Tom Rini]

On Sat, Dec 24, 2016 at 12:33:56AM +0100, Jagan Teki wrote:

> Hi Tom,
> 
> Please pull this fix.
> 
> thanks!
> Jagan.
> 
> The following changes since commit 4cf5c5f1e60e6541630ae829b5fa2db704c268f0:
> 
>   Prepare v2017.01-rc2 (2016-12-19 16:08:57 -0500)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-sunxi.git master 
> 
> for you to fetch changes up to c23749dbf2601986a23e2654d153e0d66a9804ba:
> 
>   sunxi: fix SID read on H3 (2016-12-23 13:07:04 +0100)
> 

Applied to u-boot/master, thanks!

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[U-Boot] [PATCH 4/4] i2c: i2c-cdns: No need for dedicated probe function

[Moritz Fischer]

The generic probe code in dm works, so get rid of the leftover cruft.

Signed-off-by: Moritz Fischer 
Cc: Heiko Schocher 
Cc: Michal Simek 
Cc: u-boot@lists.denx.de
---
 drivers/i2c/i2c-cdns.c | 21 -
 1 file changed, 21 deletions(-)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 4a46dbf..cd5cce0 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -226,26 +226,6 @@ static int cdns_i2c_set_bus_speed(struct udevice *dev, 
unsigned int speed)
return 0;
 }
 
-/* Probe to see if a chip is present. */
-static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr,
-   uint chip_flags)
-{
-   struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus);
-   struct cdns_i2c_regs *regs = i2c_bus->regs;
-
-   /* Attempt to read a byte */
-   setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
-   CDNS_I2C_CONTROL_RW);
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
-   writel(0xFF, >interrupt_status);
-   writel(chip_addr, >address);
-   writel(1, >transfer_size);
-
-   return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
-   CDNS_I2C_INTERRUPT_NACK) &
-   CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
-}
-
 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 
*data,
   u32 len)
 {
@@ -453,7 +433,6 @@ static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
 
 static const struct dm_i2c_ops cdns_i2c_ops = {
.xfer = cdns_i2c_xfer,
-   .probe_chip = cdns_i2c_probe_chip,
.set_bus_speed = cdns_i2c_set_bus_speed,
 };
 
-- 
2.7.4

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[U-Boot] [PATCH 3/4] i2c: i2c-cdns: Implement workaround for hold quirk of the rev 1.0

[Moritz Fischer]

Revision 1.0 of this IP has a quirk where if during a long read transfer
the transfer_size register will go to 0, the master will send a NACK to
the slave prematurely.
The way to work around this is to reprogram the transfer_size register
mid-transfer when the only the receive fifo is known full, i.e. the I2C
bus is known non-active.
The workaround is based on the implementation in the linux-kernel.

Signed-off-by: Moritz Fischer 
Cc: Heiko Schocher 
Cc: Michal Simek 
Cc: u-boot@lists.denx.de
---
 drivers/i2c/i2c-cdns.c | 121 -
 1 file changed, 89 insertions(+), 32 deletions(-)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 9a1b520..4a46dbf 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -67,6 +68,8 @@ struct cdns_i2c_regs {
 
 #define CDNS_I2C_FIFO_DEPTH16
 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
+#define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
+
 #define CDNS_I2C_BROKEN_HOLD_BIT   BIT(0)
 
 #ifdef DEBUG
@@ -247,15 +250,20 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus 
*i2c_bus, u32 addr, u8 *data,
   u32 len)
 {
u8 *cur_data = data;
-
struct cdns_i2c_regs *regs = i2c_bus->regs;
 
+   /* Set the controller in Master transmit mode and clear FIFO */
setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO);
-
-
clrbits_le32(>control, CDNS_I2C_CONTROL_RW);
 
+   /* Check message size against FIFO depth, and set hold bus bit
+* if it is greater than FIFO depth */
+   if (len > CDNS_I2C_FIFO_DEPTH)
+   setbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+
+   /* Clear the interrupts in status register */
writel(0xFF, >interrupt_status);
+
writel(addr, >address);
 
while (len--) {
@@ -280,48 +288,98 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus 
*i2c_bus, u32 addr, u8 *data,
return 0;
 }
 
+static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
+{
+   return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
+}
+
 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
- u32 len)
+ u32 recv_count)
 {
-   u32 status;
-   u32 i = 0;
u8 *cur_data = data;
-
-   /* TODO: Fix this */
struct cdns_i2c_regs *regs = i2c_bus->regs;
+   int curr_recv_count;
+   int updatetx, hold_quirk;
 
/* Check the hardware can handle the requested bytes */
-   if ((len < 0))
+   if ((recv_count < 0))
return -EINVAL;
 
+   curr_recv_count = recv_count;
+
+   /* Check for the message size against the FIFO depth */
+   if (recv_count > CDNS_I2C_FIFO_DEPTH)
+   setbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+
setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
CDNS_I2C_CONTROL_RW);
 
+   if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
+   curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
+   writel(curr_recv_count, >transfer_size);
+   } else {
+   writel(recv_count, >transfer_size);
+   }
+
/* Start reading data */
writel(addr, >address);
-   writel(len, >transfer_size);
-
-   /* Wait for data */
-   do {
-   status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
-   CDNS_I2C_INTERRUPT_DATA);
-   if (!status) {
-   /* Release the bus */
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
-   return -ETIMEDOUT;
+
+   updatetx = recv_count > curr_recv_count;
+
+   hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
+
+   while (recv_count) {
+   while (readl(>status) & CDNS_I2C_STATUS_RXDV) {
+   if (recv_count < CDNS_I2C_FIFO_DEPTH &&
+   !i2c_bus->hold_flag) {
+   clrbits_le32(>control,
+CDNS_I2C_CONTROL_HOLD);
+   }
+   *(cur_data)++ = readl(>data);
+   recv_count--;
+   curr_recv_count--;
+
+   if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
+   break;
}
-   debug("Read %d bytes\n",
- len - readl(>transfer_size));
-   for (; i < len - readl(>transfer_size); i++)
-   *(cur_data++) = readl(>data);
-   } while (readl(>transfer_size) != 0);
-   /* All done... release the bus */
-   if (!i2c_bus->hold_flag)
-   

[U-Boot] [PATCH 2/4] i2c: i2c-cdns: Reorder timeout loop for interrupt waiting

[Moritz Fischer]

Reorder the timeout loop such that we first check if the
condition is already true, and then call udelay() so if
the condition is already true, break early.

Signed-off-by: Moritz Fischer 
Cc: Heiko Schocher 
Cc: Michal Simek 
Cc: u-boot@lists.denx.de
---
 drivers/i2c/i2c-cdns.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index c69e7e8..9a1b520 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -130,10 +130,10 @@ static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, 
u32 mask)
int timeout, int_status;
 
for (timeout = 0; timeout < 100; timeout++) {
-   udelay(100);
int_status = readl(_i2c->interrupt_status);
if (int_status & mask)
break;
+   udelay(100);
}
 
/* Clear interrupt status flags */
-- 
2.7.4

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[U-Boot] [PATCH 1/4] i2c: i2c-cdns: Detect unsupported sequences for rev 1.0

[Moritz Fischer]

Revision 1.0 of this IP has a couple of issues, such as not supporting
repeated start conditions for read transfers.

So scan through the list of i2c messages for these conditions
and report an error if they are attempted.

This has been fixed for revision 1.4 of the IP, so only report the error
when the IP can really not do it.

Signed-off-by: Moritz Fischer 
Cc: Heiko Schocher 
Cc: Michal Simek 
Cc: u-boot@lists.denx.de
---
 drivers/i2c/i2c-cdns.c | 69 --
 1 file changed, 55 insertions(+), 14 deletions(-)

diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index f49f60b..c69e7e8 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -67,6 +67,7 @@ struct cdns_i2c_regs {
 
 #define CDNS_I2C_FIFO_DEPTH16
 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
+#define CDNS_I2C_BROKEN_HOLD_BIT   BIT(0)
 
 #ifdef DEBUG
 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
@@ -114,6 +115,13 @@ struct i2c_cdns_bus {
int id;
unsigned int input_freq;
struct cdns_i2c_regs __iomem *regs; /* register base */
+
+   int hold_flag;
+   u32 quirks;
+};
+
+struct cdns_i2c_platform_data {
+   u32 quirks;
 };
 
 /* Wait for an interrupt */
@@ -236,18 +244,14 @@ static int cdns_i2c_probe_chip(struct udevice *bus, uint 
chip_addr,
 }
 
 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 
*data,
-  u32 len, bool next_is_read)
+  u32 len)
 {
u8 *cur_data = data;
 
struct cdns_i2c_regs *regs = i2c_bus->regs;
 
-   setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
-   CDNS_I2C_CONTROL_HOLD);
+   setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO);
 
-   /* if next is a read, we need to clear HOLD, doesn't work */
-   if (next_is_read)
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
 
clrbits_le32(>control, CDNS_I2C_CONTROL_RW);
 
@@ -267,7 +271,9 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus 
*i2c_bus, u32 addr, u8 *data,
}
 
/* All done... release the bus */
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+   if (!i2c_bus->hold_flag)
+   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+
/* Wait for the address and data to be sent */
if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
return -ETIMEDOUT;
@@ -285,7 +291,7 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, 
u32 addr, u8 *data,
struct cdns_i2c_regs *regs = i2c_bus->regs;
 
/* Check the hardware can handle the requested bytes */
-   if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX))
+   if ((len < 0))
return -EINVAL;
 
setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
@@ -310,7 +316,8 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, 
u32 addr, u8 *data,
*(cur_data++) = readl(>data);
} while (readl(>transfer_size) != 0);
/* All done... release the bus */
-   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
+   if (!i2c_bus->hold_flag)
+   clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
 
 #ifdef DEBUG
cdns_i2c_debug_status(regs);
@@ -322,19 +329,43 @@ static int cdns_i2c_xfer(struct udevice *dev, struct 
i2c_msg *msg,
 int nmsgs)
 {
struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
-   int ret;
+   int ret, count;
+   bool hold_quirk;
+
+
+   printf("i2c_xfer: %d messages\n", nmsgs);
+   hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
+
+   if (nmsgs > 1) {
+   /*
+* This controller does not give completion interrupt after a
+* master receive message if HOLD bit is set (repeated start),
+* resulting in SW timeout. Hence, if a receive message is
+* followed by any other message, an error is returned
+* indicating that this sequence is not supported.
+*/
+   for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
+   if (msg[count].flags & I2C_M_RD) {
+   printf("Can't do repeated start after a receive 
message\n");
+   return -EOPNOTSUPP;
+   }
+   }
+
+   i2c_bus->hold_flag = 1;
+   setbits_le32(_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
+   } else {
+   i2c_bus->hold_flag = 0;
+   }
 
debug("i2c_xfer: %d messages\n", nmsgs);
for (; nmsgs > 0; nmsgs--, msg++) {
-   bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
-
debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);

Re: [U-Boot] [PATCH] arm: samsung: goni: use the driver model for max8998

[Jaehoon Chung]

Hi,

On 12/27/2016 11:31 PM, Minkyu Kang wrote:
> Hi,
> 
> On 27 December 2016 at 17:33, Jaehoon Chung  wrote:
> 
>> Remove the "ifndef CONFIG_DM_I2C".
>> Instead, use the driver model for max8998.
>>
>> Signed-off-by: Jaehoon Chung 
>> ---
>>  board/samsung/goni/goni.c | 61 --
>> -
>>  1 file changed, 31 insertions(+), 30 deletions(-)
>>
>> diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
>> index b066832..c1d7438 100644
>> --- a/board/samsung/goni/goni.c
>> +++ b/board/samsung/goni/goni.c
>> @@ -9,6 +9,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -43,19 +44,6 @@ void i2c_init_board(void)
>>  }
>>  #endif
>>
>> -int power_init_board(void)
>> -{
>> -#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
>> -   /*
>> -* For PMIC the I2C bus is named as I2C5, but it is connected
>> -* to logical I2C adapter 0
>> -*/
>> -   return pmic_init(I2C_0);
>> -#else
>> -   return 0;
>> -#endif
>> -}
>> -
>>  int dram_init(void)
>>  {
>> gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE +
>> @@ -146,34 +134,47 @@ int board_mmc_init(bd_t *bis)
>>  #ifdef CONFIG_USB_GADGET
>>  static int s5pc1xx_phy_control(int on)
>>  {
>> -#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
>> -   int ret;
>> +#ifdef CONFIG_DM_PMIC_MAX8998
>>
> 
> I think, we don't need it.
> What do you think?

Yes, we can remove it. Will remove.

> 
> +   struct udevice *dev;
>> static int status;
>> -   struct pmic *p = pmic_get("MAX8998_PMIC");
>> -   if (!p)
>> -   return -ENODEV;
>> +   int reg, ret;
>>
>> -   if (pmic_probe(p))
>> -   return -1;
>> +   ret = pmic_get("max8998_pmix", );
>>
> 
> pmix -> typo?

Sorry. "max8998_pmic" is right.
Will fix.

Best Regards,
Jaehoon Chung

> 
> 
>> +   if (ret)
>> +   return ret;
>>
>> if (on && !status) {
>> -   ret = pmic_set_output(p, MAX8998_REG_ONOFF1,
>> - MAX8998_LDO3, LDO_ON);
>> -   ret = pmic_set_output(p, MAX8998_REG_ONOFF2,
>> - MAX8998_LDO8, LDO_ON);
>> +   reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
>> +   reg |= MAX8998_LDO3;
>> +   ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
>> if (ret) {
>> puts("MAX8998 LDO setting error!\n");
>> -   return -1;
>> +   return -EINVAL;
>> +   }
>> +
>> +   reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
>> +   reg |= MAX8998_LDO8;
>> +   ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
>> +   if (ret) {
>> +   puts("MAX8998 LDO setting error!\n");
>> +   return -EINVAL;
>> }
>> status = 1;
>> } else if (!on && status) {
>> -   ret = pmic_set_output(p, MAX8998_REG_ONOFF1,
>> - MAX8998_LDO3, LDO_OFF);
>> -   ret = pmic_set_output(p, MAX8998_REG_ONOFF2,
>> - MAX8998_LDO8, LDO_OFF);
>> +   reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
>> +   reg &= ~MAX8998_LDO3;
>> +   ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
>> +   if (ret) {
>> +   puts("MAX8998 LDO setting error!\n");
>> +   return -EINVAL;
>> +   }
>> +
>> +   reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
>> +   reg &= ~MAX8998_LDO8;
>> +   ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
>> if (ret) {
>> puts("MAX8998 LDO setting error!\n");
>> -   return -1;
>> +   return -EINVAL;
>> }
>> status = 0;
>> }
>> --
>> 2.10.2
>>
>> ___
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>> http://lists.denx.de/mailman/listinfo/u-boot
>>
> 
> 
> Thanks,
> 

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Re: [U-Boot] [PATCH v3 4/6] mmc: tegra: allow disabling external clock loopback

[Jaehoon Chung]

On 12/22/2016 01:26 PM, Marcel Ziswiler wrote:
> From: Marcel Ziswiler 
> 
> Introduce CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK to disable the external 
> clock
> loopback and use the internal one on SDMMC3 as per the 
> SDMMC_VENDOR_MISC_CNTRL_0
> register's SDMMC_SPARE1 bits being set to 0xfffd according to the TRM.
> 
> Signed-off-by: Marcel Ziswiler 
> Reviewed-by: Simon Glass 

Reviewed-by: Jaehoon Chung 

Best Regards,
Jaehoon Chung

> 
> ---
> 
> Changes in v3: None
> Changes in v2:
> - Added Simon's reviewed-by.
> - Added TODO(email) as suggested by Simon so it is clear this is
>   temporary and will be moved to device tree controlled approach once
>   proper kernel integration made it mainline.
> 
>  arch/arm/include/asm/arch-tegra/tegra_mmc.h |  2 ++
>  drivers/mmc/Kconfig | 11 +++
>  drivers/mmc/tegra_mmc.c | 16 
>  3 files changed, 29 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h 
> b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
> index 64c848a..c40599a 100644
> --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
> +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
> @@ -108,6 +108,8 @@ struct tegra_mmc {
>  #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT8
>  #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8)
>  
> +#define TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK (1 << 17)
> +
>  #define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0)
>  #define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE(1 << 1)
>  #define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE(1 << 2)
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index 18f0e97..6372876 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -116,4 +116,15 @@ config TEGRA_MMC
>   help
> This selects support for SDHCI on Tegra SoCs.
>  
> +config TEGRA124_MMC_DISABLE_EXT_LOOPBACK
> + bool "Disable external clock loopback"
> + depends on TEGRA_MMC && TEGRA124
> + help
> +   Disable the external clock loopback and use the internal one on SDMMC3
> +   as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits
> +   being set to 0xfffd according to the TRM.
> +
> +   TODO(marcel.ziswi...@toradex.com): Move to device tree controlled
> +   approach once proper kernel integration made it mainline.
> +
>  endmenu
> diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
> index 97b1154..839b15d 100644
> --- a/drivers/mmc/tegra_mmc.c
> +++ b/drivers/mmc/tegra_mmc.c
> @@ -511,6 +511,22 @@ static int tegra_mmc_init(struct mmc *mmc)
>  
>   tegra_mmc_reset(priv, mmc);
>  
> +#if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
> + /*
> +  * Disable the external clock loopback and use the internal one on
> +  * SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
> +  * bits being set to 0xfffd according to the TRM.
> +  *
> +  * TODO(marcel.ziswi...@toradex.com): Move to device tree controlled
> +  * approach once proper kernel integration made it mainline.
> +  */
> + if (priv->reg == (void *)0x700b0400) {
> + mask = readl(>reg->venmiscctl);
> + mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK;
> + writel(mask, >reg->venmiscctl);
> + }
> +#endif
> +
>   priv->version = readw(>reg->hcver);
>   debug("host version = %x\n", priv->version);
>  
> 

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Re: [U-Boot] [PATCH v3 3/6] mmc: tegra: move CONFIG_TEGRA_MMC from headers to defconfigs

[Jaehoon Chung]

On 12/22/2016 01:26 PM, Marcel Ziswiler wrote:
> From: Marcel Ziswiler 
> 
> Basically running the following script:
> 
> tools/moveconfig.py CONFIG_TEGRA_MMC
> 
> Note that I left the SPL specific handling in
> include/configs/tegra-common-post.h unchanged.
> 
> Signed-off-by: Marcel Ziswiler 
> Reviewed-by: Simon Glass 

Reviewed-by: Jaehoon Chung 

Best Regards,
Jaehoon Chung
> 
> ---
> 
> Changes in v3:
> - My recent fresh install of Fedora 25 was missing an aarch64 toolchain
>   which made moveconfig.py not properly handle the 6 newer Tegras. I now
>   re-run moveconfig.py after installing an aarch64 toolchain and it all
>   looks sane. Sorry about that, Tom.
> 
> Changes in v2:
> - Added Simon's reviewed-by.
> 
> BTW: I will look at converting tegra to use CONFIG_BLK and
> CONFIG_DM_MMC_OPS in a later separate step.
> 
> ---
>  configs/apalis-tk1_defconfig | 1 +
>  configs/apalis_t30_defconfig | 1 +
>  configs/beaver_defconfig | 1 +
>  configs/cardhu_defconfig | 1 +
>  configs/cei-tk1-som_defconfig| 1 +
>  configs/colibri_t20_defconfig| 1 +
>  configs/colibri_t30_defconfig| 1 +
>  configs/dalmore_defconfig| 1 +
>  configs/e2220-1170_defconfig | 9 +
>  configs/harmony_defconfig| 1 +
>  configs/jetson-tk1_defconfig | 1 +
>  configs/medcom-wide_defconfig| 1 +
>  configs/nyan-big_defconfig   | 1 +
>  configs/p2371-_defconfig | 9 +
>  configs/p2371-2180_defconfig | 9 +
>  configs/p2571_defconfig  | 9 +
>  configs/p2771--000_defconfig | 9 +
>  configs/p2771--500_defconfig | 9 +
>  configs/paz00_defconfig  | 1 +
>  configs/plutux_defconfig | 1 +
>  configs/seaboard_defconfig   | 1 +
>  configs/tec-ng_defconfig | 1 +
>  configs/tec_defconfig| 1 +
>  configs/trimslice_defconfig  | 1 +
>  configs/venice2_defconfig| 1 +
>  configs/ventana_defconfig| 1 +
>  configs/whistler_defconfig   | 1 +
>  include/configs/apalis-tk1.h | 1 -
>  include/configs/apalis_t30.h | 1 -
>  include/configs/beaver.h | 1 -
>  include/configs/cardhu.h | 1 -
>  include/configs/cei-tk1-som.h| 1 -
>  include/configs/colibri_t20.h| 1 -
>  include/configs/colibri_t30.h| 1 -
>  include/configs/dalmore.h| 1 -
>  include/configs/e2220-1170.h | 1 -
>  include/configs/harmony.h| 1 -
>  include/configs/jetson-tk1.h | 1 -
>  include/configs/medcom-wide.h| 1 -
>  include/configs/nyan-big.h   | 1 -
>  include/configs/p2371-.h | 1 -
>  include/configs/p2371-2180.h | 1 -
>  include/configs/p2571.h  | 1 -
>  include/configs/p2771-.h | 1 -
>  include/configs/paz00.h  | 1 -
>  include/configs/plutux.h | 1 -
>  include/configs/seaboard.h   | 1 -
>  include/configs/tec-ng.h | 1 -
>  include/configs/tec.h| 1 -
>  include/configs/trimslice.h  | 1 -
>  include/configs/venice2.h| 1 -
>  include/configs/ventana.h| 1 -
>  include/configs/whistler.h   | 1 -
>  scripts/config_whitelist.txt | 1 -
>  54 files changed, 27 insertions(+), 75 deletions(-)
> 
> diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig
> index ae95f6b..c1caef1 100644
> --- a/configs/apalis-tk1_defconfig
> +++ b/configs/apalis-tk1_defconfig
> @@ -36,6 +36,7 @@ CONFIG_SPL_DM=y
>  CONFIG_DFU_MMC=y
>  CONFIG_DFU_RAM=y
>  # CONFIG_DM_MMC_OPS is not set
> +CONFIG_TEGRA_MMC=y
>  CONFIG_E1000=y
>  CONFIG_PCI=y
>  CONFIG_DM_PCI=y
> diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
> index 691148c..0822e2e 100644
> --- a/configs/apalis_t30_defconfig
> +++ b/configs/apalis_t30_defconfig
> @@ -25,6 +25,7 @@ CONFIG_SPL_DM=y
>  CONFIG_DFU_MMC=y
>  CONFIG_DFU_RAM=y
>  # CONFIG_DM_MMC_OPS is not set
> +CONFIG_TEGRA_MMC=y
>  CONFIG_E1000=y
>  CONFIG_PCI=y
>  CONFIG_DM_PCI=y
> diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
> index 5cb73c0..69c9ccd 100644
> --- a/configs/beaver_defconfig
> +++ b/configs/beaver_defconfig
> @@ -28,6 +28,7 @@ CONFIG_DFU_MMC=y
>  CONFIG_DFU_RAM=y
>  CONFIG_DFU_SF=y
>  # CONFIG_DM_MMC_OPS is not set
> +CONFIG_TEGRA_MMC=y
>  CONFIG_SPI_FLASH=y
>  CONFIG_SPI_FLASH_WINBOND=y
>  CONFIG_RTL8169=y
> diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
> index 0214758..e8e8b20 100644
> --- a/configs/cardhu_defconfig
> +++ b/configs/cardhu_defconfig
> @@ -23,6 +23,7 @@ CONFIG_CMD_EXT4_WRITE=y
>  CONFIG_SPL_DM=y
>  # CONFIG_BLK is not set
>  # CONFIG_DM_MMC_OPS is not set
> +CONFIG_TEGRA_MMC=y
>  CONFIG_SPI_FLASH=y
>  CONFIG_SPI_FLASH_WINBOND=y
>  CONFIG_RTL8169=y
> diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig
> index 909b367..57b87c9 100644
> --- a/configs/cei-tk1-som_defconfig
> +++ b/configs/cei-tk1-som_defconfig
> @@ -28,6 

Re: [U-Boot] [PATCH v3 2/6] mmc: tegra: introduce CONFIG_TEGRA_MMC to Kconfig

[Jaehoon Chung]

On 12/22/2016 01:26 PM, Marcel Ziswiler wrote:
> From: Marcel Ziswiler 
> 
> Signed-off-by: Marcel Ziswiler 
> Reviewed-by: Simon Glass 

Reviewed-by: Jaehoon Chung 

Best Regards,
Jaehoon Chung

> 
> ---
> 
> Changes in v3: None
> Changes in v2:
> - Added Simon's reviewed-by.
> 
>  drivers/mmc/Kconfig | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index 5e84a41..18f0e97 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -110,4 +110,10 @@ config SANDBOX_MMC
> improves build coverage for sandbox and makes it easier to detect
> MMC build errors with sandbox.
>  
> +config TEGRA_MMC
> + bool "Tegra SDHCI aka MMC support"
> + depends on DM_MMC && TEGRA
> + help
> +   This selects support for SDHCI on Tegra SoCs.
> +
>  endmenu
> 

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Re: [U-Boot] [PATCH V2 18/20] mmc: fsl_esdhc: support i.MX7ULP

[Jaehoon Chung]

Hi Peng,

On 12/27/2016 07:04 PM, Peng Fan wrote:
> Add compatible property for i.MX7ULP.
> Add a weak init_usdhc_clk function, i.MX7ULP use this to init the clock.
> 
> Signed-off-by: Peng Fan 
> Cc: Stefano Babic 
> Cc: Jaehoon Chung 

Reviewed-by: Jaehoon Chung 

Best Regards,
Jaehoon Chung

> ---
> 
> V2:
>  None
> 
>  drivers/mmc/fsl_esdhc.c | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> index 9796d39..c6b1ec9 100644
> --- a/drivers/mmc/fsl_esdhc.c
> +++ b/drivers/mmc/fsl_esdhc.c
> @@ -938,6 +938,10 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd)
>  
>  #ifdef CONFIG_DM_MMC
>  #include 
> +__weak void init_clk_usdhc(u32 index)
> +{
> +}
> +
>  static int fsl_esdhc_probe(struct udevice *dev)
>  {
>   struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
> @@ -997,6 +1001,9 @@ static int fsl_esdhc_probe(struct udevice *dev)
>* correctly get the seq as 2 and 3, then let mxc_get_clock
>* work as expected.
>*/
> +
> + init_clk_usdhc(dev->seq);
> +
>   priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
>   if (priv->sdhc_clk <= 0) {
>   dev_err(dev, "Unable to get clk for %s\n", dev->name);
> @@ -1021,6 +1028,7 @@ static const struct udevice_id fsl_esdhc_ids[] = {
>   { .compatible = "fsl,imx6sl-usdhc", },
>   { .compatible = "fsl,imx6q-usdhc", },
>   { .compatible = "fsl,imx7d-usdhc", },
> + { .compatible = "fsl,imx7ulp-usdhc", },
>   { /* sentinel */ }
>  };
>  
> 

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Re: [U-Boot] [RESEND PATCH v2] mmc: rockchip_sdhci: add clock init for mmc

[Jaehoon Chung]

Hi Kever,

On 12/27/2016 10:09 PM, Kever Yang wrote:
> Init the clock rate to CONFIG_ROCKCHIP_SDHCI_MAX_FREQ with clock driver
> api.
> 
> Signed-off-by: Kever Yang 
> ---
> 
> Changes in v2:
> - using the return value
> 
>  drivers/mmc/rockchip_sdhci.c | 11 +++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
> index c56e1a3..96049f3 100644
> --- a/drivers/mmc/rockchip_sdhci.c
> +++ b/drivers/mmc/rockchip_sdhci.c
> @@ -12,6 +12,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  /* 400KHz is max freq for card ID etc. Use that as min */
>  #define EMMC_MIN_FREQ40
> @@ -33,6 +34,16 @@ static int arasan_sdhci_probe(struct udevice *dev)
>   struct rockchip_sdhc *prv = dev_get_priv(dev);
>   struct sdhci_host *host = >host;
>   int ret;
> + struct clk clk;
> +
> + ret = clk_get_by_index(dev, 0, );
> + if (!ret) {
> + ret = clk_set_rate(, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ);

How about getting clock value from dt?

Best Regards,
Jaehoon Chung

> + if (IS_ERR_VALUE(ret))
> + printf("%s clk set rate fail!\n", __func__);
> + } else {
> + printf("%s fail to get clk\n", __func__);
> + }
>  
>   host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
>  
> 

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[U-Boot] [PATCH] tools: binman: Use /usr/bin/env to find python executable

[Emmanuel Vadot]

Some OS (all BSD and probably others) do not have python in /usr/bin
but in another directory.
It is a common usage to use /usr/bin/env python as shebang for python
scripts so use this for binman.

Signed-off-by: Emmanuel Vadot 
---
 tools/binman/binman.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/binman/binman.py b/tools/binman/binman.py
index 7fb67cb25f..4cc431fbbe 100755
--- a/tools/binman/binman.py
+++ b/tools/binman/binman.py
@@ -1,4 +1,4 @@
-#!/usr/bin/python
+#!/usr/bin/env python
 
 # Copyright (c) 2016 Google, Inc
 # Written by Simon Glass 
-- 
2.11.0

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Re: [U-Boot] [U-Boot, v3, 1/4] arm: am57xx: cl-som-am57x: add initial board support

[Tom Rini]

On Thu, Dec 08, 2016 at 05:37:52PM +0200, Uri Mashiach wrote:

> From: Dmitry Lifshitz 
> 
> Features supported :
> 
> * Serial console
> * SPI Flash
> * MMC/SD Card
> * eMMC storage
> * SATA
> * PCA9555 - GPIO expander over I2C5 bus
> * USB
> 
> Use spl alternate boot device feature to define fallback to
> the main boot device as it is defined by hardware.
> 
> Signed-off-by: Dmitry Lifshitz 
> [uri.mashi...@compulab.co.il: Adjust to v2016.11]
> Signed-off-by: Uri Mashiach 
> Acked-by: Igor Grinberg 
> Reviewed-by: Tom Rini 

Please rebase onto master (and test, there's been a few related changes
in this area), thanks!

-- 
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Re: [U-Boot] [PATCH] fs/ext4: Initialize group descriptor size for revision level 0 filesystems

[Tom Rini]

On Tue, Dec 27, 2016 at 05:15:45PM +0100, Stefan Bruens wrote:
> On Dienstag, 27. Dezember 2016 10:44:07 CET Kever Yang wrote:
> > Hi Stefan,
> > 
> >  With this patch, the image create by genext2fs can be mount in
> > U-Boot, thanks.
> 
> Thanks for testing.
> 
> @Tom: this is probably a candidate for u-boot 2017.01 ...

Thanks, I'm putting this and some other changes through their paces now.

>  
> > On 12/27/2016 09:35 AM, Stefan Brüns wrote:
> > > genext2fs creates revision level 0 filesystems, which are not readable
> > > by u-boot due to the initialized group descriptor size field.
> > > f798b1dda1c5de818b806189e523d1b75db7e72d
> > > 
> > > Reported-by: Kever Yang 
> > > Reported-by: frostyby...@protonmail.com
> > > Signed-off-by: Stefan Brüns 
> > > ---
> > > 
> > >   fs/ext4/ext4_common.c | 1 +
> > >   1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
> > > index bfebe7e379..621c61e5c7 100644
> > > --- a/fs/ext4/ext4_common.c
> > > +++ b/fs/ext4/ext4_common.c
> > > @@ -2334,6 +2334,7 @@ int ext4fs_mount(unsigned part_length)
> > > 
> > >   if (le32_to_cpu(data->sblock.revision_level) == 0) {
> > >   
> > >   fs->inodesz = 128;
> > > 
> > > + fs->gdsize = 32;
> > > 
> > >   } else {
> > >   
> > >   debug("EXT4 features COMPAT: %08x INCOMPAT: %08x 
> > > RO_COMPAT: %08x\n",
> > >   
> > > __le32_to_cpu(data->sblock.feature_compatibility),
> > 
> > Tested-by: Kever Yang 
> > 
> > Thanks,
> > - Kever
> 
> 
> -- 
> Stefan Brüns  /  Bergstraße 21  /  52062 Aachen
> home: +49 241 53809034 mobile: +49 151 50412019
> work: +49 2405 49936-424

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Re: [U-Boot] [PATCH] fs/ext4: Initialize group descriptor size for revision level 0 filesystems

[Stefan Bruens]

On Dienstag, 27. Dezember 2016 10:44:07 CET Kever Yang wrote:
> Hi Stefan,
> 
>  With this patch, the image create by genext2fs can be mount in
> U-Boot, thanks.

Thanks for testing.

@Tom: this is probably a candidate for u-boot 2017.01 ...
 
> On 12/27/2016 09:35 AM, Stefan Brüns wrote:
> > genext2fs creates revision level 0 filesystems, which are not readable
> > by u-boot due to the initialized group descriptor size field.
> > f798b1dda1c5de818b806189e523d1b75db7e72d
> > 
> > Reported-by: Kever Yang 
> > Reported-by: frostyby...@protonmail.com
> > Signed-off-by: Stefan Brüns 
> > ---
> > 
> >   fs/ext4/ext4_common.c | 1 +
> >   1 file changed, 1 insertion(+)
> > 
> > diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
> > index bfebe7e379..621c61e5c7 100644
> > --- a/fs/ext4/ext4_common.c
> > +++ b/fs/ext4/ext4_common.c
> > @@ -2334,6 +2334,7 @@ int ext4fs_mount(unsigned part_length)
> > 
> > if (le32_to_cpu(data->sblock.revision_level) == 0) {
> > 
> > fs->inodesz = 128;
> > 
> > +   fs->gdsize = 32;
> > 
> > } else {
> > 
> > debug("EXT4 features COMPAT: %08x INCOMPAT: %08x RO_COMPAT: 
> > %08x\n",
> > 
> >   __le32_to_cpu(data->sblock.feature_compatibility),
> 
> Tested-by: Kever Yang 
> 
> Thanks,
> - Kever


-- 
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home: +49 241 53809034 mobile: +49 151 50412019
work: +49 2405 49936-424
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[U-Boot] [PATCH] imx_common: check for bmode Serial Downloader

[Stefan Agner]

From: Stefan Agner 

Before commit 81c4eccb55cc ("imx: mx6: fix USB bmode to use
reserved value") a non-reserved value has been used to trigger
Serial Downloader using bmode, which translated to a GPR9 value
of 0x10. However, on some boards the non-reserved value lead to
unreliable bmode command. With the above mentioned commit, U-boot
switched to use [7:4] b0001, which translates to GPR9 0x10 for
Serial Downloader mode. Check for the new value and classify it
as Serial Downloader mode.

Signed-off-by: Stefan Agner 
CC: Stefano Babic 
CC: Tim Harvey 
CC: Fabio Estevam 
CC: Eric Nelson 
---

 arch/arm/imx-common/spl.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
index bdcda7de93..098953dce1 100644
--- a/arch/arm/imx-common/spl.c
+++ b/arch/arm/imx-common/spl.c
@@ -26,8 +26,7 @@ u32 spl_boot_device(void)
 * Check for BMODE if serial downloader is enabled
 * BOOT_MODE - see IMX6DQRM Table 8-1
 */
-   if bmode >> 24) & 0x03)  == 0x01) || /* Serial Downloader */
-   (gpr10_boot && (reg == 1)))
+   if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
return BOOT_DEVICE_UART;
/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
switch ((reg & 0x00FF) >> 4) {
@@ -39,6 +38,9 @@ u32 spl_boot_device(void)
else
return BOOT_DEVICE_NOR;
break;
+   /* Reserved: Used to force Serial Downloader */
+   case 0x1:
+   return BOOT_DEVICE_UART;
/* SATA: See 8.5.4, Table 8-20 */
case 0x2:
return BOOT_DEVICE_SATA;
-- 
2.11.0

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[U-Boot] [PATCH v2 1/5] delay: collect {m, n, u}delay declarations to include/linux/delay.h

[Masahiro Yamada]

Currently, mdelay() and udelay() are declared in include/common.h,
while ndelay() in include/linux/compat.h.  It would be nice to
collect them into include/linux/delay.h like Linux.

While we are here, fix the ndelay() implementation; I used the
DIV_ROUND_UP() instead of (x)/1000 because it must wait *longer*
than the given period of time.

Signed-off-by: Masahiro Yamada 
Reviewed-by: Simon Glass 
---

Changes in v2: None

 include/common.h   |  6 +-
 include/linux/compat.h |  2 --
 include/linux/delay.h  | 24 
 lib/time.c |  6 --
 4 files changed, 25 insertions(+), 13 deletions(-)
 create mode 100644 include/linux/delay.h

diff --git a/include/common.h b/include/common.h
index a8d833b..682205d 100644
--- a/include/common.h
+++ b/include/common.h
@@ -19,6 +19,7 @@ typedef volatile unsigned charvu_char;
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -776,7 +777,6 @@ uint64_t get_ticks(void);
 void   wait_ticks(unsigned long);
 
 /* arch/$(ARCH)/lib/time.c */
-void   __udelay  (unsigned long);
 ulong  usec2ticks(unsigned long usec);
 ulong  ticks2usec(unsigned long ticks);
 intinit_timebase (void);
@@ -833,10 +833,6 @@ void qsort(void *base, size_t nmemb, size_t size,
   int(*compar)(const void *, const void *));
 int strcmp_compar(const void *, const void *);
 
-/* lib/time.c */
-void   udelay(unsigned long);
-void mdelay(unsigned long);
-
 /* lib/uuid.c */
 #include 
 
diff --git a/include/linux/compat.h b/include/linux/compat.h
index 533983f..a43e4d6 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -15,8 +15,6 @@ struct p_current{
 
 extern struct p_current *current;
 
-#define ndelay(x)  udelay((x) < 1000 ? 1 : (x)/1000)
-
 #define dev_dbg(dev, fmt, args...) \
debug(fmt, ##args)
 #define dev_vdbg(dev, fmt, args...)\
diff --git a/include/linux/delay.h b/include/linux/delay.h
new file mode 100644
index 000..3dcd435
--- /dev/null
+++ b/include/linux/delay.h
@@ -0,0 +1,24 @@
+/*
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _LINUX_DELAY_H
+#define _LINUX_DELAY_H
+
+#include 
+
+void __udelay(unsigned long usec);
+void udelay(unsigned long usec);
+
+static inline void mdelay(unsigned long msec)
+{
+   while (msec--)
+   udelay(1000);
+}
+
+static inline void ndelay(unsigned long nsec)
+{
+   udelay(DIV_ROUND_UP(nsec, 1000));
+}
+
+#endif /* defined(_LINUX_DELAY_H) */
diff --git a/lib/time.c b/lib/time.c
index f37150f..3c49243 100644
--- a/lib/time.c
+++ b/lib/time.c
@@ -154,9 +154,3 @@ void udelay(unsigned long usec)
usec -= kv;
} while(usec);
 }
-
-void mdelay(unsigned long msec)
-{
-   while (msec--)
-   udelay(1000);
-}
-- 
2.7.4

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[U-Boot] [PATCH v2 0/5] Introduce basic headers for time, typecheck, iopoll

[Masahiro Yamada]

Changes in v2:
  - Fix typo   include/timer.h -> include/time.h

Masahiro Yamada (5):
  delay: collect {m,n,u}delay declarations to include/linux/delay.h
  time: move timer APIs to include/time.h
  typecheck: import include/linux/typecheck.h from Linux 4.9
  time: import time_after, time_before and friends from Linux
  iopoll: import include/linux/iopoll.h from Linux 4.9

 include/common.h  | 14 ++
 include/linux/compat.h|  2 --
 include/linux/delay.h | 24 +
 include/linux/iopoll.h| 68 +++
 include/linux/typecheck.h | 24 +
 include/time.h| 57 +++
 lib/time.c|  6 -
 7 files changed, 175 insertions(+), 20 deletions(-)
 create mode 100644 include/linux/delay.h
 create mode 100644 include/linux/iopoll.h
 create mode 100644 include/linux/typecheck.h
 create mode 100644 include/time.h

-- 
2.7.4

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[U-Boot] [PATCH v2 2/5] time: move timer APIs to include/time.h

[Masahiro Yamada]

The include/common.h is a collection of unrelated declarations,
macros, etc.

It is horrible to include such a cluttered header just for some
timer functions.  Split out timer functions into include/time.h.

Signed-off-by: Masahiro Yamada 
Reviewed-by: Simon Glass 
---

Changes in v2:
  - Fix typo   include/timer.h -> include/time.h

 include/common.h |  8 +---
 include/time.h   | 16 
 2 files changed, 17 insertions(+), 7 deletions(-)
 create mode 100644 include/time.h

diff --git a/include/common.h b/include/common.h
index 682205d..08f581c 100644
--- a/include/common.h
+++ b/include/common.h
@@ -17,6 +17,7 @@ typedef volatile unsigned charvu_char;
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -577,12 +578,6 @@ void ddr_enable_ecc(unsigned int dram_size);
 #endif
 #endif
 
-/*
- * Return the current value of a monotonically increasing microsecond timer.
- * Granularity may be larger than 1us if hardware does not support this.
- */
-ulong timer_get_us(void);
-
 /* $(CPU)/cpu.c */
 static inline int cpumask_next(int cpu, unsigned int mask)
 {
@@ -721,7 +716,6 @@ voidexternal_interrupt (struct pt_regs *);
 void   irq_install_handler(int, interrupt_handler_t *, void *);
 void   irq_free_handler   (int);
 void   reset_timer(void);
-ulong  get_timer  (ulong base);
 
 /* Return value of monotonic microsecond timer */
 unsigned long timer_get_us(void);
diff --git a/include/time.h b/include/time.h
new file mode 100644
index 000..5ed021f
--- /dev/null
+++ b/include/time.h
@@ -0,0 +1,16 @@
+/*
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _TIME_H
+#define _TIME_H
+
+unsigned long get_timer(unsigned long base);
+
+/*
+ * Return the current value of a monotonically increasing microsecond timer.
+ * Granularity may be larger than 1us if hardware does not support this.
+ */
+unsigned long timer_get_us(void);
+
+#endif /* _TIME_H */
-- 
2.7.4

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[U-Boot] [PATCH v2 4/5] time: import time_after, time_before and friends from Linux

[Masahiro Yamada]

It is not safe to compare timer values directly.

On 32-bit systems, for example, timer_get_us() wraps around every
72 min. (2 ^ 32 / 100 =~ 4295 sec =~ 72 min).  Depending on
the get_ticks() implementation, it may wrap more frequently.
The 72 min might be possible on the use of U-Boot.

Let's borrow time_after, time_before, and friends to solve the
wrap-around problem.

These macros were copied from include/linux/jiffies.h of Linux 4.9.

Signed-off-by: Masahiro Yamada 
---

Changes in v2: None

 include/time.h | 41 +
 1 file changed, 41 insertions(+)

diff --git a/include/time.h b/include/time.h
index 5ed021f..5746ad9 100644
--- a/include/time.h
+++ b/include/time.h
@@ -5,6 +5,8 @@
 #ifndef _TIME_H
 #define _TIME_H
 
+#include 
+
 unsigned long get_timer(unsigned long base);
 
 /*
@@ -13,4 +15,43 @@ unsigned long get_timer(unsigned long base);
  */
 unsigned long timer_get_us(void);
 
+/*
+ * These inlines deal with timer wrapping correctly. You are
+ * strongly encouraged to use them
+ * 1. Because people otherwise forget
+ * 2. Because if the timer wrap changes in future you won't have to
+ *alter your driver code.
+ *
+ * time_after(a,b) returns true if the time a is after time b.
+ *
+ * Do this with "<0" and ">=0" to only test the sign of the result. A
+ * good compiler would generate better code (and a really good compiler
+ * wouldn't care). Gcc is currently neither.
+ */
+#define time_after(a,b)\
+   (typecheck(unsigned long, a) && \
+typecheck(unsigned long, b) && \
+((long)((b) - (a)) < 0))
+#define time_before(a,b)   time_after(b,a)
+
+#define time_after_eq(a,b) \
+   (typecheck(unsigned long, a) && \
+typecheck(unsigned long, b) && \
+((long)((a) - (b)) >= 0))
+#define time_before_eq(a,b)time_after_eq(b,a)
+
+/*
+ * Calculate whether a is in the range of [b, c].
+ */
+#define time_in_range(a,b,c) \
+   (time_after_eq(a,b) && \
+time_before_eq(a,c))
+
+/*
+ * Calculate whether a is in the range of [b, c).
+ */
+#define time_in_range_open(a,b,c) \
+   (time_after_eq(a,b) && \
+time_before(a,c))
+
 #endif /* _TIME_H */
-- 
2.7.4

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[U-Boot] [PATCH v2 3/5] typecheck: import include/linux/typecheck.h from Linux 4.9

[Masahiro Yamada]

Copied from Linux 4.9.

Signed-off-by: Masahiro Yamada 
---

Changes in v2: None

 include/linux/typecheck.h | 24 
 1 file changed, 24 insertions(+)
 create mode 100644 include/linux/typecheck.h

diff --git a/include/linux/typecheck.h b/include/linux/typecheck.h
new file mode 100644
index 000..eb5b74a
--- /dev/null
+++ b/include/linux/typecheck.h
@@ -0,0 +1,24 @@
+#ifndef TYPECHECK_H_INCLUDED
+#define TYPECHECK_H_INCLUDED
+
+/*
+ * Check at compile time that something is of a particular type.
+ * Always evaluates to 1 so you may use it easily in comparisons.
+ */
+#define typecheck(type,x) \
+({ type __dummy; \
+   typeof(x) __dummy2; \
+   (void)(&__dummy == &__dummy2); \
+   1; \
+})
+
+/*
+ * Check at compile time that 'function' is a certain type, or is a pointer
+ * to that type (needs to use typedef for the function type.)
+ */
+#define typecheck_fn(type,function) \
+({ typeof(type) __tmp = function; \
+   (void)__tmp; \
+})
+
+#endif /* TYPECHECK_H_INCLUDED */
-- 
2.7.4

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[U-Boot] [PATCH v2 5/5] iopoll: import include/linux/iopoll.h from Linux 4.9

[Masahiro Yamada]

This was imported from Linux 4.9 and adjusted for U-Boot.

 - Replace the license block with SPDX
 - Drop all *_atomic variants, which make no sense for U-Boot
 - Remove the sleep_us argument, which makes no sense for U-Boot

Signed-off-by: Masahiro Yamada 
---

Changes in v2: None

 include/linux/iopoll.h | 68 ++
 1 file changed, 68 insertions(+)
 create mode 100644 include/linux/iopoll.h

diff --git a/include/linux/iopoll.h b/include/linux/iopoll.h
new file mode 100644
index 000..31c55ae
--- /dev/null
+++ b/include/linux/iopoll.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2012-2014 The Linux Foundation. All rights reserved.
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _LINUX_IOPOLL_H
+#define _LINUX_IOPOLL_H
+
+#include 
+#include 
+#include 
+
+/**
+ * readx_poll_timeout - Periodically poll an address until a condition is met 
or a timeout occurs
+ * @op: accessor function (takes @addr as its only argument)
+ * @addr: Address to poll
+ * @val: Variable to read the value into
+ * @cond: Break condition (usually involving @val)
+ * @timeout_us: Timeout in us, 0 means never timeout
+ *
+ * Returns 0 on success and -ETIMEDOUT upon a timeout. In either
+ * case, the last read value at @addr is stored in @val.
+ *
+ * When available, you'll probably want to use one of the specialized
+ * macros defined below rather than this macro directly.
+ */
+#define readx_poll_timeout(op, addr, val, cond, timeout_us)\
+({ \
+   unsigned long timeout = timer_get_us() + timeout_us; \
+   for (;;) { \
+   (val) = op(addr); \
+   if (cond) \
+   break; \
+   if (timeout_us && time_after(timer_get_us(), timeout)) { \
+   (val) = op(addr); \
+   break; \
+   } \
+   } \
+   (cond) ? 0 : -ETIMEDOUT; \
+})
+
+
+#define readb_poll_timeout(addr, val, cond, timeout_us) \
+   readx_poll_timeout(readb, addr, val, cond, timeout_us)
+
+#define readw_poll_timeout(addr, val, cond, timeout_us) \
+   readx_poll_timeout(readw, addr, val, cond, timeout_us)
+
+#define readl_poll_timeout(addr, val, cond, timeout_us) \
+   readx_poll_timeout(readl, addr, val, cond, timeout_us)
+
+#define readq_poll_timeout(addr, val, cond, timeout_us) \
+   readx_poll_timeout(readq, addr, val, cond, timeout_us)
+
+#define readb_relaxed_poll_timeout(addr, val, cond, timeout_us) \
+   readx_poll_timeout(readb_relaxed, addr, val, cond, timeout_us)
+
+#define readw_relaxed_poll_timeout(addr, val, cond, timeout_us) \
+   readx_poll_timeout(readw_relaxed, addr, val, cond, timeout_us)
+
+#define readl_relaxed_poll_timeout(addr, val, cond, timeout_us) \
+   readx_poll_timeout(readl_relaxed, addr, val, cond, timeout_us)
+
+#define readq_relaxed_poll_timeout(addr, val, cond, timeout_us) \
+   readx_poll_timeout(readq_relaxed, addr, val, cond, timeout_us)
+
+#endif /* _LINUX_IOPOLL_H */
-- 
2.7.4

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Re: [U-Boot] [PATCH] arm: samsung: goni: use the driver model for max8998

[Minkyu Kang]

Hi,

On 27 December 2016 at 17:33, Jaehoon Chung  wrote:

> Remove the "ifndef CONFIG_DM_I2C".
> Instead, use the driver model for max8998.
>
> Signed-off-by: Jaehoon Chung 
> ---
>  board/samsung/goni/goni.c | 61 --
> -
>  1 file changed, 31 insertions(+), 30 deletions(-)
>
> diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
> index b066832..c1d7438 100644
> --- a/board/samsung/goni/goni.c
> +++ b/board/samsung/goni/goni.c
> @@ -9,6 +9,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -43,19 +44,6 @@ void i2c_init_board(void)
>  }
>  #endif
>
> -int power_init_board(void)
> -{
> -#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
> -   /*
> -* For PMIC the I2C bus is named as I2C5, but it is connected
> -* to logical I2C adapter 0
> -*/
> -   return pmic_init(I2C_0);
> -#else
> -   return 0;
> -#endif
> -}
> -
>  int dram_init(void)
>  {
> gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE +
> @@ -146,34 +134,47 @@ int board_mmc_init(bd_t *bis)
>  #ifdef CONFIG_USB_GADGET
>  static int s5pc1xx_phy_control(int on)
>  {
> -#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
> -   int ret;
> +#ifdef CONFIG_DM_PMIC_MAX8998
>

I think, we don't need it.
What do you think?

+   struct udevice *dev;
> static int status;
> -   struct pmic *p = pmic_get("MAX8998_PMIC");
> -   if (!p)
> -   return -ENODEV;
> +   int reg, ret;
>
> -   if (pmic_probe(p))
> -   return -1;
> +   ret = pmic_get("max8998_pmix", );
>

pmix -> typo?


> +   if (ret)
> +   return ret;
>
> if (on && !status) {
> -   ret = pmic_set_output(p, MAX8998_REG_ONOFF1,
> - MAX8998_LDO3, LDO_ON);
> -   ret = pmic_set_output(p, MAX8998_REG_ONOFF2,
> - MAX8998_LDO8, LDO_ON);
> +   reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
> +   reg |= MAX8998_LDO3;
> +   ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
> if (ret) {
> puts("MAX8998 LDO setting error!\n");
> -   return -1;
> +   return -EINVAL;
> +   }
> +
> +   reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
> +   reg |= MAX8998_LDO8;
> +   ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
> +   if (ret) {
> +   puts("MAX8998 LDO setting error!\n");
> +   return -EINVAL;
> }
> status = 1;
> } else if (!on && status) {
> -   ret = pmic_set_output(p, MAX8998_REG_ONOFF1,
> - MAX8998_LDO3, LDO_OFF);
> -   ret = pmic_set_output(p, MAX8998_REG_ONOFF2,
> - MAX8998_LDO8, LDO_OFF);
> +   reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
> +   reg &= ~MAX8998_LDO3;
> +   ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
> +   if (ret) {
> +   puts("MAX8998 LDO setting error!\n");
> +   return -EINVAL;
> +   }
> +
> +   reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
> +   reg &= ~MAX8998_LDO8;
> +   ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
> if (ret) {
> puts("MAX8998 LDO setting error!\n");
> -   return -1;
> +   return -EINVAL;
> }
> status = 0;
> }
> --
> 2.10.2
>
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Thanks,
-- 
from. prom.
www.promsoft.net
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[U-Boot] [RESEND PATCH v2] mmc: rockchip_sdhci: add clock init for mmc

[Kever Yang]

Init the clock rate to CONFIG_ROCKCHIP_SDHCI_MAX_FREQ with clock driver
api.

Signed-off-by: Kever Yang 
---

Changes in v2:
- using the return value

 drivers/mmc/rockchip_sdhci.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index c56e1a3..96049f3 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /* 400KHz is max freq for card ID etc. Use that as min */
 #define EMMC_MIN_FREQ  40
@@ -33,6 +34,16 @@ static int arasan_sdhci_probe(struct udevice *dev)
struct rockchip_sdhc *prv = dev_get_priv(dev);
struct sdhci_host *host = >host;
int ret;
+   struct clk clk;
+
+   ret = clk_get_by_index(dev, 0, );
+   if (!ret) {
+   ret = clk_set_rate(, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ);
+   if (IS_ERR_VALUE(ret))
+   printf("%s clk set rate fail!\n", __func__);
+   } else {
+   printf("%s fail to get clk\n", __func__);
+   }
 
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
 
-- 
1.9.1

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[U-Boot] [PATCH v2] mmc: rockchip_sdhci: add clock init for mmc

[Kever Yang]

Init the clock rate to CONFIG_ROCKCHIP_SDHCI_MAX_FREQ with clock driver
api.

Signed-off-by: Kever Yang 
---

Changes in v2:
- using the return value

 drivers/mmc/rockchip_sdhci.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index c56e1a3..c37c697 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /* 400KHz is max freq for card ID etc. Use that as min */
 #define EMMC_MIN_FREQ  40
@@ -33,6 +34,16 @@ static int arasan_sdhci_probe(struct udevice *dev)
struct rockchip_sdhc *prv = dev_get_priv(dev);
struct sdhci_host *host = >host;
int ret;
+   struct clk clk;
+
+   ret = clk_get_by_index(dev, 0, );
+   if (!ret) {
+   ret = clk_set_rate(, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ);
+   if (IS_ERR_VALUE(ret))
+   printf("%s clk set rate fail!\n", __func__);
+   } else {
+   printf("%s fail to get clk\n", __func__)
+   }
 
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
 
-- 
1.9.1

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Re: [U-Boot] [PATCH v2 0/6] mmc: move some config options to Kconfig

[Tom Rini]

On Mon, Dec 26, 2016 at 08:53:53PM +0900, Masahiro Yamada wrote:
> Hi Tom,
> 
> 
> 2016-12-20 15:17 GMT+09:00 Masahiro Yamada :
> > Hi Tom.
> >
> >
> > 2016-12-07 22:10 GMT+09:00 Masahiro Yamada :
> >>
> >> I wrote a new SDHCI driver for my new SoCs, but before posting it,
> >> I just want to make a clean base for my driver entry.
> >>
> >> Of course, I could enable some needed options in my header file
> >> (for options in the "white-list"), but I just thought it is a good
> >> habit to contribute to Kconfig moves in the area I am working on now.
> >>
> >> Some people are actively working on such moves, so this kind of work
> >> is really conflict-prone.
> >>
> >> I described how to generate each commit in its git-log
> >> in case this series becomes out of date.
> >>
> >> I created this series based on v2017.01-rc1, but if some other pull
> >> requests go in first, I hope Tom will easily reproduce it by following
> >> each instruction in the log.
> >>
> >
> > This series got Reviewed-by from you and Jaehoon.
> > But it has been left for a while, and it is already staled.
> >
> > I described how to generate each patch,
> > and if you are planning to manage it by yourself, that's OK.
> >
> > But, if there is something I can do to get this series in, please let me 
> > know.
> > My work is being blocked by this series.
> 
> 
> I've noticed you are not even responding.
> 
> If requested, I can regenerate the series based on the current tree.
> 
> If you continue to be silent, I will enable CONFIG in my header
> in a legacy way to finish my work.

Sorry, I'll be taking a look at applying various patches soon, thanks!

-- 
Tom


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[U-Boot] Hoping to dual-boot an M8S Pro / Amlogic S812 machine

[Alexandru Lovin]

Hello everyone, happy holidays,

I want to dual-boot Gentoo and the original Android on one of these

boxes. To install Gentoo, I found an equivalent tutorial for a box named
TrimSlice, here . Nowhere in that
tutorial do they actually make the target box dual-bootable, so that is my
question:

How do I make that M8S Pro dual-boot with U-boot? I don't want to nuke the
original Android off it.
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[U-Boot] [PATCH V2 10/20] mx7ulp: Add iomux pins header file

[Peng Fan]

From: Ye Li 

Add the iomux pins header file from iomux tool team. Change the IOMUXC0 pins
to add IOMUX_CONFIG_MPORTS flags.

Note: The IOMUXC0 offset provided in this file is from 0xD000, this is not
aligned with IOMUXC0 base address. We have adjusted the IOMUXC0 base address
to aligin with it.

Signed-off-by: Peng Fan 
Signed-off-by: Ye Li 
Cc: Stefano Babic 
---

V2:
 None

 arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h | 910 +
 1 file changed, 910 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h

diff --git a/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h 
b/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h
new file mode 100644
index 000..4e4740c
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h
@@ -0,0 +1,910 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_IMX7ULP_PINS_H__
+#define __ASM_ARCH_IMX7ULP_PINS_H__
+
+#include 
+
+enum {
+   MX7ULP_PAD_PTA0__CMP0_IN1_3V = 
IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x0, 0x, 0x0, 0),
+   MX7ULP_PAD_PTA0__PTA0= 
IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x1, 0x, 0x0, 0),
+   MX7ULP_PAD_PTA0__LPSPI0_PCS1 = 
IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x2, 0),
+   MX7ULP_PAD_PTA0__LPUART0_CTS_b   = 
IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x2, 0),
+   MX7ULP_PAD_PTA0__LPI2C0_SCL  = 
IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x2, 0),
+   MX7ULP_PAD_PTA0__TPM0_CLKIN  = 
IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x2, 0),
+   MX7ULP_PAD_PTA0__I2S0_RX_BCLK= 
IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8, 0x2, 0),
+   MX7ULP_PAD_PTA0__LLWU0_P0= 
IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0xd, 0x, 0x0, 0),
+   MX7ULP_PAD_PTA1__CMP0_IN2_3V = 
IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x0, 0x, 0x0, 0),
+   MX7ULP_PAD_PTA1__PTA1= 
IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x1, 0x, 0x0, 0),
+   MX7ULP_PAD_PTA1__LPSPI0_PCS2 = 
IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x1, 0),
+   MX7ULP_PAD_PTA1__LPUART0_RTS_b   = 
IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x4, 0x, 0x0, 0),
+   MX7ULP_PAD_PTA1__LPI2C0_SDA  = 
IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x1, 0),
+   MX7ULP_PAD_PTA1__TPM0_CH0= 
IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x1, 0),
+   MX7ULP_PAD_PTA1__I2S0_RX_FS  = 
IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x7, 0xD1BC, 0x1, 0),
+   MX7ULP_PAD_PTA2__CMP1_IN2_3V = 
IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x0, 0x, 0x0, 0),
+   MX7ULP_PAD_PTA2__PTA2= 
IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x1, 0x, 0x0, 0),
+   MX7ULP_PAD_PTA2__LPSPI0_PCS3 = 
IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x1, 0),
+   MX7ULP_PAD_PTA2__LPUART0_TX  = 
IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x4, 0xD200, 0x1, 0),
+   MX7ULP_PAD_PTA2__LPI2C0_HREQ = 
IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x5, 0xD178, 0x1, 0),
+   MX7ULP_PAD_PTA2__TPM0_CH1= 
IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x1, 0),
+   MX7ULP_PAD_PTA2__I2S0_RXD0   = 
IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x7, 0xD1DC, 0x1, 0),
+   MX7ULP_PAD_PTA3__CMP1_IN4_3V = 
IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x0, 0x, 0x0, 0),
+   MX7ULP_PAD_PTA3__PTA3= 
IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x1, 0x, 0x0, 0),
+   MX7ULP_PAD_PTA3__LPSPI0_PCS0 = 
IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x1, 0),
+   MX7ULP_PAD_PTA3__LPUART0_RX  = 
IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x4, 0xD1FC, 0x1, 0),
+   MX7ULP_PAD_PTA3__TPM0_CH2= 
IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x6, 0xD140, 0x1, 0),
+   MX7ULP_PAD_PTA3__I2S0_RXD1   = 
IOMUX_PAD(0xD00C, 

[U-Boot] [PATCH] cmd: net: fix function name in comment

[Baruch Siach]

In commit 7044c6bb6 (net: cosmetic: Clean up DHCP variables and functions)
BootpCopyNetParams() was renamed to store_net_params(). Update the reference in
comment.

Cc: Joe Hershberger 
Signed-off-by: Baruch Siach 
---
 cmd/net.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cmd/net.c b/cmd/net.c
index bed76e4bcb08..df8b6c9b53f0 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -136,7 +136,7 @@ static void netboot_update_env(void)
}
 #if !defined(CONFIG_BOOTP_SERVERIP)
/*
-* Only attempt to change serverip if net/bootp.c:BootpCopyNetParams()
+* Only attempt to change serverip if net/bootp.c:store_net_params()
 * could have set it
 */
if (net_server_ip.s_addr) {
-- 
2.11.0

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Re: [U-Boot] Linux 4.9 on cortex-M4 STM32F429-disc1

[Steven VALSESIA]

Sorry guys, I found the problem.

the XIP_PHYS_ADDR was wrong, it's 0x08060040 not 0x0806, i forgot the
64bytes header!!!


Thanks anyway for your work, fabulous!!! Love you guys!!! Merry Christmas!!

2016-12-26 18:52 GMT+01:00 Steven VALSESIA :

> Hi,
>
> I'm stuck since days with this problem, Linux don't boot.
>
> My board flash start 0x0800  2MB.
> My board external RAM start at 0xD000  8MB.
> I have a Linux 4.9, near the default stm32f2_defconfig.
> U-BOOT at 0x0800 .
> DTB at 0x0804 .
> XIP kernel at 0x0806 .
>
> I just have "Starting kernel..." on last message.
>
> I tried to add a LED toggle on the kernel start 
> (arch/arm/boot/compressed/head.S)
> and it's not called. Same asm code run fine with u-boot on init.
>
> more details here: http://stackoverflow.com/questions/41321971/running-
> linux-4-9-on-cortex-m4-stm32f4-29i-disc1
>
>
> If you have any clues, any idea, don't hesitate, I'm desperate.
>
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[U-Boot] Linux 4.9 on cortex-M4 STM32F429-disc1

[Steven VALSESIA]

Hi,

I'm stuck since days with this problem, Linux don't boot.

My board flash start 0x0800  2MB.
My board external RAM start at 0xD000  8MB.
I have a Linux 4.9, near the default stm32f2_defconfig.
U-BOOT at 0x0800 .
DTB at 0x0804 .
XIP kernel at 0x0806 .

I just have "Starting kernel..." on last message.

I tried to add a LED toggle on the kernel start
(arch/arm/boot/compressed/head.S) and it's not called. Same asm code run
fine with u-boot on init.

more details here:
http://stackoverflow.com/questions/41321971/running-linux-4-9-on-cortex-m4-stm32f4-29i-disc1


If you have any clues, any idea, don't hesitate, I'm desperate.
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[U-Boot] [PATCH V2 06/20] imx: mx7ulp: handle all the lpuarts in get_lpuart_clk

[Peng Fan]

Add handle the lpuarts in get_lpuart_clk.

Signed-off-by: Peng Fan 
Signed-off-by: Ye Li 
Cc: Stefano Babic 
---

V2:
 None

 arch/arm/cpu/armv7/mx7ulp/clock.c | 34 +++---
 1 file changed, 31 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx7ulp/clock.c 
b/arch/arm/cpu/armv7/mx7ulp/clock.c
index 534f632..0c34d88 100644
--- a/arch/arm/cpu/armv7/mx7ulp/clock.c
+++ b/arch/arm/cpu/armv7/mx7ulp/clock.c
@@ -42,7 +42,35 @@ static u32 get_ipg_clk(void)
 
 u32 get_lpuart_clk(void)
 {
-   return pcc_clock_get_rate(PER_CLK_LPUART4);
+   int index = 0;
+
+   const u32 lpuart_array[] = {
+   LPUART0_RBASE,
+   LPUART1_RBASE,
+   LPUART2_RBASE,
+   LPUART3_RBASE,
+   LPUART4_RBASE,
+   LPUART5_RBASE,
+   LPUART6_RBASE,
+   LPUART7_RBASE,
+   };
+
+   const enum pcc_clk lpuart_pcc_clks[] = {
+   PER_CLK_LPUART4,
+   PER_CLK_LPUART5,
+   PER_CLK_LPUART6,
+   PER_CLK_LPUART7,
+   };
+
+   for (index = 0; index < 8; index++) {
+   if (lpuart_array[index] == LPUART_BASE)
+   break;
+   }
+
+   if (index < 4 || index > 7)
+   return 0;
+
+   return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]);
 }
 
 unsigned int mxc_get_clock(enum mxc_clock clk)
@@ -59,7 +87,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
case MXC_I2C_CLK:
return pcc_clock_get_rate(PER_CLK_LPI2C4);
case MXC_UART_CLK:
-   return pcc_clock_get_rate(PER_CLK_LPUART4);
+   return get_lpuart_clk();
case MXC_ESDHC_CLK:
return pcc_clock_get_rate(PER_CLK_USDHC0);
case MXC_ESDHC2_CLK:
@@ -264,7 +292,7 @@ int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 
printf("CORE   %8d kHz\n", scg_clk_get_rate(SCG_CORE_CLK) / 1000);
printf("IPG%8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
-   printf("UART   %8d kHz\n", pcc_clock_get_rate(PER_CLK_LPUART4) / 
1000);
+   printf("UART   %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
printf("AHB%8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
printf("AXI%8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
printf("DDR%8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
-- 
2.6.2

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[U-Boot] [PATCH] imx: mx6sllevk: add MAINTAINERS file

[Peng Fan]

add MAINTAINERS files

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 board/freescale/mx6sllevk/MAINTAINERS | 7 +++
 1 file changed, 7 insertions(+)
 create mode 100644 board/freescale/mx6sllevk/MAINTAINERS

diff --git a/board/freescale/mx6sllevk/MAINTAINERS 
b/board/freescale/mx6sllevk/MAINTAINERS
new file mode 100644
index 000..b82273c
--- /dev/null
+++ b/board/freescale/mx6sllevk/MAINTAINERS
@@ -0,0 +1,7 @@
+MX6SLLEVK BOARD
+M: Peng Fan 
+S: Maintained
+F: board/freescale/mx6sllevk/
+F: include/configs/mx6sllevk.h
+F: configs/mx6sllevk_defconfig
+F: configs/mx6sllevk_plugin_defconfig
-- 
2.6.6

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Re: [U-Boot] [PATCH V2 20/20] imx: mx7ulp_evk: enable mmc/regulator support

[Peng Fan]

> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Fabio
> Estevam
> Sent: Tuesday, December 27, 2016 7:23 PM
> To: Peng Fan 
> Cc: U-Boot-Denx 
> Subject: Re: [U-Boot] [PATCH V2 20/20] imx: mx7ulp_evk: enable
> mmc/regulator support
> 
> On Tue, Dec 27, 2016 at 8:04 AM, Peng Fan  wrote:
> 
> > +#define CONFIG_EXTRA_ENV_SETTINGS \
> > +   "script=boot.scr\0" \
> > +   "image=zImage\0" \
> > +   "console=ttyLP0\0" \
> > +   "fdt_high=0x\0" \
> > +   "initrd_high=0x\0" \
> > +   "fdt_file=imx7ulp-evk.dtb\0" \
> > +   "fdt_addr=0x6300\0" \
> > +   "boot_fdt=try\0" \
> 
> On this platform we will always boot from dt, so we can remove this 
> variable...


Fix in v3.

> 
> > +   "earlycon=lpuart32,0x402D0010\0" \
> > +   "ip_dyn=yes\0" \
> > +   "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> > +   "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> > +   "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> > +   "mmcautodetect=yes\0" \
> > +   "mmcargs=setenv bootargs console=${console},${baudrate} " \
> > +   "root=${mmcroot}\0" \
> > +   "loadbootscript=" \
> > +   "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" 
> > \
> > +   "bootscript=echo Running bootscript from mmc ...; " \
> > +   "source\0" \
> > +   "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> ${image}\0" \
> > +   "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0"
> \
> > +   "mmcboot=echo Booting from mmc ...; " \
> > +   "run mmcargs; " \
> > +   "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then 
> > " \
> 
> ,which will also simplify things here.

Agree.

Thanks,
Peng.

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Re: [U-Boot] [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system initialization

[Z.Q. Hou]

Hi Prabhakar,

Thanks a lot for your comments!

> -Original Message-
> From: Prabhakar Kushwaha
> Sent: 2016年12月27日 16:59
> To: Z.Q. Hou ; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; york sun ; Mingkai Hu
> ; Calvin Johnson 
> Cc: Z.Q. Hou 
> Subject: RE: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system
> initialization
> 
> 
> > -Original Message-
> > From: Zhiqiang Hou [mailto:zhiqiang@nxp.com]
> > Sent: Tuesday, December 27, 2016 1:06 PM
> > To: u-boot@lists.denx.de; albert.u.b...@aribaud.net; york sun
> > ; Mingkai Hu ; Prabhakar
> > Kushwaha ; Calvin Johnson
> > 
> > Cc: Z.Q. Hou 
> > Subject: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system
> > initialization
> >
> > From: Hou Zhiqiang 
> >
> > Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like
> > LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of
> > differences, for instance, the IP modules have different dividers to
> > derive its clock from Platform PLL. And the core cluster PLL and
> > platform PLL maybe have different reference clocks, such as LS1012A.
> > Another problem is which clock/PLL should be described by
> > sys_info->freq_systembus, it is confused in Layerscape Chissis 2.
> >
> > This patch is to bind the sys_info->freq_systembus to the Platform
> > PLL, and handle the different divider of IP modules separately between
> > different SoCs, and separate reference clocks of core cluster PLL and
> > platform PLL.
> >
> > Signed-off-by: Hou Zhiqiang 
> > ---
> > V3:
> >  - Generate the patch set base on the latest
> > git://git.denx.de/u-boot-fsl- qoriq.git.
> >  - Use the Kconfig instead of header file to add CONFIG_*
> >
> >  arch/arm/cpu/armv8/fsl-layerscape/Kconfig  | 76
> > ++
> >  arch/arm/cpu/armv8/fsl-layerscape/cpu.c|  3 +-
> >  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 68
> > ++-  .../include/asm/arch-fsl-layerscape/immap_lsch2.h
> |  1 +
> >  include/configs/ls1012a_common.h   |  6 +-
> >  include/configs/ls1043a_common.h   |  3 +-
> >  include/configs/ls1046a_common.h   |  3 +-
> >  include/configs/ls2080aqds.h   |  2 -
> >  include/configs/ls2080ardb.h   |  1 -
> >  9 files changed, 134 insertions(+), 29 deletions(-)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > index cc0dc88..de1e5a4 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > @@ -87,6 +87,82 @@ config MAX_CPUS
> >   cores, count the reserved ports. This will allocate enough memory
> >   in spin table to properly handle all cores.
> >
> > +menu "Layerscape clock tree configuration"
> > +   depends on FSL_LSCH2 || FSL_LSCH3
> > +
> > +config SYS_FSL_CLK
> > +   bool "Enable clock tree initialization"
> > +   default y
> > +
> > +config CLUSTER_CLK_FREQ
> > +   int "Reference clock of core cluster"
> > +   depends on ARCH_LS1012A
> > +   default 1
> > +   help
> > + This number is the reference clock frequency of core PLL.
> > + For most platforms, the core PLL and Platform PLL have the same
> > + reference clock, but for some platforms, LS1012A for instance,
> > + they are provided sepatately.
> > +
> > +config SYS_FSL_PCLK_DIV
> > +   int "Platform clock divider"
> > +   default 1 if ARCH_LS1043A
> > +   default 1 if ARCH_LS1046A
> > +   default 2
> 
> Only LS2080A and LS2088A requires Platform_PLL_freq / 2. So make 1 as
> default and exception for LS2080A and LS2088A
> 
The LS1012A also requires Platform_PLL_freq / 2 to derive Platform clock, 
referring to LS1012A Reference Manual, Rev. C.
Isn't it better to make 2 the default value?

> 
> > +   help
> > + This is the divider that is used to derive Platform clock from
> > + Platform PLL, in another word:
> > +   Platform_clk = Platform_PLL_freq / this_divider
> > +
> 
> 
> 
> > +#endif
> > +   cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
> > +
> >  #ifdef CONFIG_DDR_CLK_FREQ
> > sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;  #else
> > sys_info->freq_ddrbus = sysclk;
> >  #endif
> >
> > -#ifdef CONFIG_ARCH_LS1012A
> > -   sys_info->freq_ddrbus *= (gur_in32(>rcwsr[0]) >>
> > -   FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> > -   FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> > -#else
> > +   /* The freq_systembus is used to record frequency of platform PLL */
> > sys_info->freq_systembus *= (gur_in32(>rcwsr[0]) >>
> > FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> > 

Re: [U-Boot] [PATCH V2 20/20] imx: mx7ulp_evk: enable mmc/regulator support

[Fabio Estevam]

On Tue, Dec 27, 2016 at 8:04 AM, Peng Fan  wrote:

> +#define CONFIG_EXTRA_ENV_SETTINGS \
> +   "script=boot.scr\0" \
> +   "image=zImage\0" \
> +   "console=ttyLP0\0" \
> +   "fdt_high=0x\0" \
> +   "initrd_high=0x\0" \
> +   "fdt_file=imx7ulp-evk.dtb\0" \
> +   "fdt_addr=0x6300\0" \
> +   "boot_fdt=try\0" \

On this platform we will always boot from dt, so we can remove this variable...

> +   "earlycon=lpuart32,0x402D0010\0" \
> +   "ip_dyn=yes\0" \
> +   "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> +   "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> +   "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> +   "mmcautodetect=yes\0" \
> +   "mmcargs=setenv bootargs console=${console},${baudrate} " \
> +   "root=${mmcroot}\0" \
> +   "loadbootscript=" \
> +   "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
> +   "bootscript=echo Running bootscript from mmc ...; " \
> +   "source\0" \
> +   "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
> +   "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
> +   "mmcboot=echo Booting from mmc ...; " \
> +   "run mmcargs; " \
> +   "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \

,which will also simplify things here.
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[U-Boot] [PATCH] board: samsung: update the MAINTAINERS file

[Jaehoon Chung]

Update the maintainer from Przemyslaw and Lukasz to me.

Signed-off-by: Jaehoon Chung 
---
 board/samsung/odroid/MAINTAINERS | 2 +-
 board/samsung/smdk5420/MAINTAINERS   | 2 +-
 board/samsung/trats/MAINTAINERS  | 2 +-
 board/samsung/trats2/MAINTAINERS | 2 +-
 board/samsung/universal_c210/MAINTAINERS | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/board/samsung/odroid/MAINTAINERS b/board/samsung/odroid/MAINTAINERS
index 2131d365ce..3f2cf14bec 100644
--- a/board/samsung/odroid/MAINTAINERS
+++ b/board/samsung/odroid/MAINTAINERS
@@ -1,5 +1,5 @@
 ODROID BOARD
-M: Przemyslaw Marczak 
+M: Jaehoon Chung 
 S: Maintained
 F: board/samsung/odroid/
 F: include/configs/odroid.h
diff --git a/board/samsung/smdk5420/MAINTAINERS 
b/board/samsung/smdk5420/MAINTAINERS
index 0361657ede..590a1140b0 100644
--- a/board/samsung/smdk5420/MAINTAINERS
+++ b/board/samsung/smdk5420/MAINTAINERS
@@ -10,7 +10,7 @@ F:include/configs/peach-pi.h
 F: configs/peach-pi_defconfig
 
 ODROID-XU3 BOARD
-M: Przemyslaw Marczak 
+M: Jaehoon Chung 
 S: Maintained
 F: board/samsung/smdk5420/
 F: include/configs/odroid_xu3.h
diff --git a/board/samsung/trats/MAINTAINERS b/board/samsung/trats/MAINTAINERS
index 1b219b4cfe..060bcdb64b 100644
--- a/board/samsung/trats/MAINTAINERS
+++ b/board/samsung/trats/MAINTAINERS
@@ -1,5 +1,5 @@
 TRATS BOARD
-M: Lukasz Majewski 
+M: Jaehoon Chung 
 S: Maintained
 F: board/samsung/trats/
 F: include/configs/trats.h
diff --git a/board/samsung/trats2/MAINTAINERS b/board/samsung/trats2/MAINTAINERS
index 70183002f6..ba17b4e0a6 100644
--- a/board/samsung/trats2/MAINTAINERS
+++ b/board/samsung/trats2/MAINTAINERS
@@ -1,5 +1,5 @@
 TRATS2 BOARD
-M: Lukasz Majewski 
+M: Jaehoon Chung 
 S: Maintained
 F: board/samsung/trats2/
 F: include/configs/trats2.h
diff --git a/board/samsung/universal_c210/MAINTAINERS 
b/board/samsung/universal_c210/MAINTAINERS
index 676067813b..00d611042c 100644
--- a/board/samsung/universal_c210/MAINTAINERS
+++ b/board/samsung/universal_c210/MAINTAINERS
@@ -1,5 +1,5 @@
 UNIVERSAL_C210 BOARD
-M: Przemyslaw Marczak 
+M: Jaehoon Chung 
 S: Maintained
 F: board/samsung/universal_c210/
 F: include/configs/s5pc210_universal.h
-- 
2.11.0

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[U-Boot] [PATCH V2 05/20] imx: mx7ulp: Add soc level initialization codes and functions

[Peng Fan]

Implement soc level functions to get cpu rev, reset cause, enable cache,
etc. We will disable the wdog and init clocks in s_init at very early u-boot
phase.

Since the we are seeking the way to get chip id for mx7ulp, the get_cpu_rev
is hard coded to a fixed value. This may change in future.

Reuse some code in imx-common.

Signed-off-by: Peng Fan 
Signed-off-by: Ye Li 
Cc: Stefano Babic 
---

V2:
 Reuse code in imx-common

 arch/arm/Makefile|   2 +-
 arch/arm/cpu/armv7/mx7ulp/Makefile   |   2 +-
 arch/arm/cpu/armv7/mx7ulp/soc.c  | 274 +++
 arch/arm/imx-common/Makefile |   4 +
 arch/arm/include/asm/arch-imx/cpu.h  |   2 +
 arch/arm/include/asm/arch-mx7ulp/imx-regs.h  |   5 +
 arch/arm/include/asm/arch-mx7ulp/sys_proto.h |  21 ++
 7 files changed, 308 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/mx7ulp/soc.c
 create mode 100644 arch/arm/include/asm/arch-mx7ulp/sys_proto.h

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ef4f69d..0921a66 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -99,7 +99,7 @@ ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter 
$(SOC), mx25 mx27 mx5
 libs-y += arch/arm/imx-common/
 endif
 else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35 mxs vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs vf610))
 libs-y += arch/arm/imx-common/
 endif
 endif
diff --git a/arch/arm/cpu/armv7/mx7ulp/Makefile 
b/arch/arm/cpu/armv7/mx7ulp/Makefile
index 6f37e8c..0248ea8 100644
--- a/arch/arm/cpu/armv7/mx7ulp/Makefile
+++ b/arch/arm/cpu/armv7/mx7ulp/Makefile
@@ -5,4 +5,4 @@
 #
 #
 
-obj-y  := clock.o iomux.o pcc.o scg.o
+obj-y  := soc.o clock.o iomux.o pcc.o scg.o
diff --git a/arch/arm/cpu/armv7/mx7ulp/soc.c b/arch/arm/cpu/armv7/mx7ulp/soc.c
new file mode 100644
index 000..d04edc5
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx7ulp/soc.c
@@ -0,0 +1,274 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include 
+#include 
+#include 
+#include 
+
+static char *get_reset_cause(char *);
+
+u32 get_cpu_rev(void)
+{
+   /* Temporally hard code the CPU rev to 0x73, rev 1.0. Fix it later */
+   return (MXC_CPU_MX7ULP << 12) | (1 << 4);
+}
+
+#ifdef CONFIG_REVISION_TAG
+u32 __weak get_board_rev(void)
+{
+   return get_cpu_rev();
+}
+#endif
+
+enum bt_mode get_boot_mode(void)
+{
+   u32 bt0_cfg = 0;
+
+   bt0_cfg = readl(CMC0_RBASE + 0x40);
+   bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
+
+   if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
+   /* No low power boot */
+   if (bt0_cfg & BT0CFG_DUALBOOT_MASK)
+   return DUAL_BOOT;
+   else
+   return SINGLE_BOOT;
+   }
+
+   return LOW_POWER_BOOT;
+}
+
+int arch_cpu_init(void)
+{
+   return 0;
+}
+
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+int board_postclk_init(void)
+{
+   return 0;
+}
+#endif
+
+#define UNLOCK_WORD0 0xC520 /* 1st unlock word */
+#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
+#define REFRESH_WORD0 0xA602 /* 1st refresh word */
+#define REFRESH_WORD1 0xB480 /* 2nd refresh word */
+
+static void disable_wdog(u32 wdog_base)
+{
+   writel(UNLOCK_WORD0, (wdog_base + 0x04));
+   writel(UNLOCK_WORD1, (wdog_base + 0x04));
+   writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
+   writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
+   writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
+
+   writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
+   writel(REFRESH_WORD1, (wdog_base + 0x04));
+}
+
+void init_wdog(void)
+{
+   /*
+* ROM will configure WDOG1, disable it or enable it
+* depending on FUSE. The update bit is set for reconfigurable.
+* We have to use unlock sequence to reconfigure it.
+* WDOG2 is not touched by ROM, so it will have default value
+* which is enabled. We can directly configure it.
+* To simplify the codes, we still use same reconfigure
+* process as WDOG1. Because the update bit is not set for
+* WDOG2, the unlock sequence won't take effect really.
+* It actually directly configure the wdog.
+* In this function, we will disable both WDOG1 and WDOG2,
+* and set update bit for both. So that kernel can reconfigure them.
+*/
+   disable_wdog(WDG1_RBASE);
+   disable_wdog(WDG2_RBASE);
+}
+
+
+void s_init(void)
+{
+   /* Disable wdog */
+   init_wdog();
+
+   /* clock configuration. */
+   clock_init();
+
+   return;
+}
+
+#ifndef CONFIG_ULP_WATCHDOG
+void reset_cpu(ulong addr)
+{
+   setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET);
+   while (1)
+   ;
+}
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+const char 

Re: [U-Boot] [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system initialization

[Z.Q. Hou]

> -Original Message-
> From: Zhiqiang Hou [mailto:zhiqiang@nxp.com]
> Sent: 2016年12月27日 15:36
> To: u-boot@lists.denx.de; albert.u.b...@aribaud.net; york sun
> ; Mingkai Hu ; Prabhakar
> Kushwaha ; Calvin Johnson
> 
> Cc: Z.Q. Hou 
> Subject: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system 
> initialization
> 
> From: Hou Zhiqiang 
> 
> Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A,
> LS1046A and LS1012A. But the clocks tree has a lot of differences, for 
> instance,
> the IP modules have different dividers to derive its clock from Platform PLL.
> And the core cluster PLL and platform PLL maybe have different reference
> clocks, such as LS1012A. Another problem is which clock/PLL should be
> described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2.
> 
> This patch is to bind the sys_info->freq_systembus to the Platform PLL, and
> handle the different divider of IP modules separately between different SoCs,
> and separate reference clocks of core cluster PLL and platform PLL.
> 
> Signed-off-by: Hou Zhiqiang 
> ---
> V3:
>  - Generate the patch set base on the latest
> git://git.denx.de/u-boot-fsl-qoriq.git.
>  - Use the Kconfig instead of header file to add CONFIG_*
> 
>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig  | 76
> ++
>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c|  3 +-
>  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 68
> ++-  .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |
> 1 +
>  include/configs/ls1012a_common.h   |  6 +-
>  include/configs/ls1043a_common.h   |  3 +-
>  include/configs/ls1046a_common.h   |  3 +-
>  include/configs/ls2080aqds.h   |  2 -
>  include/configs/ls2080ardb.h   |  1 -
>  9 files changed, 134 insertions(+), 29 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index cc0dc88..de1e5a4 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -87,6 +87,82 @@ config MAX_CPUS
> cores, count the reserved ports. This will allocate enough memory
> in spin table to properly handle all cores.
> 
> +menu "Layerscape clock tree configuration"
> + depends on FSL_LSCH2 || FSL_LSCH3
> +
> +config SYS_FSL_CLK
> + bool "Enable clock tree initialization"
> + default y
> +
> +config CLUSTER_CLK_FREQ
> + int "Reference clock of core cluster"
> + depends on ARCH_LS1012A
> + default 1
> + help
> +   This number is the reference clock frequency of core PLL.
> +   For most platforms, the core PLL and Platform PLL have the same
> +   reference clock, but for some platforms, LS1012A for instance,
> +   they are provided sepatately.
> +
> +config SYS_FSL_PCLK_DIV
> + int "Platform clock divider"
> + default 1 if ARCH_LS1043A
> + default 1 if ARCH_LS1046A
> + default 2
> + help
> +   This is the divider that is used to derive Platform clock from
> +   Platform PLL, in another word:
> + Platform_clk = Platform_PLL_freq / this_divider
> +
> +config SYS_FSL_DSPI_CLK_DIV
> + int "DSPI clock divider"
> + default 1 if ARCH_LS1043A
> + default 2
> + help
> +   This is the divider that is used to derive DSPI clock from Platform
> +   PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.

There is a description error, the IP modules' clock should be derived from 
Platform clock instead of Platform PLL. Will fix next version.

> +
> +config SYS_FSL_DUART_CLK_DIV
> + int "DUART clock divider"
> + default 1 if ARCH_LS1043A
> + default 2
> + help
> +   This is the divider that is used to derive DUART clock from Platform
> +   PLL, in another word DUART_clk = Platform_PLL_freq / this_divider.
> +
> +config SYS_FSL_I2C_CLK_DIV
> + int "I2C clock divider"
> + default 1 if ARCH_LS1043A
> + default 2
> + help
> +   This is the divider that is used to derive I2C clock from Platform
> +   PLL, in another word I2C_clk = Platform_PLL_freq / this_divider.
> +
> +config SYS_FSL_IFC_CLK_DIV
> + int "IFC clock divider"
> + default 1 if ARCH_LS1043A
> + default 2
> + help
> +   This is the divider that is used to derive IFC clock from Platform
> +   PLL, in another word IFC_clk = Platform_PLL_freq / this_divider.
> +
> +config SYS_FSL_LPUART_CLK_DIV
> + int "LPUART clock divider"
> + default 1 if ARCH_LS1043A
> + default 2
> + help
> +   This is the divider that is used to derive LPUART clock from Platform
> +   PLL, in another word LPUART_clk = Platform_PLL_freq / this_divider.
> +
> +config 

[U-Boot] [PATCH V2 14/20] serial: lpuart: restructure lpuart driver

[Peng Fan]

Drop CONFIG_LPUART_32B_REG.
Move the register structure to a common file include/fsl_lpuart.h
Define lpuart_serial_platdata structure which includes the reg base and flags.
For 32Bit register access, use lpuart_read32/lpuart_write32 which handles
big/little endian.
For 8Bit register access, still use the orignal code.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Bhuvanchandra DV 
Cc: York Sun 
Cc: Shaohui Xie 
Cc: Alison Wang 
---

V2:
 New. I do not have vf610 and LSx board, please help test if you have the board.

 arch/arm/cpu/armv7/vf610/generic.c |   5 +
 .../arm/include/asm/arch-fsl-layerscape/imx-regs.h |  42 
 arch/arm/include/asm/arch-ls102xa/imx-regs.h   |  40 ---
 arch/arm/include/asm/arch-vf610/clock.h|   1 +
 arch/arm/include/asm/arch-vf610/imx-regs.h |  28 ---
 drivers/serial/serial_lpuart.c | 267 +++--
 6 files changed, 148 insertions(+), 235 deletions(-)

diff --git a/arch/arm/cpu/armv7/vf610/generic.c 
b/arch/arm/cpu/armv7/vf610/generic.c
index 50eb0c6..0328096 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -204,6 +204,11 @@ static u32 get_dspi_clk(void)
return get_ipg_clk();
 }
 
+u32 get_lpuart_clk(void)
+{
+   return get_uart_clk();
+}
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
switch (clk) {
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h 
b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
index 57e417b..b0e58ca 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
@@ -10,46 +10,4 @@
 
 #define I2C_QUIRK_REG  /* enable 8-bit driver */
 
-#ifdef CONFIG_FSL_LPUART
-#ifdef CONFIG_LPUART_32B_REG
-struct lpuart_fsl {
-   u32 baud;
-   u32 stat;
-   u32 ctrl;
-   u32 data;
-   u32 match;
-   u32 modir;
-   u32 fifo;
-   u32 water;
-};
-#else
-struct lpuart_fsl {
-   u8 ubdh;
-   u8 ubdl;
-   u8 uc1;
-   u8 uc2;
-   u8 us1;
-   u8 us2;
-   u8 uc3;
-   u8 ud;
-   u8 uma1;
-   u8 uma2;
-   u8 uc4;
-   u8 uc5;
-   u8 ued;
-   u8 umodem;
-   u8 uir;
-   u8 reserved;
-   u8 upfifo;
-   u8 ucfifo;
-   u8 usfifo;
-   u8 utwfifo;
-   u8 utcfifo;
-   u8 urwfifo;
-   u8 urcfifo;
-   u8 rsvd[28];
-};
-#endif
-#endif /* CONFIG_FSL_LPUART */
-
 #endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-ls102xa/imx-regs.h 
b/arch/arm/include/asm/arch-ls102xa/imx-regs.h
index f9cd75b..7190f3d 100644
--- a/arch/arm/include/asm/arch-ls102xa/imx-regs.h
+++ b/arch/arm/include/asm/arch-ls102xa/imx-regs.h
@@ -10,44 +10,4 @@
 
 #define I2C_QUIRK_REG  /* enable 8-bit driver */
 
-#ifdef CONFIG_LPUART_32B_REG
-struct lpuart_fsl {
-   u32 baud;
-   u32 stat;
-   u32 ctrl;
-   u32 data;
-   u32 match;
-   u32 modir;
-   u32 fifo;
-   u32 water;
-};
-#else
-struct lpuart_fsl {
-   u8 ubdh;
-   u8 ubdl;
-   u8 uc1;
-   u8 uc2;
-   u8 us1;
-   u8 us2;
-   u8 uc3;
-   u8 ud;
-   u8 uma1;
-   u8 uma2;
-   u8 uc4;
-   u8 uc5;
-   u8 ued;
-   u8 umodem;
-   u8 uir;
-   u8 reserved;
-   u8 upfifo;
-   u8 ucfifo;
-   u8 usfifo;
-   u8 utwfifo;
-   u8 utcfifo;
-   u8 urwfifo;
-   u8 urcfifo;
-   u8 rsvd[28];
-};
-#endif
-
 #endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-vf610/clock.h 
b/arch/arm/include/asm/arch-vf610/clock.h
index e5a5c6d..c5ba240 100644
--- a/arch/arm/include/asm/arch-vf610/clock.h
+++ b/arch/arm/include/asm/arch-vf610/clock.h
@@ -22,6 +22,7 @@ enum mxc_clock {
 
 void enable_ocotp_clk(unsigned char enable);
 unsigned int mxc_get_clock(enum mxc_clock clk);
+u32 get_lpuart_clk(void);
 
 #define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
 
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h 
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 9758323..cac68ef 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -429,34 +429,6 @@ struct fuse_bank4_regs {
u32 rsvd7[3];
 };
 
-/* UART */
-struct lpuart_fsl {
-   u8 ubdh;
-   u8 ubdl;
-   u8 uc1;
-   u8 uc2;
-   u8 us1;
-   u8 us2;
-   u8 uc3;
-   u8 ud;
-   u8 uma1;
-   u8 uma2;
-   u8 uc4;
-   u8 uc5;
-   u8 ued;
-   u8 umodem;
-   u8 uir;
-   u8 reserved;
-   u8 upfifo;
-   u8 ucfifo;
-   u8 usfifo;
-   u8 utwfifo;
-   u8 utcfifo;
-   u8 urwfifo;
-   u8 urcfifo;
-   u8 rsvd[28];
-};
-
 /* MSCM Interrupt Router */
 struct mscm_ir {
u32 ircp0ir;
diff --git a/drivers/serial/serial_lpuart.c