Re: [U-Boot] [RESEND PATCH v3 1/2] mmc: rockchip_sdhci: add clock init for mmc

[Jaehoon Chung]

Hi

On 12/29/2016 09:53 AM, Kever Yang wrote:
> Hi Stefan,
> 
> Thanks for your review comment.
> On 12/29/2016 02:35 AM, Stefan Herbrechtsmeier wrote:
>> Hi,
>>
>> Am 28.12.2016 um 12:01 schrieb Jaehoon Chung:
>>> On 12/28/2016 12:32 PM, Kever Yang wrote:
 Init the clock rate to max-frequency from dts with clock driver api.

 Signed-off-by: Kever Yang 
>>> Reviewed-by: Jaehoon Chung 
>> This is an incorrect use of the max-frequency property.
>>
>> The max-frequency value limit the output clock of the mmc interface and 
>> depends on the controller, circuit (level shifter), board and so on. It 
>> doesn't represents the clock frequency of the controller.
>>
>> The clock setup inside the clock framework should use the 
>> assigned-clock-rates property. The mmc driver should only enable the clock 
>> and pass the clock rate together with the max-frequency to the mmc framework.
> 
> I'm not good at mmc controller and driver framework, but seems that the sdhci 
> core treats the max-frequency as the clock input from clock module, right?
> What if the mmc controller max-frequency is not equal to the clock module 
> output which is possible? Does kernel deal with this, and how.

If my understanding is right, some controller should be broken the CLOCK_BASE 
capability. (Refer to Linux kernel)
And then they needs to get value from CMU.

host->max_clk should be used the card's maximum value.

In Linux Kernel's case
if max_frequency property is defined, assigned to mmc->f_max
and host->f_max is assigned to clk_get_rate() value. (If Broken clock_base 
capability)
And check "mmc->f_max > host->f_max" or "mmc->f_max == 0"
if true
then mmc->_f_max = f_max;
else
then mmc->f_max is used to "max_frequency" value.

In Conclusion,
host's maximum value is used. ("max_frequency" property is used to 
QUIRK_BROKEN_CAP_CLOCK_BASE in Linux kernel.)

Kever's patch is not problem.

Best Regards,
Jaehoon Chung

> 
> Thanks,
> - Kever
>>
>> Regards,
>>   Stefan
>>
>>
>>
>>
> 
> 
> 
> 
> 

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[U-Boot] [PATCH v2 17/30] arm: socfpga: arria10: update dwmac reset function to support Arria10

[Chee Tien Fong]

From: Dinh Nguyen 

On the Arria10, the EMAC phy mode configuration for each EMACs is located
in separate registers versus being in 1 register for the GEN5 devices. The
Arria10 also has 3 EMACs compared to 2 for the GEN5 devices.

Update the dwmac_deassert_reset function to support both GEN5 and Arria10
devices.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/include/mach/system_manager.h |  4 +---
 arch/arm/mach-socfpga/misc.c| 14 ++
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 9ca889a..831ba4a 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -133,9 +133,7 @@ struct socfpga_system_manager {
u32  usb0_l3master;
u32  usb1_l3master;
u32  emac_global;
-   u32  emac0;
-   u32  emac1;
-   u32  emac2;
+   u32  emac[3];
u32  _pad_0x50_0x5f[4];
u32  fpgaintf_en_global;
u32  fpgaintf_en_0;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index c97caea..510aa1d 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -21,7 +21,11 @@
 #include 
 #include 
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
+#else
+#include 
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -95,15 +99,25 @@ static void dwmac_deassert_reset(const unsigned int 
of_reset_id,
} else if (of_reset_id == EMAC1_RESET) {
physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
reset = SOCFPGA_RESET(EMAC1);
+#ifndef CONFIG_TARGET_SOCFPGA_GEN5
+   } else if (of_reset_id == EMAC2_RESET) {
+   reset = SOCFPGA_RESET(EMAC2);
+#endif
} else {
printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
return;
}
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* configure to PHY interface select choosed */
clrsetbits_le32(_regs->emacgrp_ctrl,
SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
phymode << physhift);
+#else
+   clrsetbits_le32(_regs->emac[of_reset_id - EMAC0_RESET],
+   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
+   phymode);
+#endif
 
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
-- 
2.2.2

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[U-Boot] [PATCH v2 16/30] arm: socfpga: add reset manager defines for Arria10

[Chee Tien Fong]

From: Dinh Nguyen 

Add the Arria10 reset manager defines that is used in Linux. Change the
license to SPDX.

[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]

Signed-off-by: Dinh Nguyen 
---
 include/dt-bindings/reset/altr,rst-mgr-a10.h | 103 +++
 1 file changed, 103 insertions(+)
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h

diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h 
b/include/dt-bindings/reset/altr,rst-mgr-a10.h
new file mode 100644
index 000..7619ca2
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-a10.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Steffen Trumtrar 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+
+/* MPUMODRST */
+#define CPU0_RESET 0
+#define CPU1_RESET 1
+#define WDS_RESET  2
+#define SCUPER_RESET   3
+
+/* PER0MODRST */
+#define EMAC0_RESET32
+#define EMAC1_RESET33
+#define EMAC2_RESET34
+#define USB0_RESET 35
+#define USB1_RESET 36
+#define NAND_RESET 37
+#define QSPI_RESET 38
+#define SDMMC_RESET39
+#define EMAC0_OCP_RESET40
+#define EMAC1_OCP_RESET41
+#define EMAC2_OCP_RESET42
+#define USB0_OCP_RESET 43
+#define USB1_OCP_RESET 44
+#define NAND_OCP_RESET 45
+#define QSPI_OCP_RESET 46
+#define SDMMC_OCP_RESET47
+#define DMA_RESET  48
+#define SPIM0_RESET49
+#define SPIM1_RESET50
+#define SPIS0_RESET51
+#define SPIS1_RESET52
+#define DMA_OCP_RESET  53
+#define EMAC_PTP_RESET 54
+/* 55 is empty*/
+#define DMAIF0_RESET   56
+#define DMAIF1_RESET   57
+#define DMAIF2_RESET   58
+#define DMAIF3_RESET   59
+#define DMAIF4_RESET   60
+#define DMAIF5_RESET   61
+#define DMAIF6_RESET   62
+#define DMAIF7_RESET   63
+
+/* PER1MODRST */
+#define L4WD0_RESET64
+#define L4WD1_RESET65
+#define L4SYSTIMER0_RESET  66
+#define L4SYSTIMER1_RESET  67
+#define SPTIMER0_RESET 68
+#define SPTIMER1_RESET 69
+/* 70-71 is reserved */
+#define I2C0_RESET 72
+#define I2C1_RESET 73
+#define I2C2_RESET 74
+#define I2C3_RESET 75
+#define I2C4_RESET 76
+/* 77-79 is reserved */
+#define UART0_RESET80
+#define UART1_RESET81
+/* 82-87 is reserved */
+#define GPIO0_RESET88
+#define GPIO1_RESET89
+#define GPIO2_RESET90
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET 96
+#define LWHPS2FPGA_RESET   97
+#define FPGA2HPS_RESET 98
+#define F2SSDRAM0_RESET99
+#define F2SSDRAM1_RESET100
+#define F2SSDRAM2_RESET101
+#define DDRSCH_RESET   102
+
+/* SYSMODRST*/
+#define ROM_RESET  128
+#define OCRAM_RESET129
+/* 130 is reserved */
+#define FPGAMGR_RESET  131
+#define S2F_RESET  132
+#define SYSDBG_RESET   133
+#define OCRAM_OCP_RESET134
+
+/* COLDMODRST */
+#define CLKMGRCOLD_RESET   160
+/* 161-162 is reserved */
+#define S2FCOLD_RESET  163
+#define TIMESTAMPCOLD_RESET164
+#define TAPCOLD_RESET  165
+#define HMCCOLD_RESET  166
+#define IOMGRCOLD_RESET167
+
+/* NRSTMODRST */
+#define NRSTPINOE_RESET192
+
+/* DBGMODRST */
+#define DBG_RESET  224
+#endif
-- 
2.2.2

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[U-Boot] [PATCH v2 15/30] arm: socfpga: combine clrbits/setbits into a single clrsetbits

[Chee Tien Fong]

From: Dinh Nguyen 

There is no dependency on doing a separate clrbits first in the
dwmac_deassert_reset function. Combine them into a single
clrsetbits call.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/misc.c | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 2645129..c97caea 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -100,13 +100,10 @@ static void dwmac_deassert_reset(const unsigned int 
of_reset_id,
return;
}
 
-   /* Clearing emac0 PHY interface select to 0 */
-   clrbits_le32(_regs->emacgrp_ctrl,
-SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
-
/* configure to PHY interface select choosed */
-   setbits_le32(_regs->emacgrp_ctrl,
-phymode << physhift);
+   clrsetbits_le32(_regs->emacgrp_ctrl,
+   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
+   phymode << physhift);
 
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
-- 
2.2.2

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[U-Boot] [PATCH v2 14/30] arm: socfpga: arria10: remove board_init and s_init

[Chee Tien Fong]

From: Dinh Nguyen 

These functions are already in arch/arm/mach-socfpga/board.c

Signed-off-by: Dinh Nguyen 
---
 board/altera/arria10-socdk/socfpga.c | 17 -
 1 file changed, 17 deletions(-)

diff --git a/board/altera/arria10-socdk/socfpga.c 
b/board/altera/arria10-socdk/socfpga.c
index abedc22..8516633 100644
--- a/board/altera/arria10-socdk/socfpga.c
+++ b/board/altera/arria10-socdk/socfpga.c
@@ -5,20 +5,3 @@
  */
 
 #include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void)
-{
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
-   /* Address of boot parameters for ATAG (if ATAG is used) */
-   gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-   return 0;
-}
-- 
2.2.2

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[U-Boot] [PATCH v2 13/30] arm: socfpga: arria10 fpga does not have bridges mapped

[Chee Tien Fong]

From: Dinh Nguyen 

On the Arria10 device, the bridges are not mapped through the interconnect.

Signed-off-by: Dinh Nguyen 
---
 drivers/fpga/socfpga.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index f1b2f2c..bfefafd 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -278,8 +278,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
socfpga_bridges_reset(1);
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* Unmap the bridges from NIC-301 */
writel(0x1, SOCFPGA_L3REGS_ADDRESS);
+#endif
 
/* Initialize the FPGA Manager */
status = fpgamgr_program_init();
-- 
2.2.2

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[U-Boot] [PATCH v2 12/30] arm: socfpga: arria10: don't build GEN5 sdram for arria10

[Chee Tien Fong]

From: Dinh Nguyen 

The Arria10 device will not be able to re-use the GEN5 SDRAM controller,
so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig
option in drivers/ddr/altera/Kconfig.

Signed-off-by: Dinh Nguyen 
---
 drivers/Kconfig  | 2 ++
 drivers/ddr/Kconfig  | 1 +
 drivers/ddr/altera/Kconfig   | 6 ++
 include/configs/socfpga_common.h | 5 -
 4 files changed, 9 insertions(+), 5 deletions(-)
 create mode 100644 drivers/ddr/Kconfig
 create mode 100644 drivers/ddr/altera/Kconfig

diff --git a/drivers/Kconfig b/drivers/Kconfig
index e8c9e0a..0178498 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/cpu/Kconfig"
 
 source "drivers/crypto/Kconfig"
 
+source "drivers/ddr/Kconfig"
+
 source "drivers/demo/Kconfig"
 
 source "drivers/dfu/Kconfig"
diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig
new file mode 100644
index 000..b764add
--- /dev/null
+++ b/drivers/ddr/Kconfig
@@ -0,0 +1 @@
+source "drivers/ddr/altera/Kconfig"
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
new file mode 100644
index 000..9554da7
--- /dev/null
+++ b/drivers/ddr/altera/Kconfig
@@ -0,0 +1,6 @@
+config ALTERA_SDRAM
+   bool "SoCFPGA SDRAM for Arria5/Cyclone5 devices"
+   default y if TARGET_SOCFPGA_GEN5
+   help
+ This is for building the SDRAM controller for the Arria5/Cyclone5
+ devices.
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 58a6550..f6a2f8d 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -77,11 +77,6 @@
 #define CONFIG_SYS_PL310_BASE  SOCFPGA_MPUL2_ADDRESS
 
 /*
- * SDRAM controller
- */
-#define CONFIG_ALTERA_SDRAM
-
-/*
  * EPCS/EPCQx1 Serial Flash Controller
  */
 #ifdef CONFIG_ALTERA_SPI
-- 
2.2.2

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[U-Boot] [PATCH v2 09/30] arm: socfpga: add define for bootinfo bsel bit shift

[Chee Tien Fong]

From: Dinh Nguyen 

On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10,
the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that
the reading the bsel can generic.

Suggested-by: Marek Vasut 
Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/include/mach/system_manager.h | 2 ++
 arch/arm/mach-socfpga/misc.c| 4 ++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index e688c50..9ca889a 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -203,8 +203,10 @@ struct socfpga_system_manager {
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define SYSMGR_SDMMC_SMPLSEL_SHIFT 3
+#define SYSMGR_BOOTINFO_BSEL_SHIFT 0
 #else
 #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
+#define SYSMGR_BOOTINFO_BSEL_SHIFT 12
 #endif
 
 #define SYSMGR_SDMMC_DRVSEL_SHIFT  0
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index c1e5969..2645129 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -261,12 +261,12 @@ static int socfpga_fpga_id(const bool print_id)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
+   const u32 bsel = (readl(_regs->bootinfo) >>
+ SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7;
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-   const u32 bsel = readl(_regs->bootinfo) & 0x7;
puts("CPU:   Altera SoCFPGA Platform\n");
socfpga_fpga_id(1);
 #else
-   const u32 bsel = (readl(_regs->bootinfo) >> 12) & 0x7;
puts("CPU:   Altera SoCFPGA Arria 10\n");
 #endif
printf("BOOT:  %s\n", bsel_str[bsel].name);
-- 
2.2.2

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[U-Boot] [PATCH v2 08/30] arm: socfpga: arria10: add config option build for arria10

[Chee Tien Fong]

From: Dinh Nguyen 

Signed-off-by: Dinh Nguyen 
---
 arch/arm/Kconfig  |  4 ++--
 arch/arm/mach-socfpga/Kconfig | 10 ++
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d871a45..74b769f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -554,9 +554,9 @@ config ARCH_SNAPDRAGON
 config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select CPU_V7
-   select SUPPORT_SPL
+   select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
select OF_CONTROL
-   select SPL_OF_CONTROL
+   select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
select DM
select DM_SPI_FLASH
select DM_SPI
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 6991af8..d9a5178 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -31,6 +31,9 @@ config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
 
+config TARGET_SOCFPGA_ARRIA10
+   bool
+
 config TARGET_SOCFPGA_CYCLONE5
bool
select TARGET_SOCFPGA_GEN5
@@ -50,6 +53,10 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_ARRIA10_SOCDK
+   bool "Altera SOCFPGA SoCDK (Arria 10)"
+   select TARGET_SOCFPGA_ARRIA10
+
 config TARGET_SOCFPGA_DENX_MCVEVK
bool "DENX MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -86,6 +93,7 @@ endchoice
 
 config SYS_BOARD
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
@@ -98,6 +106,7 @@ config SYS_BOARD
 
 config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -111,6 +120,7 @@ config SYS_SOC
 
 config SYS_CONFIG_NAME
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+   default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
-- 
2.2.2

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[U-Boot] [PATCH v2 10/30] arm: socfpga: arria10: add reset manager for Arria10

[Chee Tien Fong]

From: Dinh Nguyen 

Add the defines for the reset manager and some basic reset functionality.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/include/mach/reset_manager.h | 65 ++
 arch/arm/mach-socfpga/reset_manager.c  | 24 +++-
 2 files changed, 88 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 2f070f2..6225118 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -15,6 +15,7 @@ void socfpga_bridges_reset(int enable);
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -28,6 +29,42 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
 };
+#else
+struct socfpga_reset_manager {
+   u32 stat;
+   u32 ramstat;
+   u32 miscstat;
+   u32 ctrl;
+   u32 hdsken;
+   u32 hdskreq;
+   u32 hdskack;
+   u32 counts;
+   u32 mpu_mod_reset;
+   u32 per_mod_reset;  /* stated as per0_mod_reset in A10 datasheet */
+   u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */
+   u32 brg_mod_reset;
+   u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */
+   u32 coldmodrst;
+   u32 nrstmodrst;
+   u32 dbgmodrst;
+   u32 mpuwarmmask;
+   u32 per0warmmask;
+   u32 per1warmmask;
+   u32 brgwarmmask;
+   u32 syswarmmask;
+   u32 nrstwarmmask;
+   u32 l3warmmask;
+   u32 tststa;
+   u32 tstscratch;
+   u32 hdsktimeout;
+   u32 hmcintr;
+   u32 hmcintren;
+   u32 hmcintrens;
+   u32 hmcintrenr;
+   u32 hmcgpout;
+   u32 hmcgpin;
+};
+#endif
 
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
@@ -55,6 +92,7 @@ struct socfpga_reset_manager {
 #define RSTMGR_BANK(_reset)\
(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 /*
  * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
  * 0 ... mpumodrst
@@ -75,6 +113,33 @@ struct socfpga_reset_manager {
 #define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 22)
 #define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
 #define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
+#else
+/*
+ * SocFPGA Arria10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ * 4 ... sysmodrst
+ */
+#define RSTMGR_EMAC0   RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1   RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2   RSTMGR_DEFINE(1, 2)
+#define RSTMGR_L4WD0   RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1   RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
+#define RSTMGR_SPTIMER0RSTMGR_DEFINE(2, 4)
+#define RSTMGR_SPTIMER1RSTMGR_DEFINE(2, 5)
+#define RSTMGR_UART0   RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1   RSTMGR_DEFINE(2, 17)
+#define RSTMGR_SPIM0   RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1   RSTMGR_DEFINE(1, 18)
+#define RSTMGR_QSPIRSTMGR_DEFINE(1, 6)
+#define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 7)
+#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
+#define RSTMGR_DDRSCH  RSTMGR_DEFINE(3, 6)
+#endif
 
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)   RSTMGR_##_name
diff --git a/arch/arm/mach-socfpga/reset_manager.c 
b/arch/arm/mach-socfpga/reset_manager.c
index b6beaa2..d0ff6c4 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -18,7 +18,9 @@ static const struct socfpga_reset_manager *reset_manager_base 
=
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
-/* Assert or de-assert SoCFPGA reset manager reset. */
+/*
+ * Assert or de-assert SoCFPGA reset manager reset.
+ */
 void socfpga_per_reset(u32 reset, int set)
 {
const void *reg;
@@ -46,13 +48,29 @@ void socfpga_per_reset(u32 reset, int set)
  * Assert reset on every peripheral but L4WD0.
  * Watchdog must be kept intact to prevent glitches
  * and/or hangs.
+ * For the Arria10, we disable all the peripherals except L4 watchdog0,
+ * L4 Timer 0, and ECC.
  */
 void socfpga_per_reset_all(void)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
 
writel(~l4wd0, _manager_base->per_mod_reset);

[U-Boot] [PATCH v2 11/30] arm: socfpga: wrap system manager functions for A5/C5 devices

[Chee Tien Fong]

From: Dinh Nguyen 

The system manager on Arria10 is not used for pin muxing duties, so wrap
these functions for GEN5 devices only.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/system_manager.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-socfpga/system_manager.c 
b/arch/arm/mach-socfpga/system_manager.c
index 75a65f3..9e1c3fd 100644
--- a/arch/arm/mach-socfpga/system_manager.c
+++ b/arch/arm/mach-socfpga/system_manager.c
@@ -19,6 +19,7 @@ static struct socfpga_system_manager *sysmgr_regs =
  * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
  * CONFIG_SYSMGR_ISWGRP_HANDOFF.
  */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void populate_sysmgr_fpgaintf_module(void)
 {
uint32_t handoff_val = 0;
@@ -83,3 +84,4 @@ void sysmgr_config_warmrstcfgio(int enable)
clrbits_le32(_regs->romcodegrp_ctrl,
 SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
 }
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
-- 
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[U-Boot] [PATCH v2 05/30] arm: socfpga: arria10: add misc functions for Arria10

[Chee Tien Fong]

From: Dinh Nguyen 

Add arch_early_init_r function. The Arria10 has a firewall protection
around the SDRAM and OCRAM. These firewalls are to be disabled in order
for U-Boot to function.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/misc.c | 51 
 1 file changed, 51 insertions(+)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index dd6b53b..c1e5969 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -30,8 +31,15 @@ static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 static struct socfpga_reset_manager *reset_manager_base =
(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
+#else
+static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
+   (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
+static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
+   (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
+#endif
 static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 
@@ -253,9 +261,14 @@ static int socfpga_fpga_id(const bool print_id)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
const u32 bsel = readl(_regs->bootinfo) & 0x7;
puts("CPU:   Altera SoCFPGA Platform\n");
socfpga_fpga_id(1);
+#else
+   const u32 bsel = (readl(_regs->bootinfo) >> 12) & 0x7;
+   puts("CPU:   Altera SoCFPGA Arria 10\n");
+#endif
printf("BOOT:  %s\n", bsel_str[bsel].name);
return 0;
 }
@@ -338,6 +351,7 @@ int arch_cpu_init(void)
return 0;
 }
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 /*
  * Convert all NIC-301 AMBA slaves from secure to non-secure
  */
@@ -461,6 +475,43 @@ int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
 
return 0;
 }
+#else
+/*
++ * This function initializes security policies to be consistent across
++ * all logic units in the Arria 10.
++ *
++ * The idea is to set all security policies to be normal, nonsecure
++ * for all units.
++ */
+static void initialize_security_policies(void)
+{
+   /* Put OCRAM in non-secure */
+   writel(0x003f, _fw_ocram_base->region0);
+   writel(0x1, _fw_ocram_base->enable);
+
+   /* Put DDR in non-secure */
+   writel(0x, _fw_ddr_l3_base->hpsregion0addr);
+   writel(0x1, _fw_ddr_l3_base->enable);
+}
+
+int arch_early_init_r(void)
+{
+   initialize_security_policies();
+
+   /* Configure the L2 controller to make SDRAM start at 0 */
+   writel(0x1, >pl310_addr_filter_start);
+
+   /* assert reset to all except L4WD0 and L4TIMER0 */
+   socfpga_per_reset_all();
+
+   /* configuring the clock based on handoff */
+   /* TODO: Add call to cm_basic_init() */
+
+   /* Add device descriptor to FPGA device table */
+   socfpga_fpga_add();
+   return 0;
+}
+#endif
 
 U_BOOT_CMD(
bridge, 2, 1, do_bridge,
-- 
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[U-Boot] [PATCH v2 07/30] arm: socfpga: arria10: add socfpga_arria10_defconfig

[Chee Tien Fong]

From: Dinh Nguyen 

Add a defconfig file for Arria10, which does not include enabling SPL.

Signed-off-by: Dinh Nguyen 
Acked-by: Marek Vasut 
---
 configs/socfpga_arria10_defconfig | 16 
 1 file changed, 16 insertions(+)
 create mode 100644 configs/socfpga_arria10_defconfig

diff --git a/configs/socfpga_arria10_defconfig 
b/configs/socfpga_arria10_defconfig
new file mode 100644
index 000..422261b
--- /dev/null
+++ b/configs/socfpga_arria10_defconfig
@@ -0,0 +1,16 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_ARRIA10=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DM_MMC=y
-- 
2.2.2

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[U-Boot] [PATCH v2 04/30] arm: socfpga: arria10: add system manager defines

[Chee Tien Fong]

From: Tien Fong Chee 

Add system manager defines for Arria10.

Signed-off-by: Dinh Nguyen 
---
 .../arm/mach-socfpga/include/mach/system_manager.h | 122 +
 1 file changed, 122 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index c45edea..e688c50 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -15,6 +15,7 @@ void sysmgr_config_warmrstcfgio(int enable);
 void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 struct socfpga_system_manager {
/* System Manager Module */
u32 siliconid1; /* 0x00 */
@@ -115,6 +116,77 @@ struct socfpga_system_manager {
u32 _pad_0x734;
u32 spim0usefpga;   /* 0x738 */
 };
+#else /* Arria10 System Manager */
+struct socfpga_system_manager {
+   u32  siliconid1;
+   u32  siliconid2;
+   u32  wddbg;
+   u32  bootinfo;
+   u32  mpu_ctrl_l2_ecc;
+   u32  _pad_0x14_0x1f[3];
+   u32  dma;
+   u32  dma_periph;
+   u32  sdmmcgrp_ctrl;
+   u32  sdmmc_l3master;
+   u32  nand_bootstrap;
+   u32  nand_l3master;
+   u32  usb0_l3master;
+   u32  usb1_l3master;
+   u32  emac_global;
+   u32  emac0;
+   u32  emac1;
+   u32  emac2;
+   u32  _pad_0x50_0x5f[4];
+   u32  fpgaintf_en_global;
+   u32  fpgaintf_en_0;
+   u32  fpgaintf_en_1;
+   u32  fpgaintf_en_2;
+   u32  fpgaintf_en_3;
+   u32  _pad_0x74_0x7f[3];
+   u32  noc_addr_remap_value;
+   u32  noc_addr_remap_set;
+   u32  noc_addr_remap_clear;
+   u32  _pad_0x8c_0x8f;
+   u32  ecc_intmask_value;
+   u32  ecc_intmask_set;
+   u32  ecc_intmask_clr;
+   u32  ecc_intstatus_serr;
+   u32  ecc_intstatus_derr;
+   u32  mpu_status_l2_ecc;
+   u32  mpu_clear_l2_ecc;
+   u32  mpu_status_l1_parity;
+   u32  mpu_clear_l1_parity;
+   u32  mpu_set_l1_parity;
+   u32  _pad_0xb8_0xbf[2];
+   u32  noc_timeout;
+   u32  noc_idlereq_set;
+   u32  noc_idlereq_clr;
+   u32  noc_idlereq_value;
+   u32  noc_idleack;
+   u32  noc_idlestatus;
+   u32  fpga2soc_ctrl;
+   u32  _pad_0xdc_0xff[9];
+   u32  tsmc_tsel_0;
+   u32  tsmc_tsel_1;
+   u32  tsmc_tsel_2;
+   u32  tsmc_tsel_3;
+   u32  _pad_0x110_0x200[60];
+   u32  romhw_ctrl;
+   u32  romcode_ctrl;
+   u32  romcode_cpu1startaddr;
+   u32  romcode_initswstate;
+   u32  romcode_initswlastld;
+   u32  _pad_0x214_0x217;
+   u32  warmram_enable;
+   u32  warmram_datastart;
+   u32  warmram_length;
+   u32  warmram_execution;
+   u32  warmram_crc;
+   u32  _pad_0x22c_0x22f;
+   u32  isw_handoff[8];
+   u32  romcode_bootromswstate[8];
+};
+#endif
 
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX(1 << 0)
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO(1 << 1)
@@ -146,4 +218,54 @@ struct socfpga_system_manager {
 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB2
 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK0x3
 
+/* For dedicated IO configuration */
+/* Voltage select enums */
+#define VOLTAGE_SEL_3V 0x0
+#define VOLTAGE_SEL_1P8V   0x1
+#define VOLTAGE_SEL_2P5V   0x2
+
+/* Input buffer enable */
+#define INPUT_BUF_DISABLE  0
+#define INPUT_BUF_1P8V 1
+#define INPUT_BUF_2P5V3V   2
+
+/* Weak pull up enable */
+#define WK_PU_DISABLE  0
+#define WK_PU_ENABLE   1
+
+/* Pull up slew rate control */
+#define PU_SLW_RT_SLOW 0
+#define PU_SLW_RT_FAST 1
+#define PU_SLW_RT_DEFAULT  PU_SLW_RT_SLOW
+
+/* Pull down slew rate control */
+#define PD_SLW_RT_SLOW 0
+#define PD_SLW_RT_FAST 1
+#define PD_SLW_RT_DEFAULT  PD_SLW_RT_SLOW
+
+/* Drive strength control */
+#define PU_DRV_STRG_DEFAULT0x10
+#define PD_DRV_STRG_DEFAULT0x10
+
+/* bit position */
+#define PD_DRV_STRG_LSB0
+#define PD_SLW_RT_LSB  5
+#define PU_DRV_STRG_LSB8
+#define PU_SLW_RT_LSB  13
+#define WK_PU_LSB  16
+#define INPUT_BUF_LSB  17
+#define BIAS_TRIM_LSB  19
+#define VOLTAGE_SEL_LSB0
+
+#define ALT_SYSMGR_NOC_H2F_SET_MSK 0x0001
+#define ALT_SYSMGR_NOC_LWH2F_SET_MSK   0x0010
+#define ALT_SYSMGR_NOC_F2H_SET_MSK 0x0100
+#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK  0x0001
+#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK  0x0010
+#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK  0x0100
+#define ALT_SYSMGR_NOC_TMO_EN_SET_MSK  0x0001
+
+#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK  0x0002
+#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK  0x0002
+
 #endif /* 

[U-Boot] [PATCH v2 06/30] arm: socfpga: arria10: add socfpga_arria10_socdk config

[Chee Tien Fong]

From: Dinh Nguyen 

Add config for the Arria10 SoC Development Kit.

Signed-off-by: Dinh Nguyen 
Acked-by: Marek Vasut 
---
 include/configs/socfpga_arria10_socdk.h | 94 +
 1 file changed, 94 insertions(+)
 create mode 100644 include/configs/socfpga_arria10_socdk.h

diff --git a/include/configs/socfpga_arria10_socdk.h 
b/include/configs/socfpga_arria10_socdk.h
new file mode 100644
index 000..577f60f
--- /dev/null
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -0,0 +1,94 @@
+/*
+ *  Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
+#define __CONFIG_SOCFGPA_ARRIA10_H__
+
+#include 
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+
+/*
+ * Memory configurations
+ */
+#define PHYS_SDRAM_1_SIZE  0x200
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY   3
+#define CONFIG_BOOTFILE"zImage"
+#define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND  "run mmcload; run mmcboot"
+#define CONFIG_LOADADDR0x0100
+#define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
+
+/*
+ * Display CPU and Board Info
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+
+#endif
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */
+#define CONFIG_ENV_OFFSET  512/* just after the MBR */
+
+/*
+ * arguments passed to the bootz command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+   "verify=n\0" \
+   "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+   "bootm ${loadaddr} - ${fdt_addr}\0" \
+   "bootimage=zImage\0" \
+   "fdt_addr=100\0" \
+   "fdtimage=socfpga.dtb\0" \
+   "fsloadcmd=ext2load\0" \
+   "bootm ${loadaddr} - ${fdt_addr}\0" \
+   "mmcroot=/dev/mmcblk0p2\0" \
+   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+   " root=${mmcroot} rw rootwait;" \
+   "bootz ${loadaddr} - ${fdt_addr}\0" \
+   "mmcload=mmc rescan;" \
+   "load mmc 0:1 ${loadaddr} ${bootimage};" \
+   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+   "qspiroot=/dev/mtdblock0\0" \
+   "qspirootfstype=jffs2\0" \
+   "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+   " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+   "bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* The rest of the configuration is shared */
+#include 
+#endif /* __CONFIG_H */
-- 
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[U-Boot] [PATCH v2 03/30] arm: socfpga: arria10: add board files for the Arria10 SoCDK

[Chee Tien Fong]

From: Dinh Nguyen 

Add minimal support for the Arria10 SoCDK.

Signed-off-by: Dinh Nguyen 
---
 board/altera/arria10-socdk/Kconfig   | 18 ++
 board/altera/arria10-socdk/Makefile  |  7 +++
 board/altera/arria10-socdk/socfpga.c | 24 
 3 files changed, 49 insertions(+)
 create mode 100644 board/altera/arria10-socdk/Kconfig
 create mode 100644 board/altera/arria10-socdk/Makefile
 create mode 100644 board/altera/arria10-socdk/socfpga.c

diff --git a/board/altera/arria10-socdk/Kconfig 
b/board/altera/arria10-socdk/Kconfig
new file mode 100644
index 000..b80cc6d
--- /dev/null
+++ b/board/altera/arria10-socdk/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_SOCFPGA_ARRIA10
+
+config SYS_CPU
+   default "armv7"
+
+config SYS_BOARD
+   default "socfpga_arria10"
+
+config SYS_VENDOR
+   default "altera"
+
+config SYS_SOC
+   default "socfpga_arria10"
+
+config SYS_CONFIG_NAME
+   default "socfpga_arria10"
+
+endif
diff --git a/board/altera/arria10-socdk/Makefile 
b/board/altera/arria10-socdk/Makefile
new file mode 100644
index 000..1d885ce
--- /dev/null
+++ b/board/altera/arria10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Altera Corporation 
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y  := socfpga.o
diff --git a/board/altera/arria10-socdk/socfpga.c 
b/board/altera/arria10-socdk/socfpga.c
new file mode 100644
index 000..abedc22
--- /dev/null
+++ b/board/altera/arria10-socdk/socfpga.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void)
+{
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+   /* Address of boot parameters for ATAG (if ATAG is used) */
+   gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+   return 0;
+}
-- 
2.2.2

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[U-Boot] [PATCH v2 01/30] arm: socfpga: arria10: add additional i2c nodes for Arria10

[Chee Tien Fong]

From: Dinh Nguyen 

Add remaining 3 I2C base addresses for the Arria10.

Signed-off-by: Dinh Nguyen 
Reviewed-by: Stefan Roese 
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index a7056d4..902c321 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -29,6 +29,9 @@
 #define SOCFPGA_MPUL2_ADDRESS  0xf000
 #define SOCFPGA_I2C0_ADDRESS   0xffc02200
 #define SOCFPGA_I2C1_ADDRESS   0xffc02300
+#define SOCFPGA_I2C2_ADDRESS   0xffc02400
+#define SOCFPGA_I2C3_ADDRESS   0xffc02500
+#define SOCFPGA_I2C4_ADDRESS   0xffc02600
 
 #define SOCFPGA_ECC_OCRAM_ADDRESS  0xff8c3000
 #define SOCFPGA_UART0_ADDRESS  0xffc02000
-- 
2.2.2

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[U-Boot] [PATCH v2 02/30] arm: socfpga: arria10: add sdram defines for Arria10

[Chee Tien Fong]

From: Dinh Nguyen 

Add the structures for the SDRAM controller on Arria10.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 +
 1 file changed, 380 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_a10.h

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_a10.h 
b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
new file mode 100644
index 000..0403531
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) 2015 Altera Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef_SOCFPGA_SDRAM_A10_H_
+#define_SOCFPGA_SDRAM_A10_H_
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_ecc_hmc {
+   u32 ip_rev_id;
+   u32 _pad_0x4_0x7;
+   u32 ddrioctrl;
+   u32 ddrcalstat;
+   u32 mpr_0beat1;
+   u32 mpr_1beat1;
+   u32 mpr_2beat1;
+   u32 mpr_3beat1;
+   u32 mpr_4beat1;
+   u32 mpr_5beat1;
+   u32 mpr_6beat1;
+   u32 mpr_7beat1;
+   u32 mpr_8beat1;
+   u32 mpr_0beat2;
+   u32 mpr_1beat2;
+   u32 mpr_2beat2;
+   u32 mpr_3beat2;
+   u32 mpr_4beat2;
+   u32 mpr_5beat2;
+   u32 mpr_6beat2;
+   u32 mpr_7beat2;
+   u32 mpr_8beat2;
+   u32 _pad_0x58_0x5f[2];
+   u32 auto_precharge;
+   u32 _pad_0x64_0xff[39];
+   u32 eccctrl;
+   u32 eccctrl2;
+   u32 _pad_0x108_0x10f[2];
+   u32 errinten;
+   u32 errintens;
+   u32 errintenr;
+   u32 intmode;
+   u32 intstat;
+   u32 diaginttest;
+   u32 modstat;
+   u32 derraddra;
+   u32 serraddra;
+   u32 _pad_0x134_0x137;
+   u32 autowb_corraddr;
+   u32 serrcntreg;
+   u32 autowb_drop_cntreg;
+   u32 _pad_0x144_0x147;
+   u32 ecc_reg2wreccdatabus;
+   u32 ecc_rdeccdata2regbus;
+   u32 ecc_reg2rdeccdatabus;
+   u32 _pad_0x154_0x15f[3];
+   u32 ecc_diagon;
+   u32 ecc_decstat;
+   u32 _pad_0x168_0x16f[2];
+   u32 ecc_errgenaddr_0;
+   u32 ecc_errgenaddr_1;
+   u32 ecc_errgenaddr_2;
+   u32 ecc_errgenaddr_3;
+};
+
+struct socfpga_noc_ddr_scheduler {
+   u32 ddr_t_main_scheduler_id_coreid;
+   u32 ddr_t_main_scheduler_id_revisionid;
+   u32 ddr_t_main_scheduler_ddrconf;
+   u32 ddr_t_main_scheduler_ddrtiming;
+   u32 ddr_t_main_scheduler_ddrmode;
+   u32 ddr_t_main_scheduler_readlatency;
+   u32 _pad_0x20_0x34[8];
+   u32 ddr_t_main_scheduler_activate;
+   u32 ddr_t_main_scheduler_devtodev;
+};
+
+/*
+ * OCRAM firewall
+ */
+struct socfpga_noc_fw_ocram {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 region0;
+   u32 region1;
+   u32 region2;
+   u32 region3;
+   u32 region4;
+   u32 region5;
+};
+
+/* for master such as MPU and FPGA */
+struct socfpga_noc_fw_ddr_mpu_fpga2sdram {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 _pad_0xc_0xf;
+   u32 mpuregion0addr;
+   u32 mpuregion1addr;
+   u32 mpuregion2addr;
+   u32 mpuregion3addr;
+   u32 fpga2sdram0region0addr;
+   u32 fpga2sdram0region1addr;
+   u32 fpga2sdram0region2addr;
+   u32 fpga2sdram0region3addr;
+   u32 fpga2sdram1region0addr;
+   u32 fpga2sdram1region1addr;
+   u32 fpga2sdram1region2addr;
+   u32 fpga2sdram1region3addr;
+   u32 fpga2sdram2region0addr;
+   u32 fpga2sdram2region1addr;
+   u32 fpga2sdram2region2addr;
+   u32 fpga2sdram2region3addr;
+};
+
+/* for L3 master */
+struct socfpga_noc_fw_ddr_l3 {
+   u32 enable;
+   u32 enable_set;
+   u32 enable_clear;
+   u32 hpsregion0addr;
+   u32 hpsregion1addr;
+   u32 hpsregion2addr;
+   u32 hpsregion3addr;
+   u32 hpsregion4addr;
+   u32 hpsregion5addr;
+   u32 hpsregion6addr;
+   u32 hpsregion7addr;
+};
+
+struct socfpga_io48_mmr {
+   u32 dbgcfg0;
+   u32 dbgcfg1;
+   u32 dbgcfg2;
+   u32 dbgcfg3;
+   u32 dbgcfg4;
+   u32 dbgcfg5;
+   u32 dbgcfg6;
+   u32 reserve0;
+   u32 reserve1;
+   u32 reserve2;
+   u32 ctrlcfg0;
+   u32 ctrlcfg1;
+   u32 ctrlcfg2;
+   u32 ctrlcfg3;
+   u32 ctrlcfg4;
+   u32 ctrlcfg5;
+   u32 ctrlcfg6;
+   u32 ctrlcfg7;
+   u32 ctrlcfg8;
+   u32 ctrlcfg9;
+   u32 dramtiming0;
+   u32 dramodt0;
+   u32 dramodt1;
+   u32 sbcfg0;
+   u32 sbcfg1;
+   u32 sbcfg2;
+   u32 sbcfg3;
+   u32 sbcfg4;
+   u32 sbcfg5;
+   u32 sbcfg6;
+   u32 sbcfg7;
+   u32 caltiming0;
+   u32 caltiming1;
+   u32 caltiming2;
+   u32 caltiming3;
+   u32 caltiming4;
+   u32 caltiming5;
+   u32 caltiming6;
+   u32 caltiming7;
+   u32 caltiming8;
+   u32 caltiming9;
+   u32 caltiming10;
+   u32 dramaddrw;
+   u32 sideband0;
+   u32 sideband1;
+ 

Re: [U-Boot] [RESEND PATCH v3 1/2] mmc: rockchip_sdhci: add clock init for mmc

[Kever Yang]

Hi Stefan,

Thanks for your review comment.
On 12/29/2016 02:35 AM, Stefan Herbrechtsmeier wrote:

Hi,

Am 28.12.2016 um 12:01 schrieb Jaehoon Chung:

On 12/28/2016 12:32 PM, Kever Yang wrote:

Init the clock rate to max-frequency from dts with clock driver api.

Signed-off-by: Kever Yang 

Reviewed-by: Jaehoon Chung 

This is an incorrect use of the max-frequency property.

The max-frequency value limit the output clock of the mmc interface 
and depends on the controller, circuit (level shifter), board and so 
on. It doesn't represents the clock frequency of the controller.


The clock setup inside the clock framework should use the 
assigned-clock-rates property. The mmc driver should only enable the 
clock and pass the clock rate together with the max-frequency to the 
mmc framework.


I'm not good at mmc controller and driver framework, but seems that the 
sdhci core treats the max-frequency as the clock input from clock 
module, right?
What if the mmc controller max-frequency is not equal to the clock 
module output which is possible? Does kernel deal with this, and how.


Thanks,
- Kever


Regards,
  Stefan







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Re: [U-Boot] [PATCH v2 21/30] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

[Marek Vasut]

On 12/28/2016 07:34 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee 
> 
> Enhanced defconfig file for Arria10 to enable SPL build and supporting
> device tree build for SDMMC.
> 
> Signed-off-by: Tien Fong Chee 
> Cc: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Chin Liang See 
> Cc: Tien Fong 
> ---
> Changes for V2
> - Removed boot header info setup since it already fixed in mainline
> ---
>  configs/socfpga_arria10_defconfig | 18 +-
>  1 file changed, 13 insertions(+), 5 deletions(-)

There's no arria10 defconfig in mainline ?
I only received patches 18/30 and on ?

> diff --git a/configs/socfpga_arria10_defconfig 
> b/configs/socfpga_arria10_defconfig
> index 422261b..755bb66 100644
> --- a/configs/socfpga_arria10_defconfig
> +++ b/configs/socfpga_arria10_defconfig
> @@ -3,14 +3,22 @@ CONFIG_ARCH_SOCFPGA=y
>  CONFIG_TARGET_SOCFPGA_ARRIA10=y
>  CONFIG_DM_GPIO=y
>  CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
> -CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk"
> +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
> +CONFIG_IDENT_STRING="socfpga_arria10"
>  # CONFIG_CMD_IMLS is not set
>  # CONFIG_CMD_FLASH is not set
>  CONFIG_CMD_GPIO=y
>  CONFIG_DWAPB_GPIO=y
> -CONFIG_DM_ETH=y
> -CONFIG_ETH_DESIGNWARE=y
>  CONFIG_SYS_NS16550=y
> -CONFIG_CADENCE_QSPI=y
> -CONFIG_DESIGNWARE_SPI=y
>  CONFIG_DM_MMC=y
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_CMD_MMC=y
> +CONFIG_USE_TINY_PRINTF=y
> +CONFIG_SPL=y
> +CONFIG_SPL_DM=y
> +CONFIG_SPL_SIMPLE_BUS=y
> +CONFIG_SPL_DM_SEQ_ALIAS=y
> +CONFIG_SPL_MMC_SUPPORT=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL_OF_LIBFDT=y
> +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
> 


-- 
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Marek Vasut
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Re: [U-Boot] [PATCH] SPL: NOR: Add CONFIG_SPL_NOR_COPY_ENTIRE_IMAGE define to enable whole image copy from NOR

[Marek Vasut]

On 12/28/2016 09:52 AM, Lukasz Majewski wrote:
> Hi Marek,
> 
>> On 12/26/2016 05:36 PM, Lukasz Majewski wrote:
>>> Hi Marek,
>>>
 On 11/29/2016 07:18 PM, Tom Rini wrote:
> On Tue, Nov 29, 2016 at 11:50:34AM +0100, Marek Vasut wrote:
>> On 11/29/2016 10:11 AM, Lukasz Majewski wrote:
>>> Hi Marek,
>>>
 On 11/28/2016 10:09 PM, Lukasz Majewski wrote:
> This define gives the possibility to copy entire image
> (including header - e.g. u-boot.img) from NOR parallel memory
> to e.g. SDRAM. The current code only supports loading the raw
> binary image (the u-boot.bin).
>
> The legacy behavior is preserved, since other board don't
> enabled this option.

 So, what's the usecase again ? ;-) 
>>>
>>> :-)
>>>
>>> The use case is to allow u-boot.img being loaded from Parallel
>>> NOR. The current code only supports u-boot.bin.
>>
>> Why is u-boot.bin (or the payload) not sufficient ? Why do you
>> need the header ?
>
> Well, the general use-case and code flow is that we load
> u-boot.img (or a FIT image) and if all else fails, fall back to
> assuming a .bin and a known address).
>
 And exactly how is that whole image useful in RAM ? Sorry, I still
 do not see it, usually you just need the executable payload,
 although even that can be left in flash most of the time.
>>>
>>> The use case is that I do want to boot from SD card/eMMC and NOR
>>> with using u-boot.img.
>>>
>>> I would like to avoid situation when for NOR I must use u-boot.bin
>>> and for eMMC u-boot.img.
>>>
>>> Such approach keeps things as simple as possible :-)
>>
>> Oh, so it allows you to detect bitrot for the content in SPI NOR ?
> 
> I do not use SPI NOR, it is parallel NOR.

Sorry, I meant parallel NOR of course.

>> It's a bit strange we had to use u-boot.bin with SPL there.
>>
> 
> This is how the legacy system behaves. It uses (by default) Parallel
> NOR for booting (with advised/provided NOR memory timings). After doing
> some measurements, it turned out that for "tunned" u-boot/SPL there
> would be the best way to copy it to ram and execute it from there (just
> like eMMC).
> 
> Hence, I would like to use u-boot.img in both booting scenarios.

I think I was mistaken yesterday, I don't think I understand why copying
the image including the header into RAM has any benefit compared to
copying just the image payload to RAM (and yes, we're
getting back to my original question).

-- 
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[U-Boot] [RFC PATCH 2/4] sunxi: add basic V3s support

[Icenowy Zheng]

Currently a working SPL for V3s can be built now.

The U-Boot main binary still cannot work.

Signed-off-by: Icenowy Zheng 
---
 arch/arm/include/asm/arch-sunxi/gpio.h |  1 +
 arch/arm/mach-sunxi/board.c|  9 +++--
 arch/arm/mach-sunxi/cpu_info.c |  2 ++
 board/sunxi/Kconfig| 13 -
 include/configs/sun8i.h|  2 ++
 5 files changed, 24 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h 
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 85a4ec3b0e..24f85206c8 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -161,6 +161,7 @@ enum sunxi_gpio_number {
 #define SUN8I_GPB_UART22
 #define SUN8I_A33_GPB_UART03
 #define SUN8I_A83T_GPB_UART0   2
+#define SUN8I_V3S_GPB_UART03
 #define SUN50I_GPB_UART0   4
 
 #define SUNXI_GPC_NAND 2
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index aa11493748..3b28478e2d 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -110,6 +110,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
+   sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
+   sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
+   sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
@@ -180,10 +184,11 @@ void s_init(void)
/* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
 #endif
 
-#if defined CONFIG_MACH_SUN6I || \
+#if (defined CONFIG_MACH_SUN6I || \
 defined CONFIG_MACH_SUN7I || \
 defined CONFIG_MACH_SUN8I || \
-defined CONFIG_MACH_SUN9I
+defined CONFIG_MACH_SUN9I) && \
+!defined CONFIG_MACH_SUN8I_V3S
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n"
diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
index f1f6fd5ba4..15f1e0e45a 100644
--- a/arch/arm/mach-sunxi/cpu_info.c
+++ b/arch/arm/mach-sunxi/cpu_info.c
@@ -87,6 +87,8 @@ int print_cpuinfo(void)
printf("CPU:   Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id());
 #elif defined CONFIG_MACH_SUN8I_H3
printf("CPU:   Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
+#elif defined CONFIG_MACH_SUN8I_V3S
+   printf("CPU:   Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id());
 #elif defined CONFIG_MACH_SUN9I
puts("CPU:   Allwinner A80 (SUN9I)\n");
 #elif defined CONFIG_MACH_SUN50I
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index c11d40ee7e..09af3537b2 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -122,6 +122,17 @@ config MACH_SUN8I_H3
select SUNXI_H3_DW_DRAM
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
+config MACH_SUN8I_V3S
+   bool "sun8i (Allwinner V3s)"
+   select CPU_V7
+   select CPU_V7_HAS_NONSEC
+   select CPU_V7_HAS_VIRT
+   select SUNXI_GEN_SUN6I
+   select SUPPORT_SPL
+   select SUNXI_H3_DW_DRAM
+   select SUNXI_H3_DRAM_DDR2
+   select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+
 config MACH_SUN9I
bool "sun9i (Allwinner A80)"
select CPU_V7
@@ -138,7 +149,7 @@ endchoice
 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
 config MACH_SUN8I
bool
-   default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || 
MACH_SUN8I_A83T
+   default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || 
MACH_SUN8I_A83T || MACH_SUN8I_V3S
 
 config DRAM_TYPE
int "sunxi dram type"
diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
index a4c3fb69e4..6ac42acaea 100644
--- a/include/configs/sun8i.h
+++ b/include/configs/sun8i.h
@@ -21,6 +21,8 @@
#define CONFIG_SUNXI_USB_PHYS   4
 #elif defined CONFIG_MACH_SUN8I_A83T
#define CONFIG_SUNXI_USB_PHYS   3
+#elif defined CONFIG_MACH_SUN8I_V3S
+   #define CONFIG_SUNXI_USB_PHYS   1
 #else
#define CONFIG_SUNXI_USB_PHYS   2
 #endif
-- 
2.11.0

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[U-Boot] [PATCH] sunxi: H3/A64: fix non-ODT setting

[Icenowy Zheng]

From: Andre Przywara 

According to Jens disabling the on-die-termination should set bit 5,
not bit 1 in the respective register. Fix this.

Reported-by: Jens Kuske 
Signed-off-by: Andre Przywara 
---
 arch/arm/mach-sunxi/dram_sun8i_h3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c 
b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index b08b8e67cc..8e2527dee1 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -347,7 +347,7 @@ static int mctl_channel_init(struct dram_para *para)
clrsetbits_le32(_ctl->datx[i].gcr, (0x3 << 4) |
(0x1 << 1) | (0x3 << 2) | (0x3 << 12) |
(0x3 << 14),
-   IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2);
+   IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x20);
 
/* AC PDR should always ON */
setbits_le32(_ctl->aciocr, 0x1 << 1);
-- 
2.11.0

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[U-Boot] [PATCH] sunxi: makes an invisible option for H3-like DRAM controllers

[Icenowy Zheng]

Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like
DesignWare DRAM controller, which do not have official free DRAM
initialization code, but can use modified dram_sun8i_h3.c.

Add a invisible option for easier DRAM initialization code reuse.

Signed-off-by: Icenowy Zheng 
---
 arch/arm/include/asm/arch-sunxi/dram.h | 2 +-
 arch/arm/mach-sunxi/Makefile   | 2 +-
 board/sunxi/Kconfig| 7 +++
 3 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/dram.h 
b/arch/arm/include/asm/arch-sunxi/dram.h
index e0be744dba..c5456658a3 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -24,7 +24,7 @@
 #include 
 #elif defined(CONFIG_MACH_SUN8I_A83T)
 #include 
-#elif defined(CONFIG_MACH_SUN8I_H3)
+#elif defined(CONFIG_SUNXI_H3_DW_DRAM)
 #include 
 #elif defined(CONFIG_MACH_SUN9I)
 #include 
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index e73114ee64..dc737db4b9 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -48,6 +48,6 @@ obj-$(CONFIG_MACH_SUN7I)  += dram_sun4i.o
 obj-$(CONFIG_MACH_SUN8I_A23)   += dram_sun8i_a23.o
 obj-$(CONFIG_MACH_SUN8I_A33)   += dram_sun8i_a33.o
 obj-$(CONFIG_MACH_SUN8I_A83T)  += dram_sun8i_a83t.o
-obj-$(CONFIG_MACH_SUN8I_H3)+= dram_sun8i_h3.o
+obj-$(CONFIG_SUNXI_H3_DW_DRAM) += dram_sun8i_h3.o
 obj-$(CONFIG_MACH_SUN9I)   += dram_sun9i.o
 endif
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index e1d4ab148f..4ddd992684 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -42,6 +42,12 @@ config SUNXI_GEN_SUN6I
separate ahb reset control registers, custom pmic bus, new style
watchdog, etc.
 
+config SUNXI_H3_DW_DRAM
+   bool
+   ---help---
+   Select this for sunxi SoCs which uses a DRAM controller like the
+   DesignWare controller used in H3, mainly SoCs after H3, which do
+   not have official open-source DRAM initialization code.
 
 choice
prompt "Sunxi SoC Variant"
@@ -113,6 +119,7 @@ config MACH_SUN8I_H3
select ARCH_SUPPORT_PSCI
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+   select SUNXI_H3_DW_DRAM
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
 config MACH_SUN9I
-- 
2.11.0

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Re: [U-Boot] [RESEND PATCH v3 1/2] mmc: rockchip_sdhci: add clock init for mmc

[Stefan Herbrechtsmeier]

Hi,

Am 28.12.2016 um 12:01 schrieb Jaehoon Chung:

On 12/28/2016 12:32 PM, Kever Yang wrote:

Init the clock rate to max-frequency from dts with clock driver api.

Signed-off-by: Kever Yang 

Reviewed-by: Jaehoon Chung 

This is an incorrect use of the max-frequency property.

The max-frequency value limit the output clock of the mmc interface and 
depends on the controller, circuit (level shifter), board and so on. It 
doesn't represents the clock frequency of the controller.


The clock setup inside the clock framework should use the 
assigned-clock-rates property. The mmc driver should only enable the 
clock and pass the clock rate together with the max-frequency to the mmc 
framework.


Regards,
  Stefan

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Re: [U-Boot] [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system initialization

[Prabhakar Kushwaha]

> -Original Message-
> From: Z.Q. Hou
> Sent: Wednesday, December 28, 2016 11:41 AM
> To: Prabhakar Kushwaha ; u-
> b...@lists.denx.de; albert.u.b...@aribaud.net; york sun ;
> Mingkai Hu ; Calvin Johnson 
> Subject: RE: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system
> initialization
> 
> Hi Prabhakar,
> 
> Thanks a lot for your comments!
> 
> > -Original Message-
> > From: Prabhakar Kushwaha
> > Sent: 2016年12月28日 12:06
> > To: Z.Q. Hou ; u-boot@lists.denx.de;
> > albert.u.b...@aribaud.net; york sun ; Mingkai Hu
> > ; Calvin Johnson 
> > Subject: RE: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system
> > initialization
> >
> >
> > > -Original Message-
> > > From: Z.Q. Hou
> > > Sent: Tuesday, December 27, 2016 3:58 PM
> > > To: Prabhakar Kushwaha ; u-
> > > b...@lists.denx.de; albert.u.b...@aribaud.net; york sun
> > > ; Mingkai Hu ; Calvin Johnson
> > > 
> > > Subject: RE: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system
> > > initialization
> > >
> > > Hi Prabhakar,
> > >
> > > Thanks a lot for your comments!
> > >
> > > > -Original Message-
> > > > From: Prabhakar Kushwaha
> > > > Sent: 2016年12月27日 16:59
> > > > To: Z.Q. Hou ; u-boot@lists.denx.de;
> > > > albert.u.b...@aribaud.net; york sun ; Mingkai Hu
> > > > ; Calvin Johnson 
> > > > Cc: Z.Q. Hou 
> > > > Subject: RE: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock
> > > > system initialization
> > > >
> > > >
> > > > > -Original Message-
> > > > > From: Zhiqiang Hou [mailto:zhiqiang@nxp.com]
> > > > > Sent: Tuesday, December 27, 2016 1:06 PM
> > > > > To: u-boot@lists.denx.de; albert.u.b...@aribaud.net; york sun
> > > > > ; Mingkai Hu ; Prabhakar
> > > > > Kushwaha ; Calvin Johnson
> > > > > 
> > > > > Cc: Z.Q. Hou 
> > > > > Subject: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system
> > > > > initialization
> > > > >
> > > > > From: Hou Zhiqiang 
> > > > >
> > > > > Up to now, there are 3 kind of SoCs under Layerscape Chassis 2,
> > > > > like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot
> > > > > of differences, for instance, the IP modules have different
> > > > > dividers to derive its clock from Platform PLL. And the core
> > > > > cluster PLL and platform PLL maybe have different reference clocks, 
> > > > > such
> > as LS1012A.
> > > > > Another problem is which clock/PLL should be described by
> > > > > sys_info->freq_systembus, it is confused in Layerscape Chissis 2.
> > > > >
> > > > > This patch is to bind the sys_info->freq_systembus to the Platform
> > > > > PLL, and handle the different divider of IP modules separately
> > > > > between different SoCs, and separate reference clocks of core
> > > > > cluster PLL and platform PLL.
> > > > >
> > > > > Signed-off-by: Hou Zhiqiang 
> > > > > ---
> > > > > V3:
> > > > >  - Generate the patch set base on the latest
> > > > > git://git.denx.de/u-boot-fsl- qoriq.git.
> > > > >  - Use the Kconfig instead of header file to add CONFIG_*
> > > > >
> > > > >  arch/arm/cpu/armv8/fsl-layerscape/Kconfig  | 76
> > > > > ++
> > > > >  arch/arm/cpu/armv8/fsl-layerscape/cpu.c|  3 +-
> > > > >  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 68
> > > > > ++-
> > > > > ++.../include/asm/arch-fsl-layerscape/immap_lsch2.h
> > > > |  1 +
> > > > >  include/configs/ls1012a_common.h   |  6 +-
> > > > >  include/configs/ls1043a_common.h   |  3 +-
> > > > >  include/configs/ls1046a_common.h   |  3 +-
> > > > >  include/configs/ls2080aqds.h   |  2 -
> > > > >  include/configs/ls2080ardb.h   |  1 -
> > > > >  9 files changed, 134 insertions(+), 29 deletions(-)
> > > > >
> > > > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > > > > b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > > > > index cc0dc88..de1e5a4 100644
> > > > > --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > > > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > > > > @@ -87,6 +87,82 @@ config MAX_CPUS
> > > > > cores, count the reserved ports. This will allocate enough 
> > > > > memory
> > > > > in spin table to properly handle all cores.
> > > > >
> > > > > +menu "Layerscape clock tree configuration"
> > > > > + depends on FSL_LSCH2 || FSL_LSCH3
> > > > > +
> > > > > +config SYS_FSL_CLK
> > > > > + bool "Enable clock tree initialization"
> > > 

[U-Boot] [PATCH 18/24] ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to Kconfig

[York Sun]

Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing
usage in ls102xa and fsl-layerscape. Remove all powerpc macros in
config header and board header files.

Signed-off-by: York Sun 
---

 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |  5 -
 arch/powerpc/include/asm/config_mpc85xx.h | 17 -
 drivers/ddr/fsl/Kconfig   | 14 ++
 include/configs/B4860QDS.h|  1 -
 include/configs/BSC9131RDB.h  |  1 -
 include/configs/MPC8349EMDS.h |  1 -
 include/configs/MPC8536DS.h   |  1 -
 include/configs/MPC8540ADS.h  |  1 -
 include/configs/MPC8541CDS.h  |  1 -
 include/configs/MPC8544DS.h   |  1 -
 include/configs/MPC8548CDS.h  |  1 -
 include/configs/MPC8555CDS.h  |  1 -
 include/configs/MPC8560ADS.h  |  1 -
 include/configs/MPC8568MDS.h  |  1 -
 include/configs/MPC8569MDS.h  |  1 -
 include/configs/MPC8572DS.h   |  1 -
 include/configs/MPC8610HPCD.h |  1 -
 include/configs/MPC8641HPCN.h |  1 -
 include/configs/P1022DS.h |  1 -
 include/configs/T1040QDS.h|  1 -
 include/configs/T104xRDB.h|  1 -
 include/configs/T4240RDB.h|  1 -
 include/configs/UCP1020.h |  1 -
 include/configs/controlcenterd.h  |  1 -
 include/configs/p1_p2_rdb_pc.h|  1 -
 include/configs/p1_twr.h  |  1 -
 include/configs/sbc8548.h |  1 -
 include/configs/sbc8641d.h|  2 --
 include/configs/socrates.h|  1 -
 include/configs/t4qds.h   |  1 -
 include/configs/xpedite517x.h |  1 -
 include/configs/xpedite520x.h |  1 -
 include/configs/xpedite537x.h |  1 -
 include/configs/xpedite550x.h |  1 -
 scripts/config_whitelist.txt  |  1 -
 36 files changed, 14 insertions(+), 59 deletions(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 4b904f3..9ffb90e 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -33,10 +33,6 @@ config MAX_CPUS
  cores, count the reserved ports. This will allocate enough memory
  in spin table to properly handle all cores.
 
-config NUM_DDR_CONTROLLERS
-   int "Maximum DDR controllers"
-   default 1
-
 config SECURE_BOOT
bool"Secure Boot"
help
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index af84e40..de0b580 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -115,11 +115,6 @@ config MAX_CPUS
  cores, count the reserved ports. This will allocate enough memory
  in spin table to properly handle all cores.
 
-config NUM_DDR_CONTROLLERS
-   int "Maximum DDR controllers"
-   default 3 if ARCH_LS2080A
-   default 1
-
 config SECURE_BOOT
bool
help
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 0eaa944..dbc8d7a 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -66,7 +66,6 @@
 #elif defined(CONFIG_ARCH_P1010)
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_TSECV2
-#define CONFIG_NUM_DDR_CONTROLLERS 1
 #define CONFIG_USB_MAX_CONTROLLER_COUNT1
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  4
 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
@@ -102,7 +101,6 @@
 #elif defined(CONFIG_ARCH_P1023)
 #define CONFIG_SYS_NUM_FMAN1
 #define CONFIG_SYS_NUM_FM1_DTSEC   2
-#define CONFIG_NUM_DDR_CONTROLLERS 1
 #define CONFIG_USB_MAX_CONTROLLER_COUNT1
 #define CONFIG_SYS_QMAN_NUM_PORTALS3
 #define CONFIG_SYS_BMAN_NUM_PORTALS3
@@ -139,7 +137,6 @@
 #define CONFIG_SYS_NUM_FMAN1
 #define CONFIG_SYS_NUM_FM1_DTSEC   5
 #define CONFIG_SYS_NUM_FM1_10GEC   1
-#define CONFIG_NUM_DDR_CONTROLLERS 1
 #define CONFIG_USB_MAX_CONTROLLER_COUNT2
 #define CONFIG_SYS_FM_MURAM_SIZE   0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV   32
@@ -159,7 +156,6 @@
 #define CONFIG_SYS_NUM_FMAN1
 #define CONFIG_SYS_NUM_FM1_DTSEC   5
 #define CONFIG_SYS_NUM_FM1_10GEC   1
-#define CONFIG_NUM_DDR_CONTROLLERS 1
 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
 #define CONFIG_SYS_FM_MURAM_SIZE   0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV   32
@@ -182,7 +178,6 @@
 #define CONFIG_SYS_NUM_FM2_DTSEC   4
 #define CONFIG_SYS_NUM_FM1_10GEC   1
 #define CONFIG_SYS_NUM_FM2_10GEC   1
-#define CONFIG_NUM_DDR_CONTROLLERS 2
 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
 #define CONFIG_USB_MAX_CONTROLLER_COUNT2
 #define 

[U-Boot] [PATCH 14/24] fsl_ddr: Move DDR config options to driver Kconfig

[York Sun]

Create driver/ddr/fsl/Kconfig and move existing options. Clean up
existing macros.

Signed-off-by: York Sun 
---

 arch/arm/Kconfig  |   1 +
 arch/arm/cpu/armv7/ls102xa/Kconfig|  47 +
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |  57 ++
 arch/arm/include/asm/arch-fsl-layerscape/config.h |   4 +-
 arch/powerpc/Kconfig  |   4 +
 arch/powerpc/cpu/mpc83xx/Kconfig  |   3 +
 arch/powerpc/cpu/mpc85xx/Kconfig  |  46 
 arch/powerpc/cpu/mpc86xx/Kconfig  |   4 +
 arch/powerpc/include/asm/config.h |   3 -
 arch/powerpc/include/asm/config_mpc85xx.h |  21 
 arch/powerpc/include/asm/config_mpc86xx.h |   2 -
 configs/MPC8349EMDS_defconfig |   1 +
 configs/MPC8536DS_36BIT_defconfig |   1 +
 configs/MPC8536DS_SDCARD_defconfig|   1 +
 configs/MPC8536DS_SPIFLASH_defconfig  |   1 +
 configs/MPC8536DS_defconfig   |   1 +
 configs/MPC8548CDS_36BIT_defconfig|   1 +
 configs/MPC8548CDS_defconfig  |   1 +
 configs/MPC8548CDS_legacy_defconfig   |   1 +
 configs/MPC8572DS_36BIT_defconfig |   1 +
 configs/MPC8572DS_defconfig   |   1 +
 configs/MPC8610HPCD_defconfig |   1 +
 configs/MPC8641HPCN_36BIT_defconfig   |   1 +
 configs/MPC8641HPCN_defconfig |   1 +
 configs/T1023RDB_NAND_defconfig   |   1 +
 configs/T1023RDB_SDCARD_defconfig |   1 +
 configs/T1023RDB_SECURE_BOOT_defconfig|   1 +
 configs/T1023RDB_SPIFLASH_defconfig   |   1 +
 configs/T1023RDB_defconfig|   1 +
 configs/T1024QDS_DDR4_SECURE_BOOT_defconfig   |   2 +-
 configs/T1024QDS_DDR4_defconfig   |   2 +-
 configs/T1024QDS_NAND_defconfig   |   1 +
 configs/T1024QDS_SDCARD_defconfig |   1 +
 configs/T1024QDS_SECURE_BOOT_defconfig|   1 +
 configs/T1024QDS_SPIFLASH_defconfig   |   1 +
 configs/T1024QDS_defconfig|   1 +
 configs/T1024RDB_NAND_defconfig   |   1 +
 configs/T1024RDB_SDCARD_defconfig |   1 +
 configs/T1024RDB_SECURE_BOOT_defconfig|   1 +
 configs/T1024RDB_SPIFLASH_defconfig   |   1 +
 configs/T1024RDB_defconfig|   1 +
 configs/T1040D4RDB_NAND_defconfig |   3 +-
 configs/T1040D4RDB_SDCARD_defconfig   |   3 +-
 configs/T1040D4RDB_SECURE_BOOT_defconfig  |   2 +-
 configs/T1040D4RDB_SPIFLASH_defconfig |   3 +-
 configs/T1040D4RDB_defconfig  |   2 +-
 configs/T1040QDS_DDR4_defconfig   |   2 +-
 configs/T1040QDS_SECURE_BOOT_defconfig|   1 +
 configs/T1040QDS_defconfig|   1 +
 configs/T1040RDB_NAND_defconfig   |   1 +
 configs/T1040RDB_SDCARD_defconfig |   1 +
 configs/T1040RDB_SECURE_BOOT_defconfig|   1 +
 configs/T1040RDB_SPIFLASH_defconfig   |   1 +
 configs/T1040RDB_defconfig|   1 +
 configs/T1042D4RDB_NAND_defconfig |   3 +-
 configs/T1042D4RDB_SDCARD_defconfig   |   3 +-
 configs/T1042D4RDB_SECURE_BOOT_defconfig  |   2 +-
 configs/T1042D4RDB_SPIFLASH_defconfig |   3 +-
 configs/T1042D4RDB_defconfig  |   2 +-
 configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig|   1 +
 configs/T1042RDB_PI_NAND_defconfig|   1 +
 configs/T1042RDB_PI_SDCARD_defconfig  |   1 +
 configs/T1042RDB_PI_SPIFLASH_defconfig|   1 +
 configs/T1042RDB_PI_defconfig |   1 +
 configs/T1042RDB_SECURE_BOOT_defconfig|   1 +
 configs/T1042RDB_defconfig|   1 +
 configs/ls1046aqds_defconfig  |   1 -
 configs/ls1046aqds_nand_defconfig |   2 +-
 configs/ls1046aqds_qspi_defconfig |   1 -
 configs/ls1046aqds_sdcard_ifc_defconfig   |   2 +-
 configs/ls1046aqds_sdcard_qspi_defconfig  |   2 +-
 configs/ls1046ardb_emmc_defconfig |   2 +-
 configs/ls1046ardb_qspi_defconfig |   1 -
 configs/ls1046ardb_sdcard_defconfig   |   2 +-
 configs/ls2080a_emu_defconfig |   2 +-
 configs/ls2080aqds_SECURE_BOOT_defconfig  |   2 +-
 configs/ls2080aqds_defconfig  |   2 +-
 configs/ls2080aqds_nand_defconfig |   2 +-
 configs/ls2080aqds_qspi_defconfig |   2 +-
 configs/ls2080ardb_SECURE_BOOT_defconfig  |   2 +-
 configs/ls2080ardb_defconfig  |   3 +-
 configs/ls2080ardb_nand_defconfig 

[U-Boot] [PATCH 00/24] Lift mpc85xx config options to Kconfig

[York Sun]

In this set, more mpc85xx config options are moved into Kconfig, including
some shared configuration for DDR, crypto, mmc, etc.


York Sun (24):
  powerpc: E500: Move CONFIG_E500 and CONFIG_E500MC to Kconfig
  powerpc: mpc85xx: Move CONFIG_SYS_NUM_TLBCAMS to Kconfig
  powerpc: mpc85xx: Move CONFIG_SYS_PPC_E500_DEBUG_TLB to Kconfig
  crypto: Move SYS_FSL_SEC_COMPAT into driver Kconfig
  crypto: Move CONFIG_SYS_FSL_SEC_LE and _BE to Kconfig
  powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014
  powerpc: T1023RDB: Remove macro CONFIG_T1023RDB
  powerpc: T1024RDB: Remove macro CONFIG_T1024RDB
  powerpc: T1040QDS: Remove macro CONFIG_T1040QDS
  powerpc: T2080QDS: Remove macro T2080QDS
  powerpc: T2080RDB: Remove macro CONFIG_T2080RDB
  powerpc: T2081QDS: Remove macro T2081QDS
  powerpc: T104xQDS: Remove macro CONFIG_T104xD4QDS
  fsl_ddr: Move DDR config options to driver Kconfig
  arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig
  mmc: move CONFIG_SYS_FSL_ERRATUM_ESDHC* to Kconfig
  powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig
  ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to Kconfig
  ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and
CONFIG_SYS_NUM_DDR_CTRLS
  ddr: fsl: Move CONFIG_SYS_FSL_DDR_VER to Kconfig
  powerpc: mpc85xx: Remove unused ifdef in config header
  powerpc: E6500: Move macro CONFIG_E6500 to Kconfig
  powerpc: mpc85xx: Move CONFIG_SYS_FSL_QORIQ_CHASSIS* to Kconfig
  powerpc: mpc85xx: Move macro CONFIG_SYS_PPC64 to Kconfig

 README|   9 -
 arch/arm/Kconfig  |  14 +
 arch/arm/cpu/armv7/ls102xa/Kconfig|  61 +-
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |  87 ++-
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  30 +-
 arch/arm/include/asm/arch-ls102xa/config.h|   6 -
 arch/powerpc/Kconfig  |   7 +
 arch/powerpc/cpu/mpc83xx/Kconfig  |   6 +
 arch/powerpc/cpu/mpc85xx/Kconfig  | 648 +-
 arch/powerpc/cpu/mpc85xx/Makefile |   4 -
 arch/powerpc/cpu/mpc85xx/cmd_errata.c |   2 +-
 arch/powerpc/cpu/mpc85xx/cpu.c|  22 +-
 arch/powerpc/cpu/mpc85xx/cpu_init.c   |  18 +-
 arch/powerpc/cpu/mpc86xx/Kconfig  |   4 +
 arch/powerpc/include/asm/config.h |  11 -
 arch/powerpc/include/asm/config_mpc85xx.h | 331 +--
 arch/powerpc/include/asm/config_mpc86xx.h |   2 -
 arch/powerpc/include/asm/fsl_secure_boot.h|   7 +-
 arch/powerpc/include/asm/immap_85xx.h |   6 +-
 board/freescale/b4860qds/ddr.c|   4 +-
 board/freescale/corenet_ds/ddr.c  |   6 +-
 board/freescale/t102xrdb/Makefile |   2 +-
 board/freescale/t102xrdb/ddr.c|   2 +-
 board/freescale/t102xrdb/eth_t102xrdb.c   |  10 +-
 board/freescale/t102xrdb/t102xrdb.c   |  22 +-
 board/freescale/t102xrdb/t102xrdb.h   |   2 +-
 board/freescale/t208xqds/Makefile |   4 +-
 board/freescale/t208xqds/eth_t208xqds.c   |  32 +-
 board/freescale/t208xqds/t208xqds.c   |   8 +-
 board/freescale/t208xrdb/Makefile |   2 +-
 configs/MPC8349EMDS_defconfig |   1 +
 configs/MPC8536DS_36BIT_defconfig |   1 +
 configs/MPC8536DS_SDCARD_defconfig|   1 +
 configs/MPC8536DS_SPIFLASH_defconfig  |   1 +
 configs/MPC8536DS_defconfig   |   1 +
 configs/MPC8548CDS_36BIT_defconfig|   1 +
 configs/MPC8548CDS_defconfig  |   1 +
 configs/MPC8548CDS_legacy_defconfig   |   1 +
 configs/MPC8572DS_36BIT_defconfig |   1 +
 configs/MPC8572DS_defconfig   |   1 +
 configs/MPC8610HPCD_defconfig |   1 +
 configs/MPC8641HPCN_36BIT_defconfig   |   1 +
 configs/MPC8641HPCN_defconfig |   1 +
 configs/T1023RDB_NAND_defconfig   |   3 +-
 configs/T1023RDB_SDCARD_defconfig |   3 +-
 configs/T1023RDB_SECURE_BOOT_defconfig|   2 +-
 configs/T1023RDB_SPIFLASH_defconfig   |   3 +-
 configs/T1023RDB_defconfig|   2 +-
 configs/T1024QDS_DDR4_SECURE_BOOT_defconfig   |   2 +-
 configs/T1024QDS_DDR4_defconfig   |   2 +-
 configs/T1024QDS_NAND_defconfig   |   1 +
 configs/T1024QDS_SDCARD_defconfig |   1 +
 configs/T1024QDS_SECURE_BOOT_defconfig|   1 +
 configs/T1024QDS_SPIFLASH_defconfig   |   1 +
 configs/T1024QDS_defconfig|   1 +
 configs/T1024RDB_NAND_defconfig   |   3 +-
 configs/T1024RDB_SDCARD_defconfig |   3 +-
 configs/T1024RDB_SECURE_BOOT_defconfig|   2 +-
 

[U-Boot] [PATCH 05/24] crypto: Move CONFIG_SYS_FSL_SEC_LE and _BE to Kconfig

[York Sun]

Use Kconfig option to set little- or big-endian access to secure
boot and trust architecture.

Signed-off-by: York Sun 
---

 arch/arm/Kconfig  |  2 ++
 arch/arm/cpu/armv7/ls102xa/Kconfig|  1 +
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |  2 ++
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  4 ---
 arch/arm/include/asm/arch-ls102xa/config.h|  1 -
 arch/powerpc/Kconfig  |  1 +
 arch/powerpc/cpu/mpc85xx/Kconfig  | 35 +++
 arch/powerpc/include/asm/config.h |  7 -
 arch/powerpc/include/asm/config_mpc85xx.h |  1 -
 drivers/crypto/fsl/Kconfig|  6 
 include/configs/mx6_common.h  |  1 -
 include/configs/mx7_common.h  |  1 -
 include/fsl_sec.h |  2 +-
 scripts/config_whitelist.txt  |  2 --
 14 files changed, 48 insertions(+), 18 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ff601ea..15a6233 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -466,12 +466,14 @@ config ARCH_MX7
select CPU_V7
select SYS_FSL_HAS_SEC if SECURE_BOOT
select SYS_FSL_SEC_COMPAT_4
+   select SYS_FSL_SEC_LE
 
 config ARCH_MX6
bool "Freescale MX6"
select CPU_V7
select SYS_FSL_HAS_SEC if SECURE_BOOT
select SYS_FSL_SEC_COMPAT_4
+   select SYS_FSL_SEC_LE
 
 config ARCH_MX5
bool "Freescale MX5"
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index e233aa4..d154f7b 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -7,6 +7,7 @@ config ARCH_LS1021A
select SYS_FSL_DDR_VER_50
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
+   select SYS_FSL_SEC_LE
 
 menu "LS102xA architecture"
depends on ARCH_LS1021A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 17b470d..a1f781e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -31,12 +31,14 @@ config ARCH_LS2080A
select SYS_FSL_HAS_DP_DDR
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
+   select SYS_FSL_SEC_LE
select SYS_FSL_SRDS_2
 
 config FSL_LSCH2
bool
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
+   select SYS_FSL_SEC_BE
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index f4f9eaa..29fc33d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -55,9 +55,6 @@
 #define CONFIG_SYS_FSL_SFP_LE
 #define CONFIG_SYS_FSL_SRK_LE
 
-/* SEC */
-#define CONFIG_SYS_FSL_SEC_LE
-
 /* Security Monitor */
 #define CONFIG_SYS_FSL_SEC_MON_LE
 
@@ -144,7 +141,6 @@
 #define CONFIG_SYS_FSL_QSPI_BE
 #define CONFIG_SYS_FSL_CCSR_GUR_BE
 #define CONFIG_SYS_FSL_PEX_LUT_BE
-#define CONFIG_SYS_FSL_SEC_BE
 
 /* SoC related */
 #ifdef CONFIG_LS1043A
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index 97c69e9..1c5158b 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -106,7 +106,6 @@
 #define CONFIG_SYS_FSL_QSPI_BE
 #define CONFIG_SYS_FSL_DCU_BE
 #define CONFIG_SYS_FSL_SEC_MON_LE
-#define CONFIG_SYS_FSL_SEC_LE
 #define CONFIG_SYS_FSL_SFP_VER_3_2
 #define CONFIG_SYS_FSL_SFP_BE
 #define CONFIG_SYS_FSL_SRK_LE
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 9fc1d5c..853e265 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -24,6 +24,7 @@ config MPC83xx
bool "MPC83xx"
select CREATE_ARCH_SYMLINK
select SYS_FSL_HAS_SEC
+   select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
 
 config MPC85xx
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 1287ab6..f36114a 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -326,6 +326,7 @@ config ARCH_B4420
select E500MC
select FSL_LAW
select SYS_FSL_HAS_SEC
+   select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
 
 config ARCH_B4860
@@ -333,18 +334,21 @@ config ARCH_B4860
select E500MC
select FSL_LAW
select SYS_FSL_HAS_SEC
+   select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
 
 config ARCH_BSC9131
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+   select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
 
 config ARCH_BSC9132
bool
select FSL_LAW
select SYS_FSL_HAS_SEC
+   select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select 

[U-Boot] [PATCH 04/24] crypto: Move SYS_FSL_SEC_COMPAT into driver Kconfig

[York Sun]

Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC
and ARM SoCs, move it to Kconfig under the driver.

Signed-off-by: York Sun 
---

 arch/arm/Kconfig  |  4 ++
 arch/arm/cpu/armv7/ls102xa/Kconfig|  2 +
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |  4 ++
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  2 -
 arch/arm/include/asm/arch-ls102xa/config.h|  1 -
 arch/powerpc/Kconfig  |  2 +
 arch/powerpc/cpu/mpc85xx/Kconfig  | 70 +++
 arch/powerpc/include/asm/config.h |  1 -
 arch/powerpc/include/asm/config_mpc85xx.h | 30 --
 drivers/crypto/fsl/Kconfig| 33 +++
 include/configs/mx6_common.h  |  1 -
 include/configs/mx7_common.h  |  1 -
 scripts/config_whitelist.txt  |  1 -
 13 files changed, 115 insertions(+), 37 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 587f288..ff601ea 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -464,10 +464,14 @@ config ARCH_MESON
 config ARCH_MX7
bool "Freescale MX7"
select CPU_V7
+   select SYS_FSL_HAS_SEC if SECURE_BOOT
+   select SYS_FSL_SEC_COMPAT_4
 
 config ARCH_MX6
bool "Freescale MX6"
select CPU_V7
+   select SYS_FSL_HAS_SEC if SECURE_BOOT
+   select SYS_FSL_SEC_COMPAT_4
 
 config ARCH_MX5
bool "Freescale MX5"
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index f94568a..e233aa4 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -5,6 +5,8 @@ config ARCH_LS1021A
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
+   select SYS_FSL_HAS_SEC
+   select SYS_FSL_SEC_COMPAT_5
 
 menu "LS102xA architecture"
depends on ARCH_LS1021A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index cc0dc88..17b470d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -29,10 +29,14 @@ config ARCH_LS2080A
select SYS_FSL_DDR_LE
select SYS_FSL_DDR_VER_50
select SYS_FSL_HAS_DP_DDR
+   select SYS_FSL_HAS_SEC
+   select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SRDS_2
 
 config FSL_LSCH2
bool
+   select SYS_FSL_HAS_SEC
+   select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index c50894a..f4f9eaa 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -57,7 +57,6 @@
 
 /* SEC */
 #define CONFIG_SYS_FSL_SEC_LE
-#define CONFIG_SYS_FSL_SEC_COMPAT  5
 
 /* Security Monitor */
 #define CONFIG_SYS_FSL_SEC_MON_LE
@@ -135,7 +134,6 @@
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 #elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_FSL_SEC_COMPAT  5
 #define CONFIG_SYS_FSL_OCRAM_BASE  0x1000 /* initial RAM */
 #define CONFIG_SYS_FSL_OCRAM_SIZE  0x0020 /* 2M */
 
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index ec65cc0..97c69e9 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -114,7 +114,6 @@
 #define DCU_LAYER_MAX_NUM  16
 
 #ifdef CONFIG_LS102XA
-#define CONFIG_SYS_FSL_SEC_COMPAT  5
 #define CONFIG_USB_MAX_CONTROLLER_COUNT1
 #define CONFIG_SYS_FSL_ERRATUM_A008378
 #define CONFIG_SYS_FSL_ERRATUM_A009663
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 18451d3..9fc1d5c 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -23,6 +23,8 @@ config MPC8260
 config MPC83xx
bool "MPC83xx"
select CREATE_ARCH_SYMLINK
+   select SYS_FSL_HAS_SEC
+   select SYS_FSL_SEC_COMPAT_2
 
 config MPC85xx
bool "MPC85xx"
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 7f04a09..1287ab6 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -325,29 +325,41 @@ config ARCH_B4420
bool
select E500MC
select FSL_LAW
+   select SYS_FSL_HAS_SEC
+   select SYS_FSL_SEC_COMPAT_4
 
 config ARCH_B4860
bool
select E500MC
select FSL_LAW
+   select SYS_FSL_HAS_SEC
+   select SYS_FSL_SEC_COMPAT_4
 
 config ARCH_BSC9131
bool
select FSL_LAW
+   select SYS_FSL_HAS_SEC
+   select SYS_FSL_SEC_COMPAT_4
 
 config ARCH_BSC9132
bool
select FSL_LAW
+   select SYS_FSL_HAS_SEC
+   select SYS_FSL_SEC_COMPAT_4
select 

[U-Boot] [PATCH 01/24] powerpc: E500: Move CONFIG_E500 and CONFIG_E500MC to Kconfig

[York Sun]

Use Kconfig option for E500 and E500MC macros.

Signed-off-by: York Sun 
---

 arch/powerpc/cpu/mpc85xx/Kconfig| 30 ++
 include/configs/B4860QDS.h  |  3 ---
 include/configs/BSC9131RDB.h|  2 --
 include/configs/BSC9132QDS.h|  2 --
 include/configs/C29XPCIE.h  |  2 --
 include/configs/MPC8536DS.h |  4 
 include/configs/MPC8540ADS.h|  4 
 include/configs/MPC8541CDS.h|  2 --
 include/configs/MPC8544DS.h |  4 
 include/configs/MPC8548CDS.h|  4 
 include/configs/MPC8555CDS.h|  2 --
 include/configs/MPC8560ADS.h|  2 --
 include/configs/MPC8568MDS.h|  4 
 include/configs/MPC8569MDS.h|  4 
 include/configs/MPC8572DS.h |  2 --
 include/configs/P1010RDB.h  |  3 ---
 include/configs/P1022DS.h   |  2 --
 include/configs/P1023RDB.h  |  2 --
 include/configs/P2041RDB.h  |  3 ---
 include/configs/T102xQDS.h  |  3 ---
 include/configs/T102xRDB.h  |  3 ---
 include/configs/T1040QDS.h  |  3 ---
 include/configs/T104xRDB.h  |  3 ---
 include/configs/T208xQDS.h  |  3 ---
 include/configs/T208xRDB.h  |  3 ---
 include/configs/T4240RDB.h  |  3 ---
 include/configs/UCP1020.h   |  5 -
 include/configs/controlcenterd.h|  2 --
 include/configs/corenet_ds.h|  3 ---
 include/configs/cyrus.h |  3 ---
 include/configs/km/kmp204x-common.h |  3 ---
 include/configs/p1_p2_rdb_pc.h  |  4 
 include/configs/p1_twr.h|  4 
 include/configs/qemu-ppce500.h  |  4 
 include/configs/sbc8548.h   |  2 --
 include/configs/socrates.h  |  2 --
 include/configs/t4qds.h |  3 ---
 include/configs/xpedite520x.h   |  2 --
 include/configs/xpedite537x.h   |  2 --
 include/configs/xpedite550x.h   |  2 --
 scripts/config_whitelist.txt|  2 --
 41 files changed, 30 insertions(+), 115 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index e4873f5..6d8709e 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -323,10 +323,12 @@ endchoice
 
 config ARCH_B4420
bool
+   select E500MC
select FSL_LAW
 
 config ARCH_B4860
bool
+   select E500MC
select FSL_LAW
 
 config ARCH_BSC9131
@@ -419,22 +421,27 @@ config ARCH_P2020
 
 config ARCH_P2041
bool
+   select E500MC
select FSL_LAW
 
 config ARCH_P3041
bool
+   select E500MC
select FSL_LAW
 
 config ARCH_P4080
bool
+   select E500MC
select FSL_LAW
 
 config ARCH_P5020
bool
+   select E500MC
select FSL_LAW
 
 config ARCH_P5040
bool
+   select E500MC
select FSL_LAW
 
 config ARCH_QEMU_E500
@@ -442,36 +449,59 @@ config ARCH_QEMU_E500
 
 config ARCH_T1023
bool
+   select E500MC
select FSL_LAW
 
 config ARCH_T1024
bool
+   select E500MC
select FSL_LAW
 
 config ARCH_T1040
bool
+   select E500MC
select FSL_LAW
 
 config ARCH_T1042
bool
+   select E500MC
select FSL_LAW
 
 config ARCH_T2080
bool
+   select E500MC
select FSL_LAW
 
 config ARCH_T2081
bool
+   select E500MC
select FSL_LAW
 
 config ARCH_T4160
bool
+   select E500MC
select FSL_LAW
 
 config ARCH_T4240
bool
+   select E500MC
select FSL_LAW
 
+config BOOKE
+   bool
+   default y
+
+config E500
+   bool
+   default y
+   help
+   Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
+
+config E500MC
+   bool
+   help
+   Enble PowerPC E500MC core
+
 config FSL_LAW
bool
help
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 7d3ebf3..e3ed317 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -50,9 +50,6 @@
 #endif
 
 /* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500/* BOOKE e500 family */
-#define CONFIG_E500MC  /* BOOKE e500mc family */
 #define CONFIG_SYS_BOOK3E_HV   /* Category E.HV supported */
 #define CONFIG_MP  /* support multiple processors */
 
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index eecbd75..33c015a 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -46,8 +46,6 @@
 #endif
 
 /* High Level Configuration Options */
-#define CONFIG_BOOKE   /* BOOKE */
-#define CONFIG_E500/* BOOKE e500 family */
 #define CONFIG_FSL_IFC /* Enable IFC Support */
 #define CONFIG_FSL_CAAM/* Enable SEC/CAAM */
 
diff --git a/include/configs/BSC9132QDS.h 

[U-Boot] [PATCH 24/24] powerpc: mpc85xx: Move macro CONFIG_SYS_PPC64 to Kconfig

[York Sun]

Use Kconfig option SYS_PPC64 instead.

Signed-off-by: York Sun 

---

 arch/powerpc/cpu/mpc85xx/Kconfig  | 11 +++
 arch/powerpc/include/asm/config_mpc85xx.h |  5 -
 scripts/config_whitelist.txt  |  1 -
 3 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index ac6c197..53c7802 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -344,6 +344,7 @@ config ARCH_B4420
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+   select SYS_PPC64
 
 config ARCH_B4860
bool
@@ -366,6 +367,7 @@ config ARCH_B4860
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+   select SYS_PPC64
 
 config ARCH_BSC9131
bool
@@ -722,6 +724,7 @@ config ARCH_P5020
select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+   select SYS_PPC64
 
 config ARCH_P5040
bool
@@ -741,6 +744,7 @@ config ARCH_P5040
select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+   select SYS_PPC64
 
 config ARCH_QEMU_E500
bool
@@ -828,6 +832,7 @@ config ARCH_T2080
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+   select SYS_PPC64
 
 config ARCH_T2081
bool
@@ -846,6 +851,7 @@ config ARCH_T2081
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+   select SYS_PPC64
 
 config ARCH_T4160
bool
@@ -865,6 +871,7 @@ config ARCH_T4160
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+   select SYS_PPC64
 
 config ARCH_T4240
bool
@@ -885,6 +892,7 @@ config ARCH_T4240
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+   select SYS_PPC64
 
 config BOOKE
bool
@@ -1205,6 +1213,9 @@ config SYS_NUM_TLBCAMS
Number of TLB CAM entries for Book-E chips. 64 for E500MC,
16 for other E500 SoCs.
 
+config SYS_PPC64
+   bool
+
 config SYS_PPC_E500_USE_DEBUG_TLB
bool
 
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 8cde05c..6fd218a 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -172,7 +172,6 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff00
 
 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
-#define CONFIG_SYS_PPC64   /* 64-bit core */
 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
 #define CONFIG_SYS_NUM_FMAN1
@@ -191,7 +190,6 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc000
 
 #elif defined(CONFIG_ARCH_P5040)
-#define CONFIG_SYS_PPC64
 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
 #define CONFIG_SYS_NUM_FMAN2
@@ -233,7 +231,6 @@
 #define CONFIG_ESDHC_HC_BLK_ADDR
 
 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
-#define CONFIG_SYS_PPC64   /* 64-bit core */
 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
@@ -277,7 +274,6 @@
 #define CONFIG_SYS_FSL_PCI_VER_3_X
 
 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
-#define CONFIG_SYS_PPC64   /* 64-bit core */
 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
@@ -388,7 +384,6 @@
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 
 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
-#define CONFIG_SYS_PPC64   /* 64-bit core */
 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 241d047..43c5cdc 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -7134,7 +7134,6 @@ CONFIG_SYS_POST_WATCHDOG
 CONFIG_SYS_POST_WORD_ADDR
 CONFIG_SYS_POWER_MANAGER
 CONFIG_SYS_PPC4XX_USB_ADDR
-CONFIG_SYS_PPC64
 CONFIG_SYS_PPC_DDR_WIMGE
 CONFIG_SYS_PQSPAR
 CONFIG_SYS_PRELIM_OR_AM
-- 
2.7.4

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[U-Boot] [PATCH 22/24] powerpc: E6500: Move macro CONFIG_E6500 to Kconfig

[York Sun]

Use Kconfig option E6500 and clean up existing usage.

Signed-off-by: York Sun 
---

 arch/powerpc/cpu/mpc85xx/Kconfig  | 16 
 arch/powerpc/include/asm/config_mpc85xx.h |  9 -
 scripts/config_whitelist.txt  |  1 -
 3 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 7b64ae0..8b905e2 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -326,6 +326,7 @@ endchoice
 config ARCH_B4420
bool
select E500MC
+   select E6500
select FSL_LAW
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A004477
@@ -346,6 +347,7 @@ config ARCH_B4420
 config ARCH_B4860
bool
select E500MC
+   select E6500
select FSL_LAW
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A004477
@@ -801,6 +803,7 @@ config ARCH_T1042
 config ARCH_T2080
bool
select E500MC
+   select E6500
select FSL_LAW
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A006379
@@ -817,6 +820,7 @@ config ARCH_T2080
 config ARCH_T2081
bool
select E500MC
+   select E6500
select FSL_LAW
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A006379
@@ -833,6 +837,7 @@ config ARCH_T2081
 config ARCH_T4160
bool
select E500MC
+   select E6500
select FSL_LAW
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A004468
@@ -850,6 +855,7 @@ config ARCH_T4160
 config ARCH_T4240
bool
select E500MC
+   select E6500
select FSL_LAW
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A004468
@@ -880,6 +886,11 @@ config E500MC
help
Enble PowerPC E500MC core
 
+config E6500
+   bool
+   help
+   Enable PowerPC E6500 core
+
 config FSL_LAW
bool
help
@@ -1160,6 +1171,11 @@ config SYS_FSL_NUM_LAWS
Number of local access windows. This is fixed per SoC.
If not sure, do not change.
 
+config SYS_FSL_THREADS_PER_CORE
+   int
+   default 2 if E6500
+   default 1
+
 config SYS_NUM_TLBCAMS
int "Number of TLB CAM entries"
default 64 if E500MC
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 2a826fe..92c96d7 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -238,7 +238,6 @@
 #define CONFIG_ESDHC_HC_BLK_ADDR
 
 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
-#define CONFIG_E6500
 #define CONFIG_SYS_PPC64   /* 64-bit core */
 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2  /* Freescale Chassis generation 2 */
@@ -284,7 +283,6 @@
 #define CONFIG_SYS_FSL_PCI_VER_3_X
 
 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
-#define CONFIG_E6500
 #define CONFIG_SYS_PPC64   /* 64-bit core */
 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2  /* Freescale Chassis generation 2 */
@@ -399,7 +397,6 @@
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 
 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
-#define CONFIG_E6500
 #define CONFIG_SYS_PPC64   /* 64-bit core */
 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2  /* Freescale Chassis generation 2 */
@@ -451,12 +448,6 @@
 
 #endif
 
-#ifdef CONFIG_E6500
-#define CONFIG_SYS_FSL_THREADS_PER_CORE 2
-#else
-#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
-#endif
-
 #if !defined(CONFIG_ARCH_C29X)
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 #endif
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index df3965f..2cc8f0c 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -5517,7 +5517,6 @@ CONFIG_SYS_FSL_SRIO_OB_WIN_NUM
 CONFIG_SYS_FSL_SRIO_OFFSET
 CONFIG_SYS_FSL_SRK_LE
 CONFIG_SYS_FSL_TBCLK_DIV
-CONFIG_SYS_FSL_THREADS_PER_CORE
 CONFIG_SYS_FSL_TIMER_ADDR
 CONFIG_SYS_FSL_USB1_ADDR
 CONFIG_SYS_FSL_USB1_PHY_ENABLE
-- 
2.7.4

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[U-Boot] [PATCH 21/24] powerpc: mpc85xx: Remove unused ifdef in config header

[York Sun]

After most config options are moved to Kconfig, the unused ifdef
or elif can be removed.

Signed-off-by: York Sun 
---

 arch/powerpc/include/asm/config_mpc85xx.h | 20 +---
 1 file changed, 1 insertion(+), 19 deletions(-)

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 4986f38..2a826fe 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -22,25 +22,13 @@
 #define CONFIG_SYS_FSL_SFP_BE
 #define CONFIG_SYS_FSL_SEC_MON_BE
 
-#if defined(CONFIG_ARCH_MPC8536)
-
-#elif defined(CONFIG_ARCH_MPC8540)
-
-#elif defined(CONFIG_ARCH_MPC8541)
-
-#elif defined(CONFIG_ARCH_MPC8544)
-
-#elif defined(CONFIG_ARCH_MPC8548)
+#if defined(CONFIG_ARCH_MPC8548)
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  1
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
 #define CONFIG_SYS_FSL_RMU
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM   2
 
-#elif defined(CONFIG_ARCH_MPC8555)
-
-#elif defined(CONFIG_ARCH_MPC8560)
-
 #elif defined(CONFIG_ARCH_MPC8568)
 #define QE_MURAM_SIZE  0x1UL
 #define MAX_QE_RISC2
@@ -61,8 +49,6 @@
 #define CONFIG_SYS_FSL_RMU
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM   2
 
-#elif defined(CONFIG_ARCH_MPC8572)
-
 #elif defined(CONFIG_ARCH_P1010)
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_TSECV2
@@ -463,10 +449,6 @@
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  3
 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET  0x2
 
-#elif defined(CONFIG_ARCH_QEMU_E500)
-
-#else
-#error Processor type not defined for this platform
 #endif
 
 #ifdef CONFIG_E6500
-- 
2.7.4

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[U-Boot] [PATCH 23/24] powerpc: mpc85xx: Move CONFIG_SYS_FSL_QORIQ_CHASSIS* to Kconfig

[York Sun]

Use Kconfig option to select chassis version.

Signed-off-by: York Sun 
---

 arch/powerpc/cpu/mpc85xx/Kconfig  | 21 +
 arch/powerpc/include/asm/config_mpc85xx.h | 10 --
 scripts/config_whitelist.txt  |  2 --
 3 files changed, 21 insertions(+), 12 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 8b905e2..ac6c197 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -341,6 +341,7 @@ config ARCH_B4420
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
+   select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
 
@@ -362,6 +363,7 @@ config ARCH_B4860
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
+   select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
 
@@ -641,6 +643,7 @@ config ARCH_P2041
select SYS_FSL_ERRATUM_USB14
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
+   select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
 
@@ -663,6 +666,7 @@ config ARCH_P3041
select SYS_FSL_ERRATUM_USB14
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
+   select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
 
@@ -696,6 +700,7 @@ config ARCH_P4080
select SYS_P4080_ERRATUM_SERDES_A005
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
+   select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
 
@@ -714,6 +719,7 @@ config ARCH_P5020
select SYS_FSL_ERRATUM_USB14
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
+   select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
 
@@ -732,6 +738,7 @@ config ARCH_P5040
select SYS_FSL_ERRATUM_USB14
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
+   select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
 
@@ -750,6 +757,7 @@ config ARCH_T1023
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select SYS_FSL_HAS_SEC
+   select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
 
@@ -765,6 +773,7 @@ config ARCH_T1024
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select SYS_FSL_HAS_SEC
+   select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
 
@@ -781,6 +790,7 @@ config ARCH_T1040
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select SYS_FSL_HAS_SEC
+   select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
 
@@ -797,6 +807,7 @@ config ARCH_T1042
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select SYS_FSL_HAS_SEC
+   select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
 
@@ -814,6 +825,7 @@ config ARCH_T2080
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
+   select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
 
@@ -831,6 +843,7 @@ config ARCH_T2081
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
+   select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
 
@@ -849,6 +862,7 @@ config ARCH_T4160
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
+   select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
 
@@ -868,6 +882,7 @@ config ARCH_T4240
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
+   select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
 
@@ -1127,6 +1142,12 @@ config SYS_P4080_ERRATUM_SERDES_A001
 config SYS_P4080_ERRATUM_SERDES_A005
bool
 
+config SYS_FSL_QORIQ_CHASSIS1
+   bool
+
+config SYS_FSL_QORIQ_CHASSIS2
+   bool
+
 config SYS_FSL_NUM_LAWS
int "Number of local access windows"
depends on FSL_LAW
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 92c96d7..8cde05c 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -117,7 +117,6 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT1
 
 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
 

[U-Boot] [PATCH 19/24] ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS

[York Sun]

These two macros are used for the same thing, the total number of DDR
controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and
merge existing usage.

Signed-off-by: York Sun 
---

 arch/powerpc/cpu/mpc85xx/cpu.c  | 22 +++---
 arch/powerpc/cpu/mpc85xx/cpu_init.c | 16 
 board/freescale/b4860qds/ddr.c  |  4 ++--
 board/freescale/corenet_ds/ddr.c|  6 +++---
 drivers/ddr/fsl/Kconfig |  2 +-
 drivers/ddr/fsl/arm_ddr_gen3.c  |  6 +++---
 drivers/ddr/fsl/ctrl_regs.c |  6 +++---
 drivers/ddr/fsl/fsl_ddr_gen4.c  |  6 +++---
 drivers/ddr/fsl/interactive.c   | 14 +++---
 drivers/ddr/fsl/main.c  | 30 +++---
 drivers/ddr/fsl/mpc85xx_ddr_gen3.c  |  6 +++---
 drivers/ddr/fsl/options.c   | 30 +++---
 drivers/ddr/fsl/util.c  | 28 ++--
 include/configs/B4860QDS.h  |  2 +-
 include/configs/P2041RDB.h  |  2 +-
 include/configs/T102xQDS.h  |  2 +-
 include/configs/T102xRDB.h  |  2 +-
 include/configs/T1040QDS.h  |  2 +-
 include/configs/T104xRDB.h  |  2 +-
 include/configs/T208xQDS.h  |  2 +-
 include/configs/T208xRDB.h  |  2 +-
 include/configs/T4240RDB.h  |  2 +-
 include/configs/corenet_ds.h|  2 +-
 include/configs/cyrus.h |  2 +-
 include/configs/km/kmp204x-common.h |  2 +-
 include/configs/t4qds.h |  2 +-
 include/fsl_ddr.h   |  3 +--
 scripts/config_whitelist.txt|  1 -
 28 files changed, 102 insertions(+), 104 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index d180c73..cc30fa6 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -482,17 +482,17 @@ static void dump_spd_ddr_reg(void)
int i, j, k, m;
u8 *p_8;
u32 *p_32;
-   struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
+   struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
generic_spd_eeprom_t
-   spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
+   spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
 
-   for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+   for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
 
puts("SPD data of all dimms (zero value is omitted)...\n");
puts("Byte (hex)  ");
k = 1;
-   for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+   for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
printf("Dimm%d ", k++);
}
@@ -500,7 +500,7 @@ static void dump_spd_ddr_reg(void)
for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
m = 0;
printf("%3d (0x%02x)  ", k, k);
-   for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+   for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
p_8 = (u8 *) [i][j];
if (p_8[k]) {
@@ -516,22 +516,22 @@ static void dump_spd_ddr_reg(void)
puts("\r");
}
 
-   for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+   for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
switch (i) {
case 0:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
 #endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
 #endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
@@ -545,13 +545,13 @@ static void dump_spd_ddr_reg(void)
printf("DDR registers dump for all controllers "
"(zero value is omitted)...\n");
puts("Offset (hex)   ");
-   for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+   for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
printf(" Base + 0x%04x", (u32)ddr[i] & 0x);
puts("\n");
for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
m = 0;
  

[U-Boot] [PATCH 20/24] ddr: fsl: Move CONFIG_SYS_FSL_DDR_VER to Kconfig

[York Sun]

Use Kconfig to select DDR version instead of using config header.

Signed-off-by: York Sun 
---

 arch/powerpc/cpu/mpc85xx/Kconfig  | 17 +
 arch/powerpc/include/asm/config_mpc85xx.h | 12 
 2 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 9154168..7b64ae0 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -327,6 +327,7 @@ config ARCH_B4420
bool
select E500MC
select FSL_LAW
+   select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A005871
select SYS_FSL_ERRATUM_A006379
@@ -346,6 +347,7 @@ config ARCH_B4860
bool
select E500MC
select FSL_LAW
+   select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A005871
select SYS_FSL_ERRATUM_A006379
@@ -364,6 +366,7 @@ config ARCH_B4860
 config ARCH_BSC9131
bool
select FSL_LAW
+   select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ESDHC111
@@ -375,6 +378,7 @@ config ARCH_BSC9131
 config ARCH_BSC9132
bool
select FSL_LAW
+   select SYS_FSL_DDR_VER_46
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_A005434
@@ -390,6 +394,7 @@ config ARCH_BSC9132
 config ARCH_C29X
bool
select FSL_LAW
+   select SYS_FSL_DDR_VER_46
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
@@ -641,6 +646,7 @@ config ARCH_P3041
bool
select E500MC
select FSL_LAW
+   select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004849
select SYS_FSL_ERRATUM_A005812
@@ -662,6 +668,7 @@ config ARCH_P4080
bool
select E500MC
select FSL_LAW
+   select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004580
select SYS_FSL_ERRATUM_A004849
@@ -694,6 +701,7 @@ config ARCH_P5020
bool
select E500MC
select FSL_LAW
+   select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A006261
select SYS_FSL_ERRATUM_DDR_A003
@@ -711,6 +719,7 @@ config ARCH_P5040
bool
select E500MC
select FSL_LAW
+   select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004699
select SYS_FSL_ERRATUM_A005812
@@ -731,6 +740,7 @@ config ARCH_T1023
bool
select E500MC
select FSL_LAW
+   select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009942
@@ -745,6 +755,7 @@ config ARCH_T1024
bool
select E500MC
select FSL_LAW
+   select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009942
@@ -759,6 +770,7 @@ config ARCH_T1040
bool
select E500MC
select FSL_LAW
+   select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008044
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A009663
@@ -774,6 +786,7 @@ config ARCH_T1042
bool
select E500MC
select FSL_LAW
+   select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008044
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A009663
@@ -789,6 +802,7 @@ config ARCH_T2080
bool
select E500MC
select FSL_LAW
+   select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A006379
select SYS_FSL_ERRATUM_A006593
select SYS_FSL_ERRATUM_A007186
@@ -804,6 +818,7 @@ config ARCH_T2081
bool
select E500MC
select FSL_LAW
+   select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A006379
select SYS_FSL_ERRATUM_A006593
select SYS_FSL_ERRATUM_A007186
@@ -819,6 +834,7 @@ config ARCH_T4160
bool
select E500MC
select FSL_LAW
+   select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A004468
select SYS_FSL_ERRATUM_A005871
select SYS_FSL_ERRATUM_A006379
@@ -835,6 +851,7 @@ config ARCH_T4240
bool
select E500MC
select FSL_LAW
+   select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A004468
select SYS_FSL_ERRATUM_A005871
select SYS_FSL_ERRATUM_A006261
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index dbc8d7a..4986f38 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -156,7 +156,6 @@
 #define CONFIG_SYS_NUM_FMAN1
 #define CONFIG_SYS_NUM_FM1_DTSEC 

[U-Boot] [PATCH 17/24] powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig

[York Sun]

Use Kconfig to select errata workaround.

Signed-off-by: York Sun 
---

 arch/powerpc/cpu/mpc85xx/Kconfig  | 317 ++
 arch/powerpc/cpu/mpc85xx/cmd_errata.c |   2 +-
 arch/powerpc/cpu/mpc85xx/cpu_init.c   |   2 +-
 arch/powerpc/include/asm/config_mpc85xx.h | 157 ---
 drivers/ddr/fsl/Kconfig   |  15 ++
 include/configs/BSC9132QDS.h  |   1 -
 scripts/config_whitelist.txt  |  52 -
 7 files changed, 334 insertions(+), 212 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index dc81a3b..9154168 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -327,6 +327,16 @@ config ARCH_B4420
bool
select E500MC
select FSL_LAW
+   select SYS_FSL_ERRATUM_A004477
+   select SYS_FSL_ERRATUM_A005871
+   select SYS_FSL_ERRATUM_A006379
+   select SYS_FSL_ERRATUM_A006384
+   select SYS_FSL_ERRATUM_A006475
+   select SYS_FSL_ERRATUM_A006593
+   select SYS_FSL_ERRATUM_A007075
+   select SYS_FSL_ERRATUM_A007186
+   select SYS_FSL_ERRATUM_A007212
+   select SYS_FSL_ERRATUM_A009942
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -336,6 +346,16 @@ config ARCH_B4860
bool
select E500MC
select FSL_LAW
+   select SYS_FSL_ERRATUM_A004477
+   select SYS_FSL_ERRATUM_A005871
+   select SYS_FSL_ERRATUM_A006379
+   select SYS_FSL_ERRATUM_A006384
+   select SYS_FSL_ERRATUM_A006475
+   select SYS_FSL_ERRATUM_A006593
+   select SYS_FSL_ERRATUM_A007075
+   select SYS_FSL_ERRATUM_A007186
+   select SYS_FSL_ERRATUM_A007212
+   select SYS_FSL_ERRATUM_A009942
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -344,6 +364,8 @@ config ARCH_B4860
 config ARCH_BSC9131
bool
select FSL_LAW
+   select SYS_FSL_ERRATUM_A004477
+   select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
@@ -353,7 +375,12 @@ config ARCH_BSC9131
 config ARCH_BSC9132
bool
select FSL_LAW
+   select SYS_FSL_ERRATUM_A004477
+   select SYS_FSL_ERRATUM_A005125
+   select SYS_FSL_ERRATUM_A005434
select SYS_FSL_ERRATUM_ESDHC111
+   select SYS_FSL_ERRATUM_I2C_A004447
+   select SYS_FSL_ERRATUM_IFC_A002769
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -363,6 +390,7 @@ config ARCH_BSC9132
 config ARCH_C29X
bool
select FSL_LAW
+   select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
@@ -373,6 +401,8 @@ config ARCH_C29X
 config ARCH_MPC8536
bool
select FSL_LAW
+   select SYS_FSL_ERRATUM_A004508
+   select SYS_FSL_ERRATUM_A005125
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
@@ -396,6 +426,7 @@ config ARCH_MPC8541
 config ARCH_MPC8544
bool
select FSL_LAW
+   select SYS_FSL_ERRATUM_A005125
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -405,6 +436,11 @@ config ARCH_MPC8544
 config ARCH_MPC8548
bool
select FSL_LAW
+   select SYS_FSL_ERRATUM_A005125
+   select SYS_FSL_ERRATUM_NMG_DDR120
+   select SYS_FSL_ERRATUM_NMG_LBC103
+   select SYS_FSL_ERRATUM_NMG_ETSEC129
+   select SYS_FSL_ERRATUM_I2C_A004447
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_DDR1
select SYS_FSL_HAS_SEC
@@ -436,6 +472,8 @@ config ARCH_MPC8568
 config ARCH_MPC8569
bool
select FSL_LAW
+   select SYS_FSL_ERRATUM_A004508
+   select SYS_FSL_ERRATUM_A005125
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -444,6 +482,10 @@ config ARCH_MPC8569
 config ARCH_MPC8572
bool
select FSL_LAW
+   select SYS_FSL_ERRATUM_A004508
+   select SYS_FSL_ERRATUM_A005125
+   select SYS_FSL_ERRATUM_DDR_115
+   select SYS_FSL_ERRATUM_DDR111_DDR134
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
@@ -453,7 +495,17 @@ config ARCH_MPC8572
 config ARCH_P1010
bool
select FSL_LAW
+   select SYS_FSL_ERRATUM_A004477
+   select SYS_FSL_ERRATUM_A004508
+   select SYS_FSL_ERRATUM_A005125
+   select SYS_FSL_ERRATUM_A006261
+   select SYS_FSL_ERRATUM_A007075
select SYS_FSL_ERRATUM_ESDHC111
+   select SYS_FSL_ERRATUM_I2C_A004447
+   select SYS_FSL_ERRATUM_IFC_A002769
+   select SYS_FSL_ERRATUM_P1010_A003549
+   select SYS_FSL_ERRATUM_SEC_A003571
+   select SYS_FSL_ERRATUM_IFC_A003399
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select 

[U-Boot] [PATCH 11/24] powerpc: T2080RDB: Remove macro CONFIG_T2080RDB

[York Sun]

Use TARGET_T2080RDB from Kconfig instead.

Signed-off-by: York Sun 
---

 arch/powerpc/include/asm/fsl_secure_boot.h | 2 +-
 board/freescale/t208xrdb/Makefile  | 2 +-
 include/configs/T208xRDB.h | 1 -
 scripts/config_whitelist.txt   | 1 -
 4 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h 
b/arch/powerpc/include/asm/fsl_secure_boot.h
index 95569a1..89ca45c 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -30,7 +30,7 @@
defined(CONFIG_TARGET_T4160QDS) || \
defined(CONFIG_TARGET_T4240QDS) || \
defined(CONFIG_TARGET_T2080QDS) || \
-   defined(CONFIG_T2080RDB) || \
+   defined(CONFIG_TARGET_T2080RDB) || \
defined(CONFIG_TARGET_T1040QDS) || \
defined(CONFIG_T104xD4QDS) || \
defined(CONFIG_TARGET_T1040RDB) || \
diff --git a/board/freescale/t208xrdb/Makefile 
b/board/freescale/t208xrdb/Makefile
index cd8fe09..25ea66a 100644
--- a/board/freescale/t208xrdb/Makefile
+++ b/board/freescale/t208xrdb/Makefile
@@ -7,7 +7,7 @@
 ifdef CONFIG_SPL_BUILD
 obj-y  += spl.o
 else
-obj-$(CONFIG_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o
+obj-$(CONFIG_TARGET_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o
 obj-$(CONFIG_PCI)  += pci.o
 endif
 
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index fbdb0bd..42261ed 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -11,7 +11,6 @@
 #ifndef __T2080RDB_H
 #define __T2080RDB_H
 
-#define CONFIG_T2080RDB
 #define CONFIG_ICS307_REFCLK_HZ 2500  /* ICS307 ref clk freq */
 #define CONFIG_MMC
 #define CONFIG_USB_EHCI
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 4d9514f..161096b 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -7794,7 +7794,6 @@ CONFIG_SYS_XWAY_EBU_BOOTCFG
 CONFIG_SYS_ZYNQ_QSPI_WAIT
 CONFIG_SYS_ZYNQ_SPI_WAIT
 CONFIG_SYS_i2C_FSL
-CONFIG_T2080RDB
 CONFIG_T2081QDS
 CONFIG_TAM3517_SETTINGS
 CONFIG_TAM3517_SW3_SETTINGS
-- 
2.7.4

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[U-Boot] [PATCH 15/24] arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig

[York Sun]

Use Kconfig to select errata workaround.

Signed-off-by: York Sun 
---

 arch/arm/cpu/armv7/ls102xa/Kconfig|  7 
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 41 +++
 arch/arm/include/asm/arch-fsl-layerscape/config.h | 20 ---
 arch/arm/include/asm/arch-ls102xa/config.h|  4 ---
 drivers/ddr/fsl/Kconfig   | 21 
 5 files changed, 69 insertions(+), 24 deletions(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index eca1d06..4b904f3 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -1,5 +1,9 @@
 config ARCH_LS1021A
bool
+   select SYS_FSL_ERRATUM_A008378
+   select SYS_FSL_ERRATUM_A008407
+   select SYS_FSL_ERRATUM_A009663
+   select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
@@ -56,4 +60,7 @@ config SYS_FSL_IFC_BANK_COUNT
depends on ARCH_LS1021A
default 8
 
+config SYS_FSL_ERRATUM_A008407
+   bool
+
 endmenu
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index bee7d15..af84e40 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -11,6 +11,11 @@ config ARCH_LS1043A
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
+   select SYS_FSL_ERRATUM_A008850
+   select SYS_FSL_ERRATUM_A009660
+   select SYS_FSL_ERRATUM_A009663
+   select SYS_FSL_ERRATUM_A009929
+   select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_HAS_DDR3
@@ -22,6 +27,11 @@ config ARCH_LS1046A
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
+   select SYS_FSL_ERRATUM_A008511
+   select SYS_FSL_ERRATUM_A009801
+   select SYS_FSL_ERRATUM_A009803
+   select SYS_FSL_ERRATUM_A009942
+   select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
@@ -38,6 +48,16 @@ config ARCH_LS2080A
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
select SYS_FSL_SRDS_2
+   select SYS_FSL_ERRATUM_A008336
+   select SYS_FSL_ERRATUM_A008511
+   select SYS_FSL_ERRATUM_A008514
+   select SYS_FSL_ERRATUM_A008585
+   select SYS_FSL_ERRATUM_A009635
+   select SYS_FSL_ERRATUM_A009663
+   select SYS_FSL_ERRATUM_A009801
+   select SYS_FSL_ERRATUM_A009803
+   select SYS_FSL_ERRATUM_A009942
+   select SYS_FSL_ERRATUM_A010165
 
 config FSL_LSCH2
bool
@@ -132,3 +152,24 @@ config SYS_HAS_SERDES
bool
 
 endmenu
+
+config SYS_FSL_ERRATUM_A008336
+   bool
+
+config SYS_FSL_ERRATUM_A008514
+   bool
+
+config SYS_FSL_ERRATUM_A008585
+   bool
+
+config SYS_FSL_ERRATUM_A008850
+   bool
+
+config SYS_FSL_ERRATUM_A009635
+   bool
+
+config SYS_FSL_ERRATUM_A009660
+   bool
+
+config SYS_FSL_ERRATUM_A009929
+   bool
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index db40669..6073d44 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -111,17 +111,7 @@
 #define EPU_EPCTR5 0x700060a14ULL
 #define EPU_EPGCR  0x70006ULL
 
-#define CONFIG_SYS_FSL_ERRATUM_A008336
-#define CONFIG_SYS_FSL_ERRATUM_A008511
-#define CONFIG_SYS_FSL_ERRATUM_A008514
-#define CONFIG_SYS_FSL_ERRATUM_A008585
 #define CONFIG_SYS_FSL_ERRATUM_A008751
-#define CONFIG_SYS_FSL_ERRATUM_A009635
-#define CONFIG_SYS_FSL_ERRATUM_A009663
-#define CONFIG_SYS_FSL_ERRATUM_A009801
-#define CONFIG_SYS_FSL_ERRATUM_A009803
-#define CONFIG_SYS_FSL_ERRATUM_A009942
-#define CONFIG_SYS_FSL_ERRATUM_A010165
 
 /* ARM A57 CORE ERRATA */
 #define CONFIG_ARM_ERRATA_826974
@@ -169,11 +159,6 @@
 #define GICD_BASE  0x01401000
 #define GICC_BASE  0x01402000
 
-#define CONFIG_SYS_FSL_ERRATUM_A008850
-#define CONFIG_SYS_FSL_ERRATUM_A009663
-#define CONFIG_SYS_FSL_ERRATUM_A009929
-#define CONFIG_SYS_FSL_ERRATUM_A009942
-#define CONFIG_SYS_FSL_ERRATUM_A009660
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 
 #elif defined(CONFIG_ARCH_LS1012A)
@@ -204,11 +189,6 @@
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 
-#define CONFIG_SYS_FSL_ERRATUM_A008511
-#define CONFIG_SYS_FSL_ERRATUM_A009801
-#define CONFIG_SYS_FSL_ERRATUM_A009803
-#define CONFIG_SYS_FSL_ERRATUM_A009942
-#define CONFIG_SYS_FSL_ERRATUM_A010165
 #else
 #error SoC not defined
 #endif
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index 1c5158b..fccd4ff 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ 

[U-Boot] [PATCH 16/24] mmc: move CONFIG_SYS_FSL_ERRATUM_ESDHC* to Kconfig

[York Sun]

Add option SYS_FSL_ERRATUM_ESDHC111, SYS_FSL_ERRATUM_ESDHC13,
SYS_FSL_ERRATUM_ESDHC135, SYS_FSL_ERRATUM_ESDHC_A001 to mmc Kconfig.
Move existing macros to related Kconfig.

Signed-off-by: York Sun 
---

 arch/arm/Kconfig  |  7 +++
 arch/powerpc/cpu/mpc83xx/Kconfig  |  3 +++
 arch/powerpc/cpu/mpc85xx/Kconfig  | 25 +
 arch/powerpc/include/asm/config_mpc85xx.h | 22 --
 drivers/mmc/Kconfig   | 12 
 include/configs/MPC8308RDB.h  |  1 -
 include/configs/colibri_vf.h  |  2 --
 include/configs/hrcon.h   |  1 -
 include/configs/pcm052.h  |  3 ---
 include/configs/s32v234evb.h  |  2 --
 include/configs/strider.h |  1 -
 include/configs/ts4800.h  |  2 --
 include/configs/vf610twr.h|  2 --
 scripts/config_whitelist.txt  |  4 
 14 files changed, 47 insertions(+), 40 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d6a0a23..6a312bd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -546,6 +546,7 @@ config ARCH_RMOBILE
 config TARGET_S32V234EVB
bool "Support s32v234evb"
select ARM64
+   select SYS_FSL_ERRATUM_ESDHC111
 
 config ARCH_SNAPDRAGON
bool "Qualcomm Snapdragon SoCs"
@@ -602,18 +603,24 @@ config TARGET_TS4600
 config TARGET_TS4800
bool "Support TS4800"
select CPU_V7
+   select SYS_FSL_ERRATUM_ESDHC_A001
 
 config TARGET_VF610TWR
bool "Support vf610twr"
select CPU_V7
+   select SYS_FSL_ERRATUM_ESDHC111
 
 config TARGET_COLIBRI_VF
bool "Support Colibri VF50/61"
select CPU_V7
+   select SYS_FSL_ERRATUM_ESDHC111
 
 config TARGET_PCM052
bool "Support pcm-052"
select CPU_V7
+   select SYS_FSL_ERRATUM_ESDHC111
+   select SYS_FSL_ERRATUM_ESDHC135
+   select SYS_FSL_ERRATUM_ESDHC_A001
 
 config TARGET_BK4R1
bool "Support BK4r1"
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 6e4a931..184063c 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -22,6 +22,7 @@ config TARGET_VME8349
 
 config TARGET_MPC8308RDB
bool "Support MPC8308RDB"
+   select SYS_FSL_ERRATUM_ESDHC111
 
 config TARGET_MPC8313ERDB
bool "Support MPC8313ERDB"
@@ -69,9 +70,11 @@ config TARGET_TQM834X
 
 config TARGET_HRCON
bool "Support hrcon"
+   select SYS_FSL_ERRATUM_ESDHC111
 
 config TARGET_STRIDER
bool "Support strider"
+   select SYS_FSL_ERRATUM_ESDHC111
 
 endchoice
 
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 3e90c70..dc81a3b 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -344,6 +344,7 @@ config ARCH_B4860
 config ARCH_BSC9131
bool
select FSL_LAW
+   select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -352,6 +353,7 @@ config ARCH_BSC9131
 config ARCH_BSC9132
bool
select FSL_LAW
+   select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -361,6 +363,7 @@ config ARCH_BSC9132
 config ARCH_C29X
bool
select FSL_LAW
+   select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -450,6 +453,7 @@ config ARCH_MPC8572
 config ARCH_P1010
bool
select FSL_LAW
+   select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -459,6 +463,7 @@ config ARCH_P1010
 config ARCH_P1011
bool
select FSL_LAW
+   select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -468,6 +473,7 @@ config ARCH_P1011
 config ARCH_P1020
bool
select FSL_LAW
+   select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -477,6 +483,7 @@ config ARCH_P1020
 config ARCH_P1021
bool
select FSL_LAW
+   select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -486,6 +493,7 @@ config ARCH_P1021
 config ARCH_P1022
bool
select FSL_LAW
+   select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -503,6 +511,7 @@ config ARCH_P1023
 config ARCH_P1024
bool
select FSL_LAW
+   select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -512,6 +521,7 @@ config ARCH_P1024
 config ARCH_P1025

[U-Boot] [PATCH 10/24] powerpc: T2080QDS: Remove macro T2080QDS

[York Sun]

Use TARGET_T2080QDS from Kconfig instead.

Signed-off-by: York Sun 
---

 arch/powerpc/include/asm/fsl_secure_boot.h |  2 +-
 board/freescale/t208xqds/Makefile  |  2 +-
 board/freescale/t208xqds/eth_t208xqds.c| 16 
 board/freescale/t208xqds/t208xqds.c|  6 +++---
 include/configs/T208xQDS.h |  1 -
 scripts/config_whitelist.txt   |  1 -
 6 files changed, 13 insertions(+), 15 deletions(-)

diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h 
b/arch/powerpc/include/asm/fsl_secure_boot.h
index 6949ee8..95569a1 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -29,7 +29,7 @@
defined(CONFIG_TARGET_B4420QDS) || \
defined(CONFIG_TARGET_T4160QDS) || \
defined(CONFIG_TARGET_T4240QDS) || \
-   defined(CONFIG_T2080QDS) || \
+   defined(CONFIG_TARGET_T2080QDS) || \
defined(CONFIG_T2080RDB) || \
defined(CONFIG_TARGET_T1040QDS) || \
defined(CONFIG_T104xD4QDS) || \
diff --git a/board/freescale/t208xqds/Makefile 
b/board/freescale/t208xqds/Makefile
index ef04a26..3a6d030 100644
--- a/board/freescale/t208xqds/Makefile
+++ b/board/freescale/t208xqds/Makefile
@@ -7,7 +7,7 @@
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
 else
-obj-$(CONFIG_T2080QDS) += t208xqds.o eth_t208xqds.o
+obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o
 obj-$(CONFIG_T2081QDS) += t208xqds.o eth_t208xqds.o
 obj-$(CONFIG_PCI)  += pci.o
 endif
diff --git a/board/freescale/t208xqds/eth_t208xqds.c 
b/board/freescale/t208xqds/eth_t208xqds.c
index e92b5d3..59480a3 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -32,7 +32,7 @@
 #define EMI1_RGMII10
 #define EMI1_RGMII2 1
 #define EMI1_SLOT1 2
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
 #define EMI1_SLOT2 6
 #define EMI1_SLOT3 3
 #define EMI1_SLOT4 4
@@ -59,7 +59,7 @@
 static int mdio_mux[NUM_FM_PORTS];
 
 static const char * const mdio_names[] = {
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
"T2080QDS_MDIO_RGMII1",
"T2080QDS_MDIO_RGMII2",
"T2080QDS_MDIO_SLOT1",
@@ -82,7 +82,7 @@ static const char * const mdio_names[] = {
 };
 
 /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
 static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
 #elif defined(CONFIG_T2081QDS)
 static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
@@ -204,7 +204,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, 
phys_addr_t addr,
int off;
 
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_T2080QDS
+#ifdef CONFIG_TARGET_T2080QDS
serdes_corenet_t *srds_regs =
(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
u32 srds1_pccr1 = in_be32(_regs->srdspccr1);
@@ -217,7 +217,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, 
phys_addr_t addr,
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
phy = fm_info_get_phy_address(port);
switch (port) {
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
case FM1_DTSEC1:
if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
media_type = 1;
@@ -454,7 +454,7 @@ static void initialize_lane_to_slot(void)
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
switch (srds_s1) {
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
case 0x51:
case 0x5f:
case 0x65:
@@ -552,7 +552,7 @@ int board_eth_init(bd_t *bis)
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
 #endif
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
@@ -663,7 +663,7 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
break;
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
case 0xd9:
case 0xd3:
case 0xcb:
diff --git a/board/freescale/t208xqds/t208xqds.c 
b/board/freescale/t208xqds/t208xqds.c
index d016329..e307ccb 100644
--- a/board/freescale/t208xqds/t208xqds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -99,7 +99,7 @@ int brd_mux_lane_to_slot(void)
srds_prtcl_s1 = in_be32(>rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-#if defined(CONFIG_T2080QDS)
+#if 

[U-Boot] [PATCH 13/24] powerpc: T104xQDS: Remove macro CONFIG_T104xD4QDS

[York Sun]

Remove this macro. It was added by e622d9ed but actually wasn't used.

Signed-off-by: York Sun 
---

 arch/powerpc/include/asm/fsl_secure_boot.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h 
b/arch/powerpc/include/asm/fsl_secure_boot.h
index 89ca45c..10e26d6 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -32,7 +32,6 @@
defined(CONFIG_TARGET_T2080QDS) || \
defined(CONFIG_TARGET_T2080RDB) || \
defined(CONFIG_TARGET_T1040QDS) || \
-   defined(CONFIG_T104xD4QDS) || \
defined(CONFIG_TARGET_T1040RDB) || \
defined(CONFIG_TARGET_T1040D4RDB) || \
defined(CONFIG_TARGET_T1042RDB) || \
-- 
2.7.4

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[U-Boot] [PATCH 12/24] powerpc: T2081QDS: Remove macro T2081QDS

[York Sun]

Use TARGET_T2081QDS from Kconfig instead.

Signed-off-by: York Sun 
---

 board/freescale/t208xqds/Makefile   |  2 +-
 board/freescale/t208xqds/eth_t208xqds.c | 16 
 board/freescale/t208xqds/t208xqds.c |  2 +-
 include/configs/T208xQDS.h  |  1 -
 scripts/config_whitelist.txt|  1 -
 5 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/board/freescale/t208xqds/Makefile 
b/board/freescale/t208xqds/Makefile
index 3a6d030..587903a 100644
--- a/board/freescale/t208xqds/Makefile
+++ b/board/freescale/t208xqds/Makefile
@@ -8,7 +8,7 @@ ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
 else
 obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o
-obj-$(CONFIG_T2081QDS) += t208xqds.o eth_t208xqds.o
+obj-$(CONFIG_TARGET_T2081QDS) += t208xqds.o eth_t208xqds.o
 obj-$(CONFIG_PCI)  += pci.o
 endif
 
diff --git a/board/freescale/t208xqds/eth_t208xqds.c 
b/board/freescale/t208xqds/eth_t208xqds.c
index 59480a3..c880294 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -38,7 +38,7 @@
 #define EMI1_SLOT4 4
 #define EMI1_SLOT5 5
 #define EMI27
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
 #define EMI1_SLOT2  3
 #define EMI1_SLOT3  4
 #define EMI1_SLOT5  5
@@ -68,7 +68,7 @@ static const char * const mdio_names[] = {
"T2080QDS_MDIO_SLOT5",
"T2080QDS_MDIO_SLOT2",
"T2080QDS_MDIO_10GC",
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
"T2081QDS_MDIO_RGMII1",
"T2081QDS_MDIO_RGMII2",
"T2081QDS_MDIO_SLOT1",
@@ -84,7 +84,7 @@ static const char * const mdio_names[] = {
 /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
 #if defined(CONFIG_TARGET_T2080QDS)
 static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
 static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
 #endif
 
@@ -311,7 +311,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, 
phys_addr_t addr,
fdt_status_okay_by_alias(fdt, "emi1_slot2");
}
break;
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC5:
@@ -481,7 +481,7 @@ static void initialize_lane_to_slot(void)
lane_to_slot[6] = 3;
lane_to_slot[7] = 3;
break;
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
case 0x6b:
lane_to_slot[4] = 1;
lane_to_slot[5] = 3;
@@ -556,7 +556,7 @@ int board_eth_init(bd_t *bis)
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
 #endif
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
-#if defined(CONFIG_T2081QDS)
+#if defined(CONFIG_TARGET_T2081QDS)
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
 #endif
@@ -675,7 +675,7 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
break;
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
case 0xca:
case 0xcb:
/* SGMII in Slot3 */
@@ -731,7 +731,7 @@ int board_eth_init(bd_t *bis)
fm_info_set_mdio(i, mii_dev_for_muxval(
 mdio_mux[i]));
break;
-#if defined(CONFIG_T2081QDS)
+#if defined(CONFIG_TARGET_T2081QDS)
case 5:
mdio_mux[i] = EMI1_SLOT5;
fm_info_set_mdio(i, mii_dev_for_muxval(
diff --git a/board/freescale/t208xqds/t208xqds.c 
b/board/freescale/t208xqds/t208xqds.c
index e307ccb..26093ea 100644
--- a/board/freescale/t208xqds/t208xqds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -191,7 +191,7 @@ int brd_mux_lane_to_slot(void)
 */
 QIXIS_WRITE(brdcfg[12], 0x1a);
 break;
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
case 0x50:
case 0x51:
/* SD1(A:D) => SLOT2 XAUI
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 15da358..fd5cb72 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -20,7 +20,6 @@
 #define CONFIG_SRIO1   /* SRIO port 1 */
 #define CONFIG_SRIO2   /* SRIO port 2 */
 #elif defined(CONFIG_ARCH_T2081)
-#define CONFIG_T2081QDS
 #endif
 
 /* High Level Configuration Options */
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 161096b..99a6d25 100644
--- a/scripts/config_whitelist.txt
+++ 

[U-Boot] [PATCH 09/24] powerpc: T1040QDS: Remove macro CONFIG_T1040QDS

[York Sun]

Use TARGET_T1040QDS from Kconfig instead.

Signed-off-by: York Sun 
---

 arch/powerpc/include/asm/fsl_secure_boot.h | 2 +-
 include/configs/T1040QDS.h | 1 -
 scripts/config_whitelist.txt   | 1 -
 3 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h 
b/arch/powerpc/include/asm/fsl_secure_boot.h
index 808adae..6949ee8 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -31,7 +31,7 @@
defined(CONFIG_TARGET_T4240QDS) || \
defined(CONFIG_T2080QDS) || \
defined(CONFIG_T2080RDB) || \
-   defined(CONFIG_T1040QDS) || \
+   defined(CONFIG_TARGET_T1040QDS) || \
defined(CONFIG_T104xD4QDS) || \
defined(CONFIG_TARGET_T1040RDB) || \
defined(CONFIG_TARGET_T1040D4RDB) || \
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 8e13f3b..dc8d86a 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -26,7 +26,6 @@
 /*
  * T1040 QDS board configuration file
  */
-#define CONFIG_T1040QDS
 
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE   CONFIG_SYS_TEXT_BASE
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index ff7f3d1..304a341 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -7794,7 +7794,6 @@ CONFIG_SYS_XWAY_EBU_BOOTCFG
 CONFIG_SYS_ZYNQ_QSPI_WAIT
 CONFIG_SYS_ZYNQ_SPI_WAIT
 CONFIG_SYS_i2C_FSL
-CONFIG_T1040QDS
 CONFIG_T2080QDS
 CONFIG_T2080RDB
 CONFIG_T2081QDS
-- 
2.7.4

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[U-Boot] [PATCH 08/24] powerpc: T1024RDB: Remove macro CONFIG_T1024RDB

[York Sun]

Use TARGET_T1024RDB from Kconfig instead.

Signed-off-by: York Sun 
---

 board/freescale/t102xrdb/Makefile   |  2 +-
 board/freescale/t102xrdb/eth_t102xrdb.c |  6 +++---
 board/freescale/t102xrdb/t102xrdb.c | 10 +-
 configs/T1024RDB_NAND_defconfig |  2 +-
 configs/T1024RDB_SDCARD_defconfig   |  2 +-
 configs/T1024RDB_SECURE_BOOT_defconfig  |  1 -
 configs/T1024RDB_SPIFLASH_defconfig |  2 +-
 configs/T1024RDB_defconfig  |  1 -
 include/configs/T102xRDB.h  | 24 
 scripts/config_whitelist.txt|  1 -
 10 files changed, 24 insertions(+), 27 deletions(-)

diff --git a/board/freescale/t102xrdb/Makefile 
b/board/freescale/t102xrdb/Makefile
index 6452865..ddeb44f 100644
--- a/board/freescale/t102xrdb/Makefile
+++ b/board/freescale/t102xrdb/Makefile
@@ -8,7 +8,7 @@ ifdef CONFIG_SPL_BUILD
 obj-y  += spl.o
 else
 obj-y   += t102xrdb.o
-obj-$(CONFIG_T1024RDB)   += cpld.o
+obj-$(CONFIG_TARGET_T1024RDB)   += cpld.o
 obj-y   += eth_t102xrdb.o
 obj-$(CONFIG_PCI)   += pci.o
 endif
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c 
b/board/freescale/t102xrdb/eth_t102xrdb.c
index dadfaf1..c06d1b8 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -58,7 +58,7 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
 
switch (srds_s1) {
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
case 0x95:
/* set the on-board RGMII2  PHY */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
@@ -94,7 +94,7 @@ int board_eth_init(bd_t *bis)
case PHY_INTERFACE_MODE_SGMII:
 #if defined(CONFIG_TARGET_T1023RDB)
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-#elif defined(CONFIG_T1024RDB)
+#elif defined(CONFIG_TARGET_T1024RDB)
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
 #endif
fm_info_set_mdio(i, dev);
@@ -128,7 +128,7 @@ int board_eth_init(bd_t *bis)
 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
  enum fm_port port, int offset)
 {
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
 (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
(port == FM1_DTSEC3)) {
diff --git a/board/freescale/t102xrdb/t102xrdb.c 
b/board/freescale/t102xrdb/t102xrdb.c
index 3174726..56f7c1a 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -17,7 +17,7 @@
 #include 
 #include 
 #include "t102xrdb.h"
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
 #include "cpld.h"
 #elif defined(CONFIG_TARGET_T1023RDB)
 #include 
@@ -51,7 +51,7 @@ int checkboard(void)
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
printf("Board: %sRDB, ", cpu->name);
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
   CPLD_READ(hw_ver), CPLD_READ(sw_ver));
 #elif defined(CONFIG_TARGET_T1023RDB)
@@ -63,7 +63,7 @@ int checkboard(void)
puts("SD/MMC\n");
 #elif CONFIG_SPIFLASH
puts("SPI\n");
-#elif defined(CONFIG_T1024RDB)
+#elif defined(CONFIG_TARGET_T1024RDB)
u8 reg;
 
reg = CPLD_READ(flash_csr);
@@ -91,7 +91,7 @@ int checkboard(void)
return 0;
 }
 
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
 static void board_mux_lane(void)
 {
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -150,7 +150,7 @@ int board_early_init_r(void)
0, flash_esel, BOOKE_PAGESZ_256M, 1);
 #endif
 
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
board_mux_lane();
 #endif
 
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index 96a6b65..d6ad422 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -12,7 +12,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_BOOTDELAY=10
 CONFIG_SILENT_CONSOLE=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/T1024RDB_SDCARD_defconfig 
b/configs/T1024RDB_SDCARD_defconfig
index c6fdb22..8ef312f 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -12,7 +12,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
 CONFIG_BOOTDELAY=10
 CONFIG_SILENT_CONSOLE=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig 

[U-Boot] [PATCH 06/24] powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014

[York Sun]

Remove these SoCs from Kconfig because they don't have individual
configuration. Clean up existing macros.

Signed-off-by: York Sun 
---

 arch/powerpc/cpu/mpc85xx/Kconfig  | 12 +---
 arch/powerpc/cpu/mpc85xx/Makefile |  4 
 arch/powerpc/include/asm/config_mpc85xx.h |  6 ++
 arch/powerpc/include/asm/immap_85xx.h |  6 ++
 drivers/net/fm/Makefile   |  2 --
 5 files changed, 5 insertions(+), 25 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index f36114a..f27ade2 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -655,8 +655,6 @@ config MAX_CPUS
 ARCH_P1025 || \
 ARCH_P2020 || \
 ARCH_P5020 || \
-ARCH_T1020 || \
-ARCH_T1022 || \
 ARCH_T1023 || \
 ARCH_T1024
default 1
@@ -698,10 +696,6 @@ config SYS_CCSRBAR_DEFAULT
ARCH_P4080  || \
ARCH_P5020  || \
ARCH_P5040  || \
-   ARCH_T1013  || \
-   ARCH_T1014  || \
-   ARCH_T1020  || \
-   ARCH_T1022  || \
ARCH_T1023  || \
ARCH_T1024  || \
ARCH_T1040  || \
@@ -731,11 +725,7 @@ config SYS_FSL_NUM_LAWS
ARCH_T2081  || \
ARCH_T4160  || \
ARCH_T4240
-   default 16 if   ARCH_T1013  || \
-   ARCH_T1014  || \
-   ARCH_T1020  || \
-   ARCH_T1022  || \
-   ARCH_T1023  || \
+   default 16 if   ARCH_T1023  || \
ARCH_T1024  || \
ARCH_T1040  || \
ARCH_T1042
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile 
b/arch/powerpc/cpu/mpc85xx/Makefile
index 46ed22c..04585d0 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -50,8 +50,6 @@ obj-$(CONFIG_ARCH_B4420) += b4860_ids.o
 obj-$(CONFIG_ARCH_B4860) += b4860_ids.o
 obj-$(CONFIG_ARCH_T1040) += t1040_ids.o
 obj-$(CONFIG_ARCH_T1042)   += t1040_ids.o
-obj-$(CONFIG_PPC_T1020)+= t1040_ids.o
-obj-$(CONFIG_PPC_T1022)+= t1040_ids.o
 obj-$(CONFIG_ARCH_T1023) += t1024_ids.o
 obj-$(CONFIG_ARCH_T1024) += t1024_ids.o
 obj-$(CONFIG_ARCH_T2080) += t2080_ids.o
@@ -92,8 +90,6 @@ obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o
 obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o
 obj-$(CONFIG_ARCH_T1040) += t1040_serdes.o
 obj-$(CONFIG_ARCH_T1042)   += t1040_serdes.o
-obj-$(CONFIG_PPC_T1020)+= t1040_serdes.o
-obj-$(CONFIG_PPC_T1022)+= t1040_serdes.o
 obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o
 obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o
 obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 8bae577..4e9fcc8 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -538,8 +538,7 @@
 #define CONFIG_NUM_DDR_CONTROLLERS 1
 #endif
 
-#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\
-defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
+#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
 #define CONFIG_E5500
 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2  /* Freescale Chassis generation 2 */
@@ -582,8 +581,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_SYS_FSL_ERRATUM_A009663
 #define CONFIG_SYS_FSL_ERRATUM_A009942
 
-#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) ||\
-defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
+#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
 #define CONFIG_E5500
 #define CONFIG_FSL_CORENET  /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2  /* Freescale Chassis generation 2 */
diff --git a/arch/powerpc/include/asm/immap_85xx.h 
b/arch/powerpc/include/asm/immap_85xx.h
index 786e4f6..762b174 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1775,8 +1775,7 @@ typedef struct ccsr_gur {
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL0x00ff
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT  16
 #define FSL_CORENET_RCWSR6_BOOT_LOC0x0f80
-#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\
-defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
+#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL0xff00
 

[U-Boot] [PATCH 07/24] powerpc: T1023RDB: Remove macro CONFIG_T1023RDB

[York Sun]

Use TARGET_T1023RDB from Kconfig instead.

Signed-off-by: York Sun 
---

 board/freescale/t102xrdb/ddr.c  |  2 +-
 board/freescale/t102xrdb/eth_t102xrdb.c |  4 ++--
 board/freescale/t102xrdb/t102xrdb.c | 12 ++--
 board/freescale/t102xrdb/t102xrdb.h |  2 +-
 configs/T1023RDB_NAND_defconfig |  2 +-
 configs/T1023RDB_SDCARD_defconfig   |  2 +-
 configs/T1023RDB_SECURE_BOOT_defconfig  |  1 -
 configs/T1023RDB_SPIFLASH_defconfig |  2 +-
 configs/T1023RDB_defconfig  |  1 -
 include/configs/T102xRDB.h  | 20 ++--
 scripts/config_whitelist.txt|  1 -
 11 files changed, 23 insertions(+), 26 deletions(-)

diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
index 9e1b16b..c09199f 100644
--- a/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c
@@ -136,7 +136,7 @@ found:
popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
 #endif
 
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
popts->wrlvl_ctl_2 = 0x07070606;
popts->half_strength_driver_enable = 1;
popts->cpo_sample = 0x43;
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c 
b/board/freescale/t102xrdb/eth_t102xrdb.c
index 02b283d..dadfaf1 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -73,7 +73,7 @@ int board_eth_init(bd_t *bis)
case 0x135:
/* set the on-board 2.5G SGMII AQR105 PHY */
fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
/* set the on-board 1G SGMII RTL8211F PHY */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
 #endif
@@ -92,7 +92,7 @@ int board_eth_init(bd_t *bis)
fm_info_set_mdio(i, dev);
break;
case PHY_INTERFACE_MODE_SGMII:
-#if defined(CONFIG_T1023RDB)
+#if defined(CONFIG_TARGET_T1023RDB)
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
 #elif defined(CONFIG_T1024RDB)
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
diff --git a/board/freescale/t102xrdb/t102xrdb.c 
b/board/freescale/t102xrdb/t102xrdb.c
index 24df4b4..3174726 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -19,7 +19,7 @@
 #include "t102xrdb.h"
 #ifdef CONFIG_T1024RDB
 #include "cpld.h"
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
 #include 
 #include 
 #endif
@@ -27,7 +27,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
 enum {
GPIO1_SD_SEL= 0x0002, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
GPIO1_EMMC_SEL,
@@ -54,7 +54,7 @@ int checkboard(void)
 #if defined(CONFIG_T1024RDB)
printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
   CPLD_READ(hw_ver), CPLD_READ(sw_ver));
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
 #endif
printf("boot from ");
@@ -74,7 +74,7 @@ int checkboard(void)
reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
printf("NOR vBank%d\n", reg);
}
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
 #ifdef CONFIG_NAND
puts("NAND\n");
 #else
@@ -196,7 +196,7 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_board_enet(blob);
 #endif
 
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
fdt_enable_nor(blob);
 #endif
@@ -204,7 +204,7 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0;
 }
 
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
 /* Enable NOR flash for RevC */
 static void fdt_enable_nor(void *blob)
 {
diff --git a/board/freescale/t102xrdb/t102xrdb.h 
b/board/freescale/t102xrdb/t102xrdb.h
index ae5c60f..6634e7a 100644
--- a/board/freescale/t102xrdb/t102xrdb.h
+++ b/board/freescale/t102xrdb/t102xrdb.h
@@ -9,7 +9,7 @@
 
 void fdt_fixup_board_enet(void *blob);
 void pci_of_setup(void *blob, bd_t *bd);
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
 static u32 t1023rdb_ctrl(u32 ctrl_type);
 static void fdt_enable_nor(void *blob);
 #endif
diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig
index 5649652..71de2a5 100644
--- a/configs/T1023RDB_NAND_defconfig
+++ b/configs/T1023RDB_NAND_defconfig
@@ -12,7 +12,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
 CONFIG_BOOTDELAY=10
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SPL=y
diff --git a/configs/T1023RDB_SDCARD_defconfig 
b/configs/T1023RDB_SDCARD_defconfig
index cc15635..dee5690 100644
--- 

[U-Boot] [PATCH 02/24] powerpc: mpc85xx: Move CONFIG_SYS_NUM_TLBCAMS to Kconfig

[York Sun]

Use Kconfig option for SYS_NUM_TLBCAMS and clean up existing macros.

Signed-off-by: York Sun 
---

 arch/powerpc/cpu/mpc85xx/Kconfig  | 8 
 arch/powerpc/include/asm/config_mpc85xx.h | 7 ---
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 6d8709e..2b1d0f6 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -647,6 +647,14 @@ config SYS_FSL_NUM_LAWS
Number of local access windows. This is fixed per SoC.
If not sure, do not change.
 
+config SYS_NUM_TLBCAMS
+   int "Number of TLB CAM entries"
+   default 64 if E500MC
+   default 16
+   help
+   Number of TLB CAM entries for Book-E chips. 64 for E500MC,
+   16 for other E500 SoCs.
+
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 8cfc612..5761218 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -24,13 +24,6 @@
 #define CONFIG_SYS_FSL_SFP_BE
 #define CONFIG_SYS_FSL_SEC_MON_BE
 
-/* Number of TLB CAM entries we have on FSL Book-E chips */
-#if defined(CONFIG_E500MC)
-#define CONFIG_SYS_NUM_TLBCAMS 64
-#elif defined(CONFIG_E500)
-#define CONFIG_SYS_NUM_TLBCAMS 16
-#endif
-
 #if defined(CONFIG_ARCH_MPC8536)
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB  1
 #define CONFIG_SYS_FSL_SEC_COMPAT  2
-- 
2.7.4

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[U-Boot] [PATCH 03/24] powerpc: mpc85xx: Move CONFIG_SYS_PPC_E500_DEBUG_TLB to Kconfig

[York Sun]

Use Kconfig SYS_PPC_E500_DEBUG_TLB and clean up existing macros.

Signed-off-by: York Sun 
---

 README|  9 ---
 arch/powerpc/cpu/mpc85xx/Kconfig  | 40 +++
 arch/powerpc/include/asm/config_mpc85xx.h | 14 ---
 scripts/config_whitelist.txt  |  1 -
 4 files changed, 40 insertions(+), 24 deletions(-)

diff --git a/README b/README
index 25cad2f..f6d3781 100644
--- a/README
+++ b/README
@@ -376,15 +376,6 @@ The following options need to be configured:
Defines the string to utilize when trying to match PCIe device
tree nodes for the given platform.
 
-   CONFIG_SYS_PPC_E500_DEBUG_TLB
-
-   Enables a temporary TLB entry to be used during boot to work
-   around limitations in e500v1 and e500v2 external debugger
-   support. This reduces the portions of the boot code where
-   breakpoints and single stepping do not work.  The value of this
-   symbol should be set to the TLB1 entry to be used for this
-   purpose.
-
CONFIG_SYS_FSL_ERRATUM_A004510
 
Enables a workaround for erratum A004510.  If set,
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 2b1d0f6..7f04a09 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -338,14 +338,17 @@ config ARCH_BSC9131
 config ARCH_BSC9132
bool
select FSL_LAW
+   select SYS_PPC_E500_USE_DEBUG_TLB
 
 config ARCH_C29X
bool
select FSL_LAW
+   select SYS_PPC_E500_USE_DEBUG_TLB
 
 config ARCH_MPC8536
bool
select FSL_LAW
+   select SYS_PPC_E500_USE_DEBUG_TLB
 
 config ARCH_MPC8540
bool
@@ -358,10 +361,12 @@ config ARCH_MPC8541
 config ARCH_MPC8544
bool
select FSL_LAW
+   select SYS_PPC_E500_USE_DEBUG_TLB
 
 config ARCH_MPC8548
bool
select FSL_LAW
+   select SYS_PPC_E500_USE_DEBUG_TLB
 
 config ARCH_MPC8555
bool
@@ -386,22 +391,27 @@ config ARCH_MPC8572
 config ARCH_P1010
bool
select FSL_LAW
+   select SYS_PPC_E500_USE_DEBUG_TLB
 
 config ARCH_P1011
bool
select FSL_LAW
+   select SYS_PPC_E500_USE_DEBUG_TLB
 
 config ARCH_P1020
bool
select FSL_LAW
+   select SYS_PPC_E500_USE_DEBUG_TLB
 
 config ARCH_P1021
bool
select FSL_LAW
+   select SYS_PPC_E500_USE_DEBUG_TLB
 
 config ARCH_P1022
bool
select FSL_LAW
+   select SYS_PPC_E500_USE_DEBUG_TLB
 
 config ARCH_P1023
bool
@@ -410,14 +420,17 @@ config ARCH_P1023
 config ARCH_P1024
bool
select FSL_LAW
+   select SYS_PPC_E500_USE_DEBUG_TLB
 
 config ARCH_P1025
bool
select FSL_LAW
+   select SYS_PPC_E500_USE_DEBUG_TLB
 
 config ARCH_P2020
bool
select FSL_LAW
+   select SYS_PPC_E500_USE_DEBUG_TLB
 
 config ARCH_P2041
bool
@@ -655,6 +668,33 @@ config SYS_NUM_TLBCAMS
Number of TLB CAM entries for Book-E chips. 64 for E500MC,
16 for other E500 SoCs.
 
+config SYS_PPC_E500_USE_DEBUG_TLB
+   bool
+
+config SYS_PPC_E500_DEBUG_TLB
+   int "Temporary TLB entry for external debugger"
+   depends on SYS_PPC_E500_USE_DEBUG_TLB
+   default 0 ifARCH_MPC8544 || ARCH_MPC8548
+   default 1 ifARCH_MPC8536
+   default 2 ifARCH_MPC8572|| \
+   ARCH_P1011  || \
+   ARCH_P1020  || \
+   ARCH_P1021  || \
+   ARCH_P1022  || \
+   ARCH_P1024  || \
+   ARCH_P1025  || \
+   ARCH_P2020
+   default 3 ifARCH_P1010  || \
+   ARCH_BSC9132|| \
+   ARCH_C29X
+   help
+   Select a temporary TLB entry to be used during boot to work
+around limitations in e500v1 and e500v2 external debugger
+support. This reduces the portions of the boot code where
+breakpoints and single stepping do not work. The value of this
+symbol should be set to the TLB1 entry to be used for this
+purpose. If unsure, do not change.
+
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 5761218..cbaba36 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -25,7 +25,6 @@
 #define CONFIG_SYS_FSL_SEC_MON_BE
 
 #if defined(CONFIG_ARCH_MPC8536)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB  1
 #define CONFIG_SYS_FSL_SEC_COMPAT  2
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 #define 

[U-Boot] [PATCH v4 3/4] arm: am57xx: cl-som-am57x: add ETH support

[Uri Mashiach]

From: Dmitry Lifshitz 

Add MAC support.

Use PHY, connected to RGMII1 as a default Eth adapter,
by appropriate setting of 'cpsw_data.active_slave'.

'cpsw_phy' env variable can override this setting.

Set the MAC addresses in the U-Boot environment.
The addresses are retrieved from the on-board EEPROM or from the SOC's
MAC fuses.

Set the following PHYs RGMII clock delays:
- Enable RX delay
- Disable TX delay

Signed-off-by: Dmitry Lifshitz 
[uri.mashi...@compulab.co.il: add RGMII clock delays]
Signed-off-by: Uri Mashiach 
Acked-by: Igor Grinberg 
Reviewed-by: Tom Rini 
---
v3 -> v4: No modifications

 board/compulab/cl-som-am57x/Makefile |   2 +
 board/compulab/cl-som-am57x/eth.c| 198 +++
 board/compulab/cl-som-am57x/mux.c|  23 
 include/configs/cl-som-am57x.h   |  17 +++
 4 files changed, 240 insertions(+)
 create mode 100644 board/compulab/cl-som-am57x/eth.c

diff --git a/board/compulab/cl-som-am57x/Makefile 
b/board/compulab/cl-som-am57x/Makefile
index 0c59781..566366b 100644
--- a/board/compulab/cl-som-am57x/Makefile
+++ b/board/compulab/cl-som-am57x/Makefile
@@ -13,3 +13,5 @@ obj-y += spl.o mux.o
 else
 obj-y  += cl-som-am57x.o mux.o
 endif
+
+obj-$(CONFIG_DRIVER_TI_CPSW)   += eth.o
diff --git a/board/compulab/cl-som-am57x/eth.c 
b/board/compulab/cl-som-am57x/eth.c
new file mode 100644
index 000..0c4bf91
--- /dev/null
+++ b/board/compulab/cl-som-am57x/eth.c
@@ -0,0 +1,198 @@
+/*
+ * Ethernet specific code for CompuLab CL-SOM-AM57x module
+ *
+ * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
+ *
+ * Author: Uri Mashiach 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "../common/eeprom.h"
+
+static void cpsw_control(int enabled)
+{
+   /* VTP can be added here */
+}
+
+static struct cpsw_slave_data cl_som_am57x_cpsw_slaves[] = {
+   {
+   .slave_reg_ofs  = 0x208,
+   .sliver_reg_ofs = 0xd80,
+   .phy_addr   = 0,
+   .phy_if = PHY_INTERFACE_MODE_RMII,
+   },
+   {
+   .slave_reg_ofs  = 0x308,
+   .sliver_reg_ofs = 0xdc0,
+   .phy_addr   = 1,
+   .phy_if = PHY_INTERFACE_MODE_RMII,
+
+   },
+};
+
+static struct cpsw_platform_data cl_som_am57_cpsw_data = {
+   .mdio_base  = CPSW_MDIO_BASE,
+   .cpsw_base  = CPSW_BASE,
+   .mdio_div   = 0xff,
+   .channels   = 8,
+   .cpdma_reg_ofs  = 0x800,
+   .slaves = 2,
+   .slave_data = cl_som_am57x_cpsw_slaves,
+   .ale_reg_ofs= 0xd00,
+   .ale_entries= 1024,
+   .host_port_reg_ofs  = 0x108,
+   .hw_stats_reg_ofs   = 0x900,
+   .bd_ram_ofs = 0x2000,
+   .mac_control= (1 << 5),
+   .control= cpsw_control,
+   .host_port_num  = 0,
+   .version= CPSW_CTRL_VERSION_2,
+};
+
+/*
+ * cl_som_am57x_efuse_read_mac_addr() - read Ethernet port MAC address.
+ *   The information is retrieved from the SOC's registers.
+ * @buff: read buffer.
+ * @port_num: port number.
+ */
+static void cl_som_am57x_efuse_read_mac_addr(uchar *buff, uint port_num)
+{
+   uint32_t mac_hi, mac_lo;
+
+   if (port_num) {
+   mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
+   mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
+   } else {
+   mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
+   mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
+   }
+
+   buff[0] = (mac_hi & 0xFF) >> 16;
+   buff[1] = (mac_hi & 0xFF00) >> 8;
+   buff[2] = mac_hi & 0xFF;
+   buff[3] = (mac_lo & 0xFF) >> 16;
+   buff[4] = (mac_lo & 0xFF00) >> 8;
+   buff[5] = mac_lo & 0xFF;
+}
+
+/*
+ * cl_som_am57x_handle_mac_address() - set MAC address in the U-Boot
+ * environment.
+ *  The address is retrieved retrieved from an EEPROM field or from the
+ * SOC's registers.
+ * @env_name: U-Boot environment name.
+ * @field_name: EEPROM field name.
+ * @port_num: SOC's port number.
+ */
+static int cl_som_am57x_handle_mac_address(char *env_name, uint port_num)
+{
+   int ret;
+   uint8_t enetaddr[6];
+
+   ret = eth_getenv_enetaddr(env_name, enetaddr);
+   if (ret)
+   return 0;
+
+   ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
+
+   if (ret || !is_valid_ethaddr(enetaddr))
+   cl_som_am57x_efuse_read_mac_addr(enetaddr, port_num);
+
+   if (!is_valid_ethaddr(enetaddr))
+   return -1;
+
+   ret = eth_setenv_enetaddr(env_name, enetaddr);
+   if (ret)
+   

[U-Boot] [PATCH v4 1/4] arm: am57xx: cl-som-am57x: add initial board support

[Uri Mashiach]

From: Dmitry Lifshitz 

Features supported :

* Serial console
* SPI Flash
* MMC/SD Card
* eMMC storage
* SATA
* PCA9555 - GPIO expander over I2C5 bus
* USB

Use spl alternate boot device feature to define fallback to
the main boot device as it is defined by hardware.

Signed-off-by: Dmitry Lifshitz 
[uri.mashi...@compulab.co.il: Adjust to v2016.11]
Signed-off-by: Uri Mashiach 
Acked-by: Igor Grinberg 
---
v3 -> v4: Adjusted to v2017.01-rc2:
  * arch/arm/mach-omap2/omap5/Kconfig - new board configuration moved 
to a new location.
  * Variable cl_som_am57x_volts initialization.

 arch/arm/mach-omap2/omap5/Kconfig  |   4 +
 board/compulab/cl-som-am57x/Kconfig|  12 ++
 board/compulab/cl-som-am57x/MAINTAINERS|   6 +
 board/compulab/cl-som-am57x/Makefile   |  15 ++
 board/compulab/cl-som-am57x/cl-som-am57x.c |  62 
 board/compulab/cl-som-am57x/mux.c  | 100 
 board/compulab/cl-som-am57x/spl.c  | 234 +
 configs/cl-som-am57x_defconfig |  41 +
 include/configs/cl-som-am57x.h | 105 +
 9 files changed, 579 insertions(+)
 create mode 100644 board/compulab/cl-som-am57x/Kconfig
 create mode 100644 board/compulab/cl-som-am57x/MAINTAINERS
 create mode 100644 board/compulab/cl-som-am57x/Makefile
 create mode 100644 board/compulab/cl-som-am57x/cl-som-am57x.c
 create mode 100644 board/compulab/cl-som-am57x/mux.c
 create mode 100644 board/compulab/cl-som-am57x/spl.c
 create mode 100644 configs/cl-som-am57x_defconfig
 create mode 100644 include/configs/cl-som-am57x.h

diff --git a/arch/arm/mach-omap2/omap5/Kconfig 
b/arch/arm/mach-omap2/omap5/Kconfig
index 018e584..242d1ee 100644
--- a/arch/arm/mach-omap2/omap5/Kconfig
+++ b/arch/arm/mach-omap2/omap5/Kconfig
@@ -40,6 +40,9 @@ choice
prompt "OMAP5 board select"
optional
 
+config TARGET_CL_SOM_AM57X
+   bool "CompuLab CL-SOM-AM57x"
+
 config TARGET_CM_T54
bool "CompuLab CM-T54"
 
@@ -179,6 +182,7 @@ endchoice
 endmenu
 endif
 
+source "board/compulab/cl-som-am57x/Kconfig"
 source "board/compulab/cm_t54/Kconfig"
 source "board/ti/omap5_uevm/Kconfig"
 source "board/ti/dra7xx/Kconfig"
diff --git a/board/compulab/cl-som-am57x/Kconfig 
b/board/compulab/cl-som-am57x/Kconfig
new file mode 100644
index 000..85fc9a1
--- /dev/null
+++ b/board/compulab/cl-som-am57x/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CL_SOM_AM57X
+
+config SYS_BOARD
+   default "cl-som-am57x"
+
+config SYS_VENDOR
+   default "compulab"
+
+config SYS_CONFIG_NAME
+   default "cl-som-am57x"
+
+endif
diff --git a/board/compulab/cl-som-am57x/MAINTAINERS 
b/board/compulab/cl-som-am57x/MAINTAINERS
new file mode 100644
index 000..e0195f4
--- /dev/null
+++ b/board/compulab/cl-som-am57x/MAINTAINERS
@@ -0,0 +1,6 @@
+CL-SOM-AM57x BOARD
+M: Uri Mashiach 
+S: Maintained
+F: board/compulab/cl-som-am57x/
+F: include/configs/cl-som-am57x.h
+F: configs/cl-som-am57x_defconfig
diff --git a/board/compulab/cl-som-am57x/Makefile 
b/board/compulab/cl-som-am57x/Makefile
new file mode 100644
index 000..0c59781
--- /dev/null
+++ b/board/compulab/cl-som-am57x/Makefile
@@ -0,0 +1,15 @@
+#
+# Makefile
+#
+# (C) Copyright 2016 CompuLab, Ltd. 
+#
+# Author: Dmitry Lifshitz 
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y  += spl.o mux.o
+else
+obj-y  += cl-som-am57x.o mux.o
+endif
diff --git a/board/compulab/cl-som-am57x/cl-som-am57x.c 
b/board/compulab/cl-som-am57x/cl-som-am57x.c
new file mode 100644
index 000..4bad644
--- /dev/null
+++ b/board/compulab/cl-som-am57x/cl-som-am57x.c
@@ -0,0 +1,62 @@
+/*
+ * Board functions for CompuLab cl_som_am57x board
+ *
+ * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
+ *
+ * Author: Dmitry Lifshitz 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+   "Board: CL-SOM-AM57x\n"
+};
+
+int board_init(void)
+{
+   /* Disable PMIC Powerhold feature, DEV_CTRL.DEV_ON = 1 */
+   palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
+
+   gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+   return 0;
+}
+
+#ifdef CONFIG_GENERIC_MMC
+#define SB_SOM_CD_GPIO 187
+#define SB_SOM_WP_GPIO 188
+
+int board_mmc_init(bd_t *bis)
+{
+   int ret0, ret1;
+
+   ret0 = omap_mmc_init(0, 0, 0, SB_SOM_CD_GPIO, SB_SOM_WP_GPIO);
+   if (ret0)
+   printf("cl-som-am57x: failed to initialize mmc0\n");
+
+   ret1 = omap_mmc_init(1, 0, 0, -1, -1);
+   if (ret1)
+   printf("cl-som-am57x: failed to initialize mmc1\n");
+
+   return ret0 && ret1;
+}
+#endif /* CONFIG_GENERIC_MMC */
+
+#ifdef 

[U-Boot] [PATCH v4 0/4] cl-som-am57x: initial support

[Uri Mashiach]

This patch series adds support for CompuLab CL-SOM-AM57X board and the
SBC-AM57X evaluation kit.

CL-SOM-AM57x is a miniature System-on-Module (SoM) based on
TI Sitara AM57x ARM Cortex-A15 System-on-Chip family.

SBC-AM57x is a single board computer, implemented with the
CL-SOM-AM57x computer-on-module and the SB-SOM-AM57x carrier board.
The CL-SOM-AM57x providing most of the functions and the SB-SOM-AM57x providing
additional peripheral functions and connectors.

The SBC-AM57x has the following features:


CPU:Texas Instruments Sitara AM5728 dual-core ARM Cortex-A15, 
1.5GHz or
Texas Instruments Sitara AM5718 single-core ARM Cortex-A15, 
1.5GHz

RAM:DDR3, 512MB – 4GB

Storage:NAND flash, 512MB - 1GB or eMMC flash, 4GB - 32GB
SPI-flash 2MB

Ethernet:   Up to 2x 10/100/1000Mbps Ethernet ports (MAC+PHY)

WiFi/BT:802.11b/g/n WiFi interface (TI WiLink 8 WL1801 chipset) or
Dual-band 2x2 802.11a/b/g/n WiFi interface (TI WiLink 8 WL1837 
chipset)

Analog Audio:   Audio codec with stereo output, stereo input and microphone 
support

More details can be found here:

https://www.compulab.co.il/products/computer-on-modules/cl-som-am57x-ti-am5728-am5718-system-on-module/

https://www.compulab.co.il/products/sbcs/sbc-am57x-ti-am5728-am5718-single-board-computer/

---
v3 -> v4: Adjusted to v2017.01-rc2

Dmitry Lifshitz (3):
  arm: am57xx: cl-som-am57x: add initial board support
  arm: am57xx: cl-som-am57x: fetch board rev from EEPROM
  arm: am57xx: cl-som-am57x: add ETH support

Uri Mashiach (1):
  arm: am57xx: cl-som-am57x: update default env

 arch/arm/mach-omap2/omap5/Kconfig  |   4 +
 board/compulab/cl-som-am57x/Kconfig|  12 ++
 board/compulab/cl-som-am57x/MAINTAINERS|   6 +
 board/compulab/cl-som-am57x/Makefile   |  17 +++
 board/compulab/cl-som-am57x/cl-som-am57x.c |  76 ++
 board/compulab/cl-som-am57x/eth.c  | 198 
 board/compulab/cl-som-am57x/mux.c  | 123 +++
 board/compulab/cl-som-am57x/spl.c  | 234 +
 configs/cl-som-am57x_defconfig |  41 +
 include/configs/cl-som-am57x.h | 197 
 10 files changed, 908 insertions(+)
 create mode 100644 board/compulab/cl-som-am57x/Kconfig
 create mode 100644 board/compulab/cl-som-am57x/MAINTAINERS
 create mode 100644 board/compulab/cl-som-am57x/Makefile
 create mode 100644 board/compulab/cl-som-am57x/cl-som-am57x.c
 create mode 100644 board/compulab/cl-som-am57x/eth.c
 create mode 100644 board/compulab/cl-som-am57x/mux.c
 create mode 100644 board/compulab/cl-som-am57x/spl.c
 create mode 100644 configs/cl-som-am57x_defconfig
 create mode 100644 include/configs/cl-som-am57x.h

-- 
2.7.4

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[U-Boot] [PATCH v4 2/4] arm: am57xx: cl-som-am57x: fetch board rev from EEPROM

[Uri Mashiach]

From: Dmitry Lifshitz 

Add PCB revision message.
Implement board revision get_board_rev API.

Signed-off-by: Dmitry Lifshitz 
Commit description update.
Signed-off-by: Uri Mashiach 
Acked-by: Igor Grinberg 
Reviewed-by: Tom Rini 
---
v3 -> v4: No modifications

 board/compulab/cl-som-am57x/cl-som-am57x.c | 14 ++
 include/configs/cl-som-am57x.h | 14 ++
 2 files changed, 28 insertions(+)

diff --git a/board/compulab/cl-som-am57x/cl-som-am57x.c 
b/board/compulab/cl-som-am57x/cl-som-am57x.c
index 4bad644..bdd0a2b 100644
--- a/board/compulab/cl-som-am57x/cl-som-am57x.c
+++ b/board/compulab/cl-som-am57x/cl-som-am57x.c
@@ -14,6 +14,8 @@
 #include 
 #include 
 #include 
+#include "../common/common.h"
+#include "../common/eeprom.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -60,3 +62,15 @@ int board_usb_init(int index, enum usb_init_type init)
return 0;
 }
 #endif /* CONFIG_USB_XHCI_OMAP */
+
+int misc_init_r(void)
+{
+   cl_print_pcb_info();
+
+   return 0;
+}
+
+u32 get_board_rev(void)
+{
+   return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
+}
diff --git a/include/configs/cl-som-am57x.h b/include/configs/cl-som-am57x.h
index c8d4a00..48c0f7f 100644
--- a/include/configs/cl-som-am57x.h
+++ b/include/configs/cl-som-am57x.h
@@ -24,6 +24,10 @@
 
 #include 
 
+/* misc */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_REVISION_TAG
+
 /* Status LED */
 #define CONFIG_STATUS_LED  /* Status LED enabled */
 #define CONFIG_GPIO_LED
@@ -65,6 +69,16 @@
 #define CONFIG_ENV_OFFSET  (768 * 1024)
 #define CONFIG_ENV_SPI_MAX_HZ  4800
 
+/* EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR  0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
+#define CONFIG_SYS_I2C_EEPROM_BUS   3
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_EEPROM_SIZE 256
+
 #ifndef CONFIG_SPL_BUILD
 /* SATA */
 #define CONFIG_CMD_SCSI
-- 
2.7.4

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[U-Boot] [PATCH v4 4/4] arm: am57xx: cl-som-am57x: update default env

[Uri Mashiach]

Modify U-Boot default env settings.

Boot sequence:
1. SD card boot script
2. SD card boot no script
3. SATA boot script
4. SATA boot no script
5. eMMC boot script
6. eMMC boot no script

Signed-off-by: Uri Mashiach 
Acked-by: Igor Grinberg 
Reviewed-by: Tom Rini 
---
v3 -> v4: No modifications

 include/configs/cl-som-am57x.h | 61 ++
 1 file changed, 61 insertions(+)

diff --git a/include/configs/cl-som-am57x.h b/include/configs/cl-som-am57x.h
index 2001b0c..8297182 100644
--- a/include/configs/cl-som-am57x.h
+++ b/include/configs/cl-som-am57x.h
@@ -133,4 +133,65 @@
 
 #endif /* !CONFIG_SPL_BUILD */
 
+/* Default environment */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+   DEFAULT_LINUX_BOOT_ENV \
+   "autoload=no\0" \
+   "baudrate=115200\0" \
+   "console=ttyO2,115200n8\0" \
+   "bootdelay=3\0" \
+   "fdtfile=am57xx-sbc-am57x.dtb\0" \
+   "kernel=zImage-cl-som-am57x\0" \
+   "bootscr=bootscr.img\0" \
+   "displaytype=hdmi\0" \
+   "bootkernel=bootz ${loadaddr} - ${fdtaddr}\0" \
+   "mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
+   "mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \
+   "load_mmc=mmc dev ${mmcdev} && mmc rescan && " \
+   "run mmcloadkernel run mmcloadfdt\0" \
+   "mmcroot=/dev/mmcblk1p2\0" \
+   "mmcrootfstype=ext4 rw rootwait\0" \
+   "mmcargs=setenv bootargs console=${console} root=${mmcroot} " \
+   "rootfstype=${mmcrootfstype}\0" \
+   "mmcbootscript=setenv mmcdev 0; mmc dev ${mmcdev} && mmc rescan && " \
+   "load mmc ${mmcdev} ${loadaddr} ${bootscr} && " \
+   "echo Running bootscript from MMC/SD Card ... && " \
+   "source ${loadaddr}\0" \
+   "mmcboot=setenv mmcdev 0 && run load_mmc && " \
+   "run mmcargs && echo Booting from MMC/SD Card ... && " \
+   "run bootkernel\0" \
+   "emmcroot=/dev/mmcblk0p2\0" \
+   "emmcrootfstype=ext4 rw rootwait\0" \
+   "emmcargs=setenv bootargs console=${console} " \
+   "root=${emmcroot} " \
+   "rootfstype=${emmcrootfstype}\0" \
+   "emmcbootscript=setenv mmcdev 1; mmc dev ${mmcdev} && mmc rescan && " \
+   "load mmc ${mmcdev} ${loadaddr} ${bootscr} && " \
+   "echo Running bootscript from eMMC ... && " \
+   "source ${loadaddr}\0" \
+   "emmcboot=setenv mmcdev 1 && run load_mmc && " \
+   "run emmcargs && echo Booting from eMMC ... && " \
+   "run bootkernel\0" \
+   "sataroot=/dev/sda2\0" \
+   "satarootfstype=ext4 rw rootwait\0" \
+   "load_sata=load scsi 0 ${loadaddr} ${kernel} && " \
+   "load scsi 0 ${fdtaddr} ${fdtfile}\0" \
+   "sataargs=setenv bootargs console=${console} " \
+   "root=${sataroot} " \
+   "rootfstype=${satarootfstype}\0" \
+   "satabootscript=load scsi 0 ${loadaddr} ${bootscr} && " \
+   "echo Running bootscript from SATA ... && " \
+   "source ${loadaddr}\0" \
+   "sataboot=run load_sata && run sataargs && " \
+   "echo Booting from SATA ... && " \
+   "run bootkernel\0" \
+
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND \
+   "run mmcbootscript || run mmcboot || " \
+   "run satabootscript || run sataboot || " \
+   "run emmcbootscript || run emmcboot"
+
+
 #endif /* __CONFIG_CL_SOM_AM57X_H */
-- 
2.7.4

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[U-Boot] curious snippet in drivers/mtd/dataflash.c

[Robert P. J. Day]

  not sure about this bit of code in that source file:

/* Set the environment according to the label...*/
if(protected == FLAG_PROTECT_INVALID) {
dataflash_info[i].Device.area_list[j].protected =
FLAG_PROTECT_INVALID;
} else {
dataflash_info[i].Device.area_list[j].protected =
protected;
}

is that not just setting the value to "protected" in both cases? what
is the point of that conditional?

rday

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[U-Boot] i'm assuming comment "/* board/?/flash.c */" in flash.h is way obsolete

[Robert P. J. Day]

  digging around in CONFIG_SYS_FLASH_PROTECTION, and i see this
snippet in include/flash.h:

  /* board/?/flash.c */
  #if defined(CONFIG_SYS_FLASH_PROTECTION)
  extern int flash_real_protect(flash_info_t *info, long sector, int prot);
  extern void flash_read_user_serial(flash_info_t * info, void * buffer,   int 
offset, int len);
  extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int 
offset, int len);
  #endif  /* CONFIG_SYS_FLASH_PROTECTION */

i'm assuming that opening comment is long-since obsolete, yes? i can
submit a patch to trash it, but since i'm poring over that file, i can
collect any other tweaks anyone else wants to suggest to make it worth
it. any other content in that file that needs updating or removal?

  no rush.

rday

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[U-Boot] [PATCH] armv8: release slave cores from CPU_RELEASE_ADDR

[Oded Gabbay]

When using ARMv8 with ARMV8_SPIN_TABLE=y, we want the slave cores to
wait on spin_table_cpu_release_addr, until the Linux kernel will "wake" them
by writing to that location. The address of spin_table_cpu_release_addr is
transferred to the kernel using the device tree that is updated by
spin_table_update_dt().

However, if we also use SPL, then the slave cores are stuck at
CPU_RELEASE_ADDR instead and as a result, never wake up.

This patch releases the slave cores by writing spl_image->entry_point to
CPU_RELEASE_ADDR location before the end of the SPL code
(at jump_to_image_no_args()).

That way, the slave cores will start to execute the u-boot and will get to
the spin-table code and wait on the correct address
(spin_table_cpu_release_addr).

Signed-off-by: Oded Gabbay 
Cc: Simon Glass 
---
 common/spl/spl.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index f7df834..63d7db9 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -167,6 +167,14 @@ __weak void __noreturn jump_to_image_no_args(struct 
spl_image_info *spl_image)
(image_entry_noargs_t)(unsigned long)spl_image->entry_point;
 
debug("image entry point: 0x%X\n", spl_image->entry_point);
+#if defined(CONFIG_ARMV8_SPIN_TABLE) && defined(CONFIG_ARMV8_MULTIENTRY)
+   /*
+* Release all slave cores from CPU_RELEASE_ADDR so they could
+* arrive to the spin-table code in start.S of the u-boot
+*/
+   *(ulong *)CPU_RELEASE_ADDR = (ulong)spl_image->entry_point;
+#endif
+
image_entry();
 }
 
-- 
2.7.4

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Re: [U-Boot] [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system initialization

[Z.Q. Hou]

Hi Prabhakar,

> -Original Message-
> From: Prabhakar Kushwaha
> Sent: 2016年12月28日 17:27
> To: Z.Q. Hou ; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; york sun ; Mingkai Hu
> ; Calvin Johnson 
> Subject: RE: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system
> initialization
> 
> 
> > -Original Message-
> > From: Z.Q. Hou
> > Sent: Wednesday, December 28, 2016 11:41 AM
> > To: Prabhakar Kushwaha ; u-
> > b...@lists.denx.de; albert.u.b...@aribaud.net; york sun
> > ; Mingkai Hu ; Calvin Johnson
> > 
> > Subject: RE: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock system
> > initialization
> >
> > Hi Prabhakar,
> >
> > Thanks a lot for your comments!
> >
> > > -Original Message-
> > > From: Prabhakar Kushwaha
> > > Sent: 2016年12月28日 12:06
> > > To: Z.Q. Hou ; u-boot@lists.denx.de;
> > > albert.u.b...@aribaud.net; york sun ; Mingkai Hu
> > > ; Calvin Johnson 
> > > Subject: RE: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock
> > > system initialization
> > >
> > >
> > > > -Original Message-
> > > > From: Z.Q. Hou
> > > > Sent: Tuesday, December 27, 2016 3:58 PM
> > > > To: Prabhakar Kushwaha ; u-
> > > > b...@lists.denx.de; albert.u.b...@aribaud.net; york sun
> > > > ; Mingkai Hu ; Calvin
> > > > Johnson 
> > > > Subject: RE: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock
> > > > system initialization
> > > >
> > > > Hi Prabhakar,
> > > >
> > > > Thanks a lot for your comments!
> > > >
> > > > > -Original Message-
> > > > > From: Prabhakar Kushwaha
> > > > > Sent: 2016年12月27日 16:59
> > > > > To: Z.Q. Hou ; u-boot@lists.denx.de;
> > > > > albert.u.b...@aribaud.net; york sun ; Mingkai
> > > > > Hu ; Calvin Johnson 
> > > > > Cc: Z.Q. Hou 
> > > > > Subject: RE: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock
> > > > > system initialization
> > > > >
> > > > >
> > > > > > -Original Message-
> > > > > > From: Zhiqiang Hou [mailto:zhiqiang@nxp.com]
> > > > > > Sent: Tuesday, December 27, 2016 1:06 PM
> > > > > > To: u-boot@lists.denx.de; albert.u.b...@aribaud.net; york sun
> > > > > > ; Mingkai Hu ;
> Prabhakar
> > > > > > Kushwaha ; Calvin Johnson
> > > > > > 
> > > > > > Cc: Z.Q. Hou 
> > > > > > Subject: [PATCHv3 1/2] armv8/fsl-lsch2: refactor the clock
> > > > > > system initialization
> > > > > >
> > > > > > From: Hou Zhiqiang 
> > > > > >
> > > > > > Up to now, there are 3 kind of SoCs under Layerscape Chassis
> > > > > > 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has
> > > > > > a lot of differences, for instance, the IP modules have
> > > > > > different dividers to derive its clock from Platform PLL. And
> > > > > > the core cluster PLL and platform PLL maybe have different
> > > > > > reference clocks, such
> > > as LS1012A.
> > > > > > Another problem is which clock/PLL should be described by
> > > > > > sys_info->freq_systembus, it is confused in Layerscape Chissis 2.
> > > > > >
> > > > > > This patch is to bind the sys_info->freq_systembus to the
> > > > > > Platform PLL, and handle the different divider of IP modules
> > > > > > separately between different SoCs, and separate reference
> > > > > > clocks of core cluster PLL and platform PLL.
> > > > > >
> > > > > > Signed-off-by: Hou Zhiqiang 
> > > > > > ---
> > > > > > V3:
> > > > > >  - Generate the patch set base on the latest
> > > > > > git://git.denx.de/u-boot-fsl- qoriq.git.
> > > > > >  - Use the Kconfig instead of header file to add CONFIG_*
> > > > > >
> > > > > >  arch/arm/cpu/armv8/fsl-layerscape/Kconfig  | 76
> > > > > > ++
> > > > > >  arch/arm/cpu/armv8/fsl-layerscape/cpu.c|  3 +-
> > > > > >  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 68
> > > > > > ++-
> > > > > > ++.../include/asm/arch-fsl-layerscape/immap_lsch2.
> > > > > > ++h
> > > > > |  1 +
> > > > > >  include/configs/ls1012a_common.h   |  6 +-
> > > > > >  include/configs/ls1043a_common.h   |  3 +-
> > > > > >  include/configs/ls1046a_common.h   |  3 +-
> > > > > >  include/configs/ls2080aqds.h   |  2 -
> > > > > >  include/configs/ls2080ardb.h   |  1 -
> > > > > >  9 files changed, 134 insertions(+), 29 deletions(-)
> > > > > >
> > > > > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > > > > > 

Re: [U-Boot] [RESEND PATCH v3 1/2] mmc: rockchip_sdhci: add clock init for mmc

[Jaehoon Chung]

On 12/28/2016 12:32 PM, Kever Yang wrote:
> Init the clock rate to max-frequency from dts with clock driver api.
> 
> Signed-off-by: Kever Yang 

Reviewed-by: Jaehoon Chung 

Best Regards,
Jaehoon Chung

> ---
> 
> Changes in v3:
> - using dt for max-frequency
> Series-changes: 2
> - using the return value
> 
>  drivers/mmc/rockchip_sdhci.c | 19 +--
>  1 file changed, 17 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
> index c56e1a3..e33e35e 100644
> --- a/drivers/mmc/rockchip_sdhci.c
> +++ b/drivers/mmc/rockchip_sdhci.c
> @@ -12,7 +12,9 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
> +DECLARE_GLOBAL_DATA_PTR;
>  /* 400KHz is max freq for card ID etc. Use that as min */
>  #define EMMC_MIN_FREQ40
>  
> @@ -32,11 +34,24 @@ static int arasan_sdhci_probe(struct udevice *dev)
>   struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
>   struct rockchip_sdhc *prv = dev_get_priv(dev);
>   struct sdhci_host *host = >host;
> - int ret;
> + int max_frequency, ret;
> + struct clk clk;
> +
> +
> + max_frequency = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
> + "max-frequency", 0);
> + ret = clk_get_by_index(dev, 0, );
> + if (!ret) {
> + ret = clk_set_rate(, max_frequency);
> + if (IS_ERR_VALUE(ret))
> + printf("%s clk set rate fail!\n", __func__);
> + } else {
> + printf("%s fail to get clk\n", __func__);
> + }
>  
>   host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
>  
> - ret = sdhci_setup_cfg(>cfg, host, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ,
> + ret = sdhci_setup_cfg(>cfg, host, max_frequency,
>   EMMC_MIN_FREQ);
>  
>   host->mmc = >mmc;
> 

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Re: [U-Boot] [RESEND PATCH v3 2/2] dts: arm64: rk3399: add max-frequency for sdhci

[Jaehoon Chung]

On 12/28/2016 12:32 PM, Kever Yang wrote:
> Add 'max-frequency' for sdhci node for clock init.
> 
> Signed-off-by: Kever Yang 

Reviewed-by: Jaehoon Chung 

Best Regards,
Jaehoon Chung

> ---
> 
> Changes in v3: None
> 
>  arch/arm/dts/rk3399.dtsi | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
> index 179860c..22277ff 100644
> --- a/arch/arm/dts/rk3399.dtsi
> +++ b/arch/arm/dts/rk3399.dtsi
> @@ -188,6 +188,7 @@
>   interrupts = ;
>   assigned-clocks = < SCLK_EMMC>;
>   assigned-clock-rates = <2>;
> + max-frequency = <2>;
>   clocks = < SCLK_EMMC>, < ACLK_EMMC>;
>   clock-names = "clk_xin", "clk_ahb";
>   phys = <_phy>;
> 

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Re: [U-Boot] [U-Boot,v6,11/13] sunxi: Use binman for sunxi boards

[Emmanuel Vadot]

On Wed, 28 Dec 2016 11:30:10 +0100
Emmanuel Vadot  wrote:

> 
>  Hello Simon,
> 
> On Fri, 23 Dec 2016 01:39:06 -0700
> Simon Glass  wrote:
> 
> > On 18 December 2016 at 19:48, Tom Rini  wrote:
> > > On Fri, Nov 25, 2016 at 08:16:01PM -0700, Simon Glass wrote:
> > >
> > >> Move sunxi boards to use binman. This involves adding the image 
> > >> definition
> > >> to the device tree and using it in the Makefile.
> > >>
> > >> Signed-off-by: Simon Glass 
> > >
> > > Reviewed-by: Tom Rini 
> > >
> > > --
> > > Tom
> > 
> > Applied to u-boot-dm and now in mainline.
> 
>  Shouldn't all the config for sunxi board defines
> CONFIG_SPL_OF_PLATDATA=y now so libfdt.so will be built ?
> 

 Sorry, I meant the python module.

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Re: [U-Boot] [U-Boot,v6,11/13] sunxi: Use binman for sunxi boards

[Emmanuel Vadot]

 Hello Simon,

On Fri, 23 Dec 2016 01:39:06 -0700
Simon Glass  wrote:

> On 18 December 2016 at 19:48, Tom Rini  wrote:
> > On Fri, Nov 25, 2016 at 08:16:01PM -0700, Simon Glass wrote:
> >
> >> Move sunxi boards to use binman. This involves adding the image definition
> >> to the device tree and using it in the Makefile.
> >>
> >> Signed-off-by: Simon Glass 
> >
> > Reviewed-by: Tom Rini 
> >
> > --
> > Tom
> 
> Applied to u-boot-dm and now in mainline.

 Shouldn't all the config for sunxi board defines
CONFIG_SPL_OF_PLATDATA=y now so libfdt.so will be built ?

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Re: [U-Boot] [PATCH v2 28/63] x86: Refactor relocation to prepare for 64-bit

[Bin Meng]

Hi Simon,

On Sun, Nov 20, 2016 at 4:25 AM, Simon Glass  wrote:
> Move the core relocation code into a separate function so that the checking
> code can be used for 64-bit relocation also.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  arch/x86/lib/relocate.c | 57 
> -
>  1 file changed, 33 insertions(+), 24 deletions(-)
>
> diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c
> index 0d683bf..21cd1db 100644
> --- a/arch/x86/lib/relocate.c
> +++ b/arch/x86/lib/relocate.c
> @@ -47,38 +47,18 @@ int clear_bss(void)
> return 0;
>  }
>
> -/*
> - * This function has more error checking than you might expect. Please see
> - * the commit message for more informaiton.
> - */
> -int do_elf_reloc_fixups(void)
> +static void do_elf_reloc_fixups32(unsigned int text_base, uintptr_t size,
> + Elf32_Rel *re_src, Elf32_Rel *re_end)
>  {
> -   Elf32_Rel *re_src = (Elf32_Rel *)(&__rel_dyn_start);
> -   Elf32_Rel *re_end = (Elf32_Rel *)(&__rel_dyn_end);
> -
> Elf32_Addr *offset_ptr_rom, *last_offset = NULL;
> Elf32_Addr *offset_ptr_ram;
> -   unsigned int text_base = 0;
> -
> -   /* The size of the region of u-boot that runs out of RAM. */
> -   uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start;
> -
> -   if (gd->flags & GD_FLG_SKIP_RELOC)
> -   return 0;
> -   if (re_src == re_end)
> -   panic("No relocation data");
>
> -#ifdef CONFIG_SYS_TEXT_BASE
> -   text_base = CONFIG_SYS_TEXT_BASE;
> -#else
> -   panic("No CONFIG_SYS_TEXT_BASE");
> -#endif
> do {
> /* Get the location from the relocation entry */
> -   offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
> +   offset_ptr_rom = (Elf32_Addr *)(uintptr_t)re_src->r_offset;
>
> /* Check that the location of the relocation is in .text */
> -   if (offset_ptr_rom >= (Elf32_Addr *)text_base &&
> +   if (offset_ptr_rom >= (Elf32_Addr *)(uintptr_t)text_base &&
> offset_ptr_rom > last_offset) {
>
> /* Switch to the in-RAM version */
> @@ -103,6 +83,35 @@ int do_elf_reloc_fixups(void)
> last_offset = offset_ptr_rom;
>
> } while (++re_src < re_end);
> +}
> +
> +/*
> + * This function has more error checking than you might expect. Please see
> + * the commit message for more informaiton.

nits: I suspect we should add the commit id here since you refactored
the code in this commit, so guess it's not easy for people to track
previous commit id..

> + */
> +int do_elf_reloc_fixups(void)
> +{
> +   void *re_src = (void *)(&__rel_dyn_start);
> +   void *re_end = (void *)(&__rel_dyn_end);
> +   uint text_base;
> +
> +   /* The size of the region of u-boot that runs out of RAM. */
> +   uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start;
> +
> +   if (gd->flags & GD_FLG_SKIP_RELOC)
> +   return 0;
> +   if (re_src == re_end) {
> +   printf("No relocation data %p %p", re_src, re_end);

can we use: panic() instead of printf() here?

> +   while (1);
> +   panic("No relocation data");

The above 2 lines are not needed

> +   }
> +
> +#ifdef CONFIG_SYS_TEXT_BASE
> +   text_base = CONFIG_SYS_TEXT_BASE;
> +#else
> +   panic("No CONFIG_SYS_TEXT_BASE");
> +#endif
> +   do_elf_reloc_fixups32(text_base, size, re_src, re_end);
>
> return 0;
>  }
> --

Regards,
Bin
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[U-Boot] [PATCH] arm64: rk3399: update rockchip_get_cru API

[Kever Yang]

rk3399 has two clock-controller: cru and pmucru, update the
rockchip_get_crui() API, and rockchip_get_clk() do not used for
other module.

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c 
b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
index 7663591..ce706a6 100644
--- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
@@ -11,10 +11,10 @@
 #include 
 #include 
 
-int rockchip_get_clk(struct udevice **devp)
+static int rockchip_get_cruclk(struct udevice **devp)
 {
return uclass_get_device_by_driver(UCLASS_CLK,
-   DM_GET_DRIVER(rockchip_rk3399_pmuclk), devp);
+   DM_GET_DRIVER(clk_rk3399), devp);
 }
 
 void *rockchip_get_cru(void)
@@ -23,7 +23,7 @@ void *rockchip_get_cru(void)
struct udevice *dev;
int ret;
 
-   ret = rockchip_get_clk();
+   ret = rockchip_get_cruclk();
if (ret)
return ERR_PTR(ret);
 
-- 
1.9.1

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Re: [U-Boot] [PATCH] SPL: NOR: Add CONFIG_SPL_NOR_COPY_ENTIRE_IMAGE define to enable whole image copy from NOR

[Lukasz Majewski]

Hi Marek,

> On 12/26/2016 05:36 PM, Lukasz Majewski wrote:
> > Hi Marek,
> > 
> >> On 11/29/2016 07:18 PM, Tom Rini wrote:
> >>> On Tue, Nov 29, 2016 at 11:50:34AM +0100, Marek Vasut wrote:
>  On 11/29/2016 10:11 AM, Lukasz Majewski wrote:
> > Hi Marek,
> >
> >> On 11/28/2016 10:09 PM, Lukasz Majewski wrote:
> >>> This define gives the possibility to copy entire image
> >>> (including header - e.g. u-boot.img) from NOR parallel memory
> >>> to e.g. SDRAM. The current code only supports loading the raw
> >>> binary image (the u-boot.bin).
> >>>
> >>> The legacy behavior is preserved, since other board don't
> >>> enabled this option.
> >>
> >> So, what's the usecase again ? ;-) 
> >
> > :-)
> >
> > The use case is to allow u-boot.img being loaded from Parallel
> > NOR. The current code only supports u-boot.bin.
> 
>  Why is u-boot.bin (or the payload) not sufficient ? Why do you
>  need the header ?
> >>>
> >>> Well, the general use-case and code flow is that we load
> >>> u-boot.img (or a FIT image) and if all else fails, fall back to
> >>> assuming a .bin and a known address).
> >>>
> >> And exactly how is that whole image useful in RAM ? Sorry, I still
> >> do not see it, usually you just need the executable payload,
> >> although even that can be left in flash most of the time.
> > 
> > The use case is that I do want to boot from SD card/eMMC and NOR
> > with using u-boot.img.
> > 
> > I would like to avoid situation when for NOR I must use u-boot.bin
> > and for eMMC u-boot.img.
> > 
> > Such approach keeps things as simple as possible :-)
> 
> Oh, so it allows you to detect bitrot for the content in SPI NOR ?

I do not use SPI NOR, it is parallel NOR.

> It's a bit strange we had to use u-boot.bin with SPL there.
> 

This is how the legacy system behaves. It uses (by default) Parallel
NOR for booting (with advised/provided NOR memory timings). After doing
some measurements, it turned out that for "tunned" u-boot/SPL there
would be the best way to copy it to ram and execute it from there (just
like eMMC).

Hence, I would like to use u-boot.img in both booting scenarios.

Best regards,
Łukasz Majewski



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[U-Boot] [PATCH] spl: don't use %#l with CONFIG_USE_TINY_PRINTF

[Oded Gabbay]

In the tiny-printf implementation, there is no support for %# and/or %l. This
patch checks if CONFIG_USE_TINY_PRINTF is defined and if so, prints a
different debug statement which doesn't use %#l

Signed-off-by: Oded Gabbay 
Cc: Simon Glass 
---
 common/spl/spl.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index f7df834..23dfa2d 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -385,9 +385,14 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
debug("Unsupported OS image.. Jumping nevertheless..\n");
}
 #if defined(CONFIG_SYS_MALLOC_F_LEN) && !defined(CONFIG_SYS_SPL_MALLOC_SIZE)
+#ifdef CONFIG_USE_TINY_PRINTF
+   debug("SPL malloc() used 0x%x bytes (%d KB)\n",
+   (uint) gd->malloc_ptr, (uint) gd->malloc_ptr / 1024);
+#else
debug("SPL malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr,
  gd->malloc_ptr / 1024);
 #endif
+#endif
 
debug("loaded - jumping to U-Boot...");
spl_board_prepare_for_boot();
-- 
2.7.4

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