Re: [U-Boot] example: api: ARM example needs memset

[Emmanuel Vadot]

On Mon, 2 Jan 2017 16:30:05 -0500
Tom Rini  wrote:

> On Sat, Dec 31, 2016 at 07:05:50PM +0100, Emmanuel Vadot wrote:
> 
> > Add memset.S to the needed object for the API example and do not
> > hardcode powerpc as the arch for library assembly files.
> > 
> > Signed-off-by: Emmanuel Vadot 
> 
> This patch isn't quite correct.  Not all cases of ARM will have the
> optimized memset available to them (currently), so we can't apply this
> today.  I'm going to re-examine this post release when I'm going to have
> optimized memset/memcpy more widely available on ARM, thanks!
> 
> -- 
> Tom

 Hi Tom,

 Mhm right, I'll admit I've only tested the board I have.
 We'll just use this patch on FreeBSD for now, it seems we are the only
consumer of the API so we hit errors that nobody sees.

 Thanks !

-- 
Emmanuel Vadot  
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Re: [U-Boot] [PATCH v2 29/30] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

[Chee, Tien Fong]

On Jum, 2016-12-30 at 06:14 -0600, Dinh Nguyen wrote:
> 
> On 12/28/2016 12:34 AM, Chee Tien Fong wrote:
> > 
> > From: Tien Fong Chee 
> > 
> > This patch adding the Arria10 critical hardware initialization
> > before
> > enabling console print out in spl.
> > 
> > Signed-off-by: Tien Fong Chee 
> > Cc: Marek Vasut 
> > Cc: Dinh Nguyen 
> > Cc: Chin Liang See 
> > Cc: Tien Fong 
> > ---
> > Changes for V2
> > - Release UART from reset before enalbing console, and reverting
> > license
> >   changes.
> > ---
> >  arch/arm/mach-socfpga/spl.c | 84
> > +++--
> >  1 file changed, 82 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-
> > socfpga/spl.c
> > index fec4c7a..9e27f82 100644
> > --- a/arch/arm/mach-socfpga/spl.c
> > +++ b/arch/arm/mach-socfpga/spl.c
> > @@ -1,5 +1,5 @@
> >  /*
> > - *  Copyright (C) 2012 Altera Corporation 
> > + *  Copyright (C) 2012-2016 Altera Corporation 
> >   *
> >   * SPDX-License-Identifier:GPL-2.0+
> >   */
> > @@ -19,22 +19,32 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> > +#include 
> > +#include 
> > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +#include 
> > +#endif
> >  
> >  DECLARE_GLOBAL_DATA_PTR;
> >  
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >  static struct pl310_regs *const pl310 =
> >     (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> >  static struct scu_registers *scu_regs =
> >     (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
> >  static struct nic301_registers *nic301_regs =
> >     (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> > -static struct socfpga_system_manager *sysmgr_regs =
> > +#endif
> > +
> > +static const struct socfpga_system_manager *sysmgr_regs =
> >     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> >  
> >  u32 spl_boot_device(void)
> >  {
> >     const u32 bsel = readl(_regs->bootinfo);
> >  
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >     switch (bsel & 0x7) {
> >     case 0x1:   /* FPGA (HPS2FPGA Bridge) */
> >     return BOOT_DEVICE_RAM;
> > @@ -55,6 +65,24 @@ u32 spl_boot_device(void)
> >     printf("Invalid boot device (bsel=%08x)!\n",
> > bsel);
> >     hang();
> >     }
> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +   switch ((bsel>>12) & 0x7) {
> Spaces around the '>>'.
> 
> > 
> > +   case 0x1:   /* FPGA (HPS2FPGA Bridge) */
> > +   return BOOT_DEVICE_RAM;
> > +   case 0x2:   /* NAND Flash (1.8V) */
> > +   case 0x3:   /* NAND Flash (3.0V) */
> > +   return BOOT_DEVICE_NAND;
> > +   case 0x4:   /* SD/MMC External Transceiver (1.8V) */
> > +   case 0x5:   /* SD/MMC Internal Transceiver (3.0V) */
> > +   return BOOT_DEVICE_MMC1;
> > +   case 0x6:   /* QSPI Flash (1.8V) */
> > +   case 0x7:   /* QSPI Flash (3.0V) */
> > +   return BOOT_DEVICE_SPI;
> > +   default:
> > +   printf("Invalid boot device (bsel=%08x)!\n",
> > bsel);
> > +   hang();
> > +   }
> > +#endif
> >  }
> You missed my comment from V1:
> 
> You should just do a shift define  here, so you don't have to add
> all
> this extra code here. Something like
> 
>   switch ((bsel >> BOOTINFO_BSEL_SHIFT) & 0x7)
> 
Okay, noted.
> 
> Dinh
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Re: [U-Boot] [PATCH v2 21/30] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

[Chee, Tien Fong]

On Jum, 2016-12-30 at 20:04 +0100, Marek Vasut wrote:
> On 12/29/2016 05:54 AM, Chee, Tien Fong wrote:
> > 
> > On Kha, 2016-12-29 at 00:51 +0100, Marek Vasut wrote:
> > > 
> > > On 12/28/2016 07:34 AM, Chee Tien Fong wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee 
> > > > 
> > > > Enhanced defconfig file for Arria10 to enable SPL build and
> > > > supporting
> > > > device tree build for SDMMC.
> > > > 
> > > > Signed-off-by: Tien Fong Chee 
> > > > Cc: Marek Vasut 
> > > > Cc: Dinh Nguyen 
> > > > Cc: Chin Liang See 
> > > > Cc: Tien Fong 
> > > > ---
> > > > Changes for V2
> > > > - Removed boot header info setup since it already fixed in
> > > > mainline
> > > > ---
> > > >  configs/socfpga_arria10_defconfig | 18 +-
> > > >  1 file changed, 13 insertions(+), 5 deletions(-)
> > > There's no arria10 defconfig in mainline ?
> > > I only received patches 18/30 and on ?
> > > 
> > patch1 to patch17 are 01-arria10 rebase on u-boot.git, i believe
> > those
> > patches not CC to you orginally. Could you get from U-Boot Digest,
> > Vol
> > 103, Issue 53, or you want me to edit those patches CC to you?
> No, you cannot get them from the digest, it's a digest after all.
> I can get them from the list, but please always CC maintainers on
> relevant patches.
> 
Yeah, i think so. I re-send patch1 to patch17 last week, i believe you 
received all of them already.
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Re: [U-Boot] [linux-sunxi] [PATCH v4 00/26] sunxi: Allwinner A64: SPL support

[jonsm...@gmail.com]

I recently ran into a probably with the UARTs on the A64. Many
Bluetooth modules (like Ampak) use the UART. The data rate of EDR BT
is 3Mb/s with about 2.1Mb/s though put. To handle this most systems
set the speed of the BT UART to 3Mb/s.

By default the Allwinner UART clock input is OSC24. When using OSC24
the maximum speed the UART can be set to is 1.5Mb/s. The clock input
(apb2) can be changed over to PERIPH0x2 (1.2ghz) via the device tree
and 3Mb/s is then supported.

But... there's a problem, UART0 (the console) is using the same master
clock source. So when you change the clock input over to PERIPH0x2 the
console stops working. There is no mechanism in Linux to handle this
clock source change and adjust the dividers on active uarts. So it
would be best if this master clock was set very early in u-boot and
then the console is adjusted to use it.

Are there any downsides to making this change in u-boot?

On Mon, Jan 2, 2017 at 6:48 AM, Andre Przywara  wrote:
> Hi,
>
> hopefully the final version of the SPL support series for the Allwinner A64
> SoC. Actually no real code changes this time, just rebased on top of recent
> master, adding some comments in patches 16/26 and 19/26 following Maxime's
> suggestions and adding Acked-by:s and Reviewed-by:s.
> I left the final patch 26/26 in for the sake of completeness, but don't expect
> it to be merged. We need a clever solution to unify 32-bit and 64-bit board
> configurations, but that shouldn't hold back this series for now.
> Merging everything until and including patch 21/26 (sunxi: A64: enable SPL)
> would be great, the other patches until 25/26 can go in as well, I think.
>
> -
> As the previous versions this one includes support for both AArch64 and
> AArch32 SPL builds. The FIT support is still missing, which means the
> functionality is limited. Due to the missing ARM Trusted Firmware (ATF)
> in this firmware chain we lose Ethernet and SMP, among other minor things.
> A full 64-bit build can be written to an SD card as expected and will
> boot the U-Boot proper prompt. However Linux will crash on boot, as
> PSCI is missing.
> Building the 32-bit version of the SPL and combining this with an ATF
> build and the 64-bit U-Boot proper allows to use FEL booting now:
> # sunxi-fel spl sunxi-spl.bin write 0x4a00 u-boot-dtb.bin \
>   write 0x44000 bl31.bin reset64 0x44000
> This way of booting the board gives full functionality.
>
> The first patch is a rather simple fix (with no changes to v2).
> Patches 2-8 prepare the SPL code to be compiled for 64-bit in general and
> AArch64 in particular.
> Patches 9-11 refactor the existing boot0 header functionality to be used
> by patch 12, which introduces the 64-bit switch in the first SPL
> instructions.
> Patches 13-20 then introduce the actual core of the SPL support: the DRAM
> initialization, courtesy of Jens. This piggy backs on the existing
> H3 DRAM code, deviating where needed. This has been reworked compared to
> v2: I added a patch from Philipp to replace the rather uninspired
> register writes in the MBUS priority setup function with some meaningful
> code, explaining the various bits. Also the actual A64 DRAM code is no
> longer #ifdef'ed into the H3 driver, but uses parameters to (static)
> functions. The compiler detects this and removes the dead code from
> the other variant, resulting in the same binary size for the H3.
>
> Patch 21 finally enables the 64-bit SPL support. So now building the
> existing pine64_plus_defconfig will generate a sunxi-spl.bin, which
> can be prepended to the U-Boot proper image (not .bin) to boot from
> an SD card. Due to the missing ATF support this is of limited usability
> at the moment, though. Also FEL support requires more love - to switch
> back to AArch32 before returning to FEL (without crashing, that is ;-),
> so this is disabled.
> On my setup this results in a 26KB SPL binary, which is close to the
> 28K limit mksunxiboot imposes at the moment. Adding anything (like
> FIT support or DEBUG) will exceed this, and although I have patches
> to let mksunxiboot get close to 32KB, this is the ulimate frontier.
>
> So patches 22-25 then teach the SPL how to detect an U-Boot image file
> of a different bitness and do the RMR switch from AArch32 to AArch64,
> if needed.
> This is used by the final patch 26, which creates another _defconfig
> to let the SPL compile for AArch32 using the Thumb2 encoding. This
> results in a binary of less than 17KB in my case, so has plenty of
> room for extensions.
>
> Cheers,
> Andre.
>
> Changelog v3 .. v4:
> - rebased on top of latest HEAD
> - add various Reviewed-by: and Acked-by: tags
> - add comments about register bit meanings in non-ODT-setting fix
> - clarify meaning of delay values in single bit delay support patch
> - removing stray semicolons from boot0.h header
>
> Changelog v2 .. v3:
> - add various Reviewed-by: and Acked-by: tags
> - split tiny-printf fix to handle "-" separately

Re: [U-Boot] [GIT PULL] Please pull u-boot-mmc master

[Jaehoon Chung]

On 01/03/2017 10:17 AM, Jaehoon Chung wrote:
> Dear Tom,
> 
> Could you pull these patches on your master branch?
> There is a patch relevant to PMIC for PR.
> I considered to make the pmic branch, but just included this patch in this PR.
> (If you want to split the PR, I will do it.)
> If there is an issue, let me know, plz.

Sorry for late.

> 
> The following changes since commit 87f5f5417fc897df0b05826b408f0f4b7d2ee388:
> 
>   Prepare v2017.01-rc3 (2017-01-02 20:00:55 -0500)
> 
> are available in the git repository at:
> 
>   http://git.denx.de/u-boot-master master
> 
> for you to fetch changes up to 4c73d121d86f431221d48ae215f17887f06abff2:
> 
>   power: change from meaningless value to error number (2017-01-03 10:11:34 
> +0900)
> 
> 
> Jaehoon Chung (12):
>   mmc: sdhci: disable the 8bit mode when host doesn't support it
>   mmc: sdhci: add the get_cd callback function in sdhci_ops
>   mmc: sdhci: remove the unused code about testing Card detect
>   mmc: pic32_sdhci: move the code to pic32_sdhci.c
>   mmc: sdhci: remove the SDHCI_QUIRK_NO_CD
>   mmc: change the set_ios return type from void to int
>   mmc: s5p_sdhci: add the s5p_set_clock function
>   mmc: sdhci: move the callback function into sdhci_ops
>   mmc: sdhci: use the bitops APIs in sdhci.h
>   mmc: sdhci: remove the SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER
>   mmc: sdhci: combine the Host controller v3.0 feature into one condition
>   power: change from meaningless value to error number
> 
> Masahiro Yamada (2):
>   mmc: sdhci-cadence: add Cadence SD4HC support
>   mmc: uniphier-sd: fix Kconfig dependency
> 
>  drivers/mmc/Kconfig|  16 ++--
>  drivers/mmc/Makefile   |   1 +
>  drivers/mmc/dw_mmc.c   |   5 ++---
>  drivers/mmc/pic32_sdhci.c  |  15 ++-
>  drivers/mmc/s5p_sdhci.c|  15 ---
>  drivers/mmc/sdhci-cadence.c| 125 
> +
>  drivers/mmc/sdhci.c|  59 
> +--
>  drivers/power/axp152.c |   2 +-
>  drivers/power/axp209.c |   2 +-
>  drivers/power/battery/bat_trats2.c |   2 +-
>  drivers/power/exynos-tmu.c |   8 
>  drivers/power/fuel_gauge/fg_max17042.c |   4 ++--
>  drivers/power/mfd/fg_max77693.c|   4 ++--
>  drivers/power/mfd/pmic_max77693.c  |   8 
>  drivers/power/palmas.c |  11 +++
>  drivers/power/pmic/pmic_hi6553.c   |   4 ++--
>  drivers/power/pmic/pmic_max77686.c |  18 +-
>  drivers/power/pmic/pmic_max8997.c  |   8 
>  drivers/power/power_core.c |   8 
>  drivers/power/power_i2c.c  |  22 +++---
>  drivers/power/power_spi.c  |  18 ++
>  drivers/power/tps6586x.c   |  12 ++--
>  include/mmc.h  |   2 +-
>  include/sdhci.h| 131 
> +--
>  24 files changed, 315 insertions(+), 185 deletions(-)
>  create mode 100644 drivers/mmc/sdhci-cadence.c
> 
> Best Regards,
> Jaehoon Chung
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> 
> 

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[U-Boot] [GIT PULL] Please pull u-boot-mmc master

[Jaehoon Chung]

Dear Tom,

Could you pull these patches on your master branch?
There is a patch relevant to PMIC for PR.
I considered to make the pmic branch, but just included this patch in this PR.
(If you want to split the PR, I will do it.)
If there is an issue, let me know, plz.

The following changes since commit 87f5f5417fc897df0b05826b408f0f4b7d2ee388:

  Prepare v2017.01-rc3 (2017-01-02 20:00:55 -0500)

are available in the git repository at:

  http://git.denx.de/u-boot-master master

for you to fetch changes up to 4c73d121d86f431221d48ae215f17887f06abff2:

  power: change from meaningless value to error number (2017-01-03 10:11:34 
+0900)


Jaehoon Chung (12):
  mmc: sdhci: disable the 8bit mode when host doesn't support it
  mmc: sdhci: add the get_cd callback function in sdhci_ops
  mmc: sdhci: remove the unused code about testing Card detect
  mmc: pic32_sdhci: move the code to pic32_sdhci.c
  mmc: sdhci: remove the SDHCI_QUIRK_NO_CD
  mmc: change the set_ios return type from void to int
  mmc: s5p_sdhci: add the s5p_set_clock function
  mmc: sdhci: move the callback function into sdhci_ops
  mmc: sdhci: use the bitops APIs in sdhci.h
  mmc: sdhci: remove the SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER
  mmc: sdhci: combine the Host controller v3.0 feature into one condition
  power: change from meaningless value to error number

Masahiro Yamada (2):
  mmc: sdhci-cadence: add Cadence SD4HC support
  mmc: uniphier-sd: fix Kconfig dependency

 drivers/mmc/Kconfig|  16 ++--
 drivers/mmc/Makefile   |   1 +
 drivers/mmc/dw_mmc.c   |   5 ++---
 drivers/mmc/pic32_sdhci.c  |  15 ++-
 drivers/mmc/s5p_sdhci.c|  15 ---
 drivers/mmc/sdhci-cadence.c| 125 
+
 drivers/mmc/sdhci.c|  59 
+--
 drivers/power/axp152.c |   2 +-
 drivers/power/axp209.c |   2 +-
 drivers/power/battery/bat_trats2.c |   2 +-
 drivers/power/exynos-tmu.c |   8 
 drivers/power/fuel_gauge/fg_max17042.c |   4 ++--
 drivers/power/mfd/fg_max77693.c|   4 ++--
 drivers/power/mfd/pmic_max77693.c  |   8 
 drivers/power/palmas.c |  11 +++
 drivers/power/pmic/pmic_hi6553.c   |   4 ++--
 drivers/power/pmic/pmic_max77686.c |  18 +-
 drivers/power/pmic/pmic_max8997.c  |   8 
 drivers/power/power_core.c |   8 
 drivers/power/power_i2c.c  |  22 +++---
 drivers/power/power_spi.c  |  18 ++
 drivers/power/tps6586x.c   |  12 ++--
 include/mmc.h  |   2 +-
 include/sdhci.h| 131 
+--
 24 files changed, 315 insertions(+), 185 deletions(-)
 create mode 100644 drivers/mmc/sdhci-cadence.c

Best Regards,
Jaehoon Chung
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Re: [U-Boot] [PATCH] mmc: uniphier-sd: fix Kconfig dependency

[Jaehoon Chung]

On 12/30/2016 11:20 PM, Masahiro Yamada wrote:
> Some MMC drivers describe operations with the DM_MMC_OPS form, but
> there are still several drivers with older implementation.  We can
> not compile drivers from different groups at the same time because
> the core framework is shared with #ifdef CONFIG_DM_MMC_OPS.
> 
> Every driver should have "depends on DM_MMC_OPS" (or !DM_MMC_OPS)
> explicitly to express which framework it is based on.  This will
> avoid enabling drivers with incompatible interface at the same time.
> It is incorrect to make a driver "select DM_MMC_OPS".
> 
> While we are here, add "depends on OF_CONTROL" as well because this
> driver can be configured only by Device Tree.
> 
> Signed-off-by: Masahiro Yamada 

Applied on u-boot-mmc. Thanks!

Best Regards,
Jaehoon Chung

> ---
> 
>  drivers/mmc/Kconfig | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index ff4344f..75b6ba1 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -107,8 +107,8 @@ config ROCKCHIP_SDHCI
>  config MMC_UNIPHIER
>   bool "UniPhier SD/MMC Host Controller support"
>   depends on ARCH_UNIPHIER
> - depends on BLK
> - select DM_MMC_OPS
> + depends on BLK && DM_MMC_OPS
> + depends on OF_CONTROL
>   help
> This selects support for the SD/MMC Host Controller on UniPhier SoCs.
>  
> 

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Re: [U-Boot] [PATCH 00/11] mmc: clean the sdhci host controller

[Jaehoon Chung]

On 12/30/2016 03:30 PM, Jaehoon Chung wrote:
> It's cleaned the condes related to SDHCI host controller.
> Move the callback function into sdhci_ops structure.
> And removed the unnecessary things.
> 
> My next step should be more clearly than now.
> - Support DM feature than now.
> - Make driver model for controller that unused driver mode.
> 
> Jaehoon Chung (11):
>   mmc: sdhci: disable the 8bit mode when host doesn't support it
>   mmc: sdhci: add the get_cd callback function in sdhci_ops
>   mmc: sdhci: remove the unused code about testing Card detect
>   mmc: pic32_sdhci: move the code to pic32_sdhci.c
>   mmc: sdhci: remove the SDHCI_QUIRK_NO_CD
>   mmc: change the set_ios return type from void to int
>   mmc: s5p_sdhci: add the s5p_set_clock function
>   mmc: sdhci: move the callback function into sdhci_ops
>   mmc: sdhci: use the bitops APIs in sdhci.h
>   mmc: sdhci: remove the SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER
>   mmc: sdhci: combine the Host controller v3.0 feature into one
> condition
> 
>  drivers/mmc/dw_mmc.c  |   5 +-
>  drivers/mmc/pic32_sdhci.c |  15 +-
>  drivers/mmc/s5p_sdhci.c   |  15 --
>  drivers/mmc/sdhci.c   |  59 ++---
>  include/mmc.h |   2 +-
>  include/sdhci.h   | 131 
> +++---
>  6 files changed, 111 insertions(+), 116 deletions(-)

Applied on u-boot-mmc.

Thanks!

> 

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Re: [U-Boot] [PATCH v2] mmc: sdhci-cadence: add Cadence SD4HC support

[Jaehoon Chung]

On 12/30/2016 10:41 PM, Masahiro Yamada wrote:
> Add a driver for the Cadence SD4HC SD/SDIO/eMMC Controller.
> 
> Signed-off-by: Masahiro Yamada 

Applied on u-boot-mmc. Thanks!

Best Regards,
Jaehoon Chung

> ---
> 
> Changes in v2:
>   - Remove unneeded version setting
>   - Add SoC specific compatible "socionext,uniphier-sd4hc"
>   - Add "depends on BLK && DM_MMC_OPS && MMC_SDHCI"
> 
>  drivers/mmc/Kconfig |  12 +
>  drivers/mmc/Makefile|   1 +
>  drivers/mmc/sdhci-cadence.c | 125 
> 
>  3 files changed, 138 insertions(+)
>  create mode 100644 drivers/mmc/sdhci-cadence.c
> 
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index 2ba1254..ff4344f 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -159,6 +159,18 @@ config MMC_SDHCI_BCM2835
>  
> If unsure, say N.
>  
> +config MMC_SDHCI_CADENCE
> + bool "SDHCI support for the Cadence SD/SDIO/eMMC controller"
> + depends on BLK && DM_MMC_OPS
> + depends on MMC_SDHCI
> + depends on OF_CONTROL
> + help
> +   This selects the Cadence SD/SDIO/eMMC driver.
> +
> +   If you have a controller with this interface, say Y here.
> +
> +   If unsure, say N.
> +
>  config MMC_SDHCI_KONA
>   bool "SDHCI support on Broadcom KONA platform"
>   depends on MMC_SDHCI
> diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
> index 2b136ea..a543188 100644
> --- a/drivers/mmc/Makefile
> +++ b/drivers/mmc/Makefile
> @@ -64,6 +64,7 @@ obj-$(CONFIG_MSM_SDHCI) += msm_sdhci.o
>  # SDHCI
>  obj-$(CONFIG_MMC_SDHCI)  += sdhci.o
>  obj-$(CONFIG_MMC_SDHCI_BCM2835)  += bcm2835_sdhci.o
> +obj-$(CONFIG_MMC_SDHCI_CADENCE)  += sdhci-cadence.o
>  obj-$(CONFIG_MMC_SDHCI_KONA) += kona_sdhci.o
>  obj-$(CONFIG_MMC_SDHCI_MV)   += mv_sdhci.o
>  obj-$(CONFIG_MMC_SDHCI_S5P)  += s5p_sdhci.o
> diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c
> new file mode 100644
> index 000..2253bbc
> --- /dev/null
> +++ b/drivers/mmc/sdhci-cadence.c
> @@ -0,0 +1,125 @@
> +/*
> + * Copyright (C) 2016 Socionext Inc.
> + *   Author: Masahiro Yamada 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/* HRS - Host Register Set (specific to Cadence) */
> +#define SDHCI_CDNS_HRS04 0x10/* PHY access port */
> +#define   SDHCI_CDNS_HRS04_ACK   BIT(26)
> +#define   SDHCI_CDNS_HRS04_RDBIT(25)
> +#define   SDHCI_CDNS_HRS04_WRBIT(24)
> +#define   SDHCI_CDNS_HRS04_RDATA_SHIFT   12
> +#define   SDHCI_CDNS_HRS04_WDATA_SHIFT   8
> +#define   SDHCI_CDNS_HRS04_ADDR_SHIFT0
> +
> +/* SRS - Slot Register Set (SDHCI-compatible) */
> +#define SDHCI_CDNS_SRS_BASE  0x200
> +
> +/* PHY */
> +#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
> +#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT0x01
> +#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
> +#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
> +#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
> +#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
> +#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY   0x06
> +#define SDHCI_CDNS_PHY_DLY_EMMC_SDR  0x07
> +#define SDHCI_CDNS_PHY_DLY_EMMC_DDR  0x08
> +
> +struct sdhci_cdns_plat {
> + struct mmc_config cfg;
> + struct mmc mmc;
> + void __iomem *hrs_addr;
> +};
> +
> +static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat,
> +  u8 addr, u8 data)
> +{
> + void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04;
> + u32 tmp;
> +
> + tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) |
> +   (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT);
> + writel(tmp, reg);
> +
> + tmp |= SDHCI_CDNS_HRS04_WR;
> + writel(tmp, reg);
> +
> + tmp &= ~SDHCI_CDNS_HRS04_WR;
> + writel(tmp, reg);
> +}
> +
> +static void sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat)
> +{
> + sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_SD_HS, 4);
> + sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_SD_DEFAULT, 4);
> + sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_LEGACY, 9);
> + sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_SDR, 2);
> + sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_DDR, 3);
> +}
> +
> +static int sdhci_cdns_bind(struct udevice *dev)
> +{
> + struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
> +
> + return sdhci_bind(dev, >mmc, >cfg);
> +}
> +
> +static int sdhci_cdns_probe(struct udevice *dev)
> +{
> + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
> + struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
> + struct sdhci_host *host = dev_get_priv(dev);
> + fdt_addr_t base;
> + int ret;
> +
> + base = 

Re: [U-Boot] [U-Boot, v2] doc/README.cfi: Update code snippet, and add example.

[Tom Rini]

On Thu, Dec 29, 2016 at 05:23:19AM -0500, Robert P. J. Day wrote:

> First, update the code snippet referenced in the README file. And
> since there are only two boards that override flash_cmd_reset(),
> might as well show them both.
> 
> Signed-off-by: Robert P. J. Day 

Applied to u-boot/master, thanks!

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Re: [U-Boot] ARM: OMAP3_LOGIC: Remove ONENAND config options

[Tom Rini]

On Sat, Dec 31, 2016 at 05:51:27AM -0600, Adam Ford wrote:

> These boards do not and never have had ONENAND support, so let's remove it.
> 
> Signed-off-by: Adam Ford 

Applied to u-boot/master, thanks!

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[U-Boot] [ANN] U-Boot v2017.01-rc3 released

[Tom Rini]

Hey all,

It's release day and v2017.01-rc3 is out.  I'm pretty happy with the
state of my queue right now.  If there's anything really urgent
outstanding still, please speak up.  Otherwise I expect things to be
quiet in the tree until release, next Monday.

Thanks all!

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Re: [U-Boot] OMAP3: omap3_logic: Remove display parameter

[Tom Rini]

On Sat, Dec 31, 2016 at 06:33:46AM -0600, Adam Ford wrote:

> The display is done in the device tree now, and there is no need
> to pass 'display' kernel parameter any longer.
> 
> Signed-off-by: Adam Ford 
> 
> diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
> index d66b507..b38811e 100644

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v4, 1/4] arm: am57xx: cl-som-am57x: add initial board support

[Tom Rini]

On Wed, Dec 28, 2016 at 06:28:33PM +0200, Uri Mashiach wrote:

> From: Dmitry Lifshitz 
> 
> Features supported :
> 
> * Serial console
> * SPI Flash
> * MMC/SD Card
> * eMMC storage
> * SATA
> * PCA9555 - GPIO expander over I2C5 bus
> * USB
> 
> Use spl alternate boot device feature to define fallback to
> the main boot device as it is defined by hardware.
> 
> Signed-off-by: Dmitry Lifshitz 
> [uri.mashi...@compulab.co.il: Adjust to v2016.11]
> Signed-off-by: Uri Mashiach 
> Acked-by: Igor Grinberg 

Applied to u-boot/master, thanks!

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Re: [U-Boot] tools: binman: Use /usr/bin/env to find python executable

[Tom Rini]

On Tue, Dec 27, 2016 at 10:36:08PM +0100, Emmanuel Vadot wrote:

> Some OS (all BSD and probably others) do not have python in /usr/bin
> but in another directory.
> It is a common usage to use /usr/bin/env python as shebang for python
> scripts so use this for binman.
> 
> Signed-off-by: Emmanuel Vadot 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v4, 3/4] arm: am57xx: cl-som-am57x: add ETH support

[Tom Rini]

On Wed, Dec 28, 2016 at 06:28:35PM +0200, Uri Mashiach wrote:

> From: Dmitry Lifshitz 
> 
> Add MAC support.
> 
> Use PHY, connected to RGMII1 as a default Eth adapter,
> by appropriate setting of 'cpsw_data.active_slave'.
> 
> 'cpsw_phy' env variable can override this setting.
> 
> Set the MAC addresses in the U-Boot environment.
> The addresses are retrieved from the on-board EEPROM or from the SOC's
> MAC fuses.
> 
> Set the following PHYs RGMII clock delays:
> - Enable RX delay
> - Disable TX delay
> 
> Signed-off-by: Dmitry Lifshitz 
> [uri.mashi...@compulab.co.il: add RGMII clock delays]
> Signed-off-by: Uri Mashiach 
> Acked-by: Igor Grinberg 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v4, 4/4] arm: am57xx: cl-som-am57x: update default env

[Tom Rini]

On Wed, Dec 28, 2016 at 06:28:36PM +0200, Uri Mashiach wrote:

> Modify U-Boot default env settings.
> 
> Boot sequence:
> 1. SD card boot script
> 2. SD card boot no script
> 3. SATA boot script
> 4. SATA boot no script
> 5. eMMC boot script
> 6. eMMC boot no script
> 
> Signed-off-by: Uri Mashiach 
> Acked-by: Igor Grinberg 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] digsy_mtc.c: Minor spelling/grammar fixes.

[Tom Rini]

On Thu, Dec 29, 2016 at 05:06:41AM -0500, Robert P. J. Day wrote:

> Signed-off-by: Robert P. J. Day 
> 
> diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c 
> b/board/intercontrol/digsy_mtc/digsy_mtc.c
> index 37eb6c7..05d673d 100644

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, v4, 2/4] arm: am57xx: cl-som-am57x: fetch board rev from EEPROM

[Tom Rini]

On Wed, Dec 28, 2016 at 06:28:34PM +0200, Uri Mashiach wrote:

> From: Dmitry Lifshitz 
> 
> Add PCB revision message.
> Implement board revision get_board_rev API.
> 
> Signed-off-by: Dmitry Lifshitz 
> Commit description update.
> Signed-off-by: Uri Mashiach 
> Acked-by: Igor Grinberg 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PULL] Please pull u-boot-imx

[Tom Rini]

On Mon, Jan 02, 2017 at 06:08:01PM +0100, Stefano Babic wrote:

> Hi Tom,
> 
> please pull from u-boot-imx, thanks !
> 
> The following changes since commit 3d3a74cc8c774345be7d1661b21ad41f4515:
> 
>   mmc: move MMC_SDHCI_IO_ACCESSORS to Kconfig (2016-12-29 13:08:17 -0500)
> 
> are available in the git repository at:
> 
>   git://www.denx.de/git/u-boot-imx.git master
> 
> for you to fetch changes up to 7c4f0ff81e6fc3b58b8af5f64c3da98624e40132:
> 
>   udoo: neo: Fix indentation (2017-01-02 17:55:58 +0100)
> 

Applied to u-boot/master, thanks!

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[U-Boot] [PATCH v2] arm: samsung: goni: use the driver model for max8998

[Jaehoon Chung]

Remove the "ifndef CONFIG_DM_I2C".
Instead, use the driver model for max8998.

Signed-off-by: Jaehoon Chung 
---
Changelog on V2:
- Removes the CONFIG_DM_PMIC_MAX8998
- Fixes the typo s/max8998_pmix/max8998_pmic

 board/samsung/goni/goni.c | 61 +++
 1 file changed, 30 insertions(+), 31 deletions(-)

diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
index b066832..80fd0d4 100644
--- a/board/samsung/goni/goni.c
+++ b/board/samsung/goni/goni.c
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -43,19 +44,6 @@ void i2c_init_board(void)
 }
 #endif
 
-int power_init_board(void)
-{
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
-   /*
-* For PMIC the I2C bus is named as I2C5, but it is connected
-* to logical I2C adapter 0
-*/
-   return pmic_init(I2C_0);
-#else
-   return 0;
-#endif
-}
-
 int dram_init(void)
 {
gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE +
@@ -146,39 +134,50 @@ int board_mmc_init(bd_t *bis)
 #ifdef CONFIG_USB_GADGET
 static int s5pc1xx_phy_control(int on)
 {
-#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
-   int ret;
+   struct udevice *dev;
static int status;
-   struct pmic *p = pmic_get("MAX8998_PMIC");
-   if (!p)
-   return -ENODEV;
+   int reg, ret;
 
-   if (pmic_probe(p))
-   return -1;
+   ret = pmic_get("max8998_pmic", );
+   if (ret)
+   return ret;
 
if (on && !status) {
-   ret = pmic_set_output(p, MAX8998_REG_ONOFF1,
- MAX8998_LDO3, LDO_ON);
-   ret = pmic_set_output(p, MAX8998_REG_ONOFF2,
- MAX8998_LDO8, LDO_ON);
+   reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
+   reg |= MAX8998_LDO3;
+   ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
if (ret) {
puts("MAX8998 LDO setting error!\n");
-   return -1;
+   return -EINVAL;
+   }
+
+   reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
+   reg |= MAX8998_LDO8;
+   ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
+   if (ret) {
+   puts("MAX8998 LDO setting error!\n");
+   return -EINVAL;
}
status = 1;
} else if (!on && status) {
-   ret = pmic_set_output(p, MAX8998_REG_ONOFF1,
- MAX8998_LDO3, LDO_OFF);
-   ret = pmic_set_output(p, MAX8998_REG_ONOFF2,
- MAX8998_LDO8, LDO_OFF);
+   reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
+   reg &= ~MAX8998_LDO3;
+   ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
+   if (ret) {
+   puts("MAX8998 LDO setting error!\n");
+   return -EINVAL;
+   }
+
+   reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
+   reg &= ~MAX8998_LDO8;
+   ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
if (ret) {
puts("MAX8998 LDO setting error!\n");
-   return -1;
+   return -EINVAL;
}
status = 0;
}
udelay(1);
-#endif
return 0;
 }
 
-- 
2.10.2

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[U-Boot] [PATCH v2] mtd: nand: mxs_nand_spl: Fix to remove twise 'NAND' print

[Jagan Teki]

SPL from nand will print 'NAND' in boot_from_devices based on
the image_loader name, remove the extra 'NAND ' in mxs_nand_spl driver.

Original behaviour:
---
U-Boot SPL 2017.01-rc2-gf84dd8b (Jan 02 2017 - 22:24:19)
Trying to boot from NANDNAND : 512 MiB

After the fix:
-
U-Boot SPL 2017.01-rc2-gf84dd8b-dirty (Jan 02 2017 - 23:17:00)
Trying to boot from NAND: 512 MiB

Cc: Tom Rini 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- Fix commit message about fix logs

 drivers/mtd/nand/mxs_nand_spl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c
index ff28df4..b6c9208 100644
--- a/drivers/mtd/nand/mxs_nand_spl.c
+++ b/drivers/mtd/nand/mxs_nand_spl.c
@@ -153,7 +153,7 @@ static int mxs_nand_init(void)
nand_chip.numchips = 1;
 
/* identify flash device */
-   puts("NAND : ");
+   puts(": ");
if (mxs_flash_ident(mtd)) {
printf("Failed to identify\n");
return -1;
-- 
1.9.1

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[U-Boot] [PATCH 2/2] spi: Zap cf_qspi driver and related code

[Jagan Teki]

Dropped becuase
- driver not used any board.
- no dm conversion.

Cc: Angelo Dureghello 
Cc: Richard Retanubun 
Signed-off-by: Jagan Teki 
---
 arch/m68k/cpu/mcf52x2/cpu_init.c |  12 --
 drivers/spi/Makefile |   1 -
 drivers/spi/cf_qspi.c| 354 ---
 drivers/spi/cf_spi.c |   4 -
 scripts/config_whitelist.txt |   1 -
 5 files changed, 372 deletions(-)
 delete mode 100644 drivers/spi/cf_qspi.c

diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c
index edcb092..7b66720 100644
--- a/arch/m68k/cpu/mcf52x2/cpu_init.c
+++ b/arch/m68k/cpu/mcf52x2/cpu_init.c
@@ -318,18 +318,6 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 }
 #endif /* CONFIG_CMD_NET */
 
-#if defined(CONFIG_CF_QSPI)
-
-/* Configure PIOs for SIN, SOUT, and SCK */
-void cfspi_port_conf(void)
-{
-   mbar_writeByte(MCF_GPIO_PAR_QSPI,
-  MCF_GPIO_PAR_QSPI_SIN_SIN   |
-  MCF_GPIO_PAR_QSPI_SOUT_SOUT |
-  MCF_GPIO_PAR_QSPI_SCK_SCK);
-}
-#endif /* CONFIG_CF_QSPI */
-
 #endif /* CONFIG_M5271 */
 
 #if defined(CONFIG_M5272)
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 521911b..896b093 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
 obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
 obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
 obj-$(CONFIG_CF_SPI) += cf_spi.o
-obj-$(CONFIG_CF_QSPI) += cf_qspi.o
 obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
 obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
 obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
diff --git a/drivers/spi/cf_qspi.c b/drivers/spi/cf_qspi.c
deleted file mode 100644
index e57e63e..000
--- a/drivers/spi/cf_qspi.c
+++ /dev/null
@@ -1,354 +0,0 @@
-/*
- * Freescale Coldfire Queued SPI driver
- *
- * NOTE:
- * This driver is written to transfer 8 bit at-a-time and uses the dedicated
- * SPI slave select pins as bit-banged GPIO to work with spi_flash subsystem.
- *
- * Copyright (C) 2011 Ruggedcom, Inc.
- * Richard Retanubun (richardretanu...@freescale.com)
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define to_cf_qspi_slave(s) container_of(s, struct cf_qspi_slave, slave)
-
-struct cf_qspi_slave {
-   struct spi_slave slave; /* Specific bus:cs ID for each device */
-   qspi_t *regs;   /* Pointer to SPI controller registers */
-   u16 qmr;/* QMR: Queued Mode Register */
-   u16 qwr;/* QWR: Queued Wrap Register */
-   u16 qcr;/* QCR: Queued Command Ram */
-};
-
-/* Register write wrapper functions */
-static void write_qmr(volatile qspi_t *qspi, u16 val)   { qspi->mr = val; }
-static void write_qdlyr(volatile qspi_t *qspi, u16 val) { qspi->dlyr = val; }
-static void write_qwr(volatile qspi_t *qspi, u16 val)   { qspi->wr = val; }
-static void write_qir(volatile qspi_t *qspi, u16 val)   { qspi->ir = val; }
-static void write_qar(volatile qspi_t *qspi, u16 val)   { qspi->ar = val; }
-static void write_qdr(volatile qspi_t *qspi, u16 val)   { qspi->dr = val; }
-/* Register read wrapper functions */
-static u16 read_qdlyr(volatile qspi_t *qspi) { return qspi->dlyr; }
-static u16 read_qwr(volatile qspi_t *qspi)   { return qspi->wr; }
-static u16 read_qir(volatile qspi_t *qspi)   { return qspi->ir; }
-static u16 read_qdr(volatile qspi_t *qspi)   { return qspi->dr; }
-
-/* These call points may be different for each ColdFire CPU */
-extern void cfspi_port_conf(void);
-static void cfspi_cs_activate(uint bus, uint cs, uint cs_active_high);
-static void cfspi_cs_deactivate(uint bus, uint cs, uint cs_active_high);
-
-int spi_claim_bus(struct spi_slave *slave)
-{
-   return 0;
-}
-void spi_release_bus(struct spi_slave *slave)
-{
-}
-
-__attribute__((weak))
-void spi_init(void)
-{
-   cfspi_port_conf();
-}
-
-__attribute__((weak))
-void spi_cs_activate(struct spi_slave *slave)
-{
-   struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
-
-   cfspi_cs_activate(slave->bus, slave->cs, !(dev->qwr & QSPI_QWR_CSIV));
-}
-
-__attribute__((weak))
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-   struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
-
-   cfspi_cs_deactivate(slave->bus, slave->cs, !(dev->qwr & QSPI_QWR_CSIV));
-}
-
-__attribute__((weak))
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-   /* Only 1 bus and 4 chipselect per controller */
-   if (bus == 0 && (cs >= 0 && cs < 4))
-   return 1;
-   else
-   return 0;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-   struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
-
-   free(dev);
-}
-
-/* Translate 

[U-Boot] [PATCH 1/2] spi: Zap ep93xx_spi driver and related code

[Jagan Teki]

Dropped becuase
- driver and related configs not used any board.
- no dm conversion.

Cc: Heiko Schocher 
Cc: Sergey Kostanbaev 
Signed-off-by: Jagan Teki 
---
 board/cirrus/edb93xx/edb93xx.c |  98 ---
 drivers/spi/Makefile   |   1 -
 drivers/spi/ep93xx_spi.c   | 272 -
 include/configs/edb93xx.h  |  10 --
 scripts/config_whitelist.txt   |   4 -
 5 files changed, 385 deletions(-)
 delete mode 100644 drivers/spi/ep93xx_spi.c

diff --git a/board/cirrus/edb93xx/edb93xx.c b/board/cirrus/edb93xx/edb93xx.c
index 8963d3a..51ff162 100644
--- a/board/cirrus/edb93xx/edb93xx.c
+++ b/board/cirrus/edb93xx/edb93xx.c
@@ -282,101 +282,3 @@ int dram_init(void)
gd->ram_size = dram_init_banksize_int(1);
return 0;
 }
-
-
-#ifdef CONFIG_EP93XX_SPI
-#include 
-
-/*
- * EGIO0-EGIPO7 -> port A
- * EGIO8-EGIP15 -> port B
- */
-
-static void ep93xx_set_epgio(unsigned num)
-{
-   struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
-   if (num < 8)
-   writel(readl(>padr) | (1<padr);
-   else
-   writel(readl(>pbdr) | (1<<(num-8)), >pbdr);
-}
-
-static void ep93xx_clear_epgio(unsigned num)
-{
-   struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
-   if (num < 8)
-   writel(readl(>padr) & (~(1<padr);
-   else
-   writel(readl(>pbdr) & (~(1<<(num-8))), >pbdr);
-}
-
-static void ep93xx_dir_epgio_out(unsigned num)
-{
-   struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
-   if (num < 8)
-   writel(readl(>paddr) | (1<paddr);
-   else
-   writel(readl(>pbddr) | (1<<(num-8)), >pbddr);
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-   if (bus == 0 && cs < 16)
-   return 1;
-
-   return 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-   ep93xx_clear_epgio(slave->cs);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-   ep93xx_set_epgio(slave->cs);
-}
-
-#ifdef CONFIG_MMC_SPI
-#include 
-
-#ifndef CONFIG_MMC_SPI_CS_EPGIO
-# define CONFIG_MMC_SPI_CS_EPGIO   4
-#endif
-
-#ifndef CONFIG_MMC_SPI_SPEED
-# define CONFIG_MMC_SPI_SPEED  2500
-#endif
-
-#ifndef CONFIG_MMC_SPI_MODE
-# define CONFIG_MMC_SPI_MODE   SPI_MODE_0
-#endif
-
-int board_mmc_init(bd_t *bis)
-{
-   struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
-
-   ep93xx_set_epgio(CONFIG_MMC_SPI_CS_EPGIO);
-   ep93xx_dir_epgio_out(CONFIG_MMC_SPI_CS_EPGIO);
-
-#ifdef CONFIG_MMC_SPI_POWER_EGPIO
-   ep93xx_dir_epgio_out(CONFIG_MMC_SPI_POWER_EGPIO);
-   ep93xx_set_epgio(CONFIG_MMC_SPI_POWER_EGPIO);
-#elif defined(CONFIG_MMC_SPI_NPOWER_EGPIO)
-   ep93xx_dir_epgio_out(CONFIG_MMC_SPI_NPOWER_EGPIO);
-   ep93xx_clear_epgio(CONFIG_MMC_SPI_NPOWER_EGPIO);
-#endif
-   struct mmc *mmc = mmc_spi_init(0, CONFIG_MMC_SPI_CS_EPGIO,
-   CONFIG_MMC_SPI_SPEED, CONFIG_MMC_SPI_MODE);
-
-   if (!mmc) {
-   printf("Failed to create MMC Device\n");
-   return 1;
-   }
-   mmc_init(mmc);
-   return 0;
-}
-
-
-#endif /* CONFIG_MMC_SPI */
-#endif /* CONFIG_EP93XX_SPI */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index c1ce158..521911b 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_CF_SPI) += cf_spi.o
 obj-$(CONFIG_CF_QSPI) += cf_qspi.o
 obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
 obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
-obj-$(CONFIG_EP93XX_SPI) += ep93xx_spi.o
 obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
 obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
 obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
diff --git a/drivers/spi/ep93xx_spi.c b/drivers/spi/ep93xx_spi.c
deleted file mode 100644
index cb682dd..000
--- a/drivers/spi/ep93xx_spi.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * SPI Driver for EP93xx
- *
- * Copyright (C) 2013 Sergey Kostanabev  fairwaves.ru>
- *
- * Inspired form linux kernel driver and atmel uboot driver
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-
-#include 
-
-#include 
-
-#define SSPBASESPI_BASE
-
-#define SSPCR0 0x
-#define SSPCR0_MODE_SHIFT  6
-#define SSPCR0_SCR_SHIFT   8
-#define SSPCR0_SPH BIT(7)
-#define SSPCR0_SPO BIT(6)
-#define SSPCR0_FRF_SPI 0
-#define SSPCR0_DSS_8BIT7
-
-#define SSPCR1 0x0004
-#define SSPCR1_RIE BIT(0)
-#define SSPCR1_TIE BIT(1)
-#define SSPCR1_RORIE   BIT(2)
-#define SSPCR1_LBM BIT(3)
-#define SSPCR1_SSE BIT(4)
-#define SSPCR1_MS  BIT(5)
-#define SSPCR1_SOD BIT(6)
-
-#define SSPDR  0x0008
-
-#define SSPSR  0x000c
-#define SSPSR_TFE  BIT(0)
-#define SSPSR_TNF

[U-Boot] [PATCH] mtd: nand: mxs_nand_spl: Fix to remove twise 'NAND' print

[Jagan Teki]

SPL from nand will print 'NAND' in boot_from_devices based on
the image_loader name, remove the extra 'NAND ' in mxs_nand_spl driver.

After the fix:
-
U-Boot SPL 2017.01-rc2-gf84dd8b (Jan 02 2017 - 22:24:19)
Trying to boot from NANDNAND : 512 MiB

Original behaviour:
---
U-Boot SPL 2017.01-rc2-gf84dd8b-dirty (Jan 02 2017 - 23:17:00)
Trying to boot from NAND: 512 MiB

Cc: Tom Rini 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/nand/mxs_nand_spl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c
index ff28df4..b6c9208 100644
--- a/drivers/mtd/nand/mxs_nand_spl.c
+++ b/drivers/mtd/nand/mxs_nand_spl.c
@@ -153,7 +153,7 @@ static int mxs_nand_init(void)
nand_chip.numchips = 1;
 
/* identify flash device */
-   puts("NAND : ");
+   puts(": ");
if (mxs_flash_ident(mtd)) {
printf("Failed to identify\n");
return -1;
-- 
1.9.1

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[U-Boot] [RESEND PATCH] tools: imximage: refactor header length calculations for imximage v1

[Martin Kaiser]

From: Martin Kaiser 

We can use the same header length calculations for both imximage v1 and
v2. This addresses TODO comments about imximage v1 in the current code.

With this patch applied, *header_size_ptr in imximage_set_header() will
have the correct value for both imximage v1 and v2. This is necessary
for people wanting to add proprietary data behind the created imximage.

Signed-off-by: Martin Kaiser 
Cc: sba...@denx.de
---

I discovered the problem when I tried to use csf_ptr with imximage v1
(as part of a private modification).

*csf_ptr = params->ep + *header_size_ptr - imximage_init_loadsize;
 = params->ep + sbuf->st_size +
 imximage_ivt_offset - imximage_init_loadsize;
 = params->ep + padded data file size + alloc_len -
 (imximage_init_loadsize - imximage_ivt_offset);

This works only if
alloc_len == imximage_init_loadsize - imximage_ivt_offset,
not if alloc_len is always 4096.

I rebased my tree to make sure that the patch still applies against
current master. I'd really appreciate any feedback, this has been
pending since September.

 tools/imximage.c |   38 --
 1 file changed, 16 insertions(+), 22 deletions(-)

diff --git a/tools/imximage.c b/tools/imximage.c
index 2cd8d88..0c43196 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -300,8 +300,7 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, 
uint32_t dcd_len,
/* Set magic number */
fhdr_v1->app_code_barker = APP_CODE_BARKER;
 
-   /* TODO: check i.MX image V1 handling, for now use 'old' style */
-   hdr_base = entry_point - 4096;
+   hdr_base = entry_point - imximage_init_loadsize + flash_offset;
fhdr_v1->app_dest_ptr = hdr_base - flash_offset;
fhdr_v1->app_code_jump_vector = entry_point;
 
@@ -833,18 +832,19 @@ static void imximage_set_header(void *ptr, struct stat 
*sbuf, int ifd,
/* Parse dcd configuration file */
dcd_len = parse_cfg_file(imxhdr, params->imagename);
 
-   if (imximage_version == IMXIMAGE_V2) {
+   if (imximage_version == IMXIMAGE_V1)
+   header_size = sizeof(flash_header_v1_t);
+   else {
header_size = sizeof(flash_header_v2_t) + sizeof(boot_data_t);
if (!plugin_image)
header_size += sizeof(dcd_v2_t);
else
header_size += MAX_PLUGIN_CODE_SIZE;
-
-   if (imximage_init_loadsize < imximage_ivt_offset + header_size)
-   imximage_init_loadsize = imximage_ivt_offset +
-   header_size;
}
 
+   if (imximage_init_loadsize < imximage_ivt_offset + header_size)
+   imximage_init_loadsize = imximage_ivt_offset + 
header_size;
+
/* Set the imx header */
(*set_imx_hdr)(imxhdr, dcd_len, params->ep, imximage_ivt_offset);
 
@@ -913,23 +913,21 @@ static int imximage_generate(struct image_tool_params 
*params,
/* Parse dcd configuration file */
parse_cfg_file(_header, params->imagename);
 
-   /* TODO: check i.MX image V1 handling, for now use 'old' style */
-   if (imximage_version == IMXIMAGE_V1) {
-   alloc_len = 4096;
-   header_size = 4096;
-   } else {
+   if (imximage_version == IMXIMAGE_V1)
+   header_size = sizeof(imx_header_v1_t);
+   else {
header_size = sizeof(flash_header_v2_t) + sizeof(boot_data_t);
if (!plugin_image)
header_size += sizeof(dcd_v2_t);
else
header_size += MAX_PLUGIN_CODE_SIZE;
-
-   if (imximage_init_loadsize < imximage_ivt_offset + header_size)
-   imximage_init_loadsize = imximage_ivt_offset +
-   header_size;
-   alloc_len = imximage_init_loadsize - imximage_ivt_offset;
}
 
+   if (imximage_init_loadsize < imximage_ivt_offset + header_size)
+   imximage_init_loadsize = imximage_ivt_offset + 
header_size;
+
+   alloc_len = imximage_init_loadsize - imximage_ivt_offset;
+
if (alloc_len < header_size) {
fprintf(stderr, "%s: header error\n",
params->cmdname);
@@ -959,11 +957,7 @@ static int imximage_generate(struct image_tool_params 
*params,
 
pad_len = ROUND(sbuf.st_size, 4096) - sbuf.st_size;
 
-   /* TODO: check i.MX image V1 handling, for now use 'old' style */
-   if (imximage_version == IMXIMAGE_V1)
-   return 0;
-   else
-   return pad_len;
+   return pad_len;
 }
 
 
-- 
1.7.10.4

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[U-Boot] question about boot timing -- should it all depend on BOOTSTAGE?

[Robert P. J. Day]

  looking at another Kconfig file -- common/Kconfig -- and i find it
curious that there are a couple BOOTSTAGE config options that don't
depend on BOOTSTAGE:

config BOOTSTAGE_USER_COUNT
hex "Number of boot ID numbers available for user use"
default 20
help
  This is the number of available user bootstage records.
  Each time you call bootstage_mark(BOOTSTAGE_ID_ALLOC, ...)
  a new ID will be allocated from this stash. If you exceed
  the limit, recording will stop.

... snip ...

config BOOTSTAGE_STASH_ADDR
hex "Address to stash boot timing information"
default 0
help
  Provide an address which will not be overwritten by the OS when it
  starts, so that it can read this information when ready.

config BOOTSTAGE_STASH_SIZE
hex "Size of boot timing stash region"
default 4096
help
  This should be large enough to hold the bootstage stash. A value of
  4096 (4KiB) is normally plenty.

endmenu

  do those Kbuild options really not need BOOTSTAGE to be selected
first?

rday

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http://crashcourse.ca

Twitter:   http://twitter.com/rpjday
LinkedIn:   http://ca.linkedin.com/in/rpjday


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[U-Boot] [PATCH] Kconfig: Refactoring of top-level Kconfig file

[Robert P. J. Day]

Some refactoring of the top-level Kconfig file which includes:

* using "if" to remove numerous identical dependency tests
* reordering config entries to group related ones
* spelling and grammar fixes

There should be no functional changes, only aesthetic ones.

Signed-off-by: Robert P. J. Day 

---
  AFAICT, there should be no functional difference, but i'm willing to
be corrected.

diff --git a/Kconfig b/Kconfig
index a44ac91..93c0ec7 100644
--- a/Kconfig
+++ b/Kconfig
@@ -126,7 +126,7 @@ config TOOLS_DEBUG
  it is possible to set breakpoints on particular lines, single-step
  debug through the source code, etc.

-endif
+endif # EXPERT

 config PHYS_64BIT
bool "64bit physical address support"
@@ -142,35 +142,26 @@ menu "Boot images"
 config FIT
bool "Support Flattened Image Tree"
help
- This option allows to boot the new uImage structrure,
+ This option allows you to boot the new uImage structure,
  Flattened Image Tree.  FIT is formally a FDT, which can include
  images of various types (kernel, FDT blob, ramdisk, etc.)
  in a single blob.  To boot this new uImage structure,
  pass the address of the blob to the "bootm" command.
  FIT is very flexible, supporting compression, multiple images,
  multiple configurations, verification through hashing and also
- verified boot (secure boot using RSA). This option enables that
- feature.
+ verified boot (secure boot using RSA).

-config SPL_FIT
-   bool "Support Flattened Image Tree within SPL"
-   depends on FIT
-   depends on SPL
-
-config FIT_VERBOSE
-   bool "Display verbose messages on FIT boot"
-   depends on FIT
+if FIT

 config FIT_SIGNATURE
bool "Enable signature verification of FIT uImages"
-   depends on FIT
depends on DM
select RSA
help
  This option enables signature verification of FIT uImages,
  using a hash signed and verified using RSA. If
  CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
- hashing is available using hardware, then then RSA library will use
+ hashing is available using hardware, then the RSA library will use
  it. See doc/uImage.FIT/signature.txt for more details.

  WARNING: When relying on signed FIT images with a required signature
@@ -179,15 +170,16 @@ config FIT_SIGNATURE
  format support in this case, enable it using
  CONFIG_IMAGE_FORMAT_LEGACY.

-config SPL_FIT_SIGNATURE
-   bool "Enable signature verification of FIT firmware within SPL"
-   depends on SPL_FIT
-   depends on SPL_DM
-   select SPL_RSA
+config FIT_VERBOSE
+   bool "Show verbose messages when FIT images fail"
+   help
+ Generally a system will have valid FIT images so debug messages
+ are a waste of code space. If you are debugging your images then
+ you can enable this option to get more verbose information about
+ failures.

 config FIT_BEST_MATCH
bool "Select the best match for the kernel device tree"
-   depends on FIT
help
  When no configuration is explicitly selected, default to the
  one whose fdt's compatibility field best matches that of
@@ -195,14 +187,55 @@ config FIT_BEST_MATCH
  most specific compatibility entry of U-Boot's fdt's root node.
  The order of entries in the configuration's fdt is ignored.

-config FIT_VERBOSE
-   bool "Show verbose messages when FIT images fails"
-   depends on FIT
+config FIT_IMAGE_POST_PROCESS
+   bool "Enable post-processing of FIT artifacts after loading by U-Boot"
+   depends on TI_SECURE_DEVICE
help
- Generally a system will have valid FIT images so debug messages
- are a waste of code space. If you are debugging your images then
- you can enable this option to get more verbose information about
- failures.
+ Allows doing any sort of manipulation to blobs after they got 
extracted
+ from FIT images like stripping off headers or modifying the size of 
the
+ blob, verification, authentication, decryption etc. in a platform or
+ board specific way. In order to use this feature a platform or board-
+ specific implementation of board_fit_image_post_process() must be
+ provided. Also, anything done during this post-processing step would
+ need to be comprehended in how the images were prepared before being
+ injected into the FIT creation (i.e. the blobs would have been pre-
+ processed before being added to the FIT image).
+
+config SPL_FIT
+   bool "Support Flattened Image Tree within SPL"
+   depends on SPL
+
+config SPL_FIT_SIGNATURE
+   bool "Enable signature verification of FIT firmware within SPL"
+   depends on SPL_FIT
+   depends on SPL_DM
+   select 

Re: [U-Boot] example: api: ARM example needs memset

[Tom Rini]

On Sat, Dec 31, 2016 at 07:05:50PM +0100, Emmanuel Vadot wrote:

> Add memset.S to the needed object for the API example and do not
> hardcode powerpc as the arch for library assembly files.
> 
> Signed-off-by: Emmanuel Vadot 

This patch isn't quite correct.  Not all cases of ARM will have the
optimized memset available to them (currently), so we can't apply this
today.  I'm going to re-examine this post release when I'm going to have
optimized memset/memcpy more widely available on ARM, thanks!

-- 
Tom


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[U-Boot] why two "config FIT_VERBOSE" lines in top-level Kconfig?

[Robert P. J. Day]

  weird ...

  config FIT_VERBOSE
bool "Display verbose messages on FIT boot"
depends on FIT

  ... jump to a bit lower down ...

  config FIT_VERBOSE
bool "Show verbose messages when FIT images fails"
depends on FIT
help
  Generally a system will have valid FIT images so debug messages
  are a waste of code space. If you are debugging your images then
  you can enable this option to get more verbose information about
  failures.

this is really a lead-in to a larger question -- any objection to
refactoring some of the Kconfig files that have numerous identical
dependency lines which could be replaced by a simpler "if" test?

  that top-level Kconfig file is a candidate, given the number of
"depends on FIT" lines that could be removed and surrounded by:

  if FIT
  ...
  endif

and some Kconfig files have entries in a weird order such that, if you
select a feature, dependent features suddenly pop up somewhere else in
the display, a bit disconcerting.

  anyway, i'll post a refactored top-level Kconfig, so people can see
what i'm talking about.

rday

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Re: [U-Boot] [PATCH 1/4] i2c: i2c-cdns: Detect unsupported sequences for rev 1.0

[Moritz Fischer]

Hi Michal,

On Mon, Jan 2, 2017 at 6:29 AM, Michal Simek  wrote:
> +Siva: please test it.
>
> On 27.12.2016 23:46, Moritz Fischer wrote:
>> Revision 1.0 of this IP has a couple of issues, such as not supporting
>> repeated start conditions for read transfers.
>>
>> So scan through the list of i2c messages for these conditions
>> and report an error if they are attempted.
>>
>> This has been fixed for revision 1.4 of the IP, so only report the error
>> when the IP can really not do it.
>>
>> Signed-off-by: Moritz Fischer 
>> Cc: Heiko Schocher 
>> Cc: Michal Simek 
>> Cc: u-boot@lists.denx.de
>> ---
>>  drivers/i2c/i2c-cdns.c | 69 
>> --
>>  1 file changed, 55 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
>> index f49f60b..c69e7e8 100644
>> --- a/drivers/i2c/i2c-cdns.c
>> +++ b/drivers/i2c/i2c-cdns.c
>> @@ -67,6 +67,7 @@ struct cdns_i2c_regs {
>>
>>  #define CDNS_I2C_FIFO_DEPTH  16
>>  #define CDNS_I2C_TRANSFER_SIZE_MAX   255 /* Controller transfer limit */
>> +#define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
>>
>>  #ifdef DEBUG
>>  static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
>> @@ -114,6 +115,13 @@ struct i2c_cdns_bus {
>>   int id;
>>   unsigned int input_freq;
>>   struct cdns_i2c_regs __iomem *regs; /* register base */
>> +
>
> no reason.
>
>> + int hold_flag;
>> + u32 quirks;
>> +};
>> +
>> +struct cdns_i2c_platform_data {
>> + u32 quirks;
>>  };
>>
>>  /* Wait for an interrupt */
>> @@ -236,18 +244,14 @@ static int cdns_i2c_probe_chip(struct udevice *bus, 
>> uint chip_addr,
>>  }
>>
>>  static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 
>> *data,
>> -u32 len, bool next_is_read)
>> +u32 len)
>>  {
>>   u8 *cur_data = data;
>>
>>   struct cdns_i2c_regs *regs = i2c_bus->regs;
>>
>> - setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
>> - CDNS_I2C_CONTROL_HOLD);
>> + setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO);
>>
>> - /* if next is a read, we need to clear HOLD, doesn't work */
>> - if (next_is_read)
>> - clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
>>
>
> two blank line after removing this code.

Whoops...
>
>>   clrbits_le32(>control, CDNS_I2C_CONTROL_RW);
>>
>> @@ -267,7 +271,9 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus 
>> *i2c_bus, u32 addr, u8 *data,
>>   }
>>
>>   /* All done... release the bus */
>> - clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
>> + if (!i2c_bus->hold_flag)
>> + clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
>> +
>>   /* Wait for the address and data to be sent */
>>   if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
>>   return -ETIMEDOUT;
>> @@ -285,7 +291,7 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus 
>> *i2c_bus, u32 addr, u8 *data,
>>   struct cdns_i2c_regs *regs = i2c_bus->regs;
>>
>>   /* Check the hardware can handle the requested bytes */
>> - if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX))
>> + if ((len < 0))
>>   return -EINVAL;
>>
>>   setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
>> @@ -310,7 +316,8 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus 
>> *i2c_bus, u32 addr, u8 *data,
>>   *(cur_data++) = readl(>data);
>>   } while (readl(>transfer_size) != 0);
>>   /* All done... release the bus */
>> - clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
>> + if (!i2c_bus->hold_flag)
>> + clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
>>
>>  #ifdef DEBUG
>>   cdns_i2c_debug_status(regs);
>> @@ -322,19 +329,43 @@ static int cdns_i2c_xfer(struct udevice *dev, struct 
>> i2c_msg *msg,
>>int nmsgs)
>>  {
>>   struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
>> - int ret;
>> + int ret, count;
>> + bool hold_quirk;
>> +
>> +
>
> ditto.
>
>> + printf("i2c_xfer: %d messages\n", nmsgs);
>
> debug?

Yeah, will fix.
>
>
>> + hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
>> +
>> + if (nmsgs > 1) {
>> + /*
>> +  * This controller does not give completion interrupt after a
>> +  * master receive message if HOLD bit is set (repeated start),
>> +  * resulting in SW timeout. Hence, if a receive message is
>> +  * followed by any other message, an error is returned
>> +  * indicating that this sequence is not supported.
>> +  */
>> + for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
>> + if (msg[count].flags & I2C_M_RD) {
>> + printf("Can't do repeated start after a 
>> receive message\n");
>> + 

Re: [U-Boot] [PATCH] i2c: mux: Allow muxes to work as children of i2c bus without i2c-parent

[Moritz Fischer]

Hi Michal,

On Mon, Jan 2, 2017 at 6:24 AM, Michal Simek  wrote:
> On 29.12.2016 23:50, Moritz Fischer wrote:
>> For mux check if the parent is already a device of UCLASS_I2C and if yes
>> just use that. Otherwise see if someone specified an i2c-parent phandle.
>> This mimics the behavior found in the Kernel, as it removes the
>> requirement to explicitly specify a i2c-parent phandle.
>>
>> Signed-off-by: Moritz Fischer 
>> Cc: Heiko Schocher 
>> Cc: Bin Meng 
>> Cc: Simon Glass 
>> Cc: Michal Simek 
>> Cc: u-boot@lists.denx.de
>> ---
>>  drivers/i2c/muxes/i2c-mux-uclass.c | 9 +
>>  1 file changed, 9 insertions(+)
>>
>> diff --git a/drivers/i2c/muxes/i2c-mux-uclass.c 
>> b/drivers/i2c/muxes/i2c-mux-uclass.c
>> index 7a698b6..e01b773 100644
>> --- a/drivers/i2c/muxes/i2c-mux-uclass.c
>> +++ b/drivers/i2c/muxes/i2c-mux-uclass.c
>> @@ -86,6 +86,15 @@ static int i2c_mux_post_probe(struct udevice *mux)
>>   debug("%s: %s\n", __func__, mux->name);
>>   priv->selected = -1;
>>
>> + /* if parent is of i2c uclass already, we'll take that, otherwise
>> +  * look if we find an i2c-parent phandle */
>
> Incorrect comment style.

Yeah, wasn't flagged by checkpatch  will fix.
>
>> + if (UCLASS_I2C == device_get_uclass_id(mux->parent)) {
>> + priv->i2c_bus = dev_get_parent(mux);
>> + debug("%s: bus=%p/%s\n", __func__, priv->i2c_bus,
>> +   priv->i2c_bus->name);
>> + return 0;
>> + }
>> +
>>   ret = uclass_get_device_by_phandle(UCLASS_I2C, mux, "i2c-parent",
>>  >i2c_bus);
>>   if (ret)
>>
>
> The part of this will be good to also handle
> req_seq for mux busses. But at least this should solved part of the
> problems.

I'm not sure I understand this comment.

Thanks for the review, will resubmit

Moritz
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Re: [U-Boot] [PATCH] SPL: NOR: Add CONFIG_SPL_NOR_COPY_ENTIRE_IMAGE define to enable whole image copy from NOR

[Marek Vasut]

On 01/02/2017 01:07 AM, Lukasz Majewski wrote:
> Hi Marek,
> 
>> On 12/30/2016 10:28 PM, Lukasz Majewski wrote:
>>> Hi Marek,
>>>
 On 12/29/2016 04:26 PM, Tom Rini wrote:
> On Thu, Dec 29, 2016 at 12:41:06AM +0100, Marek Vasut wrote:
>> On 12/28/2016 09:52 AM, Lukasz Majewski wrote:
>>> Hi Marek,
>>>
 On 12/26/2016 05:36 PM, Lukasz Majewski wrote:
> Hi Marek,
>
>> On 11/29/2016 07:18 PM, Tom Rini wrote:
>>> On Tue, Nov 29, 2016 at 11:50:34AM +0100, Marek Vasut wrote:
 On 11/29/2016 10:11 AM, Lukasz Majewski wrote:
> Hi Marek,
>
>> On 11/28/2016 10:09 PM, Lukasz Majewski wrote:
>>> This define gives the possibility to copy entire image
>>> (including header - e.g. u-boot.img) from NOR parallel
>>> memory to e.g. SDRAM. The current code only supports
>>> loading the raw binary image (the u-boot.bin).
>>>
>>> The legacy behavior is preserved, since other board
>>> don't enabled this option.
>>
>> So, what's the usecase again ? ;-) 
>
> :-)
>
> The use case is to allow u-boot.img being loaded from
> Parallel NOR. The current code only supports u-boot.bin.

 Why is u-boot.bin (or the payload) not sufficient ? Why do
 you need the header ?
>>>
>>> Well, the general use-case and code flow is that we load
>>> u-boot.img (or a FIT image) and if all else fails, fall back
>>> to assuming a .bin and a known address).
>>>
>> And exactly how is that whole image useful in RAM ? Sorry, I
>> still do not see it, usually you just need the executable
>> payload, although even that can be left in flash most of the
>> time.
>
> The use case is that I do want to boot from SD card/eMMC and
> NOR with using u-boot.img.
>
> I would like to avoid situation when for NOR I must use
> u-boot.bin and for eMMC u-boot.img.
>
> Such approach keeps things as simple as possible :-)

 Oh, so it allows you to detect bitrot for the content in SPI
 NOR ?
>>>
>>> I do not use SPI NOR, it is parallel NOR.
>>
>> Sorry, I meant parallel NOR of course.
>>
 It's a bit strange we had to use u-boot.bin with SPL there.

>>>
>>> This is how the legacy system behaves. It uses (by default)
>>> Parallel NOR for booting (with advised/provided NOR memory
>>> timings). After doing some measurements, it turned out that for
>>> "tunned" u-boot/SPL there would be the best way to copy it to
>>> ram and execute it from there (just like eMMC).
>>>
>>> Hence, I would like to use u-boot.img in both booting scenarios.
>>
>> I think I was mistaken yesterday, I don't think I understand why
>> copying the image including the header into RAM has any benefit
>> compared to copying just the image payload to RAM (and yes, we're
>> getting back to my original question).
>
> Code complexity and forward compatibility?

 This is adding code complexity, but this is not my point.

> The general case in the SPL
> framework is that we have either a "legacy" image or a FIT image
> and we fall back to "well, just run it!".

 Well, this doesn't answer my question, because if I understand this
 patch correctly, it copies the entire legacy image (incl. header)
 into RAM instead of copying just the image payload (which we
 already do). I don't really understand why we want to do this. Or
 do I misunderstand something ?
>>>
>>> No, you understood everything correctly. After some thoughts, I
>>> think that only payload should be copied.
>>
>> But that's what we already do, no ? So what is the point of this
>> patch ?
> 
> So now I do know a bit more ...
> 
> Let's start with ./common/spl/spl.c - spl_parse_image_header()
> 
> With SPL_COPY_PAYLOAD_ONLY flag set (@ common/spl/spl_nor.c) we go to:
> 
> if (spl_image->flags & SPL_COPY_PAYLOAD_ONLY) {
>   /*
>* On some system (e.g. powerpc), the load-address and
>* entry-point is located at address 0. We can't load
>* to 0-0x40. So skip header in this case.
>*/
>   spl_image->load_addr = image_get_load(header);
>   spl_image->entry_point = image_get_ep(header);
>   ^^^- here we set it to 0x0 by default (which
>   is not true for our setup - we expect to boot from 0x1780)
> 
>   spl_image->size = image_get_data_size(header);
> }
> 
> My patch:
> 
> 1. Do not set SPL_COPY_PAYLOAD_ONLY flag, so we go to else clause,
> which according to comment:
> "/* Load including the header */"
> and performs some address manipulation.
> 
> 2. In my patch I undo those address 

[U-Boot] [PULL] Please pull u-boot-imx

[Stefano Babic]

Hi Tom,

please pull from u-boot-imx, thanks !

The following changes since commit 3d3a74cc8c774345be7d1661b21ad41f4515:

  mmc: move MMC_SDHCI_IO_ACCESSORS to Kconfig (2016-12-29 13:08:17 -0500)

are available in the git repository at:

  git://www.denx.de/git/u-boot-imx.git master

for you to fetch changes up to 7c4f0ff81e6fc3b58b8af5f64c3da98624e40132:

  udoo: neo: Fix indentation (2017-01-02 17:55:58 +0100)


Fabio Estevam (4):
  udoo_neo: Remove USDHC3 entry
  udoo_neo: Use 'fdtfile' variable name
  mx6qsabreauto: Fix the EIM clock for the mx6qp variant
  udoo: neo: Fix indentation

Jagan Teki (12):
  imx6: engicam: Use bootm instead of bootz
  configs: engicam: Rename nand with gpmi-name in mtdparts
  defconfigs: engicam: Enable MMC commands in nand
  defconfigs: engicam: Enable UBI commands
  imx6: engicam: Add nandboot env support
  defconfigs: imx6: engicam: Enable FIT
  configs: engicam: Enable CONFIG_IMAGE_FORMAT_LEGACY
  configs: engicam: Cleanup on mmcboot env
  configs: engicam: Add fitboot env support
  imx6ul: geam6ul: Add MAINTAINERS for nand_defconfig
  imx6ul: geam6ul: Enable I2C support

Kevin Hilman (1):
  ARM: imx7s-warp: enable USB gadget ethernet

Peng Fan (1):
  imx: thermal: Kconfig: add MX7

Sven Ebenfeld (5):
  arm: imx: remove bmode , hdmidet and dek commands from SPL
  arm: imx: add HAB authentication of image to SPL boot
  tools: mkimage: add firmware-ivt image type for HAB verification
  doc: imx6: add section for secure boot with SPL
  Makefile: preserve output for images that can contain HAB Blocks

 .gitignore|   2 +-
 Makefile  |  15 +--
 arch/arm/Makefile |   2 +-
 arch/arm/imx-common/Makefile  |   6 ++
 arch/arm/imx-common/hab.c | 129
+---
 arch/arm/imx-common/spl.c |  25
+
 arch/arm/imx-common/spl_sd.cfg|  10 ++
 arch/arm/include/asm/imx-common/hab.h |   2 ++
 board/engicam/geam6ul/MAINTAINERS |   1 +
 board/freescale/mx6qsabreauto/mx6qsabreauto.c |  28

 board/udoo/neo/neo.c  |   7 +++
 board/warp7/warp7.c   |  14 ++
 common/image.c|   6 ++
 configs/imx6dl_icore_mmc_defconfig|   4 +++-
 configs/imx6dl_icore_nand_defconfig   |  10 +-
 configs/imx6dl_icore_rqs_mmc_defconfig|   4 +++-
 configs/imx6q_icore_mmc_defconfig |   4 +++-
 configs/imx6q_icore_nand_defconfig|  10 +-
 configs/imx6q_icore_rqs_mmc_defconfig |   4 +++-
 configs/imx6ul_geam_mmc_defconfig |   4 +++-
 configs/imx6ul_geam_nand_defconfig|  12 +++-
 configs/warp7_defconfig   |   5 +
 doc/README.imx6   |  49
+
 drivers/thermal/Kconfig   |   2 +-
 include/configs/imx6qdl_icore.h   |  77
+---
 include/configs/imx6qdl_icore_rqs.h   |  43
++-
 include/configs/imx6ul_geam.h |  76
---
 include/configs/mx6_common.h  |   3 +++
 include/configs/udoo_neo.h|  12 ++--
 include/configs/warp7.h   |   7 +++
 include/image.h   |   1 +
 scripts/Makefile.lib  |   3 ++-
 scripts/Makefile.spl  |   4 +++-
 tools/default_image.c |  10 --
 tools/mkimage.c   |  32

 35 files changed, 486 insertions(+), 137 deletions(-)

Best regards,
Stefano

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Re: [U-Boot] [RESEND PATCH v3 1/2] mmc: rockchip_sdhci: add clock init for mmc

[Stefan Herbrechtsmeier]

Hi,

Am 02.01.2017 um 02:29 schrieb Jaehoon Chung:

Hi Stefan,

[snip]


Of_course, it needs to consider the base clock broken case.

The whole discussion is about the base clock broken case. Otherwise the 
host->max_clk is extracted from the SDHCI_CAPABILITIES.
The linux kernel use a callback to request the host->max_clk from the driver in the base 
clock broken case. The current u-boot implementation only supports the host->max_clk but 
call it unfortunately mmc->cfg->f_max which could be mistaken as mmc->f_max from the 
kernel which represents max-frequency.


Linux kernel has two options. One is get_max_clock(), the other is "using 
'max-frequency' property".
The 'max-frequency' is read in host.c into f_max and used to limit the 
maximum clock in mmc_set_clock() in core.c.


In sdhci.c the f_max is set to max_clk if f_max is zero or higher then 
max_clk.


The whole sdhci.c use only the max_clk to calculate the divider and 
multiplier for the requested clock.


Most sdhci-*.c drivers use a preset clock rate or set a fixed clock rate.

Only  the  sdhci-bcm-kona.c and sdhci-st.c use the f_max for 
clk_set_rate(). They should instead use the 'clock-frequency' or 
'assigned-clock-rates'. Especially the last assume three specific clock 
rates and set the clock to a minimum of 50 MHz even for a lower 
'max-frequency'.


You always need to values. One to set the clock and one to limit the 
max-frequency independent of the base clock.



Kever's patch is not problem.

The problem is that the patch "init the clock rate to max-frequency" and this 
is wrong and differs from the kernel which use the assigned-clock-rates. What happens if 
somebody sets the max-frequency to 40? Does the clock controller supports such a low 
frequency? What happens if the clock controller use a different clock as requested and 
the mmc framework assume the requested clock rate?

Agreed this point, It needs to implement the clk_set_rate() in 
rockchip_sdhci.c. with value passed by set_ios().

Does we speak about the sdhci or dw_mmc controller? The sdhci don't change the 
host->max_clk and don't need the clk_set_rate(). It have its own divider and 
optional multiplier and doesn't change the base clock.


sdhci and dwmmc controller are using the clk_set_rate() in each SoC's drivers.
Where can I find this code? Even in u-boot some drivers use the preset 
clock values.



Since driver's divider has a limitation. So i think it needs to use the 
"clk_set_rate()".

Do you plan to change all Linux drivers?




The mmc drivers shouldn't use the max-frequency to request a clock rate. It 
should only request the current clock rate or set a default clock rate 
independent of the max-frequency.

Back to this patch. It should use the CONFIG_ROCKCHIP_SDHCI_MAX_FREQ in the 
clk_set_rate() or use the default rate and only request it with clk_get_rate().

Maybe my last patch could be generalized and the max-frequency support could be 
moved inside the sdhci driver.

I don't want to use CONFIG_ROCKCHIP_SDHCI_MAX_FREQ...i will remove the all 
CONFIG_ for using value.
But then you need to encode this specific values inside the device tree 
and don't misuse the 'max-frequency' property. You need to support a 
fixed clock frequency for sdhci controller with a lower 'max-frequency' 
for the external mmc interface.


Regards
  Stefan

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Re: [U-Boot] [PATCH 00/10] i.MX6: engicam: Add nandboot env and FIT support

[Jagan Teki]

On Mon, Jan 2, 2017 at 5:52 PM, Stefano Babic  wrote:
> On 21/12/2016 12:00, Jagan Teki wrote:
>> From: Jagan Teki 
>>
>> This patchset, add support for
>> - legacy image boot, with bootm
>> - NAND boot env support, with UBIFS as rootfs
>> - FIT image boot support
>>
>> on i.MX6 based Engicam Quad/DualLite/Dual/Solo module kits.
>>
>> Jagan Teki (10):
>>   configs: engicam: Increase nand kernel partition size
>>   imx6: engicam: Use bootm instead of bootz
>>   configs: engicam: Rename nand with gpmi-name in mtdparts
>>   defconfigs: engicam: Enable MMC commands in nand
>>   defconfigs: engicam: Enable UBI commands
>>   imx6: engicam: Add nandboot env support
>>   defconfigs: imx6: engicam: Enable FIT
>>   configs: engicam: Enable CONFIG_IMAGE_FORMAT_LEGACY
>>   configs: engicam: Cleanup on mmcboot env
>>   configs: engicam: Add fitboot env support
>>
>>  configs/imx6dl_icore_mmc_defconfig |  4 +-
>>  configs/imx6dl_icore_nand_defconfig| 10 -
>>  configs/imx6dl_icore_rqs_mmc_defconfig |  4 +-
>>  configs/imx6q_icore_mmc_defconfig  |  4 +-
>>  configs/imx6q_icore_nand_defconfig | 10 -
>>  configs/imx6q_icore_rqs_mmc_defconfig  |  4 +-
>>  configs/imx6ul_geam_mmc_defconfig  |  4 +-
>>  configs/imx6ul_geam_nand_defconfig | 10 -
>>  include/configs/imx6qdl_icore.h| 77 
>> +-
>>  include/configs/imx6qdl_icore_rqs.h| 43 +--
>>  include/configs/imx6ul_geam.h  | 76 
>> -
>>  11 files changed, 187 insertions(+), 59 deletions(-)
>>
>
> Applied (after small rebasing) to u-boot-imx, -master, thanks !

Thanks.

-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH] udoo_neo: Remove USDHC3 entry

[Stefano Babic]

On 16/12/2016 14:18, Fabio Estevam wrote:
> Commit c94981efa20cc58 ("udoo_neo: Remove USDHC3 support") removed
> the SDHC3 support, but missed to remove the entry from the usdhc_cfg
> structure, so just remove it. 
> 
> Signed-off-by: Fabio Estevam 
> ---
>  board/udoo/neo/neo.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
> index 688b522..c5058b4 100644
> --- a/board/udoo/neo/neo.c
> +++ b/board/udoo/neo/neo.c
> @@ -389,9 +389,8 @@ int board_early_init_f(void)
>   return 0;
>  }
>  
> -static struct fsl_esdhc_cfg usdhc_cfg[2] = {
> +static struct fsl_esdhc_cfg usdhc_cfg[1] = {
>   {USDHC2_BASE_ADDR, 0, 4},
> - {USDHC3_BASE_ADDR, 0, 4},
>  };
>  
>  #define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
> 

Applied to u-boot-imx, -master, thanks !

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH] udoo: neo: Fix indentation

[Stefano Babic]

On 02/01/2017 11:44, Fabio Estevam wrote:
> From: Fabio Estevam 
> 
> The standard way is to put ifdef/endif in the very first column.
> 
> Signed-off-by: Fabio Estevam 
> ---
>  board/udoo/neo/neo.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
> index 688b522..288674a 100644
> --- a/board/udoo/neo/neo.c
> +++ b/board/udoo/neo/neo.c
> @@ -349,9 +349,9 @@ int board_init(void)
>   /* Active high for ncp692 */
>   gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
>  
> - #ifdef CONFIG_SYS_I2C_MXC
> +#ifdef CONFIG_SYS_I2C_MXC
>   setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, _pad_info1);
> - #endif
> +#endif
>  
>   return 0;
>  }
> 
Applied to u-boot-imx, -master, thanks !

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH] imx6ul: geam6ul: Enable I2C support

[Stefano Babic]

On 21/12/2016 22:14, Jagan Teki wrote:
> From: Jagan Teki 
> 
> Enable I2C support for Engicam GEAM6UL NAND module.
> 
> Cc: Stefano Babic 
> Cc: Matteo Lisi 
> Cc: Michael Trimarchi 
> Signed-off-by: Jagan Teki 
> ---
>  configs/imx6ul_geam_nand_defconfig | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/configs/imx6ul_geam_nand_defconfig 
> b/configs/imx6ul_geam_nand_defconfig
> index 71ef06a..66274e5 100644
> --- a/configs/imx6ul_geam_nand_defconfig
> +++ b/configs/imx6ul_geam_nand_defconfig
> @@ -26,6 +26,7 @@ CONFIG_CMD_PING=y
>  CONFIG_CMD_NAND=y
>  CONFIG_CMD_UBI=y
>  CONFIG_CMD_CACHE=y
> +CONFIG_CMD_I2C=y
>  CONFIG_CMD_EXT4=y
>  CONFIG_CMD_EXT4_WRITE=y
>  CONFIG_CMD_FAT=y
> @@ -37,6 +38,7 @@ CONFIG_NAND_MXS=y
>  CONFIG_IMX_THERMAL=y
>  CONFIG_PINCTRL=y
>  CONFIG_PINCTRL_IMX6=y
> +CONFIG_SYS_I2C_MXC=y
>  CONFIG_SPL_LIBCOMMON_SUPPORT=y
>  CONFIG_SPL_LIBGENERIC_SUPPORT=y
>  CONFIG_SPL_SERIAL_SUPPORT=y
> 

Applied to u-boot-imx, -master, thanks !

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH] imx6ul: geam6ul: Add MAINTAINERS for nand_defconfig

[Stefano Babic]

On 21/12/2016 12:02, Jagan Teki wrote:
> From: Jagan Teki 
> 
> Add Jagan as MAINTAINERS of configs/imx6ul_geam_nand_defconfig
> 
> Cc: Stefano Babic 
> Cc: Matteo Lisi 
> Cc: Michael Trimarchi 
> Signed-off-by: Jagan Teki 
> ---
>  board/engicam/geam6ul/MAINTAINERS | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/board/engicam/geam6ul/MAINTAINERS 
> b/board/engicam/geam6ul/MAINTAINERS
> index 6691450..079370c 100644
> --- a/board/engicam/geam6ul/MAINTAINERS
> +++ b/board/engicam/geam6ul/MAINTAINERS
> @@ -4,3 +4,4 @@ S:Maintained
>  F:   board/engicam/geam6ul
>  F:   include/configs/imx6ul_geam.h
>  F:   configs/imx6ul_geam_mmc_defconfig
> +F:   configs/imx6ul_geam_nand_defconfig
> 

Applied to u-boot-imx, -master, thanks !

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH] mx6qsabreauto: Fix the EIM clock for the mx6qp variant

[Stefano Babic]

On 27/12/2016 02:04, Fabio Estevam wrote:
> From: Fabio Estevam 
> 
> On the MX6Q the aclk_eim_slow_podf field is '1' after POR, while on the
> MX6DQP it is '3'.
> 
> This makes the EIM clock to be only 66MHz on the mx6qp variant, instead of
> 132 MHz.
> 
> Instead of relying on the POR values for the CSMR1 register, make sure to
> manually configure the clk_eim_slow_sel field as '00' so that EIM clock is
> derived from AXI clock and the aclk_eim_slow_podf field as '1' so that EIM
> clock can be AXI clock divided by 2.
> 
> This way a consistent EIM clock frequency is configured for all the mx6
> variants.
> 
> Signed-off-by: Fabio Estevam 
> ---
>  board/freescale/mx6qsabreauto/mx6qsabreauto.c | 28 
> +++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c 
> b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
> index 5fca4d1..51bbbc4 100644
> --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
> +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
> @@ -231,6 +231,33 @@ static void eimnor_cs_setup(void)
>   set_chipselect_size(CS0_128);
>  }
>  
> +static void eim_clk_setup(void)
> +{
> + struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> + int cscmr1, ccgr6;
> +
> +
> + /* Turn off EIM clock */
> + ccgr6 = readl(_ccm->CCGR6);
> + ccgr6 &= ~(0x3 << 10);
> + writel(ccgr6, _ccm->CCGR6);
> +
> + /*
> +  * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
> +  * and aclk_eim_slow_podf = 01 --> divide by 2
> +  * so that we can have EIM at the maximum clock of 132MHz
> +  */
> + cscmr1 = readl(_ccm->cscmr1);
> + cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
> + MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
> + cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
> + writel(cscmr1, _ccm->cscmr1);
> +
> + /* Turn on EIM clock */
> + ccgr6 |= (0x3 << 10);
> + writel(ccgr6, _ccm->CCGR6);
> +}
> +
>  static void setup_iomux_eimnor(void)
>  {
>   imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
> @@ -519,6 +546,7 @@ int board_early_init_f(void)
>  #ifdef CONFIG_NAND_MXS
>   setup_gpmi_nand();
>  #endif
> + eim_clk_setup();
>  
>   return 0;
>  }
> 

Applied to u-boot-imx, -master, thanks !

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH 00/10] i.MX6: engicam: Add nandboot env and FIT support

[Stefano Babic]

On 21/12/2016 12:00, Jagan Teki wrote:
> From: Jagan Teki 
> 
> This patchset, add support for
> - legacy image boot, with bootm
> - NAND boot env support, with UBIFS as rootfs
> - FIT image boot support
> 
> on i.MX6 based Engicam Quad/DualLite/Dual/Solo module kits.
> 
> Jagan Teki (10):
>   configs: engicam: Increase nand kernel partition size
>   imx6: engicam: Use bootm instead of bootz
>   configs: engicam: Rename nand with gpmi-name in mtdparts
>   defconfigs: engicam: Enable MMC commands in nand
>   defconfigs: engicam: Enable UBI commands
>   imx6: engicam: Add nandboot env support
>   defconfigs: imx6: engicam: Enable FIT
>   configs: engicam: Enable CONFIG_IMAGE_FORMAT_LEGACY
>   configs: engicam: Cleanup on mmcboot env
>   configs: engicam: Add fitboot env support
> 
>  configs/imx6dl_icore_mmc_defconfig |  4 +-
>  configs/imx6dl_icore_nand_defconfig| 10 -
>  configs/imx6dl_icore_rqs_mmc_defconfig |  4 +-
>  configs/imx6q_icore_mmc_defconfig  |  4 +-
>  configs/imx6q_icore_nand_defconfig | 10 -
>  configs/imx6q_icore_rqs_mmc_defconfig  |  4 +-
>  configs/imx6ul_geam_mmc_defconfig  |  4 +-
>  configs/imx6ul_geam_nand_defconfig | 10 -
>  include/configs/imx6qdl_icore.h| 77 
> +-
>  include/configs/imx6qdl_icore_rqs.h| 43 +--
>  include/configs/imx6ul_geam.h  | 76 -
>  11 files changed, 187 insertions(+), 59 deletions(-)
> 

Applied (after small rebasing) to u-boot-imx, -master, thanks !

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH] udoo_neo: Remove USDHC3 entry

[Stefano Babic]

On 16/12/2016 14:18, Fabio Estevam wrote:
> Commit c94981efa20cc58 ("udoo_neo: Remove USDHC3 support") removed
> the SDHC3 support, but missed to remove the entry from the usdhc_cfg
> structure, so just remove it. 
> 
> Signed-off-by: Fabio Estevam 
> ---
>  board/udoo/neo/neo.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
> index 688b522..c5058b4 100644
> --- a/board/udoo/neo/neo.c
> +++ b/board/udoo/neo/neo.c
> @@ -389,9 +389,8 @@ int board_early_init_f(void)
>   return 0;
>  }
>  
> -static struct fsl_esdhc_cfg usdhc_cfg[2] = {
> +static struct fsl_esdhc_cfg usdhc_cfg[1] = {
>   {USDHC2_BASE_ADDR, 0, 4},
> - {USDHC3_BASE_ADDR, 0, 4},
>  };
>  
>  #define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
> 

Applied to u-boot-imx, -master, thanks !

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH] ARM: imx7s-warp: enable USB gadget ethernet

[Stefano Babic]

On 16/12/2016 22:04, Kevin Hilman wrote:
> Enable USB gadget ethernet by default to have networking capabilities.
> 
> Tested using DHCP and TFTP to transfer kernel, DT, ramdisk.
> 
> Cc: Fabio Estevam 
> Signed-off-by: Kevin Hilman 
> ---
> Applies to v2016.11
> 
>  board/warp7/warp7.c | 14 ++
>  configs/warp7_defconfig |  5 +
>  include/configs/warp7.h |  7 +++
>  3 files changed, 26 insertions(+)
> 
> diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c
> index da9afb4ccd86..df8e9da6f919 100644
> --- a/board/warp7/warp7.c
> +++ b/board/warp7/warp7.c
> @@ -19,6 +19,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include "../freescale/common/pfuze.h"
> @@ -138,6 +139,19 @@ int power_init_board(void)
>  }
>  #endif
>  
> +int board_eth_init(bd_t *bis)
> +{
> + int ret = 0;
> +
> +#ifdef CONFIG_USB_ETHER
> + ret = usb_eth_initialize(bis);
> + if (ret < 0)
> + printf("Error %d registering USB ether.\n", ret);
> +#endif
> +
> + return ret;
> +}
> +
>  int board_init(void)
>  {
>   /* address of boot parameters */
> diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
> index 0f0ec99e50ca..81acd8ff15c8 100644
> --- a/configs/warp7_defconfig
> +++ b/configs/warp7_defconfig
> @@ -35,3 +35,8 @@ CONFIG_G_DNL_MANUFACTURER="FSL"
>  CONFIG_G_DNL_VENDOR_NUM=0x0525
>  CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
>  CONFIG_OF_LIBFDT=y
> +
> +CONFIG_CMD_NET=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_CMD_DHCP=y
> +
> diff --git a/include/configs/warp7.h b/include/configs/warp7.h
> index d3b0c5e0d62c..f4a92319ebad 100644
> --- a/include/configs/warp7.h
> +++ b/include/configs/warp7.h
> @@ -38,6 +38,7 @@
>   "script=boot.scr\0" \
>   "image=zImage\0" \
>   "console=ttymxc0\0" \
> + "ethact=usb_ether\0" \
>   "fdt_high=0x\0" \
>   "initrd_high=0x\0" \
>   "fdt_file=imx7s-warp.dtb\0" \
> @@ -145,4 +146,10 @@
>  #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
>  #define DFU_DEFAULT_POLL_TIMEOUT 300
>  
> +#define CONFIG_USB_ETHER
> +#define CONFIG_USB_ETH_CDC
> +#define CONFIG_USB_ETH_RNDIS
> +#define CONFIG_USBNET_HOST_ADDR  "de:ad:be:af:00:00"
> +#define CONFIG_USBNET_DEV_ADDR   "de:ad:be:af:00:01"
> +
>  #endif
> 
Applied to u-boot-imx, -master, thanks !

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH] imx: thermal: Kconfig: add MX7

[Stefano Babic]

On 02/12/2016 06:43, Peng Fan wrote:
> The thermal drivers support i.MX6 and i.MX7, add MX7 in Kconfig file.
> 
> Signed-off-by: Peng Fan 
> Cc: Stefano Babic 
> ---
>  drivers/thermal/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
> index f0ffbb3..886f5fa 100644
> --- a/drivers/thermal/Kconfig
> +++ b/drivers/thermal/Kconfig
> @@ -10,7 +10,7 @@ if DM_THERMAL
>  
>  config IMX_THERMAL
>   bool "Temperature sensor driver for Freescale i.MX SoCs"
> - depends on MX6
> + depends on MX6 || MX7
>   help
> Support for Temperature Monitor (TEMPMON) found on Freescale i.MX 
> SoCs.
>It supports one critical trip point and one passive trip point.  
> The
> 

Applied to u-boot-imx, -master, thanks !

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH] udoo_neo: Use 'fdtfile' variable name

[Stefano Babic]

On 15/12/2016 23:10, Fabio Estevam wrote:
> From: Fabio Estevam 
> 
> 'fdtfile' is the preferred name for the variable that contains the
> device tree blob according to the README file.
> 
> It also makes it consistent with other i.MX boards that use config_distro,
> so change it accordingly.
> 
> Signed-off-by: Fabio Estevam 
> ---
>  include/configs/udoo_neo.h | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h
> index 81e0481..e5057be 100644
> --- a/include/configs/udoo_neo.h
> +++ b/include/configs/udoo_neo.h
> @@ -36,7 +36,7 @@
>   "console=ttymxc0,115200\0" \
>   "fdt_high=0x\0" \
>   "initrd_high=0x\0" \
> - "fdt_file=undefined\0" \
> + "fdtfile=undefined\0" \
>   "fdt_addr=0x8300\0" \
>   "ip_dyn=yes\0" \
>   "mmcdev=0\0" \
> @@ -44,14 +44,14 @@
>   "mmcautodetect=no\0" \
>   "findfdt="\
>   "if test $board_name = BASIC; then " \
> - "setenv fdt_file imx6sx-udoo-neo-basic.dtb; fi; " \
> + "setenv fdtfile imx6sx-udoo-neo-basic.dtb; fi; " \
>   "if test $board_name = BASICKS; then " \
> - "setenv fdt_file imx6sx-udoo-neo-basic.dtb; fi; " \
> + "setenv fdtfile imx6sx-udoo-neo-basic.dtb; fi; " \
>   "if test $board_name = FULL; then " \
> - "setenv fdt_file imx6sx-udoo-neo-full.dtb; fi; " \
> + "setenv fdtfile imx6sx-udoo-neo-full.dtb; fi; " \
>   "if test $board_name = EXTENDED; then " \
> - "setenv fdt_file imx6sx-udoo-neo-extended.dtb; fi; " \
> - "if test $fdt_file = UNDEFINED; then " \
> + "setenv fdtfile imx6sx-udoo-neo-extended.dtb; fi; " \
> + "if test $fdtfile = UNDEFINED; then " \
>   "echo WARNING: Could not determine dtb to use; fi; \0" \
>   "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
>   "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
> 

Applied to u-boot-imx, -master, thanks !

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH v2 0/5] arm: imx6: Enable Secure Boot (HAB) with SPL Builds

[Stefano Babic]

On 06/11/2016 16:37, Sven Ebenfeld wrote:
> When trying to build U-Boot for Wandboard with Secure Boot, the build fails
> because it tries to compile the dekblob commands within the SPL. The dekblob
> command depends on the CAAM driver, which is also not required in the SPL. 
> Additionally, this blows the SPL up to a size beyond the limit of 69KiB in
> i.MX6DL OCRAM. Therefore I deactivate building the commands during SPL build.
> 
> Next I implemented HAB verification before jumping to the loaded image. To
> create images that are HAB compatible, I updated the mkimage tool and added 
> some
> documentation. At last I try to make the signing process easier as the output 
> of
> the mkimage tool will be preserverd within the build dir. The output contains
> information required to correctly sign HAB images.
> 
> Cc: sba...@denx.de
> 
> v2 Changes:
>  - Repair build failures in many SPLs due to incorrect variable assignment.
>  - Repair mx31 and mx27 builds without imx-common libs (nothing is built there
>for them.
> 
> Sven Ebenfeld (5):
>   arm: imx: remove bmode , hdmidet and dek commands from SPL
>   arm: imx: add HAB authentication of image to SPL boot
>   tools: mkimage: add firmware-ivt image type for HAB verification
>   doc: imx6: add section for secure boot with SPL
>   Makefile: preserve output for images that can contain HAB Blocks
> 
>  .gitignore|   2 +-
>  Makefile  |  15 +++-
>  arch/arm/Makefile |   2 +-
>  arch/arm/imx-common/Makefile  |   6 ++
>  arch/arm/imx-common/hab.c | 129 
> ++
>  arch/arm/imx-common/spl.c |  25 +++
>  arch/arm/imx-common/spl_sd.cfg|  10 +++
>  arch/arm/include/asm/imx-common/hab.h |   2 +
>  common/image.c|   6 ++
>  doc/README.imx6   |  49 +
>  include/configs/mx6_common.h  |   3 +
>  include/image.h   |   1 +
>  scripts/Makefile.lib  |   3 +-
>  scripts/Makefile.spl  |   4 +-
>  tools/default_image.c |  10 ++-
>  tools/mkimage.c   |  32 +
>  16 files changed, 232 insertions(+), 67 deletions(-)
> 

Applied to u-boot-imx, -master, thanks !

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH 00/10] i.MX6: engicam: Add nandboot env and FIT support

[Stefano Babic]

On 01/01/2017 20:05, Jagan Teki wrote:
> Hi Stefano,
> 
> On Thu, Dec 29, 2016 at 2:37 PM, Jagan Teki  wrote:
>> Hi Stefano,
>>
>> On Wed, Dec 21, 2016 at 12:00 PM, Jagan Teki  wrote:
>>> From: Jagan Teki 
>>>
>>> This patchset, add support for
>>> - legacy image boot, with bootm
>>> - NAND boot env support, with UBIFS as rootfs
>>> - FIT image boot support
>>>
>>> on i.MX6 based Engicam Quad/DualLite/Dual/Solo module kits.
>>>
>>> Jagan Teki (10):
>>>   configs: engicam: Increase nand kernel partition size
>>>   imx6: engicam: Use bootm instead of bootz
>>>   configs: engicam: Rename nand with gpmi-name in mtdparts
>>>   defconfigs: engicam: Enable MMC commands in nand
>>>   defconfigs: engicam: Enable UBI commands
>>>   imx6: engicam: Add nandboot env support
>>>   defconfigs: imx6: engicam: Enable FIT
>>>   configs: engicam: Enable CONFIG_IMAGE_FORMAT_LEGACY
>>>   configs: engicam: Cleanup on mmcboot env
>>>   configs: engicam: Add fitboot env support
>>
>> Please pick this series, buildman works fine.
> 
> Since these changes related to engicam doesn't effect any other, is it
> OK if I send PR for this?
> 

Generally speaking, the series should flow into -next because it was
sent after merge window is closed. But I agree, the series touches just
files for engicam - I will apply it before my (last) PR for this release.

Best regards,
Stefano Babic

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[U-Boot] [PATCH v4] BOARD: MCCMON6: Provide support for iMX6q based mccmon6 board

[Lukasz Majewski]

This patch provides u-boot support for Liebherr (LWN) mccmon6 board.

Signed-off-by: Lukasz Majewski 
---
Changes for v4:
- Update board/liebherr/mccmon6/MAINTAINERS entry to quiet buildman warnings

Changes for v3:
- Define CONFIG_SYS_UBOOT_START to load u-boot image from NOR to correct address
  (so the SPL: NOR: Add CONFIG_SPL_NOR_COPY_ENTIRE_IMAGE define to enable whole 
image copy from NOR
  can be dropped)
- Update author information

Changes for v2:
- Provide space after "quiet" console boot parameter to not pollute next
  parameters
---
 arch/arm/cpu/armv7/mx6/Kconfig   |   5 +
 board/liebherr/mccmon6/Kconfig   |  12 +
 board/liebherr/mccmon6/MAINTAINERS   |   7 +
 board/liebherr/mccmon6/Makefile  |   8 +
 board/liebherr/mccmon6/mccmon6.c | 490 +++
 board/liebherr/mccmon6/mon6_imximage_nor.cfg |   9 +
 board/liebherr/mccmon6/mon6_imximage_sd.cfg  |   9 +
 board/liebherr/mccmon6/spl.c | 317 +
 configs/mccmon6_nor_defconfig|  36 ++
 configs/mccmon6_sd_defconfig |  37 ++
 include/configs/mccmon6.h| 333 ++
 11 files changed, 1263 insertions(+)
 create mode 100644 board/liebherr/mccmon6/Kconfig
 create mode 100644 board/liebherr/mccmon6/MAINTAINERS
 create mode 100644 board/liebherr/mccmon6/Makefile
 create mode 100644 board/liebherr/mccmon6/mccmon6.c
 create mode 100644 board/liebherr/mccmon6/mon6_imximage_nor.cfg
 create mode 100644 board/liebherr/mccmon6/mon6_imximage_sd.cfg
 create mode 100644 board/liebherr/mccmon6/spl.c
 create mode 100644 configs/mccmon6_nor_defconfig
 create mode 100644 configs/mccmon6_sd_defconfig
 create mode 100644 include/configs/mccmon6.h

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index c646966..9eddd7e 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -114,6 +114,10 @@ config TARGET_KOSAGI_NOVENA
bool "Kosagi Novena"
select SUPPORT_SPL
 
+config TARGET_MCCMON6
+   bool "mccmon6"
+   select SUPPORT_SPL
+
 config TARGET_MX6CUBOXI
bool "Solid-run mx6 boards"
select SUPPORT_SPL
@@ -327,6 +331,7 @@ source "board/phytec/pcm058/Kconfig"
 source "board/gateworks/gw_ventana/Kconfig"
 source "board/kosagi/novena/Kconfig"
 source "board/samtec/vining_2000/Kconfig"
+source "board/liebherr/mccmon6/Kconfig"
 source "board/seco/Kconfig"
 source "board/solidrun/mx6cuboxi/Kconfig"
 source "board/technexion/pico-imx6ul/Kconfig"
diff --git a/board/liebherr/mccmon6/Kconfig b/board/liebherr/mccmon6/Kconfig
new file mode 100644
index 000..4cc7fc2
--- /dev/null
+++ b/board/liebherr/mccmon6/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MCCMON6
+
+config SYS_BOARD
+   default "mccmon6"
+
+config SYS_VENDOR
+   default "liebherr"
+
+config SYS_CONFIG_NAME
+   default "mccmon6"
+
+endif
diff --git a/board/liebherr/mccmon6/MAINTAINERS 
b/board/liebherr/mccmon6/MAINTAINERS
new file mode 100644
index 000..c9c7183
--- /dev/null
+++ b/board/liebherr/mccmon6/MAINTAINERS
@@ -0,0 +1,7 @@
+MCCMON6 BOARD
+M: Lukasz Majewski 
+S: Maintained
+F: board/liebherr/mccmon6/
+F: include/configs/mccmon6.h
+F: configs/mccmon6_nor_defconfig
+F: configs/mccmon6_sd_defconfig
diff --git a/board/liebherr/mccmon6/Makefile b/board/liebherr/mccmon6/Makefile
new file mode 100644
index 000..e37baf8
--- /dev/null
+++ b/board/liebherr/mccmon6/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2016-2017
+# Lukasz Majewski, DENX Software Engineering, lu...@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := mccmon6.o spl.o
diff --git a/board/liebherr/mccmon6/mccmon6.c b/board/liebherr/mccmon6/mccmon6.c
new file mode 100644
index 000..eb5eae4
--- /dev/null
+++ b/board/liebherr/mccmon6/mccmon6.c
@@ -0,0 +1,490 @@
+/*
+ * Copyright (C) 2016-2017
+ * Lukasz Majewski, DENX Software Engineering, lu...@denx.de
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |  \
+   PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+   PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |   \
+   PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+   PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |  \
+   PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |\
+   PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL   (PAD_CTL_PUS_100K_UP |  \
+   

[U-Boot] [PATCH v3] BOARD: MCCMON6: Provide support for iMX6q based mccmon6 board

[Lukasz Majewski]

This patch provides u-boot support for Liebherr (LWN) mccmon6 board.

Signed-off-by: Lukasz Majewski 
---
Changes for v3:
- Define CONFIG_SYS_UBOOT_START to load u-boot image from NOR to correct address
  (so the SPL: NOR: Add CONFIG_SPL_NOR_COPY_ENTIRE_IMAGE define to enable whole 
image copy from NOR
  can be dropped)
- Update author information

Changes for v2:
- Provide space after "quiet" console boot parameter to not pollute next
  parameters
---
 arch/arm/cpu/armv7/mx6/Kconfig   |   5 +
 board/liebherr/mccmon6/Kconfig   |  12 +
 board/liebherr/mccmon6/MAINTAINERS   |   6 +
 board/liebherr/mccmon6/Makefile  |   8 +
 board/liebherr/mccmon6/mccmon6.c | 490 +++
 board/liebherr/mccmon6/mon6_imximage_nor.cfg |   9 +
 board/liebherr/mccmon6/mon6_imximage_sd.cfg  |   9 +
 board/liebherr/mccmon6/spl.c | 317 +
 configs/mccmon6_nor_defconfig|  36 ++
 configs/mccmon6_sd_defconfig |  37 ++
 include/configs/mccmon6.h| 333 ++
 11 files changed, 1262 insertions(+)
 create mode 100644 board/liebherr/mccmon6/Kconfig
 create mode 100644 board/liebherr/mccmon6/MAINTAINERS
 create mode 100644 board/liebherr/mccmon6/Makefile
 create mode 100644 board/liebherr/mccmon6/mccmon6.c
 create mode 100644 board/liebherr/mccmon6/mon6_imximage_nor.cfg
 create mode 100644 board/liebherr/mccmon6/mon6_imximage_sd.cfg
 create mode 100644 board/liebherr/mccmon6/spl.c
 create mode 100644 configs/mccmon6_nor_defconfig
 create mode 100644 configs/mccmon6_sd_defconfig
 create mode 100644 include/configs/mccmon6.h

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index c646966..9eddd7e 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -114,6 +114,10 @@ config TARGET_KOSAGI_NOVENA
bool "Kosagi Novena"
select SUPPORT_SPL
 
+config TARGET_MCCMON6
+   bool "mccmon6"
+   select SUPPORT_SPL
+
 config TARGET_MX6CUBOXI
bool "Solid-run mx6 boards"
select SUPPORT_SPL
@@ -327,6 +331,7 @@ source "board/phytec/pcm058/Kconfig"
 source "board/gateworks/gw_ventana/Kconfig"
 source "board/kosagi/novena/Kconfig"
 source "board/samtec/vining_2000/Kconfig"
+source "board/liebherr/mccmon6/Kconfig"
 source "board/seco/Kconfig"
 source "board/solidrun/mx6cuboxi/Kconfig"
 source "board/technexion/pico-imx6ul/Kconfig"
diff --git a/board/liebherr/mccmon6/Kconfig b/board/liebherr/mccmon6/Kconfig
new file mode 100644
index 000..4cc7fc2
--- /dev/null
+++ b/board/liebherr/mccmon6/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MCCMON6
+
+config SYS_BOARD
+   default "mccmon6"
+
+config SYS_VENDOR
+   default "liebherr"
+
+config SYS_CONFIG_NAME
+   default "mccmon6"
+
+endif
diff --git a/board/liebherr/mccmon6/MAINTAINERS 
b/board/liebherr/mccmon6/MAINTAINERS
new file mode 100644
index 000..ce956c8
--- /dev/null
+++ b/board/liebherr/mccmon6/MAINTAINERS
@@ -0,0 +1,6 @@
+MCCMON6 BOARD
+M: Lukasz Majewski 
+S: Maintained
+F: board/liebherr/mccmon6/
+F: include/configs/mccmon6.h
+F: configs/mccmon6_defconfig
diff --git a/board/liebherr/mccmon6/Makefile b/board/liebherr/mccmon6/Makefile
new file mode 100644
index 000..e37baf8
--- /dev/null
+++ b/board/liebherr/mccmon6/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2016-2017
+# Lukasz Majewski, DENX Software Engineering, lu...@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := mccmon6.o spl.o
diff --git a/board/liebherr/mccmon6/mccmon6.c b/board/liebherr/mccmon6/mccmon6.c
new file mode 100644
index 000..eb5eae4
--- /dev/null
+++ b/board/liebherr/mccmon6/mccmon6.c
@@ -0,0 +1,490 @@
+/*
+ * Copyright (C) 2016-2017
+ * Lukasz Majewski, DENX Software Engineering, lu...@denx.de
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |  \
+   PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+   PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |   \
+   PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+   PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |  \
+   PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |\
+   PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL   (PAD_CTL_PUS_100K_UP |  \
+   PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
+   PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | 

Re: [U-Boot] [PATCH] SPL: NOR: Add CONFIG_SPL_NOR_COPY_ENTIRE_IMAGE define to enable whole image copy from NOR

[Lukasz Majewski]

Hi Marek,

> On 12/30/2016 10:28 PM, Lukasz Majewski wrote:
> > Hi Marek,
> > 
> >> On 12/29/2016 04:26 PM, Tom Rini wrote:
> >>> On Thu, Dec 29, 2016 at 12:41:06AM +0100, Marek Vasut wrote:
>  On 12/28/2016 09:52 AM, Lukasz Majewski wrote:
> > Hi Marek,
> >
> >> On 12/26/2016 05:36 PM, Lukasz Majewski wrote:
> >>> Hi Marek,
> >>>
>  On 11/29/2016 07:18 PM, Tom Rini wrote:
> > On Tue, Nov 29, 2016 at 11:50:34AM +0100, Marek Vasut wrote:
> >> On 11/29/2016 10:11 AM, Lukasz Majewski wrote:
> >>> Hi Marek,
> >>>
>  On 11/28/2016 10:09 PM, Lukasz Majewski wrote:
> > This define gives the possibility to copy entire image
> > (including header - e.g. u-boot.img) from NOR parallel
> > memory to e.g. SDRAM. The current code only supports
> > loading the raw binary image (the u-boot.bin).
> >
> > The legacy behavior is preserved, since other board
> > don't enabled this option.
> 
>  So, what's the usecase again ? ;-) 
> >>>
> >>> :-)
> >>>
> >>> The use case is to allow u-boot.img being loaded from
> >>> Parallel NOR. The current code only supports u-boot.bin.
> >>
> >> Why is u-boot.bin (or the payload) not sufficient ? Why do
> >> you need the header ?
> >
> > Well, the general use-case and code flow is that we load
> > u-boot.img (or a FIT image) and if all else fails, fall back
> > to assuming a .bin and a known address).
> >
>  And exactly how is that whole image useful in RAM ? Sorry, I
>  still do not see it, usually you just need the executable
>  payload, although even that can be left in flash most of the
>  time.
> >>>
> >>> The use case is that I do want to boot from SD card/eMMC and
> >>> NOR with using u-boot.img.
> >>>
> >>> I would like to avoid situation when for NOR I must use
> >>> u-boot.bin and for eMMC u-boot.img.
> >>>
> >>> Such approach keeps things as simple as possible :-)
> >>
> >> Oh, so it allows you to detect bitrot for the content in SPI
> >> NOR ?
> >
> > I do not use SPI NOR, it is parallel NOR.
> 
>  Sorry, I meant parallel NOR of course.
> 
> >> It's a bit strange we had to use u-boot.bin with SPL there.
> >>
> >
> > This is how the legacy system behaves. It uses (by default)
> > Parallel NOR for booting (with advised/provided NOR memory
> > timings). After doing some measurements, it turned out that for
> > "tunned" u-boot/SPL there would be the best way to copy it to
> > ram and execute it from there (just like eMMC).
> >
> > Hence, I would like to use u-boot.img in both booting scenarios.
> 
>  I think I was mistaken yesterday, I don't think I understand why
>  copying the image including the header into RAM has any benefit
>  compared to copying just the image payload to RAM (and yes, we're
>  getting back to my original question).
> >>>
> >>> Code complexity and forward compatibility?
> >>
> >> This is adding code complexity, but this is not my point.
> >>
> >>> The general case in the SPL
> >>> framework is that we have either a "legacy" image or a FIT image
> >>> and we fall back to "well, just run it!".
> >>
> >> Well, this doesn't answer my question, because if I understand this
> >> patch correctly, it copies the entire legacy image (incl. header)
> >> into RAM instead of copying just the image payload (which we
> >> already do). I don't really understand why we want to do this. Or
> >> do I misunderstand something ?
> > 
> > No, you understood everything correctly. After some thoughts, I
> > think that only payload should be copied.
> 
> But that's what we already do, no ? So what is the point of this
> patch ?

So now I do know a bit more ...

Let's start with ./common/spl/spl.c - spl_parse_image_header()

With SPL_COPY_PAYLOAD_ONLY flag set (@ common/spl/spl_nor.c) we go to:

if (spl_image->flags & SPL_COPY_PAYLOAD_ONLY) {
/*
 * On some system (e.g. powerpc), the load-address and
 * entry-point is located at address 0. We can't load
 * to 0-0x40. So skip header in this case.
 */
spl_image->load_addr = image_get_load(header);
spl_image->entry_point = image_get_ep(header);
^^^- here we set it to 0x0 by default (which
is not true for our setup - we expect to boot from 0x1780)

spl_image->size = image_get_data_size(header);
}

My patch:

1. Do not set SPL_COPY_PAYLOAD_ONLY flag, so we go to else clause,
which according to comment:
"/* Load including the header */"
and performs some address manipulation.

2. In my patch I undo those address calculations to load only payload.


Conclusion :-)
--

And most of all 

Re: [U-Boot] [PATCH 0/7] mmc: more Kconfig conversion, MMC related clean-up

[Marek Vasut]

On 01/01/2017 01:11 PM, Masahiro Yamada wrote:
> This series is based on commit 3d3a74cc8c.
> Each git-log describes how to re-generate it.
> Buildman test passed.
> 
> 
> 
> Masahiro Yamada (7):
>   socfpga: remove unused CONFIG option and cleanup README.socfpga
>   mmc: rename CONFIG_ROCKCHIP_DWMMC to CONFIG_MMC_DW_ROCKCHIP
>   mmc: move CONFIG_DWMMC to Kconfig, renaming to CONFIG_MMC_DW
>   mmc: move DesignWare-based drivers to Kconfig
>   ARM: davinci: remove unused CONFIG_DAVINCI_MMC_SD1
>   mmc: move more driver config options to Kconfig
>   sunxi: remove bare default for CONFIG_MMC

Looks fine to me,
Reviewed-by: Marek Vasut 

Thanks!


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [RFC PATCH 0/3] arm64: rk3399: enable SPL with ATF support

[Michal Simek]

Hi,

separation of rk3399 SPL from ATF SPL would be worth.

Thanks,
Michal

On 29.12.2016 11:25, Kever Yang wrote:
> 
> RK3399 SPL is not enable bacause of the lack of ATF support in SPL,
> after port some source code from ATF, I manage to enable the support for
> ATF in SPL. This patch set depends on some patch for SPL support multi
> binary in FIT which is from Andre.
> 
> The patch of sdram controller is still not clean, because I want to get
> comments from upstream.I port this driver from coreboot, and I don't
> want to make much change on it. The rk3399 dram controller has many registers
> to config, I want to make them directly used by driver instead of parse
> and copy them one by one from dts.
> 
> Another part of comment is welcome for the implementation of spl_atf.c
> and the entry in spl.c
> 
> 
> 
> Kever Yang (3):
>   arm64: rk3399: add SPL support
>   arm64: rk3399: add ddr controller driver
>   spl: add support to booting with ATF
> 
>  arch/arm/Kconfig   |1 +
>  arch/arm/dts/rk3399.dtsi   |   24 +
>  arch/arm/include/asm/arch-rockchip/grf_rk3399.h|  118 ++
>  arch/arm/include/asm/arch-rockchip/sdram_rk3399.h  |  188 +++
>  arch/arm/mach-rockchip/Kconfig |2 +
>  arch/arm/mach-rockchip/Makefile|1 +
>  arch/arm/mach-rockchip/rk3399-board-spl.c  |  157 ++
>  arch/arm/mach-rockchip/rk3399/Makefile |1 +
>  arch/arm/mach-rockchip/rk3399/sdram-lpddr3-4GB.inc | 1565 
> 
>  arch/arm/mach-rockchip/rk3399/sdram_rk3399.c   | 1121 ++
>  common/spl/Kconfig |   14 +
>  common/spl/Makefile|1 +
>  common/spl/spl.c   |4 +
>  common/spl/spl_atf.c   |   91 ++
>  configs/evb-rk3399_defconfig   |   17 +
>  drivers/clk/rockchip/clk_rk3399.c  |   42 +-
>  drivers/pinctrl/rockchip/pinctrl_rk3399.c  |  106 --
>  include/atf_common.h   |  295 
>  include/configs/rk3399_common.h|   11 +
>  include/dt-bindings/clock/rk3399-cru.h |   16 +-
>  include/spl.h  |1 +
>  21 files changed, 3663 insertions(+), 113 deletions(-)
>  create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
>  create mode 100644 arch/arm/mach-rockchip/rk3399-board-spl.c
>  create mode 100644 arch/arm/mach-rockchip/rk3399/sdram-lpddr3-4GB.inc
>  create mode 100644 arch/arm/mach-rockchip/rk3399/sdram_rk3399.c
>  create mode 100644 common/spl/spl_atf.c
>  create mode 100644 include/atf_common.h
> 

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Re: [U-Boot] [RFC PATCH 3/3] spl: add support to booting with ATF

[Michal Simek]

On 29.12.2016 11:25, Kever Yang wrote:
> ATF(ARM Trust Firmware) is used by ARM arch64 SoCs, find more infomation
> about ATF at:
> 
> SPL is consider as BL2 in ATF, it needs to load other part of ATF binary

SPL replaces BL2 in ATF

> like BL31, BL32, SCP-BL30, and BL33(U-Boot). And needs to prepare the
> parameter for BL31 which including entry and image information for all
> other images. Then the SPL handle PC to BL31 with the parameter, the
> BL31 will do the rest of work and at last get into U-Boot(BL33).

But the main question for this is how do load that images and in which
format. It means I would think that you will introduce fit format which
contain BL33(U-Boot), BL32(secure os) and BL31(ATF) and SPL will be able
to load all of them.

If you look at zynqmp I did a small trick where I consider case that
with ATF it is OS boot where kernel is ATF and dtb is full u-boot to get
it boot.

If you adopt fit format then I expect SPL will be able to remember which
part is where and based on that fill structure for ATF.
Then SPL_ATF_TEXT_BASE address is not needed because it will be read
from fit format.



> 
> Signed-off-by: Kever Yang 
> ---
> 
>  common/spl/Kconfig   |  14 +++
>  common/spl/Makefile  |   1 +
>  common/spl/spl.c |   4 +
>  common/spl/spl_atf.c |  91 
>  include/atf_common.h | 295 
> +++
>  include/spl.h|   1 +
>  6 files changed, 406 insertions(+)
>  create mode 100644 common/spl/spl_atf.c
>  create mode 100644 include/atf_common.h
> 
> diff --git a/common/spl/Kconfig b/common/spl/Kconfig
> index cba51f5..1bb4360 100644
> --- a/common/spl/Kconfig
> +++ b/common/spl/Kconfig
> @@ -577,6 +577,20 @@ config SPL_YMODEM_SUPPORT
> means of transmitting U-Boot over a serial line for using in SPL,
> with a checksum to ensure correctness.
>  
> +config SPL_ATF_SUPPORT
> + bool "Support ARM trust firmware"
> + depends on SPL
> + help
> +   ATF(ARM Trust Firmware) is component for ARM arch64 which need to
> +   load by SPL(consider as BL2 in ATF).
> +   More detail at: https://github.com/ARM-software/arm-trusted-firmware
> +
> +config SPL_ATF_TEXT_BASE
> + depends on SPL_ATF_SUPPORT
> + hex "ATF TEXT BASE addr"
> + help
> +   This is the base address in memory for ATF text and entry point.
> +
>  config TPL_ENV_SUPPORT
>   bool "Support an environment"
>   depends on TPL
> diff --git a/common/spl/Makefile b/common/spl/Makefile
> index ed02635..620ae90 100644
> --- a/common/spl/Makefile
> +++ b/common/spl/Makefile
> @@ -20,6 +20,7 @@ endif
>  obj-$(CONFIG_SPL_UBI) += spl_ubi.o
>  obj-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o
>  obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o
> +obj-$(CONFIG_SPL_ATF_SUPPORT) += spl_atf.o
>  obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o
>  obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o
>  obj-$(CONFIG_SPL_EXT_SUPPORT) += spl_ext.o
> diff --git a/common/spl/spl.c b/common/spl/spl.c
> index 1729034..7daf7bd 100644
> --- a/common/spl/spl.c
> +++ b/common/spl/spl.c
> @@ -390,6 +390,10 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
> gd->malloc_ptr / 1024);
>  #endif
>  
> +#ifdef CONFIG_SPL_ATF_SUPPORT
> + bl31_entry();
> +#endif
> +
>   debug("loaded - jumping to U-Boot...");
>   spl_board_prepare_for_boot();
>   jump_to_image_no_args(_image);
> diff --git a/common/spl/spl_atf.c b/common/spl/spl_atf.c
> new file mode 100644
> index 000..cf23b7a
> --- /dev/null
> +++ b/common/spl/spl_atf.c
> @@ -0,0 +1,91 @@
> +/*
> + * Copyright (C) 2016 Rockchip Electronic Co.,Ltd
> + * Written by Kever Yang 
> + *
> + * origin from arm-trust-firmware
> + * plat/arm/common/arm_bl2_setup.c
> + * SPDX-License-Identifier: GPL-2.0+

this is not based on gpl file that's why license should be different.


> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +static struct bl2_to_bl31_params_mem_t bl31_params_mem;
> +static struct bl31_params_t *bl2_to_bl31_params;
> +
> +/***
> + * This function assigns a pointer to the memory that the platform has kept
> + * aside to pass platform specific and trusted firmware related information
> + * to BL31. This memory is allocated by allocating memory to
> + * bl2_to_bl31_params_mem_t structure which is a superset of all the
> + * structure whose information is passed to BL31
> + * NOTE: This function should be called only once and should be done
> + * before generating params to BL31
> + 
> **/
> +struct bl31_params_t *bl2_plat_get_bl31_params(void)
> +{
> + struct entry_point_info_t *bl33_ep_info;
> +
> + /*
> +  * Initialise the memory for all the arguments that needs to
> +  * be passed to BL31
> +  */
> + memset(_params_mem, 0, sizeof(struct 

Re: [U-Boot] [PATCH 3/4] i2c: i2c-cdns: Implement workaround for hold quirk of the rev 1.0

[Michal Simek]

On 27.12.2016 23:46, Moritz Fischer wrote:
> Revision 1.0 of this IP has a quirk where if during a long read transfer
> the transfer_size register will go to 0, the master will send a NACK to
> the slave prematurely.
> The way to work around this is to reprogram the transfer_size register
> mid-transfer when the only the receive fifo is known full, i.e. the I2C
> bus is known non-active.
> The workaround is based on the implementation in the linux-kernel.
> 
> Signed-off-by: Moritz Fischer 
> Cc: Heiko Schocher 
> Cc: Michal Simek 
> Cc: u-boot@lists.denx.de
> ---
>  drivers/i2c/i2c-cdns.c | 121 
> -
>  1 file changed, 89 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
> index 9a1b520..4a46dbf 100644
> --- a/drivers/i2c/i2c-cdns.c
> +++ b/drivers/i2c/i2c-cdns.c
> @@ -17,6 +17,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -67,6 +68,8 @@ struct cdns_i2c_regs {
>  
>  #define CDNS_I2C_FIFO_DEPTH  16
>  #define CDNS_I2C_TRANSFER_SIZE_MAX   255 /* Controller transfer limit */
> +#define CDNS_I2C_TRANSFER_SIZE   (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
> +
>  #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
>  
>  #ifdef DEBUG
> @@ -247,15 +250,20 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus 
> *i2c_bus, u32 addr, u8 *data,
>  u32 len)
>  {
>   u8 *cur_data = data;
> -
>   struct cdns_i2c_regs *regs = i2c_bus->regs;
>  
> + /* Set the controller in Master transmit mode and clear FIFO */
>   setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO);
> -
> -
>   clrbits_le32(>control, CDNS_I2C_CONTROL_RW);
>  
> + /* Check message size against FIFO depth, and set hold bus bit
> +  * if it is greater than FIFO depth */
> + if (len > CDNS_I2C_FIFO_DEPTH)
> + setbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
> +
> + /* Clear the interrupts in status register */
>   writel(0xFF, >interrupt_status);
> +
>   writel(addr, >address);
>  
>   while (len--) {
> @@ -280,48 +288,98 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus 
> *i2c_bus, u32 addr, u8 *data,
>   return 0;
>  }
>  
> +static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
> +{
> + return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
> +}
> +
>  static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 
> *data,
> -   u32 len)
> +   u32 recv_count)
>  {
> - u32 status;
> - u32 i = 0;
>   u8 *cur_data = data;
> -
> - /* TODO: Fix this */
>   struct cdns_i2c_regs *regs = i2c_bus->regs;
> + int curr_recv_count;
> + int updatetx, hold_quirk;
>  
>   /* Check the hardware can handle the requested bytes */
> - if ((len < 0))
> + if ((recv_count < 0))
>   return -EINVAL;
>  
> + curr_recv_count = recv_count;
> +
> + /* Check for the message size against the FIFO depth */
> + if (recv_count > CDNS_I2C_FIFO_DEPTH)
> + setbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
> +
>   setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
>   CDNS_I2C_CONTROL_RW);
>  
> + if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
> + curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
> + writel(curr_recv_count, >transfer_size);
> + } else {
> + writel(recv_count, >transfer_size);
> + }
> +
>   /* Start reading data */
>   writel(addr, >address);
> - writel(len, >transfer_size);
> -
> - /* Wait for data */
> - do {
> - status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
> - CDNS_I2C_INTERRUPT_DATA);
> - if (!status) {
> - /* Release the bus */
> - clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
> - return -ETIMEDOUT;
> +
> + updatetx = recv_count > curr_recv_count;
> +
> + hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
> +
> + while (recv_count) {
> + while (readl(>status) & CDNS_I2C_STATUS_RXDV) {
> + if (recv_count < CDNS_I2C_FIFO_DEPTH &&
> + !i2c_bus->hold_flag) {
> + clrbits_le32(>control,
> +  CDNS_I2C_CONTROL_HOLD);
> + }
> + *(cur_data)++ = readl(>data);
> + recv_count--;
> + curr_recv_count--;
> +
> + if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
> + break;
>   }
> - debug("Read %d bytes\n",
> -   len - readl(>transfer_size));
> - for (; i < len - readl(>transfer_size); i++)
> -   

Re: [U-Boot] [PATCH 1/4] i2c: i2c-cdns: Detect unsupported sequences for rev 1.0

[Michal Simek]

+Siva: please test it.

On 27.12.2016 23:46, Moritz Fischer wrote:
> Revision 1.0 of this IP has a couple of issues, such as not supporting
> repeated start conditions for read transfers.
> 
> So scan through the list of i2c messages for these conditions
> and report an error if they are attempted.
> 
> This has been fixed for revision 1.4 of the IP, so only report the error
> when the IP can really not do it.
> 
> Signed-off-by: Moritz Fischer 
> Cc: Heiko Schocher 
> Cc: Michal Simek 
> Cc: u-boot@lists.denx.de
> ---
>  drivers/i2c/i2c-cdns.c | 69 
> --
>  1 file changed, 55 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
> index f49f60b..c69e7e8 100644
> --- a/drivers/i2c/i2c-cdns.c
> +++ b/drivers/i2c/i2c-cdns.c
> @@ -67,6 +67,7 @@ struct cdns_i2c_regs {
>  
>  #define CDNS_I2C_FIFO_DEPTH  16
>  #define CDNS_I2C_TRANSFER_SIZE_MAX   255 /* Controller transfer limit */
> +#define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
>  
>  #ifdef DEBUG
>  static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
> @@ -114,6 +115,13 @@ struct i2c_cdns_bus {
>   int id;
>   unsigned int input_freq;
>   struct cdns_i2c_regs __iomem *regs; /* register base */
> +

no reason.

> + int hold_flag;
> + u32 quirks;
> +};
> +
> +struct cdns_i2c_platform_data {
> + u32 quirks;
>  };
>  
>  /* Wait for an interrupt */
> @@ -236,18 +244,14 @@ static int cdns_i2c_probe_chip(struct udevice *bus, 
> uint chip_addr,
>  }
>  
>  static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 
> *data,
> -u32 len, bool next_is_read)
> +u32 len)
>  {
>   u8 *cur_data = data;
>  
>   struct cdns_i2c_regs *regs = i2c_bus->regs;
>  
> - setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
> - CDNS_I2C_CONTROL_HOLD);
> + setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO);
>  
> - /* if next is a read, we need to clear HOLD, doesn't work */
> - if (next_is_read)
> - clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
>  

two blank line after removing this code.

>   clrbits_le32(>control, CDNS_I2C_CONTROL_RW);
>  
> @@ -267,7 +271,9 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus 
> *i2c_bus, u32 addr, u8 *data,
>   }
>  
>   /* All done... release the bus */
> - clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
> + if (!i2c_bus->hold_flag)
> + clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
> +
>   /* Wait for the address and data to be sent */
>   if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
>   return -ETIMEDOUT;
> @@ -285,7 +291,7 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus 
> *i2c_bus, u32 addr, u8 *data,
>   struct cdns_i2c_regs *regs = i2c_bus->regs;
>  
>   /* Check the hardware can handle the requested bytes */
> - if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX))
> + if ((len < 0))
>   return -EINVAL;
>  
>   setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
> @@ -310,7 +316,8 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus 
> *i2c_bus, u32 addr, u8 *data,
>   *(cur_data++) = readl(>data);
>   } while (readl(>transfer_size) != 0);
>   /* All done... release the bus */
> - clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
> + if (!i2c_bus->hold_flag)
> + clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
>  
>  #ifdef DEBUG
>   cdns_i2c_debug_status(regs);
> @@ -322,19 +329,43 @@ static int cdns_i2c_xfer(struct udevice *dev, struct 
> i2c_msg *msg,
>int nmsgs)
>  {
>   struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
> - int ret;
> + int ret, count;
> + bool hold_quirk;
> +
> +

ditto.

> + printf("i2c_xfer: %d messages\n", nmsgs);

debug?


> + hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
> +
> + if (nmsgs > 1) {
> + /*
> +  * This controller does not give completion interrupt after a
> +  * master receive message if HOLD bit is set (repeated start),
> +  * resulting in SW timeout. Hence, if a receive message is
> +  * followed by any other message, an error is returned
> +  * indicating that this sequence is not supported.
> +  */
> + for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
> + if (msg[count].flags & I2C_M_RD) {
> + printf("Can't do repeated start after a receive 
> message\n");
> + return -EOPNOTSUPP;
> + }
> + }
> +
> + i2c_bus->hold_flag = 1;
> + setbits_le32(_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
> + } else {
> + i2c_bus->hold_flag = 0;

Re: [U-Boot] [PATCH 4/4] i2c: i2c-cdns: No need for dedicated probe function

[Michal Simek]

Hi, +Siva

do you know why this was done in this way? I know I was playing with
similar patch and using xfer function but can't remember why it was
failing.

Thanks,
Michal

On 27.12.2016 23:46, Moritz Fischer wrote:
> The generic probe code in dm works, so get rid of the leftover cruft.
> 
> Signed-off-by: Moritz Fischer 
> Cc: Heiko Schocher 
> Cc: Michal Simek 
> Cc: u-boot@lists.denx.de
> ---
>  drivers/i2c/i2c-cdns.c | 21 -
>  1 file changed, 21 deletions(-)
> 
> diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
> index 4a46dbf..cd5cce0 100644
> --- a/drivers/i2c/i2c-cdns.c
> +++ b/drivers/i2c/i2c-cdns.c
> @@ -226,26 +226,6 @@ static int cdns_i2c_set_bus_speed(struct udevice *dev, 
> unsigned int speed)
>   return 0;
>  }
>  
> -/* Probe to see if a chip is present. */
> -static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr,
> - uint chip_flags)
> -{
> - struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus);
> - struct cdns_i2c_regs *regs = i2c_bus->regs;
> -
> - /* Attempt to read a byte */
> - setbits_le32(>control, CDNS_I2C_CONTROL_CLR_FIFO |
> - CDNS_I2C_CONTROL_RW);
> - clrbits_le32(>control, CDNS_I2C_CONTROL_HOLD);
> - writel(0xFF, >interrupt_status);
> - writel(chip_addr, >address);
> - writel(1, >transfer_size);
> -
> - return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
> - CDNS_I2C_INTERRUPT_NACK) &
> - CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
> -}
> -
>  static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 
> *data,
>  u32 len)
>  {
> @@ -453,7 +433,6 @@ static int cdns_i2c_ofdata_to_platdata(struct udevice 
> *dev)
>  
>  static const struct dm_i2c_ops cdns_i2c_ops = {
>   .xfer = cdns_i2c_xfer,
> - .probe_chip = cdns_i2c_probe_chip,
>   .set_bus_speed = cdns_i2c_set_bus_speed,
>  };
>  
> 

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Re: [U-Boot] [PATCH] i2c: mux: Allow muxes to work as children of i2c bus without i2c-parent

[Michal Simek]

On 29.12.2016 23:50, Moritz Fischer wrote:
> For mux check if the parent is already a device of UCLASS_I2C and if yes
> just use that. Otherwise see if someone specified an i2c-parent phandle.
> This mimics the behavior found in the Kernel, as it removes the
> requirement to explicitly specify a i2c-parent phandle.
> 
> Signed-off-by: Moritz Fischer 
> Cc: Heiko Schocher 
> Cc: Bin Meng 
> Cc: Simon Glass 
> Cc: Michal Simek 
> Cc: u-boot@lists.denx.de
> ---
>  drivers/i2c/muxes/i2c-mux-uclass.c | 9 +
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/i2c/muxes/i2c-mux-uclass.c 
> b/drivers/i2c/muxes/i2c-mux-uclass.c
> index 7a698b6..e01b773 100644
> --- a/drivers/i2c/muxes/i2c-mux-uclass.c
> +++ b/drivers/i2c/muxes/i2c-mux-uclass.c
> @@ -86,6 +86,15 @@ static int i2c_mux_post_probe(struct udevice *mux)
>   debug("%s: %s\n", __func__, mux->name);
>   priv->selected = -1;
>  
> + /* if parent is of i2c uclass already, we'll take that, otherwise
> +  * look if we find an i2c-parent phandle */

Incorrect comment style.

> + if (UCLASS_I2C == device_get_uclass_id(mux->parent)) {
> + priv->i2c_bus = dev_get_parent(mux);
> + debug("%s: bus=%p/%s\n", __func__, priv->i2c_bus,
> +   priv->i2c_bus->name);
> + return 0;
> + }
> +
>   ret = uclass_get_device_by_phandle(UCLASS_I2C, mux, "i2c-parent",
>  >i2c_bus);
>   if (ret)
> 

The part of this will be good to also handle
req_seq for mux busses. But at least this should solved part of the
problems.

Thanks,
Michal
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Re: [U-Boot] [PATCH v2 3/4] mmc: zynq: Determine base clock frequency via clock framework

[Michal Simek]

On 2.1.2017 15:02, Stefan Herbrechtsmeier wrote:
> Hi Michal,
> 
> Am 02.01.2017 um 08:00 schrieb Michal Simek:
>> Hi,
>>
>> On 27.12.2016 11:10, Stefan Herbrechtsmeier wrote:
>>> Hi Michal,
>>>
>>> Am 28.11.2016 um 08:42 schrieb Michal Simek:
 Hi, +Siva,
>>> 
>>>
 Moving current zynq clk driver to driver model shouldn't be that hard
 because all should be in place. and then you can keep just that
 if defined(CONFIG_CLK) part above.
>>> I have port the CLK driver to DM but therefore I have to rework it and
>>> remove the clk cmd support. I will post a tested version next week.
>> ok. I want to know the reason why this is necessary.
> The zynq clock driver save all data even the static clock tree and
> unused information in an dynamic array. This needs much memory and
> complicates the strip down for the SPL.

For SPL this should be out for sure - there is no reason to have this there.

> 
> The clock framework doesn't support the clock command nor supplies the
> names of clocks. If you prefer I could add the clock command
> implementation to the DM zynq driver or keep clock driver specific data
> in the mach directory.

We have added that clk command and it should stay there. Definitely
there could be new subcommands added in connection to DM but that can be
solved separately.

> Should I move everything in one patch or should I first remove some
> function, move the clock driver and add functionality back?

For all these conversions it should be done in 3 steps.

1. Add ifdef CONFIG_CLK
#else
#endif

2. Move drivers and enable CONFIG_CLK by default

3. Remove !CONFIG_CLK part.


I expect your patches will do ad 1). And you move mmc driver which is
part ad 2). And then we can check what else is necessary to move (We
have moved gem recently for zynqmp). And step 3 should be done when all
drivers are moved.

Thanks,
Michal
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Re: [U-Boot] [PATCH v2 3/4] mmc: zynq: Determine base clock frequency via clock framework

[Stefan Herbrechtsmeier]

Hi Michal,

Am 02.01.2017 um 08:00 schrieb Michal Simek:

Hi,

On 27.12.2016 11:10, Stefan Herbrechtsmeier wrote:

Hi Michal,

Am 28.11.2016 um 08:42 schrieb Michal Simek:

Hi, +Siva,




Moving current zynq clk driver to driver model shouldn't be that hard
because all should be in place. and then you can keep just that
if defined(CONFIG_CLK) part above.

I have port the CLK driver to DM but therefore I have to rework it and
remove the clk cmd support. I will post a tested version next week.

ok. I want to know the reason why this is necessary.
The zynq clock driver save all data even the static clock tree and 
unused information in an dynamic array. This needs much memory and 
complicates the strip down for the SPL.


The clock framework doesn't support the clock command nor supplies the 
names of clocks. If you prefer I could add the clock command 
implementation to the DM zynq driver or keep clock driver specific data 
in the mach directory.


Should I move everything in one patch or should I first remove some 
function, move the clock driver and add functionality back?


Regards
  Stefan

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Re: [U-Boot] [PATCH 2/4] i2c: i2c-cdns: Reorder timeout loop for interrupt waiting

[Michal Simek]

On 27.12.2016 23:46, Moritz Fischer wrote:
> Reorder the timeout loop such that we first check if the
> condition is already true, and then call udelay() so if
> the condition is already true, break early.
> 
> Signed-off-by: Moritz Fischer 
> Cc: Heiko Schocher 
> Cc: Michal Simek 
> Cc: u-boot@lists.denx.de
> ---
>  drivers/i2c/i2c-cdns.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
> index c69e7e8..9a1b520 100644
> --- a/drivers/i2c/i2c-cdns.c
> +++ b/drivers/i2c/i2c-cdns.c
> @@ -130,10 +130,10 @@ static u32 cdns_i2c_wait(struct cdns_i2c_regs 
> *cdns_i2c, u32 mask)
>   int timeout, int_status;
>  
>   for (timeout = 0; timeout < 100; timeout++) {
> - udelay(100);
>   int_status = readl(_i2c->interrupt_status);
>   if (int_status & mask)
>   break;
> + udelay(100);
>   }
>  
>   /* Clear interrupt status flags */
> 

Reviewed-by: Michal Simek 

Thanks,
Michal
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[U-Boot] some questions about u-boot's driver model

[Robert P. J. Day]

  i'm currently trying to wrap my head around the aspects of
converting the various u-boot subsystems to use the driver model, and
i'll do this in a number of posts so as to not have one monstrously
large post, and i'm sure i will have some truly dumb questions, so
apologies beforehand for those.

  i'm working off this page as a starting point:

http://www.denx.de/wiki/U-Boot/DriverModel

and pawing through the code base to try to understand the big picture,
so first question.

  i can see that general driver model support is defined in
drivers/core/Kconfig:

  menu "Generic Driver Options"

  config DM
bool "Enable Driver Model"
help
  This config option enables Driver Model. This brings in the core
  support, including scanning of platform data on start-up. If
  CONFIG_OF_CONTROL is enabled, the device tree will be scanned also
  when available.

(side note about that file: seems like a lot of Kbuild entries in that
file contain the line "depends on DM", when it looks like one could
just wrap a large part of that file in a single "if DM" testi to
simplify things. but ... onward.)

  i initially thought driver model support was included by one having
to specifically select that option, until i saw all the "select DM"
Kbuild lines scattered throughout the code base that explicitly
selected that option based on architecture or target board.

  for instance, here's some snippets from arch/Kconfig (irrelevant
lines removed):

  config NIOS2
bool "Nios II architecture"
select SUPPORT_OF_CONTROL
select OF_CONTROL
select DM
select CPU

  config SANDBOX
bool "Sandbox"
select SUPPORT_OF_CONTROL
select DM
select DM_KEYBOARD
select DM_SPI_FLASH
select DM_SERIAL
select DM_I2C
select DM_SPI
select DM_GPIO
select DM_MMC

  config X86
bool "x86 architecture"
select CREATE_ARCH_SYMLINK
select HAVE_PRIVATE_LIBGCC
select SUPPORT_OF_CONTROL
select DM
select DM_KEYBOARD
select DM_SERIAL
select DM_GPIO
select DM_SPI
select DM_SPI_FLASH

so i can see that a variety of driver model support is selected either
at the architecture level, in some cases including driver model
support for particular subsystems, or if not at the architecture
level:

  config ARM
bool "ARM architecture"
select CREATE_ARCH_SYMLINK
select HAVE_PRIVATE_LIBGCC if !ARM64
select SUPPORT_OF_CONTROL

then possibly at the CPU or board level:

  arch/arm/Kconfig:

  config ARCH_MVEBU
bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
select OF_CONTROL
select OF_SEPARATE
select DM
select DM_ETH
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH

or:

  arch/arm/mach-litesom/Kconfig:

  config LITESOM
bool
select MX6UL
select DM
select DM_THERMAL
select SUPPORT_SPL

so what is the general workflow for adding/selecting driver model
support? seems like it can be selected/defined at a number of levels:

  * entire architecture
  * CPU
  * target board

is there a recipe for how driver model is slowly added to u-boot,
based on updating Kconfig files for the above?

  more questions coming as i keep reading ...

rday

-- 


Robert P. J. Day Ottawa, Ontario, CANADA
http://crashcourse.ca

Twitter:   http://twitter.com/rpjday
LinkedIn:   http://ca.linkedin.com/in/rpjday


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Re: [U-Boot] [PATCH 2/2] ARM64: zynqmp: Fix i2c node's compatible string

[Michal Simek]

On 22.12.2016 18:36, Moritz Fischer wrote:
> The Zynq Ultrascale MP uses version 1.4 of the Cadence IP core
> which fixes some silicon bugs that needed software workarounds
> in Version 1.0 that was used on Zynq systems.
> 
> Signed-off-by: Moritz Fischer 
> Cc: Michal Simek 
> Cc: Heiko Schocher 
> ---
>  arch/arm/dts/zynqmp.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
> index ab5c243..20c5efc 100644
> --- a/arch/arm/dts/zynqmp.dtsi
> +++ b/arch/arm/dts/zynqmp.dtsi
> @@ -619,7 +619,7 @@
>   };
>  
>   i2c0: i2c@ff02 {
> - compatible = "cdns,i2c-r1p10";
> + compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
>   status = "disabled";
>   interrupt-parent = <>;
>   interrupts = <0 17 4>;
> @@ -630,7 +630,7 @@
>   };
>  
>   i2c1: i2c@ff03 {
> - compatible = "cdns,i2c-r1p10";
> + compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
>   status = "disabled";
>   interrupt-parent = <>;
>   interrupts = <0 18 4>;
> 


Applied both.

Thanks,
Michal
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[U-Boot] [PATCH v4 25/26] sunxi: introduce RMR switch to enter payloads in 64-bit mode

[Andre Przywara]

The ARMv8 capable Allwinner A64 SoC comes out of reset in AArch32 mode.
To run AArch64 code, we have to trigger a warm reset via the RMR register,
which proceeds with code execution at the address stored in the RVBAR
register.
If the bootable payload in the FIT image is using a different
architecture than the SPL has been compiled for, enter it via this said
RMR switch mechanism, by writing the entry point address into the MMIO
mapped, writable version of the RVBAR register.
Then the warm reset is triggered via a system register write.
If the payload architecture is the same as the SPL, we use the normal
branch as usual.

Signed-off-by: Andre Przywara 
Acked-by: Maxime Ripard 
---
 arch/arm/mach-sunxi/Makefile |  1 +
 arch/arm/mach-sunxi/spl_switch.c | 81 
 2 files changed, 82 insertions(+)
 create mode 100644 arch/arm/mach-sunxi/spl_switch.c

diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 7daba11..128091e 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -51,4 +51,5 @@ obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o
 obj-$(CONFIG_MACH_SUN8I_H3)+= dram_sun8i_h3.o
 obj-$(CONFIG_MACH_SUN9I)   += dram_sun9i.o
 obj-$(CONFIG_MACH_SUN50I)  += dram_sun8i_h3.o
+obj-$(CONFIG_MACH_SUN50I)  += spl_switch.o
 endif
diff --git a/arch/arm/mach-sunxi/spl_switch.c b/arch/arm/mach-sunxi/spl_switch.c
new file mode 100644
index 000..855379e
--- /dev/null
+++ b/arch/arm/mach-sunxi/spl_switch.c
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2016 ARM Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+
+#include 
+#include 
+
+static void __noreturn jump_to_image_native(struct spl_image_info *spl_image)
+{
+   typedef void __noreturn (*image_entry_noargs_t)(void);
+
+   image_entry_noargs_t image_entry =
+   (image_entry_noargs_t)spl_image->entry_point;
+
+   image_entry();
+}
+
+/*
+ * Do a warm-reset via the RMR register to enter the processor in a different
+ * execution mode. This allows to switch from AArch32 to AArch64 and vice
+ * versa. Execution starts at the address hold in the RVBAR register, which
+ * needs to be set before.
+ */
+static void __noreturn reset_rmr_switch(void)
+{
+#ifdef CONFIG_ARM64
+   __asm__ volatile ( "mrs  x0, RMR_EL3\n\t"
+  "bic  x0, x0, #1\n\t"   /* Clear enter-in-64 bit */
+  "orr  x0, x0, #2\n\t"   /* set reset request bit */
+  "msr  RMR_EL3, x0\n\t"
+  "isb  sy\n\t"
+  "nop\n\t"
+  "wfi\n\t"
+  "b.\n"
+  ::: "x0");
+#else
+   __asm__ volatile ( "mrc  15, 0, r0, cr12, cr0, 2\n\t"
+  "orr  r0, r0, #3\n\t"   /* request reset in 64 bit */
+  "mcr  15, 0, r0, cr12, cr0, 2\n\t"
+  "isb\n\t"
+  "nop\n\t"
+  "wfi\n\t"
+  "b.\n"
+  ::: "r0");
+#endif
+   while (1);  /* to avoid a compiler warning about __noreturn */
+}
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+   if (spl_image->arch == IH_ARCH_DEFAULT) {
+   /*
+* If the image to be executed is using the same architecture
+* as we are currently running in, just branch to the target
+* address.
+*/
+   debug("entering by branch\n");
+   jump_to_image_native(spl_image);
+   } else {
+   /*
+* If the target architecture and the current one differ, use
+* the RMR routine to change it.
+*/
+   debug("entering by RMR switch\n");
+   /*
+* The start address at which execution continues after the
+* RMR switch is held in the RVBAR system register, which is
+* architecturally read-only.
+* Allwinner provides a writeable alias in MMIO space for it.
+*/
+   writel(spl_image->entry_point, 0x17000a0);
+   DSB;
+   ISB;
+   reset_rmr_switch();
+   }
+}
-- 
2.8.2

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[U-Boot] [PATCH v4 26/26] sunxi: A64: add 32-bit SPL support

[Andre Przywara]

When compiling the SPL for the Allwinner A64 in AArch64 mode, we can't
use the more compact Thumb2 encoding, which only exists for AArch32
code. This makes the SPL rather big, up to a point where any code
additions or even a different compiler may easily exceed the 32KB limit
that the Allwinner BROM imposes.
Introduce a separate, mostly generic sun50i-a64 configuration, which
defines the CPU_V7 symbol and thus will create a 32-bit binary using
the memory-saving Thumb2 encoding.
This should only be used for the SPL, the U-Boot proper should still be
using the existing 64-bit configuration. The SPL code can switch to
AArch64 if needed, so a 32-bit SPL can be combined with a 64-bit U-Boot
proper to eventually launch arm64 kernels.

Signed-off-by: Andre Przywara 
---
 board/sunxi/Kconfig| 14 --
 configs/pine64_plus_defconfig  |  2 +-
 configs/sun50i_spl32_defconfig | 10 ++
 3 files changed, 23 insertions(+), 3 deletions(-)
 create mode 100644 configs/sun50i_spl32_defconfig

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 0001133..0d77c3a 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -43,6 +43,10 @@ config SUNXI_GEN_SUN6I
watchdog, etc.
 
 
+config MACH_SUN50I
+   bool
+   select SUNXI_GEN_SUN6I
+
 choice
prompt "Sunxi SoC Variant"
optional
@@ -121,10 +125,16 @@ config MACH_SUN9I
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
 
-config MACH_SUN50I
+config MACH_SUN50I_64
bool "sun50i (Allwinner A64)"
+   select MACH_SUN50I
select ARM64
-   select SUNXI_GEN_SUN6I
+   select SUPPORT_SPL
+
+config MACH_SUN50I_32
+   bool "sun50i (Allwinner A64) SPL-32bit"
+   select MACH_SUN50I
+   select CPU_V7
select SUPPORT_SPL
 
 endchoice
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 2374170..a76f66a 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN50I=y
+CONFIG_MACH_SUN50I_64=y
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_CONSOLE_MUX=y
diff --git a/configs/sun50i_spl32_defconfig b/configs/sun50i_spl32_defconfig
new file mode 100644
index 000..29c6a47
--- /dev/null
+++ b/configs/sun50i_spl32_defconfig
@@ -0,0 +1,10 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I_32=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
+CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-- 
2.8.2

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[U-Boot] [PATCH v4 24/26] ARM: SPL/FIT: differentiate between arm and arm64 arch properties

[Andre Przywara]

Since the SPL FIT loader can now differentiate between different
architectures, teach it how to tell arm and arm64 apart when a FIT
image is used.
We just support those two for now, as these are so far the only sensible
alternatives.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
---
 arch/arm/lib/spl.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c
index e606d47..45d285c 100644
--- a/arch/arm/lib/spl.c
+++ b/arch/arm/lib/spl.c
@@ -63,3 +63,18 @@ void __noreturn jump_to_image_linux(struct spl_image_info 
*spl_image, void *arg)
image_entry(0, machid, arg);
 }
 #endif
+
+/* This overwrites the weak definition in spl_fit.c */
+u8 spl_genimg_get_arch_id(const char *arch_str)
+{
+   if (!arch_str)
+   return IH_ARCH_DEFAULT;
+
+   if (!strcmp(arch_str, "arm"))
+   return IH_ARCH_ARM;
+
+   if (!strcmp(arch_str, "arm64"))
+   return IH_ARCH_ARM64;
+
+   return IH_ARCH_DEFAULT;
+}
-- 
2.8.2

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[U-Boot] [PATCH v4 19/26] sunxi: H3/A64: fix non-ODT setting

[Andre Przywara]

According to Jens disabling the on-die-termination should set bit 5,
not bit 1 in the respective register. Fix this.

Reported-by: Jens Kuske 
Signed-off-by: Andre Przywara 
---
 arch/arm/mach-sunxi/dram_sun8i_h3.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c 
b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index fe9cf9a..1311eda 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -414,6 +414,11 @@ static void mctl_sys_init(uint16_t socid, struct dram_para 
*para)
udelay(500);
 }
 
+/* These are more guessed based on some Allwinner code. */
+#define DX_GCR_ODT_DYNAMIC (0x0 << 4)
+#define DX_GCR_ODT_ALWAYS_ON   (0x1 << 4)
+#define DX_GCR_ODT_OFF (0x2 << 4)
+
 static int mctl_channel_init(uint16_t socid, struct dram_para *para)
 {
struct sunxi_mctl_com_reg * const mctl_com =
@@ -443,7 +448,8 @@ static int mctl_channel_init(uint16_t socid, struct 
dram_para *para)
clrsetbits_le32(_ctl->dx[i].gcr, (0x3 << 4) |
(0x1 << 1) | (0x3 << 2) | (0x3 << 12) |
(0x3 << 14),
-   IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2);
+   IS_ENABLED(CONFIG_DRAM_ODT_EN) ?
+   DX_GCR_ODT_DYNAMIC : DX_GCR_ODT_OFF);
 
/* AC PDR should always ON */
setbits_le32(_ctl->aciocr, 0x1 << 1);
-- 
2.8.2

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[U-Boot] [PATCH v4 21/26] sunxi: A64: enable SPL

[Andre Przywara]

Now that the SPL is ready to be compiled in AArch64 and the DRAM
init code is ready, enable SPL support for the A64 SoC and in the
Pine64 defconfig.
For now we keep the boot0 header in the U-Boot proper, as this allows
to still use boot0 as an SPL replacement without hurting the SPL use
case.
We disable FEL support for now by making its compilation conditional
and disabling it for ARM64, as the code isn't ready yet.

Signed-off-by: Andre Przywara 
Acked-by: Maxime Ripard 
Reviewed-by: Simon Glass 
---
 arch/arm/mach-sunxi/board.c| 2 +-
 board/sunxi/Kconfig| 2 ++
 configs/pine64_plus_defconfig  | 1 +
 include/configs/sunxi-common.h | 2 ++
 4 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index aa11493..52be5b0 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -133,7 +133,7 @@ static int gpio_init(void)
return 0;
 }
 
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
 static int spl_board_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
 {
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index c2eb85e..0001133 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -125,6 +125,7 @@ config MACH_SUN50I
bool "sun50i (Allwinner A64)"
select ARM64
select SUNXI_GEN_SUN6I
+   select SUPPORT_SPL
 
 endchoice
 
@@ -196,6 +197,7 @@ config DRAM_ODT_EN
bool "sunxi dram odt enable"
default n if !MACH_SUN8I_A23
default y if MACH_SUN8I_A23
+   default y if MACH_SUN50I
---help---
Select this to enable dram odt (on die termination).
 
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index ebc24b8..2374170 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN50I=y
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_CONSOLE_MUX=y
+CONFIG_SPL=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index e05c318..ab2d33f 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -183,7 +183,9 @@
 
 #define CONFIG_SPL_FRAMEWORK
 
+#ifndef CONFIG_ARM64   /* AArch64 FEL support is not ready yet */
 #define CONFIG_SPL_BOARD_LOAD_IMAGE
+#endif
 
 #if defined(CONFIG_MACH_SUN9I)
 #define CONFIG_SPL_TEXT_BASE   0x10040 /* sram start+header */
-- 
2.8.2

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[U-Boot] [PATCH v4 20/26] sunxi: DRAM: fix H3 DRAM size display on aarch64

[Andre Przywara]

Fix the output of the DRAM size on AArch64 SPLs.

Signed-off-by: Andre Przywara 
Reviewed-by: Alexander Graf 
Reviewed-by: Simon Glass 
Acked-by: Maxime Ripard 
---
 arch/arm/mach-sunxi/dram_sun8i_h3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c 
b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index 1311eda..9f7cc7f 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -664,6 +664,6 @@ unsigned long sunxi_dram_init(void)
mctl_auto_detect_dram_size();
mctl_set_cr();
 
-   return (1 << (para.row_bits + 3)) * para.page_size *
+   return (1UL << (para.row_bits + 3)) * para.page_size *
(para.dual_rank ? 2 : 1);
 }
-- 
2.8.2

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[U-Boot] [PATCH v4 23/26] Makefile: use "arm64" architecture for U-Boot image files

[Andre Przywara]

At the moment we use the arch/arm directory for arm64 boards as well,
so the Makefile will pick up the "arm" name for the architecture to use
for tagging binaries in U-Boot image files.
Differentiate between the two by looking at the CPU variable being defined
to "armv8", and use the arm64 architecture name on creating the image
file if that matches.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
---
 Makefile | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index 0874964..bae1256 100644
--- a/Makefile
+++ b/Makefile
@@ -929,13 +929,18 @@ quiet_cmd_cpp_cfg = CFG $@
 cmd_cpp_cfg = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \
-DDO_DEPS_ONLY -D__ASSEMBLY__ -x assembler-with-cpp -P -dM -E -o $@ $<
 
+ifeq ($(CPU),armv8)
+IH_ARCH := arm64
+else
+IH_ARCH := $(ARCH)
+endif
 ifdef CONFIG_SPL_LOAD_FIT
-MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
+MKIMAGEFLAGS_u-boot.img = -f auto -A $(IH_ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
 else
-MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
+MKIMAGEFLAGS_u-boot.img = -A $(IH_ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
 endif
-- 
2.8.2

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[U-Boot] [PATCH v4 18/26] sunxi: A64: use H3 DRAM initialization code for A64 as well

[Andre Przywara]

From: Jens Kuske 

The A64 DRAM controller is very similar to the H3 one,
so the code can be reused with some small changes.
This refactoring does not change the code size for the existing H3 part.

[Andre: rework from #ifdefs to using socid parameters in static
functions, minor fixes, merging in fixes from Jens]

Signed-off-by: Jens Kuske 
Signed-off-by: Andre Przywara 
Acked-by: Maxime Ripard 
---
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h   |   1 +
 arch/arm/include/asm/arch-sunxi/cpu.h   |   3 +
 arch/arm/include/asm/arch-sunxi/dram.h  |   2 +-
 arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h |  10 +-
 arch/arm/mach-sunxi/Makefile|   1 +
 arch/arm/mach-sunxi/clock_sun6i.c   |   2 +-
 arch/arm/mach-sunxi/dram_sun8i_h3.c | 211 ++--
 7 files changed, 174 insertions(+), 56 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index be9fcfd..3f87672 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -322,6 +322,7 @@ struct sunxi_ccm_reg {
 #define CCM_DRAMCLK_CFG_DIV0_MASK  (0xf << 8)
 #define CCM_DRAMCLK_CFG_SRC_PLL5   (0x0 << 20)
 #define CCM_DRAMCLK_CFG_SRC_PLL6x2 (0x1 << 20)
+#define CCM_DRAMCLK_CFG_SRC_PLL11  (0x1 << 20) /* A64 only */
 #define CCM_DRAMCLK_CFG_SRC_MASK   (0x3 << 20)
 #define CCM_DRAMCLK_CFG_UPD(0x1 << 16)
 #define CCM_DRAMCLK_CFG_RST(0x1 << 31)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h 
b/arch/arm/include/asm/arch-sunxi/cpu.h
index 73583ed..6f96a97 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -13,4 +13,7 @@
 #include 
 #endif
 
+#define SOCID_A64  0x1689
+#define SOCID_H3   0x1680
+
 #endif /* _SUNXI_CPU_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h 
b/arch/arm/include/asm/arch-sunxi/dram.h
index e0be744..53e6d47 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -24,7 +24,7 @@
 #include 
 #elif defined(CONFIG_MACH_SUN8I_A83T)
 #include 
-#elif defined(CONFIG_MACH_SUN8I_H3)
+#elif defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
 #include 
 #elif defined(CONFIG_MACH_SUN9I)
 #include 
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h 
b/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
index 346538c..25d07d9 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
@@ -15,7 +15,8 @@
 
 struct sunxi_mctl_com_reg {
u32 cr; /* 0x00 control register */
-   u8 res0[0xc];   /* 0x04 */
+   u8 res0[0x8];   /* 0x04 */
+   u32 tmr;/* 0x0c (unused on H3) */
u32 mcr[16][2]; /* 0x10 */
u32 bwcr;   /* 0x90 bandwidth control register */
u32 maer;   /* 0x94 master enable register */
@@ -32,7 +33,9 @@ struct sunxi_mctl_com_reg {
u32 swoffr; /* 0xc4 */
u8 res2[0x8];   /* 0xc8 */
u32 cccr;   /* 0xd0 */
-   u8 res3[0x72c]; /* 0xd4 */
+   u8 res3[0x54];  /* 0xd4 */
+   u32 mdfs_bwlr[3];   /* 0x128 (unused on H3) */
+   u8 res4[0x6cc]; /* 0x134 */
u32 protect;/* 0x800 */
 };
 
@@ -81,7 +84,8 @@ struct sunxi_mctl_ctl_reg {
u32 rfshtmg;/* 0x90 refresh timing */
u32 rfshctl1;   /* 0x94 */
u32 pwrtmg; /* 0x98 */
-   u8  res3[0x20]; /* 0x9c */
+   u8 res3[0x1c];  /* 0x9c */
+   u32 vtfcr;  /* 0xb8 (unused on H3) */
u32 dqsgmr; /* 0xbc */
u32 dtcr;   /* 0xc0 */
u32 dtar[4];/* 0xc4 */
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index e73114e..7daba11 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -50,4 +50,5 @@ obj-$(CONFIG_MACH_SUN8I_A33)  += dram_sun8i_a33.o
 obj-$(CONFIG_MACH_SUN8I_A83T)  += dram_sun8i_a83t.o
 obj-$(CONFIG_MACH_SUN8I_H3)+= dram_sun8i_h3.o
 obj-$(CONFIG_MACH_SUN9I)   += dram_sun9i.o
+obj-$(CONFIG_MACH_SUN50I)  += dram_sun8i_h3.o
 endif
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c 
b/arch/arm/mach-sunxi/clock_sun6i.c
index 8e39bbe..d123b3a 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -217,7 +217,7 @@ done:
 }
 #endif
 
-#ifdef CONFIG_MACH_SUN8I_A33
+#if defined(CONFIG_MACH_SUN8I_A33) || defined(CONFIG_MACH_SUN50I)
 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
 {
struct sunxi_ccm_reg * const ccm =
diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c 
b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index 

[U-Boot] [PATCH v4 22/26] SPL: read and store arch property from U-Boot image

[Andre Przywara]

Read the specified "arch" value from a legacy or FIT U-Boot image and
store it in our SPL data structure.
This allows loaders to take the target architecture in account for
custom loading procedures.
Having the complete string -> arch mapping for FIT based images in the
SPL would be too big, so we leave it up to architectures (or boards) to
overwrite the weak function that does the actual translation, possibly
covering only the required subset there.
Document struct spl_image_info on the way.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
---
 common/spl/spl.c |  1 +
 common/spl/spl_fit.c |  8 
 include/spl.h| 15 ++-
 3 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index a76ea3a..ef195e0 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -114,6 +114,7 @@ int spl_parse_image_header(struct spl_image_info *spl_image,
header_size;
}
spl_image->os = image_get_os(header);
+   spl_image->arch = image_get_arch(header);
spl_image->name = image_get_name(header);
debug("spl: payload image: %.*s load addr: 0x%lx size: %d\n",
(int)sizeof(spl_image->name), spl_image->name,
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index aae556f..a5d903b 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -123,6 +123,11 @@ static int get_aligned_image_size(struct spl_load_info 
*info, int data_size,
return (data_size + info->bl_len - 1) / info->bl_len;
 }
 
+__weak u8 spl_genimg_get_arch_id(const char *arch_str)
+{
+   return IH_ARCH_DEFAULT;
+}
+
 int spl_load_simple_fit(struct spl_image_info *spl_image,
struct spl_load_info *info, ulong sector, void *fit)
 {
@@ -136,6 +141,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
int base_offset, align_len = ARCH_DMA_MINALIGN - 1;
int src_sector;
void *dst, *src;
+   const char *arch_str;
 
/*
 * Figure out where the external images start. This is the base for the
@@ -184,10 +190,12 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
data_offset = fdt_getprop_u32(fit, node, "data-offset");
data_size = fdt_getprop_u32(fit, node, "data-size");
load = fdt_getprop_u32(fit, node, "load");
+   arch_str = fdt_getprop(fit, node, "arch", NULL);
debug("data_offset=%x, data_size=%x\n", data_offset, data_size);
spl_image->load_addr = load;
spl_image->entry_point = load;
spl_image->os = IH_OS_U_BOOT;
+   spl_image->arch = spl_genimg_get_arch_id(arch_str);
 
/*
 * Work out where to place the image. We read it so that the first
diff --git a/include/spl.h b/include/spl.h
index bde4437..8223f4b 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -20,13 +20,26 @@
 #define MMCSD_MODE_FS  2
 #define MMCSD_MODE_EMMCBOOT3
 
+/*
+ * Information about an U-Boot image file as described in include/image.h.
+ * Parsed by the SPL code from a legacy or FIT image file.
+ *
+ * @name: descriptive string (mkimage -n)
+ * @load_addr: address to load the image file to (mkimage -a)
+ * @entry_point: address of first instruction to execute (mkimage -e)
+ * @size: size of image in bytes
+ * @flags: optional, used only for SPL_COPY_PAYLOAD_ONLY so far
+ * @os: target operating system, one of IH_OS_* (mkimage -O)
+ * @arch: target architecture, one of IH_ARCH_* (mkimage -A)
+ */
 struct spl_image_info {
const char *name;
-   u8 os;
ulong load_addr;
ulong entry_point;
u32 size;
u32 flags;
+   u8 os;
+   u8 arch;
 };
 
 /*
-- 
2.8.2

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[U-Boot] [PATCH v4 16/26] sunxi: H3: add DRAM controller single bit delay support

[Andre Przywara]

From: Jens Kuske 

So far the DRAM driver for the H3 SoC (and apparently boot0/libdram as
well) only applied coarse delay line settings, with one delay value for
all the data lines in each byte lane and one value for the control lines.

Instead of setting the delays for whole bytes only allow setting it for
each individual bit. Also add support for address/command lane delays.

For the purpose of this patch the rules for the existing coarse settings
were just applied to the new scheme, so the actual register writes don't
change for the H3. Other SoCs will utilize this feature later properly.

With a stock GCC 5.3.0 this increases the dram_sun8i_h3.o code size from
2296 to 2344 Bytes.

[Andre: move delay parameters into macros to ease later sharing, use
defines for numbers of delay registers, extend commit message]

Signed-off-by: Jens Kuske 
Signed-off-by: Andre Przywara 
---
 arch/arm/mach-sunxi/dram_sun8i_h3.c | 77 -
 1 file changed, 50 insertions(+), 27 deletions(-)

diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c 
b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index 539268f..4396754 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -15,13 +15,24 @@
 #include 
 #include 
 
+/*
+ * The delay parameters below allow to allegedly specify delay times of some
+ * unknown unit for each individual bit trace in each of the four data bytes
+ * the 32-bit wide access consists of. Also three control signals can be
+ * adjusted individually.
+ */
+#define BITS_PER_BYTE  8
+#define NR_OF_BYTE_LANES   (32 / BITS_PER_BYTE)
+/* The eight data lines (DQn) plus DM, DQS and DQSN */
+#define LINES_PER_BYTE_LANE(BITS_PER_BYTE + 3)
 struct dram_para {
-   u32 read_delays;
-   u32 write_delays;
u16 page_size;
u8 bus_width;
u8 dual_rank;
u8 row_bits;
+   const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
+   const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
+   const u8 ac_delays[31];
 };
 
 static inline int ns_to_t(int nanoseconds)
@@ -64,34 +75,25 @@ static void mctl_phy_init(u32 val)
mctl_await_completion(_ctl->pgsr[0], PGSR_INIT_DONE, 0x1);
 }
 
-static void mctl_dq_delay(u32 read, u32 write)
+static void mctl_set_bit_delays(struct dram_para *para)
 {
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
int i, j;
-   u32 val;
-
-   for (i = 0; i < 4; i++) {
-   val = DXBDLR_WRITE_DELAY((write >> (i * 4)) & 0xf) |
- DXBDLR_READ_DELAY(((read >> (i * 4)) & 0xf) * 2);
-
-   for (j = DXBDLR_DQ(0); j <= DXBDLR_DM; j++)
-   writel(val, _ctl->dx[i].bdlr[j]);
-   }
 
clrbits_le32(_ctl->pgcr[0], 1 << 26);
 
-   for (i = 0; i < 4; i++) {
-   val = DXBDLR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) |
- DXBDLR_READ_DELAY((read >> (16 + i * 4)) & 0xf);
+   for (i = 0; i < NR_OF_BYTE_LANES; i++)
+   for (j = 0; j < LINES_PER_BYTE_LANE; j++)
+   writel(DXBDLR_WRITE_DELAY(para->dx_write_delays[i][j]) |
+  DXBDLR_READ_DELAY(para->dx_read_delays[i][j]),
+  _ctl->dx[i].bdlr[j]);
 
-   writel(val, _ctl->dx[i].bdlr[DXBDLR_DQS]);
-   writel(val, _ctl->dx[i].bdlr[DXBDLR_DQSN]);
-   }
+   for (i = 0; i < 31; i++)
+   writel(ACBDLR_WRITE_DELAY(para->ac_delays[i]),
+  _ctl->acbdlr[i]);
 
setbits_le32(_ctl->pgcr[0], 1 << 26);
-
-   udelay(1);
 }
 
 enum {
@@ -412,11 +414,8 @@ static int mctl_channel_init(struct dram_para *para)
clrsetbits_le32(_ctl->dtcr, 0xf << 24,
(para->dual_rank ? 0x3 : 0x1) << 24);
 
-
-   if (para->read_delays || para->write_delays) {
-   mctl_dq_delay(para->read_delays, para->write_delays);
-   udelay(50);
-   }
+   mctl_set_bit_delays(para);
+   udelay(50);
 
mctl_zq_calibration(para);
 
@@ -490,6 +489,29 @@ static void mctl_auto_detect_dram_size(struct dram_para 
*para)
break;
 }
 
+/*
+ * The actual values used here are taken from Allwinner provided boot0
+ * binaries, though they are probably board specific, so would likely benefit
+ * from invidual tuning for each board. Apparently a lot of boards copy from
+ * some Allwinner reference design, so we go with those generic values for now
+ * in the hope that they are reasonable for most (all?) boards.
+ */
+#define SUN8I_H3_DX_READ_DELAYS\
+   {{ 18, 18, 18, 18, 18, 18, 18, 18, 18,  0,  0 },\
+{ 14, 14, 14, 14, 14, 14, 14, 14, 14,  0,  0 },\
+{ 18, 18, 18, 18, 18, 18, 18, 18, 18,  0,  0 

[U-Boot] [PATCH v4 17/26] sunxi: clocks: Use the correct pattern register for PLL11

[Andre Przywara]

From: Philipp Tomsich 

Signed-off-by: Philipp Tomsich 
Signed-off-by: Andre Przywara 
Acked-by: Maxime Ripard 
---
 arch/arm/mach-sunxi/clock_sun6i.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/clock_sun6i.c 
b/arch/arm/mach-sunxi/clock_sun6i.c
index 80cfc0b..8e39bbe 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -224,7 +224,7 @@ void clock_set_pll11(unsigned int clk, bool 
sigma_delta_enable)
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
if (sigma_delta_enable)
-   writel(CCM_PLL11_PATTERN, >pll5_pattern_cfg);
+   writel(CCM_PLL11_PATTERN, >pll11_pattern_cfg0);
 
writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
   (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
-- 
2.8.2

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[U-Boot] [PATCH v4 14/26] sunxi: H3: Rework MBUS priority setup

[Andre Przywara]

From: Philipp Tomsich 

So far the MBUS priority setup was done by writing "magic" values taken
from a DRAM controller register dump after a boot0 run.
By peeking at the Linux (sic!) MBUS driver [1] from the Allwinner BSP
kernel, we learned more about the actual meaning of those bits.
Add macros and refactor the setup function to make the MBUS setup much
more readable and meaningful.
The actual values used now are a transformation of the values used
before, which are assembled by the new code to result in the same register
writes. So this rework does not change any settings, also the code size
stays the same.

The respective source files in the BSP kernel had a proper GPL header,
so lifting this code and information into U-Boot is legal.

[Andre: provide a convenience macro to fit definitions on one line]

[1] 
https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65/drivers/bus/sunxi_mbus.c

Signed-off-by: Philipp Tomsich 
Signed-off-by: Andre Przywara 
Acked-by: Maxime Ripard 
---
 arch/arm/mach-sunxi/dram_sun8i_h3.c | 88 +++--
 1 file changed, 64 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c 
b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index b08b8e6..8925446 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -94,6 +94,58 @@ static void mctl_dq_delay(u32 read, u32 write)
udelay(1);
 }
 
+enum {
+   MBUS_PORT_CPU   = 0,
+   MBUS_PORT_GPU   = 1,
+   MBUS_PORT_UNUSED= 2,
+   MBUS_PORT_DMA   = 3,
+   MBUS_PORT_VE= 4,
+   MBUS_PORT_CSI   = 5,
+   MBUS_PORT_NAND  = 6,
+   MBUS_PORT_SS= 7,
+   MBUS_PORT_TS= 8,
+   MBUS_PORT_DI= 9,
+   MBUS_PORT_DE= 10,
+   MBUS_PORT_DE_CFD= 11,
+};
+
+enum {
+   MBUS_QOS_LOWEST = 0,
+   MBUS_QOS_LOW,
+   MBUS_QOS_HIGH,
+   MBUS_QOS_HIGHEST
+};
+
+inline void mbus_configure_port(u8 port,
+   bool bwlimit,
+   bool priority,
+   u8 qos, /* MBUS_QOS_LOWEST .. 
MBUS_QOS_HIGEST */
+   u8 waittime,/* 0 .. 0xf */
+   u8 acs, /* 0 .. 0xff */
+   u16 bwl0,   /* 0 .. 0x, bandwidth limit 
in MB/s */
+   u16 bwl1,
+   u16 bwl2)
+{
+   struct sunxi_mctl_com_reg * const mctl_com =
+   (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+   const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0)
+  | (priority ? (1 << 1) : 0)
+  | ((qos & 0x3) << 2)
+  | ((waittime & 0xf) << 4)
+  | ((acs & 0xff) << 8)
+  | (bwl0 << 16) );
+   const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0x);
+
+   debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
+   writel(cfg0, _com->mcr[port][0]);
+   writel(cfg1, _com->mcr[port][1]);
+}
+
+#define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2)   \
+   mbus_configure_port(MBUS_PORT_ ## port, bwlimit, false, \
+   MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
+
 static void mctl_set_master_priority(void)
 {
struct sunxi_mctl_com_reg * const mctl_com =
@@ -105,30 +157,18 @@ static void mctl_set_master_priority(void)
/* set cpu high priority */
writel(0x0001, _com->mapr);
 
-   writel(0x020d, _com->mcr[0][0]);
-   writel(0x00800100, _com->mcr[0][1]);
-   writel(0x0609, _com->mcr[1][0]);
-   writel(0x01000400, _com->mcr[1][1]);
-   writel(0x020d, _com->mcr[2][0]);
-   writel(0x00600100, _com->mcr[2][1]);
-   writel(0x010d, _com->mcr[3][0]);
-   writel(0x00200080, _com->mcr[3][1]);
-   writel(0x0709, _com->mcr[4][0]);
-   writel(0x01000640, _com->mcr[4][1]);
-   writel(0x010d, _com->mcr[5][0]);
-   writel(0x00200080, _com->mcr[5][1]);
-   writel(0x0109, _com->mcr[6][0]);
-   writel(0x00400080, _com->mcr[6][1]);
-   writel(0x010d, _com->mcr[7][0]);
-   writel(0x00400080, _com->mcr[7][1]);
-   writel(0x010d, _com->mcr[8][0]);
-   writel(0x00400080, _com->mcr[8][1]);
-   writel(0x0409, _com->mcr[9][0]);
-   writel(0x00400100, _com->mcr[9][1]);
-   writel(0x230d, _com->mcr[10][0]);
-   writel(0x04001800, _com->mcr[10][1]);
-   writel(0x0409, _com->mcr[11][0]);
-   writel(0x00400120, _com->mcr[11][1]);
+   MBUS_CONF(   CPU,  true, HIGHEST, 0,  512,  256,  128);
+   MBUS_CONF(   GPU,  true,HIGH, 0, 1536, 1024,  256);
+   

[U-Boot] [PATCH v4 15/26] sunxi: H3: add and rename some DRAM contoller registers

[Andre Przywara]

From: Jens Kuske 

The IOCR registers got renamed to BDLR to match the public
documentation of similar controllers.

Signed-off-by: Jens Kuske 
Signed-off-by: Andre Przywara 
---
 arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h | 43 ++---
 arch/arm/mach-sunxi/dram_sun8i_h3.c | 34 +--
 2 files changed, 41 insertions(+), 36 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h 
b/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
index d0f2b8a..346538c 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
@@ -106,20 +106,23 @@ struct sunxi_mctl_ctl_reg {
u32 perfhpr[2]; /* 0x1c4 */
u32 perflpr[2]; /* 0x1cc */
u32 perfwr[2];  /* 0x1d4 */
-   u8 res8[0x2c];  /* 0x1dc */
-   u32 aciocr; /* 0x208 */
-   u8 res9[0xf4];  /* 0x20c */
+   u8 res8[0x24];  /* 0x1dc */
+   u32 acmdlr; /* 0x200 AC master delay line register */
+   u32 aclcdlr;/* 0x204 AC local calibrated delay line 
register */
+   u32 aciocr; /* 0x208 AC I/O configuration register */
+   u8 res9[0x4];   /* 0x20c */
+   u32 acbdlr[31]; /* 0x210 AC bit delay line registers */
+   u8 res10[0x74]; /* 0x28c */
struct {/* 0x300 DATX8 modules*/
-   u32 mdlr;   /* 0x00 */
-   u32 lcdlr[3];   /* 0x04 */
-   u32 iocr[11];   /* 0x10 IO configuration register */
-   u32 bdlr6;  /* 0x3c */
-   u32 gtr;/* 0x40 */
-   u32 gcr;/* 0x44 */
-   u32 gsr[3]; /* 0x48 */
+   u32 mdlr;   /* 0x00 master delay line register */
+   u32 lcdlr[3];   /* 0x04 local calibrated delay line 
registers */
+   u32 bdlr[12];   /* 0x10 bit delay line registers */
+   u32 gtr;/* 0x40 general timing register */
+   u32 gcr;/* 0x44 general configuration register 
*/
+   u32 gsr[3]; /* 0x48 general status registers */
u8 res0[0x2c];  /* 0x54 */
-   } datx[4];
-   u8 res10[0x388];/* 0x500 */
+   } dx[4];
+   u8 res11[0x388];/* 0x500 */
u32 upd2;   /* 0x888 */
 };
 
@@ -172,14 +175,16 @@ struct sunxi_mctl_ctl_reg {
 
 #define PGSR_INIT_DONE (0x1 << 0)  /* PHY init done */
 
-#define ZQCR_PWRDOWN   (0x1 << 31) /* ZQ power down */
+#define ZQCR_PWRDOWN   (1U << 31)  /* ZQ power down */
 
-#define DATX_IOCR_DQ(x)(x) /* DQ0-7 IOCR index */
-#define DATX_IOCR_DM   (8) /* DM IOCR index */
-#define DATX_IOCR_DQS  (9) /* DQS IOCR index */
-#define DATX_IOCR_DQSN (10)/* DQSN IOCR index */
+#define ACBDLR_WRITE_DELAY(x)  ((x) << 8)
 
-#define DATX_IOCR_WRITE_DELAY(x)   ((x) << 8)
-#define DATX_IOCR_READ_DELAY(x)((x) << 0)
+#define DXBDLR_DQ(x)   (x) /* DQ0-7 BDLR index */
+#define DXBDLR_DM  8   /* DM BDLR index */
+#define DXBDLR_DQS 9   /* DQS BDLR index */
+#define DXBDLR_DQSN10  /* DQSN BDLR index */
+
+#define DXBDLR_WRITE_DELAY(x)  ((x) << 8)
+#define DXBDLR_READ_DELAY(x)   ((x) << 0)
 
 #endif /* _SUNXI_DRAM_SUN8I_H3_H */
diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c 
b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index 8925446..539268f 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -72,21 +72,21 @@ static void mctl_dq_delay(u32 read, u32 write)
u32 val;
 
for (i = 0; i < 4; i++) {
-   val = DATX_IOCR_WRITE_DELAY((write >> (i * 4)) & 0xf) |
- DATX_IOCR_READ_DELAY(((read >> (i * 4)) & 0xf) * 2);
+   val = DXBDLR_WRITE_DELAY((write >> (i * 4)) & 0xf) |
+ DXBDLR_READ_DELAY(((read >> (i * 4)) & 0xf) * 2);
 
-   for (j = DATX_IOCR_DQ(0); j <= DATX_IOCR_DM; j++)
-   writel(val, _ctl->datx[i].iocr[j]);
+   for (j = DXBDLR_DQ(0); j <= DXBDLR_DM; j++)
+   writel(val, _ctl->dx[i].bdlr[j]);
}
 
clrbits_le32(_ctl->pgcr[0], 1 << 26);
 
for (i = 0; i < 4; i++) {
-   val = DATX_IOCR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) |
- DATX_IOCR_READ_DELAY((read >> (16 + i * 4)) & 0xf);
+   val = DXBDLR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) |
+ DXBDLR_READ_DELAY((read >> (16 + i * 4)) & 0xf);
 
-   writel(val, _ctl->datx[i].iocr[DATX_IOCR_DQS]);
-   writel(val, _ctl->datx[i].iocr[DATX_IOCR_DQSN]);
+   

[U-Boot] [PATCH v4 13/26] sunxi: provide default DRAM config for sun50i in Kconfig

[Andre Przywara]

To avoid enumerating the very same DRAM values in defconfig files
for each and every Allwinner A64 board out there, let's put some sane
default values in the Kconfig file.
Boards with different needs can override them at any time.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
Acked-by: Maxime Ripard 
---
 board/sunxi/Kconfig   | 2 ++
 configs/pine64_plus_defconfig | 2 --
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index f020573..c2eb85e 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -168,6 +168,7 @@ config DRAM_CLK
default 792 if MACH_SUN9I
default 312 if MACH_SUN6I || MACH_SUN8I
default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
+   default 672 if MACH_SUN50I
---help---
Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
must be a multiple of 24. For the sun9i (A80), the tested values
@@ -187,6 +188,7 @@ config DRAM_ZQ
default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
default 127 if MACH_SUN7I
default 4145117 if MACH_SUN9I
+   default 3881915 if MACH_SUN50I
---help---
Set the dram zq value.
 
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index ea53b96..ebc24b8 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -2,8 +2,6 @@ CONFIG_ARM=y
 CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_MACH_SUN50I=y
-CONFIG_DRAM_CLK=672
-CONFIG_DRAM_ZQ=3881915
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_CONSOLE_MUX=y
-- 
2.8.2

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[U-Boot] [PATCH v4 12/26] sunxi: A64: do an RMR switch if started in AArch32 mode

[Andre Przywara]

The Allwinner A64 SoC starts execution in AArch32 mode, and both
the boot ROM and Allwinner's boot0 keep running in this mode.
So U-Boot gets entered in 32-bit, although we want it to run in AArch64.

By using a "magic" instruction, which happens to be an almost-NOP in
AArch64 and a branch in AArch32, we differentiate between being
entered in 64-bit or 32-bit mode.
If in 64-bit mode, we proceed with the branch to reset, but in 32-bit
mode we trigger an RMR write to bring the core into AArch64/EL3 and
re-enter U-Boot at CONFIG_SYS_TEXT_BASE.
This allows a 64-bit U-Boot to be both entered in 32 and 64-bit mode,
so we can use the same start code for the SPL and the U-Boot proper.

We use the existing custom header (boot0.h) functionality, but restrict
the existing boot0 header reservation to the non-SPL build now. A SPL
wouldn't need such header anyway. This allows to have both options
defined and lets us use one for the SPL and the other for U-Boot proper.

Also add arch/arm/mach-sunxi/rmr_switch.S, which contains the original
ARM assembly code and instructions how to re-generate the encoded
version.

Signed-off-by: Andre Przywara 
Acked-by: Maxime Ripard 
---
 arch/arm/include/asm/arch-sunxi/boot0.h | 30 
 arch/arm/mach-sunxi/rmr_switch.S| 41 +
 board/sunxi/Kconfig | 14 +++
 3 files changed, 85 insertions(+)
 create mode 100644 arch/arm/mach-sunxi/rmr_switch.S

diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h 
b/arch/arm/include/asm/arch-sunxi/boot0.h
index 6a13db5..9c6d82d 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -4,6 +4,36 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
+#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && 
!defined(CONFIG_SPL_BUILD)
 /* reserve space for BOOT0 header information */
b   reset
.space  1532
+#elif defined(CONFIG_ARM_BOOT_HOOK_RMR)
+/*
+ * Switch into AArch64 if needed.
+ * Refer to arch/arm/mach-sunxi/rmr_switch.S for the original source.
+ */
+   tst x0, x0  // this is "b #0x84" in ARM
+   b   reset
+   .space  0x7c
+   .word   0xe59f1024  // ldr r1, [pc, #36] ; 0x17a0
+   .word   0xe59f0024  // ldr r0, [pc, #36] ; CONFIG_*_TEXT_BASE
+   .word   0xe581  // str r0, [r1]
+   .word   0xf57ff04f  // dsb sy
+   .word   0xf57ff06f  // isb sy
+   .word   0xee1c0f50  // mrc 15, 0, r0, cr12, cr0, {2} ; RMR
+   .word   0xe383  // orr r0, r0, #3
+   .word   0xee0c0f50  // mcr 15, 0, r0, cr12, cr0, {2} ; RMR
+   .word   0xf57ff06f  // isb sy
+   .word   0xe320f003  // wfi
+   .word   0xeafd  // b   @wfi
+   .word   0x017000a0  // writeable RVBAR mapping address
+#ifdef CONFIG_SPL_BUILD
+   .word   CONFIG_SPL_TEXT_BASE
+#else
+   .word   CONFIG_SYS_TEXT_BASE
+#endif
+#else
+/* normal execution */
+   b   reset
+#endif
diff --git a/arch/arm/mach-sunxi/rmr_switch.S b/arch/arm/mach-sunxi/rmr_switch.S
new file mode 100644
index 000..cefa930
--- /dev/null
+++ b/arch/arm/mach-sunxi/rmr_switch.S
@@ -0,0 +1,41 @@
+@
+@ ARMv8 RMR reset sequence on Allwinner SoCs.
+@
+@ All 64-bit capable Allwinner SoCs reset in AArch32 (and continue to
+@ exectute the Boot ROM in this state), so we need to switch to AArch64
+@ at some point.
+@ Section G6.2.133 of the ARMv8 ARM describes the Reset Management Register
+@ (RMR), which triggers a warm-reset of a core and can request to switch
+@ into a different execution state (AArch32 or AArch64).
+@ The address at which execution starts after the reset is held in the
+@ RVBAR system register, which is architecturally read-only.
+@ Allwinner provides a writable alias of this register in MMIO space, so
+@ we can easily set the start address of AArch64 code.
+@ This code below switches to AArch64 and starts execution at the specified
+@ start address. It needs to be assembled by an ARM(32) assembler and
+@ the machine code must be inserted as verbatim .word statements into the
+@ beginning of the AArch64 U-Boot code.
+@ To get the encoded bytes, use:
+@ ${CROSS_COMPILE}gcc -c -o rmr_switch.o rmr_switch.S
+@ ${CROSS_COMPILE}objdump -d rmr_switch.o
+@
+@ The resulting words should be inserted into the U-Boot file at
+@ arch/arm/include/asm/arch-sunxi/boot0.h.
+@
+@ This file is not build by the U-Boot build system, but provided only as a
+@ reference and to be able to regenerate a (probably fixed) version of this
+@ code found in encoded form in boot0.h.
+
+.text
+
+   ldr r1, =0x017000a0 @ MMIO mapped RVBAR[0] register
+   ldr r0, =0x57aA7add @ start address, to be replaced
+   str r0, [r1]
+   dsb sy
+   isb sy
+   mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register

[U-Boot] [PATCH v4 11/26] sunxi: introduce extra config option for boot0 header

[Andre Przywara]

The ENABLE_ARM_SOC_BOOT0_HOOK option is a generic option shared with
other boards. To allow alternative code to be inserted, we create
another, now function specific config symbol on top of it to simplify
later additions. No functional change at this time.

Signed-off-by: Andre Przywara 
Acked-by: Maxime Ripard 
Reviewed-by: Simon Glass 
---
 board/sunxi/Kconfig   | 9 +
 configs/pine64_plus_defconfig | 2 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index e1d4ab1..0cd57a2 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -133,6 +133,15 @@ config MACH_SUN8I
bool
default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || 
MACH_SUN8I_A83T
 
+config RESERVE_ALLWINNER_BOOT0_HEADER
+   bool "reserve space for Allwinner boot0 header"
+   select ENABLE_ARM_SOC_BOOT0_HOOK
+   ---help---
+   Prepend a 1536 byte (empty) header to the U-Boot image file, to be
+   filled with magic values post build. The Allwinner provided boot0
+   blob relies on this information to load and execute U-Boot.
+   Only needed on 64-bit Allwinner boards so far when using boot0.
+
 config DRAM_TYPE
int "sunxi dram type"
depends on MACH_SUN8I_A83T
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 6d0198f..ea53b96 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_MACH_SUN50I=y
 CONFIG_DRAM_CLK=672
-- 
2.8.2

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[U-Boot] [PATCH v4 10/26] ARM: boot0 hook: remove macro, include whole header file

[Andre Przywara]

For prepending some board specific header area to U-Boot images we
were so far including a header file with a macro definition containing
the actual header specification.
This works fine if there are just a few statements and if there is only
one alternative.
However adding more complex code quickly gets messy with this approach,
so let's just drop that intermediate macro and let the #include actually
insert the code directly.
This converts the callers and the callees, but doesn't change anything
at this point.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
Tested-by: Steve Rae 
---
 arch/arm/cpu/armv8/start.S | 1 -
 arch/arm/include/asm/arch-bcm235xx/boot0.h | 8 +---
 arch/arm/include/asm/arch-bcm281xx/boot0.h | 8 +---
 arch/arm/include/asm/arch-sunxi/boot0.h| 8 +---
 arch/arm/lib/vectors.S | 1 -
 5 files changed, 3 insertions(+), 23 deletions(-)

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index ee393d7..140609d 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -26,7 +26,6 @@ _start:
  * use it here.
  */
 #include 
-ARM_SOC_BOOT0_HOOK
 #else
b   reset
 #endif
diff --git a/arch/arm/include/asm/arch-bcm235xx/boot0.h 
b/arch/arm/include/asm/arch-bcm235xx/boot0.h
index 7e72882..a747bd3 100644
--- a/arch/arm/include/asm/arch-bcm235xx/boot0.h
+++ b/arch/arm/include/asm/arch-bcm235xx/boot0.h
@@ -4,12 +4,6 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#ifndef __BOOT0_H
-#define __BOOT0_H
-
 /* BOOT0 header information */
-#define ARM_SOC_BOOT0_HOOK \
-   .word   0xbabeface; \
+   .word   0xbabeface
.word   _end - _start
-
-#endif /* __BOOT0_H */
diff --git a/arch/arm/include/asm/arch-bcm281xx/boot0.h 
b/arch/arm/include/asm/arch-bcm281xx/boot0.h
index 7e72882..a747bd3 100644
--- a/arch/arm/include/asm/arch-bcm281xx/boot0.h
+++ b/arch/arm/include/asm/arch-bcm281xx/boot0.h
@@ -4,12 +4,6 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#ifndef __BOOT0_H
-#define __BOOT0_H
-
 /* BOOT0 header information */
-#define ARM_SOC_BOOT0_HOOK \
-   .word   0xbabeface; \
+   .word   0xbabeface
.word   _end - _start
-
-#endif /* __BOOT0_H */
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h 
b/arch/arm/include/asm/arch-sunxi/boot0.h
index 6f28d63..6a13db5 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -4,12 +4,6 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#ifndef __BOOT0_H
-#define __BOOT0_H
-
 /* reserve space for BOOT0 header information */
-#define ARM_SOC_BOOT0_HOOK \
-   b   reset;  \
+   b   reset
.space  1532
-
-#endif /* __BOOT0_H */
diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S
index 5cc132b..9fe7415 100644
--- a/arch/arm/lib/vectors.S
+++ b/arch/arm/lib/vectors.S
@@ -67,7 +67,6 @@ _start:
  * use it here.
  */
 #include 
-ARM_SOC_BOOT0_HOOK
 #endif
 
 /*
-- 
2.8.2

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[U-Boot] [PATCH v4 09/26] armv8: move reset branch into boot hook

[Andre Przywara]

The boot0 hook we have so far is applied _after_ the initial branch
to the "reset" entry point. An upcoming change requires even this
branch to be changed, so we apply the hook macro at the earliest
point, and have the branch in the hook file as well.
This is no functional change at this point, just refactoring to simplify
upcoming patches.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
---
 arch/arm/cpu/armv8/start.S  | 4 ++--
 arch/arm/include/asm/arch-sunxi/boot0.h | 1 +
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 4f5f6d8..ee393d7 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -19,8 +19,6 @@
 
 .globl _start
 _start:
-   b   reset
-
 #ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
 /*
  * Various SoCs need something special and SoC-specific up front in
@@ -29,6 +27,8 @@ _start:
  */
 #include 
 ARM_SOC_BOOT0_HOOK
+#else
+   b   reset
 #endif
 
.align 3
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h 
b/arch/arm/include/asm/arch-sunxi/boot0.h
index ea5675e..6f28d63 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -9,6 +9,7 @@
 
 /* reserve space for BOOT0 header information */
 #define ARM_SOC_BOOT0_HOOK \
+   b   reset;  \
.space  1532
 
 #endif /* __BOOT0_H */
-- 
2.8.2

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[U-Boot] [PATCH v4 08/26] armv8: add simple sdelay implementation

[Andre Przywara]

The sunxi DRAM setup code needs an sdelay() implementation, which
wasn't defined for armv8 so far.
Shamelessly copy the armv7 version and adjust it to work in AArch64.

Signed-off-by: Andre Przywara 
---
 arch/arm/cpu/armv8/cpu.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
index 5dcb5e2..28a27f7 100644
--- a/arch/arm/cpu/armv8/cpu.c
+++ b/arch/arm/cpu/armv8/cpu.c
@@ -17,6 +17,20 @@
 #include 
 #include 
 
+/*
+ * sdelay() - simple spin loop.
+ *
+ * Will delay execution by roughly (@loops * 2) cycles.
+ * This is necessary to be used before timers are accessible.
+ *
+ * A value of "0" will results in 2^64 loops.
+ */
+void sdelay(unsigned long loops)
+{
+   __asm__ volatile ("1:\n" "subs %0, %0, #1\n"
+ "b.ne 1b" : "=r" (loops) : "0"(loops) : "cc");
+}
+
 int cleanup_before_linux(void)
 {
/*
-- 
2.8.2

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[U-Boot] [PATCH v4 07/26] SPL: make struct spl_image 64-bit safe

[Andre Przywara]

Since entry_point and load_addr are addresses, they should be
represented as longs to cover the whole address space and to avoid
warning when compiling the SPL in 64-bit.
Also adjust debug prints to add the 'l' specifier, where needed.

Signed-off-by: Andre Przywara 
Reviewed-by: Alexander Graf 
Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
Acked-by: Maxime Ripard 
---
 arch/arm/mach-omap2/boot-common.c | 2 +-
 arch/arm/mach-tegra/spl.c | 2 +-
 common/spl/spl.c  | 8 
 common/spl/spl_mmc.c  | 2 +-
 include/spl.h | 4 ++--
 5 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-omap2/boot-common.c 
b/arch/arm/mach-omap2/boot-common.c
index 385310b..7ae3d80 100644
--- a/arch/arm/mach-omap2/boot-common.c
+++ b/arch/arm/mach-omap2/boot-common.c
@@ -228,7 +228,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info 
*spl_image)
 
u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
 
-   debug("image entry point: 0x%X\n", spl_image->entry_point);
+   debug("image entry point: 0x%lX\n", spl_image->entry_point);
/* Pass the saved boot_params from rom code */
image_entry((u32 *)boot_params);
 }
diff --git a/arch/arm/mach-tegra/spl.c b/arch/arm/mach-tegra/spl.c
index e0f9d5b..41c88cb 100644
--- a/arch/arm/mach-tegra/spl.c
+++ b/arch/arm/mach-tegra/spl.c
@@ -42,7 +42,7 @@ u32 spl_boot_device(void)
 
 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 {
-   debug("image entry point: 0x%X\n", spl_image->entry_point);
+   debug("image entry point: 0x%lX\n", spl_image->entry_point);
 
start_cpu((u32)spl_image->entry_point);
halt_avp();
diff --git a/common/spl/spl.c b/common/spl/spl.c
index f7df834..a76ea3a 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -115,7 +115,7 @@ int spl_parse_image_header(struct spl_image_info *spl_image,
}
spl_image->os = image_get_os(header);
spl_image->name = image_get_name(header);
-   debug("spl: payload image: %.*s load addr: 0x%x size: %d\n",
+   debug("spl: payload image: %.*s load addr: 0x%lx size: %d\n",
(int)sizeof(spl_image->name), spl_image->name,
spl_image->load_addr, spl_image->size);
} else {
@@ -140,7 +140,7 @@ int spl_parse_image_header(struct spl_image_info *spl_image,
spl_image->load_addr = CONFIG_SYS_LOAD_ADDR;
spl_image->entry_point = CONFIG_SYS_LOAD_ADDR;
spl_image->size = end - start;
-   debug("spl: payload zImage, load addr: 0x%x size: %d\n",
+   debug("spl: payload zImage, load addr: 0x%lx size: 
%d\n",
  spl_image->load_addr, spl_image->size);
return 0;
}
@@ -164,9 +164,9 @@ __weak void __noreturn jump_to_image_no_args(struct 
spl_image_info *spl_image)
typedef void __noreturn (*image_entry_noargs_t)(void);
 
image_entry_noargs_t image_entry =
-   (image_entry_noargs_t)(unsigned long)spl_image->entry_point;
+   (image_entry_noargs_t)spl_image->entry_point;
 
-   debug("image entry point: 0x%X\n", spl_image->entry_point);
+   debug("image entry point: 0x%lX\n", spl_image->entry_point);
image_entry();
 }
 
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 85e3de8..0cd355c 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -36,7 +36,7 @@ static int mmc_load_legacy(struct spl_image_info *spl_image, 
struct mmc *mmc,
/* Read the header too to avoid extra memcpy */
count = blk_dread(mmc_get_blk_desc(mmc), sector, image_size_sectors,
  (void *)(ulong)spl_image->load_addr);
-   debug("read %x sectors to %x\n", image_size_sectors,
+   debug("read %x sectors to %lx\n", image_size_sectors,
  spl_image->load_addr);
if (count != image_size_sectors)
return -EIO;
diff --git a/include/spl.h b/include/spl.h
index 6e746b2..bde4437 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -23,8 +23,8 @@
 struct spl_image_info {
const char *name;
u8 os;
-   u32 load_addr;
-   u32 entry_point;
+   ulong load_addr;
+   ulong entry_point;
u32 size;
u32 flags;
 };
-- 
2.8.2

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[U-Boot] [PATCH v4 04/26] SPL: tiny-printf: add "l" modifier

[Andre Przywara]

tiny-printf does not know about the "l" modifier so far, which breaks
the crash dump on AArch64, because it uses %lx to print the registers.
Add an easy way of handling longs correctly.

Using a relatively decent compiler (GCC 5.3.0) this does _not_ increase
the code size of tiny-printf.o for 32-bit builds (where long and int
are actually the same), actually it looses three (ARM Thumb2) instructions
from the actual SPL (numbers for orangepi_plus_defconfig):
  textdata bss dec hex filename
   758   0   0 758 2f6 spl/lib/tiny-printf.obefore
 18839 488 232   195594c67 spl/u-boot-spl   before
   758   0   0 758 2f6 spl/lib/tiny-printf.oafter
 18833 488 232   195534c61 spl/u-boot-spl   after

This adds some substantial amount of code to a 64-bit build, though:
(taken after a later commit, which enables the ARM64 SPL build for sunxi)
  textdata bss dec hex filename
  1542   0   01542 606 spl/lib/tiny-printf.obefore
 25830 392 360   2658267d6 spl/u-boot-spl   before
  1758   0   01758 6de spl/lib/tiny-printf.oafter
 26040 392 360   2679268a8 spl/u-boot-spl   after

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
---
 lib/tiny-printf.c | 47 ---
 1 file changed, 36 insertions(+), 11 deletions(-)

diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 30ac759..0b8512f 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -38,8 +38,8 @@ static void out_dgt(struct printf_info *info, char dgt)
info->zs = 1;
 }
 
-static void div_out(struct printf_info *info, unsigned int *num,
-   unsigned int div)
+static void div_out(struct printf_info *info, unsigned long *num,
+   unsigned long div)
 {
unsigned char dgt = 0;
 
@@ -56,9 +56,9 @@ int _vprintf(struct printf_info *info, const char *fmt, 
va_list va)
 {
char ch;
char *p;
-   unsigned int num;
+   unsigned long num;
char buf[12];
-   unsigned int div;
+   unsigned long div;
 
while ((ch = *(fmt++))) {
if (ch != '%') {
@@ -66,6 +66,7 @@ int _vprintf(struct printf_info *info, const char *fmt, 
va_list va)
} else {
bool lz = false;
int width = 0;
+   bool islong = false;
 
ch = *(fmt++);
if (ch == '0') {
@@ -80,6 +81,11 @@ int _vprintf(struct printf_info *info, const char *fmt, 
va_list va)
ch = *fmt++;
}
}
+   if (ch == 'l') {
+   ch = *(fmt++);
+   islong = true;
+   }
+
info->bf = buf;
p = info->bf;
info->zs = 0;
@@ -89,24 +95,43 @@ int _vprintf(struct printf_info *info, const char *fmt, 
va_list va)
goto abort;
case 'u':
case 'd':
-   num = va_arg(va, unsigned int);
-   if (ch == 'd' && (int)num < 0) {
-   num = -(int)num;
-   out(info, '-');
+   div = 10;
+   if (islong) {
+   num = va_arg(va, unsigned long);
+   if (sizeof(long) > 4)
+   div *= div * 10;
+   } else {
+   num = va_arg(va, unsigned int);
+   }
+
+   if (ch == 'd') {
+   if (islong && (long)num < 0) {
+   num = -(long)num;
+   out(info, '-');
+   } else if (!islong && (int)num < 0) {
+   num = -(int)num;
+   out(info, '-');
+   }
}
if (!num) {
out_dgt(info, 0);
} else {
-   for (div = 10; div; div /= 10)
+   for (; div; div /= 10)
div_out(info, , div);
}
break;
case 'x':
-

[U-Boot] [PATCH v4 06/26] move UL() macro from armv8/mmu.h into common.h

[Andre Przywara]

The UL() macro is pretty useful in sharing constants between assembly
and C files while still being able to specify a type for C.
Move the macro from an armv8 specific header into a common header file
to be able to use it by arm code (for instance) as well.

Signed-off-by: Andre Przywara 
Reviewed-by: Alexander Graf 
---
 arch/arm/include/asm/armv8/mmu.h |  8 
 include/common.h | 13 -
 2 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index aa0f3c4..e9b4cdb 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -8,14 +8,6 @@
 #ifndef _ASM_ARMV8_MMU_H_
 #define _ASM_ARMV8_MMU_H_
 
-#ifdef __ASSEMBLY__
-#define _AC(X, Y)  X
-#else
-#define _AC(X, Y)  (X##Y)
-#endif
-
-#define UL(x)  _AC(x, UL)
-
 /***/
 /*
  * The following definitions are related each other, shoud be
diff --git a/include/common.h b/include/common.h
index a8d833b..ee0436b 100644
--- a/include/common.h
+++ b/include/common.h
@@ -15,6 +15,9 @@ typedef volatile unsigned longvu_long;
 typedef volatile unsigned short vu_short;
 typedef volatile unsigned char vu_char;
 
+/* Allow sharing constants with type modifiers between C and assembly. */
+#define _AC(X, Y)   (X##Y)
+
 #include 
 #include 
 #include 
@@ -936,7 +939,12 @@ int cpu_disable(int nr);
 int cpu_release(int nr, int argc, char * const argv[]);
 #endif
 
-#endif /* __ASSEMBLY__ */
+#else  /* __ASSEMBLY__ */
+
+/* Drop a C type modifier (like in 3UL) for constants used in assembly. */
+#define _AC(X, Y)   X
+
+#endif /* __ASSEMBLY__ */
 
 #ifdef CONFIG_PPC
 /*
@@ -948,6 +956,9 @@ int cpu_release(int nr, int argc, char * const argv[]);
 
 /* Put only stuff here that the assembler can digest */
 
+/* Declare an unsigned long constant digestable both by C and an assembler. */
+#define UL(x)   _AC(x, UL)
+
 #ifdef CONFIG_POST
 #define CONFIG_HAS_POST
 #ifndef CONFIG_POST_ALT_LIST
-- 
2.8.2

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[U-Boot] [PATCH v4 05/26] SPL: tiny-printf: ignore "-" modifier

[Andre Przywara]

tiny-printf does not know about the "-" modifier, which aligns numbers.
This is used by some SPL code, but as it's purely cosmetical, we just
ignore this modifier here to avoid changing correct printf strings.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
---
 lib/tiny-printf.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 0b8512f..dfa8432 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -69,6 +69,9 @@ int _vprintf(struct printf_info *info, const char *fmt, 
va_list va)
bool islong = false;
 
ch = *(fmt++);
+   if (ch == '-')
+   ch = *(fmt++);
+
if (ch == '0') {
ch = *(fmt++);
lz = 1;
-- 
2.8.2

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[U-Boot] [PATCH v4 03/26] armv8: add lowlevel_init.S

[Andre Przywara]

For boards that call s_init() when the SPL runs, we are expected to
setup an early stack before calling this C function.
Implement the proper AArch64 version of this based on the ARMv7 code.
This allows sunxi boards to setup the basic peripherals even with a
64-bit SPL.

Signed-off-by: Andre Przywara 
Reviewed-by: Simon Glass 
---
 arch/arm/cpu/armv8/Makefile|  1 +
 arch/arm/cpu/armv8/lowlevel_init.S | 44 ++
 2 files changed, 45 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/lowlevel_init.S

diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index 28ba786..e780afc 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_S32V234) += s32v234/
 obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
 obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
 obj-$(CONFIG_ARMV8_PSCI) += psci.o
+obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o
diff --git a/arch/arm/cpu/armv8/lowlevel_init.S 
b/arch/arm/cpu/armv8/lowlevel_init.S
new file mode 100644
index 000..189e35f
--- /dev/null
+++ b/arch/arm/cpu/armv8/lowlevel_init.S
@@ -0,0 +1,44 @@
+/*
+ * A lowlevel_init function that sets up the stack to call a C function to
+ * perform further init.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+ENTRY(lowlevel_init)
+   /*
+* Setup a temporary stack. Global data is not available yet.
+*/
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+   ldr w0, =CONFIG_SPL_STACK
+#else
+   ldr w0, =CONFIG_SYS_INIT_SP_ADDR
+#endif
+   bic sp, x0, #0xf/* 16-byte alignment for ABI compliance */
+
+   /*
+* Save the old LR(passed in x29) and the current LR to stack
+*/
+   stp x29, x30, [sp, #-16]!
+
+   /*
+* Call the very early init function. This should do only the
+* absolute bare minimum to get started. It should not:
+*
+* - set up DRAM
+* - use global_data
+* - clear BSS
+* - try to start a console
+*
+* For boards with SPL this should be empty since SPL can do all of
+* this init in the SPL board_init_f() function which is called
+* immediately after this.
+*/
+   bl  s_init
+   ldp x29, x30, [sp]
+   ret
+ENDPROC(lowlevel_init)
-- 
2.8.2

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[U-Boot] [PATCH v4 01/26] sun6i: Restrict some register initialization to Allwinner A31 SoC

[Andre Przywara]

These days many Allwinner SoCs use clock_sun6i.c, although out of them
only the (original sun6i) A31 has a second MBUS clock register.
Also the requirement for setting up the PRCM PLL_CTLR1 register to provide
the proper voltage seems to be a property of older SoCs only as well.

Restrict the MBUS initialization to this SoC only to avoid writing bogus
values to (undefined) registers in other chips.
I can only verify that the PLL voltage setup is not needed for H3 and
A64, so for now we only spare those two SoCs.

Signed-off-by: Andre Przywara 
Reviewed-by: Alexander Graf 
Reviewed-by: Chen-Yu Tsai 
Reviewed-by: Simon Glass 
Acked-by: Maxime Ripard 
---
 arch/arm/mach-sunxi/clock_sun6i.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/clock_sun6i.c 
b/arch/arm/mach-sunxi/clock_sun6i.c
index ed8cd9b..80cfc0b 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -21,6 +21,8 @@ void clock_init_safe(void)
 {
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+#if !defined(CONFIG_MACH_SUN8I_H3) && !defined(CONFIG_MACH_SUN50I)
struct sunxi_prcm_reg * const prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
 
@@ -31,6 +33,7 @@ void clock_init_safe(void)
PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
clrbits_le32(>pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
+#endif
 
clock_set_pll1(40800);
 
@@ -41,7 +44,8 @@ void clock_init_safe(void)
writel(AHB1_ABP1_DIV_DEFAULT, >ahb1_apb1_div);
 
writel(MBUS_CLK_DEFAULT, >mbus0_clk_cfg);
-   writel(MBUS_CLK_DEFAULT, >mbus1_clk_cfg);
+   if (IS_ENABLED(CONFIG_MACH_SUN6I))
+   writel(MBUS_CLK_DEFAULT, >mbus1_clk_cfg);
 }
 #endif
 
-- 
2.8.2

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[U-Boot] [PATCH v4 02/26] armv8: prevent using THUMB

[Andre Przywara]

The predominantely 32-bit ARM targets try to compile the SPL in Thumb
mode to reduce code size.
The 64-bit AArch64 instruction set does not know an alternative, concise
encoding, so the Thumb build option should only be set for 32-bit
targets.
Likewise -marm machine options are only valid for ARMv7 targets.

Signed-off-by: Andre Przywara 
Reviewed-by: Alexander Graf 
Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
Acked-by: Maxime Ripard 
---
 arch/arm/lib/Makefile  | 2 ++
 include/configs/sunxi-common.h | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 0051f76..024139d 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -77,8 +77,10 @@ ifndef CONFIG_HAS_THUMB2
 
 # for C files, just apend -marm, which will override previous -mthumb*
 
+ifndef CONFIG_ARM64
 CFLAGS_cache.o := -marm
 CFLAGS_cache-cp15.o := -marm
+endif
 
 # For .S, drop -mthumb* and other thumb-related options.
 # CFLAGS_REMOVE_* would not have an effet, so AFLAGS_REMOVE_*
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index b0bfc0d..e05c318 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -35,7 +35,7 @@
 /*
  * High Level Configuration Options
  */
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64)
 #define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */
 #endif
 
-- 
2.8.2

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[U-Boot] [PATCH v4 00/26] sunxi: Allwinner A64: SPL support

[Andre Przywara]

Hi,

hopefully the final version of the SPL support series for the Allwinner A64
SoC. Actually no real code changes this time, just rebased on top of recent
master, adding some comments in patches 16/26 and 19/26 following Maxime's
suggestions and adding Acked-by:s and Reviewed-by:s.
I left the final patch 26/26 in for the sake of completeness, but don't expect
it to be merged. We need a clever solution to unify 32-bit and 64-bit board
configurations, but that shouldn't hold back this series for now.
Merging everything until and including patch 21/26 (sunxi: A64: enable SPL)
would be great, the other patches until 25/26 can go in as well, I think.

-
As the previous versions this one includes support for both AArch64 and
AArch32 SPL builds. The FIT support is still missing, which means the
functionality is limited. Due to the missing ARM Trusted Firmware (ATF)
in this firmware chain we lose Ethernet and SMP, among other minor things.
A full 64-bit build can be written to an SD card as expected and will
boot the U-Boot proper prompt. However Linux will crash on boot, as
PSCI is missing.
Building the 32-bit version of the SPL and combining this with an ATF
build and the 64-bit U-Boot proper allows to use FEL booting now:
# sunxi-fel spl sunxi-spl.bin write 0x4a00 u-boot-dtb.bin \
  write 0x44000 bl31.bin reset64 0x44000
This way of booting the board gives full functionality.

The first patch is a rather simple fix (with no changes to v2).
Patches 2-8 prepare the SPL code to be compiled for 64-bit in general and
AArch64 in particular.
Patches 9-11 refactor the existing boot0 header functionality to be used
by patch 12, which introduces the 64-bit switch in the first SPL
instructions.
Patches 13-20 then introduce the actual core of the SPL support: the DRAM
initialization, courtesy of Jens. This piggy backs on the existing
H3 DRAM code, deviating where needed. This has been reworked compared to
v2: I added a patch from Philipp to replace the rather uninspired
register writes in the MBUS priority setup function with some meaningful
code, explaining the various bits. Also the actual A64 DRAM code is no
longer #ifdef'ed into the H3 driver, but uses parameters to (static)
functions. The compiler detects this and removes the dead code from
the other variant, resulting in the same binary size for the H3.

Patch 21 finally enables the 64-bit SPL support. So now building the
existing pine64_plus_defconfig will generate a sunxi-spl.bin, which
can be prepended to the U-Boot proper image (not .bin) to boot from
an SD card. Due to the missing ATF support this is of limited usability
at the moment, though. Also FEL support requires more love - to switch
back to AArch32 before returning to FEL (without crashing, that is ;-),
so this is disabled.
On my setup this results in a 26KB SPL binary, which is close to the
28K limit mksunxiboot imposes at the moment. Adding anything (like
FIT support or DEBUG) will exceed this, and although I have patches
to let mksunxiboot get close to 32KB, this is the ulimate frontier.

So patches 22-25 then teach the SPL how to detect an U-Boot image file
of a different bitness and do the RMR switch from AArch32 to AArch64,
if needed.
This is used by the final patch 26, which creates another _defconfig
to let the SPL compile for AArch32 using the Thumb2 encoding. This
results in a binary of less than 17KB in my case, so has plenty of
room for extensions.

Cheers,
Andre.

Changelog v3 .. v4:
- rebased on top of latest HEAD
- add various Reviewed-by: and Acked-by: tags
- add comments about register bit meanings in non-ODT-setting fix
- clarify meaning of delay values in single bit delay support patch
- removing stray semicolons from boot0.h header

Changelog v2 .. v3:
- add various Reviewed-by: and Acked-by: tags
- split tiny-printf fix to handle "-" separately
- add various comments and extend commit messages
- add assembly file to re-create the embedded RMR switch code
- add patch 14/26 to explain the MBUS priority setup
- move DRAM r/w delay values into #defines to simplify re-usablity
- replace #ifdef'ed addition of A64 support to the H3 DRAM driver with an
  approach using static parameters

Changelog v1 .. v2:
- drop SPI build fix (already merged)
- confine A31 register init change to H3 and A64
- use IS_ENABLED() instead of #idef to guard MBUS2 clock init
- fix tiny-printf (proper sign extension for 32-bit integers)
- add "size" output in commit msg to document tiny-printf size impact
- fix sdelay(): use only one register, add "cc" clobber
- update RMR switch code to provide easy access to RVBAR register address
- drop redundant DRAM frequency setting from Pine64 defconfig
- minor changes as requested by reviewers

Andre Przywara (21):
  sun6i: Restrict some register initialization to Allwinner A31 SoC
  armv8: prevent using THUMB
  armv8: add lowlevel_init.S
  SPL: tiny-printf: add "l" modifier
  SPL: tiny-printf: ignore "-" modifier
  move UL() macro from armv8/mmu.h into 

[U-Boot] [PATCH] udoo: neo: Fix indentation

[Fabio Estevam]

From: Fabio Estevam 

The standard way is to put ifdef/endif in the very first column.

Signed-off-by: Fabio Estevam 
---
 board/udoo/neo/neo.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
index 688b522..288674a 100644
--- a/board/udoo/neo/neo.c
+++ b/board/udoo/neo/neo.c
@@ -349,9 +349,9 @@ int board_init(void)
/* Active high for ncp692 */
gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
 
-   #ifdef CONFIG_SYS_I2C_MXC
+#ifdef CONFIG_SYS_I2C_MXC
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, _pad_info1);
-   #endif
+#endif
 
return 0;
 }
-- 
2.7.4

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Re: [U-Boot] Missing SCSI block device connected to SATA adapter

[Michal Simek]

Hi Konstantin, + Ken

your colleague contacted me privately regarding similar stuff and he has
DM based driver. I think you should get in touch together to discuss this.

Thanks,
Michal


On 29.12.2016 16:45, Kostya Porotchkin wrote:
> Hello,
> 
> I am trying to use the new SCSI code with CONFIG_BLK=y on a Marvell board.
> I added CONFIG_DM_SCSI=y to my default configuration too.
> However "scsi reset" does not detect the connected hard disk since the 
> execution flow never entered the "uclass_foreach_dev" loop in scsi_scan() 
> function.
> My device is "UCLASS_AHCI" (arch/arm/mach-mvebu/sata.c) and calls ahci_init().
> Should I take any additional steps for being registered as a SCSI device too?
> 
> Thank you for help!
> Konstantin
> 
> U-Boot 2016.11-00446-g7b1402b-dirty (Dec 29 2016 - 17:44:24 +0200)
> 
> DRAM:  2 GiB
> Pre-reloc malloc() used 0x218 bytes (0 KB)
> Now running in RAM - U-Boot at: 7ff39000
> Comphy chip #0:
> Comphy-0: PEX0 
> Comphy-1: PEX0 
> Comphy-2: PEX0 
> Comphy-3: PEX0 
> Comphy-4: KR   
> Comphy-5: SATA1
> Comphy chip #1:
> Comphy-0: SGMII21.25 Gbps 
> Comphy-1: SATA0
> Comphy-2: USB3_HOST0   
> Comphy-3: SATA1
> Comphy-4: KR   
> Comphy-5: SGMII31.25 Gbps 
> UTMI PHY 0 initialized to USB Host0
> UTMI PHY 1 initialized to USB Host1
> UTMI PHY 2 initialized to USB Host0
> SATA link 0 timeout.
> Target spinup took 0 ms.
> AHCI 0001. 32 slots 2 ports 6 Gbps 0x3 impl SATA mode
> flags: 64bit ncq led only pmp fbss pio slum part sxs 
> MMC:   sdhci@6e: 0
> SF: Detected w25q32bv with page size 256 Bytes, erase size 4 KiB, total 4 MiB
> Model: MACCHIATOBin-8040
> Net:   No ethernet found.
> => 
> => scsi reset
> 
> Reset SCSI
> scanning bus for devices (DM)...
> Get UCLASS_SCSI - OK
> => dm tree
>  Class   Probed   Name
> 
>  root[ + ]root_driver
>  simple_bus  [ + ]|-- ap806
>  simple_bus  [ + ]|   `-- config-space
>  pinctrl [ + ]|   |-- ap-pinctl@6F4000
>  pinconfig   [   ]|   |   |-- i2c-pins-0
>  pinconfig   [ + ]|   |   `-- emmc-pins-0
>  gpio[   ]|   |-- gpio@6F5040
>  serial  [ + ]|   |-- serial@512000
>  mmc [ + ]|   `-- sdhci@6e
>  blk [   ]|   `-- sd...@6e.blk
>  simple_bus  [ + ]|-- cp110-master
>  simple_bus  [ + ]|   |-- config-space
>  pinctrl [   ]|   |   |-- cpm-pinctl@44
>  pinconfig   [   ]|   |   |   |-- cpm-i2c-pins-0
>  pinconfig   [   ]|   |   |   |-- cpm-i2c-pins-1
>  pinconfig   [   ]|   |   |   |-- cpm-ge-rgmii-pins-0
>  pinconfig   [   ]|   |   |   |-- cpm-pca0_pins
>  pinconfig   [   ]|   |   |   |-- cpm-sdhi-pins-0
>  pinconfig   [   ]|   |   |   `-- cpm-spi-pins-0
>  gpio[   ]|   |   |-- gpio@440100
>  gpio[   ]|   |   |-- gpio@440140
>  ahci[ + ]|   |   |-- sata@54
>  i2c [   ]|   |   |-- i2c@701000
>  i2c [   ]|   |   |-- i2c@701100
>  misc[ + ]|   |   `-- comphy@441000
>  pci [   ]|   `-- pcie@f260
>  simple_bus  [ + ]`-- cp110-slave
>  simple_bus  [ + ]`-- config-space
>  pinctrl [ + ]|-- cps-pinctl@44
>  pinconfig   [   ]|   |-- cps-ge-rgmii-pins-0
>  pinconfig   [ + ]|   `-- cps-spi-pins-1
>  gpio[   ]|-- gpio@440100
>  gpio[   ]|-- gpio@440140
>  ahci[   ]|-- sata@54
>  usb [   ]|-- usb3@50
>  spi [ + ]|-- spi@700680
>  spi_flash   [   ]|   `-- spi_flash@0:0
>  misc[ + ]`-- comphy@441000
> 

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[U-Boot] [PATCH] scsi: dm: Unbind all scsi based block devices before new scan

[Michal Simek]

New scan should unbind all block devices not to be listed again.
Without this patch if scsi reset or scan is called new block devices are
created which point to the same id and lun.

For example:
ZynqMP> scsi scan
scsi_scan: if_type=2, devnum=0: sd...@ff17.blk, 6, 0
scsi_scan: if_type=2, devnum=0: ahci@fd0c.id1lun0, 2, 0
scsi_scan: if_type=2, devnum=0: ahci@fd0c.id1lun0, 2, 1
scsi_scan: if_type=2, devnum=0: ahci@fd0c.id1lun0, 2, 2
scsi_scan: if_type=2, devnum=0: ahci@fd0c.id1lun0, 2, 3
scsi_scan: if_type=2, devnum=0: ahci@fd0c.id1lun0, 2, 4
scanning bus for devices...
  Device 0: (1:0) Vendor: ATA Prod.: KINGSTON SVP200S Rev: 501A
Type: Hard Disk
Capacity: 57241.8 MB = 55.9 GB (117231408 x 512)

Reported-by: Ken Ma 
Signed-off-by: Michal Simek 
---

 common/scsi.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/common/scsi.c b/common/scsi.c
index e7efa5ae797c..fb5b407f6b15 100644
--- a/common/scsi.c
+++ b/common/scsi.c
@@ -559,6 +559,8 @@ int scsi_scan(int mode)
if (mode == 1)
printf("scanning bus for devices...\n");
 
+   blk_unbind_all(IF_TYPE_SCSI);
+
ret = uclass_get(UCLASS_SCSI, );
if (ret)
return ret;
-- 
1.9.1

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