Re: [U-Boot] [PATCH] mpc5200: Correct return value of memcpy function

[Thomas Graziadei]

On 02/07/2017 05:59 PM, york sun wrote:

On 01/24/2017 05:41 AM, thomas.grazia...@omicronenergy.com wrote:

From: Mark Marshall 

The memcpy() function returns a pointer to trg.

Signed-off-by: Mark Marshall 
Reviewed-by: Thomas Graziadei 
---
  arch/powerpc/lib/memcpy_mpc5200.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/lib/memcpy_mpc5200.c 
b/arch/powerpc/lib/memcpy_mpc5200.c
index 75a3ef9..7e5a005 100644
--- a/arch/powerpc/lib/memcpy_mpc5200.c
+++ b/arch/powerpc/lib/memcpy_mpc5200.c
@@ -31,7 +31,7 @@ void *memcpy(void *trg, const void *src, size_t len)
extern void* __memcpy(void *, const void *, size_t);
char *s = (char *)src;
char *t = (char *)trg;
-   void *dest = (void *)src;
+   void *dest = (void *)trg;

/*
 * Check is source address is in flash:


Looks like this is a duplicated patch.

Yes this is a duplicate.


York

thanks,
Thomas
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Re: [U-Boot] [PATCH 2/3] armv8: fsl-lsch3: Update VID support

[Priyanka Jain]

> -Original Message-
> From: york sun
> Sent: Tuesday, February 07, 2017 10:38 PM
> To: Priyanka Jain ; u-boot@lists.denx.de
> Cc: Arpit Goel 
> Subject: Re: [PATCH 2/3] armv8: fsl-lsch3: Update VID support
> 
> On 01/29/2017 11:21 PM, Priyanka Jain wrote:
> >
> >
> >> -Original Message-
> >> From: york sun
> >> Sent: Friday, January 27, 2017 11:13 PM
> >> To: Priyanka Jain ; u-boot@lists.denx.de
> >> Cc: Arpit Goel 
> >> Subject: Re: [PATCH 2/3] armv8: fsl-lsch3: Update VID support
> >>
> >> On 01/18/2017 09:43 PM, Priyanka Jain wrote:
> >>> VID support in NXP layerscape Chassis-3 (lsch3) compilant SoCs like
> >>> LS2088A, LS2080A differs from existing logic.
> >>> -VDD voltage array is different
> >>> -Registers are different
> >>> -VDD calculation logic is different
> >>>
> >>> Add new function adjust_vdd() for LSCH3 compliant SoCs
> >>>
> >>> Signed-off-by: Priyanka Jain 
> >>> Signed-off-by: Arpit Goel 
> >>> ---
> >>>  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |4 +-
> >>>  board/freescale/common/vid.c   |  174 
> >>> ++--
> >>>  2 files changed, 164 insertions(+), 14 deletions(-)
> >>>
> >>> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> >>> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> >>> index 38a6d03..fc4d33b 100644
> >>> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> >>> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> >>> @@ -187,9 +187,9 @@ struct ccsr_gur {
> >>>   u32 gpporcr3;
> >>>   u32 gpporcr4;
> >>>   u8  res_030[0x60-0x30];
> >>> -#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT   25
> >>> +#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT   2
> >>>  #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK0x1F
> >>> -#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT20
> >>> +#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT7
> >>>  #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
> >>
> >>
> >> Priyanka,
> >>
> >> You changed the fuse register offset and fuse position in this and
> >> previous patch of this set. What's going on? I presume you have verified 
> >> it on
> LS2080ARDB.
> >> How did it work before? Do we have two fuse status registers?
> >>
> >> York
> >
> > York,
> >
> > These code changes are valid for both LS2080A and LS2088A.
> > VID was not working before on LS2080A also.
> >
> 
> I have to ask, does VID work now with this change set? Have you verified on
> both RDB and QDS? How about other SoCs in LSCH3 family?
> 
> York

We have verified VID support on LS2080AQDS, LS2080ARDB, LS2088AQDS, LS2080ARDB 
(all SoCs in upstream for which LSCH3 flag is applicable)

Priyanka
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[U-Boot] how to trigger DM rescan ?

[Hannes Schmelzer]

Hello,

i've following trouble on a new custom zynq board:

There is a axi4pcie root-complex implemented within the FPGA, i added 
this to my devicetree:


pci_express: axi-pcie@9000 {
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
status = "disabled";
compatible = "xlnx,axi-pcie-host-1.00.a";
reg = < 0x9000 0x100 >;
device_type = "pci";
interrupts = < 0 116 4 >;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 _intc 1>,
<0 0 0 2 _intc 2>,
<0 0 0 3 _intc 3>,
<0 0 0 4 _intc 4>;
ranges = < 0x0200 0 0x8000 0x8000 0 0x1000 >;

pcie_intc: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};

As you can see the node is "disabled". For me this makes sense since 
during very first come up of u-boot the FPGA is not configured yet and 
the registers of the root-complex aren't accessible.
Later on, during "board_init(...)" i bring up the FPGA (load bitstream 
from spi flash into FPGA) and set the fdt-node property status to "okay".


Trouble is that dm-scan, probe, ... is already done at this point and 
the root-complex is left ofter uninitialized and is not in the dm-tree 
at all (since it was disabled through first scan).


=> dm tree
 Class   Probed   Name

 root[ + ]root_driver
 simple_bus  [ + ]`-- amba
 gpio[ + ]|-- gpio@e000a000
 i2c [   ]|-- i2c@e0004000
 i2c [ + ]|-- i2c@e0005000
 i2c_generic [ + ]|   `-- generic_60
 serial  [ + ]|-- serial@e000
 serial  [   ]|-- serial@e0001000
 spi [ + ]|-- spi@e000d000
 spi_flash   [ + ]|   `-- spiflash@0
 eth [   ]|-- ethernet@e000b000
 mmc [ + ]|-- sdhci@e010
 blk [   ]|   `-- sd...@e010.blk
 mmc [ + ]|-- sdhci@e0101000
 blk [   ]|   `-- sd...@e0101000.blk
 simple_bus  [   ]|-- slcr@f800
 usb [   ]`-- usb@e0003000
=>

Is there a possibility to trigger a dm-scan after bringing up such new 
devices ?
Or is it the wrong way having the node "disabled" first and enabled it 
later ? are there better ways to prevent accessing not yet ready devices 
from access ?


many thanks for your help and
best regards,
Hannes



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Re: [U-Boot] [PATCH] drivers: net: phy: atheros: apply the previous register setting for AR8031 to fix the voltage peak issue

[Yung-Ching LIN]

On Tue, Feb 7, 2017 at 12:50 AM, Sekhar Nori  wrote:
> On Monday 06 February 2017 11:06 PM, Ken.Lin wrote:
>
 The register setting would turn out to be 0x3D47 on our project boards and
>>> our signal measurement results show the patch (v2 version,
>>> https://patchwork.ozlabs.org/patch/723461/)) could fix the voltage peak 
>>> issue.
 The proposed solution is to follow the implementation in previous commits,
>>> which include the reserved bits settings in SerDes Test and System Mode 
>>> Control
>>> register.
>
>>> So what does the register setting turn out to be with my patch below ?
>>>
>>> What are the "previous commits" you refer to ?
>
> Thanks for the references to the commits. You left out answering my
> question about what register settings you see with my patch.
>
> I have included another patch now with some debug enabled. Can you
> apply this patch to latest u-boot master, run on your board and send me
> the log ? Here is what I see on AM335x EVM-SK:
>
> U-Boot 2017.03-rc1-00058-g1216f9a0851f (Feb 07 2017 - 13:55:38 +0530)
>
> CPU  : AM335X-GP rev 1.0
> Model: TI AM335x EVM-SK
> DRAM:  256 MiB
> NAND:  0 MiB
> MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
> reading uboot.env
> ERROR: No USB device found
>
> at ../drivers/usb/gadget/ether.c:2709/usb_ether_init()
> Net:   ar8031_config: value read back 0x2c47, written: 0x2d47
> eth0: ethernet@4a10
> Hit any key to stop autoboot:  0
>
> Thanks,
> Sekhar
>
> ---8<---
> diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
> index b34cdd3d87dc..5c0a36676ce9 100644
> --- a/drivers/net/phy/atheros.c
> +++ b/drivers/net/phy/atheros.c
> @@ -28,12 +28,18 @@ static int ar8021_config(struct phy_device *phydev)
>
>  static int ar8031_config(struct phy_device *phydev)
>  {
> +   int regval;
> +
> if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
> phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
> phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
>   AR803x_DEBUG_REG_5);
> +   regval = phy_read(phydev, MDIO_DEVAD_NONE,
> + AR803x_PHY_DEBUG_DATA_REG);
> +   printf("%s: value read back 0x%x, written: 0x%x\n",
> +   __func__, regval, regval | 
> AR803x_RGMII_TX_CLK_DLY);
> phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
> - AR803x_RGMII_TX_CLK_DLY);
> + regval | AR803x_RGMII_TX_CLK_DLY);
> }
>
> if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
>



Hi ,

Your patch doesn't work for the issue case on our project board.
I added more debug messages for your reference.



diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 3304fddc69..e7a8680a7f 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -7,6 +7,7 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
+#define DEBUG

 #include 
 #include 
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index b34cdd3d87..0d9380f833 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -28,12 +28,22 @@ static int ar8021_config(struct phy_device *phydev)

 static int ar8031_config(struct phy_device *phydev)
 {
+   int regval;
+
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
  AR803x_DEBUG_REG_5);
+
+   regval = phy_read(phydev, MDIO_DEVAD_NONE,
+ AR803x_PHY_DEBUG_DATA_REG);
+
+   printf("%s: value read back 0x%x, written: 0x%x\n",
+   __func__, regval, regval |
+AR803x_RGMII_TX_CLK_DLY);
+
phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
- AR803x_RGMII_TX_CLK_DLY);
+ regval | AR803x_RGMII_TX_CLK_DLY);
}

if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
@@ -44,6 +54,21 @@ static int ar8031_config(struct phy_device *phydev)
  AR803x_RGMII_RX_CLK_DLY);
}

+
+#if 1
+phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
+  AR803x_DEBUG_REG_5);
+
+   regval = phy_read(phydev, MDIO_DEVAD_NONE,
+ AR803x_PHY_DEBUG_DATA_REG);
+




U-Boot 2017.03-rc1-00057-gc83a824e62-dirty (Feb 08 2017 - 02:54:43 +0800)

CPU:   Freescale i.MX6D rev1.5 at 792 MHz
Reset cause: POR
BOARD: General Electric B850v3
I2C:   ready
DRAM:  2 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
SF: Detected n25q32 with page size 256 Bytes, erase size 4 KiB, total 4 MiB
*** Warning - bad CRC, using default environment

In:serial
Out:   serial
Err:   serial
Net:   eth_init: fec_probe(bd, -1, 4) @ 02188000

[U-Boot] [PATCH 1/1] Enable IE (Key extention) Feature in LS2080A

[Udit Agarwal]

For validating images from uboot (Such as Kernel Image), either keys
from SoC fuses can be used or keys from a verified table of public keys
can be used. The latter feature is called IE Key Extension Feature.

On ls-ch3 platforms,IE table is validated by Bootrom and address of this
table is written in scratch registers 13 and 14 via PBI commands.

The procedure is to first verify IE table using Keys stored in fuses,
and then use the keys in this table to verify further images. So the steps
are:

1) Verify IE Table (If "IE Table Flag" set in any image
i.e. Verify IE Table only when any image needs IE Table's Key to be verified)
2) Install IE table. (To be used across verification of multiple images.
Stored in a static global structure.)
3) If IE flag enabled in header of any image, Use keys from IE table,
otherwise use keys tied up with SoC's fuses (SRK).

Signed-off-by: Aneesh Bansal 
Signed-off-by: Saksham Jain 
Signed-off-by: Udit Agarwal 
---
 arch/arm/include/asm/fsl_secure_boot.h |  6 +--
 board/freescale/common/fsl_validate.c  | 88 +++---
 include/fsl_validate.h | 24 +-
 3 files changed, 97 insertions(+), 21 deletions(-)

diff --git a/arch/arm/include/asm/fsl_secure_boot.h 
b/arch/arm/include/asm/fsl_secure_boot.h
index 27cf096..a612b7d 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -51,11 +51,11 @@
  * in boot ROM of the SoC.
  * The feature is only applicable in case of NOR boot and is
  * not applicable in case of RAMBOOT (NAND, SD, SPI).
+ * For LS, this feature is available for all device if IE Table
+ * is copied to XIP memory
+ * Also, for LS, ISBC doesn't verify this table.
  */
-#ifndef CONFIG_ESBC_HDR_LS
-/* Current Key EXT feature not available in LS ESBC Header */
 #define CONFIG_FSL_ISBC_KEY_EXT
-#endif
 
 #endif
 
diff --git a/board/freescale/common/fsl_validate.c 
b/board/freescale/common/fsl_validate.c
index 2b723a4..7396aa2 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -27,6 +27,10 @@
 #define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \
 ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \
 ((key_len) == 2 * KEY_SIZE_BYTES))
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+/* Global data structure */
+static struct fsl_secboot_glb glb;
+#endif
 
 /* This array contains DER value for SHA-256 */
 static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60,
@@ -60,7 +64,7 @@ self:
 #if defined(CONFIG_FSL_ISBC_KEY_EXT)
 static u32 check_ie(struct fsl_secboot_img_priv *img)
 {
-   if (img->hdr.ie_flag)
+   if (img->hdr.ie_flag & IE_FLAG_MASK)
return 1;
 
return 0;
@@ -119,7 +123,21 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
 }
 #endif
 
-static int get_ie_info_addr(u32 *ie_addr)
+#if defined(CONFIG_ESBC_HDR_LS)
+static int get_ie_info_addr(uintptr_t *ie_addr)
+{
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   /* For LS-CH3, the address of IE Table is
+* stated in Scratch13 and scratch14 of DCFG.
+* Bootrom validates this table while validating uboot.
+* DCFG is LE*/
+   *ie_addr = in_le32(>scratchrw[SCRATCH_IE_HIGH_ADR - 1]);
+   *ie_addr = *ie_addr << 32;
+   *ie_addr |= in_le32(>scratchrw[SCRATCH_IE_LOW_ADR - 1]);
+   return 0;
+}
+#else /* CONFIG_ESBC_HDR_LS */
+static int get_ie_info_addr(uintptr_t *ie_addr)
 {
struct fsl_secboot_img_hdr *hdr;
struct fsl_secboot_sg_table *sg_tbl;
@@ -147,16 +165,17 @@ static int get_ie_info_addr(u32 *ie_addr)
 
/* IE Key Table is the first entry in the SG Table */
 #if defined(CONFIG_MPC85xx)
-   *ie_addr = (sg_tbl->src_addr & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
-  flash_base_addr;
+   *ie_addr = (uintptr_t)((sg_tbl->src_addr &
+   ~(CONFIG_SYS_PBI_FLASH_BASE)) +
+   flash_base_addr);
 #else
-   *ie_addr = sg_tbl->src_addr;
+   *ie_addr = (uintptr_t)sg_tbl->src_addr;
 #endif
 
-   debug("IE Table address is %x\n", *ie_addr);
+   debug("IE Table address is %lx\n", *ie_addr);
return 0;
 }
-
+#endif /* CONFIG_ESBC_HDR_LS */
 #endif
 
 #ifdef CONFIG_KEY_REVOCATION
@@ -164,7 +183,10 @@ static int get_ie_info_addr(u32 *ie_addr)
 static u32 check_srk(struct fsl_secboot_img_priv *img)
 {
 #ifdef CONFIG_ESBC_HDR_LS
-   /* In LS, No SRK Flag as SRK is always present*/
+   /* In LS, No SRK Flag as SRK is always present if IE not present*/
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+   return !check_ie(img);
+#endif
return 1;
 #else
if (img->hdr.len_kr.srk_table_flag & SRK_FLAG)
@@ -253,14 +275,29 @@ static u32 read_validate_single_key(struct 
fsl_secboot_img_priv *img)
 #endif /* CONFIG_ESBC_HDR_LS */
 
 

Re: [U-Boot] [PATCH] drivers: net: phy: atheros: apply the previous register setting for AR8031 to fix the voltage peak issue

[Sekhar Nori]

On Wednesday 08 February 2017 12:36 AM, Yung-Ching LIN wrote:
> On Tue, Feb 7, 2017 at 12:50 AM, Sekhar Nori  wrote:
>> On Monday 06 February 2017 11:06 PM, Ken.Lin wrote:
>>
> The register setting would turn out to be 0x3D47 on our project boards and
 our signal measurement results show the patch (v2 version,
 https://patchwork.ozlabs.org/patch/723461/)) could fix the voltage peak 
 issue.
> The proposed solution is to follow the implementation in previous commits,
 which include the reserved bits settings in SerDes Test and System Mode 
 Control
 register.
>>
 So what does the register setting turn out to be with my patch below ?

 What are the "previous commits" you refer to ?
>>
>> Thanks for the references to the commits. You left out answering my
>> question about what register settings you see with my patch.
>>
>> I have included another patch now with some debug enabled. Can you
>> apply this patch to latest u-boot master, run on your board and send me
>> the log ? Here is what I see on AM335x EVM-SK:
>>
>> U-Boot 2017.03-rc1-00058-g1216f9a0851f (Feb 07 2017 - 13:55:38 +0530)
>>
>> CPU  : AM335X-GP rev 1.0
>> Model: TI AM335x EVM-SK
>> DRAM:  256 MiB
>> NAND:  0 MiB
>> MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
>> reading uboot.env
>> ERROR: No USB device found
>>
>> at ../drivers/usb/gadget/ether.c:2709/usb_ether_init()
>> Net:   ar8031_config: value read back 0x2c47, written: 0x2d47
>> eth0: ethernet@4a10
>> Hit any key to stop autoboot:  0
>>
>> Thanks,
>> Sekhar
>>
>> ---8<---
>> diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
>> index b34cdd3d87dc..5c0a36676ce9 100644
>> --- a/drivers/net/phy/atheros.c
>> +++ b/drivers/net/phy/atheros.c
>> @@ -28,12 +28,18 @@ static int ar8021_config(struct phy_device *phydev)
>>
>>  static int ar8031_config(struct phy_device *phydev)
>>  {
>> +   int regval;
>> +
>> if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
>> phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
>> phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
>>   AR803x_DEBUG_REG_5);
>> +   regval = phy_read(phydev, MDIO_DEVAD_NONE,
>> + AR803x_PHY_DEBUG_DATA_REG);
>> +   printf("%s: value read back 0x%x, written: 0x%x\n",
>> +   __func__, regval, regval | 
>> AR803x_RGMII_TX_CLK_DLY);
>> phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
>> - AR803x_RGMII_TX_CLK_DLY);
>> + regval | AR803x_RGMII_TX_CLK_DLY);
>> }
>>
>> if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
>>
> 
> 
> 
> Hi ,
> 
> Your patch doesn't work for the issue case on our project board.
> I added more debug messages for your reference.
> 

[...]

> 
> U-Boot 2017.03-rc1-00057-gc83a824e62-dirty (Feb 08 2017 - 02:54:43 +0800)
> 
> CPU:   Freescale i.MX6D rev1.5 at 792 MHz
> Reset cause: POR
> BOARD: General Electric B850v3
> I2C:   ready
> DRAM:  2 GiB
> MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
> SF: Detected n25q32 with page size 256 Bytes, erase size 4 KiB, total 4 MiB
> *** Warning - bad CRC, using default environment
> 
> In:serial
> Out:   serial
> Err:   serial
> Net:   eth_init: fec_probe(bd, -1, 4) @ 02188000
> fec_mii_setspeed: mii_speed 001a
> fec_mdio_read: phy: 04 reg:02 val:0x4d
> fec_mdio_read: phy: 04 reg:03 val:0xd074
> fec_mii_setspeed: mii_speed 001a
> fec_mdio_write: phy: 04 reg:00 val:0x8000
> fec_mdio_read: phy: 04 reg:00 val:0x0
> fec_mdio_write: phy: 04 reg:0d val:0x7
> fec_mdio_write: phy: 04 reg:0e val:0x8016
> fec_mdio_write: phy: 04 reg:0d val:0x4007
> fec_mdio_write: phy: 04 reg:0e val:0x18
> fec_mdio_write: phy: 04 reg:1d val:0x5
> fec_mdio_write: phy: 04 reg:1e val:0x100
> fec_mdio_write: phy: 04 reg:1d val:0x5
> fec_mdio_read: phy: 04 reg:1e val:0x100
> ar8031_config check: value read back 0x100, written: 0x100

Hmm, so in effect you are forced to use the magic value of 0x3c47 as the
reset default when actually it is 0x100 on your board. And there is no
backing public documentation on why the reset default should be 0x3c47.
And whether it will work for all boards that use this PHY.

Thats pretty unmaintainable in my opinion. If this value does not work
for the next person that comes along, we will be in trouble again.

I guess the best thing that can be done at this point is to use this
magic reset default value in a board specific way. By specifying it
using device-tree, perhaps. I would wait for some feedback from Joe
Hershberger though.

BTW, do you have the same problem in kernel ? Because AFAICS, even
drivers/net/phy/at803x.c in kernel does not have any such provision for
magic reset default values.

> fec_mdio_read: phy: 04 reg:04 val:0x1de1
> fec_mdio_write: phy: 04 reg:04 val:0x11e1
> fec_mdio_read: phy: 04 reg:01 val:0x7949
> 

Re: [U-Boot] [RFC PATCH 2/2] efi_loader: gop: add support to use cfb_console's framebuffer

[Simon Glass]

Hi,

On 7 February 2017 at 21:50, Icenowy Zheng  wrote:
>
> 2017年2月8日 10:44于 Bin Meng 写道：
>>
>> On Tue, Feb 7, 2017 at 8:58 PM, Icenowy Zheng  wrote:
>> > As cfb_console now can expose its GraphicDevice, use it in the
>> > implementation of EFI GOP protocol, so that the graphics framebuffer can
>> > be passed to EFI applications.
>> >
>> > Signed-off-by: Icenowy Zheng 
>> > ---
>> >
>> > Tested on an Allwinner H3 board with out-of-tree display support.
>> >
>> >  cmd/bootefi.c|  2 +-
>> >  lib/efi_loader/Makefile  |  1 +
>> >  lib/efi_loader/efi_gop.c | 29 -
>> >  3 files changed, 26 insertions(+), 6 deletions(-)
>> >
>>
>> Instead of adding support on legacy CFB console driver, can we use the
>> DM video driver instead?
>
> Many platforms are still using legacy video_hw_init, and may not have the 
> possibility to get ported...

Eventually these boads will be removed if they really don't get
converted. But we should not be adding new features to legacy code.
It's even worse when it is not added to the new code. How would anyone
ever upgrade? The new code becomes a backwater.

So please do this with driver model - ask for help if needed.

Regards,
Simon
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Re: [U-Boot] [PATCH 6/6] arm64: rk3399: add SPL support

[Simon Glass]

Hi Kever,

On 4 February 2017 at 19:01, Kever Yang  wrote:
> Hi Simon,
>
>
> On 01/26/2017 10:23 PM, Simon Glass wrote:
>>
>> Hi Kever,
>>
>> On 18 January 2017 at 05:16, Kever Yang  wrote:
>>>
>>> Add spl support for rk3399, default with of-platdata enabled.
>>>
>>> Signed-off-by: Kever Yang 
>>> ---
>>>
>>>   arch/arm/Kconfig  |   1 +
>>>   arch/arm/dts/rk3399-evb.dts   |   2 +
>>>   arch/arm/dts/rk3399.dtsi  |  44 +++
>>>   arch/arm/include/asm/arch-rockchip/clock.h|   3 +
>>>   arch/arm/mach-rockchip/Kconfig|   2 +
>>>   arch/arm/mach-rockchip/Makefile   |   1 +
>>>   arch/arm/mach-rockchip/rk3399-board-spl.c | 158
>>> ++
>>>   arch/arm/mach-rockchip/rk3399/syscon_rk3399.c |  40 +++
>>>   configs/evb-rk3399_defconfig  |  18 +++
>>>   include/configs/rk3399_common.h   |  11 ++
>>>   10 files changed, 280 insertions(+)
>>>   create mode 100644 arch/arm/mach-rockchip/rk3399-board-spl.c
>>
>> Reviewed-by: Simon Glass 
>>
>> But there is too much in this patch. Please split out the patches. My
>> suggestion:
>>
>> - syscon additions
>> - dts/dtsi additions
>> - arch/arm/Kconfig and include/configs changes
>> - board-spl.c stuff
>> - defconfig changes to enable everything
>>
>> So it should be possible to enable/disable SPL just in the final patch.
>
>
> Cc Tom here.
> I have some confuse for patch split in U-Boot, last time I see a patch set
> to init support
> for other SoC, patches split very detail and almost one patch for one
> module(like your comment
> in this patch), then Tom's comment says there is no need for that detail,
> only one patch for SoC
> and one patch for board is OK.
>
> My understand(for U-Boot) is:
> - driver patch is very clear and should be split out,
> - other parts like dts/defconfig and soc/board for one new SoC support,
>could be gather in one patch or two if there goes to the same maintainer
> and branch.
>
> The grf definition and clock driver has split out as your comment in my
> 'RFC' version,
> I can split this patch into 5 patches if you still required.

Well let's leave it for now, and keep it in mind for the future. It is
useful to split things up for easier review and also it allows us to
bisect / revert for problems more easily.

Regards,
Simon
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Re: [U-Boot] [PATCH 1/6] arm64: rk3399: add ddr controller driver

[Simon Glass]

+Tom in case you have some thoughts

Hi Kever,

On 4 February 2017 at 18:45, Kever Yang  wrote:
> Hi Simon,
>
> On 01/26/2017 10:23 PM, Simon Glass wrote:
>>
>> Hi Kever,
>>
>> On 18 January 2017 at 05:16, Kever Yang  wrote:
>>>
>>> RK3399 support DDR3, LPDDR3, DDR4 sdram, this patch is porting from
>>> coreboot, support 4GB lpddr3 in this version.
>>>
>>> Signed-off-by: Kever Yang 
>>> ---
>>>
>>>   arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi| 1536
>>> +
>>>   arch/arm/include/asm/arch-rockchip/sdram_rk3399.h |  120 ++
>>>   arch/arm/mach-rockchip/rk3399/Makefile|1 +
>>>   arch/arm/mach-rockchip/rk3399/sdram_rk3399.c  | 1243
>>> +
>>>   4 files changed, 2900 insertions(+)
>>>   create mode 100644 arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi
>>>   create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
>>>   create mode 100644 arch/arm/mach-rockchip/rk3399/sdram_rk3399.c
>>>
>> Change log?
>
>
> Sorry for missing change log, basically, I apply all the comments from you
> but
> MASK/SHIFT.
>
>>
>> Re your comments about MASK/SHIFT and register definitions, I'm not
>> convinced. In my case I set up a Python script to create the registers
>> (with the MASK set incorrectly unfortunately) and did something like
>> this:
>>
>> pdftotext -layout  -f 130 -l 350 rk3288-fs.pdf /tmp/asc
>> tools/rkmux.py /tmp/asc GRF_GPIO4C_IOMUX
>>
>> to generate the definitions. Does that help?
>
>
> Is not only header file need to update, but also almost all the register
> operation in C source code.

Yes that's right.

>>
>>
>> My concern is that if we don't write a good quality driver now, when
>> will it be updated/fixed? It seems better to do it now. Is it really a
>> lot of work?
>
>
> I agree that we should write a good quality driver, but it does not mean
> the quality is not good if I don't include SHIFT in MASK, right?
> I would like to include the SHIFT in MASK if this is the first time for
> the driver commit to public as the requirement from maintainer,
> but this is porting from coreboot which has prove to be a good quality
> driver
> with a lot of test.
> Another point is that in order to make it easier to maintain the source
> code,
> we have already sync our internal source code to the copy on coreboot, it's
> really not convenient for the driver owner(not me, there are other guys
> focus
> on dram drivers) to maintain all these drivers in different platform.
> And here comes another question, what should we do for next SoC driver
> if we need to upstream the driver to coreboot and U-Boot, and maybe UEFI,
> make totally different format version for different platform? I think try to
> convince some of the maintainer should be the best choice and then we can
> focus on maintain the same one copy of source code, right?
>
> Back to U-Boot, I don't the format of MASK is so important, just like no
> more
> than 80-bytes in one line in coding style, we should consider to accept it
> if
> there are some reason. There are also many MASKs in U-Boot drivers without
> SHIFT in it, I wouldn't say which kind is better, but U-Boot can say prefer
> to
> use MASKs with SHIFT, but please don't refuse everything other than that.

Well we can leave the MASK to not include the SHIFT. That was my
mistake originally so perhaps I should clean it up.

But this sort of thing:

> +#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16)))
> +#define SYS_REG_DEC_DBW(n, ch) (2 >> ((n >> (0 + 16 * ch)) & 0x3))

is really not nice IMO, particularly for something that is only used
once in the C code. Does coreboot actually require this style, or
could it use the more explicit SHIFT/MASK used like U-Boot?

I do understand the problem of multiple platforms but in general each
project has its own code style and we try to stick to it. U-Boot
follows kernel style pretty closely, but it is try that SHIFT/MASK
things are much more common in U-Boot than Linux since it sets up
hardware.

Re keeping the drivers in sync, yes it is a pain. But I hope that it
becomes easier to maintain. There is a pretty big user community
around U-Boot, and Rockchip is a popular chip. So I'm trying to keep
it as a good example of how to do things.

So I'd really like to change this.

Regards,
Simon

>
> Thanks,
> - Kever
>
>
>>
>>> diff --git a/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi
>>> b/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi
>>> new file mode 100644
>>> index 000..5568be2
>>> --- /dev/null
>>> +++ b/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi
>>> @@ -0,0 +1,1536 @@
>>> +/*
>>> + * (C) Copyright 2016 Rockchip Electronics Co., Ltd
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0+
>>> + */
>>> +
>>> + {
>>> +   rockchip,sdram-params = <
>>> +   0x2
>>> +   0xA
>>
>> Can you use lower-case hex please?
>>
>>> +   0x3
>>> +   

Re: [U-Boot] [PATCH 0/6] rk3399: enable SPL driver

[Simon Glass]

Hi Kever,

On 4 February 2017 at 17:41, Kever Yang  wrote:
> Hi Simon,
>
> On 01/24/2017 09:51 PM, Simon Glass wrote:
>
> Hi Kever,
>
> On 18 January 2017 at 05:16, Kever Yang  wrote:
>> This series patch enable basic driver for rk3399 SPL, the ATF support
>> has been split as a separate patch.
>>
>> SPL_OF_PLATDATA is consider to be must because the dram driver has much
>> configuration parameter from dts, but we don't want to do the copy.
>>
>> Other driver like clock, pinctrl, sdhci has update to support
>> OF-PLATDATA.
>>
>>
>>
>> Kever Yang (6):
>> arm64: rk3399: add ddr controller driver
>> arm64: rk3399: move grf register definitions to grf_rk3399.h
>> clk: rk3399: update driver for spl
>> sdhci: rk3399: update driver to support of-platdata
>> pinctrl: rk3399: add the of-platdata support
>> arm64: rk3399: add SPL support
>
> What is the limit in SPL size on rk3399?
>
>
> rk3399 has 192KB internal SRAM, the bootrom use the first 8K,
> so the SPL size limit should be 184KB.

The of-platdata feature is intended for highly constrained devices
where there is not enough SRAM for libfdt. To me it does not seem
worth the pain of using it for this chip, which has plenty of SRAM.

Regards,
Simon
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Re: [U-Boot] of-platdata address map decode for 64-bits

[Simon Glass]

Hi Kever,

On 4 February 2017 at 16:30, Kever Yang  wrote:
> Hi Simon,
>
> For rk3399, the data for sdram driver in dts is big, I don't want to do
> the copy for it,

Are you referring to the call to fdtdec_get_int_array()? Don't you
have heaps of SRAM though? So why does it matter? If you are really
worried about it you could loop through the data word by word instead.
But why?

> so I think use of-platdata is a good method, and for image size, its
> smaller, then it's sooner to load.

Yes it reduces the image size, but only by a small amount. I have not
checked it on ARM64 but it should be around 5KB. I don't think it is
very important.

Regards,
Simon


>
> Thanks,
> - Kever
>
> On 01/26/2017 10:22 PM, Simon Glass wrote:
>>
>> Hi Kever,
>>
>> On 17 January 2017 at 23:37, Kever Yang  wrote:
>>>
>>> Hi Simon,
>>>
>>>  For my rk3399(64bit) dts, the address is described as below:
>>> #address-cells = <2>;
>>> reg = <0x0 0xfe32 0x0 0x4000>;
>>>
>>> not like 32-bit soc which reg address describe like:
>>> reg = <0xfe32 0x4000>;
>>>
>>>  There should have some update for this dts decode, right?
>>> like:
>>> map_sysmem()
>>> regmap_init_mem_platdata()
>>>
>>>  Do you have a idea to update all these kind of function call?
>>> It will be very great if you can send a patch for it.
>>>
>>> Thanks,
>>> - Kever
>>>
>> Yes I think so.
>>
>> But first I'd like to understand why we need to use of-platdata on
>> this very modern SoC. Can you tell me the maximum SPL size you can
>> support on this SoC? I thought you had removed the 30KB limit?
>>
>> Using of-platdata only saves 3-4KB.
>>
>> Regards,
>> Simon
>>
>>
>>
>
>
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Re: [U-Boot] [PATCH 2/2] dts: rk3288: change the dmc configuration to LPDDR3

[Simon Glass]

Hi Eddie,

On 17 January 2017 at 21:51, Eddie Cai  wrote:
> Thanks Kever
> Hi Simon
>
> I did some search and found you acked the Jacob's patch, see [0]. But didn't
> apply it. Did you lost this patch?
>
> [0]https://patchwork.ozlabs.org/patch/694820/

Yes I did - will reply on that thread.

Regards,
Simon
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Re: [U-Boot] [PATCH 1/3] dts: rk3288: correct sdram setting for miniarm

[Simon Glass]

On 10 January 2017 at 06:44, Jacob Chen  wrote:
>
> 2016-11-18 9:13 GMT+08:00 Simon Glass :
> > On 14 November 2016 at 21:01, Jacob Chen  wrote:
> >> miniarm board use lpddr3
> >>
> >> Signed-off-by: Jacob Chen 
> >> ---
> >>
> >>  arch/arm/dts/rk3288-miniarm.dts | 16 
> >>  1 file changed, 8 insertions(+), 8 deletions(-)
> >
> > Acked-by: Simon Glass 
> > ___
> > U-Boot mailing list
> > U-Boot@lists.denx.de
> > http://lists.denx.de/mailman/listinfo/u-boot
>
>
> Hi,
>
> Sorry for sending patch in disorder. It seems this patch have been ignored.

Yes I marked it superseded. It looks like I was confused by your patch series.

See 
http://patchwork.ozlabs.org/project/uboot/list/?submitter=69649=*==both=

It looks like you sent a v2 series, but left out this patch and I
didn't notice. Anyway:

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [U-boot] [PATCH 2/2] rockchip: firefly: configs: use spl back to brom

[Simon Glass]

On 20 January 2017 at 19:51, Simon Glass  wrote:
> On 16 January 2017 at 21:19, Jacob Chen  wrote:
>> Keep it same with other boards otherwise i have to write special script for 
>> it..
>>
>> Signed-off-by: Jacob Chen 
>> ---
>>
>>  configs/firefly-rk3288_defconfig | 2 +-
>>  include/configs/firefly-rk3288.h | 5 -
>>  2 files changed, 1 insertion(+), 6 deletions(-)
>
> Reviewed-by: Simon Glass 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [PATCH] rockchip: Correct MAINTAINER entry for chromebook_minnie

[Simon Glass]

On 14 January 2017 at 09:26, Simon Glass  wrote:
> This is wrong at present, so genboardscfg.py gives the following warnings:
>
> WARNING: no status info for 'chromebook_minnie'
> WARNING: no maintainers for 'chromebook_minnie'
>
> Fix it.
>
> Signed-off-by: Simon Glass 
> ---
>
>  board/google/veyron/MAINTAINERS | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Applied to u-boot-rockchip
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Re: [U-Boot] [PATCH 2/2] rockchip: Enable ETH address randomization for the firefly-rk3288

[Simon Glass]

On 20 January 2017 at 19:51, Simon Glass  wrote:
> On 17 January 2017 at 02:32, Romain Perier  
> wrote:
>> This commit enables ethernet MAC address randomization on the
>> firefly-rk3288. It removes the error at startup 'ethernet@ff29
>> address not set'.
>>
>> Signed-off-by: Romain Perier 
>> ---
>>  configs/firefly-rk3288_defconfig | 1 +
>>  1 file changed, 1 insertion(+)
>
> Reviewed-by: Simon Glass 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [U-boot] [PATCH 1/2] rockchip: configs: move env offset to common header

[Simon Glass]

On 20 January 2017 at 19:51, Simon Glass  wrote:
> On 16 January 2017 at 21:19, Jacob Chen  wrote:
>> To reduce redundant code.
>>
>> Signed-off-by: Jacob Chen 
>> ---
>>
>>  include/configs/evb_rk3288.h  | 14 --
>>  include/configs/fennec_rk3288.h   | 14 --
>>  include/configs/kylin_rk3036.h| 14 --
>>  include/configs/miniarm_rk3288.h  | 14 --
>>  include/configs/popmetal_rk3288.h | 14 --
>>  include/configs/rock2.h   | 14 --
>>  include/configs/rockchip-common.h | 14 ++
>>  7 files changed, 14 insertions(+), 84 deletions(-)
>
> Reviewed-by: Simon Glass 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [PATCH] simple-bus: enable suport for of-platdata

[Simon Glass]

Hi Kever,

On 4 February 2017 at 17:24, Kever Yang  wrote:
>
> Hi Simon,
>
> Found 1 typo on the subject, 'suport' should be 'support',
> do I need to send a new patch or you can correct it when you apply?

I can correct it when I apply, should be soon.

- Simon

>
> Thanks,
> - Kever
>
> On 01/26/2017 10:23 PM, Simon Glass wrote:
>>
>> On 18 January 2017 at 05:25, Kever Yang  wrote:
>>>
>>> Just do nothing in post_bind if of-platdata enabled,
>>> for there is no dm_scan_fdt_dev().
>>>
>>> Signed-off-by: Kever Yang 
>>> ---
>>>
>>>   drivers/core/simple-bus.c | 4 
>>>   1 file changed, 4 insertions(+)
>>
>> Reviewed-by: Simon Glass 
>>
>>
>>
>
>
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Re: [U-Boot] [PATCH] nand: atmel: add drvice tree support and dm gpio APIs

[Simon Glass]

Hi Wenyou,

On 3 February 2017 at 18:32, Wenyou Yang  wrote:
>
> In order to use the driver model gpio APIs, add the device tree
> support.
>
> Signed-off-by: Wenyou Yang 
> ---
>
>  drivers/mtd/nand/atmel_nand.c | 143 
> ++
>  include/fdtdec.h  |   1 +
>  lib/fdtdec.c  |   1 +
>  3 files changed, 119 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
> index 8669432deb..87ff5c2eb4 100644
> --- a/drivers/mtd/nand/atmel_nand.c
> +++ b/drivers/mtd/nand/atmel_nand.c
> @@ -14,29 +14,34 @@
>  #include 
>  #include 
>  #include 
> +#ifdef CONFIG_DM_GPIO
> +#include 
> +#endif
>
> +#include 
>  #include 
>  #include 
>  #include 
>  #include 
>
> -#ifdef CONFIG_ATMEL_NAND_HWECC
> -
> -/* Register access macros */
> -#define ecc_readl(add, reg)\
> -   readl(add + ATMEL_ECC_##reg)
> -#define ecc_writel(add, reg, value)\
> -   writel((value), add + ATMEL_ECC_##reg)

What is happening here? Seems like it should be a separate patch.

> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct atmel_nand_data {
> +   struct gpio_desc enable_pin;/* chip enable */
> +   struct gpio_desc det_pin;   /* card detect */
> +   struct gpio_desc rdy_pin;   /* ready/busy */
> +   u8  ale;/* address line number connected to ALE */
> +   u8  cle;/* address line number connected to CLE */
> +   u8  bus_width_16;   /* buswidth is 16 bit */
> +   u8  ecc_mode;   /* ecc mode */
> +   u8  on_flash_bbt;   /* bbt on flash */
> +};
>
> -#include "atmel_nand_ecc.h"/* Hardware ECC registers */
> +struct atmel_nand_host {
> +   void __iomem*io_base;
> +   struct atmel_nand_data  board;
>
>  #ifdef CONFIG_ATMEL_NAND_HW_PMECC
> -
> -#ifdef CONFIG_SPL_BUILD
> -#undef CONFIG_SYS_NAND_ONFI_DETECTION
> -#endif
> -
> -struct atmel_nand_host {
> struct pmecc_regs __iomem *pmecc;
> struct pmecc_errloc_regs __iomem *pmerrloc;
> void __iomem*pmecc_rom_base;
> @@ -63,9 +68,26 @@ struct atmel_nand_host {
> int *pmecc_mu;
> int *pmecc_dmu;
> int *pmecc_delta;
> +#endif
>  };
>
> -static struct atmel_nand_host pmecc_host;
> +static struct atmel_nand_host nand_host;
> +#ifdef CONFIG_ATMEL_NAND_HWECC
> +
> +/* Register access macros */
> +#define ecc_readl(add, reg)\
> +   readl(add + ATMEL_ECC_##reg)
> +#define ecc_writel(add, reg, value)\
> +   writel((value), add + ATMEL_ECC_##reg)
> +
> +#include "atmel_nand_ecc.h"/* Hardware ECC registers */
> +
> +#ifdef CONFIG_ATMEL_NAND_HW_PMECC
> +
> +#ifdef CONFIG_SPL_BUILD
> +#undef CONFIG_SYS_NAND_ONFI_DETECTION
> +#endif
> +
>  static struct nand_ecclayout atmel_pmecc_oobinfo;
>
>  /*
> @@ -805,12 +827,9 @@ static uint16_t *create_lookup_table(int sector_size)
>  static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
> struct mtd_info *mtd)
>  {
> -   struct atmel_nand_host *host;
> +   struct atmel_nand_host *host = nand_get_controller_data(nand);
> int cap, sector_size;
>
> -   host = _host;
> -   nand_set_controller_data(nand, host);
> -
> nand->ecc.mode = NAND_ECC_HW;
> nand->ecc.calculate = NULL;
> nand->ecc.correct = NULL;
> @@ -1207,12 +1226,24 @@ int atmel_hwecc_nand_init_param(struct nand_chip 
> *nand, struct mtd_info *mtd)
>  #endif /* CONFIG_ATMEL_NAND_HWECC */
>
>  static void at91_nand_hwcontrol(struct mtd_info *mtd,
> -int cmd, unsigned int ctrl)
> +   int cmd, unsigned int ctrl)
>  {
> struct nand_chip *this = mtd_to_nand(mtd);
> +#if CONFIG_IS_ENABLED(OF_CONTROL)
> +   struct atmel_nand_host *host = nand_get_controller_data(this);
> +#endif
>
> if (ctrl & NAND_CTRL_CHANGE) {
> -   ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
> +   ulong IO_ADDR_W = (ulong)this->IO_ADDR_W;
> +#if CONFIG_IS_ENABLED(OF_CONTROL)
> +   IO_ADDR_W &= ~((1 << host->board.ale)
> +| (1 << host->board.cle));
> +
> +   if (ctrl & NAND_CLE)
> +   IO_ADDR_W |= (1 << host->board.cle);
> +   if (ctrl & NAND_ALE)
> +   IO_ADDR_W |= (1 << host->board.ale);
> +#else
> IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
>  | CONFIG_SYS_NAND_MASK_CLE);

You could adjust it so that CONFIG_SYS_NAND_MASK_CLE is assigned to
host->board.cle in the init function, and then avoid this #ifdef here.

>
> @@ -1220,10 +1251,18 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
> IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
>   

Re: [U-Boot] [RFC PATCH 2/2] efi_loader: gop: add support to use cfb_console's framebuffer

[Icenowy Zheng]

2017年2月8日 10:44于 Bin Meng 写道：
>
> On Tue, Feb 7, 2017 at 8:58 PM, Icenowy Zheng  wrote: 
> > As cfb_console now can expose its GraphicDevice, use it in the 
> > implementation of EFI GOP protocol, so that the graphics framebuffer can 
> > be passed to EFI applications. 
> > 
> > Signed-off-by: Icenowy Zheng  
> > --- 
> > 
> > Tested on an Allwinner H3 board with out-of-tree display support. 
> > 
> >  cmd/bootefi.c    |  2 +- 
> >  lib/efi_loader/Makefile  |  1 + 
> >  lib/efi_loader/efi_gop.c | 29 - 
> >  3 files changed, 26 insertions(+), 6 deletions(-) 
> > 
>
> Instead of adding support on legacy CFB console driver, can we use the 
> DM video driver instead? 

Many platforms are still using legacy video_hw_init, and may not have the 
possibility to get ported...

>
> Regards, 
> Bin 
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Re: [U-Boot] [PATCH] armv8/fsl-layerscape: fdt: remove SYSCLK frequency fixup for ls1012a

[york sun]

On 02/07/2017 07:30 PM, Y.B. Lu wrote:
>> -Original Message-
>> From: york sun
>> Sent: Wednesday, February 08, 2017 1:03 AM
>> To: Scott Wood; Y.B. Lu; u-boot@lists.denx.de
>> Cc: Albert Aribaud; Z.Q. Hou
>> Subject: Re: [U-Boot] [PATCH] armv8/fsl-layerscape: fdt: remove SYSCLK
>> frequency fixup for ls1012a
>>
>> On 01/20/2017 05:13 PM, york sun wrote:
>>>
>>> Then a proper fix would be check the clock name or compatible. If none
>>> of them exists, we should fix the device tree first.
>>
>> Yangbo,
>>
>> Can you fix the code to check clock name or compatible?
>>
>> York
>
> [Lu Yangbo-B47093] Hi York, do you mean check the clock name or compatible to 
> make sure it's sysclk and then fix it?
> Scott's patch added coreclock node also with compatible 'fixed-clock'.
> https://patchwork.kernel.org/patch/9536515/
>
> If we check clock name, I found most names with 'fixed-clock' compatible are 
> 'sysclk', but some are not.
> fsl-ls1012a-frdm.dts:
> sys_mclk: clock-mclk {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> clock-frequency = <2500>;
> };
>
> fsl-ls1012a-qds.dts:
> sys_mclk: clock-mclk {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> clock-frequency = <24576000>;
> };
>

Clearly "fixed-clock" is not a good compatible string to search for. It 
just tells you this clock is fixed in frequency. It doesn't tell you if 
a clock is system clock.

Can you find this clock by its name? If you need to unify the device 
tree, it may be the time now.

York
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Re: [U-Boot] [PATCH] armv8/fsl-layerscape: fdt: remove SYSCLK frequency fixup for ls1012a

[Y.B. Lu]

> -Original Message-
> From: york sun
> Sent: Wednesday, February 08, 2017 1:03 AM
> To: Scott Wood; Y.B. Lu; u-boot@lists.denx.de
> Cc: Albert Aribaud; Z.Q. Hou
> Subject: Re: [U-Boot] [PATCH] armv8/fsl-layerscape: fdt: remove SYSCLK
> frequency fixup for ls1012a
> 
> On 01/20/2017 05:13 PM, york sun wrote:
> >
> > Then a proper fix would be check the clock name or compatible. If none
> > of them exists, we should fix the device tree first.
> 
> Yangbo,
> 
> Can you fix the code to check clock name or compatible?
> 
> York

[Lu Yangbo-B47093] Hi York, do you mean check the clock name or compatible to 
make sure it's sysclk and then fix it?
Scott's patch added coreclock node also with compatible 'fixed-clock'.
https://patchwork.kernel.org/patch/9536515/

If we check clock name, I found most names with 'fixed-clock' compatible are 
'sysclk', but some are not.
fsl-ls1012a-frdm.dts:
sys_mclk: clock-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <2500>;
};

fsl-ls1012a-qds.dts:
sys_mclk: clock-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};

Do you have any suggestion?
Thanks.


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Re: [U-Boot] [PATCH v2] Add single register pin controller driver

[Masahiro Yamada]

Hi.



2017-02-07 22:30 GMT+09:00 Felix Brack :

> +
> +static int single_set_state_simple(struct udevice *dev,
> +  struct udevice *periph)
> +{
> +   const void *fdt = gd->fdt_blob;
> +   const struct single_fdt_pin_cfg *prop;
> +   int len;
> +
> +   prop = fdt_getprop(fdt, periph->of_offset, "pinctrl-single,pins", 
> );


This seems wrong to me.


The "periph" is a peripheral device (like UART, eMMC, USB, etc.).

So, you are parsing the "pinctrl-single,pins" property
in the peripheral device, like

uart: uart {

  pinctrl-single,pins = <
  .
  >;

};




In pinctrl, peripheral nodes should have a phandle to a child of the
pinctrl device.
As you see Linux, the DT should look like this:


 uart: uart {

   pinctrl-0 = <_pins>;

};


pinctrl {

   uart_pins: uart_pins {
  pinctrl-single,pins = <
   
  >;
   };

 };






-- 
Best Regards
Masahiro Yamada
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Re: [U-Boot] [RFC PATCH 2/2] efi_loader: gop: add support to use cfb_console's framebuffer

[Bin Meng]

On Tue, Feb 7, 2017 at 8:58 PM, Icenowy Zheng  wrote:
> As cfb_console now can expose its GraphicDevice, use it in the
> implementation of EFI GOP protocol, so that the graphics framebuffer can
> be passed to EFI applications.
>
> Signed-off-by: Icenowy Zheng 
> ---
>
> Tested on an Allwinner H3 board with out-of-tree display support.
>
>  cmd/bootefi.c|  2 +-
>  lib/efi_loader/Makefile  |  1 +
>  lib/efi_loader/efi_gop.c | 29 -
>  3 files changed, 26 insertions(+), 6 deletions(-)
>

Instead of adding support on legacy CFB console driver, can we use the
DM video driver instead?

Regards,
Bin
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Re: [U-Boot] [PATCH] fsl-layerscape/ppa: cleanup ppa.h

[Z.Q. Hou]

Hi York,

Thanks a lot for your comments!

> -Original Message-
> From: york sun
> Sent: 2017年2月8日 0:32
> To: Z.Q. Hou ; u-boot@lists.denx.de; Mingkai Hu
> ; Prabhakar Kushwaha
> 
> Subject: Re: [PATCH] fsl-layerscape/ppa: cleanup ppa.h
> 
> On 02/05/2017 07:41 PM, Zhiqiang Hou wrote:
> > From: Hou Zhiqiang 
> >
> > Moved the ifdef into ppa.h and removed the duplicated macros.
> >
> > Signed-off-by: Hou Zhiqiang 
> > ---
> >  arch/arm/include/asm/arch-fsl-layerscape/ppa.h | 7 ++-
> >  arch/arm/include/asm/armv8/sec_firmware.h  | 4 
> >  board/freescale/ls1043ardb/ls1043ardb.c| 2 --
> >  3 files changed, 2 insertions(+), 11 deletions(-)
> >
> 
> Zhiqiang,
> 
> There are other places (ls1012a boards) ppa.h is included with #ifdef.
> Can they be cleaned up as well?
> 

Yes, they can.

Thanks,
Zhiqiang
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Re: [U-Boot] [PATCH] board: freescale: ls2080a: Intergrate and enable PPA on LS2080A

[york sun]

On 01/04/2017 02:14 PM, york sun wrote:
> On 12/29/2016 10:01 PM, Prabhakar Kushwaha wrote:
>>
>>> -Original Message-
>>> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Abhimanyu
>>> Saini
>>> Sent: Thursday, December 29, 2016 9:52 AM
>>> To: york sun ; u-boot@lists.denx.de
>>> Cc: Priyanka Jain 
>>> Subject: [U-Boot] [PATCH] board: freescale: ls2080a: Intergrate and enable 
>>> PPA
>>> on LS2080A
>>>
>>> Integrate and enable PPA on LS2080ARDB, LS2080AQDS, LS2088ARDB
>>> and LS2088AQDS boards.
>>>
>>> Signed-off-by: Abhimanyu Saini 
>>> ---
>>>  board/freescale/ls2080aqds/ls2080aqds.c |  6 ++
>>>  board/freescale/ls2080ardb/ls2080ardb.c |  6 ++
>>>  include/configs/ls2080aqds.h| 10 ++
>>>  include/configs/ls2080ardb.h| 10 ++
>>>  4 files changed, 32 insertions(+)
>>>
>>> diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
>>> b/board/freescale/ls2080aqds/ls2080aqds.c
>>> index 73a61fd..811b9a6 100644
>>> --- a/board/freescale/ls2080aqds/ls2080aqds.c
>>> +++ b/board/freescale/ls2080aqds/ls2080aqds.c
>>> @@ -19,6 +19,9 @@
>>>  #include 
>>>  #include 
>>>  #include 
>>> +#ifdef CONFIG_FSL_LS_PPA
>>> +#include 
>>> +#endif
>>>
>>>  #include "../common/qixis.h"
>>>  #include "ls2080aqds_qixis.h"
>>> @@ -223,6 +226,9 @@ int board_init(void)
>>>  #endif
>>> select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
>>> rtc_enable_32khz_output();
>>> +#ifdef CONFIG_FSL_LS_PPA
>>> +   ppa_init();
>>> +#endif
>>>
>>> return 0;
>>>  }
>>> diff --git a/board/freescale/ls2080ardb/ls2080ardb.c
>>> b/board/freescale/ls2080ardb/ls2080ardb.c
>>> index 02954ef..339fa78 100644
>>> --- a/board/freescale/ls2080ardb/ls2080ardb.c
>>> +++ b/board/freescale/ls2080ardb/ls2080ardb.c
>>> @@ -19,6 +19,9 @@
>>>  #include 
>>>  #include 
>>>  #include 
>>> +#ifdef CONFIG_FSL_LS_PPA
>>> +#include 
>>> +#endif
>>>
>>>  #include "../common/qixis.h"
>>>  #include "ls2080ardb_qixis.h"
>>> @@ -184,6 +187,9 @@ int board_init(void)
>>> /* invert AQR405 IRQ pins polarity */
>>> out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
>>>  #endif
>>> +#ifdef CONFIG_FSL_LS_PPA
>>> +   ppa_init();
>>> +#endif
>>>
>>> return 0;
>>>  }
>>> diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
>>> index 838568f..5573e94 100644
>>> --- a/include/configs/ls2080aqds.h
>>> +++ b/include/configs/ls2080aqds.h
>>> @@ -14,6 +14,16 @@ unsigned long get_board_sys_clk(void);
>>>  unsigned long get_board_ddr_clk(void);
>>>  #endif
>>>
>>> +#define CONFIG_FSL_LS_PPA
>>
>> I am not finding CONFIG_FSL_LS_PPA being defined in board header file.
>
> Since this config option has been moved into Kconfig, we don't use board
> header file to define it any more. Actually, existing board don't enable
> this by default either. We can make it default after the PPA image is
> readily available to public.
>
>> Please refer arch/arm/cpu/armv8/fsl-layerscape/Kconfig. Looks like its 
>> enablement is govern from here.
>
> This patch lacks modification of
> arch/arm/cpu/armv8/fsl-layerscape/Kconfig to enable FSL_LS_PPA for
> LS2080A. There are some floating patches to change the
> CONFIG_SYS_LS_PPA_FW_IN_XIP. Please work with Zhiqiang on this.
>
>

Abhimanyu,

Where are we on this patch? Please send an update ASAP.

York

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Re: [U-Boot] [PATCH] arm: socfpga: set the mpuclk divider in the Altera group register

[Marek Vasut]

On 02/08/2017 02:21 AM, Marek Vasut wrote:
> On 01/31/2017 07:33 PM, Dinh Nguyen wrote:
>> The mpuclk register in the Altera group of the clock manager
>> divides the mpu_clk that is generated from the C0 output of the main
>> pll.
>>
>> Without this patch, the default value of the register is 1, so the mpuclk
>> will always get divided by 2 if the correct value is not set. For example,
>> on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be
>> 1.05 GHz.
> 
> Applied to u-boot-socfpga/next (so for 2017.05), as the MW is closed and
> I'd rather be a bit careful here. Is my assumption correct that
> until now, the performance of the CPU in both C/V and A/V was halved?

Hm in fact, it is already zero on C/V (I just checked) , so this seems
to be A/V specific ?

> It'd still be great to have people test it, so I added some more people
> to CC.
> 
>> Signed-off-by: Dinh Nguyen 
>> ---
>>  arch/arm/mach-socfpga/clock_manager.c  | 3 +++
>>  arch/arm/mach-socfpga/include/mach/clock_manager.h | 3 +++
>>  arch/arm/mach-socfpga/wrap_pll_config.c| 3 +++
>>  3 files changed, 9 insertions(+)
>>
>> diff --git a/arch/arm/mach-socfpga/clock_manager.c 
>> b/arch/arm/mach-socfpga/clock_manager.c
>> index aa71636..29e18f8 100644
>> --- a/arch/arm/mach-socfpga/clock_manager.c
>> +++ b/arch/arm/mach-socfpga/clock_manager.c
>> @@ -167,6 +167,9 @@ void cm_basic_init(const struct cm_config * const cfg)
>>  /* main mpu */
>>  writel(cfg->mpuclk, _manager_base->main_pll.mpuclk);
>>  
>> +/* altera group mpuclk */
>> +writel(cfg->altera_grp_mpuclk, _manager_base->altera.mpuclk);
>> +
>>  /* main main clock */
>>  writel(cfg->mainclk, _manager_base->main_pll.mainclk);
>>  
>> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h 
>> b/arch/arm/mach-socfpga/include/mach/clock_manager.h
>> index 2675951..803c926 100644
>> --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
>> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
>> @@ -55,6 +55,9 @@ struct cm_config {
>>  uint32_t ddr2xdqsclk;
>>  uint32_t ddrdqclk;
>>  uint32_t s2fuser2clk;
>> +
>> +/* altera group */
>> +uint32_t altera_grp_mpuclk;
>>  };
>>  
>>  void cm_basic_init(const struct cm_config * const cfg);
>> diff --git a/arch/arm/mach-socfpga/wrap_pll_config.c 
>> b/arch/arm/mach-socfpga/wrap_pll_config.c
>> index 8a0a0e6..72b5f92 100644
>> --- a/arch/arm/mach-socfpga/wrap_pll_config.c
>> +++ b/arch/arm/mach-socfpga/wrap_pll_config.c
>> @@ -116,6 +116,9 @@ static const struct cm_config cm_default_cfg = {
>>  CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
>>  (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
>>  CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
>> +
>> +/* altera group */
>> +CONFIG_HPS_ALTERAGRP_MPUCLK,
>>  };
>>  
>>  const struct cm_config * const cm_get_default_config(void)
>>
> 
> 


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] Please pull u-boot-x86

[Tom Rini]

On Tue, Feb 07, 2017 at 01:51:22PM +0800, Bin Meng wrote:

> Hi Tom,
> 
> This is U-Boot x86 64-bit preliminary support, on Google Chromebook
> Link and QEMU targets.
> 
> The following changes since commit c83a824e62277162ad35f52879b2316902c0eff5:
> 
>   Merge git://git.denx.de/u-boot-fsl-qoriq (2017-02-03 20:33:42 -0500)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-x86.git
> 
> for you to fetch changes up to 446d4e048ee3b00f7907e15cd02aa404cc714c77:
> 
>   x86: make LOAD_FROM_32_BIT visible for platforms (2017-02-07 13:36:50 +0800)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] arm: socfpga: set the mpuclk divider in the Altera group register

[Marek Vasut]

On 01/31/2017 07:33 PM, Dinh Nguyen wrote:
> The mpuclk register in the Altera group of the clock manager
> divides the mpu_clk that is generated from the C0 output of the main
> pll.
> 
> Without this patch, the default value of the register is 1, so the mpuclk
> will always get divided by 2 if the correct value is not set. For example,
> on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be
> 1.05 GHz.

Applied to u-boot-socfpga/next (so for 2017.05), as the MW is closed and
I'd rather be a bit careful here. Is my assumption correct that
until now, the performance of the CPU in both C/V and A/V was halved?

It'd still be great to have people test it, so I added some more people
to CC.

> Signed-off-by: Dinh Nguyen 
> ---
>  arch/arm/mach-socfpga/clock_manager.c  | 3 +++
>  arch/arm/mach-socfpga/include/mach/clock_manager.h | 3 +++
>  arch/arm/mach-socfpga/wrap_pll_config.c| 3 +++
>  3 files changed, 9 insertions(+)
> 
> diff --git a/arch/arm/mach-socfpga/clock_manager.c 
> b/arch/arm/mach-socfpga/clock_manager.c
> index aa71636..29e18f8 100644
> --- a/arch/arm/mach-socfpga/clock_manager.c
> +++ b/arch/arm/mach-socfpga/clock_manager.c
> @@ -167,6 +167,9 @@ void cm_basic_init(const struct cm_config * const cfg)
>   /* main mpu */
>   writel(cfg->mpuclk, _manager_base->main_pll.mpuclk);
>  
> + /* altera group mpuclk */
> + writel(cfg->altera_grp_mpuclk, _manager_base->altera.mpuclk);
> +
>   /* main main clock */
>   writel(cfg->mainclk, _manager_base->main_pll.mainclk);
>  
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h 
> b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> index 2675951..803c926 100644
> --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> @@ -55,6 +55,9 @@ struct cm_config {
>   uint32_t ddr2xdqsclk;
>   uint32_t ddrdqclk;
>   uint32_t s2fuser2clk;
> +
> + /* altera group */
> + uint32_t altera_grp_mpuclk;
>  };
>  
>  void cm_basic_init(const struct cm_config * const cfg);
> diff --git a/arch/arm/mach-socfpga/wrap_pll_config.c 
> b/arch/arm/mach-socfpga/wrap_pll_config.c
> index 8a0a0e6..72b5f92 100644
> --- a/arch/arm/mach-socfpga/wrap_pll_config.c
> +++ b/arch/arm/mach-socfpga/wrap_pll_config.c
> @@ -116,6 +116,9 @@ static const struct cm_config cm_default_cfg = {
>   CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
>   (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
>   CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
> +
> + /* altera group */
> + CONFIG_HPS_ALTERAGRP_MPUCLK,
>  };
>  
>  const struct cm_config * const cm_get_default_config(void)
> 


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] DTS: Enable top USB port on CEI-TK1-SOM

[Peter.Chubb]

> "Allen" == Allen Martin  writes:

Allen> On Tue, Feb 07, 2017 at 01:57:47PM +1100, Peter Chubb wrote:
>> From: Peter Chubb 
>> 
>> + usb@7d004000 {
>> +status = "okay";
>> + };
>> +
>> + usb-phy@7d004000 {
>> +status = "okay";
>> + };

Allen> Shouldn't these have a vbus-gpio and vbus-supply?

U-Boot seems to work OK without -- I can see storage devices plugged
into the port.
-- 
Dr Peter Chubb Tel: +61 2 9490 5852  http://ts.data61.csiro.au/
Trustworthy Systems Group   Data61 (formerly NICTA)
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[U-Boot] [PATCH] defconfig: am43xx_hs_evm: Sync HS defconfig with non-HS defconfig

[Andrew F. Davis]

The non-HS defconfig has been modified without equivalent changes being
applied to the HS defconfig. Sync these here.

Signed-off-by: Andrew F. Davis 
---
 configs/am43xx_hs_evm_defconfig | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index 8bb1b3535a..05365ee61a 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -10,12 +10,15 @@ CONFIG_FIT=y
 CONFIG_FIT_IMAGE_POST_PROCESS=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1, NAND"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,NAND"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ETH_SUPPORT=y
 CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -41,6 +44,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ISO_PARTITION=y
 CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
 CONFIG_DM=y
 # CONFIG_BLK is not set
 CONFIG_DFU_MMC=y
@@ -53,8 +57,8 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_DM_ETH=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
-- 
2.11.0

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[U-Boot] [PATCH] spl: net: Add FIT image support over network boot

[Andrew F. Davis]

FIT support in the net boot case is much like the RAM boot case in that
we load our image to "load_addr" and pass a dummy read function into
"spl_load_simple_fit()". As the load address is no longer hard-coded to
the final execution address, RAW image loading will rely on "load_addr"
pointing to the execution address as they should have before.

Signed-off-by: Andrew F. Davis 
---
 common/spl/spl_net.c | 30 +++---
 1 file changed, 27 insertions(+), 3 deletions(-)

diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c
index 0fba0172ea..b7a4a89198 100644
--- a/common/spl/spl_net.c
+++ b/common/spl/spl_net.c
@@ -11,19 +11,29 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static ulong spl_net_load_read(struct spl_load_info *load, ulong sector,
+  ulong count, void *buf)
+{
+   debug("%s: sector %lx, count %lx, buf %lx\n",
+ __func__, sector, count, (ulong)buf);
+   memcpy(buf, (void *)(load_addr + sector), count);
+   return count;
+}
+
 #if defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)
 static int spl_net_load_image(struct spl_image_info *spl_image,
  struct spl_boot_device *bootdev)
 {
+   struct image_header *header = (struct image_header *)load_addr;
int rv;
 
env_init();
env_relocate();
setenv("autoload", "yes");
-   load_addr = CONFIG_SYS_TEXT_BASE - sizeof(struct image_header);
rv = eth_initialize();
if (rv == 0) {
printf("No Ethernet devices found\n");
@@ -36,8 +46,22 @@ static int spl_net_load_image(struct spl_image_info 
*spl_image,
printf("Problem booting with BOOTP\n");
return rv;
}
-   return spl_parse_image_header(spl_image,
- (struct image_header *)load_addr);
+
+   if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+   image_get_magic(header) == FDT_MAGIC) {
+   struct spl_load_info load;
+
+   debug("Found FIT\n");
+   load.bl_len = 1;
+   load.read = spl_net_load_read;
+   rv = spl_load_simple_fit(spl_image, , 0, header);
+   } else {
+   debug("Legacy image\n");
+
+   rv = spl_parse_image_header(spl_image, header);
+   }
+
+   return rv;
 }
 #endif
 
-- 
2.11.0

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Re: [U-Boot] [PATCH] fsl-layerscape/ppa: cleanup ppa.h

[york sun]

On 02/05/2017 07:41 PM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang 
>
> Moved the ifdef into ppa.h and removed the duplicated macros.
>
> Signed-off-by: Hou Zhiqiang 
> ---
>  arch/arm/include/asm/arch-fsl-layerscape/ppa.h | 7 ++-
>  arch/arm/include/asm/armv8/sec_firmware.h  | 4 
>  board/freescale/ls1043ardb/ls1043ardb.c| 2 --
>  3 files changed, 2 insertions(+), 11 deletions(-)
>

Zhiqiang,

There are other places (ls1012a boards) ppa.h is included with #ifdef. 
Can they be cleaned up as well?

York

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[U-Boot] [PATCH 2/2] defconfig: Sync with non-HS and add SPL NAND support to AM335x HS

[Andrew F. Davis]

Sync new additions to non-HS defconfig with HS defconfig. Also add SPL
NAND support, this was disabled before due to size constraints, enable
this now at the expense of the less used GPT partition support.

Signed-off-by: Andrew F. Davis 
---
 configs/am335x_hs_evm_defconfig | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index d6224bcdfb..a2694247cc 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_AM33XX=y
 CONFIG_TI_SECURE_DEVICE=y
 # CONFIG_SPL_EXT_SUPPORT is not set
-# CONFIG_SPL_NAND_SUPPORT is not set
 CONFIG_TARGET_AM335X_EVM=y
 CONFIG_ISW_ENTRY_ADDR=0x40300350
 CONFIG_SPL_STACK_R_ADDR=0x8200
@@ -10,12 +9,13 @@ CONFIG_SPL_STACK_R_ADDR=0x8200
 CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_FIT_IMAGE_POST_PROCESS=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
-CONFIG_FIT_IMAGE_POST_PROCESS=y
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
@@ -32,6 +32,7 @@ CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_OF_LIST="am335x-evm"
 # CONFIG_BLK is not set
@@ -39,6 +40,7 @@ CONFIG_DFU_MMC=y
 CONFIG_DFU_NAND=y
 CONFIG_DFU_RAM=y
 CONFIG_DM_I2C=y
+CONFIG_MISC=y
 CONFIG_DM_MMC=y
 # CONFIG_DM_MMC_OPS is not set
 CONFIG_MMC_OMAP_HS=y
@@ -49,8 +51,10 @@ CONFIG_SYS_NS16550=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_TI=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-- 
2.11.0

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[U-Boot] [PATCH 1/2] defconfig: Add a config for AM335x High Security EVM with UART Boot support

[Andrew F. Davis]

Add a new defconfig file for the AM335x High Security EVM. This config
is specific for the case of UART booting

Signed-off-by: Andrew F. Davis 
---
 configs/am335x_hs_evm_uart_defconfig | 69 
 1 file changed, 69 insertions(+)
 create mode 100644 configs/am335x_hs_evm_uart_defconfig

diff --git a/configs/am335x_hs_evm_uart_defconfig 
b/configs/am335x_hs_evm_uart_defconfig
new file mode 100644
index 00..26ea3e3aab
--- /dev/null
+++ b/configs/am335x_hs_evm_uart_defconfig
@@ -0,0 +1,69 @@
+CONFIG_ARM=y
+CONFIG_AM33XX=y
+CONFIG_TI_SECURE_DEVICE=y
+# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_FAT_SUPPORT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+# CONFIG_SPL_MMC_SUPPORT is not set
+# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_TARGET_AM335X_EVM=y
+CONFIG_ISW_ENTRY_ADDR=0x40301750
+CONFIG_SPL_STACK_R_ADDR=0x8200
+CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_IMAGE_POST_PROCESS=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_MUSB_NEW_SUPPORT=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am335x-evm"
+# CONFIG_BLK is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_NAND=y
+CONFIG_DFU_RAM=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_MMC_OMAP_HS=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_TI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_RSA=y
+CONFIG_SPL_OF_LIBFDT=y
-- 
2.11.0

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Re: [U-Boot] [PATCH] armv8/fsl-layerscape: fdt: remove SYSCLK frequency fixup for ls1012a

[york sun]

On 01/20/2017 05:13 PM, york sun wrote:
>
> Then a proper fix would be check the clock name or compatible. If none
> of them exists, we should fix the device tree first.

Yangbo,

Can you fix the code to check clock name or compatible?

York
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Re: [U-Boot] [PATCH] armv8:fsl-layerscape: Add registers space defination for CCI-400 bus

[york sun]

On 02/01/2017 05:49 AM, Ashish Kumar wrote:
>  CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
>  provides full cache coherency between two clusters of multi-core
>  CPUs and I/O coherency for devices and I/O masters.
>
>  This patch add new CONFIG defination and move existing register
>  space definaton of CCI-400 bus from from immap_lsch2 to fsl_immap,
>  so that it can be used for both chasis 2 and chasis 3.
>

Please don't indent the commit message.

> Signed-off-by: Prabhakar Kushwaha 
> Signed-off-by: Ashish Kumar 
> ---
>  README |  9 
>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  6 +++
>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c|  1 +
>  arch/arm/cpu/armv8/fsl-layerscape/soc.c|  1 +
>  .../include/asm/arch-fsl-layerscape/immap_lsch2.h  | 48 
>  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
>  include/fsl_immap.h| 51 
> ++
>  7 files changed, 69 insertions(+), 48 deletions(-)
>
> diff --git a/README b/README
> index a95348a..f70ad49 100644
> --- a/README
> +++ b/README
> @@ -315,6 +315,15 @@ Many of the options are named exactly as the 
> corresponding Linux
>  kernel configuration options. The intention is to make it easier to
>  build a config tool - later.
>
> +- ARM Platform Bus Type(CCI):
> + CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
> + provides full cache coherency between two clusters of multi-core
> + CPUs and I/O coherency for devices and I/O masters
> +
> + CONFIG_SYS_FSL_HAS_CCI400
> +
> + Defined For SoC that has cache coherent interconnect
> + CCN-400
>
>  The following options need to be configured:
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index 47897f4..0ea43c6 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -7,6 +7,7 @@ config ARCH_LS1012A
>   select SYS_FSL_ERRATUM_A010315
>   select ARCH_EARLY_INIT_R
>   select BOARD_EARLY_INIT_F
> + select SYS_FSL_HAS_CCI400
>
>  config ARCH_LS1043A
>   bool
> @@ -26,6 +27,7 @@ config ARCH_LS1043A
>   select SYS_FSL_HAS_DDR4
>   select ARCH_EARLY_INIT_R
>   select BOARD_EARLY_INIT_F
> + select SYS_FSL_HAS_CCI400
>
>  config ARCH_LS1046A
>   bool
> @@ -44,6 +46,7 @@ config ARCH_LS1046A
>   select SYS_FSL_SRDS_2
>   select ARCH_EARLY_INIT_R
>   select BOARD_EARLY_INIT_F
> + select SYS_FSL_HAS_CCI400
>
>  config ARCH_LS2080A
>   bool
> @@ -184,6 +187,9 @@ config SYS_FSL_IFC_BANK_COUNT
>  config SYS_FSL_HAS_DP_DDR
>   bool
>
> +config SYS_FSL_HAS_CCI400
> + bool
> +

Please try to keep the config option in order. Easier to search later.

York
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Re: [U-Boot] [u-boot PATCH v3 7/8] ARM: k2g: setup PRU ethernet MAC addresses

[Tom Rini]

On Tue, Feb 07, 2017 at 09:52:25AM +0200, Igor Grinberg wrote:
> Hi Roger,
> 
> On 02/06/17 11:36, Roger Quadros wrote:
> > PRU ethernet MAC address range is present in the
> > board EEPROM. Parse it and setup eth?addr
> > environment variables.
> > 
> > Signed-off-by: Roger Quadros 
> > Reviewed-by: Lokesh Vutla 
> > ---
> >  board/ti/ks2_evm/board_k2g.c | 19 +++
> >  1 file changed, 19 insertions(+)
> > 
> > diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
> > index 40edbaa..a738dd2 100644
> > --- a/board/ti/ks2_evm/board_k2g.c
> > +++ b/board/ti/ks2_evm/board_k2g.c
> > @@ -12,6 +12,7 @@
> >  #include 
> >  #include 
> >  #include "mux-k2g.h"
> > +#include "../common/board_detect.h"
> >  
> >  #define SYS_CLK2400
> >  
> > @@ -149,6 +150,24 @@ int board_early_init_f(void)
> >  }
> >  #endif
> >  
> > +#ifdef CONFIG_BOARD_LATE_INIT
> > +int board_late_init(void)
> > +{
> > +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
> > +   int rc;
> > +
> > +   rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
> > +   CONFIG_EEPROM_CHIP_ADDRESS);
> > +   if (rc)
> > +   printf("ti_i2c_eeprom_init failed %d\n", rc);
> > +
> > +   board_ti_set_ethaddr(1);
> 
> What if the MAC address has already been set in the environment?
> AFAIR, the MAC address in the environment has a higher precedence
> than others.
> May be I missed this, but I don't remember any discussion about changing
> this assumption.
> So, if the assumption is still correct, you shouldn't change the MAC in the 
> env.

This is true.  Can we perhaps come up with a helper function that's
normally called to set the "eth?addr" to MAC if unset already, instead
of having N instances of the same logic?

-- 
Tom


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Re: [U-Boot] [PATCH v2 3/6] drivers: net: Provide Kconfig menu for PHYLIB

[Tom Rini]

On Mon, Feb 06, 2017 at 07:17:34PM -0800, Alexandru Gagniuc wrote:

> Provide the necessary Kconfig symbols so that PHYLIB support may be
> enabled in Kconfig, as opposed to needing to #define these symbols in
> C source headers.
> 
> BITBANGMII and MV88E6352_SWITCH are left out of the PHYLIB submenu as
> they don't seem to explicitly depend on it (i.e. they do not use the
> phy_driver class).
> 
> Signed-off-by: Alexandru Gagniuc 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [PATCH v2 1/6] configs: am335x_evm: Enable FASTBOOT based on kconfig

[Tom Rini]

On Mon, Feb 06, 2017 at 07:17:32PM -0800, Alexandru Gagniuc wrote:

> When CONFIG_CMD_FASTBOOT or CONFIG_USB_FUNCTION_FASTBOOT are defined
> in am335x_evm.h, a dependency on g_dnl.c is created. This in turn
> creates a dependency on having USB gadget enabled.
> As a result we can't create configs with USB gadget disabled.
> 
> Since these CONFIG_ variables are now part of kconfig, move them to
> the board defconfigs, and out of am335x_evm.h. This both preserves
> current defaults, and allows creating configs with USB gadget off.
> 
> Signed-off-by: Alexandru Gagniuc 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [PATCH v2 2/6] am33xx: board: Refactor USB initialization into separate function

[Tom Rini]

On Mon, Feb 06, 2017 at 07:17:33PM -0800, Alexandru Gagniuc wrote:

> The declaration of otg*_plat and otg*_board_data is guarded by
> CONFIG_USB_MUSB_*, but their use in arch_misc_init is not. The
> ifdef flow goes something like:
> 
> if (CONFIG_USB_MUSB_* && other_conditions)
>   declare usb_data
> if (other_conditions)
>   use usb_data
> 
> Thus when CONFIG_USB_MUSB_* is not declared, we try to use the
> data structures, but these structures aren't defined.
> 
> To fix this, move the USB initialization code into the same #ifdef
> which guards the declaration of the data structures. Since the DM_USB
> vs legacy cases are completely different, use two versions of
> arch_misc_init(), for readability.
> 
> Signed-off-by: Alexandru Gagniuc 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [PATCH] drivers: mmc: omap_hsmmc: Fix IO Buffer on OMAP36xx

[Tom Rini]

On Mon, Feb 06, 2017 at 11:31:43AM -0600, aford...@gmail.com wrote:

> From: Adam Ford 
> 
> On the OMAP36xx/37xx the CONTROL_WKUP_CTRL register has
> a field (bit 6) named GPIO_IO_PWRDNZ.  If 0, the IO buffers which
> are related to GPIO_126, 127 and 129 are disabled. Some boards may
> need this for MMC. After the PBIAS is configured, this bit should
> be set high to enable these GPIO pins.
> 
> Signed-off-by: Adam Ford 
> 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [PATCH v2 4/6] drivers: net: Move PHYLIB to Kconfig

[Tom Rini]

On Mon, Feb 06, 2017 at 07:17:35PM -0800, Alexandru Gagniuc wrote:

> From: "Andrew F. Davis" 
> 
> Signed-off-by: Andrew F. Davis 
[snip]
>  756 files changed, 860 insertions(+), 579 deletions(-)

So this shows we have some places where we need to add 'select PHYLIB'
to drivers and that we need to move net drivers to Kconfig first and
then move to select.

-- 
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Re: [U-Boot] [PATCH v2 4/6] drivers: net: Move PHYLIB to Kconfig

[Tom Rini]

On Tue, Feb 07, 2017 at 11:15:48AM -0600, Joe Hershberger wrote:
> On Tue, Feb 7, 2017 at 10:55 AM, Andrew F. Davis  wrote:
> > On 02/06/2017 09:17 PM, Alexandru Gagniuc wrote:
> >> From: "Andrew F. Davis" 
> >>
> >
> > By the way, I don't have compilers for the following boards:
> >
> > adp-ag101p_defconfig
> > 3c120_defconfig
> > 10m50_defconfig
> > openrisc-generic_defconfig
> >
> > So it would be nice if someone could check these manually.
> 
> I'll be running it through travis...
> https://travis-ci.org/jhershbe/u-boot/builds/199298196

But travis doesn't cover nios2/nds32/openrisc.  The first two can be
fetched outside of buildman, but openrisc is currently broken and on my
hard-choices list currently.

-- 
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Re: [U-Boot] [PATCH 2/3] armv8: fsl-lsch3: Update VID support

[york sun]

On 01/29/2017 11:21 PM, Priyanka Jain wrote:
>
>
>> -Original Message-
>> From: york sun
>> Sent: Friday, January 27, 2017 11:13 PM
>> To: Priyanka Jain ; u-boot@lists.denx.de
>> Cc: Arpit Goel 
>> Subject: Re: [PATCH 2/3] armv8: fsl-lsch3: Update VID support
>>
>> On 01/18/2017 09:43 PM, Priyanka Jain wrote:
>>> VID support in NXP layerscape Chassis-3 (lsch3) compilant SoCs like
>>> LS2088A, LS2080A differs from existing logic.
>>> -VDD voltage array is different
>>> -Registers are different
>>> -VDD calculation logic is different
>>>
>>> Add new function adjust_vdd() for LSCH3 compliant SoCs
>>>
>>> Signed-off-by: Priyanka Jain 
>>> Signed-off-by: Arpit Goel 
>>> ---
>>>  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |4 +-
>>>  board/freescale/common/vid.c   |  174 
>>> ++--
>>>  2 files changed, 164 insertions(+), 14 deletions(-)
>>>
>>> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
>>> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
>>> index 38a6d03..fc4d33b 100644
>>> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
>>> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
>>> @@ -187,9 +187,9 @@ struct ccsr_gur {
>>> u32 gpporcr3;
>>> u32 gpporcr4;
>>> u8  res_030[0x60-0x30];
>>> -#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
>>> +#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
>>>  #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK  0x1F
>>> -#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT  20
>>> +#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT  7
>>>  #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK   0x1F
>>
>>
>> Priyanka,
>>
>> You changed the fuse register offset and fuse position in this and previous 
>> patch
>> of this set. What's going on? I presume you have verified it on LS2080ARDB.
>> How did it work before? Do we have two fuse status registers?
>>
>> York
>
> York,
>
> These code changes are valid for both LS2080A and LS2088A.
> VID was not working before on LS2080A also.
>

I have to ask, does VID work now with this change set? Have you verified 
on both RDB and QDS? How about other SoCs in LSCH3 family?

York
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Re: [U-Boot] [PATCH] Remove unused symbol CONGIG_CMD_STORAGE from board configs

[Tom Rini]

On Mon, Feb 06, 2017 at 12:30:19PM +0100, Lars Poeschel wrote:

> Albeit it's a typo, neither CONGIG_CMD_STORAGE nor CONFIG_CMD_STORAGE
> are used anywhere, so remove the define from the board configs.
> 
> Signed-off-by: Lars Poeschel 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH v2 00/15] nand: device model bringup on am335x evm and am437x gpevm

[Tom Rini]

On Mon, Feb 06, 2017 at 12:50:25PM -0600, Grygorii Strashko wrote:
> Hi Tom,
> 
> On 02/05/2017 07:56 PM, Tom Rini wrote:
> > On Tue, Jan 31, 2017 at 03:37:02PM -0600, Grygorii Strashko wrote:
> > 
> >> This patch seires adds nand uclass driver and enables omap_gpmc to
> >> adopt driver model. This has been tested on AM335x GP EVM and
> >> AM437x GP EVM.
> >>
> >> As preparation for introducing nand uclass driver the new API
> >> get_nand_dev_by_index() was added to avoid direct acces to nand_info array 
> >> and
> >> u-boot core files were updated to use it.
> >>
> >> Patches can be found at:
> >> g...@git.ti.com:~gragst/ti-u-boot/gragsts-ti-u-boot.git dm-nand-v2
> > 
> > My conceptual concern here is that we need to address (as I've stated
> > elsewhere) the need to get DM/DT support within SPL on these families
> > (and yes, figure out what we'll do with respect to HS and the further
> > size constraints) before we push farther down this path of DM/DT
> > conversion as it's adding more #if/#else/#endif code that we need to be
> > able to drop.  Thanks!
> > 
> 
> I understand your concern and see it's discussed now in [1], but I'd 
> like to understand how to proceed with this series.
> 
> The original patches from from Mugunthan are at about 1 year old and
> and it took me pretty a lot of time to just re-base them properly,
> so will it be acceptable if i will re-send only patches 1-10 as they are
> do not depend on TI SPL and will unblock DM conversation of other drivers?
> Really want to reduce existed patch queue :(
> 
> [1] https://www.mail-archive.com/u-boot@lists.denx.de/msg237938.html

We can take up some of the underlying patches now, yes.  But we really
need to do the DM conversion fully, in order to really unblock progress.

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Re: [U-Boot] [PATCH v2 4/6] drivers: net: Move PHYLIB to Kconfig

[Joe Hershberger]

On Tue, Feb 7, 2017 at 10:55 AM, Andrew F. Davis  wrote:
> On 02/06/2017 09:17 PM, Alexandru Gagniuc wrote:
>> From: "Andrew F. Davis" 
>>
>
> By the way, I don't have compilers for the following boards:
>
> adp-ag101p_defconfig
> 3c120_defconfig
> 10m50_defconfig
> openrisc-generic_defconfig
>
> So it would be nice if someone could check these manually.

I'll be running it through travis...
https://travis-ci.org/jhershbe/u-boot/builds/199298196

Cheers,
-Joe

>
> Thanks,
> Andrew
>
>> Signed-off-by: Andrew F. Davis 
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Re: [U-Boot] [RFC PATCH] mmc: omap_hsmmc: convert to use dm block devies

[Tom Rini]

On Mon, Feb 06, 2017 at 11:31:14AM -0600, Andrew F. Davis wrote:
> On 02/03/2017 11:23 AM, Tom Rini wrote:
> > On Fri, Feb 03, 2017 at 09:57:03AM +0530, Vignesh R wrote:
> >>
> >>
> >> On Friday 03 February 2017 03:48 AM, Strashko, Grygorii wrote:
> >>> Convert OMAP hsmmc driver to use driver-model block devices.
> >>>
> >>> Signed-off-by: Grygorii Strashko 
> >>> ---
> >>> Hi All,
> >>>
> >>> First of all, sorry if my questions/problems are looks dumb, I'm very new 
> >>> with u-boot.
> >>>
> >>> This is my attampt to enable CONFIG_BLK on OMAP platforms which is 
> >>> blocked now
> >>> by omap_hsmmc driver. omap_hsmmc required to be updated to use 
> >>> driver-model block
> >>> devices at minimum (and max to use dm_mmc_ops). Also, as per my 
> >>> understanding,
> >>> CONFIG_BLK is blocker for other tasks like enabling driver model for OMAP 
> >>> sata devices.
> >>>
> >>> With this patch I can boot from mmc on am335x-evm, but there are
> >>> two problems I need help with: 
> >>> 1) My changes in Makefiles looks really ugly, but without them SPL build 
> >>> will
> >>>   fail because undef'ing in include/configs/am335x_evm.h does not take 
> >>> effect
> >>>   in Makefile (thanks Vignesh for the information [1]) and I, honestly, 
> >>> do not
> >>>   know how to fix it in better way, so I'd be appreciated for any help.
> >>>   Comparing to Vignesh's case, files which need to be excluded from build
> >>>   are generic and I worry that there can be dependecy from CONFIG_SPL_DM.
> >>>
> >>
> >>>
> >>> diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
> >>> index 6f624e9..d36e7d4 100644
> >>> --- a/configs/am335x_evm_defconfig
> >>> +++ b/configs/am335x_evm_defconfig
> >>> @@ -30,7 +30,6 @@ CONFIG_CMD_GPIO=y
> >>>  CONFIG_CMD_EXT4_WRITE=y
> >>>  CONFIG_OF_CONTROL=y
> >>>  CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk 
> >>> am335x-bonegreen am335x-icev2"
> >>> -# CONFIG_BLK is not set
> >>>  CONFIG_DFU_MMC=y
> >>>  CONFIG_DFU_NAND=y
> >>>  CONFIG_DFU_RAM=y
> >>> diff --git a/drivers/block/Makefile b/drivers/block/Makefile
> >>> index 41217c1..44baee3 100644
> >>> --- a/drivers/block/Makefile
> >>> +++ b/drivers/block/Makefile
> >>> @@ -5,12 +5,16 @@
> >>>  # SPDX-License-Identifier:   GPL-2.0+
> >>>  #
> >>>  
> >>> -obj-$(CONFIG_BLK) += blk-uclass.o
> >>> +obj-$(CONFIG_$(SPL_)BLK) += blk-uclass.o
> >>>  
> >>>  ifndef CONFIG_BLK
> >>>  obj-y += blk_legacy.o
> >>>  endif
> >>>  
> >>> +ifdef SPL_
> >>> +obj-y += blk_legacy.o
> >>> +endif
> >>
> >>
> >> I am facing a same problem with DM_ETH as well.
> >> How about something like:
> >>
> >> ifeq ($(CONFIG_$(SPL_)DM)$(CONFIG_BLK),yy)
> >> obj-y += blk_uclass.o
> >> else
> >> obj-y += blk_legacy.o
> >> endif
> >>
> >>
> >> Is this an acceptable solution?
> > 
> > No, I think this is really highlighting that we need to figure out a
> > solution to using DM inside of SPL on these classes of devices.  I think
> > the last time I started to think out loud about how to solve this my
> > suggestion was to make a "dummy" board dts file that is correct enough
> > for SPL needs and that we can bring up full U-Boot on.  Off the top of
> > my head, the differences between BBB/BBW/GP-EVM/EVM-SK/BBG are not
> > things we would see inside of SPL.  In a similar manner we should be
> > able to get am43xx going, and dra7xx/am57xx going.
> > 
> > 
> 
> We don't really need DT support in SPL for using DM, we could statically
> instantiate device drivers using a board file type system,
> platform_add_device(device_data) etc..
> 
> My biggest objection is in SPL bloat. What do we get by adding DM to
> SPL? Code re-use is nice, but SPL had hard needs in speed and size that
> will continue to be eroded by these changes.
> 
> Perhaps it is time to re-consider adding separate defconfigs/Makefiles
> for SPL?

The problem we need to solve is to also clean up the code and keep it
clean.  The fine line we need to walk is the ability to fit into both
reasonably small and still reasonably supported SoCs and the need to
continue to be able to re-use code and unify code.  And part of the
answer here may be to say that newer compilers will be the required
minimum in some platforms too.  For example with am335x_hs:
gcc-6.1.1 (Debian 6.1.1-9):
$ size am335x_hs_evm/u-boot-spl
   textdata bss dec hex filename
  378102452  198920  239182   3a64e am335x_hs_evm/u-boot-spl
gcc-4.9.0:
$ size am335x_hs_evm/u-boot-spl
   textdata bss dec hex filename
  420822452  198980  243514   3b73a am335x_hs_evm/u-boot-spl

Since we're just talking text my assumption is that the fix for
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54303 being available vs
not (it's also not fixed in gcc-5) is what is making up that large
difference.  And going from 698 bytes headroom to 4970 bytes headroom
will make things a little easier to deal with.

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Re: [U-Boot] [PATCH] mpc5200: Correct return value of memcpy function

[york sun]

On 01/24/2017 05:41 AM, thomas.grazia...@omicronenergy.com wrote:
> From: Mark Marshall 
>
> The memcpy() function returns a pointer to trg.
>
> Signed-off-by: Mark Marshall 
> Reviewed-by: Thomas Graziadei 
> ---
>  arch/powerpc/lib/memcpy_mpc5200.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/lib/memcpy_mpc5200.c 
> b/arch/powerpc/lib/memcpy_mpc5200.c
> index 75a3ef9..7e5a005 100644
> --- a/arch/powerpc/lib/memcpy_mpc5200.c
> +++ b/arch/powerpc/lib/memcpy_mpc5200.c
> @@ -31,7 +31,7 @@ void *memcpy(void *trg, const void *src, size_t len)
>   extern void* __memcpy(void *, const void *, size_t);
>   char *s = (char *)src;
>   char *t = (char *)trg;
> - void *dest = (void *)src;
> + void *dest = (void *)trg;
>
>   /*
>* Check is source address is in flash:
>

Looks like this is a duplicated patch.

York
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Re: [U-Boot] latest u-boot on Technexion LS1021A-IOT v1.0

[york sun]

+ Feng Li

On 02/06/2017 11:19 PM, Leon Brits wrote:
> Hi all,
>
>
>
> I’ve compiled u-boot 2017.01 for the TechNexion LS1021A-IOT v1.0 but
> there is no output of the u-boot boot process. The serial port
> application does report that it is connected.
>
>
>
> I have a 700-28203 REV X2 / SCH-28203 REV B3 unit which shows, when
> booted with its default u-boot from 2014, as v1.0. The u-boot is working
> fine on the v2.0 unit.
>
>
>
> Can any body help me?
>

Leon,

Feng is the maintainer of this board. Please wait for comments.

York

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Re: [U-Boot] [PATCH] armv8: fsl-lsch3: Put TZASC configuration in hash define

[york sun]

On 02/02/2017 05:43 AM, Ashish Kumar wrote:
> Number of TZASC instances may vary across NXP SoCs.
>
> So put TZASC configuration under instance specific defines.
>
> Signed-off-by: Prabhakar Kushwaha 
> Signed-off-by: Ashish Kumar 
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig|  8 
>  arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 24 +---
>  2 files changed, 21 insertions(+), 11 deletions(-)

I get what you mean in the subject, but "hash define" is not exactly 
what you did. Can you revise the subject?

York

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Re: [U-Boot] [PATCH] armv8: fsl-lsch3: Conditionally Remove errata a0009203 from lsch3 init

[york sun]

On 02/02/2017 01:16 AM, Ashish Kumar wrote:
>  This i2c errata is only valid for ls2080 and ls2088 SoC
>
> Signed-off-by: Ashish Kumar 
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 
>  arch/arm/cpu/armv8/fsl-layerscape/soc.c   | 4 
>  2 files changed, 8 insertions(+)

The subject is a little bit confusing. It sounds like LS2085A is 
excluded. We only use LS2080A throughout U-Boot. The only place you see 
LS2085A and LS2088A is SVR related. Please either spell out each SoC, or 
use "LS2080A and its variants".

York
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Re: [U-Boot] [PATCH v2 3/6] drivers: net: Provide Kconfig menu for PHYLIB

[Joe Hershberger]

On Mon, Feb 6, 2017 at 9:17 PM, Alexandru Gagniuc  wrote:
> Provide the necessary Kconfig symbols so that PHYLIB support may be
> enabled in Kconfig, as opposed to needing to #define these symbols in
> C source headers.
>
> BITBANGMII and MV88E6352_SWITCH are left out of the PHYLIB submenu as
> they don't seem to explicitly depend on it (i.e. they do not use the
> phy_driver class).
>
> Signed-off-by: Alexandru Gagniuc 

Acked-by: Joe Hershberger 
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Re: [U-Boot] [PATCH] drivers: net: Move PHYLIB to Kconfig

[Joe Hershberger]

On Mon, Feb 6, 2017 at 3:45 PM, Andrew F. Davis  wrote:
> Signed-off-by: Andrew F. Davis 

Thanks, guys!

Acked-by: Joe Hershberger 
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[U-Boot] [PATCH 1/3] regmap: use fdt address translation

[Jean-Jacques Hiblot]

In the DTS, the addresses are defined relative to the parent bus. We need
to translate them to get the address as seen by the CPU core.

Signed-off-by: Jean-Jacques Hiblot 
---

to: s...@chromium.org

 drivers/core/regmap.c | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index c68bcba..07a6614 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c
@@ -70,6 +70,7 @@ int regmap_init_mem(struct udevice *dev, struct regmap **mapp)
int addr_len, size_len, both_len;
int parent;
int len;
+   int index;
 
parent = dev->parent->of_offset;
addr_len = fdt_address_cells(blob, parent);
@@ -86,13 +87,14 @@ int regmap_init_mem(struct udevice *dev, struct regmap 
**mapp)
if (!map)
return -ENOMEM;
 
-   map->base = fdtdec_get_number(cell, addr_len);
-
-   for (range = map->range; count > 0;
-count--, cell += both_len, range++) {
-   range->start = fdtdec_get_number(cell, addr_len);
-   range->size = fdtdec_get_number(cell + addr_len, size_len);
+   for (range = map->range, index = 0; count > 0;
+count--, cell += both_len, range++, index++) {
+   fdt_size_t sz;
+   range->start = fdtdec_get_addr_size_fixed(blob, dev->of_offset,
+   "reg", index, addr_len, size_len, , true);
+   range->size = sz;
}
+   map->base = map->range[0].start;
 
*mapp = map;
 
-- 
1.9.1

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[U-Boot] [PATCH 2/3] drivers: ti_qspi: use syscon to get the address ctrl_mod_mmap register

[Jean-Jacques Hiblot]

We used to get the address of the optionnal ctrl_mod_mmap register as the
third memory range of the "reg" property. the linux driver moved to use a
syscon instead. In order to keep the DTS as close as possible to that of
linux, we move to using a syscon as well.

If CONFIG_SYSCON is no set, the driver reverts to the old way of getting
the address from the 3rd memory range

Signed-off-by: Jean-Jacques Hiblot 
---
 drivers/spi/ti_qspi.c | 47 ++-
 1 file changed, 42 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 6f9f983..d964b50 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -17,6 +17,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -549,21 +551,56 @@ static int ti_qspi_probe(struct udevice *bus)
return 0;
 }
 
+static void *map_syscon_chipselects(struct udevice *bus)
+{
+#if defined(CONFIG_SYSCON) && !defined(CONFIG_SPL_BUILD)
+   struct udevice *syscon;
+   struct regmap *regmap;
+   const fdt32_t *cell;
+   int len, err;
+
+   err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
+  "syscon-chipselects", );
+   if (err) {
+   debug("%s: unable to find syscon device (%d)\n", __func__,
+ err);
+   return NULL;
+   }
+
+   regmap = syscon_get_regmap(syscon);
+   if (IS_ERR(regmap)) {
+   debug("%s: unable to find regmap (%ld)\n", __func__,
+ PTR_ERR(regmap));
+   return NULL;
+   }
+
+   cell = fdt_getprop(gd->fdt_blob, bus->of_offset, "syscon-chipselects",
+  );
+   if (len < 2*sizeof(fdt32_t)) {
+   debug("%s: offset not available\n", __func__);
+   return NULL;
+   }
+
+   return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
+#else
+   fdt_addr_t addr;
+   addr = dev_get_addr_index(bus, 2);
+   return (addr == FDT_ADDR_T_NONE) ? NULL :
+   map_physmem(addr, 0, MAP_NOCACHE);
+#endif
+}
+
 static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
 {
struct ti_qspi_priv *priv = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
-   fdt_addr_t addr;
-   void *mmap;
 
+   priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
priv->base = map_physmem(dev_get_addr(bus), sizeof(struct ti_qspi_regs),
 MAP_NOCACHE);
priv->memory_map = map_physmem(dev_get_addr_index(bus, 1), 0,
   MAP_NOCACHE);
-   addr = dev_get_addr_index(bus, 2);
-   mmap = map_physmem(dev_get_addr_index(bus, 2), 0, MAP_NOCACHE);
-   priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : mmap;
 
priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
if (priv->max_hz < 0) {
-- 
1.9.1

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[U-Boot] [PATCH 3/3] configs: dra7x/am57x: Enable the SYSCON and REGMAP features

[Jean-Jacques Hiblot]

This is required by the ti_qspi driver to get from the DTS the address of
the ctrl_mod_mmap register.

Signed-off-by: Jean-Jacques Hiblot 
---
 configs/am57xx_evm_defconfig| 2 ++
 configs/am57xx_hs_evm_defconfig | 2 ++
 configs/dra7xx_evm_defconfig| 2 ++
 configs/dra7xx_hs_evm_defconfig | 2 ++
 4 files changed, 8 insertions(+)

diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index a582055..15bb474 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -50,6 +50,8 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am572x-idk 
am571x-idk"
 CONFIG_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 # CONFIG_BLK is not set
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 4dcfce4..fc37b58 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -52,6 +52,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 # CONFIG_BLK is not set
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 64fe038..624cfe4 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -50,6 +50,8 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm"
 CONFIG_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 # CONFIG_BLK is not set
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index b890a06..028b212 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -55,6 +55,8 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm"
 CONFIG_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 # CONFIG_BLK is not set
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
-- 
1.9.1

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[U-Boot] [PATCH 0/3] driver: ti_qspi: Use a SYSCON device to map the ctrl_mod_mmap register

[Jean-Jacques Hiblot]

This series allows the ti_qspi driver to use the same dts description as the
linux kernel. In Linux since 4.6 the ctrl_mod_mmap is described in the DTS as a
syscon. It used to be the 3rd memory range in "reg".

The first patch of this series is a generic one. It changes the regmap 
initialization
to take in account the required address translation.

The second patch adds the mechanism in the ti_qspi driver to get the address
of ctrl_mod_mmap from the syscon

The last patch simply enable the SYSCON feature in the default config for the
dra7xx and am57xx evms.

Jean-Jacques Hiblot (3):
  regmap: use fdt address translation
  drivers: ti_qspi: use syscon to get the address ctrl_mod_mmap register
  configs: dra7x/am57x: Enable the SYSCON and REGMAP features

 configs/am57xx_evm_defconfig|  2 ++
 configs/am57xx_hs_evm_defconfig |  2 ++
 configs/dra7xx_evm_defconfig|  2 ++
 configs/dra7xx_hs_evm_defconfig |  2 ++
 drivers/core/regmap.c   | 14 ++--
 drivers/spi/ti_qspi.c   | 47 -
 6 files changed, 58 insertions(+), 11 deletions(-)

-- 
1.9.1

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Re: [U-Boot] [PATCH v3 04/13] sunxi: simplify ACTLR.SMP bit set #ifdef

[Maxime Ripard]

On Mon, Feb 06, 2017 at 11:29:26AM +, Andre Przywara wrote:
> Hi,
> 
> On 03/02/17 10:52, Jagan Teki wrote:
> > On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara  
> > wrote:
> >> Instead of enumerating all SoC families that need that bit set, let's
> >> just express this more clearly: The SMP bits needs to be set on
> >> SMP capable ARMv7 CPUs. It's much easier in Kconfig to express it the
> >> other way round, so we use ! CPU_IS_UP and ! ARM64.
> >>
> >> Signed-off-by: Andre Przywara 
> >> Acked-by: Maxime Ripard 
> >> ---
> >>  arch/arm/Kconfig| 4 
> >>  arch/arm/mach-sunxi/board.c | 5 +
> >>  board/sunxi/Kconfig | 2 ++
> >>  3 files changed, 7 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> >> index fc36723..98791c0 100644
> >> --- a/arch/arm/Kconfig
> >> +++ b/arch/arm/Kconfig
> >> @@ -126,6 +126,10 @@ config ENABLE_ARM_SOC_BOOT0_HOOK
> >>   ARM_SOC_BOOT0_HOOK which contains the required assembler
> >>   preprocessor code.
> >>
> >> +config ARM_CORTEX_CPU_IS_UP
> >> +   bool
> >> +   default n
> > 
> > Better to place this in sunxi, since no other code using this expect
> > sunxi and the name CORTEX may also refer arm64 use something 32
> > related.
> 
> Sigh, can you please check back with Maxime on what's the right thing here?
> http://lists.denx.de/pipermail/u-boot/2017-January/279417.html
> 
> If it's about the name, shall we use ARM_CORTEX_V7_CPU_IS_UP?
> 
> I was briefly tempted to unify all ACTLR.SMP bit sets from all over the
> ARM code, but this looks like a can of worms to me, so I'd rather keep
> this one closed.

There's at least one other SoC in a similar situation (imx7 solo), so
I think it should really be made generic. I don't really care about
the name though, but keeping it in sunxi is just creating yet another
candidate for a duplicated and redundant option.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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Re: [U-Boot] [PATCH v3 12/13] sunxi: dts: add basic OrangePi PC 2 device tree file

[Maxime Ripard]

On Mon, Feb 06, 2017 at 10:18:14AM +, Andre Przywara wrote:
> Hi,
> 
> On 03/02/17 11:14, Jagan Teki wrote:
> > On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara  
> > wrote:
> >> The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC.
> >> Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi
> >> and changing the differing components accordingly.
> >> This is a preliminary device tree mostly for U-Boot's own sake, it
> >> is expected to be updated once the official DT gets accepted upstream.
> >>
> >> Signed-off-by: Andre Przywara 
> >> ---
> >>  arch/arm/dts/Makefile   |   2 +
> >>  arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 147 
> >> 
> > 
> > Please squash 13/13 with this, I would see a single patch for initial 
> > support.
> 
> How comes?
> I think those two are really separate topics, and having a DT file in
> this directory really doesn't hurt anything, until it actually gets
> referenced in the next patch.
> I'd keep DT patches separate, really, and in general always would prefer
> more, but smaller patches to fewer, but bigger ones.

I concur.

Maxime

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Re: [U-Boot] [PATCH] arm: dts: dra7: add qspi register map for control module

[Jean-Jacques Hiblot]

On 06/02/2017 14:37, Tom Rini wrote:

On Mon, Feb 06, 2017 at 02:27:42PM +0100, Jean-Jacques Hiblot wrote:


On 06/02/2017 13:47, Tom Rini wrote:

On Mon, Feb 06, 2017 at 12:09:12PM +0100, Jean-Jacques Hiblot wrote:

On 03/02/2017 17:52, Tom Rini wrote:

On Wed, Feb 01, 2017 at 11:53:42AM +0100, Jean-Jacques Hiblot wrote:


Add qspi control module register maps to device tree. This register map had
been removed by error when syncing the DTS with the latest linux at the
time (commit 7aa1a4087 "ARM: dts: dra7xx: sync DT with latest Linux").
Without this entry the driver do not support memory-mapped access and the
data read from the SF is invalid.

Signed-off-by: Jean-Jacques Hiblot 

Why is this not in the upstream DTS file?

In Linux, a syscon/regmap is  used to map this register while the
QSPI driver in u-boot uses a direct memory access.

OK, but it's a valid part of the upstream kernel binding, yes?

syscon-chipselects is part of the mainlined binding. Using a 3rd
memory range used to be the way to do it, but it is not supported
anymore (I think it has been removed removed in 4.6).
Using a third memory range has been supported in u-boot for some time now.
So you think we should move to using the syscon ?

Based on what I see in v4.10-rc7, yes, we should adapt the driver to
know about the new property and things are working as expected wrt DT
compatibility.

Ok. I have prepared a new series to do this




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Re: [U-Boot] [PATCH] armv7m: Add SysTick timer driver

[Phil Edworthy]

Hi Tom,

On 07 February 2017 14:23, Tom Rini wrote:
> On Tue, Feb 07, 2017 at 02:19:39PM +, Phil Edworthy wrote:
> > Hi Kamil,
> >
> > On 07 February 2017 14:12, Kamil Lulko wrote:
> > > On Mon, Feb 6, 2017 at 12:16 AM, Tom Rini  wrote:
> > > > On Fri, Feb 03, 2017 at 02:48:40PM +, Phil Edworthy wrote:
> > > >
> > > > > The SysTick is a 24-bit down counter that is found on all ARM Cortex
> > > > > M3, M4, M7 devices and is always located at a fixed address.
> > > > >
> > > > > Signed-off-by: Phil Edworthy 
> > > > > ---
> > > > >  arch/arm/cpu/armv7m/Makefile|  2 +
> > > > >  arch/arm/cpu/armv7m/systick-timer.c | 91
> > > +
> > > > >  2 files changed, 93 insertions(+)
> > > > >  create mode 100644 arch/arm/cpu/armv7m/systick-timer.c
> > > > >
> > > > > diff --git a/arch/arm/cpu/armv7m/Makefile
> > > b/arch/arm/cpu/armv7m/Makefile
> > > > > index aff60e8..e1a6c40 100644
> > > > > --- a/arch/arm/cpu/armv7m/Makefile
> > > > > +++ b/arch/arm/cpu/armv7m/Makefile
> > > > > @@ -7,3 +7,5 @@
> > > > >
> > > > >  extra-y := start.o
> > > > >  obj-y += cpu.o
> > > > > +
> > > > > +obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o
> > > > > diff --git a/arch/arm/cpu/armv7m/systick-timer.c
> > > b/arch/arm/cpu/armv7m/systick-timer.c
> > > > > new file mode 100644
> > > > > index 000..6ccc2fb
> > > > > --- /dev/null
> > > > > +++ b/arch/arm/cpu/armv7m/systick-timer.c
> > > > > @@ -0,0 +1,91 @@
> > > > > +/*
> > > > > + * ARM Cortex M3/M4/M7 SysTick timer driver
> > > > > + * (C) Copyright 2017 Renesas Electronics Europe Ltd
> > > > > + *
> > > > > + * Based on arch/arm/mach-stm32/stm32f1/timer.c
> > > > > + * (C) Copyright 2015
> > > > > + * Kamil Lulko, 
> > > > > + *
> > > > > + * Copyright 2015 ATS Advanced Telematics Systems GmbH
> > > > > + * Copyright 2015 Konsulko Group, Matt Porter
> 
> > > > > + *
> > > > > + * SPDX-License-Identifier: GPL-2.0+
> > > > > + */
> > > > > +
> > > > > +#include 
> > > > > +#include 
> > > > > +
> > > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > > +
> > > > > +/* SysTick Base Address - fixed for all Cortex M3, M4 and M7 devices 
> > > > > */
> > > > > +#define SYSTICK_BASE 0xE000E010
> > > > > +
> > > > > +struct cm3_systick {
> > > > > + uint32_t ctrl;
> > > > > + uint32_t reload;
> > > > > + uint32_t val;
> > > > > + uint32_t calibration;
> > > > > +};
> > > > > +
> > > > > +#define TIMER_LOAD_VAL   0x00FF
> > > > > +#define SYSTICK_CTRL_EN  BIT(0)
> > > > > +/* Clock source: 0 = Ref clock, 1 = CPU clock */
> > > > > +#define SYSTICK_CTRL_CPU_CLK BIT(2)
> > > > > +
> > > > > +/* read the 24-bit timer */
> > > > > +static ulong read_timer(void)
> > > > > +{
> > > > > + struct cm3_systick *systick = (struct cm3_systick 
> > > > > *)SYSTICK_BASE;
> > > > > +
> > > > > + /* The timer counts down, therefore convert to an incrementing 
> > > > > timer
> */
> > > > > + return TIMER_LOAD_VAL - readl(>val);
> > > > > +}
> > > > > +
> > > > > +int timer_init(void)
> > > > > +{
> > > > > + struct cm3_systick *systick = (struct cm3_systick 
> > > > > *)SYSTICK_BASE;
> > > > > +
> > > > > + writel(TIMER_LOAD_VAL, >reload);
> > > > > + writel(TIMER_LOAD_VAL, >val);
> > > > > +
> > > > > +#ifdef CONFIG_ARMCORTEXM3_SYSTICK_CPU
> > > > > + /* Use CPU clock, no interrupts */
> > > > > + writel(SYSTICK_CTRL_EN | SYSTICK_CTRL_CPU_CLK, >ctrl);
> > > > > +#else
> > > > > + /* Use external clock, no interrupts */
> > > > > + writel(SYSTICK_CTRL_EN, >ctrl);
> > > > > +#endif
> > > > > +
> > > > > + gd->arch.tbl = 0;
> > > > > + gd->arch.tbu = 0;
> > > > > + gd->arch.lastinc = read_timer();
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > +/* return milli-seconds timer value */
> > > > > +ulong get_timer(ulong base)
> > > > > +{
> > > > > + unsigned long long t = get_ticks() * 1000;
> > > > > +
> > > > > + return (ulong)((t / CONFIG_SYS_HZ_CLOCK)) - base;
> > > > > +}
> > > > > +
> > > > > +unsigned long long get_ticks(void)
> > > > > +{
> > > > > + u32 now = read_timer();
> > > > > +
> > > > > + if (now >= gd->arch.lastinc)
> > > > > + gd->arch.tbl += (now - gd->arch.lastinc);
> > > > > + else
> > > > > + gd->arch.tbl += (TIMER_LOAD_VAL - gd->arch.lastinc) + 
> > > > > now;
> > > > > +
> > > > > + gd->arch.lastinc = now;
> > > > > +
> > > > > + return gd->arch.tbl;
> > > > > +}
> > > > > +
> > > > > +ulong get_tbclk(void)
> > > > > +{
> > > > > + return CONFIG_SYS_HZ_CLOCK;
> > > > > +}
> > > >
> > > > And (cc'ing maintainers) we could use this in place of
> > > > arch/arm/mach-stm32/*/timer.c I assume, yes?  Thanks!
> > > >
> > > > --
> > > > Tom
> > >
> > > Yes, however as far as I remember the systick is only 24-bit and
> > > usually runs on CPU clock so it will roll over too 

[U-Boot] latest u-boot on Technexion LS1021A-IOT v1.0

[Leon Brits]

Hi all,

I've compiled u-boot 2017.01 for the TechNexion LS1021A-IOT v1.0 but there is 
no output of the u-boot boot process. The serial port application does report 
that it is connected.

I have a 700-28203 REV X2 / SCH-28203 REV B3 unit which shows, when booted with 
its default u-boot from 2014, as v1.0. The u-boot is working fine on the v2.0 
unit.

Can any body help me?

Regards
LJB
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Re: [U-Boot] [PATCH] armv7m: Add SysTick timer driver

[Tom Rini]

On Tue, Feb 07, 2017 at 02:19:39PM +, Phil Edworthy wrote:
> Hi Kamil,
> 
> On 07 February 2017 14:12, Kamil Lulko wrote:
> > On Mon, Feb 6, 2017 at 12:16 AM, Tom Rini  wrote:
> > > On Fri, Feb 03, 2017 at 02:48:40PM +, Phil Edworthy wrote:
> > >
> > > > The SysTick is a 24-bit down counter that is found on all ARM Cortex
> > > > M3, M4, M7 devices and is always located at a fixed address.
> > > >
> > > > Signed-off-by: Phil Edworthy 
> > > > ---
> > > >  arch/arm/cpu/armv7m/Makefile|  2 +
> > > >  arch/arm/cpu/armv7m/systick-timer.c | 91
> > +
> > > >  2 files changed, 93 insertions(+)
> > > >  create mode 100644 arch/arm/cpu/armv7m/systick-timer.c
> > > >
> > > > diff --git a/arch/arm/cpu/armv7m/Makefile
> > b/arch/arm/cpu/armv7m/Makefile
> > > > index aff60e8..e1a6c40 100644
> > > > --- a/arch/arm/cpu/armv7m/Makefile
> > > > +++ b/arch/arm/cpu/armv7m/Makefile
> > > > @@ -7,3 +7,5 @@
> > > >
> > > >  extra-y := start.o
> > > >  obj-y += cpu.o
> > > > +
> > > > +obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o
> > > > diff --git a/arch/arm/cpu/armv7m/systick-timer.c
> > b/arch/arm/cpu/armv7m/systick-timer.c
> > > > new file mode 100644
> > > > index 000..6ccc2fb
> > > > --- /dev/null
> > > > +++ b/arch/arm/cpu/armv7m/systick-timer.c
> > > > @@ -0,0 +1,91 @@
> > > > +/*
> > > > + * ARM Cortex M3/M4/M7 SysTick timer driver
> > > > + * (C) Copyright 2017 Renesas Electronics Europe Ltd
> > > > + *
> > > > + * Based on arch/arm/mach-stm32/stm32f1/timer.c
> > > > + * (C) Copyright 2015
> > > > + * Kamil Lulko, 
> > > > + *
> > > > + * Copyright 2015 ATS Advanced Telematics Systems GmbH
> > > > + * Copyright 2015 Konsulko Group, Matt Porter 
> > > > + *
> > > > + * SPDX-License-Identifier: GPL-2.0+
> > > > + */
> > > > +
> > > > +#include 
> > > > +#include 
> > > > +
> > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > +
> > > > +/* SysTick Base Address - fixed for all Cortex M3, M4 and M7 devices */
> > > > +#define SYSTICK_BASE 0xE000E010
> > > > +
> > > > +struct cm3_systick {
> > > > + uint32_t ctrl;
> > > > + uint32_t reload;
> > > > + uint32_t val;
> > > > + uint32_t calibration;
> > > > +};
> > > > +
> > > > +#define TIMER_LOAD_VAL   0x00FF
> > > > +#define SYSTICK_CTRL_EN  BIT(0)
> > > > +/* Clock source: 0 = Ref clock, 1 = CPU clock */
> > > > +#define SYSTICK_CTRL_CPU_CLK BIT(2)
> > > > +
> > > > +/* read the 24-bit timer */
> > > > +static ulong read_timer(void)
> > > > +{
> > > > + struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE;
> > > > +
> > > > + /* The timer counts down, therefore convert to an incrementing 
> > > > timer */
> > > > + return TIMER_LOAD_VAL - readl(>val);
> > > > +}
> > > > +
> > > > +int timer_init(void)
> > > > +{
> > > > + struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE;
> > > > +
> > > > + writel(TIMER_LOAD_VAL, >reload);
> > > > + writel(TIMER_LOAD_VAL, >val);
> > > > +
> > > > +#ifdef CONFIG_ARMCORTEXM3_SYSTICK_CPU
> > > > + /* Use CPU clock, no interrupts */
> > > > + writel(SYSTICK_CTRL_EN | SYSTICK_CTRL_CPU_CLK, >ctrl);
> > > > +#else
> > > > + /* Use external clock, no interrupts */
> > > > + writel(SYSTICK_CTRL_EN, >ctrl);
> > > > +#endif
> > > > +
> > > > + gd->arch.tbl = 0;
> > > > + gd->arch.tbu = 0;
> > > > + gd->arch.lastinc = read_timer();
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +/* return milli-seconds timer value */
> > > > +ulong get_timer(ulong base)
> > > > +{
> > > > + unsigned long long t = get_ticks() * 1000;
> > > > +
> > > > + return (ulong)((t / CONFIG_SYS_HZ_CLOCK)) - base;
> > > > +}
> > > > +
> > > > +unsigned long long get_ticks(void)
> > > > +{
> > > > + u32 now = read_timer();
> > > > +
> > > > + if (now >= gd->arch.lastinc)
> > > > + gd->arch.tbl += (now - gd->arch.lastinc);
> > > > + else
> > > > + gd->arch.tbl += (TIMER_LOAD_VAL - gd->arch.lastinc) + now;
> > > > +
> > > > + gd->arch.lastinc = now;
> > > > +
> > > > + return gd->arch.tbl;
> > > > +}
> > > > +
> > > > +ulong get_tbclk(void)
> > > > +{
> > > > + return CONFIG_SYS_HZ_CLOCK;
> > > > +}
> > >
> > > And (cc'ing maintainers) we could use this in place of
> > > arch/arm/mach-stm32/*/timer.c I assume, yes?  Thanks!
> > >
> > > --
> > > Tom
> > 
> > Yes, however as far as I remember the systick is only 24-bit and
> > usually runs on CPU clock so it will roll over too fast to be useful
> > without using interrupts. Maybe I have missed something?
> 
> Yes, it is only a 24-bit counter. On the device I am using, the clock
> is not the cpu clock, but a low speed clock at 6.25MHz. Even at that
> low clock it will still wrap every ~2.6 seconds.

So are you able to use the timer then, given the quick overflow?

-- 
Tom


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Re: [U-Boot] [PATCH] armv7m: Add SysTick timer driver

[Phil Edworthy]

Hi Kamil,

On 07 February 2017 14:12, Kamil Lulko wrote:
> On Mon, Feb 6, 2017 at 12:16 AM, Tom Rini  wrote:
> > On Fri, Feb 03, 2017 at 02:48:40PM +, Phil Edworthy wrote:
> >
> > > The SysTick is a 24-bit down counter that is found on all ARM Cortex
> > > M3, M4, M7 devices and is always located at a fixed address.
> > >
> > > Signed-off-by: Phil Edworthy 
> > > ---
> > >  arch/arm/cpu/armv7m/Makefile|  2 +
> > >  arch/arm/cpu/armv7m/systick-timer.c | 91
> +
> > >  2 files changed, 93 insertions(+)
> > >  create mode 100644 arch/arm/cpu/armv7m/systick-timer.c
> > >
> > > diff --git a/arch/arm/cpu/armv7m/Makefile
> b/arch/arm/cpu/armv7m/Makefile
> > > index aff60e8..e1a6c40 100644
> > > --- a/arch/arm/cpu/armv7m/Makefile
> > > +++ b/arch/arm/cpu/armv7m/Makefile
> > > @@ -7,3 +7,5 @@
> > >
> > >  extra-y := start.o
> > >  obj-y += cpu.o
> > > +
> > > +obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o
> > > diff --git a/arch/arm/cpu/armv7m/systick-timer.c
> b/arch/arm/cpu/armv7m/systick-timer.c
> > > new file mode 100644
> > > index 000..6ccc2fb
> > > --- /dev/null
> > > +++ b/arch/arm/cpu/armv7m/systick-timer.c
> > > @@ -0,0 +1,91 @@
> > > +/*
> > > + * ARM Cortex M3/M4/M7 SysTick timer driver
> > > + * (C) Copyright 2017 Renesas Electronics Europe Ltd
> > > + *
> > > + * Based on arch/arm/mach-stm32/stm32f1/timer.c
> > > + * (C) Copyright 2015
> > > + * Kamil Lulko, 
> > > + *
> > > + * Copyright 2015 ATS Advanced Telematics Systems GmbH
> > > + * Copyright 2015 Konsulko Group, Matt Porter 
> > > + *
> > > + * SPDX-License-Identifier: GPL-2.0+
> > > + */
> > > +
> > > +#include 
> > > +#include 
> > > +
> > > +DECLARE_GLOBAL_DATA_PTR;
> > > +
> > > +/* SysTick Base Address - fixed for all Cortex M3, M4 and M7 devices */
> > > +#define SYSTICK_BASE 0xE000E010
> > > +
> > > +struct cm3_systick {
> > > + uint32_t ctrl;
> > > + uint32_t reload;
> > > + uint32_t val;
> > > + uint32_t calibration;
> > > +};
> > > +
> > > +#define TIMER_LOAD_VAL   0x00FF
> > > +#define SYSTICK_CTRL_EN  BIT(0)
> > > +/* Clock source: 0 = Ref clock, 1 = CPU clock */
> > > +#define SYSTICK_CTRL_CPU_CLK BIT(2)
> > > +
> > > +/* read the 24-bit timer */
> > > +static ulong read_timer(void)
> > > +{
> > > + struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE;
> > > +
> > > + /* The timer counts down, therefore convert to an incrementing 
> > > timer */
> > > + return TIMER_LOAD_VAL - readl(>val);
> > > +}
> > > +
> > > +int timer_init(void)
> > > +{
> > > + struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE;
> > > +
> > > + writel(TIMER_LOAD_VAL, >reload);
> > > + writel(TIMER_LOAD_VAL, >val);
> > > +
> > > +#ifdef CONFIG_ARMCORTEXM3_SYSTICK_CPU
> > > + /* Use CPU clock, no interrupts */
> > > + writel(SYSTICK_CTRL_EN | SYSTICK_CTRL_CPU_CLK, >ctrl);
> > > +#else
> > > + /* Use external clock, no interrupts */
> > > + writel(SYSTICK_CTRL_EN, >ctrl);
> > > +#endif
> > > +
> > > + gd->arch.tbl = 0;
> > > + gd->arch.tbu = 0;
> > > + gd->arch.lastinc = read_timer();
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +/* return milli-seconds timer value */
> > > +ulong get_timer(ulong base)
> > > +{
> > > + unsigned long long t = get_ticks() * 1000;
> > > +
> > > + return (ulong)((t / CONFIG_SYS_HZ_CLOCK)) - base;
> > > +}
> > > +
> > > +unsigned long long get_ticks(void)
> > > +{
> > > + u32 now = read_timer();
> > > +
> > > + if (now >= gd->arch.lastinc)
> > > + gd->arch.tbl += (now - gd->arch.lastinc);
> > > + else
> > > + gd->arch.tbl += (TIMER_LOAD_VAL - gd->arch.lastinc) + now;
> > > +
> > > + gd->arch.lastinc = now;
> > > +
> > > + return gd->arch.tbl;
> > > +}
> > > +
> > > +ulong get_tbclk(void)
> > > +{
> > > + return CONFIG_SYS_HZ_CLOCK;
> > > +}
> >
> > And (cc'ing maintainers) we could use this in place of
> > arch/arm/mach-stm32/*/timer.c I assume, yes?  Thanks!
> >
> > --
> > Tom
> 
> Yes, however as far as I remember the systick is only 24-bit and
> usually runs on CPU clock so it will roll over too fast to be useful
> without using interrupts. Maybe I have missed something?

Yes, it is only a 24-bit counter. On the device I am using, the clock
is not the cpu clock, but a low speed clock at 6.25MHz. Even at that
low clock it will still wrap every ~2.6 seconds.

> /Kamil

Thanks
Phil
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Re: [U-Boot] [PATCH] armv7m: Add SysTick timer driver

[Kamil Lulko]

On Mon, Feb 6, 2017 at 12:16 AM, Tom Rini  wrote:
>
> On Fri, Feb 03, 2017 at 02:48:40PM +, Phil Edworthy wrote:
>
> > The SysTick is a 24-bit down counter that is found on all ARM Cortex
> > M3, M4, M7 devices and is always located at a fixed address.
> >
> > Signed-off-by: Phil Edworthy 
> > ---
> >  arch/arm/cpu/armv7m/Makefile|  2 +
> >  arch/arm/cpu/armv7m/systick-timer.c | 91 
> > +
> >  2 files changed, 93 insertions(+)
> >  create mode 100644 arch/arm/cpu/armv7m/systick-timer.c
> >
> > diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile
> > index aff60e8..e1a6c40 100644
> > --- a/arch/arm/cpu/armv7m/Makefile
> > +++ b/arch/arm/cpu/armv7m/Makefile
> > @@ -7,3 +7,5 @@
> >
> >  extra-y := start.o
> >  obj-y += cpu.o
> > +
> > +obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o
> > diff --git a/arch/arm/cpu/armv7m/systick-timer.c 
> > b/arch/arm/cpu/armv7m/systick-timer.c
> > new file mode 100644
> > index 000..6ccc2fb
> > --- /dev/null
> > +++ b/arch/arm/cpu/armv7m/systick-timer.c
> > @@ -0,0 +1,91 @@
> > +/*
> > + * ARM Cortex M3/M4/M7 SysTick timer driver
> > + * (C) Copyright 2017 Renesas Electronics Europe Ltd
> > + *
> > + * Based on arch/arm/mach-stm32/stm32f1/timer.c
> > + * (C) Copyright 2015
> > + * Kamil Lulko, 
> > + *
> > + * Copyright 2015 ATS Advanced Telematics Systems GmbH
> > + * Copyright 2015 Konsulko Group, Matt Porter 
> > + *
> > + * SPDX-License-Identifier: GPL-2.0+
> > + */
> > +
> > +#include 
> > +#include 
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +/* SysTick Base Address - fixed for all Cortex M3, M4 and M7 devices */
> > +#define SYSTICK_BASE 0xE000E010
> > +
> > +struct cm3_systick {
> > + uint32_t ctrl;
> > + uint32_t reload;
> > + uint32_t val;
> > + uint32_t calibration;
> > +};
> > +
> > +#define TIMER_LOAD_VAL   0x00FF
> > +#define SYSTICK_CTRL_EN  BIT(0)
> > +/* Clock source: 0 = Ref clock, 1 = CPU clock */
> > +#define SYSTICK_CTRL_CPU_CLK BIT(2)
> > +
> > +/* read the 24-bit timer */
> > +static ulong read_timer(void)
> > +{
> > + struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE;
> > +
> > + /* The timer counts down, therefore convert to an incrementing timer 
> > */
> > + return TIMER_LOAD_VAL - readl(>val);
> > +}
> > +
> > +int timer_init(void)
> > +{
> > + struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE;
> > +
> > + writel(TIMER_LOAD_VAL, >reload);
> > + writel(TIMER_LOAD_VAL, >val);
> > +
> > +#ifdef CONFIG_ARMCORTEXM3_SYSTICK_CPU
> > + /* Use CPU clock, no interrupts */
> > + writel(SYSTICK_CTRL_EN | SYSTICK_CTRL_CPU_CLK, >ctrl);
> > +#else
> > + /* Use external clock, no interrupts */
> > + writel(SYSTICK_CTRL_EN, >ctrl);
> > +#endif
> > +
> > + gd->arch.tbl = 0;
> > + gd->arch.tbu = 0;
> > + gd->arch.lastinc = read_timer();
> > +
> > + return 0;
> > +}
> > +
> > +/* return milli-seconds timer value */
> > +ulong get_timer(ulong base)
> > +{
> > + unsigned long long t = get_ticks() * 1000;
> > +
> > + return (ulong)((t / CONFIG_SYS_HZ_CLOCK)) - base;
> > +}
> > +
> > +unsigned long long get_ticks(void)
> > +{
> > + u32 now = read_timer();
> > +
> > + if (now >= gd->arch.lastinc)
> > + gd->arch.tbl += (now - gd->arch.lastinc);
> > + else
> > + gd->arch.tbl += (TIMER_LOAD_VAL - gd->arch.lastinc) + now;
> > +
> > + gd->arch.lastinc = now;
> > +
> > + return gd->arch.tbl;
> > +}
> > +
> > +ulong get_tbclk(void)
> > +{
> > + return CONFIG_SYS_HZ_CLOCK;
> > +}
>
> And (cc'ing maintainers) we could use this in place of
> arch/arm/mach-stm32/*/timer.c I assume, yes?  Thanks!
>
> --
> Tom

Yes, however as far as I remember the systick is only 24-bit and
usually runs on CPU clock so it will roll over too fast to be useful
without using interrupts. Maybe I have missed something?

/Kamil
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[U-Boot] [PATCH v2] Add single register pin controller driver

[Felix Brack]

This patch adds a pin controller driver supporting devices
using a single configuration register per pin.
Signed-off-by: Felix Brack 
---

Changes in v2:
- add a comment on function single_configure_pins() explaining
  the function and its parameters
- use fdt_getprop() to simplify retrieval of property
  'pinctrl-single,pins' from FDT
- change the return value of single_ofdata_to_platdata()
  to -EINVAL in case of failure
- change the driver name from pcs_pinctrl to single_pinctrl
- minor reformatting to comply with coding style

 drivers/pinctrl/Kconfig  |  10 +++
 drivers/pinctrl/Makefile |   1 +
 drivers/pinctrl/pinctrl-single.c | 143 +++
 3 files changed, 154 insertions(+)
 create mode 100644 drivers/pinctrl/pinctrl-single.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index efcb4c0..32bda65 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -175,6 +175,16 @@ config PIC32_PINCTRL
  by a device tree node which contains both GPIO defintion and pin 
control
  functions.
 
+config PINCTRL_SINGLE
+   bool "Single register pin-control and pin-multiplex driver"
+   depends on DM
+   help
+ This enables pinctrl driver for systems using a single register for
+ pin configuration and multiplexing. TI's AM335X SoCs are examples of
+ such systems.
+ Depending on the platform make sure to also enable OF_TRANSLATE and
+ eventually SPL_OF_TRANSLATE to get correct address translations.
+
 endif
 
 source "drivers/pinctrl/meson/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 512112a..f148f94 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,3 +16,4 @@ obj-$(CONFIG_PIC32_PINCTRL)   += pinctrl_pic32.o
 obj-$(CONFIG_PINCTRL_EXYNOS)   += exynos/
 obj-$(CONFIG_PINCTRL_MESON)+= meson/
 obj-$(CONFIG_PINCTRL_MVEBU)+= mvebu/
+obj-$(CONFIG_PINCTRL_SINGLE)   += pinctrl-single.o
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
new file mode 100644
index 000..e85a4d7
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) EETS GmbH, 2017, Felix Brack 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct single_pdata {
+   fdt_addr_t base;/* first configuration register */
+   int offset; /* index of last configuration register */
+   u32 mask;   /* configuration-value mask bits */
+   int width;  /* configuration register bit width */
+};
+
+struct single_fdt_pin_cfg {
+   fdt32_t reg;/* configuration register offset */
+   fdt32_t val;/* configuration register value */
+};
+
+/**
+ * single_configure_pins() - Configure pins based on FDT data
+ *
+ * @dev: Pointer to single pin configuration device which is the parent of
+ *   the pins node holding the pin configuration data.
+ * @pins: Pointer to the first element of an array of register/value pairs
+ *of type 'struct single_fdt_pin_cfg'. Each such pair describes the
+ *the pin to be configured and the value to be used for configuration.
+ *This pointer points to a 'pinctrl-single,pins' property in the
+ *device-tree.
+ * @size: Size of the 'pins' array in bytes.
+ *The number of register/value pairs in the 'pins' array therefore
+ *equals to 'size / sizeof(struct single_fdt_pin_cfg)'.
+ */
+static int single_configure_pins(struct udevice *dev,
+const struct single_fdt_pin_cfg *pins,
+int size)
+{
+   struct single_pdata *pdata = dev->platdata;
+   int count = size / sizeof(struct single_fdt_pin_cfg);
+   int n, reg;
+   u32 val;
+
+   for (n = 0; n < count; n++) {
+   reg = fdt32_to_cpu(pins->reg);
+   if ((reg < 0) || (reg > pdata->offset)) {
+   dev_dbg(dev, "  invalid register offset 0x%08x\n", reg);
+   pins++;
+   continue;
+   }
+   reg += pdata->base;
+   switch (pdata->width) {
+   case 32:
+   val = readl(reg) & ~pdata->mask;
+   val |= fdt32_to_cpu(pins->val) & pdata->mask;
+   writel(val, reg);
+   dev_dbg(dev, "  reg/val 0x%08x/0x%08x\n",
+   reg, val);
+   break;
+   default:
+   dev_warn(dev, "unsupported register width %i\n",
+pdata->width);
+   }
+   pins++;
+   }
+   return 0;
+}
+
+static int single_set_state_simple(struct udevice *dev,
+  

[U-Boot] [PATCH] armv7m: Make reset_cpu() weak

[Phil Edworthy]

Some devices/boards have their own way to reset the cpu.

Signed-off-by: Phil Edworthy 
---
 arch/arm/cpu/armv7m/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7m/cpu.c b/arch/arm/cpu/armv7m/cpu.c
index 58cde93..c3e4734 100644
--- a/arch/arm/cpu/armv7m/cpu.c
+++ b/arch/arm/cpu/armv7m/cpu.c
@@ -24,7 +24,7 @@ int cleanup_before_linux(void)
 /*
  * Perform the low-level reset.
  */
-void reset_cpu(ulong addr)
+__weak void reset_cpu(ulong addr)
 {
/*
 * Perform reset but keep priority group unchanged.
-- 
2.7.4

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Re: [U-Boot] [PATCH v2 4/7] STiH410: Add STi SDHCI driver

[Patrice CHOTARD]

Hi Jaehoon

On 02/07/2017 11:42 AM, Jaehoon Chung wrote:
> Hi Patrice,
>
> On 02/03/2017 02:13 AM, patrice.chot...@st.com wrote:
>> From: Patrice Chotard 
>>
>> Add SDHCI host controller found on STMicroelctronics SoCs
>
> Just wonder what is flashSS?
> Add the minor comments.

On some ST SoCs, i.e. STiH407/STiH410, the MMC devices can live inside a 
dedicated flashSS sub-system that provides an extend subset of registers 
that can be used to configure the Arasan MMC/SD Host Controller.

This means, that the SDHCI Arasan Controller can be configured to be
eMMC4.5 or 4.3 spec compliant.

W/o these settings the SDHCI will configure and use the MMC/SD
controller with limited features e.g. PIO mode, no DMA, no HS etc.

i will add a comments about that



>
>>
>> Signed-off-by: Patrice Chotard 
>> ---
>>  arch/arm/Kconfig  |   2 +
>>  arch/arm/include/asm/arch-stih410/sdhci.h |  69 +++
>>  drivers/mmc/Kconfig   |   7 ++
>>  drivers/mmc/Makefile  |   1 +
>>  drivers/mmc/sti_sdhci.c   | 140 
>> ++
>>  5 files changed, 219 insertions(+)
>>  create mode 100644 arch/arm/include/asm/arch-stih410/sdhci.h
>>  create mode 100644 drivers/mmc/sti_sdhci.c
>>
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>> index b91a5b7..477f36b 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -987,6 +987,8 @@ config ARCH_STI
>>  select CPU_V7
>>  select DM
>>  select DM_SERIAL
>> +select BLK
>> +select DM_MMC
>>  help
>>Support for STMicroelectronics STiH407/10 SoC family.
>>This SoC is used on Linaro 96Board STiH410-B2260
>> diff --git a/arch/arm/include/asm/arch-stih410/sdhci.h 
>> b/arch/arm/include/asm/arch-stih410/sdhci.h
>> new file mode 100644
>> index 000..f45b961
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-stih410/sdhci.h
>> @@ -0,0 +1,69 @@
>> +/*
>> + * (C) Copyright 2017 Patrice Chotard 
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#ifndef __STI_SDHCI_H__
>> +#define __STI_SDHCI_H__
>> +
>> +#define FLASHSS_MMC_CORE_CONFIG_1   0x400
>> +#define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZBIT(24)
>> +#define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MINBIT(12)
>> +
>> +#define STI_FLASHSS_MMC_CORE_CONFIG_1   \
>> +(FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ   | \
>> + FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN)
>> +
>> +#define FLASHSS_MMC_CORE_CONFIG_2   0x404
>> +#define FLASHSS_MMC_CORECFG_HIGH_SPEED  BIT(28)
>> +#define FLASHSS_MMC_CORECFG_8BIT_EMMC   BIT(20)
>> +#define MAX_BLK_LENGTH_1024 BIT(16)
>> +#define BASE_CLK_FREQ_200   0xc8
>> +
>> +
>
> remove unnecessary white space.

ok

>
>> +#define STI_FLASHSS_MMC_CORE_CONFIG2\
>> +(FLASHSS_MMC_CORECFG_HIGH_SPEED | \
>> + FLASHSS_MMC_CORECFG_8BIT_EMMC  | \
>> + MAX_BLK_LENGTH_1024| \
>> + BASE_CLK_FREQ_200 << 0)
>> +
>> +#define STI_FLASHSS_SDCARD_CORE_CONFIG2 \
>> +(FLASHSS_MMC_CORECFG_HIGH_SPEED | \
>> + MAX_BLK_LENGTH_1024| \
>> + BASE_CLK_FREQ_200)
>> +
>> +#define FLASHSS_MMC_CORE_CONFIG_3   0x408
>> +#define FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC  BIT(28)
>> +#define FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT BIT(20)
>> +#define FLASHSS_MMC_CORECFG_3P3_VOLTBIT(8)
>> +#define FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORTBIT(4)
>> +#define FLASHSS_MMC_CORECFG_SDMABIT(0)
>> +
>> +#define STI_FLASHSS_MMC_CORE_CONFIG3\
>> + (FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC| \
>> + FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT| \
>> + FLASHSS_MMC_CORECFG_3P3_VOLT   | \
>> + FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT   | \
>> + FLASHSS_MMC_CORECFG_SDMA)
>> +
>> +#define STI_FLASHSS_SDCARD_CORE_CONFIG3 \
>> + (FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT   | \
>> + FLASHSS_MMC_CORECFG_3P3_VOLT   | \
>> + FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT   | \
>> + FLASHSS_MMC_CORECFG_SDMA)
>> +
>> +#define FLASHSS_MMC_CORE_CONFIG_4   0x40c
>> +#define FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORTBIT(20)
>> +#define FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORTBIT(16)
>> +#define FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORTBIT(12)
>> +
>> +#define STI_FLASHSS_MMC_CORE_CONFIG4\
>> +(FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT   | \
>> + FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT   | \
>> + FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT)
>> +
>> +#define ST_MMC_CCONFIG_REG_5

Re: [U-Boot] [PATCH 1/7] arm: Add support for STMicroelectronics STiH410 soc

[Patrice CHOTARD]

Hi Simon

On 02/06/2017 04:34 PM, Simon Glass wrote:
> H Patrice,
>
> On 2 February 2017 at 09:00,   wrote:
>> From: Patrice Chotard 
>>
>> The STiH410 is an advanced multi-HD AVC processor with 3D
>> graphics acceleration and 1.5-GHz ARM Cortex-A9 SMP CPU
>> part of the stih407 family.
>>
>> It has wide connectivity including USB 3.0, PCI-e, SATA
>> and gigabit ethernet.
>>
>> Signed-off-by: Patrice Chotard 
>> ---
>>  arch/arm/Kconfig   |  9 ++
>>  arch/arm/Makefile  |  1 +
>>  arch/arm/include/asm/arch-stih410/gpio.h   | 20 +
>>  arch/arm/include/asm/arch-stih410/sti.h| 14 +
>>  arch/arm/include/asm/arch-stih410/syscfg.h | 20 +
>>  arch/arm/mach-sti/Kconfig  | 31 
>>  arch/arm/mach-sti/Makefile |  8 +
>>  arch/arm/mach-sti/cpu.c| 16 ++
>>  arch/arm/mach-sti/timer.c  | 47 
>> ++
>>  9 files changed, 166 insertions(+)
>>  create mode 100644 arch/arm/include/asm/arch-stih410/gpio.h
>>  create mode 100644 arch/arm/include/asm/arch-stih410/sti.h
>>  create mode 100644 arch/arm/include/asm/arch-stih410/syscfg.h
>>  create mode 100644 arch/arm/mach-sti/Kconfig
>>  create mode 100644 arch/arm/mach-sti/Makefile
>>  create mode 100644 arch/arm/mach-sti/cpu.c
>>  create mode 100644 arch/arm/mach-sti/timer.c
>
> Are you able to use driver model for the timer (and maybe even CPU)?

I will have a look at this and will try to convert timer and CPU do DM 
in the next series submission

Thanks

Patrice

>
> Regards,
> Simon
>
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Re: [U-Boot] [PATCH v2 1/3] scripts: import bin2c.c from Linux 4.10-rc6

[Tom Rini]

On Tue, Feb 07, 2017 at 09:23:38PM +0900, Masahiro Yamada wrote:
> Hi Bin,
> 
> 2017-02-07 11:38 GMT+09:00 Bin Meng :
> > On Mon, Jan 30, 2017 at 10:12 AM, Masahiro Yamada
> >  wrote:
> >> Import scripts/basic/bin2c.c of Linux.
> >>
> >> In Linux Kernel, this file was moved to scripts/basic directory by
> >> commit 8370edea81e3 ("bin2c: move bin2c in scripts/basic").
> >>
> >> In U-boot, we do not need to follow that commit.  Just put it in the
> >
> > Sorry for jumping out late, but one nits:
> >
> > U-boot -> U-Boot
> 
> Thanks for pointing this out.
> 
> 
> Tom,
> Could you fix s/U-boot/U-Boot/ when this patch is applied, please?

I'll endeavor to remember :)

-- 
Tom


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[U-Boot] [PATCH] ARM: uniphier: enable generic EHCI driver for uniphier_v8_defconfig

[Masahiro Yamada]

The LD11 SoC is equipped with USB EHCI controllers.

Signed-off-by: Masahiro Yamada 
---

 configs/uniphier_v8_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig
index b6010cc..5dadc4c 100644
--- a/configs/uniphier_v8_defconfig
+++ b/configs/uniphier_v8_defconfig
@@ -30,4 +30,6 @@ CONFIG_MMC_SDHCI_CADENCE=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
-- 
2.7.4

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Re: [U-Boot] [PATCH v2 1/3] scripts: import bin2c.c from Linux 4.10-rc6

[Masahiro Yamada]

Hi Bin,

2017-02-07 11:38 GMT+09:00 Bin Meng :
> On Mon, Jan 30, 2017 at 10:12 AM, Masahiro Yamada
>  wrote:
>> Import scripts/basic/bin2c.c of Linux.
>>
>> In Linux Kernel, this file was moved to scripts/basic directory by
>> commit 8370edea81e3 ("bin2c: move bin2c in scripts/basic").
>>
>> In U-boot, we do not need to follow that commit.  Just put it in the
>
> Sorry for jumping out late, but one nits:
>
> U-boot -> U-Boot

Thanks for pointing this out.


Tom,
Could you fix s/U-boot/U-Boot/ when this patch is applied, please?





-- 
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Masahiro Yamada
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Re: [U-Boot] [PATCH v2 4/7] STiH410: Add STi SDHCI driver

[Jaehoon Chung]

Hi Patrice,

On 02/03/2017 02:13 AM, patrice.chot...@st.com wrote:
> From: Patrice Chotard 
> 
> Add SDHCI host controller found on STMicroelctronics SoCs

Just wonder what is flashSS?
Add the minor comments.

> 
> Signed-off-by: Patrice Chotard 
> ---
>  arch/arm/Kconfig  |   2 +
>  arch/arm/include/asm/arch-stih410/sdhci.h |  69 +++
>  drivers/mmc/Kconfig   |   7 ++
>  drivers/mmc/Makefile  |   1 +
>  drivers/mmc/sti_sdhci.c   | 140 
> ++
>  5 files changed, 219 insertions(+)
>  create mode 100644 arch/arm/include/asm/arch-stih410/sdhci.h
>  create mode 100644 drivers/mmc/sti_sdhci.c
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index b91a5b7..477f36b 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -987,6 +987,8 @@ config ARCH_STI
>   select CPU_V7
>   select DM
>   select DM_SERIAL
> + select BLK
> + select DM_MMC
>   help
> Support for STMicroelectronics STiH407/10 SoC family.
> This SoC is used on Linaro 96Board STiH410-B2260
> diff --git a/arch/arm/include/asm/arch-stih410/sdhci.h 
> b/arch/arm/include/asm/arch-stih410/sdhci.h
> new file mode 100644
> index 000..f45b961
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-stih410/sdhci.h
> @@ -0,0 +1,69 @@
> +/*
> + * (C) Copyright 2017 Patrice Chotard 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#ifndef __STI_SDHCI_H__
> +#define __STI_SDHCI_H__
> +
> +#define FLASHSS_MMC_CORE_CONFIG_10x400
> +#define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ BIT(24)
> +#define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN BIT(12)
> +
> +#define STI_FLASHSS_MMC_CORE_CONFIG_1\
> + (FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ   | \
> +  FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN)
> +
> +#define FLASHSS_MMC_CORE_CONFIG_20x404
> +#define FLASHSS_MMC_CORECFG_HIGH_SPEED   BIT(28)
> +#define FLASHSS_MMC_CORECFG_8BIT_EMMCBIT(20)
> +#define MAX_BLK_LENGTH_1024  BIT(16)
> +#define BASE_CLK_FREQ_2000xc8
> +
> +

remove unnecessary white space.

> +#define STI_FLASHSS_MMC_CORE_CONFIG2 \
> + (FLASHSS_MMC_CORECFG_HIGH_SPEED | \
> +  FLASHSS_MMC_CORECFG_8BIT_EMMC  | \
> +  MAX_BLK_LENGTH_1024| \
> +  BASE_CLK_FREQ_200 << 0)
> +
> +#define STI_FLASHSS_SDCARD_CORE_CONFIG2  \
> + (FLASHSS_MMC_CORECFG_HIGH_SPEED | \
> +  MAX_BLK_LENGTH_1024| \
> +  BASE_CLK_FREQ_200)
> +
> +#define FLASHSS_MMC_CORE_CONFIG_30x408
> +#define FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC   BIT(28)
> +#define FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT  BIT(20)
> +#define FLASHSS_MMC_CORECFG_3P3_VOLT BIT(8)
> +#define FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT BIT(4)
> +#define FLASHSS_MMC_CORECFG_SDMA BIT(0)
> +
> +#define STI_FLASHSS_MMC_CORE_CONFIG3 \
> +  (FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC| \
> +  FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT| \
> +  FLASHSS_MMC_CORECFG_3P3_VOLT   | \
> +  FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT   | \
> +  FLASHSS_MMC_CORECFG_SDMA)
> +
> +#define STI_FLASHSS_SDCARD_CORE_CONFIG3  \
> +  (FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT   | \
> +  FLASHSS_MMC_CORECFG_3P3_VOLT   | \
> +  FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT   | \
> +  FLASHSS_MMC_CORECFG_SDMA)
> +
> +#define FLASHSS_MMC_CORE_CONFIG_40x40c
> +#define FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT BIT(20)
> +#define FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT BIT(16)
> +#define FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT BIT(12)
> +
> +#define STI_FLASHSS_MMC_CORE_CONFIG4 \
> + (FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT   | \
> +  FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT   | \
> +  FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT)
> +
> +#define ST_MMC_CCONFIG_REG_5 0x210
> +#define SYSCONF_MMC1_ENABLE_BIT  3
> +
> +#endif   /* _STI_SDHCI_H_ */
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index 0c07781..dfdec27 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -287,6 +287,13 @@ config MMC_SDHCI_SPEAR
>  
> If unsure, say N.
>  
> +config MMC_SDHCI_STI
> + bool "SDHCI support for STMicroelectronics SoC"
> + depends on MMC_SDHCI
> + help
> +   This selects the Secure Digital Host Controller Interface (SDHCI)
> +   on STMicroelectronics STiH410 SoC.
> +
>  config MMC_SDHCI_XENON
>   bool "SDHCI support for the Xenon SDHCI controller"
>   depends on 

Re: [U-Boot] [PATCH v1] Add single register pin controller driver

[Felix Brack]

Hello Simon,

Thank you for the review! I will submit an improved version of the patch.

On 06.02.2017 16:34, Simon Glass wrote:
> Hi Felix,
> 
> On 3 February 2017 at 05:29, Felix Brack  wrote:
>> This patch adds a pin controller driver supporting devices
>> using a single configuration register per pin.
>> Signed-off-by: Felix Brack 
>> ---
>>
>>  drivers/pinctrl/Kconfig  |  10 +++
>>  drivers/pinctrl/Makefile |   1 +
>>  drivers/pinctrl/pinctrl-single.c | 138 
>> +++
>>  3 files changed, 149 insertions(+)
>>  create mode 100644 drivers/pinctrl/pinctrl-single.c
>>
>> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
>> index efcb4c0..32bda65 100644
>> --- a/drivers/pinctrl/Kconfig
>> +++ b/drivers/pinctrl/Kconfig
>> @@ -175,6 +175,16 @@ config PIC32_PINCTRL
>>   by a device tree node which contains both GPIO defintion and pin 
>> control
>>   functions.
>>
>> +config PINCTRL_SINGLE
>> +   bool "Single register pin-control and pin-multiplex driver"
>> +   depends on DM
>> +   help
>> + This enables pinctrl driver for systems using a single register for
>> + pin configuration and multiplexing. TI's AM335X SoCs are examples 
>> of
>> + such systems.
>> + Depending on the platform make sure to also enable OF_TRANSLATE and
>> + eventually SPL_OF_TRANSLATE to get correct address translations.
>> +
>>  endif
>>
>>  source "drivers/pinctrl/meson/Kconfig"
>> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
>> index 512112a..f148f94 100644
>> --- a/drivers/pinctrl/Makefile
>> +++ b/drivers/pinctrl/Makefile
>> @@ -16,3 +16,4 @@ obj-$(CONFIG_PIC32_PINCTRL)   += pinctrl_pic32.o
>>  obj-$(CONFIG_PINCTRL_EXYNOS)   += exynos/
>>  obj-$(CONFIG_PINCTRL_MESON)+= meson/
>>  obj-$(CONFIG_PINCTRL_MVEBU)+= mvebu/
>> +obj-$(CONFIG_PINCTRL_SINGLE)   += pinctrl-single.o
>> diff --git a/drivers/pinctrl/pinctrl-single.c 
>> b/drivers/pinctrl/pinctrl-single.c
>> new file mode 100644
>> index 000..f9e04f0
>> --- /dev/null
>> +++ b/drivers/pinctrl/pinctrl-single.c
>> @@ -0,0 +1,138 @@
>> +/*
>> + * Copyright (C) EETS GmbH, 2017, Felix Brack 
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +struct single_pdata {
>> +   fdt_addr_t base;/* first configuration register */
>> +   int offset; /* index of last configuration register */
>> +   u32 mask;   /* configuration-value mask bits */
>> +   int width;  /* configuration register bit width */
>> +};
>> +
>> +struct single_fdt_pin_cfg {
>> +   fdt32_t reg;
>> +   fdt32_t val;
>> +};
>> +
>> +static int single_configure_pins(struct udevice *dev,
>> +const struct single_fdt_pin_cfg *pins,
>> +int size)
> 
> Can you add a comment about this function? In particular, mention that
> pins is a pointer to a device-tree property.
> 

Yes, I will.

>> +{
>> +   struct single_pdata *pdata = dev->platdata;
>> +   int count = size / sizeof(struct single_fdt_pin_cfg);
>> +   int n, reg;
>> +   u32 val;
>> +
>> +   for (n = 0; n < count; n++) {
>> +   reg = fdt32_to_cpu(pins->reg);
> 
> 
>> +   if ((reg < 0) || (reg > pdata->offset)) {
>> +   dev_dbg(dev, "  invalid register offset 0x%08x\n", 
>> reg);
>> +   pins++;
>> +   continue;
>> +   }
>> +   reg += pdata->base;
>> +   switch (pdata->width) {
>> +   case 32: {
> 
> case should be at same level as switch
> 

Right, my bad.

>> +   val = readl(reg) & ~pdata->mask;
>> +   val |= fdt32_to_cpu(pins->val) & pdata->mask;
>> +   writel(val, reg);
>> +   dev_dbg(dev, "  reg/val 0x%08x/0x%08x\n",
>> +   reg, val);
>> +   break;
>> +   }
>> +   default: {
>> +   dev_warn(dev, "unsupported register width 
>> %i\n",
>> +pdata->width);
>> +   }
>> +   }
>> +   pins++;
>> +   }
>> +   return 0;
>> +}
>> +
>> +static int single_set_state_simple(struct udevice *dev,
>> +  struct udevice *periph)
>> +{
>> +   const void *fdt = gd->fdt_blob;
>> +   const struct single_fdt_pin_cfg *prop;
>> +   int len;
>> +   int offset;
>> +   const char *name;
>> +
>> +   offset = fdt_first_property_offset(fdt, periph->of_offset);
>> +   if (offset < 0)
>> +   

[U-Boot] [PATCH v2 4/4] configs: at91sam9x5ek: move SYS_NO_FLASH to defconfig

[Wenyou Yang]

Move CONFIG_SYS_NO_FLASH to the configs/sama5d4*_defconfig file.

Signed-off-by: Wenyou Yang 
Reviewed-by: Simon Glass 
---

Changes in v2:
 - rebase on the patch set:
[RESEND PATCH v2] ARM: at91: add default config file for sama5d36ek CMP 
board
http://lists.denx.de/pipermail/u-boot/2017-February/280525.html

 configs/at91sam9x5ek_dataflash_defconfig | 1 +
 configs/at91sam9x5ek_mmc_defconfig   | 1 +
 configs/at91sam9x5ek_nandflash_defconfig | 1 +
 configs/at91sam9x5ek_spiflash_defconfig  | 1 +
 include/configs/at91sam9x5ek.h   | 3 ---
 5 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/configs/at91sam9x5ek_dataflash_defconfig 
b/configs/at91sam9x5ek_dataflash_defconfig
index d7408e8b29..8351281a79 100644
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -6,6 +6,7 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_DATAFLASH"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9x5ek_mmc_defconfig 
b/configs/at91sam9x5ek_mmc_defconfig
index 07f62fc38b..6d212d40e8 100644
--- a/configs/at91sam9x5ek_mmc_defconfig
+++ b/configs/at91sam9x5ek_mmc_defconfig
@@ -6,6 +6,7 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_MMC"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/configs/at91sam9x5ek_nandflash_defconfig 
b/configs/at91sam9x5ek_nandflash_defconfig
index 15ac465abd..d90481ec1c 100644
--- a/configs/at91sam9x5ek_nandflash_defconfig
+++ b/configs/at91sam9x5ek_nandflash_defconfig
@@ -11,6 +11,7 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/at91sam9x5ek_spiflash_defconfig 
b/configs/at91sam9x5ek_spiflash_defconfig
index d44d851848..b9fbf39d08 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -6,6 +6,7 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index a11d5748da..c133eb85ab 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -50,9 +50,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-/* no NOR flash */
-#define CONFIG_SYS_NO_FLASH
-
 /*
  * Command line configuration.
  */
-- 
2.11.0

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[U-Boot] [PATCH v2 3/4] board: at91sam9x5ek: enable early debug UART

[Wenyou Yang]

Enable early debug UART to debug problems when an ICE or other
debug mechanism is not available.

Signed-off-by: Wenyou Yang 
Reviewed-by: Simon Glass 
---

Changes in v2: None

 board/atmel/at91sam9x5ek/at91sam9x5ek.c  | 14 ++
 configs/at91sam9x5ek_dataflash_defconfig |  6 ++
 configs/at91sam9x5ek_mmc_defconfig   |  6 ++
 configs/at91sam9x5ek_nandflash_defconfig |  6 ++
 configs/at91sam9x5ek_spiflash_defconfig  |  6 ++
 5 files changed, 38 insertions(+)

diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c 
b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index 9bd5eaf363..77714db3e7 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -192,11 +193,24 @@ int board_mmc_init(bd_t *bd)
 }
 #endif
 
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+   at91_seriald_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
+#ifdef CONFIG_DEBUG_UART
+   debug_uart_init();
+#else
at91_seriald_hw_init();
+#endif
return 0;
 }
+#endif
 
 int board_init(void)
 {
diff --git a/configs/at91sam9x5ek_dataflash_defconfig 
b/configs/at91sam9x5ek_dataflash_defconfig
index c3feca28bc..d7408e8b29 100644
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -37,6 +37,12 @@ CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xf200
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
 CONFIG_DM_SPI=y
 CONFIG_ATMEL_SPI=y
diff --git a/configs/at91sam9x5ek_mmc_defconfig 
b/configs/at91sam9x5ek_mmc_defconfig
index f4b0edd4ca..07f62fc38b 100644
--- a/configs/at91sam9x5ek_mmc_defconfig
+++ b/configs/at91sam9x5ek_mmc_defconfig
@@ -37,6 +37,12 @@ CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xf200
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
 CONFIG_DM_SPI=y
 CONFIG_ATMEL_SPI=y
diff --git a/configs/at91sam9x5ek_nandflash_defconfig 
b/configs/at91sam9x5ek_nandflash_defconfig
index 5c3463260e..15ac465abd 100644
--- a/configs/at91sam9x5ek_nandflash_defconfig
+++ b/configs/at91sam9x5ek_nandflash_defconfig
@@ -44,6 +44,12 @@ CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_ATMEL_USART=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xf200
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DM_SPI=y
 CONFIG_ATMEL_SPI=y
 CONFIG_USB=y
diff --git a/configs/at91sam9x5ek_spiflash_defconfig 
b/configs/at91sam9x5ek_spiflash_defconfig
index 939a6bbd4a..d44d851848 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -37,6 +37,12 @@ CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xf200
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
 CONFIG_DM_SPI=y
 CONFIG_ATMEL_SPI=y
-- 
2.11.0

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[U-Boot] [PATCH v2 2/4] board: at91sam9x5ek: clean up code

[Wenyou Yang]

Since the introduction of the pinctrl and clk driver and
the dts file, remove unneeded hard coded related code from
the board file

Signed-off-by: Wenyou Yang 
Reviewed-by: Simon Glass 
---

Changes in v2: None

 board/atmel/at91sam9x5ek/at91sam9x5ek.c | 68 -
 1 file changed, 68 deletions(-)

diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c 
b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index 0ae42dd158..9bd5eaf363 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -15,17 +15,10 @@
 #include 
 #include 
 #include 
-#ifdef CONFIG_MACB
-#include 
-#endif
-#include 
 #ifdef CONFIG_LCD_INFO
 #include 
 #include 
 #endif
-#ifdef CONFIG_ATMEL_SPI
-#include 
-#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -92,21 +85,6 @@ static void at91sam9x5ek_nand_hw_init(void)
 }
 #endif
 
-int board_eth_init(bd_t *bis)
-{
-   int rc = 0;
-
-#ifdef CONFIG_MACB
-   if (has_emac0())
-   rc = macb_eth_initialize(0,
-   (void *)ATMEL_BASE_EMAC0, 0x00);
-   if (has_emac1())
-   rc = macb_eth_initialize(1,
-   (void *)ATMEL_BASE_EMAC1, 0x00);
-#endif
-   return rc;
-}
-
 #ifdef CONFIG_LCD
 vidinfo_t panel_info = {
.vl_col = 800,
@@ -205,42 +183,6 @@ void lcd_show_board_info(void)
 #endif /* CONFIG_LCD_INFO */
 #endif /* CONFIG_LCD */
 
-#ifndef CONFIG_DM_SPI
-/* SPI chip select control */
-#ifdef CONFIG_ATMEL_SPI
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-   return bus == 0 && cs < 2;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-   switch (slave->cs) {
-   case 1:
-   at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
-   break;
-   case 0:
-   default:
-   at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
-   break;
-   }
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-   switch (slave->cs) {
-   case 1:
-   at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
-   break;
-   case 0:
-   default:
-   at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
-   break;
-   }
-}
-#endif /* CONFIG_ATMEL_SPI */
-#endif
-
 #ifdef CONFIG_GENERIC_ATMEL_MCI
 int board_mmc_init(bd_t *bd)
 {
@@ -268,14 +210,6 @@ int board_init(void)
at91sam9x5ek_nand_hw_init();
 #endif
 
-#ifdef CONFIG_ATMEL_SPI
-   at91_spi0_hw_init(1 << 4);
-#endif
-
-#ifdef CONFIG_MACB
-   at91_macb_hw_init();
-#endif
-
 #if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI)
at91_uhp_hw_init();
 #endif
@@ -302,8 +236,6 @@ void at91_spl_board_init(void)
at91_mci_hw_init();
 #elif CONFIG_SYS_USE_NANDFLASH
at91sam9x5ek_nand_hw_init();
-#elif CONFIG_SYS_USE_SPIFLASH
-   at91_spi0_hw_init(1 << 4);
 #endif
 }
 
-- 
2.11.0

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[U-Boot] [PATCH v2 1/4] board: at91sam9x5ek: move config options to defconfig

[Wenyou Yang]

Enable CONFIG_CLK and CONFIG_PINCTRL to support at91 clock
driver and at91 pinctrl driver.

Move some config options to configs/sama5d4ek_*_defconfig, and
make the drivers, spi, emac, gpio, serial and ehci usb to support
the driver model.

Due to the limitation of internal SRAM size, disable the SPL option
for the spi flash configuration.

Signed-off-by: Wenyou Yang 
Reviewed-by: Simon Glass 
---

Changes in v2: None

 board/atmel/at91sam9x5ek/at91sam9x5ek.c  |  2 ++
 configs/at91sam9x5ek_dataflash_defconfig | 20 +++-
 configs/at91sam9x5ek_mmc_defconfig   | 20 +++-
 configs/at91sam9x5ek_nandflash_defconfig | 20 +++-
 configs/at91sam9x5ek_spiflash_defconfig  | 27 +++
 include/configs/at91sam9x5ek.h   | 19 +--
 6 files changed, 79 insertions(+), 29 deletions(-)

diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c 
b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index cc81776f9b..0ae42dd158 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -205,6 +205,7 @@ void lcd_show_board_info(void)
 #endif /* CONFIG_LCD_INFO */
 #endif /* CONFIG_LCD */
 
+#ifndef CONFIG_DM_SPI
 /* SPI chip select control */
 #ifdef CONFIG_ATMEL_SPI
 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
@@ -238,6 +239,7 @@ void spi_cs_deactivate(struct spi_slave *slave)
}
 }
 #endif /* CONFIG_ATMEL_SPI */
+#endif
 
 #ifdef CONFIG_GENERIC_ATMEL_MCI
 int board_mmc_init(bd_t *bd)
diff --git a/configs/at91sam9x5ek_dataflash_defconfig 
b/configs/at91sam9x5ek_dataflash_defconfig
index e07e2175e0..c3feca28bc 100644
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9X5EK=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_DATAFLASH"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
@@ -21,9 +22,26 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9x5ek_mmc_defconfig 
b/configs/at91sam9x5ek_mmc_defconfig
index 9a95a0496a..f4b0edd4ca 100644
--- a/configs/at91sam9x5ek_mmc_defconfig
+++ b/configs/at91sam9x5ek_mmc_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9X5EK=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_MMC"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
@@ -21,9 +22,26 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9x5ek_nandflash_defconfig 
b/configs/at91sam9x5ek_nandflash_defconfig
index 05907b7859..5c3463260e 100644
--- a/configs/at91sam9x5ek_nandflash_defconfig
+++ b/configs/at91sam9x5ek_nandflash_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
@@ -27,9 +28,26 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/at91sam9x5ek_spiflash_defconfig 
b/configs/at91sam9x5ek_spiflash_defconfig
index 5fc512b998..939a6bbd4a 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -1,18 +1,12 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9X5EK=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y

[U-Boot] [PATCH v2 0/4] board: at91sam9x5ek: convert board to support DM and DT

[Wenyou Yang]

The purpose of the patch set is to convert the board to support
Driver Model and Device Tree.
It is based on the patch set:
[PATCH v5 0/2] pinctrl: at91: Add pinctrl driver
http://lists.denx.de/pipermail/u-boot/2017-February/280463.html

Changes in v2:
 - rebase on the patch set:
[RESEND PATCH v2] ARM: at91: add default config file for sama5d36ek CMP 
board
http://lists.denx.de/pipermail/u-boot/2017-February/280525.html

Wenyou Yang (4):
  board: at91sam9x5ek: move config options to defconfig
  board: at91sam9x5ek: clean up code
  board: at91sam9x5ek: enable early debug UART
  configs: at91sam9x5ek: move SYS_NO_FLASH to defconfig

 board/atmel/at91sam9x5ek/at91sam9x5ek.c  | 80 ++--
 configs/at91sam9x5ek_dataflash_defconfig | 27 ++-
 configs/at91sam9x5ek_mmc_defconfig   | 27 ++-
 configs/at91sam9x5ek_nandflash_defconfig | 27 ++-
 configs/at91sam9x5ek_spiflash_defconfig  | 34 ++
 include/configs/at91sam9x5ek.h   | 22 +
 6 files changed, 119 insertions(+), 98 deletions(-)

-- 
2.11.0

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[U-Boot] [PATCH v5] dm/mmc: gen_atmel_mci: Add driver model support for mci

[Wenyou Yang]

Add the driver model support for Atmel mci while retaining the
existing legacy code. This allows the driver to support boards
that have converted to driver model as well as those that have not.

Signed-off-by: Wenyou Yang 
Reviewed-by: Simon Glass 
---

Changes in v5:
 - Add the Reviewed-by tag.
 - Rebase

Changes in v4:
 - Remove unneeded #ifdef CONFIG_DM_MMC.

Changes in v3:
 - Use unified #ifdef CONFIG_DM_MMC #else...#endif, instead of #ifndef 
CONFIG_DM_MMC
   #else...#endif.

Changes in v2:
 - Change the return type of atmel_mci_setup_cfg() from int to void.
 - Add comments on the features depends on the IP version.
 - Add the error handle path of clock.
 - Fix the missing use priv->bus_clk_rate.
 - Return from mmc_bind() directly, instead of checking its return.

 drivers/mmc/Kconfig |   9 +++
 drivers/mmc/gen_atmel_mci.c | 161 +++-
 2 files changed, 169 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 0c07781115..70e3c8cf81 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -36,6 +36,15 @@ config DM_MMC_OPS
 
 if MMC
 
+config GENERIC_ATMEL_MCI
+   bool "Atmel Multimedia Card Interface support"
+   depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_AT91
+   help
+ This enables support for Atmel High Speed Multimedia Card Interface
+ (HSMCI), which supports the MultiMedia Card (MMC) Specification V4.3,
+ the SD Memory Card Specification V2.0, the SDIO V2.0 specification
+ and CE-ATA V1.1.
+
 config SPL_MMC_TINY
bool "Tiny MMC framework in SPL"
help
diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c
index 7dc4a5de74..0ca68c05be 100644
--- a/drivers/mmc/gen_atmel_mci.c
+++ b/drivers/mmc/gen_atmel_mci.c
@@ -10,6 +10,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -18,8 +19,11 @@
 #include 
 #include 
 #include 
+#include 
 #include "atmel_mci.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CONFIG_SYS_MMC_CLK_OD
 # define CONFIG_SYS_MMC_CLK_OD 15
 #endif
@@ -37,6 +41,10 @@ struct atmel_mci_priv {
struct atmel_mci*mci;
unsigned intinitialized:1;
unsigned intcurr_clk;
+#ifdef CONFIG_DM_MMC
+   struct mmc  mmc;
+   ulong   bus_clk_rate;
+#endif
 };
 
 /* Read Atmel MCI IP version */
@@ -58,11 +66,19 @@ static void dump_cmd(u32 cmdr, u32 arg, u32 status, const 
char* msg)
 }
 
 /* Setup for MCI Clock and Block Size */
+#ifdef CONFIG_DM_MMC
+static void mci_set_mode(struct atmel_mci_priv *priv, u32 hz, u32 blklen)
+{
+   struct mmc *mmc = >mmc;
+   u32 bus_hz = priv->bus_clk_rate;
+#else
 static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
 {
struct atmel_mci_priv *priv = mmc->priv;
-   atmel_mci_t *mci = priv->mci;
u32 bus_hz = get_mci_clk_rate();
+#endif
+
+   atmel_mci_t *mci = priv->mci;
u32 clkdiv = 255;
unsigned int version = atmel_mci_get_version(mci);
u32 clkodd = 0;
@@ -202,10 +218,18 @@ io_fail:
  * Sends a command out on the bus and deals with the block data.
  * Takes the mmc pointer, a command pointer, and an optional data pointer.
  */
+#ifdef CONFIG_DM_MMC
+static int atmel_mci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+   struct atmel_mci_priv *priv = dev_get_priv(dev);
+   struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
 static int
 mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 {
struct atmel_mci_priv *priv = mmc->priv;
+#endif
atmel_mci_t *mci = priv->mci;
u32 cmdr;
u32 error_flags = 0;
@@ -335,17 +359,29 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct 
mmc_data *data)
return 0;
 }
 
+#ifdef CONFIG_DM_MMC
+static int atmel_mci_set_ios(struct udevice *dev)
+{
+   struct atmel_mci_priv *priv = dev_get_priv(dev);
+   struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
 /* Entered into mmc structure during driver init */
 static int mci_set_ios(struct mmc *mmc)
 {
struct atmel_mci_priv *priv = mmc->priv;
+#endif
+
atmel_mci_t *mci = priv->mci;
int bus_width = mmc->bus_width;
unsigned int version = atmel_mci_get_version(mci);
int busw;
 
/* Set the clock speed */
+#ifdef CONFIG_DM_MMC
+   mci_set_mode(priv, mmc->clock, MMC_DEFAULT_BLKLEN);
+#else
mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN);
+#endif
 
/*
 * set the bus width and select slot for this interface
@@ -374,10 +410,17 @@ static int mci_set_ios(struct mmc *mmc)
return 0;
 }
 
+
+#ifdef CONFIG_DM_MMC
+static int atmel_mci_hw_init(struct atmel_mci_priv *priv)
+{
+#else
 /* Entered into mmc structure during driver init */
 static int mci_init(struct mmc *mmc)
 {
struct atmel_mci_priv *priv = mmc->priv;
+#endif
+
 

[U-Boot] [RESEND PATCH v2] ARM: at91: add default config file for sama5d36ek CMP board

[Wenyou Yang]

The sama5d36ek CMP board is the variant of sama5d3xek board.
It is equipped with the low-power DDR2 SDRAM, PMIC ACT8865, and
some power rail. Its main purpose is used to measure the power
consumption. As those changes are done in at91bootstrap,
in U-Boot, use another device tree file, no code to change.

As there is additional power consumption due to the USB Host
and USB Device enabled, for the power consumption measurement,
disable the USB host and device.

Signed-off-by: Wenyou Yang 
---

Changes in v2:
 - rebase on the patch set:
[PATCH v2 0/7] board: sama5d3: convert boards to support DM/DT
http://lists.denx.de/pipermail/u-boot/2017-February/280515.html

 configs/sama5d36ek_cmp_mmc_defconfig   | 58 ++
 configs/sama5d36ek_cmp_nandflash_defconfig | 57 +
 configs/sama5d36ek_cmp_spiflash_defconfig  | 57 +
 3 files changed, 172 insertions(+)
 create mode 100644 configs/sama5d36ek_cmp_mmc_defconfig
 create mode 100644 configs/sama5d36ek_cmp_nandflash_defconfig
 create mode 100644 configs/sama5d36ek_cmp_spiflash_defconfig

diff --git a/configs/sama5d36ek_cmp_mmc_defconfig 
b/configs/sama5d36ek_cmp_mmc_defconfig
new file mode 100644
index 00..ee72c59afe
--- /dev/null
+++ b/configs/sama5d36ek_cmp_mmc_defconfig
@@ -0,0 +1,58 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3XEK=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xee00
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
+CONFIG_LCD=y
diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig 
b/configs/sama5d36ek_cmp_nandflash_defconfig
new file mode 100644
index 00..aabbf4a4da
--- /dev/null
+++ b/configs/sama5d36ek_cmp_nandflash_defconfig
@@ -0,0 +1,57 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3XEK=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names 
interrupt-parent"
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xee00
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
+CONFIG_LCD=y
diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig 
b/configs/sama5d36ek_cmp_spiflash_defconfig
new file mode 100644
index 00..e4131d9d2a
--- /dev/null
+++ b/configs/sama5d36ek_cmp_spiflash_defconfig
@@ -0,0 +1,57 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3XEK=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH"

[U-Boot] [PATCH v2] ARM: at91: add default config file for sama5d36ek CMP board

[Wenyou Yang]

The sama5d36ek CMP board is the variant of sama5d3xek board.
It is equipped with the low-power DDR2 SDRAM, PMIC ACT8865, and
some power rail. Its main purpose is used to measure the power
consumption. As those changes are done in at91bootstrap,
in U-Boot, use another device tree file, no code to change.

As there is additional power consumption due to the USB Host
and USB Device enabled, for the power consumption measurement,
disable the USB host and device.

Signed-off-by: Wenyou Yang 
---

Changes in v2:
 - rebase on the patch set:
[PATCH v2 0/7] board: sama5d3: convert boards to support DM/DT
http://lists.denx.de/pipermail/u-boot/2017-February/280515.html

 configs/sama5d36ek_cmp_mmc_defconfig   | 58 ++
 configs/sama5d36ek_cmp_nandflash_defconfig | 57 +
 configs/sama5d36ek_cmp_spiflash_defconfig  | 57 +
 include/configs/sama5d3xek.h   |  1 +
 4 files changed, 173 insertions(+)
 create mode 100644 configs/sama5d36ek_cmp_mmc_defconfig
 create mode 100644 configs/sama5d36ek_cmp_nandflash_defconfig
 create mode 100644 configs/sama5d36ek_cmp_spiflash_defconfig

diff --git a/configs/sama5d36ek_cmp_mmc_defconfig 
b/configs/sama5d36ek_cmp_mmc_defconfig
new file mode 100644
index 00..ee72c59afe
--- /dev/null
+++ b/configs/sama5d36ek_cmp_mmc_defconfig
@@ -0,0 +1,58 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3XEK=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xee00
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
+CONFIG_LCD=y
diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig 
b/configs/sama5d36ek_cmp_nandflash_defconfig
new file mode 100644
index 00..aabbf4a4da
--- /dev/null
+++ b/configs/sama5d36ek_cmp_nandflash_defconfig
@@ -0,0 +1,57 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3XEK=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names 
interrupt-parent"
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xee00
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
+CONFIG_LCD=y
diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig 
b/configs/sama5d36ek_cmp_spiflash_defconfig
new file mode 100644
index 00..e4131d9d2a
--- /dev/null
+++ b/configs/sama5d36ek_cmp_spiflash_defconfig
@@ -0,0 +1,57 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3XEK=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
+CONFIG_FIT=y

Re: [U-Boot] [PATCH] drivers: net: phy: atheros: apply the previous register setting for AR8031 to fix the voltage peak issue

[Sekhar Nori]

On Monday 06 February 2017 11:06 PM, Ken.Lin wrote:

>>> The register setting would turn out to be 0x3D47 on our project boards and
>> our signal measurement results show the patch (v2 version,
>> https://patchwork.ozlabs.org/patch/723461/)) could fix the voltage peak 
>> issue.
>>> The proposed solution is to follow the implementation in previous commits,
>> which include the reserved bits settings in SerDes Test and System Mode 
>> Control
>> register.

>> So what does the register setting turn out to be with my patch below ?
>>
>> What are the "previous commits" you refer to ?

Thanks for the references to the commits. You left out answering my 
question about what register settings you see with my patch.

I have included another patch now with some debug enabled. Can you 
apply this patch to latest u-boot master, run on your board and send me 
the log ? Here is what I see on AM335x EVM-SK:

U-Boot 2017.03-rc1-00058-g1216f9a0851f (Feb 07 2017 - 13:55:38 +0530)

CPU  : AM335X-GP rev 1.0
Model: TI AM335x EVM-SK
DRAM:  256 MiB
NAND:  0 MiB
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
reading uboot.env
ERROR: No USB device found

at ../drivers/usb/gadget/ether.c:2709/usb_ether_init()
Net:   ar8031_config: value read back 0x2c47, written: 0x2d47
eth0: ethernet@4a10
Hit any key to stop autoboot:  0 

Thanks,
Sekhar

---8<---
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index b34cdd3d87dc..5c0a36676ce9 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -28,12 +28,18 @@ static int ar8021_config(struct phy_device *phydev)
 
 static int ar8031_config(struct phy_device *phydev)
 {
+   int regval;
+
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
  AR803x_DEBUG_REG_5);
+   regval = phy_read(phydev, MDIO_DEVAD_NONE,
+ AR803x_PHY_DEBUG_DATA_REG);
+   printf("%s: value read back 0x%x, written: 0x%x\n",
+   __func__, regval, regval | 
AR803x_RGMII_TX_CLK_DLY);
phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
- AR803x_RGMII_TX_CLK_DLY);
+ regval | AR803x_RGMII_TX_CLK_DLY);
}
 
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||

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[U-Boot] [PATCH v2 7/7] configs: sama5d3_xplained: move CONFIG_SYS_NO_FLASH to defconfig

[Wenyou Yang]

Move CONFIG_SYS_NO_FLASH to the configs/sama5d3x_xplained_*_defconfig
files.

Signed-off-by: Wenyou Yang 
---

Changes in v2:
 - rebase on the patch set:
[PATCH v3 0/8] board: sama5d4: convert boards to support DM/DT
http://lists.denx.de/pipermail/u-boot/2017-February/280506.html

 configs/sama5d3_xplained_mmc_defconfig   | 1 +
 configs/sama5d3_xplained_nandflash_defconfig | 1 +
 include/configs/sama5d3_xplained.h   | 3 ---
 3 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/configs/sama5d3_xplained_mmc_defconfig 
b/configs/sama5d3_xplained_mmc_defconfig
index a9890cc3d3..49089664de 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
 CONFIG_BOOTDELAY=3
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig 
b/configs/sama5d3_xplained_nandflash_defconfig
index 05798d666c..5f427c4bbd 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
 CONFIG_BOOTDELAY=3
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
diff --git a/include/configs/sama5d3_xplained.h 
b/include/configs/sama5d3_xplained.h
index 85997a6281..f98643a963 100644
--- a/include/configs/sama5d3_xplained.h
+++ b/include/configs/sama5d3_xplained.h
@@ -10,9 +10,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/* No NOR flash, this definition should put before common header */
-#define CONFIG_SYS_NO_FLASH
-
 #include "at91-sama5_common.h"
 
 /*
-- 
2.11.0

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[U-Boot] [PATCH v2 6/7] board: sama5d3_xplained: enable early debug UART

[Wenyou Yang]

Enable early debug UART to debug problems when an ICE or other
debug mechanism is not available.

Signed-off-by: Wenyou Yang 
---

Changes in v2: None

 board/atmel/sama5d3_xplained/sama5d3_xplained.c | 16 +++-
 configs/sama5d3_xplained_mmc_defconfig  |  6 ++
 configs/sama5d3_xplained_nandflash_defconfig|  6 ++
 3 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c 
b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
index c4d67a7748..692fec66a7 100644
--- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c
+++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -67,12 +68,25 @@ static void sama5d3_xplained_mci0_hw_init(void)
 }
 #endif
 
-int board_early_init_f(void)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
 {
at91_seriald_hw_init();
+}
+#endif
 
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+   debug_uart_init();
+#else
+   sama5d4_xplained_serial3_hw_init();
+   at91_seriald_hw_init();
+#endif
return 0;
 }
+#endif
 
 int board_init(void)
 {
diff --git a/configs/sama5d3_xplained_mmc_defconfig 
b/configs/sama5d3_xplained_mmc_defconfig
index 8940f1633b..a9890cc3d3 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -46,6 +46,12 @@ CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xee00
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig 
b/configs/sama5d3_xplained_nandflash_defconfig
index 6020513e17..05798d666c 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -44,6 +44,12 @@ CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xee00
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-- 
2.11.0

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[U-Boot] [PATCH v2 1/7] board: sama5d3xek: move config options to defconfig

[Wenyou Yang]

Enable CONFIG_CLK and CONFIG_PINCTRL to support at91 clock
driver and at91 pinctrl driver.

Move some config options to configs/sama5d3xek_*_defconfig.

Signed-off-by: Wenyou Yang 
---

Changes in v2: None

 board/atmel/sama5d3xek/sama5d3xek.c|  2 ++
 configs/sama5d3xek_mmc_defconfig   | 24 +++-
 configs/sama5d3xek_nandflash_defconfig | 25 -
 configs/sama5d3xek_spiflash_defconfig  | 24 +++-
 include/configs/sama5d3xek.h   | 20 
 5 files changed, 72 insertions(+), 23 deletions(-)

diff --git a/board/atmel/sama5d3xek/sama5d3xek.c 
b/board/atmel/sama5d3xek/sama5d3xek.c
index f0016964de..08f1be4fc1 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -331,6 +331,7 @@ int board_mmc_init(bd_t *bis)
 #ifdef CONFIG_ATMEL_SPI
 #include 
 
+#ifndef CONFIG_DM_SPI
 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 {
return bus == 0 && cs < 4;
@@ -367,6 +368,7 @@ void spi_cs_deactivate(struct spi_slave *slave)
break;
}
 }
+#endif
 #endif /* CONFIG_ATMEL_SPI */
 
 #ifdef CONFIG_BOARD_LATE_INIT
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index ea6d4b984b..d8556ab607 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -8,6 +8,7 @@ CONFIG_SPL_FAT_SUPPORT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
 CONFIG_BOOTDELAY=3
@@ -27,11 +28,32 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3xek_nandflash_defconfig 
b/configs/sama5d3xek_nandflash_defconfig
index f8504cc402..7cf875d92b 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
 CONFIG_BOOTDELAY=3
@@ -25,11 +26,33 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names 
interrupt-parent"
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3xek_spiflash_defconfig 
b/configs/sama5d3xek_spiflash_defconfig
index b5cabaf16a..7906fe7330 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH"
 CONFIG_BOOTDELAY=3
@@ -26,11 +27,32 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
 CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index 05e96f9fc4..7039d027b6 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -21,11 +21,6 @@
 
 #define 

[U-Boot] [PATCH v2 4/7] board: sama5d3_xplained: move config options to defconfig

[Wenyou Yang]

Enable CONFIG_CLK and CONFIG_PINCTRL to support at91 clock
driver and at91 pinctrl driver.

Move some config options to configs/sama5d3xek_*_defconfig.

Signed-off-by: Wenyou Yang 
---

Changes in v2: None

 configs/sama5d3_xplained_mmc_defconfig   | 21 -
 configs/sama5d3_xplained_nandflash_defconfig | 21 -
 include/configs/sama5d3_xplained.h   | 12 
 3 files changed, 40 insertions(+), 14 deletions(-)

diff --git a/configs/sama5d3_xplained_mmc_defconfig 
b/configs/sama5d3_xplained_mmc_defconfig
index 4f4e51b875..8940f1633b 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -8,6 +8,7 @@ CONFIG_SPL_FAT_SUPPORT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
 CONFIG_BOOTDELAY=3
@@ -29,6 +30,24 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig 
b/configs/sama5d3_xplained_nandflash_defconfig
index e83d047ef1..6020513e17 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
 CONFIG_BOOTDELAY=3
@@ -27,6 +28,24 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/sama5d3_xplained.h 
b/include/configs/sama5d3_xplained.h
index 2a8b8a1a6e..85997a6281 100644
--- a/include/configs/sama5d3_xplained.h
+++ b/include/configs/sama5d3_xplained.h
@@ -15,11 +15,6 @@
 
 #include "at91-sama5_common.h"
 
-/* serial console */
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE  ATMEL_BASE_DBGU
-#define CONFIG_USART_IDATMEL_ID_DBGU
-
 /*
  * This needs to be defined for the OHCI code to work but it is defined as
  * ATMEL_ID_UHPHS in the CPU specific header files.
@@ -78,13 +73,6 @@
 #define CONFIG_RGMII
 #define CONFIG_PHYLIB
 
-/* MMC */
-
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_ATMEL_MCI
-#define CONFIG_ATMEL_MCI_8BIT
-#endif
-
 /* USB */
 
 #ifdef CONFIG_CMD_USB
-- 
2.11.0

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[U-Boot] [PATCH v2 5/7] board: sama5d3_xplained: clean up code

[Wenyou Yang]

Since the introduction of the pinctrl and clk driver and
the dts file, remove unneeded hard coded related code from
the board file.

Signed-off-by: Wenyou Yang 
---

Changes in v2: None

 board/atmel/sama5d3_xplained/sama5d3_xplained.c | 19 ---
 1 file changed, 19 deletions(-)

diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c 
b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
index 2b9da91b2d..c4d67a7748 100644
--- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c
+++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
@@ -6,14 +6,12 @@
  */
 
 #include 
-#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -65,20 +63,12 @@ static void sama5d3_xplained_usb_hw_init(void)
 #ifdef CONFIG_GENERIC_ATMEL_MCI
 static void sama5d3_xplained_mci0_hw_init(void)
 {
-   at91_mci_hw_init();
-
at91_set_pio_output(AT91_PIO_PORTE, 2, 0);  /* MCI0 Power */
 }
 #endif
 
 int board_early_init_f(void)
 {
-   at91_periph_clk_enable(ATMEL_ID_PIOA);
-   at91_periph_clk_enable(ATMEL_ID_PIOB);
-   at91_periph_clk_enable(ATMEL_ID_PIOC);
-   at91_periph_clk_enable(ATMEL_ID_PIOD);
-   at91_periph_clk_enable(ATMEL_ID_PIOE);
-
at91_seriald_hw_init();
 
return 0;
@@ -122,15 +112,6 @@ int board_eth_init(bd_t *bis)
return 0;
 }
 
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-int board_mmc_init(bd_t *bis)
-{
-   atmel_mci_init((void *)ATMEL_BASE_MCI0);
-
-   return 0;
-}
-#endif
-
 /* SPL */
 #ifdef CONFIG_SPL_BUILD
 void spl_board_init(void)
-- 
2.11.0

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[U-Boot] [PATCH v2 2/7] board: sama5d3xek: clean up code

[Wenyou Yang]

Since the introduction of the pinctrl and clk driver and
the dts file, remove unneeded hard coded related code from
the board file.

Signed-off-by: Wenyou Yang 
---

Changes in v2: None

 board/atmel/sama5d3xek/sama5d3xek.c | 73 +
 1 file changed, 1 insertion(+), 72 deletions(-)

diff --git a/board/atmel/sama5d3xek/sama5d3xek.c 
b/board/atmel/sama5d3xek/sama5d3xek.c
index 08f1be4fc1..a3486437bd 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -16,7 +16,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -135,8 +134,6 @@ static void sama5d3xek_usb_hw_init(void)
 #ifdef CONFIG_GENERIC_ATMEL_MCI
 static void sama5d3xek_mci_hw_init(void)
 {
-   at91_mci_hw_init();
-
at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */
 }
 #endif
@@ -217,12 +214,6 @@ void lcd_show_board_info(void)
 
 int board_early_init_f(void)
 {
-   at91_periph_clk_enable(ATMEL_ID_PIOA);
-   at91_periph_clk_enable(ATMEL_ID_PIOB);
-   at91_periph_clk_enable(ATMEL_ID_PIOC);
-   at91_periph_clk_enable(ATMEL_ID_PIOD);
-   at91_periph_clk_enable(ATMEL_ID_PIOE);
-
at91_seriald_hw_init();
 
return 0;
@@ -248,9 +239,6 @@ int board_init(void)
 #ifdef CONFIG_GENERIC_ATMEL_MCI
sama5d3xek_mci_hw_init();
 #endif
-#ifdef CONFIG_ATMEL_SPI
-   at91_spi0_hw_init(1 << 0);
-#endif
 #ifdef CONFIG_MACB
if (has_emac())
at91_macb_hw_init();
@@ -316,61 +304,6 @@ int board_eth_init(bd_t *bis)
return rc;
 }
 
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-int board_mmc_init(bd_t *bis)
-{
-   int rc = 0;
-
-   rc = atmel_mci_init((void *)ATMEL_BASE_MCI0);
-
-   return rc;
-}
-#endif
-
-/* SPI chip select control */
-#ifdef CONFIG_ATMEL_SPI
-#include 
-
-#ifndef CONFIG_DM_SPI
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-   return bus == 0 && cs < 4;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-   switch (slave->cs) {
-   case 0:
-   at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
-   case 1:
-   at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
-   case 2:
-   at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
-   case 3:
-   at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
-   default:
-   break;
-   }
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-   switch (slave->cs) {
-   case 0:
-   at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
-   case 1:
-   at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
-   case 2:
-   at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
-   case 3:
-   at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
-   default:
-   break;
-   }
-}
-#endif
-#endif /* CONFIG_ATMEL_SPI */
-
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
@@ -394,12 +327,8 @@ int board_late_init(void)
 #ifdef CONFIG_SPL_BUILD
 void spl_board_init(void)
 {
-#ifdef CONFIG_SYS_USE_MMC
-   sama5d3xek_mci_hw_init();
-#elif CONFIG_SYS_USE_NANDFLASH
+#if CONFIG_SYS_USE_NANDFLASH
sama5d3xek_nand_hw_init();
-#elif CONFIG_SYS_USE_SERIALFLASH
-   at91_spi0_hw_init(1 << 0);
 #endif
 }
 
-- 
2.11.0

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[U-Boot] [PATCH v2 3/7] board: sama5d3xek: enable early debug UART

[Wenyou Yang]

Enable early debug UART to debug problems when an ICE or other
debug mechanism is not available.

Signed-off-by: Wenyou Yang 
---

Changes in v2: None

 board/atmel/sama5d3xek/sama5d3xek.c| 15 ++-
 configs/sama5d3xek_mmc_defconfig   |  6 ++
 configs/sama5d3xek_nandflash_defconfig |  6 ++
 configs/sama5d3xek_spiflash_defconfig  |  6 ++
 4 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/board/atmel/sama5d3xek/sama5d3xek.c 
b/board/atmel/sama5d3xek/sama5d3xek.c
index a3486437bd..6bd4a688e7 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -212,12 +213,24 @@ void lcd_show_board_info(void)
 #endif /* CONFIG_LCD_INFO */
 #endif /* CONFIG_LCD */
 
-int board_early_init_f(void)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
 {
at91_seriald_hw_init();
+}
+#endif
 
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+   debug_uart_init();
+#else
+   at91_seriald_hw_init();
+#endif
return 0;
 }
+#endif
 
 int board_init(void)
 {
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index d8556ab607..a8345520be 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -47,6 +47,12 @@ CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xee00
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
 CONFIG_DM_SPI=y
 CONFIG_ATMEL_SPI=y
diff --git a/configs/sama5d3xek_nandflash_defconfig 
b/configs/sama5d3xek_nandflash_defconfig
index 7cf875d92b..2e53ee947f 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -46,6 +46,12 @@ CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xee00
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
 CONFIG_DM_SPI=y
 CONFIG_ATMEL_SPI=y
diff --git a/configs/sama5d3xek_spiflash_defconfig 
b/configs/sama5d3xek_spiflash_defconfig
index 7906fe7330..6f26b4b5cc 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -46,6 +46,12 @@ CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xee00
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
 CONFIG_DM_SPI=y
 CONFIG_ATMEL_SPI=y
-- 
2.11.0

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[U-Boot] [PATCH v2 0/7] board: sama5d3: convert boards to support DM/DT

[Wenyou Yang]

The purpose of patch set is to convert the board to support Device
Tree and Driver Model.
It is based on the patch set:
[PATCH v5 0/2] pinctrl: at91: Add pinctrl driver
http://lists.denx.de/pipermail/u-boot/2017-February/280463.htm

Changes in v2:
 - rebase on the patch set:
[PATCH v3 0/8] board: sama5d4: convert boards to support DM/DT
http://lists.denx.de/pipermail/u-boot/2017-February/280506.html

Wenyou Yang (7):
  board: sama5d3xek: move config options to defconfig
  board: sama5d3xek: clean up code
  board: sama5d3xek: enable early debug UART
  board: sama5d3_xplained: move config options to defconfig
  board: sama5d3_xplained: clean up code
  board: sama5d3_xplained: enable early debug UART
  configs: sama5d3_xplained: move CONFIG_SYS_NO_FLASH to defconfig

 board/atmel/sama5d3_xplained/sama5d3_xplained.c | 35 +-
 board/atmel/sama5d3xek/sama5d3xek.c | 86 +
 configs/sama5d3_xplained_mmc_defconfig  | 28 +++-
 configs/sama5d3_xplained_nandflash_defconfig| 28 +++-
 configs/sama5d3xek_mmc_defconfig| 30 -
 configs/sama5d3xek_nandflash_defconfig  | 31 -
 configs/sama5d3xek_spiflash_defconfig   | 30 -
 include/configs/sama5d3_xplained.h  | 15 -
 include/configs/sama5d3xek.h| 20 --
 9 files changed, 172 insertions(+), 131 deletions(-)

-- 
2.11.0

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[U-Boot] [PATCH v3 8/8] configs: sama5d4: move CONFIG_SYS_NO_FLASH to *defconfig

[Wenyou Yang]

Move CONFIG_SYS_NO_FLASH to the configs/sama5d4*_defconfig file.

Signed-off-by: Wenyou Yang 
Reviewed-by: Andreas Bießmann 
---

Changes in v3:
 - add the Reviewed-by tags.
 - rebase on the patch:
[PATCH v2] ARM: dts: at91: add device tree files for at91sam9x5ek
http://lists.denx.de/pipermail/u-boot/2017-February/280504.html

Changes in v2: None

 configs/sama5d4_xplained_mmc_defconfig   | 1 +
 configs/sama5d4_xplained_nandflash_defconfig | 1 +
 configs/sama5d4_xplained_spiflash_defconfig  | 1 +
 configs/sama5d4ek_mmc_defconfig  | 1 +
 configs/sama5d4ek_nandflash_defconfig| 1 +
 configs/sama5d4ek_spiflash_defconfig | 1 +
 include/configs/sama5d4_xplained.h   | 3 ---
 include/configs/sama5d4ek.h  | 3 ---
 8 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/configs/sama5d4_xplained_mmc_defconfig 
b/configs/sama5d4_xplained_mmc_defconfig
index e7518e819b..dfd607070d 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
 CONFIG_BOOTDELAY=3
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/sama5d4_xplained_nandflash_defconfig 
b/configs/sama5d4_xplained_nandflash_defconfig
index 790d7d13d1..3ac745c01e 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
 CONFIG_BOOTDELAY=3
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig 
b/configs/sama5d4_xplained_spiflash_defconfig
index af6263fcaa..bd3353b5a0 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
 CONFIG_BOOTDELAY=3
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index 76b785569e..799fbbc689 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -14,6 +14,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/sama5d4ek_nandflash_defconfig 
b/configs/sama5d4ek_nandflash_defconfig
index 1bef32227a..cf2d71483f 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -12,6 +12,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/sama5d4ek_spiflash_defconfig 
b/configs/sama5d4ek_spiflash_defconfig
index bd7325efaf..67e2fab3d8 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -13,6 +13,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_NO_FLASH=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
diff --git a/include/configs/sama5d4_xplained.h 
b/include/configs/sama5d4_xplained.h
index e3abedb9a6..3fe67b3c86 100644
--- a/include/configs/sama5d4_xplained.h
+++ b/include/configs/sama5d4_xplained.h
@@ -10,9 +10,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/* No NOR flash, this definition should put before common header */
-#define CONFIG_SYS_NO_FLASH
-
 #include "at91-sama5_common.h"
 
 /* SDRAM */
diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h
index 0cd6f37167..e86276fd33 100644
--- a/include/configs/sama5d4ek.h
+++ b/include/configs/sama5d4ek.h
@@ -10,9 +10,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/* No NOR flash, this definition should put before common header */
-#define CONFIG_SYS_NO_FLASH
-
 #include "at91-sama5_common.h"
 
 /* SDRAM */
-- 
2.11.0

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[U-Boot] [PATCH v3 6/8] board: sama5d4ek: clean up code

[Wenyou Yang]

Since the introduction of the pinctrl and clk driver and
the dts file, remove unneeded hard coded related code from
the board file.

Signed-off-by: Wenyou Yang 
Reviewed-by: Andreas Bießmann 
---

Changes in v3: None
Changes in v2:
 - Restore the wrong removal USB related code.
 - Update the commit log.

 board/atmel/sama5d4ek/sama5d4ek.c | 88 +--
 1 file changed, 1 insertion(+), 87 deletions(-)

diff --git a/board/atmel/sama5d4ek/sama5d4ek.c 
b/board/atmel/sama5d4ek/sama5d4ek.c
index a0e4bb791e..c5479e7d7e 100644
--- a/board/atmel/sama5d4ek/sama5d4ek.c
+++ b/board/atmel/sama5d4ek/sama5d4ek.c
@@ -16,48 +16,14 @@
 #include 
 #include 
 #include 
-#include 
 #include 
-#include 
 #include 
 #include 
 #include 
-#include 
 #include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_ATMEL_SPI
-#ifndef CONFIG_DM_SPI
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-   return bus == 0 && cs == 0;
-}
-#endif
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-   at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-   at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
-}
-
-static void sama5d4ek_spi0_hw_init(void)
-{
-   at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0);   /* SPI0_MISO */
-   at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0);   /* SPI0_MOSI */
-   at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0);   /* SPI0_SPCK */
-
-   at91_set_pio_output(AT91_PIO_PORTC, 3, 1);  /* SPI0_CS0 */
-
-   /* Enable clock */
-   at91_periph_clk_enable(ATMEL_ID_SPI0);
-}
-#endif /* CONFIG_ATMEL_SPI */
-
 #ifdef CONFIG_NAND_ATMEL
 static void sama5d4ek_nand_hw_init(void)
 {
@@ -198,42 +164,6 @@ void lcd_show_board_info(void)
 
 #endif /* CONFIG_LCD */
 
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-void sama5d4ek_mci1_hw_init(void)
-{
-   at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1);  /* MCI1 CDA */
-   at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1);  /* MCI1 DA0 */
-   at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1);  /* MCI1 DA1 */
-   at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1);  /* MCI1 DA2 */
-   at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1);  /* MCI1 DA3 */
-   at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0);  /* MCI1 CLK */
-
-   /*
-* As the mci io internal pull down is too strong, so if the io needs
-* external pull up, the pull up resistor will be very small, if so
-* the power consumption will increase, so disable the interanl pull
-* down to save the power.
-*/
-   at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
-   at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
-   at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
-   at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
-   at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
-   at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
-
-   /* Enable clock */
-   at91_periph_clk_enable(ATMEL_ID_MCI1);
-}
-
-int board_mmc_init(bd_t *bis)
-{
-   /* Enable power for MCI1 interface */
-   at91_set_pio_output(AT91_PIO_PORTE, 15, 0);
-
-   return atmel_mci_init((void *)ATMEL_BASE_MCI1);
-}
-#endif /* CONFIG_GENERIC_ATMEL_MCI */
-
 #ifdef CONFIG_MACB
 void sama5d4ek_macb0_hw_init(void)
 {
@@ -264,12 +194,6 @@ static void sama5d4ek_serial3_hw_init(void)
 
 int board_early_init_f(void)
 {
-   at91_periph_clk_enable(ATMEL_ID_PIOA);
-   at91_periph_clk_enable(ATMEL_ID_PIOB);
-   at91_periph_clk_enable(ATMEL_ID_PIOC);
-   at91_periph_clk_enable(ATMEL_ID_PIOD);
-   at91_periph_clk_enable(ATMEL_ID_PIOE);
-
sama5d4ek_serial3_hw_init();
 
return 0;
@@ -280,15 +204,9 @@ int board_init(void)
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-#ifdef CONFIG_ATMEL_SPI
-   sama5d4ek_spi0_hw_init();
-#endif
 #ifdef CONFIG_NAND_ATMEL
sama5d4ek_nand_hw_init();
 #endif
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-   sama5d4ek_mci1_hw_init();
-#endif
 #ifdef CONFIG_MACB
sama5d4ek_macb0_hw_init();
 #endif
@@ -334,12 +252,8 @@ int board_eth_init(bd_t *bis)
 #ifdef CONFIG_SPL_BUILD
 void spl_board_init(void)
 {
-#ifdef CONFIG_SYS_USE_MMC
-   sama5d4ek_mci1_hw_init();
-#elif CONFIG_SYS_USE_NANDFLASH
+#if CONFIG_SYS_USE_NANDFLASH
sama5d4ek_nand_hw_init();
-#elif CONFIG_SYS_USE_SERIALFLASH
-   sama5d4ek_spi0_hw_init();
 #endif
 }
 
-- 
2.11.0

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[U-Boot] [PATCH v3 7/8] board: sama5d4ek: enable early debug UART

[Wenyou Yang]

Enable early debug UART to debug problems when an ICE or other
debug mechanism is not available.

Signed-off-by: Wenyou Yang 
Reviewed-by: Andreas Bießmann 
---

Changes in v3: None
Changes in v2: None

 board/atmel/sama5d4ek/sama5d4ek.c | 15 ++-
 configs/sama5d4ek_mmc_defconfig   |  6 ++
 configs/sama5d4ek_nandflash_defconfig |  6 ++
 configs/sama5d4ek_spiflash_defconfig  |  6 ++
 4 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/board/atmel/sama5d4ek/sama5d4ek.c 
b/board/atmel/sama5d4ek/sama5d4ek.c
index c5479e7d7e..2c2036c496 100644
--- a/board/atmel/sama5d4ek/sama5d4ek.c
+++ b/board/atmel/sama5d4ek/sama5d4ek.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -192,12 +193,24 @@ static void sama5d4ek_serial3_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_USART3);
 }
 
-int board_early_init_f(void)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
 {
sama5d4ek_serial3_hw_init();
+}
+#endif
 
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+   debug_uart_init();
+#else
+   sama5d4ek_serial3_hw_init();
+#endif
return 0;
 }
+#endif
 
 int board_init(void)
 {
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index fd49b58ab6..76b785569e 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -48,6 +48,12 @@ CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xfc00c000
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
 CONFIG_DM_SPI=y
 CONFIG_ATMEL_SPI=y
diff --git a/configs/sama5d4ek_nandflash_defconfig 
b/configs/sama5d4ek_nandflash_defconfig
index 34f5234e54..1bef32227a 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -46,6 +46,12 @@ CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xfc00c000
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
 CONFIG_DM_SPI=y
 CONFIG_ATMEL_SPI=y
diff --git a/configs/sama5d4ek_spiflash_defconfig 
b/configs/sama5d4ek_spiflash_defconfig
index c7f4655950..bd7325efaf 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -47,6 +47,12 @@ CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xfc00c000
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
 CONFIG_DM_SPI=y
 CONFIG_ATMEL_SPI=y
-- 
2.11.0

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[U-Boot] [PATCH v3 2/8] board: sama5d4_xplained: move config options to defconfig

[Wenyou Yang]

Enable CONFIG_CLK and CONFIG_PINCTRL to support at91 clock
driver and at91 pinctrl driver.

Move some config options to configs/sama5d4_xplained_*_defconfig
files.

Signed-off-by: Wenyou Yang 
Reviewed-by: Andreas Bießmann 
---

Changes in v3: None
Changes in v2:
 - Restore the wrong removal #define CONFIG_USB_ETHER.
 - Update the commit log.

 board/atmel/sama5d4_xplained/sama5d4_xplained.c |  2 ++
 configs/sama5d4_xplained_mmc_defconfig  | 24 +++-
 configs/sama5d4_xplained_nandflash_defconfig| 26 -
 configs/sama5d4_xplained_spiflash_defconfig | 24 +++-
 include/configs/sama5d4_xplained.h  | 30 -
 5 files changed, 73 insertions(+), 33 deletions(-)

diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c 
b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index 47f0bae8c1..6684276e05 100644
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -28,10 +28,12 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_ATMEL_SPI
+#ifndef CONFIG_DM_SPI
 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 {
return bus == 0 && cs == 0;
 }
+#endif
 
 void spi_cs_activate(struct spi_slave *slave)
 {
diff --git a/configs/sama5d4_xplained_mmc_defconfig 
b/configs/sama5d4_xplained_mmc_defconfig
index 5ff4688d4a..e25b26a520 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -8,6 +8,7 @@ CONFIG_SPL_FAT_SUPPORT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
 CONFIG_BOOTDELAY=3
@@ -26,10 +27,31 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d4_xplained_nandflash_defconfig 
b/configs/sama5d4_xplained_nandflash_defconfig
index 800a8b20f4..53dfdd6457 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
 CONFIG_BOOTDELAY=3
@@ -21,13 +22,36 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig 
b/configs/sama5d4_xplained_spiflash_defconfig
index e5d2f54458..17fd9a22b5 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
 CONFIG_BOOTDELAY=3
@@ -25,10 +26,31 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
-CONFIG_OF_LIBFDT=y
diff --git 

[U-Boot] [PATCH v3 5/8] board: sama5d4ek: move config options to defconfig

[Wenyou Yang]

Enable CONFIG_CLK and CONFIG_PINCTRL to support at91 clock
driver and at91 pinctrl driver.

Move some config options to configs/sama5d4ek_*_defconfig.

Signed-off-by: Wenyou Yang 
Reviewed-by: Andreas Bießmann 
---

Changes in v3: None
Changes in v2:
 - Restore wrong removal of #define CONFIG_USB_ETHER.
 - Update the commit log.

 board/atmel/sama5d4ek/sama5d4ek.c |  2 ++
 configs/sama5d4ek_mmc_defconfig   | 23 +++
 configs/sama5d4ek_nandflash_defconfig | 23 +++
 configs/sama5d4ek_spiflash_defconfig  | 23 +++
 include/configs/sama5d4ek.h   | 30 --
 5 files changed, 71 insertions(+), 30 deletions(-)

diff --git a/board/atmel/sama5d4ek/sama5d4ek.c 
b/board/atmel/sama5d4ek/sama5d4ek.c
index d1b5ff5797..a0e4bb791e 100644
--- a/board/atmel/sama5d4ek/sama5d4ek.c
+++ b/board/atmel/sama5d4ek/sama5d4ek.c
@@ -28,10 +28,12 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_ATMEL_SPI
+#ifndef CONFIG_DM_SPI
 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 {
return bus == 0 && cs == 0;
 }
+#endif
 
 void spi_cs_activate(struct spi_slave *slave)
 {
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index 48999704c7..fd49b58ab6 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -8,6 +8,7 @@ CONFIG_SPL_FAT_SUPPORT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
 CONFIG_BOOTDELAY=3
@@ -28,9 +29,31 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
diff --git a/configs/sama5d4ek_nandflash_defconfig 
b/configs/sama5d4ek_nandflash_defconfig
index 9ebe295af3..34f5234e54 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
 CONFIG_BOOTDELAY=3
@@ -26,9 +27,31 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
diff --git a/configs/sama5d4ek_spiflash_defconfig 
b/configs/sama5d4ek_spiflash_defconfig
index dff8995c4e..c7f4655950 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
 CONFIG_BOOTDELAY=3
@@ -27,9 +28,31 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_ATMEL_USBA=y
diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h
index 354e5104c5..0cd6f37167 100644
--- a/include/configs/sama5d4ek.h
+++ b/include/configs/sama5d4ek.h
@@ -15,11 +15,6 @@
 
 #include "at91-sama5_common.h"
 
-/* serial console */
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE  ATMEL_BASE_USART3
-#defineCONFIG_USART_ID 

[U-Boot] [PATCH v3 3/8] board: sama5d4_xplained: clean up code

[Wenyou Yang]

Since the introduction of the pinctrl and clk driver and
the dts file, remove unneeded hard coded related code from
the board file.

Signed-off-by: Wenyou Yang 
Reviewed-by: Andreas Bießmann 
---

Changes in v3: None
Changes in v2:
 - Restore the wrong removal of USB related code.
 - Update the commit log.

 board/atmel/sama5d4_xplained/sama5d4_xplained.c | 87 +
 1 file changed, 1 insertion(+), 86 deletions(-)

diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c 
b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index 6684276e05..2b51e4cf84 100644
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -16,48 +16,14 @@
 #include 
 #include 
 #include 
-#include 
 #include 
-#include 
 #include 
 #include 
 #include 
-#include 
 #include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_ATMEL_SPI
-#ifndef CONFIG_DM_SPI
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-   return bus == 0 && cs == 0;
-}
-#endif
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-   at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-   at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
-}
-
-static void sama5d4_xplained_spi0_hw_init(void)
-{
-   at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0);   /* SPI0_MISO */
-   at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0);   /* SPI0_MOSI */
-   at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0);   /* SPI0_SPCK */
-
-   at91_set_pio_output(AT91_PIO_PORTC, 3, 1);  /* SPI0_CS0 */
-
-   /* Enable clock */
-   at91_periph_clk_enable(ATMEL_ID_SPI0);
-}
-#endif /* CONFIG_ATMEL_SPI */
-
 #ifdef CONFIG_NAND_ATMEL
 static void sama5d4_xplained_nand_hw_init(void)
 {
@@ -202,41 +168,6 @@ void lcd_show_board_info(void)
 
 #endif /* CONFIG_LCD */
 
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-void sama5d4_xplained_mci1_hw_init(void)
-{
-   at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1);  /* MCI1 CDA */
-   at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1);  /* MCI1 DA0 */
-   at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1);  /* MCI1 DA1 */
-   at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1);  /* MCI1 DA2 */
-   at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1);  /* MCI1 DA3 */
-   at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0);  /* MCI1 CLK */
-
-   /*
-* As the mci io internal pull down is too strong, so if the io needs
-* external pull up, the pull up resistor will be very small, if so
-* the power consumption will increase, so disable the interanl pull
-* down to save the power.
-*/
-   at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
-   at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
-   at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
-   at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
-   at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
-   at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
-
-   /* Enable clock */
-   at91_periph_clk_enable(ATMEL_ID_MCI1);
-}
-
-int board_mmc_init(bd_t *bis)
-{
-   /* Enable the power supply */
-   at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
-
-   return atmel_mci_init((void *)ATMEL_BASE_MCI1);
-}
-#endif /* CONFIG_GENERIC_ATMEL_MCI */
 
 #ifdef CONFIG_MACB
 void sama5d4_xplained_macb0_hw_init(void)
@@ -268,12 +199,6 @@ static void sama5d4_xplained_serial3_hw_init(void)
 
 int board_early_init_f(void)
 {
-   at91_periph_clk_enable(ATMEL_ID_PIOA);
-   at91_periph_clk_enable(ATMEL_ID_PIOB);
-   at91_periph_clk_enable(ATMEL_ID_PIOC);
-   at91_periph_clk_enable(ATMEL_ID_PIOD);
-   at91_periph_clk_enable(ATMEL_ID_PIOE);
-
sama5d4_xplained_serial3_hw_init();
 
return 0;
@@ -284,15 +209,9 @@ int board_init(void)
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-#ifdef CONFIG_ATMEL_SPI
-   sama5d4_xplained_spi0_hw_init();
-#endif
 #ifdef CONFIG_NAND_ATMEL
sama5d4_xplained_nand_hw_init();
 #endif
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-   sama5d4_xplained_mci1_hw_init();
-#endif
 #ifdef CONFIG_MACB
sama5d4_xplained_macb0_hw_init();
 #endif
@@ -338,12 +257,8 @@ int board_eth_init(bd_t *bis)
 #ifdef CONFIG_SPL_BUILD
 void spl_board_init(void)
 {
-#ifdef CONFIG_SYS_USE_MMC
-   sama5d4_xplained_mci1_hw_init();
-#elif CONFIG_SYS_USE_NANDFLASH
+#if CONFIG_SYS_USE_NANDFLASH
sama5d4_xplained_nand_hw_init();
-#elif CONFIG_SYS_USE_SERIALFLASH
-   sama5d4_xplained_spi0_hw_init();
 #endif
 }
 
-- 
2.11.0

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[U-Boot] [PATCH v3 4/8] board: sama5d4_xplained: enable early debug UART

[Wenyou Yang]

Enable early debug UART to debug problems when an ICE or other
debug mechanism is not available.

Signed-off-by: Wenyou Yang 
Reviewed-by: Andreas Bießmann 
---

Changes in v3: None
Changes in v2: None

 board/atmel/sama5d4_xplained/sama5d4_xplained.c | 15 ++-
 configs/sama5d4_xplained_mmc_defconfig  |  6 ++
 configs/sama5d4_xplained_nandflash_defconfig|  6 ++
 configs/sama5d4_xplained_spiflash_defconfig |  6 ++
 4 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c 
b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index 2b51e4cf84..c46a7a450b 100644
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -197,12 +198,24 @@ static void sama5d4_xplained_serial3_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_USART3);
 }
 
-int board_early_init_f(void)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
 {
sama5d4_xplained_serial3_hw_init();
+}
+#endif
 
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+   debug_uart_init();
+#else
+   sama5d4_xplained_serial3_hw_init();
+#endif
return 0;
 }
+#endif
 
 int board_init(void)
 {
diff --git a/configs/sama5d4_xplained_mmc_defconfig 
b/configs/sama5d4_xplained_mmc_defconfig
index e25b26a520..e7518e819b 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -46,6 +46,12 @@ CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xfc00c000
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
 CONFIG_DM_SPI=y
 CONFIG_ATMEL_SPI=y
diff --git a/configs/sama5d4_xplained_nandflash_defconfig 
b/configs/sama5d4_xplained_nandflash_defconfig
index 53dfdd6457..790d7d13d1 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -45,6 +45,12 @@ CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xfc00c000
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
 CONFIG_DM_SPI=y
 CONFIG_ATMEL_SPI=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig 
b/configs/sama5d4_xplained_spiflash_defconfig
index 17fd9a22b5..af6263fcaa 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -45,6 +45,12 @@ CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AT91=y
 CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xfc00c000
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
 CONFIG_DM_SPI=y
 CONFIG_ATMEL_SPI=y
-- 
2.11.0

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