[U-Boot] [PATCH 04/33] mmc: rework high speed mode selection

[Ziyuan Xu]

Select timing parameter for the host since HS mode switch is completed.

Signed-off-by: Ziyuan Xu 
---

 drivers/mmc/mmc.c | 16 ++--
 include/mmc.h |  6 ++
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 1b3652a..0b30172 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -552,6 +552,19 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
 
 }
 
+static int mmc_select_hs(struct mmc *mmc)
+{
+   int ret;
+
+   ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS);
+
+   if (!ret)
+   mmc_set_timing(mmc, MMC_TIMING_MMC_HS);
+
+   return ret;
+}
+
 static u32 mmc_select_card_type(struct mmc *mmc, u8 *ext_csd)
 {
u8 card_type;
@@ -630,8 +643,7 @@ static int mmc_change_freq(struct mmc *mmc)
avail_type = mmc_select_card_type(mmc, ext_csd);
 
if (avail_type & EXT_CSD_CARD_TYPE_HS)
-   err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
-EXT_CSD_HS_TIMING, 1);
+   err = mmc_select_hs(mmc);
else
err = -EINVAL;
 
diff --git a/include/mmc.h b/include/mmc.h
index 68b6790..060c1f8 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -228,6 +228,12 @@
 #define EXT_CSD_DDR_BUS_WIDTH_45   /* Card is in 4 bit DDR mode */
 #define EXT_CSD_DDR_BUS_WIDTH_86   /* Card is in 8 bit DDR mode */
 
+#define EXT_CSD_TIMING_BC  0   /* Backwards compatility */
+#define EXT_CSD_TIMING_HS  1   /* High speed */
+#define EXT_CSD_TIMING_HS200   2   /* HS200 */
+#define EXT_CSD_TIMING_HS400   3   /* HS400 */
+#define EXT_CSD_DRV_STR_SHIFT  4   /* Driver Strength shift */
+
 #define EXT_CSD_BOOT_ACK_ENABLE(1 << 6)
 #define EXT_CSD_BOOT_PARTITION_ENABLE  (1 << 3)
 #define EXT_CSD_PARTITION_ACCESS_ENABLE(1 << 0)
-- 
2.7.4


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[U-Boot] [PATCH 03/33] mmc: xenon_sdhci: drop redundant timing definitions

[Ziyuan Xu]

Remove the redundant mmc timing definitions which have defined in mmc.h.

Signed-off-by: Ziyuan Xu 
---

 drivers/mmc/xenon_sdhci.c | 12 
 1 file changed, 12 deletions(-)

diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c
index 2a0d8b4..f0a33c1 100644
--- a/drivers/mmc/xenon_sdhci.c
+++ b/drivers/mmc/xenon_sdhci.c
@@ -94,18 +94,6 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Hyperion only have one slot 0 */
 #define XENON_MMC_SLOT_ID_HYPERION 0
 
-#define MMC_TIMING_LEGACY  0
-#define MMC_TIMING_MMC_HS  1
-#define MMC_TIMING_SD_HS   2
-#define MMC_TIMING_UHS_SDR12   3
-#define MMC_TIMING_UHS_SDR25   4
-#define MMC_TIMING_UHS_SDR50   5
-#define MMC_TIMING_UHS_SDR104  6
-#define MMC_TIMING_UHS_DDR50   7
-#define MMC_TIMING_MMC_DDR52   8
-#define MMC_TIMING_MMC_HS200   9
-#define MMC_TIMING_MMC_HS400   10
-
 #define XENON_MMC_MAX_CLK  4
 
 enum soc_pad_ctrl_type {
-- 
2.7.4


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[U-Boot] [PATCH 01/33] mmc: select the available type from host_caps and card_caps

[Ziyuan Xu]

The original implementation select HS timing by default, add available
type selection for higher speed mode compatibility, such as hs200,
hs400, hs400es.

By the way, we assume that card run at 1.8V or 1.2V I/O when its timing
is ddr52/hs200/hs400(es).

Signed-off-by: Ziyuan Xu 
---

 drivers/mmc/mmc.c | 59 ++-
 include/mmc.h | 16 +++
 2 files changed, 74 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 72fc177..f5b2280 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -546,10 +546,62 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 
value)
 
 }
 
+static u32 mmc_select_card_type(struct mmc *mmc, u8 *ext_csd)
+{
+   u8 card_type;
+   u32 host_caps, avail_type = 0;
+
+   card_type = ext_csd[EXT_CSD_CARD_TYPE];
+   host_caps = mmc->cfg->host_caps;
+
+   if ((host_caps & MMC_MODE_HS) &&
+   (card_type & EXT_CSD_CARD_TYPE_26))
+   avail_type |= EXT_CSD_CARD_TYPE_26;
+
+   if ((host_caps & MMC_MODE_HS) &&
+   (card_type & EXT_CSD_CARD_TYPE_52))
+   avail_type |= EXT_CSD_CARD_TYPE_52;
+
+   /*
+* For the moment, u-boot doesn't support signal voltage
+* switch, therefor we assume that host support ddr52
+* at 1.8v or 3.3v I/O(1.2v I/O not supported, hs200 and
+* hs400 are the same).
+*/
+   if ((host_caps & MMC_MODE_DDR_52MHz) &&
+   (card_type & EXT_CSD_CARD_TYPE_DDR_1_8V))
+   avail_type |= EXT_CSD_CARD_TYPE_DDR_1_8V;
+
+   if ((host_caps & MMC_MODE_HS200) &&
+   (card_type & EXT_CSD_CARD_TYPE_HS200_1_8V))
+   avail_type |= EXT_CSD_CARD_TYPE_HS200_1_8V;
+
+   /*
+* If host can support HS400, it means that host can also
+* support HS200.
+*/
+   if ((host_caps & MMC_MODE_HS400) &&
+   (host_caps & MMC_MODE_8BIT) &&
+   (card_type & EXT_CSD_CARD_TYPE_HS400_1_8V))
+   avail_type |= EXT_CSD_CARD_TYPE_HS200_1_8V |
+   EXT_CSD_CARD_TYPE_HS400_1_8V;
+
+   if ((host_caps & MMC_MODE_HS400ES) &&
+   (host_caps & MMC_MODE_8BIT) &&
+   ext_csd[EXT_CSD_STROBE_SUPPORT] &&
+   (avail_type & EXT_CSD_CARD_TYPE_HS400_1_8V))
+   avail_type |= EXT_CSD_CARD_TYPE_HS200_1_8V |
+   EXT_CSD_CARD_TYPE_HS400_1_8V |
+   EXT_CSD_CARD_TYPE_HS400ES;
+
+   return avail_type;
+}
+
 static int mmc_change_freq(struct mmc *mmc)
 {
ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
char cardtype;
+   u32 avail_type;
int err;
 
mmc->card_caps = 0;
@@ -569,8 +621,13 @@ static int mmc_change_freq(struct mmc *mmc)
return err;
 
cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
+   avail_type = mmc_select_card_type(mmc, ext_csd);
 
-   err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
+   if (avail_type & EXT_CSD_CARD_TYPE_HS)
+   err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+EXT_CSD_HS_TIMING, 1);
+   else
+   err = -EINVAL;
 
if (err)
return err;
diff --git a/include/mmc.h b/include/mmc.h
index fad12d6..0bae1a1 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -58,6 +58,9 @@
 #define MMC_MODE_8BIT  (1 << 3)
 #define MMC_MODE_SPI   (1 << 4)
 #define MMC_MODE_DDR_52MHz (1 << 5)
+#define MMC_MODE_HS200 (1 << 6)
+#define MMC_MODE_HS400 (1 << 7)
+#define MMC_MODE_HS400ES   (1 << 8)
 
 #define SD_DATA_4BIT   0x0004
 
@@ -182,6 +185,7 @@
 #define EXT_CSD_BOOT_BUS_WIDTH 177
 #define EXT_CSD_PART_CONF  179 /* R/W */
 #define EXT_CSD_BUS_WIDTH  183 /* R/W */
+#define EXT_CSD_STROBE_SUPPORT 184 /* RO */
 #define EXT_CSD_HS_TIMING  185 /* R/W */
 #define EXT_CSD_REV192 /* RO */
 #define EXT_CSD_CARD_TYPE  196 /* RO */
@@ -201,6 +205,18 @@
 
 #define EXT_CSD_CARD_TYPE_26   (1 << 0)/* Card can run at 26MHz */
 #define EXT_CSD_CARD_TYPE_52   (1 << 1)/* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_HS   (EXT_CSD_CARD_TYPE_26 | \
+EXT_CSD_CARD_TYPE_52)
+#define EXT_CSD_CARD_TYPE_HS200_1_8V   BIT(4)  /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_HS200_1_2V   BIT(5)  /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_HS200(EXT_CSD_CARD_TYPE_HS200_1_8V | 
\
+EXT_CSD_CARD_TYPE_HS200_1_2V)
+#define EXT_CSD_CARD_TYPE_HS400_1_8V   BIT(6)  /* Card can run at 200MHz DDR, 
1.8V */
+#define EXT_CSD_CARD_TYPE_HS400_1_2V   BIT(7)  /* Card can run at 200MHz DDR, 
1.2V */
+#define EXT_CSD_CARD_TYPE_HS400(EXT_CSD_CARD_TYPE_HS400_1_8V | 
\
+  

[U-Boot] [PATCH] ARM: dts: uniphier: sync DT with Linux

[Masahiro Yamada]

Fix the following DTC warnings:
Warning (simple_bus_reg): Node 
/soc/system-bus@58c0/support_card@1,1f0/ethernet@ simple-bus 
unit address format error, expected "0"
Warning (simple_bus_reg): Node 
/soc/system-bus@58c0/support_card@1,1f0/uart@000b simple-bus unit 
address format error, expected "b"
Warning (simple_bus_reg): Node /soc/smpctrl@5980 simple-bus unit address 
format error, expected "59801000"

Signed-off-by: Masahiro Yamada 
---

 arch/arm/dts/uniphier-ld11.dtsi |  2 +-
 arch/arm/dts/uniphier-ld20.dtsi |  2 +-
 arch/arm/dts/uniphier-ld4.dtsi  | 42 ++---
 arch/arm/dts/uniphier-pro4.dtsi | 42 ++---
 arch/arm/dts/uniphier-pro5.dtsi |  2 +-
 arch/arm/dts/uniphier-pxs2.dtsi |  2 +-
 arch/arm/dts/uniphier-pxs3.dtsi | 40 +--
 arch/arm/dts/uniphier-sld3.dtsi | 42 ++---
 arch/arm/dts/uniphier-sld8.dtsi | 42 ++---
 arch/arm/dts/uniphier-support-card.dtsi | 42 ++---
 10 files changed, 237 insertions(+), 21 deletions(-)

diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi
index 5294a90..af7a22f 100644
--- a/arch/arm/dts/uniphier-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ld11.dtsi
@@ -273,7 +273,7 @@
pinctrl-0 = <_system_bus>;
};
 
-   smpctrl@5980 {
+   smpctrl@59801000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi
index 2906471..dccb569 100644
--- a/arch/arm/dts/uniphier-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ld20.dtsi
@@ -342,7 +342,7 @@
pinctrl-0 = <_system_bus>;
};
 
-   smpctrl@5980 {
+   smpctrl@59801000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi
index 0d3d963..0fd4cbf 100644
--- a/arch/arm/dts/uniphier-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ld4.dtsi
@@ -4,7 +4,43 @@
  * Copyright (C) 2015-2016 Socionext Inc.
  *   Author: Masahiro Yamada 
  *
- * SPDX-License-Identifier:GPL-2.0+X11
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
  */
 
 / {
@@ -282,7 +318,7 @@
pinctrl-0 = <_system_bus>;
};
 
-   smpctrl@5980 {
+   smpctrl@59801000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
@@ -446,7 +482,7 @@
};
 
nand: nand@6800 {
-   compatible = "socionext,denali-nand-v5a";
+ 

[U-Boot] [GIT PULL] Please pull u-boot-mmc master

[Jaehoon Chung]

Dear Tom,

Could you pull these patches into u-boot/master?
If there are problems, let me knows.


The following changes since commit 22f3368e71321db1e0e15dfbf54b052367890ec7:

  Merge branch 'master' of git://git.denx.de/u-boot-mips (2017-05-13 16:45:35 
-0400)

are available in the git repository at:

  git://git.denx.de/u-boot-mmc.git master

for you to fetch changes up to 08c424fc0073cfad854ebc6164a24c99f31aa125:

  mmc: atmel_sdhci: Enable the quirk SDHCI_QUIRK_WAIT_SEND_CMD (2017-05-15 
14:00:07 +0900)


Jean-Jacques Hiblot (2):
  include: config: am335x: disable DM_MMC_OPS if DM_MMC is disabled
  drivers: omap_hsmmc: move to DM_MMC_OPS

Masahiro Yamada (5):
  mmc: sdhci-cadence: import updates from Linux 4.12
  sandbox_noblk_defconfig: disable CONFIG_GENERIC_MMC
  blanche_defconfig: enable CONFIG_MMC
  mmc: replace CONFIG_GENERIC_MMC with CONFIG_MMC
  mmc: descend into drivers/mmc only when CONFIG_MMC is enabled

Philipp Tomsich (2):
  env_mmc: configure environment offsets via device tree
  doc: document u-boot, mmc-env-offset and u-boot, mmc-env-offset-redund

Wenyou Yang (2):
  mmc: sdhci: Fix maximum clock for programmable clock mode
  mmc: atmel_sdhci: Enable the quirk SDHCI_QUIRK_WAIT_SEND_CMD

 Makefile   |  1 -
 arch/arm/Kconfig   |  2 +-
 board/BuR/common/common.c  |  2 +-
 board/bosch/shc/board.c|  2 +-
 board/compulab/cl-som-am57x/cl-som-am57x.c |  4 +-
 board/compulab/cm_t35/cm_t35.c |  4 +-
 board/compulab/cm_t3517/cm_t3517.c |  2 +-
 board/compulab/cm_t54/cm_t54.c |  2 +-
 board/corscience/tricorder/tricorder.c |  4 +-
 board/gumstix/duovero/duovero.c|  2 +-
 board/hisilicon/hikey/hikey.c  |  2 +-
 board/isee/igep00x0/igep00x0.c |  4 +-
 board/logicpd/am3517evm/am3517evm.c|  2 +-
 board/logicpd/omap3som/omap3logic.c|  4 +-
 board/logicpd/zoom1/zoom1.c|  2 +-
 board/overo/overo.c|  4 +-
 board/pandora/pandora.c|  2 +-
 board/quipos/cairo/cairo.c |  2 +-
 board/samsung/arndale/arndale.c|  2 +-
 board/samsung/common/board.c   |  2 +-
 board/samsung/common/misc.c|  4 +-
 board/samsung/goni/goni.c  |  2 +-
 board/samsung/smdkv310/smdkv310.c  |  2 +-
 board/sunxi/board.c|  2 +-
 board/technexion/tao3530/tao3530.c |  4 +-
 board/ti/am3517crane/am3517crane.c |  2 +-
 board/ti/am57xx/board.c|  2 +-
 board/ti/beagle/beagle.c   |  4 +-
 board/ti/dra7xx/evm.c  |  2 +-
 board/ti/evm/evm.c |  4 +-
 board/ti/ks2_evm/board_k2g.c   |  2 +-
 board/ti/omap5_uevm/evm.c  |  2 +-
 board/ti/panda/panda.c |  2 +-
 board/ti/sdp4430/sdp.c |  2 +-
 board/ti/ti814x/evm.c  |  2 +-
 board/timll/devkit8000/devkit8000.c|  4 +-
 common/board_r.c   |  4 +-
 common/env_mmc.c   | 31 --
 common/spl/Kconfig |  4 +-
 configs/blanche_defconfig  |  3 +-
 configs/sandbox_noblk_defconfig|  1 -
 doc/device-tree-bindings/config.txt| 12 ++
 drivers/Makefile   |  1 +
 drivers/mmc/Kconfig|  5 +--
 drivers/mmc/Makefile   | 28 ++---
 drivers/mmc/atmel_sdhci.c  |  4 +-
 drivers/mmc/davinci_mmc.c  |  2 +-
 drivers/mmc/omap_hsmmc.c   | 38 ++---
 drivers/mmc/sdhci-cadence.c| 67 +-
 drivers/mmc/sdhci.c| 18 
 include/configs/am335x_evm.h   |  2 +
 include/configs/am335x_shc.h   |  1 +
 include/configs/chiliboard.h   |  1 +
 53 files changed, 211 insertions(+), 104 deletions(-)

Best Regards,
Jaehoon Chung
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Re: [U-Boot] [PATCH v2] mmc: sdhci-cadence: import updates from Linux 4.12

[Jaehoon Chung]

On 05/09/2017 03:52 PM, Masahiro Yamada wrote:
> This driver is a counterpart of drivers/mmc/host/sdhci-cadence.c
> from Linux.  Some updates for v4.12-rc1 can be imported to U-Boot.
> 
>  - Fix value of SDHCI_CDNS_HRS04_RDATA_SHIFT
>  - Add polling for ACK bit to be sure that data are written to
>the PHY register
>  - Retrieve PHY values from DT properties instead of fixed data
> 
> The following is the list of upstream commits:
> 
>  - Linux commit 4e03f628b464e0580abadf5161eaa38c61d20943
>mmc: sdhci-cadence: fix bit shift of read data from PHY port
> 
>  - Linux commit a0f8243229ed071c8da0ea7cedc1b7bf1b1515da
>mmc: sdhci-cadence: Fix writing PHY delay
> 
>  - Linux commit a89c472d8b55c5afc4c79e6e3d1338730034eb01
>mmc: sdhci-cadence: Update PHY delay configuration
> 
> Signed-off-by: Masahiro Yamada 

Applied to u-boot-mmc. Thanks!

Best Regards,
Jaehoon Chung

> ---
> 
> Changes in v2:
>  - Add missing "commit" to git-log
> 
>  drivers/mmc/sdhci-cadence.c | 67 
> ++---
>  1 file changed, 57 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c
> index 2253bbc..dc86d10 100644
> --- a/drivers/mmc/sdhci-cadence.c
> +++ b/drivers/mmc/sdhci-cadence.c
> @@ -7,8 +7,10 @@
>  
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  
> @@ -17,7 +19,7 @@
>  #define   SDHCI_CDNS_HRS04_ACK   BIT(26)
>  #define   SDHCI_CDNS_HRS04_RDBIT(25)
>  #define   SDHCI_CDNS_HRS04_WRBIT(24)
> -#define   SDHCI_CDNS_HRS04_RDATA_SHIFT   12
> +#define   SDHCI_CDNS_HRS04_RDATA_SHIFT   16
>  #define   SDHCI_CDNS_HRS04_WDATA_SHIFT   8
>  #define   SDHCI_CDNS_HRS04_ADDR_SHIFT0
>  
> @@ -34,6 +36,9 @@
>  #define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY   0x06
>  #define SDHCI_CDNS_PHY_DLY_EMMC_SDR  0x07
>  #define SDHCI_CDNS_PHY_DLY_EMMC_DDR  0x08
> +#define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b
> +#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c
> +#define SDHCI_CDNS_PHY_DLY_STROBE0x0d
>  
>  struct sdhci_cdns_plat {
>   struct mmc_config cfg;
> @@ -41,11 +46,31 @@ struct sdhci_cdns_plat {
>   void __iomem *hrs_addr;
>  };
>  
> -static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat,
> -  u8 addr, u8 data)
> +struct sdhci_cdns_phy_cfg {
> + const char *property;
> + u8 addr;
> +};
> +
> +static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
> + { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
> + { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
> + { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
> + { "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
> + { "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
> + { "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
> + { "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
> + { "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
> + { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
> + { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
> + { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
> +};
> +
> +static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat,
> + u8 addr, u8 data)
>  {
>   void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04;
>   u32 tmp;
> + int ret;
>  
>   tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) |
> (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT);
> @@ -54,17 +79,36 @@ static void sdhci_cdns_write_phy_reg(struct 
> sdhci_cdns_plat *plat,
>   tmp |= SDHCI_CDNS_HRS04_WR;
>   writel(tmp, reg);
>  
> + ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 10);
> + if (ret)
> + return ret;
> +
>   tmp &= ~SDHCI_CDNS_HRS04_WR;
>   writel(tmp, reg);
> +
> + return 0;
>  }
>  
> -static void sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat)
> +static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat,
> + const void *fdt, int nodeoffset)
>  {
> - sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_SD_HS, 4);
> - sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_SD_DEFAULT, 4);
> - sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_LEGACY, 9);
> - sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_SDR, 2);
> - sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_DDR, 3);
> + const u32 *prop;
> + int ret, i;
> +
> + for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
> + prop = fdt_getprop(fdt, nodeoffset,
> +sdhci_cdns_phy_cfgs[i].property, NULL);
> + if 

Re: [U-Boot] [PATCH 2/2][v5] armv8: ls2080aqds: Add support for SD boot

[Santan Kumar]

> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Friday, May 12, 2017 9:31 PM
> To: Santan Kumar ; u-boot@lists.denx.de
> Cc: Priyanka Jain ; Abhimanyu Saini
> 
> Subject: Re: [PATCH 2/2][v5] armv8: ls2080aqds: Add support for SD boot
> 
> On 05/05/2017 03:10 AM, Santan Kumar wrote:
> > Signed-off-by: Santan Kumar 
> > Signed-off-by: Priyanka Jain 
> > Signed-off-by: Abhimanyu Saini 
> > ---
> > Changes in v5:
> >  1. Update MAINTAINERS file
> >  2. Updated the memory layout
> >
> >  arch/arm/cpu/armv8/fsl-layerscape/cpu.c|  6 +--
> >  .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c|  6 +--
> >  board/freescale/ls2080a/ls2080a.c  |  6 +--
> >  board/freescale/ls2080aqds/MAINTAINERS |  1 +
> >  board/freescale/ls2080aqds/README  | 13 +
> >  board/freescale/ls2080aqds/eth.c   |  8 +---
> >  board/freescale/ls2080aqds/ls2080aqds.c|  4 +-
> >  configs/ls2080aqds_sdcard_defconfig| 55
> ++
> >  include/configs/ls2080a_common.h   |  9 +++-
> >  include/configs/ls2080aqds.h   | 27 ++-
> >  10 files changed, 116 insertions(+), 19 deletions(-)  create mode
> > 100644 configs/ls2080aqds_sdcard_defconfig
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > index bb02960..e5da7a2 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > @@ -462,7 +462,7 @@ int cpu_eth_init(bd_t *bis)  {
> > int error = 0;
> >
> > -#ifdef CONFIG_FSL_MC_ENET
> > +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
> 
> You have many changes like this in this patch. Why don't you change the
> Kconfig
> 
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -96,7 +96,7 @@ config FSL_LSCH3
>   config FSL_MC_ENET
>  bool "Management Complex network"
>  depends on ARCH_LS2080A
> -   default y
> +   default y if !SPL_BUILD
>  select RESV_RAM
>  help
>Enable Management Complex (MC) network
> 
> Please try it.
> 
> York
[Santan Kumar] I have already tried it. SPL_BUILD flag was not enabled when we 
this code is executing. That's why I haven't added it in Kconfig.
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Re: [U-Boot] [PATCH v3 11/12] Drop CONFIG_I2CFAST

[Heiko Schocher]

Hello Simon,

Am 13.05.2017 um 05:09 schrieb Simon Glass:

This option is not used in U-Boot. Drop it.

Signed-off-by: Simon Glass 
---

Changes in v3: None
Changes in v2: None

  README   |  6 --
  common/board_r.c | 17 -
  scripts/config_whitelist.txt |  1 -
  3 files changed, 24 deletions(-)


Thanks!

Applied to u-boot-i2c.git master

u-boot-i2c master just testing on travis:
https://travis-ci.org/hsdenx/u-boot-i2c/builds/232288665

bye,
Heiko


diff --git a/README b/README
index 96ce6289ea..71d8de0ba8 100644
--- a/README
+++ b/README
@@ -2323,12 +2323,6 @@ The following options need to be configured:
custom i2c_init_board() routine in boards/xxx/board.c
is run early in the boot sequence.

-   CONFIG_I2CFAST (PPC405GP|PPC405EP only)
-
-   This option enables configuration of bi_iic_fast[] flags
-   in u-boot bd_info structure based on u-boot environment
-   variable "i2cfast". (see also i2cfast)
-
CONFIG_I2C_MULTI_BUS

This option allows the use of multiple I2C buses, each of which
diff --git a/common/board_r.c b/common/board_r.c
index d69a33c4a3..dba2102b18 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -485,24 +485,7 @@ static int initr_env(void)

/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
-#if defined(CONFIG_SYS_EXTBDINFO)
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
-#if defined(CONFIG_I2CFAST)
-   /*
-* set bi_iic_fast for linux taking environment variable
-* "i2cfast" into account
-*/
-   {
-   char *s = getenv("i2cfast");

-   if (s && ((*s == 'y') || (*s == 'Y'))) {
-   gd->bd->bi_iic_fast[0] = 1;
-   gd->bd->bi_iic_fast[1] = 1;
-   }
-   }
-#endif /* CONFIG_I2CFAST */
-#endif /* CONFIG_405GP, CONFIG_405EP */
-#endif /* CONFIG_SYS_EXTBDINFO */
return 0;
  }

diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 5cdca33f87..7cdfcd0a52 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -1319,7 +1319,6 @@ CONFIG_HW_ENV_SETTINGS
  CONFIG_HW_WATCHDOG
  CONFIG_HW_WATCHDOG_TIMEOUT_MS
  CONFIG_I2C
-CONFIG_I2CFAST
  CONFIG_I2C_CHIPADDRESS
  CONFIG_I2C_CMD_TREE
  CONFIG_I2C_ENV_EEPROM_BUS



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Re: [U-Boot] [PATCH v3 10/12] i2c: Drop CONFIG_SYS_I2C_BOARD_LATE_INIT

[Heiko Schocher]

Hello Simon,

Am 13.05.2017 um 05:09 schrieb Simon Glass:

This option is not used by any boards. Drop it.

Signed-off-by: Simon Glass 
---

Changes in v3: None
Changes in v2: None

  README   | 11 ---
  drivers/i2c/fsl_i2c.c|  9 -
  drivers/i2c/fti2c010.c   |  9 -
  include/i2c.h|  3 ---
  scripts/config_whitelist.txt |  1 -
  5 files changed, 33 deletions(-)


Thanks!

Applied to u-boot-i2c.git master

u-boot-i2c master just testing on travis:
https://travis-ci.org/hsdenx/u-boot-i2c/builds/232288665

bye,
Heiko


diff --git a/README b/README
index 9f9265dc6d..96ce6289ea 100644
--- a/README
+++ b/README
@@ -2323,17 +2323,6 @@ The following options need to be configured:
custom i2c_init_board() routine in boards/xxx/board.c
is run early in the boot sequence.

-   CONFIG_SYS_I2C_BOARD_LATE_INIT
-
-   An alternative to CONFIG_SYS_I2C_INIT_BOARD. If this option is
-   defined a custom i2c_board_late_init() routine in
-   boards/xxx/board.c is run AFTER the operations in i2c_init()
-   is completed. This callpoint can be used to unreset i2c bus
-   using CPU i2c controller register accesses for CPUs whose i2c
-   controller provide such a method. It is called at the end of
-   i2c_init() to allow i2c_init operations to setup the i2c bus
-   controller on the CPU (e.g. setting bus speed & slave address).
-
CONFIG_I2CFAST (PPC405GP|PPC405EP only)

This option enables configuration of bi_iic_fast[] flags
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index a1406baa87..ff3dc25927 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -284,15 +284,6 @@ static void __i2c_init(const struct fsl_i2c_base *base, 
int speed, int

break;
}
-
-#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
-   /* Call board specific i2c bus reset routine AFTER the bus has been
-* initialized. Use either this callpoint or i2c_init_board;
-* which is called before i2c_init operations.
-* For details about this problem see doc/I2C_Edge_Conditions.
-   */
-   i2c_board_late_init();
-#endif
  }

  static int
diff --git a/drivers/i2c/fti2c010.c b/drivers/i2c/fti2c010.c
index b35d0d2d9c..4da959fa53 100644
--- a/drivers/i2c/fti2c010.c
+++ b/drivers/i2c/fti2c010.c
@@ -146,15 +146,6 @@ static void fti2c010_init(struct i2c_adapter *adap, int 
speed, int slaveaddr)
set_i2c_bus_speed(chip, speed);

/* slave init, don't care */
-
-#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
-   /* Call board specific i2c bus reset routine AFTER the bus has been
-* initialized. Use either this callpoint or i2c_init_board;
-* which is called before fti2c010_init operations.
-* For details about this problem see doc/I2C_Edge_Conditions.
-   */
-   i2c_board_late_init();
-#endif
  }

  /*
diff --git a/include/i2c.h b/include/i2c.h
index cd7f61e1c1..a88cc7cddf 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -706,9 +706,6 @@ void i2c_early_init_f(void);
  #endif
  void i2c_init(int speed, int slaveaddr);
  void i2c_init_board(void);
-#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
-void i2c_board_late_init(void);
-#endif

  #ifdef CONFIG_SYS_I2C
  /*
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index da37e49c83..5cdca33f87 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -4222,7 +4222,6 @@ CONFIG_SYS_I2C_BASE2
  CONFIG_SYS_I2C_BASE3
  CONFIG_SYS_I2C_BASE4
  CONFIG_SYS_I2C_BASE5
-CONFIG_SYS_I2C_BOARD_LATE_INIT
  CONFIG_SYS_I2C_BOOT_EEPROM_ADDR
  CONFIG_SYS_I2C_BUSES
  CONFIG_SYS_I2C_BUS_MAX



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Re: [U-Boot] [PATCH v3 06/12] i2c: mxc_i2c: Drop use of CONFIG_I2C_HARD

[Heiko Schocher]

Hello Simon,

Am 13.05.2017 um 05:09 schrieb Simon Glass:

Drop use of this long-deprecated option.

Signed-off-by: Simon Glass 
---

Changes in v3: None
Changes in v2: None

  drivers/i2c/mxc_i2c.c | 4 
  1 file changed, 4 deletions(-)


Thanks!

Applied to u-boot-i2c.git master

u-boot-i2c master just testing on travis:
https://travis-ci.org/hsdenx/u-boot-i2c/builds/232288665

bye,
Heiko


diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 13ec0e63b1..b68e82770b 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -69,10 +69,6 @@ DECLARE_GLOBAL_DATA_PTR;
  #define I2SR_IIF_CLEAR(0 << 1)
  #endif

-#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
-#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
-#endif
-
  #ifdef I2C_QUIRK_REG
  static u16 i2c_clk_div[60][2] = {
{ 20,   0x00 }, { 22,   0x01 }, { 24,   0x02 }, { 26,   0x03 },



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Re: [U-Boot] [PATCH v3 09/12] i2c: README: Drop CONFIG_SYS_I2C_INIT_MPC5XXX

[Heiko Schocher]

Hello Simon,

Am 13.05.2017 um 05:09 schrieb Simon Glass:

This option is not used in U-Boot. Drop it.

Signed-off-by: Simon Glass 
---

Changes in v3: None
Changes in v2: None

  README | 2 --
  1 file changed, 2 deletions(-)


Thanks!

Applied to u-boot-i2c.git master

u-boot-i2c master just testing on travis:
https://travis-ci.org/hsdenx/u-boot-i2c/builds/232288665

bye,
Heiko


diff --git a/README b/README
index 11fa84ccc4..9f9265dc6d 100644
--- a/README
+++ b/README
@@ -2228,8 +2228,6 @@ The following options need to be configured:
eg, MPC823e User's Manual p.16-473). So, set
CONFIG_SYS_I2C_SLAVE to 0.

-   CONFIG_SYS_I2C_INIT_MPC5XXX
-
When a board is reset during an i2c bus transfer
chips might think that the current transfer is still
in progress.  Reset the slave devices by sending start



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Re: [U-Boot] [PATCH v3 07/12] i2c: omap: Modify code to work without CONFIG_I2C_HARD

[Heiko Schocher]

Hello Simon,

Am 13.05.2017 um 05:09 schrieb Simon Glass:

Drop use of this long-deprecated option.

Signed-off-by: Simon Glass 
Suggested-by: Lokesh Vutla 
---

Changes in v3: None
Changes in v2:
- Add new patch to adjust omap boards to not need CONFIG_I2C_HARD

  board/ti/am335x/board.c | 3 ++-
  board/ti/am43xx/board.c | 3 ++-
  2 files changed, 4 insertions(+), 2 deletions(-)


Thanks!

Applied to u-boot-i2c.git master

u-boot-i2c master just testing on travis:
https://travis-ci.org/hsdenx/u-boot-i2c/builds/232288665

bye,
Heiko


diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 3e81521399..517965c0f0 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -72,7 +72,8 @@ void do_board_detect(void)
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);

-   if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
+   if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+CONFIG_EEPROM_CHIP_ADDRESS))
printf("ti_i2c_eeprom_init failed\n");
  }
  #endif
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index f633e2f85d..f44103d4d6 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -42,7 +42,8 @@ static struct ctrl_dev *cdev = (struct ctrl_dev 
*)CTRL_DEVICE_BASE;
  #ifdef CONFIG_TI_I2C_BOARD_DETECT
  void do_board_detect(void)
  {
-   if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
+   if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+CONFIG_EEPROM_CHIP_ADDRESS))
printf("ti_i2c_eeprom_init failed\n");
  }
  #endif



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Re: [U-Boot] [PATCH v3 12/12] Drop use of CONFIG_I2C_SOFT

[Heiko Schocher]

Hello Simon,

Am 13.05.2017 um 05:10 schrieb Simon Glass:

This option is not used in U-Boot. Drop it.

Signed-off-by: Simon Glass 
---

Changes in v3:
- Rebase to master

Changes in v2:
- Rebase to master

  README | 32 +---
  1 file changed, 1 insertion(+), 31 deletions(-)


Thanks!

Applied to u-boot-i2c.git master

u-boot-i2c master just testing on travis:
https://travis-ci.org/hsdenx/u-boot-i2c/builds/232288665

bye,
Heiko


diff --git a/README b/README
index 71d8de0ba8..9525199551 100644
--- a/README
+++ b/README
@@ -2204,37 +2204,7 @@ The following options need to be configured:

If you do not have i2c muxes on your board, omit this define.

-under removal:
-
-- Legacy I2C Support:  CONFIG_SOFT_I2C
-
-   NOTE: It is intended to move drivers to CONFIG_SYS_I2C which
-   provides the following compelling advantages:
-
-   - more than one i2c adapter is usable
-   - approved multibus support
-   - better i2c mux support
-
-   ** CONFIG_SOFT_I2C is now being removed **
-
-   With CONFIG_SOFT_I2C you will need to define
-   CONFIG_SYS_I2C_SPEED to be the frequency (in Hz) at which you
-   wish your i2c bus to run and CONFIG_SYS_I2C_SLAVE to be the
-   address of this node (ie the CPU's i2c node address).
-
-   Now, the u-boot i2c code for the mpc8xx
-   (arch/powerpc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node
-   and so its address should therefore be cleared to 0 (See,
-   eg, MPC823e User's Manual p.16-473). So, set
-   CONFIG_SYS_I2C_SLAVE to 0.
-
-   When a board is reset during an i2c bus transfer
-   chips might think that the current transfer is still
-   in progress.  Reset the slave devices by sending start
-   commands until the slave device responds.
-
-   That's all that's required for CONFIG_HARD_I2C.
-
+- Legacy I2C Support:
If you use the software i2c interface (CONFIG_SYS_I2C_SOFT)
then the following macros need to be defined (examples are
from include/configs/lwmon.h):



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Re: [U-Boot] [PATCH v3 05/12] i2c: keymile: Drop use of CONFIG_I2C_HARD

[Heiko Schocher]

Hello simon,

Am 13.05.2017 um 05:09 schrieb Simon Glass:

Drop use of this long-deprecated option.

Signed-off-by: Simon Glass 
---

Changes in v3: None
Changes in v2: None

  board/keymile/km82xx/km82xx.c | 5 -
  board/keymile/km_arm/km_arm.c | 4 
  2 files changed, 9 deletions(-)


Thanks!

Applied to u-boot-i2c.git master

u-boot-i2c master just testing on travis:
https://travis-ci.org/hsdenx/u-boot-i2c/builds/232288665

bye,
Heiko


diff --git a/board/keymile/km82xx/km82xx.c b/board/keymile/km82xx/km82xx.c
index 51b4571d40..f5a98b33e7 100644
--- a/board/keymile/km82xx/km82xx.c
+++ b/board/keymile/km82xx/km82xx.c
@@ -153,13 +153,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
{ 0, 0,   0,   0,   0,   0 }, /* PD18*/
{ 0, 0,   0,   0,   0,   0 }, /* PD17*/
{ 0, 0,   0,   0,   0,   0 }, /* PD16*/
-#if defined(CONFIG_HARD_I2C)
-   { 1, 1,   1,   0,   1,   0 }, /* PD15 I2C SDA*/
-   { 1, 1,   1,   0,   1,   0 }, /* PD14 I2C SCL*/
-#else
{ 1, 0,   0,   0,   1,   1 }, /* PD15*/
{ 1, 0,   0,   1,   1,   1 }, /* PD14*/
-#endif
{ 0, 0,   0,   0,   0,   0 }, /* PD13*/
{ 0, 0,   0,   0,   0,   0 }, /* PD12*/
{ 0, 0,   0,   0,   0,   0 }, /* PD11*/
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 079509c979..85785ffc02 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -75,10 +75,6 @@ static const u32 kwmpp_config[] = {
  #if defined(CONFIG_SYS_I2C_SOFT)
MPP8_GPIO,  /* SDA */
MPP9_GPIO,  /* SCL */
-#endif
-#if defined(CONFIG_HARD_I2C)
-   MPP8_TW_SDA,
-   MPP9_TW_SCK,
  #endif
MPP10_UART0_TXD,
MPP11_UART0_RXD,



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Re: [U-Boot] [PATCH v3 08/12] i2c: Finish dropping use of CONFIG_I2C_HARD

[Heiko Schocher]

Hello Simon,

Am 13.05.2017 um 05:09 schrieb Simon Glass:

Drop use of this long-deprecated option.

Signed-off-by: Simon Glass 
---

Changes in v3:
- Update commit message so that it is unique in the series
- Fix up #ifdef in cmd/eeprom.c
- Drop changes to include/config headers

Changes in v2:
- Drop changes to omap board.c files

  README   | 16 
  cmd/eeprom.c |  2 --
  common/board_f.c |  4 ++--
  common/stdio.c   |  5 +
  scripts/config_whitelist.txt |  1 -
  5 files changed, 11 insertions(+), 17 deletions(-)


Thanks!

Applied to u-boot-i2c.git master

u-boot-i2c master just testing on travis:
https://travis-ci.org/hsdenx/u-boot-i2c/builds/232288665

bye,
Heiko


diff --git a/README b/README
index 86f0814f79..11fa84ccc4 100644
--- a/README
+++ b/README
@@ -2204,7 +2204,9 @@ The following options need to be configured:

If you do not have i2c muxes on your board, omit this define.

-- Legacy I2C Support:  CONFIG_HARD_I2C
+under removal:
+
+- Legacy I2C Support:  CONFIG_SOFT_I2C

NOTE: It is intended to move drivers to CONFIG_SYS_I2C which
provides the following compelling advantages:
@@ -2213,14 +2215,12 @@ The following options need to be configured:
- approved multibus support
- better i2c mux support

-   ** CONFIG_HARD_I2C is now being removed **
-
-under removal:
+   ** CONFIG_SOFT_I2C is now being removed **

-   In both cases you will need to define CONFIG_SYS_I2C_SPEED
-   to be the frequency (in Hz) at which you wish your i2c bus
-   to run and CONFIG_SYS_I2C_SLAVE to be the address of this node 
(ie
-   the CPU's i2c node address).
+   With CONFIG_SOFT_I2C you will need to define
+   CONFIG_SYS_I2C_SPEED to be the frequency (in Hz) at which you
+   wish your i2c bus to run and CONFIG_SYS_I2C_SLAVE to be the
+   address of this node (ie the CPU's i2c node address).

Now, the u-boot i2c code for the mpc8xx
(arch/powerpc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node
diff --git a/cmd/eeprom.c b/cmd/eeprom.c
index 0a0e4a2c1c..e43566bc56 100644
--- a/cmd/eeprom.c
+++ b/cmd/eeprom.c
@@ -73,11 +73,9 @@ void eeprom_init(int bus)
  #endif

/* I2C EEPROM */
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
  #if defined(CONFIG_SYS_I2C)
if (bus >= 0)
i2c_set_bus_num(bus);
-#endif
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  #endif
  }
diff --git a/common/board_f.c b/common/board_f.c
index d9431ee79a..eed3e7be2a 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -184,7 +184,7 @@ __weak int dram_init_banksize(void)
return 0;
  }

-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
+#if defined(CONFIG_SYS_I2C)
  static int init_func_i2c(void)
  {
puts("I2C:   ");
@@ -765,7 +765,7 @@ static const init_fnc_t init_sequence_f[] = {
misc_init_f,
  #endif
INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
+#if defined(CONFIG_SYS_I2C)
init_func_i2c,
  #endif
  #if defined(CONFIG_HARD_SPI)
diff --git a/common/stdio.c b/common/stdio.c
index 4d30017530..ee4f0bda9e 100644
--- a/common/stdio.c
+++ b/common/stdio.c
@@ -21,7 +21,7 @@
  #include 
  #endif

-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
+#if defined(CONFIG_SYS_I2C)
  #include 
  #endif

@@ -346,9 +346,6 @@ int stdio_add_devices(void)
  #ifdef CONFIG_SYS_I2C
i2c_init_all();
  #else
-#if defined(CONFIG_HARD_I2C)
-   i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
  #endif
  #ifdef CONFIG_DM_VIDEO
/*
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 7646bb6842..da37e49c83 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -1134,7 +1134,6 @@ CONFIG_G_DNL_UMS_VENDOR_NUM
  CONFIG_H264_FREQ
  CONFIG_H8300
  CONFIG_HALEAKALA
-CONFIG_HARD_I2C
  CONFIG_HARD_SPI
  CONFIG_HASH_VERIFY
  CONFIG_HAS_DATAFLASH



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Re: [U-Boot] [PATCH v3 03/12] i2c: cm5200: Drop use of CONFIG_I2C_HARD

[Heiko Schocher]

Hello Simon,

Am 13.05.2017 um 05:09 schrieb Simon Glass:

Drop use of this long-deprecated option.

Signed-off-by: Simon Glass 
---

Changes in v3: None
Changes in v2: None

  board/cm5200/cm5200.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)


Thanks!

Applied to u-boot-i2c.git master

u-boot-i2c master just testing on travis:
https://travis-ci.org/hsdenx/u-boot-i2c/builds/232288665

bye,
Heiko


diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c
index 2f55191caf..0c647bbd3d 100644
--- a/board/cm5200/cm5200.c
+++ b/board/cm5200/cm5200.c
@@ -214,7 +214,7 @@ static void compose_module_name(hw_id_t hw_id, char *buf)
strcat(buf, tmp);
  }

-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
+#if defined(CONFIG_SYS_I2C_SOFT)
  /*
   * Compose string with hostname.
   * buf is assumed to have enough space, and be null-terminated.
@@ -295,7 +295,7 @@ int board_early_init_r(void)
  #ifdef CONFIG_MISC_INIT_R
  int misc_init_r(void)
  {
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
+#if defined(CONFIG_SYS_I2C_SOFT)
uchar buf[6];
char str[18];
char hostname[MODULE_NAME_MAXLEN];
@@ -323,7 +323,7 @@ int misc_init_r(void)
compose_hostname(hw_id, hostname);
setenv("hostname", hostname);

-#endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) */
+#endif /* defined(CONFIG_SYS_I2C_SOFT) */
if (!getenv("ethaddr"))
printf(LOG_PREFIX "MAC address not set, networking is not "
"operational\n");



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Re: [U-Boot] [PATCH v3 04/12] i2c: pdm360ng: Drop use of CONFIG_I2C_HARD

[Heiko Schocher]

Hello Simon,

Am 13.05.2017 um 05:09 schrieb Simon Glass:

Drop use of this long-deprecated option.

Signed-off-by: Simon Glass 
---

Changes in v3: None
Changes in v2: None

  board/pdm360ng/pdm360ng.c | 30 --
  1 file changed, 30 deletions(-)


Thanks!

Applied to u-boot-i2c.git master

u-boot-i2c master just testing on travis:
https://travis-ci.org/hsdenx/u-boot-i2c/builds/232288665

bye,
Heiko


diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c
index 9db31d3312..371bcd9e6b 100644
--- a/board/pdm360ng/pdm360ng.c
+++ b/board/pdm360ng/pdm360ng.c
@@ -169,36 +169,6 @@ int misc_init_r(void)
clrsetbits_be32(>gpio.gpdat, 0x0100, 0x0004);
  #endif

-#if defined(CONFIG_HARD_I2C)
-   if (!getenv("ethaddr")) {
-   uchar buf[6];
-   uchar ifm_oui[3] = { 0, 2, 1, };
-   int ret;
-
-   /* I2C-0 for on-board eeprom */
-   i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS_NUM);
-
-   /* Read ethaddr from EEPROM */
-   ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR,
-  CONFIG_SYS_I2C_EEPROM_MAC_OFFSET, 1, buf, 6);
-   if (ret != 0) {
-   printf("Error: Unable to read MAC from I2C"
-   " EEPROM at address %02X:%02X\n",
-   CONFIG_SYS_I2C_EEPROM_ADDR,
-   CONFIG_SYS_I2C_EEPROM_MAC_OFFSET);
-   return 1;
-   }
-
-   /* Owned by IFM ? */
-   if (memcmp(buf, ifm_oui, sizeof(ifm_oui))) {
-   printf("Illegal MAC address in EEPROM: %pM\n", buf);
-   return 1;
-   }
-
-   eth_setenv_enetaddr("ethaddr", buf);
-   }
-#endif /* defined(CONFIG_HARD_I2C) */
-
return 0;
  }




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Re: [U-Boot] [PATCH v3 02/12] i2c: powerpc: Remove use of CONFIG_HARD_I2C

[Heiko Schocher]

Hello Simon,

Am 13.05.2017 um 05:09 schrieb Simon Glass:

Drop use of this long-deprecated option for powerpc.

Signed-off-by: Simon Glass 
---

Changes in v3: None
Changes in v2: None

  arch/powerpc/cpu/mpc512x/Makefile   |   1 -
  arch/powerpc/cpu/mpc512x/i2c.c  | 386 ---
  arch/powerpc/cpu/mpc5xxx/Makefile   |   1 -
  arch/powerpc/cpu/mpc5xxx/i2c.c  | 456 --
  arch/powerpc/cpu/mpc8260/Makefile   |   2 +-
  arch/powerpc/cpu/mpc8260/commproc.c |   4 -
  arch/powerpc/cpu/mpc8260/i2c.c  | 741 
  arch/powerpc/cpu/mpc8xx/Makefile|   1 -
  arch/powerpc/cpu/mpc8xx/i2c.c   | 672 
  board/freescale/m52277evb/README|   1 -
  board/freescale/m53017evb/README|   1 -
  board/freescale/m5373evb/README |   1 -
  board/freescale/m54455evb/README|   1 -
  board/freescale/m547xevb/README |   1 -
  14 files changed, 1 insertion(+), 2268 deletions(-)
  delete mode 100644 arch/powerpc/cpu/mpc512x/i2c.c
  delete mode 100644 arch/powerpc/cpu/mpc5xxx/i2c.c
  delete mode 100644 arch/powerpc/cpu/mpc8260/i2c.c
  delete mode 100644 arch/powerpc/cpu/mpc8xx/i2c.c


Thanks!

Applied to u-boot-i2c.git master

u-boot-i2c master just testing on travis:
https://travis-ci.org/hsdenx/u-boot-i2c/builds/232288665

bye,
Heiko


diff --git a/arch/powerpc/cpu/mpc512x/Makefile 
b/arch/powerpc/cpu/mpc512x/Makefile
index 98991c688b..933deebdae 100644
--- a/arch/powerpc/cpu/mpc512x/Makefile
+++ b/arch/powerpc/cpu/mpc512x/Makefile
@@ -9,7 +9,6 @@ obj-y   := cpu.o
  obj-y += traps.o
  obj-y += cpu_init.o
  obj-y += fixed_sdram.o
-obj-y += i2c.o
  obj-y += interrupts.o
  obj-y += iopin.o
  obj-y += serial.o
diff --git a/arch/powerpc/cpu/mpc512x/i2c.c b/arch/powerpc/cpu/mpc512x/i2c.c
deleted file mode 100644
index 15d519a116..00
--- a/arch/powerpc/cpu/mpc512x/i2c.c
+++ /dev/null
@@ -1,386 +0,0 @@
-/*
- * (C) Copyright 2003 - 2009
- * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
- *
- * SPDX-License-Identifier:GPL-2.0+
- *
- * Based on the MPC5xxx code.
- */
-
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_HARD_I2C
-
-#include 
-
-/* by default set I2C bus 0 active */
-static unsigned int bus_num __attribute__ ((section (".data"))) = 0;
-
-#define I2C_TIMEOUT100
-#define I2C_RETRIES3
-
-struct mpc512x_i2c_tap {
-   int scl2tap;
-   int tap2tap;
-};
-
-static int  mpc_reg_in(volatile u32 *reg);
-static void mpc_reg_out(volatile u32 *reg, int val, int mask);
-static int  wait_for_bb(void);
-static int  wait_for_pin(int *status);
-static int  do_address(uchar chip, char rdwr_flag);
-static int  send_bytes(uchar chip, char *buf, int len);
-static int  receive_bytes(uchar chip, char *buf, int len);
-static int  mpc_get_fdr(int);
-
-static int mpc_reg_in (volatile u32 *reg)
-{
-   int ret = in_be32(reg) >> 24;
-
-   return ret;
-}
-
-static void mpc_reg_out (volatile u32 *reg, int val, int mask)
-{
-   if (!mask) {
-   out_be32(reg, val << 24);
-   } else {
-   clrsetbits_be32(reg, mask << 24, (val & mask) << 24);
-   }
-}
-
-static int wait_for_bb (void)
-{
-   volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-   volatile i2c512x_dev_t *regs = >i2c.dev[bus_num];
-   int timeout = I2C_TIMEOUT;
-   int status;
-
-   status = mpc_reg_in (>msr);
-
-   while (timeout-- && (status & I2C_BB)) {
-   mpc_reg_out (>mcr, I2C_STA, I2C_STA);
-   (void)mpc_reg_in(>mdr);
-   mpc_reg_out (>mcr, 0, I2C_STA);
-   mpc_reg_out (>mcr, 0, 0);
-   mpc_reg_out (>mcr, I2C_EN, 0);
-
-   udelay (1000);
-   status = mpc_reg_in (>msr);
-   }
-
-   return (status & I2C_BB);
-}
-
-static int wait_for_pin (int *status)
-{
-   volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-   volatile i2c512x_dev_t *regs = >i2c.dev[bus_num];
-   int timeout = I2C_TIMEOUT;
-
-   *status = mpc_reg_in (>msr);
-
-   while (timeout-- && !(*status & I2C_IF)) {
-   udelay (1000);
-   *status = mpc_reg_in (>msr);
-   }
-
-   if (!(*status & I2C_IF)) {
-   return -1;
-   }
-
-   mpc_reg_out (>msr, 0, I2C_IF);
-
-   return 0;
-}
-
-static int do_address (uchar chip, char rdwr_flag)
-{
-   volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-   volatile i2c512x_dev_t *regs = >i2c.dev[bus_num];
-   int status;
-
-   chip <<= 1;
-
-   if (rdwr_flag) {
-   chip |= 1;
-   }
-
-   mpc_reg_out (>mcr, I2C_TX, I2C_TX);
-   mpc_reg_out (>mdr, chip, 0);
-
-   if (wait_for_pin ()) {
-   return -2;
-   }
-
-   if (status & I2C_RXAK) {
-   return -3;
-   }
-
-   return 0;
-}
-
-static int send_bytes (uchar chip, char *buf, int len)
-{
-   volatile immap_t *im = (immap_t *) 

Re: [U-Boot] [PATCH v3 01/12] i2c: Drop use of CONFIG_I2C_HARD

[Heiko Schocher]

Hello Simon,

Am 13.05.2017 um 05:09 schrieb Simon Glass:

This option is pretty old. It predates CONFIG_SYS_I2C which is itself
deprecated in favour of driver model. Disable it for all boards.

Also drop I2C options which depend on this.

Signed-off-by: Simon Glass 
---


Thanks!

Applied to u-boot-i2c.git master

u-boot-2ic master just testing on travis:
https://travis-ci.org/hsdenx/u-boot-i2c/builds/232288665

bye,
Heiko


Changes in v3: None
Changes in v2: None

  README   |  17 +--
  arch/arm/include/asm/arch-armada100/config.h |  12 --
  board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c   |  12 +-
  board/cm5200/cm5200.c|  32 ++---
  board/cm5200/cmd_cm5200.c|  32 +
  board/davedenx/aria/aria.c   |   3 -
  board/esd/mecp5123/mecp5123.c|  12 +-
  board/freescale/mpc5121ads/mpc5121ads.c  |  21 
  board/ifm/ac14xx/ac14xx.c|  53 +---
  board/renesas/r0p7734/r0p7734.c  |  12 +-
  board/tqc/tqm5200/tqm5200.c  |  18 +--
  configs/MiniFAP_defconfig|   2 -
  configs/O2D300_defconfig |   1 -
  configs/O2DNT2_RAMBOOT_defconfig |   1 -
  configs/O2DNT2_defconfig |   1 -
  configs/O2D_defconfig|   1 -
  configs/O2I_defconfig|   1 -
  configs/O2MNT_O2M110_defconfig   |   1 -
  configs/O2MNT_O2M112_defconfig   |   1 -
  configs/O2MNT_O2M113_defconfig   |   1 -
  configs/O2MNT_defconfig  |   1 -
  configs/O3DNT_defconfig  |   1 -
  configs/TQM5200S_HIGHBOOT_defconfig  |   2 -
  configs/TQM5200S_defconfig   |   2 -
  configs/TQM5200_B_HIGHBOOT_defconfig |   2 -
  configs/TQM5200_B_defconfig  |   2 -
  configs/TQM5200_STK100_defconfig |   2 -
  configs/TQM5200_defconfig|   2 -
  configs/a4m072_defconfig |   1 -
  configs/ac14xx_defconfig |   1 -
  configs/ap_sh4a_4a_defconfig |   1 -
  configs/apx4devkit_defconfig |   2 -
  configs/aria_defconfig   |   1 -
  configs/aspenite_defconfig   |   1 -
  configs/cam5200_defconfig|   2 -
  configs/cam5200_niosflash_defconfig  |   2 -
  configs/charon_defconfig |   1 -
  configs/cm5200_defconfig |   1 -
  configs/digsy_mtc_RAMBOOT_defconfig  |   2 -
  configs/digsy_mtc_defconfig  |   2 -
  configs/digsy_mtc_rev5_RAMBOOT_defconfig |   2 -
  configs/digsy_mtc_rev5_defconfig |   2 -
  configs/fo300_defconfig  |   2 -
  configs/gplugd_defconfig |   1 -
  configs/ipek01_defconfig |   2 -
  configs/m28evk_defconfig |   1 -
  configs/mecp5123_defconfig   |   2 -
  configs/motionpro_defconfig  |   2 -
  configs/mpc5121ads_defconfig |   2 -
  configs/mpc5121ads_rev2_defconfig|   2 -
  configs/pcm030_LOWBOOT_defconfig |   2 -
  configs/pcm030_defconfig |   2 -
  configs/pdm360ng_defconfig   |   2 -
  configs/r0p7734_defconfig|   1 -
  configs/v38b_defconfig   |   2 -
  include/common.h |  10 ++
  include/configs/M54418TWR.h  |   1 -
  include/configs/TQM5200.h|  64 +-
  include/configs/a4m072.h |  20 ---
  include/configs/ac14xx.h |  18 ---
  include/configs/ap_sh4a_4a.h |  14 ---
  include/configs/apx4devkit.h |   6 -
  include/configs/aria.h   |  21 
  include/configs/axs10x.h |   2 +-
  include/configs/cm5200.h |  12 +-
  include/configs/digsy_mtc.h  |  31 -
  include/configs/ids8313.h|   1 -
  include/configs/ipek01.h |  23 
  include/configs/jupiter.h|  19 ---
  include/configs/m28evk.h |   6 -
  include/configs/manroland/mpc5200-common.h   | 176 +++
  include/configs/mecp5123.h   |  18 +--
  include/configs/motionpro.h  |  22 
  include/configs/mpc5121ads.h |  18 ---
  include/configs/mxs.h|  10 --
  include/configs/o2dnt-common.h   |  22 
  include/configs/pcm030.h |  31 +
  include/configs/pdm360ng.h   |  30 -
  include/configs/r0p7734.h|  14 ---
  include/configs/s32v234evb.h |  10 --
  

[U-Boot] [USB]USB2.0 device timeout issue.

[Terry Zhou]

+ Nadav Haklai.

Best Regards,
Terry

From: Terry Zhou
Sent: 2017年5月11日 9:02
To: 'u-boot@lists.denx.de' ; 'ma...@denx.de' 

Cc: 'Stefan Roese' ; 'Simon Glass' ; 
'ma...@denx.de' 
Subject: [U-boot][USB]]USB2.0 device timeout issue.

+ Marek Vasut

Best Regards,
Terry

From: Terry Zhou
Sent: 2017年5月10日 15:10
To: u-boot@lists.denx.de
Cc: Wilson Ding >; 'Stefan 
Roese' >; 'Simon Glass' 
>
Subject: USB2.0 device timeout issue.

Hi all,
This is Terry from Marvell BSP team in ShangHai China.
We got one issue in USB like below:


1)  When reading large files(larger than 32M ) from USB2.0 u-disk, two of 
the disks got the timeout error like below:
Marvell>> fatload usb 0:1 0x100 got.mkv 0x200
reading got.mkv
EHCI timed out on TD - token=0x1e008d80
EHCI timed out on TD - token=0x1e008d80
EHCI timed out on TD - token=0x1e008d80
Error reading cluster
** Unable to read file got.mkv **

2)  I did some research on this issue and found that this issue disappear 
if we set “USB_MAX_XFER_BLK” to a smaller value.
/common/usb_storage.c
@@ -145,7 +145,7 @@ struct us_data {
  * limited to 65535 blocks.
  */
#elif defined(CONFIG_USB_EHCI)
-#define USB_MAX_XFER_BLK  65535
+#define USB_MAX_XFER_BLK  8000


3)  We also did some test in linux, it works in linux, we found that linux 
set the max_sectors to 240, and even we set them to a larger value,

The maximum value is 512, which is safe compares to the 8000 in Uboot.

Reference link for linux: http://www.linux-usb.org/FAQ.html#i5


4)  I found in Uboot forum, other guys met the same problem with us, see 
the link below:

https://lists.denx.de/pipermail/u-boot/2016-February/246405.html

and there is also some patches to find the optimal value of USB_MAX_XFER_BLK

https://www.mail-archive.com/u-boot@lists.denx.de/msg215952.html
But these patches have not been pushed to the mainline code.

Could you please share your ideas, why we didn’t merge the patches and how 
should we fix this issue?
Thanks.

Best Regards,
Terry
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Re: [U-Boot] [PATCH 02/17] omap24xx_i2c.c: Drop references to CONFIG_OMAP243X

[Heiko Schocher]

Hello Tom,

Am 13.05.2017 um 04:33 schrieb Tom Rini:

We have nothing defining CONFIG_OMAP243X since we dropped the omap243x
platforms, drop these tests.

Signed-off-by: Tom Rini 
---
  drivers/i2c/omap24xx_i2c.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)


as you have delegated this patch to your Patchwork ToDo list:

Acked-by: Heiko Schocher 

bye,
Heiko


diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index a23737ab7813..4b8397a890d6 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -122,7 +122,7 @@ static int wait_for_bb(struct i2c *i2c_base, int waitdelay)
u16 stat;

writew(0x, _base->stat); /* clear current interrupts...*/
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+#if defined(CONFIG_OMAP34XX)
while ((stat = readw(_base->stat) & I2C_STAT_BB) && timeout--) {
  #else
/* Read RAW status */
@@ -153,7 +153,7 @@ static u16 wait_for_event(struct i2c *i2c_base, int 
waitdelay)

do {
udelay(waitdelay);
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+#if defined(CONFIG_OMAP34XX)
status = readw(_base->stat);
  #else
/* Read RAW status */
@@ -338,7 +338,7 @@ retry:
/* own address */
writew(slaveadd, _base->oa);

-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+#if defined(CONFIG_OMAP34XX)
/*
 * Have to enable interrupts for OMAP2/3, these IPs don't have
 * an 'irqstatus_raw' register and we shall have to poll 'stat'



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Re: [U-Boot] [PATCH 18/22] mmc: add HS200 support in MMC core

[Simon Glass]

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:
> Add HS200 to the list of supported modes and introduce tuning in the MMC
> startup process.
>
> Signed-off-by: Kishon Vijay Abraham I 
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/mmc.c | 22 --
>  include/mmc.h | 17 +
>  2 files changed, 37 insertions(+), 2 deletions(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 05/22] mmc: introduces mmc modes.

[Simon Glass]

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:

Subject: drop the period at the end

Also I think 'mmc: Introduce MMC modes' is better (imperative tense)

> no functionnal changes.
> In order to add the support for the high speed SD and MMC modes, it is
> useful to track this information.
>
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/mmc.c | 53 ++---
>  include/mmc.h | 34 --
>  2 files changed, 74 insertions(+), 13 deletions(-)
>

Reviewed-by: Simon Glass 

Also see below

> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
> index 344d760..2e1cb0d 100644
> --- a/drivers/mmc/mmc.c
> +++ b/drivers/mmc/mmc.c
> @@ -149,6 +149,36 @@ void mmc_trace_state(struct mmc *mmc, struct mmc_cmd 
> *cmd)
>  }
>  #endif
>
> +const char *mmc_mode_name(enum bus_mode mode)
> +{
> +   static const char *const names[] = {
> + [MMC_LEGACY]  = "MMC legacy",
> + [SD_LEGACY]   = "SD Legacy",
> + [MMC_HS]  = "MMC High Speed (26MHz)",
> + [SD_HS]   = "SD High Speed (50MHz)",
> + [UHS_SDR12]   = "UHS SDR12 (25MHz)",
> + [UHS_SDR25]   = "UHS SDR25 (50MHz)",
> + [UHS_SDR50]   = "UHS SDR50 (100MHz)",
> + [UHS_SDR104]  = "UHS SDR104 (208MHz)",
> + [UHS_DDR50]   = "UHS DDR50 (50MHz)",
> + [MMC_HS_52]   = "MMC High Speed (52MHz)",
> + [MMC_DDR_52]  = "MMC DDR52 (52MHz)",
> + [MMC_HS_200]  = "HS200 (200MHz)",

Can we hide this behind a Kconfig so boards can turn it off to reduce
code size in SPL?

> +   };
> +
> +   if (mode >= MMC_MODES_END)
> +   return "Unknown mode";
> +   else
> +   return names[mode];
> +}
> +static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
> +{
> +   mmc->selected_mode = mode;
> +   debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
> + mmc->tran_speed / 100);
> +   return 0;
> +}
> +
>  #ifndef CONFIG_DM_MMC_OPS
>  int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
>  {
> @@ -1138,10 +1168,13 @@ static int sd_select_bus_freq_width(struct mmc *mmc)
> if (err)
> return err;
>
> -   if (mmc->card_caps & MMC_MODE_HS)
> +   if (mmc->card_caps & MMC_MODE_HS) {
> +   mmc_select_mode(mmc, SD_HS);
> mmc->tran_speed = 5000;
> -   else
> +   } else {
> +   mmc_select_mode(mmc, SD_LEGACY);
> mmc->tran_speed = 2500;
> +   }
>
> return 0;
>  }
> @@ -1255,11 +1288,15 @@ static int mmc_select_bus_freq_width(struct mmc *mmc)
> if (err)
> return err;
>
> -   if (mmc->card_caps & MMC_MODE_HS) {
> -   if (mmc->card_caps & MMC_MODE_HS_52MHz)
> -   mmc->tran_speed = 5200;
> +   if (mmc->card_caps & MMC_MODE_HS_52MHz) {
> +   if (mmc->ddr_mode)
> +   mmc_select_mode(mmc, MMC_DDR_52);
> else
> -   mmc->tran_speed = 2600;
> +   mmc_select_mode(mmc, MMC_HS_52);
> +   mmc->tran_speed = 5200;
> +   } else if (mmc->card_caps & MMC_MODE_HS) {
> +   mmc_select_mode(mmc, MMC_HS);
> +   mmc->tran_speed = 2600;
> }
>
> return err;
> @@ -1529,7 +1566,9 @@ static int mmc_startup(struct mmc *mmc)
> freq = fbase[(cmd.response[0] & 0x7)];
> mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
>
> -   mmc->tran_speed = freq * mult;
> +   mmc->legacy_speed = freq * mult;
> +   mmc->tran_speed = mmc->legacy_speed;
> +   mmc_select_mode(mmc, MMC_LEGACY);
>
> mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
> mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
> diff --git a/include/mmc.h b/include/mmc.h
> index 9af6b52..60a43b0 100644
> --- a/include/mmc.h
> +++ b/include/mmc.h
> @@ -52,12 +52,15 @@
>  #define MMC_VERSION_5_0MAKE_MMC_VERSION(5, 0, 0)
>  #define MMC_VERSION_5_1MAKE_MMC_VERSION(5, 1, 0)
>
> -#define MMC_MODE_HS(1 << 0)
> -#define MMC_MODE_HS_52MHz  (1 << 1)
> -#define MMC_MODE_4BIT  (1 << 2)
> -#define MMC_MODE_8BIT  (1 << 3)
> -#define MMC_MODE_SPI   (1 << 4)
> -#define MMC_MODE_DDR_52MHz (1 << 5)
> +#define MMC_CAP(mode)  (1 << mode)
> +#define MMC_MODE_HS(MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
> +#define MMC_MODE_HS_52MHz  MMC_CAP(MMC_HS_52)
> +#define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
> +
> +#define MMC_MODE_8BIT  (1 << 30)
> +#define MMC_MODE_4BIT  (1 << 29)
> +#define MMC_MODE_SPI   (1 << 27)
> +
>
>  #define SD_DATA_4BIT   0x0004
>
> @@ -402,6 

Re: [U-Boot] [PATCH 10/22] mmc: refactor MMC startup to make it easier to support new modes

[Simon Glass]

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:
> The MMC startup process currently handles 4 modes. To make it easier to
> add support for more modes, let's make the process more generic and use a
> list of the modes to try.
> The major functional change is that when a mode fails we try the next one.
> Not all modes are tried, only those supported by the card and the host.
>
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/mmc.c | 238 
> +-
>  include/mmc.h |  15 +++-
>  2 files changed, 157 insertions(+), 96 deletions(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 14/22] mmc: add power cyle support in mmc core

[Simon Glass]

Hi,

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:
> mmc/sd specification requires vdd to be disabled for 1 ms
> and then enabled again during power cycle. Add a
> function in mmc core to perform power cycle and set
> the io signal to it's initial state.
>
> Signed-off-by: Kishon Vijay Abraham I 
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/mmc.c | 50 +-
>  1 file changed, 41 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
> index d40a22b..032260b 100644
> --- a/drivers/mmc/mmc.c
> +++ b/drivers/mmc/mmc.c
> @@ -30,6 +30,7 @@ static const unsigned int sd_au_size[] = {
> SZ_16M / 512,   (SZ_16M + SZ_8M) / 512, SZ_32M / 512,   SZ_64M / 512,
>  };
>  static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
> +static void mmc_power_cycle(struct mmc *mmc);
>
>  #if CONFIG_IS_ENABLED(MMC_TINY)
>  static struct mmc mmc_static;
> @@ -1915,6 +1916,45 @@ static int mmc_power_init(struct mmc *mmc)
> return 0;
>  }
>
> +static void mmc_set_initial_state(struct mmc *mmc)

Function comment

> +{
> +   int err;
> +
> +   /* First try to set 3.3V. If it fails set to 1.8V */
> +   err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
> +   if (err != 0)
> +   err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
> +   if (err != 0)
> +   printf("failed to set signal voltage\n");
> +
> +   mmc_set_bus_width(mmc, 1);
> +   mmc_set_clock(mmc, 1);
> +   mmc_select_mode(mmc, MMC_LEGACY);
> +}
> +
> +static void mmc_power_up(struct mmc *mmc)
> +{
> +   mmc_set_initial_state(mmc);
> +   mmc_set_vdd(mmc, true);
> +   udelay(1);

Eek. Please add a comment as to why

> +}
> +
> +static void mmc_power_off(struct mmc *mmc)
> +{
> +   mmc_set_vdd(mmc, false);
> +}
> +
> +static void mmc_power_cycle(struct mmc *mmc)
> +{
> +   mmc_power_off(mmc);
> +   /*
> +* SD spec recommends at least 1ms of delay. Let's wait for 2ms
> +* to be on the safer side.
> +*/
> +   udelay(2000);
> +   mmc_power_up(mmc);
> +}
> +
>  int mmc_start_init(struct mmc *mmc)
>  {
> bool no_card;
> @@ -1952,16 +1992,8 @@ int mmc_start_init(struct mmc *mmc)
> return err;
>  #endif
> mmc->ddr_mode = 0;
> -   mmc_set_vdd(mmc, true);
> -   /* First try to set 3.3V. If it fails set to 1.8V */
> -   err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
> -   if (err != 0)
> -   err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
> -   if (err != 0)
> -   printf("failed to set signal voltage\n");

Return error? Also please add some mmc: to your message.

>
> -   mmc_set_bus_width(mmc, 1);
> -   mmc_set_clock(mmc, 1);
> +   mmc_power_cycle(mmc);
>
> /* Reset the Card */
> err = mmc_go_idle(mmc);
> --
> 1.9.1
>

Regards,
Simon
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Re: [U-Boot] [PATCH 15/22] mmc: add a new mmc parameter to disable mmc clock

[Simon Glass]

Hi,

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:
> mmc clock has to be disabled in certain cases like during
> the voltage switch sequence. Modify mmc_set_clock function
> to take disable as an argument that signifies if the
> clock has to be enabled or disabled.
>
> Signed-off-by: Kishon Vijay Abraham I 
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/fsl_esdhc.c |  2 +-
>  drivers/mmc/mmc.c   | 11 ++-
>  include/mmc.h   |  3 ++-
>  3 files changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> index f3c6358..b631392 100644
> --- a/drivers/mmc/fsl_esdhc.c
> +++ b/drivers/mmc/fsl_esdhc.c
> @@ -658,7 +658,7 @@ static int esdhc_init(struct mmc *mmc)
>  #endif
>
> /* Set the initial clock speed */
> -   mmc_set_clock(mmc, 40);
> +   mmc_set_clock(mmc, 40, false);
>
> /* Disable the BRR and BWR bits in IRQSTAT */
> esdhc_clrbits32(>irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
> index 032260b..70b7d19 100644
> --- a/drivers/mmc/mmc.c
> +++ b/drivers/mmc/mmc.c
> @@ -1216,7 +1216,7 @@ static int mmc_set_ios(struct mmc *mmc)
>  }
>  #endif
>
> -int mmc_set_clock(struct mmc *mmc, uint clock)
> +int mmc_set_clock(struct mmc *mmc, uint clock, u8 disable)
>  {
> if (clock > mmc->cfg->f_max)
> clock = mmc->cfg->f_max;
> @@ -1225,6 +1225,7 @@ int mmc_set_clock(struct mmc *mmc, uint clock)
> clock = mmc->cfg->f_min;
>
> mmc->clock = clock;
> +   mmc->clk_disable = disable;
>
> return mmc_set_ios(mmc);
>  }
> @@ -1316,7 +1317,7 @@ static int sd_select_mode_and_width(struct mmc *mmc)
>
> /* configure the bus mode (host) */
> mmc_select_mode(mmc, mwt->mode);
> -   mmc_set_clock(mmc, mmc->tran_speed);
> +   mmc_set_clock(mmc, mmc->tran_speed, false);
>
> err = sd_read_ssr(mmc);
> if (!err)
> @@ -1327,7 +1328,7 @@ static int sd_select_mode_and_width(struct mmc *mmc)
>  error:
> /* revert to a safer bus speed */
> mmc_select_mode(mmc, SD_LEGACY);
> -   mmc_set_clock(mmc, mmc->tran_speed);
> +   mmc_set_clock(mmc, mmc->tran_speed, false);
> }
> }
> }
> @@ -1465,7 +1466,7 @@ static int mmc_select_mode_and_width(struct mmc *mmc)
>
> /* configure the bus mode (host) */
> mmc_select_mode(mmc, mwt->mode);
> -   mmc_set_clock(mmc, mmc->tran_speed);
> +   mmc_set_clock(mmc, mmc->tran_speed, false);
>
> /* do a transfer to check the configuration */
> err = mmc_read_and_compare_ext_csd(mmc);
> @@ -1928,7 +1929,7 @@ static void mmc_set_initial_state(struct mmc *mmc)
> printf("failed to set signal voltage\n");
>
> mmc_set_bus_width(mmc, 1);
> -   mmc_set_clock(mmc, 1);
> +   mmc_set_clock(mmc, 1, false);
> mmc_select_mode(mmc, MMC_LEGACY);
>  }
>
> diff --git a/include/mmc.h b/include/mmc.h
> index 43d37a4..097a685 100644
> --- a/include/mmc.h
> +++ b/include/mmc.h
> @@ -466,6 +466,7 @@ struct mmc {
> void *priv;
> uint has_init;
> int high_capacity;
> +   u8 clk_disable;

bool? Also add comment.

> uint bus_width;
> uint clock;
> uint signal_voltage;
> @@ -557,7 +558,7 @@ int mmc_unbind(struct udevice *dev);
>  int mmc_initialize(bd_t *bis);
>  int mmc_init(struct mmc *mmc);
>  int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
> -int mmc_set_clock(struct mmc *mmc, uint clock);
> +int mmc_set_clock(struct mmc *mmc, uint clock, u8 disable);

Function comment

>  struct mmc *find_mmc_device(int dev_num);
>  int mmc_set_dev(int dev_num);
>  void print_mmc_devices(char separator);
> --
> 1.9.1
>
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Re: [U-Boot] [PATCH 11/22] mmc: make mmc_set_ios() return status

[Simon Glass]

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:
> set_ios callback has a return value of 'int' but the mmc_set_ios()
> function ignore this. Modify mmc_set_ios() and the callers of mmc_set_ios() to
> to return the error status.
>
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/mmc.c | 16 ++--
>  include/mmc.h |  2 +-
>  2 files changed, 11 insertions(+), 7 deletions(-)

Reviewed-by: Simon Glass 

>
> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
> index 2931871..2ae6f1c 100644
> --- a/drivers/mmc/mmc.c
> +++ b/drivers/mmc/mmc.c
> @@ -1193,14 +1193,18 @@ static inline int bus_width(uint cap)
>  }
>
>  #ifndef CONFIG_DM_MMC_OPS
> -static void mmc_set_ios(struct mmc *mmc)
> +static int mmc_set_ios(struct mmc *mmc)
>  {
> +   int ret = 0;
> +
> if (mmc->cfg->ops->set_ios)
> -   mmc->cfg->ops->set_ios(mmc);
> +   ret = mmc->cfg->ops->set_ios(mmc);
> +
> +   return ret;
>  }
>  #endif
>
> -void mmc_set_clock(struct mmc *mmc, uint clock)
> +int mmc_set_clock(struct mmc *mmc, uint clock)
>  {
> if (clock > mmc->cfg->f_max)
> clock = mmc->cfg->f_max;
> @@ -1210,14 +1214,14 @@ void mmc_set_clock(struct mmc *mmc, uint clock)
>
> mmc->clock = clock;
>
> -   mmc_set_ios(mmc);
> +   return mmc_set_ios(mmc);
>  }
>
> -static void mmc_set_bus_width(struct mmc *mmc, uint width)
> +static int mmc_set_bus_width(struct mmc *mmc, uint width)
>  {
> mmc->bus_width = width;
>
> -   mmc_set_ios(mmc);
> +   return mmc_set_ios(mmc);
>  }
>
>  void mmc_dump_capabilities(const char *text, uint caps)
> diff --git a/include/mmc.h b/include/mmc.h
> index 3c6971d..9f20eb4 100644
> --- a/include/mmc.h
> +++ b/include/mmc.h
> @@ -540,7 +540,7 @@ int mmc_unbind(struct udevice *dev);
>  int mmc_initialize(bd_t *bis);
>  int mmc_init(struct mmc *mmc);
>  int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
> -void mmc_set_clock(struct mmc *mmc, uint clock);
> +int mmc_set_clock(struct mmc *mmc, uint clock);

Please add function comment.

>  struct mmc *find_mmc_device(int dev_num);
>  int mmc_set_dev(int dev_num);
>  void print_mmc_devices(char separator);
> --
> 1.9.1
>
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Re: [U-Boot] [PATCH 20/22] mmc: Add support for UHS modes

[Simon Glass]

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:
> Add UHS modes to the list of supported modes, get the UHS capabilites of
> the SDcard and implement the procedure to switch the voltage (UHS modes
> use 1v8 IO lines)
> During the voltage switch procedure, DAT0 is used by the card to signal
> when it's ready. The optional card_busy() callback can be used to get this
> information from the host driver.
>
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/mmc.c | 169 
> +++---
>  include/mmc.h |  27 -
>  2 files changed, 188 insertions(+), 8 deletions(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 13/22] mmc: Add a new callback function to enable/disable vdd

[Simon Glass]

Hi,

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:
> From: Kishon Vijay Abraham I 
>
> Add a new callback function *set_vdd* which can be used
> by the platform mmc driver to enable or disable vdd.
> The mmc core can use *mmc_set_vdd* in order to invoke
> the callback function. This will be used during power cycle
> where the specification requires vdd to be disabled for
> 1ms and enabled again.
>
> Signed-off-by: Kishon Vijay Abraham I 
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/mmc-uclass.c | 14 ++
>  drivers/mmc/mmc.c| 12 +++-
>  include/mmc.h| 12 
>  3 files changed, 37 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
> index 9c07871..e1f7995 100644
> --- a/drivers/mmc/mmc-uclass.c
> +++ b/drivers/mmc/mmc-uclass.c
> @@ -52,6 +52,20 @@ int mmc_set_ios(struct mmc *mmc)
> return dm_mmc_set_ios(mmc->dev);
>  }
>
> +int dm_mmc_set_vdd(struct udevice *dev, bool enable)
> +{
> +   struct dm_mmc_ops *ops = mmc_get_ops(dev);
> +
> +   if (!ops->set_vdd)
> +   return -ENOSYS;
> +   return ops->set_vdd(dev, enable);
> +}
> +
> +int mmc_set_vdd(struct mmc *mmc, bool enable)
> +{
> +   return dm_mmc_set_vdd(mmc->dev, enable);
> +}
> +
>  int dm_mmc_get_wp(struct udevice *dev)
>  {
> struct dm_mmc_ops *ops = mmc_get_ops(dev);
> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
> index 10af81d..d40a22b 100644
> --- a/drivers/mmc/mmc.c
> +++ b/drivers/mmc/mmc.c
> @@ -1194,6 +1194,16 @@ static inline int bus_width(uint cap)
>  }
>
>  #ifndef CONFIG_DM_MMC_OPS

Please don't do this. This option is the current way of doing things -
we should not support features in legacy code. Instead, boards should
upgrade to DM to get new features.

> +static int mmc_set_vdd(struct mmc *mmc, bool enable)
> +{
> +   int ret = 0;
> +
> +   if (mmc->cfg->ops->set_vdd)
> +   ret = mmc->cfg->ops->set_vdd(mmc, enable);
> +
> +   return ret;
> +}
> +
>  static int mmc_set_ios(struct mmc *mmc)
>  {
> int ret = 0;
> @@ -1942,7 +1952,7 @@ int mmc_start_init(struct mmc *mmc)
> return err;
>  #endif
> mmc->ddr_mode = 0;
> -
> +   mmc_set_vdd(mmc, true);
> /* First try to set 3.3V. If it fails set to 1.8V */
> err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
> if (err != 0)
> diff --git a/include/mmc.h b/include/mmc.h
> index 89cb26c..43d37a4 100644
> --- a/include/mmc.h
> +++ b/include/mmc.h
> @@ -352,6 +352,15 @@ struct dm_mmc_ops {
> int (*set_ios)(struct udevice *dev);
>
> /**
> +* set_vdd() - Enable or Disable the Vdd line
> +*
> +* @dev:Device to update
> +* @enable: true or false to enable or disable Vdd respectively
> +* @return 0 if OK, -ve on error
> +*/
> +   int (*set_vdd)(struct udevice *dev, bool enable);
> +
> +   /**
>  * get_cd() - See whether a card is present
>  *
>  * @dev:Device to check
> @@ -373,11 +382,13 @@ struct dm_mmc_ops {
>  int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
> struct mmc_data *data);
>  int dm_mmc_set_ios(struct udevice *dev);
> +int dm_mmc_set_vdd(struct udevice *dev, bool enable);
>  int dm_mmc_get_cd(struct udevice *dev);
>  int dm_mmc_get_wp(struct udevice *dev);
>
>  /* Transition functions for compatibility */
>  int mmc_set_ios(struct mmc *mmc);
> +int mmc_set_vdd(struct mmc *mmc, bool enable);
>  int mmc_getcd(struct mmc *mmc);
>  int mmc_getwp(struct mmc *mmc);
>
> @@ -387,6 +398,7 @@ struct mmc_ops {
> struct mmc_cmd *cmd, struct mmc_data *data);
> int (*set_ios)(struct mmc *mmc);
> int (*init)(struct mmc *mmc);
> +   int (*set_vdd)(struct mmc *mmc, bool enable);

Just drop this.

> int (*getcd)(struct mmc *mmc);
> int (*getwp)(struct mmc *mmc);
>  };
> --
> 1.9.1
>

Regards,
Simon
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Re: [U-Boot] [PATCH 19/22] mmc: Add a new callback function to check if the card is busy

[Simon Glass]

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:
> Add a new callback function *card_busy* which can be used to check if the
> card is busy. This is useful during UHS voltage switching to check if the
> switch was successful. Not all controllers may support this, so it's
> optional and when not provided the card is deemed ready.
>
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/mmc-uclass.c | 14 ++
>  drivers/mmc/mmc.c| 10 ++
>  include/mmc.h| 11 +++
>  3 files changed, 35 insertions(+)
>

Again please don't add to legacy code. There is enough of it already!
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Re: [U-Boot] [PATCH 06/22] mmc: Add a fonction to dump the mmc capabilities

[Simon Glass]

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:
> This adds a simple helper function to display information (bus width and
> mode) based on a capability mask. Useful for debug.
>
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/mmc.c | 17 +
>  include/mmc.h |  1 +
>  2 files changed, 18 insertions(+)

subject: fonction typo

>
> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
> index 2e1cb0d..5d418c5 100644
> --- a/drivers/mmc/mmc.c
> +++ b/drivers/mmc/mmc.c
> @@ -1133,6 +1133,23 @@ static void mmc_set_bus_width(struct mmc *mmc, uint 
> width)
> mmc_set_ios(mmc);
>  }
>
> +void mmc_dump_capabilities(const char *text, uint caps)
> +{
> +   enum bus_mode mode;
> +
> +   printf("%s: widths [", text);
> +   if (caps & MMC_MODE_8BIT)
> +   printf("8, ");
> +   if (caps & MMC_MODE_4BIT)
> +   printf("4, ");
> +   printf("1] modes [");
> +
> +   for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
> +   if (MMC_CAP(mode) & caps)
> +   printf("%s, ", mmc_mode_name(mode));
> +   printf("\b\b]\n");
> +}
> +
>  static int sd_select_bus_freq_width(struct mmc *mmc)
>  {
> int err;
> diff --git a/include/mmc.h b/include/mmc.h
> index 60a43b0..afda02d 100644
> --- a/include/mmc.h
> +++ b/include/mmc.h
> @@ -422,6 +422,7 @@ enum bus_mode {
>  };
>
>  const char *mmc_mode_name(enum bus_mode mode);
> +void mmc_dump_capabilities(const char *text, uint caps);

Add function comment

>  /*
>   * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
>   * with mmc_get_mmc_dev().
> --
> 1.9.1
>
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Re: [U-Boot] [PATCH 16/22] mmc: disable the mmc clock during power off

[Simon Glass]

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:
> From: Kishon Vijay Abraham I 
>
> There is no point in having the mmc clock enabled during
> power off. Disable the mmc clock. This is similar to how it's
> programmed in Linux Kernel.
>
> Signed-off-by: Kishon Vijay Abraham I 
> Signed-off-by: Vignesh R 
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/mmc.c | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 03/22] mmc: make ext_csd part of struct mmc

[Simon Glass]

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:
> The ext csd is used for comparison many times. Keep a reference content
> of the ext csd in the struct mmc to avoid reading multiple times
>
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/mmc.c | 22 +-
>  include/mmc.h |  1 +
>  2 files changed, 18 insertions(+), 5 deletions(-)

Reviewed-by: Simon Glass 

But I think debug() is better than error() to avoid code bloat for
something that cannot happen.
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Re: [U-Boot] [PATCH 22/22] mmc: Retry some MMC cmds on failure

[Simon Glass]

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:
> From: Vignesh R 
>
> With certain SD cards like Kingston 8GB/16GB UHS card, it is seen that
> MMC_CMD_ALL_SEND_CID cmd fails on first attempt, but succeeds
> subsequently. Therefore, retry MMC_CMD_ALL_SEND_CID cmd at least thrice
> as done in Linux kernel.
> Similarly, it is seen that MMC_CMD_SET_BLOCKLEN may fail on first
> attempt, therefore retry this cmd five times as done in kernel.
>
> Signed-off-by: Vignesh R 
> Signed-off-by: Kishon Vijay Abraham I 
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/mmc.c | 15 ---
>  1 file changed, 12 insertions(+), 3 deletions(-)
>

So sad to see this sort of thing.

Can we enable this via a quirk and a Kconfig? Could default to on, but
I'm not sure we want this code in regardless.

Reviewed-by: Simon Glass 


> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
> index c7dda64..49edf52 100644
> --- a/drivers/mmc/mmc.c
> +++ b/drivers/mmc/mmc.c
> @@ -275,6 +275,8 @@ int mmc_send_status(struct mmc *mmc, int timeout)
>  int mmc_set_blocklen(struct mmc *mmc, int len)
>  {
> struct mmc_cmd cmd;
> +   int retries = 5;
> +   int err;
>
> if (mmc->ddr_mode)
> return 0;
> @@ -282,8 +284,13 @@ int mmc_set_blocklen(struct mmc *mmc, int len)
> cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
> cmd.resp_type = MMC_RSP_R1;
> cmd.cmdarg = len;
> +   do {
> +   err = mmc_send_cmd(mmc, , NULL);
> +   if (!err)
> +   break;
> +   } while (retries--);
>
> -   return mmc_send_cmd(mmc, , NULL);
> +   return err;
>  }
>
>  static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
> @@ -1867,6 +1874,7 @@ static int mmc_startup(struct mmc *mmc)
> u64 cmult, csize;
> struct mmc_cmd cmd;
> struct blk_desc *bdesc;
> +   int retries = 3;
>
>  #ifdef CONFIG_MMC_SPI_CRC_ON
> if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
> @@ -1874,7 +1882,6 @@ static int mmc_startup(struct mmc *mmc)
> cmd.resp_type = MMC_RSP_R1;
> cmd.cmdarg = 1;
> err = mmc_send_cmd(mmc, , NULL);
> -
> if (err)
> return err;
> }
> @@ -1886,7 +1893,9 @@ static int mmc_startup(struct mmc *mmc)
> cmd.resp_type = MMC_RSP_R2;
> cmd.cmdarg = 0;
>
> -   err = mmc_send_cmd(mmc, , NULL);
> +   do {
> +   err = mmc_send_cmd(mmc, , NULL);
> +   } while (err && retries-- > 0);
>
> if (err)
> return err;
> --
> 1.9.1
>
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Re: [U-Boot] [PATCH 08/22] cmd: mmc: display the mode name and current bus speed in the mmc info

[Simon Glass]

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:
> Display the mode name when the user execute 'mmc info'. Also instead of
> displaying tran_speed, display the actual bus speed.
>
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  cmd/mmc.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 17/22] mmc: Add a execute_tuning() callback to the mmc operations.

[Simon Glass]

Hi,

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:
> Tuning is a mandatory step in the initialization of SDR104 and HS200 modes.
> This callback execute the tuning process.
>
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/mmc-uclass.c | 14 ++
>  drivers/mmc/mmc.c|  5 +
>  include/mmc.h| 12 
>  3 files changed, 31 insertions(+)

This should only support boards which define CONFIG_DM_MMC and DM_MMC_OPS.

Please don't add to the legacy code.
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Re: [U-Boot] [PATCH 12/22] mmc: Enable signal voltage to be selected from mmc core

[Simon Glass]

Hi Jen-Jacques,

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:
> From: Kishon Vijay Abraham I 
>
> Add a new function *mmc_set_signal_voltage* in mmc core
> which can be used during mmc initialization to select the
> signal voltage. Platform driver should use the set_ios
> callback function to select the signal voltage.
>
> Signed-off-by: Kishon Vijay Abraham I 
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/mmc.c | 15 +++
>  include/mmc.h |  5 +
>  2 files changed, 20 insertions(+)
>
> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
> index 2ae6f1c..10af81d 100644
> --- a/drivers/mmc/mmc.c
> +++ b/drivers/mmc/mmc.c
> @@ -29,6 +29,7 @@ static const unsigned int sd_au_size[] = {
> SZ_4M / 512,SZ_8M / 512,(SZ_8M + SZ_4M) / 512,
> SZ_16M / 512,   (SZ_16M + SZ_8M) / 512, SZ_32M / 512,   SZ_64M / 512,
>  };
> +static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
>
>  #if CONFIG_IS_ENABLED(MMC_TINY)
>  static struct mmc mmc_static;
> @@ -1247,6 +1248,12 @@ struct mode_width_tuning {
> uint widths;
>  };
>
> +static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
> +{
> +   mmc->signal_voltage = signal_voltage;
> +   return mmc_set_ios(mmc);
> +}
> +
>  static const struct mode_width_tuning sd_modes_by_pref[] = {
> {
> .mode = SD_HS,
> @@ -1935,6 +1942,14 @@ int mmc_start_init(struct mmc *mmc)
> return err;
>  #endif
> mmc->ddr_mode = 0;
> +
> +   /* First try to set 3.3V. If it fails set to 1.8V */
> +   err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
> +   if (err != 0)
> +   err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
> +   if (err != 0)
> +   printf("failed to set signal voltage\n");

Return error?

> +
> mmc_set_bus_width(mmc, 1);
> mmc_set_clock(mmc, 1);
>
> diff --git a/include/mmc.h b/include/mmc.h
> index 9f20eb4..89cb26c 100644
> --- a/include/mmc.h
> +++ b/include/mmc.h
> @@ -266,6 +266,10 @@
>  #define ENHNCD_SUPPORT (0x2)
>  #define PART_ENH_ATTRIB(0x1f)
>
> +#define MMC_SIGNAL_VOLTAGE_330 1
> +#define MMC_SIGNAL_VOLTAGE_180 2
> +#define MMC_SIGNAL_VOLTAGE_120 3
> +
>  /* Maximum block size for MMC */
>  #define MMC_MAX_BLOCK_LEN  512
>
> @@ -452,6 +456,7 @@ struct mmc {
> int high_capacity;
> uint bus_width;
> uint clock;
> +   uint signal_voltage;

Comment. What does this value mean? What units is it? Millivolts or
something else?

> uint card_caps;
> uint ocr;
> uint dsr;
> --
> 1.9.1
>

Regards,
Simon
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Re: [U-Boot] [PATCH 07/22] mmc: use mmc modes to select the correct bus speed

[Simon Glass]

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:

Please add commit message which what is happening and motivation.

> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/mmc.c | 40 +---
>  1 file changed, 29 insertions(+), 11 deletions(-)

Reviewed-by: Simon Glass 

>
> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
> index 5d418c5..dc7985f 100644
> --- a/drivers/mmc/mmc.c
> +++ b/drivers/mmc/mmc.c
> @@ -171,9 +171,35 @@ const char *mmc_mode_name(enum bus_mode mode)
> else
> return names[mode];
>  }
> +
> +static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
> +{
> +   static const int freqs[] = {
> + [SD_LEGACY]   = 2500,
> + [MMC_HS]  = 2600,
> + [SD_HS]   = 5000,
> + [UHS_SDR12]   = 2500,
> + [UHS_SDR25]   = 5000,
> + [UHS_SDR50]   = 1,
> + [UHS_SDR104]  = 20800,
> + [UHS_DDR50]   = 5000,
> + [MMC_HS_52]   = 5200,
> + [MMC_DDR_52]  = 5200,
> + [MMC_HS_200]  = 2,
> +   };
> +
> +   if (mode == MMC_LEGACY)
> +   return mmc->legacy_speed;
> +   else if (mode >= MMC_MODES_END)
> +   return 0;
> +   else
> +   return freqs[mode];
> +}
> +
>  static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
>  {
> mmc->selected_mode = mode;
> +   mmc->tran_speed = mmc_mode2freq(mmc, mode);
> debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
>   mmc->tran_speed / 100);
> return 0;
> @@ -1185,13 +1211,10 @@ static int sd_select_bus_freq_width(struct mmc *mmc)
> if (err)
> return err;
>
> -   if (mmc->card_caps & MMC_MODE_HS) {
> +   if (mmc->card_caps & MMC_MODE_HS)
> mmc_select_mode(mmc, SD_HS);
> -   mmc->tran_speed = 5000;
> -   } else {
> +   else
> mmc_select_mode(mmc, SD_LEGACY);
> -   mmc->tran_speed = 2500;
> -   }
>
> return 0;
>  }
> @@ -1310,11 +1333,8 @@ static int mmc_select_bus_freq_width(struct mmc *mmc)
> mmc_select_mode(mmc, MMC_DDR_52);
> else
> mmc_select_mode(mmc, MMC_HS_52);
> -   mmc->tran_speed = 5200;
> -   } else if (mmc->card_caps & MMC_MODE_HS) {
> +   } else if (mmc->card_caps & MMC_MODE_HS)
> mmc_select_mode(mmc, MMC_HS);
> -   mmc->tran_speed = 2600;
> -   }
>
> return err;
>  }
> @@ -1584,7 +1604,6 @@ static int mmc_startup(struct mmc *mmc)
> mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
>
> mmc->legacy_speed = freq * mult;
> -   mmc->tran_speed = mmc->legacy_speed;
> mmc_select_mode(mmc, MMC_LEGACY);
>
> mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
> @@ -1659,7 +1678,6 @@ static int mmc_startup(struct mmc *mmc)
> if (err)
> return err;
>
> -   mmc_set_clock(mmc, mmc->tran_speed);
>
> /* Fix the block length for DDR mode */
> if (mmc->ddr_mode) {
> --
> 1.9.1
>
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Re: [U-Boot] [PATCH v2 5/5] usb: host: extend generic OHCI with CLOCK, RESET and PHY

[Simon Glass]

On 12 May 2017 at 11:27,   wrote:
> From: Patrice Chotard 
>
> Add CLOCK, RESET and generic PHY frameworks support
>
> Signed-off-by: Patrice Chotard 
> ---
>
> v2: _ add error path management
> _ add .remove callback
>
>  drivers/usb/host/ohci-generic.c | 99 
> +++--
>  1 file changed, 96 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c
> index f3307f4..f86e223 100644
> --- a/drivers/usb/host/ohci-generic.c
> +++ b/drivers/usb/host/ohci-generic.c
> @@ -5,26 +5,119 @@
>   */
>
>  #include 
> +#include 
>  #include 
> +#include 
> +#include 
> +#include 
> +
>  #include "ohci.h"
>
>  #if !defined(CONFIG_USB_OHCI_NEW)
>  # error "Generic OHCI driver requires CONFIG_USB_OHCI_NEW"
>  #endif
>
> +#define OHCI_MAX_CLOCKS 3
> +#define OHCI_MAX_RESETS 3
> +
>  struct generic_ohci {
> ohci_t ohci;
> +   struct clk clks[OHCI_MAX_CLOCKS];
> +   struct reset_ctl resets[OHCI_MAX_RESETS];
> +   struct phy phy;
>  };
>
> +static void ohci_assert_resets(struct udevice *dev) {
> +   struct generic_ohci *priv = dev_get_priv(dev);
> +   struct reset_ctl reset;
> +   int i;
> +
> +   for (i = OHCI_MAX_RESETS; i >= 0; --i) {
> +   reset = priv->resets[i];
> +
> +   if (reset.dev) {
> +   reset_request();
> +   reset_assert();
> +   reset_free();

Don't you need error checking here?

> +   }
> +   }
> +}
> +
> +static void ohci_disable_clocks(struct udevice *dev) {
> +   struct generic_ohci *priv = dev_get_priv(dev);
> +   struct clk clk;
> +   int i;
> +
> +   for (i = OHCI_MAX_CLOCKS; i >= 0; --i) {
> +   clk = priv->clks[i];
> +
> +   if (clk.dev) {
> +   clk_request(clk.dev, );
> +   clk_disable();
> +   clk_free();
> +   }
> +   }
> +}
> +
>  static int ohci_usb_probe(struct udevice *dev)
>  {
> struct ohci_regs *regs = (struct ohci_regs *)dev_get_addr(dev);
> +   struct generic_ohci *priv = dev_get_priv(dev);
> +   int i, ret;
> +
> +   for (i = 0; i < OHCI_MAX_CLOCKS; i++) {
> +   struct clk clk = priv->clks[i];
>
> -   return ohci_register(dev, regs);
> +   ret = clk_get_by_index(dev, i, );
> +   if (ret < 0)
> +   break;
> +   if (clk_enable()) {
> +   error("failed to enable clock %d\n", i);
> +   clk_free();
> +   goto clk_err;
> +   }
> +   clk_free();
> +   }
> +
> +   for (i = 0; i < OHCI_MAX_RESETS ; i++) {
> +   struct reset_ctl reset = priv->resets[i];
> +
> +   ret = reset_get_by_index(dev, i, );
> +   if (ret < 0)
> +   break;
> +   if (reset_deassert()) {
> +   error("failed to deassert reset %d\n", i);
> +   reset_free();
> +   goto reset_err;
> +   }
> +   reset_free();
> +   }
> +
> +   if (!generic_phy_get_by_index(dev, 0, >phy))
> +   if (generic_phy_init(>phy))
> +   error("failed to init usb phy %d\n", i);
> +
> +   ret = ohci_register(dev, regs);
> +   if (!ret)
> +   return ret;
> +
> +   generic_phy_exit(>phy);
> +
> +reset_err:
> +   ohci_assert_resets(dev);
> +clk_err:
> +   ohci_disable_clocks(dev);
> +
> +   return ret;
>  }
>
> -static int ohci_usb_remove(struct udevice *dev)
> -{
> +static int ohci_usb_remove(struct udevice *dev) {
> +   struct generic_ohci *priv = dev_get_priv(dev);
> +
> +   generic_phy_exit(>phy);
> +   ohci_assert_resets(dev);
> +   ohci_disable_clocks(dev);
> +
> return ohci_deregister(dev);
>  }
>
> --
> 1.9.1
>

Regards,
Simon
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Re: [U-Boot] [PATCH 04/22] mmc: add a function to read and test the ext csd (mmc >= 4)

[Simon Glass]

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:
> This will be reused later in the selection of high speed and ddr modes.
>
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/mmc.c | 49 +
>  1 file changed, 29 insertions(+), 20 deletions(-)

Reviewed-by: Simon Glass 

Please add a function comment.

>
> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
> index 4bd6a96..344d760 100644
> --- a/drivers/mmc/mmc.c
> +++ b/drivers/mmc/mmc.c
> @@ -1146,10 +1146,35 @@ static int sd_select_bus_freq_width(struct mmc *mmc)
> return 0;
>  }
>
> -static int mmc_select_bus_freq_width(struct mmc *mmc)
> +static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
>  {
> -   ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
> +   int err;
> const u8 *ext_csd = mmc->ext_csd;
> +   ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
> +
> +   err = mmc_send_ext_csd(mmc, test_csd);
> +   if (err)
> +   return err;
> +
> +   /* Only compare read only fields */
> +   if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
> +   == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
> +   ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
> +   == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
> +   ext_csd[EXT_CSD_REV]
> +   == test_csd[EXT_CSD_REV] &&
> +   ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
> +   == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
> +   memcmp(_csd[EXT_CSD_SEC_CNT],
> +   _csd[EXT_CSD_SEC_CNT], 4) == 0)
> +   return 0;
> +
> +   return -EBADMSG;
> +}
> +
> +
> +static int mmc_select_bus_freq_width(struct mmc *mmc)
> +{
> /* An array of possible bus widths in order of preference */
> static const unsigned ext_csd_bits[] = {
> EXT_CSD_DDR_BUS_WIDTH_8,
> @@ -1222,25 +1247,9 @@ static int mmc_select_bus_freq_width(struct mmc *mmc)
> mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
> mmc_set_bus_width(mmc, widths[idx]);
>
> -   err = mmc_send_ext_csd(mmc, test_csd);
> -
> -   if (err)
> -   continue;
> -
> -   /* Only compare read only fields */
> -   if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
> -   == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
> -   ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
> -   == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
> -   ext_csd[EXT_CSD_REV]
> -   == test_csd[EXT_CSD_REV] &&
> -   ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
> -   == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
> -   memcmp(_csd[EXT_CSD_SEC_CNT],
> -   _csd[EXT_CSD_SEC_CNT], 4) == 0)
> +   err = mmc_read_and_compare_ext_csd(mmc);
> +   if (!err)
> break;
> -   else
> -   err = -EBADMSG;
> }
>
> if (err)
> --
> 1.9.1
>
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Re: [U-Boot] [PATCH 09/22] mmc: refactor SD startup to make it easier to support new modes

[Simon Glass]

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:
> The SDcard startup process currently handles only 2 modes. To make it
> easier to add support for more modes, let's make the process more generic
> and use a list of the modes to try.
> The major functional change is that when a mode fails we try the next one.
> Not all modes are tried, only those supported by the card and the host.
>
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/mmc.c | 180 
> ++
>  include/mmc.h |   1 +
>  2 files changed, 128 insertions(+), 53 deletions(-)

Reviewed-by: Simon Glass 

Will you be using that foreach macro multiple times?
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Re: [U-Boot] [PATCH 21/22] mmc: Change mode when switching to a boot partition

[Simon Glass]

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:
> Boot partitions do not support HS200. Changing to a lower performance mode
> is required to access them.
> mmc_select_mode_and_width() and sd_select_mode_and_width() are modified to
> make it easier to call them outside of the initialization context.
>
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/mmc.c | 66 
> +--
>  include/mmc.h |  1 +
>  2 files changed, 50 insertions(+), 17 deletions(-)

Reviewed-by: Simon Glass 

Please comment best_mode.
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Re: [U-Boot] [PATCH 01/22] mmc: split mmc_startup()

[Simon Glass]

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:
> No functionnal change here. The function is really big and can be split.
> The part related to bus configuration are put in 2 separate functions: one
> for MMC and one for SD.
>
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/mmc.c | 275 
> +-
>  1 file changed, 149 insertions(+), 126 deletions(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 02/22] mmc: move the MMC startup for version above v4.0 in a separate function

[Simon Glass]

On 12 May 2017 at 12:16, Jean-Jacques Hiblot  wrote:
> no functionnal change. This is only to further reduce the size o
> mmc_startup().
>
> Signed-off-by: Jean-Jacques Hiblot 
> ---
>  drivers/mmc/mmc.c | 316 
> --
>  1 file changed, 165 insertions(+), 151 deletions(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH v2 4/5] usb: host: replace printf() by error() in ehci-generic

[Simon Glass]

On 12 May 2017 at 14:51, Marek Vasut  wrote:
> On 05/12/2017 07:27 PM, patrice.chot...@st.com wrote:
>> From: Patrice Chotard 
>
> Commit message does not explain WHY this change is needed. In fact ...
> commit message is missing altogether ...

Yes it really helps to have a commit message!

>
>> Signed-off-by: Patrice Chotard 
>> ---
>>
>> v2:   _ create this independant path for printf() replacement

Reviewed-by: Simon Glass 

>>
>>  drivers/usb/host/ehci-generic.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/usb/host/ehci-generic.c 
>> b/drivers/usb/host/ehci-generic.c
>> index 808..39b56de 100644
>> --- a/drivers/usb/host/ehci-generic.c
>> +++ b/drivers/usb/host/ehci-generic.c
>> @@ -74,7 +74,7 @@ static int ehci_usb_probe(struct udevice *dev)
>>   if (ret < 0)
>>   break;
>>   if (clk_enable()) {
>> - printf("failed to enable clock %d\n", i);
>> + error("failed to enable clock %d\n", i);
>>   clk_free();
>>   goto clk_err;
>>   }
>> @@ -88,7 +88,7 @@ static int ehci_usb_probe(struct udevice *dev)
>>   if (ret < 0)
>>   break;
>>   if (reset_deassert()) {
>> - printf("failed to deassert reset %d\n", i);
>> + error("failed to deassert reset %d\n", i);
>>   reset_free();
>>   goto reset_err;
>>   }
>>
>
>
> --
> Best regards,
> Marek Vasut
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Re: [U-Boot] [PATCH v2] mmc: atmel_sdhci: Enable the quirk SDHCI_QUIRK_WAIT_SEND_CMD

[Simon Glass]

On 10 May 2017 at 18:25, Wenyou Yang  wrote:
> To fix the timeout of sending the write command, enable the quirk
> SDHCI_QUIRK_WAIT_SEND_CMD.
>
> Signed-off-by: Wenyou Yang 
> ---
>
> Changes in v2:
>  - Add missed this quirk in atmel_sdhci_init().
>
>  drivers/mmc/atmel_sdhci.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH v5 13/14] ARM: DTS: STiH410: rework ohci nodes

[Simon Glass]

On 10 May 2017 at 10:09,   wrote:
> From: Patrice Chotard 
>
> Update the compatible string in order to use ehci-generic
> driver instead of a STi specific one
>
> Signed-off-by: Patrice Chotard 
> ---
>
> v5:   _ update compatible to fit with ohci-generic driver
>
>  arch/arm/dts/stih410.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 4/5] tools: add secure_boot_helper.py

[Simon Glass]

Hi,

On 11 May 2017 at 09:14, Anatolij Gustschin  wrote:
> From: Markus Valentin 
>
> This script should be used for simple creation of secure bootable
> images for baytrail platforms
>
> Signed-off-by: Markus Valentin 
> ---
>  tools/secure_boot_helper.py | 313 
> 
>  1 file changed, 313 insertions(+)
>  create mode 100644 tools/secure_boot_helper.py

It seems to me that this should use binman rather than a separate tool.

Regards,
Simon
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Re: [U-Boot] [PATCH 1/5] x86: congatec: add secureboot enabled defconfig for conga-qeval20-qa3-e3845

[Simon Glass]

On 11 May 2017 at 09:14, Anatolij Gustschin  wrote:
> From: Markus Valentin 
>
> Signed-off-by: Markus Valentin 
> [agust: rebased, fixed to build with v2017.05]
> Signed-off-by: Anatolij Gustschin 
> ---
>  ...0-qa3-e3845-internal-uart-secure-boot_defconfig | 77 
> ++
>  1 file changed, 77 insertions(+)
>  create mode 100644 
> configs/conga-qeval20-qa3-e3845-internal-uart-secure-boot_defconfig

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH v5 11/14] ARM: DTS: STiH410: rework ehci nodes

[Simon Glass]

On 10 May 2017 at 10:09,   wrote:
> From: Patrice Chotard 
>
> Update the compatible string in order to use ehci-generic
> driver instead of a STi specific one
>
> Reverse the order of resets, due to the fact that softreset
> must be deasserted first.
>
> Signed-off-by: Patrice Chotard 
> ---
>
> v5:   _ update compatible and reset order to fit with ehci_generic driver
>
>  arch/arm/dts/stih410.dtsi | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
>

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH] sandbox: Fix comparison of unsigned enum expression warning

[Simon Glass]

On 13 May 2017 at 18:11, Tom Rini  wrote:
> In os_dirent_get_typename() we are checking that type falls within the
> known values of the enum os_dirent_t.  With clang-3.8 testing this value
> as being >= 0 results in a warning as it will always be true.  This
> assumes of course that we are only given valid data.  Given that we want
> to sanity check the input, we change this to check that it falls within
> the range of the first to the last entry in the given enum.
>
> Cc: Simon Glass 
> Signed-off-by: Tom Rini 
> ---
>  arch/sandbox/cpu/os.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH] rockchip: rk3036: clock: code clean

[Simon Glass]

Hi Kever,

On 9 May 2017 at 06:11, Kever Yang  wrote:
> Embeded the shift in mask MACRO, and a few fix btw:
> - hclk/pclk_div range use '<=' instead of '<'
> - use GPLL for pd_bus
> - peri HCLK/PCLK clock rate should not bigger than ACLK

Can you please split out a patch that changes the shift/mask meaning
(and put that patch first)?

Otherwise looks good.

>
> Signed-off-by: Kever Yang 
> ---
>
>  arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 76 ++--
>  drivers/clk/rockchip/clk_rk3036.c   | 93 
> +++--
>  2 files changed, 79 insertions(+), 90 deletions(-)
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Re: [U-Boot] [PATCH v2 2/5] usb: host: add error path and remove callback in ehci-generic

[Simon Glass]

Hi Patrice,

On 12 May 2017 at 11:27,   wrote:
> From: Patrice Chotard 
>
> Add error path to disable enabled clocks and to assert
> deasserted resets
> Populate the remove callback
>
> Signed-off-by: Patrice Chotard 
> ---
> v2: _ split previous path 1, add error path and .remove callback
>
>  drivers/usb/host/ehci-generic.c | 81 
> +++--
>  1 file changed, 70 insertions(+), 11 deletions(-)

Reviewed-by: Simon Glass 

Please see below.

>
> diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c
> index 2190adb..0c29f63 100644
> --- a/drivers/usb/host/ehci-generic.c
> +++ b/drivers/usb/host/ehci-generic.c
> @@ -11,6 +11,9 @@
>  #include 
>  #include "ehci.h"
>
> +#define EHCI_MAX_CLOCKS 3
> +#define EHCI_MAX_RESETS 3
> +
>  /*
>   * Even though here we don't explicitly use "struct ehci_ctrl"
>   * ehci_register() expects it to be the first thing that resides in
> @@ -18,35 +21,74 @@
>   */
>  struct generic_ehci {
> struct ehci_ctrl ctrl;
> +   struct clk clks[EHCI_MAX_CLOCKS];
> +   struct reset_ctl resets[EHCI_MAX_RESETS];
>  };
>
> +static void ehci_assert_resets(struct udevice *dev) {
> +   struct generic_ehci *priv = dev_get_priv(dev);

You could pass priv instead of dev to avoid this line.

> +   struct reset_ctl reset;
> +   int i;
> +
> +   for (i = EHCI_MAX_RESETS; i >= 0; --i) {
> +   reset = priv->resets[i];
> +
> +   if (reset.dev) {
> +reset_request();
> +reset_assert();
> +reset_free();
> +   }
> +   }
> +}
> +
> +static void ehci_disable_clocks(struct udevice *dev) {
> +   struct generic_ehci *priv = dev_get_priv(dev);
> +   struct clk clk;
> +   int i;
> +
> +   for (i = EHCI_MAX_CLOCKS; i >= 0; --i) {

Do you think it is worth adding a function in the uclass to do this to
a list of clks?

> +   clk = priv->clks[i];
> +
> +   if (clk.dev) {
> +   clk_request(clk.dev, );
> +   clk_disable();
> +   clk_free();
> +   }
> +   }
> +}
> +
>  static int ehci_usb_probe(struct udevice *dev)
>  {
> +   struct generic_ehci *priv = dev_get_priv(dev);
> struct ehci_hccr *hccr;
> struct ehci_hcor *hcor;
> -   int i;
> +   int i, ret;
>
> -   for (i = 0; ; i++) {
> -   struct clk clk;
> -   int ret;
> +   for (i = 0; i < EHCI_MAX_CLOCKS; i++) {
> +   struct clk clk = priv->clks[i];
>
> ret = clk_get_by_index(dev, i, );
> if (ret < 0)
> break;
> -   if (clk_enable())
> +   if (clk_enable()) {
> printf("failed to enable clock %d\n", i);
> +   clk_free();
> +   goto clk_err;
> +   }
> clk_free();
> }
>
> -   for (i = 0; ; i++) {
> -   struct reset_ctl reset;
> -   int ret;
> +   for (i = 0; i < EHCI_MAX_RESETS ; i++) {
> +   struct reset_ctl reset = priv->resets[i];
>
> ret = reset_get_by_index(dev, i, );
> if (ret < 0)
> break;
> -   if (reset_deassert())
> +   if (reset_deassert()) {
> printf("failed to deassert reset %d\n", i);
> +   reset_free();
> +   goto reset_err;
> +   }
> reset_free();
> }
>
> @@ -54,7 +96,24 @@ static int ehci_usb_probe(struct udevice *dev)
> hcor = (struct ehci_hcor *)((uintptr_t)hccr +
> HC_LENGTH(ehci_readl(>cr_capbase)));
>
> -   return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
> +   ret = ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
> +   if (!ret)
> +   return ret;
> +
> +reset_err:
> +   ehci_assert_resets(dev);
> +clk_err:
> +   ehci_disable_clocks(dev);
> +
> +   return ret;
> +}
> +
> +static int ehci_usb_remove(struct udevice *dev) {
> +
> +   ehci_assert_resets(dev);
> +   ehci_disable_clocks(dev);
> +
> +   return ehci_deregister(dev);
>  }
>
>  static const struct udevice_id ehci_usb_ids[] = {
> @@ -67,7 +126,7 @@ U_BOOT_DRIVER(ehci_generic) = {
> .id = UCLASS_USB,
> .of_match = ehci_usb_ids,
> .probe = ehci_usb_probe,
> -   .remove = ehci_deregister,
> +   .remove = ehci_usb_remove,
> .ops= _usb_ops,
> .priv_auto_alloc_size = sizeof(struct generic_ehci),
> .flags  = DM_FLAG_ALLOC_PRIV_DMA,
> --
> 1.9.1
>

Regards,
Simon
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Re: [U-Boot] [PATCH v5 14/14] STiH410-B2260: enable USB, fastboot, reset related flags

[Simon Glass]

On 10 May 2017 at 10:09,   wrote:
> From: Patrice Chotard 
>
> Signed-off-by: Patrice Chotard 
> ---
> v5: _ remove CONFIG_USB_OHCI_STI and CONFIG_USB_EHCI_STI
> _ enable CONFIG_USB_EHCI_GENERIC and CONFIG_USB_OHCI_GENERIC
>
> v4: _ enable CONFIG_PHY and CONFIG_STI_USB_PHY
>
> v3: _ none
>
> v2: _ none
>
>  configs/stih410-b2260_defconfig | 38 ++
>  1 file changed, 34 insertions(+), 4 deletions(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH v2 3/5] usb: host: extend generic EHCI driver with PHY

[Simon Glass]

Hi Patrice,

On 12 May 2017 at 11:27,   wrote:
> From: Patrice Chotard 
>
> Add support of generic PHY framework
>
> Signed-off-by: Patrice Chotard 
> ---
>
> v2: _ split previous path 1, add generic PHY framework
>
>  drivers/usb/host/ehci-generic.c | 11 +++
>  1 file changed, 11 insertions(+)
>
> diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c
> index 0c29f63..808 100644
> --- a/drivers/usb/host/ehci-generic.c
> +++ b/drivers/usb/host/ehci-generic.c
> @@ -6,6 +6,8 @@
>
>  #include 
>  #include 
> +#include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -23,6 +25,7 @@ struct generic_ehci {
> struct ehci_ctrl ctrl;
> struct clk clks[EHCI_MAX_CLOCKS];
> struct reset_ctl resets[EHCI_MAX_RESETS];
> +   struct phy phy;
>  };
>
>  static void ehci_assert_resets(struct udevice *dev) {
> @@ -92,6 +95,10 @@ static int ehci_usb_probe(struct udevice *dev)
> reset_free();
> }
>
> +   if (!generic_phy_get_by_index(dev, 0, >phy))

Can you check for the error you expect here when it is not present? I
think it might be -ENOENT? That way you are not ignoring a real error.

> +   if (generic_phy_init(>phy))
> +   error("failed to init usb phy %d\n", i);

Shouldn't you return the error here? I don't think USB will work
without the PHY.

> +
> hccr = map_physmem(dev_get_addr(dev), 0x100, MAP_NOCACHE);
> hcor = (struct ehci_hcor *)((uintptr_t)hccr +
> HC_LENGTH(ehci_readl(>cr_capbase)));
> @@ -100,6 +107,8 @@ static int ehci_usb_probe(struct udevice *dev)
> if (!ret)
> return ret;
>
> +   generic_phy_exit(>phy);
> +
>  reset_err:
> ehci_assert_resets(dev);
>  clk_err:
> @@ -109,7 +118,9 @@ clk_err:
>  }
>
>  static int ehci_usb_remove(struct udevice *dev) {
> +   struct generic_ehci *priv = dev_get_priv(dev);
>
> +   generic_phy_exit(>phy);
> ehci_assert_resets(dev);
> ehci_disable_clocks(dev);
>
> --
> 1.9.1
>

Regards,
Simon
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Re: [U-Boot] [PATCH 3/5] x86: baytrail: secureboot: Add functions for verification of u-boot

[Simon Glass]

Hi,

On 11 May 2017 at 09:14, Anatolij Gustschin  wrote:
> From: Markus Valentin 
>
> Introduce functions that check the integrity of u-boot by utilising the
> hashes stored in the oem-data block.

U-Boot

>
> The verification functions get called in fsp_init()
>
> Signed-off-by: Markus Valentin 
> ---
>  arch/x86/cpu/baytrail/Makefile |   1 +
>  arch/x86/cpu/baytrail/secure_boot.c| 117 
> +
>  .../include/asm/arch-baytrail/fsp/fsp_configs.h|   3 +
>  arch/x86/lib/fsp/fsp_support.c |  15 +++
>  4 files changed, 136 insertions(+)
>  create mode 100644 arch/x86/cpu/baytrail/secure_boot.c
>
> diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile
> index a0216f3..dbf9a82 100644
> --- a/arch/x86/cpu/baytrail/Makefile
> +++ b/arch/x86/cpu/baytrail/Makefile
> @@ -8,4 +8,5 @@ obj-y += cpu.o
>  obj-y += early_uart.o
>  obj-y += fsp_configs.o
>  obj-y += valleyview.o
> +obj-$(CONFIG_BAYTRAIL_SECURE_BOOT) += secure_boot.o
>  obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
> diff --git a/arch/x86/cpu/baytrail/secure_boot.c 
> b/arch/x86/cpu/baytrail/secure_boot.c
> new file mode 100644
> index 000..37c83db
> --- /dev/null
> +++ b/arch/x86/cpu/baytrail/secure_boot.c
> @@ -0,0 +1,117 @@
> +/*
> + * Copyright (C) 2017 Markus Valentin 
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include 
> +
> +#define SB_MANIFEST_BASE   0xFFFE
> +#define SB_MANIFEST_SIZE   0x400
> +#define SB_MANIFEST_OEM_DATA_OFFSET0x58
> +#define SB_MANIFEST_OEM_HASH_OFFSET(SB_MANIFEST_OEM_DATA_OFFSET + 4)
> +#define SB_MANIFEST_OEM_HASH_BASE  (SB_MANIFEST_BASE +\
> +SB_MANIFEST_OEM_HASH_OFFSET)
> +#define SB_MANIFEST_END(SB_MANIFEST_BASE + 
> SB_MANIFEST_SIZE)
> +
> +#define PUB_KEY_MODULUS_SIZE   0x100
> +#define U_BOOT_STAGE_SIZE  0xDD360
> +#define U_BOOT_OFFSET  0x2CA0
> +
> +#define U_BOOT_STAGE_START (CONFIG_SYS_TEXT_BASE + U_BOOT_OFFSET)
> +#define U_BOOT_STAGE_END   (U_BOOT_STAGE_START + 
> U_BOOT_STAGE_SIZE)
> +
> +#define SHA256_U_BOOT_STAGE_ID 0
> +#define SHA256_FSP_STAGE2_ID   1
> +#define SHA256_FIT_PUB_KEY_ID  2
> +
> +#define FIT_KEY_NAME   "dev"
> +
> +/**
> + * This function compares a hash which gets retrieved from the oem data block

I think the function style we have settled on is:

/**
 * verify_oem_sha256() - one line summary
 *
 * More explanation here
 *
 * @hashid: ...
 * ...
 */

> + * with the runtime calculated hash of start_address+size. If they match,
> + * this function returns true. If not, it returns false.
> + *
> + * @param hash_id  offset of oem-data block for hash to compare
> + * @param start_addressaddress where the hash calculation should 
> start
> + * @param size length of the region for hash calculation
> + * @return true on success, false on error
> + */
> +static bool verify_oem_sha256(unsigned int hash_id,
> + void *start_address,
> + size_t size)
> +{
> +   uint8_t value[SHA256_SUM_LEN];
> +   int value_len;
> +
> +   /* calculate address of hash to compare in the oemdata block*/
> +   void *hash_to_verify = (void *)SB_MANIFEST_OEM_HASH_BASE +
> +  (SHA256_SUM_LEN * hash_id);
> +#ifdef DEBUG
> +   unsigned int i = 0;
> +   uint8_t oem_value[SHA256_SUM_LEN];
> +
> +   memcpy(oem_value, hash_to_verify, SHA256_SUM_LEN);
> +   printf("SB: Hash to verify:\t");
> +   for (i = 0; i < SHA256_SUM_LEN; i++)
> +   printf("%X", oem_value[i]);
> +   printf("\n");
> +#endif
> +
> +   /* caluclate the hash of the binary */
> +   calculate_hash(start_address, size, "sha256", (unsigned char *)value,
> +  _len);
> +
> +#ifdef DEBUG
> +   printf("SB: calculated hash:\t");
> +   for (i = 0; i < SHA256_SUM_LEN; i++)
> +   printf("%X", value[i]);
> +   printf("\n");
> +#endif
> +   /* compare the two hash  values */
> +   if (memcmp(hash_to_verify, value, SHA256_SUM_LEN))
> +   return false;
> +   return true;
> +}
> +
> +/**
> + * This function verifies the integrity for u-boot, its devicetree and the 
> ucode
> + * appended or inserted to the devicetree.
> + *
> + * @return true on success, false on error
> + */

Can you put this comment in the header file?

> +bool verify_u_boot_bin(void)
> +{
> +   return verify_oem_sha256(SHA256_U_BOOT_STAGE_ID,
> +(void *)U_BOOT_STAGE_START,
> +U_BOOT_STAGE_SIZE);
> +}
> +
> +/**
> + * This function verifies the integrity for the modulus of the public key 
> which
> + * is stored in the u-boot devicetree for fit 

Re: [U-Boot] [PATCH v5 09/14] STiH410-B2260: enable USB Host Networking

[Simon Glass]

On 10 May 2017 at 10:09,   wrote:

It's a good idea to always have a commit message.

> From: Patrice Chotard 
>
> Signed-off-by: Patrice Chotard 
> ---
>
> v5: _ none
> v4: _ none
> v3: _ none
> v2: _ none
>
>
>  include/configs/stih410-b2260.h | 12 
>  1 file changed, 12 insertions(+)
>

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Re: [U-Boot] [PATCH 3/3] sunxi: video: Add H3/H5 TV out driver

[Simon Glass]

Hi,

On 12 May 2017 at 10:06, Maxime Ripard  wrote:
> Hi Jernej,
>
> The patch content looks fine, but there's a few things that would need
> to be addressed.
>
> On Wed, May 10, 2017 at 06:46:30PM +0200, Jernej Skrabec wrote:
>> This commit adds support for TV (composite) output.
>>
>> Signed-off-by: Jernej Skrabec 
>> ---
>>
>>  arch/arm/include/asm/arch-sunxi/cpu_sun4i.h |  10 ++
>>  arch/arm/include/asm/arch-sunxi/display2.h  |  17 +++
>>  arch/arm/include/asm/arch-sunxi/tve.h   |  17 ++-
>>  drivers/video/sunxi/Makefile|   2 +-
>>  drivers/video/sunxi/sunxi_de2.c |  60 ---
>>  drivers/video/sunxi/sunxi_tve.c | 156 
>> 
>>  drivers/video/sunxi/tve.c   |   6 +-
>
> The difference between sunxi_tve and tve is not really obvious. What
> about calling sunxi_tve tve-uclass, or something like that?

That name is reserved for actual uclasses.

Regards,
Simon
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Re: [U-Boot] [PATCH v2 1/5] reset: add reset_request()

[Simon Glass]

On 12 May 2017 at 11:27,   wrote:
> From: Patrice Chotard 
>
> This is needed in error path to assert previously deasserted
> reset by using a saved reset_ctl reference.
>
> Signed-off-by: Patrice Chotard 
> ---
>  drivers/reset/reset-uclass.c | 9 +
>  include/reset.h  | 9 +
>  2 files changed, 18 insertions(+)

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Re: [U-Boot] [PATCH v5 03/14] mmc: sti_sdhci: Use reset framework

[Simon Glass]

Hi Patrice,

On 10 May 2017 at 10:09,   wrote:
> From: Patrice Chotard 
>
> Signed-off-by: Patrice Chotard 
> Reviewed-by: Jaehoon Chung 
> ---
>
> v5: _ none
> v4: _ none
> v3: _ none
> v2: _ none
>
>
>  drivers/mmc/sti_sdhci.c | 31 ++-
>  1 file changed, 22 insertions(+), 9 deletions(-)
>

Reviewed-by: Simon Glass 

This is fine as is. But please see questions below.

> diff --git a/drivers/mmc/sti_sdhci.c b/drivers/mmc/sti_sdhci.c
> index d6c4d67..8b1b2c0 100644
> --- a/drivers/mmc/sti_sdhci.c
> +++ b/drivers/mmc/sti_sdhci.c
> @@ -8,6 +8,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>
> @@ -16,6 +17,7 @@ DECLARE_GLOBAL_DATA_PTR;
>  struct sti_sdhci_plat {
> struct mmc_config cfg;
> struct mmc mmc;
> +   struct reset_ctl reset;
> int instance;
>  };
>
> @@ -37,17 +39,19 @@ struct sti_sdhci_plat {
>   * W/o these settings the SDHCI could configure and use the embedded 
> controller
>   * with limited features.
>   */
> -static void sti_mmc_core_config(struct udevice *dev)
> +static int sti_mmc_core_config(struct udevice *dev)
>  {
> struct sti_sdhci_plat *plat = dev_get_platdata(dev);
> struct sdhci_host *host = dev_get_priv(dev);
> -   unsigned long *sysconf;
> +   int ret;
>
> /* only MMC1 has a reset line */
> if (plat->instance) {
> -   sysconf = (unsigned long *)(STIH410_SYSCONF5_BASE +
> - ST_MMC_CCONFIG_REG_5);
> -   generic_set_bit(SYSCONF_MMC1_ENABLE_BIT, sysconf);
> +   ret = reset_deassert(>reset);
> +   if (ret < 0) {
> +   error("MMC1 deassert failed: %d", ret);
> +   return ret;
> +   }
> }
>
> writel(STI_FLASHSS_MMC_CORE_CONFIG_1,
> @@ -66,6 +70,8 @@ static void sti_mmc_core_config(struct udevice *dev)
> }
> writel(STI_FLASHSS_MMC_CORE_CONFIG4,
>host->ioaddr + FLASHSS_MMC_CORE_CONFIG_4);
> +
> +   return 0;
>  }
>
>  static int sti_sdhci_probe(struct udevice *dev)
> @@ -80,13 +86,20 @@ static int sti_sdhci_probe(struct udevice *dev)
>  * MMC0 is wired to the SD slot,
>  * MMC1 is wired on the high speed connector
>  */
> -
> -   if (fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "resets", NULL))
> +   if (fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "resets", NULL)) {
> plat->instance = 1;
> -   else
> +   ret = reset_get_by_name(dev, "softreset", >reset);

Two questions:

1. The name "softreset" is in the "resets" property, isn't it? If so,
can you use it instead of hard-coding "softreset" here?
2. Can you not call reset_get_by_name() and deal with the error return
(-ENOENT I think) if there is no such reset?

> +   if (ret) {
> +   error("can't get reset for %s (%d)", dev->name, ret);
> +   return ret;
> +   }
> +   } else {
> plat->instance = 0;
> +   }
>
> -   sti_mmc_core_config(dev);
> +   ret = sti_mmc_core_config(dev);
> +   if (ret)
> +   return ret;
>
> host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
>SDHCI_QUIRK_32BIT_DMA_ADDR |
> --
> 1.9.1
>

Regards,
Simon
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Re: [U-Boot] [PATCH 5/5] doc: x86: Add section about secure boot on Baytrail

[Simon Glass]

On 11 May 2017 at 09:14, Anatolij Gustschin  wrote:
> From: Markus Valentin 
>
> Signed-off-by: Markus Valentin 
> [agust: slightly reworded and fixed alignment]
> Signed-off-by: Anatolij Gustschin 
> ---
>  doc/README.x86 | 41 +
>  1 file changed, 41 insertions(+)
>

Looks good. Please use 'U-Boot' consistently. May need adjusting to use binman.

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Re: [U-Boot] [PATCH v5 08/14] board: STiH410-B2260: add fastboot support

[Simon Glass]

On 10 May 2017 at 10:09,   wrote:
> From: Patrice Chotard 
>
> Add usb_gadget_handle_interrupts(), board_usb_init(),
> board_usb_cleanup() and g_dnl_board_usb_cable_connected()
> callbacks needed for FASTBOOT support
>
> Signed-off-by: Patrice Chotard 
> ---
> v5: _ none
> v4: _ none
> v3: _ none
> v2: _ none
>
>  board/st/stih410-b2260/board.c | 44 
> ++
>  1 file changed, 44 insertions(+)

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Re: [U-Boot] [PATCH 1/3] sunxi: video: Split out TVE code

[Simon Glass]

On 10 May 2017 at 10:46, Jernej Skrabec  wrote:
> Newer SoCs use same TV encoder unit. Split it out so it can be reused
> with new DM video driver.
>
> Signed-off-by: Jernej Skrabec 
> ---
>
>  arch/arm/include/asm/arch-sunxi/display.h | 107 
>  arch/arm/include/asm/arch-sunxi/tve.h | 131 
> ++
>  drivers/video/sunxi/Makefile  |   2 +-
>  drivers/video/sunxi/sunxi_display.c   |  73 +++--
>  drivers/video/sunxi/tve.c |  86 
>  5 files changed, 230 insertions(+), 169 deletions(-)
>  create mode 100644 arch/arm/include/asm/arch-sunxi/tve.h
>  create mode 100644 drivers/video/sunxi/tve.c

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Re: [U-Boot] [PATCH v5 07/14] board: STiH410-B2260: add OHCI and XHCI related defines

[Simon Glass]

On 10 May 2017 at 10:09,   wrote:
> From: Patrice Chotard 
>
> Signed-off-by: Patrice Chotard 
> ---
>
> v5: _ none
> v4: _ none
> v3: _ none
> v2: _ none
>
>  include/configs/stih410-b2260.h | 4 
>  1 file changed, 4 insertions(+)

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Re: [U-Boot] [PATCH v2 05/71] dm: Add a function to create a 'live' device tree

[Simon Glass]

Hi Lothar,

On 11 May 2017 at 08:59, Lothar Waßmann  wrote:
> Hi,
>
> On Wed, 10 May 2017 08:20:44 -0600 Simon Glass wrote:
>> This function converts the flat device tree into a hierarchical one with
>> C structures and pointers. This is easier to access.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>> Changes in v2: None
>>
>>  include/of_live.h |  24 
>>  lib/Makefile  |   1 +
>>  lib/of_live.c | 333 
>> ++
>>  3 files changed, 358 insertions(+)
>>  create mode 100644 include/of_live.h
>>  create mode 100644 lib/of_live.c
>>
>> diff --git a/include/of_live.h b/include/of_live.h
>> new file mode 100644
>> index 00..f5303bb018
>> --- /dev/null
>> +++ b/include/of_live.h
>> @@ -0,0 +1,24 @@
>> +/*
>> + * Copyright (c) 2017 Google, Inc
>> + * Written by Simon Glass 
>> + *
>> + * SPDX-License-Identifier:  GPL-2.0+
>> + *
>> + * Support for a 'live' (as opposed to flat) device tree
>> + */
>> +
>> +#ifndef _OF_LIVE_H
>> +#define _OF_LIVE_H
>> +
>> +struct device_node;
>> +
>> +/**
>> + * of_live_build() - build a live (hierarchical) tree from a flat DT
>> + *
>> + * @fdt_blob: Input tree to convert
>> + * @rootp: Returns live tree that was created
>> + * @return 0 if OK, -ve on error
>> + */
>> +int of_live_build(const void *fdt_blob, struct device_node **rootp);
>> +
>> +#endif
>> diff --git a/lib/Makefile b/lib/Makefile
>> index 23e9f1ef11..bc2fb0a361 100644
>> --- a/lib/Makefile
>> +++ b/lib/Makefile
>> @@ -15,6 +15,7 @@ obj-$(CONFIG_ZLIB) += zlib/
>>  obj-$(CONFIG_BZIP2) += bzip2/
>>  obj-$(CONFIG_TIZEN) += tizen/
>>  obj-$(CONFIG_FIT) += libfdt/
>> +obj-$(CONFIG_OF_LIVE) += of_live.o
>>  obj-$(CONFIG_CMD_DHRYSTONE) += dhry/
>>
>>  obj-$(CONFIG_AES) += aes.o
>> diff --git a/lib/of_live.c b/lib/of_live.c
>> new file mode 100644
>> index 00..51927f9e91
>> --- /dev/null
>> +++ b/lib/of_live.c
>> @@ -0,0 +1,333 @@
>> +/*
>> + * Copyright 2009 Benjamin Herrenschmidt, IBM Corp
>> + * b...@kernel.crashing.org
>> + *
>> + * Based on parts of drivers/of/fdt.c from Linux v4.9
>> + * Modifications for U-Boot
>> + * Copyright (c) 2017 Google, Inc
>> + *
>> + * SPDX-License-Identifier:  GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +static void *unflatten_dt_alloc(void **mem, unsigned long size,
>> + unsigned long align)
>> +{
>> + void *res;
>> +
>> + *mem = PTR_ALIGN(*mem, align);
>> + res = *mem;
>> + *mem += size;
>> +
>> + return res;
>> +}
>> +
>> +/**
>> + * unflatten_dt_node() - Alloc and populate a device_node from the flat tree
>> + * @blob: The parent device tree blob
>> + * @mem: Memory chunk to use for allocating device nodes and properties
>> + * @poffset: pointer to node in flat tree
>> + * @dad: Parent struct device_node
>> + * @nodepp: The device_node tree created by the call
>> + * @fpsize: Size of the node path up at t05he current depth.
>> + * @dryrun: If true, do not allocate device nodes but still calculate needed
>> + * memory size
>> + */
>> +static void *unflatten_dt_node(const void *blob, void *mem, int *poffset,
>> +struct device_node *dad,
>> +struct device_node **nodepp,
>> +unsigned long fpsize, bool dryrun)
>> +{
>> + const __be32 *p;
>> + struct device_node *np;
>> + struct property *pp, **prev_pp = NULL;
>> + const char *pathp;
>> + int l;
>> + unsigned int allocl;
>> + static int depth;
>> + int old_depth;
>> + int offset;
>> + int has_name = 0;
>> + int new_format = 0;
>> +
>> + pathp = fdt_get_name(blob, *poffset, );
>> + if (!pathp)
>> + return mem;
>> +
>> + allocl = ++l;
>> +
>> + /*
>> +  * version 0x10 has a more compact unit name here instead of the full
>> +  * path. we accumulate the full path size using "fpsize", we'll rebuild
>> +  * it later. We detect this because the first character of the name is
>> +  * not '/'.
>> +  */
>> + if ((*pathp) != '/') {
>> + new_format = 1;
>> + if (fpsize == 0) {
>> + /*
>> +  * root node: special case. fpsize accounts for path
>> +  * plus terminating zero. root node only has '/', so
>> +  * fpsize should be 2, but we want to avoid the first
>> +  * level nodes to have two '/' so we use fpsize 1 here
>> +  */
>> + fpsize = 1;
>> + allocl = 2;
>> + l = 1;
>> + pathp = "";
>> + } else {
>> + /*
>> +  * account for '/' and path size minus terminal 0
>> +  * already in 'l'
>> +  

Re: [U-Boot] [PATCH 5/5 v2] spi: ich: Configure SPI BIOS parameters for Linux upon U-Boot exit

[Simon Glass]

Hi Jagan,

On 9 May 2017 at 18:47, Bin Meng  wrote:
> On Tue, May 9, 2017 at 7:20 PM, Stefan Roese  wrote:
>> (Added Simon to Cc)
>
> Really added Simon :-)
>
>>
>>
>> On 09.05.2017 13:14, Jagan Teki wrote:
>>>
>>> On Mon, Apr 24, 2017 at 1:18 PM, Stefan Roese  wrote:

 This patch adds a remove function to the Intel ICH SPI driver, that will
 be called upon U-Boot exit, directly before the OS (Linux) is started.
 This function takes care of configuring the BIOS registers in the SPI
 controller (similar to what a "standard" BIOS or coreboot does), so that
 the Linux MTD device driver is able to correctly read/write to the SPI
 NOR chip. Without this, the chip is not detected at all.

 Signed-off-by: Stefan Roese 
 Reviewed-by: Simon Glass 
 Cc: Bin Meng 
 Cc: Jagan Teki 
 ---
 v2:
 - Added Simons RB line

  drivers/spi/ich.c | 18 ++
  drivers/spi/ich.h | 54
 +++---
  2 files changed, 65 insertions(+), 7 deletions(-)

 diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
 index 893fe33b66..bf2e99b5cc 100644
 --- a/drivers/spi/ich.c
 +++ b/drivers/spi/ich.c
 @@ -617,6 +617,22 @@ static int ich_spi_probe(struct udevice *dev)
 return 0;
  }

 +static int ich_spi_remove(struct udevice *bus)
 +{
 +   struct ich_spi_priv *ctlr = dev_get_priv(bus);
 +
 +   /*
 +* Configure SPI controller so that the Linux MTD driver can
 fully
 +* access the SPI NOR chip
 +*/
 +   ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop);
 +   ich_writew(ctlr, SPI_OPTYPE, ctlr->optype);
 +   ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu);
 +   ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
 +
 +   return 0;
 +}
 +
  static int ich_spi_set_speed(struct udevice *bus, uint speed)
  {
 struct ich_spi_priv *priv = dev_get_priv(bus);
 @@ -700,4 +716,6 @@ U_BOOT_DRIVER(ich_spi) = {
 .priv_auto_alloc_size = sizeof(struct ich_spi_priv),
 .child_pre_probe = ich_spi_child_pre_probe,
 .probe  = ich_spi_probe,
 +   .remove = ich_spi_remove,
 +   .flags  = DM_FLAG_OS_PREPARE,
  };
 diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h
 index bd0a820809..dcb8a9048f 100644
 --- a/drivers/spi/ich.h
 +++ b/drivers/spi/ich.h
 @@ -102,13 +102,6 @@ enum {
  };

  enum {
 -   SPI_OPCODE_TYPE_READ_NO_ADDRESS =   0,
 -   SPI_OPCODE_TYPE_WRITE_NO_ADDRESS =  1,
 -   SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2,
 -   SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS =3
 -};
 -
 -enum {
 ICH_MAX_CMD_LEN = 5,
  };

 @@ -124,8 +117,55 @@ struct spi_trans {
 uint32_t offset;
  };

 +#define SPI_OPCODE_WRSR0x01
 +#define SPI_OPCODE_PAGE_PROGRAM0x02
 +#define SPI_OPCODE_READ0x03
 +#define SPI_OPCODE_WRDIS   0x04
 +#define SPI_OPCODE_RDSR0x05
  #define SPI_OPCODE_WREN0x06
  #define SPI_OPCODE_FAST_READ   0x0b
 +#define SPI_OPCODE_ERASE_SECT  0x20
 +#define SPI_OPCODE_READ_ID 0x9f
 +#define SPI_OPCODE_ERASE_BLOCK 0xd8
>>>
>>>
>>> Wonder why the flash part should be part of SPI, can't we use existing
>>> spi_flash through command interface if there is specific stuff like
>>> this?

This driver is odd in that it tries to decode low-level SPI requests
coming in via spi_xfer() and issue high-level (SPI flash) commands to
the controller. The controller does not actually support generic SPI
operation.

>>
>
> These flash commands need to be programmed to SPI controller register,
> by Intel's design, to make Linux MTD driver happy. Possibly we may do
> like this, like get such value dynamically from spi_flash to program
> this to SPI controller? I once asked a question about this: if some
> other flash part that does not have the exact same command set as what
> was programmed to the SPI controller, will Linux MTD driver still
> work?
>
>>
>> This patch only changes some defines here and passes some allowed
>> opcodes via some configuration registers to the Linux driver.
>>
>> I didn't look closely into this U-Boot driver and how it interacts
>> with the SPI NOR. Simon is most likely the best person to answer
>> on your questions regarding the usage of spi_flash. Simon could
>> you please answer Jagan's questions?
>
> Regards,
> Bin

Regards,
Simon
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Re: [U-Boot] [PATCH 2/5] x86: baytrail: Add fsp-header verification for secure boot fsp

[Simon Glass]

On 11 May 2017 at 09:14, Anatolij Gustschin  wrote:
> From: Markus Valentin 
>
> Introduce a new Kconfig variable for secure boot on baytrail based
> platforms. If this variable is set the build process tries to use
> fsp-sb.bin instead of fsp.bin (-sb is the secure boot enabled fsp).
>
> Also check the two fsp headers against each other and print if secure
> boot is enabled or not.
>
> Signed-off-by: Markus Valentin 
> ---
>  arch/x86/Kconfig   | 13 -
>  arch/x86/include/asm/fsp/fsp_support.h |  2 ++
>  arch/x86/lib/fsp/fsp_support.c | 16 
>  3 files changed, 30 insertions(+), 1 deletion(-)
>

Reviewed-by: Simon Glass 

But please see below

> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> index 9ead3eb..8cea393 100644
> --- a/arch/x86/Kconfig
> +++ b/arch/x86/Kconfig
> @@ -348,7 +348,8 @@ config HAVE_FSP
>  config FSP_FILE
> string "Firmware Support Package binary filename"
> depends on HAVE_FSP
> -   default "fsp.bin"
> +   default "fsp.bin" if !BAYTRAIL_SECURE_BOOT
> +   default "fsp-sb.bin" if BAYTRAIL_SECURE_BOOT
> help
>   The filename of the file to use as Firmware Support Package binary
>   in the board directory.
> @@ -400,6 +401,16 @@ config FSP_BROKEN_HOB
>   do not overwrite the important boot service data which is used by
>   FSP, otherwise the subsequent call to fsp_notify() will fail.
>
> +config BAYTRAIL_SECURE_BOOT
> +   bool "Enable Secure Boot on BayTrail"
> +   depends on HAVE_FSP
> +   default n
> +   help
> + Use the SecureBoot Features of the BayTrail platform. This switch
> + enables the usage of the secure-boot enabled fsp.bin(fsp-sb.bin)
> + for your board you need to provide this yourself. You can 
> reconfigure
> + your fsp with the Intel BCT tool to enable SecureBoot.
> +
>  config ENABLE_MRC_CACHE
> bool "Enable MRC cache"
> depends on !EFI && !SYS_COREBOOT
> diff --git a/arch/x86/include/asm/fsp/fsp_support.h 
> b/arch/x86/include/asm/fsp/fsp_support.h
> index 61d811f..bae17bc 100644
> --- a/arch/x86/include/asm/fsp/fsp_support.h
> +++ b/arch/x86/include/asm/fsp/fsp_support.h
> @@ -21,6 +21,8 @@
>  #define FSP_LOWMEM_BASE0x10UL
>  #define FSP_HIGHMEM_BASE   0x1ULL
>  #define UPD_TERMINATOR 0x55AA
> +#define FSP_FIRST_HEADER_OFFSET0x94
> +#define FSP_SECOND_HEADER_OFFSET   0x20494
>
>
>  /**
> diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
> index a480361..3a537d0 100644
> --- a/arch/x86/lib/fsp/fsp_support.c
> +++ b/arch/x86/lib/fsp/fsp_support.c
> @@ -119,6 +119,13 @@ void fsp_init(u32 stack_top, u32 boot_mode, void 
> *nvs_buf)
> /* No valid FSP info header was found */
> panic("Invalid FSP header");
> }
> +#ifdef CONFIG_BAYTRAIL_SECURE_BOOT

Can you use if (IS_ENABLED(CONFIG_BAYTRAIL_SECURE_BOOT) instead of
#ifdef? It reduces the number of build paths.

> +   /* compare primary and secondary header */
> +   if (memcmp((void *)(CONFIG_FSP_ADDR + FSP_FIRST_HEADER_OFFSET),
> +  (void *)(CONFIG_FSP_ADDR + FSP_SECOND_HEADER_OFFSET),
> +  fsp_hdr->hdr_len))
> +   panic("SB: first & secondary FSP headers don't match");

How about s/SB/Secure Boot/?

> +#endif
>
> config_data.common.fsp_hdr = fsp_hdr;
> config_data.common.stack_top = stack_top;
> @@ -134,6 +141,15 @@ void fsp_init(u32 stack_top, u32 boot_mode, void 
> *nvs_buf)
>
> fsp_upd = _data.fsp_upd;
>
> +#ifdef CONFIG_BAYTRAIL_SECURE_BOOT
> +   /*
> +* if the enable secure boot flag is not 1, secure boot has not
> +* been activated in the FSP which results in the TXE-Engine not
> +* getting loaded
> +*/
> +   printf("FSP: Secure Boot %sabled\n",
> +  fsp_vpd->enable_secure_boot == 1 ? "en" : "dis");
> +#endif
> /* Copy default data from Flash */
> memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset),
>sizeof(struct upd_region));
> --
> 2.7.4
>
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Re: [U-Boot] [PATCH v5 02/14] ARM: dts: stih410-family: Add missing reset_names for mmc1 node

[Simon Glass]

On 10 May 2017 at 10:09,   wrote:
> From: Patrice Chotard 
>
> reset-names property is needed to use the reset
> API for STi sdhci driver.
>
> Signed-off-by: Patrice Chotard 
> Reviewed-by: Jaehoon Chung 
> ---
>
> v5: _ none
> v4: _ none
> v3: _ none
> v2: _ none
>
>  arch/arm/dts/stih407-family.dtsi | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH v5 06/14] usb: dwc3: Add dwc3 glue driver support for STi

[Simon Glass]

Hi Patrice,

On 10 May 2017 at 10:09,   wrote:
> From: Patrice Chotard 
>
> This patch adds the ST glue logic to manage the DWC3 HC
> on STiH407 SoC family. It configures the internal glue
> logic and syscfg registers.
>
> Part of this code been extracted from kernel.org driver
> (drivers/usb/dwc3/dwc3-st.c)
>
> Signed-off-by: Patrice Chotard 
> ---
> v5: _ none
>
> v4: _ none
>
> v3: _ rename dwc3-sti.c to dwc3-sti-glue.c
> _ respect device tree hierarchy, this driver is now responsible
>   for xhci-sti binding (done in sti_dwc3_glue_bind())
>
> v2: _ use setbits_le32() instead of read, modify, write sequence
> _ add missing parenthesis
>
>  arch/arm/include/asm/arch-stih410/sys_proto.h |  11 +
>  doc/device-tree-bindings/usb/dwc3-st.txt  |  60 ++
>  drivers/usb/host/Makefile |   2 +-
>  drivers/usb/host/dwc3-sti-glue.c  | 278 
> ++
>  include/dwc3-sti-glue.h   |  43 
>  5 files changed, 393 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/include/asm/arch-stih410/sys_proto.h
>  create mode 100644 doc/device-tree-bindings/usb/dwc3-st.txt
>  create mode 100644 drivers/usb/host/dwc3-sti-glue.c
>  create mode 100644 include/dwc3-sti-glue.h
>

Reviewed-by: Simon Glass 

Please see below.

> diff --git a/arch/arm/include/asm/arch-stih410/sys_proto.h 
> b/arch/arm/include/asm/arch-stih410/sys_proto.h
> new file mode 100644
> index 000..5c40d3b
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-stih410/sys_proto.h
> @@ -0,0 +1,11 @@
> +/*
> + * Copyright (c) 2017
> + * Patrice Chotard 
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#ifndef _ASM_ARCH_SYS_PROTO_H
> +#define _ASM_ARCH_SYS_PROTO_H
> +
> +#endif /* _ASM_ARCH_SYS_PROTO_H */
> diff --git a/doc/device-tree-bindings/usb/dwc3-st.txt 
> b/doc/device-tree-bindings/usb/dwc3-st.txt
> new file mode 100644
> index 000..a26a139
> --- /dev/null
> +++ b/doc/device-tree-bindings/usb/dwc3-st.txt
> @@ -0,0 +1,60 @@
> +ST DWC3 glue logic
> +
> +This file documents the parameters for the dwc3-st driver.
> +This driver controls the glue logic used to configure the dwc3 core on
> +STiH407 based platforms.
> +
> +Required properties:
> + - compatible  : must be "st,stih407-dwc3"
> + - reg : glue logic base address and USB syscfg ctrl register offset
> + - reg-names   : should be "reg-glue" and "syscfg-reg"
> + - st,syscon   : should be phandle to system configuration node which
> + encompasses the glue registers
> + - resets  : list of phandle and reset specifier pairs. There should be 
> two entries, one
> + for the powerdown and softreset lines of the usb3 IP
> + - reset-names : list of reset signal names. Names should be "powerdown" and 
> "softreset"
> +
> + - #address-cells, #size-cells : should be '1' if the device has sub-nodes
> +   with 'reg' property
> +
> + - pinctl-names: A pinctrl state named "default" must be defined
> +
> + - pinctrl-0   : Pin control group
> +
> + - ranges  : allows valid 1:1 translation between child's address space 
> and
> + parent's address space
> +
> +Sub-nodes:
> +The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
> +example below.
> +
> +NB: The dr_mode property is NOT optional for this driver, as the default 
> value
> +is "otg", which isn't supported by this SoC. Valid dr_mode values for 
> dwc3-st are
> +either "host" or "device".
> +
> +Example:
> +
> +st_dwc3: dwc3@8f94000 {
> +   status  = "disabled";
> +   compatible  = "st,stih407-dwc3";
> +   reg = <0x08f94000 0x1000>, <0x110 0x4>;
> +   reg-names   = "reg-glue", "syscfg-reg";
> +   st,syscfg   = <_core>;
> +   resets  = < STIH407_USB3_POWERDOWN>,
> + < STIH407_MIPHY2_SOFTRESET>;
> +   reset-names = "powerdown", "softreset";
> +   #address-cells  = <1>;
> +   #size-cells = <1>;
> +   pinctrl-names   = "default";
> +   pinctrl-0   = <_usb3>;
> +   ranges;
> +
> +   dwc3: dwc3@990 {
> +   compatible  = "snps,dwc3";
> +   reg = <0x0990 0x10>;
> +   interrupts  = ;
> +   dr_mode = "host";
> +   phy-names   = "usb2-phy", "usb3-phy";
> +   phys= <_picophy2>, <_port2 
> PHY_TYPE_USB3>;
> +   };
> +};

Is this the binding used in Linux?

> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index 48a99f4..af7b7fb 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -64,7 +64,7 @@ obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
>  obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o
>  obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
>  

Re: [U-Boot] USB2.0 device timeout issue.

[Simon Glass]

+Marek

Hi Terry,

On 10 May 2017 at 01:09, Terry Zhou  wrote:
> Hi all,
>
> This is Terry from Marvell BSP team in ShangHai China.
>
> We got one issue in USB like below:
>
>
>
> 1)  When reading large files(larger than 32M ) from USB2.0 u-disk, two
> of the disks got the timeout error like below:
>
> Marvell>> fatload usb 0:1 0x100 got.mkv 0x200
> reading got.mkv
> EHCI timed out on TD - token=0x1e008d80
> EHCI timed out on TD - token=0x1e008d80
> EHCI timed out on TD - token=0x1e008d80
> Error reading cluster
> ** Unable to read file got.mkv **
>
> 2)  I did some research on this issue and found that this issue
> disappear if we set “USB_MAX_XFER_BLK” to a smaller value.
>
> /common/usb_storage.c
>
> @@ -145,7 +145,7 @@ struct us_data {
>
>   * limited to 65535 blocks.
>
>   */
>
> #elif defined(CONFIG_USB_EHCI)
>
> -#define USB_MAX_XFER_BLK  65535
>
> +#define USB_MAX_XFER_BLK  8000
>
>
>
> 3)  We also did some test in linux, it works in linux, we found that
> linux set the max_sectors to 240, and even we set them to a larger value,
>
> The maximum value is 512, which is safe compares to the 8000 in Uboot.
>
> Reference link for linux: http://www.linux-usb.org/FAQ.html#i5
>
>
>
> 4)  I found in Uboot forum, other guys met the same problem with us, see
> the link below:
>
> https://lists.denx.de/pipermail/u-boot/2016-February/246405.html
>
> and there is also some patches to find the optimal value of USB_MAX_XFER_BLK
>
> https://www.mail-archive.com/u-boot@lists.denx.de/msg215952.html
>
> But these patches have not been pushed to the mainline code.
>
>
>
> Could you please share your ideas, why we didn’t merge the patches and how
> should we fix this issue?

I'm not sure why they were not merged. It looks like there were some
comments to address? If that is true then you could resend the series
yourself with the fixes and get it applied.

Regards,
Simon
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Re: [U-Boot] [PATCH] rockchip: Add basic support for phyCORE-RK3288 SoM based carrier board

[Simon Glass]

Hi,

On 8 May 2017 at 07:18, Wadim Egorov  wrote:
> The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC.
> The module can be connected to different carrier boards.
> It can be also equipped with different RAM, SPI flash and eMMC variants.
> The Rapid Development Kit option is using the following setup:
>
>   - 1 GB DDR3 RAM (2 Banks)
>   - 1x 4 KB EEPROM
>   - DP83867 Gigabit Ethernet PHY
>   - 16 MB SPI Flash
>   - 4 GB eMMC Flash
>
> Add basic support for the PCM-947 carrier board, a RK3288 based development
> board made by PHYTEC. This board works in a combination with
> the phyCORE-RK3288 System on Module.
>
> Signed-off-by: Wadim Egorov 
> ---
>  arch/arm/dts/Makefile|   1 +
>  arch/arm/dts/rk3288-phycore-rdk.dts  | 289 +++
>  arch/arm/dts/rk3288-phycore-som.dtsi | 503 
> +++
>  arch/arm/mach-rockchip/rk3288-board-spl.c|  33 +-
>  arch/arm/mach-rockchip/rk3288/Kconfig|  11 +
>  board/phytec/phycore_rk3288/Kconfig  |  15 +
>  board/phytec/phycore_rk3288/MAINTAINERS  |   6 +
>  board/phytec/phycore_rk3288/Makefile |   8 +
>  board/phytec/phycore_rk3288/phycore-rk3288.c |  16 +
>  configs/phycore-rk3288_defconfig |  69 
>  include/configs/phycore_rk3288.h |  23 ++
>  11 files changed, 973 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/rk3288-phycore-rdk.dts
>  create mode 100644 arch/arm/dts/rk3288-phycore-som.dtsi
>  create mode 100644 board/phytec/phycore_rk3288/Kconfig
>  create mode 100644 board/phytec/phycore_rk3288/MAINTAINERS
>  create mode 100644 board/phytec/phycore_rk3288/Makefile
>  create mode 100644 board/phytec/phycore_rk3288/phycore-rk3288.c
>  create mode 100644 configs/phycore-rk3288_defconfig
>  create mode 100644 include/configs/phycore_rk3288.h

Reviewed-by: Simon Glass 

But a few comments below.

[..]

> diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c 
> b/arch/arm/mach-rockchip/rk3288-board-spl.c
> index 74f3379..d1cdc91 100644
> --- a/arch/arm/mach-rockchip/rk3288-board-spl.c
> +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
> @@ -8,6 +8,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -25,6 +26,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> @@ -162,7 +164,10 @@ void board_init_f(ulong dummy)
> struct udevice *pinctrl;
> struct udevice *dev;
> int ret;
> -
> +#if defined(CONFIG_TARGET_PHYCORE_RK3288)
> +   struct udevice *pmic;
> +   uint reg;
> +#endif
> /* Example code showing how to enable the debug UART on RK3288 */
>  #ifdef EARLY_UART
>  #include 
> @@ -206,6 +211,32 @@ void board_init_f(ulong dummy)
> return;
> }
>
> +#if defined(CONFIG_TARGET_PHYCORE_RK3288)

Can you please put all of this in a separate function? Also does it
bloat the code too much to use of_machine_is_compatible() instead of
#ifdef?

> +   ret = uclass_get_device(UCLASS_I2C, 0, );
> +   if (ret) {
> +   debug("I2C init failed: %d\n", ret);
> +   return;
> +   }
> +
> +   ret = i2c_get_chip(dev, 0x1c, 1, );
> +   if (ret) {
> +   debug("Cannot find RK818: %d\n", ret);
> +   return;
> +   }
> +
> +   reg = dm_i2c_reg_read(pmic, REG_USB_CTRL);
> +
> +   /*
> +* Increase USB input current selection to 2A and close charger
> +* when usb lower then 3.4V.
> +*/
> +   reg |= 0x77;
> +   ret = dm_i2c_reg_write(pmic, REG_USB_CTRL, reg);
> +   if (ret) {
> +   debug("Unable to set RK818 REG_USB_CTRL: %d\n", ret);
> +   return;
> +   }
> +#endif
> ret = uclass_get_device(UCLASS_RAM, 0, );
> if (ret) {
> debug("DRAM init failed: %d\n", ret);
> diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig 
> b/arch/arm/mach-rockchip/rk3288/Kconfig
> index 8e7355e..796d731 100644
> --- a/arch/arm/mach-rockchip/rk3288/Kconfig
> +++ b/arch/arm/mach-rockchip/rk3288/Kconfig
> @@ -66,6 +66,15 @@ config TARGET_MIQI_RK3288
>   has 1 or 2 GiB SDRAM. Expansion connectors provide access to
>   I2C, SPI, UART, GPIOs and fan control.
>
> +config TARGET_PHYCORE_RK3288
> +   bool "phyCORE-RK3288"
> +select BOARD_LATE_INIT
> +   help
> + Add basic support for the PCM-947 carrier board, a RK3288 based
> + development board made by PHYTEC. This board works in a combination
> + with the phyCORE-RK3288 System on Module.
> +
> +
>  config TARGET_POPMETAL_RK3288
> bool "PopMetal-RK3288"
> select BOARD_LATE_INIT
> @@ -129,6 +138,8 @@ source "board/google/veyron/Kconfig"
>
>  source "board/mqmaker/miqi_rk3288/Kconfig"
>
> +source "board/phytec/phycore_rk3288/Kconfig"
> +
>  source "board/radxa/rock2/Kconfig"
>
>  

Re: [U-Boot] [PATCH 2/2] x86: minnowmax: Remove incorrect pad-offset of several pins

[Simon Glass]

On 7 May 2017 at 20:52, Bin Meng  wrote:
> Remove 'pad-offset' of soc_gpio_s5_0, soc_gpio_s5_1, soc_gpio_s5_2,
> pin_usb_host_en0 and pin_usb_host_en1. These offsets are actually
> wrong. Correct value should be added by 0x2000, but since they
> are supposed to be 'mode-gpio', 'pad-offset' is not needed at all.
>
> Signed-off-by: Bin Meng 
> ---
>
>  arch/x86/dts/minnowmax.dts | 5 -
>  1 file changed, 5 deletions(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH v5 01/14] mmc: sti_sdhci: Rework sti_mmc_core_config()

[Simon Glass]

On 10 May 2017 at 10:09,   wrote:
> From: Patrice Chotard 
>
> Use struct udevice* as input parameter. Previous
> parameters are retrieved through plat and priv data.
>
> This to prepare to use the reset framework.
>
> Signed-off-by: Patrice Chotard 
> Reviewed-by: Jaehoon Chung 
> ---
> v5: _ none
> v4: _ none
> v3: _ none
> v2: _ none
>
>  drivers/mmc/sti_sdhci.c | 33 ++---
>  1 file changed, 18 insertions(+), 15 deletions(-)

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Re: [U-Boot] [PATCH 1/2] x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode

[Simon Glass]

On 7 May 2017 at 20:52, Bin Meng  wrote:
> Add a device-tree property use-lvl-write-cache that will cause
> writes to lvl to be cached instead of read from lvl before each
> write. This is required on some platforms that have the register
> implemented as dual read/write (such as Baytrail).
>
> Prior to this fix the blue USB port on the Minnowboard Max was
> unusable since USB_HOST_EN0 was set high then immediately set
> low when USB_HOST_EN1 was written.
>
> This also resolves the 'gpio clear | set' command warning like:
>   "Warning: value of pin is still 0"
>
> Signed-off-by: George McCollister 
> 
> Signed-off-by: Bin Meng 
>
> ---
>
>  arch/x86/dts/bayleybay.dts|  6 ++
>  arch/x86/dts/baytrail_som-db5800-som-6867.dts |  6 ++
>  arch/x86/dts/conga-qeval20-qa3-e3845.dts  |  6 ++
>  arch/x86/dts/dfi-bt700.dtsi   |  6 ++
>  arch/x86/dts/minnowmax.dts|  6 ++
>  drivers/gpio/intel_ich6_gpio.c| 30 
> ++-
>  6 files changed, 55 insertions(+), 5 deletions(-)

Reviewed-by: Simon Glass 

I think we need a binding file for intel,ich6-gpio.
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[U-Boot] [PATCH 13/15] armv8/fsl-layerscape: add dwc3 gadget driver support

[yinbo . zhu]

From: Rajat Srivastava 

Implements the dwc3 gadget driver support for LS1043
platform, and performs below operations:
1. Enables snooping support for DWC3 controller.
2. Enables cache coherency in LS1043 platform.

Signed-off-by: Rajat Srivastava 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: yinbo.zhu 
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 93 +-
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  7 ++
 2 files changed, 99 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 6e536d1..12b4278 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -25,6 +25,9 @@
 #include 
 #endif
 #include 
+#include 
+#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -570,11 +573,19 @@ void fsl_lsch2_early_init_f(void)
out_be32(>qspi_cfg, SCFG_QSPI_CLKSEL);
 #endif
/* Make SEC reads and writes snoopable */
+#if defined(CONFIG_LS1043A)
+setbits_be32(>snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
+SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
+SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
+SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
+SCFG_SNPCNFGCR_USB3WRSNP);
+#else
+/* Make SEC reads and writes snoopable */
setbits_be32(>snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
 SCFG_SNPCNFGCR_SECWRSNP |
 SCFG_SNPCNFGCR_SATARDSNP |
 SCFG_SNPCNFGCR_SATAWRSNP);
-
+#endif
/*
 * Enable snoop requests and DVM message requests for
 * Slave insterface S4 (A53 core cluster)
@@ -633,6 +644,86 @@ int qspi_ahb_init(void)
 }
 #endif
 
+#ifdef CONFIG_USB_DWC3
+
+#if defined(CONFIG_LS1043A)
+static struct dwc3_device dwc3_device_data0 = {
+   .maximum_speed = USB_SPEED_HIGH,
+   .base = CONFIG_SYS_FSL_XHCI_USB1_ADDR,
+   .dr_mode = USB_DR_MODE_PERIPHERAL,
+   .index = 0,
+};
+
+static struct dwc3_device dwc3_device_data1 = {
+   .maximum_speed = USB_SPEED_HIGH,
+   .base = CONFIG_SYS_FSL_XHCI_USB2_ADDR,
+   .dr_mode = USB_DR_MODE_PERIPHERAL,
+   .index = 1,
+};
+
+static struct dwc3_device dwc3_device_data2 = {
+   .maximum_speed = USB_SPEED_HIGH,
+   .base = CONFIG_SYS_FSL_XHCI_USB3_ADDR,
+   .dr_mode = USB_DR_MODE_PERIPHERAL,
+   .index = 2,
+};
+
+int usb_gadget_handle_interrupts(int index)
+{
+   dwc3_uboot_handle_interrupt(index);
+   return 0;
+}
+#endif
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+   switch (init) {
+   case USB_INIT_DEVICE:
+   switch (index) {
+#if defined(CONFIG_LS1043A)
+   case 0:
+   dwc3_uboot_init(_device_data0);
+   break;
+   case 1:
+   dwc3_uboot_init(_device_data1);
+   break;
+   case 2:
+   dwc3_uboot_init(_device_data2);
+   break;
+#endif
+   default:
+   printf("Invalid Controller Index\n");
+   return -1;
+   }
+#if defined(CONFIG_LS1043A)
+   dwc3_core_incr_burst_enable(index, 0xf, 0xf);
+   dwc3_core_set_snooping(index, true);
+#endif
+   break;
+   default:
+   break;
+   }
+
+   return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+   switch (init) {
+   case USB_INIT_DEVICE:
+#if defined(CONFIG_LS1043A)
+   dwc3_uboot_exit(index);
+#endif
+   break;
+   default:
+   break;
+   }
+   return 0;
+}
+#endif
+
+
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 9ac124f..5255cdd 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -361,6 +361,13 @@ struct ccsr_gur {
 
 #define SCFG_SNPCNFGCR_SECRDSNP0x8000
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
+#define SCFG_SNPCNFGCR_USB1RDSNP   0x0020
+#define SCFG_SNPCNFGCR_USB1WRSNP   0x0010
+#define SCFG_SNPCNFGCR_USB2RDSNP   0x8000
+#define SCFG_SNPCNFGCR_USB2WRSNP   0x0001
+#define SCFG_SNPCNFGCR_USB3RDSNP   0x2000
+#define SCFG_SNPCNFGCR_USB3WRSNP   0x4000
+
 #define SCFG_SNPCNFGCR_SATARDSNP   0x0080
 #define SCFG_SNPCNFGCR_SATAWRSNP   0x0040
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 05/15] armv8: Add workaround for USB erratum A-009798

[yinbo . zhu]

From: Suresh Gupta 

USB High Speed Squelch Threshold Adjustment
This patch is adding the erratum for LS1043 and LS2080 SoCs.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: yinbo.zhu 
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 22 ++
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  1 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  5 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  2 ++
 4 files changed, 30 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 1544eaa..8d0f1b8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -28,6 +28,25 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
+val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
+val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 bool soc_has_dp_ddr(void)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -200,6 +219,8 @@ void fsl_lsch3_early_init_f(void)
 #endif
erratum_a008514();
erratum_a008336();
+   erratum_a009008();
+   erratum_a009798();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -471,6 +492,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009929();
erratum_a009660();
erratum_a010539();
+   erratum_a009798();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 8f66938..e66253f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -113,6 +113,7 @@
 #define EPU_EPGCR  0x70006ULL
 
 #define CONFIG_SYS_FSL_ERRATUM_A008751
+#define CONFIG_SYS_FSL_ERRATUM_A009798
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 5210b8c..5763586 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -198,6 +198,11 @@ struct ccsr_gur {
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x0040
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x8000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x4000
+#define SCFG_USB3PRM1CR_USB2   0x07C
+#define SCFG_USB3PRM1CR_USB3   0x088
+#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE   0xFC7F
+
u32 devdisr2;   /* Device disable control 2 */
u32 devdisr3;   /* Device disable control 3 */
u32 devdisr4;   /* Device disable control 4 */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index f5e8adb..5e458ae 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -140,6 +140,8 @@
 #define SCFG_BASE  0x01fc
 #define SCFG_USB3PRM1CR0x000
 #define SCFG_USB3PRM1CR_INIT   0x27672b2a
+#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE   0xFC7F
 #define SCFG_QSPICLKCTLR   0x10
 
 #define TP_ITYP_AV 0x0001  /* Initiator available */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 09/15] usb: dwc3: Add helper functions to enable snooping and burst settings

[yinbo . zhu]

From: Rajat Srivastava 

Adds helper functions to enable snooping and outstanding burst beat
settings.

Signed-off-by: Rajat Srivastava 
Signed-off-by: Rajesh Bhagat 
---
 drivers/usb/dwc3/core.c | 45 +
 drivers/usb/dwc3/core.h |  7 +++
 2 files changed, 52 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 85cc96a..4ac599a 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -599,6 +599,51 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc)
 
 #define DWC3_ALIGN_MASK(16 - 1)
 
+void dwc3_core_incr_burst_enable(int index, int btype_incr_val,
+int breq_limit)
+{
+   struct dwc3 *dwc;
+   u32 reg;
+
+   list_for_each_entry(dwc, _list, list) {
+   if (dwc->index != index)
+   continue;
+
+   /*
+* Change burst beat and outstanding pipelined
+* transfers requests
+*/
+   reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
+   reg = (reg & ~DWC3_INCR_BTYPE_MASK) | btype_incr_val;
+   dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
+
+   reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG1);
+   reg = (reg & ~DWC3_BREQ_LIMIT_MASK) | (breq_limit << 8);
+   dwc3_writel(dwc->regs, DWC3_GSBUSCFG1, reg);
+   break;
+   }
+}
+
+void dwc3_core_set_snooping(int index, bool snoop)
+{
+   struct dwc3 *dwc;
+   u32 reg;
+
+   list_for_each_entry(dwc, _list, list) {
+   if (dwc->index != index)
+   continue;
+
+   /* Enable/Disable snooping */
+   reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
+   if (snoop)
+   reg |= DWC3_SNOOP_ENABLE;
+   else
+   reg &= ~DWC3_SNOOP_ENABLE;
+   dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
+   break;
+   }
+}
+
 /**
  * dwc3_uboot_init - dwc3 core uboot initialization code
  * @dwc3_dev: struct dwc3_device containing initialization data
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 72d2fcd..455e7fa 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -593,6 +593,13 @@ struct dwc3_hwparams {
 /* HWPARAMS7 */
 #define DWC3_RAM1_DEPTH(n) ((n) & 0x)
 
+/* GSBUSCFG0 */
+#define DWC3_SNOOP_ENABLE  (0x)
+#define DWC3_INCR_BTYPE_MASK   (0xff)
+
+/* GSBUSCFG1 */
+#define DWC3_BREQ_LIMIT_MASK   (0xf00)
+
 struct dwc3_request {
struct usb_request  request;
struct list_headlist;
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 11/15] config: ls1012aqds: Add USB EHCI support for ls1012aqds

[yinbo . zhu]

From: Rajesh Bhagat 

Add USB EHCI support for ls1012aqds platform

Signed-off-by: Rajat Srivastava 
Signed-off-by: Rajesh Bhagat 
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 +
 include/configs/ls1012aqds.h   | 2 ++
 include/usb/ehci-ci.h  | 2 +-
 3 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 2634195..9ac124f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -35,6 +35,7 @@
 #define CONFIG_SYS_XHCI_USB1_ADDR  (CONFIG_SYS_IMMR + 0x01f0)
 #define CONFIG_SYS_XHCI_USB2_ADDR  (CONFIG_SYS_IMMR + 0x0200)
 #define CONFIG_SYS_XHCI_USB3_ADDR  (CONFIG_SYS_IMMR + 0x0210)
+#define CONFIG_SYS_EHCI_USB1_ADDR  (CONFIG_SYS_IMMR + 0x0760)
 #define CONFIG_SYS_PCIE1_ADDR  (CONFIG_SYS_IMMR + 0x240)
 #define CONFIG_SYS_PCIE2_ADDR  (CONFIG_SYS_IMMR + 0x250)
 #define CONFIG_SYS_PCIE3_ADDR  (CONFIG_SYS_IMMR + 0x260)
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index 5aaf3a7..ebc8d58 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -118,6 +118,8 @@
 #ifdef CONFIG_HAS_FSL_DR_USB
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_ULPI
+#define CONFIG_USB_ULPI_VIEWPORT
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #endif
 
diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h
index 882aed4..ea3b580 100644
--- a/include/usb/ehci-ci.h
+++ b/include/usb/ehci-ci.h
@@ -159,7 +159,7 @@
 #elif defined(CONFIG_MPC512X)
 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR   0
-#elif defined(CONFIG_LS102XA)
+#elif defined(CONFIG_LS102XA) || defined(CONFIG_ARCH_LS1012A)
 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR0
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 15/15] uboot: Kconfig: add ERRATUM config to Kconfig for solve compile issue.

[yinbo . zhu]

add erratum config to Kconfig and instead of config.h's config
for solve ls2080rdb compiling issue

Signed-off-by: Sriram Dash 
Signed-off-by: yinbo.zhu 
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  | 4 
 arch/arm/include/asm/arch-fsl-layerscape/config.h  | 7 ---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
 3 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 4b87dd2..fb2a9ba 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -107,6 +107,10 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A009203
+   select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
+   select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
select SYS_FSL_HAS_CCN504
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index b36bdac..8f66938 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -113,13 +113,6 @@
 #define EPU_EPGCR  0x70006ULL
 
 #define CONFIG_SYS_FSL_ERRATUM_A008751
-#define CONFIG_SYS_FSL_ERRATUM_A009008
-#define CONFIG_SYS_FSL_ERRATUM_A009798
-#define CONFIG_SYS_FSL_ERRATUM_A008997
-#define CONFIG_SYS_FSL_ERRATUM_A009007
-#define CONFIG_SYS_FSL_ERRATUM_A010165
-
-
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 24523eb..27c90fc 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -130,6 +130,7 @@
 #define DCFG_RCWSR15_IFCGRPABASE_QSPI  0x3
 
 #define DCFG_DCSR_BASE 0X70010ULL
+#define DCSR_BASE  0x7ULL
 #define DCSR_USB_PHY1  0x460
 #define DCSR_USB_PHY2  0x461
 #define DCSR_USB_PHY_RX_OVRD_IN_HI 0x1006
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 06/15] armv8: Add workaround for USB erratum A-008997

[yinbo . zhu]

From: Suresh Gupta 

USB3 LFPS Peak-Peak Differential Output Voltage Adjustment
This patch is adding the erratum for LS1043 and LS2080 SoCs.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: yinbo.zhu 
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 29 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  4 +++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  2 ++
 3 files changed, 35 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 8d0f1b8..2b9eb54 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -47,6 +47,33 @@ scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB1 / 4);
+   val &= ~(0x7F << 9);
+   scfg_out32(scfg + SCFG_USB3PRM2CR_USB1 / 4,
+  val | (USB_PCSTXSWINGFULL << 9));
+   val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB2 / 4);
+   val &= ~(0x7F << 9);
+   scfg_out32(scfg + SCFG_USB3PRM2CR_USB2 / 4,
+  val | (USB_PCSTXSWINGFULL << 9));
+   val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB3 / 4);
+   val &= ~(0x7F << 9);
+   scfg_out32(scfg + SCFG_USB3PRM2CR_USB3 / 4,
+  val | (USB_PCSTXSWINGFULL << 9));
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR / 4);
+   val &= ~(0x7F << 9);
+   scfg_out32(scfg + SCFG_USB3PRM2CR / 4,
+  val | (USB_PCSTXSWINGFULL << 9));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
 bool soc_has_dp_ddr(void)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -221,6 +248,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008336();
erratum_a009008();
erratum_a009798();
+   erratum_a008997();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -493,6 +521,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009660();
erratum_a010539();
erratum_a009798();
+   erratum_a008997();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 5763586..554def5 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -198,8 +198,12 @@ struct ccsr_gur {
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x0040
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x8000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x4000
+#define SCFG_BASE  0x0157
+#define SCFG_USB3PRM1CR_USB1   0x070
+#define SCFG_USB3PRM2CR_USB1   0x074
 #define SCFG_USB3PRM1CR_USB2   0x07C
 #define SCFG_USB3PRM1CR_USB3   0x088
+#define SCFG_USB3PRM2CR_USB3   0x08c
 #define USB_TXVREFTUNE 0x9
 #define USB_SQRXTUNE   0xFC7F
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 5e458ae..c7c53b9 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -139,9 +139,11 @@
 /* Supplemental Configuration */
 #define SCFG_BASE  0x01fc
 #define SCFG_USB3PRM1CR0x000
+#define SCFG_USB3PRM2CR 0x004
 #define SCFG_USB3PRM1CR_INIT   0x27672b2a
 #define USB_TXVREFTUNE 0x9
 #define USB_SQRXTUNE   0xFC7F
+#define USB_PCSTXSWINGFULL 0x47
 #define SCFG_QSPICLKCTLR   0x10
 
 #define TP_ITYP_AV 0x0001  /* Initiator available */
-- 
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[U-Boot] [PATCH 10/15] usb: ums: support multiple controllers using controller_index

[yinbo . zhu]

From: Rajesh Bhagat 

Adds a new field in fsg_common namely controller_index to support
multiple controllers usb gadget support.

Signed-off-by: Rajat Srivastava 
Signed-off-by: Rajesh Bhagat 
Acked-by: Lukasz Majewski 
---
 cmd/usb_mass_storage.c  |  2 +-
 drivers/usb/gadget/f_mass_storage.c | 11 +--
 include/usb_mass_storage.h  |  2 +-
 3 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
index 86398fc..139b537 100644
--- a/cmd/usb_mass_storage.c
+++ b/cmd/usb_mass_storage.c
@@ -214,7 +214,7 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
while (1) {
usb_gadget_handle_interrupts(controller_index);
 
-   rc = fsg_main_thread(NULL);
+   rc = fsg_main_thread(controller_index);
if (rc) {
/* Check I/O error */
if (rc == -EIO)
diff --git a/drivers/usb/gadget/f_mass_storage.c 
b/drivers/usb/gadget/f_mass_storage.c
index 1ecb92a..27ca5fe 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -362,6 +362,7 @@ struct fsg_common {
char inquiry_string[8 + 16 + 4 + 1];
 
struct kref ref;
+   unsigned int controller_index;
 };
 
 struct fsg_config {
@@ -691,7 +692,7 @@ static int sleep_thread(struct fsg_common *common)
k = 0;
}
 
-   usb_gadget_handle_interrupts(0);
+   usb_gadget_handle_interrupts(common->controller_index);
}
common->thread_wakeup_needed = 0;
return rc;
@@ -2402,10 +2403,14 @@ static void handle_exception(struct fsg_common *common)
 
 /*-*/
 
-int fsg_main_thread(void *common_)
+int fsg_main_thread(unsigned int controller_index)
 {
int ret;
struct fsg_common   *common = the_fsg_common;
+
+   /* update the controller_index */
+   common->controller_index = controller_index;
+
/* The main loop */
do {
if (exception_in_progress(common)) {
@@ -2476,6 +2481,7 @@ static struct fsg_common *fsg_common_init(struct 
fsg_common *common,
 
common->ops = NULL;
common->private_data = NULL;
+   common->controller_index = 0;
 
common->gadget = gadget;
common->ep0 = gadget->ep0;
@@ -2770,6 +2776,7 @@ int fsg_add(struct usb_configuration *c)
 
fsg_common->ops = NULL;
fsg_common->private_data = NULL;
+   fsg_common->controller_index = 0;
 
the_fsg_common = fsg_common;
 
diff --git a/include/usb_mass_storage.h b/include/usb_mass_storage.h
index 8229f62..f21cc7a 100644
--- a/include/usb_mass_storage.h
+++ b/include/usb_mass_storage.h
@@ -28,6 +28,6 @@ struct ums {
 
 int fsg_init(struct ums *ums_devs, int count);
 void fsg_cleanup(void);
-int fsg_main_thread(void *);
+int fsg_main_thread(unsigned int);
 int fsg_add(struct usb_configuration *c);
 #endif /* __USB_MASS_STORAGE_H__ */
-- 
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[U-Boot] [PATCH 14/15] drivers:usb:xhci:fsl: Implement Erratum A-010151 for FSL USB3 controller

[yinbo . zhu]

From: Sriram Dash 

Currently the controller by default enables the Receive Detect feature in P3
mode in USB 3.0 PHY. However, USB 3.0 PHY does not reliably support receive
detection in P3 mode.
Enabling the USB3 controller to configure USB in P2 mode whenever the Receive
Detect feature is required.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: yinbo.zhu 
---
 drivers/usb/host/xhci-dwc3.c | 5 +
 drivers/usb/host/xhci-fsl.c  | 7 +++
 include/linux/usb/dwc3.h | 1 +
 3 files changed, 13 insertions(+)

diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index 33961cd..adbd9b5 100644
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -97,3 +97,8 @@ void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
setbits_le32(_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
GFLADJ_30MHZ(val));
 }
+
+void dwc3_set_rxdetect_power_mode(struct dwc3 *dwc3_reg, u32 val)
+{
+   setbits_le32(_reg->g_usb3pipectl[0], val);
+}
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index 3a16624..e8e90fa 100644
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -86,6 +86,13 @@ static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg);
 
/*
+   * A-010151: USB controller to configure USB in P2 mode
+   * whenever the Receive Detect feature is required
+   */
+   dwc3_set_rxdetect_power_mode(fsl_xhci->dwc3_reg,
+DWC3_GUSB3PIPECTL_DISRXDETP3);
+
+   /*
 * A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not
 * reliably support Rx Detect in P3 mode(P3 is the default
 * setting). Therefore, some USB3.0 devices may not be detected
diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
index c1b23b2..873b4db 100644
--- a/include/linux/usb/dwc3.h
+++ b/include/linux/usb/dwc3.h
@@ -220,5 +220,6 @@ void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
 int dwc3_core_init(struct dwc3 *dwc3_reg);
 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val);
+void dwc3_set_rxdetect_power_mode(struct dwc3 *dwc3_reg, u32 val);
 #endif
 #endif /* __DWC3_H_ */
-- 
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[U-Boot] [PATCH 08/15] USB: config: fix compiler problem for ls1021atwr

[yinbo . zhu]

remove erratum config from ls102xa for fix compiled issue
because this config was redefined

Signed-off-by: Sriram Dash 
Signed-off-by: yinbo.zhu 
---
 arch/arm/include/asm/arch-ls102xa/config.h | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index 20a7baf..2f7233f 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -110,13 +110,6 @@
 
 #ifdef CONFIG_LS102XA
 #define CONFIG_USB_MAX_CONTROLLER_COUNT1
-#define CONFIG_SYS_FSL_ERRATUM_A008378
-#define CONFIG_SYS_FSL_ERRATUM_A009663
-#define CONFIG_SYS_FSL_ERRATUM_A009008
-#define CONFIG_SYS_FSL_ERRATUM_A009798
-#define CONFIG_SYS_FSL_ERRATUM_A008997
-#define CONFIG_SYS_FSL_ERRATUM_A009007
-#define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 #else
 #error SoC not defined
-- 
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[U-Boot] [PATCH 12/15] armv8: Add workaround for USB erratum A-009008

[yinbo . zhu]

From: Suresh Gupta 

USB High Speed (HS) EYE Height Adjustment
This patch is adding the erratum for LS1043 and LS2080 SoCs.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: yinbo.zhu 
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 26 ++
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  1 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
 3 files changed, 28 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 1597444..6e536d1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -28,6 +28,30 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+val &= ~(0xF << 6);
+scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4, val|(USB_TXVREFTUNE << 6));
+val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+val &= ~(0xF << 6);
+scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4, val|(USB_TXVREFTUNE << 6));
+val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+val &= ~(0xF << 6);
+scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4, val|(USB_TXVREFTUNE << 6));
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+val &= ~(0xF << 6);
+scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
+
 static void erratum_a009798(void)
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
@@ -288,6 +312,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008514();
erratum_a008336();
erratum_a009008();
+   erratum_a009008();
erratum_a009798();
erratum_a008997();
erratum_a009007();
@@ -562,6 +587,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009929();
erratum_a009660();
erratum_a010539();
+   erratum_a009008();
erratum_a009798();
erratum_a008997();
erratum_a009007();
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 7d263fa..b36bdac 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -113,6 +113,7 @@
 #define EPU_EPGCR  0x70006ULL
 
 #define CONFIG_SYS_FSL_ERRATUM_A008751
+#define CONFIG_SYS_FSL_ERRATUM_A009008
 #define CONFIG_SYS_FSL_ERRATUM_A009798
 #define CONFIG_SYS_FSL_ERRATUM_A008997
 #define CONFIG_SYS_FSL_ERRATUM_A009007
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 79857f4..24523eb 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -149,6 +149,7 @@
 #define SCFG_USB3PRM2CR 0x004
 #define SCFG_USB3PRM1CR_INIT   0x27672b2a
 #define USB_TXVREFTUNE 0x9
+#define USB_TXVREFTUNE 0x9
 #define USB_SQRXTUNE   0xFC7F
 #define USB_PCSTXSWINGFULL 0x47
 #define SCFG_QSPICLKCTLR   0x10
-- 
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[U-Boot] [PATCH 04/15] armv7: Add workaround for USB erratum A-009007

[yinbo . zhu]

From: Suresh Gupta 

USB3PHY Observing Intermittent Failure in Rx
This patch is adding the erratum for LS1021.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: yinbo.zhu 
---
 arch/arm/cpu/armv7/ls102xa/soc.c  | 12 
 arch/arm/include/asm/arch-ls102xa/config.h|  1 +
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  5 +
 3 files changed, 18 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 19eb361..4754907 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -94,6 +94,17 @@ static void erratum_a008997(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
+static void erratum_a009007(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
+   u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY_BASE;
+   writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
 void s_init(void)
 {
 }
@@ -184,6 +195,7 @@ int arch_soc_init(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+   erratum_a009007();
return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index 1bec9d0..20a7baf 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -115,6 +115,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A009008
 #define CONFIG_SYS_FSL_ERRATUM_A009798
 #define CONFIG_SYS_FSL_ERRATUM_A008997
+#define CONFIG_SYS_FSL_ERRATUM_A009007
 #define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 #else
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 5f05e0d..fc406f7 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -181,10 +181,15 @@ struct ccsr_gur {
 #define USB_PHY_MPLL_OVRD_IN_HI 0x0024
 #define USB_PHY_LEVEL_OVRD_IN   0x002a
 #define USB_PHY_TX_OVRD_IN_HI   0x2002
+#define USB_PHY_RX_OVRD_IN_HI   0x200c
 #define USB_PHY_TX_OVRD_DRV_LO_VAL  0x784C
 #define USB_PHY_MPLL_OVRD_IN_HI_VAL 0x0080
 #define USB_PHY_LEVEL_OVRD_IN_VAL   0xA9A5
 #define USB_PHY_TX_OVRD_IN_HI_VAL   0x0003
+#define USB_PHY_RX_EQ_VAL_1 0x
+#define USB_PHY_RX_EQ_VAL_2 0x8000
+#define USB_PHY_RX_EQ_VAL_3 0x8004
+#define USB_PHY_RX_EQ_VAL_4 0x800C
 
 
 /* Supplemental Configuration Unit */
-- 
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[U-Boot] [PATCH 07/15] armv8: Add workaround for USB erratum A-009007

[yinbo . zhu]

From: Suresh Gupta 

USB3PHY Observing Intermittent Failure in Rx
This patch is adding the erratum for LS1043 and LS2080 SoCs.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: yinbo.zhu 
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 43 ++
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  5 +++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  | 12 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  7 
 4 files changed, 67 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 2b9eb54..1597444 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -74,6 +74,47 @@ static void erratum_a008997(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
+static void erratum_a009007(void)
+{
+/* TODO:implement the out_be16 instead of writew which is taking
+little endian style */
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+   u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY1;
+   writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   usb_phy = (u32 __iomem *)USB_PHY2;
+   writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   usb_phy = (u32 __iomem *)USB_PHY3;
+   writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+   u32 __iomem *dcsr = (u32 __iomem *)DCSR_BASE;
+   writew(USB_PHY_RX_EQ_VAL_1,
+  (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2,
+  (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3,
+  (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4,
+  (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_1,
+  (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2,
+  (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3,
+  (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4,
+  (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
 bool soc_has_dp_ddr(void)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -249,6 +290,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+   erratum_a009007();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -522,6 +564,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a010539();
erratum_a009798();
erratum_a008997();
+   erratum_a009007();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index e66253f..7d263fa 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -114,6 +114,11 @@
 
 #define CONFIG_SYS_FSL_ERRATUM_A008751
 #define CONFIG_SYS_FSL_ERRATUM_A009798
+#define CONFIG_SYS_FSL_ERRATUM_A008997
+#define CONFIG_SYS_FSL_ERRATUM_A009007
+#define CONFIG_SYS_FSL_ERRATUM_A010165
+
+
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 554def5..2634195 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -206,6 +206,18 @@ struct ccsr_gur {
 #define SCFG_USB3PRM2CR_USB3   0x08c
 #define USB_TXVREFTUNE 0x9
 #define USB_SQRXTUNE   0xFC7F
+#define USB_PCSTXSWINGFULL 0x47
+#define USB_PHY1   0x084F
+#define USB_PHY2   0x0850
+#define USB_PHY3   

[U-Boot] [PATCH 03/15] armv7: Add workaround for USB erratum A-008997

[yinbo . zhu]

From: Suresh Gupta 

USB3 LFPS Peak-Peak Differential Output Voltage Adjustment
This patch is adding the erratum for LS1021.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: yinbo.zhu 
---
 arch/arm/cpu/armv7/ls102xa/soc.c  | 16 
 arch/arm/include/asm/arch-ls102xa/config.h|  1 +
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  9 +
 3 files changed, 26 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 2e64708..19eb361 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -79,6 +79,21 @@ static void erratum_a009798(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+   u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY_BASE;
+   writew(USB_PHY_TX_OVRD_DRV_LO_VAL,
+  (u8 *)(usb_phy) + USB_PHY_TX_OVRD_DRV_LO);
+   writew(USB_PHY_MPLL_OVRD_IN_HI_VAL,
+  (u8 *)(usb_phy) + USB_PHY_MPLL_OVRD_IN_HI);
+   writew(USB_PHY_LEVEL_OVRD_IN_VAL,
+  (u8 *)(usb_phy) + USB_PHY_LEVEL_OVRD_IN);
+   writew(USB_PHY_TX_OVRD_IN_HI_VAL,
+  (u8 *)(usb_phy) + USB_PHY_TX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
 void s_init(void)
 {
 }
@@ -168,6 +183,7 @@ int arch_soc_init(void)
/* Erratum */
erratum_a009008();
erratum_a009798();
+   erratum_a008997();
return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index 14d5de1..1bec9d0 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -114,6 +114,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A009663
 #define CONFIG_SYS_FSL_ERRATUM_A009008
 #define CONFIG_SYS_FSL_ERRATUM_A009798
+#define CONFIG_SYS_FSL_ERRATUM_A008997
 #define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 #else
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index bfc92ee..5f05e0d 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -176,6 +176,15 @@ struct ccsr_gur {
 #define SCFG_USB3PRM1CR 0x070
 #define USB_TXVREFTUNE  0x9
 #define USB_SQRXTUNE0xFC7F
+#define USB_PHY_BASE0x0851
+#define USB_PHY_TX_OVRD_DRV_LO  0x2004
+#define USB_PHY_MPLL_OVRD_IN_HI 0x0024
+#define USB_PHY_LEVEL_OVRD_IN   0x002a
+#define USB_PHY_TX_OVRD_IN_HI   0x2002
+#define USB_PHY_TX_OVRD_DRV_LO_VAL  0x784C
+#define USB_PHY_MPLL_OVRD_IN_HI_VAL 0x0080
+#define USB_PHY_LEVEL_OVRD_IN_VAL   0xA9A5
+#define USB_PHY_TX_OVRD_IN_HI_VAL   0x0003
 
 
 /* Supplemental Configuration Unit */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 02/15] armv7: Add workaround for USB erratum A-009798

[yinbo . zhu]

From: Suresh Gupta 

USB High Speed Squelch Threshold Adjustment
This patch is adding the erratum for LS1021.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: yinbo.zhu 
---
 arch/arm/cpu/armv7/ls102xa/soc.c  | 10 ++
 arch/arm/include/asm/arch-ls102xa/config.h|  1 +
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  1 +
 3 files changed, 12 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index c54daee..2e64708 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -70,6 +70,15 @@ static void erratum_a009008(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
 }
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+   out_be32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 void s_init(void)
 {
 }
@@ -158,6 +167,7 @@ int arch_soc_init(void)
 
/* Erratum */
erratum_a009008();
+   erratum_a009798();
return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index 5b89f16..14d5de1 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -113,6 +113,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A008378
 #define CONFIG_SYS_FSL_ERRATUM_A009663
 #define CONFIG_SYS_FSL_ERRATUM_A009008
+#define CONFIG_SYS_FSL_ERRATUM_A009798
 #define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 #else
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index f474cfd..bfc92ee 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -175,6 +175,7 @@ struct ccsr_gur {
 #define SCFG_BASE   0x0157
 #define SCFG_USB3PRM1CR 0x070
 #define USB_TXVREFTUNE  0x9
+#define USB_SQRXTUNE0xFC7F
 
 
 /* Supplemental Configuration Unit */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 01/15] armv7: Add workaround for USB erratum A-009008

[yinbo . zhu]

From: Suresh Gupta 

USB High Speed (HS) EYE Height Adjustment
This patch is adding the erratum for LS1021.

Signed-off-by: Sriram Dash 
Signed-off-by: yinbo.zhu 
---
 arch/arm/cpu/armv7/ls102xa/soc.c  | 12 
 arch/arm/include/asm/arch-ls102xa/config.h|  4 
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  4 
 3 files changed, 20 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 52fb6f8..c54daee 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -60,6 +60,16 @@ unsigned int get_soc_major_rev(void)
return major;
 }
 
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+   val &= ~(0xF << 6);
+   out_be32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
 void s_init(void)
 {
 }
@@ -146,6 +156,8 @@ int arch_soc_init(void)
 */
out_be32(>eddrtqcfg, 0x63b20042);
 
+   /* Erratum */
+   erratum_a009008();
return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index 2f7233f..5b89f16 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -110,6 +110,10 @@
 
 #ifdef CONFIG_LS102XA
 #define CONFIG_USB_MAX_CONTROLLER_COUNT1
+#define CONFIG_SYS_FSL_ERRATUM_A008378
+#define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_ERRATUM_A009008
+#define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 #else
 #error SoC not defined
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c34fd63..f474cfd 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -172,6 +172,10 @@ struct ccsr_gur {
 #define SCFG_PMCINTECR_ETSECERRG0  0x0008
 #define SCFG_PMCINTECR_ETSECERRG1  0x0004
 #define SCFG_CLUSTERPMCR_WFIL2EN   0x8000
+#define SCFG_BASE   0x0157
+#define SCFG_USB3PRM1CR 0x070
+#define USB_TXVREFTUNE  0x9
+
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH 00/22] mmc: Add support for HS200 and UHS modes

[Jaehoon Chung]

Hi Jean,

On 05/13/2017 03:16 AM, Jean-Jacques Hiblot wrote:
> This series brings support for HS200 and UHS modes to the mmc core.
> It has been tested with the hsmmc driver on several platforms (DRA7,
> AM57x, AM437x, beaglebone black). Some modifications are required in
> the host driver to take advantage of this (voltage switching, tuning).
> The changes to the host driver will be posted a another series as this
> one is already long enough. 
> 
> The series starts with a small refactoring of th sd/mmc startup. The first 4 
> commits
> are mostly moving code around with little or no functionnal change.
> 
> Then the notion of "mode" is introduced. Until now, this information wasn't
> kept in struct mmc. Only the clock and a flag for ddr was kept. Later the mode
> information will be used to select the clock frequency, the ddr flag and the
> tuning procedure. It will be also be check against the host capabilities.
> 
> Then comes the big refactoring job in:
> "mmc: refactor MMC startup to make it easier to support new modes" and
> "mmc: refactor SD startup to make it easier to support new modes"
> Since the number of modes is increasing, it makes sense to try them in a more
> organized way. those commits use a list of supported modes and iterate through
> them to find the best working one. It also allows to switch more easilly from
> one mode to another (switching from HS200 to DDR52 to access boot partitions 
> for example)

Thanks for sending patches. After testing your patches, i will reply.

Best Regards,
Jaehoon Chung

> 
> Then there are a couple of new callback added to:
> - enable/disable Vdd
> - check if the card is busy (used during UHS voltage switching)
> - select the IO voltage
> 
> Then Power cycle is added. Without power cycle, if a UHS card fails to 
> enumerate in
> UHS mode, it can't fall back to high speed mode and card enumeration will 
> fail.
> 
> And finally the last commits add the support for HS200 and UHS.
> I haven't been able to test the UHS SDR104 mode by lack of compatible sdcard.
> 
> With this in place and the required changes in the HSMMC (including DAM), we 
> observe significant
> improvements in the performances on a DRA7 evm:
> eMMC HS200: 130 MB/s
> eMMC DDR52: 80 MB/s
> sd   SDR50: 80 MB/s
> 
> cheers,
> 
> Jean-Jacques
> 
> 
> Jean-Jacques Hiblot (18):
>   mmc: split mmc_startup()
>   mmc: move the MMC startup for version above v4.0 in a separate
> function
>   mmc: make ext_csd part of struct mmc
>   mmc: add a function to read and test the ext csd (mmc >= 4)
>   mmc: introduces mmc modes.
>   mmc: Add a fonction to dump the mmc capabilities
>   mmc: use mmc modes to select the correct bus speed
>   cmd: mmc: display the mode name and current bus speed in the mmc info
>   mmc: refactor SD startup to make it easier to support new modes
>   mmc: refactor MMC startup to make it easier to support new modes
>   mmc: make mmc_set_ios() return status
>   mmc: add power cyle support in mmc core
>   mmc: add a new mmc parameter to disable mmc clock
>   mmc: Add a execute_tuning() callback to the mmc operations.
>   mmc: add HS200 support in MMC core
>   mmc: Add a new callback function to check if the card is busy
>   mmc: Add support for UHS modes
>   mmc: Change mode when switching to a boot partition
> 
> Kishon Vijay Abraham I (3):
>   mmc: Enable signal voltage to be selected from mmc core
>   mmc: Add a new callback function to enable/disable vdd
>   mmc: disable the mmc clock during power off
> 
> Vignesh R (1):
>   mmc: Retry some MMC cmds on failure
> 
>  cmd/mmc.c|3 +-
>  drivers/mmc/fsl_esdhc.c  |2 +-
>  drivers/mmc/mmc-uclass.c |   42 ++
>  drivers/mmc/mmc.c| 1220 
> +-
>  include/mmc.h|  138 +-
>  5 files changed, 1058 insertions(+), 347 deletions(-)
> 

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[U-Boot] [PATCH] meson-gxbb: Add NanoPi K2

[Andreas Färber]

The FriendlyARM NanoPi K2 is a single-board computer.

The Device Tree is taken from the v1 kernel patchset.

Cc: techsupp...@friendlyarm.com
Signed-off-by: Andreas Färber 
---
 arch/arm/dts/meson-gxbb-nanopi-k2.dts | 152 ++
 arch/arm/mach-meson/Kconfig   |   8 ++
 board/amlogic/nanopi-k2/Kconfig   |  12 +++
 board/amlogic/nanopi-k2/MAINTAINERS   |   6 ++
 board/amlogic/nanopi-k2/Makefile  |   7 ++
 board/amlogic/nanopi-k2/nanopi-k2.c   |  54 
 configs/nanopi-k2_defconfig   |  30 +++
 include/configs/nanopi-k2.h   |  19 +
 8 files changed, 288 insertions(+)
 create mode 100644 arch/arm/dts/meson-gxbb-nanopi-k2.dts
 create mode 100644 board/amlogic/nanopi-k2/Kconfig
 create mode 100644 board/amlogic/nanopi-k2/MAINTAINERS
 create mode 100644 board/amlogic/nanopi-k2/Makefile
 create mode 100644 board/amlogic/nanopi-k2/nanopi-k2.c
 create mode 100644 configs/nanopi-k2_defconfig
 create mode 100644 include/configs/nanopi-k2.h

diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts 
b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
new file mode 100644
index 00..a42c89fc75
--- /dev/null
+++ b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2017 Andreas Färber
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+
+#include "meson-gxbb.dtsi"
+#include 
+
+/ {
+   compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
+
+   aliases {
+   serial0 = _AO;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x0 0x0 0x0 0x8000>;
+   };
+
+   vddio_ao3v3: regulator-vddio-ao3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "VDDIO_AO3.3V";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+
+   vddio_tf: gpio-regulator-vddio-tf {
+   compatible = "regulator-gpio";
+
+   regulator-name = "VDDIO_TF";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <330>;
+
+   gpios = <_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
+   gpios-states = <0>;
+
+   states = <330 0>,
+<180 1>;
+   };
+};
+
+ {
+   status = "okay";
+   pinctrl-0 = <_rgmii_pins>;
+   pinctrl-names = "default";
+
+   phy-handle = <_phy0>;
+   phy-mode = "rgmii";
+
+   amlogic,tx-delay-ns = <2>;
+
+   snps,reset-gpio = < GPIOZ_14 0>;
+   snps,reset-delays-us = <0 1 100>;
+   snps,reset-active-low;
+
+   mdio {
+   compatible = "snps,dwmac-mdio";
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   eth_phy0: ethernet-phy@0 {
+   /* Realtek RTL8211F (0x001cc916) */
+

[U-Boot] [PATCH] mx6sabresd: Remove non-SPL targets

[Fabio Estevam]

From: Fabio Estevam 

Now that mx6sabresd_spl_defconfig can be used to boot all
mx6sabresd variants, the non-SPL targets can be safely removed.

Signed-off-by: Fabio Estevam 
---
This patch depends on my previous series where mx6dlsabresd SPL support
has been added.

 board/freescale/mx6sabresd/mx6dlsabresd.cfg | 131 --
 board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg | 169 
 configs/mx6dlsabresd_defconfig  |  44 --
 configs/mx6qsabresd_defconfig   |  44 --
 4 files changed, 388 deletions(-)
 delete mode 100644 board/freescale/mx6sabresd/mx6dlsabresd.cfg
 delete mode 100644 board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
 delete mode 100644 configs/mx6dlsabresd_defconfig
 delete mode 100644 configs/mx6qsabresd_defconfig

diff --git a/board/freescale/mx6sabresd/mx6dlsabresd.cfg 
b/board/freescale/mx6sabresd/mx6dlsabresd.cfg
deleted file mode 100644
index be9f87f..000
--- a/board/freescale/mx6sabresd/mx6dlsabresd.cfg
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-
-BOOT_FROM  sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type   AddressValue
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address   absolute address of the register
- * value value to be stored in the register
- */
-DATA 4 0x020e0774 0x000C
-DATA 4 0x020e0754 0x
-DATA 4 0x020e04ac 0x0030
-DATA 4 0x020e04b0 0x0030
-DATA 4 0x020e0464 0x0030
-DATA 4 0x020e0490 0x0030
-DATA 4 0x020e074c 0x0030
-DATA 4 0x020e0494 0x0030
-DATA 4 0x020e04a0 0x
-DATA 4 0x020e04b4 0x0030
-DATA 4 0x020e04b8 0x0030
-DATA 4 0x020e076c 0x0030
-DATA 4 0x020e0750 0x0002
-DATA 4 0x020e04bc 0x0030
-DATA 4 0x020e04c0 0x0030
-DATA 4 0x020e04c4 0x0030
-DATA 4 0x020e04c8 0x0030
-DATA 4 0x020e04cc 0x0030
-DATA 4 0x020e04d0 0x0030
-DATA 4 0x020e04d4 0x0030
-DATA 4 0x020e04d8 0x0030
-DATA 4 0x020e0760 0x0002
-DATA 4 0x020e0764 0x0030
-DATA 4 0x020e0770 0x0030
-DATA 4 0x020e0778 0x0030
-DATA 4 0x020e077c 0x0030
-DATA 4 0x020e0780 0x0030
-DATA 4 0x020e0784 0x0030
-DATA 4 0x020e078c 0x0030
-DATA 4 0x020e0748 0x0030
-DATA 4 0x020e0470 0x0030
-DATA 4 0x020e0474 0x0030
-DATA 4 0x020e0478 0x0030
-DATA 4 0x020e047c 0x0030
-DATA 4 0x020e0480 0x0030
-DATA 4 0x020e0484 0x0030
-DATA 4 0x020e0488 0x0030
-DATA 4 0x020e048c 0x0030
-DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b080c 0x001F001F
-DATA 4 0x021b0810 0x001F001F
-DATA 4 0x021b480c 0x001F001F
-DATA 4 0x021b4810 0x001F001F
-DATA 4 0x021b083c 0x4220021F
-DATA 4 0x021b0840 0x0207017E
-DATA 4 0x021b483c 0x4201020C
-DATA 4 0x021b4840 0x01660172
-DATA 4 0x021b0848 0x4A4D4E4D
-DATA 4 0x021b4848 0x4A4F5049
-DATA 4 0x021b0850 0x3F3C3D31
-DATA 4 0x021b4850 0x3238372B
-DATA 4 0x021b081c 0x
-DATA 4 0x021b0820 0x
-DATA 4 0x021b0824 0x
-DATA 4 0x021b0828 0x
-DATA 4 0x021b481c 0x
-DATA 4 0x021b4820 0x
-DATA 4 0x021b4824 0x
-DATA 4 0x021b4828 0x
-DATA 4 0x021b08b8 0x0800
-DATA 4 0x021b48b8 0x0800
-DATA 4 0x021b0004 0x0002002D
-DATA 4 0x021b0008 0x00333030
-DATA 4 0x021b000c 0x3F435313
-DATA 4 0x021b0010 0xB66E8B63
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b0018 0x1740
-DATA 4 0x021b001c 0x8000
-DATA 4 0x021b002c 0x26d2
-DATA 4 0x021b0030 0x00431023
-DATA 4 0x021b0040 0x0027
-DATA 4 0x021b 0x831A
-DATA 4 0x021b001c 0x04008032
-DATA 4 0x021b001c 0x8033
-DATA 4 0x021b001c 0x00048031
-DATA 4 0x021b001c 0x05208030
-DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b0020 0x5800
-DATA 4 0x021b0818 0x0007
-DATA 4 0x021b4818 0x0007
-DATA 4 0x021b0004 0x0002556D
-DATA 4 0x021b0404 0x00011006
-DATA 4 0x021b001c 0x
-
-/* set the default clock gate to save power */
-DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC03
-DATA 4 0x020c4070 0x0FFFC000
-DATA 4 0x020c4074 0x3FF0
-DATA 4 0x020c4078 0x00FFF300
-DATA 4 0x020c407c 0x0FC3
-DATA 4 0x020c4080 0x03FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4 0x020e0010 0xF0CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4 0x020e0018 0x007F007F
-DATA 4 0x020e001c 0x007F007F
diff --git a/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg 
b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
deleted file mode 100644
index bb6c60b..000
--- a/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
+++ /dev/null

[U-Boot] [PATCH] mx6sabresd: Remove non-SPL targets

[Fabio Estevam]

From: Fabio Estevam 

Now that mx6sabresd_spl_defconfig can be used to boot all
mx6sabresd variants, the non-SPL targets can be safely removed.

Signed-off-by: Fabio Estevam 
---
This patch depends on my previous series where mx6dlsabresd SPL support
has been added.

 board/freescale/mx6sabresd/mx6dlsabresd.cfg | 131 --
 board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg | 169 
 configs/mx6dlsabresd_defconfig  |  44 --
 configs/mx6qsabresd_defconfig   |  44 --
 4 files changed, 388 deletions(-)
 delete mode 100644 board/freescale/mx6sabresd/mx6dlsabresd.cfg
 delete mode 100644 board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
 delete mode 100644 configs/mx6dlsabresd_defconfig
 delete mode 100644 configs/mx6qsabresd_defconfig

diff --git a/board/freescale/mx6sabresd/mx6dlsabresd.cfg 
b/board/freescale/mx6sabresd/mx6dlsabresd.cfg
deleted file mode 100644
index be9f87f..000
--- a/board/freescale/mx6sabresd/mx6dlsabresd.cfg
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-
-BOOT_FROM  sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type   AddressValue
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address   absolute address of the register
- * value value to be stored in the register
- */
-DATA 4 0x020e0774 0x000C
-DATA 4 0x020e0754 0x
-DATA 4 0x020e04ac 0x0030
-DATA 4 0x020e04b0 0x0030
-DATA 4 0x020e0464 0x0030
-DATA 4 0x020e0490 0x0030
-DATA 4 0x020e074c 0x0030
-DATA 4 0x020e0494 0x0030
-DATA 4 0x020e04a0 0x
-DATA 4 0x020e04b4 0x0030
-DATA 4 0x020e04b8 0x0030
-DATA 4 0x020e076c 0x0030
-DATA 4 0x020e0750 0x0002
-DATA 4 0x020e04bc 0x0030
-DATA 4 0x020e04c0 0x0030
-DATA 4 0x020e04c4 0x0030
-DATA 4 0x020e04c8 0x0030
-DATA 4 0x020e04cc 0x0030
-DATA 4 0x020e04d0 0x0030
-DATA 4 0x020e04d4 0x0030
-DATA 4 0x020e04d8 0x0030
-DATA 4 0x020e0760 0x0002
-DATA 4 0x020e0764 0x0030
-DATA 4 0x020e0770 0x0030
-DATA 4 0x020e0778 0x0030
-DATA 4 0x020e077c 0x0030
-DATA 4 0x020e0780 0x0030
-DATA 4 0x020e0784 0x0030
-DATA 4 0x020e078c 0x0030
-DATA 4 0x020e0748 0x0030
-DATA 4 0x020e0470 0x0030
-DATA 4 0x020e0474 0x0030
-DATA 4 0x020e0478 0x0030
-DATA 4 0x020e047c 0x0030
-DATA 4 0x020e0480 0x0030
-DATA 4 0x020e0484 0x0030
-DATA 4 0x020e0488 0x0030
-DATA 4 0x020e048c 0x0030
-DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b080c 0x001F001F
-DATA 4 0x021b0810 0x001F001F
-DATA 4 0x021b480c 0x001F001F
-DATA 4 0x021b4810 0x001F001F
-DATA 4 0x021b083c 0x4220021F
-DATA 4 0x021b0840 0x0207017E
-DATA 4 0x021b483c 0x4201020C
-DATA 4 0x021b4840 0x01660172
-DATA 4 0x021b0848 0x4A4D4E4D
-DATA 4 0x021b4848 0x4A4F5049
-DATA 4 0x021b0850 0x3F3C3D31
-DATA 4 0x021b4850 0x3238372B
-DATA 4 0x021b081c 0x
-DATA 4 0x021b0820 0x
-DATA 4 0x021b0824 0x
-DATA 4 0x021b0828 0x
-DATA 4 0x021b481c 0x
-DATA 4 0x021b4820 0x
-DATA 4 0x021b4824 0x
-DATA 4 0x021b4828 0x
-DATA 4 0x021b08b8 0x0800
-DATA 4 0x021b48b8 0x0800
-DATA 4 0x021b0004 0x0002002D
-DATA 4 0x021b0008 0x00333030
-DATA 4 0x021b000c 0x3F435313
-DATA 4 0x021b0010 0xB66E8B63
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b0018 0x1740
-DATA 4 0x021b001c 0x8000
-DATA 4 0x021b002c 0x26d2
-DATA 4 0x021b0030 0x00431023
-DATA 4 0x021b0040 0x0027
-DATA 4 0x021b 0x831A
-DATA 4 0x021b001c 0x04008032
-DATA 4 0x021b001c 0x8033
-DATA 4 0x021b001c 0x00048031
-DATA 4 0x021b001c 0x05208030
-DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b0020 0x5800
-DATA 4 0x021b0818 0x0007
-DATA 4 0x021b4818 0x0007
-DATA 4 0x021b0004 0x0002556D
-DATA 4 0x021b0404 0x00011006
-DATA 4 0x021b001c 0x
-
-/* set the default clock gate to save power */
-DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC03
-DATA 4 0x020c4070 0x0FFFC000
-DATA 4 0x020c4074 0x3FF0
-DATA 4 0x020c4078 0x00FFF300
-DATA 4 0x020c407c 0x0FC3
-DATA 4 0x020c4080 0x03FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4 0x020e0010 0xF0CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4 0x020e0018 0x007F007F
-DATA 4 0x020e001c 0x007F007F
diff --git a/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg 
b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
deleted file mode 100644
index bb6c60b..000
--- a/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
+++ /dev/null
@@ 

Re: [U-Boot] [U-Boot 3/3] rockchip: rk3288: enable rockusb support on rk3288 based device

[Lukasz Majewski]

Dear Simon, Eddie,

> >>
> >> Let's convert them soon!  
> > Does it means i can keep it in rk3288_common.h?  
> 
> Anything new you add must go into defconfig. If it depends on a
> non-Kconfig option, then just leave out the depend. We cannot add new
> things to the config whitelist, so you should get a build error if you
> try to add a new option outside Kconfig.

Ok. Then I will wait for next iteration


Best regards,

Lukasz Majewski

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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[U-Boot] [PATCH] block: sata: ceva: drop extraneous netdev.h include

[Peter Robinson]

Drop include of netdev.h as it's a SATA driver not a network driver.

Signed-off-by: Peter Robinson 
---
 drivers/block/sata_ceva.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/block/sata_ceva.c b/drivers/block/sata_ceva.c
index 9b5466483a..9ac195bac2 100644
--- a/drivers/block/sata_ceva.c
+++ b/drivers/block/sata_ceva.c
@@ -6,7 +6,6 @@
  */
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
-- 
2.13.0

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Re: [U-Boot] [PATCH] omap3: omap3_logic: switch to using TI_COMMON_CMD_OPTION

[Tom Rini]

On Sat, May 13, 2017 at 08:14:37AM -0500, Adam Ford wrote:

> Enable TI_COMMON_CMD_OPTIONS and remove similar options
> from the defconfig. Updated with savedefconfig
> 
> CMD_USB isn't enabled yet.  I have some testing to do with
> musb.
> 
> Signed-off-by: Adam Ford 
> 
> diff --git a/board/logicpd/omap3som/Kconfig b/board/logicpd/omap3som/Kconfig
> index 03d272a..68d40dc 100644

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [PATCH] power: twl4030: Add imply CMD_POWEROFF when TWL4030 is enabled

[Tom Rini]

On Sat, May 13, 2017 at 07:02:24AM -0500, Adam Ford wrote:

> Now that CMD_POWEROFF can turn off the twl4030, let's imply that
> just incase someone wants to disable it.
> 
> Signed-off-by: Adam Ford 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [PATCH 2/3] orion_wdt: Support for the Orion Watchdog

[Tom Rini]

On Fri, May 12, 2017 at 04:10:07PM +0200, Marek Behún wrote:

> This watchdog can be found on some Armada chips.
> 
> Signed-off-by: Marek Behun 
> ---
>  drivers/watchdog/Kconfig |   7 +++
>  drivers/watchdog/Makefile|   1 +
>  drivers/watchdog/orion_wdt.c | 128 
> +++
>  3 files changed, 136 insertions(+)
>  create mode 100644 drivers/watchdog/orion_wdt.c

In a few places you're adding 2 newlines instead of one, please fix.
Also:
[snip]
> +config ORION_WATCHDOG
> + bool "Enable "
> + select HW_WATCHDOG

You need to finish the "Enable" line, and most likely add a depends on
... as well, unless you can also enable and build it for sandbox (which
would be great, that's where we get our static analysis done).

> + * This file is licensed under  the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.

SPDX tag please.

For the rest of it, please make it use the watchdog uclass and so forth,
thanks!

-- 
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Re: [U-Boot] [PATCH v3 6/8] rockchip: board: puma_rk3399: enable BMP_16BPP, BMP_24BPP and BMP_32BPP

[Dr. Philipp Tomsich]

Changes in v3:
- SYS_WHITE_ON_BLACK has been migrated to KConfig (upstream) and is on by 
default.


> On 14 May 2017, at 11:13, Simon Glass  wrote:
> 
> Hi Philipp,
> 
> On 5 May 2017 at 13:48, Philipp Tomsich
>  > wrote:
>> With video output support for the RK3399-Q7 (Puma) available, we want
>> CMD_BMP enabled and the support for 16bit, 24bit and 32bit BMPs
>> defined.
>> 
>> Signed-off-by: Philipp Tomsich > >
>> 
>> ---
>> 
>> Changes in v3: None
>> Changes in v2:
>> - enable SYS_WHITE_ON_BLACK via defconfig
> 
> I cannot see this in this patch.
> 
>> 
>> configs/puma-rk3399_defconfig | 1 +
>> include/configs/puma_rk3399.h | 4 +++-
>> 2 files changed, 4 insertions(+), 1 deletion(-)
> 
> Acked-by: Simon Glass >
> 
>> 
>> diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
>> index 207445d..a8f60ae 100644
>> --- a/configs/puma-rk3399_defconfig
>> +++ b/configs/puma-rk3399_defconfig
>> @@ -47,6 +47,7 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y
>> CONFIG_SPI_FLASH=y
>> CONFIG_SPI_FLASH_WINBOND=y
>> CONFIG_PHY_MICREL=y
>> +CONFIG_PHY_MICREL_KSZ9031=y
>> CONFIG_DM_ETH=y
>> CONFIG_ETH_DESIGNWARE=y
>> CONFIG_GMAC_ROCKCHIP=y
>> diff --git a/include/configs/puma_rk3399.h b/include/configs/puma_rk3399.h
>> index 4081362..af1dae8 100644
>> --- a/include/configs/puma_rk3399.h
>> +++ b/include/configs/puma_rk3399.h
>> @@ -26,6 +26,8 @@
>> #define CONFIG_SERIAL_TAG
>> #define CONFIG_ENV_OVERWRITE
>> 
>> -#define CONFIG_SYS_WHITE_ON_BLACK
>> +#define CONFIG_BMP_16BPP
>> +#define CONFIG_BMP_24BPP
>> +#define CONFIG_BMP_32BPP
>> 
>> #endif
>> --
>> 1.9.1
>> 
> 
> Regards,
> Simon

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Re: [U-Boot] [PATCH] ARMv8/sec_firmware : Update chosen/kaslr-seed

[Tom Rini]

On Sat, May 13, 2017 at 05:37:05AM +0530, Ruchika Gupta wrote:

> kASLR support in kernel requires a random number to be passed via
> chosen/kaslr-seed propert. sec_firmware generates this random seed
> which can then be passed in the device tree node
> 
> sec_firmware reserves JR3 for it's own usage. Node for JR3 is
> removed from device-tree.
> 
> Signed-off-by: Ruchika Gupta 
[snip]
> @@ -345,6 +345,75 @@ static void fdt_fixup_msi(void *blob)
>  }
>  #endif
>  
> +
> +int fdt_fixup_kaslr(void *fdt)

There's a few places like this where you're adding extra whitespace,
please fix.

-- 
Tom


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