Re: [U-Boot] [PATCH] LS1012A: change the size of flash

[Suresh Gupta]

> -Original Message-
> From: york sun
> Sent: Tuesday, May 23, 2017 9:50 PM
> To: Suresh Gupta ; u-boot@lists.denx.de
> Cc: ja...@openedev.com
> Subject: Re: [PATCH] LS1012A: change the size of flash
> 
> On 04/25/2017 02:20 AM, Suresh Gupta wrote:
> > LS1012A has S25FS512S flash of 64M size
> >
> > Signed-off-by: Suresh Gupta 
> > ---
> >  include/configs/ls1012a_common.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/include/configs/ls1012a_common.h
> > b/include/configs/ls1012a_common.h
> > index 0db926f..861cbc3 100644
> > --- a/include/configs/ls1012a_common.h
> > +++ b/include/configs/ls1012a_common.h
> > @@ -56,7 +56,7 @@
> >  #define QSPI0_AMBA_BASE0x4000
> >  #define CONFIG_SPI_FLASH_SPANSION
> >
> > -#define FSL_QSPI_FLASH_SIZE(1 << 24)
> > +#define FSL_QSPI_FLASH_SIZESZ_64M
> >  #define FSL_QSPI_FLASH_NUM 2
> >
> >  /*
> >
> 
> Suresh,
> 
> LS1012A doesn't have any flash built-in. Do you mean all boards supporting
> LS1012A have the same flash chip with 64MB in size? Please clarify.
> 
> York
York,
You are right, all boards has 64MB (S25FS512S) flash.
Sorry for confusion.

SuresH 
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[U-Boot] [PATCH] power: pmic: tps65218: Fix tps65218_voltage_update function

[Keerthy]

Currently while setting the vsel value for dcdc1 and dcdc2
the driver is wrongly masking the entire 8 bits in the process
clearing PFM (bit7) field as well. Hence describe an appropriate
mask for vsel field and modify only those bits in the vsel
mask.

Source: http://www.ti.com/lit/ds/symlink/tps65218.pdf

Signed-off-by: Keerthy 
Fixes: 86db550b38 ("power: Add support for the TPS65218 PMIC")
---
 drivers/power/pmic/pmic_tps65218.c | 2 +-
 include/power/tps65218.h   | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/power/pmic/pmic_tps65218.c 
b/drivers/power/pmic/pmic_tps65218.c
index f32fa40..c5e768a 100644
--- a/drivers/power/pmic/pmic_tps65218.c
+++ b/drivers/power/pmic/pmic_tps65218.c
@@ -101,7 +101,7 @@ int tps65218_voltage_update(uchar dc_cntrl_reg, uchar 
volt_sel)
 
/* set voltage level */
if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, dc_cntrl_reg, volt_sel,
-  TPS65218_MASK_ALL_BITS))
+  TPS65218_DCDC_VSEL_MASK))
return 1;
 
/* set GO bit to initiate voltage transition */
diff --git a/include/power/tps65218.h b/include/power/tps65218.h
index 4d68faa..e3538e2 100644
--- a/include/power/tps65218.h
+++ b/include/power/tps65218.h
@@ -56,6 +56,8 @@ enum {
 
 #define TPS65218_MASK_ALL_BITS 0xFF
 
+#define TPS65218_DCDC_VSEL_MASK0x3F
+
 #define TPS65218_DCDC_VOLT_SEL_0950MV  0x0a
 #define TPS65218_DCDC_VOLT_SEL_1100MV  0x19
 #define TPS65218_DCDC_VOLT_SEL_1200MV  0x23
-- 
1.9.1

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Re: [U-Boot] [PATCH] edid: Fix gcc 7.1 warning

[Jernej Škrabec]

Hi,

Dne sreda, 24. maj 2017 ob 03:00:16 CEST je Tom Rini napisal(a):
> On Tue, May 23, 2017 at 11:05:30PM +0200, Jernej Skrabec wrote:
> > This commit fixes the warning produced by gcc 7.1.
> > 
> > Signed-off-by: Jernej Skrabec 
> 
> Reviewed-by: Tom Rini 
> 
> And I'm curious, where is your gcc-7.1 toolchain from, self built or
> something else?  Thanks!

It's from Arch Linux repository.

I'm sorry to say that there seems to be something wrong with either gcc 7.1 or 
bootp code. With OrangePi 2 board, bootp crashes and resets the board 
(ethernet cable is not connected). I didn't have time to investigate it 
further.

Best regards,
Jernej



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[U-Boot] Heads-up: Compilation error with arm-none-eabi-gcc version 7.1

[Kernel Hacker]

Hi,

I just upgraded my Arch Linux system to the latest arm-none-eabi-gcc 
version which is "7.1.0-1" (from 6.3.1-1). After I did this I ran into 
two issues. First, u-boot no longer links. I get several linker errors 
[1]. Secondly, if I build a Linux kernel v4.10 image with this compiler 
it won't boot. It hangs at "Starting kernel...". Reverting back to v6.3 
of gcc fixes both issues. Don't know if this is an issue with gcc or 
with the gcc package (from community. I did not build it myself) that is 
built for Arch Linux.


[1]

fs/built-in.o: In function `read_symbol':
/uboot/u-boot-marvell.git/fs/jffs2/mini_inflate.c:129: undefined 
reference to `pull_bit'

fs/built-in.o: In function `decompress_huffman':
/uboot/u-boot-marvell.git/fs/jffs2/mini_inflate.c:159: undefined 
reference to `pull_bits'
/uboot/u-boot-marvell.git/fs/jffs2/mini_inflate.c:170: undefined 
reference to `pull_bits'

fs/built-in.o: In function `init_code_tables':
/uboot/u-boot-marvell.git/fs/jffs2/mini_inflate.c:208: undefined 
reference to `cramfs_memset'
/uboot/u-boot-marvell.git/fs/jffs2/mini_inflate.c:209: undefined 
reference to `cramfs_memset'
/uboot/u-boot-marvell.git/fs/jffs2/mini_inflate.c:210: undefined 
reference to `cramfs_memset'

fs/built-in.o: In function `decompress_block':
/uboot/u-boot-marvell.git/fs/jffs2/mini_inflate.c:360: undefined 
reference to `pull_bit'
/uboot/u-boot-marvell.git/fs/jffs2/mini_inflate.c:361: undefined 
reference to `pull_bits'

fs/built-in.o: In function `decompress_none':
/uboot/u-boot-marvell.git/fs/jffs2/mini_inflate.c:115: undefined 
reference to `pull_bits'

fs/built-in.o: In function `decompress_dynamic':
/uboot/u-boot-marvell.git/fs/jffs2/mini_inflate.c:230: undefined 
reference to `pull_bits'
/uboot/u-boot-marvell.git/fs/jffs2/mini_inflate.c:231: undefined 
reference to `pull_bits'
/uboot/u-boot-marvell.git/fs/jffs2/mini_inflate.c:232: undefined 
reference to `pull_bits'
fs/built-in.o:/uboot/u-boot-marvell.git/fs/jffs2/mini_inflate.c:244: 
more undefined references to `pull_bits' follow

fs/built-in.o: In function `decompress_fixed':
/uboot/u-boot-marvell.git/fs/jffs2/mini_inflate.c:326: undefined 
reference to `cramfs_memset'
/uboot/u-boot-marvell.git/fs/jffs2/mini_inflate.c:327: undefined 
reference to `cramfs_memset'
/uboot/u-boot-marvell.git/fs/jffs2/mini_inflate.c:328: undefined 
reference to `cramfs_memset'
/uboot/u-boot-marvell.git/fs/jffs2/mini_inflate.c:329: undefined 
reference to `cramfs_memset'
/uboot/u-boot-marvell.git/fs/jffs2/mini_inflate.c:330: undefined 
reference to `cramfs_memset'
fs/built-in.o:/uboot/u-boot-marvell.git/fs/jffs2/mini_inflate.c:331: 
more undefined references to `cramfs_memset' follow
arm-none-eabi-ld.bfd: BFD (GNU Binutils) 2.28 assertion fail 
elf32-arm.c:9512
arm-none-eabi-ld.bfd: BFD (GNU Binutils) 2.28 assertion fail 
elf32-arm.c:9512
arm-none-eabi-ld.bfd: BFD (GNU Binutils) 2.28 assertion fail 
elf32-arm.c:9512

make: *** [Makefile:1207: u-boot] Error 1

/

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Re: [U-Boot] [PATCH 11/11] ARM: am437x-gp-evm-u-boot.dtsi: Enable nodes for USB device boot

[Lokesh Vutla]

On Tuesday 23 May 2017 05:25 PM, Vignesh R wrote:
> Enable USB nodes required to support RNDIS boot in SPL.
> 
> Signed-off-by: Vignesh R 
> ---
>  arch/arm/dts/am437x-gp-evm-u-boot.dtsi | 20 
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm/dts/am437x-gp-evm-u-boot.dtsi 
> b/arch/arm/dts/am437x-gp-evm-u-boot.dtsi
> index 885a9a92dbd3..a689cd68a593 100644
> --- a/arch/arm/dts/am437x-gp-evm-u-boot.dtsi
> +++ b/arch/arm/dts/am437x-gp-evm-u-boot.dtsi
> @@ -36,3 +36,23 @@
>  _sel {
>   u-boot,dm-pre-reloc;
>  };

Can you mark all the below node as "u-boot,dm-spl" instead of
u-boot,dm-pre-reloc?

Thanks and regards,
Lokesh

> +
> +_control_usb2phy1 {
> + u-boot,dm-pre-reloc;
> +};
> +
> + {
> + u-boot,dm-pre-reloc;
> +
> + phy@483a8000 {
> + u-boot,dm-pre-reloc;
> + };
> +};
> +
> +_1 {
> + u-boot,dm-pre-reloc;
> +
> + usb@4839 {
> + u-boot,dm-pre-reloc;
> + };
> +};
> 
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Re: [U-Boot] [PATCH 3/6] rockchip: evb-rk3328: set uart2 and sdmmc io routing

[Kever Yang]

Hi Simon,


On 05/20/2017 10:29 AM, Simon Glass wrote:

Hi Kever,

On 16 May 2017 at 21:44, Kever Yang  wrote:

In rk3328, some function pin may have more than one choice, and muxed
with more than one IO, for example, the UART2 controller IO,
TX and RX, have 3 choice(setting in com_iomux):
- M0 which mux with GPIO1A0/GPIO1A1
- M1 which mux with GPIO2A0/GPIO2A1
- usb2phy which mux with USB2.0 DP/DM pin.

We should set these IO routing in board file.

Signed-off-by: Kever Yang 
---

  board/rockchip/evb_rk3328/evb-rk3328.c | 12 
  1 file changed, 12 insertions(+)

diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c 
b/board/rockchip/evb_rk3328/evb-rk3328.c
index a7895cb..d9dc782 100644
--- a/board/rockchip/evb_rk3328/evb-rk3328.c
+++ b/board/rockchip/evb_rk3328/evb-rk3328.c
@@ -5,7 +5,10 @@
   */

  #include 
+#include 
+#include 
  #include 
+#include 
  #include 
  #include 

@@ -13,6 +16,15 @@ DECLARE_GLOBAL_DATA_PTR;

  int board_init(void)
  {
+#define GRF_BASE   0xff10
+   struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
+
+   /* uart2 select m1, sdcard select m1*/
+   rk_clrsetreg(>com_iomux,
+IOMUX_SEL_UART2_MASK | IOMUX_SEL_SDMMC_MASK,
+IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT |
+IOMUX_SEL_SDMMC_M1 << IOMUX_SEL_SDMMC_SHIFT);
+
 return 0;
  }

This needs to be done via a call to some sort of driver. The above
hack is OK in SPL but not in U-Boot proper.


Yes, SPL also needs this. I thinks here should be the right place
before there is a SPL for rk3328.


See my comments elsewhere about using a misc driver with an IOCTL
interface to do this sort of thing. Although here I wonder why you
cannot use pinctrl?


This is different from traditional pinctrl, kernel also still not have
final solution on this, see [0], and some people think it should be
done in boot loader.


Thanks,
- Kever
[0] 
http://lists.infradead.org/pipermail/linux-rockchip/2016-August/011209.html


Regards,
Simon




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[U-Boot] [PATCH v6 5/6] arm: socfpga: Move FPGA manager driver to FPGA driver

[tien . fong . chee]

From: Tien Fong Chee 

Move FPGA manager driver which is Gen5 specific code from arch/arm/
into FPGA driver at driver/fpga/. No functional change.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/Makefile   |  1 -
 arch/arm/mach-socfpga/fpga_manager.c | 78 
 drivers/fpga/socfpga_gen5.c  | 54 +
 3 files changed, 54 insertions(+), 79 deletions(-)
 delete mode 100644 arch/arm/mach-socfpga/fpga_manager.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 286bfef..824cd8e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -20,7 +20,6 @@ obj-y += reset_manager_gen5.o
 obj-y  += scan_manager.o
 obj-y  += system_manager_gen5.o
 obj-y  += wrap_pll_config.o
-obj-y  += fpga_manager.o
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
diff --git a/arch/arm/mach-socfpga/fpga_manager.c 
b/arch/arm/mach-socfpga/fpga_manager.c
deleted file mode 100644
index f909573..000
--- a/arch/arm/mach-socfpga/fpga_manager.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (C) 2012 Altera Corporation 
- * All rights reserved.
- *
- * This file contains only support functions used also by the SoCFPGA
- * platform code, the real meat is located in drivers/fpga/socfpga.c .
- *
- * SPDX-License-Identifier:BSD-3-Clause
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Timeout count */
-#define FPGA_TIMEOUT_CNT   0x100
-
-static struct socfpga_fpga_manager *fpgamgr_regs =
-   (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
-
-/* Check whether FPGA Init_Done signal is high */
-static int is_fpgamgr_initdone_high(void)
-{
-   unsigned long val;
-
-   val = readl(_regs->gpio_ext_porta);
-   return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
-}
-
-/* Get the FPGA mode */
-int fpgamgr_get_mode(void)
-{
-   unsigned long val;
-
-   val = readl(_regs->stat);
-   return val & FPGAMGRREGS_STAT_MODE_MASK;
-}
-
-/* Check whether FPGA is ready to be accessed */
-int fpgamgr_test_fpga_ready(void)
-{
-   /* Check for init done signal */
-   if (!is_fpgamgr_initdone_high())
-   return 0;
-
-   /* Check again to avoid false glitches */
-   if (!is_fpgamgr_initdone_high())
-   return 0;
-
-   if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
-   return 0;
-
-   return 1;
-}
-
-/* Poll until FPGA is ready to be accessed or timeout occurred */
-int fpgamgr_poll_fpga_ready(void)
-{
-   unsigned long i;
-
-   /* If FPGA is blank, wait till WD invoke warm reset */
-   for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
-   /* check for init done signal */
-   if (!is_fpgamgr_initdone_high())
-   continue;
-   /* check again to avoid false glitches */
-   if (!is_fpgamgr_initdone_high())
-   continue;
-   return 1;
-   }
-
-   return 0;
-}
diff --git a/drivers/fpga/socfpga_gen5.c b/drivers/fpga/socfpga_gen5.c
index 3dfb030..d8f222a 100644
--- a/drivers/fpga/socfpga_gen5.c
+++ b/drivers/fpga/socfpga_gen5.c
@@ -21,6 +21,60 @@ static struct socfpga_fpga_manager *fpgamgr_regs =
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
+/* Check whether FPGA Init_Done signal is high */
+static int is_fpgamgr_initdone_high(void)
+{
+   unsigned long val;
+
+   val = readl(_regs->gpio_ext_porta);
+   return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
+}
+
+/* Get the FPGA mode */
+int fpgamgr_get_mode(void)
+{
+   unsigned long val;
+
+   val = readl(_regs->stat);
+   return val & FPGAMGRREGS_STAT_MODE_MASK;
+}
+
+/* Check whether FPGA is ready to be accessed */
+int fpgamgr_test_fpga_ready(void)
+{
+   /* Check for init done signal */
+   if (!is_fpgamgr_initdone_high())
+   return 0;
+
+   /* Check again to avoid false glitches */
+   if (!is_fpgamgr_initdone_high())
+   return 0;
+
+   if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
+   return 0;
+
+   return 1;
+}
+
+/* Poll until FPGA is ready to be accessed or timeout occurred */
+int fpgamgr_poll_fpga_ready(void)
+{
+   unsigned long i;
+
+   /* If FPGA is blank, wait till WD invoke warm reset */
+   for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+   /* check for init done signal */
+   if (!is_fpgamgr_initdone_high())
+   continue;
+   /* check again to avoid false glitches */
+   if (!is_fpgamgr_initdone_high())
+   continue;
+   return 1;
+   }
+
+   return 0;
+}
+
 /* Set CD ratio */
 static void fpgamgr_set_cd_ratio(unsigned long ratio)
 {
-- 
2.2.0

[U-Boot] [PATCH v6 4/6] arm: socfpga: Enable FPGA driver build on SPL

[tien . fong . chee]

From: Tien Fong Chee 

Enable FPGA driver build for SPL because FPGA driver is needed for SPL
to configure and getting DDR up before loading U-boot into DDR and
booting from there.

Signed-off-by: Tien Fong Chee 
---
 drivers/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/Makefile b/drivers/Makefile
index 4a4b237..bb35c9a 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
 obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
 obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
 obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
+obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/
 endif
 
 ifdef CONFIG_TPL_BUILD
-- 
2.2.0

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[U-Boot] [PATCH v6 6/6] arm: socfpga: Add FPGA driver support for Arria 10

[tien . fong . chee]

From: Tien Fong Chee 

Add FPGA driver support for Arria 10.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/include/mach/fpga_manager.h  |   2 +
 .../include/mach/fpga_manager_arria10.h| 100 +
 drivers/fpga/Makefile  |   1 +
 drivers/fpga/socfpga_arria10.c | 479 +
 include/configs/socfpga_common.h   |   3 +-
 5 files changed, 583 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
 create mode 100644 drivers/fpga/socfpga_arria10.c

diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h 
b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
index b046c2c..a21c716 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
@@ -12,6 +12,8 @@
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
 #endif
 
 /* FPGA CD Ratio Value */
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
new file mode 100644
index 000..9cbf696
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2017 Intel Corporation 
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _FPGA_MANAGER_ARRIA10_H_
+#define _FPGA_MANAGER_ARRIA10_H_
+
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK  BIT(0)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK   BIT(2)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSKBIT(3)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSKBIT(4)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSKBIT(6)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK  BIT(8)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK   BIT(9)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSKBIT(10)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK   BIT(11)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSKBIT(12)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSKBIT(13)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK  BIT(16)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK  BIT(17)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK  BIT(18)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\
+   ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
+   ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
+   ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK   BIT(24)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSKBIT(25)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK  BIT(28)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSKBIT(29)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB  16
+
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK  BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK  BIT(1)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK  BIT(2)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK  BIT(8)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK   BIT(16)
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK   BIT(24)
+
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK   BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK   BIT(16)
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK  BIT(24)
+
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK  BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK  BIT(8)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK  0x0003
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB  16
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_fpga_manager {
+   u32  _pad_0x0_0x7[2];
+   u32  dclkcnt;
+   u32  dclkstat;
+   u32  gpo;
+   u32  gpi;
+   u32  misci;
+   u32  _pad_0x1c_0x2f[5];
+   u32  emr_data0;
+   u32  emr_data1;
+   u32  emr_data2;
+   u32  emr_data3;
+   u32  emr_data4;
+   u32  emr_data5;
+   u32  emr_valid;
+   u32  emr_en;
+   u32  jtag_config;
+   u32  jtag_status;
+   u32  jtag_kick;
+   u32  _pad_0x5c_0x5f;
+   u32  jtag_data_w;
+   u32  jtag_data_r;
+   u32  _pad_0x68_0x6f[2];
+   u32  imgcfg_ctrl_00;
+   u32 

[U-Boot] [PATCH v6 3/6] arm: socfpga: Enable FPGA driver on SPL

[tien . fong . chee]

From: Tien Fong Chee 

This patch is for enabling the FPGA driver support on SPL.

Signed-off-by: Tien Fong Chee 
---
 include/configs/socfpga_common.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index da7e4ad..e74e7eb 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -110,6 +110,7 @@
 #define CONFIG_FPGA
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_SOCFPGA
+#define CONFIG_SPL_FPGA_SUPPORT
 #define CONFIG_FPGA_COUNT  1
 #endif
 #endif
-- 
2.2.0

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[U-Boot] [PATCH v6 2/6] arm: socfpga: Restructure FPGA driver in the preparation to support A10

[tien . fong . chee]

From: Tien Fong Chee 

Move FPGA driver which is Gen5 specific code into Gen5 driver file
and keeping common FPGA driver intact. All the changes are still keeping
in driver/fpga/ and no functional change. Subsequent patch would move
FPGA manager driver from arch/arm into driver/fpga/.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/Makefile |   2 +-
 arch/arm/mach-socfpga/include/mach/fpga_manager.h  |  68 +-
 .../mach/{fpga_manager.h => fpga_manager_gen5.h}   |  69 +++---
 drivers/fpga/Makefile  |   1 +
 drivers/fpga/socfpga.c | 241 +
 drivers/fpga/{socfpga.c => socfpga_gen5.c} |  54 +
 6 files changed, 49 insertions(+), 386 deletions(-)
 copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => 
fpga_manager_gen5.h} (57%)
 copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (83%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 41b779c..286bfef 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -9,7 +9,6 @@
 
 obj-y  += board.o
 obj-y  += clock_manager.o
-obj-y  += fpga_manager.o
 obj-y  += misc.o
 obj-y  += reset_manager.o
 obj-y  += timer.o
@@ -21,6 +20,7 @@ obj-y += reset_manager_gen5.o
 obj-y  += scan_manager.o
 obj-y  += system_manager_gen5.o
 obj-y  += wrap_pll_config.o
+obj-y  += fpga_manager.o
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h 
b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
index a077e22..b046c2c 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 Altera Corporation 
+ * Copyright (C) 2012-2017 Altera Corporation 
  * All rights reserved.
  *
  * SPDX-License-Identifier:BSD-3-Clause
@@ -10,58 +10,9 @@
 
 #include 
 
-struct socfpga_fpga_manager {
-   /* FPGA Manager Module */
-   u32 stat;   /* 0x00 */
-   u32 ctrl;
-   u32 dclkcnt;
-   u32 dclkstat;
-   u32 gpo;/* 0x10 */
-   u32 gpi;
-   u32 misci;  /* 0x18 */
-   u32 _pad_0x1c_0x82c[517];
-
-   /* Configuration Monitor (MON) Registers */
-   u32 gpio_inten; /* 0x830 */
-   u32 gpio_intmask;
-   u32 gpio_inttype_level;
-   u32 gpio_int_polarity;
-   u32 gpio_intstatus; /* 0x840 */
-   u32 gpio_raw_intstatus;
-   u32 _pad_0x848;
-   u32 gpio_porta_eoi;
-   u32 gpio_ext_porta; /* 0x850 */
-   u32 _pad_0x854_0x85c[3];
-   u32 gpio_1s_sync;   /* 0x860 */
-   u32 _pad_0x864_0x868[2];
-   u32 gpio_ver_id_code;
-   u32 gpio_config_reg2;   /* 0x870 */
-   u32 gpio_config_reg1;
-};
-
-#define FPGAMGRREGS_STAT_MODE_MASK 0x7
-#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
-#define FPGAMGRREGS_STAT_MSEL_LSB  3
-
-#define FPGAMGRREGS_CTRL_CFGWDTH_MASK  0x200
-#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
-#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK  0x4
-#define FPGAMGRREGS_CTRL_NCE_MASK  0x2
-#define FPGAMGRREGS_CTRL_EN_MASK   0x1
-#define FPGAMGRREGS_CTRL_CDRATIO_LSB   6
-
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK0x8
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
-
-/* FPGA Mode */
-#define FPGAMGRREGS_MODE_FPGAOFF   0x0
-#define FPGAMGRREGS_MODE_RESETPHASE0x1
-#define FPGAMGRREGS_MODE_CFGPHASE  0x2
-#define FPGAMGRREGS_MODE_INITPHASE 0x3
-#define FPGAMGRREGS_MODE_USERMODE  0x4
-#define FPGAMGRREGS_MODE_UNKNOWN   0x5
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include 
+#endif
 
 /* FPGA CD Ratio Value */
 #define CDRATIO_x1 0x0
@@ -69,9 +20,14 @@ struct socfpga_fpga_manager {
 #define CDRATIO_x4 0x2
 #define CDRATIO_x8 0x3
 
-/* SoCFPGA support functions */
-int fpgamgr_test_fpga_ready(void);
-int fpgamgr_poll_fpga_ready(void);
+#ifndef __ASSEMBLY__
+
+/* Common prototypes */
 int fpgamgr_get_mode(void);
+int fpgamgr_poll_fpga_ready(void);
+void fpgamgr_program_write(const void *rbf_data, size_t rbf_size);
+int fpgamgr_test_fpga_ready(void);
+int fpgamgr_dclkcnt_set(unsigned long cnt);
 
+#endif /* __ASSEMBLY__ */
 #endif /* _FPGA_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h 
b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
similarity index 57%
copy from arch/arm/mach-socfpga/include/mach/fpga_manager.h
copy to 

[U-Boot] [PATCH v6 1/6] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset

[tien . fong . chee]

From: Tien Fong Chee 

Remove parameter from socfpga_bridges_reset(), and keeping this function
for single purpose which is just triggering reset on bridges.
socfpga_reset_deassert_bridges_handoff() can be called for releasing reset
on any bridges based on the bridge setting defined in fdt.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h | 2 +-
 arch/arm/mach-socfpga/reset_manager_arria10.c  | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
index 7922db8..b6d7f4f 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -17,7 +17,7 @@ int socfpga_reset_deassert_bridges_handoff(void);
 void socfpga_reset_assert_fpga_connected_peripherals(void);
 void socfpga_reset_deassert_osc1wd0(void);
 void socfpga_reset_uart(int assert);
-int socfpga_bridges_reset(int enable);
+int socfpga_bridges_reset(void);
 
 struct socfpga_reset_manager {
u32 stat;
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c 
b/arch/arm/mach-socfpga/reset_manager_arria10.c
index d8c858c..66f1ec2 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -318,13 +318,13 @@ void socfpga_per_reset_all(void)
 }
 
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-int socfpga_bridges_reset(int enable)
+int socfpga_bridges_reset(void)
 {
/* For SoCFPGA-VT, this is NOP. */
return 0;
 }
 #else
-int socfpga_bridges_reset(int enable)
+int socfpga_bridges_reset(void)
 {
int ret;
 
-- 
2.2.0

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[U-Boot] [PATCH v6 0/6] Add Intel Arria 10 SoC FPGA driver

[tien . fong . chee]

From: Tien Fong Chee 

This is the 6th version of patchset to adds support for Intel Arria 10 SoC FPGA
driver. This version mainly resolved comments from Dinh in [v5].
This series is working on top of u-boot-socfpga-next branch
http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/next.

[v5]: https://www.mail-archive.com/u-boot@lists.denx.de/msg250517.html

v5 -> v6 changes:
-
- Created separate patch for enabling FPGA driver support.

Patchset history

[v1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg247788.html
[v2]: https://www.mail-archive.com/u-boot@lists.denx.de/msg248541.html
[v3]: https://www.mail-archive.com/u-boot@lists.denx.de/msg249160.html
[v4]: https://www.mail-archive.com/u-boot@lists.denx.de/msg250149.html

Tien Fong Chee (6):
  arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset
  arm: socfpga: Restructure FPGA driver in the preparation to support
A10
  arm: socfpga: Enable FPGA driver on SPL
  arm: socfpga: Enable FPGA driver build on SPL
  arm: socfpga: Move FPGA manager driver to FPGA driver
  arm: socfpga: Add FPGA driver support for Arria 10

 arch/arm/mach-socfpga/Makefile |   1 -
 arch/arm/mach-socfpga/fpga_manager.c   |  78 
 arch/arm/mach-socfpga/include/mach/fpga_manager.h  |  70 +--
 .../include/mach/fpga_manager_arria10.h| 100 +
 .../mach/{fpga_manager.h => fpga_manager_gen5.h}   |  69 ++-
 .../include/mach/reset_manager_arria10.h   |   2 +-
 arch/arm/mach-socfpga/reset_manager_arria10.c  |   4 +-
 drivers/Makefile   |   1 +
 drivers/fpga/Makefile  |   2 +
 drivers/fpga/socfpga.c | 241 +--
 drivers/fpga/socfpga_arria10.c | 479 +
 drivers/fpga/{socfpga.c => socfpga_gen5.c} |  98 ++---
 include/configs/socfpga_common.h   |   4 +-
 13 files changed, 685 insertions(+), 464 deletions(-)
 delete mode 100644 arch/arm/mach-socfpga/fpga_manager.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
 copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => 
fpga_manager_gen5.h} (57%)
 create mode 100644 drivers/fpga/socfpga_arria10.c
 copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (85%)

-- 
2.2.0

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[U-Boot] [PATCH] nds32: mmc: Support ftsdc010 DM.

[Andes]

From: rick 

Support Andestech ftsdc010 SD/MMC device tree flow
on AG101P/AE3XX platforms.
Verification : boot linux kernel from sd card

NDS32 # mmc rescan
NDS32 # fatls mmc 0:1
13938796   boomimage-310y-ag101p.bin

1 file(s)

NDS32 # fatload mmc 0:1 0x60 boomimage-310y-ag101p.bin
reading boomimage-310y-ag101p.bin
13938796 bytes read in 17358 ms (784.2 KiB/s)
NDS32 # bootm 0x60
 Image Name:
 Created:  2017-05-23   1:58:24 UTC
 Image Type:   NDS32 Linux Kernel Image (uncompressed)
 Data Size:13938732 Bytes = 13.3 MiB
 Load Address: c000
 Entry Point:  c000
 Verifying Checksum ... OK
 Loading Kernel Image ... OK
Linux version 3.10.102-20420-g301b0f6 (rick@app09) (gcc version 4.9.3
(2016-07-06_nds32le-linux-glibc-v3_experimental) )#798
PREEMPT Tue May 23 09:57:59 CST 2017
CPU: NDS32 N13, AndesCore ID(wb), CPU_VER 0x0d0c003f(id 13, rev 12, cfg 63)
...
...
Signed-off-by: rick 
---
 arch/nds32/dts/ae3xx.dts|8 ++
 arch/nds32/dts/ag101p.dts   |8 ++
 board/AndesTech/adp-ae3xx/adp-ae3xx.c   |4 +-
 board/AndesTech/adp-ag101p/adp-ag101p.c |7 +-
 configs/adp-ae3xx_defconfig |5 ++
 configs/adp-ag101p_defconfig|5 ++
 drivers/mmc/Kconfig |   12 +++
 drivers/mmc/Makefile|1 +
 drivers/mmc/ftsdc010_mci.c  |  140 ---
 drivers/mmc/ftsdc010_mci.h  |   54 
 drivers/mmc/nds32_mmc.c |  139 ++
 include/configs/adp-ae3xx.h |1 -
 include/configs/adp-ag101p.h|1 -
 13 files changed, 344 insertions(+), 41 deletions(-)
 create mode 100644 drivers/mmc/ftsdc010_mci.h
 create mode 100644 drivers/mmc/nds32_mmc.c

diff --git a/arch/nds32/dts/ae3xx.dts b/arch/nds32/dts/ae3xx.dts
index 4221e4b..781eabc 100644
--- a/arch/nds32/dts/ae3xx.dts
+++ b/arch/nds32/dts/ae3xx.dts
@@ -62,6 +62,14 @@
interrupts = <25 4>;
};
 
+   mmc0: mmc@f0e0 {
+   compatible = "andestech,atsdc010";
+   clock-freq-min-max = <40 1>;
+   fifo-depth = <0x10>;
+   reg = <0xf0e0 0x1000>;
+   interrupts = <17 4>;
+   };
+
nor@0,0 {
compatible = "cfi-flash";
reg = <0x8800 0x1000>;
diff --git a/arch/nds32/dts/ag101p.dts b/arch/nds32/dts/ag101p.dts
index 99cde2f..dd2bf8f 100644
--- a/arch/nds32/dts/ag101p.dts
+++ b/arch/nds32/dts/ag101p.dts
@@ -60,4 +60,12 @@
reg = <0x9090 0x1000>;
interrupts = <25 4>;
};
+
+   mmc0: mmc@98e0 {
+   compatible = "andestech,atsdc010";
+   clock-freq-min-max = <40 3000>;
+   fifo-depth = <0x10>;
+   reg = <0x98e0 0x1000>;
+   interrupts = <5 4>;
+   };
 };
diff --git a/board/AndesTech/adp-ae3xx/adp-ae3xx.c 
b/board/AndesTech/adp-ae3xx/adp-ae3xx.c
index 98ed4d9..3903427 100644
--- a/board/AndesTech/adp-ae3xx/adp-ae3xx.c
+++ b/board/AndesTech/adp-ae3xx/adp-ae3xx.c
@@ -77,10 +77,8 @@ ulong board_flash_get_legacy(ulong base, int banknum, 
flash_info_t *info)
 
 int board_mmc_init(bd_t *bis)
 {
-#ifndef CONFIG_DM_MMC
-#ifdef CONFIG_FTSDC010
+#if defined(CONFIG_FTSDC010) && !defined(CONFIG_DM_MMC)
ftsdc010_mmc_init(0);
 #endif
-#endif
return 0;
 }
diff --git a/board/AndesTech/adp-ag101p/adp-ag101p.c 
b/board/AndesTech/adp-ag101p/adp-ag101p.c
index a462941..826ba14 100644
--- a/board/AndesTech/adp-ag101p/adp-ag101p.c
+++ b/board/AndesTech/adp-ag101p/adp-ag101p.c
@@ -20,7 +20,6 @@ DECLARE_GLOBAL_DATA_PTR;
 /*
  * Miscellaneous platform dependent initializations
  */
-
 int board_init(void)
 {
/*
@@ -30,7 +29,6 @@ int board_init(void)
printf("Board: %s\n" , CONFIG_SYS_BOARD);
gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P;
gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
-
return 0;
 }
 
@@ -39,11 +37,8 @@ int dram_init(void)
unsigned long sdram_base = PHYS_SDRAM_0;
unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
unsigned long actual_size;
-
actual_size = get_ram_size((void *)sdram_base, expected_size);
-
gd->ram_size = actual_size;
-
if (expected_size != actual_size) {
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
@@ -83,7 +78,7 @@ ulong board_flash_get_legacy(ulong base, int banknum, 
flash_info_t *info)
 
 int board_mmc_init(bd_t *bis)
 {
-#ifdef CONFIG_FTSDC010
+#if defined(CONFIG_FTSDC010) && !defined(CONFIG_DM_MMC)
ftsdc010_mmc_init(0);
 #endif
return 0;
diff --git a/configs/adp-ae3xx_defconfig b/configs/adp-ae3xx_defconfig
index 

[U-Boot] Uboot send pull request

[uboot]

 Hi Tom,

 Please pull the following patch from u-boot-nds32 into your tree.
 Thanks!

The following changes since commit be71a179bdd935336fb0bee8283be729144ac965:

  nds32: eth: Support ftmac100 DM. (2017-05-23 13:48:27 +0800)

are available in the git repository at:

  git://git.denx.de/u-boot-nds32.git master

for you to fetch changes up to be71a179bdd935336fb0bee8283be729144ac965:

  nds32: eth: Support ftmac100 DM. (2017-05-23 13:48:27 +0800)
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Re: [U-Boot] [PATCH v5 3/5] arm: socfpga: Enable FPGA driver on SPL

[Chee, Tien Fong]

On Sel, 2017-05-23 at 09:11 -0500, Dinh Nguyen wrote:
> 
> On 05/23/2017 01:25 AM, tien.fong.c...@intel.com wrote:
> > 
> > From: Tien Fong Chee 
> > 
> > Enable FPGA driver build for SPL. FPGA driver is needed for SPL
> > to configure and getting DDR up before loading U-boot into DDR and
> > booting from there.
> > 
> > Signed-off-by: Tien Fong Chee 
> > ---
> >  drivers/Makefile | 1 +
> >  include/configs/socfpga_common.h | 1 +
> >  2 files changed, 2 insertions(+)
> > 
> > diff --git a/drivers/Makefile b/drivers/Makefile
> > index 4a4b237..bb35c9a 100644
> > --- a/drivers/Makefile
> > +++ b/drivers/Makefile
> > @@ -47,6 +47,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
> >  obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
> >  obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
> >  obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
> > +obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/
> >  endif
> >  
> >  ifdef CONFIG_TPL_BUILD
> > diff --git a/include/configs/socfpga_common.h
> > b/include/configs/socfpga_common.h
> > index da7e4ad..e74e7eb 100644
> > --- a/include/configs/socfpga_common.h
> > +++ b/include/configs/socfpga_common.h
> > @@ -110,6 +110,7 @@
> >  #define CONFIG_FPGA
> >  #define CONFIG_FPGA_ALTERA
> >  #define CONFIG_FPGA_SOCFPGA
> > +#define CONFIG_SPL_FPGA_SUPPORT
> This change should be in a separate patch.
> 
> Dinh

Okay
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Re: [U-Boot] [PATCH V6 4/4] rockchip: rk3288: enable rockusb support on rk3288 based device

[Eddie Cai]

2017-05-24 8:44 GMT+08:00 Simon Glass :
> Hi Eddie,
>
> On 22 May 2017 at 00:43, Eddie Cai  wrote:
>> this patch enable rockusb support on rk3288 based device.
>>
>> Signed-off-by: Eddie Cai 
>>
>> Changes in v6:
>> -enable rockusb in defconfig
>>
>> Changes in v5:
>> -none
>>
>> Changes in v4:
>> -move to rk3288_common.h
>>
>> Changes in v3:
>> -move to defconfig
>>
>> ---
>>  configs/evb-rk3288_defconfig  | 11 +++
>>  configs/fennec-rk3288_defconfig   |  8 
>>  configs/firefly-rk3288_defconfig  |  8 
>>  configs/miqi-rk3288_defconfig |  8 
>>  configs/popmetal-rk3288_defconfig |  8 
>>  configs/tinker-rk3288_defconfig   |  8 
>>  include/configs/rk3288_common.h   |  7 ---
>>  7 files changed, 51 insertions(+), 7 deletions(-)
>
> Reviewed-by: Simon Glass 
>
> But can you use imply in the Kconfig to enable this for all rk2388 boards?
I found only SPL things use imply in the Kconfig. Will it be compiled
to SPL if i do so?
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Re: [U-Boot] [PATCH] rockchip: rk8xx: allocate priv structure for driver

[sjg]

On 5 May 2017 at 00:50, Kever Yang  wrote:
> The rk8xx_priv structure need to allocate for driver, or else
> it will cause data abort when CPU access it.
>
> This is a bug fix for below patch set:
> https://www.mail-archive.com/u-boot@lists.denx.de/msg247345.html
>
> Signed-off-by: Kever Yang 
> ---
>
>  drivers/power/pmic/rk8xx.c | 1 +
>  1 file changed, 1 insertion(+)
>

Acked-by: Simon Glass 

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Re: [U-Boot] [PATCH] edid: Fix gcc 7.1 warning

[Tom Rini]

On Tue, May 23, 2017 at 11:05:30PM +0200, Jernej Skrabec wrote:

> This commit fixes the warning produced by gcc 7.1.
> 
> Signed-off-by: Jernej Skrabec 

Reviewed-by: Tom Rini 

And I'm curious, where is your gcc-7.1 toolchain from, self built or
something else?  Thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] regulator: pwm: Fix handling of missing init voltage

[sjg]

Since priv->init_voltage is an unsigned integer it can never be
negative.  So the current code fails to detect a missing
'regulator-init-microvolt' property and instead misconfigures the
PWM device.  Fix this by making the relevant members of
'struct pwm_regulator_info' signed integers.

Signed-off-by: Mark Kettenis 
---

The current device tree for the Firefly-RK3399 does not have a
'regulator-init-microvolt' property for the 'vdd-log' regulator.
Without this fix U-Boot configures a voltage that is too low which
causes the Ethernet interface to drop almost all packets.

This is the same patch that I sent a couple of days ago, but was bounced
since I wasn't subscribed to the mailing list at that point.  Funily enough
the message did make it into the mailing list archive.  Resending to make
sure it does reach subscribers.

 drivers/power/regulator/pwm_regulator.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

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Re: [U-Boot] [PATCH v2 1/7] rockchip: rk3368: Add clock driver

[sjg]

On 15 May 2017 at 03:49, Andy Yan  wrote:
> Add driver to setup the various PLLs and peripheral
> clocks on the RK3368.
>
> Signed-off-by: Andy Yan 
> ---
>
> Changes in v2:
>  - fix typo in subject
>  - remove CRU base definition in cru head file
>  - Drop extra blank lines
>
>  arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 124 ++
>  drivers/clk/rockchip/Makefile   |   1 +
>  drivers/clk/rockchip/clk_rk3368.c   | 291 
> 
>  3 files changed, 416 insertions(+)
>  create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3368.h
>  create mode 100644 drivers/clk/rockchip/clk_rk3368.c

Reviewed-by: Simon Glass 

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Re: [U-Boot] [PATCH v2 3/7] rockchip: rk3368: Add core start-up code for RK3368

[sjg]

From: Andreas Färber 

The RK3368 is an octa-core Cortex-A53 SoC from Rockchip.
This adds basic support to chain-load U-Boot from Rockchip's
miniloader.

Signed-off-by: Andreas Färber 
Signed-off-by: Andy Yan 
Reviewed-by: Simon Glass 
---

Changes in v2:
- remove directly reference of GRF and CRU register base

 arch/arm/dts/rk3368.dtsi  | 1090 +
 arch/arm/mach-rockchip/Kconfig|   13 +
 arch/arm/mach-rockchip/Makefile   |1 +
 arch/arm/mach-rockchip/rk3368/Kconfig |6 +
 arch/arm/mach-rockchip/rk3368/Makefile|8 +
 arch/arm/mach-rockchip/rk3368/clk_rk3368.c|   32 +
 arch/arm/mach-rockchip/rk3368/rk3368.c|   86 ++
 arch/arm/mach-rockchip/rk3368/syscon_rk3368.c |   25 +
 include/configs/rk3368_common.h   |   49 ++
 include/dt-bindings/clock/rk3368-cru.h|  384 +
 10 files changed, 1694 insertions(+)
 create mode 100644 arch/arm/dts/rk3368.dtsi
 create mode 100644 arch/arm/mach-rockchip/rk3368/Kconfig
 create mode 100644 arch/arm/mach-rockchip/rk3368/Makefile
 create mode 100644 arch/arm/mach-rockchip/rk3368/clk_rk3368.c
 create mode 100644 arch/arm/mach-rockchip/rk3368/rk3368.c
 create mode 100644 arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
 create mode 100644 include/configs/rk3368_common.h
 create mode 100644 include/dt-bindings/clock/rk3368-cru.h

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Re: [U-Boot] [PATCH v3 4/4] rockchip: defconfig: puma-rk3399: enable RK3399 efuse driver

[sjg]

On 5 May 2017 at 11:21, Philipp Tomsich
 wrote:
> With everything in place (i.e. the new efuse driver, the clk-support
> for the non-secure efuse block, and the board-specific functions to
> derive 'serial#' from the cpu-id within the efuses), enable this in
> the RK3399-Q7 defconfig.
>
> Signed-off-by: Philipp Tomsich 
>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  configs/puma-rk3399_defconfig | 2 ++
>  1 file changed, 2 insertions(+)

Acked-by: Simon Glass 

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Re: [U-Boot] [PATCH v3 2/4] rockchip: board: puma_rk3399: add support for serial# and cpuid# via efuses

[sjg]

On 5 May 2017 at 11:21, Philipp Tomsich
 wrote:
> With our efuse driver for the RK3399 ready, we can add the
> board-specific code that consumes the cpuid from the efuse block and
> postprocesses it into the system serial (using the same CRC32 based
> derivation as in Linux).
>
> We expose the cpuid via two distinct environment variables:
>serial# - the serial number, as derived in Linux
>cpuid#  - the raw 16 byte CPU id field from the fuse block
>
> Signed-off-by: Philipp Tomsich 
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  board/theobroma-systems/puma_rk3399/puma-rk3399.c | 79 
> +++
>  include/configs/puma_rk3399.h |  6 ++
>  2 files changed, 85 insertions(+)

Acked-by: Simon Glass 

But don't you want to use the same mechanism to make sure you get the
right misc driver?

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Re: [U-Boot] [PATCH 2/8] rockchip: dts: rk3328: add ehci and ohci node and enable host0 port

[sjg]

On 17 May 2017 at 04:21, Meng Dongyang  wrote:

Commit message?

> Signed-off-by: Meng Dongyang 
> ---
>  arch/arm/dts/rk3328-evb.dts |  8 
>  arch/arm/dts/rk3328.dtsi| 14 ++
>  2 files changed, 22 insertions(+)

Reviewed-by: Simon Glass 

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Re: [U-Boot] [PATCH v2 2/7] rockchip: rk3368: Add pinctrl driver

[sjg]

On 15 May 2017 at 03:50, Andy Yan  wrote:
> Add driver to support iomux setup for the most commonly
> used peripherals on rk3368.
>
> Signed-off-by: Andy Yan 
> ---
>
> Changes in v2:
> - remove GRF base definition in cru head file
> - remove unused function
>
>  arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 440 
> 
>  drivers/pinctrl/Kconfig |  10 +
>  drivers/pinctrl/rockchip/Makefile   |   1 +
>  drivers/pinctrl/rockchip/pinctrl_rk3368.c   | 149 
>  4 files changed, 600 insertions(+)
>  create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>  create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3368.c
>

Reviewed-by: Simon Glass 

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Re: [U-Boot] [PATCH 5/8] rockchip: dts: rk3328: support and enable xhci

[sjg]

On 17 May 2017 at 04:25, Meng Dongyang  wrote:

Commit message?

> Signed-off-by: Meng Dongyang 
> ---
>  arch/arm/dts/rk3328-evb.dts |  5 +
>  arch/arm/dts/rk3328.dtsi| 11 +++
>  2 files changed, 16 insertions(+)
>

Reviewed-by: Simon Glass 

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Re: [U-Boot] [PATCH v2 5/7] rockchip: rk3368: add Sheep board

[sjg]

Hi Simon:


On 2017年05月17日 09:38, Simon Glass wrote:
> On 15 May 2017 at 03:53, Andy Yan  wrote:
>> Sheep board is designed by Rockchip as a EVB for rk3368.
>> Currently it is able to boot a linux kernel and system
>> to console with the miniloader run as fist level loader.
>>
>> Reviewed-by: Simon Glass 
>> Signed-off-by: Andy Yan 
>> ---
>>
>> Changes in v2:
>> - add a README to describe how to boot the board
>>
>>   arch/arm/dts/Makefile  |   1 +
>>   arch/arm/dts/rk3368-sheep.dts  | 283 
>> +
>>   arch/arm/mach-rockchip/rk3368/Kconfig  |  11 ++
>>   board/rockchip/sheep_rk3368/Kconfig|  15 ++
>>   board/rockchip/sheep_rk3368/MAINTAINERS|   6 +
>>   board/rockchip/sheep_rk3368/Makefile   |   7 +
>>   board/rockchip/sheep_rk3368/README |  44 +
>>   board/rockchip/sheep_rk3368/sheep_rk3368.c |  37 
>>   configs/sheep-rk3368_defconfig |  28 +++
>>   include/configs/sheep_rk3368.h |  21 +++
>>   10 files changed, 453 insertions(+)
>>   create mode 100644 arch/arm/dts/rk3368-sheep.dts
>>   create mode 100644 board/rockchip/sheep_rk3368/Kconfig
>>   create mode 100644 board/rockchip/sheep_rk3368/MAINTAINERS
>>   create mode 100644 board/rockchip/sheep_rk3368/Makefile
>>   create mode 100644 board/rockchip/sheep_rk3368/README
>>   create mode 100644 board/rockchip/sheep_rk3368/sheep_rk3368.c
>>   create mode 100644 configs/sheep-rk3368_defconfig
>>   create mode 100644 include/configs/sheep_rk3368.h
>>
> Can you also please add the board to README.rockchip with a link to
> the README file.


  Okay, I will do it in next version.
>
>



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Re: [U-Boot] [PATCH v2 1/3] rockchip: rk3036: clean mask definition for cru reg

[sjg]

On 15 May 2017 at 06:52, Kever Yang  wrote:
> Embeded the shift in mask MACRO definition in cru header file
> and clock driver.
>
> Signed-off-by: Kever Yang 
> ---
>
> Changes in v2:
> - split into two patches
>
>  arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 70 +++---
>  drivers/clk/rockchip/clk_rk3036.c   | 79 
> +++--
>  2 files changed, 69 insertions(+), 80 deletions(-)
>

Reviewed-by: Simon Glass 

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Re: [U-Boot] [PATCH] power: rk808: fix ldo register offset

[sjg]

On 6 May 2017 at 13:21, Heiko Stuebner  wrote:
> Till now get_ldo_reg did a return _ldo[num - 1]; to return
> the ldo register offset but didn't take into account that its
> calling functions already created the ldo as ldo = dev->driver_data - 1.
>
> This resulted in the setting for ldo8 writing to the register of ldo7
> and so on. So fix this and get the correct ldo register data.
>
> Signed-off-by: Heiko Stuebner 
> ---
>  drivers/power/regulator/rk8xx.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>

Acked-by: Simon Glass 

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Re: [U-Boot] [PATCH v2 7/7] rockchip: rk3368: Add PX5 Evaluation board

[sjg]

PX5 EVB is designed by Rockchip for automotive field
with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS
HDMI video input/output interface, audio codec ES8396,
WIFI / BT (on RTL8723BS), Gsensor BMA250E and light
sensor STK3410.

Signed-off-by: Andy Yan 
Reviewed-by: Simon Glass 
---

Changes in v2:
- fix rebase Conflicts

 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/rk3368-px5-evb.dts   | 319 ++
 arch/arm/mach-rockchip/rk3368/Kconfig |  10 ++
 board/rockchip/evb_px5/Kconfig|  15 ++
 board/rockchip/evb_px5/MAINTAINERS|   6 +
 board/rockchip/evb_px5/Makefile   |   7 +
 board/rockchip/evb_px5/README |   1 +
 board/rockchip/evb_px5/evb-px5.c  |  51 ++
 configs/evb-px5_defconfig |  30 
 include/configs/evb_px5.h |  17 ++
 10 files changed, 457 insertions(+)
 create mode 100644 arch/arm/dts/rk3368-px5-evb.dts
 create mode 100644 board/rockchip/evb_px5/Kconfig
 create mode 100644 board/rockchip/evb_px5/MAINTAINERS
 create mode 100644 board/rockchip/evb_px5/Makefile
 create mode 100644 board/rockchip/evb_px5/README
 create mode 100644 board/rockchip/evb_px5/evb-px5.c
 create mode 100644 configs/evb-px5_defconfig
 create mode 100644 include/configs/evb_px5.h

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Re: [U-Boot] [PATCH v2 6/7] rockchip: rk3368: Add initial support for RK3368 based GeekBox

[sjg]

On 15 May 2017 at 03:54, Andy Yan  wrote:
> From: Andreas Färber 
>
> The GeekBox is a TV box from GeekBuying, based on an MXM3 module.
> The module can be used with base boards such as the GeekBox Landingship.
> This adds basic support to chain-load U-Boot from Rockchip's miniloader.
>
> Signed-off-by: Andreas Färber 
> Signed-off-by: Andy Yan 
> ---
>
> Changes in v2: None
>
>  arch/arm/dts/Makefile |   1 +
>  arch/arm/dts/rk3368-geekbox.dts   | 319 
> ++
>  arch/arm/mach-rockchip/rk3368/Kconfig |   5 +
>  board/geekbuying/geekbox/Kconfig  |  15 ++
>  board/geekbuying/geekbox/MAINTAINERS  |   6 +
>  board/geekbuying/geekbox/Makefile |   7 +
>  board/geekbuying/geekbox/README   |   1 +
>  board/geekbuying/geekbox/geekbox.c|  28 +++
>  configs/geekbox_defconfig |  22 +++
>  include/configs/geekbox.h |  17 ++
>  10 files changed, 421 insertions(+)
>  create mode 100644 arch/arm/dts/rk3368-geekbox.dts
>  create mode 100644 board/geekbuying/geekbox/Kconfig
>  create mode 100644 board/geekbuying/geekbox/MAINTAINERS
>  create mode 100644 board/geekbuying/geekbox/Makefile
>  create mode 100644 board/geekbuying/geekbox/README
>  create mode 100644 board/geekbuying/geekbox/geekbox.c
>  create mode 100644 configs/geekbox_defconfig
>  create mode 100644 include/configs/geekbox.h
>

Reviewed-by: Simon Glass 

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Re: [U-Boot] [PATCH] rockchip: board: puma_rk3399: build FIT image via u-boot.itb

[sjg]

On 5 May 2017 at 11:22, Philipp Tomsich
 wrote:

Commit message?

> Signed-off-by: Philipp Tomsich 
> ---
>
>  board/theobroma-systems/puma_rk3399/README | 5 ++---
>  configs/puma-rk3399_defconfig  | 1 +
>  2 files changed, 3 insertions(+), 3 deletions(-)
>

Acked-by: Simon Glass 

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Re: [U-Boot] [PATCH 1/8] configs: rk3328: add support for usb and config ehci and ohci driver

[sjg]

On 17 May 2017 at 04:21, Meng Dongyang  wrote:
> Add defconfig for usb and ehci and ohci controller, config maximal
> number of ports of the root hub for ohci driver.
>
> Signed-off-by: Meng Dongyang 
> ---
>  configs/evb-rk3328_defconfig| 8 
>  include/configs/rk3328_common.h | 3 +++
>  2 files changed, 11 insertions(+)

Reviewed-by: Simon Glass 

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Re: [U-Boot] [PATCH v3 3/4] rockchip: board: puma_rk3399: derive ethaddr from cpuid

[sjg]

From: Klaus Goger 

Generate a MAC address based on the cpuid available in the efuse
block: Use the first 6 byte of the cpuid's SHA256 hash and set the
locally administered bits. Also ensure that the multicast bit is
cleared.

The MAC address is only generated and set if there is no ethaddr
present in the saved environment.

Signed-off-by: Klaus Goger 
Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 

---

Changes in v3:
- uses uclass_get_device_by_driver() to ensure we don't pick up the wrong
  misc-device

Changes in v2:
- added derivation of ethaddr from cpuid

 board/theobroma-systems/puma_rk3399/puma-rk3399.c | 43 +--
 1 file changed, 41 insertions(+), 2 deletions(-)

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Re: [U-Boot] [PATCH v3 1/4] rockchip: efuse: add (misc) driver for RK3399 non-secure efuse block

[sjg]

This adds a simple driver for reading the efuse block of the RK3399.
It should be easy enough to add drivers for other devices (e.g. the
RK3328, RK3368, etc.) by passing the device details via driver_data.

Unlike the kernel driver (using the nvmem subsystem), we don't expose
the efuse as multiple named cells, but rather as a linear memory that
can be read using misc_read(...).

The primary use case (as of today) is the generation of a 'serial#'
(and a 'cpuid#') environment variable for the RK3399-Q7 (Puma)
system-on-module.

Note that this adds a debug-only (i.e. only if DEBUG is defined)
command 'rk3399_dump_efuses' that dumps the efuse block's content.
N.B.: The name 'rk3399_dump_efuses' was intentionally chosen to
  include a SoC-name (together with a comment in the function) to
  remind whoever adds support for additional SoCs that this
  function currently makes assumptions regarding the size of the
  fuse-box based on the RK3399. The hope is that the function is
  adjusted to reflect any changes resulting from generalising the
  driver for multiple SoCs and is then renamed.

Signed-off-by: Philipp Tomsich 

Reviewed-by: Simon Glass 

---

Changes in v3:
- uses uclass_get_device_by_driver() to ensure we don't pick up the wrong
  misc-device

Changes in v2: None

 drivers/misc/Kconfig  |  14 
 drivers/misc/Makefile |   1 +
 drivers/misc/rockchip-efuse.c | 162 ++
 3 files changed, 177 insertions(+)
 create mode 100644 drivers/misc/rockchip-efuse.c

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Re: [U-Boot] [PATCH v2 2/3] rockchip: clock: rk3036: some fix according TRM

[sjg]

On 15 May 2017 at 06:52, Kever Yang  wrote:
> - hclk/pclk_div range　should use '<=' instead of '<'
> - use GPLL for pd_bus clock source
> - pd_bus HCLK/PCLK clock rate should not bigger than ACLK
>
> Signed-off-by: Kever Yang 
> ---
>
> Changes in v2: None
>
>  arch/arm/include/asm/arch-rockchip/cru_rk3036.h |  6 +++---
>  drivers/clk/rockchip/clk_rk3036.c   | 18 +-
>  2 files changed, 12 insertions(+), 12 deletions(-)

Reviewed-by: Simon Glass 

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Re: [U-Boot] [PATCH] defconfig: firefly-rk3399: fix pinctrl config option

[sjg]

On 3 May 2017 at 17:29, Heiko Stuebner  wrote:
>
> The option is named PINCTRL_ROCKCHIP_RK3399 not ROCKCHIP_RK3399_PINCTRL.
> Set the correct option.
>
> Signed-off-by: Heiko Stuebner 
> ---
>  configs/firefly-rk3399_defconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Acked-by: Simon Glass 

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Re: [U-Boot] [PATCH v2 3/3] rockchip: rk3036: clean mask definition for grf reg

[sjg]

On 15 May 2017 at 06:52, Kever Yang  wrote:
> U-Boot prefer to use MASKs with SHIFT embeded, clean the Macro
> definition in grf header file and pinctrl driver.
>
> Signed-off-by: Kever Yang 
> ---
>
> Changes in v2:
> - add grf code clean
>
>  arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 133 
> 
>  drivers/pinctrl/rockchip/pinctrl_rk3036.c   |  44 +++-
>  2 files changed, 82 insertions(+), 95 deletions(-)
>

Reviewed-by: Simon Glass 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [PATCH v2 4/7] rockchip: rk3368: Add sysreset driver

[sjg]

Add sysreset driver to reset rk3368 SOC.

Signed-off-by: Andy Yan 
Reviewed-by: Simon Glass 
---

Changes in v2:
 - slect soft reset source before reset

 drivers/sysreset/Makefile  |  1 +
 drivers/sysreset/sysreset_rk3368.c | 62 ++
 2 files changed, 63 insertions(+)
 create mode 100644 drivers/sysreset/sysreset_rk3368.c

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [PATCH] rockchip; rk3399: disable SRAM security region

[sjg]

On 4 May 2017 at 21:01, Kever Yang  wrote:
> Some host like SD and eMMC may use DMA to transter data to SRAM,
> set memory to non-secure to make sure the address can be accessed.
>
> The security of SRAM in OS suppose to initialized in ATF bl31, and
> the SPL is before the bl31.
>
> Signed-off-by: Kever Yang 
> ---
>
>  arch/arm/mach-rockchip/rk3399-board-spl.c | 8 +---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>

Acked-by: Simon Glass 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [PATCH 3/8] configs: rk3328: config xhci controller

[sjg]

On 17 May 2017 at 04:21, Meng Dongyang  wrote:
> Add config of max root ports and add config to enable xhci
> controller.
>
> Signed-off-by: Meng Dongyang 
> ---
>  configs/evb-rk3328_defconfig| 3 +++
>  include/configs/rk3328_common.h | 3 +++
>  2 files changed, 6 insertions(+)

Reviewed-by: Simon Glass 

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Re: [U-Boot] [PATCH v2 1/2] rockchip: Add basic support for phyCORE-RK3288 SoM based carrier board

[Simon Glass]

Hi Wadim,

On 15 May 2017 at 08:19, Wadim Egorov  wrote:
> The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC.
> The module can be connected to different carrier boards.
> It can be also equipped with different RAM, SPI flash and eMMC variants.
> The Rapid Development Kit option is using the following setup:
>
>   - 1 GB DDR3 RAM (2 Banks)
>   - 1x 4 KB EEPROM
>   - DP83867 Gigabit Ethernet PHY
>   - 16 MB SPI Flash
>   - 4 GB eMMC Flash
>
> Add basic support for the PCM-947 carrier board, a RK3288 based development
> board made by PHYTEC. This board works in a combination with
> the phyCORE-RK3288 System on Module.
>
> Signed-off-by: Wadim Egorov 
> Reviewed-by: Simon Glass 
> ---
> Changes in v2:
> - Move phycore initialization to an own function
> - Use of_machine_is_compatible() instead of #ifdef
> - Drop board_boot_order() and use spl_boot_device()
> - Added Reviewed-by: Simon Glass 
>
> ---
>  arch/arm/dts/Makefile|   1 +
>  arch/arm/dts/rk3288-phycore-rdk.dts  | 294 
>  arch/arm/dts/rk3288-phycore-som.dtsi | 503 
> +++
>  arch/arm/mach-rockchip/rk3288-board-spl.c|  37 ++
>  arch/arm/mach-rockchip/rk3288/Kconfig|  10 +
>  board/phytec/phycore_rk3288/Kconfig  |  15 +
>  board/phytec/phycore_rk3288/MAINTAINERS  |   6 +
>  board/phytec/phycore_rk3288/Makefile |   8 +
>  board/phytec/phycore_rk3288/phycore-rk3288.c |   8 +
>  configs/phycore-rk3288_defconfig |  69 
>  include/configs/phycore_rk3288.h |  23 ++
>  11 files changed, 974 insertions(+)
>  create mode 100644 arch/arm/dts/rk3288-phycore-rdk.dts
>  create mode 100644 arch/arm/dts/rk3288-phycore-som.dtsi
>  create mode 100644 board/phytec/phycore_rk3288/Kconfig
>  create mode 100644 board/phytec/phycore_rk3288/MAINTAINERS
>  create mode 100644 board/phytec/phycore_rk3288/Makefile
>  create mode 100644 board/phytec/phycore_rk3288/phycore-rk3288.c
>  create mode 100644 configs/phycore-rk3288_defconfig
>  create mode 100644 include/configs/phycore_rk3288.h

This unfortunately causes build errors on various rockchip boards.

Try 'buildman rockchip' to see it.

Please see below.

[...]

> diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c 
> b/arch/arm/mach-rockchip/rk3288-board-spl.c
> index 74f3379..724dcb4 100644
> --- a/arch/arm/mach-rockchip/rk3288-board-spl.c
> +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
> @@ -8,6 +8,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -25,6 +26,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> @@ -157,6 +159,38 @@ static int configure_emmc(struct udevice *pinctrl)
>  }
>  #endif
>
> +void phycore_init(void)
> +{
> +   struct udevice *dev;
> +   uint reg;
> +   int ret;
> +
> +   ret = uclass_get_device(UCLASS_I2C, 0, );
> +   if (ret) {
> +   debug("I2C init failed: %d\n", ret);
> +   return;
> +   }
> +
> +   ret = i2c_get_chip(dev, 0x1c, 1, );

We should not be hard-coding the bus address here.

See veyron_init() for an example of another way to do this.

> +   if (ret) {
> +   debug("Cannot find RK818: %d\n", ret);
> +   return;
> +   }
> +
> +   reg = dm_i2c_reg_read(dev, REG_USB_CTRL);
> +
> +   /*
> +* Increase USB input current selection to 2A and close charger
> +* when usb lower then 3.4V.
> +*/
> +   reg |= 0x77;
> +   ret = dm_i2c_reg_write(dev, REG_USB_CTRL, reg);

Here you are hacking registers in the PMIC. This should go in the PMIC
driver. See rk8xx_spl_configure_buck() for how to do this in SPL
without bringing in the whole regulator framework.

> +   if (ret) {
> +   debug("Unable to set RK818 REG_USB_CTRL: %d\n", ret);
> +   return;
> +   }
> +}
> +

Regards,
Simon
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Re: [U-Boot] [PATCH] buildman: Fix bloat option when 'new' only drops functions

[Simon Glass]

On 22 May 2017 at 11:48, Tom Rini  wrote:
> In the case where a new build only decreases sizes and does not increase
> any size we still want to report what functions have been dropped when
> doing a bloat comparison.
>
> Cc: Simon Glass 
> Signed-off-by: Tom Rini 
> ---
> This is important when doing Kconfig migrations and a given target has
> only decreased in size, we want to know what was dropped so we can see
> what needs to be re-enabled.
> ---
>  tools/buildman/builder.py | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH] rockchip: dts: rk3328: add aliases for mmc controller

[Simon Glass]

Hi,

On 23 May 2017 at 16:18, Andreas Färber  wrote:
> Hi Heiko,
>
> Am 23.05.2017 um 23:27 schrieb Heiko Stuebner:
>> Am Dienstag, 23. Mai 2017, 17:14:19 CEST schrieb Tom Rini:
>>> On Tue, May 23, 2017 at 11:03:23PM +0200, Mark Kettenis wrote:
> From: Heiko Stuebner 
> Date: Tue, 23 May 2017 22:29:33 +0200
>
> Hi Kever, Tom,
>
> Am Dienstag, 23. Mai 2017, 14:32:44 CEST schrieb Kever Yang:
>>  This is not from kernel, seems the kernel mmc driver does not
>> support aliases now,
>>
>> thought I hope they both support the aliases for ordering.
>
> there was a lengthy discussion about the pros and cons of ordering
> mmc devices last year [0].
>
> With the outcome that explicit ordering via aliases is not desired
> and the argument being that mmc devices are not so different from
> usb storage or scsi/sata devices whose ordering is random all the time.

 Aren't you intepreting the outcome of that discussion a bit too
 broadly tough?  That discussion seems to reject an explicit ordering
 of mmc device names in the Linux kernel, mainly because better
 mechanisms exist to refer to a particular device than its device
 name/number.  But that doesn't preclude having a meaningful set of
 aliases for certain boards if there is some sort of canonical boot
 order or if devices are actually numbered on a board?

 In OpenFirmware the primary purpose of these aliases is to specify
 which device to boot from.
>>
>> readding the lkml-link for the above:
>> [0] https://lkml.org/lkml/2016/4/29/621
>>
>>
>> As for that being to broad, wasn't that why Tom suggested moving that
>> to a -u-boot.dtsi file, because while generally not desired, it may
>> benefit uboot to get some sane boot order / type marks (emmc, sd-card),
>> but doesn't influence the core devicetree files that should ideally be
>> synced from the kernel or wherever?
>
> I think you're mixing three very distinct topics here:
> a) Whether Linux drivers should use aliases for ordering.
> b) Whether to add aliases in the DT.
> c) Sync'ing .dts files from Linux vs. local changes.
>
> I don't see what's wrong with b) as it is useful as a shorthand for
> access to a particular node, e.g. for U-Boot's fdt commands.
>
> Tom's point is that if a certain change is not in the Linux .dts and is
> needed for U-Boot, it should go into a U-Boot specific .dtsi file, so
> that the change doesn't get overwritten with the next .dts update from
> Linux.
> In the UEFI boot path we rely on a recent upstream-compatible DT being
> provided by U-Boot if none is installed by the OS in a way U-Boot can
> load, so the .dts will need to be re-sync'ed later on even if it doesn't
> affect U-Boot drivers. Therefore the commit messages also need to
> indicate where the .dts comes from, to avoid regressions on re-sync from
> different trees.

Further to that, I think U-Boot needs the aliases because we refer to
devices by number.

At a future date if U-Boot moves away from this to named devices, we
can revisit it.

But so far as I can tell, without the aliases, U-Boot cannot operate
in a reliable, repeatable manner.

Regards,
Simon
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Re: [U-Boot] [PATCH v2 3/3] usb: host: xhci-dwc3: Add generic PHY support

[Simon Glass]

On 22 May 2017 at 01:42,   wrote:
> From: Patrice Chotard 
>
> Add support of generic PHY framework support
>
> Signed-off-by: Patrice Chotard 
> ---
>
> v2: _ none
>
>  drivers/usb/host/xhci-dwc3.c | 32 
>  1 file changed, 32 insertions(+)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 00/26] dm: tegra: Move nyan-big to livetree

[Simon Glass]

Hi Tom,

On 22 May 2017 at 16:15, Tom Rini  wrote:
> On Fri, May 19, 2017 at 08:30:43AM -0600, Simon Glass wrote:
>> This moves an entire board to use a live device tree as an example of the
>> impact.
>>
>> Nyan-big was chosen because I can easily and boot U-Boot without any
>> media swapping, etc.
>>
>> Total code size impact on this board is approximately 9KB on U-Boot and
>> 64 bytes on SPL:
>>
>> 27: dm: tegra: nyan-big: Move to livetree
>>arm: (for 1/1 boards) all +9264.0 bss -16.0 data +44.0 rodata +92.0
>>   spl/u-boot-spl:all +326.0 spl/u-boot-spl:rodata +262.0
>>   spl/u-boot-spl:text +64.0 text +9144.0
>>
>> Tegra does not use Thumb2, which would likely reduce the code size by about
>> 25%, indicating a code-size impact of perhaps 7KB.
>
> So, did your buildman output get messed up in the copy/paste?  I see
> both of the numbers you're saying, but it's all vs u-boot-spl.  The 64
> bytes in SPL sounds good.

I think this is right. See 'text +9144.0' which means 9KB of extra in
ARM (not Thumb).

>
>> I have not yet collected reliable detailed timing information. I will do
>> that with the next version of this series, after comments are received.
>> I expect that building the live tree will take a little time, and that
>> using it will be very slightly faster.
>
> I assume that you're in the process of rectifying this with the
> bootstage patches you posted but FWIW I still use
> http://elinux.org/Grabserial as my first weapon-of-choice in these kinds
> of things.

Fair enough, but it's hard to measure down to milliseconds isn't it?
Also, outputting text affects the timing.

Yes I have completed the timing. Sneak preview...the times above are
times to start up driver model at each stage, in microseconds:

Boot time is affected slightly. For nyan-big the times with flat tree are:

 2,108  dm_r
 7,924  dm_spl
   120,724  dm_f
   171,816  lcd

With the livetree:

   721  dm_r
 3,764  of_live
 7,990  dm_spl
   120,736  dm_f
   168,215  lcd

As expected the spl and pre-relocation times are not affected. In the
post-relocation case, the live tree must be built, which here takes about
3.8ms. Driver-model device creation takes a bit of 1ms less time with the
livetree, so all up the cost is about 2.4ms. After DM init there appears
to be a slight reduction in the time taken to set up devices (from 327ms
to 319ms) so overall the live tree does not appear to be any slower. This
is because pre-parsing the device tree makes reading it later faster.

Regards,
Simon
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Re: [U-Boot] [PATCH v2 2/3] usb: host: xhci-dwc3: Add dual role mode support from DT

[Simon Glass]

On 22 May 2017 at 01:42,   wrote:
> From: Patrice Chotard 
>
> DWC3 dual role mode is selected using DT "dr_mode"
> property. If not found, DWC3 controller is configured
> in HOST mode by default
>
> Signed-off-by: Patrice Chotard 
> ---
>
> v2: _ none
>
>  drivers/usb/host/xhci-dwc3.c | 9 +
>  1 file changed, 9 insertions(+)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH v2 1/3] usb: host: xhci-dwc3: Convert driver to DM

[Simon Glass]

On 22 May 2017 at 01:42,   wrote:
> From: Patrice Chotard 
>
> Add Driver Model support with use of generic DT
> compatible string "snps,dwc3"
>
> Signed-off-by: Patrice Chotard 
> ---
>
> v2: _ use dev_get_addr() and removed useless piece of code
>
>  drivers/usb/host/xhci-dwc3.c | 50 
> 
>  1 file changed, 50 insertions(+)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH V6 4/4] rockchip: rk3288: enable rockusb support on rk3288 based device

[Simon Glass]

Hi Eddie,

On 22 May 2017 at 00:43, Eddie Cai  wrote:
> this patch enable rockusb support on rk3288 based device.
>
> Signed-off-by: Eddie Cai 
>
> Changes in v6:
> -enable rockusb in defconfig
>
> Changes in v5:
> -none
>
> Changes in v4:
> -move to rk3288_common.h
>
> Changes in v3:
> -move to defconfig
>
> ---
>  configs/evb-rk3288_defconfig  | 11 +++
>  configs/fennec-rk3288_defconfig   |  8 
>  configs/firefly-rk3288_defconfig  |  8 
>  configs/miqi-rk3288_defconfig |  8 
>  configs/popmetal-rk3288_defconfig |  8 
>  configs/tinker-rk3288_defconfig   |  8 
>  include/configs/rk3288_common.h   |  7 ---
>  7 files changed, 51 insertions(+), 7 deletions(-)

Reviewed-by: Simon Glass 

But can you use imply in the Kconfig to enable this for all rk2388 boards?
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Re: [U-Boot] [GIT PULL] u-boot-sh/rmobile

[Tom Rini]

On Wed, May 24, 2017 at 04:49:41AM +0900, Nobuhiro Iwamatsu wrote:

> Hi Tom,
> 
> Please pull ARM/r-mobile updates for v2017.07.
> 
> The following changes since commit a375ff8e14bea0a5cbfff99d6456aa8d9a3320ab:
> 
>   Merge branch 'master' of git://www.denx.de/git/u-boot-imx
> (2017-05-18 17:17:45 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-sh.git rmobile
> 
> for you to fetch changes up to 16071b1ba1ef0c938718d1544bb78937a896a4c1:
> 
>   ARM: rmobile: Move address of IICDVFS(I2C) to rcar-gen3-base.h
> (2017-05-22 15:07:31 +0900)
> 

Applied to u-boot/master, thanks!

-- 
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[U-Boot] [PATCH] rockchip: Set up default PWM flags

[Simon Glass]

At present if the PWM set_invert() method is not called then the flags are
not set up and the driver does not work properly. Fix this by setting up
the default flags when probing.

Signed-off-by: Simon Glass 
Fixes: 874ee59 (rockchip: pwm: implement pwm_set_invert())
---

 drivers/pwm/rk_pwm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c
index f3b2f7615d..5d78d4a67d 100644
--- a/drivers/pwm/rk_pwm.c
+++ b/drivers/pwm/rk_pwm.c
@@ -92,6 +92,7 @@ static int rk_pwm_probe(struct udevice *dev)
return -EINVAL;
}
priv->freq = clk_get_rate();
+   priv->enable_conf = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE;
 
return 0;
 }
-- 
2.13.0.219.gdb65acc882-goog

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Re: [U-Boot] [PATCH v2 0/2] sunxi: update Pine64 device tree

[Andreas Färber]

Hi Andre,

Am 23.05.2017 um 12:09 schrieb Andre Przywara:
> an updated version: the first patch is unchanged (still the exact
> same DT as in Linux), but the second patch reformats the Ethernet nodes
> as a .dtsi and uses the new U-Boot specific DT addon feature to make
> it clear that these nodes are for a (preliminary) U-Boot specific binding.
> Once the Ethernet driver made it into Linux, we will either adapt the
> U-Boot driver to cope with the new binding or get a new (Designware based)
> driver anyway. In any case this -u-boot.dtsi can then just be removed.

Could we squash the two? Or add the .dtsi first? That would keep the
series bisectable.

Cheers,
Andreas

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Re: [U-Boot] [PATCH] rockchip: dts: rk3328: add aliases for mmc controller

[Andreas Färber]

Hi Heiko,

Am 23.05.2017 um 23:27 schrieb Heiko Stuebner:
> Am Dienstag, 23. Mai 2017, 17:14:19 CEST schrieb Tom Rini:
>> On Tue, May 23, 2017 at 11:03:23PM +0200, Mark Kettenis wrote:
 From: Heiko Stuebner 
 Date: Tue, 23 May 2017 22:29:33 +0200

 Hi Kever, Tom,

 Am Dienstag, 23. Mai 2017, 14:32:44 CEST schrieb Kever Yang:
>  This is not from kernel, seems the kernel mmc driver does not 
> support aliases now,
>
> thought I hope they both support the aliases for ordering.

 there was a lengthy discussion about the pros and cons of ordering
 mmc devices last year [0].

 With the outcome that explicit ordering via aliases is not desired
 and the argument being that mmc devices are not so different from
 usb storage or scsi/sata devices whose ordering is random all the time.
>>>
>>> Aren't you intepreting the outcome of that discussion a bit too
>>> broadly tough?  That discussion seems to reject an explicit ordering
>>> of mmc device names in the Linux kernel, mainly because better
>>> mechanisms exist to refer to a particular device than its device
>>> name/number.  But that doesn't preclude having a meaningful set of
>>> aliases for certain boards if there is some sort of canonical boot
>>> order or if devices are actually numbered on a board?
>>>
>>> In OpenFirmware the primary purpose of these aliases is to specify
>>> which device to boot from.
> 
> readding the lkml-link for the above:
> [0] https://lkml.org/lkml/2016/4/29/621
> 
> 
> As for that being to broad, wasn't that why Tom suggested moving that
> to a -u-boot.dtsi file, because while generally not desired, it may
> benefit uboot to get some sane boot order / type marks (emmc, sd-card),
> but doesn't influence the core devicetree files that should ideally be
> synced from the kernel or wherever?

I think you're mixing three very distinct topics here:
a) Whether Linux drivers should use aliases for ordering.
b) Whether to add aliases in the DT.
c) Sync'ing .dts files from Linux vs. local changes.

I don't see what's wrong with b) as it is useful as a shorthand for
access to a particular node, e.g. for U-Boot's fdt commands.

Tom's point is that if a certain change is not in the Linux .dts and is
needed for U-Boot, it should go into a U-Boot specific .dtsi file, so
that the change doesn't get overwritten with the next .dts update from
Linux.
In the UEFI boot path we rely on a recent upstream-compatible DT being
provided by U-Boot if none is installed by the OS in a way U-Boot can
load, so the .dts will need to be re-sync'ed later on even if it doesn't
affect U-Boot drivers. Therefore the commit messages also need to
indicate where the .dts comes from, to avoid regressions on re-sync from
different trees.

Regards,
Andreas

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Re: [U-Boot] [PATCH] rockchip: dts: rk3328: add aliases for mmc controller

[Heiko Stuebner]

Hi,

Am Dienstag, 23. Mai 2017, 17:14:19 CEST schrieb Tom Rini:
> On Tue, May 23, 2017 at 11:03:23PM +0200, Mark Kettenis wrote:
> > > From: Heiko Stuebner 
> > > Date: Tue, 23 May 2017 22:29:33 +0200
> > > 
> > > Hi Kever, Tom,
> > > 
> > > Am Dienstag, 23. Mai 2017, 14:32:44 CEST schrieb Kever Yang:
> > > >  This is not from kernel, seems the kernel mmc driver does not 
> > > > support aliases now,
> > > > 
> > > > thought I hope they both support the aliases for ordering.
> > > 
> > > there was a lengthy discussion about the pros and cons of ordering
> > > mmc devices last year [0].
> > > 
> > > With the outcome that explicit ordering via aliases is not desired
> > > and the argument being that mmc devices are not so different from
> > > usb storage or scsi/sata devices whose ordering is random all the time.
> > 
> > Aren't you intepreting the outcome of that discussion a bit too
> > broadly tough?  That discussion seems to reject an explicit ordering
> > of mmc device names in the Linux kernel, mainly because better
> > mechanisms exist to refer to a particular device than its device
> > name/number.  But that doesn't preclude having a meaningful set of
> > aliases for certain boards if there is some sort of canonical boot
> > order or if devices are actually numbered on a board?
> > 
> > In OpenFirmware the primary purpose of these aliases is to specify
> > which device to boot from.

readding the lkml-link for the above:
[0] https://lkml.org/lkml/2016/4/29/621


As for that being to broad, wasn't that why Tom suggested moving that
to a -u-boot.dtsi file, because while generally not desired, it may
benefit uboot to get some sane boot order / type marks (emmc, sd-card),
but doesn't influence the core devicetree files that should ideally be
synced from the kernel or wherever?


Heiko
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Re: [U-Boot] [PATCH] rockchip: dts: rk3328: add aliases for mmc controller

[Tom Rini]

On Tue, May 23, 2017 at 11:03:23PM +0200, Mark Kettenis wrote:
> > From: Heiko Stuebner 
> > Date: Tue, 23 May 2017 22:29:33 +0200
> > 
> > Hi Kever, Tom,
> > 
> > Am Dienstag, 23. Mai 2017, 14:32:44 CEST schrieb Kever Yang:
> > >  This is not from kernel, seems the kernel mmc driver does not 
> > > support aliases now,
> > > 
> > > thought I hope they both support the aliases for ordering.
> > 
> > there was a lengthy discussion about the pros and cons of ordering
> > mmc devices last year [0].
> > 
> > With the outcome that explicit ordering via aliases is not desired
> > and the argument being that mmc devices are not so different from
> > usb storage or scsi/sata devices whose ordering is random all the time.
> 
> Aren't you intepreting the outcome of that discussion a bit too
> broadly tough?  That discussion seems to reject an explicit ordering
> of mmc device names in the Linux kernel, mainly because better
> mechanisms exist to refer to a particular device than its device
> name/number.  But that doesn't preclude having a meaningful set of
> aliases for certain boards if there is some sort of canonical boot
> order or if devices are actually numbered on a board?
> 
> In OpenFirmware the primary purpose of these aliases is to specify
> which device to boot from.

Rob?

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[U-Boot] [PATCH] edid: Fix gcc 7.1 warning

[Jernej Skrabec]

This commit fixes the warning produced by gcc 7.1.

Signed-off-by: Jernej Skrabec 
---

 common/edid.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/edid.c b/common/edid.c
index 19410aa4fc..854d40c8f8 100644
--- a/common/edid.c
+++ b/common/edid.c
@@ -295,7 +295,7 @@ static void edid_print_dtd(struct edid_monitor_descriptor 
*monitor,
 
h_total = h_active + h_blanking;
v_total = v_active + v_blanking;
-   if (v_total * h_total)
+   if (v_total > 0 && h_total > 0)
vfreq = pixclock / (v_total * h_total);
else
vfreq = 1; /* Error case */
-- 
2.13.0

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Re: [U-Boot] [PATCH] rockchip: dts: rk3328: add aliases for mmc controller

[Mark Kettenis]

> From: Heiko Stuebner 
> Date: Tue, 23 May 2017 22:29:33 +0200
> 
> Hi Kever, Tom,
> 
> Am Dienstag, 23. Mai 2017, 14:32:44 CEST schrieb Kever Yang:
> >  This is not from kernel, seems the kernel mmc driver does not 
> > support aliases now,
> > 
> > thought I hope they both support the aliases for ordering.
> 
> there was a lengthy discussion about the pros and cons of ordering
> mmc devices last year [0].
> 
> With the outcome that explicit ordering via aliases is not desired
> and the argument being that mmc devices are not so different from
> usb storage or scsi/sata devices whose ordering is random all the time.

Aren't you intepreting the outcome of that discussion a bit too
broadly tough?  That discussion seems to reject an explicit ordering
of mmc device names in the Linux kernel, mainly because better
mechanisms exist to refer to a particular device than its device
name/number.  But that doesn't preclude having a meaningful set of
aliases for certain boards if there is some sort of canonical boot
order or if devices are actually numbered on a board?

In OpenFirmware the primary purpose of these aliases is to specify
which device to boot from.
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Re: [U-Boot] [PATCH] rockchip: dts: rk3328: add aliases for mmc controller

[Tom Rini]

On Tue, May 23, 2017 at 10:29:33PM +0200, Heiko Stuebner wrote:
> Hi Kever, Tom,
> 
> Am Dienstag, 23. Mai 2017, 14:32:44 CEST schrieb Kever Yang:
> >  This is not from kernel, seems the kernel mmc driver does not 
> > support aliases now,
> > 
> > thought I hope they both support the aliases for ordering.
> 
> there was a lengthy discussion about the pros and cons of ordering
> mmc devices last year [0].
> 
> With the outcome that explicit ordering via aliases is not desired
> and the argument being that mmc devices are not so different from
> usb storage or scsi/sata devices whose ordering is random all the time.

Ug, that's right.  This at least needs to go into the -u-boot.dtsi file
then and we can see if we can do anything else (probably not) to ensure
sanity with respect to ordering.

-- 
Tom


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Re: [U-Boot] [PATCH] rockchip: dts: rk3328: add aliases for mmc controller

[Heiko Stuebner]

Hi Kever, Tom,

Am Dienstag, 23. Mai 2017, 14:32:44 CEST schrieb Kever Yang:
>  This is not from kernel, seems the kernel mmc driver does not 
> support aliases now,
> 
> thought I hope they both support the aliases for ordering.

there was a lengthy discussion about the pros and cons of ordering
mmc devices last year [0].

With the outcome that explicit ordering via aliases is not desired
and the argument being that mmc devices are not so different from
usb storage or scsi/sata devices whose ordering is random all the time.


Heiko

[0] https://lkml.org/lkml/2016/4/29/621


> Thanks,
> - Kever
> On 05/23/2017 05:18 AM, Tom Rini wrote:
> > On Thu, May 18, 2017 at 04:05:20PM +0800, Kever Yang wrote:
> >
> >> Add aliases for mmc controller to get a fixed order with
> >> emmc at index 0 and sdmmc at index 1.
> >>
> >> Signed-off-by: Kever Yang 
> >> ---
> >>
> >>   arch/arm/dts/rk3328.dtsi | 3 +++
> >>   1 file changed, 3 insertions(+)
> >>
> >> diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
> >> index 8a98ee3..e1af030 100644
> >> --- a/arch/arm/dts/rk3328.dtsi
> >> +++ b/arch/arm/dts/rk3328.dtsi
> >> @@ -25,6 +25,9 @@
> >>i2c1 = 
> >>i2c2 = 
> >>i2c3 = 
> >> +  mmc0 = 
> >> +  mmc1 = 
> >> +  mmc2 = _ext;
> >>};
> >>   
> >>cpus {
> > Does this come from re-syncing the dts with the kernel?  Are they going
> > to the kernel?  Thanks!
> >
> 
> 
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Re: [U-Boot] [PATCH v2 4/4] sunxi: video: Add H3/H5 TV out driver

[Maxime Ripard]

Hi Jernej,

On Mon, May 22, 2017 at 08:49:57PM +0200, Jernej Škrabec wrote:
> Dne ponedeljek, 22. maj 2017 ob 09:35:56 CEST je Maxime Ripard napisal(a):
> > On Fri, May 19, 2017 at 05:41:17PM +0200, Jernej Skrabec wrote:
> > > This commit adds support for TV (composite) output.
> > > 
> > > Because there is no mechanism to select TV standard, PAL is
> > > hardcoded.
> > 
> > I'd rather use a consistent mechanism with the old driver (even if we
> > only support PAL right now and reject any other option), and using
> > composite-pal as monitor.
> > 
> 
> I have few arguments against that:
> 
> 1. Code for parsing that env variable is in videomodes.[c|h], which is 
> clearly 
> a part of an older video framework (ctfb). I didn't want to include any 
> legacy 
> code.
> 
> 2. Even if this code is used for parsing, it would bring a lot of confusion. 
> For now, we can say that docs/README.video does not apply to H3 and newer 
> SoCs. If we implement this only partially, we would need to describe in 
> details which of each setting is honored with the new driver and which not. 
> Even then, a lot of users would skip that description and complain anyway.

The issue with this, and we've been bitten very hard on this one with
the CHIP, is that you don't really have a clear majority on that
one. If you support only PAL, half the world will be left out, and
same thing with NTSC (for some reason, we never needed to support the
less common ones like PAL-M or NTSC-J, but that just might be because
it never really sold that well in those countries, I don't have any
numbers on that).

The point is, if you just hardcode PAL for now, you will have half
your users complain, and then, when we will introduce NTSC support
eventually, we'll have to introduce some mechanism to switch between
the two, then we'll probably break the behaviour our users relied on
before, making the other half of our users pissed.

I'm not sure this is something we should just discard, or at least the
second part. Having the selection mechanism in place, even if we don't
support all the settings and just report an error in the logs in such
a case address the latter issue.

You'll also need to address how to setup the overscan, since this is
really something you want to have very quick.

> 3. If anything is done in this direction, I think that it is better
> to extend DM video framework so other drivers would benefit from
> that work too.

That makes sense, but again, this is a pre-requisite for me. And it's
not that hard to support the video modelines with a device model
driver, Linux does it, and you have a string identifier at the
beginning of it. It just has to be deterministic, but I don't think
this is an issue with U-Boot's DM.

Maxime

-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com


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[U-Boot] [GIT PULL] u-boot-sh/rmobile

[Nobuhiro Iwamatsu]

Hi Tom,

Please pull ARM/r-mobile updates for v2017.07.

The following changes since commit a375ff8e14bea0a5cbfff99d6456aa8d9a3320ab:

  Merge branch 'master' of git://www.denx.de/git/u-boot-imx
(2017-05-18 17:17:45 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-sh.git rmobile

for you to fetch changes up to 16071b1ba1ef0c938718d1544bb78937a896a4c1:

  ARM: rmobile: Move address of IICDVFS(I2C) to rcar-gen3-base.h
(2017-05-22 15:07:31 +0900)


Hiroyuki Yokoyama (1):
  serial: sh: Add r8a7796 support

Kouei Abe (1):
  gpio: rcar_gen3: Fix GPIO read support

Marek Vasut (24):
  net: ravb: Add Renesas Ethernet RAVB driver
  ARM: rmobile: Update R8A7795 PFC and GPIO tables
  ARM: rmobile: Import R8A7796 PFC and GPIO tables
  ARM: rmobile: Zap RCAR_GEN3_EXTRAM_BOOT
  ARM: rmobile: Update link address to match latest BL2
  ARM: rmobile: Make the Gen3 SoC configurable
  ARM: rmobile: Add R8A7795 into the CPU table
  ARM: rmobile: Add R8A7796 into the CPU table
  ARM: rmobile: Handle R8A7796 r1.1 in the PRR code
  ARM: rmobile: Add R8A7796 support
  ARM: rmobile: Allow R8A7796 Salvator-X configuration
  ARM: rmobile: salvator-x: Use BIT() macro in board file
  ARM: rmobile: salvator-x: Move OF_LIBFDT and CMD_FDT to board config
  ARM: rmobile: salvator-x: Set default device tree
  ARM: rmobile: salvator-x: Zap redefined DECLARE_GLOBAL_DATA_PTR
  ARM: rmobile: salvator-x: Adjust UART clock
  ARM: rmobile: salvator-x: Add SD support
  ARM: rmobile: salvator-x: Add RAVB ethernet support
  ARM: rmobile: salvator-x: Add DVFS and PMIC support
  ARM: rmobile: salvator-x: Add USB support
  ARM: rmobile: salvator-x: Count all DRAM in all slots
  ARM: rmobile: salvator-x: Enable SCIF2 clock
  ARM: rmobile: salvator-x: Rename the defconfig to match the SoC
  ARM: rmobile: salvator-x: Add R8A7796 support

Nobuhiro Iwamatsu (1):
  ARM: rmobile: Move address of IICDVFS(I2C) to rcar-gen3-base.h

 arch/arm/mach-rmobile/Kconfig.64|   18 +-
 arch/arm/mach-rmobile/Makefile  |1 +
 arch/arm/mach-rmobile/cpu_info-rcar.c   |   19 +-
 arch/arm/mach-rmobile/cpu_info.c|2 +
 arch/arm/mach-rmobile/include/mach/gpio.h   |3 +
 arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h   |  182 ++--
 arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h   | 1084 ++
 arch/arm/mach-rmobile/include/mach/r8a7796.h|   36 +
 arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h |3 +
 arch/arm/mach-rmobile/include/mach/rmobile.h|2 +
 arch/arm/mach-rmobile/memmap-r8a7796.c  |   30 +
 arch/arm/mach-rmobile/pfc-r8a7795.c | 1465
+
 arch/arm/mach-rmobile/pfc-r8a7796.c | 5253

 board/renesas/salvator-x/MAINTAINERS|3 +-
 board/renesas/salvator-x/salvator-x.c   |  225 +++-
 configs/r8a7795_salvator-x_defconfig|   31 +
 configs/r8a7796_salvator-x_defconfig|   31 +
 configs/salvator-x_defconfig|   12 -
 drivers/gpio/sh_pfc.c   |   17 +-
 drivers/net/Kconfig |8 +
 drivers/net/Makefile|1 +
 drivers/net/ravb.c  |  601 ++
 drivers/serial/serial_sh.h  |3 +-
 include/configs/rcar-gen3-common.h  |   37 +-
 include/configs/salvator-x.h|   42 +-
 scripts/config_whitelist.txt|1 +
 26 files changed, 8307 insertions(+), 803 deletions(-)
 create mode 100644 arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h
 create mode 100644 arch/arm/mach-rmobile/include/mach/r8a7796.h
 create mode 100644 arch/arm/mach-rmobile/memmap-r8a7796.c
 create mode 100644 arch/arm/mach-rmobile/pfc-r8a7796.c
 create mode 100644 configs/r8a7795_salvator-x_defconfig
 create mode 100644 configs/r8a7796_salvator-x_defconfig
 delete mode 100644 configs/salvator-x_defconfig
 create mode 100644 drivers/net/ravb.c


-- 
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   iwamatsu at {nigauri.org / debian.org}
   GPG ID: 40AD1FA6
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[U-Boot] [PATCH 3/4] mips: bmips: add bcm63xx-hsspi driver support for BCM63268

[Álvaro Fernández Rojas]

This driver manages the high speed SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas 
---
 arch/mips/dts/brcm,bcm63268.dtsi | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi
index 6e3d9c3..4d4e36c 100644
--- a/arch/mips/dts/brcm,bcm63268.dtsi
+++ b/arch/mips/dts/brcm,bcm63268.dtsi
@@ -15,6 +15,7 @@
 
aliases {
spi0 = 
+   spi1 = 
};
 
cpus {
@@ -44,6 +45,12 @@
#size-cells = <1>;
u-boot,dm-pre-reloc;
 
+   hsspi_pll: hsspi-pll {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <4>;
+   };
+
periph_osc: periph-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -153,6 +160,20 @@
status = "disabled";
};
 
+   hsspi: spi@10001000 {
+   compatible = "brcm,bcm6328-hsspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x10001000 0x600>;
+   clocks = <_clk BCM63268_CLK_HSSPI>, <_pll>;
+   clock-names = "hsspi", "pll";
+   resets = <_rst BCM63268_RST_SPI>;
+   spi-max-frequency = <5000>;
+   num-cs = <8>;
+
+   status = "disabled";
+   };
+
leds: led-controller@10001900 {
compatible = "brcm,bcm6328-leds";
reg = <0x10001900 0x24>;
-- 
2.1.4

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[U-Boot] [PATCH 1/4] dm: spi: add BCM63xx HSSPI driver

[Álvaro Fernández Rojas]

This driver is a simplified version of linux/drivers/spi/spi-bcm63xx-hsspi.c

Signed-off-by: Álvaro Fernández Rojas 
---
 drivers/spi/Kconfig |   8 +
 drivers/spi/Makefile|   1 +
 drivers/spi/bcm63xx_hsspi.c | 392 
 3 files changed, 401 insertions(+)
 create mode 100644 drivers/spi/bcm63xx_hsspi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index e452223..a67c05f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -40,6 +40,14 @@ config ATMEL_SPI
  many AT32 (AVR32) and AT91 (ARM) chips. This driver can be
  used to access the SPI Flash, such as AT25DF321.
 
+config BCM6328_HSSPI
+   bool "BCM6328 HSSPI driver"
+   depends on ARCH_BMIPS
+   help
+ Enable the BCM6328 HSSPI driver. This driver can be used to
+ access the SPI NOR flash on platforms embedding this Broadcom
+ SPI core.
+
 choice
prompt "BCM63xx SPI driver"
depends on ARCH_BMIPS
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index c9ba648..a12a354 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
 obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
 obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
 obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
+obj-$(CONFIG_BCM6328_HSSPI) += bcm63xx_hsspi.o
 obj-$(CONFIG_BCM6338_SPI)$(CONFIG_BCM6358_SPI) += bcm63xx_spi.o
 obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
 obj-$(CONFIG_CF_SPI) += cf_spi.o
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
new file mode 100644
index 000..bdd2e3e
--- /dev/null
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -0,0 +1,392 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas 
+ *
+ * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
+ * Copyright (C) 2000-2010 Broadcom Corporation
+ * Copyright (C) 2012-2013 Jonas Gorski 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SPI_PP_SEL 0
+
+#define SPI_MAX_SYNC_CLOCK 3000
+
+/* SPI Control register */
+#define SPI_CTL_REG0x000
+#define SPI_CTL_CS_POL_SHIFT   0
+#define SPI_CTL_CS_POL_MASK(0xff << SPI_CTL_CS_POL_SHIFT)
+#define SPI_CTL_CLK_GATE_SHIFT 16
+#define SPI_CTL_CLK_GATE_MASK  (1 << SPI_CTL_CLK_GATE_SHIFT)
+#define SPI_CTL_CLK_POL_SHIFT  17
+#define SPI_CTL_CLK_POL_MASK   (1 << SPI_CTL_CLK_POL_SHIFT)
+
+/* SPI Interrupts registers */
+#define SPI_IR_STAT_REG0x008
+#define SPI_IR_ST_MASK_REG 0x00c
+#define SPI_IR_MASK_REG0x010
+
+#define SPI_IR_CLEAR_ALL   0xff001f1f
+
+/* SPI Ping-Pong Command registers */
+#define SPI_PP_CMD_REG (0x080 + (0x40 * (SPI_PP_SEL)) + 0x00)
+#define SPI_PP_CMD_OP_SHIFT0
+#define SPI_PP_CMD_OP_START(0x1 << SPI_PP_CMD_OP_SHIFT)
+#define SPI_PP_CMD_PFL_SHIFT   8
+#define SPI_PP_CMD_PFL_MASK(0x7 << SPI_PP_CMD_PFL_SHIFT)
+#define SPI_PP_CMD_SLAVE_SHIFT 12
+#define SPI_PP_CMD_SLAVE_MASK  (0x7 << SPI_PP_CMD_SLAVE_SHIFT)
+
+/* SPI Ping-Pong Status registers */
+#define SPI_PP_STAT_REG(0x080 + (0x40 * (SPI_PP_SEL)) 
+ 0x04)
+#define SPI_PP_STAT_SRCBUSY_SHIFT  1
+#define SPI_PP_STAT_SRCBUSY_MASK   (1 << SPI_PP_STAT_SRCBUSY_SHIFT)
+
+/* SPI Profile Clock registers */
+#define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00)
+#define SPI_PFL_CLK_FREQ_SHIFT 0
+#define SPI_PFL_CLK_FREQ_MASK  (0x3fff << SPI_PFL_CLK_FREQ_SHIFT)
+#define SPI_PFL_CLK_RSTLOOP_SHIFT  15
+#define SPI_PFL_CLK_RSTLOOP_MASK   (1 << SPI_PFL_CLK_RSTLOOP_SHIFT)
+
+/* SPI Profile Signal registers */
+#define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04)
+#define SPI_PFL_SIG_LATCHRIS_SHIFT 12
+#define SPI_PFL_SIG_LATCHRIS_MASK  (1 << SPI_PFL_SIG_LATCHRIS_SHIFT)
+#define SPI_PFL_SIG_LAUNCHRIS_SHIFT13
+#define SPI_PFL_SIG_LAUNCHRIS_MASK (1 << SPI_PFL_SIG_LAUNCHRIS_SHIFT)
+#define SPI_PFL_SIG_ASYNCIN_SHIFT  16
+#define SPI_PFL_SIG_ASYNCIN_MASK   (1 << SPI_PFL_SIG_ASYNCIN_SHIFT)
+
+/* SPI Profile Mode registers */
+#define SPI_PFL_MODE_REG(x)(0x100 + (0x20 * (x)) + 0x08)
+#define SPI_PFL_MODE_FILL_SHIFT0
+#define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT)
+#define SPI_PFL_MODE_MDRDSZ_SHIFT  16
+#define SPI_PFL_MODE_MDRDSZ_MASK   (1 << SPI_PFL_MODE_MDRDSZ_SHIFT)
+#define SPI_PFL_MODE_MDWRSZ_SHIFT  18
+#define SPI_PFL_MODE_MDWRSZ_MASK   (1 << SPI_PFL_MODE_MDWRSZ_SHIFT)
+#define SPI_PFL_MODE_3WIRE_SHIFT   20
+#define SPI_PFL_MODE_3WIRE_MASK(1 << SPI_PFL_MODE_3WIRE_SHIFT)
+
+/* SPI Ping-Pong 

[U-Boot] [PATCH 0/4] mips: bmips: add HSSPI support

[Álvaro Fernández Rojas]

BCM63xx HSSPI controller has the same issue as BCM63xx SPI controller: it
doesn't allow keeping CS active between transfers.
However, this controller allows changing CS polarities, which is used in the
linux upstream driver to manage CS as desired.

Álvaro Fernández Rojas (4):
  dm: spi: add BCM63xx HSSPI driver
  mips: bmips: add bcm63xx-hsspi driver support for BCM6328
  mips: bmips: add bcm63xx-hsspi driver support for BCM63268
  mips: bmips: enable the SPI flash on the Comtrend AR-5387un

 arch/mips/dts/brcm,bcm63268.dtsi|  21 ++
 arch/mips/dts/brcm,bcm6328.dtsi |  24 ++
 arch/mips/dts/comtrend,ar-5387un.dts|  12 +
 configs/comtrend_ar5387un_ram_defconfig |   8 +
 drivers/spi/Kconfig |   8 +
 drivers/spi/Makefile|   1 +
 drivers/spi/bcm63xx_hsspi.c | 392 
 7 files changed, 466 insertions(+)
 create mode 100644 drivers/spi/bcm63xx_hsspi.c

-- 
2.1.4

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[U-Boot] [PATCH v2 29/30] ARM: k2g: Add K2G ICE DTB to the list of possible DTBs

[Franklin S Cooper Jr]

K2G ICE evm will have its own dtb. Therefore, add it to the list of dtbs
located in the appended U-boot dtb FIT image. Therefore, when swapping out
dtbs K2G ICE boards can grab the correct one.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
---
 board/ti/ks2_evm/board_k2g.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index 5f3fc76..bbd74ee 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -225,6 +225,8 @@ int board_fit_config_name_match(const char *name)
return 0;
else if (!strcmp(name, "keystone-k2g-evm") && board_ti_is("66AK2GGP"))
return 0;
+   else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
+   return 0;
else
return -1;
 }
-- 
2.10.0

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[U-Boot] [PATCH v2 28/30] ARM: dts: k2g: Add DT support for K2G Industrial Communication Engine evm

[Franklin S Cooper Jr]

Add basic DT support for K2G ICE evm. Only minimal peripherals are
supported to allow console output and MMC boot.

Signed-off-by: Franklin S Cooper Jr 
---
Version 2 changes:
Updated to the dts recently accepted into the Linux kernel.

 arch/arm/dts/Makefile |  3 ++-
 arch/arm/dts/keystone-k2g-ice-u-boot.dtsi | 19 
 arch/arm/dts/keystone-k2g-ice.dts | 36 +++
 3 files changed, 57 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/keystone-k2g-ice-u-boot.dtsi
 create mode 100644 arch/arm/dts/keystone-k2g-ice.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 63450f5..89bac41 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -355,7 +355,8 @@ dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \
keystone-k2e-evm.dtb \
keystone-k2g-evm.dtb \
-   keystone-k2g-generic.dtb
+   keystone-k2g-generic.dtb \
+   keystone-k2g-ice.dtb
 
 dtb-$(CONFIG_TARGET_AT91SAM9263EK) += at91sam9263ek.dtb
 
diff --git a/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi 
b/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi
new file mode 100644
index 000..4d073f3
--- /dev/null
+++ b/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/{
+   soc {
+   u-boot,dm-pre-reloc;
+   };
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/keystone-k2g-ice.dts 
b/arch/arm/dts/keystone-k2g-ice.dts
new file mode 100644
index 000..be63782
--- /dev/null
+++ b/arch/arm/dts/keystone-k2g-ice.dts
@@ -0,0 +1,36 @@
+/*
+ * Device Tree Source for K2G Industrial Communication Engine EVM
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/dts-v1/;
+
+#include "keystone-k2g.dtsi"
+
+/ {
+   compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
+   model = "Texas Instruments K2G Industrial Communication EVM";
+
+   chosen {
+   stdout-path = 
+   };
+
+   memory@8000 {
+   device_type = "memory";
+   reg = <0x8000 0x2000>;
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
-- 
2.10.0

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[U-Boot] [PATCH v2 20/30] ARM: k2g: Add pinmux support for K2G ICE evm

[Franklin S Cooper Jr]

Add basic pinmux data for new K2G ICE evm. Also add pinmuxing for a
generic K2G evm which includes I2C 0 and 1 used for board detection
purposes.

Since multiple K2G boards are supported that means initially generic
pinmuxing should be used when board detection hasn't ran. Once board
detection runs the proper pinmuxing can be reran to match the board
being ran on.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
---
 board/ti/ks2_evm/board_k2g.c |  2 ++
 board/ti/ks2_evm/mux-k2g.h   | 45 +++-
 2 files changed, 46 insertions(+), 1 deletion(-)

diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index d796fd1..a93ef47 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -274,6 +274,8 @@ int embedded_dtb_select(void)
 
fdtdec_setup();
 
+   k2g_mux_config();
+
k2g_reset_mux_config();
 
/* deassert FLASH_HOLD */
diff --git a/board/ti/ks2_evm/mux-k2g.h b/board/ti/ks2_evm/mux-k2g.h
index 773f9b7..630103d 100644
--- a/board/ti/ks2_evm/mux-k2g.h
+++ b/board/ti/ks2_evm/mux-k2g.h
@@ -11,6 +11,22 @@
 #include 
 #include 
 #include 
+#include "board.h"
+
+struct pin_cfg k2g_generic_pin_cfg[] = {
+   /* UART0 */
+   { 115,  MODE(0) },  /* SOC_UART0_RXD */
+   { 116,  MODE(0) },  /* SOC_UART0_TXD */
+
+   /* I2C 0 */
+   { 223,  MODE(0) },  /* SOC_I2C0_SCL */
+   { 224,  MODE(0) },  /* SOC_I2C0_SDA */
+
+   /* I2C 1 */
+   { 225,  MODE(0) },  /* SOC_I2C1_SCL */
+   { 226,  MODE(0) },  /* SOC_I2C1_SDA */
+   { MAX_PIN_N, }
+};
 
 struct pin_cfg k2g_evm_pin_cfg[] = {
/* GPMC */
@@ -307,7 +323,34 @@ struct pin_cfg k2g_evm_pin_cfg[] = {
{ MAX_PIN_N, }
 };
 
+struct pin_cfg k2g_ice_evm_pin_cfg[] = {
+   /* MMC 1 */
+   { 63, MODE(0) | PIN_PTD },  /* MMC1_DAT3.MMC1_DAT3 */
+   { 64, MODE(0) | PIN_PTU },  /* MMC1_DAT2.MMC1_DAT2 */
+   { 65, MODE(0) | PIN_PTU },  /* MMC1_DAT1.MMC1_DAT1 */
+   { 66, MODE(0) | PIN_PTD },  /* MMC1_DAT0.MMC1_DAT0 */
+   { 67, MODE(0) | PIN_PTD },  /* MMC1_CLK.MMC1_CLK   */
+   { 68, MODE(0) | PIN_PTD },  /* MMC1_CMD.MMC1_CMD   */
+   { 69, MODE(3) | PIN_PTU },  /* MMC1_SDCD.GPIO0_69  */
+   { 70, MODE(0) | PIN_PTU },  /* MMC1_SDWP.MMC1_SDWP */
+   { 71, MODE(0) | PIN_PTD },  /* MMC1_POW.MMC1_POW   */
+
+   /* I2C 0 */
+   { 223,  MODE(0) },  /* SOC_I2C0_SCL */
+   { 224,  MODE(0) },  /* SOC_I2C0_SDA */
+   { MAX_PIN_N, }
+};
+
 void k2g_mux_config(void)
 {
-   configure_pin_mux(k2g_evm_pin_cfg);
+   if (!board_ti_was_eeprom_read()) {
+   configure_pin_mux(k2g_generic_pin_cfg);
+   } else if (board_is_k2g_gp()) {
+   configure_pin_mux(k2g_evm_pin_cfg);
+   } else if (board_is_k2g_ice()) {
+   configure_pin_mux(k2g_ice_evm_pin_cfg);
+   } else {
+   puts("Unknown board, cannot configure pinmux.");
+   hang();
+   }
 }
-- 
2.10.0

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[U-Boot] [PATCH v2 23/30] ARM: k2g: Use board detection to wrap K2G GP specific calls

[Franklin S Cooper Jr]

Certain peripherals used by K2G GP aren't used on K2G ICE evm. Or
configuration is slightly different. Therefore, use board detection to
deal with these variations.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
---
 board/ti/ks2_evm/board_k2g.c | 16 ++--
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index a93ef47..96b313f 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -208,7 +208,9 @@ int board_mmc_init(bd_t *bis)
return -1;
}
 
-   omap_mmc_init(0, 0, 0, -1, -1);
+   if (board_is_k2g_gp())
+   omap_mmc_init(0, 0, 0, -1, -1);
+
omap_mmc_init(1, 0, 0, -1, -1);
return 0;
 }
@@ -278,11 +280,13 @@ int embedded_dtb_select(void)
 
k2g_reset_mux_config();
 
-   /* deassert FLASH_HOLD */
-   clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
-BIT(9));
-   setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
-BIT(9));
+   if (board_is_k2g_gp()) {
+   /* deassert FLASH_HOLD */
+   clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
+BIT(9));
+   setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
+BIT(9));
+   }
 
return 0;
 }
-- 
2.10.0

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[U-Boot] [PATCH v2 04/30] fdt: Enable selecting correct DTB from appended FIT Image

[Franklin S Cooper Jr]

This patch gives U-boot the runtime support to have the board specific
code decide which FDT to use. This is especially useful for devices
that need this type of runtime determination and also doesn't use SPL.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Lokesh Vutla 
Reviewed-by: Tom Rini 
---
 lib/fdtdec.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index c072e54..8bd2940 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -4,6 +4,7 @@
  */
 
 #ifndef USE_HOSTCC
+#include 
 #include 
 #include 
 #include 
@@ -1251,6 +1252,15 @@ int fdtdec_setup(void)
gd->fdt_blob = (ulong *)&_image_binary_end;
else
gd->fdt_blob = (ulong *)&__bss_end;
+
+#  elif defined CONFIG_FIT_EMBED
+   gd->fdt_blob = locate_dtb_in_fit(&_end);
+
+   if (gd->fdt_blob == NULL || gd->fdt_blob <= ((void *)&_end)) {
+   puts("Failed to find proper dtb in embedded FIT Image\n");
+   return -1;
+   }
+
 #  else
/* FDT is at end of image */
gd->fdt_blob = (ulong *)&_end;
-- 
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[U-Boot] [PATCH v2 30/30] defconfig: k2g_evm_defconfig: Add K2G ICE to OF_LIST

[Franklin S Cooper Jr]

Include K2G ICE to OF_LIST so it can be used for runtime board
detection.

Signed-off-by: Franklin S Cooper Jr 
---
 configs/k2g_evm_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 7b105da..a5639ea 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -48,4 +48,4 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_DTB_RESELECT=y
 CONFIG_FIT_EMBED=y
-CONFIG_OF_LIST="keystone-k2g-generic keystone-k2g-evm"
+CONFIG_OF_LIST="keystone-k2g-generic keystone-k2g-evm keystone-k2g-ice"
-- 
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[U-Boot] [PATCH v2 01/30] ti: common: board_detect: Allow settings board detection variables manually

[Franklin S Cooper Jr]

From: Nishanth Menon 

In some situations the EEPROM used for board detection may not be
programmed or simply programmed incorrectly. Therefore, it may be
necessary to "simulate" reading the contents of the EEPROM to set
appropriate variables used in the board detection code.

This may also be helpful in certain boot modes where doing i2c reads
may be costly and the config supports running only a specific board.

Signed-off-by: Nishanth Menon 
Signed-off-by: Tero Kristo 
Signed-off-by: Keerthy 
Signed-off-by: Franklin S Cooper Jr. 
---
 board/ti/common/board_detect.c | 24 
 board/ti/common/board_detect.h | 17 +
 2 files changed, 41 insertions(+)

diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
index 6fdcb61..bf594cb 100644
--- a/board/ti/common/board_detect.c
+++ b/board/ti/common/board_detect.c
@@ -173,6 +173,30 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, 
int dev_addr,
return 0;
 }
 
+int __maybe_unused ti_i2c_eeprom_am_set(const char *name, const char *rev)
+{
+   struct ti_common_eeprom *ep;
+
+   if (!name || !rev)
+   return -1;
+
+   ep = TI_EEPROM_DATA;
+   if (ep->header == TI_EEPROM_HEADER_MAGIC)
+   goto already_set;
+
+   /* Set to 0 all fields */
+   memset(ep, 0, sizeof(*ep));
+   strncpy(ep->name, name, TI_EEPROM_HDR_NAME_LEN);
+   strncpy(ep->version, rev, TI_EEPROM_HDR_REV_LEN);
+   /* Some dummy serial number to identify the platform */
+   strncpy(ep->serial, "", TI_EEPROM_HDR_SERIAL_LEN);
+   /* Mark it with a valid header */
+   ep->header = TI_EEPROM_HEADER_MAGIC;
+
+already_set:
+   return 0;
+}
+
 int __maybe_unused ti_i2c_eeprom_am_get(int bus_addr, int dev_addr)
 {
int rc;
diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h
index 88b0a59..e8d9484 100644
--- a/board/ti/common/board_detect.h
+++ b/board/ti/common/board_detect.h
@@ -205,4 +205,21 @@ void set_board_info_env(char *name);
  */
 void board_ti_set_ethaddr(int index);
 
+/**
+ * ti_i2c_eeprom_am_set() - Setup the eeprom data with predefined values
+ * @name:  Name of the board
+ * @rev:   Revision of the board
+ *
+ * In some cases such as in RTC-only mode, we are able to skip reading eeprom
+ * and wasting i2c based initialization time by using predefined flags for
+ * detecting what platform we are booting on. For those platforms, provide
+ * a handy function to pre-program information.
+ *
+ * NOTE: many eeprom information such as serial number, mac address etc is not
+ * available.
+ *
+ * Return: 0 if all went fine, else return error.
+ */
+int ti_i2c_eeprom_am_set(const char *name, const char *rev);
+
 #endif /* __BOARD_DETECT_H */
-- 
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[U-Boot] [PATCH v2 09/30] board_f: Add new function to allow runtime DTB selection

[Franklin S Cooper Jr]

Runtime U-boot dtb selection is generally a two step process. First step
is to simply use an initial generic dtb. The second step is to select
the dtb and perhaps execute additional code ones U-boot knows what board
it is running on. Embedded_dtb_select handles the second step by allowing
board specific code to run and perform what ever necessary configuration
that is needed.

Signed-off-by: Franklin S Cooper Jr 
---
 common/Kconfig   | 10 ++
 common/board_f.c |  3 +++
 include/common.h |  4 
 3 files changed, 17 insertions(+)

diff --git a/common/Kconfig b/common/Kconfig
index 2429953..b6327f0 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -421,6 +421,16 @@ config SYS_STDIO_DEREGISTER
 
 endmenu
 
+config DTB_RESELECT
+   bool "Support swapping dtbs at a later point in boot"
+   depends on FIT_EMBED
+   default n
+   help
+ It is possible during initial boot you may need to use a generic
+ dtb until you can fully determine the board your running on. This
+ config allows boards to implement a function at a later point
+ during boot to switch to the "correct" dtb.
+
 config FIT_EMBED
bool "Support a FIT image embedded in the U-boot image"
default n
diff --git a/common/board_f.c b/common/board_f.c
index a212f2b..b383239 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -759,6 +759,9 @@ static const init_fnc_t init_sequence_f[] = {
 #if defined(CONFIG_DISPLAY_CPUINFO)
print_cpuinfo,  /* display cpu info (and speed) */
 #endif
+#if defined(CONFIG_DTB_RESELECT)
+   embedded_dtb_select,
+#endif
 #if defined(CONFIG_DISPLAY_BOARDINFO)
show_board_info,
 #endif
diff --git a/include/common.h b/include/common.h
index 45f190a..ebc716e 100644
--- a/include/common.h
+++ b/include/common.h
@@ -478,6 +478,10 @@ void   pci_init_board(void);
 #endif
 #endif
 
+#if defined(CONFIG_DTB_RESELECT)
+intembedded_dtb_select(void);
+#endif
+
 intmisc_init_f   (void);
 intmisc_init_r   (void);
 
-- 
2.10.0

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[U-Boot] [PATCH v2 22/30] board: ks2: Use board detection to wrap code not specific to K2G ICE evm

[Franklin S Cooper Jr]

Some code doesn't apply to K2G ICE evm. Therefore, use board detection to
wrap these calls.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
---
 board/ti/ks2_evm/board.c | 14 +-
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 4792311..c61baee 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -45,13 +45,17 @@ int dram_init(void)
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
 #if defined(CONFIG_TI_AEMIF)
-   aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
+   if (!board_is_k2g_ice())
+   aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
 #endif
 
-   if (ddr3_size)
-   ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
-   else
-   ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, gd->ram_size >> 30);
+   if (!board_is_k2g_ice()) {
+   if (ddr3_size)
+   ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
+   else
+   ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE,
+ gd->ram_size >> 30);
+   }
 
return 0;
 }
-- 
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[U-Boot] [PATCH v2 07/30] ARM: dts: k2g: Introduce U-boot specific dtsi file

[Franklin S Cooper Jr]

Introduce K2G evm specific dtsi file for U-boot specific configurations.
This will help seperate U-boot only configurations thus making it easier to
keep device tree files synced between U-boot and Linux.

For now only add nodes to allow i2c drivers to be probed early during
the boot process.

Signed-off-by: Franklin S Cooper Jr 
---
 arch/arm/dts/keystone-k2g-evm-u-boot.dtsi | 19 +++
 1 file changed, 19 insertions(+)
 create mode 100644 arch/arm/dts/keystone-k2g-evm-u-boot.dtsi

diff --git a/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi 
b/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
new file mode 100644
index 000..4d073f3
--- /dev/null
+++ b/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/{
+   soc {
+   u-boot,dm-pre-reloc;
+   };
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
-- 
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[U-Boot] [PATCH v2 24/30] ARM: k2g: Update board_name u-boot env variable at runtime

[Franklin S Cooper Jr]

Enable CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG to allow "board_name" to
be set depending on the board it is being ran on.

Update findfdt to use this new dynamic board_name value to determine
which dtb should be used.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
---
 board/ti/ks2_evm/board_k2g.c |  6 ++
 include/configs/k2g_evm.h| 13 +++--
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index 96b313f..5f3fc76 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -306,6 +306,12 @@ int board_late_init(void)
board_ti_set_ethaddr(1);
 #endif
 
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+   if (board_is_k2g_gp())
+   setenv("board_name", "66AK2GGP\0");
+   else if (board_is_k2g_ice())
+   setenv("board_name", "66AK2GIC\0");
+#endif
return 0;
 }
 #endif
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index bee1be7..c6eab0f 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -16,6 +16,8 @@
 /* Platform type */
 #define CONFIG_SOC_K2G
 
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
 /* U-Boot general configuration */
 #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS\
DEFAULT_MMC_TI_ARGS \
@@ -28,7 +30,14 @@
"rd_spec=-\0"   \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"   \
-   "name_fdt=keystone-k2g-evm.dtb\0"   \
+   "findfdt="\
+   "if test $board_name = 66AK2GGP; then " \
+"setenv name_fdt keystone-k2g-evm.dtb; " \
+   "else if test $board_name = 66AK2GIC; then " \
+"setenv name_fdt keystone-k2g-ice.dtb; " \
+   "else if test $name_fdt = undefined; then " \
+   "echo WARNING: Could not determine device tree to use;"\
+   "fi;fi;fi;\0" \
"name_mon=skern-k2g.bin\0"  \
"name_ubi=k2g-evm-ubifs.ubi\0"  \
"name_uboot=u-boot-spi-k2g-evm.gph\0"   \
@@ -46,7 +55,7 @@
"run envboot; " \
"run set_name_pmmc init_${boot} init_fw_rd_${boot} "\
"get_pmmc_${boot} run_pmmc get_mon_${boot} run_mon "\
-   "get_fdt_${boot} get_kern_${boot} run_kern"
+   "findfdt get_fdt_${boot} get_kern_${boot} run_kern"
 
 #include 
 
-- 
2.10.0

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[U-Boot] [PATCH v2 14/30] ks2_evm: Add EEPROM based board detection

[Franklin S Cooper Jr]

Some K2G evms have their EEPROM programming while most do not. Therefore,
add EEPROM board detection to be used as the default method and fall back
to the alternative board detection when needed.

Also reorder board configuration. Perform bare minimal configuration
initially since board detection hasn't ran. Finish board configuration
once the board has been identified.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
---
 board/ti/ks2_evm/board.h |  1 +
 board/ti/ks2_evm/board_k2g.c | 44 +++-
 2 files changed, 24 insertions(+), 21 deletions(-)

diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h
index 2bbd792..0698921 100644
--- a/board/ti/ks2_evm/board.h
+++ b/board/ti/ks2_evm/board.h
@@ -11,6 +11,7 @@
 #define _KS2_BOARD
 
 #include 
+#include "../common/board_detect.h"
 
 extern struct eth_priv_t eth_priv_cfg[];
 
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index d354415..d796fd1 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -246,24 +246,6 @@ static int k2g_alt_board_detect(void)
return 0;
 }
 
-int embedded_dtb_select(void)
-{
-   int rc;
-
-   rc = k2g_alt_board_detect();
-   if (rc) {
-   printf("Unable to do board detection\n");
-   return -1;
-   }
-
-   fdtdec_setup();
-
-   return 0;
-}
-#endif
-
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-
 static void k2g_reset_mux_config(void)
 {
/* Unlock the reset mux register */
@@ -277,11 +259,20 @@ static void k2g_reset_mux_config(void)
setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
 }
 
-int board_early_init_f(void)
+int embedded_dtb_select(void)
 {
-   init_plls();
+   int rc;
+   rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+   CONFIG_EEPROM_CHIP_ADDRESS);
+   if (rc) {
+   rc = k2g_alt_board_detect();
+   if (rc) {
+   printf("Unable to do board detection\n");
+   return -1;
+   }
+   }
 
-   k2g_mux_config();
+   fdtdec_setup();
 
k2g_reset_mux_config();
 
@@ -313,6 +304,17 @@ int board_late_init(void)
 }
 #endif
 
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+   init_plls();
+
+   k2g_mux_config();
+
+   return 0;
+}
+#endif
+
 #ifdef CONFIG_SPL_BUILD
 void spl_init_keystone_plls(void)
 {
-- 
2.10.0

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[U-Boot] [PATCH v2 27/30] ARM: dts: k2g: Disable netcp by default

[Franklin S Cooper Jr]

Disable netcp by default like all other peripherals in the dtsi file.
Enable the peripheral explicitly in the board specific dts file.

Signed-off-by: Franklin S Cooper Jr 
---
 arch/arm/dts/keystone-k2g-evm.dts| 4 
 arch/arm/dts/keystone-k2g-netcp.dtsi | 1 +
 2 files changed, 5 insertions(+)

diff --git a/arch/arm/dts/keystone-k2g-evm.dts 
b/arch/arm/dts/keystone-k2g-evm.dts
index f6fce33..de208b3 100644
--- a/arch/arm/dts/keystone-k2g-evm.dts
+++ b/arch/arm/dts/keystone-k2g-evm.dts
@@ -37,6 +37,10 @@
phy-handle = <>;
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 
diff --git a/arch/arm/dts/keystone-k2g-netcp.dtsi 
b/arch/arm/dts/keystone-k2g-netcp.dtsi
index a9b26c3..d76f2a1 100644
--- a/arch/arm/dts/keystone-k2g-netcp.dtsi
+++ b/arch/arm/dts/keystone-k2g-netcp.dtsi
@@ -99,6 +99,7 @@ netcp: netcp@400 {
reg = <0x2620110 0x8>;
reg-names = "efuse";
compatible = "ti,netcp-1.0";
+   status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
/* power-domains = <_pds K2G_DEV_NSS0>; */
-- 
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[U-Boot] [PATCH v2 19/30] ks2_evm: Add EEPROM based board detection helper functions

[Franklin S Cooper Jr]

Add a function that can be used to determine if the board being ran on is
a K2G Industrial Communication Engine EVM or K2G General Purpose EVM based
on values programmed on the EEPROM.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
---
 board/ti/ks2_evm/board.h | 20 
 1 file changed, 20 insertions(+)

diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h
index 0698921..b3ad188 100644
--- a/board/ti/ks2_evm/board.h
+++ b/board/ti/ks2_evm/board.h
@@ -15,6 +15,26 @@
 
 extern struct eth_priv_t eth_priv_cfg[];
 
+#if defined(CONFIG_TI_I2C_BOARD_DETECT)
+static inline int board_is_k2g_gp(void)
+{
+   return board_ti_is("66AK2GGP");
+}
+static inline int board_is_k2g_ice(void)
+{
+   return board_ti_is("66AK2GIC");
+}
+#else
+static inline int board_is_k2g_gp(void)
+{
+   return false;
+}
+static inline int board_is_k2g_ice(void)
+{
+   return false;
+}
+#endif
+
 int get_num_eth_ports(void);
 void spl_init_keystone_plls(void);
 
-- 
2.10.0

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[U-Boot] [PATCH v2 11/30] ARM: keystone2: Allow to build with all image formats

[Franklin S Cooper Jr]

u-boot.bin is a copy of:
u-boot-fit-dtb.bin if CONFIG_FIT_EMBED is enabled,
u-boot-dtb.bin if CONFIG_OF_SEPARATE is enabled,
u-boot-nodtb.bin if DT is not enabled.
So, use u-boot.bin to to generate keystone images instead of
u-boot-dtb.bin

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
---
 arch/arm/mach-keystone/config.mk | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-keystone/config.mk b/arch/arm/mach-keystone/config.mk
index db556ea..5806f8f 100644
--- a/arch/arm/mach-keystone/config.mk
+++ b/arch/arm/mach-keystone/config.mk
@@ -22,13 +22,13 @@ spl/u-boot-spl.gph: spl/u-boot-spl.bin FORCE
 
 OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary 
--pad-to=$(CONFIG_SPL_PAD_TO) \
  --gap-fill=0
-u-boot-spi.gph: spl/u-boot-spl.gph u-boot-dtb.img FORCE
+u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE
$(call if_changed,pad_cat)
 
 ifndef CONFIG_SPL_BUILD
 MKIMAGEFLAGS_MLO = -A $(ARCH) -T gpimage -C none \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -n U-Boot
-MLO: u-boot-dtb.bin FORCE
+MLO: u-boot.bin FORCE
$(call if_changed,mkimage)
@dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@
 endif
-- 
2.10.0

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[U-Boot] [PATCH v2 15/30] defconfig: keystone2: Enable U-boot runtime DTB detection

[Franklin S Cooper Jr]

Enable various config options to allow U-boot at runtime to select the
proper dtb to use from the list of dtb's within the FIT image.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
---
 configs/k2e_evm_defconfig  | 3 +++
 configs/k2g_evm_defconfig  | 3 +++
 configs/k2hk_evm_defconfig | 3 +++
 configs/k2l_evm_defconfig  | 3 +++
 4 files changed, 12 insertions(+)

diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 83e2138..9ab08c6 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -44,3 +44,6 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DTB_RESELECT=y
+CONFIG_FIT_EMBED=y
+CONFIG_OF_LIST="keystone-k2e-evm"
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 674ddcc..7b105da 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -46,3 +46,6 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DTB_RESELECT=y
+CONFIG_FIT_EMBED=y
+CONFIG_OF_LIST="keystone-k2g-generic keystone-k2g-evm"
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 7dc5cf5..a751a4f 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -43,3 +43,6 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DTB_RESELECT=y
+CONFIG_FIT_EMBED=y
+CONFIG_OF_LIST="keystone-k2hk-evm"
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 6be4941..cf24d27 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -43,3 +43,6 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_DTB_RESELECT=y
+CONFIG_FIT_EMBED=y
+CONFIG_OF_LIST="keystone-k2l-evm"
-- 
2.10.0

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[U-Boot] [PATCH v2 21/30] ARM: k2g: Add DDR3 configuration for K2G ICE evm

[Franklin S Cooper Jr]

Add configuration settings used by the K2G ICE evm. Also use board
detection to determine which DDR3 configuration to use.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
---
 board/ti/ks2_evm/ddr3_k2g.c | 62 +++--
 1 file changed, 60 insertions(+), 2 deletions(-)

diff --git a/board/ti/ks2_evm/ddr3_k2g.c b/board/ti/ks2_evm/ddr3_k2g.c
index 3b12943..44db335 100644
--- a/board/ti/ks2_evm/ddr3_k2g.c
+++ b/board/ti/ks2_evm/ddr3_k2g.c
@@ -10,7 +10,9 @@
 #include 
 #include "ddr3_cfg.h"
 #include 
+#include "board.h"
 
+/* K2G GP EVM DDR3 Configuration */
 struct ddr3_phy_config ddr3phy_800_2g = {
.pllcr  = 0x000DC000ul,
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
@@ -61,13 +63,69 @@ struct ddr3_emif_config ddr3_800_2g = {
.sdrfc  = 0x0C34ul,
 };
 
+/* K2G ICE evm DDR3 Configuration */
+struct ddr3_phy_config ddr3phy_800_512mb = {
+   .pllcr  = 0x000DC000ul,
+   .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+   .pgcr1_val  = ((1 << 2) | (2 << 7) | (1 << 23)),
+   .ptr0   = 0x42C21590ul,
+   .ptr1   = 0xD05612C0ul,
+   .ptr2   = 0,
+   .ptr3   = 0x06C30D40ul,
+   .ptr4   = 0x06413880ul,
+   .dcr_mask   = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+   .dcr_val= ((1 << 10)),
+   .dtpr0  = 0x550E6644ul,
+   .dtpr1  = 0x32834200ul,
+   .dtpr2  = 0x50022A00ul,
+   .mr0= 0x1430ul,
+   .mr1= 0x0006ul,
+   .mr2= 0x0008ul,
+   .dtcr   = 0x710035C7ul,
+   .pgcr2  = 0x00F03D09ul,
+   .zq0cr1 = 0x0001005Dul,
+   .zq1cr1 = 0x0001005Bul,
+   .zq2cr1 = 0x0001005Bul,
+   .pir_v1 = 0x0033ul,
+   .datx8_2_mask   = DXEN_MASK,
+   .datx8_2_val= 0,
+   .datx8_3_mask   = DXEN_MASK,
+   .datx8_3_val= 0,
+   .datx8_4_mask   = DXEN_MASK,
+   .datx8_4_val= 0,
+   .datx8_5_mask   = DXEN_MASK,
+   .datx8_5_val= 0,
+   .datx8_6_mask   = DXEN_MASK,
+   .datx8_6_val= 0,
+   .datx8_7_mask   = DXEN_MASK,
+   .datx8_7_val= 0,
+   .datx8_8_mask   = DXEN_MASK,
+   .datx8_8_val= 0,
+   .pir_v2 = 0x0F81ul,
+};
+
+struct ddr3_emif_config ddr3_800_512mb = {
+   .sdcfg  = 0x62006662ul,
+   .sdtim1 = 0x0A385033ul,
+   .sdtim2 = 0x1CA5ul,
+   .sdtim3 = 0x21ADFF32ul,
+   .sdtim4 = 0x533F067Ful,
+   .zqcfg  = 0x70073200ul,
+   .sdrfc  = 0x0C34ul,
+};
+
 u32 ddr3_init(void)
 {
/* Reset DDR3 PHY after PLL enabled */
ddr3_reset_ddrphy();
 
-   ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, _800_2g);
-   ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, _800_2g);
+   if (board_is_k2g_gp()) {
+   ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, _800_2g);
+   ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, _800_2g);
+   } else if (board_is_k2g_ice()) {
+   ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, _800_512mb);
+   ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, _800_512mb);
+   }
 
return 0;
 }
-- 
2.10.0

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[U-Boot] [PATCH v2 25/30] ARM: dts: keystone-k2g: Remove skeleton.dtsi

[Franklin S Cooper Jr]

Adding the unit address to the memory node was causing the below error:
Warning (reg_format): "reg" property in /memory has invalid length
(8 bytes) (#address-cells == 2, #size-cells == 2)

Further debugging showed that this was due to the memory node added by
default to skeleton.dtsi which was being included in keystone-k2g.dtsi.
Adding a missing node was all that was needed to remove this deprecated
dtsi file from the SoC dtsi. With skeleton.dtsi removed the dtc compiler
no longer complained about including the unit address for the memory node.

Signed-off-by: Franklin S Cooper Jr 
---
This patch mimics similar changes being pulled into Linux kernel.

 arch/arm/dts/keystone-k2g.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/keystone-k2g.dtsi b/arch/arm/dts/keystone-k2g.dtsi
index 191e3f1..f05afb7 100644
--- a/arch/arm/dts/keystone-k2g.dtsi
+++ b/arch/arm/dts/keystone-k2g.dtsi
@@ -9,7 +9,6 @@
  */
 
 #include 
-#include "skeleton.dtsi"
 
 / {
model = "Texas Instruments K2G SoC";
@@ -17,6 +16,8 @@
#size-cells = <1>;
interrupt-parent = <>;
 
+   chosen { };
+
aliases {
serial0 = 
spi0 = 
-- 
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[U-Boot] [PATCH v2 18/30] ARM: k2g: Program DDRPHY_DATX8 registers via mask and value variables

[Franklin S Cooper Jr]

Different K2G evms may need to program the various
KS2_DDRPHY_DATX8_X_OFFSET registers in different ways. Therefore, use
the mask and val registers for each KS2_DDRPHY_DATAX_X_OFFSET to
properly program the register.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
---
 arch/arm/mach-keystone/ddr3.c | 32 +++-
 board/ti/ks2_evm/ddr3_k2g.c   | 14 ++
 2 files changed, 41 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c
index 25a9637..4cad6a2 100644
--- a/arch/arm/mach-keystone/ddr3.c
+++ b/arch/arm/mach-keystone/ddr3.c
@@ -65,11 +65,33 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config 
*phy_cfg)
;
 
if (cpu_is_k2g()) {
-   setbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1);
-   clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1);
-   clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1);
-   clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1);
-   clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1);
+   clrsetbits_le32(base + KS2_DDRPHY_DATX8_2_OFFSET,
+   phy_cfg->datx8_2_mask,
+   phy_cfg->datx8_2_val);
+
+   clrsetbits_le32(base + KS2_DDRPHY_DATX8_3_OFFSET,
+   phy_cfg->datx8_3_mask,
+   phy_cfg->datx8_3_val);
+
+   clrsetbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET,
+   phy_cfg->datx8_4_mask,
+   phy_cfg->datx8_4_val);
+
+   clrsetbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET,
+   phy_cfg->datx8_5_mask,
+   phy_cfg->datx8_5_val);
+
+   clrsetbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET,
+   phy_cfg->datx8_6_mask,
+   phy_cfg->datx8_6_val);
+
+   clrsetbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET,
+   phy_cfg->datx8_7_mask,
+   phy_cfg->datx8_7_val);
+
+   clrsetbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET,
+   phy_cfg->datx8_8_mask,
+   phy_cfg->datx8_8_val);
}
 
__raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
diff --git a/board/ti/ks2_evm/ddr3_k2g.c b/board/ti/ks2_evm/ddr3_k2g.c
index aeb7da6..3b12943 100644
--- a/board/ti/ks2_evm/ddr3_k2g.c
+++ b/board/ti/ks2_evm/ddr3_k2g.c
@@ -34,6 +34,20 @@ struct ddr3_phy_config ddr3phy_800_2g = {
.zq1cr1 = 0x0001005Bul,
.zq2cr1 = 0x0001005Bul,
.pir_v1 = 0x0033ul,
+   .datx8_2_mask   = 0,
+   .datx8_2_val= 0,
+   .datx8_3_mask   = 0,
+   .datx8_3_val= 0,
+   .datx8_4_mask   = 0,
+   .datx8_4_val= ((1 << 0)),
+   .datx8_5_mask   = DXEN_MASK,
+   .datx8_5_val= 0,
+   .datx8_6_mask   = DXEN_MASK,
+   .datx8_6_val= 0,
+   .datx8_7_mask   = DXEN_MASK,
+   .datx8_7_val= 0,
+   .datx8_8_mask   = DXEN_MASK,
+   .datx8_8_val= 0,
.pir_v2 = 0x0F81ul,
 };
 
-- 
2.10.0

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[U-Boot] [PATCH v2 08/30] arm: dts: Add new "generic" 66AK2Gx device tree file.

[Franklin S Cooper Jr]

With U-boot runtime board detect for DTB selection a "default" dtb needs
to be created. This will be used temporarily until the "proper" dtb is
selected.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
---

Version 2 changes:
Added -u-boot.dtsi with U-boot specific dts changes.

 arch/arm/dts/Makefile |  3 ++-
 arch/arm/dts/keystone-k2g-generic-u-boot.dtsi | 19 ++
 arch/arm/dts/keystone-k2g-generic.dts | 29 +++
 3 files changed, 50 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/keystone-k2g-generic-u-boot.dtsi
 create mode 100644 arch/arm/dts/keystone-k2g-generic.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e2c2584..63450f5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -354,7 +354,8 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
 dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \
keystone-k2e-evm.dtb \
-   keystone-k2g-evm.dtb
+   keystone-k2g-evm.dtb \
+   keystone-k2g-generic.dtb
 
 dtb-$(CONFIG_TARGET_AT91SAM9263EK) += at91sam9263ek.dtb
 
diff --git a/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi 
b/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi
new file mode 100644
index 000..4d073f3
--- /dev/null
+++ b/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/{
+   soc {
+   u-boot,dm-pre-reloc;
+   };
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/keystone-k2g-generic.dts 
b/arch/arm/dts/keystone-k2g-generic.dts
new file mode 100644
index 000..09a0bf7
--- /dev/null
+++ b/arch/arm/dts/keystone-k2g-generic.dts
@@ -0,0 +1,29 @@
+/*
+ * Device Tree Source for Generic 66AK2G0X EVM
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "keystone-k2g.dtsi"
+
+/ {
+   compatible = "ti,k2g-generic", "ti,k2g", "ti,keystone";
+   model = "Texas Instruments 66AK2G02 Generic";
+
+   chosen {
+   stdout-path = 
+   };
+};
+
+ {
+status = "okay";
+};
+
+ {
+status = "okay";
+};
+
-- 
2.10.0

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[U-Boot] [PATCH v2 26/30] ARM: dts: keystone-k2g-evm: Add unit address to memory node

[Franklin S Cooper Jr]

Upstream Linux has the unit address being added to the various 66AK2Gx
boards dts. Therefore, update the dts to mimic this change.

Also remove memory node from the base K2G dtsi file.

Signed-off-by: Franklin S Cooper Jr 
---
Version 2 changes:
This patch attempts to get the dts closer to what is used in the Linux
kernel

 arch/arm/dts/keystone-k2g-evm.dts | 5 +
 arch/arm/dts/keystone-k2g.dtsi| 5 -
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/keystone-k2g-evm.dts 
b/arch/arm/dts/keystone-k2g-evm.dts
index 2c99df4..f6fce33 100644
--- a/arch/arm/dts/keystone-k2g-evm.dts
+++ b/arch/arm/dts/keystone-k2g-evm.dts
@@ -18,6 +18,11 @@
chosen {
stdout-path = 
};
+
+   memory@8000 {
+   device_type = "memory";
+   reg = <0x8000 0x8000>;
+   };
 };
 
  {
diff --git a/arch/arm/dts/keystone-k2g.dtsi b/arch/arm/dts/keystone-k2g.dtsi
index f05afb7..7b2fae6 100644
--- a/arch/arm/dts/keystone-k2g.dtsi
+++ b/arch/arm/dts/keystone-k2g.dtsi
@@ -30,11 +30,6 @@
i2c2 = 
};
 
-   memory {
-   device_type = "memory";
-   reg = <0x8000 0x8000>;
-   };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
-- 
2.10.0

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[U-Boot] [PATCH v2 16/30] ARM: keystone2: Add additional fields used for DDR3 configuration

[Franklin S Cooper Jr]

Future boards will need to configure DDR3 registers in a slightly
different manner. Support this by defining additional variables and
defines that will be utilized later.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
---
 arch/arm/mach-keystone/include/mach/ddr3.h | 14 ++
 arch/arm/mach-keystone/include/mach/hardware.h |  3 +++
 2 files changed, 17 insertions(+)

diff --git a/arch/arm/mach-keystone/include/mach/ddr3.h 
b/arch/arm/mach-keystone/include/mach/ddr3.h
index 5feffe8..93789fd 100644
--- a/arch/arm/mach-keystone/include/mach/ddr3.h
+++ b/arch/arm/mach-keystone/include/mach/ddr3.h
@@ -35,6 +35,20 @@ struct ddr3_phy_config {
unsigned int zq1cr1;
unsigned int zq2cr1;
unsigned int pir_v1;
+   unsigned int datx8_2_mask;
+   unsigned int datx8_2_val;
+   unsigned int datx8_3_mask;
+   unsigned int datx8_3_val;
+   unsigned int datx8_4_mask;
+   unsigned int datx8_4_val;
+   unsigned int datx8_5_mask;
+   unsigned int datx8_5_val;
+   unsigned int datx8_6_mask;
+   unsigned int datx8_6_val;
+   unsigned int datx8_7_mask;
+   unsigned int datx8_7_val;
+   unsigned int datx8_8_mask;
+   unsigned int datx8_8_val;
unsigned int pir_v2;
 };
 
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h 
b/arch/arm/mach-keystone/include/mach/hardware.h
index 38d0190..1969a10 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -52,6 +52,8 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_DDRPHY_ZQ2CR1_OFFSET0x1A4
 #define KS2_DDRPHY_ZQ3CR1_OFFSET0x1B4
 
+#define KS2_DDRPHY_DATX8_2_OFFSET   0x240
+#define KS2_DDRPHY_DATX8_3_OFFSET   0x280
 #define KS2_DDRPHY_DATX8_4_OFFSET   0x2C0
 #define KS2_DDRPHY_DATX8_5_OFFSET   0x300
 #define KS2_DDRPHY_DATX8_6_OFFSET   0x340
@@ -70,6 +72,7 @@ typedef volatile unsigned int   *dv_reg_p;
 #define PDQ_MASK0x0070
 #define NOSRA_MASK  0x0800
 #define ECC_MASK0x0001
+#define DXEN_MASK   0x0001
 
 /* DDR3 definitions */
 #define KS2_DDR3A_EMIF_CTRL_BASE   0x2101
-- 
2.10.0

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[U-Boot] [PATCH v2 12/30] ARM: k2g: Define embedded_dtb_select for runtime DTB selection in U-boot

[Franklin S Cooper Jr]

For K2G, runtime DTB selection utilizes the embedded_dtb_select function.
Therefore, define the function which will perform a EEPROM read and then
retries selecting the correct dtb now that it can detect which board its
on. For other Keystone devices use an empty function since they will still
use the embedded FIT functionality but their FIT will only contain a single
dtb.

Most production K2G boards do not have their EEPROM programmed. Therefore,
perform a test to verify a K2G GP is currently being used and if it is then
set the values normally set by a EEPROM read.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
---
 board/ti/ks2_evm/board.c |  7 +++
 board/ti/ks2_evm/board_k2g.c | 38 ++
 2 files changed, 45 insertions(+)

diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 03254e1..4792311 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -277,3 +277,10 @@ void ft_board_setup_ex(void *blob, bd_t *bd)
ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
 }
 #endif /* CONFIG_OF_BOARD_SETUP */
+
+#if defined(CONFIG_DTB_RESELECT)
+int __weak embedded_dtb_select(void)
+{
+   return 0;
+}
+#endif
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index 21aec8f..4c3819d 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -11,9 +11,13 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include "mux-k2g.h"
 #include "../common/board_detect.h"
 
+#define K2G_GP_AUDIO_CODEC_ADDRESS 0x1B
+
 const unsigned int sysclk_array[MAX_SYSCLK] = {
1920,
2400,
@@ -210,6 +214,40 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#if defined(CONFIG_DTB_RESELECT)
+static int k2g_alt_board_detect(void)
+{
+   int rc;
+
+   rc = i2c_set_bus_num(1);
+   if (rc)
+   return rc;
+
+   rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
+   if (rc)
+   return rc;
+
+   ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
+
+   return 0;
+}
+
+int embedded_dtb_select(void)
+{
+   int rc;
+
+   rc = k2g_alt_board_detect();
+   if (rc) {
+   printf("Unable to do board detection\n");
+   return -1;
+   }
+
+   fdtdec_setup();
+
+   return 0;
+}
+#endif
+
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 
 static void k2g_reset_mux_config(void)
-- 
2.10.0

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[U-Boot] [PATCH v2 06/30] dts: Allow OF_LIST to depend on FIT_EMBED

[Franklin S Cooper Jr]

OF_LIST will be useable by SPL and U-boot. Therefore, update its
dependency to allow it to be enable by either SPL or U-boot specific
config option.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
Reviewed-by: Lokesh Vutla 
Acked-by: Andrew F. Davis 
---
 dts/Kconfig | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/dts/Kconfig b/dts/Kconfig
index 9a06221..7d688e8 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -79,14 +79,15 @@ config DEFAULT_DEVICE_TREE
 
 config OF_LIST
string "List of device tree files to include for DT control"
-   depends on SPL_LOAD_FIT
+   depends on SPL_LOAD_FIT || FIT_EMBED
default DEFAULT_DEVICE_TREE
help
  This option specifies a list of device tree files to use for DT
- control. These will be packaged into a FIT. At run-time, SPL will
- select the correct DT to use by examining the hardware (e.g.
- reading a board ID value). This is a list of device tree files
- (without the directory or .dtb suffix) separated by .
+ control. These will be packaged into a FIT. At run-time, U-boot
+ or SPL will select the correct DT to use by examining the
+ hardware (e.g. reading a board ID value). This is a list of
+ device tree files (without the directory or .dtb suffix)
+ separated by .
 
 config OF_SPL_REMOVE_PROPS
string "List of device tree properties to drop for SPL"
-- 
2.10.0

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[U-Boot] [PATCH v2 13/30] ARM: keystone2: Define board_fit_config_name_match for Keystone 2 boards

[Franklin S Cooper Jr]

Now with support for U-boot runtime dtb selection each board needs to
define board_fit_config_name_match so U-boot can determine what the
correct dtb is within the FIT blob.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
---
 board/ti/ks2_evm/board_k2e.c  | 10 ++
 board/ti/ks2_evm/board_k2g.c  | 14 ++
 board/ti/ks2_evm/board_k2hk.c | 10 ++
 board/ti/ks2_evm/board_k2l.c  | 10 ++
 4 files changed, 44 insertions(+)

diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
index 64f0c9c..266a66b 100644
--- a/board/ti/ks2_evm/board_k2e.c
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -166,6 +166,16 @@ int get_num_eth_ports(void)
 }
 #endif
 
+#if defined(CONFIG_FIT_EMBED)
+int board_fit_config_name_match(const char *name)
+{
+   if (!strcmp(name, "keystone-k2e-evm"))
+   return 0;
+
+   return -1;
+}
+#endif
+
 #if defined(CONFIG_BOARD_EARLY_INIT_F)
 int board_early_init_f(void)
 {
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index 4c3819d..d354415 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -214,6 +214,20 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#if defined(CONFIG_FIT_EMBED)
+int board_fit_config_name_match(const char *name)
+{
+   bool eeprom_read = board_ti_was_eeprom_read();
+
+   if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
+   return 0;
+   else if (!strcmp(name, "keystone-k2g-evm") && board_ti_is("66AK2GGP"))
+   return 0;
+   else
+   return -1;
+}
+#endif
+
 #if defined(CONFIG_DTB_RESELECT)
 static int k2g_alt_board_detect(void)
 {
diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c
index b35f24d..c733099 100644
--- a/board/ti/ks2_evm/board_k2hk.c
+++ b/board/ti/ks2_evm/board_k2hk.c
@@ -150,6 +150,16 @@ int board_early_init_f(void)
 }
 #endif
 
+#if defined(CONFIG_FIT_EMBED)
+int board_fit_config_name_match(const char *name)
+{
+   if (!strcmp(name, "keystone-k2hk-evm"))
+   return 0;
+
+   return -1;
+}
+#endif
+
 #ifdef CONFIG_SPL_BUILD
 void spl_init_keystone_plls(void)
 {
diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c
index f3eea42..166367b 100644
--- a/board/ti/ks2_evm/board_k2l.c
+++ b/board/ti/ks2_evm/board_k2l.c
@@ -138,6 +138,16 @@ int board_early_init_f(void)
 }
 #endif
 
+#if defined(CONFIG_FIT_EMBED)
+int board_fit_config_name_match(const char *name)
+{
+   if (!strcmp(name, "keystone-k2l-evm"))
+   return 0;
+
+   return -1;
+}
+#endif
+
 #ifdef CONFIG_SPL_BUILD
 void spl_init_keystone_plls(void)
 {
-- 
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[U-Boot] [PATCH v2 10/30] Makefile: Build additional binaries for dtb FIT blobs appended to U-boot

[Franklin S Cooper Jr]

Add additional make targets and options for building embedded FIT U-boot
images.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
---
 .gitignore |  1 +
 Makefile   | 18 --
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/.gitignore b/.gitignore
index 7fac5b3..29757aa 100644
--- a/.gitignore
+++ b/.gitignore
@@ -30,6 +30,7 @@
 #
 # Top-level generic files
 #
+fit-dtb.blob
 /MLO*
 /SPL*
 /System.map
diff --git a/Makefile b/Makefile
index bcab726..ec54c00 100644
--- a/Makefile
+++ b/Makefile
@@ -869,7 +869,21 @@ dts/dt.dtb: checkdtc u-boot
 quiet_cmd_copy = COPY$@
   cmd_copy = cp $< $@
 
-ifeq ($(CONFIG_OF_SEPARATE),y)
+ifeq ($(CONFIG_FIT_EMBED),y)
+
+fit-dtb.blob: dts/dt.dtb FORCE
+   $(call if_changed,mkimage)
+
+MKIMAGEFLAGS_fit-dtb.blob = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
+   -a 0 -e 0 -E \
+   $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) 
-d /dev/null
+
+u-boot-fit-dtb.bin: u-boot-nodtb.bin fit-dtb.blob
+   $(call if_changed,cat)
+
+u-boot.bin: u-boot-fit-dtb.bin FORCE
+   $(call if_changed,copy)
+else ifeq ($(CONFIG_OF_SEPARATE),y)
 u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE
$(call if_changed,cat)
 
@@ -1440,7 +1454,7 @@ CLEAN_DIRS  += $(MODVERDIR) \
$(filter-out include, $(shell ls -1 $d 2>/dev/null
 
 CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
-  boot* u-boot* MLO* SPL System.map
+  boot* u-boot* MLO* SPL System.map fit-dtb.blob
 
 # Directories & files removed with 'make mrproper'
 MRPROPER_DIRS  += include/config include/generated spl tpl \
-- 
2.10.0

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[U-Boot] [PATCH v2 17/30] ARM: k2g: Program DDR PHY MR2 register with the default value

[Franklin S Cooper Jr]

K2G GP doesn't require the MR2 register to be programed since the
default is good enough. However, newer K2G boards do need to change
this register value. Therefore, instead of not writing this register if
ran on a K2G board just program the value to be written to match the
default/reset value.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
---
 arch/arm/mach-keystone/ddr3.c | 3 +--
 board/ti/ks2_evm/ddr3_k2g.c   | 2 +-
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c
index ee8e12e..25a9637 100644
--- a/arch/arm/mach-keystone/ddr3.c
+++ b/arch/arm/mach-keystone/ddr3.c
@@ -52,8 +52,7 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config 
*phy_cfg)
__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
__raw_writel(phy_cfg->mr0,   base + KS2_DDRPHY_MR0_OFFSET);
__raw_writel(phy_cfg->mr1,   base + KS2_DDRPHY_MR1_OFFSET);
-   if (!cpu_is_k2g())
-   __raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);
+   __raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);
__raw_writel(phy_cfg->dtcr,  base + KS2_DDRPHY_DTCR_OFFSET);
__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
 
diff --git a/board/ti/ks2_evm/ddr3_k2g.c b/board/ti/ks2_evm/ddr3_k2g.c
index 344961d..aeb7da6 100644
--- a/board/ti/ks2_evm/ddr3_k2g.c
+++ b/board/ti/ks2_evm/ddr3_k2g.c
@@ -27,7 +27,7 @@ struct ddr3_phy_config ddr3phy_800_2g = {
.dtpr2  = 0x50022A00ul,
.mr0= 0x1430ul,
.mr1= 0x0006ul,
-   .mr2= 0x0018ul,
+   .mr2= 0xul,
.dtcr   = 0x710035C7ul,
.pgcr2  = 0x00F03D09ul,
.zq0cr1 = 0x0001005Dul,
-- 
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[U-Boot] [PATCH v2 03/30] boot_fit: Create helper functions that can be used to select DTB out of FIT

[Franklin S Cooper Jr]

Some platforms may append a FIT image to the U-boot image. This function
aids in parsing the FIT image and selecting the correct DTB at runtime.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
---
 common/Kconfig |  8 
 common/Makefile|  1 +
 common/boot_fit.c  | 58 ++
 include/boot_fit.h |  9 +
 include/image.h|  8 
 5 files changed, 84 insertions(+)
 create mode 100644 common/boot_fit.c
 create mode 100644 include/boot_fit.h

diff --git a/common/Kconfig b/common/Kconfig
index 1879aef..2429953 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -421,6 +421,14 @@ config SYS_STDIO_DEREGISTER
 
 endmenu
 
+config FIT_EMBED
+   bool "Support a FIT image embedded in the U-boot image"
+   default n
+   help
+ This option provides hooks to allow U-boot to parse an
+ appended FIT image and enable board specific code to then select
+ the correct DTB to be used.
+
 config DEFAULT_FDT_FILE
string "Default fdt file"
help
diff --git a/common/Makefile b/common/Makefile
index ccd8bbc..0c6209b 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -151,6 +151,7 @@ obj-y += image.o
 obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o
 obj-$(CONFIG_$(SPL_)OF_LIBFDT) += image-fdt.o
 obj-$(CONFIG_$(SPL_)FIT) += image-fit.o
+obj-$(CONFIG_FIT_EMBED) += boot_fit.o common_fit.o
 obj-$(CONFIG_$(SPL_)FIT_SIGNATURE) += image-sig.o
 obj-$(CONFIG_IO_TRACE) += iotrace.o
 obj-y += memsize.o
diff --git a/common/boot_fit.c b/common/boot_fit.c
new file mode 100644
index 000..ff26cf7
--- /dev/null
+++ b/common/boot_fit.c
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2017
+ * Texas Instruments, 
+ *
+ * Franklin S Cooper Jr. 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+int fdt_offset(void *fit)
+{
+   int fdt_offset, fdt_len;
+   int images;
+
+   images = fdt_path_offset(fit, FIT_IMAGES_PATH);
+   if (images < 0) {
+   debug("%s: Cannot find /images node: %d\n", __func__, images);
+   return -1;
+   }
+
+   /* Figure out which device tree the board wants to use */
+   fdt_len = fit_select_fdt(fit, images, _offset);
+
+   if (fdt_len < 0)
+   return fdt_len;
+
+   return fdt_offset;
+}
+
+void *locate_dtb_in_fit(void *fit)
+{
+   struct image_header *header;
+   int size;
+   int ret;
+
+   size = fdt_totalsize(fit);
+   size = (size + 3) & ~3;
+
+   header = (struct image_header *)fit;
+
+   if (image_get_magic(header) != FDT_MAGIC) {
+   debug("No FIT image appended to U-boot\n");
+   return NULL;
+   }
+
+   ret = fdt_offset(fit);
+
+   if (ret <= 0)
+   return NULL;
+   else
+   return (void *)fit+size+ret;
+}
diff --git a/include/boot_fit.h b/include/boot_fit.h
new file mode 100644
index 000..b7d2462
--- /dev/null
+++ b/include/boot_fit.h
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2017 Texas Instruments
+ * Written by Franklin Cooper Jr. 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+int fdt_offset(void *fit);
+void *locate_dtb_in_fit(void *fit);
diff --git a/include/image.h b/include/image.h
index 3f26f9b..1083578 100644
--- a/include/image.h
+++ b/include/image.h
@@ -18,6 +18,7 @@
 
 #include "compiler.h"
 #include 
+#include 
 
 /* Define this to avoid #ifdefs later on */
 struct lmb;
@@ -1274,6 +1275,13 @@ int board_fit_config_name_match(const char *name);
 void board_fit_image_post_process(void **p_image, size_t *p_size);
 #endif /* CONFIG_SPL_FIT_IMAGE_POST_PROCESS */
 
+#if IS_ENABLED(CONFIG_SPL_LOAD_FIT) || IS_ENABLED(CONFIG_FIT_EMBED)
+
+ulong fdt_getprop_u32(const void *fdt, int node, const char *prop);
+int fit_select_fdt(const void *fdt, int images, int *fdt_offsetp);
+
+#endif
+
 /**
  * Mapping of image types to function handlers to be invoked on the associated
  * loaded images
-- 
2.10.0

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[U-Boot] [PATCH v2 05/30] ti: common: board_detect: Add function to determine if EEPROM was read

[Franklin S Cooper Jr]

When the EEPROM is first read its contents are stored in memory as a
cache to avoid further I2C operations. To determine if the EEPROM was
previously read the easiest way is to check the memory to see if the
EEPROM's magic header value is set. Create a new function that can
determine if the EEPROM was previously read or not without having to
perform a I2C transaction.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
---
 board/ti/common/board_detect.c | 10 ++
 board/ti/common/board_detect.h |  9 +
 2 files changed, 19 insertions(+)

diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
index bf594cb..1da5ace 100644
--- a/board/ti/common/board_detect.c
+++ b/board/ti/common/board_detect.c
@@ -457,3 +457,13 @@ void board_ti_set_ethaddr(int index)
}
}
 }
+
+bool __maybe_unused board_ti_was_eeprom_read(void)
+{
+   struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+   if (ep->header == TI_EEPROM_HEADER_MAGIC)
+   return true;
+   else
+   return false;
+}
diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h
index e8d9484..893e1ed 100644
--- a/board/ti/common/board_detect.h
+++ b/board/ti/common/board_detect.h
@@ -206,6 +206,15 @@ void set_board_info_env(char *name);
 void board_ti_set_ethaddr(int index);
 
 /**
+ * board_ti_was_eeprom_read() - Check to see if the eeprom contents have been 
read
+ *
+ * This function is useful to determine if the eeprom has already been read and
+ * its contents have already been loaded into memory. It utiltzes the magic
+ * number that the header value is set to upon successful eeprom read.
+ */
+bool board_ti_was_eeprom_read(void);
+
+/**
  * ti_i2c_eeprom_am_set() - Setup the eeprom data with predefined values
  * @name:  Name of the board
  * @rev:   Revision of the board
-- 
2.10.0

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[U-Boot] [PATCH v2 02/30] spl: fit: Break out some functions into a common file

[Franklin S Cooper Jr]

Some of the functions within spl_fit will be used for non spl purposes.
Instead of duplicating functions simply break the functions to be reused
into its own file.

Signed-off-by: Franklin S Cooper Jr 
Reviewed-by: Tom Rini 
Reviewed-by: Simon Glass 
---
 common/Makefile  |  1 +
 common/common_fit.c  | 86 
 common/spl/spl_fit.c | 76 +-
 3 files changed, 88 insertions(+), 75 deletions(-)
 create mode 100644 common/common_fit.c

diff --git a/common/Makefile b/common/Makefile
index 14d0184..ccd8bbc 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -95,6 +95,7 @@ obj-$(CONFIG_SPL_DFU_SUPPORT) += cli_hush.o
 obj-$(CONFIG_SPL_HASH_SUPPORT) += hash.o
 obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
 obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
+obj-$(CONFIG_SPL_LOAD_FIT) += common_fit.o
 obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
 obj-$(CONFIG_SPL_OF_LIBFDT) += fdt_support.o
 ifdef CONFIG_SPL_USB_HOST_SUPPORT
diff --git a/common/common_fit.c b/common/common_fit.c
new file mode 100644
index 000..a08af72
--- /dev/null
+++ b/common/common_fit.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+ulong fdt_getprop_u32(const void *fdt, int node, const char *prop)
+{
+   const u32 *cell;
+   int len;
+
+   cell = fdt_getprop(fdt, node, prop, );
+   if (len != sizeof(*cell))
+   return -1U;
+   return fdt32_to_cpu(*cell);
+}
+
+int fit_select_fdt(const void *fdt, int images, int *fdt_offsetp)
+{
+   const char *name, *fdt_name;
+   int conf, node, fdt_node;
+   int len;
+
+   *fdt_offsetp = 0;
+   conf = fdt_path_offset(fdt, FIT_CONFS_PATH);
+   if (conf < 0) {
+   debug("%s: Cannot find /configurations node: %d\n", __func__,
+ conf);
+   return -EINVAL;
+   }
+   for (node = fdt_first_subnode(fdt, conf);
+node >= 0;
+node = fdt_next_subnode(fdt, node)) {
+   name = fdt_getprop(fdt, node, "description", );
+   if (!name) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+   printf("%s: Missing FDT description in DTB\n",
+  __func__);
+#endif
+   return -EINVAL;
+   }
+   if (board_fit_config_name_match(name))
+   continue;
+
+   debug("Selecting config '%s'", name);
+   fdt_name = fdt_getprop(fdt, node, FIT_FDT_PROP, );
+   if (!fdt_name) {
+   debug("%s: Cannot find fdt name property: %d\n",
+ __func__, len);
+   return -EINVAL;
+   }
+
+   debug(", fdt '%s'\n", fdt_name);
+   fdt_node = fdt_subnode_offset(fdt, images, fdt_name);
+   if (fdt_node < 0) {
+   debug("%s: Cannot find fdt node '%s': %d\n",
+ __func__, fdt_name, fdt_node);
+   return -EINVAL;
+   }
+
+   *fdt_offsetp = fdt_getprop_u32(fdt, fdt_node, "data-offset");
+   len = fdt_getprop_u32(fdt, fdt_node, "data-size");
+   debug("FIT: Selected '%s'\n", name);
+
+   return len;
+   }
+
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+   printf("No matching DT out of these options:\n");
+   for (node = fdt_first_subnode(fdt, conf);
+node >= 0;
+node = fdt_next_subnode(fdt, node)) {
+   name = fdt_getprop(fdt, node, "description", );
+   printf("   %s\n", name);
+   }
+#endif
+
+   return -ENOENT;
+}
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index aae556f..3a722d3 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -11,80 +11,6 @@
 #include 
 #include 
 
-static ulong fdt_getprop_u32(const void *fdt, int node, const char *prop)
-{
-   const u32 *cell;
-   int len;
-
-   cell = fdt_getprop(fdt, node, prop, );
-   if (len != sizeof(*cell))
-   return -1U;
-   return fdt32_to_cpu(*cell);
-}
-
-static int spl_fit_select_fdt(const void *fdt, int images, int *fdt_offsetp)
-{
-   const char *name, *fdt_name;
-   int conf, node, fdt_node;
-   int len;
-
-   *fdt_offsetp = 0;
-   conf = fdt_path_offset(fdt, FIT_CONFS_PATH);
-   if (conf < 0) {
-   debug("%s: Cannot find /configurations node: %d\n", __func__,
- conf);
-   return -EINVAL;
-   }
-   for (node = fdt_first_subnode(fdt, conf);
-node >= 0;
-node = fdt_next_subnode(fdt, node)) {
-   name = fdt_getprop(fdt, node, "description", );
- 

[U-Boot] [PATCH v2 00/30] ARM: k2g: Add support for new K2G ICE EVM.

[Franklin S Cooper Jr]

This patchset adds support for the new Keystone 2 Industrial Communication
Engine board.

This patchset includes the introduction of embedded FIT images in U-boot.
This creates a FIT image of dtb files that enables board specific code to
select which DTB to use at runtime. Initially during boot a generic DTB is
required that enables board detection to occur and once it has can later be
swapped out for the correct dtb.

Version 2 changes:
Some patches were dropped since equivalent changes have already be
incorporated in upstream already.

The addition davinci i2c device model in upstream resulted in some
patches having to be added or tweaked.

The DT for K2G ICE is based on the version that has been accepted into
Linux mainline https://lkml.org/lkml/2017/5/22/28

Franklin S Cooper Jr (29):
  spl: fit: Break out some functions into a common file
  boot_fit: Create helper functions that can be used to select DTB out
of FIT
  fdt: Enable selecting correct DTB from appended FIT Image
  ti: common: board_detect: Add function to determine if EEPROM was read
  dts: Allow OF_LIST to depend on FIT_EMBED
  ARM: dts: k2g: Introduce U-boot specific dtsi file
  arm: dts: Add new "generic" 66AK2Gx device tree file.
  board_f: Add new function to allow runtime DTB selection
  Makefile: Build additional binaries for dtb FIT blobs appended to
U-boot
  ARM: keystone2: Allow to build with all image formats
  ARM: k2g: Define embedded_dtb_select for runtime DTB selection in
U-boot
  ARM: keystone2: Define board_fit_config_name_match for Keystone 2
boards
  ks2_evm: Add EEPROM based board detection
  defconfig: keystone2: Enable U-boot runtime DTB detection
  ARM: keystone2: Add additional fields used for DDR3 configuration
  ARM: k2g: Program DDR PHY MR2 register with the default value
  ARM: k2g: Program DDRPHY_DATX8 registers via mask and value variables
  ks2_evm: Add EEPROM based board detection helper functions
  ARM: k2g: Add pinmux support for K2G ICE evm
  ARM: k2g: Add DDR3 configuration for K2G ICE evm
  board: ks2: Use board detection to wrap code not specific to K2G ICE
evm
  ARM: k2g: Use board detection to wrap K2G GP specific calls
  ARM: k2g: Update board_name u-boot env variable at runtime
  ARM: dts: keystone-k2g: Remove skeleton.dtsi
  ARM: dts: keystone-k2g-evm: Add unit address to memory node
  ARM: dts: k2g: Disable netcp by default
  ARM: dts: k2g: Add DT support for K2G Industrial Communication Engine
evm
  ARM: k2g: Add K2G ICE DTB to the list of possible DTBs
  defconfig: k2g_evm_defconfig: Add K2G ICE to OF_LIST

Nishanth Menon (1):
  ti: common: board_detect: Allow settings board detection variables
manually

 .gitignore |  1 +
 Makefile   | 18 +-
 arch/arm/dts/Makefile  |  4 +-
 arch/arm/dts/keystone-k2g-evm-u-boot.dtsi  | 19 ++
 arch/arm/dts/keystone-k2g-evm.dts  |  9 +++
 arch/arm/dts/keystone-k2g-generic-u-boot.dtsi  | 19 ++
 arch/arm/dts/keystone-k2g-generic.dts  | 29 +
 arch/arm/dts/keystone-k2g-ice-u-boot.dtsi  | 19 ++
 arch/arm/dts/keystone-k2g-ice.dts  | 36 +++
 arch/arm/dts/keystone-k2g-netcp.dtsi   |  1 +
 arch/arm/dts/keystone-k2g.dtsi |  8 +--
 arch/arm/mach-keystone/config.mk   |  4 +-
 arch/arm/mach-keystone/ddr3.c  | 35 ---
 arch/arm/mach-keystone/include/mach/ddr3.h | 14 +
 arch/arm/mach-keystone/include/mach/hardware.h |  3 +
 board/ti/common/board_detect.c | 34 ++
 board/ti/common/board_detect.h | 26 
 board/ti/ks2_evm/board.c   | 21 +--
 board/ti/ks2_evm/board.h   | 21 +++
 board/ti/ks2_evm/board_k2e.c   | 10 +++
 board/ti/ks2_evm/board_k2g.c   | 86 +++---
 board/ti/ks2_evm/board_k2hk.c  | 10 +++
 board/ti/ks2_evm/board_k2l.c   | 10 +++
 board/ti/ks2_evm/ddr3_k2g.c| 78 ++-
 board/ti/ks2_evm/mux-k2g.h | 45 +-
 common/Kconfig | 18 ++
 common/Makefile|  2 +
 common/board_f.c   |  3 +
 common/boot_fit.c  | 58 +
 common/common_fit.c| 86 ++
 common/spl/spl_fit.c   | 76 +--
 configs/k2e_evm_defconfig  |  3 +
 configs/k2g_evm_defconfig  |  3 +
 configs/k2hk_evm_defconfig |  3 +
 configs/k2l_evm_defconfig  |  3 +
 dts/Kconfig| 11 ++--
 include/boot_fit.h |  9 +++
 include/common.h  

Re: [U-Boot] [PATCH v2 0/4] sunxi: Add support for NanoPi M1

[Jagan Teki]

On Wed, May 10, 2017 at 11:56 AM, Mylène Josserand
 wrote:
> Hi everyone,
>
> Here is a V2 of the support of the Sun8i NanoPi M1 platform.
> I created a patch serie instead on a standalone patch
> because the kernel device tree for Nanopi uses a dtsi file
> that does not exist in u-boot. This dtsi will be added in
> this serie.
>
> Changes since V1:
> - Added the NanoPi dtsi from the kernel device tree
> - Updated the NanoPi Neo device tree to use the dtsi
> - Updated the dtsi from the kernel reference to remove the
> gpio-keys to be able to use this dtsi file for the
> NanoPi Neo Air. I will send this patch to the kernel if this
> modification make sense.
> - Updated the NanoPi Neo Air to use the dtsi
>
> Patch01: Add the support of the NanoPi M1 platform. Based from the kernel
> device tree so the NanoPi dtsi file is also added.
> Patch02: Update the NanoPi Neo to use the dtsi to be close to the one from
> the kernel.
> Patch03: Move the gpio-keys to the dts file to have a generic dtsi file and
> be able to use it for the NanoPi Neo Air.
> Patch04: Update the NanoPi Neo Air device tree file to use the dtsi one.
>
> Thank you in advance for your reviews/comments.
>
> Best regards,
>
> Mylène Josserand (4):
>   sunxi: Add support for NanoPi M1
>   sunxi: Update NanoPi Neo to use dtsi

These two are IN at linux-next and look good.

Reviewed-by: Jagan Teki 

thanks!
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Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH] sunxi: Use uart0 as console for Sinlinx SinA33

[Jagan Teki]

On Wed, May 10, 2017 at 12:39 AM, Maxime Ripard
 wrote:
> On Sun, May 07, 2017 at 03:51:17PM +0800, Chen-Yu Tsai wrote:
>> On the A33, uart0 is muxed on the PB pins. On SBCs these pins may be
>> available for use. Such is the case on the Sinlinx SinA33.
>>
>> Set CONS_INDEX=1 to use uart0 as the console, matching the device tree.
>>
>> Fixes: 7095f8641863 ("sunxi: Convert CONS_INDEX to Kconfig")
>> Signed-off-by: Chen-Yu Tsai 
>
> Acked-by: Maxime Ripard 

Reviewed-by: Jagan Teki 

Applied to u-boot-sunxi/master

thanks!
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Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH 1/2][v2] armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support

[york sun]

On 04/27/2017 02:38 AM, Priyanka Jain wrote:
> The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A-72 CPUs and
> is built on layerscape architecture.
>
> It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A).
> So feature-wise it is same as LS2084A.

Please clarify what is 40-pin derivative?

York

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Re: [U-Boot] [PATCH] LS1012A: change the size of flash

[york sun]

On 04/25/2017 02:20 AM, Suresh Gupta wrote:
> LS1012A has S25FS512S flash of 64M size
>
> Signed-off-by: Suresh Gupta 
> ---
>  include/configs/ls1012a_common.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/configs/ls1012a_common.h 
> b/include/configs/ls1012a_common.h
> index 0db926f..861cbc3 100644
> --- a/include/configs/ls1012a_common.h
> +++ b/include/configs/ls1012a_common.h
> @@ -56,7 +56,7 @@
>  #define QSPI0_AMBA_BASE  0x4000
>  #define CONFIG_SPI_FLASH_SPANSION
>
> -#define FSL_QSPI_FLASH_SIZE  (1 << 24)
> +#define FSL_QSPI_FLASH_SIZE  SZ_64M
>  #define FSL_QSPI_FLASH_NUM   2
>
>  /*
>

Suresh,

LS1012A doesn't have any flash built-in. Do you mean all boards 
supporting LS1012A have the same flash chip with 64MB in size? Please 
clarify.

York

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