Re: [U-Boot] [PATCH 2/2] Convert CONFIG_SYS_I2C_BUS_MAX to Kconfig

[Heiko Schocher]

Hello Adam,

Am 11.08.2017 um 13:39 schrieb Adam Ford:

This converts the following to Kconfig:
CONFIG_SYS_I2C_BUS_MAX

Signed-off-by: Adam Ford 
---
  arch/arm/include/asm/arch-am33xx/i2c.h |  1 -
  arch/arm/include/asm/arch-omap3/i2c.h  |  1 -
  arch/arm/include/asm/arch-omap4/i2c.h  |  1 -
  arch/arm/include/asm/arch-omap5/i2c.h  |  1 -
  drivers/i2c/Kconfig| 10 ++
  include/configs/socfpga_common.h   |  1 -
  include/configs/ti_armv7_keystone2.h   |  1 -
  7 files changed, 10 insertions(+), 6 deletions(-)



Reviewed-by: Heiko Schocher 

bye,
Heiko
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[U-Boot] [PATCH 09/13] x86: Add Intel Braswell SoC support

[Bin Meng]

This adds initial Intel Braswell SoC support. It uses Intel FSP
to initialize the chipset.

Similar to its predecessor BayTrail, there are some work to do to
enable the legacy UART integrated in the Braswell SoC.

Signed-off-by: Bin Meng 
---

 arch/x86/Kconfig   |   1 +
 arch/x86/cpu/Makefile  |   1 +
 arch/x86/cpu/braswell/Kconfig  |  38 +++
 arch/x86/cpu/braswell/Makefile |   7 ++
 arch/x86/cpu/braswell/braswell.c   |  36 ++
 arch/x86/cpu/braswell/cpu.c| 170 +
 arch/x86/cpu/braswell/early_uart.c |  86 +++
 arch/x86/include/asm/arch-braswell/iomap.h |  50 +
 8 files changed, 389 insertions(+)
 create mode 100644 arch/x86/cpu/braswell/Kconfig
 create mode 100644 arch/x86/cpu/braswell/Makefile
 create mode 100644 arch/x86/cpu/braswell/braswell.c
 create mode 100644 arch/x86/cpu/braswell/cpu.c
 create mode 100644 arch/x86/cpu/braswell/early_uart.c
 create mode 100644 arch/x86/include/asm/arch-braswell/iomap.h

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index f72d307..9620764 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -108,6 +108,7 @@ source "board/intel/Kconfig"
 
 # platform-specific options below
 source "arch/x86/cpu/baytrail/Kconfig"
+source "arch/x86/cpu/braswell/Kconfig"
 source "arch/x86/cpu/broadwell/Kconfig"
 source "arch/x86/cpu/coreboot/Kconfig"
 source "arch/x86/cpu/ivybridge/Kconfig"
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 999429e..94cdff1 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -27,6 +27,7 @@ endif
 
 obj-y += intel_common/
 obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
+obj-$(CONFIG_INTEL_BRASWELL) += braswell/
 obj-$(CONFIG_INTEL_BROADWELL) += broadwell/
 obj-$(CONFIG_SYS_COREBOOT) += coreboot/
 obj-$(CONFIG_EFI_APP) += efi/
diff --git a/arch/x86/cpu/braswell/Kconfig b/arch/x86/cpu/braswell/Kconfig
new file mode 100644
index 000..c993889
--- /dev/null
+++ b/arch/x86/cpu/braswell/Kconfig
@@ -0,0 +1,38 @@
+#
+# Copyright (C) 2017, Bin Meng 
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+config INTEL_BRASWELL
+   bool
+   select HAVE_FSP
+   select ARCH_MISC_INIT
+   imply HAVE_INTEL_ME
+   imply HAVE_VBT
+   imply ENABLE_MRC_CACHE
+   imply ENV_IS_IN_SPI_FLASH
+   imply AHCI_PCI
+   imply ICH_SPI
+   imply MMC
+   imply MMC_PCI
+   imply MMC_SDHCI
+   imply MMC_SDHCI_SDMA
+   imply SCSI
+   imply SPI_FLASH
+   imply SYS_NS16550
+   imply USB
+   imply USB_XHCI_HCD
+   imply VIDEO_FSP
+
+if INTEL_BRASWELL
+
+config FSP_ADDR
+   hex
+   default 0xfff2
+
+config FSP_LOCKDOWN_SPI
+   bool
+   default y
+
+endif
diff --git a/arch/x86/cpu/braswell/Makefile b/arch/x86/cpu/braswell/Makefile
new file mode 100644
index 000..19bcee6
--- /dev/null
+++ b/arch/x86/cpu/braswell/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2017, Bin Meng 
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += braswell.o cpu.o early_uart.o
diff --git a/arch/x86/cpu/braswell/braswell.c b/arch/x86/cpu/braswell/braswell.c
new file mode 100644
index 000..37099aa
--- /dev/null
+++ b/arch/x86/cpu/braswell/braswell.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2017, Bin Meng 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+int arch_cpu_init(void)
+{
+   post_code(POST_CPU_INIT);
+
+   return x86_cpu_init_f();
+}
+
+int arch_misc_init(void)
+{
+#ifdef CONFIG_ENABLE_MRC_CACHE
+   /*
+* We intend not to check any return value here, as even MRC cache
+* is not saved successfully, it is not a severe error that will
+* prevent system from continuing to boot.
+*/
+   mrccache_save();
+#endif
+
+   return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+   /* cold reset */
+   x86_full_reset();
+}
diff --git a/arch/x86/cpu/braswell/cpu.c b/arch/x86/cpu/braswell/cpu.c
new file mode 100644
index 000..6ff9036
--- /dev/null
+++ b/arch/x86/cpu/braswell/cpu.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2017, Bin Meng 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * Derived from arch/x86/cpu/baytrail/cpu.c
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static const unsigned int braswell_bus_freq_table[] = {
+   8333,
+   1,
+   1,
+   11666,
+   8000,
+   9333,
+   9000,
+   8890,
+   8750
+};
+
+static unsigned int braswell_bus_freq(void)
+{
+   msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL);
+
+   if ((clk_info.lo & 0xf) < (ARRAY_SIZE(braswell_bus_freq_table)))
+   return braswell_bus_freq_table[clk_info.lo & 0xf];
+
+   return 0;
+}
+
+static unsigned 

[U-Boot] [PATCH 05/13] tools: binman: Add a new entry type for Intel VBT

[Bin Meng]

This adds a new entry type for Intel Video BIOS Table.

Signed-off-by: Bin Meng 
---

 tools/binman/etype/intel_vbt.py| 14 ++
 tools/binman/func_test.py  |  9 -
 tools/binman/test/46_intel-vbt.dts | 14 ++
 3 files changed, 36 insertions(+), 1 deletion(-)
 create mode 100644 tools/binman/etype/intel_vbt.py
 create mode 100644 tools/binman/test/46_intel-vbt.dts

diff --git a/tools/binman/etype/intel_vbt.py b/tools/binman/etype/intel_vbt.py
new file mode 100644
index 000..29aedaf
--- /dev/null
+++ b/tools/binman/etype/intel_vbt.py
@@ -0,0 +1,14 @@
+#
+# Copyright (C) 2017, Bin Meng 
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for Intel Video BIOS Table binary blob
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_intel_vbt(Entry_blob):
+def __init__(self, image, etype, node):
+Entry_blob.__init__(self, image, etype, node)
diff --git a/tools/binman/func_test.py b/tools/binman/func_test.py
index 8b4db41..c4207ce 100644
--- a/tools/binman/func_test.py
+++ b/tools/binman/func_test.py
@@ -38,6 +38,7 @@ X86_START16_DATA= 'start16'
 U_BOOT_NODTB_DATA   = 'nodtb with microcode pointer somewhere in here'
 FSP_DATA= 'fsp'
 CMC_DATA= 'cmc'
+VBT_DATA= 'vbt'
 
 class TestFunctional(unittest.TestCase):
 """Functional tests for binman
@@ -74,6 +75,7 @@ class TestFunctional(unittest.TestCase):
 TestFunctional._MakeInputFile('u-boot-nodtb.bin', U_BOOT_NODTB_DATA)
 TestFunctional._MakeInputFile('fsp.bin', FSP_DATA)
 TestFunctional._MakeInputFile('cmc.bin', CMC_DATA)
+TestFunctional._MakeInputFile('vbt.bin', VBT_DATA)
 self._output_setup = False
 
 # ELF file with a '_dt_ucode_base_size' symbol
@@ -801,6 +803,11 @@ class TestFunctional(unittest.TestCase):
 self.assertEqual(FSP_DATA, data[:len(FSP_DATA)])
 
 def testPackCmc(self):
-"""Test that an image with a FSP binary can be created"""
+"""Test that an image with a CMC binary can be created"""
 data = self._DoReadFile('43_intel-cmc.dts')
 self.assertEqual(CMC_DATA, data[:len(CMC_DATA)])
+
+def testPackVbt(self):
+"""Test that an image with a VBT binary can be created"""
+data = self._DoReadFile('46_intel-vbt.dts')
+self.assertEqual(VBT_DATA, data[:len(VBT_DATA)])
diff --git a/tools/binman/test/46_intel-vbt.dts 
b/tools/binman/test/46_intel-vbt.dts
new file mode 100644
index 000..733f575
--- /dev/null
+++ b/tools/binman/test/46_intel-vbt.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   binman {
+   size = <16>;
+
+   intel-vbt {
+   filename = "vbt.bin";
+   };
+   };
+};
-- 
2.9.2

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[U-Boot] [PATCH 13/13] x86: Support Intel Cherry Hill board

[Bin Meng]

This adds support to Intel Cherry Hill board, a board based on
Intel Braswell SoC. The following devices are validated:

- serial port as the serial console
- on-board Realtek 8169 ethernet controller
- SATA AHCI controller
- EMMC/SDHC controller
- USB 3.0 xHCI controller
- PCIe x1 slot with a graphics card
- ICH SPI controller with an 8MB Macronix SPI flash
- Integrated graphics device as the video console

Signed-off-by: Bin Meng 

---

 arch/x86/dts/Makefile   |   1 +
 arch/x86/dts/cherryhill.dts | 215 +
 board/intel/Kconfig |  10 +
 board/intel/cherryhill/Kconfig  |  25 ++
 board/intel/cherryhill/MAINTAINERS  |   6 +
 board/intel/cherryhill/Makefile |   7 +
 board/intel/cherryhill/cherryhill.c | 596 
 board/intel/cherryhill/start.S  |   9 +
 configs/cherryhill_defconfig|  36 +++
 doc/README.x86  |  30 ++
 include/configs/cherryhill.h|  22 ++
 11 files changed, 957 insertions(+)
 create mode 100644 arch/x86/dts/cherryhill.dts
 create mode 100644 board/intel/cherryhill/Kconfig
 create mode 100644 board/intel/cherryhill/MAINTAINERS
 create mode 100644 board/intel/cherryhill/Makefile
 create mode 100644 board/intel/cherryhill/cherryhill.c
 create mode 100644 board/intel/cherryhill/start.S
 create mode 100644 configs/cherryhill_defconfig
 create mode 100644 include/configs/cherryhill.h

diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 6589495..6d0c4b6 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -3,6 +3,7 @@
 #
 
 dtb-y += bayleybay.dtb \
+   cherryhill.dtb \
chromebook_link.dtb \
chromebox_panther.dtb \
chromebook_samus.dtb \
diff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts
new file mode 100644
index 000..1ccb605
--- /dev/null
+++ b/arch/x86/dts/cherryhill.dts
@@ -0,0 +1,215 @@
+/*
+ * Copyright (C) 2017, Bin Meng 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include 
+#include 
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+   model = "Intel Cherry Hill";
+   compatible = "intel,cherryhill", "intel,braswell";
+
+   aliases {
+   serial0 = 
+   spi0 = 
+   };
+
+   config {
+   silent_console = <0>;
+   };
+
+   chosen {
+   stdout-path = "/serial";
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "intel,braswell-cpu";
+   reg = <0>;
+   intel,apic-id = <0>;
+   };
+
+   cpu@1 {
+   device_type = "cpu";
+   compatible = "intel,braswell-cpu";
+   reg = <1>;
+   intel,apic-id = <2>;
+   };
+
+   cpu@2 {
+   device_type = "cpu";
+   compatible = "intel,braswell-cpu";
+   reg = <2>;
+   intel,apic-id = <4>;
+   };
+
+   cpu@3 {
+   device_type = "cpu";
+   compatible = "intel,braswell-cpu";
+   reg = <3>;
+   intel,apic-id = <6>;
+   };
+   };
+
+   pci {
+   compatible = "pci-x86";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   u-boot,dm-pre-reloc;
+   ranges = <0x0200 0x0 0x8000 0x8000 0 0x4000
+ 0x4200 0x0 0xc000 0xc000 0 0x2000
+ 0x0100 0x0 0x2000 0x2000 0 0xe000>;
+
+   pch@1f,0 {
+   reg = <0xf800 0 0 0 0>;
+   compatible = "intel,pch9";
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   irq-router {
+   compatible = "intel,irq-router";
+   intel,pirq-config = "ibase";
+   intel,ibase-offset = <0x50>;
+   intel,pirq-link = <8 8>;
+   intel,pirq-mask = <0xdee0>;
+   intel,pirq-routing = <
+   /* Braswell PCI devices */
+   PCI_BDF(0, 2, 0) INTA PIRQA
+   PCI_BDF(0, 3, 0) INTA PIRQA
+   PCI_BDF(0, 11, 0) INTA PIRQA
+   PCI_BDF(0, 16, 0) INTA PIRQA
+   PCI_BDF(0, 17, 0) INTA PIRQA
+   

[U-Boot] [PATCH 07/13] x86: dm: video: Add a framebuffer driver that utilizes VBT

[Bin Meng]

When a VBT is given to an FSP that supports graphics initialization,
the FSP will produce a graphics info HOB that contains all necessary
information for the linear frame buffer of the integrated graphics
device. This adds a DM video driver for it.

Signed-off-by: Bin Meng 
---

 arch/x86/Kconfig|   8 +++
 arch/x86/lib/fsp/Makefile   |   1 +
 arch/x86/lib/fsp/fsp_graphics.c | 124 
 3 files changed, 133 insertions(+)
 create mode 100644 arch/x86/lib/fsp/fsp_graphics.c

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index b0d3266..f72d307 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -585,6 +585,14 @@ config VBT_ADDR
  example, base address of 0xfff9 indicates that the image will
  be put at offset 0x9 from the beginning of a 1MB flash device.
 
+config VIDEO_FSP
+   bool "Enable FSP framebuffer driver support"
+   depends on HAVE_VBT && DM_VIDEO
+   help
+ Turn on this option to enable a framebuffer driver when U-Boot is
+ using Video BIOS Table (VBT) image for FSP firmware to initialize
+ the integrated graphics device.
+
 config ROM_TABLE_ADDR
hex
default 0xf
diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile
index 3ea4880..afe83dd3 100644
--- a/arch/x86/lib/fsp/Makefile
+++ b/arch/x86/lib/fsp/Makefile
@@ -8,4 +8,5 @@ obj-y += cmd_fsp.o
 obj-y += fsp_car.o
 obj-y += fsp_common.o
 obj-y += fsp_dram.o
+obj-$(CONFIG_VIDEO_FSP) += fsp_graphics.o
 obj-y += fsp_support.o
diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c
new file mode 100644
index 000..a19b067
--- /dev/null
+++ b/arch/x86/lib/fsp/fsp_graphics.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2017, Bin Meng 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pixel {
+   u8 pos;
+   u8 size;
+};
+
+static const struct fsp_framebuffer {
+   struct pixel red;
+   struct pixel green;
+   struct pixel blue;
+   struct pixel rsvd;
+} fsp_framebuffer_format_map[] = {
+   [pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} },
+   [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} },
+};
+
+static int save_vesa_mode(struct vesa_mode_info *vesa)
+{
+   const struct hob_graphics_info *ginfo;
+   const struct fsp_framebuffer *fbinfo;
+
+   ginfo = fsp_get_graphics_info(gd->arch.hob_list, NULL);
+
+   /*
+* If there is no graphics info structure, bail out and keep
+* running on the serial console.
+*/
+   if (!ginfo) {
+   debug("FSP graphics hand-off block not found\n");
+   return -ENXIO;
+   }
+
+   vesa->x_resolution = ginfo->width;
+   vesa->y_resolution = ginfo->height;
+   vesa->bits_per_pixel = 32;
+   vesa->bytes_per_scanline = ginfo->pixels_per_scanline * 4;
+   vesa->phys_base_ptr = ginfo->fb_base;
+
+   if (ginfo->pixel_format >= pixel_bitmask) {
+   debug("FSP set unknown framebuffer format: %d\n",
+ ginfo->pixel_format);
+   return -EINVAL;
+   }
+   fbinfo = _framebuffer_format_map[ginfo->pixel_format];
+   vesa->red_mask_size = fbinfo->red.size;
+   vesa->red_mask_pos = fbinfo->red.pos;
+   vesa->green_mask_size = fbinfo->green.size;
+   vesa->green_mask_pos = fbinfo->green.pos;
+   vesa->blue_mask_size = fbinfo->blue.size;
+   vesa->blue_mask_pos = fbinfo->blue.pos;
+   vesa->reserved_mask_size = fbinfo->rsvd.size;
+   vesa->reserved_mask_pos = fbinfo->rsvd.pos;
+
+   return 0;
+}
+
+static int fsp_video_probe(struct udevice *dev)
+{
+   struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+   struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+   struct vesa_mode_info *vesa = _info.vesa;
+   int ret;
+
+   printf("Video: ");
+
+   /* Initialize vesa_mode_info structure */
+   ret = save_vesa_mode(vesa);
+   if (ret)
+   goto err;
+
+   /*
+* The framebuffer base address in the FSP graphics info HOB reflects
+* the value assigned by the FSP. After PCI enumeration the framebuffer
+* base address may be relocated. Let's get the updated one from device.
+*
+* For IGD, it seems to be always on BAR2.
+*/
+   vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2);
+
+   ret = vbe_setup_video_priv(vesa, uc_priv, plat);
+   if (ret)
+   goto err;
+
+   printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
+  vesa->bits_per_pixel);
+
+   return 0;
+
+err:
+   printf("No video mode configured in FSP!\n");
+   return ret;
+}
+
+static const struct udevice_id fsp_video_ids[] = {
+   { .compatible = "fsp-fb" },
+   { }
+};
+
+U_BOOT_DRIVER(fsp_video) = {
+ 

[U-Boot] [PATCH 12/13] x86: braswell: Disable PUNIT power configuration for B0 stepping

[Bin Meng]

FSP's built-in UPD configuration enables PUNIT power configuration,
but on B0 stepping, this causes CPU hangs in fsp_init(). Disable it.

Signed-off-by: Bin Meng 
---

 arch/x86/cpu/braswell/fsp_configs.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/x86/cpu/braswell/fsp_configs.c 
b/arch/x86/cpu/braswell/fsp_configs.c
index d984519..249f851 100644
--- a/arch/x86/cpu/braswell/fsp_configs.c
+++ b/arch/x86/cpu/braswell/fsp_configs.c
@@ -139,6 +139,12 @@ void update_fsp_configs(struct fsp_config_data *config,
 #endif
update_fsp_gpio_configs(_upd->gpio_familiy_ptr,
_upd->gpio_pad_ptr);
+   /*
+* For Braswell B0 stepping, disable_punit_pwr_config must be set to 1
+* otherwise it just hangs in fsp_init().
+*/
+   if (gd->arch.x86_mask == 2)
+   silicon_upd->disable_punit_pwr_config = 1;
silicon_upd->emmc_mode = fdtdec_get_int(blob, node,
"fsp,emmc-mode", EMMC_MODE_PCI);
silicon_upd->sata_speed = fdtdec_get_int(blob, node,
-- 
2.9.2

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[U-Boot] [PATCH 08/13] x86: fsp: Update fsp command to show spec 1.1 header

[Bin Meng]

FSP spec 1.1 adds 3 new APIs and their offsets are in the header.
Update the 'fsp hdr' command to show these new entries.

Signed-off-by: Bin Meng 
---

 arch/x86/include/asm/fsp/fsp_infoheader.h |  9 -
 arch/x86/lib/fsp/cmd_fsp.c| 24 ++--
 2 files changed, 30 insertions(+), 3 deletions(-)

diff --git a/arch/x86/include/asm/fsp/fsp_infoheader.h 
b/arch/x86/include/asm/fsp/fsp_infoheader.h
index 4a4d627..60ce61d 100644
--- a/arch/x86/include/asm/fsp/fsp_infoheader.h
+++ b/arch/x86/include/asm/fsp/fsp_infoheader.h
@@ -26,7 +26,14 @@ struct __packed fsp_header {
u32 fsp_tempram_init;   /* tempram_init offset */
u32 fsp_init;   /* fsp_init offset */
u32 fsp_notify; /* fsp_notify offset */
-   u32 reserved2;
+   u32 fsp_mem_init;   /* fsp_mem_init offset */
+   u32 fsp_tempram_exit;   /* fsp_tempram_exit offset */
+   u32 fsp_silicon_init;   /* fsp_silicon_init offset */
 };
 
+#define FSP_HEADER_REVISION_1  1
+#define FSP_HEADER_REVISION_2  2
+
+#define FSP_ATTR_GRAPHICS_SUPPORT  (1 << 0)
+
 #endif
diff --git a/arch/x86/lib/fsp/cmd_fsp.c b/arch/x86/lib/fsp/cmd_fsp.c
index 2554663..2a99cfe 100644
--- a/arch/x86/lib/fsp/cmd_fsp.c
+++ b/arch/x86/lib/fsp/cmd_fsp.c
@@ -38,17 +38,37 @@ static int do_hdr(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
for (i = 0; i < sizeof(hdr->sign); i++)
printf("%c", *sign++);
printf(", size %d, rev %d\n", hdr->hdr_len, hdr->hdr_rev);
-   printf("Image  : rev %d.%d, id ",
-  (hdr->img_rev >> 8) & 0xff, hdr->img_rev & 0xff);
+   printf("Image  : rev ");
+   if (hdr->hdr_rev == FSP_HEADER_REVISION_1) {
+   printf("%d.%d",
+  (hdr->img_rev >> 8) & 0xff, hdr->img_rev & 0xff);
+   } else {
+   printf("%d.%d.%d.%d",
+  (hdr->img_rev >> 24) & 0xff, (hdr->img_rev >> 16) & 0xff,
+  (hdr->img_rev >> 8) & 0xff, hdr->img_rev & 0xff);
+   }
+   printf(", id ");
for (i = 0; i < ARRAY_SIZE(hdr->img_id); i++)
printf("%c", hdr->img_id[i]);
printf(", addr 0x%08x, size %d\n", img_addr, hdr->img_size);
+   if (hdr->hdr_rev == FSP_HEADER_REVISION_2) {
+   printf("GFX:%ssupported\n",
+  hdr->img_attr & FSP_ATTR_GRAPHICS_SUPPORT ? " " : " un");
+   }
printf("VPD: addr 0x%08x, size %d\n",
   hdr->cfg_region_off + img_addr, hdr->cfg_region_size);
printf("\nNumber of APIs Supported : %d\n", hdr->api_num);
printf("\tTempRamInit : 0x%08x\n", hdr->fsp_tempram_init + img_addr);
printf("\tFspInit : 0x%08x\n", hdr->fsp_init + img_addr);
printf("\tFspNotify   : 0x%08x\n", hdr->fsp_notify + img_addr);
+   if (hdr->hdr_rev == FSP_HEADER_REVISION_2) {
+   printf("\tMemoryInit  : 0x%08x\n",
+  hdr->fsp_mem_init + img_addr);
+   printf("\tTempRamExit : 0x%08x\n",
+  hdr->fsp_tempram_exit + img_addr);
+   printf("\tSiliconInit : 0x%08x\n",
+  hdr->fsp_silicon_init + img_addr);
+   }
 
return 0;
 }
-- 
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[U-Boot] [PATCH 02/13] x86: fsp: Update struct common_buf for FSP spec 1.1

[Bin Meng]

FSP spec 1.1 adds one more member to the struct common_buf to
determine the memory size that can be reserved by FSP below "top
of low usable memory" for bootloader usage. This new member uses
the reserved space so that it is still compatible with previous
FSP spec 1.0.

A new HOB (FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID) is also
published when common_buf.tolum_size is valid and non zero.

Signed-off-by: Bin Meng 
---

 arch/x86/include/asm/fsp/fsp_api.h | 3 ++-
 arch/x86/include/asm/fsp/fsp_hob.h | 8 
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/fsp/fsp_api.h 
b/arch/x86/include/asm/fsp/fsp_api.h
index afafb30..43f0cdb 100644
--- a/arch/x86/include/asm/fsp/fsp_api.h
+++ b/arch/x86/include/asm/fsp/fsp_api.h
@@ -43,7 +43,8 @@ struct common_buf {
u32 stack_top;
u32 boot_mode;  /* Current system boot mode */
void*upd_data;  /* User platform configuraiton data region */
-   u32 reserved[7];/* Reserved */
+   u32 tolum_size; /* Top of low usable memory size (FSP 1.1) */
+   u32 reserved[6];/* Reserved */
 };
 
 enum fsp_phase {
diff --git a/arch/x86/include/asm/fsp/fsp_hob.h 
b/arch/x86/include/asm/fsp/fsp_hob.h
index 7c22bcd..8ce665e 100644
--- a/arch/x86/include/asm/fsp/fsp_hob.h
+++ b/arch/x86/include/asm/fsp/fsp_hob.h
@@ -242,4 +242,12 @@ static inline u16 get_guid_hob_data_size(const struct 
hob_header *hdr)
{ 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } \
}
 
+/* The following GUIDs are newly introduced in FSP spec 1.1 */
+
+#define FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID \
+   { \
+   0x73ff4f56, 0xaa8e, 0x4451, \
+   { 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44 } \
+   }
+
 #endif
-- 
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[U-Boot] [PATCH 11/13] x86: braswell: Add FSP configuration

[Bin Meng]

Add FSP related configuration for Braswell.

Signed-off-by: Bin Meng 
---

 arch/x86/cpu/braswell/Makefile |   2 +-
 arch/x86/cpu/braswell/fsp_configs.c| 158 ++
 .../include/asm/arch-braswell/fsp/fsp_configs.h|  89 
 arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h   | 172 +++
 arch/x86/include/asm/arch-braswell/gpio.h  | 234 +
 5 files changed, 654 insertions(+), 1 deletion(-)
 create mode 100644 arch/x86/cpu/braswell/fsp_configs.c
 create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
 create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
 create mode 100644 arch/x86/include/asm/arch-braswell/gpio.h

diff --git a/arch/x86/cpu/braswell/Makefile b/arch/x86/cpu/braswell/Makefile
index 19bcee6..ddf6d28 100644
--- a/arch/x86/cpu/braswell/Makefile
+++ b/arch/x86/cpu/braswell/Makefile
@@ -4,4 +4,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y += braswell.o cpu.o early_uart.o
+obj-y += braswell.o cpu.o early_uart.o fsp_configs.o
diff --git a/arch/x86/cpu/braswell/fsp_configs.c 
b/arch/x86/cpu/braswell/fsp_configs.c
new file mode 100644
index 000..d984519
--- /dev/null
+++ b/arch/x86/cpu/braswell/fsp_configs.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (C) 2017, Bin Meng 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * Override the FSP's Azalia configuration data
+ *
+ * @azalia:pointer to be updated to point to a ROM address where Azalia
+ * configuration data is stored
+ */
+__weak void update_fsp_azalia_configs(struct azalia_config **azalia)
+{
+   *azalia = NULL;
+}
+
+/**
+ * Override the FSP's GPIO configuration data
+ *
+ * @family:pointer to be updated to point to a ROM address where GPIO
+ * family configuration data is stored
+ * @pad:   pointer to be updated to point to a ROM address where GPIO
+ * pad configuration data is stored
+ */
+__weak void update_fsp_gpio_configs(struct gpio_family **family,
+   struct gpio_pad **pad)
+{
+   *family = NULL;
+   *pad = NULL;
+}
+
+/**
+ * Override the FSP's configuration data.
+ * If the device tree does not specify an integer setting, use the default
+ * provided in Intel's Braswell release FSP/BraswellFsp.bsf file.
+ */
+void update_fsp_configs(struct fsp_config_data *config,
+   struct fspinit_rtbuf *rt_buf)
+{
+   struct upd_region *fsp_upd = >fsp_upd;
+   struct memory_upd *memory_upd = _upd->memory_upd;
+   struct silicon_upd *silicon_upd = _upd->silicon_upd;
+   const void *blob = gd->fdt_blob;
+   int node;
+
+   /* Initialize runtime buffer for fsp_init() */
+   rt_buf->common.stack_top = config->common.stack_top - 32;
+   rt_buf->common.boot_mode = config->common.boot_mode;
+   rt_buf->common.upd_data = >fsp_upd;
+
+   node = fdt_node_offset_by_compatible(blob, 0, "intel,braswell-fsp");
+   if (node < 0) {
+   debug("%s: Cannot find FSP node\n", __func__);
+   return;
+   }
+
+   node = fdt_node_offset_by_compatible(blob, node,
+"intel,braswell-fsp-memory");
+   if (node < 0) {
+   debug("%s: Cannot find FSP memory node\n", __func__);
+   return;
+   }
+
+   /* Override memory UPD contents */
+   memory_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node,
+   "fsp,mrc-init-tseg-size", MRC_INIT_TSEG_SIZE_4MB);
+   memory_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node,
+   "fsp,mrc-init-mmio-size", MRC_INIT_MMIO_SIZE_2048MB);
+   memory_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node,
+   "fsp,mrc-init-spd-addr1", 0xa0);
+   memory_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node,
+   "fsp,mrc-init-spd-addr2", 0xa2);
+   memory_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node,
+   "fsp,igd-dvmt50-pre-alloc", IGD_DVMT50_PRE_ALLOC_32MB);
+   memory_upd->aperture_size = fdtdec_get_int(blob, node,
+   "fsp,aperture-size", APERTURE_SIZE_256MB);
+   memory_upd->gtt_size = fdtdec_get_int(blob, node,
+   "fsp,gtt-size", GTT_SIZE_1MB);
+   memory_upd->legacy_seg_decode = fdtdec_get_bool(blob, node,
+   "fsp,legacy-seg-decode");
+   memory_upd->enable_dvfs = fdtdec_get_bool(blob, node,
+   "fsp,enable-dvfs");
+   memory_upd->memory_type = fdtdec_get_int(blob, node,
+   "fsp,memory-type", DRAM_TYPE_DDR3);
+   memory_upd->enable_ca_mirror = fdtdec_get_bool(blob, node,
+   "fsp,enable-ca-mirror");
+
+   node = fdt_node_offset_by_compatible(blob, node,
+"intel,braswell-fsp-silicon");
+   if (node < 0) {
+ 

[U-Boot] [PATCH 04/13] x86: Add Video BIOS Table (VBT) related Kconfig options

[Bin Meng]

This adds Kconfig options for Video BIOS Table which is normally
required if you are using an Intel FSP firmware that is complaint
with spec 1.1 or later to initialize the integrated graphics device.

Signed-off-by: Bin Meng 
---

 arch/x86/Kconfig | 34 ++
 1 file changed, 34 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 5373082..b0d3266 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -551,6 +551,40 @@ config VGA_BIOS_ADDR
  address of 0xfff9 indicates that the image will be put at offset
  0x9 from the beginning of a 1MB flash device.
 
+config HAVE_VBT
+   bool "Add a Video BIOS Table (VBT) image"
+   depends on HAVE_FSP
+   help
+ Select this option if you have a Video BIOS Table (VBT) image that
+ you would like to add to your ROM. This is normally required if you
+ are using an Intel FSP firmware that is complaint with spec 1.1 or
+ later to initialize the integrated graphics device (IGD).
+
+ Video BIOS Table, or VBT, provides platform and board specific
+ configuration information to the driver that is not discoverable
+ or available through other means. By other means the most used
+ method here is to read EDID table from the attached monitor, over
+ Display Data Channel (DDC) using two pin I2C serial interface. VBT
+ configuration is related to display hardware and is available via
+ the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
+
+config VBT_FILE
+   string "Video BIOS Table (VBT) image filename"
+   depends on HAVE_VBT
+   default "vbt.bin"
+   help
+ The filename of the file to use as Video BIOS Table (VBT) image
+ in the board directory.
+
+config VBT_ADDR
+   hex "Video BIOS Table (VBT) image location"
+   depends on HAVE_VBT
+   default 0xfff9
+   help
+ The location of Video BIOS Table (VBT) image in the SPI flash. For
+ example, base address of 0xfff9 indicates that the image will
+ be put at offset 0x9 from the beginning of a 1MB flash device.
+
 config ROM_TABLE_ADDR
hex
default 0xf
-- 
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[U-Boot] [PATCH 03/13] x86: fsp: Add FSP_GRAPHICS_INFO_HOB

[Bin Meng]

This adds a new HOB type for graphics information introduced in FSP
spec 1.1. When graphics capability is included in FSP and enabled,
FSP produces an FSP_GRAPHICS_INFO_HOB as described in the EFI PI
specification which provides information about the graphics mode and
framebuffer.

Signed-off-by: Bin Meng 
---

 arch/x86/include/asm/fsp/fsp_hob.h | 26 ++
 arch/x86/include/asm/fsp/fsp_support.h | 12 
 arch/x86/lib/fsp/fsp_support.c |  7 +++
 3 files changed, 45 insertions(+)

diff --git a/arch/x86/include/asm/fsp/fsp_hob.h 
b/arch/x86/include/asm/fsp/fsp_hob.h
index 8ce665e..244f86e 100644
--- a/arch/x86/include/asm/fsp/fsp_hob.h
+++ b/arch/x86/include/asm/fsp/fsp_hob.h
@@ -127,6 +127,26 @@ struct hob_guid {
/* GUID specific data goes here */
 };
 
+enum pixel_format {
+   pixel_rgbx_8bpc,/* RGB 8 bit per color */
+   pixel_bgrx_8bpc,/* BGR 8 bit per color */
+   pixel_bitmask,
+};
+
+struct __packed hob_graphics_info {
+   phys_addr_t fb_base;/* framebuffer base address */
+   u32 fb_size;/* framebuffer size */
+   u32 version;
+   u32 width;
+   u32 height;
+   enum pixel_format pixel_format;
+   u32 red_mask;
+   u32 green_mask;
+   u32 blue_mask;
+   u32 reserved_mask;
+   u32 pixels_per_scanline;
+};
+
 /**
  * get_next_hob() - return a pointer to the next HOB in the HOB list
  *
@@ -250,4 +270,10 @@ static inline u16 get_guid_hob_data_size(const struct 
hob_header *hdr)
{ 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44 } \
}
 
+#define FSP_GRAPHICS_INFO_HOB_GUID \
+   { \
+   0x39f62cce, 0x6825, 0x4669, \
+   { 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 } \
+   }
+
 #endif
diff --git a/arch/x86/include/asm/fsp/fsp_support.h 
b/arch/x86/include/asm/fsp/fsp_support.h
index 61d811f..97a50b0 100644
--- a/arch/x86/include/asm/fsp/fsp_support.h
+++ b/arch/x86/include/asm/fsp/fsp_support.h
@@ -191,6 +191,18 @@ void *fsp_get_nvs_data(const void *hob_list, u32 *len);
 void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len);
 
 /**
+ * This function retrieves graphics information.
+ *
+ * @hob_list:  A HOB list pointer.
+ * @len:   A pointer to the graphics info HOB length.
+ * If the HOB is located, the length will be updated.
+ *
+ * @retval NULL:   Failed to find the graphics info HOB.
+ * @retval others: A pointer to struct hob_graphics_info.
+ */
+void *fsp_get_graphics_info(const void *hob_list, u32 *len);
+
+/**
  * This function overrides the default configurations of FSP.
  *
  * @config:  A pointer to the FSP configuration data structure
diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
index ab8340c..e0c49be 100644
--- a/arch/x86/lib/fsp/fsp_support.c
+++ b/arch/x86/lib/fsp/fsp_support.c
@@ -425,3 +425,10 @@ void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 
*len)
 
return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *));
 }
+
+void *fsp_get_graphics_info(const void *hob_list, u32 *len)
+{
+   const struct efi_guid guid = FSP_GRAPHICS_INFO_HOB_GUID;
+
+   return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *));
+}
-- 
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[U-Boot] [PATCH 01/13] x86: tsc: Add Airmont reference clock values

[Bin Meng]

Per the Intel 64 and IA-32 Architecture Software Developer's Manual,
add the reference clock for Intel Atom Processors based on the Airmont
Microarchitecture (Braswell).

This keeps in sync with Linux kernel commit:
  6fcb41c: x86/tsc_msr: Add Airmont reference clock values

Signed-off-by: Bin Meng 
---

 drivers/timer/tsc_timer.c | 17 ++---
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index 4d1fc9c..77040af 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -18,7 +18,7 @@
 #include 
 #include 
 
-#define MAX_NUM_FREQS  8
+#define MAX_NUM_FREQS  9
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -40,17 +40,20 @@ struct freq_desc {
 
 static struct freq_desc freq_desc_tables[] = {
/* PNW */
-   { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200 } },
+   { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },
/* CLV+ */
-   { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 } },
+   { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },
/* TNG - Intel Atom processor Z3400 series */
-   { 6, 0x4a, 1, { 0, 10, 133300, 0, 0, 0, 0, 0 } },
+   { 6, 0x4a, 1, { 0, 10, 133300, 0, 0, 0, 0, 0, 0 } },
/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
-   { 6, 0x37, 1, { 83300, 10, 133300, 116700, 8, 0, 0, 0 } },
+   { 6, 0x37, 1, { 83300, 10, 133300, 116700, 8, 0, 0, 0, 0 } },
/* ANN - Intel Atom processor Z3500 series */
-   { 6, 0x5a, 1, { 83300, 10, 133300, 10, 0, 0, 0, 0 } },
+   { 6, 0x5a, 1, { 83300, 10, 133300, 10, 0, 0, 0, 0, 0 } },
+   /* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
+   { 6, 0x4c, 1, { 83300, 10, 133300, 116700,
+   8, 93300, 9, 88900, 87500 } },
/* Ivybridge */
-   { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } },
+   { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
 };
 
 static int match_cpu(u8 family, u8 model)
-- 
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[U-Boot] [PATCH 06/13] x86: dts: Include Intel Video BIOS Table in the ROM image

[Bin Meng]

Now that binman is able to recognize the Video BIOS Table entry,
add such one in the u-boot.dtsi.

Signed-off-by: Bin Meng 
---

 arch/x86/dts/u-boot.dtsi | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index a4321d3..7e37d4f 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -67,6 +67,12 @@
pos = ;
};
 #endif
+#ifdef CONFIG_HAVE_VBT
+   intel-vbt {
+   filename = CONFIG_VBT_FILE;
+   pos = ;
+   };
+#endif
 #ifdef CONFIG_HAVE_REFCODE
intel-refcode {
pos = ;
-- 
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[U-Boot] [PATCH 00/13] x86: Add Intel Braswell SoC and Cherry Hill board support

[Bin Meng]

Intel Braswell SoC is the follow-up processor of BayTrail on the
Atom product line. This support utilizes Intel FSP firmware to
initialize the SoC. Note its FSP is spec 1.1 compliant, but it
is still backward compatible with spec 1.0. For simplicity, we
are using the spec 1.0 APIs to do the initialization.

There are 3 big differences from previous SoCs:
- No ICH6 legacy GPIO controller. FSP uses a custom table to
  configure the pin mux and pads.
- No legacy VGA BIOS is supplied. Instead a new type of binary
  called Intel Video BIOS Table (VBT) is used by FSP to initialize
  the integrated graphics device.
- No EHCI controller, only an xHCI controller integrated.

The support is validated on Intel Cherry Hill board, a board based
on Intel Braswell SoC.

This series is available at u-boot-x86/braswell-working.


Bin Meng (13):
  x86: tsc: Add Airmont reference clock values
  x86: fsp: Update struct common_buf for FSP spec 1.1
  x86: fsp: Add FSP_GRAPHICS_INFO_HOB
  x86: Add Video BIOS Table (VBT) related Kconfig options
  tools: binman: Add a new entry type for Intel VBT
  x86: dts: Include Intel Video BIOS Table in the ROM image
  x86: dm: video: Add a framebuffer driver that utilizes VBT
  x86: fsp: Update fsp command to show spec 1.1 header
  x86: Add Intel Braswell SoC support
  x86: braswell: Add microcode for B0/C0/D0 stepping SoC
  x86: braswell: Add FSP configuration
  x86: braswell: Disable PUNIT power configuration for B0 stepping
  x86: Support Intel Cherry Hill board

 arch/x86/Kconfig   |   43 +
 arch/x86/cpu/Makefile  |1 +
 arch/x86/cpu/braswell/Kconfig  |   38 +
 arch/x86/cpu/braswell/Makefile |7 +
 arch/x86/cpu/braswell/braswell.c   |   36 +
 arch/x86/cpu/braswell/cpu.c|  170 +
 arch/x86/cpu/braswell/early_uart.c |   86 +
 arch/x86/cpu/braswell/fsp_configs.c|  164 +
 arch/x86/dts/Makefile  |1 +
 arch/x86/dts/cherryhill.dts|  215 +
 arch/x86/dts/microcode/m01406c2220.dtsi| 4308 
 arch/x86/dts/microcode/m01406c3363.dtsi| 4308 
 arch/x86/dts/microcode/m01406c440a.dtsi| 4308 
 arch/x86/dts/u-boot.dtsi   |6 +
 .../include/asm/arch-braswell/fsp/fsp_configs.h|   89 +
 arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h   |  172 +
 arch/x86/include/asm/arch-braswell/gpio.h  |  234 ++
 arch/x86/include/asm/arch-braswell/iomap.h |   50 +
 arch/x86/include/asm/fsp/fsp_api.h |3 +-
 arch/x86/include/asm/fsp/fsp_hob.h |   34 +
 arch/x86/include/asm/fsp/fsp_infoheader.h  |9 +-
 arch/x86/include/asm/fsp/fsp_support.h |   12 +
 arch/x86/lib/fsp/Makefile  |1 +
 arch/x86/lib/fsp/cmd_fsp.c |   24 +-
 arch/x86/lib/fsp/fsp_graphics.c|  124 +
 arch/x86/lib/fsp/fsp_support.c |7 +
 board/intel/Kconfig|   10 +
 board/intel/cherryhill/Kconfig |   25 +
 board/intel/cherryhill/MAINTAINERS |6 +
 board/intel/cherryhill/Makefile|7 +
 board/intel/cherryhill/cherryhill.c|  596 +++
 board/intel/cherryhill/start.S |9 +
 configs/cherryhill_defconfig   |   36 +
 doc/README.x86 |   30 +
 drivers/timer/tsc_timer.c  |   17 +-
 include/configs/cherryhill.h   |   22 +
 tools/binman/etype/intel_vbt.py|   14 +
 tools/binman/func_test.py  |9 +-
 tools/binman/test/46_intel-vbt.dts |   14 +
 39 files changed, 15233 insertions(+), 12 deletions(-)
 create mode 100644 arch/x86/cpu/braswell/Kconfig
 create mode 100644 arch/x86/cpu/braswell/Makefile
 create mode 100644 arch/x86/cpu/braswell/braswell.c
 create mode 100644 arch/x86/cpu/braswell/cpu.c
 create mode 100644 arch/x86/cpu/braswell/early_uart.c
 create mode 100644 arch/x86/cpu/braswell/fsp_configs.c
 create mode 100644 arch/x86/dts/cherryhill.dts
 create mode 100644 arch/x86/dts/microcode/m01406c2220.dtsi
 create mode 100644 arch/x86/dts/microcode/m01406c3363.dtsi
 create mode 100644 arch/x86/dts/microcode/m01406c440a.dtsi
 create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
 create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
 create mode 100644 arch/x86/include/asm/arch-braswell/gpio.h
 create mode 100644 arch/x86/include/asm/arch-braswell/iomap.h
 create mode 100644 arch/x86/lib/fsp/fsp_graphics.c
 create mode 100644 board/intel/cherryhill/Kconfig
 create mode 100644 board/intel/cherryhill/MAINTAINERS
 create mode 100644 

[U-Boot] [PATCH 4/5] x86: ich-spi: Move opcode registers configuration to another routine

[Bin Meng]

At present the ICH SPI opcode registers configuration is done in the
ich_spi_remove() routine, a little bit weird but that's how current.
Linux MTD driver works. This changes to move the opcode registers
configuration to a separate routine ich_spi_config_opcode() which
might be called by U-Boot itself as well.

Signed-off-by: Bin Meng 
---

 drivers/spi/ich.c | 22 --
 1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index d4888f5..373bc26 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -338,6 +338,21 @@ static int ich_status_poll(struct ich_spi_priv *ctlr, u16 
bitmask,
return -ETIMEDOUT;
 }
 
+void ich_spi_config_opcode(struct udevice *dev)
+{
+   struct ich_spi_priv *ctlr = dev_get_priv(dev);
+
+   /*
+* PREOP, OPTYPE, OPMENU1/OPMENU2 registers can be locked down
+* to prevent accidental or intentional writes. Before they get
+* locked down, these registers should be initialized properly.
+*/
+   ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop);
+   ich_writew(ctlr, SPI_OPTYPE, ctlr->optype);
+   ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu);
+   ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
+}
+
 static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
 {
@@ -585,16 +600,11 @@ static int ich_spi_probe(struct udevice *dev)
 
 static int ich_spi_remove(struct udevice *bus)
 {
-   struct ich_spi_priv *ctlr = dev_get_priv(bus);
-
/*
 * Configure SPI controller so that the Linux MTD driver can fully
 * access the SPI NOR chip
 */
-   ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop);
-   ich_writew(ctlr, SPI_OPTYPE, ctlr->optype);
-   ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu);
-   ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
+   ich_spi_config_opcode(bus);
 
return 0;
 }
-- 
2.9.2

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[U-Boot] [PATCH 5/5] x86: fsp: Configure SPI opcode registers before SPI is locked down

[Bin Meng]

Some Intel FSP (like Braswell) does SPI lock-down during the call
to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
it's bootloader's responsibility to configure the SPI controller's
opcode registers properly otherwise SPI controller driver doesn't
know how to communicate with the SPI flash device.

This introduces a Kconfig option CONFIG_FSP_LOCKDOWN_SPI for such
FSPs. When it is on, U-Boot will configure the SPI opcode registers
before the lock-down.

Signed-off-by: Bin Meng 
---

 arch/x86/Kconfig  |  9 +
 arch/x86/lib/fsp/fsp_common.c | 24 
 2 files changed, 33 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index c26710b..5373082 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -401,6 +401,15 @@ config FSP_BROKEN_HOB
  do not overwrite the important boot service data which is used by
  FSP, otherwise the subsequent call to fsp_notify() will fail.
 
+config FSP_LOCKDOWN_SPI
+   bool
+   depends on HAVE_FSP
+   help
+ Some Intel FSP (like Braswell) does SPI lock-down during the call
+ to fsp_notify(INIT_PHASE_BOOT). This option should be turned on
+ for such FSP and U-Boot will configure the SPI opcode registers
+ before the lock-down.
+
 config ENABLE_MRC_CACHE
bool "Enable MRC cache"
depends on !EFI && !SYS_COREBOOT
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index 3397bb8..320d87d 100644
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -19,6 +19,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+extern void ich_spi_config_opcode(struct udevice *dev);
+
 int checkcpu(void)
 {
return 0;
@@ -49,6 +51,28 @@ void board_final_cleanup(void)
 {
u32 status;
 
+#ifdef CONFIG_FSP_LOCKDOWN_SPI
+   struct udevice *dev;
+
+   /*
+* Some Intel FSP (like Braswell) does SPI lock-down during the call
+* to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
+* it's bootloader's responsibility to configure the SPI controller's
+* opcode registers properly otherwise SPI controller driver doesn't
+* know how to communicate with the SPI flash device.
+*
+* Note we cannot do such configuration elsewhere (eg: during the SPI
+* controller driver's probe() routine), becasue:
+*
+* 1). U-Boot SPI controller driver does not set the lock-down bit
+* 2). Any SPI transfer will corrupt the contents of these registers
+*
+* Hence we have to do it right here before SPI lock-down bit is set.
+*/
+   if (!uclass_first_device_err(UCLASS_SPI, ))
+   ich_spi_config_opcode(dev);
+#endif
+
/* call into FspNotify */
debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
status = fsp_notify(NULL, INIT_PHASE_BOOT);
-- 
2.9.2

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[U-Boot] [PATCH 2/5] x86: ich-spi: Remove unnecessary assignment in ich_init_controller()

[Bin Meng]

There is no need to do another assignment to ich7_spi.

Signed-off-by: Bin Meng 
---

 drivers/spi/ich.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 46dd9a8..909eefc 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -126,7 +126,6 @@ static int ich_init_controller(struct udevice *dev,
if (plat->ich_version == ICHV_7) {
struct ich7_spi_regs *ich7_spi = sbase;
 
-   ich7_spi = (struct ich7_spi_regs *)sbase;
ctlr->ichspi_lock = readw(_spi->spis) & SPIS_LOCK;
ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
ctlr->menubytes = sizeof(ich7_spi->opmenu);
-- 
2.9.2

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[U-Boot] [PATCH 3/5] x86: ich-spi: Don't read cached lock status

[Bin Meng]

At present the ICH SPI controller driver reads the controller lock
status from its register in the probe routine and saves the lock
status to a member of priv. Later the driver uses the cached status
from priv to judge whether the controller setting is locked and do
different setup.

But such logic is only valid when there is only the SPI controller
driver that touches the SPI hardware. In fact the lock status change
can be trigged outside the driver, eg: during the fsp_notify() call
when Intel FSP is used.

This changes the driver to read the lock status every time when an
SPI transfer is initiated instead of reading the cached one.

Signed-off-by: Bin Meng 
---

 drivers/spi/ich.c | 29 +++--
 drivers/spi/ich.h |  2 --
 2 files changed, 23 insertions(+), 8 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 909eefc..d4888f5 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -126,7 +126,6 @@ static int ich_init_controller(struct udevice *dev,
if (plat->ich_version == ICHV_7) {
struct ich7_spi_regs *ich7_spi = sbase;
 
-   ctlr->ichspi_lock = readw(_spi->spis) & SPIS_LOCK;
ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
ctlr->menubytes = sizeof(ich7_spi->opmenu);
ctlr->optype = offsetof(struct ich7_spi_regs, optype);
@@ -141,7 +140,6 @@ static int ich_init_controller(struct udevice *dev,
} else if (plat->ich_version == ICHV_9) {
struct ich9_spi_regs *ich9_spi = sbase;
 
-   ctlr->ichspi_lock = readw(_spi->hsfs) & HSFS_FLOCKDN;
ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
ctlr->menubytes = sizeof(ich9_spi->opmenu);
ctlr->optype = offsetof(struct ich9_spi_regs, optype);
@@ -186,6 +184,23 @@ static inline void spi_use_in(struct spi_trans *trans, 
unsigned bytes)
trans->bytesin -= bytes;
 }
 
+static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase)
+{
+   int lock = 0;
+
+   if (plat->ich_version == ICHV_7) {
+   struct ich7_spi_regs *ich7_spi = sbase;
+
+   lock = readw(_spi->spis) & SPIS_LOCK;
+   } else if (plat->ich_version == ICHV_9) {
+   struct ich9_spi_regs *ich9_spi = sbase;
+
+   lock = readw(_spi->hsfs) & HSFS_FLOCKDN;
+   }
+
+   return lock != 0;
+}
+
 static void spi_setup_type(struct spi_trans *trans, int data_bytes)
 {
trans->type = 0xFF;
@@ -219,14 +234,15 @@ static void spi_setup_type(struct spi_trans *trans, int 
data_bytes)
}
 }
 
-static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans)
+static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans,
+   bool lock)
 {
uint16_t optypes;
uint8_t opmenu[ctlr->menubytes];
 
trans->opcode = trans->out[0];
spi_use_out(trans, 1);
-   if (!ctlr->ichspi_lock) {
+   if (!lock) {
/* The lock is off, so just use index 0. */
ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
optypes = ich_readw(ctlr, ctlr->optype);
@@ -336,6 +352,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int 
bitlen,
struct spi_trans *trans = >trans;
unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END);
int using_cmd = 0;
+   bool lock = spi_lock_status(plat, ctlr->base);
int ret;
 
/* We don't support writing partial bytes */
@@ -399,7 +416,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int 
bitlen,
ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
 
spi_setup_type(trans, using_cmd ? bytes : 0);
-   opcode_index = spi_setup_opcode(ctlr, trans);
+   opcode_index = spi_setup_opcode(ctlr, trans, lock);
if (opcode_index < 0)
return -EINVAL;
with_address = spi_setup_offset(trans);
@@ -412,7 +429,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int 
bitlen,
 * in order to prevent the Management Engine from
 * issuing a transaction between WREN and DATA.
 */
-   if (!ctlr->ichspi_lock)
+   if (!lock)
ich_writew(ctlr, trans->opcode, ctlr->preop);
return 0;
}
diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h
index dcb8a90..c867c57 100644
--- a/drivers/spi/ich.h
+++ b/drivers/spi/ich.h
@@ -177,8 +177,6 @@ struct ich_spi_platdata {
 };
 
 struct ich_spi_priv {
-   int ichspi_lock;
-   int locked;
int opmenu;
int menubytes;
void *base; /* Base of register set */
-- 
2.9.2

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[U-Boot] [PATCH 1/5] x86: ich-spi: Remove spi_write_protect_region()

[Bin Meng]

This routine is not called anywhere.

Signed-off-by: Bin Meng 
---

 drivers/spi/ich.c | 50 --
 1 file changed, 50 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index bf2e99b..46dd9a8 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -539,56 +539,6 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int 
bitlen,
return 0;
 }
 
-/*
- * This uses the SPI controller from the Intel Cougar Point and Panther Point
- * PCH to write-protect portions of the SPI flash until reboot. The changes
- * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's
- * done elsewhere.
- */
-int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit,
-uint32_t length, int hint)
-{
-   struct udevice *bus = dev->parent;
-   struct ich_spi_priv *ctlr = dev_get_priv(bus);
-   uint32_t tmplong;
-   uint32_t upper_limit;
-
-   if (!ctlr->pr) {
-   printf("%s: operation not supported on this chipset\n",
-  __func__);
-   return -ENOSYS;
-   }
-
-   if (length == 0 ||
-   lower_limit > (0xUL - length) + 1 ||
-   hint < 0 || hint > 4) {
-   printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__,
-  lower_limit, length, hint);
-   return -EPERM;
-   }
-
-   upper_limit = lower_limit + length - 1;
-
-   /*
-* Determine bits to write, as follows:
-*  31 Write-protection enable (includes erase operation)
-*  30:29  reserved
-*  28:16  Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff)
-*  15 Read-protection enable
-*  14:13  reserved
-*  12:0   Lower Limit (FLA address bits 24:12, with 11:0 == 0x000)
-*/
-   tmplong = 0x8000 |
-   ((upper_limit & 0x01fff000) << 4) |
-   ((lower_limit & 0x01fff000) >> 12);
-
-   printf("%s: writing 0x%08x to %p\n", __func__, tmplong,
-  >pr[hint]);
-   ctlr->pr[hint] = tmplong;
-
-   return 0;
-}
-
 static int ich_spi_probe(struct udevice *dev)
 {
struct ich_spi_platdata *plat = dev_get_platdata(dev);
-- 
2.9.2

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[U-Boot] [PATCH v3 3/3] LS2080ARDB: Secure Boot defconfig for QSPI boot.

[Sumit Garg]

From: Udit Agarwal 

Add the secure boot defconfig for QSPI boot on LS2088ARDB
platform.

Signed-off-by: Udit Agarwal 
---

Changes in v3:
Rebasing of the patch on top commit.
This patch supersedes https://patchwork.ozlabs.org/patch/767680/

 board/freescale/ls2080ardb/MAINTAINERS|  5 +++
 configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 48 +++
 2 files changed, 53 insertions(+)
 create mode 100644 configs/ls2088ardb_qspi_SECURE_BOOT_defconfig

diff --git a/board/freescale/ls2080ardb/MAINTAINERS 
b/board/freescale/ls2080ardb/MAINTAINERS
index 91f13ea..8da1c6d 100644
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -21,3 +21,8 @@ LS2080A_SECURE_BOOT BOARD
 M: Saksham Jain 
 S: Maintained
 F: configs/ls2080ardb_SECURE_BOOT_defconfig
+
+LS2088A_QSPI_SECURE_BOOT BOARD
+M: Udit Agarwal 
+S: Maintained
+F: configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig 
b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
new file mode 100644
index 000..05c799d
--- /dev/null
+++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
@@ -0,0 +1,48 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080ARDB=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_QSPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_BOOTDELAY=10
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SECURE_BOOT=y
+CONFIG_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
-- 
1.9.1

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[U-Boot] [PATCH v3 2/3] LS2080ARDB: QSPI boot: Secure Boot image validation

[Sumit Garg]

From: Udit Agarwal 

Adds header address for PPA to be validated during ESBC phase for
ARCH_LS2088 and QSPI_BOOT.

Moves sec_init prior to ppa_init as for validation of PPA, sec must
be initialised before the PPA is initialised.

Signed-off-by: Udit Agarwal 
---

Changes in v3:
Rebasing of the patches on the top commit and removes conflict
on CONFIG_EXTRA_ENV_SETTINGS.
This patch supersedes https://patchwork.ozlabs.org/patch/767679/

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 3 ++-
 arch/arm/include/asm/fsl_secure_boot.h| 5 +
 board/freescale/ls2080aqds/ls2080aqds.c   | 7 +++
 board/freescale/ls2080ardb/ls2080ardb.c   | 4 
 4 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index b7549a0..f14b1c8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -197,7 +197,8 @@ config SYS_LS_PPA_ESBC_ADDR
default 0x6068 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
default 0x4068 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
default 0x4068 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
-   default 0x58068 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
+   default 0x2068 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
+   default 0x58068 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
default 0x68 if SYS_LS_PPA_FW_IN_MMC
default 0x68 if SYS_LS_PPA_FW_IN_NAND
help
diff --git a/arch/arm/include/asm/fsl_secure_boot.h 
b/arch/arm/include/asm/fsl_secure_boot.h
index 63845a2..ec6463d 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -72,8 +72,13 @@
  * DDR memory map
  */
 #ifdef CONFIG_FSL_LSCH3
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_BS_ADDR_DEVICE  0x2060
+#define CONFIG_BS_HDR_ADDR_DEVICE  0x2064
+#else /* NOR BOOT */
 #define CONFIG_BS_ADDR_DEVICE  0x58060
 #define CONFIG_BS_HDR_ADDR_DEVICE  0x58064
+#endif /*ifdef CONFIG_QSPI_BOOT */
 #define CONFIG_BS_SIZE 0x1000
 #define CONFIG_BS_HDR_SIZE 0x4000
 #define CONFIG_BS_ADDR_RAM 0xa060
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index f36fb98..be4e8ee 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -226,15 +226,14 @@ int board_init(void)
 #endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
rtc_enable_32khz_output();
+#ifdef CONFIG_FSL_CAAM
+   sec_init();
+#endif
 
 #ifdef CONFIG_FSL_LS_PPA
ppa_init();
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-   sec_init();
-#endif
-
return 0;
 }
 
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c 
b/board/freescale/ls2080ardb/ls2080ardb.c
index df2d768..4c42c73 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -231,6 +231,10 @@ int board_init(void)
 #ifdef CONFIG_FSL_QIXIS
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
 #endif
+
+#ifdef CONFIG_FSL_CAAM
+   sec_init();
+#endif
 #ifdef CONFIG_FSL_LS_PPA
ppa_init();
 #endif
-- 
1.9.1

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[U-Boot] [PATCH v3 1/3] SECURE_BOOT: Unify memory map for Layerscape based platforms

[Sumit Garg]

Unify memory map for Layerscape based platforms. This patch includes
changes in bootscript, bootscript header and PPA header addresses
change as per unified memory map.

Signed-off-by: Sumit Garg 
Tested-by: Vinitha Pillai 
---

Changes in v3:
Rebasing of the patch on top commit.
This patch supersedes https://patchwork.ozlabs.org/patch/756260/

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 12 +++
 arch/arm/include/asm/fsl_secure_boot.h| 54 +--
 2 files changed, 28 insertions(+), 38 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 5825f9b..b7549a0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -194,12 +194,12 @@ config SYS_LS_PPA_FW_ADDR
 config SYS_LS_PPA_ESBC_ADDR
hex "hdr address of PPA firmware loading from"
depends on FSL_LS_PPA && CHAIN_OF_TRUST
-   default 0x600c if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
-   default 0x4074 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
-   default 0x4048 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
-   default 0x580c4 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
-   default 0x70 if SYS_LS_PPA_FW_IN_MMC
-   default 0x70 if SYS_LS_PPA_FW_IN_NAND
+   default 0x6068 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
+   default 0x4068 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
+   default 0x4068 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
+   default 0x58068 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
+   default 0x68 if SYS_LS_PPA_FW_IN_MMC
+   default 0x68 if SYS_LS_PPA_FW_IN_NAND
help
  If the PPA header firmware locate at XIP flash, such as NOR or
  QSPI flash, this address is a directly memory-mapped.
diff --git a/arch/arm/include/asm/fsl_secure_boot.h 
b/arch/arm/include/asm/fsl_secure_boot.h
index b0b3b93..63845a2 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -1,5 +1,6 @@
 /*
  * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -71,55 +72,44 @@
  * DDR memory map
  */
 #ifdef CONFIG_FSL_LSCH3
-#define CONFIG_BS_HDR_ADDR_DEVICE  0x580d0
-#define CONFIG_BS_ADDR_DEVICE  0x580e0
-#define CONFIG_BS_HDR_ADDR_RAM 0xa0d0
-#define CONFIG_BS_ADDR_RAM 0xa0e0
-#define CONFIG_BS_HDR_SIZE 0x2000
+#define CONFIG_BS_ADDR_DEVICE  0x58060
+#define CONFIG_BS_HDR_ADDR_DEVICE  0x58064
 #define CONFIG_BS_SIZE 0x1000
+#define CONFIG_BS_HDR_SIZE 0x4000
+#define CONFIG_BS_ADDR_RAM 0xa060
+#define CONFIG_BS_HDR_ADDR_RAM 0xa064
 #else
 #ifdef CONFIG_SD_BOOT
 /* For SD boot address and size are assigned in terms of sector
  * offset and no. of sectors respectively.
  */
-#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
-#define CONFIG_BS_HDR_ADDR_DEVICE  0x0920
-#else
-#define CONFIG_BS_HDR_ADDR_DEVICE   0x0900
-#endif
-#define CONFIG_BS_ADDR_DEVICE  0x0940
-#define CONFIG_BS_HDR_SIZE 0x0010
+#define CONFIG_BS_ADDR_DEVICE  0x3000
+#define CONFIG_BS_HDR_ADDR_DEVICE  0x3200
 #define CONFIG_BS_SIZE 0x0008
+#define CONFIG_BS_HDR_SIZE 0x0010
 #elif defined(CONFIG_NAND_BOOT)
-#define CONFIG_BS_HDR_ADDR_DEVICE  0x0080
-#define CONFIG_BS_ADDR_DEVICE  0x00802000
-#define CONFIG_BS_HDR_SIZE 0x2000
-#define CONFIG_BS_SIZE 0x1000
-#elif defined(CONFIG_QSPI_BOOT)
-#ifdef CONFIG_ARCH_LS1046A
-#define CONFIG_BS_HDR_ADDR_DEVICE  0x4078
-#define CONFIG_BS_ADDR_DEVICE  0x4080
-#elif defined(CONFIG_ARCH_LS1012A)
-#define CONFIG_BS_HDR_ADDR_DEVICE  0x400c
-#define CONFIG_BS_ADDR_DEVICE  0x4006
-#else
-#error "Platform not supported"
-#endif
+#define CONFIG_BS_ADDR_DEVICE  0x0060
+#define CONFIG_BS_HDR_ADDR_DEVICE  0x0064
+#define CONFIG_BS_SIZE 0x1000
 #define CONFIG_BS_HDR_SIZE 0x2000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_BS_ADDR_DEVICE  0x4060
+#define CONFIG_BS_HDR_ADDR_DEVICE  0x4064
 #define CONFIG_BS_SIZE 0x1000
-#else /* Default NOR Boot */
-#define CONFIG_BS_HDR_ADDR_DEVICE  0x600a
-#define CONFIG_BS_ADDR_DEVICE  0x6006
 #define CONFIG_BS_HDR_SIZE 0x2000
+#else /* Default NOR Boot */
+#define CONFIG_BS_ADDR_DEVICE  0x6060
+#define CONFIG_BS_HDR_ADDR_DEVICE  0x6064
 #define CONFIG_BS_SIZE 0x1000
+#define CONFIG_BS_HDR_SIZE 0x2000
 #endif
-#define CONFIG_BS_HDR_ADDR_RAM 0x8100
-#define CONFIG_BS_ADDR_RAM 0x8102

Re: [U-Boot] Initializing global_data on SuperH before board_init_f() ?

[Lokesh Vutla]

Hi Thomas,

On Wednesday 16 August 2017 02:37 AM, Thomas Petazzoni wrote:
> Hello,
> 
> As you probably noticed with the few patches I sent late July, I am
> porting U-Boot to an old SH7786 platform. As part of this effort, I
> stumbled across a bug: the global_data structure is not initialized to
> zero by the SuperH architecture code before calling board_init_f().
> 
> The SuperH architecture code defines the global data in
> arch/sh/lib/start.S:
> 
> mov.l   ._gd_init, r13  /* global data */
> [...]
> mov.l   ._sh_generic_init, r0
> jsr @r0
> [...]
> ._gd_init:  .long   (_start - GENERATED_GBL_DATA_SIZE)
> ._sh_generic_init:  .long   board_init_f
> 
> So basically, it makes r13 points to the global data (which is expected
> on this architecture), and then calls board_init_f().
> 
> Hence, we enter board_init_f() with global_data uninitialized, which
> have caused me quite some troubles, as I was seeing semi-random
> behavior: in various places, we test if a pointer in global_data is
> NULL or not to decide to do something (or not). This obviously goes
> really bad when global_data contains garbage.
> 
> Should we put global_data within the .bss section, so that it gets
> zero-initialized automatically? Should we zero-initialize it explicitly?

I am not sure how SuperH allocates the space for global data but
typically the following two function takes care of allocating and
zeroing global data(at least for arm):

In file common/init/board_init.c
board_init_f_alloc_reserve()
board_init_f_init_reserve()

May be, using these two functions might solve your problem.

Thanks and regards,
Lokesh

> 
> I've currently worked-around the problem by adding a memset() to zero
> of the global_data at the beginning of board_init_f(), but I'd prefer
> to find an upstreamable fix.
> 
> Thanks!
> 
> Thomas Petazzoni
> 
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Re: [U-Boot] [PATCH 0/3] arm: am57xx/dra7xx: Boot Android from eMMC

[Tom Rini]

On Tue, Aug 15, 2017 at 04:30:00PM +0300, Sam Protsenko wrote:

> Provide a way to boot Android from eMMC for AM57xx EVM and DRA7 EVM boards.
> 
> Sam Protsenko (3):
>   arm: omap: Define command for booting Android from eMMC
>   arm: am57xx: Define Android boot arguments
>   arm: dra7xx: Define Android boot arguments
> 
>  configs/am57xx_evm_defconfig  |  2 ++
>  configs/am57xx_evm_nodt_defconfig |  2 ++
>  configs/am57xx_hs_evm_defconfig   |  2 ++
>  configs/dra7xx_evm_defconfig  |  2 ++
>  configs/dra7xx_hs_evm_defconfig   |  2 ++
>  include/environment/ti/boot.h | 24 +++-
>  6 files changed, 29 insertions(+), 5 deletions(-)

This series seems to switch from "standard" Linux boot to Android Linux
boot, rather than allowing a fallback from one to the other.  Yes?  If
so, that's a problem.  Thanks!

-- 
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Re: [U-Boot] [PATCH 2/2] sf: Preserve QE bit when clearing BP# bits for Macronix flash

[Bin Meng]

Hi Jagan,

On Mon, Aug 14, 2017 at 1:35 PM, Bin Meng  wrote:
> Hi Jagan,
>
> On Mon, Aug 14, 2017 at 1:17 PM, Jagan Teki  wrote:
>> On Mon, Aug 14, 2017 at 10:34 AM, Bin Meng  wrote:
>>> Hi Jagan,
>>>
>>> On Mon, Aug 14, 2017 at 12:58 PM, Jagan Teki  
>>> wrote:
 Hi Bin,

 On Mon, Aug 14, 2017 at 8:07 AM, Bin Meng  wrote:
> Hi Jagan,
>
> On Mon, Aug 14, 2017 at 1:22 AM, Jagan Teki  
> wrote:
>> Hi Bin,
>>
>> On Wed, Aug 2, 2017 at 3:56 AM, Bin Meng  wrote:
>>> Hi Jagan,
>>>
>>> On Wed, Aug 2, 2017 at 12:01 AM, Jagan Teki  
>>> wrote:
 On Sun, Jul 23, 2017 at 8:14 PM, Bin Meng  wrote:
> On some flash (like Macronix), QE (quad enable) bit is in the same
> status register as BP# bits, and we need preserve its original value
> during a reboot cycle as this is required by some platforms (like
> Intel ICH SPI controller working under descriptor mode).
>
> Signed-off-by: Bin Meng 
> ---
>
>  drivers/mtd/spi/spi_flash.c | 17 +++--
>  1 file changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
> index 0034a28..7d8c660 100644
> --- a/drivers/mtd/spi/spi_flash.c
> +++ b/drivers/mtd/spi/spi_flash.c
> @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash)
> if (IS_ERR_OR_NULL(info))
> return -ENOENT;
>
> -   /* Flash powers up read-only, so clear BP# bits */
> +   /*
> +* Flash powers up read-only, so clear BP# bits.
> +*
> +* Note on some flash (like Macronix), QE (quad enable) bit 
> is in the
> +* same status register as BP# bits, and we need preserve its 
> original
> +* value during a reboot cycle as this is required by some 
> platforms
> +* (like Intel ICH SPI controller working under descriptor 
> mode).
> +*/
> if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL ||
> -   JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX ||
> JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST)
> write_sr(flash, 0);
> +   if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) {
> +   u8 sr = 0;
> +
> +   read_sr(flash, );
> +   sr &= STATUS_QEB_MXIC;
> +   write_sr(flash, sr);

 Better assign sr with QEB for macronix and call write_sr once.
>>>
>>> For these Macronix flashes that does not support quard RW, QEB bit is
>>> reserved. Writing 1 to a reserved bit is not a good practice.
>>
>> Yeah, i.e what I'm concern here. (apart from fixing comment) this
>> issue came-up with your controller along with specific connected chip
>> which support RW WEB.
>
> As I said, this is nothing related to the SPI controller driver. It
> can (technically) happen on other platforms. I don't understand what
> your concerns here. Your suggestion of writing SR once does not work.
>
>>
>> What if we couldn't preserve QEB? because if user need quad operation
>> anyway code will check QEB if not it will enable.
>
> The board simply bricks after a successful boot once. Because the QE
> bit is cleared by U-Boot during this successful boot, next time when
> the board powers-up, the SoC won't get a valid bootstrap setting from
> SPI flash. The bootstrap settings are stored in the SPI flash and
> there is a QE bit enable in the bootstrap setting. When SoC finds out
> the QE bit is turned on in the bootstrap setting but SPI flash's QE
> bit is off, the SoC refuses to boot.
>

Sadly, this discussion ends to nowhere again. Can you please indicate
your clear opinion on how to proceed?

Regards,
Bin
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[U-Boot] [PATCH v1 2/2] imx: use BOOT_DEVICE_BOARD instead of UART

[Stefan Agner]

From: Stefan Agner 

i.MX 6 serial downloader is not necessarily booting via UART but can
also boot from USB. In fact only some i.MX chips have serial
downloader support via UART (e.g. 6UL/ULL and Vybrid) but all of
them have serial downloader support via USB. Use the more appropriate
BOOT_DEVICE_BOARD define which is used for ROM provided recovery
mechanisms in general.

Signed-off-by: Stefan Agner 
---

 arch/arm/mach-imx/spl.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 836b334fa9..bcd1033fdb 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -27,7 +27,7 @@ u32 spl_boot_device(void)
 * BOOT_MODE - see IMX6DQRM Table 8-1
 */
if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
-   return BOOT_DEVICE_UART;
+   return BOOT_DEVICE_BOARD;
 
/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
switch ((reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
@@ -43,7 +43,7 @@ u32 spl_boot_device(void)
}
/* Reserved: Used to force Serial Downloader */
case IMX6_BMODE_RESERVED:
-   return BOOT_DEVICE_UART;
+   return BOOT_DEVICE_BOARD;
/* SATA: See 8.5.4, Table 8-20 */
case IMX6_BMODE_SATA:
return BOOT_DEVICE_SATA;
-- 
2.14.1

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[U-Boot] [PATCH v1 1/2] imx: fix USB boot mode detection for i.MX 6UL and 6ULL

[Stefan Agner]

From: Stefan Agner 

Add the reserved boot mode used in the bmode command for i.MX 6UL
and 6ULL as introduced in commit 3fd9579085fa ("imx: mx6ull: fix USB
bmode for i.MX 6UL and 6ULL").

Also replace BMODE_UART with BMODE_RESERVED, which is more appropriate.
Commit 96aac843b68d ("imx: Use IMX6_BMODE_* macros instead of numericals")
added macros for boot modes, in the process the reserved boot mode got
named BMODE_UART. We use the reserved boot mode in the bmode command to
let the boot ROM enter serial downloader recovery mode. But this is only
a side effect, the actual boot mode is reserved...

Signed-off-by: Stefan Agner 
---
Afaik there is no board yet using SPL on 6UL/ULL...

 arch/arm/include/asm/mach-imx/sys_proto.h | 7 ++-
 arch/arm/mach-imx/spl.c   | 2 +-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h 
b/arch/arm/include/asm/mach-imx/sys_proto.h
index 046df6291a..d94c095118 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -69,8 +69,13 @@ enum imx6_bmode_emi {
 
 enum imx6_bmode {
IMX6_BMODE_EMI,
-   IMX6_BMODE_UART,
+#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+   IMX6_BMODE_QSPI,
+   IMX6_BMODE_RESERVED,
+#else
+   IMX6_BMODE_RESERVED,
IMX6_BMODE_SATA,
+#endif
IMX6_BMODE_SERIAL_ROM,
IMX6_BMODE_SD,
IMX6_BMODE_ESD,
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 75698c48ea..836b334fa9 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -42,7 +42,7 @@ u32 spl_boot_device(void)
break;
}
/* Reserved: Used to force Serial Downloader */
-   case IMX6_BMODE_UART:
+   case IMX6_BMODE_RESERVED:
return BOOT_DEVICE_UART;
/* SATA: See 8.5.4, Table 8-20 */
case IMX6_BMODE_SATA:
-- 
2.14.1

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Re: [U-Boot] [PATCH 1/2] board/spear/common: move code to arch/arm/cpu/arm926ejs/spear/

[Tom Rini]

On Tue, Aug 15, 2017 at 10:52:44PM +0200, Thomas Petazzoni wrote:

> The code in board/spear/common/ is not board-specific but
> SoC-specific. Therefore, boards from other vendors than "spear" may
> want to re-use this code, which is currently difficult with the code
> being placed in board/spear/common/.
> 
> Since this code really is SoC-specific, this commit moves it to
> arch/arm/cpu/arm926ejs/spear/, with the rest of the SPEAr related
> code.
> 
> Signed-off-by: Thomas Petazzoni 
> ---
>  arch/arm/cpu/arm926ejs/spear/Makefile  |  2 ++
>  .../arm/cpu/arm926ejs/spear}/spr_lowlevel_init.S   |  0
>  .../common => arch/arm/cpu/arm926ejs/spear}/spr_misc.c |  0
>  board/spear/common/Makefile| 14 
> --
>  4 files changed, 2 insertions(+), 14 deletions(-)
>  rename {board/spear/common => 
> arch/arm/cpu/arm926ejs/spear}/spr_lowlevel_init.S (100%)
>  rename {board/spear/common => arch/arm/cpu/arm926ejs/spear}/spr_misc.c (100%)
>  delete mode 100644 board/spear/common/Makefile

So, I asked Stefan to do some cleanups related to SPEAr a while ago, but
he's been unable to find the time I believe.  Would you have interest in
being perhaps co-maintainer of these platforms?  Otherwise I fear they
need dropping due to lack of Kconfig migration.  Thanks!

-- 
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Re: [U-Boot] [PATCH v1 2/7] usb: gadget: add SDP driver

[Stefan Agner]

On 2017-08-10 01:14, Stefano Babic wrote:
> Hi Stefan,
> 
> On 05/08/2017 01:38, Stefan Agner wrote:
>> From: Stefan Agner 
>>
>> Add SDP (Serial Downloader Protocol) implementation for U-Boot. The
>> protocol is used in NXP SoC's boot ROM and allows to download program
>> images. Beside that, it can also be used to read/write registers and
>> download complete Device Configuration Data (DCD) sets. This basic
>> implementation supports downloading images with the imx header format
>> and reading registers.
>>
>> Signed-off-by: Stefan Agner 
>> ---
>>
>>  drivers/usb/gadget/Kconfig  |   7 +
>>  drivers/usb/gadget/Makefile |   1 +
>>  drivers/usb/gadget/f_sdp.c  | 723 
>> 
>>  include/sdp.h   |  16 +
>>  4 files changed, 747 insertions(+)
>>  create mode 100644 drivers/usb/gadget/f_sdp.c
>>  create mode 100644 include/sdp.h
>>
>> diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
>> index 261ed128ac..225b66bc95 100644
>> --- a/drivers/usb/gadget/Kconfig
>> +++ b/drivers/usb/gadget/Kconfig
>> @@ -103,6 +103,13 @@ config USB_GADGET_DOWNLOAD
>>
>>  if USB_GADGET_DOWNLOAD
>>
>> +config USB_FUNCTION_SDP
>> +bool "Enable USB SDP (Serial Download Protocol)"
>> +help
>> +  Enable Serial Download Protocol (SDP) device support in U-Boot. This
>> +  allows to download images into memory and execute (jump to) them
>> +  using the same protocol as implemented by the i.MX family's boot ROM.
>> +
>>  config G_DNL_MANUFACTURER
>>  string "Vendor name of USB device"
>>
>> diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
>> index 5e316a7cff..6a007d1bcb 100644
>> --- a/drivers/usb/gadget/Makefile
>> +++ b/drivers/usb/gadget/Makefile
>> @@ -28,6 +28,7 @@ obj-$(CONFIG_USB_FUNCTION_THOR) += f_thor.o
>>  obj-$(CONFIG_USB_FUNCTION_DFU) += f_dfu.o
>>  obj-$(CONFIG_USB_FUNCTION_MASS_STORAGE) += f_mass_storage.o
>>  obj-$(CONFIG_USB_FUNCTION_FASTBOOT) += f_fastboot.o
>> +obj-$(CONFIG_USB_FUNCTION_SDP) += f_sdp.o
>>  endif
>>  endif
>>  ifdef CONFIG_USB_ETHER
>> diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c
>> new file mode 100644
>> index 00..eb89695aaf
>> --- /dev/null
>> +++ b/drivers/usb/gadget/f_sdp.c
>> @@ -0,0 +1,723 @@
>> +/*
>> + * f_sdp.c -- USB HID Serial Download Protocol
>> + *
>> + * Copyright (C) 2016 Toradex
>> + * Author: Stefan Agner 
>> + *
>> + * This file implements the Serial Download Protocol (SDP) as specified in
>> + * the i.MX 6 Reference Manual. The SDP is a USB HID based protocol and
>> + * allows to download images directly to memory. The implementation
>> + * works with the imx_loader (imx_usb) USB client software on host side.
>> + *
>> + * Not all commands are implemented, e.g. WRITE_REGISTER, DCD_WRITE and
>> + * SKIP_DCD_HEADER are only stubs.
>> + *
>> + * Parts of the implementation are based on f_dfu and f_thor.
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#define HID_REPORT_ID_MASK  0x00ff
>> +
>> +/*
>> + * HID class requests
>> + */
>> +#define HID_REQ_GET_REPORT  0x01
>> +#define HID_REQ_GET_IDLE0x02
>> +#define HID_REQ_GET_PROTOCOL0x03
>> +#define HID_REQ_SET_REPORT  0x09
>> +#define HID_REQ_SET_IDLE0x0A
>> +#define HID_REQ_SET_PROTOCOL0x0B
>> +
>> +#define HID_USAGE_PAGE_LEN  76
>> +
>> +struct hid_report {
>> +u8 usage_page[HID_USAGE_PAGE_LEN];
>> +} __packed;
>> +
>> +#define SDP_READ_REGISTER   0x0101
>> +#define SDP_WRITE_REGISTER  0x0202
>> +#define SDP_WRITE_FILE  0x0404
>> +#define SDP_ERROR_STATUS0x0505
>> +#define SDP_DCD_WRITE   0x0a0a
>> +#define SDP_JUMP_ADDRESS0x0b0b
>> +#define SDP_SKIP_DCD_HEADER 0x0c0c
> 
> It looks like that I am again out of sync with documentation. Where is
> defined SDP_SKIP_DCD_HEADER ? It is undefined for MX6Q/D, Solo and DL.
> 

This is only available in newer SoC's e.g. i.MX 7.

It allows to skip the DCD header in a downloaded image. Since the DCD
header is anyway ignored by this SDP implementation, the command is kind
of useless. I still think it is a good idea to have the command type
define for completeness... And I think also some SDP host side
implementation might issue the command...

>> +
>> +#define SDP_WRITE_FILE_COMPLETE 0x
>> +#define SDP_WRITE_REGISTER_COMPLETE 0x128A8A12
>> +#define SDP_SKIP_DCD_HEADER_COMPLETE0x900DD009
>> +#define SDP_ERROR_IMXHEADER 0x000a0533
>> +
>> +#define SDP_COMMAND_LEN 16
>> +
>> +struct sdp_command {
>> +u16 cmd;
>> +u32 addr;
>> +u8 format;
>> +u32 cnt;
>> +u32 data;
>> +u8 rsvd;
>> +} __packed;
>> +
>> +enum 

[U-Boot] [PATCH] common/board_f.c: remove CONFIG_SYS_GENERIC_GLOBAL_DATA

[Thomas Petazzoni]

CONFIG_SYS_GENERIC_GLOBAL_DATA is no longer used by any board or
platform, so support for it can be dropped.

Signed-off-by: Thomas Petazzoni 
---
 README   |  6 --
 common/board_f.c | 27 ---
 scripts/config_whitelist.txt |  1 -
 3 files changed, 34 deletions(-)

diff --git a/README b/README
index 3fdb89c..15ac00d 100644
--- a/README
+++ b/README
@@ -404,12 +404,6 @@ The following options need to be configured:
supported, core will start to execute uboot when wakes up.
 
 - Generic CPU options:
-   CONFIG_SYS_GENERIC_GLOBAL_DATA
-   Defines global data is initialized in generic board 
board_init_f().
-   If this macro is defined, global data is created and cleared in
-   generic board board_init_f(). Without this macro, 
architecture/board
-   should initialize global data before calling board_init_f().
-
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
Defines the endianess of the CPU. Implementation of those
diff --git a/common/board_f.c b/common/board_f.c
index 5915e50..37bbf5a 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -211,14 +211,6 @@ static int init_func_spi(void)
 }
 #endif
 
-__maybe_unused
-static int zero_global_data(void)
-{
-   memset((void *)gd, '\0', sizeof(gd_t));
-
-   return 0;
-}
-
 static int setup_mon_len(void)
 {
 #if defined(__ARM__) || defined(__MICROBLAZE__)
@@ -910,25 +902,6 @@ static const init_fnc_t init_sequence_f[] = {
 
 void board_init_f(ulong boot_flags)
 {
-#ifdef CONFIG_SYS_GENERIC_GLOBAL_DATA
-   /*
-* For some architectures, global data is initialized and used before
-* calling this function. The data should be preserved. For others,
-* CONFIG_SYS_GENERIC_GLOBAL_DATA should be defined and use the stack
-* here to host global data until relocation.
-*/
-   gd_t data;
-
-   gd = 
-
-   /*
-* Clear global data before it is accessed at debug print
-* in initcall_run_list. Otherwise the debug print probably
-* get the wrong value of gd->have_console.
-*/
-   zero_global_data();
-#endif
-
gd->flags = boot_flags;
gd->have_console = 0;
 
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index db28457..2df02d0 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -3341,7 +3341,6 @@ CONFIG_SYS_GBIT_MII_BUSNAME
 CONFIG_SYS_GBL_DATA_OFFSET
 CONFIG_SYS_GBL_DATA_SIZE
 CONFIG_SYS_GENERIC_BOARD
-CONFIG_SYS_GENERIC_GLOBAL_DATA
 CONFIG_SYS_GIC400_ADDR
 CONFIG_SYS_GP1DIR
 CONFIG_SYS_GP1ODR
-- 
2.9.4

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[U-Boot] Initializing global_data on SuperH before board_init_f() ?

[Thomas Petazzoni]

Hello,

As you probably noticed with the few patches I sent late July, I am
porting U-Boot to an old SH7786 platform. As part of this effort, I
stumbled across a bug: the global_data structure is not initialized to
zero by the SuperH architecture code before calling board_init_f().

The SuperH architecture code defines the global data in
arch/sh/lib/start.S:

mov.l   ._gd_init, r13  /* global data */
[...]
mov.l   ._sh_generic_init, r0
jsr @r0
[...]
._gd_init:  .long   (_start - GENERATED_GBL_DATA_SIZE)
._sh_generic_init:  .long   board_init_f

So basically, it makes r13 points to the global data (which is expected
on this architecture), and then calls board_init_f().

Hence, we enter board_init_f() with global_data uninitialized, which
have caused me quite some troubles, as I was seeing semi-random
behavior: in various places, we test if a pointer in global_data is
NULL or not to decide to do something (or not). This obviously goes
really bad when global_data contains garbage.

Should we put global_data within the .bss section, so that it gets
zero-initialized automatically? Should we zero-initialize it explicitly?

I've currently worked-around the problem by adding a memset() to zero
of the global_data at the beginning of board_init_f(), but I'd prefer
to find an upstreamable fix.

Thanks!

Thomas Petazzoni
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Re: [U-Boot] [PATCH 1/3] arch/sh: don't bring common/env_embedded.o into the link

[Thomas Petazzoni]

Hello,

On Thu, 3 Aug 2017 08:20:20 +0900, Nobuhiro Iwamatsu wrote:
> Hi,
> 
> 2017-07-29 6:46 GMT+09:00 Thomas Petazzoni
> :
> > The linker script for SuperH brings the .ppcenv and .ppcenvr section
> > of common/env_embedded.o into the .text section. However, the .ppcenv
> > section is only ever filled in by env_embedded.o when
> > CONFIG_SYS_USE_PPCENV is defined, but no platforms in mainline U-Boot
> > use this.
> >
> > In addition, common/env_embedded.o is not always built (when you use
> > CONFIG_ENV_IS_NOWHERE for example), which causes the following build
> > failure:
> >
> > Fixes:
> >
> >   LD  u-boot
> > /home/thomas/sh4aeb-linux-musl/bin/sh4aeb-linux-ld.bfd: cannot find 
> > common/env_embedded.o
> >
> > We fix this by no longer adding the .ppcenv and .ppcenvr sections from
> > common/env_embedded.o into the .text section.
> >
> > Signed-off-by: Thomas Petazzoni   
> 
> Acked-by: Nobuhiro Iwamatsu 

Thanks for your review! Are you going to apply the patch, as you did
for "arch/sh: allow building in big-endian mode" ?

Thanks!

Thomas
-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com
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[U-Boot] [PATCH 2/2] arch/arm/cpu/arm926ejs/spear/cpu.c: guard do_switch_ecc() with CONFIG_NAND_FSMC

[Thomas Petazzoni]

do_switch_ecc() calls fsmc_nand_switch_ecc(), which is a direct
function call into drivers/mtd/nand/fsmc_nand.c. However, this
function is not guarded by CONFIG_NAND_FSMC, which results to a build
failure if CONFIG_NAND_FSMC is disabled.

Signed-off-by: Thomas Petazzoni 
---
 arch/arm/cpu/arm926ejs/spear/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c 
b/arch/arm/cpu/arm926ejs/spear/cpu.c
index be0d14f..7b9dc65 100644
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -84,7 +84,7 @@ int print_cpuinfo(void)
 }
 #endif
 
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH)
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH) && 
defined(CONFIG_NAND_FSMC)
 static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
 char *const argv[])
 {
-- 
2.9.4

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[U-Boot] [PATCH 1/2] board/spear/common: move code to arch/arm/cpu/arm926ejs/spear/

[Thomas Petazzoni]

The code in board/spear/common/ is not board-specific but
SoC-specific. Therefore, boards from other vendors than "spear" may
want to re-use this code, which is currently difficult with the code
being placed in board/spear/common/.

Since this code really is SoC-specific, this commit moves it to
arch/arm/cpu/arm926ejs/spear/, with the rest of the SPEAr related
code.

Signed-off-by: Thomas Petazzoni 
---
 arch/arm/cpu/arm926ejs/spear/Makefile  |  2 ++
 .../arm/cpu/arm926ejs/spear}/spr_lowlevel_init.S   |  0
 .../common => arch/arm/cpu/arm926ejs/spear}/spr_misc.c |  0
 board/spear/common/Makefile| 14 --
 4 files changed, 2 insertions(+), 14 deletions(-)
 rename {board/spear/common => 
arch/arm/cpu/arm926ejs/spear}/spr_lowlevel_init.S (100%)
 rename {board/spear/common => arch/arm/cpu/arm926ejs/spear}/spr_misc.c (100%)
 delete mode 100644 board/spear/common/Makefile

diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile 
b/arch/arm/cpu/arm926ejs/spear/Makefile
index 7b15d4e..3992401 100644
--- a/arch/arm/cpu/arm926ejs/spear/Makefile
+++ b/arch/arm/cpu/arm926ejs/spear/Makefile
@@ -16,6 +16,8 @@ obj-$(CONFIG_DDR_MT47H64M16) += 
spr600_mt47h64m16_3_333_cl5_psync.o
 obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
 obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
 obj-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
+else
+obj-y += spr_misc.o spr_lowlevel_init.o
 endif
 
 extra-$(CONFIG_SPL_BUILD) := start.o
diff --git a/board/spear/common/spr_lowlevel_init.S 
b/arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S
similarity index 100%
rename from board/spear/common/spr_lowlevel_init.S
rename to arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S
diff --git a/board/spear/common/spr_misc.c 
b/arch/arm/cpu/arm926ejs/spear/spr_misc.c
similarity index 100%
rename from board/spear/common/spr_misc.c
rename to arch/arm/cpu/arm926ejs/spear/spr_misc.c
diff --git a/board/spear/common/Makefile b/board/spear/common/Makefile
deleted file mode 100644
index b0ba320..000
--- a/board/spear/common/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-# necessary to create built-in.o
-obj- := __dummy__.o
-else
-obj-y  := spr_misc.o
-obj-y  += spr_lowlevel_init.o
-endif
-- 
2.9.4

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Re: [U-Boot] [PATCH 4/5] vsprintf.c: add GUID printing

[Heinrich Schuchardt]

On 08/10/2017 01:14 AM, Rob Clark wrote:
> This works (roughly) the same way as linux's, but we currently always
> print lower-case (ie. we just keep %pUB and %pUL for compat with linux),
> mostly just because that is what uuid_bin_to_str() supports.
> 
>   %pUb:   01020304-0506-0708-090a-0b0c0d0e0f10
>   %pUl:   04030201-0605-0807-090a-0b0c0d0e0f10
> 
> It will be used by a later efi_loader paths for efi variables and for
> device-path-to-text protocol, and also quite useful for debug prints
> of protocol GUIDs.
> 
> Signed-off-by: Rob Clark 
> ---
>  examples/api/Makefile  |  1 +
>  include/config_fallbacks.h |  1 +
>  lib/vsprintf.c | 46 
> --
>  3 files changed, 46 insertions(+), 2 deletions(-)
> 
> diff --git a/examples/api/Makefile b/examples/api/Makefile
> index 87c15d0f68..899527267d 100644
> --- a/examples/api/Makefile
> +++ b/examples/api/Makefile
> @@ -35,6 +35,7 @@ EXT_COBJ-y += lib/string.o
>  EXT_COBJ-y += lib/time.o
>  EXT_COBJ-y += lib/vsprintf.o
>  EXT_COBJ-y += lib/charset.o
> +EXT_COBJ-$(CONFIG_LIB_UUID) += lib/uuid.o
>  EXT_SOBJ-$(CONFIG_PPC) += arch/powerpc/lib/ppcstring.o
>  ifeq ($(ARCH),arm)
>  EXT_SOBJ-$(CONFIG_USE_ARCH_MEMSET) += arch/arm/lib/memset.o
> diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h
> index 961a83d758..56b9de09f2 100644
> --- a/include/config_fallbacks.h
> +++ b/include/config_fallbacks.h
> @@ -57,6 +57,7 @@
>  
>  #if (CONFIG_IS_ENABLED(PARTITION_UUIDS) || \
>   CONFIG_IS_ENABLED(EFI_PARTITION) || \
> + CONFIG_IS_ENABLED(EFI_LOADER) || \
>   defined(CONFIG_RANDOM_UUID) || \
>   defined(CONFIG_CMD_UUID) || \
>   defined(CONFIG_BOOTP_PXE)) && \
> diff --git a/lib/vsprintf.c b/lib/vsprintf.c
> index 0678b49b01..71a995dee0 100644
> --- a/lib/vsprintf.c
> +++ b/lib/vsprintf.c
> @@ -18,6 +18,7 @@
>  
>  #include 
>  #include 
> +#include 
>  
>  #include 
>  #define noinline __attribute__((noinline))
> @@ -366,6 +367,40 @@ static char *ip4_addr_string(char *buf, char *end, u8 
> *addr, int field_width,
>  }
>  #endif
>  
> +#ifdef CONFIG_LIB_UUID
> +/*
> + * This works (roughly) the same way as linux's, but we currently always
> + * print lower-case (ie. we just keep %pUB and %pUL for compat with linux),
> + * mostly just because that is what uuid_bin_to_str() supports.
> + *
> + *   %pUb:   01020304-0506-0708-090a-0b0c0d0e0f10
> + *   %pUl:   04030201-0605-0807-090a-0b0c0d0e0f10
> + */
> +static char *uuid_string(char *buf, char *end, u8 *addr, int field_width,
> +  int precision, int flags, const char *fmt)
> +{
> + char uuid[UUID_STR_LEN + 1];
> + int str_format = UUID_STR_FORMAT_STD;
> +
> + switch (*(++fmt)) {
> + case 'L':
> + case 'l':
> + str_format = UUID_STR_FORMAT_GUID;
> + break;
> + case 'B':
> + case 'b':
> + /* this is the default */
> + break;
> + default:
> + break;
> + }
> +
> + uuid_bin_to_str(addr, uuid, str_format);
> +
> + return string(buf, end, uuid, field_width, precision, flags);
> +}
> +#endif
> +
>  /*
>   * Show a '%p' thing.  A kernel extension is that the '%p' is followed
>   * by an extra set of alphanumeric characters that are extended format
> @@ -399,8 +434,8 @@ static char *pointer(const char *fmt, char *buf, char 
> *end, void *ptr,
> flags);
>  #endif
>  
> -#ifdef CONFIG_CMD_NET
>   switch (*fmt) {
> +#ifdef CONFIG_CMD_NET
>   case 'a':
>   flags |= SPECIAL | ZEROPAD;
>  
> @@ -430,8 +465,15 @@ static char *pointer(const char *fmt, char *buf, char 
> *end, void *ptr,
>  precision, flags);
>   flags &= ~SPECIAL;
>   break;
> - }
>  #endif
> +#ifdef CONFIG_LIB_UUID
> + case 'U':
> + return uuid_string(buf, end, ptr, field_width, precision,
> +flags, fmt);
> +#endif
> + default:
> + break;
> + }
>   flags |= SMALL;
>   if (field_width == -1) {
>   field_width = 2*sizeof(void *);
> 

Successfully tested printing using %pUl with a patch under development
on arm64.

Tested-by: Heinrich Schuchardt 
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[U-Boot] [PATCH 1/1] efi_loader: allow return value in EFI_CALL

[Heinrich Schuchardt]

Macro EFI_CALL was introduced to call an UEFI function.
Unfortunately is did not support return values.
Most UEFI functions have a return value.

So let's rename EFI_CALL to EFI_CALL_VOID and introduce a
new EFI_CALL macro that supports return values.

Signed-off-by: Heinrich Schuchardt 
---
 include/efi_loader.h  | 16 ++--
 lib/efi_loader/efi_boottime.c |  3 ++-
 2 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/include/efi_loader.h b/include/efi_loader.h
index 037cc7c543..1cee10ea0c 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -41,9 +41,21 @@ const char *__efi_nesting_dec(void);
})
 
 /*
- * Callback into UEFI world from u-boot:
+ * Call non-void UEFI function from u-boot and retrieve return value:
  */
-#define EFI_CALL(exp) do { \
+#define EFI_CALL(exp) ({ \
+   debug("%sEFI: Call: %s\n", __efi_nesting_inc(), #exp); \
+   assert(__efi_exit_check()); \
+   typeof(exp) r = exp; \
+   assert(__efi_entry_check()); \
+   debug("%sEFI: Return From: %s\n", __efi_nesting_dec(), #exp); \
+   r; \
+})
+
+/*
+ * Call void UEFI function world from u-boot:
+ */
+#define EFI_CALL_VOID(exp) do { \
debug("%sEFI: Call: %s\n", __efi_nesting_inc(), #exp); \
assert(__efi_exit_check()); \
exp; \
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 43f32385fa..6489a32505 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -158,7 +158,8 @@ void efi_signal_event(struct efi_event *event)
return;
event->signaled = 1;
if (event->type & EVT_NOTIFY_SIGNAL) {
-   EFI_CALL(event->notify_function(event, event->notify_context));
+   EFI_CALL_VOID(event->notify_function(event,
+event->notify_context));
}
 }
 
-- 
2.14.1

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[U-Boot] [PATCH v3 4/5] spl: fit: Support both external and embedded data

[York Sun]

SPL supports U-Boot image in FIT format which has data outside of
FIT structure. This adds support for embedded data for normal FIT
images.

Signed-off-by: York Sun 
Reviewed-by: Tom Rini 

---

Changes in v3:
Update doc/uImage.FIT/source_file_format.txt with embedded and external data

Changes in v2:
Rebase on top of "SPL: FIT: factor out spl_load_fit_image()" by Andre Przywara

 common/spl/spl_fit.c  | 52 ++-
 doc/uImage.FIT/source_file_format.txt |  4 +++
 2 files changed, 37 insertions(+), 19 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index fe41ce0..9449a22 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -132,14 +132,16 @@ static int spl_load_fit_image(struct spl_load_info *info, 
ulong sector,
  void *fit, ulong base_offset, int node,
  struct spl_image_info *image_info)
 {
-   ulong offset;
+   int offset;
size_t length;
+   int len;
ulong load_addr, load_ptr;
void *src;
ulong overhead;
int nr_sectors;
int align_len = ARCH_DMA_MINALIGN - 1;
uint8_t image_comp = -1, type = -1;
+   const void *data;
 
if (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP)) {
if (fit_image_get_comp(fit, node, _comp))
@@ -153,28 +155,40 @@ static int spl_load_fit_image(struct spl_load_info *info, 
ulong sector,
debug("%s ", genimg_get_type_name(type));
}
 
-   offset = fdt_getprop_u32(fit, node, "data-offset");
-   if (offset == FDT_ERROR)
-   return -ENOENT;
-   offset += base_offset;
-   length = fdt_getprop_u32(fit, node, "data-size");
-   if (length == FDT_ERROR)
-   return -ENOENT;
-   load_addr = fdt_getprop_u32(fit, node, "load");
-   if (load_addr == FDT_ERROR && image_info)
+   if (fit_image_get_load(fit, node, _addr))
load_addr = image_info->load_addr;
-   load_ptr = (load_addr + align_len) & ~align_len;
 
-   overhead = get_aligned_image_overhead(info, offset);
-   nr_sectors = get_aligned_image_size(info, length, offset);
+   if (!fit_image_get_data_offset(fit, node, )) {
+   /* External data */
+   offset += base_offset;
+   if (fit_image_get_data_size(fit, node, ))
+   return -ENOENT;
 
-   if (info->read(info, sector + get_aligned_image_offset(info, offset),
-  nr_sectors, (void*)load_ptr) != nr_sectors)
-   return -EIO;
-   debug("image dst=%lx, offset=%lx, size=%lx\n", load_ptr, offset,
- (unsigned long)length);
+   load_ptr = (load_addr + align_len) & ~align_len;
+   length = len;
+
+   overhead = get_aligned_image_overhead(info, offset);
+   nr_sectors = get_aligned_image_size(info, length, offset);
+
+   if (info->read(info,
+  sector + get_aligned_image_offset(info, offset),
+  nr_sectors, (void *)load_ptr) != nr_sectors)
+   return -EIO;
+
+   debug("External data: dst=%lx, offset=%x, size=%lx\n",
+ load_ptr, offset, (unsigned long)length);
+   src = (void *)load_ptr + overhead;
+   } else {
+   /* Embedded data */
+   if (fit_image_get_data(fit, node, , )) {
+   puts("Cannot get image data/size\n");
+   return -ENOENT;
+   }
+   debug("Embedded data: dst=%lx, size=%lx\n", load_addr,
+ (unsigned long)length);
+   src = (void *)data;
+   }
 
-   src = (void *)load_ptr + overhead;
 #ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
board_fit_image_post_process(, );
 #endif
diff --git a/doc/uImage.FIT/source_file_format.txt 
b/doc/uImage.FIT/source_file_format.txt
index 136d3d7..3ce47ed 100644
--- a/doc/uImage.FIT/source_file_format.txt
+++ b/doc/uImage.FIT/source_file_format.txt
@@ -288,6 +288,10 @@ The 'data-offset' property can be substituted with 
'data-position', which
 defines an absolute position or address as the offset. This is helpful when
 booting U-Boot proper before performing relocation.
 
+Normal kernel FIT image has data embedded within FIT structure. Normal U-Boot
+image has external data. Existence of 'data-offset' can be used to identify
+which format is used.
+
 9) Examples
 ---
 
-- 
2.7.4

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[U-Boot] [PATCH v3 2/5] cmd: spl: Fix compiling warning

[York Sun]

Fix warning "cast from pointer to integer of different size".

Signed-off-by: York Sun 
Reviewed-by: Tom Rini 
---

Changes in v3: None
Changes in v2: None

 cmd/spl.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/cmd/spl.c b/cmd/spl.c
index 057764a..562140a 100644
--- a/cmd/spl.c
+++ b/cmd/spl.c
@@ -108,12 +108,12 @@ static int spl_export(cmd_tbl_t *cmdtp, int flag, int 
argc, char * const argv[])
 
c = find_cmd_tbl(argv[1], _spl_export_sub[0],
ARRAY_SIZE(cmd_spl_export_sub));
-   if ((c) && ((int)c->cmd <= SPL_EXPORT_LAST)) {
+   if ((c) && ((long)c->cmd <= SPL_EXPORT_LAST)) {
argc -= 2;
argv += 2;
-   if (call_bootm(argc, argv, subcmd_list[(int)c->cmd]))
+   if (call_bootm(argc, argv, subcmd_list[(long)c->cmd]))
return -1;
-   switch ((int)c->cmd) {
+   switch ((long)c->cmd) {
 #ifdef CONFIG_OF_LIBFDT
case SPL_EXPORT_FDT:
printf("Argument image is now in RAM: 0x%p\n",
@@ -147,7 +147,7 @@ static int do_spl(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 
c = find_cmd_tbl(argv[1], _spl_sub[0], ARRAY_SIZE(cmd_spl_sub));
if (c) {
-   cmd = (int)c->cmd;
+   cmd = (long)c->cmd;
switch (cmd) {
case SPL_EXPORT:
argc--;
-- 
2.7.4

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[U-Boot] [PATCH v3 3/5] spl: fit: Eanble GZIP support for image decompression

[York Sun]

Add Kconfig option SPL_GZIP and SPL_ZLIB to enable gunzip support for
SPL boot, eg. falcon boot compressed kernel image.

Signed-off-by: York Sun 
Reviewed-by: Tom Rini 

---

Changes in v3:
Replace ifdef with if IS_ENABLED().
Add help to new Kconfig optons.

Changes in v2:
Combine Kconfig change and actual code into one patch

 common/spl/spl_fit.c | 32 ++--
 lib/Kconfig  | 12 
 lib/Makefile |  5 +++--
 3 files changed, 45 insertions(+), 4 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index d2a352e..fe41ce0 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -11,6 +11,10 @@
 #include 
 #include 
 
+#ifndef CONFIG_SYS_BOOTM_LEN
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)
+#endif
+
 /**
  * spl_fit_get_image_node(): By using the matching configuration subnode,
  * retrieve the name of an image, specified by a property name and an index
@@ -135,6 +139,19 @@ static int spl_load_fit_image(struct spl_load_info *info, 
ulong sector,
ulong overhead;
int nr_sectors;
int align_len = ARCH_DMA_MINALIGN - 1;
+   uint8_t image_comp = -1, type = -1;
+
+   if (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP)) {
+   if (fit_image_get_comp(fit, node, _comp))
+   puts("Cannot get image compression format.\n");
+   else
+   debug("%s ", genimg_get_comp_name(image_comp));
+
+   if (fit_image_get_type(fit, node, ))
+   puts("Cannot get image type.\n");
+   else
+   debug("%s ", genimg_get_type_name(type));
+   }
 
offset = fdt_getprop_u32(fit, node, "data-offset");
if (offset == FDT_ERROR)
@@ -154,7 +171,7 @@ static int spl_load_fit_image(struct spl_load_info *info, 
ulong sector,
if (info->read(info, sector + get_aligned_image_offset(info, offset),
   nr_sectors, (void*)load_ptr) != nr_sectors)
return -EIO;
-   debug("image: dst=%lx, offset=%lx, size=%lx\n", load_ptr, offset,
+   debug("image dst=%lx, offset=%lx, size=%lx\n", load_ptr, offset,
  (unsigned long)length);
 
src = (void *)load_ptr + overhead;
@@ -162,7 +179,18 @@ static int spl_load_fit_image(struct spl_load_info *info, 
ulong sector,
board_fit_image_post_process(, );
 #endif
 
-   memcpy((void*)load_addr, src, length);
+   if (IS_ENABLED(CONFIG_SPL_OS_BOOT)  &&
+   IS_ENABLED(CONFIG_SPL_GZIP) &&
+   image_comp == IH_COMP_GZIP  &&
+   type == IH_TYPE_KERNEL) {
+   if (gunzip((void *)load_addr, CONFIG_SYS_BOOTM_LEN,
+  src, )) {
+   puts("Uncompressing error\n");
+   return -EIO;
+   }
+   } else {
+   memcpy((void *)load_addr, src, length);
+   }
 
if (image_info) {
image_info->load_addr = load_addr;
diff --git a/lib/Kconfig b/lib/Kconfig
index 2f5a210..3b5e3b4 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -160,6 +160,18 @@ config LZO
bool "Enable LZO decompression support"
help
  This enables support for LZO compression algorithm.r
+
+config SPL_GZIP
+   bool "Enable gzip decompression support for SPL build"
+   select SPL_ZLIB
+   help
+ This enables support for GZIP compression altorithm for SPL boot.
+
+config SPL_ZLIB
+   bool
+   help
+ This enables compression lib for SPL boot.
+
 endmenu
 
 config ERRNO_STR
diff --git a/lib/Makefile b/lib/Makefile
index eacc7d6..455cc9d 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -11,7 +11,6 @@ obj-$(CONFIG_EFI) += efi/
 obj-$(CONFIG_EFI_LOADER) += efi_loader/
 obj-$(CONFIG_LZMA) += lzma/
 obj-$(CONFIG_LZO) += lzo/
-obj-$(CONFIG_ZLIB) += zlib/
 obj-$(CONFIG_BZIP2) += bzip2/
 obj-$(CONFIG_TIZEN) += tizen/
 obj-$(CONFIG_FIT) += libfdt/
@@ -26,7 +25,6 @@ obj-y += crc16.o
 obj-$(CONFIG_ERRNO_STR) += errno_str.o
 obj-$(CONFIG_FIT) += fdtdec_common.o
 obj-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o
-obj-$(CONFIG_GZIP) += gunzip.o
 obj-$(CONFIG_GZIP_COMPRESSED) += gzip.o
 obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o
 obj-y += initcall.o
@@ -49,6 +47,9 @@ obj-$(CONFIG_RSA) += rsa/
 obj-$(CONFIG_SHA1) += sha1.o
 obj-$(CONFIG_SHA256) += sha256.o
 
+obj-$(CONFIG_$(SPL_)ZLIB) += zlib/
+obj-$(CONFIG_$(SPL_)GZIP) += gunzip.o
+
 obj-$(CONFIG_SPL_SAVEENV) += qsort.o
 obj-$(CONFIG_$(SPL_)OF_LIBFDT) += libfdt/
 ifneq ($(CONFIG_SPL_BUILD)$(CONFIG_SPL_OF_PLATDATA),yy)
-- 
2.7.4

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[U-Boot] [PATCH v3 5/5] spl: fit: Add booting OS first

[York Sun]

If CONFIG_SPL_OS_BOOT is enabled, boot OS if kernel image is found
in FIT structure.

Signed-off-by: York Sun 
Reviewed-by: Tom Rini 

---
This presums the kernel image doesn't exist in a FIT image intended for
U-Boot. If kernel image normally co-exists with U-Boot and other images
and user intends to boot U-Boot, this patch needs to rewrite to favor
"loadables" over either "firmware" or "kernel" so user can select which
image to boot.

Changes in v3:
Update doc/uImage.FIT/multi_spl.its to explain the priority of booting image.

Changes in v2:
Split from previous patch, rebased on top of "SPL: FIT: allow loading
multiple images" by Andre Przywara.

 common/spl/spl_fit.c | 60 ++--
 doc/uImage.FIT/multi_spl.its |  7 ++
 2 files changed, 48 insertions(+), 19 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 9449a22..49ccf1c 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -222,13 +222,16 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
ulong size;
unsigned long count;
struct spl_image_info image_info;
-   int node, images, ret;
+   bool boot_os = false;
+   int node = -1;
+   int images, ret;
int base_offset, align_len = ARCH_DMA_MINALIGN - 1;
int index = 0;
 
/*
-* Figure out where the external images start. This is the base for the
-* data-offset properties in each image.
+* For FIT with external data, figure out where the external images
+* start. This is the base for the data-offset properties in each
+* image.
 */
size = fdt_totalsize(fit);
size = (size + 3) & ~3;
@@ -247,6 +250,9 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
 *
 * In fact the FIT has its own load address, but we assume it cannot
 * be before CONFIG_SYS_TEXT_BASE.
+*
+* For FIT with data embedded, data is loaded as part of FIT image.
+* For FIT with external data, data is not loaded in this step.
 */
fit = (void *)((CONFIG_SYS_TEXT_BASE - size - info->bl_len -
align_len) & ~align_len);
@@ -264,8 +270,17 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
return -1;
}
 
+#ifdef CONFIG_SPL_OS_BOOT
+   /* Find OS image first */
+   node = spl_fit_get_image_node(fit, images, FIT_KERNEL_PROP, 0);
+   if (node < 0)
+   debug("No kernel image.\n");
+   else
+   boot_os = true;
+#endif
/* find the U-Boot image */
-   node = spl_fit_get_image_node(fit, images, "firmware", 0);
+   if (node < 0)
+   node = spl_fit_get_image_node(fit, images, "firmware", 0);
if (node < 0) {
debug("could not find firmware image, trying loadables...\n");
node = spl_fit_get_image_node(fit, images, "loadables", 0);
@@ -287,24 +302,31 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
if (ret)
return ret;
 
+#ifdef CONFIG_SPL_OS_BOOT
+   if (!fit_image_get_os(fit, node, _image->os))
+   debug("Image OS is %s\n", genimg_get_os_name(spl_image->os));
+#else
spl_image->os = IH_OS_U_BOOT;
+#endif
 
-   /* Figure out which device tree the board wants to use */
-   node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP, 0);
-   if (node < 0) {
-   debug("%s: cannot find FDT node\n", __func__);
-   return node;
-   }
+   if (!boot_os) {
+   /* Figure out which device tree the board wants to use */
+   node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP, 0);
+   if (node < 0) {
+   debug("%s: cannot find FDT node\n", __func__);
+   return node;
+   }
 
-   /*
-* Read the device tree and place it after the image.
-* Align the destination address to ARCH_DMA_MINALIGN.
-*/
-   image_info.load_addr = spl_image->load_addr + spl_image->size;
-   ret = spl_load_fit_image(info, sector, fit, base_offset, node,
-_info);
-   if (ret < 0)
-   return ret;
+   /*
+* Read the device tree and place it after the image.
+* Align the destination address to ARCH_DMA_MINALIGN.
+*/
+   image_info.load_addr = spl_image->load_addr + spl_image->size;
+   ret = spl_load_fit_image(info, sector, fit, base_offset, node,
+_info);
+   if (ret < 0)
+   return ret;
+   }
 
/* Now check if there are more images for us to load */
for (; ; index++) {
diff --git a/doc/uImage.FIT/multi_spl.its b/doc/uImage.FIT/multi_spl.its
index e5551d4..d43563d 100644
--- 

[U-Boot] [PATCH v3 1/5] tools: pblimage: Fix address calculation

[York Sun]

The image size should be added to the initial pbl command, not bit
"ORed".

Signed-off-by: York Sun 
---

Changes in v3: None
Changes in v2: None

 tools/pblimage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/pblimage.c b/tools/pblimage.c
index ffc3268..d25a733 100644
--- a/tools/pblimage.c
+++ b/tools/pblimage.c
@@ -293,7 +293,7 @@ int pblimage_check_params(struct image_tool_params *params)
pbi_crc_cmd2 = 0;
pbl_cmd_initaddr = params->addr & PBL_ADDR_24BIT_MASK;
pbl_cmd_initaddr |= PBL_ACS_CONT_CMD;
-   pbl_cmd_initaddr |= uboot_size;
+   pbl_cmd_initaddr += uboot_size;
pbl_end_cmd[0] = 0x0961;
pbl_end_cmd[1] = 0x;
pbl_end_cmd[2] = 0x096100c0;
-- 
2.7.4

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[U-Boot] [PATCH v3 0/5] Extend FIT support for falcon boot

[York Sun]

This patch set extends FIT support for falcon boot. The difference
between U-Boot FIT and Linux FIT lies not only on the images inside,
but also the data offset. U-Boot FIT image has data outside of the
FIT structure while Linux FIT image can have data embedded within.
Linux FIT can use compressed image as well.

Changes in v3:
Replace ifdef with if IS_ENABLED().
Add help to new Kconfig optons.
Update doc/uImage.FIT/source_file_format.txt with embedded and external data
Update doc/uImage.FIT/multi_spl.its to explain the priority of booting image.

Changes in v2:
Combine Kconfig change and actual code into one patch
Rebase on top of "SPL: FIT: factor out spl_load_fit_image()" by Andre Przywara
Split from previous patch, rebased on top of "SPL: FIT: allow loading
multiple images" by Andre Przywara.

York Sun (5):
  tools: pblimage: Fix address calculation
  cmd: spl: Fix compiling warning
  spl: fit: Eanble GZIP support for image decompression
  spl: fit: Support both external and embedded data
  spl: fit: Add booting OS first

 cmd/spl.c |   8 +-
 common/spl/spl_fit.c  | 144 --
 doc/uImage.FIT/multi_spl.its  |   7 ++
 doc/uImage.FIT/source_file_format.txt |   4 +
 lib/Kconfig   |  12 +++
 lib/Makefile  |   5 +-
 tools/pblimage.c  |   2 +-
 7 files changed, 135 insertions(+), 47 deletions(-)

-- 
2.7.4

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[U-Boot] [PATCH] ARM: hisilicon: hikey: Fix eMMC with latest ATF & U-Boot

[Peter Griffin]

ATF can leave the MMC IP in a state where U-Boot mmc driver
can't enumerate the eMMC.

This patch provides a mmc0_reset_clk() function like we
already so do sd card controller which resets the IP
when entering U-Boot.

With this patch applied eMMC partitions are successfully
enumerated again.

=> mmc dev 0
switch to partitions #0, OK
mmc0(part 0) is current device
=> mmc part

Partition Map for MMC device 0  --   Partition Type: EFI

PartStart LBA   End LBA Name
Attributes
Type GUID
Partition GUID
  1 0x0800  0x0fff  "vrl"
attrs:  0x
type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
guid:   496847ab-56a1-4cd5-a1ad-47f4acf055c9
  2 0x1000  0x17ff  "vrl_backup"
attrs:  0x
type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
guid:   61a36fc1-8efb-4899-84d8-b61642efa723
  3 0x1800  0x1fff  "mcuimage"


Signed-off-by: Peter Griffin 
---
 board/hisilicon/hikey/hikey.c | 39 +--
 1 file changed, 37 insertions(+), 2 deletions(-)

diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
index 47bce4d..8405467 100644
--- a/board/hisilicon/hikey/hikey.c
+++ b/board/hisilicon/hikey/hikey.c
@@ -295,13 +295,47 @@ static void mmc1_reset_clk(void)
data = readl(_sc->rst0_stat);
} while (!(data & PERI_RST0_MMC1));
 
-   /* unreset mmc0 clock domain */
+   /* unreset mmc1 clock domain */
writel(PERI_RST0_MMC1, _sc->rst0_dis);
do {
data = readl(_sc->rst0_stat);
} while (data & PERI_RST0_MMC1);
 }
 
+static void mmc0_reset_clk(void)
+{
+   unsigned int data;
+
+   /* disable mmc0 bus clock */
+   hi6220_clk_disable(PERI_CLK0_MMC0, _sc->clk0_dis);
+
+   /* enable mmc0 bus clock */
+   hi6220_clk_enable(PERI_CLK0_MMC0, _sc->clk0_en);
+
+   /* reset mmc0 clock domain */
+   writel(PERI_RST0_MMC0, _sc->rst0_en);
+
+   /* bypass mmc0 clock phase */
+   data = readl(_sc->ctrl2);
+   data |= 3;
+   writel(data, _sc->ctrl2);
+
+   /* disable low power */
+   data = readl(_sc->ctrl13);
+   data |= 1 << 3;
+   writel(data, _sc->ctrl13);
+   do {
+   data = readl(_sc->rst0_stat);
+   } while (!(data & PERI_RST0_MMC0));
+
+   /* unreset mmc0 clock domain */
+   writel(PERI_RST0_MMC0, _sc->rst0_dis);
+   do {
+   data = readl(_sc->rst0_stat);
+   } while (data & PERI_RST0_MMC0);
+}
+
+
 /* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */
 static void hi6220_pmussi_init(void)
 {
@@ -349,7 +383,8 @@ static int init_dwmmc(void)
 
 #ifdef CONFIG_MMC_DW
 
-   /* mmc0 clocks are already configured by ATF */
+   /* mmc0 pll is already configured by ATF */
+   mmc0_reset_clk();
ret = hi6220_pinmux_config(PERIPH_ID_SDMMC0);
if (ret)
printf("%s: Error configuring pinmux for eMMC (%d)\n"
-- 
2.7.4

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Re: [U-Boot] [PATCH] PCI: layerscape: Make the pcie link up status judgement more specific

[York Sun]

On 08/15/2017 03:03 AM, Bao Xiaowei wrote:
> For some special reset times for longer pcie devices, in this case, the
> pcie device may on polling compliance state, the RC considers the pcie
> device is link up, but the pcie device is not link up, only the L0 state
> is link up state. So add the link up status judgement mechanisms.
> 

Xiaowei,

Let me try to rephrase your commit message. Correct me if I get it 
wrong. I think you mean

Determine PCIe link status by checking L0 state. If L0 state is detected 
within 100ms, link status is reported as up.

> Signed-off-by: Bao Xiaowei 
> ---

For future patches, please add change log here and revision number in 
the subject.

>   drivers/pci/pcie_layerscape.c | 25 +
>   drivers/pci/pcie_layerscape.h |  3 +++
>   2 files changed, 24 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
> index 78cde21..4db95c5 100644
> --- a/drivers/pci/pcie_layerscape.c
> +++ b/drivers/pci/pcie_layerscape.c
> @@ -69,13 +69,30 @@ static int ls_pcie_ltssm(struct ls_pcie *pcie)
>   
>   static int ls_pcie_link_up(struct ls_pcie *pcie)
>   {
> - int ltssm;
> + int ltssm, i;
>   
>   ltssm = ls_pcie_ltssm(pcie);
> - if (ltssm < LTSSM_PCIE_L0)
> - return 0;
>   
> - return 1;
> + /*
> +  * For some special reset times for longer pcie devices,
> +  * the pcie device may on polling compliance state,
> +  * on this state, if the device can restored to the L0 state
> +  * within 100ms considers the pcie device is link up
> +  */

> + if (ltssm == LTSSM_PCIE_DETECT_QUIET ||
> + ltssm == LTSSM_PCIE_DETECT_ACTIVE) {

Please explain the above two lines with comment.

> + return 0;
> + } else if (ltssm == LTSSM_PCIE_L0) {
> + return 1;
> + } else {

How about this comment?
/*
 * For some devices requiring longer reset time, check if L0
 * state can be reached within 100ms.
 */

> + for (i = 0; i < 100; i++) {
> + udelay(1000);
> + ltssm = ls_pcie_ltssm(pcie);
> + if (ltssm == LTSSM_PCIE_L0)
> + return 1;
> + }
> + return 0;
> + }
>   }
>   
>   static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
> diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
> index 782e3ab..4313e85 100644
> --- a/drivers/pci/pcie_layerscape.h
> +++ b/drivers/pci/pcie_layerscape.h
> @@ -70,6 +70,9 @@
>   
>   #define LTSSM_STATE_MASK0x3f
>   #define LTSSM_PCIE_L0   0x11 /* L0 state */
> +#define LTSSM_PCIE_DETECT_QUIET  0x00 /* L0 state */
> +#define LTSSM_PCIE_DETECT_ACTIVE 0x01 /* L0 state */
> +#define LTSSM_PCIE_L00x11 /* L0 state */
>   
>   #define PCIE_DBI_SIZE   0x10 /* 1M */
>   
> 

York
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Re: [U-Boot] [PATCH 1/2] arm: use $loadaddr as the standalone entry point

[Wolfgang Denk]

Dear Max,

In message <1502799746.3076.16.ca...@gmail.com> you wrote:
> 
> Wolfgang says that a board needs to decide on what image type to
> use for the standalone application and then from that set an

No, I did not say this.  On contrary, this is not up to the "board"
to decide.  This is a decision tobe made by the end user, and U-Boot
shall not put any restrictions on this.  You may want to use a raw
binary image, someone else uses an ELF file or an uImage, and I
prefer to use a FIT image.

> appropriate CONFIG_STANDALONE_LOAD_ADDR in its board configuration.

The LOAD_ADDR you use it is a misleading name for where the image
gets loaded to in memory. Note that the payload can be compressed or
encrypted or what else.  The "load address" in the intended meaning
(as present in the image headers) is where the payload of the images
gets stored in memory (which may include decryption, uncompressing
or else).  And entry point is still something else.

> Without that the standalone binaries are useless anyway and setting
> a default in arch/arm/config.mk only purpose is that the build succeeds.

For the build process, only the "load address" and "entry point
address" in their original meaning should be interesting - but his
is not what CONFIG_STANDALONE_LOAD_ADDR provides.

> My motivation to write the patch in the first place (and Tom seems to
> agree) is that for boards who define nothing at least the plain binary
> is linked to a memory address where one can load something.

I also agree with this.  I just want to use a misleading name for
this default.  If you need an start address for the text segment
you should call it like that - we already have CONFIG_SYS_TEXT_BASE
and CONFIG_SPL_TEXT_BASE, so why not use CONFIG_STANDALONE_TEXT_BASE
here?

> Note that I sent a v2 of the patchset addressing Wolfgang's first
> emails. v2 hopefully dropped the wrong connection of load/link
> address with entry point.

No, it does not, as it still uses CONFIG_LOADADDR (= default
download address of some image type) where you in fact mean the
default start address of the data payload only (and very likely this
is the same as the start of the text segment).

Best regards,

Wolfgang Denk

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[U-Boot] [PATCH 3/3] arm: dra7xx: Define Android boot arguments

[Sam Protsenko]

Signed-off-by: Sam Protsenko 
---
 configs/dra7xx_evm_defconfig| 2 ++
 configs/dra7xx_hs_evm_defconfig | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 4fff0cf734..0357abc6cd 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -14,6 +14,8 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_ENV_IS_IN_FAT is not set
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS0,115200 
androidboot.console=ttyS0 androidboot.hardware=jacinto6evmboard"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 5572472d01..246de12543 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -20,6 +20,8 @@ CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_ENV_IS_IN_FAT is not set
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS0,115200 
androidboot.console=ttyS0 androidboot.hardware=jacinto6evmboard"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_BOARD_EARLY_INIT_F=y
-- 
2.13.2

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[U-Boot] [PATCH 2/3] arm: am57xx: Define Android boot arguments

[Sam Protsenko]

Signed-off-by: Sam Protsenko 
---
 configs/am57xx_evm_defconfig  | 2 ++
 configs/am57xx_evm_nodt_defconfig | 2 ++
 configs/am57xx_hs_evm_defconfig   | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 11be1ad27f..ad93602c13 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -14,6 +14,8 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_ENV_IS_IN_FAT is not set
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 
androidboot.console=ttyS2 androidboot.hardware=am57xevmboard"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/am57xx_evm_nodt_defconfig 
b/configs/am57xx_evm_nodt_defconfig
index a6ad0d36e0..e6f71e9133 100644
--- a/configs/am57xx_evm_nodt_defconfig
+++ b/configs/am57xx_evm_nodt_defconfig
@@ -6,6 +6,8 @@ CONFIG_TARGET_AM57XX_EVM=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 
androidboot.console=ttyS2 androidboot.hardware=am57xevmboard"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 91baa2b53e..5cd34561a7 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -20,6 +20,8 @@ CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
 CONFIG_OF_BOARD_SETUP=y
 # CONFIG_ENV_IS_IN_FAT is not set
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 
androidboot.console=ttyS2 androidboot.hardware=am57xevmboard"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_BOARD_EARLY_INIT_F=y
-- 
2.13.2

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[U-Boot] [PATCH 1/3] arm: omap: Define command for booting Android from eMMC

[Sam Protsenko]

If SD card is present -- try to boot from it first. If no -- try to boot
Android from eMMC.

Signed-off-by: Sam Protsenko 
---
 include/environment/ti/boot.h | 24 +++-
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h
index 1c3ae40a99..121a668e78 100644
--- a/include/environment/ti/boot.h
+++ b/include/environment/ti/boot.h
@@ -28,7 +28,24 @@
"vram=16M\0" \
"partitions=" PARTS_DEFAULT "\0" \
"optargs=\0" \
-   "dofastboot=0\0"
+   "dofastboot=0\0" \
+   "emmc_android_boot=" \
+   "setenv eval_bootargs setenv bootargs $bootargs; " \
+   "run eval_bootargs; " \
+   "setenv mmcdev 1; " \
+   "setenv fdt_part 3; " \
+   "setenv boot_part 9; " \
+   "setenv machid fe6; " \
+   "mmc dev $mmcdev; " \
+   "mmc rescan; " \
+   "part start mmc ${mmcdev} ${fdt_part} fdt_start; " \
+   "part size mmc ${mmcdev} ${fdt_part} fdt_size; " \
+   "part start mmc ${mmcdev} ${boot_part} boot_start; " \
+   "part size mmc ${mmcdev} ${boot_part} boot_size; " \
+   "mmc read ${fdtaddr} ${fdt_start} ${fdt_size}; " \
+   "mmc read ${loadaddr} ${boot_start} ${boot_size}; " \
+   "echo Booting from eMMC ...; " \
+   "bootm $loadaddr $loadaddr $fdtaddr;\0"
 
 #ifdef CONFIG_OMAP54XX
 
@@ -72,10 +89,7 @@
"run findfdt; " \
"run envboot; " \
"run mmcboot;" \
-   "setenv mmcdev 1; " \
-   "setenv bootpart 1:2; " \
-   "setenv mmcroot /dev/mmcblk0p2 rw; " \
-   "run mmcboot;" \
+   "run emmc_android_boot; " \
""
 
 #endif /* CONFIG_OMAP54XX */
-- 
2.13.2

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[U-Boot] [PATCH 0/3] arm: am57xx/dra7xx: Boot Android from eMMC

[Sam Protsenko]

Provide a way to boot Android from eMMC for AM57xx EVM and DRA7 EVM boards.

Sam Protsenko (3):
  arm: omap: Define command for booting Android from eMMC
  arm: am57xx: Define Android boot arguments
  arm: dra7xx: Define Android boot arguments

 configs/am57xx_evm_defconfig  |  2 ++
 configs/am57xx_evm_nodt_defconfig |  2 ++
 configs/am57xx_hs_evm_defconfig   |  2 ++
 configs/dra7xx_evm_defconfig  |  2 ++
 configs/dra7xx_hs_evm_defconfig   |  2 ++
 include/environment/ti/boot.h | 24 +++-
 6 files changed, 29 insertions(+), 5 deletions(-)

-- 
2.13.2

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Re: [U-Boot] [PATCH 1/2] arm: use $loadaddr as the standalone entry point

[Wolfgang Denk]

Dear Tom,

In message <20170815113952.GE20467@bill-the-cat> you wrote:
> 
> What CONFIG_STANDALONE_LOAD_ADDR is, is the location that we want
> hello_world, or other example stand alone applications loaded into
> memory at.  CONFIG_LOADADDR is the safe default location to load things
> into memory at in order to run them.  At least on ARM, where there's a
> good number of different default memory layouts, what arch/arm/config.mk
> does today is broken for the majority of platforms.

I agree up to here.

> We should be
> providing at least a functional default value here, which we are not
> today.  This in no way precludes a 'real' standalone application from
> linking and running at whatever it wants within a platforms memory map.

This is where things become fishy.

We should use clean terms.

Please keep in mind that even the term "load address" can mean two
things: many people use this term (incorrectly) for the address where
they load an image to on RAM, and unfortunately we even provide the
"loadaddr" environment variable which carries this meaning.
Originally, the term refers to the address where the image payload gets
uncompressed and loaded to when unpacking the image.  For example,
on Power architecture, a typical setup would look like:

Output of mkimage -l:

Image Name:   Linux-4.4.8
Created:  Fri Apr 22 09:06:09 2016
Image Type:   PowerPC Linux Kernel Image (gzip compressed)
Data Size:2009139 Bytes = 1962.05 kB = 1.92 MB
Load Address: 
Entry Point:  

We download the uImage file to - say - 0x40 in RAM (so the
environment variable "loadaddr" might be 0x40),  but when we run
"bootm", U-Boot will uncompress and _load_ the Linux kernel to the
_Load_Address_ stored in the image header, i. e. 0x, and then
it will transfer control to the _Entry_Point_Address_, also stored
in the image header, here also 0x.

So we have:

download address (address of image in RAM): 0x0040
load address (start of unpacked kernel image):  0x
entry point (start of executable code): 0x


The term "load address" has always been meant to mean the address
where the kernel gets _loaded_to_ by the bootm command.  I know that
there has always been confusion of these terms, and I must have
explained this at least a hundred times here before.


I would really appreciate if you helped to avoid mixing terms of
different meaning.  If you have an idea how to avoid this it would
be more than welcome - unfortunately the (mis)use of the loadaddr
environment variable is so widespread that I feat there is no easy
way out.



Best regards,

Wolfgang Denk

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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Re: [U-Boot] [PATCH 2/2] hello_world.c: fix entry point in case of arm thumb binary

[Max Krummenacher]

Hello all

Am Montag, den 14.08.2017, 17:15 -0400 schrieb Tom Rini:

On Sat, Aug 12, 2017 at 11:03:46AM +0200, Max Krummenacher wrote:



If compiling for thumb the U-Boot 'go' command can not jump to the entry
point, as the jump will be done in the assumption that the code jumped to
is using the arm instruction set.

So add add a simple forwarder in arm instruction set which then jumps
to the 'real' entry.

Signed-off-by: Max Krummenacher 


This looks like a special case of what we're doing in f3c10882 and
dc89c6fb778e and perhaps we need to move that kind of fixup around to
somewhere else, as I assume you've found this problem on a custom
application?  Or are you utilizing hello_world in some test suites?
Just curious, thanks!


I guess the difference to f3c10882 and dc89c6fb778e is that one
knows from armv7m that the CPU is thumb only while on an armv7a
potentially both arm and thumb mode can be used.

Actually a customer asked how to run hello_world.bin, so I
tested with our regular defconfig and the produced hello_world.bin.

I'm having 'CONFIG_SYS_THUMB_BUILD=y' in e.g.
configs/colibri_imx6_nospl_defconfig thus all of the U-Boot code
including hello_world.c is compiled for thumb.

If I boot that U-Boot, load hello_world.bin into RAM at
CONFIG_STANDALONE_LOAD_ADDR and execute 'go CONFIG_STANDALONE_LOAD_ADDR'
I get output from the go command and then the CPU resets.

    Colibri iMX6 # tftp 0x1200 hello_world.bin
      ...
    Colibri iMX6 # go 0x1200                                                
     
    ## Starting application at 0x1200 ...   


With the patch I get the expected output.

But actually calling the 'go' command with bit 0 set works. So if
the user knows that he is having a thumb binary that would fix
the issue as well. With the current implementation the following works:

    Colibri iMX6 # go 0x1201

    ## Starting application at 0x1201 ...   

    Example expects ABI version 9   

    Actual U-Boot ABI version 9 

    Hello World 

    argc = 1

    argv[0] = "0x1201"  

    argv[1] = ""  

    Hit any key to exit ...                                                     
    

Max
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Re: [U-Boot] [PATCH 1/2] arm: use $loadaddr as the standalone entry point

[Max Krummenacher]

Hello all

Am Dienstag, den 15.08.2017, 07:39 -0400 schrieb Tom Rini:
> On Tue, Aug 15, 2017 at 09:32:30AM +0200, Wolfgang Denk wrote:
> > 
> > Dear Tom,
> > 
> > In message <20170814211300.GM20467@bill-the-cat> you wrote:
> > > 
> > > 
> > > But we're talking about CONFIG_STANDALONE_LOAD_ADDR not
> > > CONFIG_STANDALONE_ENTRY_POINT.  What we've been doing in
> > > arch/arm/config.mk has been on my to fix list for a long time, because
> > > it's been wrong for so many boards.  Setting this to CONFIG_LOADADDR is
> > > a reasonable default value.
> > 
> > No, it is not.  It is fundamentally broken. If you need a default
> > for the entry point address, then define one.  CONFIG_LOADADDR means
> > where the image gets loaded to, and almost all image formats have a
> > header in front of the payuload, so the entry point is somewhere
> > else.  And even if you load raw binary images, there is no guarantee
> > that the entry point is right at the start of the image,
> > 
> > Mixing things that are defined for different purposes (loading image
> > versus start address of the code) is a really bad idea.
> 
> What CONFIG_STANDALONE_LOAD_ADDR is, is the location that we want
> hello_world, or other example stand alone applications loaded into
> memory at.  CONFIG_LOADADDR is the safe default location to load things
> into memory at in order to run them.  At least on ARM, where there's a
> good number of different default memory layouts, what arch/arm/config.mk
> does today is broken for the majority of platforms.  We should be
> providing at least a functional default value here, which we are not
> today.  This in no way precludes a 'real' standalone application from
> linking and running at whatever it wants within a platforms memory map.

Wolfgang says that a board needs to decide on what image type to
use for the standalone application and then from that set an
appropriate CONFIG_STANDALONE_LOAD_ADDR in its board configuration.
Without that the standalone binaries are useless anyway and setting
a default in arch/arm/config.mk only purpose is that the build succeeds.

My motivation to write the patch in the first place (and Tom seems to
agree) is that for boards who define nothing at least the plain binary
is linked to a memory address where one can load something.

I can live with both views.

Note that I sent a v2 of the patchset addressing Wolfgang's first
emails. v2 hopefully dropped the wrong connection of load/link
address with entry point.

Max

> 
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Re: [U-Boot] [PATCH 1/2] arm: use $loadaddr as the standalone entry point

[Tom Rini]

On Tue, Aug 15, 2017 at 09:32:30AM +0200, Wolfgang Denk wrote:
> Dear Tom,
> 
> In message <20170814211300.GM20467@bill-the-cat> you wrote:
> > 
> > But we're talking about CONFIG_STANDALONE_LOAD_ADDR not
> > CONFIG_STANDALONE_ENTRY_POINT.  What we've been doing in
> > arch/arm/config.mk has been on my to fix list for a long time, because
> > it's been wrong for so many boards.  Setting this to CONFIG_LOADADDR is
> > a reasonable default value.
> 
> No, it is not.  It is fundamentally broken. If you need a default
> for the entry point address, then define one.  CONFIG_LOADADDR means
> where the image gets loaded to, and almost all image formats have a
> header in front of the payuload, so the entry point is somewhere
> else.  And even if you load raw binary images, there is no guarantee
> that the entry point is right at the start of the image,
> 
> Mixing things that are defined for different purposes (loading image
> versus start address of the code) is a really bad idea.

What CONFIG_STANDALONE_LOAD_ADDR is, is the location that we want
hello_world, or other example stand alone applications loaded into
memory at.  CONFIG_LOADADDR is the safe default location to load things
into memory at in order to run them.  At least on ARM, where there's a
good number of different default memory layouts, what arch/arm/config.mk
does today is broken for the majority of platforms.  We should be
providing at least a functional default value here, which we are not
today.  This in no way precludes a 'real' standalone application from
linking and running at whatever it wants within a platforms memory map.

-- 
Tom


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Re: [U-Boot] [PATCH] armv8: layerscape platform pcie link up state judgment strongly

[Xiaowei Bao]

Hi York,

I have add the inline comment in the new patch and have sent to you, please 
review it.

Thanks

-Original Message-
From: Xiaowei Bao 
Sent: Friday, August 11, 2017 9:39 AM
To: York Sun ; u-boot@lists.denx.de; Priyanka Jain 
; Z.q. Hou ; M.h. Lian 
; s...@chromium.org
Subject: RE: [PATCH] armv8: layerscape platform pcie link up state judgment 
strongly

Hi York,

I will add the inline comment in the patch, send it to you later.

thanks

-Original Message-
From: York Sun 
Sent: Wednesday, August 09, 2017 12:14 AM
To: Xiaowei Bao ; u-boot@lists.denx.de; Priyanka Jain 
; Z.q. Hou ; M.h. Lian 
; s...@chromium.org
Subject: Re: [PATCH] armv8: layerscape platform pcie link up state judgment 
strongly

On 08/07/2017 11:56 PM, Xiaowei Bao wrote:
> Hi York,
> 
> I will pay attention to the case of the case in commit message.
> 
> This patch is for some special reset times for longer pcie devices, in this 
> case, the pcie device may on polling compliance state, the RC considers the 
> pcie device is link up, but the pcie device is not link up, only the L0 state 
> is link up state. So add the link up status judgement mechanisms.
> 
> About 100ms timeout, the pcie spec does not specify the link up timeout time, 
> and the link up state is determined by a state machine. The state machine 
> implementation is relatively complex, refer to uboot of other platform pcie 
> link up state to determine the realization of the mechanism, we evaluated a 
> timeout, in detect state consider the pcie device is link down, in L0 state 
> consider the pcie device is link up, within  100ms in other states can be 
> restored to the L0 state considers the pcie device is link up .

Can you put this information to inline comment? It will help us when we read 
the code later.

Thanks.

York
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[U-Boot] [PATCH] PCI: layerscape: Make the pcie link up status judgement more specific

[Bao Xiaowei]

For some special reset times for longer pcie devices, in this case, the
pcie device may on polling compliance state, the RC considers the pcie
device is link up, but the pcie device is not link up, only the L0 state
is link up state. So add the link up status judgement mechanisms.

Signed-off-by: Bao Xiaowei 
---
 drivers/pci/pcie_layerscape.c | 25 +
 drivers/pci/pcie_layerscape.h |  3 +++
 2 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 78cde21..4db95c5 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -69,13 +69,30 @@ static int ls_pcie_ltssm(struct ls_pcie *pcie)
 
 static int ls_pcie_link_up(struct ls_pcie *pcie)
 {
-   int ltssm;
+   int ltssm, i;
 
ltssm = ls_pcie_ltssm(pcie);
-   if (ltssm < LTSSM_PCIE_L0)
-   return 0;
 
-   return 1;
+   /*
+* For some special reset times for longer pcie devices,
+* the pcie device may on polling compliance state,
+* on this state, if the device can restored to the L0 state
+* within 100ms considers the pcie device is link up
+*/
+   if (ltssm == LTSSM_PCIE_DETECT_QUIET ||
+   ltssm == LTSSM_PCIE_DETECT_ACTIVE) {
+   return 0;
+   } else if (ltssm == LTSSM_PCIE_L0) {
+   return 1;
+   } else {
+   for (i = 0; i < 100; i++) {
+   udelay(1000);
+   ltssm = ls_pcie_ltssm(pcie);
+   if (ltssm == LTSSM_PCIE_L0)
+   return 1;
+   }
+   return 0;
+   }
 }
 
 static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 782e3ab..4313e85 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -70,6 +70,9 @@
 
 #define LTSSM_STATE_MASK   0x3f
 #define LTSSM_PCIE_L0  0x11 /* L0 state */
+#define LTSSM_PCIE_DETECT_QUIET0x00 /* L0 state */
+#define LTSSM_PCIE_DETECT_ACTIVE   0x01 /* L0 state */
+#define LTSSM_PCIE_L0  0x11 /* L0 state */
 
 #define PCIE_DBI_SIZE  0x10 /* 1M */
 
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH v2 4/5] arm: socfpga: Add intermediate driver between flash and FPGA manager

[Marek Vasut]

On 08/14/2017 05:58 AM, Chee, Tien Fong wrote:
> On Sab, 2017-08-12 at 18:49 +0200, Marek Vasut wrote:
>> On 08/12/2017 10:03 AM, Chee, Tien Fong wrote:
>> [...]
>>>

>
> 1: It having ability to the right memory(OCRAM or SDRAM) to
> achieve
> the
> best FPGA programing performance.
 Did you find significant throughput difference ?

>>> 80% performance improvement with SDRAM.
>> This looks more like caches are not enabled ... sort of problem ?
>>
> It is because SDRAM size large enough to store whole rbf file and
> reduce significantly of the repetitive block transfer. It requires one
> time block transfer from SDRAM to FPGA compare to OCRAM which require
> more than that.

OK, do that as a subsequent optimization.

>>>

>
> 2: It can determine the right size buffer for the fpga rbf
> without
> info
> of buffer size defined by user.
 You mean like $filesize variable in the command prompt ?

>>> Yeah. No filesize is required.
>> You can use $filesize instead of reimplementing this functionality
>> yourself though ?
>>
> I'am sorry to have confused you. What i trying to say is user no longer
> require to specify the file size and location when calling fpga loadfs.
> So, this would keep the thing simple. The driver in cff.c would handle
> all these troublesome things and deciding the best route for good
> performance.

OK, separate patch

>>>

>
> 3: It has ability to know what kind of fpga rbf type, and
> security
> type, such as peripheral, core, combined rbf, encryption and
> unencryption based on any fpga file user pass in .
 Is this information used for anything ? I was under the
 impression
 that
 the user just needs to load in the correct RBF file into the
 FPGA.

>>> Yeah, the driver would decode the RBF image to know what type of
>>> RBF
>>> user loading, and applying correct method(buffer allocation, which
>>> memory to use and configuration on FPGA manager) to program FPGA.
>> If the code needs to extract some information from the RBF to
>> correctly
>> configure something in the FPGA manager, then that's where this
>> should
>> go then.
>>
> Those functions for extracting info from RBF and configuring the FPGA
> are actually come from fpga driver which i have submited as in previous
> patchset. The actualy implementation is in cff.c, as i try to explain
> cff.c drivers are mainly to handle all activities of loading rbf from
> flashes to program FPGA.

Such functionality should be generic and split between fpga loadfs and
the driver.

>>>

>
> 4: It supports the checksum.
 What checksum ? Can we have a generic hook into the FPGA
 framework ?

>>> This checksum is to ensure integrity of RBF file after loading from
>>> flash into SDRAM. This can help to prevent possibility system
>>> instability caused by programming corrupt rbf into FPGA. So, this
>>> should be implemented in cff.c .
>> Or the FPGA manager driver .
>>
> This integrity checking is implemented during RBF loading from flash to
> SDRAM before calling the functions from fpga driver to program FPGA. So
> cff.c which is designed for handling these operation and it should
> be appropriate place for checksum.

Add a checksum hook into the FPGA framework ?

>>>

>
> 5: support raw flash without fs.
 This should go into common code.

>>> raw flash is part of common codes in cff.c because it is part of
>>> mechanism like fs to determine how loading rbf from flash and
>>> program
>>> into fpga.
>> By common code I mean the stuff around FPGA LOADFS , so other FPGAs
>> can
>> also benefit from that.
>>
> But the raw flash to FPGA implementation is designed fully tied to
> common codes in cff.c. FPGA loadfs would be acted like a wrapper to it,
> so i am not sure it can be shared by other FPGA.

I do not want any ad-hoc wrapper, implement it properly be extending
fpga loadfs or the fpga framework.

>>>

>
> 6: support the file name defined in DTS and U-boot environment
> variable.
 I think you should extend the FPGA LOADFS here instead.

>>> The peripheral rbf filename and DTS are generated from our bsp
>>> tool.
>>> But user can run fpga loadfs to reconfigure FPGA in U-boot console
>>> after i have supported it.
>> And why don't you rather apply some FPGA LOADFS if this property is
>> detected in the DT instead of reimplementing it ?
>>
> We need to program the FPGA IO ring buffer from very early phase in SPL
> before SDRAM can be initialized. So we need the peripheral rbf file
> name from DTS, which is defined by user in our BSP tool. I don't think
> FPGA loadfs would be available in SPL by that time. So, i think FPGA
> loadfs is suitable for reprogramming FPGA in U-boot console, and
> filename is passed as parameter to fpga loadfs command.

Then just call the required bits from fpga loadfs during SPL . Extract
them into some fpga-loadfs-common and make both fpga loadfs 

[U-Boot] [PATCH v2 2/2] board: atmel: Use the new PIT timer driver

[Wenyou Yang]

Use the Atmel PIT timer driver which supports the driver model
and device tree.

Signed-off-by: Wenyou Yang 
---

Changes in v2:
 - Integrate the PATCH {timer: Add Atmel PIT timer driver} to
   one patch set.
 - Rebase on latest commit of uboot/master (2d3c4ae35).
 - Retain the CONFIG_SYS_TIMER_COUNTER macro in .
 - Convert all atmel boards to support the new timer driver.

 arch/arm/dts/sama5d2.dtsi  | 28 ++
 configs/at91sam9260ek_dataflash_cs0_defconfig  |  2 ++
 configs/at91sam9260ek_dataflash_cs1_defconfig  |  2 ++
 configs/at91sam9260ek_nandflash_defconfig  |  2 ++
 configs/at91sam9261ek_dataflash_cs0_defconfig  |  2 ++
 configs/at91sam9261ek_dataflash_cs3_defconfig  |  2 ++
 configs/at91sam9261ek_nandflash_defconfig  |  2 ++
 configs/at91sam9263ek_dataflash_cs0_defconfig  |  2 ++
 configs/at91sam9263ek_dataflash_defconfig  |  2 ++
 configs/at91sam9263ek_nandflash_defconfig  |  2 ++
 configs/at91sam9263ek_norflash_boot_defconfig  |  2 ++
 configs/at91sam9263ek_norflash_defconfig   |  2 ++
 configs/at91sam9g20ek_2mmc_defconfig   |  2 ++
 configs/at91sam9g20ek_2mmc_nandflash_defconfig |  2 ++
 configs/at91sam9g20ek_dataflash_cs0_defconfig  |  2 ++
 configs/at91sam9g20ek_dataflash_cs1_defconfig  |  2 ++
 configs/at91sam9g20ek_nandflash_defconfig  |  2 ++
 configs/at91sam9m10g45ek_mmc_defconfig |  2 ++
 configs/at91sam9m10g45ek_nandflash_defconfig   |  2 ++
 configs/at91sam9n12ek_mmc_defconfig|  2 ++
 configs/at91sam9n12ek_nandflash_defconfig  |  2 ++
 configs/at91sam9n12ek_spiflash_defconfig   |  2 ++
 configs/at91sam9rlek_dataflash_defconfig   |  2 ++
 configs/at91sam9rlek_mmc_defconfig |  2 ++
 configs/at91sam9rlek_nandflash_defconfig   |  2 ++
 configs/at91sam9x5ek_dataflash_defconfig   |  2 ++
 configs/at91sam9x5ek_mmc_defconfig |  2 ++
 configs/at91sam9x5ek_nandflash_defconfig   |  2 ++
 configs/at91sam9x5ek_spiflash_defconfig|  2 ++
 configs/at91sam9xeek_dataflash_cs0_defconfig   |  2 ++
 configs/at91sam9xeek_dataflash_cs1_defconfig   |  2 ++
 configs/at91sam9xeek_nandflash_defconfig   |  2 ++
 configs/gurnard_defconfig  |  2 ++
 configs/sama5d2_xplained_mmc_defconfig |  3 +++
 configs/sama5d2_xplained_spiflash_defconfig|  3 +++
 configs/sama5d36ek_cmp_mmc_defconfig   |  2 ++
 configs/sama5d36ek_cmp_nandflash_defconfig |  2 ++
 configs/sama5d36ek_cmp_spiflash_defconfig  |  2 ++
 configs/sama5d3_xplained_mmc_defconfig |  3 +++
 configs/sama5d3_xplained_nandflash_defconfig   |  3 +++
 configs/sama5d3xek_mmc_defconfig   |  3 +++
 configs/sama5d3xek_nandflash_defconfig |  3 +++
 configs/sama5d3xek_spiflash_defconfig  |  3 +++
 configs/sama5d4_xplained_mmc_defconfig |  3 +++
 configs/sama5d4_xplained_nandflash_defconfig   |  3 +++
 configs/sama5d4_xplained_spiflash_defconfig|  3 +++
 configs/sama5d4ek_mmc_defconfig|  3 +++
 configs/sama5d4ek_nandflash_defconfig  |  3 +++
 configs/sama5d4ek_spiflash_defconfig   |  3 +++
 49 files changed, 137 insertions(+)

diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi
index 8d89b83b53..d8a65145d6 100644
--- a/arch/arm/dts/sama5d2.dtsi
+++ b/arch/arm/dts/sama5d2.dtsi
@@ -632,6 +632,34 @@
status = "disabled";
};
 
+   rstc@f8048000 {
+   compatible = "atmel,sama5d3-rstc";
+   reg = <0xf8048000 0x10>;
+   clocks = <>;
+   };
+
+   shdwc@f8048010 {
+   compatible = "atmel,sama5d2-shdwc";
+   reg = <0xf8048010 0x10>;
+   clocks = <>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   atmel,wakeup-rtc-timer;
+   };
+
+   pit: timer@f8048030 {
+   compatible = "atmel,at91sam9260-pit";
+   reg = <0xf8048030 0x10>;
+   clocks = <>;
+   };
+
+   watchdog@f8048040 {
+   compatible = "atmel,sama5d4-wdt";
+   reg = <0xf8048040 0x10>;
+   clocks = <>;
+   status = "disabled";
+   };
+
sckc@f8048050 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xf8048050 0x4>;
diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig 
b/configs/at91sam9260ek_dataflash_cs0_defconfig
index 8661d9f098..c231f5f8ab 100644
--- 

[U-Boot] [PATCH v2 1/2] driver: timer: Add the Atmel PIT timer driver

[Wenyou Yang]

Add the new Atmel PIT timer driver, which supports the driver model
and device tree.

Signed-off-by: Wenyou Yang 
---

Changes in v2: None

 arch/arm/mach-at91/arm926ejs/Makefile |  2 +
 arch/arm/mach-at91/armv7/Makefile |  2 +
 drivers/timer/Kconfig |  8 
 drivers/timer/Makefile|  1 +
 drivers/timer/atmel_pit_timer.c   | 90 +++
 5 files changed, 103 insertions(+)
 create mode 100644 drivers/timer/atmel_pit_timer.c

diff --git a/arch/arm/mach-at91/arm926ejs/Makefile 
b/arch/arm/mach-at91/arm926ejs/Makefile
index 624ccd7c2f..dc935fd9e5 100644
--- a/arch/arm/mach-at91/arm926ejs/Makefile
+++ b/arch/arm/mach-at91/arm926ejs/Makefile
@@ -22,7 +22,9 @@ obj-y += cache.o
 obj-y += clock.o
 obj-y += cpu.o
 obj-y  += reset.o
+ifeq ($(CONFIG_ATMEL_PIT_TIMER),)
 obj-y  += timer.o
+endif
 
 ifndef CONFIG_SKIP_LOWLEVEL_INIT
 obj-y  += lowlevel_init.o
diff --git a/arch/arm/mach-at91/armv7/Makefile 
b/arch/arm/mach-at91/armv7/Makefile
index 9538bc1fad..1ede4cb10a 100644
--- a/arch/arm/mach-at91/armv7/Makefile
+++ b/arch/arm/mach-at91/armv7/Makefile
@@ -14,4 +14,6 @@ obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o
 obj-y += clock.o
 obj-y += cpu.o
 obj-y += reset.o
+ifeq ($(CONFIG_ATMEL_PIT_TIMER),)
 obj-y += timer.o
+endif
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 13f122350b..6305bbf01c 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -44,6 +44,14 @@ config ALTERA_TIMER
  Select this to enable a timer for Altera devices. Please find
  details on the "Embedded Peripherals IP User Guide" of Altera.
 
+config ATMEL_PIT_TIMER
+   bool "Atmel periodic interval timer support"
+   depends on TIMER
+   help
+ Select this to enable a periodic interval timer for Atmel devices,
+ it is designed to offer maximum accuracy and efficient management,
+ even for systems with long response time.
+
 config SANDBOX_TIMER
bool "Sandbox timer support"
depends on SANDBOX && TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index fa7ce7c835..69e8961a7b 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_ARC_TIMER)   += arc_timer.o
 obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
 obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o
 obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
+obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o
diff --git a/drivers/timer/atmel_pit_timer.c b/drivers/timer/atmel_pit_timer.c
new file mode 100644
index 00..999717b91f
--- /dev/null
+++ b/drivers/timer/atmel_pit_timer.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2017 Microchip Corporation
+ *   Wenyou.Yang 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define AT91_PIT_VALUE 0xf
+#define AT91_PIT_PITEN BIT(24) /* Timer Enabled */
+
+struct atmel_pit_regs {
+   u32 mode;
+   u32 status;
+   u32 value;
+   u32 value_image;
+};
+
+struct atmel_pit_platdata {
+   struct atmel_pit_regs *regs;
+};
+
+static int atmel_pit_get_count(struct udevice *dev, u64 *count)
+{
+   struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+   struct atmel_pit_regs *const regs = plat->regs;
+   u32 val = readl(>value_image);
+
+   *count = timer_conv_64(val);
+
+   return 0;
+}
+
+static int atmel_pit_probe(struct udevice *dev)
+{
+   struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+   struct atmel_pit_regs *const regs = plat->regs;
+   struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+   struct clk clk;
+   ulong clk_rate;
+   int ret;
+
+   ret = clk_get_by_index(dev, 0, );
+   if (ret)
+   return -EINVAL;
+
+   clk_rate = clk_get_rate();
+   if (!clk_rate)
+   return -EINVAL;
+
+   uc_priv->clock_rate = clk_rate / 16;
+
+   writel(AT91_PIT_VALUE | AT91_PIT_PITEN, >mode);
+
+   return 0;
+}
+
+static int atmel_pit_ofdata_to_platdata(struct udevice *dev)
+{
+   struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+
+   plat->regs = (struct atmel_pit_regs *)devfdt_get_addr_ptr(dev);
+
+   return 0;
+}
+
+static const struct timer_ops atmel_pit_ops = {
+   .get_count = atmel_pit_get_count,
+};
+
+static const struct udevice_id atmel_pit_ids[] = {
+   { .compatible = "atmel,at91sam9260-pit" },
+   { }
+};
+
+U_BOOT_DRIVER(atmel_pit) = {
+   .name   = "atmel_pit",
+   .id = UCLASS_TIMER,
+   .of_match = atmel_pit_ids,
+   .ofdata_to_platdata = atmel_pit_ofdata_to_platdata,
+   .platdata_auto_alloc_size = sizeof(struct atmel_pit_platdata),
+   .probe  = atmel_pit_probe,
+   .ops= _pit_ops,
+   .flags  = DM_FLAG_PRE_RELOC,
+};
-- 
2.13.0

[U-Boot] [PATCH v2 0/2] driver: timer: Add Atmel PIT timer driver

[Wenyou Yang]

Add the Atmel PIT timer driver which supports the driver model
and device tree, and covert the boards to support the new Atmel
PIT timer driver.

Changes in v2:
 - Integrate the PATCH {timer: Add Atmel PIT timer driver} to
   one patch set.
 - Rebase on latest commit of uboot/master (2d3c4ae35).
 - Retain the CONFIG_SYS_TIMER_COUNTER macro in .
 - Convert all atmel boards to support the new timer driver.

Wenyou Yang (2):
  driver: timer: Add the Atmel PIT timer driver
  board: atmel: Use the new PIT timer driver

 arch/arm/dts/sama5d2.dtsi  | 28 
 arch/arm/mach-at91/arm926ejs/Makefile  |  2 +
 arch/arm/mach-at91/armv7/Makefile  |  2 +
 configs/at91sam9260ek_dataflash_cs0_defconfig  |  2 +
 configs/at91sam9260ek_dataflash_cs1_defconfig  |  2 +
 configs/at91sam9260ek_nandflash_defconfig  |  2 +
 configs/at91sam9261ek_dataflash_cs0_defconfig  |  2 +
 configs/at91sam9261ek_dataflash_cs3_defconfig  |  2 +
 configs/at91sam9261ek_nandflash_defconfig  |  2 +
 configs/at91sam9263ek_dataflash_cs0_defconfig  |  2 +
 configs/at91sam9263ek_dataflash_defconfig  |  2 +
 configs/at91sam9263ek_nandflash_defconfig  |  2 +
 configs/at91sam9263ek_norflash_boot_defconfig  |  2 +
 configs/at91sam9263ek_norflash_defconfig   |  2 +
 configs/at91sam9g20ek_2mmc_defconfig   |  2 +
 configs/at91sam9g20ek_2mmc_nandflash_defconfig |  2 +
 configs/at91sam9g20ek_dataflash_cs0_defconfig  |  2 +
 configs/at91sam9g20ek_dataflash_cs1_defconfig  |  2 +
 configs/at91sam9g20ek_nandflash_defconfig  |  2 +
 configs/at91sam9m10g45ek_mmc_defconfig |  2 +
 configs/at91sam9m10g45ek_nandflash_defconfig   |  2 +
 configs/at91sam9n12ek_mmc_defconfig|  2 +
 configs/at91sam9n12ek_nandflash_defconfig  |  2 +
 configs/at91sam9n12ek_spiflash_defconfig   |  2 +
 configs/at91sam9rlek_dataflash_defconfig   |  2 +
 configs/at91sam9rlek_mmc_defconfig |  2 +
 configs/at91sam9rlek_nandflash_defconfig   |  2 +
 configs/at91sam9x5ek_dataflash_defconfig   |  2 +
 configs/at91sam9x5ek_mmc_defconfig |  2 +
 configs/at91sam9x5ek_nandflash_defconfig   |  2 +
 configs/at91sam9x5ek_spiflash_defconfig|  2 +
 configs/at91sam9xeek_dataflash_cs0_defconfig   |  2 +
 configs/at91sam9xeek_dataflash_cs1_defconfig   |  2 +
 configs/at91sam9xeek_nandflash_defconfig   |  2 +
 configs/gurnard_defconfig  |  2 +
 configs/sama5d2_xplained_mmc_defconfig |  3 +
 configs/sama5d2_xplained_spiflash_defconfig|  3 +
 configs/sama5d36ek_cmp_mmc_defconfig   |  2 +
 configs/sama5d36ek_cmp_nandflash_defconfig |  2 +
 configs/sama5d36ek_cmp_spiflash_defconfig  |  2 +
 configs/sama5d3_xplained_mmc_defconfig |  3 +
 configs/sama5d3_xplained_nandflash_defconfig   |  3 +
 configs/sama5d3xek_mmc_defconfig   |  3 +
 configs/sama5d3xek_nandflash_defconfig |  3 +
 configs/sama5d3xek_spiflash_defconfig  |  3 +
 configs/sama5d4_xplained_mmc_defconfig |  3 +
 configs/sama5d4_xplained_nandflash_defconfig   |  3 +
 configs/sama5d4_xplained_spiflash_defconfig|  3 +
 configs/sama5d4ek_mmc_defconfig|  3 +
 configs/sama5d4ek_nandflash_defconfig  |  3 +
 configs/sama5d4ek_spiflash_defconfig   |  3 +
 drivers/timer/Kconfig  |  8 +++
 drivers/timer/Makefile |  1 +
 drivers/timer/atmel_pit_timer.c| 90 ++
 54 files changed, 240 insertions(+)
 create mode 100644 drivers/timer/atmel_pit_timer.c

-- 
2.13.0

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[U-Boot] [PATCH 4/4] x86: dfi-bt700: Select SERIAL_IRQ_BUFFER via Kconfig

[Stefan Roese]

To support more input characters (longer stings pasted into the U-Boot
prompt) without dropping, lets selects the recently added UART RX
interrupt buffer for these boards.

Signed-off-by: Stefan Roese 
Cc: Simon Glass 
Cc: Bin Meng 
---
 board/dfi/dfi-bt700/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/dfi/dfi-bt700/Kconfig b/board/dfi/dfi-bt700/Kconfig
index 4b6c3fc56c..c253e1911d 100644
--- a/board/dfi/dfi-bt700/Kconfig
+++ b/board/dfi/dfi-bt700/Kconfig
@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SPI_FLASH_STMICRO
imply SPI_FLASH_SPANSION
imply SPI_FLASH_WINBOND
+   select SERIAL_IRQ_BUFFER
 
 config PCIE_ECAM_BASE
default 0xe000
-- 
2.14.1

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[U-Boot] [PATCH 1/4] x86: serial.dtsi: Add UART interrupt property

[Stefan Roese]

This patch adds the interrupt property for the legacy 0x3f8 NS16550
UART on standard x86 platforms. This can be used to enable the RX
interrupt buffer support of the ns16550 driver, so that even very
long lines can be pasted in the U-Boot console shell.

Signed-off-by: Stefan Roese 
Cc: Simon Glass 
Cc: Bin Meng 
---
 arch/x86/dts/serial.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi
index 22f7b54fed..3d0c40783f 100644
--- a/arch/x86/dts/serial.dtsi
+++ b/arch/x86/dts/serial.dtsi
@@ -6,5 +6,6 @@
reg-shift = <0>;
clock-frequency = <1843200>;
current-speed = <115200>;
+   interrupts = <4>;
};
 };
-- 
2.14.1

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[U-Boot] [PATCH 2/4] x86: dfi-bt700.dtsi: Add PCI HS-UART interrupt property

[Stefan Roese]

This patch adds the interrupt property for the PCI HS-UART NS16550
UART on Bay Trail x86 platforms. This can be used to enable the RX
interrupt buffer support of the ns16550 driver, so that even very
long lines can be pasted in the U-Boot console shell.

Please note that in general the interrupt number should be read
from the PCI config registers by the UART driver. But since the UART
driver is called very early in the init process, these PCI config
registers are not initialized yet at this time. And since the PCI
interrupt configuration is also fixed in the dfi-bt700.dtsi file,
adding this one interrupt property to the UART DT node will not cause
any problems with dynamic interrupt assignments resulting in a
different interrupt number for this PCI device.

Signed-off-by: Stefan Roese 
Cc: Simon Glass 
Cc: Bin Meng 
---
 arch/x86/dts/dfi-bt700.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi
index b62e00ff1f..1ccdf5d24b 100644
--- a/arch/x86/dts/dfi-bt700.dtsi
+++ b/arch/x86/dts/dfi-bt700.dtsi
@@ -115,6 +115,7 @@
reg-shift = <2>;
clock-frequency = <58982400>;
current-speed = <115200>;
+   interrupts = <7>;
};
 
pch@1f,0 {
-- 
2.14.1

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[U-Boot] [PATCH 3/4] x86: conga-qeval20-qa3-e3845: Select SERIAL_IRQ_BUFFER via Kconfig

[Stefan Roese]

To support more input characters (longer stings pasted into the U-Boot
prompt) without dropping, lets selects the recently added UART RX
interrupt buffer for these boards.

Signed-off-by: Stefan Roese 
Cc: Simon Glass 
Cc: Bin Meng 
---
 board/congatec/conga-qeval20-qa3-e3845/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/congatec/conga-qeval20-qa3-e3845/Kconfig 
b/board/congatec/conga-qeval20-qa3-e3845/Kconfig
index e1fae737ac..9ca24489e8 100644
--- a/board/congatec/conga-qeval20-qa3-e3845/Kconfig
+++ b/board/congatec/conga-qeval20-qa3-e3845/Kconfig
@@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SPI_FLASH_STMICRO
imply SPI_FLASH_SPANSION
imply SPI_FLASH_WINBOND
+   select SERIAL_IRQ_BUFFER
 
 config PCIE_ECAM_BASE
default 0xe000
-- 
2.14.1

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[U-Boot] [PATCH] serial: ns16550: Enhancements to the RX interrupt buffer support

[Stefan Roese]

This patch changes the RX interrupt buffer support in these ways, mostly
suggested by Bin Meng a few weeks ago:

- The RX interrupt buffers size is now configurable via Kconfig
  (default still at 256 bytes)
- For NS16550 devices on the PCI bus, the interrupt number will be
  read from the PCI config space. Please note that this might not
  result in the correct non-zero interrupt number for this PCI
  device, as the UART init code is called very early, currently on
  x86 before the PCI config registers are initialized via U-Boot
- If the interrupt number is not provided, the code falls back to
  the normal polling mode
- The RX interrupt generation is disabled in the UART in the remove
  function

While reworking this RX interrupt buffer support, the "default n" is
also removed from Kconfig as its not needed as pointed out by Bin Meng.
Also, a missing comment for the 'irq' variable is added to the
header.

Signed-off-by: Stefan Roese 
Cc: Simon Glass 
Cc: Bin Meng 
Cc: Tom Rini 
---
 drivers/serial/Kconfig   |  8 +++-
 drivers/serial/ns16550.c | 41 +++--
 include/ns16550.h|  2 +-
 3 files changed, 39 insertions(+), 12 deletions(-)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index a8e997834a..1b19b24f10 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -67,13 +67,19 @@ config DM_SERIAL
 config SERIAL_IRQ_BUFFER
bool "Enable RX interrupt buffer for serial input"
depends on DM_SERIAL
-   default n
help
  Enable RX interrupt buffer support for the serial driver.
  This enables pasting longer strings, even when the RX FIFO
  of the UART is not big enough (e.g. 16 bytes on the normal
  NS16550).
 
+config SERIAL_IRQ_BUFFER_SIZE
+   int "RX interrupt buffer size"
+   depends on SERIAL_IRQ_BUFFER
+   default 256
+   help
+ The size of the RX interrupt buffer
+
 config SPL_DM_SERIAL
bool "Enable Driver Model for serial drivers in SPL"
depends on DM_SERIAL
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 607a1b8c1d..a24ba75031 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -453,11 +453,13 @@ int ns16550_serial_probe(struct udevice *dev)
/* Allocate the RX buffer */
plat->buf = malloc(BUF_COUNT);
 
-   /* Install the interrupt handler */
-   irq_install_handler(plat->irq, ns16550_handle_irq, dev);
+   if (plat->irq) {
+   /* Install the interrupt handler */
+   irq_install_handler(plat->irq, ns16550_handle_irq, dev);
 
-   /* Enable RX interrupts */
-   serial_out(UART_IER_RDI, _port->ier);
+   /* Enable RX interrupts */
+   serial_out(UART_IER_RDI, _port->ier);
+   }
}
 #endif
 
@@ -469,9 +471,13 @@ int ns16550_serial_probe(struct udevice *dev)
 static int ns16550_serial_remove(struct udevice *dev)
 {
 #if CONFIG_IS_ENABLED(SERIAL_IRQ_BUFFER)
-   if (gd->flags & GD_FLG_RELOC) {
-   struct ns16550_platdata *plat = dev->platdata;
+   struct ns16550_platdata *plat = dev->platdata;
+
+   if ((gd->flags & GD_FLG_RELOC) && (plat->irq)) {
+   struct NS16550 *const com_port = dev_get_priv(dev);
 
+   /* Disable RX interrupts */
+   serial_out(CONFIG_SYS_NS16550_IER, _port->ier);
irq_free_handler(plat->irq);
}
 #endif
@@ -504,6 +510,7 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
struct fdt_pci_addr pci_addr;
u32 bar;
int ret;
+   u8 irq;
 
/* we prefer to use a memory-mapped register */
ret = fdtdec_get_pci_addr(gd->fdt_blob, dev_of_offset(dev),
@@ -524,6 +531,10 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
return ret;
 
addr = bar;
+
+   /* Try to get the PCI interrupt number */
+   dm_pci_read_config8(dev, PCI_INTERRUPT_LINE, );
+   plat->irq = irq;
}
 #endif
 
@@ -562,12 +573,22 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
plat->fcr |= UART_FCR_UME;
 
 #if CONFIG_IS_ENABLED(SERIAL_IRQ_BUFFER)
-   plat->irq = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-  "interrupts", 0);
+   /*
+* If the interrupt is not provided via PCI, read the number from
+* the DT instead
+*/
if (!plat->irq) {
-   debug("ns16550 interrupt not provided\n");
-   return -EINVAL;
+   plat->irq = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+  "interrupts", 0);
}
+
+   /*
+   

Re: [U-Boot] board: atmel: Enable to use new timer driver

[Yang, Wenyou]

Hi Tom,

On 2017/8/14 0:00, Tom Rini wrote:

On Fri, Aug 04, 2017 at 08:39:33AM +0800, wenyou.y...@microchip.com wrote:


Use the Atmel PIT timer driver which supports the driver model
and device tree.

Signed-off-by: Wenyou Yang 

As-is this breaks:
at91sam9x5ek_nandflash sama5d36ek_cmp_spiflash at91sam9x5ek_mmc
sama5d4ek_nandflash sama5d3xek_nandflash sama5d3xek_spiflash
at91sam9n12ek_nandflash at91sam9n12ek_spiflash sama5d4_xplained_mmc
sama5d4ek_spiflash at91sam9n12ek_mmc at91sam9m10g45ek_nandflash
sama5d4_xplained_nandflash sama5d3xek_mmc at91sam9x5ek_spiflash
sama5d2_xplained_spiflash sama5d2_xplained_mmc sama5d36ek_cmp_nandflash
sama5d4ek_mmc sama5d4_xplained_spiflash at91sam9m10g45ek_mmc
sama5d3_xplained_nandflash sama5d36ek_cmp_mmc at91sam9x5ek_dataflash
gurnard sama5d3_xplained_mmc

Will fix in the new version.

Thank you.

Wenyou Yang
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Re: [U-Boot] [PATCH 1/2] arm: use $loadaddr as the standalone entry point

[Wolfgang Denk]

Dear Tom,

In message <20170814211300.GM20467@bill-the-cat> you wrote:
> 
> But we're talking about CONFIG_STANDALONE_LOAD_ADDR not
> CONFIG_STANDALONE_ENTRY_POINT.  What we've been doing in
> arch/arm/config.mk has been on my to fix list for a long time, because
> it's been wrong for so many boards.  Setting this to CONFIG_LOADADDR is
> a reasonable default value.

No, it is not.  It is fundamentally broken. If you need a default
for the entry point address, then define one.  CONFIG_LOADADDR means
where the image gets loaded to, and almost all image formats have a
header in front of the payuload, so the entry point is somewhere
else.  And even if you load raw binary images, there is no guarantee
that the entry point is right at the start of the image,

Mixing things that are defined for different purposes (loading image
versus start address of the code) is a really bad idea.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
The faster I go, the behinder I get. -- Lewis Carroll
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[U-Boot] [PATCH v5 2/2] sun50i: a64: Add initial NanoPi A64 support

[Jagan Teki]

From: Jagan Teki 

NanoPi A64 is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner A64 SOC.

Nanopi A64 features
- Allwinner A64, 64-bit Quad-core Cortex-A53@648MHz to 1.152GHz, DVFS
- 1GB DDR3 RAM
- MicroSD
- Gigabit Ethernet (RTL8211E)
- Wi-Fi 802.11b/g/n
- IR receiver
- Audio In/Out
- Video In/Out
- Serial Debug Port
- microUSB 5V 2A DC power-supply

Signed-off-by: Jagan Teki 
Tested-by: Jagan Teki 
---
Changes for v5:
- Sync to Linux
Changes for v4:
- Added serial1 alias
- Fix to use mmc1 for SDIO instead of mmc2
- Replace buswidth by 4 instead of 8 mmc1
- Drop cap-mmc-hw-reset for mmc1
Changes for v3:
- Added ohci0, ehci0, ohic1, ehci1, usbphy, mmc1 and uart1 nodes

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/sun50i-a64-nanopi-a64.dts | 115 +
 board/sunxi/MAINTAINERS|   5 ++
 configs/nanopi_a64_defconfig   |  15 +
 4 files changed, 136 insertions(+)
 create mode 100644 arch/arm/dts/sun50i-a64-nanopi-a64.dts
 create mode 100644 configs/nanopi_a64_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c2dc240..8da32d8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -335,6 +335,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-orangepi-zero-plus2.dtb
 dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-bananapi-m64.dtb \
+   sun50i-a64-nanopi-a64.dtb \
sun50i-a64-orangepi-win.dtb \
sun50i-a64-pine64-plus.dtb \
sun50i-a64-pine64.dtb
diff --git a/arch/arm/dts/sun50i-a64-nanopi-a64.dts 
b/arch/arm/dts/sun50i-a64-nanopi-a64.dts
new file mode 100644
index 000..778636c
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-nanopi-a64.dts
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2017 Jagan Teki 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+#include 
+
+/ {
+   model = "FriendlyARM NanoPi A64";
+   compatible = "friendlyarm,nanopi-a64", "allwinner,sun50i-a64";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   reg_vcc3v3: vcc3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+/* i2c1 connected with gpio headers like pine64, bananapi */
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   status = "disabled";
+};
+
+_pins {
+   bias-pull-up;
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   vmmc-supply = <_vcc3v3>;
+   cd-gpios = < 5 6 GPIO_ACTIVE_HIGH>;
+   cd-inverted;
+   disable-wp;
+   bus-width = <4>;
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+ 

[U-Boot] [PATCH v5 1/2] sun50i: a64: Sync Linux [oe]hci0 nodes

[Jagan Teki]

From: Jagan Teki 

Synced ohci0 and ehci0 nodes from Linux for sun50i-a64.dtsi

Here is the Linux last merge tag details:
Merge: 0e91f43d e5770b7
Author: Stephen Rothwell 
Date:   Fri Jun 9 14:59:55 2017 +1000

Merge remote-tracking branch 'staging/staging-next'

Signed-off-by: Jagan Teki 
---
Changes for v5:
- none

 arch/arm/dts/sun50i-a64.dtsi | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index c7f669f..65a344d 100644
--- a/arch/arm/dts/sun50i-a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -204,6 +204,28 @@
#phy-cells = <1>;
};
 
+   ehci0: usb@01c1a000 {
+   compatible = "allwinner,sun50i-a64-ehci", 
"generic-ehci";
+   reg = <0x01c1a000 0x100>;
+   interrupts = ;
+   clocks = < CLK_BUS_OHCI0>,
+< CLK_BUS_EHCI0>,
+< CLK_USB_OHCI0>;
+   resets = < RST_BUS_OHCI0>,
+< RST_BUS_EHCI0>;
+   status = "disabled";
+   };
+
+   ohci0: usb@01c1a400 {
+   compatible = "allwinner,sun50i-a64-ohci", 
"generic-ohci";
+   reg = <0x01c1a400 0x100>;
+   interrupts = ;
+   clocks = < CLK_BUS_OHCI0>,
+< CLK_USB_OHCI0>;
+   resets = < RST_BUS_OHCI0>;
+   status = "disabled";
+   };
+
ehci1: usb@01c1b000 {
compatible = "allwinner,sun50i-a64-ehci", 
"generic-ehci";
reg = <0x01c1b000 0x100>;
-- 
2.7.4

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[U-Boot] [PATCH v2] sun50i: a64: Add A64-OLinuXino initial support

[Jagan Teki]

From: Jagan Teki 

OLimex A64-OLinuXino is an open-source hardware board
using the Allwinner A64 SOC.

OLimex A64-OLinuXino has
- A64 Quad-core Cortex-A53 64bit
- 1GB or 2GB RAM DDR3L @ 672Mhz
- microSD slot and 4/8/16GB eMMC
- Debug TTL UART
- HDMI
- LCD
- IR receiver
- 5V DC power supply

Tested-by: Jagan Teki 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- Tested on latest
- Sync to Linux

 arch/arm/dts/Makefile |  1 +
 arch/arm/dts/sun50i-a64-olinuxino.dts | 84 +++
 board/sunxi/MAINTAINERS   |  5 +++
 configs/a64-olinuxino_defconfig   | 15 +++
 4 files changed, 105 insertions(+)
 create mode 100644 arch/arm/dts/sun50i-a64-olinuxino.dts
 create mode 100644 configs/a64-olinuxino_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8da32d8..21a8103 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -336,6 +336,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
 dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-bananapi-m64.dtb \
sun50i-a64-nanopi-a64.dtb \
+   sun50i-a64-olinuxino.dtb \
sun50i-a64-orangepi-win.dtb \
sun50i-a64-pine64-plus.dtb \
sun50i-a64-pine64.dtb
diff --git a/arch/arm/dts/sun50i-a64-olinuxino.dts 
b/arch/arm/dts/sun50i-a64-olinuxino.dts
new file mode 100644
index 000..7bd4730
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-olinuxino.dts
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2017 Jagan Teki 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+#include 
+
+/ {
+   model = "Olimex A64-Olinuxino";
+   compatible = "olimex,a64-olinuxino", "allwinner,sun50i-a64";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   reg_vcc3v3: vcc3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   vmmc-supply = <_vcc3v3>;
+   cd-gpios = < 5 6 GPIO_ACTIVE_HIGH>;
+   cd-inverted;
+   disable-wp;
+   bus-width = <4>;
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+   status = "okay";
+};
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 3b8d544..ff6eea2 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -98,6 +98,11 @@ M:   Stefan Mavrodiev 
 S: Maintained
 F: configs/A33-OLinuXino_defconfig
 
+A64-OLINUXINO BOARD
+M: Jagan Teki 
+S: Maintained
+F: configs/a64-olinuxino_defconfig
+
 A80 OPTIMUS BOARD
 M: Chen-Yu Tsai 
 S: Maintained
diff --git a/configs/a64-olinuxino_defconfig