Re: [U-Boot] powerpc 4xx support

[Cédric Le Goater]

On 11/14/2017 07:21 PM, Ivan Mikhaylov1 wrote:
> hi everyone, I saw that powerpc 4xx cpus were removed from powerpc cpu tree 
> with this commit 
> 98f705c9cefdfdba62c069821bbba10273a0a8ed
> powerpc: remove 4xx support

That was quite a cleanup !

 471 files changed, 14 insertions(+), 85191 deletions(-)

> I can help to maintain this tree with further support and needs. As I 
> understood reason of this 
> removal was change to Kconfig. Anything else should be done? In this case 
> what process should be?
> 1. get cpu 4xx before removal

I don't think you would want to re-add support for all 
the cpus or all the boards. Just pick the ones you will 
maintain for IBM needs. 

Some recently added cpu/boards can serve as an example 
to organize your patchset.  

> 2. do the migration to kconfig

yes and also probably refresh some of the important drivers,
clk, sdram, reset, watchdog, etc. 

You might want to add a device tree.

> 3. send patches via uboot mail list

yes definitively.

> something like this ?
Does QEMU support such cpu/machines ? It would be good
to contribute some models if it is not too much work.

Thanks, 

C. 
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Re: [U-Boot] powerpc 4xx support

[Stefan Roese]

Hi Ivan,

On 15.11.2017 04:42, Tom Rini wrote:

On Tue, Nov 14, 2017 at 06:21:17PM +, Ivan Mikhaylov1 wrote:


hi everyone, I saw that powerpc 4xx cpus were removed from powerpc
cpu tree with this commit
98f705c9cefdfdba62c069821bbba10273a0a8ed
powerpc: remove 4xx support

I can help to maintain this tree with further support and needs.


I would very much welcome to see ppc4xx actively maintained in
U-Boot again. :)


As I understood reason of this
removal was change to Kconfig. Anything else should be done? In
this case what process should be?
1. get cpu 4xx before removal
2. do the migration to kconfig
3. send patches via uboot mail list
something like this?


So, we need active testing and maintenance.  To bring 4xx support back,
introduce patches that bring in core support and migrate the code to
using Kconfig only.  There must be no new entries to
scripts/config_whitelist.txt


Additionally to this, some (all?) device drivers would need to be
converted to DM (driver model).

Thanks,
Stefan
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Re: [U-Boot] powerpc 4xx support

[Tom Rini]

On Tue, Nov 14, 2017 at 06:21:17PM +, Ivan Mikhaylov1 wrote:

> hi everyone, I saw that powerpc 4xx cpus were removed from powerpc cpu tree 
> with this commit 
> 98f705c9cefdfdba62c069821bbba10273a0a8ed
> powerpc: remove 4xx support
> 
> I can help to maintain this tree with further support and needs. As I 
> understood reason of this 
> removal was change to Kconfig. Anything else should be done? In this case 
> what process should be?
> 1. get cpu 4xx before removal
> 2. do the migration to kconfig
> 3. send patches via uboot mail list
> something like this?

So, we need active testing and maintenance.  To bring 4xx support back,
introduce patches that bring in core support and migrate the code to
using Kconfig only.  There must be no new entries to
scripts/config_whitelist.txt

-- 
Tom


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Re: [U-Boot] [OE-core] [PATCH] u-boot: Upgrade to 2017.11 release

[Tom Rini]

On Tue, Nov 14, 2017 at 04:32:23PM -0200, Otavio Salvador wrote:

> This upgrades the U-Boot from 2017.09 to 2017.11 release.
> 
> Signed-off-by: Otavio Salvador 

Reviewed-by: Tom Rini 

-- 
Tom


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Re: [U-Boot] [RFC PATCH 1/2] board: laird: add WB45N CPU module

[Tom Rini]

On Thu, Nov 09, 2017 at 10:24:13AM +, Ben Whitten wrote:
> On 02 August 2017 15:49, Tom Rini wrote:
> > On Wed, Aug 02, 2017 at 11:58:42AM +0200, Stefano Babic wrote:
> > > On 07/07/2017 12:40, Ben Whitten wrote:
> > > > This board is based on the Atmel 9x5 eval board.
> > > > Supporting the following features:
> > > >  - Boot from NAND Flash
> > > >  - Ethernet
> > > >  - FIT
> > > >  - SPL
> > > >
> > >
> > > Patch is assigned to me. However, this is Atmel, now orphaned. I
> > > haven't work with AT-91 since a very long time, so I cannot say more
> > > about patches, but it is a pity if the patches will be lost. Tom,
> > > should I merge them even if they are not i.MX related ? Or do you pick
> > > them yourself ?
> > 
> > Ah, sorry, I saw laird, had the WiFi modules they do for i.MX series 
> > platforms
> > in mind and went "oh, must be an i.MX system".  Please toss them back to
> > me, thanks!
> 
> Hi Tom,
> Any comments on these boards? Whilst I was at ELCE I bumped into Marek and
> had a talk about adding new boards, he had mentioned new boards should be
> using DM.
> As this is the direction things are moving let me know and I can convert them.

Sorry.  Can you please re-test and re-post against top of tree and I'll
make sure it gets in, assuming no other problems show up.  Thanks!

-- 
Tom


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[U-Boot] [PATCH] atcpit100: timer: Remove arch dependency.

[Andes]

From: Rick Chen 

ATCPIT100 is often used in AE3XX platform which is
based on NDS32 architecture recently. But in the future
Andestech will have AE250 platform which is embeded
ATCPIT100 timer based on RISCV architecture.

Signed-off-by: Rick Chen 
---
 drivers/timer/Kconfig |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index fcfdf4e..3a1f831 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -107,7 +107,7 @@ config AG101P_TIMER
 
 config ATCPIT100_TIMER
bool "ATCPIT100 timer support"
-   depends on TIMER && NDS32
+   depends on TIMER
help
  Select this to enable a ATCPIT100 timer which will be embeded
in AE3XX, AE250 boards.
-- 
1.7.9.5

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Re: [U-Boot] [PATCH] enable debug uart

[rick]

Hi, All

This is wrong patch sending.

Please ignore it.

Rick

-Original Message-
From: Open Source Project uboot
Sent: Wednesday, November 15, 2017 10:48 AM
To: u-boot@lists.denx.de; w...@denx.de; d...@denx.de; s...@chromium.org
Cc: Rick Jian-Zhi Chen(陳建志)
Subject: [PATCH] enable debug uart

From: rick 

---
 common/board_f.c|2 ++
 configs/adp-ae3xx_defconfig |5 +
 drivers/serial/Kconfig  |8 
 drivers/serial/ns16550.c|5 +++--
 include/debug_uart.h|2 ++
 lib/display_options.c   |2 ++
 6 files changed, 22 insertions(+), 2 deletions(-)  mode change 100644 => 
100755 common/board_f.c  mode change 100644 => 100755 common/init/board_init.c  
mode change 100644 => 100755 configs/adp-ae3xx_defconfig  mode change 100644 => 
100755 drivers/serial/Kconfig  mode change 100644 => 100755 
drivers/serial/ns16550.c  mode change 100644 => 100755 include/debug_uart.h  
mode change 100644 => 100755 lib/display_options.c

diff --git a/common/board_f.c b/common/board_f.c old mode 100644 new mode 
100755 index 104d144..1024987
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -902,6 +902,8 @@ static const init_fnc_t init_sequence_f[] = {

 void board_init_f(ulong boot_flags)
 {
+//printf("board_init_f\n");
+//while(1);
gd->flags = boot_flags;
gd->have_console = 0;

diff --git a/common/init/board_init.c b/common/init/board_init.c old mode 
100644 new mode 100755 diff --git a/configs/adp-ae3xx_defconfig 
b/configs/adp-ae3xx_defconfig old mode 100644 new mode 100755 index 
db9ee61..02386d6
--- a/configs/adp-ae3xx_defconfig
+++ b/configs/adp-ae3xx_defconfig
@@ -38,3 +38,8 @@ CONFIG_DM_SPI=y
 CONFIG_NDS_AE3XX_SPI=y
 CONFIG_TIMER=y
 CONFIG_AE3XX_TIMER=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xf030
+CONFIG_DEBUG_UART_CLOCK=14745600
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_OFFSET=32
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig old mode 100644 
new mode 100755 index aeed538..34d49be
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -319,6 +319,14 @@ config DEBUG_UART_SHIFT
  value. Use this value to specify the shift to use, where 0=byte
  registers, 2=32-bit word registers, etc.

+config DEBUG_UART_OFFSET
+   int "UART register offset"
+   depends on DEBUG_UART
+   default 0 if DEBUG_UART
+   help
+ Offset to apply to the mapbase from the start of the registers.
+
+
 config DEBUG_UART_BOARD_INIT
bool "Enable board-specific debug UART init"
depends on DEBUG_UART
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c old mode 
100644 new mode 100755 index c702304..b67af3d
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -31,8 +31,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define serial_out(x, y)   out_le32(y, x)
 #define serial_in(y)   in_le32(y)
 #else
-#define serial_out(x, y)   writeb(x, y)
-#define serial_in(y)   readb(y)
+@
+#define serial_out(x, y)   writeb(x, y+CONFIG_SYS_NS16550_REG_OFFSET)
+#define serial_in(y)   readb(y+CONFIG_SYS_NS16550_REG_OFFSET)
 #endif
 #endif /* !CONFIG_DM_SERIAL */

diff --git a/include/debug_uart.h b/include/debug_uart.h old mode 100644 new 
mode 100755 index 6f0b0c5..a369fb2
--- a/include/debug_uart.h
+++ b/include/debug_uart.h
@@ -113,11 +113,13 @@ void printhex8(uint value);

 #define serial_dout(reg, value)\
serial_out_shift((char *)com_port + \
+   CONFIG_DEBUG_UART_OFFSET + \
((char *)reg - (char *)com_port) * \
(1 << CONFIG_DEBUG_UART_SHIFT), \
CONFIG_DEBUG_UART_SHIFT, value)
 #define serial_din(reg) \
serial_in_shift((char *)com_port + \
+   CONFIG_DEBUG_UART_OFFSET + \
((char *)reg - (char *)com_port) * \
(1 << CONFIG_DEBUG_UART_SHIFT), \
CONFIG_DEBUG_UART_SHIFT)
diff --git a/lib/display_options.c b/lib/display_options.c old mode 100644 new 
mode 100755 index 4ea27ca..8ee63ce
--- a/lib/display_options.c
+++ b/lib/display_options.c
@@ -41,6 +41,8 @@ char *display_options_get_banner(bool newlines, char *buf, 
int size)

 int display_options(void)
 {
+printf("display_options\n");
+//while(1);
char buf[DISPLAY_OPTIONS_BANNER_LENGTH];

display_options_get_banner(true, buf, sizeof(buf));
--
1.7.9.5

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Copyright ANDES TECHNOLOGY CORPORATION - All 

[U-Boot] [PATCH 3/3] dt-bindings: timer: Add andestech atcpit100 timer binding doc

[Andes]

From: Rick Chen 

Add a document to describe Andestech atcpit100 timer and
binding information.

Signed-off-by: Rick Chen 
---
 doc/device-tree-bindings/timer/atcpit100_timer.txt |   31 
 1 file changed, 31 insertions(+)
 create mode 100644 doc/device-tree-bindings/timer/atcpit100_timer.txt

diff --git a/doc/device-tree-bindings/timer/atcpit100_timer.txt 
b/doc/device-tree-bindings/timer/atcpit100_timer.txt
new file mode 100644
index 000..620814e
--- /dev/null
+++ b/doc/device-tree-bindings/timer/atcpit100_timer.txt
@@ -0,0 +1,31 @@
+Andestech ATCPIT100 timer
+--
+ATCPIT100 is a generic IP block from Andes Technology, embedded in
+Andestech AE3XX, AE250 platforms and other designs.
+
+This timer is a set of compact multi-function timers, which can be
+used as pulse width modulators (PWM) as well as simple timers.
+
+It supports up to 4 PIT channels. Each PIT channel is a
+multi-function timer and provide the following usage scenarios:
+One 32-bit timer
+Two 16-bit timers
+Four 8-bit timers
+One 16-bit PWM
+One 16-bit timer and one 8-bit PWM
+Two 8-bit timer and one 8-bit PWM
+
+Required properties:
+- compatible   : Should be "andestech,atcpit100"
+- reg  : Address and length of the register set
+- interrupts   : Reference to the timer interrupt
+- clock-frequency : The rate in HZ in input of the Andestech ATCPIT100 timer
+
+Examples:
+
+timer0: timer@f040 {
+   compatible = "andestech,atcpit100";
+   reg = <0xf040 0x1000>;
+   interrupts = <2 4>;
+   clock-frequency = <3000>;
+}:
-- 
1.7.9.5

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[U-Boot] [PATCH 2/3] nds32: defconfig: Rename AE3XX_TIMER to ATCPIT100_TIMER

[Andes]

From: Rick Chen 

Change AE3XX to its IP name ATCPIT100.

Signed-off-by: Rick Chen 
---
 configs/adp-ae3xx_defconfig |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/adp-ae3xx_defconfig b/configs/adp-ae3xx_defconfig
index 3d8383d..a3d8b29 100644
--- a/configs/adp-ae3xx_defconfig
+++ b/configs/adp-ae3xx_defconfig
@@ -38,4 +38,4 @@ CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_NDS_AE3XX_SPI=y
 CONFIG_TIMER=y
-CONFIG_AE3XX_TIMER=y
+CONFIG_ATCPIT100_TIMER=y
-- 
1.7.9.5

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[U-Boot] [PATCH] enable debug uart

[Andes]

From: rick 

---
 common/board_f.c|2 ++
 configs/adp-ae3xx_defconfig |5 +
 drivers/serial/Kconfig  |8 
 drivers/serial/ns16550.c|5 +++--
 include/debug_uart.h|2 ++
 lib/display_options.c   |2 ++
 6 files changed, 22 insertions(+), 2 deletions(-)
 mode change 100644 => 100755 common/board_f.c
 mode change 100644 => 100755 common/init/board_init.c
 mode change 100644 => 100755 configs/adp-ae3xx_defconfig
 mode change 100644 => 100755 drivers/serial/Kconfig
 mode change 100644 => 100755 drivers/serial/ns16550.c
 mode change 100644 => 100755 include/debug_uart.h
 mode change 100644 => 100755 lib/display_options.c

diff --git a/common/board_f.c b/common/board_f.c
old mode 100644
new mode 100755
index 104d144..1024987
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -902,6 +902,8 @@ static const init_fnc_t init_sequence_f[] = {
 
 void board_init_f(ulong boot_flags)
 {
+//printf("board_init_f\n");
+//while(1);
gd->flags = boot_flags;
gd->have_console = 0;
 
diff --git a/common/init/board_init.c b/common/init/board_init.c
old mode 100644
new mode 100755
diff --git a/configs/adp-ae3xx_defconfig b/configs/adp-ae3xx_defconfig
old mode 100644
new mode 100755
index db9ee61..02386d6
--- a/configs/adp-ae3xx_defconfig
+++ b/configs/adp-ae3xx_defconfig
@@ -38,3 +38,8 @@ CONFIG_DM_SPI=y
 CONFIG_NDS_AE3XX_SPI=y
 CONFIG_TIMER=y
 CONFIG_AE3XX_TIMER=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xf030
+CONFIG_DEBUG_UART_CLOCK=14745600
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_OFFSET=32
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
old mode 100644
new mode 100755
index aeed538..34d49be
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -319,6 +319,14 @@ config DEBUG_UART_SHIFT
  value. Use this value to specify the shift to use, where 0=byte
  registers, 2=32-bit word registers, etc.
 
+config DEBUG_UART_OFFSET
+   int "UART register offset"
+   depends on DEBUG_UART
+   default 0 if DEBUG_UART
+   help
+ Offset to apply to the mapbase from the start of the registers.
+
+
 config DEBUG_UART_BOARD_INIT
bool "Enable board-specific debug UART init"
depends on DEBUG_UART
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
old mode 100644
new mode 100755
index c702304..b67af3d
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -31,8 +31,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define serial_out(x, y)   out_le32(y, x)
 #define serial_in(y)   in_le32(y)
 #else
-#define serial_out(x, y)   writeb(x, y)
-#define serial_in(y)   readb(y)
+@
+#define serial_out(x, y)   writeb(x, y+CONFIG_SYS_NS16550_REG_OFFSET)
+#define serial_in(y)   readb(y+CONFIG_SYS_NS16550_REG_OFFSET)
 #endif
 #endif /* !CONFIG_DM_SERIAL */
 
diff --git a/include/debug_uart.h b/include/debug_uart.h
old mode 100644
new mode 100755
index 6f0b0c5..a369fb2
--- a/include/debug_uart.h
+++ b/include/debug_uart.h
@@ -113,11 +113,13 @@ void printhex8(uint value);
 
 #define serial_dout(reg, value)\
serial_out_shift((char *)com_port + \
+   CONFIG_DEBUG_UART_OFFSET + \
((char *)reg - (char *)com_port) * \
(1 << CONFIG_DEBUG_UART_SHIFT), \
CONFIG_DEBUG_UART_SHIFT, value)
 #define serial_din(reg) \
serial_in_shift((char *)com_port + \
+   CONFIG_DEBUG_UART_OFFSET + \
((char *)reg - (char *)com_port) * \
(1 << CONFIG_DEBUG_UART_SHIFT), \
CONFIG_DEBUG_UART_SHIFT)
diff --git a/lib/display_options.c b/lib/display_options.c
old mode 100644
new mode 100755
index 4ea27ca..8ee63ce
--- a/lib/display_options.c
+++ b/lib/display_options.c
@@ -41,6 +41,8 @@ char *display_options_get_banner(bool newlines, char *buf, 
int size)
 
 int display_options(void)
 {
+printf("display_options\n");
+//while(1);
char buf[DISPLAY_OPTIONS_BANNER_LENGTH];
 
display_options_get_banner(true, buf, sizeof(buf));
-- 
1.7.9.5

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[U-Boot] [PATCH 1/3] ae3xx: timer: Rename AE3XX to ATCPIT100

[Andes]

From: Rick Chen 

ATCPIT100 is Andestech timer IP which is embeded
in AE3XX and AE250 boards. So rename AE3XX to
ATCPIT100 will be more make sence.

Signed-off-by: Rick Chen 
---
 drivers/timer/Kconfig   |7 ++-
 drivers/timer/Makefile  |2 +-
 drivers/timer/ae3xx_timer.c |  117 ---
 drivers/timer/atcpit100_timer.c |  117 +++
 4 files changed, 122 insertions(+), 121 deletions(-)
 delete mode 100644 drivers/timer/ae3xx_timer.c
 create mode 100644 drivers/timer/atcpit100_timer.c

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 6305bbf..fcfdf4e 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -105,11 +105,12 @@ config AG101P_TIMER
help
  Select this to enable a timer for AG01P devices.
 
-config AE3XX_TIMER
-   bool "AE3XX timer support"
+config ATCPIT100_TIMER
+   bool "ATCPIT100 timer support"
depends on TIMER && NDS32
help
- Select this to enable a timer for AE3XX devices.
+ Select this to enable a ATCPIT100 timer which will be embeded
+   in AE3XX, AE250 boards.
 
 config ROCKCHIP_TIMER
 bool "Rockchip timer support"
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index 69e8961..15e5154 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -13,6 +13,6 @@ obj-$(CONFIG_AST_TIMER)   += ast_timer.o
 obj-$(CONFIG_STI_TIMER)+= sti-timer.o
 obj-$(CONFIG_ARC_TIMER)+= arc_timer.o
 obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
-obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o
+obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o
 obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
 obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o
diff --git a/drivers/timer/ae3xx_timer.c b/drivers/timer/ae3xx_timer.c
deleted file mode 100644
index b710c28..000
--- a/drivers/timer/ae3xx_timer.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Andestech ATCPIT100 timer driver
- *
- * (C) Copyright 2016
- * Rick Chen, NDS32 Software Engineering, r...@andestech.com
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-#include 
-#include 
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define REG32_TMR(x)   (*(u32 *)   ((plat->regs) + (x>>2)))
-
-/*
- * Definition of register offsets
- */
-
-/* ID and Revision Register */
-#define ID_REV 0x0
-
-/* Configuration Register */
-#define CFG0x10
-
-/* Interrupt Enable Register */
-#define INT_EN 0x14
-#define CH_INT_EN(c , i)   ((1<platdata;
-   u32 val;
-   val = ~(REG32_TMR(CH_CNT(1))+0x);
-   *count = timer_conv_64(val);
-   return 0;
-}
-
-static int atctmr_timer_probe(struct udevice *dev)
-{
-   struct atftmr_timer_platdata *plat = dev->platdata;
-   REG32_TMR(CH_REL(1)) = 0x;
-   REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32;
-   REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0);
-   return 0;
-}
-
-static int atctme_timer_ofdata_to_platdata(struct udevice *dev)
-{
-   struct atftmr_timer_platdata *plat = dev_get_platdata(dev);
-   plat->regs = map_physmem(devfdt_get_addr(dev) , 0x100 , MAP_NOCACHE);
-   return 0;
-}
-
-static const struct timer_ops ag101p_timer_ops = {
-   .get_count = atftmr_timer_get_count,
-};
-
-static const struct udevice_id ag101p_timer_ids[] = {
-   { .compatible = "andestech,atcpit100" },
-   {}
-};
-
-U_BOOT_DRIVER(altera_timer) = {
-   .name   = "ae3xx_timer",
-   .id = 

[U-Boot] [PATCH 0/3] ae3xx: timer: Rename AE3XX timer to ATCPIT100

[Andes]

From: Rick Chen 

AE3XX is board name. ATCPIT100 is timer IP name.
So rename AE3XX timer to ATCPIT100 timer.

Rick Chen (3):
  ae3xx: timer: Rename AE3XX to ATCPIT100
  nds32: defconfig: Rename AE3XX_TIMER to ATCPIT100_TIMER
  dt-bindings: timer: Add andestech atcpit100 timer binding doc

 configs/adp-ae3xx_defconfig|2 +-
 doc/device-tree-bindings/timer/atcpit100_timer.txt |   31 ++
 drivers/timer/Kconfig  |7 +-
 drivers/timer/Makefile |2 +-
 drivers/timer/ae3xx_timer.c|  117 
 drivers/timer/atcpit100_timer.c|  117 
 6 files changed, 154 insertions(+), 122 deletions(-)
 create mode 100644 doc/device-tree-bindings/timer/atcpit100_timer.txt
 delete mode 100644 drivers/timer/ae3xx_timer.c
 create mode 100644 drivers/timer/atcpit100_timer.c

-- 
1.7.9.5

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[U-Boot] [PATCH] ae3xx: timer: Fix ae3xx timer work abnormal in 64 bit.

[Andes]

From: Rick Chen 

It will be work fine with unsigned long declaretion in timer
register struct when system is 32 bit. But it will not work
well when system is 64 bit. Replace it by u32 and verify both
ok in 32/64 bit.

Signed-off-by: Rick Chen 
---
 drivers/timer/ae3xx_timer.c |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/timer/ae3xx_timer.c b/drivers/timer/ae3xx_timer.c
index bcc07a0..b710c28 100644
--- a/drivers/timer/ae3xx_timer.c
+++ b/drivers/timer/ae3xx_timer.c
@@ -14,7 +14,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define REG32_TMR(x)   (*(unsigned long *) ((plat->regs) + (x>>2)))
+#define REG32_TMR(x)   (*(u32 *)   ((plat->regs) + (x>>2)))
 
 /*
  * Definition of register offsets
@@ -68,7 +68,7 @@ struct atctmr_timer_regs {
 };
 
 struct atftmr_timer_platdata {
-   unsigned long *regs;
+   u32 *regs;
 };
 
 static int atftmr_timer_get_count(struct udevice *dev, u64 *count)
-- 
1.7.9.5

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Re: [U-Boot] [PATCH 1/1] Makefile: add coccicheck target

[Masahiro Yamada]

2017-11-15 1:21 GMT+09:00 Heinrich Schuchardt :
> On 11/14/2017 10:34 AM, Masahiro Yamada wrote:
>>
>> Hi.
>>
>>
>> 2017-11-11 3:54 GMT+09:00 Heinrich Schuchardt :
>>>
>>> Coccinelle is a program for static code analysis.
>>> For details on Coccinelle see
>>>
>>>  http://coccinelle.lip6.fr/
>>>
>>> Add scripts/coccicheck and Documentation/dev-tools/coccinelle.rst
>>> copied from Linux kernel v4.14-rc8.
>>>
>>> The coccicheck script executes the tests *.cocci in
>>> directory scripts/coccinelle by calling spatch.
>>>
>>> In Makefile add a coccicheck target. You can use it with
>>>
>>>  make coccicheck MODE=
>>>
>>> where mode in patch, report, context, org.
>>>
>>> Signed-off-by: Heinrich Schuchardt 
>>
>>
>> You can run "make coccicheck" without the .config file.
>> So, you need to add coccinelle to no-dot-config-targets.
>>
>>
>> Refer to the following code in Linux.
>>
>> no-dot-config-targets := clean mrproper distclean \
>>   cscope gtags TAGS tags help% %docs check%
>> coccicheck \
>>   $(version_h) headers_% archheaders archscripts \
>>   kernelversion %src-pkg
>>
>
> For whatever reason the Makefile without my patch already had a coccicheck
> entry in this list.
>
> We should not add it twice.
>

Oops, I missed the current Makefile had it.

Sorry for noise.



-- 
Best Regards
Masahiro Yamada
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Re: [U-Boot] [PATCH 6/6] pico-imx6ul: Use FS_GENERIC load command

[Fabio Estevam]

On Tue, Nov 14, 2017 at 4:07 PM, Otavio Salvador
 wrote:
> From: Fabio Berton 
>
> Signed-off-by: Fabio Berton 
> Signed-off-by: Otavio Salvador 

Reviewed-by: Fabio Estevam 
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Re: [U-Boot] [PATCH 5/6] pico-imx6ul: Add function to create gpt partitions

[Fabio Estevam]

On Tue, Nov 14, 2017 at 4:07 PM, Otavio Salvador
 wrote:
> From: Fabio Berton 
>
> Command run setup_emmc will create gpt partitions for mmc 0 device
> based on patitions variable.
>
> Signed-off-by: Fabio Berton 
> Signed-off-by: Otavio Salvador 

Reviewed-by: Fabio Estevam 
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Re: [U-Boot] [PATCH 3/6] pico-imx6ul: Add boot and rootfs dfu_alt_info

[Fabio Estevam]

On Tue, Nov 14, 2017 at 4:07 PM, Otavio Salvador
 wrote:
> From: Fabio Berton 
>
> Change dfu_alt_info variable to use the following altsetting:
>
>   uboot: To flash raw U-Boot
>   /zImage: boot: To copy kernel image
>   /imx6ul-pico-hobbit.dtb:   To copy dtb file
>   rootfs:To copy rootfs
>
> List the currently attached DFU capable USB devices running:
>   sudo dfu-util -l
>
> Flash U-Boot:
>   sudo dfu-util -D u-boot.imx -a uboot
>
> Copy boot files:
>   sudo dfu-util -D zImage -a /zImage
>   sudo dfu-util -D imx6ul-pico-hobbit.dtb -a /imx6ul-pico-hobbit.dtb
>
> Flash rootfs:
>   sudo dfu-util -D rootfs.ext4 -a rootfs
>
> To copy boot files you need to have a formated mmc 0:1 partition. To
> format with ext4 filesystem you can use ums.
>
> Run on target:
>   ums 0 mmc 0
>
> and on host:
>   sudo mkfs.ext4 /dev/sdx1
>
> Signed-off-by: Fabio Berton 
> Signed-off-by: Otavio Salvador 

Reviewed-by: Fabio Estevam 
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Re: [U-Boot] [PATCH 2/6] pico-imx6ul: Use PARTUUID to specify the rootfs location

[Fabio Estevam]

On Tue, Nov 14, 2017 at 4:07 PM, Otavio Salvador
 wrote:
> From: Fabio Berton 
>
> Currently the rootfs location is passed via mmcblk number and using
> the UUID method to specify the rootfs location is a better approach
> working even if mmcblk number for the eMMM changes depending on the

s/eMMM/eMMC

With this fixed:

Reviewed-by: Fabio Estevam 
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Re: [U-Boot] [PATCH 1/6] pico-imx6ul: Move dfu_alt_info to CONFIG_DFU_ENV_SETTINGS variable

[Fabio Estevam]

On Tue, Nov 14, 2017 at 4:07 PM, Otavio Salvador
 wrote:
> From: Fabio Berton 
>
> Create CONFIG_DFU_ENV_SETTINGS to set dfu environment settings to
> improve human readable code.
>
> Signed-off-by: Fabio Berton 
> Signed-off-by: Otavio Salvador 

Reviewed-by: Fabio Estevam 
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Re: [U-Boot] [PATCH] mach-stm32: Fix mpu region's attribute for STM32H7

[Vikas MANOCHA]

Hi Patrice,

Cheers,
Vikas

> -Original Message-
> From: Patrice CHOTARD
> Sent: Tuesday, November 14, 2017 12:41 AM
> To: Vikas MANOCHA ; u-boot@lists.denx.de; 
> albert.u.b...@aribaud.net; s...@chromium.org
> Cc: Patrick DELAUNAY ; Christophe KERELLO 
> 
> Subject: Re: [PATCH] mach-stm32: Fix mpu region's attribute for STM32H7
> 
> Hi Vikas
> 
> On 11/14/2017 03:16 AM, Vikas MANOCHA wrote:
> > Hi Patrice,
> >
> >> -Original Message-
> >> From: Patrice CHOTARD
> >> Sent: Monday, November 13, 2017 8:26 AM
> >> To: u-boot@lists.denx.de; albert.u.b...@aribaud.net;
> >> s...@chromium.org; Vikas MANOCHA 
> >> Cc: Patrice CHOTARD ; Patrick DELAUNAY
> >> ; Christophe KERELLO
> >> 
> >> Subject: [PATCH] mach-stm32: Fix mpu region's attribute for STM32H7
> >>
> >> From: Patrice Chotard 
> >>
> >> The SDRAM region was setup with the wrong attributes.
> >> It must be set to :
> >>_ XN_EN (Execution of an instruction fetched from this region permitted)
> >>_ O_I_WB_RD_WR_ALLOC (Outer and inner write-back, write and read
> >> allocate)
> >>
> >
> > H7 mpu configuration seems same as F7, can we have one config for F7 & H7.
> 
> Between F7 and H7, there is one difference regarding the F7's region 3 which 
> is not needed on H7 because FMC/QSPI registers are
> located inside H7's region 2.

Yes, that’s correct. Any way we can handle it at one place.
In any case, for easy maintenance let's keep the same configuration/code for 
two with this above exception.

> 
> Just one question about F7's region 1, why is it only 512MB and not 1GB long, 
> to include ITCM and DTCM area ? (see Embedded SRAM
> chapter of
> RM0385 Reference manual)

because 512MB (0x2000_) is size of armv7m code area.

Cheers,
Vikas

> 
> Nevertheless, i just notice that for H7, i can remove region 1 which overlaps 
> region 0 with exactly the same attribute.
> 
> Thanks
> 
> >
> >> This fixes hard fault when trying to load and execute kernel linux in this 
> >> area.
> >>
> >> Signed-off-by: Patrice Chotard 
> >
> > In any case,
> > Reviewed-by: Vikas Manocha 
> >
> > Cheers,
> > Vikas
> >
> >> ---
> >>   arch/arm/mach-stm32/stm32h7/soc.c | 9 ++---
> >>   1 file changed, 6 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/arch/arm/mach-stm32/stm32h7/soc.c
> >> b/arch/arm/mach-stm32/stm32h7/soc.c
> >> index 692dbcc..e0d3f11 100644
> >> --- a/arch/arm/mach-stm32/stm32h7/soc.c
> >> +++ b/arch/arm/mach-stm32/stm32h7/soc.c
> >> @@ -30,9 +30,12 @@ int arch_cpu_init(void)
> >>{ 0x, REGION_0, XN_DIS, PRIV_RW_USR_RW,
> >>O_I_WB_RD_WR_ALLOC, REGION_4GB },
> >>
> >> -  /* Code area, executable & strongly ordered */
> >> -  { 0xD000, REGION_1, XN_EN, PRIV_RW_USR_RW,
> >> -  STRONG_ORDER, REGION_8MB },
> >> +  /*
> >> +   * Code area, executable, Outer and inner write-back,
> >> +   * no write allocate
> >> +   */
> >> +  { 0xD000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
> >> +  O_I_WB_RD_WR_ALLOC, REGION_32MB },
> >>
> >>/* Device area in all H7 : Not executable */
> >>{ 0x4000, REGION_2, XN_EN, PRIV_RW_USR_RW,
> >> --
> >> 1.9.1
> >
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Re: [U-Boot] [PATCH 4/6] pico-imx6ul: Define partition layout in the environment

[Fabio Estevam]

On Tue, Nov 14, 2017 at 4:07 PM, Otavio Salvador
 wrote:
> From: Fabio Berton 
>
> Create layout with a boot 16MiB partition and rootfs with remain
> space.
>
> Signed-off-by: Fabio Berton 
> Signed-off-by: Otavio Salvador 
> ---
>
>  include/configs/pico-imx6ul.h | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
> index 6a19861da7..43ef3ef6d0 100644
> --- a/include/configs/pico-imx6ul.h
> +++ b/include/configs/pico-imx6ul.h
> @@ -68,6 +68,9 @@
> "mmcautodetect=yes\0" \
> CONFIG_DFU_ENV_SETTINGS \
> "finduuid=part uuid mmc 0:2 uuid\0" \
> +   "partitions=" \
> +   "uuid_disk=${uuid_gpt_disk};" \
> +   
> "name=boot,size=16Mib;name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \

Please make this 16MiB instead.
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Re: [U-Boot] [PATCH 13/13] binman: tegra: Convert to use binman

[Stephen Warren]

On 11/13/2017 06:55 PM, Simon Glass wrote:

Update tegra to use binman for image creation. This still includes the
current Makefile logic, but a later patch will remove this. Three output
files are created, all of which combine
SPL and U-Boot:

u-boot-tegra.bin  - standard image
u-boot-dtb-tegra.bin  - same as u-boot-tegra.bin
u-boot-nodtb  - includes U-Boot without the appended device tree


I assume that last file is u-boot-nodtb-tegra.bin?

If this series doesn't change the set of binaries produced by the build 
system (add/drop/rename), then I'm fine with it.


For the record, I know of tools that use the following files, at least:

u-boot (ELF)
u-boot.bin
u-boot.dtb
u-boot-dtb.bin
u-boot-nodtb-tegra.bin
u-boot-dtb-tegra.bin
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[U-Boot] powerpc 4xx support

[Ivan Mikhaylov1]

hi everyone, I saw that powerpc 4xx cpus were removed from powerpc cpu tree 
with this commit 
98f705c9cefdfdba62c069821bbba10273a0a8ed
powerpc: remove 4xx support

I can help to maintain this tree with further support and needs. As I 
understood reason of this 
removal was change to Kconfig. Anything else should be done? In this case what 
process should be?
1. get cpu 4xx before removal
2. do the migration to kconfig
3. send patches via uboot mail list
something like this?

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[U-Boot] [PATCH] u-boot: Upgrade to 2017.11 release

[Otavio Salvador]

This upgrades the U-Boot from 2017.09 to 2017.11 release.

Signed-off-by: Otavio Salvador 
---

 .../u-boot/{u-boot-common_2017.09.inc => u-boot-common_2017.11.inc} | 2 +-
 .../u-boot/{u-boot-fw-utils_2017.09.bb => u-boot-fw-utils_2017.11.bb}   | 0
 .../u-boot/{u-boot-mkimage_2017.09.bb => u-boot-mkimage_2017.11.bb} | 0
 meta/recipes-bsp/u-boot/{u-boot_2017.09.bb => u-boot_2017.11.bb}| 0
 4 files changed, 1 insertion(+), 1 deletion(-)
 rename meta/recipes-bsp/u-boot/{u-boot-common_2017.09.inc => 
u-boot-common_2017.11.inc} (89%)
 rename meta/recipes-bsp/u-boot/{u-boot-fw-utils_2017.09.bb => 
u-boot-fw-utils_2017.11.bb} (100%)
 rename meta/recipes-bsp/u-boot/{u-boot-mkimage_2017.09.bb => 
u-boot-mkimage_2017.11.bb} (100%)
 rename meta/recipes-bsp/u-boot/{u-boot_2017.09.bb => u-boot_2017.11.bb} (100%)

diff --git a/meta/recipes-bsp/u-boot/u-boot-common_2017.09.inc 
b/meta/recipes-bsp/u-boot/u-boot-common_2017.11.inc
similarity index 89%
rename from meta/recipes-bsp/u-boot/u-boot-common_2017.09.inc
rename to meta/recipes-bsp/u-boot/u-boot-common_2017.11.inc
index 02e51242cb..bfdf1a0d8f 100644
--- a/meta/recipes-bsp/u-boot/u-boot-common_2017.09.inc
+++ b/meta/recipes-bsp/u-boot/u-boot-common_2017.11.inc
@@ -7,7 +7,7 @@ PE = "1"
 
 # We use the revision in order to avoid having to fetch it from the
 # repo during parse
-SRCREV = "c98ac3487e413c71e5d36322ef3324b21c6f60f9"
+SRCREV = "c253573f3e269fd9a24ee6684d87dd91106018a5"
 
 SRC_URI = "git://git.denx.de/u-boot.git \
 file://MPC8315ERDB-enable-DHCP.patch \
diff --git a/meta/recipes-bsp/u-boot/u-boot-fw-utils_2017.09.bb 
b/meta/recipes-bsp/u-boot/u-boot-fw-utils_2017.11.bb
similarity index 100%
rename from meta/recipes-bsp/u-boot/u-boot-fw-utils_2017.09.bb
rename to meta/recipes-bsp/u-boot/u-boot-fw-utils_2017.11.bb
diff --git a/meta/recipes-bsp/u-boot/u-boot-mkimage_2017.09.bb 
b/meta/recipes-bsp/u-boot/u-boot-mkimage_2017.11.bb
similarity index 100%
rename from meta/recipes-bsp/u-boot/u-boot-mkimage_2017.09.bb
rename to meta/recipes-bsp/u-boot/u-boot-mkimage_2017.11.bb
diff --git a/meta/recipes-bsp/u-boot/u-boot_2017.09.bb 
b/meta/recipes-bsp/u-boot/u-boot_2017.11.bb
similarity index 100%
rename from meta/recipes-bsp/u-boot/u-boot_2017.09.bb
rename to meta/recipes-bsp/u-boot/u-boot_2017.11.bb
-- 
2.15.0

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[U-Boot] [PATCH 6/6] pico-imx6ul: Use FS_GENERIC load command

[Otavio Salvador]

From: Fabio Berton 

Signed-off-by: Fabio Berton 
Signed-off-by: Otavio Salvador 
---

 include/configs/pico-imx6ul.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index b7469f8031..4a43515782 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -74,8 +74,8 @@
"setup_emmc=gpt write mmc 0 $partitions; reset;\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=PARTUUID=${uuid} rootwait rw\0" \
-   "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-   "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+   "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+   "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run finduuid; " \
"run mmcargs; " \
-- 
2.15.0

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[U-Boot] [PATCH 3/6] pico-imx6ul: Add boot and rootfs dfu_alt_info

[Otavio Salvador]

From: Fabio Berton 

Change dfu_alt_info variable to use the following altsetting:

  uboot: To flash raw U-Boot
  /zImage: boot: To copy kernel image
  /imx6ul-pico-hobbit.dtb:   To copy dtb file
  rootfs:To copy rootfs

List the currently attached DFU capable USB devices running:
  sudo dfu-util -l

Flash U-Boot:
  sudo dfu-util -D u-boot.imx -a uboot

Copy boot files:
  sudo dfu-util -D zImage -a /zImage
  sudo dfu-util -D imx6ul-pico-hobbit.dtb -a /imx6ul-pico-hobbit.dtb

Flash rootfs:
  sudo dfu-util -D rootfs.ext4 -a rootfs

To copy boot files you need to have a formated mmc 0:1 partition. To
format with ext4 filesystem you can use ums.

Run on target:
  ums 0 mmc 0

and on host:
  sudo mkfs.ext4 /dev/sdx1

Signed-off-by: Fabio Berton 
Signed-off-by: Otavio Salvador 
---

 include/configs/pico-imx6ul.h | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index c775c32690..6a19861da7 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -48,7 +48,11 @@
 #define DFU_DEFAULT_POLL_TIMEOUT 300
 
 #define CONFIG_DFU_ENV_SETTINGS \
-   "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
+   "dfu_alt_info=uboot raw 0x2 0x400 mmcpart 1;" \
+   "boot part 0 1;" \
+   "/zImage ext4 0 1;" \
+   "/imx6ul-pico-hobbit.dtb ext4 0 1;" \
+   "rootfs part 0 2\0" \
 
 #define CONFIG_SYS_MMC_IMG_LOAD_PART   1
 
-- 
2.15.0

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[U-Boot] [PATCH 5/6] pico-imx6ul: Add function to create gpt partitions

[Otavio Salvador]

From: Fabio Berton 

Command run setup_emmc will create gpt partitions for mmc 0 device
based on patitions variable.

Signed-off-by: Fabio Berton 
Signed-off-by: Otavio Salvador 
---

 configs/pico-imx6ul_defconfig | 1 +
 include/configs/pico-imx6ul.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index e00f9f34a3..f28f9b7a4e 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -12,6 +12,7 @@ CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index 43ef3ef6d0..b7469f8031 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -71,6 +71,7 @@
"partitions=" \
"uuid_disk=${uuid_gpt_disk};" \

"name=boot,size=16Mib;name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \
+   "setup_emmc=gpt write mmc 0 $partitions; reset;\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=PARTUUID=${uuid} rootwait rw\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-- 
2.15.0

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[U-Boot] [PATCH 4/6] pico-imx6ul: Define partition layout in the environment

[Otavio Salvador]

From: Fabio Berton 

Create layout with a boot 16MiB partition and rootfs with remain
space.

Signed-off-by: Fabio Berton 
Signed-off-by: Otavio Salvador 
---

 include/configs/pico-imx6ul.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index 6a19861da7..43ef3ef6d0 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -68,6 +68,9 @@
"mmcautodetect=yes\0" \
CONFIG_DFU_ENV_SETTINGS \
"finduuid=part uuid mmc 0:2 uuid\0" \
+   "partitions=" \
+   "uuid_disk=${uuid_gpt_disk};" \
+   
"name=boot,size=16Mib;name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=PARTUUID=${uuid} rootwait rw\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-- 
2.15.0

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[U-Boot] [PATCH 2/6] pico-imx6ul: Use PARTUUID to specify the rootfs location

[Otavio Salvador]

From: Fabio Berton 

Currently the rootfs location is passed via mmcblk number and using
the UUID method to specify the rootfs location is a better approach
working even if mmcblk number for the eMMM changes depending on the
kernel versions.

Signed-off-by: Fabio Berton 
Signed-off-by: Otavio Salvador 
---

 configs/pico-imx6ul_defconfig | 1 +
 include/configs/pico-imx6ul.h | 6 +++---
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index 09b36ccb09..e00f9f34a3 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -13,6 +13,7 @@ CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_DHCP=y
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index d4b29e3950..c775c32690 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -61,14 +61,15 @@
"fdt_addr=0x8300\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
-   "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
CONFIG_DFU_ENV_SETTINGS \
+   "finduuid=part uuid mmc 0:2 uuid\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
-   "root=${mmcroot}\0" \
+   "root=PARTUUID=${uuid} rootwait rw\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
+   "run finduuid; " \
"run mmcargs; " \
"if run loadfdt; then " \
"bootz ${loadaddr} - ${fdt_addr}; " \
@@ -147,6 +148,5 @@
 
 #define CONFIG_SYS_MMC_ENV_DEV 0
 #define CONFIG_SYS_MMC_ENV_PART0
-#define CONFIG_MMCROOT "/dev/mmcblk0p2"
 
 #endif /* __PICO_IMX6UL_CONFIG_H */
-- 
2.15.0

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[U-Boot] [PATCH 1/6] pico-imx6ul: Move dfu_alt_info to CONFIG_DFU_ENV_SETTINGS variable

[Otavio Salvador]

From: Fabio Berton 

Create CONFIG_DFU_ENV_SETTINGS to set dfu environment settings to
improve human readable code.

Signed-off-by: Fabio Berton 
Signed-off-by: Otavio Salvador 
---

 include/configs/pico-imx6ul.h | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index 75658fd489..d4b29e3950 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -47,6 +47,9 @@
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
 #define DFU_DEFAULT_POLL_TIMEOUT 300
 
+#define CONFIG_DFU_ENV_SETTINGS \
+   "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
+
 #define CONFIG_SYS_MMC_IMG_LOAD_PART   1
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -60,7 +63,7 @@
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
-   "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
+   CONFIG_DFU_ENV_SETTINGS \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-- 
2.15.0

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[U-Boot] [PATCH] Move Cache-As-RAM memory from area mapped to ROM in QEMU

[Anton Gerasimov]

ROM has been made read-only in qemu recently (namely commit
208fa0e43645edd0b0d8f838857dfc79daff40a8), so this patch restores
compatibility between u-boot and qemu.

Signed-off-by: Anton Gerasimov 
---
 arch/x86/cpu/qemu/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig
index 6808c9a6b9..f4b9922a34 100644
--- a/arch/x86/cpu/qemu/Kconfig
+++ b/arch/x86/cpu/qemu/Kconfig
@@ -11,7 +11,7 @@ if QEMU
 
 config SYS_CAR_ADDR
hex
-   default 0xd
+   default 0x1
 
 config SYS_CAR_SIZE
hex
-- 
2.14.1

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Re: [U-Boot] Move Cache-As-RAM memory from area mapped to ROM in QEMU

[Heinrich Schuchardt]

On 11/13/2017 11:23 AM, Anton Gerasimov wrote:

Thank you Heinrich, I can confirm that current u-boot master works
without reverting 55751ab1. I had problems with u-boot v2017.11-rc2
apparently.


Could you, please, resubmit the patch with an updated commit message.

Regards

Heinrich


Best regards,
Anton Gerasimov

On 11/11/2017 12:08 PM, Heinrich Schuchardt wrote:

On 11/10/2017 06:51 PM, Anton Gerasimov wrote:

ROM has been made read-only in qemu recently (namely commit
208fa0e43645edd0b0d8f838857dfc79daff40a8), so this patch restores
compatibility between u-boot and qemu. It is still broken for me
unless I set CONFIG_SMP=n and disable lapic (i.e. revert patch
55751ab1e5a5cfa0962d604593a7e6f33ff6 in u-boot), but these are
separate issues


I could not reproduce that reverting 55751ab1 is necessary.
Your patch and CONFIG_SMP=n was suffcient to start U-Boot with
qemu-system-x86_64 version 2.10.1(Debian 1:2.10.0+dfsg-2)

Tested-by: Heinrich Schuchardt 



Signed-off-by: Anton Gerasimov 
---
   arch/x86/cpu/qemu/Kconfig | 2 +-
   1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig
index 6808c9a6b9..f4b9922a34 100644
--- a/arch/x86/cpu/qemu/Kconfig
+++ b/arch/x86/cpu/qemu/Kconfig
@@ -11,7 +11,7 @@ if QEMU
     config SYS_CAR_ADDR
   hex
-    default 0xd
+    default 0x1
     config SYS_CAR_SIZE
   hex






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Re: [U-Boot] [PATCH v6 1/7] armv8: lsch3: Add serdes and DDR voltage setup

[York Sun]

On 11/13/2017 11:06 PM, Rajesh Bhagat wrote:
> Adds SERDES voltage and reset SERDES lanes API and makes
> enable/disable DDR controller support 0.9V API common.
> 
> Signed-off-by: Ashish Kumar 
> Signed-off-by: Rajesh Bhagat 
> ---
> Changes in v6:
>   
>   - Corrected indentation/alignment issues at various places  
>   
>   - Changed NULL ENTRY in srds_prctl_info array to id as zero 
>   
>   - Corrected the PLL Reset logic, moved code inside for loop 
>   
>   - Used error code(-EINVAL) in setup_serdes_volt API
> 
> Changes in v5:
>   
>   - Moved local macros to static functions
>   
>   - Used array to handle PRCTL mask and shift operations
> 
> Changes in v4:
>   
>   - Added local macros instead of magical numbers 
>   
>   - Created macros to remove duplicate code
> 
> Changes in v3:
>  Restructured LS1088A VID support to use common VID driver
>  Cosmetic review comments fixed
>  Added __iomem for accessing registers
> 
> Changes in v2:
>  Checkpatch errors fixed
> 
>  .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c| 312 
> +
>  arch/arm/cpu/armv8/fsl-layerscape/soc.c|  34 +--
>  .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |   2 +-
>  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  34 +++
>  arch/arm/include/asm/arch-fsl-layerscape/soc.h |   1 +
>  5 files changed, 365 insertions(+), 18 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c 
> b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
> index 179cac6..3e4b0bc 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
> @@ -158,6 +158,318 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 
> sd_prctl_mask,
>   serdes_prtcl_map[NONE] = 1;
>  }
>  
> +__weak int get_serdes_volt(void)
> +{
> + return -1;
> +}
> +
> +__weak int set_serdes_volt(int svdd)
> +{
> + return -1;
> +}
> +
> +#define LNAGCR0_RESET_MASK   0xFF9F
> +#define LNAGCR0_RT_RSTB  0x0060
> +#define RSTCTL_RESET_MASK_1  0xFFBF
> +#define RSTCTL_RESET_MASK_2  0xFF1F
> +#define RSTCTL_RESET_MASK_3  0xFFEF
> +#define RSTCTL_RSTREQ0x1000
> +#define RSTCTL_RSTERR0x2000
> +#define RSTCTL_SDEN  0x0020
> +#define RSTCTL_SDRST_B   0x0040
> +#define RSTCTL_PLLRST_B  0x0080
> +#define RSTCTL_RST_DONE  0x4000
> +#define TCALCR_RESET_MASK0xF7FF
> +#define TCALCR_CALRST_B  0x0800
> +
> +struct serdes_prctl_info {
> + u32 id;
> + u32 mask;
> + u32 shift;
> +};
> +
> +struct serdes_prctl_info srds_prctl_info[] = {
> +#ifdef CONFIG_SYS_FSL_SRDS_1
> + {.id = 1,
> +  .mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK,
> +  .shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
> + },
> +
> +#endif
> +#ifdef CONFIG_SYS_FSL_SRDS_2
> + {.id = 2,
> +  .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
> +  .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
> + },
> +#endif
> + {.id = 0,
> +  .mask = 0,
> +  .shift = 0
> + } /* NULL ENTRY */
> +};

A simple {} will do the same.

> +
> +static int get_serdes_prctl_info_idx(u32 serdes_id)
> +{
> + int pos = 0;
> + struct serdes_prctl_info *srds_info;
> +
> + /* loop until NULL ENTRY defined by .id=0 */
> + for (srds_info = srds_prctl_info; srds_info->id != 0;
> +  srds_info++, pos++) {
> + if (srds_info->id == serdes_id)
> + return pos;
> + }
> +
> + return -1;
> +}
> +
> +static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg,
> +struct ccsr_serdes __iomem *serdes_base,
> +bool cmplt)
> +{
> + int i, pos;
> + u32 cfg_tmp, reg = 0;
> +
> + pos = get_serdes_prctl_info_idx(serdes_id);
> + if (pos == -1) {
> + printf("invalid serdes_id %d\n", serdes_id);
> + return;
> + }
> +
> + cfg_tmp = cfg & srds_prctl_info[pos].mask;
> + cfg_tmp >>= srds_prctl_info[pos].shift;
> +
> + for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
> + reg = in_le32(_base->lane[i].gcr0);
> + reg = (cmplt ? reg | LNAGCR0_RT_RSTB :
> +reg & LNAGCR0_RESET_MASK);
> + out_le32(_base->lane[i].gcr0, reg);
> + }
> +}

Have you considered to use clrbits_le32(), setbits_le32(),
clrsetbits_le32() here and below as I suggested on previous review?

York
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Re: [U-Boot] [PATCH 1/1] Makefile: add coccicheck target

[Heinrich Schuchardt]

On 11/14/2017 10:34 AM, Masahiro Yamada wrote:

Hi.


2017-11-11 3:54 GMT+09:00 Heinrich Schuchardt :

Coccinelle is a program for static code analysis.
For details on Coccinelle see

 http://coccinelle.lip6.fr/

Add scripts/coccicheck and Documentation/dev-tools/coccinelle.rst
copied from Linux kernel v4.14-rc8.

The coccicheck script executes the tests *.cocci in
directory scripts/coccinelle by calling spatch.

In Makefile add a coccicheck target. You can use it with

 make coccicheck MODE=

where mode in patch, report, context, org.

Signed-off-by: Heinrich Schuchardt 


You can run "make coccicheck" without the .config file.
So, you need to add coccinelle to no-dot-config-targets.


Refer to the following code in Linux.

no-dot-config-targets := clean mrproper distclean \
  cscope gtags TAGS tags help% %docs check% coccicheck \
  $(version_h) headers_% archheaders archscripts \
  kernelversion %src-pkg



For whatever reason the Makefile without my patch already had a 
coccicheck entry in this list.


We should not add it twice.

Best regards

Heinrich
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Re: [U-Boot] [PATCH 1/1] configs: DISTRO_DEFAULTS for MACCHIATObin

[Stefan Roese]

Hi Heinrich,

On 12.11.2017 15:47, Heinrich Schuchardt wrote:

Hello Konstantin, hello Stefan,

in which git repository do you consolidate the MVEBU_ARMADA_8K and 
MACCHIATOBin work?


All this usually goes through the u-boot-marvell repo, where
(currently) I collect the patches.


I could not find this information in
board/Marvell/mvebu_armada-8k/MAINTAINERS

It would be helpful if you could add a line like:
T:    git://github.com/foo/u-boot.git

Please, request Tom to pull the patch below for v2018.01.


I'll pull this patch later this week with the other
pending MVEBU patches.

Thanks,
Stefan
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[U-Boot] [PATCH v5 2/2] DW SPI: Get clock value from Device Tree

[Eugeniy Paltsev]

Add option to set spi controller clock frequency via device tree
using standard clock bindings.

Define dw_spi_get_clk function as 'weak' as some targets
(like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
and implement dw_spi_get_clk their own way in their clock manager.

Get rid of clock_manager.h include as we don't use
cm_get_spi_controller_clk_hz function anymore. (we use redefined
dw_spi_get_clk in SOCFPGA clock managers instead)

Signed-off-by: Eugeniy Paltsev 
---
 drivers/spi/designware_spi.c | 42 --
 1 file changed, 40 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 6cc4f51..470a3a7 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -12,6 +12,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -19,7 +20,6 @@
 #include 
 #include 
 #include 
-#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -95,6 +95,7 @@ struct dw_spi_priv {
void __iomem *regs;
unsigned int freq;  /* Default frequency */
unsigned int mode;
+   unsigned long bus_clk_rate;
 
struct gpio_desc cs_gpio;   /* External chip-select gpio */
 
@@ -195,14 +196,51 @@ static void spi_hw_init(struct dw_spi_priv *priv)
debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
 }
 
+/*
+ * We define dw_spi_get_clk function as 'weak' as some targets
+ * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) fon't use standard clock API
+ * and implement dw_spi_get_clk their own way in their clock manager.
+ */
+__weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+   struct clk clk;
+   int ret;
+
+   ret = clk_get_by_index(bus, 0, );
+   if (ret)
+   return -EINVAL;
+
+   ret = clk_enable();
+   if (ret && ret != -ENOSYS)
+   return ret;
+
+   *rate = clk_get_rate();
+   if (!*rate) {
+   clk_disable();
+   return -EINVAL;
+   }
+
+   debug("%s: get spi controller clk via device tree: %lu Hz\n",
+ __func__, *rate);
+
+   clk_free();
+
+   return 0;
+}
+
 static int dw_spi_probe(struct udevice *bus)
 {
struct dw_spi_platdata *plat = dev_get_platdata(bus);
struct dw_spi_priv *priv = dev_get_priv(bus);
+   int ret;
 
priv->regs = plat->regs;
priv->freq = plat->frequency;
 
+   ret = dw_spi_get_clk(bus, >bus_clk_rate);
+   if (ret)
+   return ret;
+
/* Currently only bits_per_word == 8 supported */
priv->bits_per_word = 8;
 
@@ -411,7 +449,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed)
spi_enable_chip(priv, 0);
 
/* clk_div doesn't support odd number */
-   clk_div = cm_get_spi_controller_clk_hz() / speed;
+   clk_div = priv->bus_clk_rate / speed;
clk_div = (clk_div + 1) & 0xfffe;
dw_write(priv, DW_SPI_BAUDR, clk_div);
 
-- 
2.9.3

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[U-Boot] [PATCH v5 1/2] SOCFPGA: clock manager: implement dw_spi_get_clk function

[Eugeniy Paltsev]

Implement dw_spi_get_clk function to override its weak
implementation in designware_spi.c driver.

We need this change to get rid of cm_get_spi_controller_clk_hz
function and clock_manager.h include in designware_spi.c driver.

Reviewed-by: Marek Vasut 
Signed-off-by: Eugeniy Paltsev 
---
 arch/arm/mach-socfpga/clock_manager_arria10.c | 9 +
 arch/arm/mach-socfpga/clock_manager_gen5.c| 9 +
 2 files changed, 18 insertions(+)

diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c 
b/arch/arm/mach-socfpga/clock_manager_arria10.c
index 482b854..623a266 100644
--- a/arch/arm/mach-socfpga/clock_manager_arria10.c
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -1076,6 +1077,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
return  cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB);
 }
 
+/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
+int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+   *rate = cm_get_spi_controller_clk_hz();
+
+   return 0;
+}
+
 void cm_print_clock_quick_summary(void)
 {
printf("MPU   %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c 
b/arch/arm/mach-socfpga/clock_manager_gen5.c
index 31fd510..a371d83 100644
--- a/arch/arm/mach-socfpga/clock_manager_gen5.c
+++ b/arch/arm/mach-socfpga/clock_manager_gen5.c
@@ -6,6 +6,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -509,6 +510,14 @@ unsigned int cm_get_spi_controller_clk_hz(void)
return clock;
 }
 
+/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
+int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+   *rate = cm_get_spi_controller_clk_hz();
+
+   return 0;
+}
+
 void cm_print_clock_quick_summary(void)
 {
printf("MPU   %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
-- 
2.9.3

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[U-Boot] [PATCH v5 0/2] DW SPI: Get clock value from Device Tree

[Eugeniy Paltsev]

As discussed with Marek during the LINUX-PITER here is v4 patch:

Add option to set spi controller clock frequency via device tree
using standard clock bindings.

Define dw_spi_get_clk function as 'weak' as some targets
(like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) fon't use standard clock API
and implement dw_spi_get_clk their own way in their clock manager.

Get rid of clock_manager.h include in designware_spi.c as we don't use
cm_get_spi_controller_clk_hz function anymore - we use redefined
dw_spi_get_clk in SOCFPGA clock managers (clock_manager_gen5.c and
clock_manager_arria10.c) instead.

Changes v4->v5:
  * Get rid of usless ifdef in dw_spi_get_clk function

Eugeniy Paltsev (2):
  SOCFPGA: clock manager: implement dw_spi_get_clk function
  DW SPI: Get clock value from Device Tree

 arch/arm/mach-socfpga/clock_manager_arria10.c |  9 +
 arch/arm/mach-socfpga/clock_manager_gen5.c|  9 +
 drivers/spi/designware_spi.c  | 47 +--
 3 files changed, 63 insertions(+), 2 deletions(-)

-- 
2.9.3

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[U-Boot] [PATCH] envtools: make sure version/timestamp header file are available

[Stefan Agner]

From: Stefan Agner 

With commit 84d46e7e8948 ("tools: env: allow to print U-Boot version")
the fw_env utilities need the version.h header file. Building only
the envtools in a pristine build directory will fail due to missing
header files.

Make sure the header files are a dependency of the envtools target.

Fixes: 84d46e7e8948 ("tools: env: allow to print U-Boot version")
Signed-off-by: Stefan Agner 
---

 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 67f01ad7e4..b93c2fb05b 100644
--- a/Makefile
+++ b/Makefile
@@ -1460,7 +1460,7 @@ checkarmreloc: u-boot
false; \
fi
 
-envtools: scripts_basic
+envtools: scripts_basic $(version_h) $(timestamp_h)
$(Q)$(MAKE) $(build)=tools/env
 
 tools-only: scripts_basic $(version_h) $(timestamp_h)
-- 
2.15.0

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[U-Boot] [PATCH v2] arm: zynq: Add ps7_init for cc108

[Michal Simek]

After some generic cleanup adding ps7_init* to repository
is not big pain now.

Signed-off-by: Michal Simek 
---

Changes in v2:
 - some cleanup with ret
 - sed -i 's/\t  / /g' on this file

 board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c | 815 
 1 file changed, 815 insertions(+)
 create mode 100644 board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c

diff --git a/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c 
b/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c
new file mode 100644
index ..9a65a27f0e70
--- /dev/null
+++ b/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c
@@ -0,0 +1,815 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+   EMIT_MASKWRITE(0XF808, 0xU, 0xDF0DU),
+   EMIT_MASKWRITE(0XF8000110, 0x0030U, 0x000FA220U),
+   EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+   EMIT_MASKWRITE(0XF8000100, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0XF8000100, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0XF8000100, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0XF800010C,  0x0001U),
+   EMIT_MASKWRITE(0XF8000100, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+   EMIT_MASKWRITE(0XF8000114, 0x0030U, 0x0012C220U),
+   EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x0002U),
+   EMIT_MASKWRITE(0XF8000104, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0XF8000104, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0XF8000104, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0XF800010C,  0x0002U),
+   EMIT_MASKWRITE(0XF8000104, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0XF8000124, 0xFFF3U, 0x0C23U),
+   EMIT_MASKWRITE(0XF8000118, 0x0030U, 0x001452C0U),
+   EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+   EMIT_MASKWRITE(0XF8000108, 0x0010U, 0x0010U),
+   EMIT_MASKWRITE(0XF8000108, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0XF8000108, 0x0001U, 0xU),
+   EMIT_MASKPOLL(0XF800010C,  0x0004U),
+   EMIT_MASKWRITE(0XF8000108, 0x0010U, 0xU),
+   EMIT_MASKWRITE(0XF804, 0xU, 0x767BU),
+   EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+   EMIT_MASKWRITE(0XF808, 0xU, 0xDF0DU),
+   EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+   EMIT_MASKWRITE(0XF8000138, 0x0011U, 0x0001U),
+   EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+   EMIT_MASKWRITE(0XF800014C, 0x3F31U, 0x0501U),
+   EMIT_MASKWRITE(0XF8000150, 0x3F33U, 0x0A02U),
+   EMIT_MASKWRITE(0XF8000154, 0x3F33U, 0x0A01U),
+   EMIT_MASKWRITE(0XF8000168, 0x3F31U, 0x0501U),
+   EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+   EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U),
+   EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U),
+   EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+   EMIT_MASKWRITE(0XF80001C4, 0x0001U, 0x0001U),
+   EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DC084DU),
+   EMIT_MASKWRITE(0XF804, 0xU, 0x767BU),
+   EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+   EMIT_MASKWRITE(0XF8006000, 0x0001U, 0x0080U),
+   EMIT_MASKWRITE(0XF8006004, 0x0007U, 0x1081U),
+   EMIT_MASKWRITE(0XF8006008, 0x03FFU, 0x03C0780FU),
+   EMIT_MASKWRITE(0XF800600C, 0x03FFU, 0x02001001U),
+   EMIT_MASKWRITE(0XF8006010, 0x03FFU, 0x00014001U),
+   EMIT_MASKWRITE(0XF8006014, 0x001FU, 0x0004159BU),
+   EMIT_MASKWRITE(0XF8006018, 0xF7FFU, 0x452460D2U),
+   EMIT_MASKWRITE(0XF800601C, 0xU, 0x720238E5U),
+   EMIT_MASKWRITE(0XF8006020, 0x7FDCU, 0x270872D0U),
+   EMIT_MASKWRITE(0XF8006024, 0x0FC3U, 0xU),
+   EMIT_MASKWRITE(0XF8006028, 0x3FFFU, 0x2007U),
+   EMIT_MASKWRITE(0XF800602C, 0xU, 0x0008U),
+   EMIT_MASKWRITE(0XF8006030, 0xU, 0x00040930U),
+   EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+   EMIT_MASKWRITE(0XF8006038, 0x0003U, 0xU),
+   EMIT_MASKWRITE(0XF800603C, 0x000FU, 0x0777U),
+   EMIT_MASKWRITE(0XF8006040, 0xU, 0xFFF0U),
+   EMIT_MASKWRITE(0XF8006044, 0x0FFFU, 0x0FF6U),
+   EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+   EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+   EMIT_MASKWRITE(0XF8006058, 0x0001U, 0xU),
+   EMIT_MASKWRITE(0XF800605C, 0xU, 0x5003U),
+   EMIT_MASKWRITE(0XF8006060, 0x17FFU, 0x003EU),
+   EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x0002U),
+   EMIT_MASKWRITE(0XF8006068, 0x03FFU, 0x00284141U),
+   

Re: [U-Boot] [PATCH] mmc: sd_sdhi: add support for 32-bit data buffer

[Chris Brandt]

Hi Marek,

On Tuesday, November 14, 2017, Marek Vasut wrote:
> On 11/13/2017 09:51 PM, Chris Brandt wrote:
> > Some controllers have a 32-bit data buffer register and do not allow
> > any other access besides 32-bit read/write.
> >
> > Signed-off-by: Chris Brandt 
> 
> Can you switch to uniphier-sd instead ? I switched Gen3 away from SH
> SDHI and the uniphier driver is so much better.

Interesting.


However...

Functionally, the SDHI in the RZ/A1 is the same as R-Car.

But, there is 1 difference: The registers are spaced 16-bits apart where
the R-Car is 64-bit spaced apart.

Also, all the RZ/A1 registers are 16-bit, except for the data register 
(SD_BUF0) which is 32-bit. That's why I had to patch the upstream kernel 
driver specifically for RZ/A1.

The uniphier-sd is only setup for 32-bit or 64-bit spacing.

So, if I can get away with just this simple patch:

static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, unsigned int reg)
{
if (priv->caps & UNIPHIER_SD_CAP_64BIT)
return readl(priv->regbase + (reg << 1));
if (priv->caps & UNIPHIER_SD_CAP_16BIT)
return readl(priv->regbase + (reg >> 1));
else
return readl(priv->regbase + reg);
}

Then maybe I can use it.

I'll try it and see how it goes since I prefer to use the same drivers as R-Car.

Chris

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[U-Boot] [PATCH v2 5/9] arm: zynq: Get rid of ps7_reset_apu() for syzygy board

[Michal Simek]

There is no reason to call separate function.

Signed-off-by: Michal Simek 
---

Changes in v2: None

 board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c | 8 +---
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c 
b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
index f2a757a5cfeb..5aa3951b8017 100644
--- a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
+++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
@@ -347,17 +347,11 @@ int ps7_post_config(void)
return ps7_config(ps7_post_config_3_0);
 }
 
-
-int ps7_reset_apu(void)
-{
-   return ps7_config(ps7_reset_apu_3_0);
-}
-
 int ps7_init(void)
 {
int ret;
 
-   ret = ps7_reset_apu();
+   ret = ps7_config(ps7_reset_apu_3_0);
if (ret != PS7_INIT_SUCCESS)
return ret;
 
-- 
1.9.1

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[U-Boot] [PATCH v2 8/9] arm: zynq: Add support for EMIT_WRITE operation

[Michal Simek]

Add proper support for EMIT_WRITE operation which is write only.
Do not use EMIT_MASKWRITE which is read-modify-write.

Signed-off-by: Michal Simek 
---

Changes in v2:
- Add own opcode for write operation
- Change commit message (was Convert EMIT_WRITE to EMIT_MASKWRITE) -
  requested by Mike

 arch/arm/mach-zynq/include/mach/ps7_init_gpl.h | 2 ++
 arch/arm/mach-zynq/ps7_spl_init.c  | 6 ++
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h 
b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
index fa5d486afb0c..0af4165a3ef1 100644
--- a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
+++ b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
@@ -13,6 +13,7 @@
 #define OPCODE_MASKWRITE   0U
 #define OPCODE_MASKPOLL1U
 #define OPCODE_MASKDELAY   2U
+#define OPCODE_WRITE   3U
 #define OPCODE_ADDRESS_MASK(~3U)
 
 /* Sentinel */
@@ -21,6 +22,7 @@
 #define EMIT_MASKWRITE(addr, mask, val)OPCODE_MASKWRITE | addr, mask, 
val
 #define EMIT_MASKPOLL(addr, mask)  OPCODE_MASKPOLL | addr, mask
 #define EMIT_MASKDELAY(addr, mask) OPCODE_MASKDELAY | addr, mask
+#define EMIT_WRITE(addr, val)  OPCODE_WRITE | addr, val
 
 /* Returns codes of ps7_init* */
 #define PS7_INIT_SUCCESS   (0)
diff --git a/arch/arm/mach-zynq/ps7_spl_init.c 
b/arch/arm/mach-zynq/ps7_spl_init.c
index 069827880d10..6dc4e0364d8b 100644
--- a/arch/arm/mach-zynq/ps7_spl_init.c
+++ b/arch/arm/mach-zynq/ps7_spl_init.c
@@ -108,6 +108,12 @@ int __weak ps7_config(unsigned long *ps7_config_init)
iowrite((ioread(addr) & ~mask) | (val & mask), addr);
break;
 
+   case OPCODE_WRITE:
+   numargs = 2;
+   val = ptr[1];
+   iowrite(val, addr);
+   break;
+
case OPCODE_MASKPOLL:
numargs = 2;
mask = ptr[1];
-- 
1.9.1

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[U-Boot] [PATCH v2 6/9] arm: zynq: Move common ps7_init* initialization to arch code

[Michal Simek]

This patch is based on work done in topic board where the first address
word also storing operation which should be done. This is reducing size
of configuration data.
This patch is not breaking an option to copy default ps7_init_gpl* files
from hdf file but it is doing preparation for ps7_init* consolidation.

The patch is also marking ps7_config as weak function.

Signed-off-by: Michal Simek 
---

Changes in v2:
- Fix indentation by using tabs instead of spaces

 arch/arm/mach-zynq/include/mach/ps7_init_gpl.h |  28 -
 arch/arm/mach-zynq/ps7_spl_init.c  | 109 +++
 board/topic/zynq/Makefile  |   2 +-
 board/topic/zynq/ps7_init_common.c | 117 -
 board/topic/zynq/ps7_init_gpl.h|  34 --
 board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c   |   2 +-
 .../topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c |   2 +-
 .../topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c |   2 +-
 8 files changed, 140 insertions(+), 156 deletions(-)
 delete mode 100644 board/topic/zynq/ps7_init_common.c
 delete mode 100644 board/topic/zynq/ps7_init_gpl.h

diff --git a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h 
b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
index 6e30108b23f4..c7c716e7f2c4 100644
--- a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
+++ b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
@@ -1,5 +1,6 @@
 /*
- * (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,8 +8,33 @@
 #ifndef _ASM_ARCH_PS7_INIT_GPL_H
 #define _ASM_ARCH_PS7_INIT_GPL_H
 
+/* Opcode exit is 0 all the time */
+#define OPCODE_EXIT0U
+#define OPCODE_MASKWRITE   0U
+#define OPCODE_MASKPOLL1U
+#define OPCODE_MASKDELAY   2U
+#define OPCODE_ADDRESS_MASK(~3U)
+
+/* Sentinel */
+#define EMIT_EXIT()OPCODE_EXIT
+/* Opcode is in lower 2 bits of address, address is always 4-byte aligned */
+#define EMIT_MASKWRITE(addr, mask, val)OPCODE_MASKWRITE | addr, mask, 
val
+#define EMIT_MASKPOLL(addr, mask)  OPCODE_MASKPOLL | addr, mask
+#define EMIT_MASKDELAY(addr, mask) OPCODE_MASKDELAY | addr, mask
+
+/* Returns codes of ps7_init* */
+#define PS7_INIT_SUCCESS   (0)
+#define PS7_INIT_CORRUPT   (1)
+#define PS7_INIT_TIMEOUT   (2)
+#define PS7_POLL_FAILED_DDR_INIT   (3)
+#define PS7_POLL_FAILED_DMA(4)
+#define PS7_POLL_FAILED_PLL(5)
+
 /* Called by spl.c */
 int ps7_init(void);
 int ps7_post_config(void);
 
+/* Defined in ps7_init_common.c */
+int ps7_config(unsigned long *ps7_config_init);
+
 #endif /* _ASM_ARCH_PS7_INIT_GPL_H */
diff --git a/arch/arm/mach-zynq/ps7_spl_init.c 
b/arch/arm/mach-zynq/ps7_spl_init.c
index 6adf852578a6..180099577b04 100644
--- a/arch/arm/mach-zynq/ps7_spl_init.c
+++ b/arch/arm/mach-zynq/ps7_spl_init.c
@@ -1,5 +1,6 @@
 /*
  * (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -25,3 +26,111 @@ __weak int ps7_post_config(void)
 */
return 0;
 }
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL   0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC  0xF8F00218
+#define APU_FREQ  6
+
+#define PS7_MASK_POLL_TIME 1
+
+/* IO accessors. No memory barriers desired. */
+static inline void iowrite(unsigned long val, unsigned long addr)
+{
+   __raw_writel(val, addr);
+}
+
+static inline unsigned long ioread(unsigned long addr)
+{
+   return __raw_readl(addr);
+}
+
+/* start timer */
+static void perf_start_clock(void)
+{
+   iowrite((1 << 0) | /* Timer Enable */
+   (1 << 3) | /* Auto-increment */
+   (0 << 8), /* Pre-scale */
+   SCU_GLOBAL_TIMER_CONTROL);
+}
+
+/* Compute mask for given delay in miliseconds*/
+static int get_number_of_cycles_for_delay(unsigned int delay)
+{
+   return (APU_FREQ / (2 * 1000)) * delay;
+}
+
+/* stop timer */
+static void perf_disable_clock(void)
+{
+   iowrite(0, SCU_GLOBAL_TIMER_CONTROL);
+}
+
+/* stop timer and reset timer count regs */
+static void perf_reset_clock(void)
+{
+   perf_disable_clock();
+   iowrite(0, SCU_GLOBAL_TIMER_COUNT_L32);
+   iowrite(0, SCU_GLOBAL_TIMER_COUNT_U32);
+}
+
+static void perf_reset_and_start_timer(void)
+{
+   perf_reset_clock();
+   perf_start_clock();
+}
+
+int __weak ps7_config(unsigned long *ps7_config_init)
+{
+   unsigned long *ptr = ps7_config_init;
+   unsigned long opcode;
+   unsigned long addr;
+   unsigned long val;
+   unsigned long mask;
+   

[U-Boot] [PATCH v2 7/9] arm: zynq: Add ps7GetSiliconVersion() to ps7_spl_init

[Michal Simek]

Unfortunately camelcase is coming from ps7_init* format.

Signed-off-by: Michal Simek 
---

Changes in v2: None

 arch/arm/mach-zynq/include/mach/ps7_init_gpl.h | 6 ++
 arch/arm/mach-zynq/ps7_spl_init.c  | 6 ++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h 
b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
index c7c716e7f2c4..fa5d486afb0c 100644
--- a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
+++ b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
@@ -30,6 +30,10 @@
 #define PS7_POLL_FAILED_DMA(4)
 #define PS7_POLL_FAILED_PLL(5)
 
+#define PCW_SILICON_VERSION_1  0
+#define PCW_SILICON_VERSION_2  1
+#define PCW_SILICON_VERSION_3  2
+
 /* Called by spl.c */
 int ps7_init(void);
 int ps7_post_config(void);
@@ -37,4 +41,6 @@ int ps7_post_config(void);
 /* Defined in ps7_init_common.c */
 int ps7_config(unsigned long *ps7_config_init);
 
+unsigned long ps7GetSiliconVersion(void);
+
 #endif /* _ASM_ARCH_PS7_INIT_GPL_H */
diff --git a/arch/arm/mach-zynq/ps7_spl_init.c 
b/arch/arm/mach-zynq/ps7_spl_init.c
index 180099577b04..069827880d10 100644
--- a/arch/arm/mach-zynq/ps7_spl_init.c
+++ b/arch/arm/mach-zynq/ps7_spl_init.c
@@ -7,6 +7,7 @@
 
 #include 
 #include 
+#include 
 #include 
 
 __weak int ps7_init(void)
@@ -134,3 +135,8 @@ int __weak ps7_config(unsigned long *ps7_config_init)
ptr += numargs;
}
 }
+
+unsigned long __weak __maybe_unused ps7GetSiliconVersion(void)
+{
+   return zynq_get_silicon_version();
+}
-- 
1.9.1

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[U-Boot] [PATCH v2 9/9] arm: zynq: Convert all board to use arch ps7_init code

[Michal Simek]

Use generic implementation. It will also reduce config data size for
converted boards.

Signed-off-by: Michal Simek 
---

Changes in v2: None

 .../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c  | 120 +-
 .../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h  |  80 -
 board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c | 173 +---
 board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h | 116 --
 board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c| 177 +---
 board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h| 116 --
 board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c| 173 +---
 board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h| 116 --
 board/xilinx/zynq/zynq-zed/ps7_init_gpl.c  | 173 +---
 board/xilinx/zynq/zynq-zed/ps7_init_gpl.h  | 116 --
 board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c | 178 +
 board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h |  97 ---
 12 files changed, 6 insertions(+), 1629 deletions(-)
 delete mode 100644 board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h
 delete mode 100644 board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h
 delete mode 100644 board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h
 delete mode 100644 board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h
 delete mode 100644 board/xilinx/zynq/zynq-zed/ps7_init_gpl.h
 delete mode 100644 board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h

diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c 
b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
index 5aa3951b8017..3bd02f3c83ec 100644
--- a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
+++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
@@ -5,8 +5,7 @@
 * SPDX-License-Identifier: GPL-2.0+
  */
 
-#include "ps7_init_gpl.h"
-#include "asm/io.h"
+#include 
 
 unsigned long ps7_pll_init_data_3_0[] = {
EMIT_WRITE(0XF808, 0xDF0DU),
@@ -255,92 +254,11 @@ unsigned long ps7_post_config_3_0[] = {
EMIT_EXIT(),
 };
 
-
 unsigned long ps7_reset_apu_3_0[] = {
EMIT_MASKWRITE(0xF8000244, 0x0022U, 0x0022U),
EMIT_EXIT(),
 };
 
-#define PS7_MASK_POLL_TIME 1
-
-static inline void iowrite(unsigned long val, unsigned long addr)
-{
-   __raw_writel(val, addr);
-}
-
-static inline unsigned long ioread(unsigned long addr)
-{
-   return __raw_readl(addr);
-}
-
-int ps7_config(unsigned long *ps7_config_init)
-{
-   unsigned long *ptr = ps7_config_init;
-
-   unsigned long opcode;   /* current instruction .. */
-   unsigned long args[16]; /* no opcode has so many args ... */
-   int numargs;/* number of arguments of this instruction */
-   int j;  /* general purpose index */
-
-   unsigned long addr;
-   unsigned long val, mask;
-
-   int finish = -1;/* loop while this is negative ! */
-   int i = 0;  /* Timeout variable */
-
-   while (finish < 0) {
-   numargs = ptr[0] & 0xF;
-   opcode = ptr[0] >> 4;
-
-   for (j = 0; j < numargs; j++)
-   args[j] = ptr[j + 1];
-   ptr += numargs + 1;
-
-   switch (opcode) {
-   case OPCODE_EXIT:
-   finish = PS7_INIT_SUCCESS;
-   break;
-
-   case OPCODE_WRITE:
-   addr = args[0];
-   val = args[1];
-   iowrite(val, addr);
-   break;
-
-   case OPCODE_MASKWRITE:
-   addr = args[0];
-   mask = args[1];
-   val = args[2];
-   iowrite((val & mask) | (ioread(addr) & ~mask) , addr);
-   break;
-
-   case OPCODE_MASKPOLL:
-   addr = args[0];
-   mask = args[1];
-   i = 0;
-   while (!(ioread(addr) & mask)) {
-   if (i == PS7_MASK_POLL_TIME) {
-   finish = PS7_INIT_TIMEOUT;
-   break;
-   }
-   i++;
-   }
-   break;
-   case OPCODE_MASKDELAY:
-   addr = args[0];
-   mask = args[1];
-   int delay = get_number_of_cycles_for_delay(mask);
-   perf_reset_and_start_timer();
-   while (ioread(addr) < delay)
-   ;
-   break;
-   default:
-   finish = PS7_INIT_CORRUPT;
-   break;
-   }
-   }
-   return finish;
-}
 
 int 

[U-Boot] [PATCH v2 3/9] arm: zynq: Remove ps7_debug code

[Michal Simek]

SPL is not calling this code that's why it is dead code and can be
removed.

Signed-off-by: Michal Simek 
---

Changes in v2: None

 .../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c  |  10 --
 .../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h  |   1 -
 board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c | 112 
 board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h |   1 -
 board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c| 112 
 board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h|   1 -
 board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c| 112 
 board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h|   1 -
 board/xilinx/zynq/zynq-zed/ps7_init_gpl.c  | 112 
 board/xilinx/zynq/zynq-zed/ps7_init_gpl.h  |   1 -
 board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c | 114 -
 board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h |   1 -
 12 files changed, 578 deletions(-)

diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c 
b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
index 7ae04758b7d5..f2a757a5cfeb 100644
--- a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
+++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
@@ -255,12 +255,6 @@ unsigned long ps7_post_config_3_0[] = {
EMIT_EXIT(),
 };
 
-unsigned long ps7_debug_3_0[] = {
-   EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
-   EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
-   EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
-   EMIT_EXIT(),
-};
 
 unsigned long ps7_reset_apu_3_0[] = {
EMIT_MASKWRITE(0xF8000244, 0x0022U, 0x0022U),
@@ -353,10 +347,6 @@ int ps7_post_config(void)
return ps7_config(ps7_post_config_3_0);
 }
 
-int ps7_debug(void)
-{
-   return ps7_config(ps7_debug_3_0);
-}
 
 int ps7_reset_apu(void)
 {
diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h 
b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h
index 158c25f3ae9b..ca90bbc5 100644
--- a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h
+++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h
@@ -69,7 +69,6 @@ extern "C" {
 int ps7_config(unsigned long *);
 int ps7_init(void);
 int ps7_post_config(void);
-int ps7_debug(void);
 
 void perf_start_clock(void);
 void perf_disable_clock(void);
diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c 
b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
index eb290023a1eb..58c31b8a50cf 100644
--- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
@@ -4121,37 +4121,6 @@ unsigned long ps7_post_config_3_0[] = {
 //
 };
 
-unsigned long ps7_debug_3_0[] = {
-// START: top
-// .. START: CROSS TRIGGER CONFIGURATIONS
-// .. .. START: UNLOCKING CTI REGISTERS
-// .. .. KEY = 0XC5ACCE55
-// .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-// .. .. ==> MASK : 0xUVAL : 0xC5ACCE55U
-// .. ..
-EMIT_MASKWRITE(0XF8898FB0, 0xU ,0xC5ACCE55U),
-// .. .. KEY = 0XC5ACCE55
-// .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-// .. .. ==> MASK : 0xUVAL : 0xC5ACCE55U
-// .. ..
-EMIT_MASKWRITE(0XF8899FB0, 0xU ,0xC5ACCE55U),
-// .. .. KEY = 0XC5ACCE55
-// .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-// .. .. ==> MASK : 0xUVAL : 0xC5ACCE55U
-// .. ..
-EMIT_MASKWRITE(0XF8809FB0, 0xU ,0xC5ACCE55U),
-// .. .. FINISH: UNLOCKING CTI REGISTERS
-// .. .. START: ENABLING CTI MODULES AND CHANNELS
-// .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-// .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-// .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
-// .. FINISH: CROSS TRIGGER CONFIGURATIONS
-// FINISH: top
-//
-EMIT_EXIT(),
-
-//
-};
 
 unsigned long ps7_pll_init_data_2_0[] = {
 // START: top
@@ -8419,37 +8388,6 @@ unsigned long ps7_post_config_2_0[] = {
 //
 };
 
-unsigned long ps7_debug_2_0[] = {
-// START: top
-// .. START: CROSS TRIGGER CONFIGURATIONS
-// .. .. START: UNLOCKING CTI REGISTERS
-// .. .. KEY = 0XC5ACCE55
-// .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
-// .. .. ==> MASK : 0xUVAL : 0xC5ACCE55U
-// .. ..
-EMIT_MASKWRITE(0XF8898FB0, 0xU ,0xC5ACCE55U),
-// .. .. KEY = 0XC5ACCE55
-// .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
-// .. .. ==> MASK : 0xUVAL : 0xC5ACCE55U
-// .. ..
-EMIT_MASKWRITE(0XF8899FB0, 0xU ,0xC5ACCE55U),
-// .. .. KEY = 0XC5ACCE55
-// .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
-// .. .. ==> MASK : 0xUVAL : 0xC5ACCE55U
-// .. ..
-EMIT_MASKWRITE(0XF8809FB0, 0xU ,0xC5ACCE55U),
-// .. .. FINISH: UNLOCKING CTI REGISTERS
-// .. .. START: ENABLING CTI MODULES AND CHANNELS
-// .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
-// .. .. START: MAPPING 

[U-Boot] [PATCH v2 2/9] arm: zynq: Enable debug uart on zc706

[Michal Simek]

Enable debug uart by default.

Signed-off-by: Michal Simek 
---

Changes in v2: None

 configs/zynq_zc706_defconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index bc6fe3a30695..52999debc115 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x400
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
+CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
@@ -51,6 +52,10 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=5000
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ZYNQ_SERIAL=y
 CONFIG_ZYNQ_QSPI=y
 CONFIG_USB=y
-- 
1.9.1

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[U-Boot] [PATCH v2 4/9] arm: zynq: Move ps7_* to separate file

[Michal Simek]

Extract ps7_* from spl code to prepare for extension.
And also return value.

Signed-off-by: Michal Simek 
---

Changes in v2: None

 arch/arm/mach-zynq/Makefile|  2 +-
 arch/arm/mach-zynq/include/mach/ps7_init_gpl.h | 14 +
 arch/arm/mach-zynq/include/mach/sys_proto.h|  4 
 arch/arm/mach-zynq/ps7_spl_init.c  | 27 ++
 arch/arm/mach-zynq/spl.c   | 18 +
 5 files changed, 43 insertions(+), 22 deletions(-)
 create mode 100644 arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
 create mode 100644 arch/arm/mach-zynq/ps7_spl_init.c

diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
index bf29b4d396d3..e3f0117da563 100644
--- a/arch/arm/mach-zynq/Makefile
+++ b/arch/arm/mach-zynq/Makefile
@@ -15,4 +15,4 @@ obj-y += slcr.o
 obj-y  += clk.o
 obj-y  += lowlevel_init.o
 AFLAGS_lowlevel_init.o := -mfpu=neon
-obj-$(CONFIG_SPL_BUILD)+= spl.o
+obj-$(CONFIG_SPL_BUILD)+= spl.o ps7_spl_init.o
diff --git a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h 
b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
new file mode 100644
index ..6e30108b23f4
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
@@ -0,0 +1,14 @@
+/*
+ * (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_PS7_INIT_GPL_H
+#define _ASM_ARCH_PS7_INIT_GPL_H
+
+/* Called by spl.c */
+int ps7_init(void);
+int ps7_post_config(void);
+
+#endif /* _ASM_ARCH_PS7_INIT_GPL_H */
diff --git a/arch/arm/mach-zynq/include/mach/sys_proto.h 
b/arch/arm/mach-zynq/include/mach/sys_proto.h
index 0ef688309da3..af61352dd110 100644
--- a/arch/arm/mach-zynq/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynq/include/mach/sys_proto.h
@@ -20,8 +20,4 @@ extern unsigned int zynq_get_silicon_version(void);
 
 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
 
-/* Driver extern functions */
-extern void ps7_init(void);
-int ps7_post_config(void);
-
 #endif /* _SYS_PROTO_H_ */
diff --git a/arch/arm/mach-zynq/ps7_spl_init.c 
b/arch/arm/mach-zynq/ps7_spl_init.c
new file mode 100644
index ..6adf852578a6
--- /dev/null
+++ b/arch/arm/mach-zynq/ps7_spl_init.c
@@ -0,0 +1,27 @@
+/*
+ * (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+__weak int ps7_init(void)
+{
+   /*
+* This function is overridden by the one in
+* board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
+*/
+   return 0;
+}
+
+__weak int ps7_post_config(void)
+{
+   /*
+* This function is overridden by the one in
+* board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
+*/
+   return 0;
+}
diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c
index e8added15567..1672fa05c26a 100644
--- a/arch/arm/mach-zynq/spl.c
+++ b/arch/arm/mach-zynq/spl.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -83,23 +84,6 @@ int spl_start_uboot(void)
 }
 #endif
 
-__weak void ps7_init(void)
-{
-   /*
-* This function is overridden by the one in
-* board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
-*/
-}
-
-__weak int ps7_post_config(void)
-{
-   /*
-* This function is overridden by the one in
-* board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
-*/
-   return 0;
-}
-
 void spl_board_prepare_for_boot(void)
 {
ps7_post_config();
-- 
1.9.1

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[U-Boot] [PATCH v2 1/9] arm: zynq: Add missing ps7_post_config declaration

[Michal Simek]

Add missing declaration to header.

Warning log:
arch/arm/mach-zynq/spl.c:94:12: warning: symbol 'ps7_post_config' was
not declared. Should it be static?

Signed-off-by: Michal Simek 
---

Changes in v2: None

 arch/arm/mach-zynq/include/mach/sys_proto.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-zynq/include/mach/sys_proto.h 
b/arch/arm/mach-zynq/include/mach/sys_proto.h
index 67238e7fbcfd..0ef688309da3 100644
--- a/arch/arm/mach-zynq/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynq/include/mach/sys_proto.h
@@ -22,5 +22,6 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
 
 /* Driver extern functions */
 extern void ps7_init(void);
+int ps7_post_config(void);
 
 #endif /* _SYS_PROTO_H_ */
-- 
1.9.1

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[U-Boot] [PATCH v2 0/9] arm: zynq: ps7* consolidation

[Michal Simek]

Hi,

this series is trying to cleanup ps7_init* file that we don't need to
have the same copy of the same functions in different locations.
This work is done based on solution from Topic.nl for miami boards
where format was changed a little bit to save one word in config data
segment.
At the same time older method of simply copying files to particular
folder is still working.
Please test this in your board to make sure I didn't break anything.
I have tested it on zybo/zc702/zc706.

Thanks,
Michal

Changes in v2:
- Fix indentation by using tabs instead of spaces
- Add own opcode for write operation
- Change commit message (was Convert EMIT_WRITE to EMIT_MASKWRITE) -
  requested by Mike

Michal Simek (9):
  arm: zynq: Add missing ps7_post_config declaration
  arm: zynq: Enable debug uart on zc706
  arm: zynq: Remove ps7_debug code
  arm: zynq: Move ps7_* to separate file
  arm: zynq: Get rid of ps7_reset_apu() for syzygy board
  arm: zynq: Move common ps7_init* initialization to arch code
  arm: zynq: Add ps7GetSiliconVersion() to ps7_spl_init
  arm: zynq: Add support for EMIT_WRITE operation
  arm: zynq: Convert all board to use arch ps7_init code

 arch/arm/mach-zynq/Makefile|   2 +-
 arch/arm/mach-zynq/include/mach/ps7_init_gpl.h |  48 
 arch/arm/mach-zynq/include/mach/sys_proto.h|   3 -
 .../arm/mach-zynq/ps7_spl_init.c   |  37 ++-
 arch/arm/mach-zynq/spl.c   |  18 +-
 .../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c  | 138 +-
 .../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h  |  81 --
 board/topic/zynq/Makefile  |   2 +-
 board/topic/zynq/ps7_init_gpl.h|  34 ---
 board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c   |   2 +-
 .../topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c |   2 +-
 .../topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c |   2 +-
 board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c | 285 +---
 board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h | 117 -
 board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c| 289 +---
 board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h| 117 -
 board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c| 285 +---
 board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h| 117 -
 board/xilinx/zynq/zynq-zed/ps7_init_gpl.c  | 285 +---
 board/xilinx/zynq/zynq-zed/ps7_init_gpl.h  | 117 -
 board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c | 292 +
 board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h |  98 ---
 configs/zynq_zc706_defconfig   |   5 +
 23 files changed, 100 insertions(+), 2276 deletions(-)
 create mode 100644 arch/arm/mach-zynq/include/mach/ps7_init_gpl.h
 rename board/topic/zynq/ps7_init_common.c => arch/arm/mach-zynq/ps7_spl_init.c 
(76%)
 delete mode 100644 board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h
 delete mode 100644 board/topic/zynq/ps7_init_gpl.h
 delete mode 100644 board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h
 delete mode 100644 board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h
 delete mode 100644 board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h
 delete mode 100644 board/xilinx/zynq/zynq-zed/ps7_init_gpl.h
 delete mode 100644 board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h

-- 
1.9.1

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[U-Boot] [PATCH] env: Remove CONFIG_ENV_AES support

[Tom Rini]

This support has been deprecated since v2017.09 due to security issues.
We now remove this support.

Signed-off-by: Tom Rini 
---
 env/Kconfig |  8 -
 env/common.c| 61 --
 include/environment.h   | 12 +---
 tools/env/Makefile  |  2 +-
 tools/env/aes.c |  1 -
 tools/env/fw_env.c  | 79 -
 tools/env/fw_env.h  |  5 
 tools/env/fw_env_main.c | 14 -
 8 files changed, 2 insertions(+), 180 deletions(-)
 delete mode 100644 tools/env/aes.c

diff --git a/env/Kconfig b/env/Kconfig
index 8c9d800f485f..2477bf85309b 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -360,14 +360,6 @@ config ENV_IS_IN_UBI
 
 endchoice
 
-config ENV_AES
-   bool "AES-128 encryption for stored environment (DEPRECATED)"
-   help
- Enable this to have the on-device stored environment be encrypted
- with AES-128.  The implementation here however has security
- complications and is not recommended for use.  Please see
- CVE-2017-3225 and CVE-2017-3226 for more details.
-
 config ENV_FAT_INTERFACE
string "Name of the block device for the environment"
depends on ENV_IS_IN_FAT
diff --git a/env/common.c b/env/common.c
index 70715bb6e756..8167ea299264 100644
--- a/env/common.c
+++ b/env/common.c
@@ -103,52 +103,6 @@ int set_default_vars(int nvars, char * const vars[])
H_NOCLEAR | H_INTERACTIVE, 0, nvars, vars);
 }
 
-#ifdef CONFIG_ENV_AES
-#include 
-/**
- * env_aes_cbc_get_key() - Get AES-128-CBC key for the environment
- *
- * This function shall return 16-byte array containing AES-128 key used
- * to encrypt and decrypt the environment. This function must be overridden
- * by the implementer as otherwise the environment encryption will not
- * work.
- */
-__weak uint8_t *env_aes_cbc_get_key(void)
-{
-   return NULL;
-}
-
-static int env_aes_cbc_crypt(env_t *env, const int enc)
-{
-   unsigned char *data = env->data;
-   uint8_t *key;
-   uint8_t key_exp[AES_EXPAND_KEY_LENGTH];
-   uint32_t aes_blocks;
-
-   key = env_aes_cbc_get_key();
-   if (!key)
-   return -EINVAL;
-
-   /* First we expand the key. */
-   aes_expand_key(key, key_exp);
-
-   /* Calculate the number of AES blocks to encrypt. */
-   aes_blocks = ENV_SIZE / AES_KEY_LENGTH;
-
-   if (enc)
-   aes_cbc_encrypt_blocks(key_exp, data, data, aes_blocks);
-   else
-   aes_cbc_decrypt_blocks(key_exp, data, data, aes_blocks);
-
-   return 0;
-}
-#else
-static inline int env_aes_cbc_crypt(env_t *env, const int enc)
-{
-   return 0;
-}
-#endif
-
 /*
  * Check if CRC is valid and (if yes) import the environment.
  * Note that "buf" may or may not be aligned.
@@ -156,7 +110,6 @@ static inline int env_aes_cbc_crypt(env_t *env, const int 
enc)
 int env_import(const char *buf, int check)
 {
env_t *ep = (env_t *)buf;
-   int ret;
 
if (check) {
uint32_t crc;
@@ -169,14 +122,6 @@ int env_import(const char *buf, int check)
}
}
 
-   /* Decrypt the env if desired. */
-   ret = env_aes_cbc_crypt(ep, 0);
-   if (ret) {
-   pr_err("Failed to decrypt env!\n");
-   set_default_env("!import failed");
-   return ret;
-   }
-
if (himport_r(_htab, (char *)ep->data, ENV_SIZE, '\0', 0, 0,
0, NULL)) {
gd->flags |= GD_FLG_ENV_READY;
@@ -242,7 +187,6 @@ int env_export(env_t *env_out)
 {
char *res;
ssize_t len;
-   int ret;
 
res = (char *)env_out->data;
len = hexport_r(_htab, '\0', 0, , ENV_SIZE, 0, NULL);
@@ -251,11 +195,6 @@ int env_export(env_t *env_out)
return 1;
}
 
-   /* Encrypt the env if desired. */
-   ret = env_aes_cbc_crypt(env_out, 1);
-   if (ret)
-   return ret;
-
env_out->crc = crc32(0, env_out->data, ENV_SIZE);
 
 #ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
diff --git a/include/environment.h b/include/environment.h
index 7b9821638960..d29f82cb5d6f 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -143,12 +143,7 @@ extern unsigned long nand_env_oob_offset;
 # define ENV_HEADER_SIZE   (sizeof(uint32_t))
 #endif
 
-#ifdef CONFIG_ENV_AES
-/* Make sure the payload is multiple of AES block size */
-#define ENV_SIZE ((CONFIG_ENV_SIZE - ENV_HEADER_SIZE) & ~(16 - 1))
-#else
 #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE)
-#endif
 
 typedef struct environment_s {
uint32_tcrc;/* CRC32 over data bytes*/
@@ -156,12 +151,7 @@ typedef struct environment_s {
unsigned char   flags;  /* active/obsolete flags*/
 #endif
unsigned char   data[ENV_SIZE]; /* Environment data */
-} env_t
-#ifdef CONFIG_ENV_AES
-/* Make sure the env 

[U-Boot] [PATCH V3] armv8: ls1012a: Modify Kernel and Environment offset

[Bhaskar Upadhaya]

Kernel is now located at 0x100 instead of 0xa0
and envirorment variables are located at 3MB offset instead of
2MB in Flash

Signed-off-by: Bhaskar Upadhaya 
---
Changes for V3: Updated Commit message

 include/configs/ls1012a_common.h | 4 ++--
 include/configs/ls1012afrdm.h| 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index d2fa50a..57cae94 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -65,7 +65,7 @@
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_ENV_SIZE0x4  /* 256KB */
-#define CONFIG_ENV_OFFSET  0x20/* 2MB */
+#define CONFIG_ENV_OFFSET  0x30/* 3MB */
 #define CONFIG_ENV_SECT_SIZE   0x4
 #endif
 
@@ -94,7 +94,7 @@
"kernel_addr=0x10\0"\
"fdt_high=0x\0" \
"initrd_high=0x\0"  \
-   "kernel_start=0xa0\0"   \
+   "kernel_start=0x100\0"  \
"kernel_load=0xa000\0"  \
"kernel_size=0x280\0"   \
 
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
index efb4c00..5b4bf28 100644
--- a/include/configs/ls1012afrdm.h
+++ b/include/configs/ls1012afrdm.h
@@ -27,7 +27,7 @@
"kernel_addr=0x10\0"\
"fdt_high=0x\0" \
"initrd_high=0x\0"  \
-   "kernel_start=0xa0\0"   \
+   "kernel_start=0x100\0"  \
"kernel_load=0x9600\0"  \
"kernel_size=0x280\0"
 
-- 
1.9.1

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[U-Boot] [PATCH v5 0/3] Support for TI bandgap temperature sensor

[Faiz Abbas]

Adding support for TI bandgap temperature sensor.
Also add dt support for bandgap sensor in spl.

v5:
Fixed terminator brackets at the end of ti_bandgap_match

v4:
 1. Added configs enabled by default in dra7xx and am57xx SOCs
 2. Split config enabling in a separate commit

v3:
Missed adding Reviewed-by in v2.

Faiz Abbas (3):
  thermal: ti-bandgap: Add support for temperature sensor
  ARM: dts: OMAP5+: Add support for bandgap sensor in SPL
  ARM: dra7: Kconfig: Add thermal configs for dra7xx and am57xx

 arch/arm/dts/omap5-u-boot.dtsi |   4 +
 arch/arm/mach-omap2/omap5/Kconfig  |   6 +
 common/spl/Kconfig |   8 +
 .../thermal/ti_soc_thermal.txt |  35 
 drivers/Makefile   |   1 +
 drivers/thermal/Kconfig|   6 +
 drivers/thermal/Makefile   |   1 +
 drivers/thermal/ti-bandgap.c   | 198 +
 8 files changed, 259 insertions(+)
 create mode 100644 doc/device-tree-bindings/thermal/ti_soc_thermal.txt
 create mode 100644 drivers/thermal/ti-bandgap.c

-- 
2.7.4

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[U-Boot] [PATCH v5 3/3] ARM: dra7: Kconfig: Add thermal configs for dra7xx and am57xx

[Faiz Abbas]

Configure thermal configs to remain set by default for dra7xx and am57xx
devices.

Signed-off-by: Faiz Abbas 
---
 arch/arm/mach-omap2/omap5/Kconfig | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/mach-omap2/omap5/Kconfig 
b/arch/arm/mach-omap2/omap5/Kconfig
index 8f58235..8c1730a 100644
--- a/arch/arm/mach-omap2/omap5/Kconfig
+++ b/arch/arm/mach-omap2/omap5/Kconfig
@@ -30,6 +30,9 @@ config TARGET_DRA7XX_EVM
imply PMIC_LP87565
imply DM_REGULATOR
imply DM_REGULATOR_LP87565
+   imply SPL_THERMAL
+   imply DM_THERMAL
+   imply TI_DRA7_THERMAL
 
 config TARGET_AM57XX_EVM
bool "AM57XX"
@@ -37,6 +40,9 @@ config TARGET_AM57XX_EVM
select DRA7XX
select TI_I2C_BOARD_DETECT
imply SCSI
+   imply SPL_THERMAL
+   imply DM_THERMAL
+   imply TI_DRA7_THERMAL
 
 endchoice
 
-- 
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[U-Boot] [PATCH v5 1/3] thermal: ti-bandgap: Add support for temperature sensor

[Faiz Abbas]

The dra7xx series of SOCs contain a temperature sensor and an
associated analog-to-digital converter (ADC) which produces
an output which is proportional to the SOC temperature.
Add support for this temperature sensor.

Signed-off-by: Faiz Abbas 
Reviewed-by: Simon Glass 
---

v5:
Added terminator brackets ({}) to ti_bandgap_match[]

v3:
Added Reviewed-by comment

v2:
 1. Removed extra elements from ti_bandgap
 2. Changed base address to ulong
 3. Changed to udev to dev to maintain consistency
 4. minor format changes

 common/spl/Kconfig |   8 +
 .../thermal/ti_soc_thermal.txt |  35 
 drivers/Makefile   |   1 +
 drivers/thermal/Kconfig|   6 +
 drivers/thermal/Makefile   |   1 +
 drivers/thermal/ti-bandgap.c   | 198 +
 6 files changed, 249 insertions(+)
 create mode 100644 doc/device-tree-bindings/thermal/ti_soc_thermal.txt
 create mode 100644 drivers/thermal/ti-bandgap.c

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 0bd8370..0bf3ee3 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -604,6 +604,14 @@ config SPL_SPI_SUPPORT
  enable SPI drivers that are needed for other purposes also, such
  as a SPI PMIC.
 
+config SPL_THERMAL
+   bool "Driver support for thermal devices"
+   help
+ Enable support for temperature-sensing devices. Some SoCs have on-chip
+ temperature sensors to permit warnings, speed throttling or even
+ automatic power-off when the temperature gets too high or low. Other
+ devices may be discrete but connected on a suitable bus.
+
 config SPL_USB_HOST_SUPPORT
bool "Support USB host drivers"
help
diff --git a/doc/device-tree-bindings/thermal/ti_soc_thermal.txt 
b/doc/device-tree-bindings/thermal/ti_soc_thermal.txt
new file mode 100644
index 000..b4e88c2
--- /dev/null
+++ b/doc/device-tree-bindings/thermal/ti_soc_thermal.txt
@@ -0,0 +1,35 @@
+* Texas Instrument dra7xx SCM bandgap bindings
+
+In the System Control Module, SoC supplies a voltage reference
+and a temperature sensor feature that are gathered in the band
+gap voltage and temperature sensor (VBGAPTS) module. The band
+gap provides current and voltage reference for its internal
+circuits and other analog IP blocks. The analog-to-digital
+converter (ADC) produces an output value that is proportional
+to the silicon temperature.
+
+Required properties:
+- compatible : Should be:
+  - "ti,dra752-bandgap"
+- interrupts : this entry should indicate which interrupt line
+the talert signal is routed to;
+- regs : this is specific to each bandgap version, because
+the mapping may change from soc to soc, apart from depending
+on available features.
+
+Optional:
+- gpios : this entry should be used to inform which GPIO
+line the tshut signal is routed to. The informed GPIO will
+be treated as an IRQ;
+
+Example:
+bandgap {
+   reg = <0x4a0021e0 0xc
+   0x4a00232c 0xc
+   0x4a002380 0x2c
+   0x4a0023C0 0x3c
+   0x4a002564 0x8
+   0x4a002574 0x50>;
+   compatible = "ti,dra752-bandgap";
+   interrupts = <0 126 4>; /* talert */
+};
diff --git a/drivers/Makefile b/drivers/Makefile
index dab5c18..e6062a5 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_SPL_SATA_SUPPORT) += ata/ scsi/
 obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
 obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
 obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/
+obj-$(CONFIG_SPL_THERMAL) += thermal/
 
 endif
 endif
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 886f5fa..a71b9be 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -17,4 +17,10 @@ config IMX_THERMAL
   cpufreq is used as the cooling device to throttle CPUs when the
   passive trip is crossed.
 
+config TI_DRA7_THERMAL
+bool "Temperature sensor driver for TI dra7xx SOCs"
+help
+Enable thermal support for for the Texas Instruments DRA752 SoC family.
+The driver supports reading CPU temperature.
+
 endif # if DM_THERMAL
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index d768f5e..f6271a5 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -7,3 +7,4 @@
 
 obj-$(CONFIG_DM_THERMAL) += thermal-uclass.o
 obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
+obj-$(CONFIG_TI_DRA7_THERMAL) += ti-bandgap.o
diff --git a/drivers/thermal/ti-bandgap.c b/drivers/thermal/ti-bandgap.c
new file mode 100644
index 000..b490391
--- /dev/null
+++ b/drivers/thermal/ti-bandgap.c
@@ -0,0 +1,198 @@
+/*
+ * TI Bandgap temperature sensor driver
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the 

[U-Boot] [PATCH v5 2/3] ARM: dts: OMAP5+: Add support for bandgap sensor in SPL

[Faiz Abbas]

Mark bandgap node as uboot,dm-spl so that it can be accessed in spl

Signed-off-by: Faiz Abbas 
Reviewed-by: Simon Glass 
Reviewed-by: Tom Rini 
---

v3:
Added Reviewed-by comment.

 arch/arm/dts/omap5-u-boot.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/omap5-u-boot.dtsi b/arch/arm/dts/omap5-u-boot.dtsi
index fdaa692..bf2684c 100644
--- a/arch/arm/dts/omap5-u-boot.dtsi
+++ b/arch/arm/dts/omap5-u-boot.dtsi
@@ -18,6 +18,10 @@
ocp2scp@4a09 {
compatible = "ti,omap-ocp2scp", "simple-bus";
};
+
+   bandgap@4a0021e0 {
+   u-boot,dm-spl;
+   };
};
 };
 
-- 
2.7.4

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Re: [U-Boot] [PATCH] gpt: add part-uuid and part-num subcommands

[Lukasz Majewski]

Hi Andrey,

> Hi Lukasz,
> 
> On Thu, Nov 9, 2017 at 2:28 PM, Lukasz Majewski
>  wrote:
> > On Thu, 9 Nov 2017 07:34:44 -0800
> > Andrey Yurovsky  wrote:
> >  
> >> On Thu, Nov 9, 2017 at 1:55 AM, Lukasz Majewski
> >>  wrote:  
> >> > Hi Andrey,
> >> >  
> >> >> Hi Otavio,
> >> >>
> >> >> On Wed, Nov 8, 2017 at 2:47 AM, Otavio Salvador
> >> >>  wrote:  
> >> >> > On Tue, Nov 7, 2017 at 10:43 PM, your name
> >> >> >  wrote:  
> >> >> >> From: Andrey Yurovsky 
> >> >> >>
> >> >> >> It is useful to be able to retrieve a partition UUID or
> >> >> >> number given the partition label, for instance some systems
> >> >> >> use the partition label to indicate the purpose of the
> >> >> >> partition (such as "rootfs0" being the 0th root file system
> >> >> >> in an A/B image scheme).
> >> >> >>
> >> >> >> Add "gpt part-uuid" to retrieve the partition UUID for a
> >> >> >> given label and "gpt part-num" to retrieve the partition
> >> >> >> number for a given label along with some documentation.
> >> >> >>
> >> >> >> Signed-off-by: Andrey Yurovsky   
> >> >> >
> >> >> > Why not use the 'part' cmd? it provides it.  
> >> >>
> >> >> Sorry, I missed the part cmd, it doesn't seem to be documented
> >> >> in doc/ and it's unclear what  means there.  
> >> >
> >> > If I may ask - Andrey, if you are now on this "topic" - would you
> >> > dare to add some ./doc entry for 'part' command?  
> >>
> >> Yes, I will do that.  
> >
> > Thanks :-)  
> 
> On further investigation I am not sure that it's possible to extend
> the part command to retrieve UUIDs by label because of the design of
> the partition type drivers. Here is how I understand it to work:
> 1. the "part" command uses part_get_info() and in turn gets a
> partition driver and can call print() there (which is how EFI/GPT
> disks are printed with "part list"). The right information (including
> label) is printed but it's not tied to the caller in any way.

Maybe you can set some env variable with proper data?

For example, please refer to ./cmd/part.c do_part_start() function.

Example call from envs (include/configs/display5.h):
"part start mmc ${mmcdev} ${kernel_part} lba_start; " \

> 2. "part uuid"  blk_get_device_part_str() which in turn can get
> information but referenced by partition number (and only partition
> number, due to how part_get_info() works). There's nothing at the
> 'part' layer tying a label to a number though so one would already
> need to know the number, which is the problem I'm trying to solve.
> 
> This layering keeps partitioning generalized and decoupled from the
> underlying partition "driver" but there's no concept of a label in the
> "driver" API. I'm not sure if it's reasonable to extend it since
> part_get_info() and similar really don't have a way to map labels at
> this layer so perhaps extending the GPT-specific command is the only
> reasonable approach?
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Re: [U-Boot] [PATCH 1/1] Makefile: add coccicheck target

[Masahiro Yamada]

Hi.


2017-11-11 3:54 GMT+09:00 Heinrich Schuchardt :
> Coccinelle is a program for static code analysis.
> For details on Coccinelle see
>
> http://coccinelle.lip6.fr/
>
> Add scripts/coccicheck and Documentation/dev-tools/coccinelle.rst
> copied from Linux kernel v4.14-rc8.
>
> The coccicheck script executes the tests *.cocci in
> directory scripts/coccinelle by calling spatch.
>
> In Makefile add a coccicheck target. You can use it with
>
> make coccicheck MODE=
>
> where mode in patch, report, context, org.
>
> Signed-off-by: Heinrich Schuchardt 

You can run "make coccicheck" without the .config file.
So, you need to add coccinelle to no-dot-config-targets.


Refer to the following code in Linux.

no-dot-config-targets := clean mrproper distclean \
 cscope gtags TAGS tags help% %docs check% coccicheck \
 $(version_h) headers_% archheaders archscripts \
 kernelversion %src-pkg






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Re: [U-Boot] [PATCH 12/13] binman: Add documentation for the symbol feature

[Lukasz Majewski]

Hi Simon,

> Add this feature to the README.
> 
> Signed-off-by: Simon Glass 
> ---
> 
>  tools/binman/README | 32 +++-
>  1 file changed, 31 insertions(+), 1 deletion(-)
> 
> diff --git a/tools/binman/README b/tools/binman/README
> index 4ef76c8f089..08c3e56bdef 100644
> --- a/tools/binman/README
> +++ b/tools/binman/README
> @@ -439,6 +439,8 @@ contents of an entry in some way. For example, it
> would be possible to create an entry containing a hash of the
> contents of some other entries. At this stage the position and size
> of entries should not be adjusted. 
> +6. WriteEntryInfo()
> +
>  7. BuildImage() - builds the image and writes it to a file. This is
> the final step.
>  
> @@ -471,6 +473,33 @@ the 'warning' line in scripts/Makefile.lib to
> see what it has found: # u_boot_dtsi_options_debug =
> $(u_boot_dtsi_options_raw) 
>  
> +Access to binman entry positions at run time
> +
> +
> +Binman assembles images and determines where each entry is placed in
> the image. +This information may be useful to U-Boot at run time. For
> example, in SPL it +is useful to be able to find the location of
> U-Boot so that it can be executed +when SPL is finished.
> +
> +Binman allows you to declare symbols in the SPL image which are
> filled in +with their correct values during the build. For example:
> +
> +binman_sym_declare(ulong, u_boot_any, pos);
> +
> +declares a ulong value which will be assigned to the position of any
> U-Boot +image (u-boot.bin, u-boot.img, u-boot-nodtb.bin) that is
> present in the image. +You can access this value with something like:
> +
> +ulong u_boot_pos = binman_sym(ulong, u_boot_any, pos);
> +
> +Thus u_boot_pos will be set to the position of U-Boot in memory,
> assuming that +the whole image has been loaded, or is available in
> flash. You can then jump to +that address to start U-Boot.
> +
> +At present this feature is only supported in SPL. In principle it is
> possible +to fill in such symbols in U-Boot proper, as well.
> +
> +
>  Code coverage
>  -
>  
> @@ -543,7 +572,8 @@ To do
>  
>  Some ideas:
>  - Fill out the device tree to include the final position and size of
> each
> -  entry (since the input file may not always specify these)
> +  entry (since the input file may not always specify these). See also
> +  'Access to binman entry positions at run time' above
>  - Use of-platdata to make the information available to code that is
> unable to use device tree (such as a very small SPL image)
>  - Write an image map to a text file

Great feature - thanks Simon.

Reviewed-by: Lukasz Majewski 


Best regards,

Lukasz Majewski

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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de


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Re: [U-Boot] ethernet: ROM MAC address vs env variable MAC address

[Mike Looijmans]

On 13-11-17 20:49, Wolfgang Denk wrote:

Dear Prabhakar,

In message 

 you wrote:


Why ROM MAC address getting overwritten by environment env MAC address.


Because in U-Boot we give the user the freedom to do what he
needs/wants to do.  Usually the environment value gets initialized
from the value in the ROM, so there is no difference anyway. But if
the user wants a specific setting, he can change it.


MAC address is something unique and assigned to a particular device. So one 
should never change its MAC address.


U-Boot follows good old UNIX style here:

"UNIX was not designed to stop you from doing stupid things,  because
that would also stop you from doing clever things."   - Doug Gwyn


Many board manufacturers "assign" this unique MAC address by printing it on a 
sticker and sticking that on the board somewhere. It's pretty darn hard to 
read a printed sticker in software, so we have to revert to solutions that 
actually work.


In the "clever things" department, protocols like IPv6 merrily broadcast your 
MAC address across gateways on the big bad internet, so if you value your 
privacy, you'll appreciate the possibility to change your MAC address at will.




Kind regards,

Mike Looijmans
System Expert

TOPIC Products
Materiaalweg 4, NL-5681 RJ Best
Postbus 440, NL-5680 AK Best
Telefoon: +31 (0) 499 33 69 79
E-mail: mike.looijm...@topicproducts.com
Website: www.topicproducts.com

Please consider the environment before printing this e-mail



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Re: [U-Boot] [PATCH] mach-stm32: Fix mpu region's attribute for STM32H7

[Patrice CHOTARD]

Hi Vikas

On 11/14/2017 03:16 AM, Vikas MANOCHA wrote:
> Hi Patrice,
> 
>> -Original Message-
>> From: Patrice CHOTARD
>> Sent: Monday, November 13, 2017 8:26 AM
>> To: u-boot@lists.denx.de; albert.u.b...@aribaud.net; s...@chromium.org; 
>> Vikas MANOCHA 
>> Cc: Patrice CHOTARD ; Patrick DELAUNAY 
>> ; Christophe KERELLO
>> 
>> Subject: [PATCH] mach-stm32: Fix mpu region's attribute for STM32H7
>>
>> From: Patrice Chotard 
>>
>> The SDRAM region was setup with the wrong attributes.
>> It must be set to :
>>_ XN_EN (Execution of an instruction fetched from this region permitted)
>>_ O_I_WB_RD_WR_ALLOC (Outer and inner write-back, write and read allocate)
>>
> 
> H7 mpu configuration seems same as F7, can we have one config for F7 & H7.

Between F7 and H7, there is one difference regarding the F7's region 3 
which is not needed on H7 because FMC/QSPI registers are located inside 
H7's region 2.

Just one question about F7's region 1, why is it only 512MB and not 1GB 
long, to include ITCM and DTCM area ? (see Embedded SRAM chapter of 
RM0385 Reference manual)

Nevertheless, i just notice that for H7, i can remove region 1 which 
overlaps region 0 with exactly the same attribute.

Thanks

> 
>> This fixes hard fault when trying to load and execute kernel linux in this 
>> area.
>>
>> Signed-off-by: Patrice Chotard 
> 
> In any case,
> Reviewed-by: Vikas Manocha 
> 
> Cheers,
> Vikas
> 
>> ---
>>   arch/arm/mach-stm32/stm32h7/soc.c | 9 ++---
>>   1 file changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/mach-stm32/stm32h7/soc.c 
>> b/arch/arm/mach-stm32/stm32h7/soc.c
>> index 692dbcc..e0d3f11 100644
>> --- a/arch/arm/mach-stm32/stm32h7/soc.c
>> +++ b/arch/arm/mach-stm32/stm32h7/soc.c
>> @@ -30,9 +30,12 @@ int arch_cpu_init(void)
>>  { 0x, REGION_0, XN_DIS, PRIV_RW_USR_RW,
>>  O_I_WB_RD_WR_ALLOC, REGION_4GB },
>>
>> -/* Code area, executable & strongly ordered */
>> -{ 0xD000, REGION_1, XN_EN, PRIV_RW_USR_RW,
>> -STRONG_ORDER, REGION_8MB },
>> +/*
>> + * Code area, executable, Outer and inner write-back,
>> + * no write allocate
>> + */
>> +{ 0xD000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
>> +O_I_WB_RD_WR_ALLOC, REGION_32MB },
>>
>>  /* Device area in all H7 : Not executable */
>>  { 0x4000, REGION_2, XN_EN, PRIV_RW_USR_RW,
>> --
>> 1.9.1
> 
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Re: [U-Boot] [PATCH] mmc: sd_sdhi: add support for 32-bit data buffer

[Marek Vasut]

On 11/13/2017 09:51 PM, Chris Brandt wrote:
> Some controllers have a 32-bit data buffer register and do not allow
> any other access besides 32-bit read/write.
> 
> Signed-off-by: Chris Brandt 

Can you switch to uniphier-sd instead ? I switched Gen3 away from SH
SDHI and the uniphier driver is so much better.

> ---
>  arch/arm/mach-rmobile/include/mach/sh_sdhi.h |  1 +
>  drivers/mmc/sh_sdhi.c| 21 -
>  2 files changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-rmobile/include/mach/sh_sdhi.h 
> b/arch/arm/mach-rmobile/include/mach/sh_sdhi.h
> index 00a135faa1..f2dbd851a5 100644
> --- a/arch/arm/mach-rmobile/include/mach/sh_sdhi.h
> +++ b/arch/arm/mach-rmobile/include/mach/sh_sdhi.h
> @@ -164,6 +164,7 @@
>  /* For quirk */
>  #define SH_SDHI_QUIRK_16BIT_BUF  BIT(0)
>  #define SH_SDHI_QUIRK_64BIT_BUF  BIT(1)
> +#define SH_SDHI_QUIRK_32BIT_BUF  BIT(2)
>  
>  int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks);
>  
> diff --git a/drivers/mmc/sh_sdhi.c b/drivers/mmc/sh_sdhi.c
> index eef061abb2..37879e6c56 100644
> --- a/drivers/mmc/sh_sdhi.c
> +++ b/drivers/mmc/sh_sdhi.c
> @@ -273,6 +273,7 @@ static int sh_sdhi_single_read(struct sh_sdhi_host *host, 
> struct mmc_data *data)
>   unsigned short blocksize, i;
>   unsigned short *p = (unsigned short *)data->dest;
>   u64 *q = (u64 *)data->dest;
> + u32 *d = (u32 *)data->dest;
>  
>   if ((unsigned long)p & 0x0001) {
>   debug(DRIVER_NAME": %s: The data pointer is unaligned.",
> @@ -296,6 +297,9 @@ static int sh_sdhi_single_read(struct sh_sdhi_host *host, 
> struct mmc_data *data)
>   if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
>   for (i = 0; i < blocksize / 8; i++)
>   *q++ = sh_sdhi_readq(host, SDHI_BUF0);
> + else if (host->quirks & SH_SDHI_QUIRK_32BIT_BUF)
> + for (i = 0; i < blocksize / 4; i++)
> + *d++ = sh_sdhi_readq(host, SDHI_BUF0);
>   else
>   for (i = 0; i < blocksize / 2; i++)
>   *p++ = sh_sdhi_readw(host, SDHI_BUF0);
> @@ -314,6 +318,7 @@ static int sh_sdhi_multi_read(struct sh_sdhi_host *host, 
> struct mmc_data *data)
>   unsigned short blocksize, i, sec;
>   unsigned short *p = (unsigned short *)data->dest;
>   u64 *q = (u64 *)data->dest;
> + u32 *d = (u32 *)data->dest;
>  
>   if ((unsigned long)p & 0x0001) {
>   debug(DRIVER_NAME": %s: The data pointer is unaligned.",
> @@ -339,6 +344,9 @@ static int sh_sdhi_multi_read(struct sh_sdhi_host *host, 
> struct mmc_data *data)
>   if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
>   for (i = 0; i < blocksize / 8; i++)
>   *q++ = sh_sdhi_readq(host, SDHI_BUF0);
> + else if (host->quirks & SH_SDHI_QUIRK_32BIT_BUF)
> + for (i = 0; i < blocksize / 4; i++)
> + *d++ = sh_sdhi_readq(host, SDHI_BUF0);
>   else
>   for (i = 0; i < blocksize / 2; i++)
>   *p++ = sh_sdhi_readw(host, SDHI_BUF0);
> @@ -354,6 +362,7 @@ static int sh_sdhi_single_write(struct sh_sdhi_host *host,
>   unsigned short blocksize, i;
>   const unsigned short *p = (const unsigned short *)data->src;
>   const u64 *q = (const u64 *)data->src;
> + const u32 *d = (const u32 *)data->src;
>  
>   if ((unsigned long)p & 0x0001) {
>   debug(DRIVER_NAME": %s: The data pointer is unaligned.",
> @@ -381,6 +390,9 @@ static int sh_sdhi_single_write(struct sh_sdhi_host *host,
>   if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
>   for (i = 0; i < blocksize / 8; i++)
>   sh_sdhi_writeq(host, SDHI_BUF0, *q++);
> + else if (host->quirks & SH_SDHI_QUIRK_32BIT_BUF)
> + for (i = 0; i < blocksize / 4; i++)
> + sh_sdhi_writeq(host, SDHI_BUF0, *d++);
>   else
>   for (i = 0; i < blocksize / 2; i++)
>   sh_sdhi_writew(host, SDHI_BUF0, *p++);
> @@ -399,6 +411,7 @@ static int sh_sdhi_multi_write(struct sh_sdhi_host *host, 
> struct mmc_data *data)
>   unsigned short i, sec, blocksize;
>   const unsigned short *p = (const unsigned short *)data->src;
>   const u64 *q = (const u64 *)data->src;
> + const u32 *d = (const u32 *)data->src;
>  
>   debug("%s: blocks = %d, blocksize = %d\n",
> __func__, data->blocks, data->blocksize);
> @@ -418,6 +431,9 @@ static int sh_sdhi_multi_write(struct sh_sdhi_host *host, 
> struct mmc_data *data)
>   if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
>   for (i = 0; i < blocksize / 8; i++)
>   sh_sdhi_writeq(host, SDHI_BUF0, *q++);
> + else if (host->quirks & SH_SDHI_QUIRK_32BIT_BUF)
> +