[U-Boot] [PATCH 3/3] fit: Add standalone image type handling

[Marek Vasut]

Just add IH_TYPE_STANDALONE to fit_get_image_type_property().

Signed-off-by: Marek Vasut 
Cc: Pantelis Antoniou 
Cc: Simon Glass 
---
 common/image-fit.c | 2 ++
 include/image.h| 1 +
 2 files changed, 3 insertions(+)

diff --git a/common/image-fit.c b/common/image-fit.c
index 98cb039376..32e343122e 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -1728,6 +1728,8 @@ static const char *fit_get_image_type_property(int type)
return FIT_LOADABLE_PROP;
case IH_TYPE_FPGA:
return FIT_FPGA_PROP;
+   case IH_TYPE_STANDALONE:
+   return FIT_STANDALONE_PROP;
}
 
return "unknown";
diff --git a/include/image.h b/include/image.h
index df701e3470..6e5750333a 100644
--- a/include/image.h
+++ b/include/image.h
@@ -922,6 +922,7 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong 
*size);
 #define FIT_SETUP_PROP "setup"
 #define FIT_FPGA_PROP  "fpga"
 #define FIT_FIRMWARE_PROP  "firmware"
+#define FIT_STANDALONE_PROP"standalone"
 
 #define FIT_MAX_HASH_LEN   HASH_MAX_DIGEST_SIZE
 
-- 
2.16.2

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[U-Boot] [PATCH] spl: Add full fitImage support

[Marek Vasut]

Add support for loading U-Boot and optionally FDT from a fitImage
in SPL by using the full fitImage support from U-Boot. While we do
have limited SPL loading support in SPL with a small footprint, it
is missing a lot of important features, like checking signatures.
This support has all the fitImage features, while the footprint is
obviously larger.

Signed-off-by: Marek Vasut 
Cc: Pantelis Antoniou 
Cc: Simon Glass 
---
V2: - Drop blank line below spl_load_fit_image()
- Explicitly enable image verification if available
---
 Kconfig  | 11 +
 common/spl/spl.c | 74 
 2 files changed, 85 insertions(+)

diff --git a/Kconfig b/Kconfig
index 7d9e971f0e..5a82c95dd8 100644
--- a/Kconfig
+++ b/Kconfig
@@ -328,6 +328,17 @@ config SPL_LOAD_FIT
  particular it can handle selecting from multiple device tree
  and passing the correct one to U-Boot.
 
+config SPL_LOAD_FIT_FULL
+   bool "Enable SPL loading U-Boot as a FIT"
+   select SPL_FIT
+   help
+ Normally with the SPL framework a legacy image is generated as part
+ of the build. This contains U-Boot along with information as to
+ where it should be loaded. This option instead enables generation
+ of a FIT (Flat Image Tree) which provides more flexibility. In
+ particular it can handle selecting from multiple device tree
+ and passing the correct one to U-Boot.
+
 config SPL_FIT_IMAGE_POST_PROCESS
bool "Enable post-processing of FIT artifacts after loading by the SPL"
depends on SPL_LOAD_FIT
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 079780c6df..7dace07543 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -150,9 +150,83 @@ void spl_set_header_raw_uboot(struct spl_image_info 
*spl_image)
spl_image->name = "U-Boot";
 }
 
+#ifdef CONFIG_SPL_LOAD_FIT_FULL
+/* Parse and load full fitImage in SPL */
+static int spl_load_fit_image(struct spl_image_info *spl_image,
+ const struct image_header *header)
+{
+   bootm_headers_t images;
+   const char *fit_uname_config = NULL;
+   const char *fit_uname_fdt = FIT_FDT_PROP;
+   const char *uname;
+   ulong fw_data = 0, dt_data = 0, img_data = 0;
+   ulong fw_len = 0, dt_len = 0, img_len = 0;
+   int idx, conf_noffset;
+   int ret;
+
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+   images.verify = 1;
+#endif
+   ret = fit_image_load(, (ulong)header,
+NULL, _uname_config,
+IH_ARCH_DEFAULT, IH_TYPE_STANDALONE, -1,
+FIT_LOAD_REQUIRED, _data, _len);
+   if (ret < 0)
+   return ret;
+
+   spl_image->size = fw_len;
+   spl_image->entry_point = fw_data;
+   spl_image->load_addr = fw_data;
+   spl_image->os = IH_OS_U_BOOT;
+   spl_image->name = "U-Boot";
+
+   debug("spl: payload image: %.*s load addr: 0x%lx size: %d\n",
+   (int)sizeof(spl_image->name), spl_image->name,
+   spl_image->load_addr, spl_image->size);
+
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+   images.verify = 1;
+#endif
+   fit_image_load(, (ulong)header,
+  _uname_fdt, _uname_config,
+  IH_ARCH_DEFAULT, IH_TYPE_FLATDT, -1,
+  FIT_LOAD_OPTIONAL, _data, _len);
+
+   conf_noffset = fit_conf_get_node((const void *)header,
+fit_uname_config);
+   if (conf_noffset <= 0)
+   return 0;
+
+   for (idx = 0;
+uname = fdt_stringlist_get((const void *)header, conf_noffset,
+   FIT_LOADABLE_PROP, idx,
+   NULL), uname;
+idx++)
+   {
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+   images.verify = 1;
+#endif
+   ret = fit_image_load(, (ulong)header,
+, _uname_config,
+IH_ARCH_DEFAULT, IH_TYPE_LOADABLE, -1,
+FIT_LOAD_OPTIONAL_NON_ZERO,
+_data, _len);
+   if (ret < 0)
+   return ret;
+   }
+
+   return 0;
+}
+#endif
+
 int spl_parse_image_header(struct spl_image_info *spl_image,
   const struct image_header *header)
 {
+#ifdef CONFIG_SPL_LOAD_FIT_FULL
+   int ret = spl_load_fit_image(spl_image, header);
+   if (!ret)
+   return ret;
+#endif
if (image_get_magic(header) == IH_MAGIC) {
 #ifdef CONFIG_SPL_LEGACY_IMAGE_SUPPORT
u32 header_size = sizeof(struct image_header);
-- 
2.16.2

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[U-Boot] [PATCH 2/3] fit: Add empty fit_print_contents() and fit_image_print()

[Marek Vasut]

These functions may be needed in SPL, so add empty variants of them
if CONFIG_SPL_FIT_PRINT is disabled.

Signed-off-by: Marek Vasut 
Cc: Pantelis Antoniou 
Cc: Simon Glass 
---
 common/image-fit.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/common/image-fit.c b/common/image-fit.c
index 578db5cc84..98cb039376 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -459,7 +459,9 @@ void fit_image_print(const void *fit, int image_noffset, 
const char *p)
}
}
 }
-
+#else
+void fit_print_contents(const void *fit) { }
+void fit_image_print(const void *fit, int image_noffset, const char *p) { }
 #endif /* !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_FIT_PRINT) */
 
 /**
-- 
2.16.2

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[U-Boot] [PATCH 1/3] fit: Fix CONFIG_FIT_SPL_PRINT

[Marek Vasut]

Rename CONFIG_FIT_SPL_PRINT to CONFIG_SPL_FIT_PRINT and add Kconfig
entry for it.

Signed-off-by: Marek Vasut 
Cc: Pantelis Antoniou 
Cc: Simon Glass 
---
 Kconfig| 6 ++
 README | 2 +-
 common/image-fit.c | 4 ++--
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/Kconfig b/Kconfig
index 9fd9de1772..7d9e971f0e 100644
--- a/Kconfig
+++ b/Kconfig
@@ -305,6 +305,12 @@ config SPL_FIT
depends on SPL
select SPL_OF_LIBFDT
 
+config SPL_FIT_PRINT
+   bool "Support FIT printing within SPL"
+   depends on SPL_FIT
+   help
+ Support printing the content of the fitImage in a verbose manner in 
SPL.
+
 config SPL_FIT_SIGNATURE
bool "Enable signature verification of FIT firmware within SPL"
depends on SPL_DM
diff --git a/README b/README
index a62aee1619..672049495b 100644
--- a/README
+++ b/README
@@ -2695,7 +2695,7 @@ FIT uImage format:
use an arch-specific makefile fragment instead, for
example if more than one image needs to be produced.
 
-   CONFIG_FIT_SPL_PRINT
+   CONFIG_SPL_FIT_PRINT
Printing information about a FIT image adds quite a bit of
code to SPL. So this is normally disabled in SPL. Use this
option to re-enable it. This will affect the output of the
diff --git a/common/image-fit.c b/common/image-fit.c
index 5b93dceae1..578db5cc84 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -142,7 +142,7 @@ int fit_get_subimage_count(const void *fit, int 
images_noffset)
return count;
 }
 
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_FIT_SPL_PRINT)
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_FIT_PRINT)
 /**
  * fit_print_contents - prints out the contents of the FIT format image
  * @fit: pointer to the FIT format image header
@@ -460,7 +460,7 @@ void fit_image_print(const void *fit, int image_noffset, 
const char *p)
}
 }
 
-#endif /* !defined(CONFIG_SPL_BUILD) || defined(CONFIG_FIT_SPL_PRINT) */
+#endif /* !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_FIT_PRINT) */
 
 /**
  * fit_get_desc - get node description property
-- 
2.16.2

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Re: [U-Boot] [PATCH v2 1/6] kconfig: re-sync with Linux 4.17-rc4

[Eugeniu Rosca]

Hi Petr,

On Sat, May 12, 2018 at 09:31:48PM +0200, Petr Vorel wrote:
> Hi Eugeniu,
> 
> > Hello Petr,
> 
> > On Sat, May 12, 2018 at 08:25:56PM +0200, Petr Vorel wrote:
> 
> > > When applied all 6 patches, I got several errors (see bellow).
> > > I tested in on 2 distros (Debian unstable and openSUSE Tumbleweed).
> > > The code I applied is here, did I make error when applying patches?
> > > https://github.com/pevik/u-boot/tree/eugeniu/kconfig.v2
> 
> > I checked your branch and got some interesting conclusions.
> > Here is the diff between my and your version of commit ("kconfig:
> > re-sync with Linux 4.17-rc4"):
> 
> > $ git diff  
> >  scripts/kconfig/tests/auto_submenu/expected_stdout| 14 
> > +++---
> >  scripts/kconfig/tests/choice/oldask0_expected_stdout  | 14 
> > +++---
> >  scripts/kconfig/tests/choice/oldask1_expected_stdout  | 12 ++--
> >  scripts/kconfig/tests/new_choice_with_dep/expected_stdout |  4 ++--
> >  4 files changed, 22 insertions(+), 22 deletions(-)
> 
> > Here is the same diff ignoring whitespace:
> 
> > $ git diff -w  
> >  scripts/kconfig/tests/auto_submenu/expected_stdout| 0
> >  scripts/kconfig/tests/choice/oldask0_expected_stdout  | 0
> >  scripts/kconfig/tests/choice/oldask1_expected_stdout  | 0
> >  scripts/kconfig/tests/new_choice_with_dep/expected_stdout | 0
> >  4 files changed, 0 insertions(+), 0 deletions(-)
> 
> > So, it seems like all the trailing white-space from above files
> > disappeared on your branch, after applying the patches from the
> > email client (who did this?...).

I hope I wasn't too harsh here. By "who" I meant the exact component or
script in your workflow which dropped the trailing spaces. By knowing
it, we could also improve our own workflows, which is a positive of
going through this issue IMHO.

> OK, my fault, I'm sorry. Applying first patch as 'git am --whitespace=warn 
> 1.mbox' fixes
> that => make testconfig works.

No worries.

> Yes I applied patches with mutt (I usually use pwclient, but somehow I didn't 
> find your v2
> in patchwork [1], nor even in ML [2]. Have I overlook something.
> 
> [1] https://patchwork.ozlabs.org/project/uboot/list/
> [2] https://lists.denx.de/pipermail/u-boot/2018-May/date.html

I think I'm subscribed to U-boot mailing list with only one of my email
addresses. The messages arriving from another one are delayed a bit
since they have to be approved by moderators.

Thanks,
Eugeniu.
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[U-Boot] [PATCH 5/6] ARM: rmobile: Drop old R8A7794 PFC tables

[Marek Vasut]

All the boards use new modern PFC framework, the old PFC tables
are no longer used, so remove them.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 arch/arm/mach-rmobile/Makefile|2 +-
 arch/arm/mach-rmobile/include/mach/gpio.h |3 -
 arch/arm/mach-rmobile/include/mach/r8a7794-gpio.h |  276 
 arch/arm/mach-rmobile/pfc-r8a7794.c   | 1650 -
 4 files changed, 1 insertion(+), 1930 deletions(-)
 delete mode 100644 arch/arm/mach-rmobile/include/mach/r8a7794-gpio.h
 delete mode 100644 arch/arm/mach-rmobile/pfc-r8a7794.c

diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index 6c09e376f9..5b5462219b 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -13,7 +13,7 @@ obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o
 obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o
 obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o
 obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o
-obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
+obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o
 obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
 obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
 obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
diff --git a/arch/arm/mach-rmobile/include/mach/gpio.h 
b/arch/arm/mach-rmobile/include/mach/gpio.h
index 83a57cb8ca..6b5e4ed4eb 100644
--- a/arch/arm/mach-rmobile/include/mach/gpio.h
+++ b/arch/arm/mach-rmobile/include/mach/gpio.h
@@ -7,9 +7,6 @@ void sh73a0_pinmux_init(void);
 #elif defined(CONFIG_R8A7740)
 #include "r8a7740-gpio.h"
 void r8a7740_pinmux_init(void);
-#elif defined(CONFIG_R8A7794)
-#include "r8a7794-gpio.h"
-void r8a7794_pinmux_init(void);
 #endif
 
 #endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7794-gpio.h 
b/arch/arm/mach-rmobile/include/mach/r8a7794-gpio.h
deleted file mode 100644
index 8a002a8918..00
--- a/arch/arm/mach-rmobile/include/mach/r8a7794-gpio.h
+++ /dev/null
@@ -1,276 +0,0 @@
-#ifndef __ASM_R8A7794_H__
-#define __ASM_R8A7794_H__
-
-/* Pin Function Controller:
- * GPIO_FN_xx - GPIO used to select pin function
- * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
- */
-enum {
-   GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
-   GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
-   GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
-   GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
-   GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
-   GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
-   GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
-   GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
-
-   GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
-   GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
-   GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
-   GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
-   GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
-   GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
-   GPIO_GP_1_24, GPIO_GP_1_25,
-
-   GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
-   GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
-   GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
-   GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
-   GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
-   GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
-   GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
-   GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
-
-   GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
-   GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
-   GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
-   GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
-   GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
-   GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
-   GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
-   GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
-
-   GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
-   GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
-   GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
-   GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
-   GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
-   GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
-   GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
-   GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
-
-   GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
-   GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
-   GPIO_GP_5_8, GPIO_GP_5_9, 

[U-Boot] [PATCH 6/6] ARM: rmobile: Unify Gen2 Makefile entry

[Marek Vasut]

Drop per-SoC Makefile entries and replace them with one unified entry
now that the PFC tables are gone. Shuffle the Makefile around a bit
to make it more organized.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 arch/arm/mach-rmobile/Makefile | 10 +++---
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index 5b5462219b..1f26adaca9 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -8,12 +8,8 @@ obj-y += emac.o
 
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
 obj-$(CONFIG_GLOBAL_TIMER) += timer.o
+obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
+obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
 obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
-obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o
-obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o
-obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o
-obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o
-obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o
+obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
 obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
-obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
-obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
-- 
2.16.2

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[U-Boot] [PATCH 4/6] ARM: rmobile: Drop old R8A7793 PFC tables

[Marek Vasut]

All the boards use new modern PFC framework, the old PFC tables
are no longer used, so remove them.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 arch/arm/mach-rmobile/Makefile|2 +-
 arch/arm/mach-rmobile/include/mach/gpio.h |3 -
 arch/arm/mach-rmobile/include/mach/r8a7793-gpio.h |  438 -
 arch/arm/mach-rmobile/pfc-r8a7793.c   | 1925 -
 4 files changed, 1 insertion(+), 2367 deletions(-)
 delete mode 100644 arch/arm/mach-rmobile/include/mach/r8a7793-gpio.h
 delete mode 100644 arch/arm/mach-rmobile/pfc-r8a7793.c

diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index b54533abae..6c09e376f9 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o 
pfc-r8a7740.o
 obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o
 obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o
 obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o
-obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o
+obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o
 obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
 obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
 obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
diff --git a/arch/arm/mach-rmobile/include/mach/gpio.h 
b/arch/arm/mach-rmobile/include/mach/gpio.h
index 532b728721..83a57cb8ca 100644
--- a/arch/arm/mach-rmobile/include/mach/gpio.h
+++ b/arch/arm/mach-rmobile/include/mach/gpio.h
@@ -7,9 +7,6 @@ void sh73a0_pinmux_init(void);
 #elif defined(CONFIG_R8A7740)
 #include "r8a7740-gpio.h"
 void r8a7740_pinmux_init(void);
-#elif defined(CONFIG_R8A7793)
-#include "r8a7793-gpio.h"
-void r8a7793_pinmux_init(void);
 #elif defined(CONFIG_R8A7794)
 #include "r8a7794-gpio.h"
 void r8a7794_pinmux_init(void);
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7793-gpio.h 
b/arch/arm/mach-rmobile/include/mach/r8a7793-gpio.h
deleted file mode 100644
index f9a29fc144..00
--- a/arch/arm/mach-rmobile/include/mach/r8a7793-gpio.h
+++ /dev/null
@@ -1,438 +0,0 @@
-#ifndef __ASM_R8A7793_H__
-#define __ASM_R8A7793_H__
-
-/* Pin Function Controller:
- * GPIO_FN_xx - GPIO used to select pin function
- * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
- */
-enum {
-   GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
-   GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
-   GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
-   GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
-   GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
-   GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
-   GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
-   GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
-
-   GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
-   GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
-   GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
-   GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
-   GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
-   GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
-   GPIO_GP_1_24, GPIO_GP_1_25,
-
-   GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
-   GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
-   GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
-   GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
-   GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
-   GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
-   GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
-   GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
-
-   GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
-   GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
-   GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
-   GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
-   GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
-   GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
-   GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
-   GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
-
-   GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
-   GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
-   GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
-   GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
-   GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
-   GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
-   GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
-   GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
-
-   GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
-   

[U-Boot] [PATCH 3/6] ARM: rmobile: Drop old R8A7792 PFC tables

[Marek Vasut]

All the boards use new modern PFC framework, the old PFC tables
are no longer used, so remove them.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 arch/arm/mach-rmobile/Makefile|2 +-
 arch/arm/mach-rmobile/include/mach/gpio.h |3 -
 arch/arm/mach-rmobile/include/mach/r8a7792-gpio.h |  220 --
 arch/arm/mach-rmobile/pfc-r8a7792.c   | 2301 -
 4 files changed, 1 insertion(+), 2525 deletions(-)
 delete mode 100644 arch/arm/mach-rmobile/include/mach/r8a7792-gpio.h
 delete mode 100644 arch/arm/mach-rmobile/pfc-r8a7792.c

diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index d8d7a79d29..b54533abae 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -11,7 +11,7 @@ obj-$(CONFIG_GLOBAL_TIMER) += timer.o
 obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
 obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o
 obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o
-obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o
+obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o
 obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o
 obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
 obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
diff --git a/arch/arm/mach-rmobile/include/mach/gpio.h 
b/arch/arm/mach-rmobile/include/mach/gpio.h
index 4e727313e2..532b728721 100644
--- a/arch/arm/mach-rmobile/include/mach/gpio.h
+++ b/arch/arm/mach-rmobile/include/mach/gpio.h
@@ -7,9 +7,6 @@ void sh73a0_pinmux_init(void);
 #elif defined(CONFIG_R8A7740)
 #include "r8a7740-gpio.h"
 void r8a7740_pinmux_init(void);
-#elif defined(CONFIG_R8A7792)
-#include "r8a7792-gpio.h"
-void r8a7792_pinmux_init(void);
 #elif defined(CONFIG_R8A7793)
 #include "r8a7793-gpio.h"
 void r8a7793_pinmux_init(void);
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7792-gpio.h 
b/arch/arm/mach-rmobile/include/mach/r8a7792-gpio.h
deleted file mode 100644
index 86931c3fee..00
--- a/arch/arm/mach-rmobile/include/mach/r8a7792-gpio.h
+++ /dev/null
@@ -1,220 +0,0 @@
-#ifndef __ASM_R8A7792_GPIO_H__
-#define __ASM_R8A7792_GPIO_H__
-
-/* Pin Function Controller:
- * GPIO_FN_xx - GPIO used to select pin function
- * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
- */
-enum {
-   GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
-   GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
-   GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
-   GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
-   GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
-   GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
-   GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
-   GPIO_GP_0_28,
-
-   GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
-   GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
-   GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
-   GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
-   GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
-   GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22,
-
-   GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
-   GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
-   GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
-   GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
-   GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
-   GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
-   GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
-   GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
-
-   GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
-   GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
-   GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
-   GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
-   GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
-   GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
-   GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
-   GPIO_GP_3_28,
-
-   GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
-   GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
-   GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
-   GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
-   GPIO_GP_4_16,
-
-   GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
-   GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
-   GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
-   GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
-   GPIO_GP_5_16,
-
-   GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
-   GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
-   GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, 

[U-Boot] [PATCH 2/6] ARM: rmobile: Drop old R8A7791 PFC tables

[Marek Vasut]

All the boards use new modern PFC framework, the old PFC tables
are no longer used, so remove them.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 arch/arm/mach-rmobile/Makefile|2 +-
 arch/arm/mach-rmobile/include/mach/gpio.h |3 -
 arch/arm/mach-rmobile/include/mach/r8a7791-gpio.h |  438 
 arch/arm/mach-rmobile/pfc-r8a7791.c   | 1116 -
 4 files changed, 1 insertion(+), 1558 deletions(-)
 delete mode 100644 arch/arm/mach-rmobile/include/mach/r8a7791-gpio.h
 delete mode 100644 arch/arm/mach-rmobile/pfc-r8a7791.c

diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index e1b97e662a..d8d7a79d29 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -10,7 +10,7 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
 obj-$(CONFIG_GLOBAL_TIMER) += timer.o
 obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
 obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o
-obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
+obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o
 obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o
 obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o
 obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
diff --git a/arch/arm/mach-rmobile/include/mach/gpio.h 
b/arch/arm/mach-rmobile/include/mach/gpio.h
index 5f37a1f8e6..4e727313e2 100644
--- a/arch/arm/mach-rmobile/include/mach/gpio.h
+++ b/arch/arm/mach-rmobile/include/mach/gpio.h
@@ -7,9 +7,6 @@ void sh73a0_pinmux_init(void);
 #elif defined(CONFIG_R8A7740)
 #include "r8a7740-gpio.h"
 void r8a7740_pinmux_init(void);
-#elif defined(CONFIG_R8A7791)
-#include "r8a7791-gpio.h"
-void r8a7791_pinmux_init(void);
 #elif defined(CONFIG_R8A7792)
 #include "r8a7792-gpio.h"
 void r8a7792_pinmux_init(void);
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7791-gpio.h 
b/arch/arm/mach-rmobile/include/mach/r8a7791-gpio.h
deleted file mode 100644
index 42e82597e7..00
--- a/arch/arm/mach-rmobile/include/mach/r8a7791-gpio.h
+++ /dev/null
@@ -1,438 +0,0 @@
-#ifndef __ASM_R8A7791_GPIO_H__
-#define __ASM_R8A7791_GPIO_H__
-
-/* Pin Function Controller:
- * GPIO_FN_xx - GPIO used to select pin function
- * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
- */
-enum {
-   GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
-   GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
-   GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
-   GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
-   GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
-   GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
-   GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
-   GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
-
-   GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
-   GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
-   GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
-   GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
-   GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
-   GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
-   GPIO_GP_1_24, GPIO_GP_1_25,
-
-   GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
-   GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
-   GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
-   GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
-   GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
-   GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
-   GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
-   GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
-
-   GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
-   GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
-   GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
-   GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
-   GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
-   GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
-   GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
-   GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
-
-   GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
-   GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
-   GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
-   GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
-   GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
-   GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
-   GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
-   GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
-
-   GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
-   GPIO_GP_5_4, GPIO_GP_5_5, 

[U-Boot] [PATCH 1/6] ARM: rmobile: Drop old R8A7790 PFC tables

[Marek Vasut]

All the boards use new modern PFC framework, the old PFC tables
are no longer used, so remove them.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 arch/arm/mach-rmobile/Makefile|2 +-
 arch/arm/mach-rmobile/include/mach/gpio.h |3 -
 arch/arm/mach-rmobile/include/mach/r8a7790-gpio.h |  387 -
 arch/arm/mach-rmobile/pfc-r8a7790.c   | 1813 -
 4 files changed, 1 insertion(+), 2204 deletions(-)
 delete mode 100644 arch/arm/mach-rmobile/include/mach/r8a7790-gpio.h
 delete mode 100644 arch/arm/mach-rmobile/pfc-r8a7790.c

diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index 51453a88dc..e1b97e662a 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -9,7 +9,7 @@ obj-y += emac.o
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
 obj-$(CONFIG_GLOBAL_TIMER) += timer.o
 obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
-obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o
+obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o
 obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
 obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o
 obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o
diff --git a/arch/arm/mach-rmobile/include/mach/gpio.h 
b/arch/arm/mach-rmobile/include/mach/gpio.h
index 448d189e92..5f37a1f8e6 100644
--- a/arch/arm/mach-rmobile/include/mach/gpio.h
+++ b/arch/arm/mach-rmobile/include/mach/gpio.h
@@ -7,9 +7,6 @@ void sh73a0_pinmux_init(void);
 #elif defined(CONFIG_R8A7740)
 #include "r8a7740-gpio.h"
 void r8a7740_pinmux_init(void);
-#elif defined(CONFIG_R8A7790)
-#include "r8a7790-gpio.h"
-void r8a7790_pinmux_init(void);
 #elif defined(CONFIG_R8A7791)
 #include "r8a7791-gpio.h"
 void r8a7791_pinmux_init(void);
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7790-gpio.h 
b/arch/arm/mach-rmobile/include/mach/r8a7790-gpio.h
deleted file mode 100644
index 74b5f1df59..00
--- a/arch/arm/mach-rmobile/include/mach/r8a7790-gpio.h
+++ /dev/null
@@ -1,387 +0,0 @@
-#ifndef __ASM_R8A7790_GPIO_H__
-#define __ASM_R8A7790_GPIO_H__
-
-/* Pin Function Controller:
- * GPIO_FN_xx - GPIO used to select pin function
- * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
- */
-enum {
-   GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
-   GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
-   GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
-   GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
-   GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
-   GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
-   GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
-   GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
-
-   GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
-   GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
-   GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
-   GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
-   GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
-   GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
-   GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
-   GPIO_GP_1_28, GPIO_GP_1_29,
-
-   GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
-   GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
-   GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
-   GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
-   GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
-   GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
-   GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
-   GPIO_GP_2_28, GPIO_GP_2_29,
-
-   GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
-   GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
-   GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
-   GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
-   GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
-   GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
-   GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
-   GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
-
-   GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
-   GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
-   GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
-   GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
-   GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
-   GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
-   GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
-   GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
-
-   GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
-   GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, 

[U-Boot] [PATCH] ARM: rmobile: Update V2H Blanche

[Marek Vasut]

The V2H Blanche port was broken since some time. This patch updates
the V2H Blanche port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 arch/arm/dts/r8a7792-blanche-u-boot.dts |   4 +
 arch/arm/mach-rmobile/Kconfig.32|   1 +
 board/renesas/blanche/Makefile  |   2 +-
 board/renesas/blanche/blanche.c | 633 +---
 configs/blanche_defconfig   |  42 ++-
 include/configs/blanche.h   |  30 +-
 6 files changed, 302 insertions(+), 410 deletions(-)

diff --git a/arch/arm/dts/r8a7792-blanche-u-boot.dts 
b/arch/arm/dts/r8a7792-blanche-u-boot.dts
index 8eb263eb5d..3555663d64 100644
--- a/arch/arm/dts/r8a7792-blanche-u-boot.dts
+++ b/arch/arm/dts/r8a7792-blanche-u-boot.dts
@@ -7,3 +7,7 @@
 
 #include "r8a7792-blanche.dts"
 #include "r8a7792-u-boot.dtsi"
+
+ {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32
index 1ceb329f1f..c0b5b2457c 100644
--- a/arch/arm/mach-rmobile/Kconfig.32
+++ b/arch/arm/mach-rmobile/Kconfig.32
@@ -41,6 +41,7 @@ config TARGET_BLANCHE
bool "Blanche board"
select DM
select DM_SERIAL
+   select USE_TINY_PRINTF
 
 config TARGET_GOSE
bool "Gose board"
diff --git a/board/renesas/blanche/Makefile b/board/renesas/blanche/Makefile
index bdbfb291ec..21986af472 100644
--- a/board/renesas/blanche/Makefile
+++ b/board/renesas/blanche/Makefile
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 
-obj-y  := blanche.o qos.o ../rcar-common/common.o
+obj-y  := blanche.o qos.o
diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c
index fb1c93973a..7d48d0faf9 100644
--- a/board/renesas/blanche/blanche.c
+++ b/board/renesas/blanche/blanche.c
@@ -7,114 +7,40 @@
  */
 
 #include 
-#include 
-#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
 #include 
 #include 
 #include 
-#include 
-#include 
-#include 
+#include 
 #include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
+#include 
 #include 
-#include 
 #include 
+#include 
 #include "qos.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct pin_db {
-   u32 addr;   /* register address */
-   u32 mask;   /* mask value */
-   u32 val;/* setting value */
-};
-
-#definePMMR0xE606
-#defineGPSR0   0xE6060004
-#defineGPSR1   0xE6060008
-#defineGPSR4   0xE6060014
-#defineGPSR5   0xE6060018
-#defineGPSR6   0xE606001C
-#defineGPSR7   0xE6060020
-#defineGPSR8   0xE6060024
-#defineGPSR9   0xE6060028
-#defineGPSR10  0xE606002C
-#defineGPSR11  0xE6060030
-#defineIPSR6   0xE6060058
-#definePUPR2   0xE6060108
-#definePUPR3   0xE606010C
-#definePUPR4   0xE6060110
-#definePUPR5   0xE6060114
-#definePUPR7   0xE606011C
-#definePUPR9   0xE6060124
-#definePUPR10  0xE6060128
-#definePUPR11  0xE606012C
-
 #defineCPG_PLL1CR  0xE6150028
 #defineCPG_PLL3CR  0xE61500DC
 
-#defineSetREG(x) \
-   writel((readl((x)->addr) & ~((x)->mask)) | ((x)->val), (x)->addr)
-
-#defineSetGuardREG(x)  \
-{ \
-   u32 val; \
-   val = (readl((x)->addr) & ~((x)->mask)) | ((x)->val); \
-   writel(~val, PMMR); \
-   writel(val, (x)->addr); \
-}
-
-struct pin_db  pin_guard[] = {
-   { GPSR0,0x, 0x0BFF },
-   { GPSR1,0x, 0x002F },
-   { GPSR4,0x, 0x0FFF },
-   { GPSR5,0x, 0x00010FFF },
-   { GPSR6,0x, 0x00010FFF },
-   { GPSR7,0x, 0x00010FFF },
-   { GPSR8,0x, 0x00010FFF },
-   { GPSR9,0x, 0x00010FFF },
-   { GPSR10,   0x, 0x04006000 },
-   { GPSR11,   0x, 0x303FEFE0 },
-   { IPSR6,0x, 0x0002000E },
-};
+#define TMU0_MSTP125   BIT(25)
+#define QSPI_MSTP917   BIT(17)
 
-struct pin_db  pin_tbl[] = {
-   { PUPR2,0x, 0x },
-   { PUPR3,0x, 0x0803FF40 },
-   { PUPR4,0x, 0x },
-   { PUPR5,0x, 0x00010FFF },
-   { PUPR7,0x, 0x0001AFFF },
-   { PUPR9,0x, 0x0001CFFF },
-   { PUPR10,   0x, 0xC0438001 },
-   { PUPR11,   0x, 0x0FC7 },
+struct reg_config {
+   u16 off;
+   u32 

[U-Boot] [PATCH 1/4] i2c: rcar_i2c: Remove the driver

[Marek Vasut]

Remove the rcar_i2c driver, since it's no longer used by any
board and will be superseded by a DM and DT capable variant.

Signed-off-by: Marek Vasut 
Cc: Heiko Schocher 
Cc: Nobuhiro Iwamatsu 
---
 drivers/i2c/Makefile   |   1 -
 drivers/i2c/rcar_i2c.c | 292 -
 2 files changed, 293 deletions(-)
 delete mode 100644 drivers/i2c/rcar_i2c.c

diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index e8bb6327fb..c48a71ac6f 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -28,7 +28,6 @@ obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
 obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
 obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o
 obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
-obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
 obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o
 obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o
 obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o
diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c
deleted file mode 100644
index a2627dca5f..00
--- a/drivers/i2c/rcar_i2c.c
+++ /dev/null
@@ -1,292 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * drivers/i2c/rcar_i2c.c
- *
- * Copyright (C) 2013 Renesas Electronics Corporation
- * Copyright (C) 2013 Nobuhiro Iwamatsu 
- *
- * NOTE: This driver should be converted to driver model before June 2017.
- * Please see doc/driver-model/i2c-howto.txt for instructions.
- */
-
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct rcar_i2c {
-   u32 icscr;
-   u32 icmcr;
-   u32 icssr;
-   u32 icmsr;
-   u32 icsier;
-   u32 icmier;
-   u32 icccr;
-   u32 icsar;
-   u32 icmar;
-   u32 icrxdtxd;
-   u32 icccr2;
-   u32 icmpr;
-   u32 ichpr;
-   u32 iclpr;
-};
-
-#define MCR_MDBS   0x80/* non-fifo mode switch */
-#define MCR_FSCL   0x40/* override SCL pin */
-#define MCR_FSDA   0x20/* override SDA pin */
-#define MCR_OBPC   0x10/* override pins*/
-#define MCR_MIE0x08/* master if enable */
-#define MCR_TSBE   0x04
-#define MCR_FSB0x02/* force stop bit   */
-#define MCR_ESG0x01/* en startbit gen. */
-
-#define MSR_MASK   0x7f
-#define MSR_MNR0x40/* nack received*/
-#define MSR_MAL0x20/* arbitration lost */
-#define MSR_MST0x10/* sent a stop  */
-#define MSR_MDE0x08
-#define MSR_MDT0x04
-#define MSR_MDR0x02
-#define MSR_MAT0x01/* slave addr xfer done */
-
-static const struct rcar_i2c *i2c_dev[CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS] = {
-   (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C0_BASE,
-   (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C1_BASE,
-   (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C2_BASE,
-   (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C3_BASE,
-};
-
-static void rcar_i2c_raw_rw_common(struct rcar_i2c *dev, u8 chip, uint addr)
-{
-   /* set slave address */
-   writel(chip << 1, >icmar);
-   /* set register address */
-   writel(addr, >icrxdtxd);
-   /* clear status */
-   writel(0, >icmsr);
-   /* start master send */
-   writel(MCR_MDBS | MCR_MIE | MCR_ESG, >icmcr);
-
-   while ((readl(>icmsr) & (MSR_MAT | MSR_MDE))
-   != (MSR_MAT | MSR_MDE))
-   udelay(10);
-
-   /* clear ESG */
-   writel(MCR_MDBS | MCR_MIE, >icmcr);
-   /* start SCLclk */
-   writel(~(MSR_MAT | MSR_MDE), >icmsr);
-
-   while (!(readl(>icmsr) & MSR_MDE))
-   udelay(10);
-}
-
-static void rcar_i2c_raw_rw_finish(struct rcar_i2c *dev)
-{
-   while (!(readl(>icmsr) & MSR_MST))
-   udelay(10);
-
-   writel(0, >icmcr);
-}
-
-static int
-rcar_i2c_raw_write(struct rcar_i2c *dev, u8 chip, uint addr, u8 *val, int size)
-{
-   rcar_i2c_raw_rw_common(dev, chip, addr);
-
-   /* set send date */
-   writel(*val, >icrxdtxd);
-   /* start SCLclk */
-   writel(~MSR_MDE, >icmsr);
-
-   while (!(readl(>icmsr) & MSR_MDE))
-   udelay(10);
-
-   /* set stop condition */
-   writel(MCR_MDBS | MCR_MIE | MCR_FSB, >icmcr);
-   /* start SCLclk */
-   writel(~MSR_MDE, >icmsr);
-
-   rcar_i2c_raw_rw_finish(dev);
-
-   return 0;
-}
-
-static u8
-rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr)
-{
-   u8 ret;
-
-   rcar_i2c_raw_rw_common(dev, chip, addr);
-
-   /* set slave address, receive */
-   writel((chip << 1) | 1, >icmar);
-   /* start master receive */
-   writel(MCR_MDBS | MCR_MIE | MCR_ESG, >icmcr);
-   /* clear status */
-   writel(0, >icmsr);
-
-   while ((readl(>icmsr) & (MSR_MAT | MSR_MDR))
-   != (MSR_MAT | MSR_MDR))
-   udelay(10);
-
-   /* clear ESG */

[U-Boot] [PATCH 3/4] ARM: rmobile: Enable DM capable RCar I2C driver on Lager

[Marek Vasut]

Enable the DM capable driver instead of the legacy one.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 configs/lager_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/lager_defconfig b/configs/lager_defconfig
index 901b34e1dd..70083bcbfe 100644
--- a/configs/lager_defconfig
+++ b/configs/lager_defconfig
@@ -54,6 +54,7 @@ CONFIG_CLK_RENESAS=y
 CONFIG_DM_GPIO=y
 CONFIG_RCAR_GPIO=y
 CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_I2C=y
 CONFIG_SYS_I2C_RCAR_IIC=y
 CONFIG_DM_MMC=y
 CONFIG_SH_MMCIF=y
-- 
2.16.2

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[U-Boot] [PATCH 4/4] ARM: rmobile: Enable DM capable RCar I2C driver on Silk

[Marek Vasut]

Enable the DM capable driver instead of the legacy one.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 configs/silk_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/silk_defconfig b/configs/silk_defconfig
index c163e823b5..a1c4e5cde3 100644
--- a/configs/silk_defconfig
+++ b/configs/silk_defconfig
@@ -54,6 +54,7 @@ CONFIG_CLK_RENESAS=y
 CONFIG_DM_GPIO=y
 CONFIG_RCAR_GPIO=y
 CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_I2C=y
 CONFIG_SYS_I2C_RCAR_IIC=y
 CONFIG_DM_MMC=y
 CONFIG_SH_MMCIF=y
-- 
2.16.2

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[U-Boot] Support for the Raspberry Pi 3B+?

[Qwerty Chouskie]

The defconfig for the 3 seems to work fine, except that for some reason 
Ethernet doesn't work (from what I understand, it is on the USB bus, 
though u-boot doesn't detect it?


A quick google found some (maybe) useful files (e.g. the DTS) here: 
https://www.spinics.net/lists/arm-kernel/msg646251.html


It would be nice to have an explicit defconfig for the 3B+ for peace of 
mind, even if it is basically the same as the 3.


-QwertyChouskie

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[U-Boot] [PATCH V2 2/4] i2c: rcar_i2c: Add DM and DT capable I2C driver

[Marek Vasut]

Add derivative of the rcar_i2c driver which is capable of
probing itself from DM and uses DT.

Signed-off-by: Marek Vasut 
Cc: Heiko Schocher 
Cc: Nobuhiro Iwamatsu 
---
 drivers/i2c/Kconfig|   6 +
 drivers/i2c/Makefile   |   1 +
 drivers/i2c/rcar_i2c.c | 353 +
 3 files changed, 360 insertions(+)
 create mode 100644 drivers/i2c/rcar_i2c.c
---
V2: Fix the license tag and minor checkpatch issue

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 7fb201d8e6..5eceab9ea8 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -339,6 +339,12 @@ config SYS_OMAP24_I2C_SPEED
  OMAP24xx Slave speed channel 0
 endif
 
+config SYS_I2C_RCAR_I2C
+   bool "Renesas RCar I2C driver"
+   depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
+   help
+ Support for Renesas RCar I2C controller.
+
 config SYS_I2C_RCAR_IIC
bool "Renesas RCar Gen3 IIC driver"
depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index c48a71ac6f..8bb3c18b57 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
 obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
 obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o
 obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
+obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o
 obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o
 obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o
 obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o
diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c
new file mode 100644
index 00..8d87c73713
--- /dev/null
+++ b/drivers/i2c/rcar_i2c.c
@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * drivers/i2c/rcar_i2c.c
+ *
+ * Copyright (C) 2018 Marek Vasut 
+ *
+ * Clock configuration based on Linux i2c-rcar.c:
+ * Copyright (C) 2014-15 Wolfram Sang 
+ * Copyright (C) 2011-2015 Renesas Electronics Corporation
+ * Copyright (C) 2012-14 Renesas Solutions Corp.
+ *   Kuninori Morimoto 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define RCAR_I2C_ICSCR 0x00
+#define RCAR_I2C_ICMCR 0x04
+#define RCAR_I2C_ICMCR_MDBSBIT(7)
+#define RCAR_I2C_ICMCR_FSCLBIT(6)
+#define RCAR_I2C_ICMCR_FSDABIT(5)
+#define RCAR_I2C_ICMCR_OBPCBIT(4)
+#define RCAR_I2C_ICMCR_MIE BIT(3)
+#define RCAR_I2C_ICMCR_TSBEBIT(2)
+#define RCAR_I2C_ICMCR_FSB BIT(1)
+#define RCAR_I2C_ICMCR_ESG BIT(0)
+#define RCAR_I2C_ICSSR 0x08
+#define RCAR_I2C_ICMSR 0x0c
+#define RCAR_I2C_ICMSR_MASK0x7f
+#define RCAR_I2C_ICMSR_MNR BIT(6)
+#define RCAR_I2C_ICMSR_MAL BIT(5)
+#define RCAR_I2C_ICMSR_MST BIT(4)
+#define RCAR_I2C_ICMSR_MDE BIT(3)
+#define RCAR_I2C_ICMSR_MDT BIT(2)
+#define RCAR_I2C_ICMSR_MDR BIT(1)
+#define RCAR_I2C_ICMSR_MAT BIT(0)
+#define RCAR_I2C_ICSIER0x10
+#define RCAR_I2C_ICMIER0x14
+#define RCAR_I2C_ICCCR 0x18
+#define RCAR_I2C_ICCCR_SCGD_OFF3
+#define RCAR_I2C_ICSAR 0x1c
+#define RCAR_I2C_ICMAR 0x20
+#define RCAR_I2C_ICRXD_ICTXD   0x24
+
+struct rcar_i2c_priv {
+   void __iomem*base;
+   struct clk  clk;
+   u32 intdelay;
+   u32 icccr;
+};
+
+static int rcar_i2c_finish(struct udevice *dev)
+{
+   struct rcar_i2c_priv *priv = dev_get_priv(dev);
+   int ret;
+
+   ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, RCAR_I2C_ICMSR_MST,
+   true, 10, true);
+
+   writel(0, priv->base + RCAR_I2C_ICSSR);
+   writel(0, priv->base + RCAR_I2C_ICMSR);
+   writel(0, priv->base + RCAR_I2C_ICMCR);
+
+   return ret;
+}
+
+static void rcar_i2c_recover(struct udevice *dev)
+{
+   struct rcar_i2c_priv *priv = dev_get_priv(dev);
+   u32 mcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_OBPC;
+   u32 mcra = mcr | RCAR_I2C_ICMCR_FSDA;
+   int i;
+
+   /* Send 9 SCL pulses */
+   for (i = 0; i < 9; i++) {
+   writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
+   udelay(5);
+   writel(mcra, priv->base + RCAR_I2C_ICMCR);
+   udelay(5);
+   }
+
+   /* Send stop condition */
+   udelay(5);
+   writel(mcra, priv->base + RCAR_I2C_ICMCR);
+   udelay(5);
+   writel(mcr, priv->base + RCAR_I2C_ICMCR);
+   udelay(5);
+   writel(mcr | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
+   udelay(5);
+   writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base 

Re: [U-Boot] [PATCH v2 1/6] kconfig: re-sync with Linux 4.17-rc4

[Petr Vorel]

Hi Eugeniu,

> My testing was limited to:
> - make defconfig all
> - make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- r8a7795_ulcb_defconfig all
> - comparing .config before and after the re-sync
> - running the newly imported Kconfig unit tests as seen below:

I tested whole patch-set with the other options:
make config
make defconfig
make menuconfig
make xconfig
make gconfig
make oldconfig

> Reviewed-by: Masahiro Yamada 
> Signed-off-by: Eugeniu Rosca 
Tested-by: Petr Vorel 

> $ make testconfig

> = test session starts 
> =
> scripts/kconfig/tests/auto_submenu/__init__.py::test PASSED [  7%]
> scripts/kconfig/tests/choice/__init__.py::test_oldask0 PASSED   [ 14%]
> scripts/kconfig/tests/choice/__init__.py::test_oldask1 PASSED   [ 21%]
> scripts/kconfig/tests/choice/__init__.py::test_allyes PASSED[ 28%]
> scripts/kconfig/tests/choice/__init__.py::test_allmod PASSED[ 35%]
> scripts/kconfig/tests/choice/__init__.py::test_allno PASSED [ 42%]
> scripts/kconfig/tests/choice/__init__.py::test_alldef PASSED[ 50%]
> scripts/kconfig/tests/choice_value_with_m_dep/__init__.py::test PASSED  [ 57%]
> scripts/kconfig/tests/err_recursive_inc/__init__.py::test PASSED[ 64%]
> scripts/kconfig/tests/inter_choice/__init__.py::test PASSED [ 71%]
> scripts/kconfig/tests/new_choice_with_dep/__init__.py::test PASSED  [ 78%]
> scripts/kconfig/tests/no_write_if_dep_unmet/__init__.py::test PASSED[ 85%]
> scripts/kconfig/tests/rand_nested_choice/__init__.py::test PASSED   [ 92%]
> scripts/kconfig/tests/warn_recursive_dep/__init__.py::test PASSED   [100%]
> == 14 passed in 0.34 seconds 
> ==

When applied all 6 patches, I got several errors (see bellow).
I tested in on 2 distros (Debian unstable and openSUSE Tumbleweed).
The code I applied is here, did I make error when applying patches?
https://github.com/pevik/u-boot/tree/eugeniu/kconfig.v2


Kind regards,
Petr

$ make testconfig
python3 -B -m pytest ./scripts/kconfig/tests \
-o cache_dir=/home/pevik/install/src/u-boot.git/scripts/kconfig/tests/.cache \

= test session starts ==
platform linux -- Python 3.6.5, pytest-3.3.2, py-1.5.3, pluggy-0.6.0 -- 
/usr/bin/python3
cachedir: scripts/kconfig/tests/.cache
rootdir: /home/pevik/install/src/u-boot.git/scripts/kconfig/tests, inifile: 
pytest.ini
collecting ... collected 14 items

scripts/kconfig/tests/auto_submenu/__init__.py::test FAILED  [  7%]
scripts/kconfig/tests/choice/__init__.py::test_oldask0 FAILED[ 14%]
scripts/kconfig/tests/choice/__init__.py::test_oldask1 FAILED[ 21%]
scripts/kconfig/tests/choice/__init__.py::test_allyes PASSED [ 28%]
scripts/kconfig/tests/choice/__init__.py::test_allmod PASSED [ 35%]
scripts/kconfig/tests/choice/__init__.py::test_allno PASSED  [ 42%]
scripts/kconfig/tests/choice/__init__.py::test_alldef PASSED [ 50%]
scripts/kconfig/tests/choice_value_with_m_dep/__init__.py::test PASSED   [ 57%]
scripts/kconfig/tests/err_recursive_inc/__init__.py::test PASSED [ 64%]
scripts/kconfig/tests/inter_choice/__init__.py::test PASSED  [ 71%]
scripts/kconfig/tests/new_choice_with_dep/__init__.py::test FAILED   [ 78%]
scripts/kconfig/tests/no_write_if_dep_unmet/__init__.py::test PASSED [ 85%]
scripts/kconfig/tests/rand_nested_choice/__init__.py::test PASSED[ 92%]
scripts/kconfig/tests/warn_recursive_dep/__init__.py::test PASSED[100%]

=== FAILURES ===
_ test _

conf = 

def test(conf):
assert conf.oldaskconfig() == 0
>   assert conf.stdout_contains('expected_stdout')
E   AssertionError

scripts/kconfig/tests/auto_submenu/__init__.py:12: AssertionError
- Captured stdout call -
[command]
/home/pevik/install/src/u-boot.git/scripts/kconfig/conf --oldaskconfig Kconfig

[retcode]
0

[stdout]
*
* Linux Kernel Configuration
*
A (A) [Y/n/?] (NEW) 
  A0 (A0) [Y/n/?] (NEW) 
A1_0 (A0_0) [N/y/?] (NEW) 
  A1 (A1) [Y/n/?] (NEW) 
choice
> 1. A1_0 (A1_0) (NEW)
  2. A1_1 (A1_1) (NEW)
choice[1-2?]: 
B (B) [N/y/?] (NEW) 
C (C) [N/y/?] (NEW) 
#
# configuration written to .config
#

[stderr]

[output for '.config']
#
# Automatically generated file; DO NOT EDIT.
# Linux Kernel Configuration
#
CONFIG_A=y
CONFIG_A0=y
# CONFIG_A0_0 is not set
CONFIG_A1=y
CONFIG_A1_0=y
# CONFIG_A1_1 is not set
# CONFIG_B is not set
# CONFIG_C is not set

_ test_oldask0 _

conf = 

def 

Re: [U-Boot] [PATCH v2 1/6] kconfig: re-sync with Linux 4.17-rc4

[Eugeniu Rosca]

Hello Petr,

On Sat, May 12, 2018 at 08:25:56PM +0200, Petr Vorel wrote:
> Hi Eugeniu,
> 
> > My testing was limited to:
> > - make defconfig all
> > - make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- r8a7795_ulcb_defconfig all
> > - comparing .config before and after the re-sync
> > - running the newly imported Kconfig unit tests as seen below:
> 
> I tested whole patch-set with the other options:
> make config
> make defconfig
> make menuconfig
> make xconfig
> make gconfig
> make oldconfig
> 
> > Reviewed-by: Masahiro Yamada 
> > Signed-off-by: Eugeniu Rosca 
> Tested-by: Petr Vorel 

Many thanks for testing!

> 
> > $ make testconfig
> 
> > = test session starts 
> > =
> > scripts/kconfig/tests/auto_submenu/__init__.py::test PASSED [  
> > 7%]
> > scripts/kconfig/tests/choice/__init__.py::test_oldask0 PASSED   [ 
> > 14%]
> > scripts/kconfig/tests/choice/__init__.py::test_oldask1 PASSED   [ 
> > 21%]
> > scripts/kconfig/tests/choice/__init__.py::test_allyes PASSED[ 
> > 28%]
> > scripts/kconfig/tests/choice/__init__.py::test_allmod PASSED[ 
> > 35%]
> > scripts/kconfig/tests/choice/__init__.py::test_allno PASSED [ 
> > 42%]
> > scripts/kconfig/tests/choice/__init__.py::test_alldef PASSED[ 
> > 50%]
> > scripts/kconfig/tests/choice_value_with_m_dep/__init__.py::test PASSED  [ 
> > 57%]
> > scripts/kconfig/tests/err_recursive_inc/__init__.py::test PASSED[ 
> > 64%]
> > scripts/kconfig/tests/inter_choice/__init__.py::test PASSED [ 
> > 71%]
> > scripts/kconfig/tests/new_choice_with_dep/__init__.py::test PASSED  [ 
> > 78%]
> > scripts/kconfig/tests/no_write_if_dep_unmet/__init__.py::test PASSED[ 
> > 85%]
> > scripts/kconfig/tests/rand_nested_choice/__init__.py::test PASSED   [ 
> > 92%]
> > scripts/kconfig/tests/warn_recursive_dep/__init__.py::test PASSED   
> > [100%]
> > == 14 passed in 0.34 seconds 
> > ==
> 
> When applied all 6 patches, I got several errors (see bellow).
> I tested in on 2 distros (Debian unstable and openSUSE Tumbleweed).
> The code I applied is here, did I make error when applying patches?
> https://github.com/pevik/u-boot/tree/eugeniu/kconfig.v2

I checked your branch and got some interesting conclusions.
Here is the diff between my and your version of commit ("kconfig:
re-sync with Linux 4.17-rc4"):

$ git diff  
 scripts/kconfig/tests/auto_submenu/expected_stdout| 14 +++---
 scripts/kconfig/tests/choice/oldask0_expected_stdout  | 14 +++---
 scripts/kconfig/tests/choice/oldask1_expected_stdout  | 12 ++--
 scripts/kconfig/tests/new_choice_with_dep/expected_stdout |  4 ++--
 4 files changed, 22 insertions(+), 22 deletions(-)

Here is the same diff ignoring whitespace:

$ git diff -w  
 scripts/kconfig/tests/auto_submenu/expected_stdout| 0
 scripts/kconfig/tests/choice/oldask0_expected_stdout  | 0
 scripts/kconfig/tests/choice/oldask1_expected_stdout  | 0
 scripts/kconfig/tests/new_choice_with_dep/expected_stdout | 0
 4 files changed, 0 insertions(+), 0 deletions(-)

So, it seems like all the trailing white-space from above files
disappeared on your branch, after applying the patches from the
email client (who did this?...).

I didn't expect that trailing white-space to be of any value for the
test results, but it turns out it is! With the whitespace removed, I can
also reproduce the failures of "make testconfig".

I am not familiar with pytest, but, based on what we see here, it looks
like every single character stored in *xpected_stdout files (including
whitespace at the end of lines) matters for the test to pass.

I wonder if Kconfig could avoid printing whitespace in command line
user dialogs. Then maybe those space characters could be removed from
the "*xpected_stdout" files.

Masahiro?

Thanks again!

Best regards,
Eugeniu.
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Re: [U-Boot] [RFC PATCH 1/2] kconfig: re-sync with Linux 4.17-rc4

[Eugeniu Rosca]

Hi Masahiro,

On Sat, May 12, 2018 at 01:46:15PM +0900, Masahiro Yamada wrote:
> > This seems to happen because the Kbuild updates apparently didn't make
> > room for both "*shipped"-based builds and flex/bison-based builds. A
> > similar problem has been reported for genksyms parser in v4.17-rc1
> > commit 833e622459432e ("genksyms: generate lexer and parser during build
> > instead of shipping"). I have figured out empirically that the warnings
> > are healed after updating the in-tree U-boot DTC to upstream v1.4.6-9,
> > same as done by Linux v4.17-rc1 commit 9130ba88464032 ("scripts/dtc:
> > Update to upstream version v1.4.6-9-gaadd0b65c987"). Whether fixing the
> > DTC-related yacc warnings should be done together with the Kconfig
> > re-sync, I would like to hear from community.
> 
> I agree.
> 
> Re-sync of scripts/dtc/ should follow.

Included in v2.

> 
> > +
> >  # Help text used by make help
> >  help:
> > @echo  '  config  - Update current config utilising a 
> > line-oriented program'
> > @@ -152,7 +169,6 @@ help:
> > @echo  '  oldconfig   - Update current config utilising a 
> > provided .config as base'
> > @echo  '  localmodconfig  - Update current config disabling modules 
> > not loaded'
> > @echo  '  localyesconfig  - Update current config converting local 
> > mods to core'
> > -   @echo  '  silentoldconfig - Same as oldconfig, but quietly, 
> > additionally update deps'
> > @echo  '  defconfig   - New config with default from ARCH 
> > supplied defconfig'
> > @echo  '  savedefconfig   - Save current config as ./defconfig 
> > (minimal config)'
> > @echo  '  allnoconfig - New config where all options are 
> > answered with no'
> > @@ -161,7 +177,7 @@ help:
> > @echo  '  alldefconfig- New config with all symbols set to 
> > default'
> > @echo  '  randconfig  - New config with random answer to all 
> > options'
> > @echo  '  listnewconfig   - List new options'
> > -   @echo  '  olddefconfig- Same as silentoldconfig but sets new 
> > symbols to their'
> > +   @echo  '  olddefconfig- Same as oldconfig but sets new symbols 
> > to their'
> > @echo  'default value'
> 
> 
> Linux commit cedd55d49dee added 'without prompting'
> after 'default value'
> 
> Could you do likewise please?

Missed that one! Fixed in v2. Thanks!

Best regards,
Eugeniu.
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[U-Boot] [PATCH v2 6/6] sandbox: dts: test: Fix wrong aliases property names

[Eugeniu Rosca]

After importing v4.17-rc1 Linux commit 9130ba884640 ("scripts/dtc:
Update to upstream version v1.4.6-9-gaadd0b65c987"), sandbox build
reports below warnings:

arch/sandbox/dts/test.dtb: Warning (alias_paths): /aliases: aliases property 
name must include only lowercase and '-'
arch/sandbox/dts/test.dtb: Warning (alias_paths): /aliases: aliases property 
name must include only lowercase and '-'
arch/sandbox/dts/test.dtb: Warning (alias_paths): /aliases: aliases property 
name must include only lowercase and '-'
arch/sandbox/dts/test.dtb: Warning (alias_paths): /aliases: aliases property 
name must include only lowercase and '-'

Silent them.

Fixes: e8d5291824e2 ("core: ofnode: Fix translation for #size-cells == 0")
Signed-off-by: Eugeniu Rosca 
---

v1->v2:
* Newly pushed

 arch/sandbox/dts/test.dts | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 683b1970e0af..3e87c5c0f3fd 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -27,10 +27,10 @@
testfdt3 = "/b-test";
testfdt5 = "/some-bus/c-test@5";
testfdt8 = "/a-test";
-   fdt_dummy0 = "/translation-test@8000/dev@0,0";
-   fdt_dummy1 = "/translation-test@8000/dev@1,100";
-   fdt_dummy2 = "/translation-test@8000/dev@2,200";
-   fdt_dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
+   fdt-dummy0 = "/translation-test@8000/dev@0,0";
+   fdt-dummy1 = "/translation-test@8000/dev@1,100";
+   fdt-dummy2 = "/translation-test@8000/dev@2,200";
+   fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
usb0 = _0;
usb1 = _1;
usb2 = _2;
-- 
2.17.0

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[U-Boot] [PATCH v2 4/6] scripts/dtc: Update to upstream version v1.4.6-9-gaadd0b65c987

[Eugeniu Rosca]

From: Rob Herring 

This adds the following commits from upstream:

aadd0b65c987 checks: centralize printing of property names in failure messages
88960e398907 checks: centralize printing of node path in check_msg
f1879e1a50eb Add limited read-only support for older (V2 and V3) device tree to 
libfdt.
37dea76e9700 srcpos: drop special handling of tab
65893da4aee0 libfdt: overlay: Add missing license
962a45ca034d Avoid installing pylibfdt when dependencies are missing
cd6ea1b2bea6 Makefile: Split INSTALL out into INSTALL_{PROGRAM,LIB,DATA,SCRIPT}
51b3a16338df Makefile.tests: Add LIBDL make(1) variable for portability sake
333d533a8f4d Attempt to auto-detect stat(1) being used if not given proper 
invocation
e54388015af1 dtc: Bump version to v1.4.6
a1fe86f380cb fdtoverlay: Switch from using alloca to malloc
c8d5472de3ff tests: Improve compatibility with other platforms
c81d389a10cc checks: add chosen node checks
e671852042a7 checks: add aliases node checks
d0c44ebe3f42 checks: check for #{size,address}-cells without child nodes
18a3d84bb802 checks: add string list check for *-names properties
8fe94fd6f19f checks: add string list check
6c5730819604 checks: add a string check for 'label' property
a384191eba09 checks: fix sound-dai phandle with arg property check
b260c4f610c0 Fix ambiguous grammar for devicetree rule
fe667e382bac tests: Add some basic tests for the pci_bridge checks
7975f6422260 Fix widespread incorrect use of strneq(), replace with new 
strprefixeq()
fca296445eab Add strstarts() helper function
cc392f089007 tests: Check non-matching cases for fdt_node_check_compatible()
bba26a5291c8 livetree: avoid assertion of orphan phandles with overlays
c8f8194d76cc implement strnlen for systems that need it
c8b38f65fdec libfdt: Remove leading underscores from identifiers
3b62fdaebfe5 Remove leading underscores from identifiers
2d45d1c5c65e Replace FDT_VERSION() with stringify()
2e6fe5a107b5 Fix some errors in comments
b0ae9e4b0ceb tests: Correct warning in sw_tree1.c

Commit c8b38f65fdec upstream ("libfdt: Remove leading underscores from
identifiers") changed the multiple inclusion define protection, so the
kernel's libfdt_env.h needs the corresponding update.

Signed-off-by: Rob Herring 
[ Linux commit: 9130ba884640328bb78aaa4840e5ddf06ccafb1c ]
[erosca: - Fixup conflicts in include/linux/libfdt_env.h caused by v2018.03-rc4
   commit b08c8c487083 ("libfdt: move headers to 
   and ")
 - Fix build errors in lib/libfdt/fdt_ro.c, tools/libfdt/fdt_rw.c by:
   - s/_fdt_mem_rsv/fdt_mem_rsv_/
   - s/_fdt_offset_ptr/fdt_offset_ptr_/
   - s/_fdt_check_node_offset/fdt_check_node_offset_/
   - s/_fdt_check_prop_offset/fdt_check_prop_offset_/
   - s/_fdt_find_add_string/fdt_find_add_string_/]
Signed-off-by: Eugeniu Rosca 
---

v1-v2:
* Newly pushed

 include/linux/libfdt_env.h   |   6 +-
 lib/libfdt/fdt_ro.c  |  18 +-
 scripts/dtc/checks.c | 439 ++-
 scripts/dtc/dtc-parser.y |  17 +-
 scripts/dtc/dtc.c|   7 +-
 scripts/dtc/dtc.h|  11 +-
 scripts/dtc/flattree.c   |   2 +-
 scripts/dtc/libfdt/fdt.c |  13 +-
 scripts/dtc/libfdt/fdt.h |   6 +-
 scripts/dtc/libfdt/fdt_overlay.c |  51 
 scripts/dtc/libfdt/fdt_ro.c  | 132 ++--
 scripts/dtc/libfdt/fdt_rw.c  |  90 +++---
 scripts/dtc/libfdt/fdt_sw.c  |  24 +-
 scripts/dtc/libfdt/fdt_wip.c |  10 +-
 scripts/dtc/libfdt/libfdt.h  |  37 +--
 scripts/dtc/libfdt/libfdt_env.h  |  33 +-
 scripts/dtc/libfdt/libfdt_internal.h |  32 +-
 scripts/dtc/livetree.c   |  10 +-
 scripts/dtc/srcpos.c |   5 -
 scripts/dtc/srcpos.h |   6 +-
 scripts/dtc/util.h   |   9 +-
 scripts/dtc/version_gen.h|   2 +-
 tools/libfdt/fdt_rw.c|   2 +-
 23 files changed, 632 insertions(+), 330 deletions(-)

diff --git a/include/linux/libfdt_env.h b/include/linux/libfdt_env.h
index 0d209a649286..e2bf79c7ee8d 100644
--- a/include/linux/libfdt_env.h
+++ b/include/linux/libfdt_env.h
@@ -6,8 +6,8 @@
  * Using the same guard name as that of scripts/dtc/libfdt/libfdt_env.h
  * prevents it from being included.
  */
-#ifndef _LIBFDT_ENV_H
-#define _LIBFDT_ENV_H
+#ifndef LIBFDT_ENV_H
+#define LIBFDT_ENV_H
 
 #include 
 
@@ -27,5 +27,5 @@ typedef __be64 fdt64_t;
 
 #define strtoul(cp, endp, base)simple_strtoul(cp, endp, base)
 
-#endif /* _LIBFDT_ENV_H */
+#endif /* LIBFDT_ENV_H */
 #endif
diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c
index 4b7008d88fe9..b6ca4e0b0c30 100644
--- a/lib/libfdt/fdt_ro.c
+++ b/lib/libfdt/fdt_ro.c
@@ -76,8 +76,8 @@ uint32_t fdt_get_max_phandle(const void *fdt)
 int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size)
 {

[U-Boot] [PATCH v2 3/6] scripts/dtc: Update to upstream version v1.4.5-6-gc1e55a5513e9

[Eugeniu Rosca]

From: Rob Herring 

Pickup the fix for handling unresolved phandles in overlays.

This adds the following commits from upstream:

c1e55a5513e9 checks: fix handling of unresolved phandles for dts plugins
f8872e29ce06 tests: Avoid 64-bit arithmetic in assembler
48c91c08bcfa libfdt: add stringlist functions to linker script

Signed-off-by: Rob Herring 
[ Linux commit: e45fe7f788dd1395befe5639149ad8dacfbd94ab ]
Signed-off-by: Eugeniu Rosca 
---

v1->v2:
* Newly pushed

 scripts/dtc/checks.c  | 9 +
 scripts/dtc/version_gen.h | 2 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/scripts/dtc/checks.c b/scripts/dtc/checks.c
index 08a3a29edae3..e66138449886 100644
--- a/scripts/dtc/checks.c
+++ b/scripts/dtc/checks.c
@@ -988,6 +988,10 @@ static void check_property_phandle_args(struct check *c,
 * entries when each index position has a specific definition.
 */
if (phandle == 0 || phandle == -1) {
+   /* Give up if this is an overlay with external 
references */
+   if (dti->dtsflags & DTSF_PLUGIN)
+   break;
+
cellsize = 0;
continue;
}
@@ -1176,6 +1180,11 @@ static void check_interrupts_property(struct check *c,
prop = get_property(parent, "interrupt-parent");
if (prop) {
phandle = propval_cell(prop);
+   /* Give up if this is an overlay with external 
references */
+   if ((phandle == 0 || phandle == -1) &&
+   (dti->dtsflags & DTSF_PLUGIN))
+   return;
+
irq_node = get_node_by_phandle(root, phandle);
if (!irq_node) {
FAIL(c, dti, "Bad interrupt-parent phandle for 
%s",
diff --git a/scripts/dtc/version_gen.h b/scripts/dtc/version_gen.h
index d88393cab14a..6a4e84798966 100644
--- a/scripts/dtc/version_gen.h
+++ b/scripts/dtc/version_gen.h
@@ -1 +1 @@
-#define DTC_VERSION "DTC 1.4.5-gb1a60033"
+#define DTC_VERSION "DTC 1.4.5-gc1e55a55"
-- 
2.17.0

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[U-Boot] [PATCH v2 2/6] board: eets: pdu001: Fix wrong default value in Kconfig

[Eugeniu Rosca]

After importing linux v4.16-rc1 commit 2c37e08464a8 ("kconfig: Warn if
choice default is not in choice"), Kconfig complains:

scripts/kconfig/conf  --syncconfig Kconfig
board/eets/pdu001/Kconfig:22:warning:\
  choice default symbol 'PDU001_RUN_LED_RED' \
  is not contained in the choice

This looks to be caused by a typo. Fix it.

Fixes: 85ab0452fefc ("arm: add support for PDU001")
Reviewed-by: Masahiro Yamada 
Signed-off-by: Eugeniu Rosca 
---

v1->v2:
* Added: Reviewed-by: Masahiro Yamada 

 board/eets/pdu001/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/eets/pdu001/Kconfig b/board/eets/pdu001/Kconfig
index f28ba6e7bff2..e64ae28875b1 100644
--- a/board/eets/pdu001/Kconfig
+++ b/board/eets/pdu001/Kconfig
@@ -19,7 +19,7 @@ config SYS_CONFIG_NAME
 
 choice
prompt "State of Run LED"
-   default PDU001_RUN_LED_RED
+   default RUN_LED_RED
help
  The PDU001 has a bi-color (red/green) LED labeled 'Run' which
  can be used to indicate the operating state of the board. By
-- 
2.17.0

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[U-Boot] [PATCH 12/12] ARM: socfpga: Adding SoCFPGA info for both SPL and U-Boot

[Marek Vasut]

From: Tien Fong Chee 

SoC FPGA info is required in both SPL and U-Boot.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/board.c| 4 
 arch/arm/mach-socfpga/misc_arria10.c | 5 -
 arch/arm/mach-socfpga/spl.c  | 6 ++
 3 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 6e0b4b3c4e..189e12a668 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -30,6 +31,9 @@ int board_init(void)
 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
/* configuring the clock based on handoff */
cm_basic_init(gd->fdt_blob);
+
+   /* Add device descriptor to FPGA device table */
+   socfpga_fpga_add();
 #endif
 
return 0;
diff --git a/arch/arm/mach-socfpga/misc_arria10.c 
b/arch/arm/mach-socfpga/misc_arria10.c
index e1d80a5a76..47a9d50ef1 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -104,11 +104,6 @@ int arch_early_init_r(void)
/* assert reset to all except L4WD0 and L4TIMER0 */
socfpga_per_reset_all();
 
-   /* configuring the clock based on handoff */
-   /* TODO: Add call to cm_basic_init() */
-
-   /* Add device descriptor to FPGA device table */
-   socfpga_fpga_add();
return 0;
 }
 #else
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 515832031a..0c9d7388e6 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -191,6 +192,11 @@ void spl_board_init(void)
 
/* enable console uart printing */
preloader_console_init();
+
+   WATCHDOG_RESET();
+
+   /* Add device descriptor to FPGA device table */
+   socfpga_fpga_add();
 }
 
 void board_init_f(ulong dummy)
-- 
2.16.2

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[U-Boot] [PATCH 09/12] configs: Add DDR Kconfig support for Arria 10

[Marek Vasut]

From: Tien Fong Chee 

This patch enables DDR Kconfig support for Arria 10.

Signed-off-by: Tien Fong Chee 
Reviewed-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/Kconfig | 1 +
 drivers/ddr/altera/Kconfig| 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 824c9fc2ba..b8fc81b20c 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -10,6 +10,7 @@ config TARGET_SOCFPGA_ARRIA5
 config TARGET_SOCFPGA_ARRIA10
bool
select SPL_BOARD_INIT if SPL
+   select ALTERA_SDRAM
 
 config TARGET_SOCFPGA_CYCLONE5
bool
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
index 021ec1d857..2b28a97f6e 100644
--- a/drivers/ddr/altera/Kconfig
+++ b/drivers/ddr/altera/Kconfig
@@ -1,5 +1,5 @@
 config ALTERA_SDRAM
bool "SoCFPGA DDR SDRAM driver"
-   depends on TARGET_SOCFPGA_GEN5
+   depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
help
  Enable DDR SDRAM controller for the SoCFPGA devices.
-- 
2.16.2

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[U-Boot] [PATCH 10/12] ARM: socfpga: Enable SPL memory allocation

[Marek Vasut]

From: Tien Fong Chee 

Enable memory allocation in SPL for preparation to enable FAT
in SPL. Memory allocation is needed by FAT to work properly.

Signed-off-by: Tien Fong Chee 
Reviewed-by: Dinh Nguyen 
---
 include/configs/socfpga_common.h | 23 ++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index a60da85499..acac4a7108 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -226,17 +226,34 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /*
  * SPL
  *
- * SRAM Memory layout:
+ * SRAM Memory layout for gen 5:
  *
  * 0x_ .. Start of SRAM
  * 0x_ .. Top of stack (grows down)
  * 0x_ .. Malloc area
  * 0x_ .. Global Data
  * 0x_FF00 .. End of SRAM
+ *
+ * SRAM Memory layout for Arria 10:
+ * 0xFFE0_ .. Start of SRAM (bottom)
+ * 0xFFEx_ .. Top of stack (grows down to bottom)
+ * 0xFFEy_ .. Global Data
+ * 0xFFEz_ .. Malloc area (grows up to top)
+ * 0xFFE3_ .. End of SRAM (top)
  */
 #define CONFIG_SPL_TEXT_BASE   CONFIG_SYS_INIT_RAM_ADDR
 #define CONFIG_SPL_MAX_SIZECONFIG_SYS_INIT_RAM_SIZE
 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+/* SPL memory allocation configuration, this is for FAT implementation */
+#ifndef CONFIG_SYS_SPL_MALLOC_START
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001
+#define CONFIG_SYS_SPL_MALLOC_START(CONFIG_SYS_INIT_RAM_SIZE - \
+CONFIG_SYS_SPL_MALLOC_SIZE + \
+CONFIG_SYS_INIT_RAM_ADDR)
+#endif
+#endif
+
 /* SPL SDMMC boot support */
 #ifdef CONFIG_SPL_MMC_SUPPORT
 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
@@ -263,7 +280,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /*
  * Stack setup
  */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SPL_STACK   CONFIG_SYS_INIT_SP_ADDR
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SPL_STACK   CONFIG_SYS_SPL_MALLOC_START
+#endif
 
 /* Extra Environment */
 #ifndef CONFIG_SPL_BUILD
-- 
2.16.2

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[U-Boot] [PATCH 11/12] ARM: socfpga: Adding clock frequency info for U-Boot

[Marek Vasut]

From: Tien Fong Chee 

Clock frequency info is required in U-Boot because info would be erased
when transition from SPL to U-Boot.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/board.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 38e12a41a3..6e0b4b3c4e 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -7,7 +7,9 @@
 
 #include 
 #include 
+#include 
 #include 
+#include 
 #include 
 
 #include 
@@ -25,6 +27,11 @@ int board_init(void)
/* Address of boot parameters for ATAG (if ATAG is used) */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   /* configuring the clock based on handoff */
+   cm_basic_init(gd->fdt_blob);
+#endif
+
return 0;
 }
 
-- 
2.16.2

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[U-Boot] [PATCH 07/12] ARM: socfpga: Add DRAM bank size initialization function

[Marek Vasut]

From: Tien Fong Chee 

Add function for both multiple DRAM bank and single DRAM bank size
initialization. This common functionality could be used by every single
SOCFPGA board.

Signed-off-by: Tien Fong Chee 
Tested-by: Ley Foon Tan 
---
 arch/arm/mach-socfpga/board.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index c23ac4ead3..38e12a41a3 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -28,6 +28,13 @@ int board_init(void)
return 0;
 }
 
+int dram_init_banksize(void)
+{
+   fdtdec_setup_memory_banksize();
+
+   return 0;
+}
+
 #ifdef CONFIG_USB_GADGET
 struct dwc2_plat_otg_data socfpga_otg_data = {
.usb_gusbcfg= 0x1417,
-- 
2.16.2

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[U-Boot] [PATCH 08/12] ARM: socfpga: Add DDR driver for Arria 10

[Marek Vasut]

From: Tien Fong Chee 

Add DDR driver support for Arria 10.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/include/mach/sdram.h |   2 +
 arch/arm/mach-socfpga/include/mach/sdram_arria10.h |   2 +
 drivers/ddr/altera/Makefile|   1 +
 drivers/ddr/altera/sdram_arria10.c | 741 +
 4 files changed, 746 insertions(+)
 create mode 100644 drivers/ddr/altera/sdram_arria10.c

diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h 
b/arch/arm/mach-socfpga/include/mach/sdram.h
index 1a4b22accd..79cb9e6064 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -9,6 +9,8 @@
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include 
 #endif
 
 #endif
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h 
b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
index 8ae8d1bc96..25b82fb285 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
@@ -7,6 +7,7 @@
 #define _SOCFPGA_SDRAM_ARRIA10_H_
 
 #ifndef __ASSEMBLY__
+int ddr_calibration_sequence(void);
 
 struct socfpga_ecc_hmc {
u32 ip_rev_id;
@@ -203,6 +204,7 @@ struct socfpga_io48_mmr {
u32 niosreserve1;
u32 niosreserve2;
 };
+
 #endif /*__ASSEMBLY__*/
 
 #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK0x1F00
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index ec1cb0b6e4..f05314a373 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -8,4 +8,5 @@
 
 ifdef CONFIG_ALTERA_SDRAM
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
 endif
diff --git a/drivers/ddr/altera/sdram_arria10.c 
b/drivers/ddr/altera/sdram_arria10.c
new file mode 100644
index 00..d953c376b8
--- /dev/null
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -0,0 +1,741 @@
+/*
+ * Copyright (C) 2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_mmr_init(void);
+static u64 sdram_size_calc(void);
+
+/* FAWBANK - Number of Bank of a given device involved in the FAW period. */
+#define ARRIA10_SDR_ACTIVATE_FAWBANK   (0x1)
+
+#define ARRIA_DDR_CONFIG(A, B, C, R) \
+   (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
+#define DDR_CONFIG_ELEMENTSARRAY_SIZE(ddr_config)
+#define DDR_REG_SEQ2CORE0xFFD0507C
+#define DDR_REG_CORE2SEQ0xFFD05078
+#define DDR_READ_LATENCY_DELAY 40
+#define DDR_SIZE_2GB_HEX   0x8000
+#define DDR_MAX_TRIES  0x0010
+
+#define IO48_MMR_DRAMSTS   0xFFCFA0EC
+#define IO48_MMR_NIOS2_RESERVE00xFFCFA110
+#define IO48_MMR_NIOS2_RESERVE10xFFCFA114
+#define IO48_MMR_NIOS2_RESERVE20xFFCFA118
+
+#define SEQ2CORE_MASK  0xF
+#define CORE2SEQ_INT_REQ   0xF
+#define SEQ2CORE_INT_RESP_BIT  3
+
+static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
+   (void *)SOCFPGA_SDR_ADDRESS;
+static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
+   (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
+static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
+   *socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
+   (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
+static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
+   (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
+static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
+   (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
+
+/* The following are the supported configurations */
+static u32 ddr_config[] = {
+   /* Chip - Row - Bank - Column Style */
+   /* All Types */
+   ARRIA_DDR_CONFIG(0, 3, 10, 12),
+   ARRIA_DDR_CONFIG(0, 3, 10, 13),
+   ARRIA_DDR_CONFIG(0, 3, 10, 14),
+   ARRIA_DDR_CONFIG(0, 3, 10, 15),
+   ARRIA_DDR_CONFIG(0, 3, 10, 16),
+   ARRIA_DDR_CONFIG(0, 3, 10, 17),
+   /* LPDDR x16 */
+   ARRIA_DDR_CONFIG(0, 3, 11, 14),
+   ARRIA_DDR_CONFIG(0, 3, 11, 15),
+   ARRIA_DDR_CONFIG(0, 3, 11, 16),
+   ARRIA_DDR_CONFIG(0, 3, 12, 15),
+   /* DDR4 Only */
+   ARRIA_DDR_CONFIG(0, 4, 10, 14),
+   ARRIA_DDR_CONFIG(0, 4, 10, 15),
+   ARRIA_DDR_CONFIG(0, 4, 10, 16),
+   ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */
+   /* Chip - Bank - Row - Column Style */
+   ARRIA_DDR_CONFIG(1, 3, 10, 12),
+   ARRIA_DDR_CONFIG(1, 3, 10, 13),
+   ARRIA_DDR_CONFIG(1, 3, 10, 14),
+   ARRIA_DDR_CONFIG(1, 3, 10, 15),
+   ARRIA_DDR_CONFIG(1, 3, 10, 16),
+   ARRIA_DDR_CONFIG(1, 3, 10, 17),
+   ARRIA_DDR_CONFIG(1, 3, 11, 14),
+   ARRIA_DDR_CONFIG(1, 3, 11, 

[U-Boot] [PATCH 05/12] ARM: socfpga: Repair A10 EMAC reset handling

[Marek Vasut]

The EMAC reset and PHY mode configuration was never working on the
Arria10 SoC, fix this. This patch pulls out the common code into
misc.c and passes the SoC-specific function call in as a function
pointer.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
---
NOTE: This should be converted to reset framework.
---
 arch/arm/mach-socfpga/include/mach/reset_manager.h |  2 +
 arch/arm/mach-socfpga/misc.c   | 65 +
 arch/arm/mach-socfpga/misc_arria10.c   | 19 +-
 arch/arm/mach-socfpga/misc_gen5.c  | 67 ++
 4 files changed, 87 insertions(+), 66 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index d3ae80bc27..8ee801c635 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -10,6 +10,8 @@ void reset_cpu(ulong addr);
 
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
+int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id,
+const u8 phymode));
 
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
 
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 5c27f1984e..7bedcb36f4 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -135,3 +135,68 @@ int arch_cpu_init(void)
 
return 0;
 }
+
+#ifdef CONFIG_ETH_DESIGNWARE
+static int dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
+{
+   if (!phymode)
+   return -EINVAL;
+
+   if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
+   *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+   return 0;
+   }
+
+   if (!strcmp(phymode, "rgmii")) {
+   *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+   return 0;
+   }
+
+   if (!strcmp(phymode, "rmii")) {
+   *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
+   return 0;
+   }
+
+   return -EINVAL;
+}
+
+int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id,
+const u8 phymode))
+{
+   const void *fdt = gd->fdt_blob;
+   struct fdtdec_phandle_args args;
+   const char *phy_mode;
+   u32 phy_modereg;
+   int nodes[2];   /* Max. two GMACs */
+   int ret, count;
+   int i, node;
+
+   count = fdtdec_find_aliases_for_id(fdt, "ethernet",
+  COMPAT_ALTERA_SOCFPGA_DWMAC,
+  nodes, ARRAY_SIZE(nodes));
+   for (i = 0; i < count; i++) {
+   node = nodes[i];
+   if (node <= 0)
+   continue;
+
+   ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
+"#reset-cells", 1, 0,
+);
+   if (ret || (args.args_count != 1)) {
+   debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
+   continue;
+   }
+
+   phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
+   ret = dwmac_phymode_to_modereg(phy_mode, _modereg);
+   if (ret) {
+   debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
+   continue;
+   }
+
+   resetfn(args.args[0], phy_modereg);
+   }
+
+   return 0;
+}
+#endif
diff --git a/arch/arm/mach-socfpga/misc_arria10.c 
b/arch/arm/mach-socfpga/misc_arria10.c
index f909568312..e1d80a5a76 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -41,8 +41,7 @@ static struct socfpga_system_manager *sysmgr_regs =
  * DesignWare Ethernet initialization
  */
 #ifdef CONFIG_ETH_DESIGNWARE
-void dwmac_deassert_reset(const unsigned int of_reset_id,
-const u32 phymode)
+static void arria10_dwmac_reset(const u8 of_reset_id, const u8 phymode)
 {
u32 reset;
 
@@ -64,6 +63,20 @@ void dwmac_deassert_reset(const unsigned int of_reset_id,
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
 }
+
+static int socfpga_eth_reset(void)
+{
+   /* Put all GMACs into RESET state. */
+   socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
+   socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
+   socfpga_per_reset(SOCFPGA_RESET(EMAC2), 1);
+   return socfpga_eth_reset_common(arria10_dwmac_reset);
+};
+#else
+static int socfpga_eth_reset(void)
+{
+   return 0;
+};
 #endif
 
 #if defined(CONFIG_SPL_BUILD)
@@ -251,6 +264,6 @@ int print_cpuinfo(void)
 #ifdef CONFIG_ARCH_MISC_INIT
 int arch_misc_init(void)
 {
-   return 0;
+   return socfpga_eth_reset();
 }
 

[U-Boot] [PATCH 06/12] ARM: socfpga: Rename the gen5 sdram driver to more specific name

[Marek Vasut]

From: Tien Fong Chee 

Current sdram driver is only applied to gen5 device, hence it is better
to rename sdram driver to more specific name which is related to gen5
device.

Signed-off-by: Tien Fong Chee 
---
 arch/arm/mach-socfpga/include/mach/sdram.h  | 432 +--
 arch/arm/mach-socfpga/include/mach/sdram_gen5.h | 442 
 drivers/ddr/altera/Makefile |   2 +-
 drivers/ddr/altera/{sdram.c => sdram_gen5.c}|   0
 4 files changed, 446 insertions(+), 430 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_gen5.h
 rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)

diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h 
b/arch/arm/mach-socfpga/include/mach/sdram.h
index a58872c3d9..1a4b22accd 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -7,435 +7,9 @@
 
 #ifndef __ASSEMBLY__
 
-unsigned long sdram_calculate_size(void);
-int sdram_mmr_init_full(unsigned int sdr_phy_reg);
-int sdram_calibration_full(void);
-
-const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
-
-void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
-void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
-const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
-const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
-const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
-
-#define SDR_CTRLGRP_ADDRESS(SOCFPGA_SDR_ADDRESS | 0x5000)
-
-struct socfpga_sdr_ctrl {
-   u32 ctrl_cfg;
-   u32 dram_timing1;
-   u32 dram_timing2;
-   u32 dram_timing3;
-   u32 dram_timing4;   /* 0x10 */
-   u32 lowpwr_timing;
-   u32 dram_odt;
-   u32 extratime1;
-   u32 __padding0[3];
-   u32 dram_addrw; /* 0x2c */
-   u32 dram_if_width;  /* 0x30 */
-   u32 dram_dev_width;
-   u32 dram_sts;
-   u32 dram_intr;
-   u32 sbe_count;  /* 0x40 */
-   u32 dbe_count;
-   u32 err_addr;
-   u32 drop_count;
-   u32 drop_addr;  /* 0x50 */
-   u32 lowpwr_eq;
-   u32 lowpwr_ack;
-   u32 static_cfg;
-   u32 ctrl_width; /* 0x60 */
-   u32 cport_width;
-   u32 cport_wmap;
-   u32 cport_rmap;
-   u32 rfifo_cmap; /* 0x70 */
-   u32 wfifo_cmap;
-   u32 cport_rdwr;
-   u32 port_cfg;
-   u32 fpgaport_rst;   /* 0x80 */
-   u32 __padding1;
-   u32 fifo_cfg;
-   u32 protport_default;
-   u32 prot_rule_addr; /* 0x90 */
-   u32 prot_rule_id;
-   u32 prot_rule_data;
-   u32 prot_rule_rdwr;
-   u32 __padding2[3];
-   u32 mp_priority;/* 0xac */
-   u32 mp_weight0; /* 0xb0 */
-   u32 mp_weight1;
-   u32 mp_weight2;
-   u32 mp_weight3;
-   u32 mp_pacing0; /* 0xc0 */
-   u32 mp_pacing1;
-   u32 mp_pacing2;
-   u32 mp_pacing3;
-   u32 mp_threshold0;  /* 0xd0 */
-   u32 mp_threshold1;
-   u32 mp_threshold2;
-   u32 __padding3[29];
-   u32 phy_ctrl0;  /* 0x150 */
-   u32 phy_ctrl1;
-   u32 phy_ctrl2;
-};
-
-/* SDRAM configuration structure for the SPL. */
-struct socfpga_sdram_config {
-   u32 ctrl_cfg;
-   u32 dram_timing1;
-   u32 dram_timing2;
-   u32 dram_timing3;
-   u32 dram_timing4;
-   u32 lowpwr_timing;
-   u32 dram_odt;
-   u32 extratime1;
-   u32 dram_addrw;
-   u32 dram_if_width;
-   u32 dram_dev_width;
-   u32 dram_intr;
-   u32 lowpwr_eq;
-   u32 static_cfg;
-   u32 ctrl_width;
-   u32 cport_width;
-   u32 cport_wmap;
-   u32 cport_rmap;
-   u32 rfifo_cmap;
-   u32 wfifo_cmap;
-   u32 cport_rdwr;
-   u32 port_cfg;
-   u32 fpgaport_rst;
-   u32 fifo_cfg;
-   u32 mp_priority;
-   u32 mp_weight0;
-   u32 mp_weight1;
-   u32 mp_weight2;
-   u32 mp_weight3;
-   u32 mp_pacing0;
-   u32 mp_pacing1;
-   u32 mp_pacing2;
-   u32 mp_pacing3;
-   u32 mp_threshold0;
-   u32 mp_threshold1;
-   u32 mp_threshold2;
-   u32 phy_ctrl0;
-};
-
-struct socfpga_sdram_rw_mgr_config {
-   u8  activate_0_and_1;
-   u8  activate_0_and_1_wait1;
-   u8  activate_0_and_1_wait2;
-   u8  activate_1;
-   u8  clear_dqs_enable;
-   u8  guaranteed_read;
-   u8  guaranteed_read_cont;
-   u8  guaranteed_write;
-   u8  guaranteed_write_wait0;
-   u8  guaranteed_write_wait1;
-   

[U-Boot] [PATCH 03/12] ARM: socfpga: Synchronize Arria10 DTs

[Marek Vasut]

Synchronize Altera Arria 10 DT sources with Linux 4.16.3 as of commit
ef8216d28a5920022cddcb694d2d75bd1f0035ca

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
---
 arch/arm/dts/socfpga_arria10.dtsi| 594 +--
 arch/arm/dts/socfpga_arria10_socdk.dtsi  | 167 
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts |  45 +-
 3 files changed, 482 insertions(+), 324 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk.dtsi

diff --git a/arch/arm/dts/socfpga_arria10.dtsi 
b/arch/arm/dts/socfpga_arria10.dtsi
index abfd0bc4f8..b51febda9c 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright Altera Corporation (C) 2014-2017. All rights reserved.
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms and conditions of the GNU General Public License,
@@ -14,7 +14,6 @@
  * this program.  If not, see .
  */
 
-#include "skeleton.dtsi"
 #include 
 #include 
 
@@ -22,29 +21,10 @@
#address-cells = <1>;
#size-cells = <1>;
 
-   aliases {
-   ethernet0 = 
-   ethernet1 = 
-   ethernet2 = 
-   serial0 = 
-   serial1 = 
-   timer0 = 
-   timer1 = 
-   timer2 = 
-   timer3 = 
-   spi0 = 
-   spi1 = 
-   };
-
-   memory {
-   name = "memory";
-   device_type = "memory";
-   reg = <0x0 0x4000>; /* 1GB */
-   };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
+   enable-method = "altr,socfpga-a10-smp";
 
cpu@0 {
compatible = "arm,cortex-a9";
@@ -102,321 +82,335 @@
};
};
 
-   clkmgr@ffd04000 {
-   compatible = "altr,clk-mgr";
-   reg = <0xffd04000 0x1000>;
-   reg-names = "soc_clock_manager_OCP_SLV";
-
-   clocks {
-   #address-cells = <1>;
-   #size-cells = <0>;
-
-   cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   };
-
-   cb_intosc_ls_clk: cb_intosc_ls_clk {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   };
+   base_fpga_region {
+   #address-cells = <0x1>;
+   #size-cells = <0x1>;
 
-   f2s_free_clk: f2s_free_clk {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   };
+   compatible = "fpga-region";
+   fpga-mgr = <_mgr>;
+   };
 
-   osc1: osc1 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   };
+   clkmgr@ffd04000 {
+   compatible = "altr,clk-mgr";
+   reg = <0xffd04000 0x1000>;
 
-   main_pll: main_pll {
+   clocks {
#address-cells = <1>;
#size-cells = <0>;
-   #clock-cells = <0>;
-   compatible = 
"altr,socfpga-a10-pll-clock";
-   clocks = <>, <_intosc_ls_clk>,
-<_free_clk>;
-   reg = <0x40>;
 
-   main_mpu_base_clk: main_mpu_base_clk {
+   cb_intosc_hs_div2_clk: 
cb_intosc_hs_div2_clk {
#clock-cells = <0>;
-   compatible = 
"altr,socfpga-a10-perip-clk";
-   clocks = <_pll>;
-   div-reg = <0x140 0 11>;
+   compatible = "fixed-clock";
};
 
-   main_noc_base_clk: main_noc_base_clk {
+   cb_intosc_ls_clk: cb_intosc_ls_clk {
 

[U-Boot] [PATCH 04/12] ARM: socfpga: Synchronize Arria10 SoCDK SDMMC handoff

[Marek Vasut]

Regenerate Altera Arria 10 SoCDK SDMMC handoff file using latest
Quartus to get the new set of clock bindings in.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
---
 .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi   | 734 +
 1 file changed, 302 insertions(+), 432 deletions(-)

diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi 
b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
index b6939b011a..39009654d9 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
@@ -14,467 +14,337 @@
 #include "socfpga_arria10.dtsi"
 
 / {
-   model = "Altera SOCFPGA Arria 10";
-   compatible = "altr,socfpga-arria10", "altr,socfpga";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   model = "SOCFPGA Arria10 Dev Kit";  /* Bootloader setting: 
uboot.model */
 
chosen {
-   /* Bootloader setting: uboot.rbf_filename */
-   cff-file = "ghrd_10as066n2.periph.rbf";
-   early-release-fpga-config;
+   cff-file = "socfpga.rbf";   /* Bootloader setting: 
uboot.rbf_filename */
};
 
-   soc {
+   /* Clock sources */
+   clocks {
u-boot,dm-pre-reloc;
-   clkmgr@ffd04000 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   /* Clock source: altera_arria10_hps_eosc1 */
+   altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
+   u-boot,dm-pre-reloc;
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <2500>;
+   clock-output-names = "altera_arria10_hps_eosc1-clk";
+   };
+
+   /* Clock source: altera_arria10_hps_cb_intosc_ls */
+   altera_arria10_hps_cb_intosc_ls: 
altera_arria10_hps_cb_intosc_ls {
+   u-boot,dm-pre-reloc;
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <6000>;
+   clock-output-names = 
"altera_arria10_hps_cb_intosc_ls-clk";
+   };
+
+   /* Clock source: altera_arria10_hps_f2h_free */
+   altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
+   u-boot,dm-pre-reloc;
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <2>;
+   clock-output-names = "altera_arria10_hps_f2h_free-clk";
+   };
+   };
+
+   /*
+* Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver
+* Version: 1.0
+* Binding: device
+*/
+   i_clk_mgr: clock_manager@0xffd04000 {
+   u-boot,dm-pre-reloc;
+   compatible = "altr,socfpga-a10-clk-init";
+   reg = <0xffd04000 0x0200>;
+   reg-names = "soc_clock_manager_OCP_SLV";
+
+   /* Address Block: 
soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */
+   mainpll {
u-boot,dm-pre-reloc;
-   clocks {
-   u-boot,dm-pre-reloc;
-   osc1 {
-   u-boot,dm-pre-reloc;
-   clock-frequency = <2500>;
-   clock-output-names = 
"altera_arria10_hps_eosc1-clk";
-   };
+   vco0-psrc = <0>;/* Field: vco0.psrc */
+   vco1-denom = <1>;   /* Field: vco1.denom */
+   vco1-numer = <191>; /* Field: vco1.numer */
+   mpuclk-cnt = <0>;   /* Field: mpuclk.cnt */
+   mpuclk-src = <0>;   /* Field: mpuclk.src */
+   nocclk-cnt = <0>;   /* Field: nocclk.cnt */
+   nocclk-src = <0>;   /* Field: nocclk.src */
+   cntr2clk-cnt = <900>;   /* Field: cntr2clk.cnt */
+   cntr3clk-cnt = <900>;   /* Field: cntr3clk.cnt */
+   cntr4clk-cnt = <900>;   /* Field: cntr4clk.cnt */
+   cntr5clk-cnt = <900>;   /* Field: cntr5clk.cnt */
+   cntr6clk-cnt = <900>;   /* Field: cntr6clk.cnt */
+   cntr7clk-cnt = <900>;   /* Field: cntr7clk.cnt */
+   cntr7clk-src = <0>; /* Field: cntr7clk.src */
+   cntr8clk-cnt = <900>;   /* Field: cntr8clk.cnt */
+   cntr9clk-cnt = <900>;   /* Field: cntr9clk.cnt */
+   cntr9clk-src = <0>; /* Field: cntr9clk.src */
+   

[U-Boot] [PATCH 02/12] ARM: socfpga: Sort the DT Makefile

[Marek Vasut]

Sort the Makefile entries, no functional change.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
---
 arch/arm/dts/Makefile | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f94940a7dd..b29ecb0060 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -182,20 +182,20 @@ dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=  \
-   socfpga_arria10_socdk_sdmmc.dtb \
socfpga_arria5_socdk.dtb\
+   socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_is1.dtb\
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_socdk.dtb  \
socfpga_cyclone5_dbm_soc1.dtb   \
-   socfpga_cyclone5_de0_nano_soc.dtb   \
+   socfpga_cyclone5_de0_nano_soc.dtb   \
socfpga_cyclone5_de1_soc.dtb\
socfpga_cyclone5_de10_nano.dtb  \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb   \
socfpga_cyclone5_sr1500.dtb \
-   socfpga_stratix10_socdk.dtb \
-   socfpga_cyclone5_vining_fpga.dtb
+   socfpga_cyclone5_vining_fpga.dtb\
+   socfpga_stratix10_socdk.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \
dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
-- 
2.16.2

___
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U-Boot@lists.denx.de
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[U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser

[Marek Vasut]

The A10 clock manager parsed DT bindings generated by Quartus the
bsp-editor to configure the A10 clocks. Sadly, those DT bindings
changed at some point. The clock manager patch used the old ones,
this patch replaces the bindings parser with one for the new set.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
---
 arch/arm/mach-socfpga/clock_manager_arria10.c  | 158 ++---
 .../include/mach/clock_manager_arria10.h   |   2 +-
 2 files changed, 111 insertions(+), 49 deletions(-)

diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c 
b/arch/arm/mach-socfpga/clock_manager_arria10.c
index 4ee6a82b5f..defa2f6261 100644
--- a/arch/arm/mach-socfpga/clock_manager_arria10.c
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -9,6 +9,9 @@
 #include 
 #include 
 
+static const struct socfpga_clock_manager *clock_manager_base =
+   (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
+
 static u32 eosc1_hz;
 static u32 cb_intosc_hz;
 static u32 f2s_free_hz;
@@ -64,89 +67,150 @@ struct perpll_cfg {
u32 cntr8clk_cnt;
u32 cntr8clk_src;
u32 cntr9clk_cnt;
+   u32 cntr9clk_src;
u32 emacctl_emac0sel;
u32 emacctl_emac1sel;
u32 emacctl_emac2sel;
u32 gpiodiv_gpiodbclk;
 };
 
-struct alteragrp_cfg {
-   u32 nocclk;
-   u32 mpuclk;
+struct strtou32 {
+   const char *str;
+   const u32 val;
 };
 
-static const struct socfpga_clock_manager *clock_manager_base =
-   (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
+static const struct strtou32 mainpll_cfg_tab[] = {
+   { "vco0-psrc", offsetof(struct mainpll_cfg, vco0_psrc) },
+   { "vco1-denom", offsetof(struct mainpll_cfg, vco1_denom) },
+   { "vco1-numer", offsetof(struct mainpll_cfg, vco1_numer) },
+   { "mpuclk-cnt", offsetof(struct mainpll_cfg, mpuclk_cnt) },
+   { "mpuclk-src", offsetof(struct mainpll_cfg, mpuclk_src) },
+   { "nocclk-cnt", offsetof(struct mainpll_cfg, nocclk_cnt) },
+   { "nocclk-src", offsetof(struct mainpll_cfg, nocclk_src) },
+   { "cntr2clk-cnt", offsetof(struct mainpll_cfg, cntr2clk_cnt) },
+   { "cntr3clk-cnt", offsetof(struct mainpll_cfg, cntr3clk_cnt) },
+   { "cntr4clk-cnt", offsetof(struct mainpll_cfg, cntr4clk_cnt) },
+   { "cntr5clk-cnt", offsetof(struct mainpll_cfg, cntr5clk_cnt) },
+   { "cntr6clk-cnt", offsetof(struct mainpll_cfg, cntr6clk_cnt) },
+   { "cntr7clk-cnt", offsetof(struct mainpll_cfg, cntr7clk_cnt) },
+   { "cntr7clk-src", offsetof(struct mainpll_cfg, cntr7clk_src) },
+   { "cntr8clk-cnt", offsetof(struct mainpll_cfg, cntr8clk_cnt) },
+   { "cntr9clk-cnt", offsetof(struct mainpll_cfg, cntr9clk_cnt) },
+   { "cntr9clk-src", offsetof(struct mainpll_cfg, cntr9clk_src) },
+   { "cntr15clk-cnt", offsetof(struct mainpll_cfg, cntr15clk_cnt) },
+   { "nocdiv-l4mainclk", offsetof(struct mainpll_cfg, nocdiv_l4mainclk) },
+   { "nocdiv-l4mpclk", offsetof(struct mainpll_cfg, nocdiv_l4mpclk) },
+   { "nocdiv-l4spclk", offsetof(struct mainpll_cfg, nocdiv_l4spclk) },
+   { "nocdiv-csatclk", offsetof(struct mainpll_cfg, nocdiv_csatclk) },
+   { "nocdiv-cstraceclk", offsetof(struct mainpll_cfg, nocdiv_cstraceclk) 
},
+   { "nocdiv-cspdbgclk", offsetof(struct mainpll_cfg, nocdiv_cspdbclk) },
+};
+
+static const struct strtou32 perpll_cfg_tab[] = {
+   { "vco0-psrc", offsetof(struct perpll_cfg, vco0_psrc) },
+   { "vco1-denom", offsetof(struct perpll_cfg, vco1_denom) },
+   { "vco1-numer", offsetof(struct perpll_cfg, vco1_numer) },
+   { "cntr2clk-cnt", offsetof(struct perpll_cfg, cntr2clk_cnt) },
+   { "cntr2clk-src", offsetof(struct perpll_cfg, cntr2clk_src) },
+   { "cntr3clk-cnt", offsetof(struct perpll_cfg, cntr3clk_cnt) },
+   { "cntr3clk-src", offsetof(struct perpll_cfg, cntr3clk_src) },
+   { "cntr4clk-cnt", offsetof(struct perpll_cfg, cntr4clk_cnt) },
+   { "cntr4clk-src", offsetof(struct perpll_cfg, cntr4clk_src) },
+   { "cntr5clk-cnt", offsetof(struct perpll_cfg, cntr5clk_cnt) },
+   { "cntr5clk-src", offsetof(struct perpll_cfg, cntr5clk_src) },
+   { "cntr6clk-cnt", offsetof(struct perpll_cfg, cntr6clk_cnt) },
+   { "cntr6clk-src", offsetof(struct perpll_cfg, cntr6clk_src) },
+   { "cntr7clk-cnt", offsetof(struct perpll_cfg, cntr7clk_cnt) },
+   { "cntr8clk-cnt", offsetof(struct perpll_cfg, cntr8clk_cnt) },
+   { "cntr8clk-src", offsetof(struct perpll_cfg, cntr8clk_src) },
+   { "cntr9clk-cnt", offsetof(struct perpll_cfg, cntr9clk_cnt) },
+   { "emacctl-emac0sel", offsetof(struct perpll_cfg, emacctl_emac0sel) },
+   { "emacctl-emac1sel", offsetof(struct perpll_cfg, emacctl_emac1sel) },
+   { "emacctl-emac2sel", offsetof(struct perpll_cfg, emacctl_emac2sel) },
+   { "gpiodiv-gpiodbclk", offsetof(struct perpll_cfg, gpiodiv_gpiodbclk) },
+};
+
+static const 

[U-Boot] [PATCH] ARM: socfpga: Convert to DM serial

[Marek Vasut]

Pull the serial port configuration from DT and use DM serial instead
of having the serial configuration in two places, DT and board config.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
---
 arch/arm/Kconfig | 3 +++
 arch/arm/dts/socfpga.dtsi| 2 ++
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 1 +
 include/configs/socfpga_common.h | 8 
 4 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 532aa41a87..2012ac6410 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -737,6 +737,7 @@ config ARCH_SOCFPGA
select ARCH_MISC_INIT
select CPU_V7A
select DM
+   select DM_SERIAL
select ENABLE_ARM_SOC_BOOT0_HOOK
select OF_CONTROL
select SPL_LIBCOMMON_SUPPORT
@@ -746,11 +747,13 @@ config ARCH_SOCFPGA
select SPL_NAND_SUPPORT if SPL_NAND_DENALI
select SPL_OF_CONTROL
select SPL_SERIAL_SUPPORT
+   select SPL_DM_SERIAL
select SPL_SPI_FLASH_SUPPORT if SPL_SPI_SUPPORT
select SPL_SPI_SUPPORT if DM_SPI
select SPL_WATCHDOG_SUPPORT
select SUPPORT_SPL
select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
+   select SYS_NS16550
select SYS_THUMB_BUILD
imply CMD_MTDPARTS
imply CRC32_VERIFY
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index e64127fcb2..314449478d 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -737,6 +737,7 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <_sp_clk>;
+   clock-frequency = <1>;
};
 
uart1: serial1@ffc03000 {
@@ -746,6 +747,7 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <_sp_clk>;
+   clock-frequency = <1>;
};
 
rst: rstmgr@ffd05000 {
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts 
b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
index b573d0e658..06b61cb0af 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -24,6 +24,7 @@
 };
 
  {
+   clock-frequency = <5000>;
u-boot,dm-pre-reloc;
status = "okay";
 };
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 54b9edc97c..a60da85499 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -173,14 +173,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  * Serial Driver
  */
 #define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE-4
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#define CONFIG_SYS_NS16550_COM1SOCFPGA_UART0_ADDRESS
-#define CONFIG_SYS_NS16550_CLK 1
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#define CONFIG_SYS_NS16550_COM1SOCFPGA_UART1_ADDRESS
-#define CONFIG_SYS_NS16550_CLK 5000
-#endif
 
 /*
  * USB
-- 
2.16.2

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[U-Boot] [PATCH] ARM: socfpga: Zap CONFIG_SOCFPGA_VIRTUAL_TARGET

[Marek Vasut]

This was never used, is not used anywhere and is just in the way
by adding annoying ifdeffery. Get rid of it.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
---
 arch/arm/mach-socfpga/include/mach/reset_manager.h |  4 
 arch/arm/mach-socfpga/misc_gen5.c  |  4 
 arch/arm/mach-socfpga/reset_manager_arria10.c  |  8 
 arch/arm/mach-socfpga/reset_manager_gen5.c |  9 -
 arch/arm/mach-socfpga/spl.c|  5 -
 include/configs/socfpga_common.h   | 13 ++---
 scripts/config_whitelist.txt   |  1 -
 7 files changed, 2 insertions(+), 42 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 7cfed7d001..d3ae80bc27 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -11,11 +11,7 @@ void reset_cpu(ulong addr);
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
-#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
-#else
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
-#endif
 
 /*
  * Define a reset identifier, from which a permodrst bank ID
diff --git a/arch/arm/mach-socfpga/misc_gen5.c 
b/arch/arm/mach-socfpga/misc_gen5.c
index b9db3aef09..efec58d555 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -264,12 +264,8 @@ int arch_early_init_r(void)
setbits_le32(_regs->sacr, 0xfff);
 
/* Configure the L2 controller to make SDRAM start at 0 */
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-   writel(0x2, _regs->remap);
-#else
writel(0x1, _regs->remap);   /* remap.mpuzero */
writel(0x1, >pl310_addr_filter_start);
-#endif
 
/* Add device descriptor to FPGA device table */
socfpga_fpga_add();
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c 
b/arch/arm/mach-socfpga/reset_manager_arria10.c
index 99e2b8e6e6..b4434f2ded 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -316,13 +316,6 @@ void socfpga_per_reset_all(void)
setbits_le32(_manager_base->per0modrst, mask_ecc_ocp);
 }
 
-#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-int socfpga_bridges_reset(void)
-{
-   /* For SoCFPGA-VT, this is NOP. */
-   return 0;
-}
-#else
 int socfpga_bridges_reset(void)
 {
int ret;
@@ -379,4 +372,3 @@ int socfpga_bridges_reset(void)
 
return 0;
 }
-#endif
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c 
b/arch/arm/mach-socfpga/reset_manager_gen5.c
index b261a94486..25baef79bc 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -69,14 +69,6 @@ void reset_deassert_peripherals_handoff(void)
writel(0, _manager_base->per_mod_reset);
 }
 
-#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-void socfpga_bridges_reset(int enable)
-{
-   /* For SoCFPGA-VT, this is NOP. */
-   return;
-}
-#else
-
 #define L3REGS_REMAP_LWHPS2FPGA_MASK   0x10
 #define L3REGS_REMAP_HPS2FPGA_MASK 0x08
 #define L3REGS_REMAP_OCRAM_MASK0x01
@@ -110,4 +102,3 @@ void socfpga_bridges_reset(int enable)
}
return;
 }
-#endif
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 4b86eadd81..515832031a 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -78,9 +78,7 @@ static void socfpga_nic301_slave_ns(void)
 
 void board_init_f(ulong dummy)
 {
-#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
const struct cm_config *cm_default_cfg = cm_get_default_config();
-#endif
unsigned long sdram_size;
unsigned long reg;
 
@@ -107,7 +105,6 @@ void board_init_f(ulong dummy)
writel(0x1, _regs->remap);   /* remap.mpuzero */
writel(0x1, >pl310_addr_filter_start);
 
-#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
debug("Freezing all I/O banks\n");
/* freeze all IO banks */
sys_mgr_frzctrl_freeze_req();
@@ -142,8 +139,6 @@ void board_init_f(ulong dummy)
sysmgr_pinmux_init();
sysmgr_config_warmrstcfgio(0);
 
-#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
-
/* De-assert reset for peripherals and bridges based on handoff */
reset_deassert_peripherals_handoff();
socfpga_bridges_reset(0);
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index cb67d539b1..54b9edc97c 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -5,9 +5,6 @@
 #ifndef __CONFIG_SOCFPGA_COMMON_H__
 #define __CONFIG_SOCFPGA_COMMON_H__
 
-/* Virtual target or real hardware */
-#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
-
 /*
  * High level configuration
  */
@@ -76,7 +73,7 @@
 /*
  * Ethernet on SoC (EMAC)
  */
-#if defined(CONFIG_CMD_NET) && 

[U-Boot] [PATCH] ARM: socfpga: Clean up Kconfig entries

[Marek Vasut]

Shuffle the default Kconfig entries around so it is not such a mess.
No functional change.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
---
 arch/arm/Kconfig  | 20 +++-
 arch/arm/mach-socfpga/Kconfig | 30 --
 2 files changed, 15 insertions(+), 35 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c9d6e0a424..532aa41a87 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -733,14 +733,24 @@ config ARCH_SNAPDRAGON
 
 config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
+   select ARCH_EARLY_INIT_R
+   select ARCH_MISC_INIT
select CPU_V7A
-   select SUPPORT_SPL
-   select OF_CONTROL
-   select SPL_OF_CONTROL
select DM
select ENABLE_ARM_SOC_BOOT0_HOOK
-   select ARCH_EARLY_INIT_R
-   select ARCH_MISC_INIT
+   select OF_CONTROL
+   select SPL_LIBCOMMON_SUPPORT
+   select SPL_LIBDISK_SUPPORT
+   select SPL_LIBGENERIC_SUPPORT
+   select SPL_MMC_SUPPORT if DM_MMC
+   select SPL_NAND_SUPPORT if SPL_NAND_DENALI
+   select SPL_OF_CONTROL
+   select SPL_SERIAL_SUPPORT
+   select SPL_SPI_FLASH_SUPPORT if SPL_SPI_SUPPORT
+   select SPL_SPI_SUPPORT if DM_SPI
+   select SPL_WATCHDOG_SUPPORT
+   select SUPPORT_SPL
+   select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
select SYS_THUMB_BUILD
imply CMD_MTDPARTS
imply CRC32_VERIFY
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index afc38d5da9..824c9fc2ba 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -1,35 +1,5 @@
 if ARCH_SOCFPGA
 
-config SPL_LIBCOMMON_SUPPORT
-   default y
-
-config SPL_LIBDISK_SUPPORT
-   default y
-
-config SPL_LIBGENERIC_SUPPORT
-   default y
-
-config SPL_MMC_SUPPORT
-   default y if DM_MMC
-
-config SPL_NAND_SUPPORT
-   default y if SPL_NAND_DENALI
-
-config SPL_SERIAL_SUPPORT
-   default y
-
-config SPL_SPI_FLASH_SUPPORT
-   default y if SPL_SPI_SUPPORT
-
-config SPL_SPI_SUPPORT
-   default y if DM_SPI
-
-config SPL_WATCHDOG_SUPPORT
-   default y
-
-config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
-   default y
-
 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
default 0xa2
 
-- 
2.16.2

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[U-Boot] [PATCH] ARM: socfpga: Put stack at the end of SRAM

[Marek Vasut]

The global data are in the .data section, so there's no point in
reserving any space for it above stack. Put stack at the end of
SRAM.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
---
 include/configs/socfpga_common.h | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 4de2aa7929..cb67d539b1 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -35,10 +35,8 @@
 #define CONFIG_SYS_INIT_RAM_ADDR   0xFFE0
 #define CONFIG_SYS_INIT_RAM_SIZE   0x4 /* 256KB */
 #endif
-#define CONFIG_SYS_INIT_SP_OFFSET  \
-   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR\
-   (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+   (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
 
 #define CONFIG_SYS_SDRAM_BASE  PHYS_SDRAM_1
 
-- 
2.16.2

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[U-Boot] [PATCH] fdt: Add another Altera Arria10 clock init compatible

[Marek Vasut]

The DT bindings for the Arria10 clock init have changed, add another
compatible to make them work with U-Boot until a proper clock driver
gets written.

Signed-off-by: Marek Vasut 
Cc: Tom Rini 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
---
 include/fdtdec.h | 1 +
 lib/fdtdec.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 5456a17d1a..c15b2a04a7 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -160,6 +160,7 @@ enum fdt_compat_id {
COMPAT_ALTERA_SOCFPGA_F2SDR2,   /* SoCFPGA fpga2SDRAM2 bridge */
COMPAT_ALTERA_SOCFPGA_FPGA0,/* SOCFPGA FPGA manager */
COMPAT_ALTERA_SOCFPGA_NOC,  /* SOCFPGA Arria 10 NOC */
+   COMPAT_ALTERA_SOCFPGA_CLK_INIT, /* SOCFPGA Arria 10 clk init */
 
COMPAT_COUNT,
 };
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 69bf12623e..f4e8dbf699 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -72,6 +72,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
COMPAT(ALTERA_SOCFPGA_FPGA0, "altr,socfpga-a10-fpga-mgr"),
COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"),
+   COMPAT(ALTERA_SOCFPGA_CLK_INIT, "altr,socfpga-a10-clk-init")
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
-- 
2.16.2

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[U-Boot] [PATCH] spl: fit: Add support for loading FPGA bitstream

[Marek Vasut]

Add support for loading FPGA into the SPL fitImage support. The
mechanism is flexible and allows user to override the actual
function for loading the FPGA itself. This is because on some
systems, the FPGA must be programmed to allow DRAM access, so
loading the full fitImage may not be possible if it contains
the bitstream. Instead, the spl_load_fpga_image() provides all
the tools to load the bitstream in parts while programming it
into the FPGA.

Signed-off-by: Marek Vasut 
Cc: Tom Rini 
---
 common/spl/spl_fit.c | 45 +
 1 file changed, 37 insertions(+), 8 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index e9acf4f3c2..40531f97ed 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -140,6 +140,14 @@ static int get_aligned_image_size(struct spl_load_info 
*info, int data_size,
return (data_size + info->bl_len - 1) / info->bl_len;
 }
 
+#ifdef CONFIG_SPL_FPGA_SUPPORT
+__weak int spl_load_fpga_image(struct spl_load_info *info, size_t length,
+  int nr_sectors, int sector_offset)
+{
+   return 0;
+}
+#endif
+
 /**
  * spl_load_fit_image(): load the image described in a certain FIT node
  * @info:  points to information about the device to load data from
@@ -161,7 +169,7 @@ static int spl_load_fit_image(struct spl_load_info *info, 
ulong sector,
  void *fit, ulong base_offset, int node,
  struct spl_image_info *image_info)
 {
-   int offset;
+   int offset, sector_offset;
size_t length;
int len;
ulong size;
@@ -177,16 +185,16 @@ static int spl_load_fit_image(struct spl_load_info *info, 
ulong sector,
int ret;
 #endif
 
+   if (fit_image_get_type(fit, node, ))
+   puts("Cannot get image type.\n");
+   else
+   debug("%s ", genimg_get_type_name(type));
+
if (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP)) {
if (fit_image_get_comp(fit, node, _comp))
puts("Cannot get image compression format.\n");
else
debug("%s ", genimg_get_comp_name(image_comp));
-
-   if (fit_image_get_type(fit, node, ))
-   puts("Cannot get image type.\n");
-   else
-   debug("%s ", genimg_get_type_name(type));
}
 
if (fit_image_get_load(fit, node, _addr))
@@ -209,9 +217,16 @@ static int spl_load_fit_image(struct spl_load_info *info, 
ulong sector,
 
overhead = get_aligned_image_overhead(info, offset);
nr_sectors = get_aligned_image_size(info, length, offset);
+   sector_offset = sector + get_aligned_image_offset(info, offset);
 
-   if (info->read(info,
-  sector + get_aligned_image_offset(info, offset),
+#ifdef CONFIG_SPL_FPGA_SUPPORT
+   if (type == IH_TYPE_FPGA) {
+   return spl_load_fpga_image(info, length, nr_sectors,
+  sector_offset);
+   }
+#endif
+
+   if (info->read(info, sector_offset,
   nr_sectors, (void *)load_ptr) != nr_sectors)
return -EIO;
 
@@ -387,6 +402,20 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
return -1;
}
 
+#ifdef CONFIG_SPL_FPGA_SUPPORT
+   node = spl_fit_get_image_node(fit, images, "fpga", 0);
+   if (node >= 0) {
+   /* Load the image and set up the spl_image structure */
+   ret = spl_load_fit_image(info, sector, fit, base_offset, node,
+spl_image);
+   if (ret) {
+   printf("%s: Cannot load the FPGA: %i\n", __func__, ret);
+   return ret;
+   }
+   node = -1;
+   }
+#endif
+
/*
 * Find the U-Boot image using the following search order:
 *   - start at 'firmware' (e.g. an ARM Trusted Firmware)
-- 
2.16.2

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Re: [U-Boot] [PATCH v2 1/6] kconfig: re-sync with Linux 4.17-rc4

[Petr Vorel]

Hi Eugeniu,

> Hello Petr,

> On Sat, May 12, 2018 at 08:25:56PM +0200, Petr Vorel wrote:

> > When applied all 6 patches, I got several errors (see bellow).
> > I tested in on 2 distros (Debian unstable and openSUSE Tumbleweed).
> > The code I applied is here, did I make error when applying patches?
> > https://github.com/pevik/u-boot/tree/eugeniu/kconfig.v2

> I checked your branch and got some interesting conclusions.
> Here is the diff between my and your version of commit ("kconfig:
> re-sync with Linux 4.17-rc4"):

> $ git diff  
>  scripts/kconfig/tests/auto_submenu/expected_stdout| 14 +++---
>  scripts/kconfig/tests/choice/oldask0_expected_stdout  | 14 +++---
>  scripts/kconfig/tests/choice/oldask1_expected_stdout  | 12 ++--
>  scripts/kconfig/tests/new_choice_with_dep/expected_stdout |  4 ++--
>  4 files changed, 22 insertions(+), 22 deletions(-)

> Here is the same diff ignoring whitespace:

> $ git diff -w  
>  scripts/kconfig/tests/auto_submenu/expected_stdout| 0
>  scripts/kconfig/tests/choice/oldask0_expected_stdout  | 0
>  scripts/kconfig/tests/choice/oldask1_expected_stdout  | 0
>  scripts/kconfig/tests/new_choice_with_dep/expected_stdout | 0
>  4 files changed, 0 insertions(+), 0 deletions(-)

> So, it seems like all the trailing white-space from above files
> disappeared on your branch, after applying the patches from the
> email client (who did this?...).
OK, my fault, I'm sorry. Applying first patch as 'git am --whitespace=warn 
1.mbox' fixes
that => make testconfig works.

Yes I applied patches with mutt (I usually use pwclient, but somehow I didn't 
find your v2
in patchwork [1], nor even in ML [2]. Have I overlook something.

[1] https://patchwork.ozlabs.org/project/uboot/list/
[2] https://lists.denx.de/pipermail/u-boot/2018-May/date.html


Kind regards,
Petr

> I didn't expect that trailing white-space to be of any value for the
> test results, but it turns out it is! With the whitespace removed, I can
> also reproduce the failures of "make testconfig".

> I am not familiar with pytest, but, based on what we see here, it looks
> like every single character stored in *xpected_stdout files (including
> whitespace at the end of lines) matters for the test to pass.

> I wonder if Kconfig could avoid printing whitespace in command line
> user dialogs. Then maybe those space characters could be removed from
> the "*xpected_stdout" files.

> Masahiro?

> Thanks again!

> Best regards,
> Eugeniu.
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Re: [U-Boot] Beaglebone Black U-boot won't buid - THUMB instruction issue

[Måns Rullgård]

John Babrick  writes:

> Hello - I am trying to work through the book "Mastering Embedded Linux
> Programming" by Chris Simmonds, and trying to work through building u-boot
> after having built the cross toolchain. I am running into an error when I
> try to build u-boot, any ideas?
>
> johann@mars:~/uboot-work/u-boot$ make
> CROSS_COMPILE=arm-cortex_a8-linux-gnueabihf- am335x_evm_defconfig
> #
> # configuration written to .config
> #
> johann@mars:~/uboot-work/u-boot$ make
> CROSS_COMPILE=arm-cortex_a8-linux-gnueabihf-
> scripts/kconfig/conf  --silentoldconfig Kconfig
>   CHK include/config.h
>   UPD include/config.h
>   CFG u-boot.cfg
>   GEN include/autoconf.mk
>   GEN include/autoconf.mk.dep
>   CFG spl/u-boot.cfg
>   GEN spl/include/autoconf.mk
>   CHK include/config/uboot.release
>   CHK include/generated/version_autogenerated.h
>   CHK include/generated/timestamp_autogenerated.h
>   UPD include/generated/timestamp_autogenerated.h
> *  CC  lib/asm-offsets.s*
> *cc1: warning: target CPU does not support THUMB instructions*
> *  CHK include/generated/generic-asm-offsets.h*
> *  CC  arch/arm/lib/asm-offsets.s*
> *cc1: warning: target CPU does not support THUMB instructions*
>   CHK include/generated/asm-offsets.h
>   HOSTCC  scripts/dtc/dtc.o
>   HOSTCC  scripts/dtc/flattree.o
>   HOSTCC  scripts/dtc/fstree.o
>   HOSTCC  scripts/dtc/data.o
>   HOSTCC  scripts/dtc/livetree.o
>   HOSTCC  scripts/dtc/treesource.o
>   HOSTCC  scripts/dtc/srcpos.o
>   HOSTCC  scripts/dtc/checks.o
>   HOSTCC  scripts/dtc/util.o
>   SHIPPED scripts/dtc/dtc-lexer.lex.c
>   SHIPPED scripts/dtc/dtc-parser.tab.h
>   HOSTCC  scripts/dtc/dtc-lexer.lex.o
>   SHIPPED scripts/dtc/dtc-parser.tab.c
>   HOSTCC  scripts/dtc/dtc-parser.tab.o
>   HOSTLD  scripts/dtc/dtc
>   HOSTCC  tools/mkenvimage.o
>   HOSTCC  tools/lib/crc32.o
>   HOSTLD  tools/mkenvimage
>   HOSTCC  tools/common/bootm.o
>   HOSTCC  tools/lib/fdtdec.o
>   HOSTCC  tools/fit_image.o
>   HOSTCC  tools/image-host.o
>   HOSTCC  tools/dumpimage.o
>   HOSTLD  tools/dumpimage
>   HOSTCC  tools/mkimage.o
>   HOSTLD  tools/mkimage
>   CC  arch/arm/cpu/armv7/cache_v7.o
> *cc1: warning: target CPU does not support THUMB instructions*
> *{standard input}: Assembler messages:*
> *{standard input}:42: Error: selected processor does not support `dsb sy'
> in ARM mode*
> *{standard input}:46: Error: selected processor does not support `isb sy'
> in ARM mode*
> *{standard input}:240: Error: selected processor does not support `dsb sy'
> in ARM mode*
> *{standard input}:244: Error: selected processor does not support `isb sy'
> in ARM mode*
> *{standard input}:368: Error: selected processor does not support `dsb sy'
> in ARM mode*
> *{standard input}:460: Error: selected processor does not support `dsb sy'
> in ARM mode*
> *{standard input}:464: Error: selected processor does not support `isb sy'
> in ARM mode*
> *{standard input}:594: Error: selected processor does not support `dsb sy'
> in ARM mode*
> *scripts/Makefile.build:278: recipe for target
> 'arch/arm/cpu/armv7/cache_v7.o' failed*
> make[1]: *** [arch/arm/cpu/armv7/cache_v7.o] Error 1
> Makefile:1363: recipe for target 'arch/arm/cpu/armv7' failed

I get a deluge of such errors with gcc-8.  Use gcc-7 or earlier until
someone fixes it (or fix it yourself and send a patch).

-- 
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Re: [U-Boot] [PATCH v7 06/35] musb: sunxi: Add OTG device clkgate and reset for H3/H5

[Marek Vasut]

On 05/11/2018 11:29 PM, Maxime Ripard wrote:
> On Mon, May 07, 2018 at 10:55:16PM +0200, Marek Vasut wrote:
>> On 05/07/2018 10:11 PM, Maxime Ripard wrote:
>>> On Mon, May 07, 2018 at 05:32:34PM +0200, Marek Vasut wrote:
 On 05/07/2018 04:52 PM, Maxime Ripard wrote:
> On Mon, May 07, 2018 at 01:47:43PM +0200, Marek Vasut wrote:
>> On 05/07/2018 09:33 AM, Jagan Teki wrote:
>>> Add OTG device clkgate and reset for H3/H5 through driver_data.
>>>
>>> Signed-off-by: Jagan Teki 
>>
>> Why don't you implement a clock driver for this SoC instead ?
>
> Aren't you asking a bit too much?

 I am not asking for anything, this is a question, not a request.
>>>
>>> My bad then, this definitely sounded like a request to me.
>>
>> So uh, how do I make this NOT sound like a request to you ?
>> Can you phrase it for me ?
> 
> You are in a situation of power here. Asking the exact same question
> when you are the one in power or is a peer doesn't have the same
> impact, unless you make it clear that it is an actual question and not
> some way to have it fixed.
> 
> Something like "Would switching to a proper clock driver be an
> option?" for example would have carried the message better imo, if
> this was a genuine question and not a request.

I have to admit, I prefer simple, frugal, direct and clear questions
which can be answered equally clearly rather than long essays filled
with verbal fluff.

I'll consider this, but given that I am not a native English speaker, I
cannot guarantee the result to be to everyone's satisfaction.

 I asked why not implement a clock driver and use it just like any other
 civilized modern driver would instead of digging in the clock controller
 registers from a USB framework driver (which is icky).
>>>
>>> From an absolute point of view, I agree. But we are where we are.
>>
>> Which is where exactly ?
> 
> Having to deal with code from 2012 everywhere.

This sounds like a massive generalization and an incorrect one to me *.

> Since the first post of these patches, you've asked to rework in a
> significant manner the driver already, including doing a new PHY
> driver to use the device model, and making other substantial changes
> to it.

 Well yes, because it was crap at the beginning and I don't want to see
 the crap accumulating. It has become much better since, as you can see I
 only had a few minor comments.
>>>
>>> And that's totally your role, but at the same time, the point of this
>>> series is not to fix the whole world, but rather add support for one
>>> particular SoC that is using pretty much the same design than any of
>>> our other SoCs' USB phy before. And here we are, 35 patches and
>>> counting.
>>
>> If I said "yes" to every single patch adding just a minor additional bit
>> of crap to the codebase, we'd be in the state in which we were in 2012,
>> sinking under the boatload of ifdeffery and ad-hoc solutions. So I think
>> some push is needed to avoid that situation.
> 
> I don't have any issue with the end goal, and your willingness to have
> the code ported over to new APIs. But if from one day to another every
> maintainer goes like this, this will simply not fly. This is not just
> about having just a simple clock driver, but also a pinctrl one, and
> converting all the consumer drivers to the device model, oh, and btw,
> the DM doesn't fit in the SPL anymore, so we would probably need to do
> an SPL driver as well. Probably with some painful Kconfig conversions
> all over the tree even.

You are massively exaggerating right there. I recently did such a
conversion for a platform and it didn't take nearly as much effort as
you describe and/or it could be well segmented.

> This is no longer a simple request, but some huge spaghetti changes
> that need to be done, mostly by volunteers.

I am not sure this "volunteers" argument really works in this
discussion, since this looks like a commercial contribution to me.

But if you want to discuss volunteering, did you ever consider that I
also do the USB maintaining in my free time and the bulk of
communication is random people demanding random stuff ? I also don't see
people coming up saying "oh, hey, I'll spend some of my own free time to
help out maintaining this piece of code". It tends to make people
stressed and burnt out ...

> And at some point, it just
> becomes easier to give up, fork, and just maintain our stuff like we
> were doing before. Or just stop maintaining it entirely. And I'm not
> sure either situation is something we want.
> 
> tl; dr: I'd like some moderation.

So much dramatization for a simple question which could've had equally
simple answer, really.

> Creating a new clock driver will take a lot of effort, and this really
> surprise me given that we've had strictly no feedback from you on this
> considering all the previous SoCs bringups we've done so far.

 What 

[U-Boot] [PATCH 4/7] mach-snapdragon: Fix UART clock flow

[Ramon Fried]

UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.

Signed-off-by: Ramon Fried 
---
 arch/arm/mach-snapdragon/clock-apq8016.c   | 23 +++---
 arch/arm/mach-snapdragon/clock-apq8096.c   |  4 ++--
 arch/arm/mach-snapdragon/clock-snapdragon.c| 17 +++-
 arch/arm/mach-snapdragon/clock-snapdragon.h|  9 +++--
 .../mach-snapdragon/include/mach/sysmap-apq8016.h  |  1 +
 5 files changed, 42 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-snapdragon/clock-apq8016.c 
b/arch/arm/mach-snapdragon/clock-apq8016.c
index 9c0cc1c22c..6e4a0ccb90 100644
--- a/arch/arm/mach-snapdragon/clock-apq8016.c
+++ b/arch/arm/mach-snapdragon/clock-apq8016.c
@@ -17,7 +17,6 @@
 
 /* GPLL0 clock control registers */
 #define GPLL0_STATUS_ACTIVE BIT(17)
-#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
 
 static const struct bcr_regs sdc_regs[] = {
{
@@ -36,11 +35,17 @@ static const struct bcr_regs sdc_regs[] = {
}
 };
 
-static struct gpll0_ctrl gpll0_ctrl = {
+static struct pll_vote_clk gpll0_vote_clk = {
.status = GPLL0_STATUS,
.status_bit = GPLL0_STATUS_ACTIVE,
.ena_vote = APCS_GPLL_ENA_VOTE,
-   .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
+   .vote_bit = BIT(0),
+};
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+   .cbcr_reg = BLSP1_AHB_CBCR,
+   .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
+   .vote_bit = BIT(10),
 };
 
 /* SDHCI */
@@ -55,7 +60,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, 
uint rate)
/* 800Mhz/div, gpll0 */
clk_rcg_set_rate_mnd(priv->base, _regs[slot], div, 0, 0,
 CFG_CLK_SRC_GPLL0);
-   clk_enable_gpll0(priv->base, _ctrl);
+   clk_enable_gpll0(priv->base, _vote_clk);
clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
 
return rate;
@@ -72,12 +77,16 @@ static const struct bcr_regs uart2_regs = {
 /* UART: 115200 */
 static int clk_init_uart(struct msm_clk_priv *priv)
 {
-   /* Enable iface clk */
-   clk_enable_cbc(priv->base + BLSP1_AHB_CBCR);
+   /* Enable AHB clock */
+   clk_enable_vote_clk(priv->base, _blsp1_ahb_clk);
+
/* 7372800 uart block clock @ GPLL0 */
clk_rcg_set_rate_mnd(priv->base, _regs, 1, 144, 15625,
 CFG_CLK_SRC_GPLL0);
-   clk_enable_gpll0(priv->base, _ctrl);
+
+   /* Vote for gpll0 clock */
+   clk_enable_gpll0(priv->base, _vote_clk);
+
/* Enable core clk */
clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
 
diff --git a/arch/arm/mach-snapdragon/clock-apq8096.c 
b/arch/arm/mach-snapdragon/clock-apq8096.c
index 008649a4c6..628c38785b 100644
--- a/arch/arm/mach-snapdragon/clock-apq8096.c
+++ b/arch/arm/mach-snapdragon/clock-apq8096.c
@@ -27,7 +27,7 @@ static const struct bcr_regs sdc_regs = {
.D = SDCC2_D,
 };
 
-static const struct gpll0_ctrl gpll0_ctrl = {
+static const struct pll_vote_clk gpll0_vote_clk = {
.status = GPLL0_STATUS,
.status_bit = GPLL0_STATUS_ACTIVE,
.ena_vote = APCS_GPLL_ENA_VOTE,
@@ -41,7 +41,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
clk_enable_cbc(priv->base + SDCC2_AHB_CBCR);
clk_rcg_set_rate_mnd(priv->base, _regs, div, 0, 0,
 CFG_CLK_SRC_GPLL0);
-   clk_enable_gpll0(priv->base, _ctrl);
+   clk_enable_gpll0(priv->base, _vote_clk);
clk_enable_cbc(priv->base + SDCC2_APPS_CBCR);
 
return rate;
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c 
b/arch/arm/mach-snapdragon/clock-snapdragon.c
index f738f57043..85526186c6 100644
--- a/arch/arm/mach-snapdragon/clock-snapdragon.c
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.c
@@ -30,7 +30,7 @@ void clk_enable_cbc(phys_addr_t cbcr)
;
 }
 
-void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *gpll0)
+void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0)
 {
if (readl(base + gpll0->status) & gpll0->status_bit)
return; /* clock already enabled */
@@ -41,6 +41,21 @@ void clk_enable_gpll0(phys_addr_t base, const struct 
gpll0_ctrl *gpll0)
;
 }
 
+#define BRANCH_ON_VAL (0)
+#define BRANCH_NOC_FSM_ON_VAL BIT(29)
+#define BRANCH_CHECK_MASK GENMASK(31, 28)
+
+void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk)
+{
+   u32 val;
+
+   setbits_le32(base + vclk->ena_vote, vclk->vote_bit);
+   do {
+   val = readl(base + vclk->cbcr_reg);
+   val &= BRANCH_CHECK_MASK;
+   } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL));
+}
+
 #define APPS_CMD_RGCR_UPDATE BIT(0)
 
 /* Update clock command via CMD_RGCR */
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h 
b/arch/arm/mach-snapdragon/clock-snapdragon.h
index 2cff4f8a06..3ae21099c2 100644
--- a/arch/arm/mach-snapdragon/clock-snapdragon.h
+++ 

[U-Boot] [PATCH 7/7] serial: serial_msm: added pinmux & config

[Ramon Fried]

Serial port configuration was missing from previous implementation.
It only worked because it was preconfigured by LK.
This patch configures the uart for 115200 8N1.
It also configures the pin mux for uart pins using DT bindings.

Signed-off-by: Ramon Fried 
---
 drivers/serial/serial_msm.c | 24 ++--
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index 22301c0e37..4a0a2cc450 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /* Serial registers - this driver works in uartdm mode*/
 
@@ -25,6 +26,9 @@
 #define UARTDM_RXFS 0x50 /* RX channel status register */
 #define UARTDM_RXFS_BUF_SHIFT   0x7  /* Number of bytes in the packing buffer 
*/
 #define UARTDM_RXFS_BUF_MASK0x7
+#define UARTDM_MR1  0x00
+#define UARTDM_MR2  0x04
+#define UARTDM_CSR  0xA0
 
 #define UARTDM_SR0xA4 /* Status register */
 #define UARTDM_SR_RX_READY   (1 << 0) /* Word is the receiver FIFO */
@@ -45,6 +49,10 @@
 #define UARTDM_TF   0x100 /* UART Transmit FIFO register */
 #define UARTDM_RF   0x140 /* UART Receive FIFO register */
 
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34
+#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10
+#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -179,6 +187,14 @@ static int msm_uart_clk_init(struct udevice *dev)
return 0;
 }
 
+static void uart_dm_init(struct msm_serial_data *priv)
+{
+   writel(UART_DM_CLK_RX_TX_BIT_RATE, priv->base + UARTDM_CSR);
+   writel(0x0, priv->base + UARTDM_MR1);
+   writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2);
+   writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR);
+   writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR);
+}
 static int msm_serial_probe(struct udevice *dev)
 {
struct msm_serial_data *priv = dev_get_priv(dev);
@@ -190,12 +206,8 @@ static int msm_serial_probe(struct udevice *dev)
if (msm_uart_clk_init(dev))
return -EINVAL;
 
-   if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
-   writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR);
-
-   writel(0, priv->base + UARTDM_IMR);
-   writel(UARTDM_CR_CMD_STALE_EVENT_DISABLE, priv->base + UARTDM_CR);
-   msm_serial_fetch(dev);
+   pinctrl_select_state(dev, "uart");
+   uart_dm_init(priv);
 
return 0;
 }
-- 
2.14.1

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[U-Boot] [PATCH 6/7] db410: added pinctrl node and serial bindings

[Ramon Fried]

Added TLMM pinctrl node for pin muxing & config.
Additionally, added a serial node for uart.

Signed-off-by: Ramon Fried 
---
 arch/arm/dts/dragonboard410c.dts | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index d9d5831f4f..182a865b0a 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 #include "skeleton64.dtsi"
+#include 
 
 / {
model = "Qualcomm Technologies, Inc. Dragonboard 410c";
@@ -38,6 +39,17 @@
ranges = <0x0 0x0 0x0 0x>;
compatible = "simple-bus";
 
+   pinctrl: qcom,tlmm@100 {
+   compatible = "qcom,tlmm-apq8016";
+   reg = <0x100 0x40>;
+
+   blsp1_uart: uart {
+   function = "blsp1_uart";
+   pins = "GPIO_4", "GPIO_5";
+   drive-strength = ;
+   bias-disable;
+   };
+   };
clkc: qcom,gcc@180 {
compatible = "qcom,gcc-apq8016";
reg = <0x180 0x8>;
@@ -49,6 +61,8 @@
compatible = "qcom,msm-uartdm-v1.4";
reg = <0x78b 0x200>;
clock = < 4>;
+   pinctrl-names = "uart";
+   pinctrl-0 = <_uart>;
};
 
soc_gpios: pinctrl@100 {
-- 
2.14.1

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[U-Boot] [PATCH 5/7] mach-snapdragon: Introduce pinctrl driver

[Ramon Fried]

This patch adds pinmux and pinctrl driver for TLMM
subsystem in snapdragon chipsets.
Currently, supporting only 8016, but implementation is
generic and 8096 can be added easily.

Driver is using the generic dt-bindings and doesn't
introduce any new bindings (yet).

Signed-off-by: Ramon Fried 
---
 arch/arm/mach-snapdragon/Makefile|   2 +
 arch/arm/mach-snapdragon/pinctrl-apq8016.c   | 162 +++
 arch/arm/mach-snapdragon/pinctrl-snapdragon.c| 118 +
 arch/arm/mach-snapdragon/pinctrl-snapdragon.h|  21 +++
 configs/dragonboard410c_defconfig|   5 +
 include/dt-bindings/pinctrl/pinctrl-snapdragon.h |  22 +++
 6 files changed, 330 insertions(+)
 create mode 100644 arch/arm/mach-snapdragon/pinctrl-apq8016.c
 create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.c
 create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.h
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-snapdragon.h

diff --git a/arch/arm/mach-snapdragon/Makefile 
b/arch/arm/mach-snapdragon/Makefile
index 1c23dc52cf..1d35fea912 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -6,4 +6,6 @@ obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o
 obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
 obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o
 obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
+obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-apq8016.o
+obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-snapdragon.o
 obj-y += clock-snapdragon.o
diff --git a/arch/arm/mach-snapdragon/pinctrl-apq8016.c 
b/arch/arm/mach-snapdragon/pinctrl-apq8016.c
new file mode 100644
index 00..8e57e2338c
--- /dev/null
+++ b/arch/arm/mach-snapdragon/pinctrl-apq8016.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm APQ8016 pinctrl
+ *
+ * (C) Copyright 2018 Ramon Fried 
+ *
+ */
+
+#include "pinctrl-snapdragon.h"
+#include 
+
+const char * const msm_pinctrl_pins[] = {
+   "GPIO_0",
+   "GPIO_1",
+   "GPIO_2",
+   "GPIO_3",
+   "GPIO_4",
+   "GPIO_5",
+   "GPIO_6",
+   "GPIO_7",
+   "GPIO_8",
+   "GPIO_9",
+   "GPIO_10",
+   "GPIO_11",
+   "GPIO_12",
+   "GPIO_13",
+   "GPIO_14",
+   "GPIO_15",
+   "GPIO_16",
+   "GPIO_17",
+   "GPIO_18",
+   "GPIO_19",
+   "GPIO_20",
+   "GPIO_21",
+   "GPIO_22",
+   "GPIO_23",
+   "GPIO_24",
+   "GPIO_25",
+   "GPIO_26",
+   "GPIO_27",
+   "GPIO_28",
+   "GPIO_29",
+   "GPIO_30",
+   "GPIO_31",
+   "GPIO_32",
+   "GPIO_33",
+   "GPIO_34",
+   "GPIO_35",
+   "GPIO_36",
+   "GPIO_37",
+   "GPIO_38",
+   "GPIO_39",
+   "GPIO_40",
+   "GPIO_41",
+   "GPIO_42",
+   "GPIO_43",
+   "GPIO_44",
+   "GPIO_45",
+   "GPIO_46",
+   "GPIO_47",
+   "GPIO_48",
+   "GPIO_49",
+   "GPIO_50",
+   "GPIO_51",
+   "GPIO_52",
+   "GPIO_53",
+   "GPIO_54",
+   "GPIO_55",
+   "GPIO_56",
+   "GPIO_57",
+   "GPIO_58",
+   "GPIO_59",
+   "GPIO_60",
+   "GPIO_61",
+   "GPIO_62",
+   "GPIO_63",
+   "GPIO_64",
+   "GPIO_65",
+   "GPIO_66",
+   "GPIO_67",
+   "GPIO_68",
+   "GPIO_69",
+   "GPIO_70",
+   "GPIO_71",
+   "GPIO_72",
+   "GPIO_73",
+   "GPIO_74",
+   "GPIO_75",
+   "GPIO_76",
+   "GPIO_77",
+   "GPIO_78",
+   "GPIO_79",
+   "GPIO_80",
+   "GPIO_81",
+   "GPIO_82",
+   "GPIO_83",
+   "GPIO_84",
+   "GPIO_85",
+   "GPIO_86",
+   "GPIO_87",
+   "GPIO_88",
+   "GPIO_89",
+   "GPIO_90",
+   "GPIO_91",
+   "GPIO_92",
+   "GPIO_93",
+   "GPIO_94",
+   "GPIO_95",
+   "GPIO_96",
+   "GPIO_97",
+   "GPIO_98",
+   "GPIO_99",
+   "GPIO_100",
+   "GPIO_101",
+   "GPIO_102",
+   "GPIO_103",
+   "GPIO_104",
+   "GPIO_105",
+   "GPIO_106",
+   "GPIO_107",
+   "GPIO_108",
+   "GPIO_109",
+   "GPIO_110",
+   "GPIO_111",
+   "GPIO_112",
+   "GPIO_113",
+   "GPIO_114",
+   "GPIO_115",
+   "GPIO_116",
+   "GPIO_117",
+   "GPIO_118",
+   "GPIO_119",
+   "GPIO_120",
+   "GPIO_121",
+   "GPIO_122",
+   "GPIO_123",
+   "GPIO_124",
+   "GPIO_125",
+   "GPIO_126",
+   "GPIO_127",
+   "GPIO_128",
+   "GPIO_129",
+   "SDC1_CLK",
+   "SDC1_CMD",
+   "SDC1_DATA",
+   "SDC2_CLK",
+   "SDC2_CMD",
+   "SDC2_DATA",
+   "QDSD_CLK",
+   "QDSD_CMD",
+   "QDSD_DATA0",
+   "QDSD_DATA1",
+   "QDSD_DATA2",
+   "QDSD_DATA3",
+};
+
+const struct pinctrl_function msm_pinctrl_functions[] = {
+   {"blsp1_uart", 2},
+};
+
+const int msm_functions_count = ARRAY_SIZE(msm_pinctrl_functions);
+const int 

[U-Boot] [PATCH 2/7] serial: serial_msm: fail probe if settings clocks fails

[Ramon Fried]

Failure to set the clocks will causes data abort exception when
trying to write to AHB uart registers.
This patch ensures that we don't touch these registers if clock
setting failed.

Signed-off-by: Ramon Fried 
---
 drivers/serial/serial_msm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index 119e6b9846..250e48c996 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -183,8 +183,8 @@ static int msm_serial_probe(struct udevice *dev)
 {
struct msm_serial_data *priv = dev_get_priv(dev);
 
-   msm_uart_clk_init(dev); /* Ignore return value and hope clock was
- properly initialized by earlier loaders */
+   if (msm_uart_clk_init(dev))
+   return -EINVAL;
 
if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR);
-- 
2.14.1

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[U-Boot] [PATCH 3/7] serial: serial_msm: initialize uart only before relocation

[Ramon Fried]

The uart is already initialized prior to relocation,
reinitialization after relocation is unnecessary.

Signed-off-by: Ramon Fried 
---
 drivers/serial/serial_msm.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index 250e48c996..22301c0e37 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -183,6 +183,10 @@ static int msm_serial_probe(struct udevice *dev)
 {
struct msm_serial_data *priv = dev_get_priv(dev);
 
+   /* No need to reinitialize the UART after relocation */
+   if ((gd->flags & GD_FLG_RELOC))
+   return 0;
+
if (msm_uart_clk_init(dev))
return -EINVAL;
 
-- 
2.14.1

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[U-Boot] [PATCH 1/7] db820c: set clk node to be probed before relocation

[Ramon Fried]

The clock and serial nodes are needed before relocation.
This patch ensures that the msm-serial driver will probe
and provide uart output before relocation.

Signed-off-by: Ramon Fried 
---
 arch/arm/dts/dragonboard820c-uboot.dtsi | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/dts/dragonboard820c-uboot.dtsi 
b/arch/arm/dts/dragonboard820c-uboot.dtsi
index 88312b3fa1..81df788fca 100644
--- a/arch/arm/dts/dragonboard820c-uboot.dtsi
+++ b/arch/arm/dts/dragonboard820c-uboot.dtsi
@@ -5,6 +5,20 @@
  * (C) Copyright 2017 Jorge Ramirez-Ortiz 
  */
 
+/ {
+   soc {
+   u-boot,dm-pre-reloc;
+
+   clock-controller@30 {
+   u-boot,dm-pre-reloc;
+   };
+
+   serial@75b {
+   u-boot,dm-pre-reloc;
+   };
+   };
+};
+
 _pon {
key_vol_down {
gpios = <_pon 1 0>;
-- 
2.14.1

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[U-Boot] [PATCH 0/7] *** Qualcomm Snapdraon serial fixes***

[Ramon Fried]

In my ongoing effort to get rid of LK (Qualcomm's bootloader) that runs
before U-boot, I found that there were some problems with the uart driver of
Snapdragon.
It appears that the uart only worked because the initialization was previously
done by LK.

While fixing, I also introduced a new pinctrl driver for snapdragon (currently
only enabled for APQ8016).
the pinctrl driver is used for muxing the uart pins and configure the pins IO
properties.

Ramon Fried (7):
  db820c: set clk node to be probed before relocation
  serial: serial_msm: fail probe if settings clocks fails
  serial: serial_msm: initialize uart only before relocation
  mach-snapdragon: Fix UART clock flow
  mach-snapdragon: Introduce pinctrl driver
  db410: added pinctrl node and serial bindings
  serial: serial_msm: added pinmux & config

 arch/arm/dts/dragonboard410c.dts   |  14 ++
 arch/arm/dts/dragonboard820c-uboot.dtsi|  14 ++
 arch/arm/mach-snapdragon/Makefile  |   2 +
 arch/arm/mach-snapdragon/clock-apq8016.c   |  23 ++-
 arch/arm/mach-snapdragon/clock-apq8096.c   |   4 +-
 arch/arm/mach-snapdragon/clock-snapdragon.c|  17 ++-
 arch/arm/mach-snapdragon/clock-snapdragon.h|   9 +-
 .../mach-snapdragon/include/mach/sysmap-apq8016.h  |   1 +
 arch/arm/mach-snapdragon/pinctrl-apq8016.c | 162 +
 arch/arm/mach-snapdragon/pinctrl-snapdragon.c  | 118 +++
 arch/arm/mach-snapdragon/pinctrl-snapdragon.h  |  21 +++
 configs/dragonboard410c_defconfig  |   5 +
 drivers/serial/serial_msm.c|  30 +++-
 include/dt-bindings/pinctrl/pinctrl-snapdragon.h   |  22 +++
 14 files changed, 423 insertions(+), 19 deletions(-)
 create mode 100644 arch/arm/mach-snapdragon/pinctrl-apq8016.c
 create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.c
 create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.h
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-snapdragon.h

-- 
2.14.1

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[U-Boot] [PATCH] mx6: remove duplicated BOUNCE_BUFFER defines

[Peter Robinson]

The mx6_common.h file already defines BOUNCE_BUFFER so no need to
definit it again in specific configs.

Signed-off-by: Peter Robinson 
---
 include/configs/advantech_dms-ba16.h | 1 -
 include/configs/apalis_imx6.h| 1 -
 include/configs/colibri_imx6.h   | 1 -
 include/configs/dh_imx6.h| 1 -
 include/configs/ge_bx50v3.h  | 1 -
 include/configs/kp_imx6q_tpc.h   | 2 --
 6 files changed, 7 deletions(-)

diff --git a/include/configs/advantech_dms-ba16.h 
b/include/configs/advantech_dms-ba16.h
index a6e99192ba..8e33d38f97 100644
--- a/include/configs/advantech_dms-ba16.h
+++ b/include/configs/advantech_dms-ba16.h
@@ -45,7 +45,6 @@
 /* MMC Configs */
 #define CONFIG_FSL_USDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR  0
-#define CONFIG_BOUNCE_BUFFER
 
 /* USB Configs */
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 00255c80d6..7225c03ac5 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -56,7 +56,6 @@
 #define CONFIG_SYS_FSL_USDHC_NUM   3
 
 #define CONFIG_SUPPORT_EMMC_BOOT   /* eMMC specific */
-#define CONFIG_BOUNCE_BUFFER
 
 /*
  * SATA Configs
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index 49ec0bf108..7e3463e184 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -54,7 +54,6 @@
 #define CONFIG_SYS_FSL_USDHC_NUM   2
 
 #define CONFIG_SUPPORT_EMMC_BOOT   /* eMMC specific */
-#define CONFIG_BOUNCE_BUFFER
 
 /* Network */
 #define CONFIG_FEC_MXC
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index 24b35161b6..3e0ac15229 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -33,7 +33,6 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
 
-#define CONFIG_BOUNCE_BUFFER
 #define CONFIG_BZIP2
 
 /* Size of malloc() pool */
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 32631a20c3..424c0dd1d0 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -62,7 +62,6 @@
 /* MMC Configs */
 #define CONFIG_FSL_USDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR  0
-#define CONFIG_BOUNCE_BUFFER
 
 /* USB Configs */
 #ifdef CONFIG_USB
diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h
index d243fc675f..bf3cc174cd 100644
--- a/include/configs/kp_imx6q_tpc.h
+++ b/include/configs/kp_imx6q_tpc.h
@@ -21,8 +21,6 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
 
-#define CONFIG_BOUNCE_BUFFER
-
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN  (4 * SZ_1M)
 
-- 
2.17.0

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[U-Boot] [PATCH] mx6: Select CONFIG_MP with MX6_SMP

[Peter Robinson]

It makes sense to select the MP multi processor option at the same time we
select the other SMP options needed for SMP capable i.MX6 SoCs.

Signed-off-by: Peter Robinson 
---
 arch/arm/mach-imx/mx6/Kconfig | 1 +
 include/configs/mx6_common.h  | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 98ea1f566c..b7a89719c0 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -5,6 +5,7 @@ config MX6_SMP
select ARM_ERRATA_761320
select ARM_ERRATA_794072
select ARM_ERRATA_845369
+   select MP
bool
 
 config MX6
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 3023701875..1b2961f68e 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -15,7 +15,6 @@
 #define CONFIG_SYS_PL310_BASE  L2_PL310_BASE
 #endif
 
-#define CONFIG_MP
 #endif
 #define CONFIG_BOARD_POSTCLK_INIT
 #define CONFIG_MXC_GPT_HCLK
-- 
2.17.0

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[U-Boot] [PATCH] mx7: remove empty ifndef statement

[Peter Robinson]

Signed-off-by: Peter Robinson 
---
 include/configs/mx7_common.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index da5a92502b..b0b7e1edd4 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -36,9 +36,6 @@
 #define CONFIG_SYS_CBSIZE  512
 #define CONFIG_SYS_MAXARGS 32
 
-#ifndef CONFIG_SYS_DCACHE_OFF
-#endif
-
 /* UART */
 #define CONFIG_MXC_UART
 
-- 
2.17.0

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[U-Boot] [PATCH] mx6 common: remove dangling comment

[Peter Robinson]

Signed-off-by: Peter Robinson 
---
 include/configs/mx6_common.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index a8182b3434..3023701875 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -51,8 +51,6 @@
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
-/* Filesystems and image support */
-
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_CBSIZE  512
 #define CONFIG_SYS_MAXARGS 32
-- 
2.17.0

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[U-Boot] [PATCH 1/2] efi_loader: adjust definitions of variable services

[Heinrich Schuchardt]

The definitons of the variable services are adjusted:
- use efi_uintn_t instead of unsigned long
- use u16 * instead of s16 * for Unicode strings
- correct definition of QueryVariableInfo
- rename efi_get_next_variable to efi_get_next_variable_name

Signed-off-by: Heinrich Schuchardt 
---
 include/efi_api.h | 24 
 include/efi_loader.h  | 18 +-
 lib/efi_loader/efi_bootmgr.c  | 10 +-
 lib/efi_loader/efi_runtime.c  | 10 +-
 lib/efi_loader/efi_variable.c | 24 
 5 files changed, 43 insertions(+), 43 deletions(-)

diff --git a/include/efi_api.h b/include/efi_api.h
index 64c27e494bc..094be6edf9b 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -214,15 +214,15 @@ struct efi_runtime_services {
uint32_t descriptor_version,
struct efi_mem_desc *virtmap);
efi_status_t (*convert_pointer)(unsigned long dbg, void **address);
-   efi_status_t (EFIAPI *get_variable)(s16 *variable_name,
-   efi_guid_t *vendor, u32 *attributes,
-   unsigned long *data_size, void *data);
-   efi_status_t (EFIAPI *get_next_variable)(
-   unsigned long *variable_name_size,
-   s16 *variable_name, efi_guid_t *vendor);
-   efi_status_t (EFIAPI *set_variable)(s16 *variable_name,
-   efi_guid_t *vendor, u32 attributes,
-   unsigned long data_size, void *data);
+   efi_status_t (EFIAPI *get_variable)(u16 *variable_name,
+   efi_guid_t *vendor, u32 *attributes,
+   efi_uintn_t *data_size, void *data);
+   efi_status_t (EFIAPI *get_next_variable_name)(
+   efi_uintn_t *variable_name_size,
+   u16 *variable_name, efi_guid_t *vendor);
+   efi_status_t (EFIAPI *set_variable)(u16 *variable_name,
+   efi_guid_t *vendor, u32 attributes,
+   efi_uintn_t data_size, void *data);
efi_status_t (EFIAPI *get_next_high_mono_count)(
uint32_t *high_count);
void (EFIAPI *reset_system)(enum efi_reset_type reset_type,
@@ -239,9 +239,9 @@ struct efi_runtime_services {
u32 reset_type);
efi_status_t (EFIAPI *query_variable_info)(
u32 attributes,
-   u64 maximum_variable_storage_size,
-   u64 remaining_variable_storage_size,
-   u64 maximum_variable_size);
+   u64 *maximum_variable_storage_size,
+   u64 *remaining_variable_storage_size,
+   u64 *maximum_variable_size);
 };
 
 /* EFI event group GUID definitions */
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 2868ca25abb..4e9e9d05c76 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -415,15 +415,15 @@ efi_status_t EFIAPI efi_selftest(efi_handle_t 
image_handle,
 struct efi_system_table *systab);
 #endif
 
-efi_status_t EFIAPI efi_get_variable(s16 *variable_name,
-   efi_guid_t *vendor, u32 *attributes,
-   unsigned long *data_size, void *data);
-efi_status_t EFIAPI efi_get_next_variable(
-   unsigned long *variable_name_size,
-   s16 *variable_name, efi_guid_t *vendor);
-efi_status_t EFIAPI efi_set_variable(s16 *variable_name,
-   efi_guid_t *vendor, u32 attributes,
-   unsigned long data_size, void *data);
+efi_status_t EFIAPI efi_get_variable(u16 *variable_name, efi_guid_t *vendor,
+u32 *attributes, efi_uintn_t *data_size,
+void *data);
+efi_status_t EFIAPI efi_get_next_variable_name(efi_uintn_t *variable_name_size,
+  u16 *variable_name,
+  efi_guid_t *vendor);
+efi_status_t EFIAPI efi_set_variable(u16 *variable_name, efi_guid_t *vendor,
+u32 attributes, efi_uintn_t data_size,
+void *data);
 
 void *efi_bootmgr_load(struct efi_device_path **device_path,
   struct efi_device_path **file_path);
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index 153e1737573..853358ab937 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -70,17 +70,17 @@ static void parse_load_option(struct load_option *lo, void 
*ptr)
 
 /* free() the result */
 static void *get_var(u16 *name, const efi_guid_t *vendor,
-unsigned long *size)
+efi_uintn_t *size)
 {
efi_guid_t *v = (efi_guid_t *)vendor;
efi_status_t ret;
void *buf 

[U-Boot] [PATCH 2/2] efi_selftest: unit test for variable services

[Heinrich Schuchardt]

Provide a unit test for variable services.

Signed-off-by: Heinrich Schuchardt 
---
 lib/efi_selftest/Makefile |   1 +
 lib/efi_selftest/efi_selftest_variables.c | 178 ++
 2 files changed, 179 insertions(+)
 create mode 100644 lib/efi_selftest/efi_selftest_variables.c

diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile
index 80c43026458..2b943bc4d84 100644
--- a/lib/efi_selftest/Makefile
+++ b/lib/efi_selftest/Makefile
@@ -28,6 +28,7 @@ efi_selftest_textinput.o \
 efi_selftest_textoutput.o \
 efi_selftest_tpl.o \
 efi_selftest_util.o \
+efi_selftest_variables.o \
 efi_selftest_watchdog.o
 
 ifeq ($(CONFIG_BLK)$(CONFIG_PARTITIONS),yy)
diff --git a/lib/efi_selftest/efi_selftest_variables.c 
b/lib/efi_selftest/efi_selftest_variables.c
new file mode 100644
index 000..992f45d60a5
--- /dev/null
+++ b/lib/efi_selftest/efi_selftest_variables.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_variables
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt 
+ *
+ * This unit test checks the following protocol services:
+ * ConnectController, DisconnectController,
+ * InstallProtocol, ReinstallProtocol, UninstallProtocol,
+ * OpenProtocol, CloseProtcol, OpenProtocolInformation
+ */
+
+#include 
+
+#define EFI_ST_MAX_DATA_SIZE 16
+#define EFI_ST_MAX_VARNAME_SIZE 40
+
+static struct efi_boot_services *boottime;
+static struct efi_runtime_services *runtime;
+static efi_guid_t guid_vendor0 =
+   EFI_GUID(0x67029eb5, 0x0af2, 0xf6b1,
+0xda, 0x53, 0xfc, 0xb5, 0x66, 0xdd, 0x1c, 0xe6);
+static efi_guid_t guid_vendor1 =
+   EFI_GUID(0xff629290, 0x1fc1, 0xd73f,
+0x8f, 0xb1, 0x32, 0xf9, 0x0c, 0xa0, 0x42, 0xea);
+
+/*
+ * Setup unit test.
+ *
+ * @handle handle of the loaded image
+ * @systable   system table
+ */
+static int setup(const efi_handle_t img_handle,
+const struct efi_system_table *systable)
+{
+   boottime = systable->boottime;
+   runtime = systable->runtime;
+
+   return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ */
+static int execute(void)
+{
+   efi_status_t ret;
+   efi_uintn_t len;
+   u32 attr;
+   u8 v[16] = {0x5d, 0xd1, 0x5e, 0x51, 0x5a, 0x05, 0xc7, 0x0c,
+   0x35, 0x4a, 0xae, 0x87, 0xa5, 0xdf, 0x0f, 0x65,};
+   u8 *data[EFI_ST_MAX_DATA_SIZE];
+   u16 varname[EFI_ST_MAX_VARNAME_SIZE];
+   int flag;
+   efi_guid_t guid;
+   u64 max_storage, rem_storage, max_size;
+
+   ret = runtime->query_variable_info(EFI_VARIABLE_BOOTSERVICE_ACCESS,
+  _storage, _storage,
+  _size);
+   if (ret != EFI_SUCCESS) {
+   efi_st_todo("QueryVariableInfo failed\n");
+   } else if (!max_storage || !rem_storage || !max_size) {
+   efi_st_error("QueryVariableInfo: wrong info\n");
+   return EFI_ST_FAILURE;
+   }
+   /* Set variable 0 */
+   ret = runtime->set_variable(L"efi_st_var0", _vendor0,
+   EFI_VARIABLE_BOOTSERVICE_ACCESS,
+   3, v + 4);
+   if (ret != EFI_SUCCESS) {
+   efi_st_error("SetVariable failed\n");
+   return EFI_ST_FAILURE;
+   }
+   /* Set variable 1 */
+   ret = runtime->set_variable(L"efi_st_var1", _vendor1,
+   EFI_VARIABLE_BOOTSERVICE_ACCESS,
+   8, v);
+   if (ret != EFI_SUCCESS) {
+   efi_st_error("SetVariable failed\n");
+   return EFI_ST_FAILURE;
+   }
+   len = EFI_ST_MAX_DATA_SIZE;
+   ret = runtime->get_variable(L"efi_st_var1", _vendor1,
+   , , data);
+   if (ret != EFI_SUCCESS) {
+   efi_st_error("GetVariable failed\n");
+   return EFI_ST_FAILURE;
+   }
+   if (len != 8) {
+   efi_st_error("GetVariable returned wrong length %u\n", len);
+   return EFI_ST_FAILURE;
+   }
+   if (efi_st_memcmp(data, v, 8)) {
+   efi_st_error("GetVariable returned wrong value\n");
+   return EFI_ST_FAILURE;
+   }
+   /* Append variable 1 */
+   ret = runtime->set_variable(L"efi_st_var1", _vendor1,
+   EFI_VARIABLE_BOOTSERVICE_ACCESS |
+   EFI_VARIABLE_APPEND_WRITE,
+   7, v + 8);
+   if (ret != EFI_SUCCESS) {
+   efi_st_error("SetVariable failed\n");
+   return EFI_ST_FAILURE;
+   }
+   len = EFI_ST_MAX_DATA_SIZE;
+   ret = runtime->get_variable(L"efi_st_var1", _vendor1,
+   , , data);
+   if (ret != EFI_SUCCESS) {
+   efi_st_error("GetVariable failed\n");
+   return EFI_ST_FAILURE;
+   }
+   if 

[U-Boot] [PATCH 0/2] efi_loader: adjust definitions of variable services

[Heinrich Schuchardt]

The definitons of the variable services are adjusted:
- use efi_uintn_t instead of unsigned long
- use u16 * instead of s16 * for Unicode strings
- correct definition of QueryVariableInfo
- rename efi_get_next_variable to efi_get_next_variable_name

A unit test for the variable services is supplied.

Heinrich Schuchardt (2):
  efi_loader: adjust definitions of variable services
  efi_selftest: unit test for variable services

 include/efi_api.h | 20 ++--
 include/efi_loader.h  | 14 +++---
 lib/efi_loader/efi_bootmgr.c  | 10 +-
 lib/efi_loader/efi_runtime.c  | 10 +-
 lib/efi_loader/efi_variable.c | 18 +-
 lib/efi_selftest/Makefile |  1 +
 6 files changed, 37 insertions(+), 36 deletions(-)

-- 
2.17.0

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[U-Boot] [PATCH] net: cpsw: ti: Reap completed packets before stopping interface

[Alex Kiernan]

If you send a final packet just before stopping the interface (e.g. a final
ACK as part of the UDP fastboot protocol), then that packet isn't reliably
delivered onto the wire.

Reap packets prior to stopping the interface to ensure any which are
in-flight make it out. Also remove buffer and len from the call to
cpdma_process() as we weren't using them on their return.

Signed-off-by: Alex Kiernan 
---

 drivers/net/cpsw.c | 24 
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index e2395db..9919d39 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -910,8 +910,22 @@ out:
return ret;
 }
 
+static int cpsw_reap_completed_packets(struct cpsw_priv *priv)
+{
+   int timeout = CPDMA_TIMEOUT;
+
+   /* reap completed packets */
+   while (timeout-- &&
+  (cpdma_process(priv, >tx_chan, NULL, NULL) >= 0))
+   ;
+
+   return timeout;
+}
+
 static void _cpsw_halt(struct cpsw_priv *priv)
 {
+   cpsw_reap_completed_packets(priv);
+
writel(0, priv->dma_regs + CPDMA_TXCONTROL);
writel(0, priv->dma_regs + CPDMA_RXCONTROL);
 
@@ -925,18 +939,12 @@ static void _cpsw_halt(struct cpsw_priv *priv)
 
 static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length)
 {
-   void *buffer;
-   int len;
-   int timeout = CPDMA_TIMEOUT;
+   int timeout;
 
flush_dcache_range((unsigned long)packet,
   (unsigned long)packet + ALIGN(length, PKTALIGN));
 
-   /* first reap completed packets */
-   while (timeout-- &&
-   (cpdma_process(priv, >tx_chan, , ) >= 0))
-   ;
-
+   timeout = cpsw_reap_completed_packets(priv);
if (timeout == -1) {
printf("cpdma_process timeout\n");
return -ETIMEDOUT;
-- 
2.7.4

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