Re: [U-Boot] [PATCH v4 12/25] mtd: ensure MTD and NOR drivers are compiled with ENV_IS_IN_FLASH

2018-12-10 Thread Miquel Raynal
Hi Tom,

Tom Rini  wrote on Mon, 10 Dec 2018 13:10:11 -0500:

> On Mon, Dec 10, 2018 at 07:02:45PM +0100, Miquel Raynal wrote:
> > Hello,
> > 
> > Miquel Raynal  wrote on Sun,  9 Dec 2018
> > 19:07:34 +0100:
> >   
> > > MTD and NOR flash support must be enabled when the environment is in
> > > NOR.
> > > 
> > > Signed-off-by: Miquel Raynal 
> > > ---
> > >  configs/armadillo-800eva_defconfig | 2 ++
> > >  1 file changed, 2 insertions(+)
> > > 
> > > diff --git a/configs/armadillo-800eva_defconfig 
> > > b/configs/armadillo-800eva_defconfig
> > > index b1d923c069..72758884b4 100644
> > > --- a/configs/armadillo-800eva_defconfig
> > > +++ b/configs/armadillo-800eva_defconfig
> > > @@ -32,6 +32,8 @@ CONFIG_CMD_PING=y
> > >  # CONFIG_CMD_MISC is not set
> > >  CONFIG_ENV_IS_IN_FLASH=y
> > >  # CONFIG_MMC is not set
> > > +CONFIG_MTD=y
> > > +CONFIG_MTD_NOR_FLASH=y
> > >  CONFIG_SH_ETHER=y
> > >  CONFIG_SCIF_CONSOLE=y
> > >  CONFIG_OF_LIBFDT=y  
> > 
> > This change triggered a build failure. This is because, despite
> > declaring an in-flash environment, there was absolutely no MTD driver
> > compiled-in. No driver named after 'flash' or 'nor' or 'mtd' was
> > compiled.
> > 
> > The fix for this issue (the only one reported by Travis for this
> > version of the series) is to just drop this patch. As it has absolutely
> > no dependency and only impacts a single defconfig, I would rather
> > prefer not re-send 24 identical patches in a v5 unless there are
> > comments that I must address.  
> 
> Thanks.  Do you have a patchwork account?  If so you should be able to
> manage the status of your own at least and marking it as "Rejected" or
> "Not Applicable" or anything like that will mean it won't be picked up
> by accident.  If not, I'll get to it soon.
> 

I do have an account on ozlabs' patchwork. I went there to discard this
patch but I saw that someone (probably you) already did it.


Thanks,
Miquèl
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Re: [U-Boot] [PATCH v2 06/20] riscv: ax25: Hide the ax25-specific Kconfig option

2018-12-10 Thread Bin Meng
Hi Rick,

On Tue, Dec 11, 2018 at 3:06 PM Rick Chen  wrote:
>
> > > Subject: [PATCH v2 06/20] riscv: ax25: Hide the ax25-specific Kconfig 
> > > option
> > >
> > > There is no need to expose RISCV_NDS to the Kconfig menu as it is an
> > > ax25-specific option.
> > >
>
> Hi Bin
>
> Can you explain why there is no need to expose RISCV_NDS here ?
>

This is specific to AX25, and there is no need to appear in the
Kconfig menu when people are building U-Boot for some other RISC-V
platforms. Also even if you select Y in the Kconfig menu for this
option for platforms other than AX25, it just does not help since all
its logic is within arch/riscv/cpu/ax25.

Regards,
Bin
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Re: [U-Boot] [PATCH v2 06/20] riscv: ax25: Hide the ax25-specific Kconfig option

2018-12-10 Thread Rick Chen
> > Subject: [PATCH v2 06/20] riscv: ax25: Hide the ax25-specific Kconfig option
> >
> > There is no need to expose RISCV_NDS to the Kconfig menu as it is an
> > ax25-specific option.
> >

Hi Bin

Can you explain why there is no need to expose RISCV_NDS here ?

Rick

> > Signed-off-by: Bin Meng 
> > ---
> >
> > Changes in v2: None
> >
> >  arch/riscv/cpu/ax25/Kconfig | 8 +++-
> >  1 file changed, 3 insertions(+), 5 deletions(-)
> >
> > diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index
> > 6c7022f..5ff9e5c 100644
> > --- a/arch/riscv/cpu/ax25/Kconfig
> > +++ b/arch/riscv/cpu/ax25/Kconfig
> > @@ -1,7 +1,5 @@
> >  config RISCV_NDS
> > - bool "AndeStar V5 ISA support"
> > - default n
> > + bool
> >   help
> > - Say Y here if you plan to run U-Boot on AndeStar v5
> > - platforms and use some specific features which are
> > - provided by Andes Technology AndeStar V5 Families.
> > +   Run U-Boot on AndeStar v5 platforms and use some specific features
> > +   which are provided by Andes Technology AndeStar V5 Families.
> > --
> > 2.7.4
>
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Re: [U-Boot] ARM: rockchip: rv1108: Fix booting with initramfs

2018-12-10 Thread Heiko Stuebner
Hi Philipp,

Am Dienstag, 11. Dezember 2018, 00:12:40 CET schrieb Philipp Tomsich:
> + Heiko
> 
> > On 10.12.2018, at 01:56, Tom Rini  wrote:
> > 
> > On Mon, Dec 10, 2018 at 01:38:36AM +0100, Philipp Tomsich wrote:
> >> Tom,
> >> 
> >> On 10.12.2018, at 01:28, Tom Rini  wrote:
> >>> 
> >>> On Mon, Dec 10, 2018 at 01:01:52AM +0100, Philipp Tomsich wrote:
> > We move the ramdisk_addr_r to 0x6800 and disable the initrd and
> > fdt relocation, so the initramfs works out of box.
> > 
> > Signed-off-by: Otavio Salvador 
> > Reviewed-by: Philipp Tomsich 
> > ---
> > 
> > include/configs/rv1108_common.h | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> > 
>  
>  Applied to u-boot-rockchip, thanks!
> >>> 
> >>> Ugh, sorry for not spotting this sooner.  Please don't disable
> >>> fdt/initrd relocation and instead use bootm_size.
> >> 
> >> Thanks for spotting this (just in time).
> >> I’ll drop it and rerun Travis for tomorrow’s PR.
> > 
> > Thanks.  And you might want to audit the rest of rockchip (and no, my
> > own house isn't 100% in order) as it looks like in general at least
> > you're using fdt_high to (good) set an upper bound but I think
> > bootm_size is more robust as we can set that and it covers fdt and
> > initrd if present (which not all rk3xxx_common.h are setting).
> 
> We may have a problem on rk3188 and rk3288 configurations. While I can
> convert these to bootm_size, I would have to do so blindly, as I don’t have
> any boards.
> 
> @Heiko: you have added the fdt_high and initrd_high in rk3188_common.h,
> do you have more info and would you have able to test this changed to
> bootm_size instead?

I think I more or less only copied that from rk3288 (adjusted for actual
ram-location) and I'm of course able to test changes you want to do on
rk3188 [Though only starting from thursday].

Heiko



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Re: [U-Boot] [Fwd: [PATCH] mpc83xx: Add support for -msingle-pic-base]

2018-12-10 Thread Mario Six
On Wed, Dec 5, 2018 at 12:56 PM Mario Six  wrote:
>
> Hi Joakim,
> On Wed, Dec 5, 2018 at 11:03 AM Joakim Tjernlund
>  wrote:
> >
> > Ping ?
> >
> > On Thu, 2018-11-29 at 14:09 +0100, Joakim Tjernlund wrote:
> > > OOPS, I forgot to include you in this patch so I do that now :)
> > >
> > >
> > > --- Forwarded Message 
> > > From: Joakim Tjernlund 
> > > To: u-boot@lists.denx.de
> > > Cc: Joakim Tjernlund 
> > > Subject: [PATCH] mpc83xx: Add support for -msingle-pic-base
> > > Date: Wed, 28 Nov 2018 10:59:55 +0100
> > >
> > > -msingle-pic-base is a new gcc(from 4.6) option for ppc and
> > > it reduces the size of my u-boot with about 4 KB.
> > > While at it, add -fno-jump-tables too to save a
> > > few more bytes.
> > >
> > > Signed-off-by: Joakim Tjernlund 
> > > ---
> > >
> > >  I think all PowerPC's can use this but I have only tested
> > >  83xx so just enable for this cpu for now.
> > >
> > >  arch/powerpc/cpu/mpc83xx/config.mk | 1 +
> > >  arch/powerpc/cpu/mpc83xx/start.S   | 3 +++
> > >  2 files changed, 4 insertions(+)
> > >
> > > diff --git a/arch/powerpc/cpu/mpc83xx/config.mk 
> > > b/arch/powerpc/cpu/mpc83xx/config.mk
> > > index 14870eec4d..a07df4d389 100644
> > > --- a/arch/powerpc/cpu/mpc83xx/config.mk
> > > +++ b/arch/powerpc/cpu/mpc83xx/config.mk
> > > @@ -3,3 +3,4 @@
> > >  # Copyright 2004 Freescale Semiconductor, Inc.
> > >
> > >  PLATFORM_CPPFLAGS += -DCONFIG_E300 -msoft-float
> > > +PLATFORM_RELFLAGS += -msingle-pic-base -fno-jump-tables
> > > diff --git a/arch/powerpc/cpu/mpc83xx/start.S 
> > > b/arch/powerpc/cpu/mpc83xx/start.S
> > > index a3bacf138c..c00bb31363 100644
> > > --- a/arch/powerpc/cpu/mpc83xx/start.S
> > > +++ b/arch/powerpc/cpu/mpc83xx/start.S
> > > @@ -288,6 +288,9 @@ in_flash:
> > >   /*--*/
> > >
> > >   GET_GOT /* initialize GOT access*/
> > > + /* Needed for -msingle-pic-base */
> > > + bl  _GLOBAL_OFFSET_TABLE_@local-4
> > > + mflrr30
> > >
> > >   /* r3: IMMR */
> > >   lis r3, CONFIG_SYS_IMMR@h
> >
> Don't worry, I was aware of the patch; just had to find some time for
> testing :-)
>
> Reviewed-by: Mario Six 
> Tested-by: Mario Six  (on MPC8308)
>
> Best regards,
> Mario

Applied to u-boot-mpc83xx/master.
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Re: [U-Boot] [PATCH] ARM: at91: Fix 'boot.bin' generation when CONFIG_SD_BOOT is enabled

2018-12-10 Thread Derald D. Woods
On Mon, Dec 10, 2018 at 03:14:05PM +, eugen.hris...@microchip.com wrote:
> 
> 
> On 10.12.2018 16:54, Derald Woods wrote:
> > 
> > 
> > On Mon, Dec 10, 2018 at 8:03 AM  > > wrote:
> > 
> > 
> > 
> > On 10.12.2018 15:01, Derald D. Woods wrote:
> >  > On Mon, Dec 10, 2018 at 08:32:33AM +,
> > eugen.hris...@microchip.com  wrote:
> >  >>
> >  >>
> >  >> On 08.12.2018 21:49, Derald D. Woods wrote:
> >  >>> On AT91 platforms configured for SD_BOOT, this commit avoids the
> >  >>> generation of the PMECC header used for booting from NAND
> > flash. This
> >  >>> issue was found by attempting to boot the SAMA5D3-XPLD board
> > with the
> >  >>> 'sama5d3_xplained_mmc_defconfig'.
> >  >>>
> >  >>> [PMECC Reference]
> >  >>> http://www.at91.com/linux4sam/bin/view/Linux4SAM/AT91Bootstrap
> >  >>>
> >  >>> [Mailing List Thread]
> >  >>> https://lists.denx.de/pipermail/u-boot/2018-December/350666.html
> >  >>>
> >  >>> Fixes: 5541543f ("configs: at91: Remove
> > CONFIG_SYS_EXTRA_OPTIONS assignment")
> >  >>> Reported-by: Daniel Evans  > >
> >  >>> Cc: Robert Nelson  > >
> >  >>> Cc: Eugen Hristev  > >
> >  >>> Cc: Wenyou Yang  > >
> >  >>> Signed-off-by: Derald D. Woods  > >
> >  >>> ---
> >  >>>    scripts/Makefile.spl | 2 ++
> >  >>>    1 file changed, 2 insertions(+)
> >  >>>
> >  >>> diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
> >  >>> index 22bd8f7c27..e727cb610f 100644
> >  >>> --- a/scripts/Makefile.spl
> >  >>> +++ b/scripts/Makefile.spl
> >  >>> @@ -166,10 +166,12 @@ ifeq ($(CONFIG_SYS_SOC),"at91")
> >  >>>    MKIMAGEFLAGS_boot.bin = -T atmelimage
> >  >>>
> >  >>>    ifeq ($(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER),y)
> >  >>> +ifneq ($(CONFIG_SD_BOOT),y)
> >  >>
> >  >> Hi Derald,
> >  >>
> >  >> Thanks for your patch, however, I don't like that we do not use the
> >  >> CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER anymore... isn't this config
> >  >> supposed to say whether we are going to generate the header or not ?
> >  >>
> >  >
> >  > That is not what is happening with this patch.
> > SPL_GENERATE_ATMEL_PMECC_HEADER
> >  > is not removed. The config still serves its orignal intent. If
> > SD_BOOT
> >  > is configured, then NAND is not being used. In this non-NAND
> > case, the
> >  > header is not needed.
> >  >
> >  >> Checking if "not sd-boot" doesn't look like a good option... we
> > may use
> >  >> SPI boot or QSPI or some other type at some point and the issue will
> >  >> still be there.
> >  >>
> >  >
> >  > This location and method would work for those nod-NAND cases
> > also. See
> >  > below.
> >  >
> >  >> I would rather fix the original patch by Wenyou, namely move the
> > #ifdef
> >  >> below to not have the GENERATE_ATMEL_PMECC enabled for SDBOOT.
> >  >>
> >  >> Does this sound good for you?
> >  >>
> >  >
> >  > If this SPL_GENERATE_ATMEL_PMECC_HEADER only needs to be there
> > for NAND,
> >  > why not guard the 'ifdef ($(CONFIG_NAND_BOOT,y))'? Would this be
> > better?
> >  > Basically we could replace the 'ifneq ($(CONFIG_SD_BOOT),y)' with the
> >  > more appropriate 'ifeq ($(CONFIG_NAND_BOOT),y)'. This would actually
> >  > allow the future use-cases to be added as they become available
> > and can
> >  > be shown to actually boot with the header applied.
> >  >
> >  > I will put together a proper version 2 of my patch later today.
> >  >
> >  > [patch v2]
> >  >
> > 
> > 
> >  > diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
> >  > index 22bd8f7..e727cb6 100644
> >  > --- a/scripts/Makefile.spl
> >  > +++ b/scripts/Makefile.spl
> >  > @@ -166,10 +166,12 @@ ifeq ($(CONFIG_SYS_SOC),"at91")
> >  >   MKIMAGEFLAGS_boot.bin = -T atmelimage
> >  >
> >  >   ifeq ($(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER),y)
> >  > +ifeq ($(CONFIG_NAND_BOOT),y)
> >  >   MKIMAGEFLAGS_boot.bin += -n $(shell
> > $(obj)/../tools/atmel_pmecc_params)
> >  >
> >  >   boot.bin: $(obj)/../tools/atmel_pmecc_params
> >  >   endif
> >  > +endif
> >  >
> >  >   boot.bin: $(obj)/u-boot-spl.bin FORCE
> >  >       $(call if_changed,mkimage)
> >  >
> > 
> > 
> >  >
> >  > This would allow other configurations to 'opt-in' to applying the
> >  > header. Which I think is the 

Re: [U-Boot] Regression: dm: i2c: Make i2c_get_chip_for_busnum() fail if the chip is not detected

2018-12-10 Thread Heiko Schocher

Hello Stephen,

Am 10.12.2018 um 19:23 schrieb Stephen Warren:

The following commit:


dm: i2c: Make i2c_get_chip_for_busnum() fail if the chip is not detected
    i2c_get_chip_for_busnum() really should check the presence of the chip on
    the bus. Most of the users of this function assume that this is done.


... causes a boot failure on NVIDIA Jetson TX2:


:-(

Thanks for detecting so fast!


U-Boot 2019.01-rc1-00220-g7ff485c68b7e (Dec 10 2018 - 11:20:41 -0700)

TEGRA186
Model: NVIDIA P2771--500
DRAM:  7.8 GiB
tegra_ivc_read_get_next_frame() timed out (-12)
tegra_board_init: Cannot find MAX77620 I2C chip
initcall sequence fffa95a8 failed at call 80083480 (err=-110)
### ERROR ### Please RESET the board ###


This may be due to the fact the bus in question is implemented by RPC to a separate CPU, and that 
mechanism hasn't been used with probing before. In general though, there's not guarantee that 
probing will work even on a local/native I2C bus, since different chips don't support all probe 
methods (see i2c-detect in Linux, which supports various different probing methods due to this), so 
I'm rather surprised this change was implemented. Is it really necessary? I believe we should revert 
it.


Hmm... yes, you are right.

Ah, Jean-Jacques first had another approach, see:

https://lists.denx.de/pipermail/u-boot/2018-October/343230.html

May it is possible to switch back to this approach ?

bye,
Heiko
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Re: [U-Boot] [RESEND PATCH v3 00/19] DM_I2C_COMPAT removal for all ti platforms

2018-12-10 Thread Heiko Schocher

Hello Simon,

Am 11.12.2018 um 02:05 schrieb Simon Glass:

Hi Tom,

On Fri, 7 Dec 2018 at 07:23, Tom Rini  wrote:


On Fri, Dec 07, 2018 at 02:50:36PM +0100, Jean-Jacques Hiblot wrote:


This series remove the usage of the DM_I2C_COMPAT option for all the ti
platforms. It also takes this opportunity to not disable DM_I2C in the SPL.

There are a couples of issues to fix:
- CMD_EEPROM does not support the DM API. Fixed by removing this option
   when DM_I2C is used without DM_I2C_COMPAT
- i2c_get_chip_for_busnum() does not work when OF_CONTROL is not used
   (as is the case with am33xx SPL).
- The I2C driver do not support DM_I2C without OF_CONTROL.
- Most of the PMIC drivers do not support the I2C DM API.
- Board detection is done prior DM initialization. Fixed by moving it after
   DM is initialized. That move breaks the DRA7 platforms (The fixes for
   that are at the last 5 patches this series)

When all this is taken care of DM_I2C_COMPAT can be removed and DM_I2C
enabled in the SPL.

This has been tested with the following boards:
- am437x SK
- am335x SK
- am335x beaglebone (both DM and non-DM config)
- dra76 evm
- am572 evm
- k2g evm

The following targets may be impacted by the changes related to
SPL_OF_CONTROL and SPL_OF_PLATDATA:
- am3517_evm_defconfig
- omap3_logic_defconfig
- chromebit_mickey_defconfig
- chromebook_jerry_defconfig
- chromebook_minnie_defconfig
- evb-rk3399_defconfig
- rock_defconfig

It would be nice it some of you could try to boot them.


So I've just reviewed-by all of the TI parts.  Heiko, do you want this
via the I2C tree?  Simon, do you want this via the DM tree?  Do both of
you just want me to grab it instead?  The window on applying this for
this release is closing quickly but this has been around for long enough
that I'd like to see it go in.  Thanks!


Agreed. I am happy to take it, or you can. Please let me know.


I just tooked them and send a pull request to Tom, see:

https://lists.denx.de/pipermail/u-boot/2018-December/351388.html

and Tom apllied it already:

https://lists.denx.de/pipermail/u-boot/2018-December/351431.html

Stephen found a regression, see:
https://lists.denx.de/pipermail/u-boot/2018-December/351480.html

I am not in front of my PC today, so I have to look, may Jean-Jacques
has time to look into?

bye,
Heiko
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Re: [U-Boot] Please pull u-boot-dm

2018-12-10 Thread Keerthy


On Tuesday 11 December 2018 06:34 AM, Simon Glass wrote:
> Hi,
> 
> On Tue, 4 Dec 2018 at 21:10, Keerthy  wrote:
>>
>>
>>
>> On Friday 30 November 2018 08:25 PM, Tom Rini wrote:
>>> On Thu, Nov 29, 2018 at 01:55:14PM -0700, Simon Glass wrote:
>>>
 Hi Tom,

 The following changes since commit 
 e16c888fab5014b022d5781dc534f204460a073b:

   Merge branch '2018-11-28-master-imports' (2018-11-28 23:04:58 -0500)

 are available in the Git repository at:

   git://git.denx.de/u-boot-dm.git tags/pull-29nov18

 for you to fetch changes up to 5ca3927deff30458f5d5b384f6699f70b9509315:

   core: ofnode: Add ofnode_get_addr_size_index (2018-11-29 09:30:06 -0700)

 Results here:

 https://travis-ci.org/sglass68/u-boot/builds/461363284
>>>
>>> NAK.  I don't know _why_ but I can confirm that both within travis:
>>> https://travis-ci.org/trini/u-boot/jobs/461494951
>>> and then locally when I installed clang-7.0 from https://apt.llvm.org/ I
>>> see that:
>>> 5ca3927deff30458f5d5b384f6699f70b9509315 is the first bad commit
>>> commit 5ca3927deff30458f5d5b384f6699f70b9509315
>>> Author: Keerthy 
>>> Date:   Mon Nov 19 11:44:48 2018 +0530
>>>
>>> core: ofnode: Add ofnode_get_addr_size_index
>>>
>>> is totally breaking test.py on sandbox.  It still starts and I don't see
>>> the obvious whats wrong, but I've bisected twice to this same commit.
>>>
>>
>> Okay i am not sure either what is going wrong there. I will take a look at 
>> this.
> 
> I am worried that this might be a unicode problem.
> 
> - build outputs error messages with backquotes, UTF-8, etc.
> - pipe from builder thread to buildman breaks things into 4KB chunks
> - sometimes a UTF-8 char break across a 4KB boundary
> - I/O error results
> 
> I suspect this because buildman's unicode handling is actually a bit
> broken - see how quotes come through in messages on some machines.
> 
> But it might be something else entirely.

Adding Lokesh

Hey Lokesh,

I am yet to dig into this. Seems my patch is breaking test.py on sandbox and
hence it was not pulled.

Regards,
Keerthy
> 
> Regards,
> Simon
> 
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Re: [U-Boot] [PATCH 1/4] scsi: ceva: add ls1046a soc support

2018-12-10 Thread Peng Ma
Hi York,

got it, thanks.

Best Regards,
Peng
>-Original Message-
>From: York Sun
>Sent: 2018年12月11日 5:10
>To: Peng Ma ; u-boot@lists.denx.de
>Cc: albert.u.b...@aribaud.net; Mingkai Hu ;
>sumit.g...@nxp.com; Pankaj Bansal ; Fabio
>Estevam ; Yinbo Zhu ;
>michal.si...@xilinx.com; s...@chromium.org; Andy Tang
>
>Subject: Re: [PATCH 1/4] scsi: ceva: add ls1046a soc support
>
>On 10/11/18 3:38 AM, Peng Ma wrote:
>> Add ahci compatible support for ls1046a soc.
>>
>> Signed-off-by: Peng Ma 
>> ---
>
>Please remember to sort defconfig using moveconfig.py in the future.
>This set is applied to fsl-qoriq master, awaiting upstream. Thanks.
>
>York
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Re: [U-Boot] [PATCH v2 16/20] riscv: Do some basic architecture level cpu initialization

2018-12-10 Thread Bin Meng
Hi Lukas,

On Tue, Dec 11, 2018 at 8:01 AM Auer, Lukas
 wrote:
>
> Hi Bin,
>
> On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> > Implement arch_cpu_init() to do some basic architecture level cpu
> > initialization, like FPU enable, etc.
> >
> > Signed-off-by: Bin Meng 
> >
> > ---
> >
> > Changes in v2:
> > - use csr_set() to set MSTATUS_FS
> > - only enabling the cycle, time, and instret counters
> > - change to use satp
> >
> >  arch/riscv/cpu/cpu.c | 19 +++
> >  1 file changed, 19 insertions(+)
> >
> > diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> > index 3858e51..194799c 100644
> > --- a/arch/riscv/cpu/cpu.c
> > +++ b/arch/riscv/cpu/cpu.c
> > @@ -7,6 +7,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >
> >  /*
> >   * prior_stage_fdt_address must be stored in the data section since
> > it is used
> > @@ -67,3 +68,21 @@ int arch_early_init_r(void)
> >
> >   return 0;
> >  }
> > +
> > +int arch_cpu_init(void)
> > +{
> > + /* Enable FPU */
> > + if (supports_extension('d') || supports_extension('f')) {
>
> supports_extension does not work when running in supervisor mode
> (unless BBL is patched). Can we maybe use the CPU driver here?
>

Yes, I think so. Will change to use info provided by the CPU driver in v3.

> > + csr_set(MODE_PREFIX(status), MSTATUS_FS);
> > + csr_write(fcsr, 0);
> > + }
> > +
> > + /* Enable perf counters for cycle, time, and instret counters
> > only */
> > + csr_write(MODE_PREFIX(counteren), GENMASK(2, 0));
>
> I would tend to only enable this in mcounteren, so for the supervisor-
> mode. Linux can still enable the counters for user-mode if required.
>

OK.

> > +
> > + /* Disable paging */
> > + if (supports_extension('s'))
> > + csr_write(satp, 0);
>
> This should only be done, when running in machine mode. In supervisor
> mode this would cause issues if we have something other than an
> identity-mapping or paging disabled.
>

I doubt we want to enable paging for S-mode U-Boot, but I am OK to do
such in M-mode only.

Regards,
Bin
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Re: [U-Boot] [PATCH v2 05/20] timer: Add generic driver for RISC-V privileged architecture defined timer

2018-12-10 Thread Bin Meng
Hi Lukas,

On Tue, Dec 11, 2018 at 7:17 AM Auer, Lukas
 wrote:
>
> Hi Bin,
>
> On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> > RISC-V privileged architecture v1.10 defines a real-time counter,
> > exposed as a memory-mapped machine-mode register - mtime. mtime must
> > run at constant frequency, and the platform must provide a mechanism
> > for determining the timebase of mtime. The mtime register has a
> > 64-bit precision on all RV32, RV64, and RV128 systems.
> >
> > Different platform may have different implementation of the mtime
> > block hence an API riscv_get_time() is required by this driver for
> > platform codes to hide such implementation details. For example,
> > on some platforms mtime is provided by the CLINT module, while on
> > some other platforms a simple 'rdtime' can be used to get the timer
> > counter.
> >
> > With this timer driver the U-Boot timer functionalities like delay
> > works correctly now.
> >
> > Signed-off-by: Bin Meng 
> >
> > ---
> >
> > Changes in v2:
> > - remove the probe to syscon driver in the timer probe, to make the
> >   driver generic, and rely on platform codes to provide the API
> >   riscv_get_time().
> >
> >  drivers/timer/Kconfig   |  8 +++
> >  drivers/timer/Makefile  |  1 +
> >  drivers/timer/riscv_timer.c | 57
> > +
> >  3 files changed, 66 insertions(+)
> >  create mode 100644 drivers/timer/riscv_timer.c
> >
> > diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
> > index b0e6f32..8995979 100644
> > --- a/drivers/timer/Kconfig
> > +++ b/drivers/timer/Kconfig
> > @@ -126,6 +126,14 @@ config OMAP_TIMER
> >   help
> > Select this to enable an timer for Omap devices.
> >
> > +config RISCV_TIMER
> > + bool "RISC-V timer support"
> > + depends on RISCV && TIMER
> > + select RISCV_CLINT
>
> Since we have one generic timer for RISC-V now, I don't think it makes
> sense to specifically select the CLINT here.
>

Ah, yes!

> > + help
> > +   Select this to enable support for the timer as defined
> > +   by the RISC-V privileged architecture spec v1.10.
>
> nit: should we explicitly mention the version here? v1.11 will also
> include the mtime CSR, for example. This is not really important, just
> noticed it now.
>

OK, will remove it in v3.

> Looks good otherwise.
>
> Reviewed-by: Lukas Auer 
>

Regards,
Bin
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Re: [U-Boot] Please pull fsl-qoriq master

2018-12-10 Thread Tom Rini
On Mon, Dec 10, 2018 at 09:22:52PM +, York Sun wrote:

> Tom,
> 
> The following changes since commit d452f27b3ea806fd99aee4b73a723318032c1d5c:
> 
>   Prepare v2019.01-rc1 (2018-12-03 23:50:13 -0500)
> 
> are available in the Git repository at:
> 
>   git://git.denx.de/u-boot-fsl-qoriq.git tags/fsl-qoriq-for-v2019.01-rc2
> 
> for you to fetch changes up to 4909b89ec763f0c7030fa8474f9b6c5df866b01f:
> 
>   armv8: lx2160a: Add LX2160A SoC Support (2018-12-06 14:37:19 -0800)
> 

Note there were a lot of new defconfigs that I added to existing
MAINTAINER entries as best I could figure.  I've added my travis test to
make this fatal, after this PR.

Applied to u-boot/master, thanks!

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Re: [U-Boot] travis: Add check for configs without MAINTAINERS entries

2018-12-10 Thread Tom Rini
On Thu, Dec 06, 2018 at 04:39:43PM -0500, Tom Rini wrote:

> The genboardscfg.py script will emit a WARNING message if we have new
> defconfig files that are not listed in a MAINTAINERS file.  Make new
> cases of this a failure we catch in Travis-CI.
> 
> Signed-off-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] Please pull u-boot-rockchip/master (for-master-20181210)

2018-12-10 Thread Tom Rini
On Mon, Dec 10, 2018 at 02:34:42PM +0100, Philipp Tomsich wrote:

> Tom,
> 
> Here’s another pull-request for rc2.
> I expect a few more bug-fixes and DTS-changes later this week after having 
> talked to
> some of the stakeholders and also having seen internal review requests.
> 
> Build-test result for this one is at 
> https://travis-ci.org/ptomsich/u-boot-rockchip/builds/465884207
> 
> Thanks,
> Philipp.
> 
> 
> 
> The following changes since commit cde578ff36b15ec9c2033f03b94ecf809af7cc64:
> 
>   ARM: mvebu: restore license information in mv_ddr_plat.{c,h} (2018-12-09 
> 17:10:13 -0500)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-rockchip.git tags/for-master-20181210
> 
> for you to fetch changes up to eff43904b7f0c05ed316755e83b5474792059a5c:
> 
>   rockchip: rk3399-puma: enable fan53555 regulators in DTS (2018-12-10 
> 10:04:45 +0100)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [GIT PULL] u-boot-mips

2018-12-10 Thread Tom Rini
On Mon, Dec 10, 2018 at 07:04:32PM +0100, Daniel Schwierzeck wrote:

> Hi Tom,
> 
> please pull some fixes for MIPS BCM platforms.
> 
> Would you accept another pull request from u-boot-mips/next with the BMIPS 
> part
> of the original series "dma: add channels support"? The changes are isolated 
> to
> BMIPS platform and it would add a user for the new DMA channel support.

So long as it's isolated, yes.

> The following changes since commit cde578ff36b15ec9c2033f03b94ecf809af7cc64:
> 
>   ARM: mvebu: restore license information in mv_ddr_plat.{c,h} (2018-12-09 
> 17:10:13 -0500)
> 
> are available in the Git repository at:
> 
>   git://git.denx.de/u-boot-mips.git tags/mips-fixes-for-2019.01
> 
> for you to fetch changes up to 1410708eeb310e74af23dbee53a7774038cb3918:
> 
>   bmips: bcm6838: fix device tree warning (2018-12-10 18:47:13 +0100)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [RESEND PATCH v3 00/19] DM_I2C_COMPAT removal for all ti platforms

2018-12-10 Thread Simon Glass
Hi Tom,

On Fri, 7 Dec 2018 at 07:23, Tom Rini  wrote:
>
> On Fri, Dec 07, 2018 at 02:50:36PM +0100, Jean-Jacques Hiblot wrote:
>
> > This series remove the usage of the DM_I2C_COMPAT option for all the ti
> > platforms. It also takes this opportunity to not disable DM_I2C in the SPL.
> >
> > There are a couples of issues to fix:
> > - CMD_EEPROM does not support the DM API. Fixed by removing this option
> >   when DM_I2C is used without DM_I2C_COMPAT
> > - i2c_get_chip_for_busnum() does not work when OF_CONTROL is not used
> >   (as is the case with am33xx SPL).
> > - The I2C driver do not support DM_I2C without OF_CONTROL.
> > - Most of the PMIC drivers do not support the I2C DM API.
> > - Board detection is done prior DM initialization. Fixed by moving it after
> >   DM is initialized. That move breaks the DRA7 platforms (The fixes for
> >   that are at the last 5 patches this series)
> >
> > When all this is taken care of DM_I2C_COMPAT can be removed and DM_I2C
> > enabled in the SPL.
> >
> > This has been tested with the following boards:
> > - am437x SK
> > - am335x SK
> > - am335x beaglebone (both DM and non-DM config)
> > - dra76 evm
> > - am572 evm
> > - k2g evm
> >
> > The following targets may be impacted by the changes related to
> > SPL_OF_CONTROL and SPL_OF_PLATDATA:
> > - am3517_evm_defconfig
> > - omap3_logic_defconfig
> > - chromebit_mickey_defconfig
> > - chromebook_jerry_defconfig
> > - chromebook_minnie_defconfig
> > - evb-rk3399_defconfig
> > - rock_defconfig
> >
> > It would be nice it some of you could try to boot them.
>
> So I've just reviewed-by all of the TI parts.  Heiko, do you want this
> via the I2C tree?  Simon, do you want this via the DM tree?  Do both of
> you just want me to grab it instead?  The window on applying this for
> this release is closing quickly but this has been around for long enough
> that I'd like to see it go in.  Thanks!

Agreed. I am happy to take it, or you can. Please let me know.

Regards,
Simon
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Re: [U-Boot] [PATCH v2 32/32] dm: MIGRATION: spi: Update SPI driver status

2018-12-10 Thread Simon Glass
On Sun, 25 Nov 2018 at 10:40, Jagan Teki  wrote:
>
> Update the spi driver dm-conversion status.
>
> Signed-off-by: Jagan Teki 
> ---
>  doc/driver-model/MIGRATION.txt | 18 +-
>  1 file changed, 1 insertion(+), 17 deletions(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 0/7] Remove defines for SPI default speed and mode

2018-12-10 Thread Simon Goldschmidt

Am 10.12.2018 um 21:17 schrieb Adam Ford:

On Mon, Dec 10, 2018 at 1:20 PM Simon Goldschmidt
 wrote:


Am 10.12.2018 um 16:42 schrieb Adam Ford:

On Mon, Dec 10, 2018 at 4:54 AM Patrick Delaunay
 wrote:



This patch-set finish (after the last Simmon comment)
and depends on the previous serie named:
"Read default speed and mode values from DT"

http://patchwork.ozlabs.org/project/uboot/list/?series=76834

This patchset remove the unnecessary defines for SPI speed and mode
when DM mode is used for SPI (CONFIG_DM_SPI_FLASH).

Build result is available for the serie in gihub and travis:
https://github.com/patrickdelaunay/u-boot/tree/topic/spi
https://travis-ci.org/patrickdelaunay/u-boot/branches



After applying both of your patches, the da850evm no longer boots from
SPI flash.


I just did test this and it worked for me. Booting from QSPI on
socfpga_socrates and loading something in U-Boot via sf probe/sf read, so:
Tested-by: Simon Goldschmidt 



U-Boot SPL 2019.01-rc1-00754-g21fb8c41b1 (Dec 10 2018 - 09:02:28 -0600)
Trying to boot from SPI
Warning: SPI speed fallback to 100 kHz

[repeat in perpetuity]

U-Boot SPL 2019.01-rc1-00754-g21fb8c41b1 (Dec 10 2018 - 09:02:28 -0600)
Trying to boot from SPI
Warning: SPI speed fallback to 100 kHz

I then tried to apply the first patch, and it also fails booting.

I'll reply to the original series with a similar message.  Looking at
the comments, it looks like the code is assuming the DM_SPI_FLASH
means DT when in reality, the da850evm's SPL is using platdata.  I
looked at the platdata structure and I didn't see entries for SPI mode
or speed.  However, I cannot prove this is the issue on the da850evm
without diving into it a bit more.


Adam, from reading the da850-emv.dts and its '-u-boot.dtsi', it seems
the fdtgrep indicators to keep the flash for the SPL dts are missing
(compare to socfpga_cyclone5_socrates-u-boot.dtsi). In this case, the
code does not find a flash node.

The same would of course apply when using platdata.


I tried modifying the -u-boot.dtsi file to look like:

 {
  compatible = "m25p64", "spi-flash";
  u-boot,dm-pre-reloc;
};


That should be correct when using DTS. I have no idea about the platform 
data, sorry. That's a todo on my list to see if it gives me enough 
memory to enable FIT/signature support in my SPL, but I haven't got to 
compile it, yet, as cadence QSPI does not seem to support platdata, yet.




Unfortunately, I not get some build errors.  Do you have any
suggestions?   I know the dtsi didn't need the "u-boot,dm-pre-reloc;"
before this patch.


Well, that's only partly true. You need this information in SPL unless 
you go the hacky way of the define that Patrick wants to remove here. 
And the standard way to get this information into SPL is the devicetree.


I think Patrick did the right move to send this series so that we can 
drop the two defines and get the values from dts. Now platdata seems to 
be missing, so this must be solved.



  Might there be a platdata example I can follow?


As written above, I don't know of any. Even without build errors, I'm 
not sure it would work...


Regards,
Simon



The build errors as as follows:

make[2]: 'arch/arm/dts/da850-evm.dtb' is up to date.
   CAT u-boot-dtb.bin
   COPYu-boot.bin
   MKIMAGE u-boot.img
   MKIMAGE u-boot-dtb.img
   DTOC C  spl/dts/dt-platdata.c
   DTOC H  include/generated/dt-structs-gen.h
Traceback (most recent call last):
Traceback (most recent call last):
   File "./tools/dtoc/dtoc", line 109, in 
   File "./tools/dtoc/dtoc", line 109, in 
 options.output)
options.output)
   File "/home/aford/src/u-boot/tools/dtoc/dtb_platdata.py", line 564,
in run_steps
   File "/home/aford/src/u-boot/tools/dtoc/dtb_platdata.py", line 564,
in run_steps
 plat.scan_reg_sizes()
plat.scan_reg_sizes()
   File "/home/aford/src/u-boot/tools/dtoc/dtb_platdata.py", line 335,
in scan_reg_sizes
   File "/home/aford/src/u-boot/tools/dtoc/dtb_platdata.py", line 335,
in scan_reg_sizes
 addr = fdt_util.fdt_cells_to_cpu(val[i:], reg.na)
addr = fdt_util.fdt_cells_to_cpu(val[i:], reg.na)
   File "/home/aford/src/u-boot/tools/dtoc/fdt_util.py", line 54, in
fdt_cells_to_cpu
   File "/home/aford/src/u-boot/tools/dtoc/fdt_util.py", line 54, in
fdt_cells_to_cpu
 out = out << 32 | fdt32_to_cpu(val[1])
out = out << 32 | fdt32_to_cpu(val[1])
IndexErrorIndexError: : list index out of rangelist index out of range

scripts/Makefile.spl:287: recipe for target 'spl/dts/dt-platdata.c' failed
make[1]: *** [spl/dts/dt-platdata.c] Error 1
make[1]: *** Waiting for unfinished jobs
scripts/Makefile.spl:284: recipe for target
'include/generated/dt-structs-gen.h' failed
make[1]: *** [include/generated/dt-structs-gen.h] Error 1
Makefile:1591: recipe for target 'spl/u-boot-spl' failed
make: *** [spl/u-boot-spl] Error 2






Regards,
Simon



adam


Patrick Delaunay (7):
spi: update management of default speed and mode
spi: add comment for 

Re: [U-Boot] [PATCH v2 2/8] fdt: parse "reserved-memory" for memory reservation

2018-12-10 Thread Simon Glass
Hi Simon,

On Thu, 29 Nov 2018 at 13:40, Simon Goldschmidt
 wrote:
>
> On 27.11.2018 06:40, Simon Goldschmidt wrote:
> > On Tue, Nov 27, 2018 at 2:02 AM Simon Glass  wrote:
> >> Hi Simon,
> >>
> >> On Sat, 17 Nov 2018 at 02:18, Simon Goldschmidt
> >>  wrote:
> >>> boot_fdt_add_mem_rsv_regions() adds reserved memory sections to an lmb
> >>> struct. Currently, it only parses regions described by /memreserve/
> >>> entries.
> >>>
> >>> Extend this to the more commonly used scheme of the "reserved-memory"
> >>> node.
> >>>
> >>> Signed-off-by: Simon Goldschmidt 
> >>> ---
> >>>
> >>> Changes in v2:
> >>> - this patch is new in v2
> >>>
> >>>   common/image-fdt.c | 52 +++---
> >>>   1 file changed, 44 insertions(+), 8 deletions(-)
> >> Reviewed-by: Simon Glass 
> >>
> >> But it would be nice to convert this to livetree.
> > OK, let me try that ;-)
>
> So I tried to convert to livetree but since the function
> 'boot_fdt_add_mem_rsv_regions' is used on devicetrees loaded to boot
> Linux, I can't really change it (the 'of' functions use gd->fdt_addr' as
> fallback, which is wrong in that case).
>
> Converting to livetree for the new usecases ('load' and 'tftp' commands)
> would be possible, but would result in code duplication.
>
> What do you think?

Yes I understand. We don't have a livetree version of the setprop APIs.

Regards,
Simon
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Re: [U-Boot] Question regarding early pinctrl and driver model in u-boot

2018-12-10 Thread Simon Glass
Hi Lukasz,

On Thu, 6 Dec 2018 at 01:50, Lukasz Majewski  wrote:
>
> Hi Simon,
>
> > Hi Lukasz,
> >
> > On Mon, 3 Dec 2018 at 15:13, Lukasz Majewski  wrote:
> > >
> > > Dear All,
> > >
> > > I've stumbled upon a following issue:
> > >
> > > - I do have a vybrid SoC which is not using SPL. It only uses U-boot
> > >   proper (u-boot.vyb).
> > >
> > > - In the board_early_init_f() (when we are still in SRAM) I do
> > > perform pinctrl (pinmux) setup for UART1 (this is the console
> > > device).
> > >
> > > - I also do use ucalss-serial.c for this device and have proper
> > > pinmux definition for it in the *.dts file - but this is done
> > > latter.
> > >
> > > The problem is that, when I try to remove pinmux setup code
> > > (imx_iomux_v3_setup_multiple_pads()) from board_early_init_f(),
> > > then I do see uart output late (no U-boot early output - U-Boot
> > > 2018.11-00052-g6552299a40-dirty (Nov 23 2018 - 16:13:51 +0100)).
> > >
> > > The reason for this is the lack of pinctrl UART pins setup.
> > >
> > >
> > > Do you see any idea how to move to full dts support for uart? The
> > > uart driver and pinmux have defined DM_FLAG_PRE_RELOC.
> >
> > Is this due to pinconfig_post_bind() only operating after relocation?
>
> Please correct me if I'm wrong, but post_bind() callback is called with
> device_bind_* family of functions?

Yes

>
> Those functions - e.g. device_bind() are used in an interesting way
> - e.g.: drivers/gpio/s5p_gpio.c -> gpio_exynos_bind().

Yes, they create child devices.

>
> The problem seems to be with the time pinctrl device itself is probed
> (way after board_early_init_f()).
>
> IMHO it would be enough to "probe" pinctrl itself very early (before
> relocation - DDR setup) to just configure pins from iomux's pictrl_hog
> group (and put there DDR and uart pins) - not waiting for other devices
> to be "discovered" (like uart).

Well, even probing a single device will cause pinctrlt to be probed,
so shouldn't this happen automatically?

Regards,
Simon
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Re: [U-Boot] [PATCH v2] spl: implement CRC check on U-Boot uImage

2018-12-10 Thread Simon Glass
On Wed, 28 Nov 2018 at 13:52, Simon Goldschmidt
 wrote:
>
> SPL currently does not check uImage CRCs when loading U-Boot.
>
> This patch adds checking the uImage CRC when SPL loads U-Boot. It does
> this by reusing the existing config option SPL_CRC32_SUPPORT to allow
> leaving out the CRC check on boards where the additional code size or
> boot time is a problem (adding the CRC check currently adds ~1.4 kByte
> to flash).
>
> The SPL_CRC32_SUPPORT config option now gets enabled by default if SPL
> support for legacy images is enabled to check the CRC on all boards
> that don't actively take countermeasures.
>
> Signed-off-by: Simon Goldschmidt 
> ---
>
> Changes in v2:
> - added Kconfig option SPL_LEGACY_IMAGE_CRC_CHECK to enable/disable
>   checking CRC on legacy images
>
>  common/spl/Kconfig | 21 +++--
>  common/spl/spl.c   | 30 +-
>  include/spl.h  |  5 +
>  3 files changed, 49 insertions(+), 7 deletions(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH] misc: fs_loader: Switching private data allocation to DM auto allocation

2018-12-10 Thread Simon Glass
On Mon, 10 Dec 2018 at 06:29,  wrote:
>
> From: Tien Fong Chee 
>
> Switching private data manual allocation to driver model auto allocation
> so users no longer need to deallocate themself because this would be
> deallocated by driver model when the device is no longer required.
>
> Signed-off-by: Tien Fong Chee 
> ---
>  doc/driver-model/fs_firmware_loader.txt |   35 ++
>  drivers/misc/fs_loader.c|  108 
> +--
>  include/fs_loader.h |   32 +
>  3 files changed, 56 insertions(+), 119 deletions(-)
>

Looks nice, thanks.

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH v5 1/9] test: add test for lib/lmb.c

2018-12-10 Thread Simon Glass
On Sun, 9 Dec 2018 at 13:45, Simon Goldschmidt
 wrote:
>
> Add basic tests for the lmb memory allocation code used to reserve and
> allocate memory during boot.
>
> Signed-off-by: Simon Goldschmidt 
> ---
>
> Changes in v5:
> - this patch is new in v5
>
>  test/lib/Makefile |   1 +
>  test/lib/lmb.c| 297 ++
>  2 files changed, 298 insertions(+)
>  create mode 100644 test/lib/lmb.c

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH v5 7/9] bootm: use new common function lmb_init_and_reserve

2018-12-10 Thread Simon Glass
On Sun, 9 Dec 2018 at 13:46, Simon Goldschmidt
 wrote:
>
> This reduces duplicate code only.
>
> Signed-off-by: Simon Goldschmidt 
> ---
>
> Changes in v5: None
> Changes in v4: None
> Changes in v2: None
>
>  common/bootm.c | 8 ++--
>  1 file changed, 2 insertions(+), 6 deletions(-)
>

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Re: [U-Boot] [PATCH v2 1/2] bootcount: add uclass for bootcount

2018-12-10 Thread Simon Glass
Hi Philipp,

On Tue, 27 Nov 2018 at 15:00, Philipp Tomsich
 wrote:
>
> The original bootcount methods do not provide an interface to DM and
> rely on a static configuration for I2C devices (e.g. bus, chip-addr,
> etc. are configured through defines statically).  On a modern system
> that exposes multiple devices in a DTS-configurable way, this is less
> than optimal and a interface to DM-based devices will be desirable.
>
> This adds a simple driver that is DM-aware and configurable via DTS.
> If ambiguous (i.e. multiple bootcount-devices are present) the
> /chosen/u-boot,bootcount-device property can be used to select one
> bootcount device.
>
> Initially, this provides support for the following DM devices:
>  * RTC devices
>
> Signed-off-by: Philipp Tomsich 
> Tested-by: Klaus Goger 
>
> ---
>
> Changes in v2:
> - changed to provide a UCLASS-based implementation, as requested by
>   SJG in his earlier review
> - split off the RV3029 driver into a separate series
>
>  doc/device-tree-bindings/chosen.txt  | 30 
>  drivers/bootcount/Kconfig|  8 
>  drivers/bootcount/Makefile   |  2 +
>  drivers/bootcount/bootcount-uclass.c | 93 
> 
>  include/bootcount.h  | 48 +++
>  include/dm/uclass-id.h   |  1 +
>  6 files changed, 182 insertions(+)
>  create mode 100644 drivers/bootcount/bootcount-uclass.c

Just checking if there is a text and sandbox driver for this?

Regards,
SImon
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Re: [U-Boot] [PATCH] test: hexdump: fix misplaced return

2018-12-10 Thread Simon Glass
On Sun, 9 Dec 2018 at 13:53, Simon Goldschmidt
 wrote:
>
> Am 05.12.2018 um 13:55 schrieb Simon Glass:
> > On Tue, 4 Dec 2018 at 13:30, Simon Goldschmidt
> >  wrote:
> >>
> >> One of the hexdump tests in test/lib/hexdump.c returns right at the
> >> start of the function without testing anything.
> >>
> >> Fix this by moving the 'return 0;' statement to the end of the function.
> >>
> >> Signed-off-by: Simon Goldschmidt 
> >> ---
> >>
> >>   test/lib/hexdump.c | 4 ++--
> >>   1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > That's one way to make a test pass.
> >
> > Reviewed-by: Simon Glass 
>
> Is there a plan to make all tests under test/ run with 'make check'?
> Seems like this one is not included there?

Yes I agree, it needs to be added.

- Simon
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Re: [U-Boot] [PATCH v5 4/9] fdt: parse "reserved-memory" for memory reservation

2018-12-10 Thread Simon Glass
On Sun, 9 Dec 2018 at 13:46, Simon Goldschmidt
 wrote:
>
> boot_fdt_add_mem_rsv_regions() adds reserved memory sections to an lmb
> struct. Currently, it only parses regions described by /memreserve/
> entries.
>
> Extend this to the more commonly used scheme of the "reserved-memory"
> node.
>
> Signed-off-by: Simon Goldschmidt 
> ---
>
> Changes in v5: None
> Changes in v4:
> - fixed invalid 'if' statement without braces in boot_fdt_reserve_region
>
> Changes in v2:
> - this patch is new in v2
>
>  common/image-fdt.c | 53 +++---
>  1 file changed, 45 insertions(+), 8 deletions(-)
>

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Re: [U-Boot] [PATCH v5 6/9] fs: prevent overwriting reserved memory

2018-12-10 Thread Simon Glass
On Sun, 9 Dec 2018 at 13:46, Simon Goldschmidt
 wrote:
>
> This fixes CVE-2018-18440 ("insufficient boundary checks in filesystem
> image load") by using lmb to check the load size of a file against
> reserved memory addresses.
>
> Signed-off-by: Simon Goldschmidt 
> ---
>
> Changes in v5: None
> Changes in v4: None
> Changes in v2: None
>
>  fs/fs.c   | 56 ---
>  include/lmb.h |  2 ++
>  lib/lmb.c | 13 
>  3 files changed, 68 insertions(+), 3 deletions(-)
>

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Re: [U-Boot] [PATCH] sandbox: add memset_io(..), memcpy_fromio(..) and memcpy_toio(..)

2018-12-10 Thread Simon Glass
On Tue, 4 Dec 2018 at 12:35, Christian Gmeiner
 wrote:
>
> From: Christian GMEINER 
>
> These functions could be used by drivers.
>
> Signed-off-by: Christian GMEINER 
> ---
>  arch/sandbox/include/asm/io.h | 12 
>  1 file changed, 12 insertions(+)
>

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Re: [U-Boot] [PATCH v4 1/6] common: command: Fix command auto-completion

2018-12-10 Thread Simon Glass
Hi Boris,

On Mon, 3 Dec 2018 at 14:54, Boris Brezillon
 wrote:
>
> When auto-completing command arguments, the last argument is not
> necessarily the one we need to auto-complete. When the last character is
> a space, a tab or '\0' what we want instead is list all possible values,
> or if there's only one possible value, place this value on the command
> line instead of trying to suffix the last valid argument with missing
> chars.
>
> Signed-off-by: Boris Brezillon 
> Reviewed-by: Tom Rini 
> ---
> Changes in v4:
> -None
>
> Changes in v3:
> - Add Tom's R-b
>
> Changes in v2:
> - None
> ---
>  common/command.c | 12 ++--
>  1 file changed, 10 insertions(+), 2 deletions(-)

I wonder if you might be able to add a test for this into test/py/tests ?

It seems useful to ensure it doesn't break in future.

Regards,
Simon
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Re: [U-Boot] [PATCH v4 06/10] dm: usb: create a new UCLASS ID for USB gadget devices

2018-12-10 Thread Simon Glass
Hi Jean-Jacques,

On Thu, 29 Nov 2018 at 02:54, Jean-Jacques Hiblot  wrote:
>
> UCLASS_USB_DEV_GENERIC was meant for USB devices connected to host
> controllers, not gadget devices.
> Adding a new UCLASS for gadget devices alone.
>
> Also move the generic DM code for USB gadgets in a separate file for
> clarity.
>
> Signed-off-by: Jean-Jacques Hiblot 
>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
>  board/sunxi/board.c |  2 +-
>  drivers/usb/dwc3/dwc3-generic.c |  2 +-
>  drivers/usb/gadget/ether.c  |  2 +-
>  drivers/usb/gadget/udc/Makefile |  4 +++
>  drivers/usb/gadget/udc/udc-core.c   | 41 --
>  drivers/usb/gadget/udc/udc-uclass.c | 58 
> +
>  drivers/usb/musb-new/omap2430.c |  2 +-
>  drivers/usb/musb-new/sunxi.c|  2 +-
>  include/dm/uclass-id.h  |  1 +
>  9 files changed, 68 insertions(+), 46 deletions(-)
>  create mode 100644 drivers/usb/gadget/udc/udc-uclass.c

We should have a test for this, with a sandbox driver for this uclass,
as we have done for UCLASS_USB.

Regards,
Simon
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Re: [U-Boot] [RESEND PATCH v3 16/19] lib: fdtdec: Add function re-setup the fdt more effeciently

2018-12-10 Thread Simon Glass
On Fri, 7 Dec 2018 at 06:51, Jean-Jacques Hiblot  wrote:
>
> In some cases it may be useful to be able to change the fdt we have been
> using and use another one instead. For example, the TI platforms uses an
> EEPROM to store board information and, based on the type of board,
> different dtbs are used by the SPL. When DM_I2C is used, a first dtb must
> be used before the I2C is initialized and only then the final dtb can be
> selected.
> To speed up the process and reduce memory usage, introduce a new function
> fdtdec_setup_best_match() that re-use the DTBs loaded in memory by
> fdtdec_setup() to select the best match.
>
> Signed-off-by: Jean-Jacques Hiblot 
>
> ---
>
> Changes in v3:
> - fdtdec_resetup() need not call fdtdec_setup() when only a single DTB is
>   used.
> - Add documentation in README-fdt-control explaining why and how to use
>   fdtdec_resetup()
>
> Changes in v2: None
>
>  doc/README.fdt-control| 18 
>  include/asm-generic/global_data.h |  4 
>  include/fdtdec.h  | 21 +++
>  lib/fdtdec.c  | 43 
> ++-
>  4 files changed, 85 insertions(+), 1 deletion(-)
>

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Re: [U-Boot] [RFC] fit: include uncompression into fit_image_load

2018-12-10 Thread Simon Glass
Hi Simon,

On Tue, 20 Nov 2018 at 14:03, Simon Goldschmidt
 wrote:
>
> On Fri, Nov 16, 2018 at 3:05 AM Simon Glass  wrote:
> >
> > Hi,
> >
> > On 22 October 2018 at 11:55, Simon Goldschmidt
> >  wrote:
> > > On 22.10.2018 19:49, Simon Glass wrote:
> > >>
> > >> Hi Simon,
> > >>
> > >> On 19 October 2018 at 00:33, Simon Goldschmidt
> > >>  wrote:
> > >>>
> > >>> On 19.10.2018 05:25, Simon Glass wrote:
> > 
> >  Hi Simon,
> > 
> >  On 17 October 2018 at 03:41, Simon Goldschmidt
> >   wrote:
> > >
> > > On Wed, Oct 17, 2018 at 8:54 AM Alexander Graf  wrote:
> > >>
> > >>
> > >>
> > >> On 16.10.18 21:33, Simon Goldschmidt wrote:
> > >>>
> > >>> Currently, only the kernel can be compressed in a FIT image.
> > >>> By moving the uncompression logic to 'fit_image_load()', all types
> > >>> of images can be compressed.
> > >>>
> > >>> This works perfectly for me when using a gzip'ed FPGA image in
> > >>> a FIT image on a cyclone5 board (socrates). Also, a gzip'ed initrd
> > >>> being unzipped by U-Boot (not the kernel) worked.
> > >>>
> > >>> To clean this up, the uncompression function would have to be moved
> > >>> from bootm.c ('bootm_decomp_image()') to a more generic location,
> > >>> but I decided to keep it for now to make the patch easier to read.
> > >>> Because of this setup, the kernel is currently uncompressed twice.
> > >>> which doesn't work...
> > >>>
> > >>> There are, however, some more things to discuss:
> > >>> - The max. size passed to gunzip() (etc.) is not known before, so
> > >>> we currently configure this to 8 MByte in U-Boot (via
> > >>> CONFIG_SYS_BOOTM_LEN), which proved too small for my initrd...
> > 
> >  We need the uncompressed size. If the legacy header doesn't have, stop
> >  using it and use FIT?
> > 
> >  Some compression formats include that in a header I think. But we
> >  should record it in the U-Boot header.
> > >>>
> > >>>
> > >>> OK, we could embed this information into the FIT by extracting in
> > >>> 'mkimage'?
> > >>> That way, we know the uncompressed size...
> > >>
> > >> Yes. In fact I don't like the way it works at present. We have to
> > >> compress the data before putting it in the FIT, since the .its file
> > >> refers to the compressed data.
> > >>
> > >> I think it would be better for the ,its to refer to the original file,
> > >> and then mkimage do the compression as it generates the FIT. That way
> > >> it knows the size of the original data, and it is simpler for people
> > >> to build images, since they don't need to compress everything
> > >> beforehand.
> > >
> > >
> > > Hmm, OK, I think it should not be a problem to add this to mkimage.
> > > Only I don't know if this workflow change would be accepted by everyone or
> > > if the old style of using pre-compressed files would have to be somehow 
> > > kept
> > > working?
> >
> > I suggest supporting the old way with a flag. Also is it possible to
> > detect an already-compressed file and print an warning?
>
> I'm working on this and have it partly running, but I had to add this
> ugly "#ifndef USE_HOSTCC" thing to many files in lib/ to get the
> compression algorithms to compile for the tools.
>
> Is this acceptable? Or should we find a more generic approach, i.e.
> fixing the central include files (common.h, etc.) to handle
> USE_HOSTCC?

What sort of things don't build? It's not great, but it may be necessary.

Bonus points if the #ifdefs can be just in a header file, like mkimage.h

Regards,
Simon
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Re: [U-Boot] Please pull u-boot-dm

2018-12-10 Thread Simon Glass
Hi,

On Tue, 4 Dec 2018 at 21:10, Keerthy  wrote:
>
>
>
> On Friday 30 November 2018 08:25 PM, Tom Rini wrote:
> > On Thu, Nov 29, 2018 at 01:55:14PM -0700, Simon Glass wrote:
> >
> >> Hi Tom,
> >>
> >> The following changes since commit 
> >> e16c888fab5014b022d5781dc534f204460a073b:
> >>
> >>   Merge branch '2018-11-28-master-imports' (2018-11-28 23:04:58 -0500)
> >>
> >> are available in the Git repository at:
> >>
> >>   git://git.denx.de/u-boot-dm.git tags/pull-29nov18
> >>
> >> for you to fetch changes up to 5ca3927deff30458f5d5b384f6699f70b9509315:
> >>
> >>   core: ofnode: Add ofnode_get_addr_size_index (2018-11-29 09:30:06 -0700)
> >>
> >> Results here:
> >>
> >> https://travis-ci.org/sglass68/u-boot/builds/461363284
> >
> > NAK.  I don't know _why_ but I can confirm that both within travis:
> > https://travis-ci.org/trini/u-boot/jobs/461494951
> > and then locally when I installed clang-7.0 from https://apt.llvm.org/ I
> > see that:
> > 5ca3927deff30458f5d5b384f6699f70b9509315 is the first bad commit
> > commit 5ca3927deff30458f5d5b384f6699f70b9509315
> > Author: Keerthy 
> > Date:   Mon Nov 19 11:44:48 2018 +0530
> >
> > core: ofnode: Add ofnode_get_addr_size_index
> >
> > is totally breaking test.py on sandbox.  It still starts and I don't see
> > the obvious whats wrong, but I've bisected twice to this same commit.
> >
>
> Okay i am not sure either what is going wrong there. I will take a look at 
> this.

I am worried that this might be a unicode problem.

- build outputs error messages with backquotes, UTF-8, etc.
- pipe from builder thread to buildman breaks things into 4KB chunks
- sometimes a UTF-8 char break across a 4KB boundary
- I/O error results

I suspect this because buildman's unicode handling is actually a bit
broken - see how quotes come through in messages on some machines.

But it might be something else entirely.

Regards,
Simon
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Re: [U-Boot] [PATCH V2 2/2] spl: introduce function prototypes

2018-12-10 Thread Simon Glass
On Sat, 17 Nov 2018 at 02:10, Peng Fan  wrote:
>
> Introduce function prototypes for board_spl_fit_size_align and
> board_spl_fit_post_load
>
> Signed-off-by: Peng Fan 
> ---
>
> V2:
>  New file per Simon's comments
>
>  include/spl.h | 12 
>  1 file changed, 12 insertions(+)

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Re: [U-Boot] [PATCH] blk: Rework guard around part_init call

2018-12-10 Thread Simon Glass
On Sun, 25 Nov 2018 at 10:37, Tom Rini  wrote:
>
> The function part_init() will only be built when we have both
> CONFIG_PARTITIONS and CONFIG_HAVE_BLOCK_DEVICE set.  Protect the call to
> this function with both of these tests now.
>
> Cc: Simon Glass 
> Signed-off-by: Tom Rini 
> ---
>  drivers/block/blk-uclass.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Yes I think we need this for now.

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Re: [U-Boot] Port old board to Kconfig

2018-12-10 Thread Tom Rini
On Mon, Dec 10, 2018 at 11:13:31AM +1100, Tim Godfrey wrote:

> Hello!
> 
> I am working with a VAR-SOM-AM43 dev board from a company called Variscite.
> The company doesn't support u-boot builds for this board after the
> migration to Kconfig (maintenance happens on a 2014.07 branch), and I would
> like to port the board to more recent u-boot sources.
> 
> The SoC on the dev board is a Texas Instruments AM4738 ARM processor. My
> understanding of the abstraction layers is
>  - Architecture: ARM
>  - CPU: armv7
>  - SoC: AM33xx
>  - Board: varsomam43
>  - target build configurations

That sounds right, yes.

> The vendor supplied Yocto layer includes the board support source files
> (board.*, mux.c, etc), so my plan had been to build u-boot with the board
> (and config, based on the old boards.cfg entry) being varsomam43:
>  - CONFIG_VARSOMAM43 (board)
> - CONFIG_TARGET_VARSOMAM43 (target)
> 
> Once I had these legacy configurations working with the new source tree I
> was planning to migrate the code to the Kconfig way of doing things (which
> I'm still learning about).

You might want to look at board/compulab/ as there's a number of am33xx
and am43xx boards there that aren't the TI reference platforms.  There's
others too of course.

> That is my plan, but there are a few things that are unclear to me or that
> I am unsure of.
>  - Is my plan a sensible approach?

Yes.

>  - Do I understand the board/config layer division correctly? It is not
> clear to me that I shouldn't build my board with the AM43XX board
> definition (that is what the Variscite sources are based on anyway), with
> the dev board I am using defined as a target of that board. Should it be
> Soc:AM33XX, Board:AM43XX, Target:varsomam43; or SoC:AM33XX,
> Board:varsomam43, Target:varsomam43, or some combination thereof?

That sounds about right.

>  - Why do the AM43XX evm boards use the AM33XX SoC definition, even though
> they are a part of the AM43XX soc series (on chip peripherals), and the
> external differences (external peripherals, pin mux configurations) are
> configured in the evm definitions?

So, the am33xx line is really the 3rd generation platform from the
ti81xx line (that had gen 1/2).  And am43xx is the 4th generation.  For
historical reasons however, am33xx was the first one fully upstreamed
and so everyone else in the family keys off of that.

>  - In the current ti-u-boot source tree in am43xx_evm_defconfig
> CONFIG_AM43XX=y is defined, but not CONFIG_TARGET_AM43XX_EVM, and the
> Kconfig options in the board source file are conditional upon that symbol
> ("if TARGET_AM43XX_EVM"). How are the Kconfig defaults configured, and
> am43xx_evm.h selected for the AM43XX_EVM target?

You should just look at the main u-boot tree itself.  And note that the
defconfig files under configs/ contain only symbols that aren't deduced
when running "oldconfig" on top of it.

-- 
Tom


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Re: [U-Boot] [PATCH 0/6] Add support for MIPS Creator CI20

2018-12-10 Thread Ezequiel Garcia
On Mon, 2018-12-10 at 19:48 -0500, Tom Rini wrote:
> On Mon, Dec 10, 2018 at 05:35:56PM -0300, Ezequiel Garcia wrote:
> 
> > As the subject says, this series adds support for CI20.
> > 
> > Most of the work was done by Paul Burton, and then by Marek Vasut.
> > I've just rescued the work from the dark wastelands of Mordor,
> > did some cleaning here and there and submitted.
> > 
> > Patches 1, 2, and 4 are completely untouched. I've picked them
> > from Marek's tree.
> > 
> > For the MMC driver (patch 3) there is some cleanup, and some
> > fixes for proper DM migration.
> > 
> > Finally, patches 5 and 6 have been changed a bit: I've cleaned
> > up the devicetree, the board support files and the defconfig.
> > 
> > This is based on top of today's master (7ff485c68b7e) and has
> > been tested by SD-card booting both U-Boot and Linux. Booting
> > Linux via TFTP was also tested.
> > 
> > Please note that I've added Paul's SOB to all the patches
> > he authored, to make the authorship chain more clear.
> > 
> > Reviews and tests are welcome. Bikesheds not so much! ;-)
> 
> There's some stuff that's been noted that needs fixing and a v5 (I
> think, really) posted with those addressed.  But if there's nothing
> else, it would be good to finally get this platform in and I would be
> open to seeing it come in still at this point in the merge window.
> Thanks all!
> 

I think that if we are worried about those infinite loops in the drivers,
and stuff along that severity level, it won't hurt to fix them as
follow-up patches.

Thanks,
Eze

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Re: [U-Boot] [PATCH 0/6] Add support for MIPS Creator CI20

2018-12-10 Thread Tom Rini
On Mon, Dec 10, 2018 at 05:35:56PM -0300, Ezequiel Garcia wrote:

> As the subject says, this series adds support for CI20.
> 
> Most of the work was done by Paul Burton, and then by Marek Vasut.
> I've just rescued the work from the dark wastelands of Mordor,
> did some cleaning here and there and submitted.
> 
> Patches 1, 2, and 4 are completely untouched. I've picked them
> from Marek's tree.
> 
> For the MMC driver (patch 3) there is some cleanup, and some
> fixes for proper DM migration.
> 
> Finally, patches 5 and 6 have been changed a bit: I've cleaned
> up the devicetree, the board support files and the defconfig.
> 
> This is based on top of today's master (7ff485c68b7e) and has
> been tested by SD-card booting both U-Boot and Linux. Booting
> Linux via TFTP was also tested.
> 
> Please note that I've added Paul's SOB to all the patches
> he authored, to make the authorship chain more clear.
> 
> Reviews and tests are welcome. Bikesheds not so much! ;-)

There's some stuff that's been noted that needs fixing and a v5 (I
think, really) posted with those addressed.  But if there's nothing
else, it would be good to finally get this platform in and I would be
open to seeing it come in still at this point in the merge window.
Thanks all!

-- 
Tom


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Re: [U-Boot] [PATCH 0/6] Add support for MIPS Creator CI20

2018-12-10 Thread Tom Rini
On Mon, Dec 10, 2018 at 09:27:53PM -0300, Ezequiel Garcia wrote:
> On Mon, 2018-12-10 at 18:41 -0500, Tom Rini wrote:
> > On Mon, Dec 10, 2018 at 06:31:29PM -0300, Ezequiel Garcia wrote:
> > > On Mon, 2018-12-10 at 22:00 +0100, Andreas Färber wrote:
> > [snip]
> > > > Further, it would be very helpful - given the history of this patchset -
> > > > to indicate which toolchain and version you used for building this.
> > > > 
> > > 
> > > I've used gcc version 5.3.0 (Sourcery CodeBench Lite 2016.05-8),
> > > installed via Buildroot. Wasn't really paying attention to the toolchain.
> > > 
> > > I'll test with a recent gcc and post the results.
> > 
> > Just to chime in on this part for now, to be clear, it needs to work
> > with the default toolchain buildman uses, which is currently the gcc-7.3
> > kernel.org ones and buildman will fetch one for you.
> > 
> 
> Done!
> 
> $ strings u-boot | grep GCC
> mips-linux-gcc (GCC) 7.3.0
> GCC: (GNU) 7.3.0
> $ strings spl/u-boot-spl | grep GCC
> GCC: (GNU) 7.3.0
> 
> U-Boot 2019.01-rc1-00226-g208679cb9307 (Dec 10 2018 - 21:19:57 -0300)
> 
> CPU:   Ingenic JZ4780
> Board: Creator CI20 (rev.1)
> DRAM:  1 GiB
> MMC:   MSC: 0, MSC: 1
> Loading Environment from MMC... OK
> In:serial@10034000
> Out:   serial@10034000
> Err:   serial@10034000
> Net:   dm9000
> Hit any key to stop autoboot:  0 
> =>

Yay!

-- 
Tom


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Re: [U-Boot] [PATCH 0/6] Add support for MIPS Creator CI20

2018-12-10 Thread Ezequiel Garcia
On Mon, 2018-12-10 at 18:41 -0500, Tom Rini wrote:
> On Mon, Dec 10, 2018 at 06:31:29PM -0300, Ezequiel Garcia wrote:
> > On Mon, 2018-12-10 at 22:00 +0100, Andreas Färber wrote:
> [snip]
> > > Further, it would be very helpful - given the history of this patchset -
> > > to indicate which toolchain and version you used for building this.
> > > 
> > 
> > I've used gcc version 5.3.0 (Sourcery CodeBench Lite 2016.05-8),
> > installed via Buildroot. Wasn't really paying attention to the toolchain.
> > 
> > I'll test with a recent gcc and post the results.
> 
> Just to chime in on this part for now, to be clear, it needs to work
> with the default toolchain buildman uses, which is currently the gcc-7.3
> kernel.org ones and buildman will fetch one for you.
> 

Done!

$ strings u-boot | grep GCC
mips-linux-gcc (GCC) 7.3.0
GCC: (GNU) 7.3.0
$ strings spl/u-boot-spl | grep GCC
GCC: (GNU) 7.3.0

U-Boot 2019.01-rc1-00226-g208679cb9307 (Dec 10 2018 - 21:19:57 -0300)

CPU:   Ingenic JZ4780
Board: Creator CI20 (rev.1)
DRAM:  1 GiB
MMC:   MSC: 0, MSC: 1
Loading Environment from MMC... OK
In:serial@10034000
Out:   serial@10034000
Err:   serial@10034000
Net:   dm9000
Hit any key to stop autoboot:  0 
=>

Regards,
Eze

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Re: [U-Boot] [PATCH 04/19] cpu: Add a RISC-V CPU driver

2018-12-10 Thread Auer, Lukas
Hi Bin,

On Fri, 2018-12-07 at 21:59 +0800, Bin Meng wrote:
> Hi Lukas,
> 
> On Thu, Nov 15, 2018 at 5:57 AM Auer, Lukas
>  wrote:
> > 
> > Hi Bin,
> > 
> > On Tue, 2018-11-13 at 00:21 -0800, Bin Meng wrote:
> > > This adds a driver for RISC-V CPU. Note the driver will bind
> > > a RISC-V timer driver if "timebase-frequency" property is
> > > present in the device tree.
> > > 
> > > Signed-off-by: Bin Meng 
> > > ---
> > > 
> > 
> > Since we have the CPU driver, we could also enable CMD_CPU.
> > 
> 
> Agreed. Will do in v2.
> 
> > >  drivers/cpu/Kconfig |   6 +++
> > >  drivers/cpu/Makefile|   1 +
> > >  drivers/cpu/riscv_cpu.c | 117
> > > 
> > >  3 files changed, 124 insertions(+)
> > >  create mode 100644 drivers/cpu/riscv_cpu.c
> > > 
> > > diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig
> > > index d405200..3d5729f 100644
> > > --- a/drivers/cpu/Kconfig
> > > +++ b/drivers/cpu/Kconfig
> > > @@ -13,3 +13,9 @@ config CPU_MPC83XX
> > >   select CLK_MPC83XX
> > >   help
> > > Support CPU cores for SoCs of the MPC83xx series.
> > > +
> > > +config CPU_RISCV
> > > + bool "Enable RISC-V CPU driver"
> > > + depends on CPU && RISCV
> > > + help
> > > +   Support CPU cores for RISC-V architecture.
> > > diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile
> > > index 858b037..be0300c 100644
> > > --- a/drivers/cpu/Makefile
> > > +++ b/drivers/cpu/Makefile
> > > @@ -8,4 +8,5 @@ obj-$(CONFIG_CPU) += cpu-uclass.o
> > > 
> > >  obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o
> > >  obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o
> > > +obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o
> > >  obj-$(CONFIG_SANDBOX) += cpu_sandbox.o
> > > diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
> > > new file mode 100644
> > > index 000..23917db
> > > --- /dev/null
> > > +++ b/drivers/cpu/riscv_cpu.c
> > > @@ -0,0 +1,117 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright (C) 2018, Bin Meng 
> > > + */
> > > +
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +
> > > +static int riscv_cpu_get_desc(struct udevice *dev, char *buf,
> > > int
> > > size)
> > > +{
> > > + const char *isa;
> > > +
> > > + isa = dev_read_string(dev, "riscv,isa");
> > > + if (size < (strlen(isa) + 1))
> > > + return -ENOSPC;
> > > +
> > > + strcpy(buf, isa);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int riscv_cpu_get_info(struct udevice *dev, struct
> > > cpu_info
> > > *info)
> > > +{
> > > + const char *mmu;
> > > +
> > > + dev_read_u32(dev, "clock-frequency", (u32 *)
> > > >cpu_freq);
> > > +
> > > + mmu = dev_read_string(dev, "mmu-type");
> > > + if (!mmu)
> > > + info->features |= BIT(CPU_FEAT_MMU);
> > > +
> > 
> > BBL also disables CPUs without an MMU, so it is good to have this
> > information. Where would you disable the CPU in U-Boot? Maybe in
> > arch_fixup_fdt() or in the CPU driver?
> > 
> 
> I think disabling CPU only needs to be done if booting to S-mode
> payload. If booting to M-mode payload we should leave it as it is.
> arch_fixup_fdt() can be a good place to fix up these sort of things
> but I think that should be another patch.
> 

Makes sense. At the moment this is done in BBL anyways, so this is
something we only have to add once we have the OpenSBI.

Thanks,
Lukas

> > > + return 0;
> > > +}
> > > +
> > > +static int riscv_cpu_get_count(struct udevice *dev)
> > > +{
> > > + ofnode node;
> > > + int num = 0;
> > > +
> > > + ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
> > > + const char *device_type;
> > > +
> > > + device_type = ofnode_read_string(node,
> > > "device_type");
> > > + if (!device_type)
> > > + continue;
> > > + if (strcmp(device_type, "cpu") == 0)
> > > + num++;
> > > + }
> > > +
> > > + return num;
> > > +}
> > > +
> > > +static int riscv_cpu_bind(struct udevice *dev)
> > > +{
> > > + struct cpu_platdata *plat = dev_get_parent_platdata(dev);
> > > + struct driver *drv;
> > > + struct udevice *timer;
> > > + int ret;
> > > +
> > > + /* save the hart id */
> > > + plat->cpu_id = dev_read_addr(dev);
> > > +
> > > + /* first examine the property in current cpu node */
> > > + ret = dev_read_u32(dev, "timebase-frequency", 
> > > > timebase_freq);
> > > 
> > > + /* if not found, then look at the parent /cpus node */
> > > + if (ret)
> > > + dev_read_u32(dev->parent, "timebase-frequency",
> > > +  >timebase_freq);
> > > +
> > > + /*
> > > +  * Bind riscv-timer driver on hart 0
> > > +  *
> > > +  * We only instantiate one timer device which is enough for
> > > U-
> > > Boot.
> > > +  * Pass the "timebase-frequency" value as the driver data
> > > for
> > > 

Re: [U-Boot] [PATCH v2 16/20] riscv: Do some basic architecture level cpu initialization

2018-12-10 Thread Auer, Lukas
Hi Bin,

On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> Implement arch_cpu_init() to do some basic architecture level cpu
> initialization, like FPU enable, etc.
> 
> Signed-off-by: Bin Meng 
> 
> ---
> 
> Changes in v2:
> - use csr_set() to set MSTATUS_FS
> - only enabling the cycle, time, and instret counters
> - change to use satp
> 
>  arch/riscv/cpu/cpu.c | 19 +++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> index 3858e51..194799c 100644
> --- a/arch/riscv/cpu/cpu.c
> +++ b/arch/riscv/cpu/cpu.c
> @@ -7,6 +7,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  /*
>   * prior_stage_fdt_address must be stored in the data section since
> it is used
> @@ -67,3 +68,21 @@ int arch_early_init_r(void)
>  
>   return 0;
>  }
> +
> +int arch_cpu_init(void)
> +{
> + /* Enable FPU */
> + if (supports_extension('d') || supports_extension('f')) {

supports_extension does not work when running in supervisor mode
(unless BBL is patched). Can we maybe use the CPU driver here?

> + csr_set(MODE_PREFIX(status), MSTATUS_FS);
> + csr_write(fcsr, 0);
> + }
> +
> + /* Enable perf counters for cycle, time, and instret counters
> only */
> + csr_write(MODE_PREFIX(counteren), GENMASK(2, 0));

I would tend to only enable this in mcounteren, so for the supervisor-
mode. Linux can still enable the counters for user-mode if required.

> +
> + /* Disable paging */
> + if (supports_extension('s'))
> + csr_write(satp, 0);

This should only be done, when running in machine mode. In supervisor
mode this would cause issues if we have something other than an
identity-mapping or paging disabled.

Thanks,
Lukas

> +
> + return 0;
> +}
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Re: [U-Boot] [PATCH 6/7] doc: android: Add simple guide for A/B updates

2018-12-10 Thread Simon Glass
Hi,

On Mon, 10 Dec 2018 at 12:11, Ruslan Trofymenko
 wrote:
>
> Hi Simon,
>
> On Thu, 6 Dec 2018 at 03:31, Simon Glass  wrote:
> >
> > Hi,
> >
> > On Tue, 27 Nov 2018 at 12:57, Ruslan Trofymenko
> >  wrote:
> > >
> > > Add a short documentation for A/B enablement and 'android_ab_select'
> > > command usage.
> > >
> > > Signed-off-by: Ruslan Trofymenko 
> > > ---
> > >  doc/README.android-ab | 67 
> > > +++
> > >  1 file changed, 67 insertions(+)
> > >  create mode 100644 doc/README.android-ab
> > >
> > > diff --git a/doc/README.android-ab b/doc/README.android-ab
> > > new file mode 100644
> > > index 000..230088c
> > > --- /dev/null
> > > +++ b/doc/README.android-ab
> > > @@ -0,0 +1,67 @@
> > > +Android A/B updates
> > > +===
> > > +
> > > +Overview
> > > +
> > > +
> > > +A/B system updates ensures modern approach for system update. This 
> > > feature
> > > +allows one to use two sets (or more) of partitions referred to as slots
> > > +(normally slot A and slot B). The system runs from the current slot 
> > > while the
> > > +partitions in the unused slot can be updated [1].
> > > +
> > > +A/B enablement
> > > +--
> > > +
> > > +The A/B updates support can be activated by specifying next options in
> > > +your board configuration file:
> > > +
> > > +CONFIG_ANDROID_AB=y
> > > +CONFIG_CMD_ANDROID_AB_SELECT=y
> > > +
> > > +The disk space on target device must be partitioned in a way so that each
> > > +partition which needs to be updated has two or more instances. The name 
> > > of
> > > +each instance must be formed by adding suffixes: _a, _b, _c, etc.
> > > +For example: boot_a, boot_b, system_a, system_b, vendor_a, vendor_b.
> > > +
> > > +As a result you can use 'android_ab_select' command to ensure A/B boot 
> > > process
> > > +in your boot script. This command analyzes and processes A/B metadata 
> > > stored
> > > +on a special partition (e.g. "misc") and determines which slot should be 
> > > used
> > > +for booting up.
> > > +
> > > +Command usage
> > > +-
> > > +
> > > +android_ab_select   
> > > 
> >
> > Can we have a shorter command?
> >
> > Perhaps we need a new 'android' command with an 'ab_select'
> > subcommand? Then the automatica abbreviation will work.
> >
>
> Agree with all your previous comments, will send v2 shortly. But this
> one I'd like to leave as is (I will drop android_ prefix though). I
> think adding "android" command may lead to unneeded architecture
> complexity in future, e.g.:
>   - we will need to re-work next commands as sub-commands of "android"
> command: fastboot, dtimg, mmc_swrite (which can be hard as ab_select
> command file has BSD license and other commands have GPL license)
>  - we will need to implement sub-sub-commands (e.g. for "android dtimg
> dump ..." etc.)
>  - having "android" command can be inconvenient for users and may
> break existing API (e.g. it will force users to use "android fastboot"
> instead of just "fastboot" command)
>  - actually I don't see any namespace issues that can be solved by
> adding "android" command
>
> Also, in subsequent patch, I will add the dedicated menu option for
> Android-related commands and will pull all existing Android commands
> (along with ab_select) to that menu entry.
>
> So I hope it's fine with you if I leave this command as "ab_select"?

Yes I think that is OK.

Regards,
Simon
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Re: [U-Boot] [PATCH v2 15/20] riscv: Add indirect stringification to csr_xxx ops

2018-12-10 Thread Auer, Lukas
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> With current csr_xxx ops, we cannot pass a macro to parameter
> 'csr', hence we need add another level to allow the parameter
> to be a macro itself, aka indirect stringification.
> 
> Signed-off-by: Bin Meng 
> 
> ---
> 
> Changes in v2:
> - new patch to add indirect stringification to csr_xxx ops
> 
>  arch/riscv/include/asm/csr.h | 16 +---
>  1 file changed, 9 insertions(+), 7 deletions(-)
> 

Reviewed-by: Lukas Auer 
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Re: [U-Boot] [PATCH v2 14/20] riscv: Add exception codes for xcause register

2018-12-10 Thread Auer, Lukas
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> This adds all exception codes in encoding.h.
> 
> Signed-off-by: Bin Meng 
> ---
> 
> Changes in v2: None
> 
>  arch/riscv/include/asm/encoding.h | 15 +++
>  1 file changed, 15 insertions(+)
> 

Reviewed-by: Lukas Auer 
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Re: [U-Boot] [PATCH v2 13/20] riscv: Add CSR numbers

2018-12-10 Thread Auer, Lukas
Hi Bin,

On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> The standard RISC-V ISA sets aside a 12-bit encoding space for up
> to 4096 CSRs. This adds all known CSR numbers as defined in the
> RISC-V Privileged Architecture Version 1.10.
> 
> Signed-off-by: Bin Meng 
> ---
> 
> Changes in v2: None
> 
>  arch/riscv/include/asm/encoding.h | 219
> ++
>  1 file changed, 219 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/encoding.h
> b/arch/riscv/include/asm/encoding.h
> index 97cf906..c910d5c 100644
> --- a/arch/riscv/include/asm/encoding.h
> +++ b/arch/riscv/include/asm/encoding.h
> @@ -152,6 +152,225 @@
>  #define RISCV_PGSHIFT 12
>  #define RISCV_PGSIZE BIT(RISCV_PGSHIFT)
>  
> +/* CSR numbers */
> +#define CSR_FFLAGS   0x1
> +#define CSR_FRM  0x2
> +#define CSR_FCSR 0x3
> +
> +#define CSR_SSTATUS  0x100

sedeleg (0x102) and sideleg (0x103) are missing here.

The user-mode CSRs are also missing. Not sure if we should include them
since I don't expect that we have to emulate them in machine mode.

Looks good otherwise.
Reviewed-by: Lukas Auer 

Thanks,
Lukas

> +#define CSR_SIE  0x104
> +#define CSR_STVEC0x105
> +#define CSR_SCOUNTEREN   0x106
> +#define CSR_SSCRATCH 0x140
> +#define CSR_SEPC 0x141
> +#define CSR_SCAUSE   0x142
> +#define CSR_STVAL0x143
> +#define CSR_SIP  0x144
> +#define CSR_SATP 0x180
> +
> +#define CSR_MSTATUS  0x300
> +#define CSR_MISA 0x301
> +#define CSR_MEDELEG  0x302
> +#define CSR_MIDELEG  0x303
> +#define CSR_MIE  0x304
> +#define CSR_MTVEC0x305
> +#define CSR_MCOUNTEREN   0x306
> +#define CSR_MHPMEVENT3   0x323
> +#define CSR_MHPMEVENT4   0x324
> +#define CSR_MHPMEVENT5   0x325
> +#define CSR_MHPMEVENT6   0x326
> +#define CSR_MHPMEVENT7   0x327
> +#define CSR_MHPMEVENT8   0x328
> +#define CSR_MHPMEVENT9   0x329
> +#define CSR_MHPMEVENT10  0x32a
> +#define CSR_MHPMEVENT11  0x32b
> +#define CSR_MHPMEVENT12  0x32c
> +#define CSR_MHPMEVENT13  0x32d
> +#define CSR_MHPMEVENT14  0x32e
> +#define CSR_MHPMEVENT15  0x32f
> +#define CSR_MHPMEVENT16  0x330
> +#define CSR_MHPMEVENT17  0x331
> +#define CSR_MHPMEVENT18  0x332
> +#define CSR_MHPMEVENT19  0x333
> +#define CSR_MHPMEVENT20  0x334
> +#define CSR_MHPMEVENT21  0x335
> +#define CSR_MHPMEVENT22  0x336
> +#define CSR_MHPMEVENT23  0x337
> +#define CSR_MHPMEVENT24  0x338
> +#define CSR_MHPMEVENT25  0x339
> +#define CSR_MHPMEVENT26  0x33a
> +#define CSR_MHPMEVENT27  0x33b
> +#define CSR_MHPMEVENT28  0x33c
> +#define CSR_MHPMEVENT29  0x33d
> +#define CSR_MHPMEVENT30  0x33e
> +#define CSR_MHPMEVENT31  0x33f
> +#define CSR_MSCRATCH 0x340
> +#define CSR_MEPC 0x341
> +#define CSR_MCAUSE   0x342
> +#define CSR_MTVAL0x343
> +#define CSR_MIP  0x344
> +#define CSR_PMPCFG0  0x3a0
> +#define CSR_PMPCFG1  0x3a1
> +#define CSR_PMPCFG2  0x3a2
> +#define CSR_PMPCFG3  0x3a3
> +#define CSR_PMPADDR0 0x3b0
> +#define CSR_PMPADDR1 0x3b1
> +#define CSR_PMPADDR2 0x3b2
> +#define CSR_PMPADDR3 0x3b3
> +#define CSR_PMPADDR4 0x3b4
> +#define CSR_PMPADDR5 0x3b5
> +#define CSR_PMPADDR6 0x3b6
> +#define CSR_PMPADDR7 0x3b7
> +#define CSR_PMPADDR8 0x3b8
> +#define CSR_PMPADDR9 0x3b9
> +#define CSR_PMPADDR100x3ba
> +#define CSR_PMPADDR110x3bb
> +#define CSR_PMPADDR120x3bc
> +#define CSR_PMPADDR130x3bd
> +#define CSR_PMPADDR140x3be
> +#define CSR_PMPADDR150x3bf
> +
> +#define CSR_TSELECT  0x7a0
> +#define CSR_TDATA1   0x7a1
> +#define CSR_TDATA2   0x7a2
> +#define CSR_TDATA3   0x7a3
> +#define CSR_DCSR 0x7b0
> +#define CSR_DPC  0x7b1
> +#define CSR_DSCRATCH 0x7b2
> +
> +#define CSR_MCYCLE   0xb00
> +#define CSR_MINSTRET 0xb02
> +#define CSR_MHPMCOUNTER3 0xb03
> +#define CSR_MHPMCOUNTER4 0xb04
> +#define CSR_MHPMCOUNTER5 0xb05
> +#define CSR_MHPMCOUNTER6 0xb06
> +#define CSR_MHPMCOUNTER7 0xb07
> +#define CSR_MHPMCOUNTER8 0xb08
> +#define CSR_MHPMCOUNTER9 0xb09
> +#define CSR_MHPMCOUNTER100xb0a
> +#define CSR_MHPMCOUNTER110xb0b
> +#define CSR_MHPMCOUNTER120xb0c
> +#define CSR_MHPMCOUNTER130xb0d
> +#define CSR_MHPMCOUNTER140xb0e
> +#define 

Re: [U-Boot] [PATCH 0/6] Add support for MIPS Creator CI20

2018-12-10 Thread Tom Rini
On Mon, Dec 10, 2018 at 06:31:29PM -0300, Ezequiel Garcia wrote:
> On Mon, 2018-12-10 at 22:00 +0100, Andreas Färber wrote:
[snip]
> > Further, it would be very helpful - given the history of this patchset -
> > to indicate which toolchain and version you used for building this.
> > 
> 
> I've used gcc version 5.3.0 (Sourcery CodeBench Lite 2016.05-8),
> installed via Buildroot. Wasn't really paying attention to the toolchain.
> 
> I'll test with a recent gcc and post the results.

Just to chime in on this part for now, to be clear, it needs to work
with the default toolchain buildman uses, which is currently the gcc-7.3
kernel.org ones and buildman will fetch one for you.

-- 
Tom


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Re: [U-Boot] [PATCH v2 09/20] riscv: Implement riscv_get_time() API using rdtime instruction

2018-12-10 Thread Auer, Lukas
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> From: Anup Patel 
> 
> This adds an implementation of riscv_get_time() API that is using
> rdtime instruction.
> 
> This is the case for S-mode U-Boot, and is useful for processors
> that support rdtime in M-mode too.
> 
> Signed-off-by: Anup Patel 
> Signed-off-by: Bin Meng 
> 
> ---
> 
> Changes in v2:
> - incorporated and reworked Anup's S-mode timer patch
>   @ http://patchwork.ozlabs.org/patch/1006663/
> 
>  arch/riscv/Kconfig  |  8 
>  arch/riscv/lib/Makefile |  1 +
>  arch/riscv/lib/rdtime.c | 36 
>  3 files changed, 45 insertions(+)
>  create mode 100644 arch/riscv/lib/rdtime.c
> 

Reviewed-by: Lukas Auer 
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Re: [U-Boot] [PATCH v2 08/20] riscv: Add a SYSCON driver for SiFive's Core Local Interruptor

2018-12-10 Thread Auer, Lukas
Hi Bin,

On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> This adds U-Boot syscon driver for SiFive's Core Local Interruptor
> (CLINT). The CLINT block holds memory-mapped control and status
> registers associated with software and timer interrupts.
> 
> This driver implements the riscv_get_time() API as required by
> the generic RISC-V timer driver, as well as some other APIs that
> are needed for handling IPI.
> 
> Signed-off-by: Bin Meng 
> 
> ---
> 
> Changes in v2:
> - rename the driver name to sifive_clint
> - save the clint base address to arch specific global data to support
>   pre-relocation stage
> - remove the probe routine
> - add riscv_clear_ipi() API
> 
>  arch/riscv/Kconfig   |  9 +
>  arch/riscv/include/asm/global_data.h |  3 ++
>  arch/riscv/include/asm/syscon.h  | 19 ++
>  arch/riscv/lib/Makefile  |  1 +
>  arch/riscv/lib/sifive_clint.c| 68
> 
>  5 files changed, 100 insertions(+)
>  create mode 100644 arch/riscv/include/asm/syscon.h
>  create mode 100644 arch/riscv/lib/sifive_clint.c
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 55c60e4..f513f52 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -95,4 +95,13 @@ config 32BIT
>  config 64BIT
>   bool
>  
> +config SIFIVE_CLINT
> + bool
> + depends on RISCV_MMODE
> + select REGMAP
> + select SYSCON
> + help
> +   The SiFive CLINT block holds memory-mapped control and status
> registers
> +   associated with software and timer interrupts.
> +
>  endmenu
> diff --git a/arch/riscv/include/asm/global_data.h
> b/arch/riscv/include/asm/global_data.h
> index 4d5d623..46fcfab 100644
> --- a/arch/riscv/include/asm/global_data.h
> +++ b/arch/riscv/include/asm/global_data.h
> @@ -12,6 +12,9 @@
>  
>  /* Architecture-specific global data */
>  struct arch_global_data {
> +#ifdef CONFIG_SIFIVE_CLINT
> + void __iomem *clint;/* clint base address */
> +#endif
>  };
>  
>  #include 
> diff --git a/arch/riscv/include/asm/syscon.h
> b/arch/riscv/include/asm/syscon.h
> new file mode 100644
> index 000..d311ee6
> --- /dev/null
> +++ b/arch/riscv/include/asm/syscon.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2018, Bin Meng 
> + */
> +
> +#ifndef _ASM_SYSCON_H
> +#define _ASM_SYSCON_H
> +
> +/*
> + * System controllers in a RISC-V system
> + *
> + * So far only SiFive's Core Local Interruptor (CLINT) is defined.
> + */
> +enum {
> + RISCV_NONE,
> + RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
> +};
> +
> +#endif /* _ASM_SYSCON_H */
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> index b58db89..b13c876 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -9,6 +9,7 @@
>  obj-$(CONFIG_CMD_BOOTM) += bootm.o
>  obj-$(CONFIG_CMD_GO) += boot.o
>  obj-y+= cache.o
> +obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
>  obj-y+= interrupts.o
>  obj-y+= reset.o
>  obj-y   += setjmp.o
> diff --git a/arch/riscv/lib/sifive_clint.c
> b/arch/riscv/lib/sifive_clint.c
> new file mode 100644
> index 000..2d4bfac
> --- /dev/null
> +++ b/arch/riscv/lib/sifive_clint.c
> @@ -0,0 +1,68 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018, Bin Meng 
> + *
> + * U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT).
> + * The CLINT block holds memory-mapped control and status registers
> + * associated with software and timer interrupts.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/* MSIP registers */
> +#define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4)
> +/* mtime compare register */
> +#define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 +
> (hart) * 8)
> +/* mtime register */
> +#define MTIME_REG(base)  ((ulong)(base) +
> 0xbff8)
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +u64 riscv_get_time(void)
> +{
> + if (!gd->arch.clint)
> + gd->arch.clint =
> syscon_get_first_range(RISCV_SYSCON_CLINT);

This should work, but it is probably better to add error handling here
to detect if syscon_get_first_range has returned an error. The error
could then be propagated in the function return value. Same thing in
the functions below.

Thanks,
Lukas

> +
> + return readq((void __iomem *)MTIME_REG(gd->arch.clint));
> +}
> +
> +void riscv_set_timecmp(int hart, u64 cmp)
> +{
> + if (!gd->arch.clint)
> + gd->arch.clint =
> syscon_get_first_range(RISCV_SYSCON_CLINT);
> +
> + writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint,
> hart));
> +}
> +
> +void riscv_send_ipi(int hart)
> +{
> + if (!gd->arch.clint)
> + gd->arch.clint =
> syscon_get_first_range(RISCV_SYSCON_CLINT);
> +
> + writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
> +}
> +
> +void riscv_clear_ipi(int hart)
> +{
> + if (!gd->arch.clint)
> +

Re: [U-Boot] [PATCH v2 07/20] riscv: Introduce a Kconfig option for machine mode

2018-12-10 Thread Auer, Lukas
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> From: Anup Patel 
> 
> So far we have a Kconfig option for supervisor mode. This adds an
> option for the machine mode.
> 
> Signed-off-by: Anup Patel 
> Signed-off-by: Bin Meng 
> 
> ---
> 
> Changes in v2:
> - incorporated and reworked Anup's S-mode timer patch
>   @ http://patchwork.ozlabs.org/patch/1006663/
> 
>  arch/riscv/Kconfig | 21 -
>  1 file changed, 16 insertions(+), 5 deletions(-)
> 

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Re: [U-Boot] [PATCH v2 06/20] riscv: ax25: Hide the ax25-specific Kconfig option

2018-12-10 Thread Auer, Lukas
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> There is no need to expose RISCV_NDS to the Kconfig menu as it is
> an ax25-specific option.
> 
> Signed-off-by: Bin Meng 
> ---
> 
> Changes in v2: None
> 
>  arch/riscv/cpu/ax25/Kconfig | 8 +++-
>  1 file changed, 3 insertions(+), 5 deletions(-)
> 

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Re: [U-Boot] [PATCH v2 05/20] timer: Add generic driver for RISC-V privileged architecture defined timer

2018-12-10 Thread Auer, Lukas
Hi Bin,

On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> RISC-V privileged architecture v1.10 defines a real-time counter,
> exposed as a memory-mapped machine-mode register - mtime. mtime must
> run at constant frequency, and the platform must provide a mechanism
> for determining the timebase of mtime. The mtime register has a
> 64-bit precision on all RV32, RV64, and RV128 systems.
> 
> Different platform may have different implementation of the mtime
> block hence an API riscv_get_time() is required by this driver for
> platform codes to hide such implementation details. For example,
> on some platforms mtime is provided by the CLINT module, while on
> some other platforms a simple 'rdtime' can be used to get the timer
> counter.
> 
> With this timer driver the U-Boot timer functionalities like delay
> works correctly now.
> 
> Signed-off-by: Bin Meng 
> 
> ---
> 
> Changes in v2:
> - remove the probe to syscon driver in the timer probe, to make the
>   driver generic, and rely on platform codes to provide the API
>   riscv_get_time().
> 
>  drivers/timer/Kconfig   |  8 +++
>  drivers/timer/Makefile  |  1 +
>  drivers/timer/riscv_timer.c | 57
> +
>  3 files changed, 66 insertions(+)
>  create mode 100644 drivers/timer/riscv_timer.c
> 
> diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
> index b0e6f32..8995979 100644
> --- a/drivers/timer/Kconfig
> +++ b/drivers/timer/Kconfig
> @@ -126,6 +126,14 @@ config OMAP_TIMER
>   help
> Select this to enable an timer for Omap devices.
>  
> +config RISCV_TIMER
> + bool "RISC-V timer support"
> + depends on RISCV && TIMER
> + select RISCV_CLINT

Since we have one generic timer for RISC-V now, I don't think it makes
sense to specifically select the CLINT here.

> + help
> +   Select this to enable support for the timer as defined
> +   by the RISC-V privileged architecture spec v1.10.

nit: should we explicitly mention the version here? v1.11 will also
include the mtime CSR, for example. This is not really important, just
noticed it now.

Looks good otherwise.

Reviewed-by: Lukas Auer 

Thanks,
Lukas

> +
>  config ROCKCHIP_TIMER
>   bool "Rockchip timer support"
>   depends on TIMER
> diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
> index c4fbab2..d0bf218 100644
> --- a/drivers/timer/Makefile
> +++ b/drivers/timer/Makefile
> @@ -13,6 +13,7 @@ obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-
> ttc.o
>  obj-$(CONFIG_DESIGNWARE_APB_TIMER)   += dw-apb-timer.o
>  obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
>  obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
> +obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
>  obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
>  obj-$(CONFIG_SANDBOX_TIMER)  += sandbox_timer.o
>  obj-$(CONFIG_STI_TIMER)  += sti-timer.o
> diff --git a/drivers/timer/riscv_timer.c
> b/drivers/timer/riscv_timer.c
> new file mode 100644
> index 000..ef3bedc
> --- /dev/null
> +++ b/drivers/timer/riscv_timer.c
> @@ -0,0 +1,57 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018, Bin Meng 
> + *
> + * RISC-V privileged architecture defined generic timer driver
> + *
> + * This driver relies on RISC-V platform codes to provide the
> essential API
> + * riscv_get_time() which is supposed to return the timer counter as
> defined
> + * by the RISC-V privileged architecture spec v1.10.
> + *
> + * This driver can be used by both M-mode and S-mode.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/**
> + * riscv_get_time() - get the timer counter
> + *
> + * Platform codes should provide this API in order to make this
> driver function.
> + *
> + * @return:  64-bit timer counter as defined by the RISC-V
> privileged
> + *   architecture spec v1.10.
> + */
> +extern u64 riscv_get_time(void);
> +
> +static int riscv_timer_get_count(struct udevice *dev, u64 *count)
> +{
> + *count = riscv_get_time();
> +
> + return 0;
> +}
> +
> +static int riscv_timer_probe(struct udevice *dev)
> +{
> + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> +
> + /* clock frequency was passed from the cpu driver as driver
> data */
> + uc_priv->clock_rate = dev->driver_data;
> +
> + return 0;
> +}
> +
> +static const struct timer_ops riscv_timer_ops = {
> + .get_count = riscv_timer_get_count,
> +};
> +
> +U_BOOT_DRIVER(riscv_timer) = {
> + .name = "riscv_timer",
> + .id = UCLASS_TIMER,
> + .probe = riscv_timer_probe,
> + .ops = _timer_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
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Re: [U-Boot] ARM: rockchip: rv1108: Fix booting with initramfs

2018-12-10 Thread Philipp Tomsich
+ Heiko

> On 10.12.2018, at 01:56, Tom Rini  wrote:
> 
> On Mon, Dec 10, 2018 at 01:38:36AM +0100, Philipp Tomsich wrote:
>> Tom,
>> 
>> On 10.12.2018, at 01:28, Tom Rini  wrote:
>>> 
>>> On Mon, Dec 10, 2018 at 01:01:52AM +0100, Philipp Tomsich wrote:
> We move the ramdisk_addr_r to 0x6800 and disable the initrd and
> fdt relocation, so the initramfs works out of box.
> 
> Signed-off-by: Otavio Salvador 
> Reviewed-by: Philipp Tomsich 
> ---
> 
> include/configs/rv1108_common.h | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
> 
 
 Applied to u-boot-rockchip, thanks!
>>> 
>>> Ugh, sorry for not spotting this sooner.  Please don't disable
>>> fdt/initrd relocation and instead use bootm_size.
>> 
>> Thanks for spotting this (just in time).
>> I’ll drop it and rerun Travis for tomorrow’s PR.
> 
> Thanks.  And you might want to audit the rest of rockchip (and no, my
> own house isn't 100% in order) as it looks like in general at least
> you're using fdt_high to (good) set an upper bound but I think
> bootm_size is more robust as we can set that and it covers fdt and
> initrd if present (which not all rk3xxx_common.h are setting).

We may have a problem on rk3188 and rk3288 configurations. While I can
convert these to bootm_size, I would have to do so blindly, as I don’t have
any boards.

@Heiko: you have added the fdt_high and initrd_high in rk3188_common.h,
do you have more info and would you have able to test this changed to
bootm_size instead?

Cheers,
Philipp.
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Re: [U-Boot] [PATCH v2 04/20] cpu: Add a RISC-V CPU driver

2018-12-10 Thread Auer, Lukas
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> This adds a driver for RISC-V CPU. Note the driver will bind
> a RISC-V timer driver if "timebase-frequency" property is
> present in the device tree.
> 
> Signed-off-by: Bin Meng 
> 
> ---
> 
> Changes in v2:
> - pass NULL as the timer device to device_bind_with_driver_data()
> 
>  drivers/cpu/Kconfig |   6 +++
>  drivers/cpu/Makefile|   1 +
>  drivers/cpu/riscv_cpu.c | 116
> 
>  3 files changed, 123 insertions(+)
>  create mode 100644 drivers/cpu/riscv_cpu.c
> 

Reviewed-by: Lukas Auer 
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Re: [U-Boot] [PATCH 0/6] Add support for MIPS Creator CI20

2018-12-10 Thread Paul Burton
Hi Ezequiel,

On Mon, Dec 10, 2018 at 06:31:29PM -0300, Ezequiel Garcia wrote:
> On Mon, 2018-12-10 at 22:00 +0100, Andreas Färber wrote:
> > Am 10.12.18 um 21:35 schrieb Ezequiel Garcia:
> > > Please note that I've added Paul's SOB to all the patches
> > > he authored, to make the authorship chain more clear.
> > 
> > That's only permitted if Paul agreed to that beforehand - did he?
> > Never add other people's Signed-off-by if their patches didn't have it!
> > 
> 
> Fair enough. Let's hope Paul is OK with this. I wasn't really comfortable
> not having Paul's SOB, given he authored all the patches.
> 
> Paul, do we have green light?

I'm OK with it in this instance, though please feel free to take
authorship if you make significant changes. I've not had the time to do
this work myself but I certainly don't want to stand in the way of
others :)

It's worth noting though that paul.bur...@imgtec.com is no longer a
valid email address, so it might be worth updating to
paul.bur...@mips.com wherever my email address appears.

Thanks,
Paul
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Re: [U-Boot] [PATCH v2 1/2] spl_spi: Read default speed and mode values from DT

2018-12-10 Thread Adam Ford
On Mon, Nov 19, 2018 at 11:55 AM Patrick Delaunay
 wrote:
>
> In case of DT boot, don't read default speed and mode for SPI from
> CONFIG_*, instead read from DT node.
>
> Signed-off-by: Christophe Kerello 
> Signed-off-by: Patrick Delaunay 
> ---
>
> Changes in v2:
> - use variables to avoid duplicated code
>
>  common/spl/spl_spi.c | 10 --
>  1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c
> index 8cd4830..b348b45 100644
> --- a/common/spl/spl_spi.c
> +++ b/common/spl/spl_spi.c
> @@ -74,15 +74,21 @@ static int spl_spi_load_image(struct spl_image_info 
> *spl_image,
> unsigned payload_offs = CONFIG_SYS_SPI_U_BOOT_OFFS;
> struct spi_flash *flash;
> struct image_header *header;
> +   unsigned int max_hz = CONFIG_SF_DEFAULT_SPEED;
> +   unsigned int spi_mode = CONFIG_SF_DEFAULT_MODE;
>

Instead of
> +#ifdef CONFIG_DM_SPI_FLASH

What about using:

#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)

> +   /* In DM mode defaults will be taken from DT */
> +   max_hz = 0, spi_mode = 0;
> +#endif

This one-line change 'should' give you what you want, the settings of
0 for boards using the device tree.  If board that uses OF_PLATDATA
cannot load the device tree, it'll default back to the configs set
above.  You could probably combine all if statements into one, and I'd
be fine with that too.

This one-line change made my board boot with this series.  I haven't
applied the follow-up series yet but if a v3 was posted with this
change, I'd mark it as 'tested-by.

adam

> /*
>  * Load U-Boot image from SPI flash into RAM
>  */
>
> flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
> CONFIG_SF_DEFAULT_CS,
> -   CONFIG_SF_DEFAULT_SPEED,
> -   CONFIG_SF_DEFAULT_MODE);
> +   max_hz,
> +   spi_mode);
> if (!flash) {
> puts("SPI probe failed.\n");
> return -ENODEV;
> --
> 2.7.4
>
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Re: [U-Boot] [PATCH 1/6] misc: Add JZ47xx efuse driver

2018-12-10 Thread Marek Vasut
On 12/10/2018 11:02 PM, Ezequiel Garcia wrote:
> On Mon, 2018-12-10 at 21:56 +0100, Marek Vasut wrote:
>> On 12/10/2018 09:35 PM, Ezequiel Garcia wrote:
>>> From: Paul Burton 
>>>
>>> Add driver for the efuse block in the JZ47xx SOC.
>>>
>>> Cc: Daniel Schwierzeck 
>>> Signed-off-by: Paul Burton 
>>> Signed-off-by: Marek Vasut 
>>
>> [...]
>>
>>> +static void jz4780_efuse_read_chunk(size_t addr, size_t count, u8 *buf)
>>> +{
>>> +   void __iomem *regs = (void __iomem *)NEMC_BASE;
>>> +   size_t i;
>>> +   u32 val;
>>> +
>>> +   val = EFUSE_EFUCTRL_RD_EN |
>>> + ((count - 1) << EFUSE_EFUCTRL_LEN_BIT) |
>>> + (addr << EFUSE_EFUCTRL_ADDR_BIT) |
>>> + ((addr > 0x200) ? EFUSE_EFUCTRL_CS : 0);
>>> +   writel(val, regs + EFUSE_EFUCTRL);
>>> +   /* FIXME -- wait_bit() */
>>> +   while (!(readl(regs + EFUSE_EFUSTATE) & EFUSE_EFUSTATE_RD_DONE))
>>> +   ;
>>
>> Does wait_for_bit_le32() fit into the SPL if you use it here ?
>>
> 
> I literally haven't looked at these (working) drivers. Let's see..
> 
> ...hm, to be honest, I'm more worried about these infinite loops
> than about fancy API uses. An infinite loop in the MMC driver caused
> a freeze during driver-model porting, so these are more serious threats.
> 
> Will try to address the unbounded loop and take a stab at using
> wait_for_bit_le32.

Right, that should fix the infinite loop problem.

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 1/6] misc: Add JZ47xx efuse driver

2018-12-10 Thread Ezequiel Garcia
On Mon, 2018-12-10 at 21:56 +0100, Marek Vasut wrote:
> On 12/10/2018 09:35 PM, Ezequiel Garcia wrote:
> > From: Paul Burton 
> > 
> > Add driver for the efuse block in the JZ47xx SOC.
> > 
> > Cc: Daniel Schwierzeck 
> > Signed-off-by: Paul Burton 
> > Signed-off-by: Marek Vasut 
> 
> [...]
> 
> > +static void jz4780_efuse_read_chunk(size_t addr, size_t count, u8 *buf)
> > +{
> > +   void __iomem *regs = (void __iomem *)NEMC_BASE;
> > +   size_t i;
> > +   u32 val;
> > +
> > +   val = EFUSE_EFUCTRL_RD_EN |
> > + ((count - 1) << EFUSE_EFUCTRL_LEN_BIT) |
> > + (addr << EFUSE_EFUCTRL_ADDR_BIT) |
> > + ((addr > 0x200) ? EFUSE_EFUCTRL_CS : 0);
> > +   writel(val, regs + EFUSE_EFUCTRL);
> > +   /* FIXME -- wait_bit() */
> > +   while (!(readl(regs + EFUSE_EFUSTATE) & EFUSE_EFUSTATE_RD_DONE))
> > +   ;
> 
> Does wait_for_bit_le32() fit into the SPL if you use it here ?
> 

I literally haven't looked at these (working) drivers. Let's see..

...hm, to be honest, I'm more worried about these infinite loops
than about fancy API uses. An infinite loop in the MMC driver caused
a freeze during driver-model porting, so these are more serious threats.

Will try to address the unbounded loop and take a stab at using
wait_for_bit_le32.

Thanks for the review!
Eze

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Re: [U-Boot] [PATCH 2/2] mtd: Get rid of board_mtdparts_default()

2018-12-10 Thread Enric Balletbo Serra
+Ladis who might be also interested.
Missatge de Boris Brezillon  del dia dl.,
10 de des. 2018 a les 16:38:
>
> The only implementer of this function has been patched to use
> CONFIG_MTD{IDS,PARTS}_DEFAULT instead. Let's get rid of this function
> and the associated CONFIG_SYS_MTDPARTS_RUNTIME option.
>
> Signed-off-by: Boris Brezillon 
> ---
>  board/isee/igep00x0/igep00x0.c   | 17 -
>  cmd/mtdparts.c   |  6 --
>  drivers/mtd/mtd_uboot.c  | 10 ++
>  include/configs/omap3_igep00x0.h |  2 --
>  scripts/config_whitelist.txt |  1 -
>  5 files changed, 2 insertions(+), 34 deletions(-)
>
> diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
> index 367af82d4a16..3552be6f3902 100644
> --- a/board/isee/igep00x0/igep00x0.c
> +++ b/board/isee/igep00x0/igep00x0.c
> @@ -239,20 +239,3 @@ int misc_init_r(void)
>
> return 0;
>  }
> -
> -void board_mtdparts_default(const char **mtdids, const char **mtdparts)
> -{
> -   struct mtd_info *mtd = get_mtd_device(NULL, 0);
> -   if (mtd) {
> -   static char ids[24];
> -   static char parts[48];
> -   const char *linux_name = "omap2-nand";
> -   if (strncmp(mtd->name, "onenand0", 8) == 0)
> -   linux_name = "omap2-onenand";
> -   snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name);
> -   snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)",
> -linux_name, 4 * mtd->erasesize >> 10);
> -   *mtdids = ids;
> -   *mtdparts = parts;
> -   }
> -}
> diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c
> index f7ed1a077974..6b5644523898 100644
> --- a/cmd/mtdparts.c
> +++ b/cmd/mtdparts.c
> @@ -122,9 +122,6 @@ DECLARE_GLOBAL_DATA_PTR;
>  #define MTDPARTS_DEFAULT NULL
>  #endif
>  #endif
> -#if defined(CONFIG_SYS_MTDPARTS_RUNTIME)
> -extern void board_mtdparts_default(const char **mtdids, const char 
> **mtdparts);
> -#endif
>  static const char *mtdids_default = MTDIDS_DEFAULT;
>  static const char *mtdparts_default = MTDPARTS_DEFAULT;
>
> @@ -1733,9 +1730,6 @@ int mtdparts_init(void)
> memset(last_ids, 0, sizeof(last_ids));
> memset(last_parts, 0, sizeof(last_parts));
> memset(last_partition, 0, sizeof(last_partition));
> -#if defined(CONFIG_SYS_MTDPARTS_RUNTIME)
> -   board_mtdparts_default(_default, _default);
> -#endif
> use_defaults = 1;
> initialized = 1;
> }
> diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c
> index d638f700d041..ed619abac390 100644
> --- a/drivers/mtd/mtd_uboot.c
> +++ b/drivers/mtd/mtd_uboot.c
> @@ -13,8 +13,6 @@
>
>  #define MTD_NAME_MAX_LEN 20
>
> -void board_mtdparts_default(const char **mtdids, const char **mtdparts);
> -
>  static const char *get_mtdids(void)
>  {
> __maybe_unused const char *mtdparts = NULL;
> @@ -23,9 +21,7 @@ static const char *get_mtdids(void)
> if (mtdids)
> return mtdids;
>
> -#if defined(CONFIG_SYS_MTDPARTS_RUNTIME)
> -   board_mtdparts_default(, );
> -#elif defined(MTDIDS_DEFAULT)
> +#if defined(MTDIDS_DEFAULT)
> mtdids = MTDIDS_DEFAULT;
>  #elif defined(CONFIG_MTDIDS_DEFAULT)
> mtdids = CONFIG_MTDIDS_DEFAULT;
> @@ -133,9 +129,7 @@ static const char *get_mtdparts(void)
> if (mtdparts || !use_defaults)
> return mtdparts;
>
> -#if defined(CONFIG_SYS_MTDPARTS_RUNTIME)
> -   board_mtdparts_default(, );
> -#elif defined(MTDPARTS_DEFAULT)
> +#if defined(MTDPARTS_DEFAULT)
> mtdparts = MTDPARTS_DEFAULT;
>  #elif defined(CONFIG_MTDPARTS_DEFAULT)
> mtdparts = CONFIG_MTDPARTS_DEFAULT;
> diff --git a/include/configs/omap3_igep00x0.h 
> b/include/configs/omap3_igep00x0.h
> index b9d65697521b..280a094cdbae 100644
> --- a/include/configs/omap3_igep00x0.h
> +++ b/include/configs/omap3_igep00x0.h
> @@ -87,8 +87,6 @@
>
>  #endif
>
> -#define CONFIG_SYS_MTDPARTS_RUNTIME
> -
>  /* OneNAND config */
>  #define CONFIG_USE_ONENAND_BOARD_INIT
>  #define CONFIG_SYS_ONENAND_BASEONENAND_MAP
> diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
> index b8addeaf693a..72608071c486 100644
> --- a/scripts/config_whitelist.txt
> +++ b/scripts/config_whitelist.txt
> @@ -3511,7 +3511,6 @@ CONFIG_SYS_MRAM_SIZE
>  CONFIG_SYS_MSC0_VAL
>  CONFIG_SYS_MSC1_VAL
>  CONFIG_SYS_MSC2_VAL
> -CONFIG_SYS_MTDPARTS_RUNTIME
>  CONFIG_SYS_MX5_CLK32
>  CONFIG_SYS_MX5_HCLK
>  CONFIG_SYS_MX6_CLK32
> --
> 2.17.1
>
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Re: [U-Boot] [PATCH 1/2] configs: igep: Define default mtdids/mtdparts

2018-12-10 Thread Enric Balletbo Serra
+Ladis who might be also interested.
Missatge de Boris Brezillon  del dia dl.,
10 de des. 2018 a les 16:38:
>
> We are trying to get rid of the weak board_mtdparts_default() function
> and we need to make sure igep defconfigs have proper proper
> CONFIG_MTD{IDS,PARTS}_DEFAULT before doing that.
>
> Signed-off-by: Boris Brezillon 
> ---
>  configs/igep0032_defconfig | 2 ++
>  configs/igep00x0_defconfig | 2 ++
>  2 files changed, 4 insertions(+)
>
> diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig
> index 383648789c53..d2a614c98f6d 100644
> --- a/configs/igep0032_defconfig
> +++ b/configs/igep0032_defconfig
> @@ -28,6 +28,8 @@ CONFIG_CMD_SPI=y
>  CONFIG_CMD_CACHE=y
>  CONFIG_CMD_EXT4_WRITE=y
>  CONFIG_CMD_MTDPARTS=y
> +CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand,onenand0=omap2-onenand"
> +CONFIG_MTDPARTS_DEFAULT="omap2-nand:512k(SPL),-(UBI);omap2-onenand:512k(SPL),-(UBI)"
>  CONFIG_CMD_UBI=y
>  # CONFIG_CMD_UBIFS is not set
>  CONFIG_NET_RANDOM_ETHADDR=y
> diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig
> index f2989e34e12e..5d3e109ee3c2 100644
> --- a/configs/igep00x0_defconfig
> +++ b/configs/igep00x0_defconfig
> @@ -28,6 +28,8 @@ CONFIG_CMD_SPI=y
>  CONFIG_CMD_CACHE=y
>  CONFIG_CMD_EXT4_WRITE=y
>  CONFIG_CMD_MTDPARTS=y
> +CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand,onenand0=omap2-onenand"
> +CONFIG_MTDPARTS_DEFAULT="omap2-nand:512k(SPL),-(UBI);omap2-onenand:512k(SPL),-(UBI)"
>  CONFIG_CMD_UBI=y
>  # CONFIG_CMD_UBIFS is not set
>  CONFIG_NET_RANDOM_ETHADDR=y
> --
> 2.17.1
>
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Re: [U-Boot] [PATCH 0/6] Add support for MIPS Creator CI20

2018-12-10 Thread Andreas Färber
Am 10.12.18 um 22:31 schrieb Ezequiel Garcia:
> On Mon, 2018-12-10 at 22:00 +0100, Andreas Färber wrote:
>> Also this is surely not a v1 patch! Marek had posted CI20 before, so
>> this should be v2 (doesn't look like I posted mine as v2, it didn't
>> fully build yet) and thus your next iteration should be v3 please.
> 
> Well, I couldn't find Marek's cover letter, and I've decided to start from 
> scratch.

That's OK, you did mention your changes in the cover letter.

> Two years have passed, we have a new try at getting this merged so I think
> it deserves it's own set of integers.

The patches need to be distinguishable in Patchwork and inboxes if the
subjects remained the same, no matter how much time passed.

Thanks,
Andreas

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HRB 21284 (AG Nürnberg)
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Re: [U-Boot] [PATCH 0/6] Add support for MIPS Creator CI20

2018-12-10 Thread Ezequiel Garcia
On Mon, 2018-12-10 at 22:00 +0100, Andreas Färber wrote:
> Hi Ezequiel,
> 
> Am 10.12.18 um 21:35 schrieb Ezequiel Garcia:
> > Please note that I've added Paul's SOB to all the patches
> > he authored, to make the authorship chain more clear.
> 
> That's only permitted if Paul agreed to that beforehand - did he?
> Never add other people's Signed-off-by if their patches didn't have it!
> 

Fair enough. Let's hope Paul is OK with this. I wasn't really comfortable
not having Paul's SOB, given he authored all the patches.

Paul, do we have green light?

> https://www.kernel.org/doc/html/latest/process/submitting-patches.html#sign-your-work-the-developer-s-certificate-of-origin
> 
> As far as the authorship chain goes, you re-did all my forward-porting,
> that I'm not being credited with Signed-off-by in MMC/SoC/defconfig
> patches or verbally anywhere?
> 

Oh, sorry, but I haven't used anything from your work. This series
is entirely based on https://github.com/marex/u-boot-mips/tree/ci20-v2018.xx.

Basically, I've cherry-picked the commits that weren't already available
in upstream, adding my SOB to those patches that I've modified.

Like I mentioned in the cover letter, most of the work has been done
by Paul Burton and Marek, so they deserve all the credit.

I'm just cleaning and submitting.

> Also this is surely not a v1 patch! Marek had posted CI20 before, so
> this should be v2 (doesn't look like I posted mine as v2, it didn't
> fully build yet) and thus your next iteration should be v3 please.
> 

Well, I couldn't find Marek's cover letter, and I've decided to start from 
scratch.

Two years have passed, we have a new try at getting this merged so I think
it deserves it's own set of integers.

> Further, it would be very helpful - given the history of this patchset -
> to indicate which toolchain and version you used for building this.
> 

I've used gcc version 5.3.0 (Sourcery CodeBench Lite 2016.05-8),
installed via Buildroot. Wasn't really paying attention to the toolchain.

I'll test with a recent gcc and post the results.

Thanks,
Eze

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Re: [U-Boot] Please pull fsl-qoriq master

2018-12-10 Thread York Sun
On 12/10/18 1:22 PM, York Sun wrote:
> Tom,
> 
> The following changes since commit d452f27b3ea806fd99aee4b73a723318032c1d5c:
> 
>   Prepare v2019.01-rc1 (2018-12-03 23:50:13 -0500)
> 
> are available in the Git repository at:
> 
>   git://git.denx.de/u-boot-fsl-qoriq.git tags/fsl-qoriq-for-v2019.01-rc2
> 
> for you to fetch changes up to 4909b89ec763f0c7030fa8474f9b6c5df866b01f:
> 
>   armv8: lx2160a: Add LX2160A SoC Support (2018-12-06 14:37:19 -0800)
>

Travis build log is here
https://travis-ci.org/yorksun/u-boot/builds/466070252

York
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[U-Boot] Please pull fsl-qoriq master

2018-12-10 Thread York Sun
Tom,

The following changes since commit d452f27b3ea806fd99aee4b73a723318032c1d5c:

  Prepare v2019.01-rc1 (2018-12-03 23:50:13 -0500)

are available in the Git repository at:

  git://git.denx.de/u-boot-fsl-qoriq.git tags/fsl-qoriq-for-v2019.01-rc2

for you to fetch changes up to 4909b89ec763f0c7030fa8474f9b6c5df866b01f:

  armv8: lx2160a: Add LX2160A SoC Support (2018-12-06 14:37:19 -0800)


Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC


Alison Wang (1):
  arm: ls1021a: Add timer_init() in board_init_f for SPL

Ashish Kumar (1):
  ls1088a: Move CONFIG_FSL_QSPI to defconfig

Pankit Garg (5):
  armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3
  drivers: ifc: dynamic chipselect mapping support
  armv8: fsl-layerscape: bootcmd identification for TFABOOT
  armv8: sec_firmware: return job ring status as true in TFABOOT
  armv8: fsl-layerscape: add support of MC framework for TFA

Peng Ma (10):
  scsi: ceva: add ls1046a soc support
  armv8: dts: fsl-ls1046a: add sata node support
  arm64: ls1046ardb: enable DM support for sata
  arm64: ls1046aqds: enable DM support for sata
  scsi: ceva: add ls1088a soc support
  armv8: dts: fsl-ls1088a: add sata node support
  arm64: ls1088a: enable DM support for sata
  scsi: ceva: add ls2080a soc support
  armv8: dts: fsl-ls2080a: add sata node support
  arm64: ls2080a: enable DM support for sata

Pramod Kumar (1):
  armv8: ls1088ardb_pb: Add support for board detection

Priyanka Jain (5):
  board/freescale/vid: Add correction for ltc3882 read error.
  armv8: lsch3: Add support of serdes3 module
  board/freescale/vid: Add vdd table for NXP LX2160A SoC
  armv8:fsl-layerscape: Add support for Chassis 3.2
  armv8: lx2160a: Add LX2160A SoC Support

Rajesh Bhagat (19):
  env: allow flash and nand env driver to compile together
  env: sf: define API to override sf environment address
  driver/ifc: replace __ilog2 with LOG2 macro
  armv8: layerscape: Add TFABOOT support
  armv8: fsl-layerscape: identify boot source from PORSR register
  armv8: layerscape: remove EL3 specific erratas for TFABOOT
  armv8: layerscape: add SMC calls for DDR size and bank info
  armv8: layerscape: skip OCRAM init for TFABOOT
  armv8: sec_firmware: change el2_to_aarch32 SMC ID
  net: fm: add TFABOOT support
  drivers: qe: add TFABOOT support
  armv8: ls1046ardb: Add TFABOOT support
  armv8: ls1046aqds: Add TFABOOT support
  armv8: ls1043ardb: Add TFABOOT support
  armv8: ls1043aqds: Add TFABOOT support
  armv8: ls1012ardb: Add TFABOOT support
  armv8: ls1012aqds: fix secure boot compilation
  armv8: ls1012aqds: Add TFABOOT support
  armv8: ls1012afrx: Add TFABOOT support

York Sun (3):
  move data structure out of cpu.h
  armv8: layerscape: Enable routing SError exception
  armv8: fsl-layerscape: Update parsing boot source

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  89 ++-
 arch/arm/cpu/armv8/fsl-layerscape/Makefile |   6 +-
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 639
-
 .../cpu/armv8/fsl-layerscape/doc/README.lsch3_2|  27 +
 arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc   |  57 ++
 .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c| 107 
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   |  14 +-
 arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 132 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 128 +
 arch/arm/cpu/armv8/sec_firmware.c  |   4 +
 arch/arm/cpu/armv8/sec_firmware_asm.S  |   2 +-
 arch/arm/dts/fsl-ls1046a-qds.dtsi  |   4 +
 arch/arm/dts/fsl-ls1046a-rdb.dts   |   4 +
 arch/arm/dts/fsl-ls1046a.dtsi  |   8 +
 arch/arm/dts/fsl-ls1088a-qds.dts   |   4 +
 arch/arm/dts/fsl-ls1088a-rdb.dts   |   4 +
 arch/arm/dts/fsl-ls1088a.dtsi  |   8 +
 arch/arm/dts/fsl-ls2080a-qds.dts   |   4 +
 arch/arm/dts/fsl-ls2080a-rdb.dts   |   4 +
 arch/arm/dts/fsl-ls2080a.dtsi  |   8 +
 arch/arm/dts/fsl-lx2160a.dtsi  | 118 
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  56 ++
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 313 +-
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |  30 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  20 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  85 ++-
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |  28 +
 .../asm/arch-fsl-layerscape/stream_id_lsch3.h  |   9 +-
 board/freescale/common/vid.c   |  42 +-
 board/freescale/ls1012afrdm/MAINTAINERS|   3 +
 

Re: [U-Boot] [PATCH][v2] armv8:fsl-layerscape: Add support for Chassis 3.2

2018-12-10 Thread York Sun
On 10/29/18 2:11 AM, Priyanka Jain wrote:
> NXP layerscape architecture Chassis 3.2 builds upon chassis3
> architecture with changes like DDR Memory map change,
> removal of IFC and support of upto 8 I2C controller.
> 
> Patch add README.lsch3_2 and the above changes under
> macro CONFIG_NXP_LSCH3_2.
> 
> Signed-off-by: Sriram Dash 
> Signed-off-by: Priyanka Jain 
> ---
> Changes for v2:
>  Rebased on top of test_qoriq branch of u-boot-fsl-qoriq.git
>  

Applied to fsl-qoriq master, awaiting upstream. Thanks.

York

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Re: [U-Boot] [PATCH][v3] armv8: lx2160a: Add LX2160A SoC Support

2018-12-10 Thread York Sun
On 10/29/18 2:17 AM, Priyanka Jain wrote:
> LX2160A Soc is based on Layerscape Chassis Generation 3.2 Architecture.
> Features:
>  16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
>  two 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
>  3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
>  4 TZASC instances, etc.
> 
> SoC personalites:
> LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
> LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs
> 
> Signed-off-by: Bao Xiaowei 
> Signed-off-by: Hou Zhiqiang 
> Signed-off-by: Meenakshi Aggarwal 
> Signed-off-by: Vabhav Sharma 
> Signed-off-by: Sriram Dash 
> Signed-off-by: Priyanka Jain 
> ---
> Changes for v3:
>  Add CONFIG_SYS_FSL_RST_ADDR define
> 
Applied to fsl-qoriq master, awaiting upstream. Thanks.

York

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Re: [U-Boot] [PATCH] board/freescale/vid: Add vdd table for NXP LX2160A SoC

2018-12-10 Thread York Sun
On 10/10/18 10:22 PM, Priyanka Jain wrote:
> Signed-off-by: Priyanka Jain 
> ---
Applied to fsl-qoriq master, awaiting upstream. Thanks.

York
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Re: [U-Boot] [PATCH][v2] armv8: lsch3: Add support of serdes3 module

2018-12-10 Thread York Sun
On 9/26/18 10:02 PM, Priyanka Jain wrote:
> Some lsch3 based SoCs like lx2160a contains three
> serdes modules.
> Add support for third serdes protocol in lsch3
> 
> Signed-off-by: Priyanka Jain 
> ---
> Changes for v2:
>   Updated copyright
>   Renamed CONFIG_SYS_FSL_SRDS_3 to CONFIG_SYS_NXP_SRDS_3
>   

Applied to fsl-qoriq master, awaiting upstream. Thanks.

York

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Re: [U-Boot] [PATCH] board/freescale/vid: Add correction for ltc3882 read error.

2018-12-10 Thread York Sun
On 10/10/18 10:11 PM, Priyanka Jain wrote:
> Voltage regulator LTC3882 device has 0.5% voltage read error.
> So for NXP SoC devices this generally equates to 2mV
> 
> Update set_voltage_to_LTC for below:
> 1.Add coorection of upto 2mV in voltage comparison
>   to take care of voltage read error of voltage regulator
> 2.Add loop max count kept as 100 to avoid infinte loop.
> 
> Signed-off-by: Priyanka Jain 
> ---

Applied to fsl-qoriq master, awaiting upstream. Thanks.

York
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Re: [U-Boot] [PATCH] ls1088a: Move CONFIG_FSL_QSPI to defconfig

2018-12-10 Thread York Sun
On 10/12/18 2:18 AM, Ashish Kumar wrote:
> Signed-off-by: Rajat Srivastava 
> Signed-off-by: Ashish Kumar 
> ---

This set is applied to fsl-qoriq master, awaiting upstream. Thanks.

York

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Re: [U-Boot] [PATCH] armv8: ls1088ardb_pb: Add support for board detection

2018-12-10 Thread York Sun
On 10/12/18 7:04 AM, Pramod Kumar wrote:
> ls1088ardb-pb and ls1088ardb both boards are ls1088a based soc,
> board type detection is dynamic at boot time
> 
> Signed-off-by: Pramod Kumar 
> ---

This set is applied to fsl-qoriq master, awaiting upstream. Thanks.

York

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Re: [U-Boot] [PATCH] arm: ls1021a: Add timer_init() in board_init_f for SPL

2018-12-10 Thread York Sun
On 10/16/18 1:23 AM, Alison Wang wrote:
> I2C is used to access DDR SPD in the DDR initialization for SPL. In
> i2c_write process, get_timer() will be called. In board_init_f for SPL,
> timer_init() is not called before. The system counter is not enabled and
> the counter frequency is not set to 12.5MHz in SPL. The parameters for
> do_div() are zero too.
> 
> It could not be found until CONFIG_USE_PRIVATE_LIBGCC is enabled in
> default. When CONFIG_USE_PRIVATE_LIBGCC is enabled, U-Boot will use its
> own set of libgcc functions. As the parameters for do_div() are zero,
> __div0 will be called. Then the processor will stay in an endless loop
> after calling hang().
> 
> This patch will add timer_init() in board_init_f for SPL and fix a
> series of issues it caused.
> 
> Signed-off-by: Alison Wang 
> ---

This set is applied to fsl-qoriq master, awaiting upstream. Thanks.

York
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Re: [U-Boot] [PATCH 1/3] scsi: ceva: add ls2080a soc support

2018-12-10 Thread York Sun
On 10/21/18 7:47 PM, Peng Ma wrote:
> Add ahci compatible support for ls2080a soc.
> 
> Signed-off-by: Peng Ma 
> ---

This set is applied to fsl-qoriq master, awaiting upstream. Thanks.

York
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Re: [U-Boot] [PATCH 7/7] spi: remove define for SPI default SPEED and MODE

2018-12-10 Thread Petr Vorel
Hi Patrick,

> On Mon, Dec 10, 2018 at 11:53 AM Patrick Delaunay
>  wrote:

> > In DM mode, the speed and mode defaults value will be taken from DT,
> > so these defines should be never used and can be removed.

> > Signed-off-by: Patrick Delaunay 
Reviewed-by: Petr Vorel 
> > ---

> >  include/spi_flash.h | 4 
> >  1 file changed, 4 insertions(+)

> > diff --git a/include/spi_flash.h b/include/spi_flash.h
> > index 36565bb..c9d20a5 100644
> > --- a/include/spi_flash.h
> > +++ b/include/spi_flash.h
> > @@ -12,12 +12,16 @@
> >  #include /* Because we dereference struct udevice here */
> >  #include 

> > +#ifndef CONFIG_DM_SPI_FLASH
> > +/* In DM mode, speed and mode value will be taken from DT */
> >  #ifndef CONFIG_SF_DEFAULT_SPEED
> >  # define CONFIG_SF_DEFAULT_SPEED   100
> >  #endif
> >  #ifndef CONFIG_SF_DEFAULT_MODE
> >  # define CONFIG_SF_DEFAULT_MODESPI_MODE_3
> >  #endif
> > +#endif
Also: maybe indent preprocessor code?


Kind regards,
Petr
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Re: [U-Boot] [PATCH 1/3] scsi: ceva: add ls1088a soc support

2018-12-10 Thread York Sun
On 10/21/18 7:43 PM, Peng Ma wrote:
> Add ahci compatible support for ls1088a soc.
> 
> Signed-off-by: Peng Ma 
> ---


This set is applied to fsl-qoriq master, awaiting upstream. Thanks.

York


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Re: [U-Boot] [PATCH 1/4] scsi: ceva: add ls1046a soc support

2018-12-10 Thread York Sun
On 10/11/18 3:38 AM, Peng Ma wrote:
> Add ahci compatible support for ls1046a soc.
> 
> Signed-off-by: Peng Ma 
> ---

Please remember to sort defconfig using moveconfig.py in the future.
This set is applied to fsl-qoriq master, awaiting upstream. Thanks.

York
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Re: [U-Boot] [PATCH 6/7] env: Read default speed and mode values from DT

2018-12-10 Thread Petr Vorel
Hi Patrick,

> In case of DT boot, don't read default speed and mode for SPI from
> CONFIG_*, instead read from DT node.

> Signed-off-by: Patrick Delaunay 
Reviewed-by: Petr Vorel 
> ---

>  env/Kconfig | 4 ++--
>  env/sf.c| 5 -
>  2 files changed, 6 insertions(+), 3 deletions(-)

...
> +++ b/env/sf.c
> @@ -24,12 +24,15 @@
>  #ifndef CONFIG_ENV_SPI_CS
>  # define CONFIG_ENV_SPI_CS   CONFIG_SF_DEFAULT_CS
>  #endif
> +
> +#ifndef CONFIG_DM_SPI_FLASH
>  #ifndef CONFIG_ENV_SPI_MAX_HZ
>  # define CONFIG_ENV_SPI_MAX_HZ   CONFIG_SF_DEFAULT_SPEED
>  #endif
>  #ifndef CONFIG_ENV_SPI_MODE
>  # define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
>  #endif
> +#endif

Maybe indent? (code style mix indent and not)
#ifndef CONFIG_DM_SPI_FLASH
# ifndef CONFIG_ENV_SPI_MAX_HZ
#  define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
# endif
# ifndef CONFIG_ENV_SPI_MODE
#  define CONFIG_ENV_SPI_MODE   CONFIG_SF_DEFAULT_MODE
# endif
#endif


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Petr
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Re: [U-Boot] [PATCH 20/21] Add inttypes.h

2018-12-10 Thread Simon Glass
Hi Masahiro,

On Wed, 5 Dec 2018 at 22:51, Masahiro Yamada
 wrote:
>
> On Sat, Nov 24, 2018 at 1:43 PM Simon Glass  wrote:
> >
> > Even if U-Boot does not use this, some libraries do. Add back this header
> > file so that the build does not fall back to using the host version, which
> > may include stdint.h and break the build due to conflicts with uint64_t,
> > etc.
>
>
>
> The root cause of the problem might be,
> those libraries mix up  from U-Boot
> and  from the compiler.
>
>
> Linux kernel has a different  for user-space tools
> in tools/include/linux/types.h

Right, but how does it enforce those tools using that file? It is non-standard.

> I agree that U-Boot has been screwed up here
> to a hopeless level.

The problem is not U-Boot. If a library that links against U-Boot
includes stdint.h, it expects it to work.

Regards,
Simon
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Re: [U-Boot] [PATCH v6 00/27] TF-A Boot support for NXP Chassis 2 platforms

2018-12-10 Thread York Sun
On 11/5/18 10:01 AM, Rajesh Bhagat wrote:
> Includes changes in u-boot framework to support TF-A for NXP Chassis 2
> platforms. A new defconfig is added namely ls*_tfa_defconfig which will
> be used for all boot sources when TF-A is used.   
>   
>   
>   
> Tested on LS1043A, LS1046A and LS1012A platforms.
> 
> Changes in v6:
>  - Rebased to master 

Fixed multiple issues found by checkpatch. Applied to fsl-qoriq master,
awaiting upstream. Thanks.

York
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Re: [U-Boot] [BUG] ut overlay fails with v2018.03 and later on qemu-arm64_defconfig

2018-12-10 Thread Simon Goldschmidt

Am 10.12.2018 um 21:43 schrieb Tom Rini:

On Sat, Dec 08, 2018 at 09:35:06AM +0100, Heinrich Schuchardt wrote:

Hello Simon,

on qemu-arm_defconfig fails with

=> ut overlay
Running 9 overlay tests
Test: fdt_overlay_add_node_by_path
test/overlay/cmd_ut_overlay.c:127, fdt_overlay_add_node_by_path(): off >= 0
Test: fdt_overlay_add_node_by_phandle
test/overlay/cmd_ut_overlay.c:113, fdt_overlay_add_node_by_phandle():
off >= 0
Test: fdt_overlay_add_str_property
test/overlay/cmd_ut_overlay.c:100, fdt_overlay_add_str_property(): 0 ==
fdt_getprop_str(fdt, "/test-node", "test-str-property-2", ):
Expected 0, got -9
Test: fdt_overlay_add_subnode_property
test/overlay/cmd_ut_overlay.c:141, fdt_overlay_add_subnode_property():
off >= 0
Test: fdt_overlay_change_int_property
test/overlay/cmd_ut_overlay.c:74, fdt_overlay_change_int_property(): 0
== ut_fdt_getprop_u32(fdt, "/test-node", "test-int-property", ):
Expected 0, got -9
Test: fdt_overlay_change_str_property
test/overlay/cmd_ut_overlay.c:87, fdt_overlay_change_str_property(): 0
== fdt_getprop_str(fdt, "/test-node", "test-str-property", ):
Expected 0, got -9
Test: fdt_overlay_local_phandle
test/overlay/cmd_ut_overlay.c:158, fdt_overlay_local_phandle(): off >= 0
Test: fdt_overlay_local_phandles
test/overlay/cmd_ut_overlay.c:183, fdt_overlay_local_phandles(): off >= 0
Test: fdt_overlay_stacked
test/overlay/cmd_ut_overlay.c:212, fdt_overlay_stacked(): 0 ==
ut_fdt_getprop_u32(fdt, "/new-local-node", "stacked-test-int-property",
): Expected 0, got -9
Failures: 9

This is reproducable with v2018.03, v2018.05, v2018.07, v2018.09,
v2018.11 and with current origin/master (358902586727 "Merge branch
'2018-12-06-master-imports'").

For the elder releases I had to apply
d796735c334b "test: overlay: add missing include"

The value of off is -9 in the tests above. This is -FDT_ERR_BADMAGIC.

Adding some debug output sheds more light:

test/overlay/cmd_ut_overlay.c(290) do_ut_overlay: fdt_base_copy
7ef33340
test/overlay/cmd_ut_overlay.c(291) do_ut_overlay: uts->priv 7ef33340
Running 9 overlay tests
Test: fdt_overlay_add_node_by_path
test/overlay/cmd_ut_overlay.c(127) fdt_overlay_add_node_by_path:
uts->priv 

This is the patch that led to problem:
e93232e15ec9 ("test: overlay: Use cmd_ut_category()")

The uts created in do_ut_overlay() is not the one used in cmd_ut_category().

The easiest fix would be using a static variable for passing the fdt.

The neatest solution would be cmd_ut_category() calling an
initialization function for the category so that we can use a single
instance of uts for the whole test.

As this API is your design I would prefer leaving the resolution to you.

Besides resolving the error I think we should run 'ut overlay' on Travis
CI for all qemu platforms.


I agree we should enable UT_OVERLAY as widely as possible in our
automated testing platforms, thanks!


+1 on that!

Until creating my first unit test for this CVE series last week, I was 
under the impression that all the unit tests under 'test/' were run 
automatically...


My experience says that a unit test that is not run automatically is not 
worth much (as we see here).


Regards,
Simon
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Re: [U-Boot] [PATCH 5/7] mips: mt76xx: gardena-smart-gateway: Read default speed and mode values from DT

2018-12-10 Thread Petr Vorel
Hi Patrick,

> In case of DT boot, don't read default speed and mode for SPI from
> CONFIG_*, instead read from DT node.

> Signed-off-by: Patrick Delaunay 
Reviewed-by: Petr Vorel 

Kind regards,
Petr
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Re: [U-Boot] [PATCH 4/7] dfu: sf: Read default speed and mode values from DT

2018-12-10 Thread Petr Vorel
Hi Patrick,

> In case of DT boot, don't read default speed and mode for SPI from
> CONFIG_*, instead read from DT node.

> Signed-off-by: Patrick Delaunay 
Reviewed-by: Petr Vorel 


Kind regards,
Petr
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Re: [U-Boot] [PATCH 0/6] Add support for MIPS Creator CI20

2018-12-10 Thread Andreas Färber
Hi Ezequiel,

Am 10.12.18 um 21:35 schrieb Ezequiel Garcia:
> Please note that I've added Paul's SOB to all the patches
> he authored, to make the authorship chain more clear.

That's only permitted if Paul agreed to that beforehand - did he?
Never add other people's Signed-off-by if their patches didn't have it!

https://www.kernel.org/doc/html/latest/process/submitting-patches.html#sign-your-work-the-developer-s-certificate-of-origin

As far as the authorship chain goes, you re-did all my forward-porting,
that I'm not being credited with Signed-off-by in MMC/SoC/defconfig
patches or verbally anywhere?

Also this is surely not a v1 patch! Marek had posted CI20 before, so
this should be v2 (doesn't look like I posted mine as v2, it didn't
fully build yet) and thus your next iteration should be v3 please.

Further, it would be very helpful - given the history of this patchset -
to indicate which toolchain and version you used for building this.

Regards,
Andreas

-- 
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GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
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Re: [U-Boot] [PATCH 0/6] Add support for MIPS Creator CI20

2018-12-10 Thread Marek Vasut
On 12/10/2018 09:35 PM, Ezequiel Garcia wrote:
> As the subject says, this series adds support for CI20.
> 
> Most of the work was done by Paul Burton, and then by Marek Vasut.
> I've just rescued the work from the dark wastelands of Mordor,
> did some cleaning here and there and submitted.
> 
> Patches 1, 2, and 4 are completely untouched. I've picked them
> from Marek's tree.
> 
> For the MMC driver (patch 3) there is some cleanup, and some
> fixes for proper DM migration.
> 
> Finally, patches 5 and 6 have been changed a bit: I've cleaned
> up the devicetree, the board support files and the defconfig.
> 
> This is based on top of today's master (7ff485c68b7e) and has
> been tested by SD-card booting both U-Boot and Linux. Booting
> Linux via TFTP was also tested.
> 
> Please note that I've added Paul's SOB to all the patches
> he authored, to make the authorship chain more clear.
> 
> Reviews and tests are welcome. Bikesheds not so much! ;-)

The platform is awfully size constrained, so it'd be nice to have it in
to keep the general bloat in check.

Except for minor nits in 1/6,
Reviewed-by: Marek Vasut 

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Re: [U-Boot] [PATCH 1/6] misc: Add JZ47xx efuse driver

2018-12-10 Thread Marek Vasut
On 12/10/2018 09:35 PM, Ezequiel Garcia wrote:
> From: Paul Burton 
> 
> Add driver for the efuse block in the JZ47xx SOC.
> 
> Cc: Daniel Schwierzeck 
> Signed-off-by: Paul Burton 
> Signed-off-by: Marek Vasut 

[...]

> +static void jz4780_efuse_read_chunk(size_t addr, size_t count, u8 *buf)
> +{
> + void __iomem *regs = (void __iomem *)NEMC_BASE;
> + size_t i;
> + u32 val;
> +
> + val = EFUSE_EFUCTRL_RD_EN |
> +   ((count - 1) << EFUSE_EFUCTRL_LEN_BIT) |
> +   (addr << EFUSE_EFUCTRL_ADDR_BIT) |
> +   ((addr > 0x200) ? EFUSE_EFUCTRL_CS : 0);
> + writel(val, regs + EFUSE_EFUCTRL);
> + /* FIXME -- wait_bit() */
> + while (!(readl(regs + EFUSE_EFUSTATE) & EFUSE_EFUSTATE_RD_DONE))
> + ;

Does wait_for_bit_le32() fit into the SPL if you use it here ?

> + if ((count % 4) == 0) {
> + for (i = 0; i < count / 4; i++) {
> + val = readl(regs + EFUSE_EFUDATA(i));
> + put_unaligned(val, (u32 *)(buf + (i * 4)));
> + }

I thought we had something like ioread*_rep(), but I guess not.

> + } else {
> + val = readl(regs + EFUSE_EFUDATA(0));
> + if (count > 2)
> + buf[2] = (val >> 16) & 0xff;
> + if (count > 1)
> + buf[1] = (val >> 8) & 0xff;
> + buf[0] = val & 0xff;
> + }
> +}
> +
> +static inline int jz4780_efuse_chunk_size(size_t count)
> +{
> + if (count >= 32)
> + return 32;
> + else if ((count / 4) > 0)
> + return (count / 4) * 4;
> + else
> + return count % 4;
> +}
> +
> +void jz4780_efuse_read(size_t addr, size_t count, u8 *buf)
> +{
> + size_t chunk;
> +
> + while (count > 0) {
> + chunk = jz4780_efuse_chunk_size(count);
> + jz4780_efuse_read_chunk(addr, chunk, buf);
> + addr += chunk;
> + buf += chunk;
> + count -= chunk;
> + }
> +}
> +
> +void jz4780_efuse_init(u32 ahb2_rate)
> +{
> + void __iomem *regs = (void __iomem *)NEMC_BASE;
> + u32 rd_adj, rd_strobe, tmp;
> +
> + rd_adj = (((6500 * (ahb2_rate / 100)) / 100) + 0xf) / 2;
> + tmp = (((35000 * (ahb2_rate / 100)) / 100) - 4) - rd_adj;
> + rd_strobe = ((tmp + 0xf) / 2 < 7) ? 7 : (tmp + 0xf) / 2;

Can you turn those magic numbers into macros ? Or if they really come
from the datasheet, well ... at least add a comment.

> + tmp = (rd_adj << EFUSE_EFUCFG_RD_ADJ_BIT) |
> +   (rd_strobe << EFUSE_EFUCFG_RD_STROBE_BIT);
> + writel(tmp, regs + EFUSE_EFUCFG);
> +}
> 


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Re: [U-Boot] [PATCH] Drivers: USB: MUSB: Remove legacy CONFIG_USB_DA8XX

2018-12-10 Thread Marek Vasut
On 12/10/2018 05:35 PM, Adam Ford wrote:
> There don't appear to be any boards enabling CONFIG_USB_DA8XX,
> and there is a newer version of the MUSB driver, so let's remove
> the legacy version of it.
> 
> Signed-off-by: Adam Ford 

CCing Jean, I'd like his A-B/R-B.
Looks good to me, so I'll pick it once I have it, thanks!

> 
> diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
> index 7e6be03f4a..2508b6ed0d 100644
> --- a/drivers/usb/musb/Kconfig
> +++ b/drivers/usb/musb/Kconfig
> @@ -15,10 +15,6 @@ config USB_OMAP3
>   bool "Legacy MUSB OMAP3 / OMAP4"
>   depends on ARCH_OMAP2PLUS
>  
> -config USB_DA8XX
> - bool "Legacy MUSB DA8xx/OMAP-L1x"
> - depends on ARCH_DAVINCI
> -
>  config USB_AM35X
>   bool"Legacy MUSB AM35x"
>   depends on ARCH_OMAP2PLUS && !USB_OMAP3
> diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
> index 1242ce1c8c..744f2cfaa2 100644
> --- a/drivers/usb/musb/Makefile
> +++ b/drivers/usb/musb/Makefile
> @@ -6,5 +6,4 @@
>  obj-$(CONFIG_USB_MUSB_HCD) += musb_hcd.o musb_core.o
>  obj-$(CONFIG_USB_MUSB_UDC) += musb_udc.o musb_core.o
>  obj-$(CONFIG_USB_OMAP3) += omap3.o
> -obj-$(CONFIG_USB_DA8XX) += da8xx.o
>  obj-$(CONFIG_USB_AM35X) += am35x.o
> diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c
> deleted file mode 100644
> index a652a7c3c1..00
> --- a/drivers/usb/musb/da8xx.c
> +++ /dev/null
> @@ -1,127 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * da8xx.c - TI's DA8xx platform specific usb wrapper functions.
> - *
> - * Author: Ajay Kumar Gupta 
> - *
> - * Based on drivers/usb/musb/davinci.c
> - *
> - * Copyright (C) 2009 Texas Instruments Incorporated
> - */
> -#include 
> -
> -#include "musb_core.h"
> -#include 
> -
> -/* MUSB platform configuration */
> -struct musb_config musb_cfg = {
> - .regs   = (struct musb_regs *)DA8XX_USB_OTG_CORE_BASE,
> - .timeout= DA8XX_USB_OTG_TIMEOUT,
> - .musb_speed = 0,
> -};
> -
> -/*
> - * This function enables VBUS by driving the GPIO Bank4 Pin 15 high.
> - */
> -static void enable_vbus(void)
> -{
> - u32 value;
> -
> - /* configure GPIO bank4 pin 15 in output direction */
> - value = readl(_gpio_bank45->dir);
> - writel((value & (~DA8XX_USB_VBUS_GPIO)), _gpio_bank45->dir);
> -
> - /* set GPIO bank4 pin 15 high to drive VBUS */
> - value = readl(_gpio_bank45->set_data);
> - writel((value | DA8XX_USB_VBUS_GPIO), _gpio_bank45->set_data);
> -}
> -
> -/*
> - * Enable the usb0 phy. This initialization procedure is explained in
> - * the DA8xx USB user guide document.
> - */
> -static u8 phy_on(void)
> -{
> - u32 timeout;
> - u32 cfgchip2;
> -
> - cfgchip2 = readl(_syscfg_regs->cfgchip2);
> -
> - cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN |
> -   CFGCHIP2_OTGMODE | CFGCHIP2_REFFREQ);
> - cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN | CFGCHIP2_PHY_PLLON |
> - CFGCHIP2_REFFREQ_24MHZ;
> -
> - writel(cfgchip2, _syscfg_regs->cfgchip2);
> -
> - /* wait until the usb phy pll locks */
> - timeout = musb_cfg.timeout;
> - while (timeout--)
> - if (readl(_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD)
> - return 1;
> -
> - /* USB phy was not turned on */
> - return 0;
> -}
> -
> -/*
> - * Disable the usb phy
> - */
> -static void phy_off(void)
> -{
> - u32 cfgchip2;
> -
> - /*
> -  * Power down the on-chip PHY.
> -  */
> - cfgchip2 = readl(_syscfg_regs->cfgchip2);
> - cfgchip2 &= ~CFGCHIP2_PHY_PLLON;
> - cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN;
> - writel(cfgchip2, _syscfg_regs->cfgchip2);
> -}
> -
> -/*
> - * This function performs DA8xx platform specific initialization for usb0.
> - */
> -int musb_platform_init(void)
> -{
> - u32  revision;
> -
> - /* enable psc for usb2.0 */
> - lpsc_on(33);
> -
> - /* enable usb vbus */
> - enable_vbus();
> -
> - /* reset the controller */
> - writel(0x1, _usb_regs->control);
> - udelay(5000);
> -
> - /* start the on-chip usb phy and its pll */
> - if (phy_on() == 0)
> - return -1;
> -
> - /* Returns zero if e.g. not clocked */
> - revision = readl(_usb_regs->revision);
> - if (revision == 0)
> - return -1;
> -
> - /* Disable all interrupts */
> - writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK |
> - DA8XX_USB_RXINT_MASK), _usb_regs->intmsk_set);
> - return 0;
> -}
> -
> -/*
> - * This function performs DA8xx platform specific deinitialization for usb0.
> - */
> -void musb_platform_deinit(void)
> -{
> - /* Turn of the phy */
> - phy_off();
> -
> - /* flush any interrupts */
> - writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK |
> - DA8XX_USB_RXINT_MASK), _usb_regs->intmsk_clr);
> - writel(0, _usb_regs->eoi);
> -}
> 


-- 
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Marek Vasut

Re: [U-Boot] [PATCH 3/7] da850evm: sf: Read default speed and mode values from DT

2018-12-10 Thread Petr Vorel
Hi Patrick,

> In case of DT boot, don't read default speed and mode for SPI from
> CONFIG_*, instead read from DT node.

> Signed-off-by: Patrick Delaunay 
Reviewed-by: Petr Vorel 


Kind regards,
Petr
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Re: [U-Boot] [PATCH 1/7] spi: update management of default speed and mode

2018-12-10 Thread Simon Goldschmidt

Am 10.12.2018 um 21:49 schrieb Petr Vorel:

Hi Patrick,


On Mon, Dec 10, 2018 at 11:53 AM Patrick Delaunay
 wrote:



The 2 default values for SPI mode and speed are
only if CONFIG_DM_SPI_FLASH is not defined
- CONFIG_SF_DEFAULT_SPEED
- CONFIG_SF_DEFAULT_MODE



Inverse the logic of the test to remove these two defines.



Signed-off-by: Patrick Delaunay 

Reviewed-by: Petr Vorel 


---



  cmd/sf.c   | 10 ++
  common/spl/spl_spi.c   | 11 ++-
  common/splash_source.c | 11 ++-

Patch only applies to cmd/sf.c, the other once do not apply (original patch was
too old).
Or am I missing something?


I have applied 
http://patchwork.ozlabs.org/project/uboot/list/?series=76834 before 
applying this series (as Patrick wrote in his cover letter) and it 
worked with current master.


Regards,
Simon




Kind regards,
Petr



  3 files changed, 18 insertions(+), 14 deletions(-)



diff --git a/cmd/sf.c b/cmd/sf.c
index 84bb057..cfea545 100644
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -81,16 +81,18 @@ static int do_spi_flash_probe(int argc, char * const argv[])
  {
 unsigned int bus = CONFIG_SF_DEFAULT_BUS;
 unsigned int cs = CONFIG_SF_DEFAULT_CS;
-   unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
-   unsigned int mode = CONFIG_SF_DEFAULT_MODE;
+   /* In DM mode, defaults will be taken from DT */
+   unsigned int speed = 0;
+   unsigned int mode = 0;
 char *endp;
  #ifdef CONFIG_DM_SPI_FLASH
 struct udevice *new, *bus_dev;
 int ret;
-   /* In DM mode defaults will be taken from DT */
-   speed = 0, mode = 0;
  #else
 struct spi_flash *new;
+
+   speed = CONFIG_SF_DEFAULT_SPEED;
+   mode = CONFIG_SF_DEFAULT_MODE;
  #endif



 if (argc >= 2) {
diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c
index b348b45..c1c1fcb 100644
--- a/common/spl/spl_spi.c
+++ b/common/spl/spl_spi.c
@@ -74,12 +74,13 @@ static int spl_spi_load_image(struct spl_image_info 
*spl_image,
 unsigned payload_offs = CONFIG_SYS_SPI_U_BOOT_OFFS;
 struct spi_flash *flash;
 struct image_header *header;
-   unsigned int max_hz = CONFIG_SF_DEFAULT_SPEED;
-   unsigned int spi_mode = CONFIG_SF_DEFAULT_MODE;
+   /* In DM mode, defaults will be taken from DT */
+   unsigned int max_hz = 0;
+   unsigned int spi_mode = 0;



-#ifdef CONFIG_DM_SPI_FLASH
-   /* In DM mode defaults will be taken from DT */
-   max_hz = 0, spi_mode = 0;
+#ifndef CONFIG_DM_SPI_FLASH
+   max_hz = CONFIG_SF_DEFAULT_SPEED;
+   spi_mode = CONFIG_SF_DEFAULT_MODE;
  #endif
 /*
  * Load U-Boot image from SPI flash into RAM
diff --git a/common/splash_source.c b/common/splash_source.c
index 427196c..d5d5550 100644
--- a/common/splash_source.c
+++ b/common/splash_source.c
@@ -24,12 +24,13 @@ DECLARE_GLOBAL_DATA_PTR;
  static struct spi_flash *sf;
  static int splash_sf_read_raw(u32 bmp_load_addr, int offset, size_t read_size)
  {
-   unsigned int max_hz = CONFIG_SF_DEFAULT_SPEED;
-   unsigned int spi_mode = CONFIG_SF_DEFAULT_MODE;
+   /* In DM mode, defaults will be taken from DT */
+   unsigned int max_hz = 0;
+   unsigned int spi_mode = 0;



-#ifdef CONFIG_DM_SPI_FLASH
-   /* In DM mode defaults will be taken from DT */
-   max_hz = 0, spi_mode = 0;
+#ifndef CONFIG_DM_SPI_FLASH
+   max_hz = CONFIG_SF_DEFAULT_SPEED;
+   spi_mode = CONFIG_SF_DEFAULT_MODE;
  #endif



 if (!sf) {



Reviewed-by: Simon Goldschmidt 



Regards,
Simon
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[U-Boot] [PATCH] am3517_evm: Use ttyS2 instead of ttyO2

2018-12-10 Thread Adam Ford
The serial driver in the kernel moved from ttyOx to ttySx a while
ago.  This patch updates the console parameter to align with the
kernel change.

Signed-off-by: Adam Ford 

diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 4e7e5209d4..eb50012ff7 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -88,7 +88,7 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x8200\0" \
-   "console=ttyO2,115200n8\0" \
+   "console=ttyS2,115200n8\0" \
"fdtfile=am3517-evm.dtb\0" \
"fdtaddr=0x82C0\0" \
"vram=16M\0" \
-- 
2.17.1

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Re: [U-Boot] [PATCH v3 03/11] drivers: spi: cf_spi: convert to driver model

2018-12-10 Thread Angelo Dureghello
Hi Jagan,

still sorry for the delay,
fixed all the points except 2, ready to send patch v4, please read below. 

On Tue, Oct 23, 2018 at 04:58:22PM +0530, Jagan Teki wrote:
> On Sun, Oct 14, 2018 at 1:00 PM Angelo Dureghello  wrote:
> >
> > Converting to driver model and removes non-dm code.
> >
> > Signed-off-by: Angelo Dureghello 
> > ---
> > Changes for v2:
> > - removed non DM code part
> > - add default setup of CTAR registers
> > - add DT CTAR register setup support
> > Changes for v3:
> > - changed commit head
> > - removed spi_slave reference
> > - add #ifdefs for the case OF_PLATDATA is used
> > ---
> >  drivers/spi/cf_spi.c| 517 +++-
> >  include/dm/platform_data/spi_coldfire.h |  29 ++
> >  2 files changed, 352 insertions(+), 194 deletions(-)
> >  create mode 100644 include/dm/platform_data/spi_coldfire.h
> >
> > diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
> > index 522631cbbf..bc6a156df9 100644
> > --- a/drivers/spi/cf_spi.c
> > +++ b/drivers/spi/cf_spi.c
> > @@ -6,16 +6,25 @@
> >   *
> >   * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
> >   * TsiChung Liew (tsi-chung.l...@freescale.com)
> > + *
> > + * Support for DM and DT, non-DM code removed.
> > + * Copyright (C) 2018 Angelo Dureghello 
> > + *
> > + * TODO: fsl_dspi.c should work as a driver for the DSPI module.
> >   */
> >
> >  #include 
> > +#include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >
> > -struct cf_spi_slave {
> > -   struct spi_slave slave;
> > +struct coldfire_spi_priv {
> > +   struct dspi *regs;
> > uint baudrate;
> > +   int mode;
> > int charbit;
> >  };
> >
> > @@ -38,14 +47,30 @@ DECLARE_GLOBAL_DATA_PTR;
> >  #define SPI_MODE_MOD   0x0020
> >  #define SPI_DBLRATE0x0010
> >
> > -static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
> > -{
> > -   return container_of(slave, struct cf_spi_slave, slave);
> > -}
> > +#define MCF_DSPI_MAX_CTAR_REGS 8
> >
> > -static void cfspi_init(void)
> > +/* Default values */
> > +#define MCF_DSPI_DEFAULT_SCK_FREQ  1000
> > +#define MCF_DSPI_DEFAULT_MAX_CS4
> > +#define MCF_DSPI_DEFAULT_MODE  0
> > +
> > +#define MCF_DSPI_DEFAULT_CTAR  (DSPI_CTAR_TRSZ(7) | \
> > +   DSPI_CTAR_PCSSCK_1CLK | \
> > +   DSPI_CTAR_PASC(0) | \
> > +   DSPI_CTAR_PDT(0) | \
> > +   DSPI_CTAR_CSSCK(0) | \
> > +   DSPI_CTAR_ASC(0) | \
> > +   DSPI_CTAR_DT(1) | \
> > +   DSPI_CTAR_BR(6))
> > +
> > -   volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
> > +   struct dspi *dspi = cfspi->regs;
> > +   int i;
> > +
> > +   /* Default CTARs */
> > +   for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
> > +   writel(MCF_DSPI_DEFAULT_CTAR, >ctar[i]);
> >
> > cfspi_port_conf();  /* port configuration */
> >
> > @@ -53,128 +78,9 @@ static void cfspi_init(void)
> > DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
> > DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
> > DSPI_MCR_CRXF | DSPI_MCR_CTXF;
> > -
> > -   /* Default setting in platform configuration */
> > -#ifdef CONFIG_SYS_DSPI_CTAR0
> > -   dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;
> > -#endif
> > -#ifdef CONFIG_SYS_DSPI_CTAR1
> > -   dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1;
> > -#endif
> > -#ifdef CONFIG_SYS_DSPI_CTAR2
> > -   dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2;
> > -#endif
> > -#ifdef CONFIG_SYS_DSPI_CTAR3
> > -   dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3;
> > -#endif
> > -#ifdef CONFIG_SYS_DSPI_CTAR4
> > -   dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4;
> > -#endif
> > -#ifdef CONFIG_SYS_DSPI_CTAR5
> > -   dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5;
> > -#endif
> > -#ifdef CONFIG_SYS_DSPI_CTAR6
> > -   dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6;
> > -#endif
> > -#ifdef CONFIG_SYS_DSPI_CTAR7
> > -   dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7;
> > -#endif
> > -}
> > -
> > -static void cfspi_tx(u32 ctrl, u16 data)
> > -{
> > -   volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
> > -
> > -   while ((dspi->sr & 0xF000) >= 4) ;
> > -
> > -   dspi->tfr = (ctrl | data);
> >  }
> >
> > -static u16 cfspi_rx(void)
> > -{
> > -   volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
> > -
> > -   while ((dspi->sr & 0x00F0) == 0) ;
> > -
> > -   return (dspi->rfr & 0x);
> > -}
> > -
> > -static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void 
> > *dout,
> > - void *din, ulong flags)
> > -{
> > -   struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
> > -   u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
> > -   u8 *spi_rd = NULL, *spi_wr = NULL;
> > -   static 

Re: [U-Boot] [PATCH 2/7] spi: add comment for spi_flash_probe_bus_cs function

2018-12-10 Thread Petr Vorel
Hi Patrick,

> On Mon, Dec 10, 2018 at 11:53 AM Patrick Delaunay
>  wrote:

> > Add Kernel style documentation for spi_flash_probe_bus_cs().

> > Signed-off-by: Patrick Delaunay 
Reviewed-by: Petr Vorel 
> > ---

> >  include/spi_flash.h | 14 ++
> >  1 file changed, 14 insertions(+)


Kind regards,
Petr
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Re: [U-Boot] [PATCH 1/7] spi: update management of default speed and mode

2018-12-10 Thread Petr Vorel
Hi Patrick,

> On Mon, Dec 10, 2018 at 11:53 AM Patrick Delaunay
>  wrote:

> > The 2 default values for SPI mode and speed are
> > only if CONFIG_DM_SPI_FLASH is not defined
> > - CONFIG_SF_DEFAULT_SPEED
> > - CONFIG_SF_DEFAULT_MODE

> > Inverse the logic of the test to remove these two defines.

> > Signed-off-by: Patrick Delaunay 
Reviewed-by: Petr Vorel 

> > ---

> >  cmd/sf.c   | 10 ++
> >  common/spl/spl_spi.c   | 11 ++-
> >  common/splash_source.c | 11 ++-
Patch only applies to cmd/sf.c, the other once do not apply (original patch was
too old).
Or am I missing something?


Kind regards,
Petr


> >  3 files changed, 18 insertions(+), 14 deletions(-)

> > diff --git a/cmd/sf.c b/cmd/sf.c
> > index 84bb057..cfea545 100644
> > --- a/cmd/sf.c
> > +++ b/cmd/sf.c
> > @@ -81,16 +81,18 @@ static int do_spi_flash_probe(int argc, char * const 
> > argv[])
> >  {
> > unsigned int bus = CONFIG_SF_DEFAULT_BUS;
> > unsigned int cs = CONFIG_SF_DEFAULT_CS;
> > -   unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
> > -   unsigned int mode = CONFIG_SF_DEFAULT_MODE;
> > +   /* In DM mode, defaults will be taken from DT */
> > +   unsigned int speed = 0;
> > +   unsigned int mode = 0;
> > char *endp;
> >  #ifdef CONFIG_DM_SPI_FLASH
> > struct udevice *new, *bus_dev;
> > int ret;
> > -   /* In DM mode defaults will be taken from DT */
> > -   speed = 0, mode = 0;
> >  #else
> > struct spi_flash *new;
> > +
> > +   speed = CONFIG_SF_DEFAULT_SPEED;
> > +   mode = CONFIG_SF_DEFAULT_MODE;
> >  #endif

> > if (argc >= 2) {
> > diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c
> > index b348b45..c1c1fcb 100644
> > --- a/common/spl/spl_spi.c
> > +++ b/common/spl/spl_spi.c
> > @@ -74,12 +74,13 @@ static int spl_spi_load_image(struct spl_image_info 
> > *spl_image,
> > unsigned payload_offs = CONFIG_SYS_SPI_U_BOOT_OFFS;
> > struct spi_flash *flash;
> > struct image_header *header;
> > -   unsigned int max_hz = CONFIG_SF_DEFAULT_SPEED;
> > -   unsigned int spi_mode = CONFIG_SF_DEFAULT_MODE;
> > +   /* In DM mode, defaults will be taken from DT */
> > +   unsigned int max_hz = 0;
> > +   unsigned int spi_mode = 0;

> > -#ifdef CONFIG_DM_SPI_FLASH
> > -   /* In DM mode defaults will be taken from DT */
> > -   max_hz = 0, spi_mode = 0;
> > +#ifndef CONFIG_DM_SPI_FLASH
> > +   max_hz = CONFIG_SF_DEFAULT_SPEED;
> > +   spi_mode = CONFIG_SF_DEFAULT_MODE;
> >  #endif
> > /*
> >  * Load U-Boot image from SPI flash into RAM
> > diff --git a/common/splash_source.c b/common/splash_source.c
> > index 427196c..d5d5550 100644
> > --- a/common/splash_source.c
> > +++ b/common/splash_source.c
> > @@ -24,12 +24,13 @@ DECLARE_GLOBAL_DATA_PTR;
> >  static struct spi_flash *sf;
> >  static int splash_sf_read_raw(u32 bmp_load_addr, int offset, size_t 
> > read_size)
> >  {
> > -   unsigned int max_hz = CONFIG_SF_DEFAULT_SPEED;
> > -   unsigned int spi_mode = CONFIG_SF_DEFAULT_MODE;
> > +   /* In DM mode, defaults will be taken from DT */
> > +   unsigned int max_hz = 0;
> > +   unsigned int spi_mode = 0;

> > -#ifdef CONFIG_DM_SPI_FLASH
> > -   /* In DM mode defaults will be taken from DT */
> > -   max_hz = 0, spi_mode = 0;
> > +#ifndef CONFIG_DM_SPI_FLASH
> > +   max_hz = CONFIG_SF_DEFAULT_SPEED;
> > +   spi_mode = CONFIG_SF_DEFAULT_MODE;
> >  #endif

> > if (!sf) {

> Reviewed-by: Simon Goldschmidt 

> Regards,
> Simon
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Re: [U-Boot] CONFIG_CMD_SETEXPR disabled in many defconfigs

2018-12-10 Thread Tom Rini
On Sun, Dec 09, 2018 at 10:15:21AM +0100, Jan Kiszka wrote:

> Hi all,
> 
> for some distro script [1], I need setexpr enabled. However, lots of
> defconfigs have that disabled, although it is default y in kconfig. I
> strongly suspect that this propagated via blind copy, rather than
> intentionally.
> 
> Can we remove it from the defconfigs? Does this have to happen case-by-case,
> or is a mass-removal imaginable?

I would suggest enabling it via DISTRO_DEFAULTS and do a travis build
and see if anything breaks as I suspect it was disabled long ago rather
unintentionally.

-- 
Tom


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Re: [U-Boot] [BUG] ut overlay fails with v2018.03 and later on qemu-arm64_defconfig

2018-12-10 Thread Tom Rini
On Sat, Dec 08, 2018 at 09:35:06AM +0100, Heinrich Schuchardt wrote:
> Hello Simon,
> 
> on qemu-arm_defconfig fails with
> 
> => ut overlay
> Running 9 overlay tests
> Test: fdt_overlay_add_node_by_path
> test/overlay/cmd_ut_overlay.c:127, fdt_overlay_add_node_by_path(): off >= 0
> Test: fdt_overlay_add_node_by_phandle
> test/overlay/cmd_ut_overlay.c:113, fdt_overlay_add_node_by_phandle():
> off >= 0
> Test: fdt_overlay_add_str_property
> test/overlay/cmd_ut_overlay.c:100, fdt_overlay_add_str_property(): 0 ==
> fdt_getprop_str(fdt, "/test-node", "test-str-property-2", ):
> Expected 0, got -9
> Test: fdt_overlay_add_subnode_property
> test/overlay/cmd_ut_overlay.c:141, fdt_overlay_add_subnode_property():
> off >= 0
> Test: fdt_overlay_change_int_property
> test/overlay/cmd_ut_overlay.c:74, fdt_overlay_change_int_property(): 0
> == ut_fdt_getprop_u32(fdt, "/test-node", "test-int-property", ):
> Expected 0, got -9
> Test: fdt_overlay_change_str_property
> test/overlay/cmd_ut_overlay.c:87, fdt_overlay_change_str_property(): 0
> == fdt_getprop_str(fdt, "/test-node", "test-str-property", ):
> Expected 0, got -9
> Test: fdt_overlay_local_phandle
> test/overlay/cmd_ut_overlay.c:158, fdt_overlay_local_phandle(): off >= 0
> Test: fdt_overlay_local_phandles
> test/overlay/cmd_ut_overlay.c:183, fdt_overlay_local_phandles(): off >= 0
> Test: fdt_overlay_stacked
> test/overlay/cmd_ut_overlay.c:212, fdt_overlay_stacked(): 0 ==
> ut_fdt_getprop_u32(fdt, "/new-local-node", "stacked-test-int-property",
> ): Expected 0, got -9
> Failures: 9
> 
> This is reproducable with v2018.03, v2018.05, v2018.07, v2018.09,
> v2018.11 and with current origin/master (358902586727 "Merge branch
> '2018-12-06-master-imports'").
> 
> For the elder releases I had to apply
> d796735c334b "test: overlay: add missing include"
> 
> The value of off is -9 in the tests above. This is -FDT_ERR_BADMAGIC.
> 
> Adding some debug output sheds more light:
> 
> test/overlay/cmd_ut_overlay.c(290) do_ut_overlay: fdt_base_copy
> 7ef33340
> test/overlay/cmd_ut_overlay.c(291) do_ut_overlay: uts->priv 7ef33340
> Running 9 overlay tests
> Test: fdt_overlay_add_node_by_path
> test/overlay/cmd_ut_overlay.c(127) fdt_overlay_add_node_by_path:
> uts->priv 
> 
> This is the patch that led to problem:
> e93232e15ec9 ("test: overlay: Use cmd_ut_category()")
> 
> The uts created in do_ut_overlay() is not the one used in cmd_ut_category().
> 
> The easiest fix would be using a static variable for passing the fdt.
> 
> The neatest solution would be cmd_ut_category() calling an
> initialization function for the category so that we can use a single
> instance of uts for the whole test.
> 
> As this API is your design I would prefer leaving the resolution to you.
> 
> Besides resolving the error I think we should run 'ut overlay' on Travis
> CI for all qemu platforms.

I agree we should enable UT_OVERLAY as widely as possible in our
automated testing platforms, thanks!

-- 
Tom


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[U-Boot] [PATCH 4/6] mips: Add SPL header

2018-12-10 Thread Ezequiel Garcia
From: Paul Burton 

Add header with SPL boot mode and type definitions.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
---
 arch/mips/include/asm/spl.h | 35 +++
 1 file changed, 35 insertions(+)
 create mode 100644 arch/mips/include/asm/spl.h

diff --git a/arch/mips/include/asm/spl.h b/arch/mips/include/asm/spl.h
new file mode 100644
index ..01baab606606
--- /dev/null
+++ b/arch/mips/include/asm/spl.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#ifndef_ASM_SPL_H_
+#define_ASM_SPL_H_
+
+enum {
+   BOOT_DEVICE_RAM,
+   BOOT_DEVICE_MMC1,
+   BOOT_DEVICE_MMC2,
+   BOOT_DEVICE_MMC2_2,
+   BOOT_DEVICE_NAND,
+   BOOT_DEVICE_ONENAND,
+   BOOT_DEVICE_NOR,
+   BOOT_DEVICE_UART,
+   BOOT_DEVICE_SPI,
+   BOOT_DEVICE_USB,
+   BOOT_DEVICE_SATA,
+   BOOT_DEVICE_I2C,
+   BOOT_DEVICE_BOARD,
+   BOOT_DEVICE_NONE
+};
+
+/* Linker symbols. */
+extern char __bss_start[];
+extern ulong __bss_end;
+
+#ifndef CONFIG_DM
+extern gd_t gdata;
+#endif
+
+#endif
-- 
2.20.0.rc2

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[U-Boot] [PATCH 6/6] mips: jz47xx: Add Creator CI20 platform

2018-12-10 Thread Ezequiel Garcia
From: Paul Burton 

Add support for the Creator CI20 platform based on the JZ4780 SoC.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
Signed-off-by: Ezequiel Garcia 
---
 arch/mips/dts/Makefile|   1 +
 arch/mips/dts/ci20.dts| 120 +++
 arch/mips/mach-jz47xx/Kconfig |  11 +
 board/imgtec/ci20/Kconfig |  15 ++
 board/imgtec/ci20/Makefile|   5 +
 board/imgtec/ci20/README  |  10 +
 board/imgtec/ci20/ci20.c  | 365 ++
 configs/ci20_defconfig|  47 +
 include/configs/ci20.h|  74 +++
 9 files changed, 648 insertions(+)
 create mode 100644 arch/mips/dts/ci20.dts
 create mode 100644 board/imgtec/ci20/Kconfig
 create mode 100644 board/imgtec/ci20/Makefile
 create mode 100644 board/imgtec/ci20/README
 create mode 100644 board/imgtec/ci20/ci20.c
 create mode 100644 configs/ci20_defconfig
 create mode 100644 include/configs/ci20.h

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index b447141f8717..647d2bf0d53b 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -16,6 +16,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
 dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
 dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f...@st1704.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
+dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/mips/dts/ci20.dts b/arch/mips/dts/ci20.dts
new file mode 100644
index ..934d9e96d24d
--- /dev/null
+++ b/arch/mips/dts/ci20.dts
@@ -0,0 +1,120 @@
+/dts-v1/;
+
+#include "jz4780.dtsi"
+
+/ {
+   compatible = "img,ci20", "ingenic,jz4780";
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   serial3 = 
+   serial4 = 
+   };
+
+   chosen {
+   stdout-path = "serial4:115200n8";
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x0 0x1000
+  0x3000 0x3000>;
+   };
+};
+
+ {
+   clock-frequency = <4800>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+
+   nandc: nand-controller@1 {
+   compatible = "ingenic,jz4780-nand";
+   reg = <1 0 0x100>;
+
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ingenic,bch-controller = <>;
+
+   ingenic,nemc-tAS = <10>;
+   ingenic,nemc-tAH = <5>;
+   ingenic,nemc-tBP = <10>;
+   ingenic,nemc-tAW = <15>;
+   ingenic,nemc-tSTRV = <100>;
+
+   nand@1 {
+   reg = <1>;
+
+   nand-ecc-step-size = <1024>;
+   nand-ecc-strength = <24>;
+   nand-ecc-mode = "hw";
+   nand-on-flash-bbt;
+
+   partitions {
+   compatible = "fixed-partitions";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   partition@0 {
+   label = "u-boot-spl";
+   reg = <0x0 0x0 0x0 0x80>;
+   };
+
+   partition@0x80 {
+   label = "u-boot";
+   reg = <0x0 0x80 0x0 0x20>;
+   };
+
+   partition@0xa0 {
+   label = "u-boot-env";
+   reg = <0x0 0xa0 0x0 0x20>;
+   };
+
+   partition@0xc0 {
+   label = "boot";
+   reg = <0x0 0xc0 0x0 0x400>;
+   };
+
+   partition@0x8c0 {
+   label = "system";
+   reg = <0x0 0x4c0 0x1 0xfb40>;
+   };
+   };
+   };
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   bus-width = <4>;
+   max-frequency = <5000>;
+   status = "okay";
+};
+
+ {
+   bus-width = <4>;
+   max-frequency = <5000>;
+   status = "okay";
+};
diff --git a/arch/mips/mach-jz47xx/Kconfig b/arch/mips/mach-jz47xx/Kconfig
index cd6944cfc252..dcaac0162866 100644
--- a/arch/mips/mach-jz47xx/Kconfig
+++ b/arch/mips/mach-jz47xx/Kconfig
@@ -12,4 +12,15 @@ config SOC_JZ4780
help
  Support for Ingenic JZ4780 family SoCs.
 
+choice
+   prompt "Board select"
+
+config 

[U-Boot] [PATCH 5/6] mips: jz47xx: Add JZ4780 SoC support

2018-12-10 Thread Ezequiel Garcia
From: Paul Burton 

Add initial support for the Ingenic JZ47xx MIPS SoC.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
Signed-off-by: Ezequiel Garcia 
---
 arch/mips/Kconfig |   7 +
 arch/mips/Makefile|   1 +
 arch/mips/dts/jz4780.dtsi | 162 ++
 arch/mips/mach-jz47xx/Kconfig |  15 +
 arch/mips/mach-jz47xx/Makefile|   7 +
 arch/mips/mach-jz47xx/include/mach/jz4780.h   | 104 
 .../mach-jz47xx/include/mach/jz4780_dram.h| 457 +++
 arch/mips/mach-jz47xx/jz4780/Makefile |   5 +
 arch/mips/mach-jz47xx/jz4780/jz4780.c | 142 +
 arch/mips/mach-jz47xx/jz4780/pll.c| 528 ++
 arch/mips/mach-jz47xx/jz4780/sdram.c  | 271 +
 arch/mips/mach-jz47xx/jz4780/timer.c  | 238 
 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds   |  52 ++
 arch/mips/mach-jz47xx/start.S |  99 
 include/dt-bindings/clock/jz4780-cgu.h|  88 +++
 15 files changed, 2176 insertions(+)
 create mode 100644 arch/mips/dts/jz4780.dtsi
 create mode 100644 arch/mips/mach-jz47xx/Kconfig
 create mode 100644 arch/mips/mach-jz47xx/Makefile
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780.h
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780_dram.h
 create mode 100644 arch/mips/mach-jz47xx/jz4780/Makefile
 create mode 100644 arch/mips/mach-jz47xx/jz4780/jz4780.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/pll.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/sdram.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/timer.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds
 create mode 100644 arch/mips/mach-jz47xx/start.S
 create mode 100644 include/dt-bindings/clock/jz4780-cgu.h

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1b1b1d7d0031..44b25460b8cc 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -88,6 +88,12 @@ config ARCH_MT7620
select SUPPORTS_LITTLE_ENDIAN
select SYSRESET
 
+config ARCH_JZ47XX
+   bool "Support Ingenic JZ47xx"
+   select SUPPORT_SPL
+   select OF_CONTROL
+   select DM
+
 config MACH_PIC32
bool "Support Microchip PIC32"
select DM
@@ -139,6 +145,7 @@ source "board/micronas/vct/Kconfig"
 source "board/qemu-mips/Kconfig"
 source "arch/mips/mach-ath79/Kconfig"
 source "arch/mips/mach-bmips/Kconfig"
+source "arch/mips/mach-jz47xx/Kconfig"
 source "arch/mips/mach-pic32/Kconfig"
 source "arch/mips/mach-mt7620/Kconfig"
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 802244a06e5d..a294e9b1e8b9 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -13,6 +13,7 @@ libs-y += arch/mips/lib/
 
 machine-$(CONFIG_ARCH_ATH79) += ath79
 machine-$(CONFIG_ARCH_BMIPS) += bmips
+machine-$(CONFIG_ARCH_JZ47XX) += jz47xx
 machine-$(CONFIG_MACH_PIC32) += pic32
 machine-$(CONFIG_ARCH_MT7620) += mt7620
 
diff --git a/arch/mips/dts/jz4780.dtsi b/arch/mips/dts/jz4780.dtsi
new file mode 100644
index ..e34f8d359036
--- /dev/null
+++ b/arch/mips/dts/jz4780.dtsi
@@ -0,0 +1,162 @@
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "ingenic,jz4780";
+
+   cpuintc: interrupt-controller {
+   #address-cells = <0>;
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   compatible = "mti,cpu-interrupt-controller";
+   };
+
+   intc: interrupt-controller@10001000 {
+   compatible = "ingenic,jz4780-intc";
+   reg = <0x10001000 0x50>;
+
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   interrupt-parent = <>;
+   interrupts = <2>;
+   };
+
+   ext: ext {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   };
+
+   rtc: rtc {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   };
+
+   cgu: jz4780-cgu@1000 {
+   compatible = "ingenic,jz4780-cgu";
+   reg = <0x1000 0x100>;
+
+   clocks = <>, <>;
+   clock-names = "ext", "rtc";
+
+   #clock-cells = <1>;
+   };
+
+   mmc0: mmc@1345 {
+   compatible = "ingenic,jz4780-mmc";
+   reg = <0x1345 0x1000>;
+
+   status = "disabled";
+
+   clocks = < JZ4780_CLK_MSC0>;
+   clock-names = "mmc";
+   };
+
+   mmc1: mmc@1346 {
+   compatible = "ingenic,jz4780-mmc";
+   reg = <0x1346 0x1000>;
+
+   clocks = < JZ4780_CLK_MSC1>;
+   clock-names = "mmc";
+
+   status = "disabled";
+   };
+
+   uart0: serial@1003 {
+   compatible = "ingenic,jz4780-uart";
+   reg = <0x1003 0x100>;
+

[U-Boot] [PATCH 3/6] mmc: Add JZ47xx SD/MMC controller driver

2018-12-10 Thread Ezequiel Garcia
From: Paul Burton 

Add driver for the JZ47xx MSC controller.

Cc: Daniel Schwierzeck 
Signed-off-by: Paul Burton 
Signed-off-by: Marek Vasut 
Signed-off-by: Ezequiel Garcia 
---
 drivers/mmc/Kconfig  |   6 +
 drivers/mmc/Makefile |   1 +
 drivers/mmc/jz_mmc.  |   0
 drivers/mmc/jz_mmc.c | 491 +++
 4 files changed, 498 insertions(+)
 create mode 100644 drivers/mmc/jz_mmc.
 create mode 100644 drivers/mmc/jz_mmc.c

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index fbd13964a084..496b2cba6405 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -332,6 +332,12 @@ config MMC_BCM2835
 
  If unsure, say N.
 
+config JZ47XX_MMC
+   bool "Ingenic JZ47xx SD/MMC Host Controller support"
+   depends on ARCH_JZ47XX
+   help
+ This selects support for the SD Card Controller on Ingenic JZ47xx 
SoCs.
+
 config MMC_SANDBOX
bool "Sandbox MMC support"
depends on SANDBOX
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 801a26d82192..7892c468f05c 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o
 obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
 obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
 obj-$(CONFIG_STM32_SDMMC2) += stm32_sdmmc2.o
+obj-$(CONFIG_JZ47XX_MMC) += jz_mmc.o
 
 # SDHCI
 obj-$(CONFIG_MMC_SDHCI)+= sdhci.o
diff --git a/drivers/mmc/jz_mmc. b/drivers/mmc/jz_mmc.
new file mode 100644
index ..e69de29bb2d1
diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c
new file mode 100644
index ..18c1810ff42c
--- /dev/null
+++ b/drivers/mmc/jz_mmc.c
@@ -0,0 +1,491 @@
+/*
+ * Ingenic JZ MMC driver
+ *
+ * Copyright (c) 2013 Imagination Technologies
+ * Author: Paul Burton 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Registers */
+#define MSC_STRPCL 0x000
+#define MSC_STAT   0x004
+#define MSC_CLKRT  0x008
+#define MSC_CMDAT  0x00c
+#define MSC_RESTO  0x010
+#define MSC_RDTO   0x014
+#define MSC_BLKLEN 0x018
+#define MSC_NOB0x01c
+#define MSC_SNOB   0x020
+#define MSC_IMASK  0x024
+#define MSC_IREG   0x028
+#define MSC_CMD0x02c
+#define MSC_ARG0x030
+#define MSC_RES0x034
+#define MSC_RXFIFO 0x038
+#define MSC_TXFIFO 0x03c
+#define MSC_LPM0x040
+#define MSC_DMAC   0x044
+#define MSC_DMANDA 0x048
+#define MSC_DMADA  0x04c
+#define MSC_DMALEN 0x050
+#define MSC_DMACMD 0x054
+#define MSC_CTRL2  0x058
+#define MSC_RTCNT  0x05c
+#define MSC_DBG0x0fc
+
+/* MSC Clock and Control Register (MSC_STRPCL) */
+#define MSC_STRPCL_EXIT_MULTIPLE   BIT(7)
+#define MSC_STRPCL_EXIT_TRANSFER   BIT(6)
+#define MSC_STRPCL_START_READWAIT  BIT(5)
+#define MSC_STRPCL_STOP_READWAIT   BIT(4)
+#define MSC_STRPCL_RESET   BIT(3)
+#define MSC_STRPCL_START_OPBIT(2)
+#define MSC_STRPCL_CLOCK_CONTROL_STOP  BIT(0)
+#define MSC_STRPCL_CLOCK_CONTROL_START BIT(1)
+
+/* MSC Status Register (MSC_STAT) */
+#define MSC_STAT_AUTO_CMD_DONE BIT(31)
+#define MSC_STAT_IS_RESETTING  BIT(15)
+#define MSC_STAT_SDIO_INT_ACTIVE   BIT(14)
+#define MSC_STAT_PRG_DONE  BIT(13)
+#define MSC_STAT_DATA_TRAN_DONEBIT(12)
+#define MSC_STAT_END_CMD_RES   BIT(11)
+#define MSC_STAT_DATA_FIFO_AFULL   BIT(10)
+#define MSC_STAT_IS_READWAIT   BIT(9)
+#define MSC_STAT_CLK_ENBIT(8)
+#define MSC_STAT_DATA_FIFO_FULLBIT(7)
+#define MSC_STAT_DATA_FIFO_EMPTY   BIT(6)
+#define MSC_STAT_CRC_RES_ERR   BIT(5)
+#define MSC_STAT_CRC_READ_ERRORBIT(4)
+#define MSC_STAT_CRC_WRITE_ERROR   BIT(2)
+#define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4)
+#define MSC_STAT_TIME_OUT_RES  BIT(1)
+#define MSC_STAT_TIME_OUT_READ BIT(0)
+
+/* MSC Bus Clock Control Register (MSC_CLKRT) */
+#define MSC_CLKRT_CLK_RATE_MASK0x7
+
+/* MSC Command Sequence Control Register (MSC_CMDAT) */
+#define MSC_CMDAT_IO_ABORT BIT(11)
+#define MSC_CMDAT_BUS_WIDTH_1BIT   (0x0 << 9)
+#define MSC_CMDAT_BUS_WIDTH_4BIT   (0x2 << 9)
+#define MSC_CMDAT_DMA_EN   BIT(8)
+#define MSC_CMDAT_INIT BIT(7)
+#define MSC_CMDAT_BUSY BIT(6)
+#define MSC_CMDAT_STREAM_BLOCK BIT(5)
+#define MSC_CMDAT_WRITE

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