Re: [U-Boot] [PATCH] fpga: zynqmp: show an error message when FPGA programming fails
On 11. 01. 19 17:09, Luca Ceresoli wrote:
> When FPGA programming fails, it does so silently, unless debugging
> code is enabled. This makes it hard to detect problems in production
> environments.
>
> Print the error message unconditionally so the error doesn't go
> unnoticed.
>
> Signed-off-by: Luca Ceresoli
> ---
> drivers/fpga/zynqmppl.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
> index c095d5ecaa85..22bfdd8dce61 100644
> --- a/drivers/fpga/zynqmppl.c
> +++ b/drivers/fpga/zynqmppl.c
> @@ -233,7 +233,7 @@ static int zynqmp_load(xilinx_desc *desc, const void
> *buf, size_t bsize,
>(u32)bsize, 0, ret_payload);
>
> if (ret)
> - debug("PL FPGA LOAD fail\n");
> + puts("PL FPGA LOAD fail\n");
>
> return ret;
> }
>
Note: Not a problem with this path. It shouldn't be hard to detect it in
production system if your scripts are checking return values.
Applied.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
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Re: [U-Boot] [PATCH v3 0/3] arm: socpfpga: gen5 clean up ETH RST & PHY mode
On 1/13/19 7:58 PM, Simon Goldschmidt wrote: > Socfpga Gen5 uses ad-hoc code to unreset the ETH MACs and set their > PHY mode. > > Change this to use the dwmac_socfpga net driver and remove the old > ad-hoc code. > > Changes in v3: > - imply CONFIG_ETH_DESIGNWARE_SOCFGPA instead of changing all defconfigs > > Changes in v2: > - remove detection of sub-mach via compatible version and handle > all FPGAs the same > - select SYSCON and REGMAP via Kconfig > - only add CONFIG_ETH_DESIGNWARE_SOCFPGA since now REGMAP and SYSCON > are selected by this one > > Simon Goldschmidt (3): > net: designware: socfpga: adapt to Gen5 > arm: socfpga: gen5 enable designware_socfpga > arm: socfpga: gen5: remove hacked ETH RST handling > > .../mach-socfpga/include/mach/reset_manager.h | 2 - > arch/arm/mach-socfpga/misc.c | 65 -- > arch/arm/mach-socfpga/misc_gen5.c | 44 +- > drivers/net/Kconfig | 3 + > drivers/net/dwmac_socfpga.c | 87 +++ > 5 files changed, 37 insertions(+), 164 deletions(-) > Applied all, thanks! -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] ARM: bcm283x: Fix definition of MBOX_TAG_TEST_PIXEL_ORDER
From: Berkus Decker
The MBOX_TAG_TEST_PIXEL_ORDER define is incorrect. According to official
documentation it has a slightly different numbering.
Correct mailbox constants are defined in e.g.
linux raspberry-firmware
https://code.woboq.org/linux/linux/include/soc/bcm2835/raspberrypi-firmware.h.html#RPI_FIRMWARE_FRAMEBUFFER_TEST_PIXEL_ORDER
These are obtained from the bcm2835 documentation
e.g.
https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface#test-pixel-order
Fix the define to get us back in sync with the spec.
Signed-off-by: Berkus Decker
[agraf: clarify subject, extend commit message]
Signed-off-by: Alexander Graf
---
arch/arm/mach-bcm283x/include/mach/mbox.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h
b/arch/arm/mach-bcm283x/include/mach/mbox.h
index 2776a396c7..e3a893e49c 100644
--- a/arch/arm/mach-bcm283x/include/mach/mbox.h
+++ b/arch/arm/mach-bcm283x/include/mach/mbox.h
@@ -348,7 +348,7 @@ struct bcm2835_mbox_tag_depth {
};
#define BCM2835_MBOX_TAG_GET_PIXEL_ORDER 0x00040006
-#define BCM2835_MBOX_TAG_TEST_PIXEL_ORDER 0x00044005
+#define BCM2835_MBOX_TAG_TEST_PIXEL_ORDER 0x00044006
#define BCM2835_MBOX_TAG_SET_PIXEL_ORDER 0x00048006
#define BCM2835_MBOX_PIXEL_ORDER_BGR 0
--
2.12.3
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[U-Boot] [PATCH v3 2/3] arm: socfpga: gen5 enable designware_socfpga
Enable the socfpga specific designware ethernet driver by default for socfpga by implying it when enabling CONFIG_ETH_DESIGNWARE for a MACH_SOCFPGA config. This is required to remove the hacky reset and phy mode handling in arch/arm/mach-socfpga. Signed-off-by: Simon Goldschmidt --- Changes in v3: - imply CONFIG_ETH_DESIGNWARE_SOCFGPA instead of changing all defconfigs Changes in v2: - only add CONFIG_ETH_DESIGNWARE_SOCFPGA since now REGMAP and SYSCON are selected by this one drivers/net/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index b7c0b921e6..46b677dba0 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -156,6 +156,7 @@ config ETH_SANDBOX_RAW config ETH_DESIGNWARE bool "Synopsys Designware Ethernet MAC" select PHYLIB + imply ETH_DESIGNWARE_SOCFPGA if ARCH_SOCFPGA help This MAC is present in SoCs from various vendors. It supports 100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 3/3] arm: socfpga: gen5: remove hacked ETH RST handling
The 'dwmac_socfpga' ETH driver can now get the MACs out of reset
via the socfpga reset driver and can set PHY mode via syscon.
This means we can now remove the ad-hoc code to do this from
arch/arm/mach-socfpga.
Signed-off-by: Simon Goldschmidt
---
Changes in v3: None
Changes in v2: None
.../mach-socfpga/include/mach/reset_manager.h | 2 -
arch/arm/mach-socfpga/misc.c | 65 ---
arch/arm/mach-socfpga/misc_gen5.c | 44 +
3 files changed, 1 insertion(+), 110 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index d9e0b33c60..42beaecdd6 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -10,8 +10,6 @@ void reset_cpu(ulong addr);
void socfpga_per_reset(u32 reset, int set);
void socfpga_per_reset_all(void);
-int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id,
-const u8 phymode));
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 78fbe28724..e1adea143c 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -120,71 +120,6 @@ int arch_cpu_init(void)
return 0;
}
-#ifdef CONFIG_ETH_DESIGNWARE
-static int dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
-{
- if (!phymode)
- return -EINVAL;
-
- if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
- *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
- return 0;
- }
-
- if (!strcmp(phymode, "rgmii")) {
- *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
- return 0;
- }
-
- if (!strcmp(phymode, "rmii")) {
- *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
- return 0;
- }
-
- return -EINVAL;
-}
-
-int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id,
-const u8 phymode))
-{
- const void *fdt = gd->fdt_blob;
- struct fdtdec_phandle_args args;
- const char *phy_mode;
- u32 phy_modereg;
- int nodes[2]; /* Max. two GMACs */
- int ret, count;
- int i, node;
-
- count = fdtdec_find_aliases_for_id(fdt, "ethernet",
- COMPAT_ALTERA_SOCFPGA_DWMAC,
- nodes, ARRAY_SIZE(nodes));
- for (i = 0; i < count; i++) {
- node = nodes[i];
- if (node <= 0)
- continue;
-
- ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
-"#reset-cells", 1, 0,
-);
- if (ret || (args.args_count != 1)) {
- debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
- continue;
- }
-
- phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
- ret = dwmac_phymode_to_modereg(phy_mode, _modereg);
- if (ret) {
- debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
- continue;
- }
-
- resetfn(args.args[0], phy_modereg);
- }
-
- return 0;
-}
-#endif
-
#ifndef CONFIG_SPL_BUILD
static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
diff --git a/arch/arm/mach-socfpga/misc_gen5.c
b/arch/arm/mach-socfpga/misc_gen5.c
index 04f237d100..6e11ba6cb2 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -54,48 +54,6 @@ static Altera_desc altera_fpga[] = {
},
};
-/*
- * DesignWare Ethernet initialization
- */
-#ifdef CONFIG_ETH_DESIGNWARE
-static void gen5_dwmac_reset(const u8 of_reset_id, const u8 phymode)
-{
- u32 physhift, reset;
-
- if (of_reset_id == EMAC0_RESET) {
- physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
- reset = SOCFPGA_RESET(EMAC0);
- } else if (of_reset_id == EMAC1_RESET) {
- physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
- reset = SOCFPGA_RESET(EMAC1);
- } else {
- printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
- return;
- }
-
- /* configure to PHY interface select choosed */
- clrsetbits_le32(_regs->emacgrp_ctrl,
- SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
- phymode << physhift);
-
- /* Release the EMAC controller from reset */
- socfpga_per_reset(reset, 0);
-}
-
-static int socfpga_eth_reset(void)
-{
- /* Put all GMACs into RESET state. */
- socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
- socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
-
[U-Boot] [PATCH v3 1/3] net: designware: socfpga: adapt to Gen5
This driver was written for Arria10, but it applies to Gen5, too.
The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the
syscon bits are encoded in the same register, thus an offset is needed.
This offset is already read from the devicetree, but for Arria10 it is
always 0, which is probably why it has been ignored. By using this
offset when writing the phy mode into the syscon regiter, we can use
this driver to set the phy mode for both of the MACs on Gen5.
Since the PHY mode bits in sysmgr are the same even for Stratix10,
let's drop the detection of the sub-mach by checking compatible
version and just use the same code for all FPGAs.
To work correctly, this driver depends on SYSCON and REGMAP, so select
those via Kconfig when it is enabeld.
Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift
offset is required).
Signed-off-by: Simon Goldschmidt
---
Changes in v3: None
Changes in v2:
- remove detection of sub-mach via compatible version and handle
all FPGAs the same
- select SYSCON and REGMAP via Kconfig
drivers/net/Kconfig | 2 +
drivers/net/dwmac_socfpga.c | 87 ++---
2 files changed, 35 insertions(+), 54 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 7044c6adf3..b7c0b921e6 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -162,6 +162,8 @@ config ETH_DESIGNWARE
provide the PHY (physical media interface).
config ETH_DESIGNWARE_SOCFPGA
+ select REGMAP
+ select SYSCON
bool "Altera SoCFPGA extras for Synopsys Designware Ethernet MAC"
depends on DM_ETH && ETH_DESIGNWARE
help
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c
index 08fc9677c4..b7bf5dbe69 100644
--- a/drivers/net/dwmac_socfpga.c
+++ b/drivers/net/dwmac_socfpga.c
@@ -17,16 +17,10 @@
#include
-enum dwmac_type {
- DWMAC_SOCFPGA_GEN5 = 0,
- DWMAC_SOCFPGA_ARRIA10,
- DWMAC_SOCFPGA_STRATIX10,
-};
-
struct dwmac_socfpga_platdata {
struct dw_eth_pdata dw_eth_pdata;
- enum dwmac_type type;
void*phy_intf;
+ u32 reg_shift;
};
static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev)
@@ -63,21 +57,7 @@ static int dwmac_socfpga_ofdata_to_platdata(struct udevice
*dev)
}
pdata->phy_intf = range + args.args[0];
-
- /*
-* Sadly, the Altera DT bindings don't have SoC-specific compatibles,
-* so we have to guesstimate which SoC we are running on from the
-* DWMAC version. Luckily, Altera at least updated the DWMAC with
-* each SoC.
-*/
- if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.70a"))
- pdata->type = DWMAC_SOCFPGA_GEN5;
-
- if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.72a"))
- pdata->type = DWMAC_SOCFPGA_ARRIA10;
-
- if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.74a"))
- pdata->type = DWMAC_SOCFPGA_STRATIX10;
+ pdata->reg_shift = args.args[1];
return designware_eth_ofdata_to_platdata(dev);
}
@@ -88,40 +68,39 @@ static int dwmac_socfpga_probe(struct udevice *dev)
struct eth_pdata *edata = >dw_eth_pdata.eth_pdata;
struct reset_ctl_bulk reset_bulk;
int ret;
- u8 modereg;
-
- if (pdata->type == DWMAC_SOCFPGA_ARRIA10) {
- switch (edata->phy_interface) {
- case PHY_INTERFACE_MODE_MII:
- case PHY_INTERFACE_MODE_GMII:
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
- break;
- case PHY_INTERFACE_MODE_RMII:
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
- break;
- case PHY_INTERFACE_MODE_RGMII:
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
- break;
- default:
- dev_err(dev, "Unsupported PHY mode\n");
- return -EINVAL;
- }
-
- ret = reset_get_bulk(dev, _bulk);
- if (ret) {
- dev_err(dev, "Failed to get reset: %d\n", ret);
- return ret;
- }
-
- reset_assert_bulk(_bulk);
-
- clrsetbits_le32(pdata->phy_intf,
- SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
- modereg);
-
- reset_release_bulk(_bulk);
+ u32 modereg;
+ u32 modemask;
+
+ switch (edata->phy_interface) {
+ case PHY_INTERFACE_MODE_MII:
+ case PHY_INTERFACE_MODE_GMII:
+ modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+
[U-Boot] [PATCH v3 0/3] arm: socpfpga: gen5 clean up ETH RST & PHY mode
Socfpga Gen5 uses ad-hoc code to unreset the ETH MACs and set their PHY mode. Change this to use the dwmac_socfpga net driver and remove the old ad-hoc code. Changes in v3: - imply CONFIG_ETH_DESIGNWARE_SOCFGPA instead of changing all defconfigs Changes in v2: - remove detection of sub-mach via compatible version and handle all FPGAs the same - select SYSCON and REGMAP via Kconfig - only add CONFIG_ETH_DESIGNWARE_SOCFPGA since now REGMAP and SYSCON are selected by this one Simon Goldschmidt (3): net: designware: socfpga: adapt to Gen5 arm: socfpga: gen5 enable designware_socfpga arm: socfpga: gen5: remove hacked ETH RST handling .../mach-socfpga/include/mach/reset_manager.h | 2 - arch/arm/mach-socfpga/misc.c | 65 -- arch/arm/mach-socfpga/misc_gen5.c | 44 +- drivers/net/Kconfig | 3 + drivers/net/dwmac_socfpga.c | 87 +++ 5 files changed, 37 insertions(+), 164 deletions(-) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] sun50i: h5: Orange Pi Zero Plus: Fix SdCard detection
The Detection pin is at PF6 and not at PH13 like defined before. I
checked the schematics and now I am am not seeing this error message any
more:
Loading Environment from FAT... Card did not respond to voltage select!
CONFIG_MMC_SUNXI_SLOT_EXTRA is also not needed because the second MCC
slot is for the Wifi card.
Fixes: 76d69eb01de ("sun50i: h5: Add initial Orange Pi Zero Plus support")
Signed-off-by: Hauke Mehrtens
---
configs/orangepi_zero_plus_defconfig | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/configs/orangepi_zero_plus_defconfig
b/configs/orangepi_zero_plus_defconfig
index 5d783c5981..2b9691a1aa 100644
--- a/configs/orangepi_zero_plus_defconfig
+++ b/configs/orangepi_zero_plus_defconfig
@@ -4,8 +4,7 @@ CONFIG_SPL=y
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881977
-CONFIG_MMC0_CD_PIN="PH13"
-CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_MMC0_CD_PIN="PF6"
CONFIG_NR_DRAM_BANKS=1
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
# CONFIG_CMD_FLASH is not set
--
2.20.1
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Re: [U-Boot] 2019.01 release question
Jagan Teki a écrit : On Sun, Jan 13, 2019 at 6:43 PM wea...@meer.net wrote: so it looks like -rcXX tags doesn't have commit eef05fd3ba68220156f33ffe6a9e68e42a6a5b53 Author: Andre Przywara Date: Mon Dec 17 10:05:45 2018 + mmc: bring back partition init for non-DM MMC drivers i realize that there are warnings for getting things to to support DM, but the warnings mention the 2019.04 release. can this patch be included in the 2019.01 release and we users get what they desrve if it hasn't been converted by 2019.04 :-) ? Its' included for this release on top of rc3 [1] thanks \p ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] net: dm: fec: Support the phy-supply binding
On Thu, Oct 4, 2018 at 12:55 PM Martin Fuzzey
wrote:
>
> Configure the phy regulator if defined by the "phy-supply" DT phandle.
>
> Signed-off-by: Martin Fuzzey
This patch seems to break the Ethernet on my board, but I think I have
a possible solution (see below)
> ---
> drivers/net/fec_mxc.c | 20
> drivers/net/fec_mxc.h | 3 +++
> 2 files changed, 23 insertions(+)
>
> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> index 163ae4c..4ae 100644
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
> @@ -15,6 +15,7 @@
> #include
> #include
> #include
> +#include
>
> #include
> #include
> @@ -1272,6 +1273,16 @@ static int fecmxc_probe(struct udevice *dev)
> if (ret)
> return ret;
>
> +#ifdef CONFIG_DM_REGULATOR
> + if (priv->phy_supply) {
> + ret = regulator_autoset(priv->phy_supply);
I have a board that uses a fixed regulator driven by a GPIO. It's
neither always-on, nor it is enabled on boot and it doesn't have a
specified current setting. With DM_REGULATOR set, regulator_autoset
fails and FEC doesn't come up.
Looking at a bunch of other drivers, and how they enable their
respective regulators, they're using regulator_set_enable instead of
autoset.
Is there a reason we couldn't use
ret = regulator_set_enable(priv->phy_supply, true);
adam
> + if (ret) {
> + printf("%s: Error enabling phy supply\n", dev->name);
> + return ret;
> + }
> + }
> +#endif
> +
> #ifdef CONFIG_DM_GPIO
> fec_gpio_reset(priv);
> #endif
> @@ -1327,6 +1338,11 @@ static int fecmxc_remove(struct udevice *dev)
> mdio_unregister(priv->bus);
> mdio_free(priv->bus);
>
> +#ifdef CONFIG_DM_REGULATOR
> + if (priv->phy_supply)
> + regulator_set_enable(priv->phy_supply, false);
> +#endif
> +
> return 0;
> }
>
> @@ -1364,6 +1380,10 @@ static int fecmxc_ofdata_to_platdata(struct udevice
> *dev)
> }
> #endif
>
> +#ifdef CONFIG_DM_REGULATOR
> + device_get_supply_regulator(dev, "phy-supply", >phy_supply);
> +#endif
> +
> return 0;
> }
>
> diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
> index fd89443..848cd7c 100644
> --- a/drivers/net/fec_mxc.h
> +++ b/drivers/net/fec_mxc.h
> @@ -250,6 +250,9 @@ struct fec_priv {
> int phy_id;
> int (*mii_postcall)(int);
> #endif
> +#ifdef CONFIG_DM_REGULATOR
> + struct udevice *phy_supply;
> +#endif
> #ifdef CONFIG_DM_GPIO
> struct gpio_desc phy_reset_gpio;
> uint32_t reset_delay;
> --
> 1.9.1
>
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Re: [U-Boot] 2019.01 release question
On Sun, Jan 13, 2019 at 6:43 PM wea...@meer.net wrote: > > so it looks like -rcXX tags doesn't have > > commit eef05fd3ba68220156f33ffe6a9e68e42a6a5b53 > Author: Andre Przywara > Date: Mon Dec 17 10:05:45 2018 + > > mmc: bring back partition init for non-DM MMC drivers > > i realize that there are warnings for getting things to to support DM, > but the warnings mention the 2019.04 release. can this patch be > included in the 2019.01 release and we users get what they desrve if > it hasn't been converted by 2019.04 :-) ? Its' included for this release on top of rc3 [1] [1] http://git.denx.de/?p=u-boot.git;a=commitdiff;h=eef05fd3ba68220156f33ffe6a9e68e42a6a5b53 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] 2019.01 release question
so it looks like -rcXX tags doesn't have commit eef05fd3ba68220156f33ffe6a9e68e42a6a5b53 Author: Andre Przywara Date: Mon Dec 17 10:05:45 2018 + mmc: bring back partition init for non-DM MMC drivers i realize that there are warnings for getting things to to support DM, but the warnings mention the 2019.04 release. can this patch be included in the 2019.01 release and we users get what they desrve if it hasn't been converted by 2019.04 :-) ? \p ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 00/10] Kconfig: spelling fixes
These were found automatically with codespell. Codespell is fairly conservative about false positives so there are likely more errors but these are the low hanging fruit. These patches should all be self-contained so subsystem/board maintainers can pick them up at will. Chris Packham (10): Kconfig: fix spelling common: spl: Kconfig: spelling fixes arm: Kconfig: spelling fixes x86: Kconfig: spelling fixes work_92105: Kconfig: spelling fixes drivers: Kconfig: spelling fixes i2c: Kconfig: spelling fixes pinctrl: Kconfig: spelling fixes video: Kconfig: spelling fixes lib: Kconfig: spelling fixes Kconfig | 2 +- arch/arm/mach-bcm283x/Kconfig | 10 +- arch/x86/cpu/qemu/Kconfig | 2 +- arch/x86/cpu/quark/Kconfig | 2 +- board/work-microwave/work_92105/Kconfig | 2 +- common/spl/Kconfig | 2 +- drivers/core/Kconfig| 2 +- drivers/i2c/Kconfig | 8 drivers/pinctrl/Kconfig | 2 +- drivers/video/rockchip/Kconfig | 2 +- lib/Kconfig | 4 ++-- 11 files changed, 19 insertions(+), 19 deletions(-) -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] arm64: mvebu: Add basic support for uDPU board
On 11.01.19 18:21, Vladimir Vid wrote:
This adds initial support for micro-DPU (uDPU) board which is based on
Armada-3720 SoC.
micro-DPU is the single-port FTTdp "distribution point unit" made by Methode
Electronics
which offers complete modularity with replaceable SFP modules both for uplink
and downlink
(G.hn over twisted-pair, G.hn over coax, 1G and 2.5G Ethernet over Cat-5e
cable).
On-board features:
- 512 MiB DDR3
- 2 x 2.5G SFP via HSGMII SERDES interface to the A3720 SoC
- USB 2.0 Type-C connector
- 4GB eMMC
- ETSI TS 101548 reverse powering via twisted pair (RJ45) or coax (F Type)
Cc: Luka Perkov
Cc: Luis Torres
Cc: Scott Roberts
Cc: Paul Arola
Signed-off-by: Vladimir Vid
---
arch/arm/dts/Makefile |1 +
arch/arm/dts/armada-3720-uDPU.dts | 197 +++
board/Marvell/mvebu_armada-37xx/MAINTAINERS |5 +
configs/uDPU_defconfig | 1242 +++
4 files changed, 1445 insertions(+)
create mode 100644 arch/arm/dts/armada-3720-uDPU.dts
create mode 100644 configs/uDPU_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dda4e59491..534dde5484 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -95,6 +95,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-3720-db.dtb \
armada-3720-espressobin.dtb \
armada-3720-turris-mox.dtb \
+ armada-3720-uDPU.dts\
armada-375-db.dtb \
armada-388-clearfog.dtb \
armada-388-gp.dtb \
diff --git a/arch/arm/dts/armada-3720-uDPU.dts
b/arch/arm/dts/armada-3720-uDPU.dts
new file mode 100644
index 00..edbc7837a7
--- /dev/null
+++ b/arch/arm/dts/armada-3720-uDPU.dts
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device tree for the uDPU board.
+ * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
+ * Copyright (C) 2016 Marvell
+ * Copyright (C) 2018 Methode
+ * Copyright (C) 2018 Telus
+ *
+ * Vladimir Vid
+ */
+
+/dts-v1/;
+
+#include "armada-37xx.dtsi"
+
+/ {
+ model = "Methode uDPU Board";
+ compatible = "marvell,armada-3720-db-v2", "marvell,armada3720",
"marvell,armada3710";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "console=ttyMV0,115200
earlycon=ar3700_uart,0xd0012000";
+ };
+
+ aliases {
+ i2c0 =
+ i2c1 =
+ spi0 =
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x 0x 0x 0x2000>;
+ };
+
+ mdio: mdio@32004 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethphy0: ethernet-phy@0 {
+reg = <0>;
+ };
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+
+ scsi: scsi {
+ compatible = "marvell,mvebu-scsi";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ max-id = <1>;
+ max-lun = <1>;
+ status = "okay";
+ };
+
+ i2c1: i2c@11080 {
+ compatible = "marvell,armada-3700-i2c", "simple-bus";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x11080 0x80>;
+ status = "okay";
+ };
+
+ uart1: serial@12200 {
+ compatible = "marvell,armada-3700-uart-ext";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ reg = <0x12200 0x30>;
+ interrupts = ;
+ status = "okay";
+ };
+
+ vcc_sd_reg0: regulator@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "vcc_sd0";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-type = "voltage";
+ states = <180 0x1
+ 330 0x0>;
+ gpios = < 23 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth0: sfp-eth0 {
+ compatible = "sff,sfp";
+ i2c-bus = <>;
+ los-gpio = < 2 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = < 3 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = < 4 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = < 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth1: sfp-eth1 {
+ compatible = "sff,sfp";
+ i2c-bus = <>;
+ sfp,ethernet = <>;
+ los-gpio = < 7 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = < 8 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = < 9 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = < 10 GPIO_ACTIVE_HIGH>;
+
[U-Boot] [PATCH 04/10] x86: Kconfig: spelling fixes
Signed-off-by: Chris Packham --- arch/x86/cpu/qemu/Kconfig | 2 +- arch/x86/cpu/quark/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig index fdf558d66077..f8f2f6473088 100644 --- a/arch/x86/cpu/qemu/Kconfig +++ b/arch/x86/cpu/qemu/Kconfig @@ -28,7 +28,7 @@ config ACPI_PM1_BASE hex default 0xe400 help - ACPI Power Managment 1 (PM1) i/o-mapped base address. + ACPI Power Management 1 (PM1) i/o-mapped base address. This device is defined in ACPI specification, with 16 bytes in size. endif diff --git a/arch/x86/cpu/quark/Kconfig b/arch/x86/cpu/quark/Kconfig index 3a18cb0dfc60..430cce184d42 100644 --- a/arch/x86/cpu/quark/Kconfig +++ b/arch/x86/cpu/quark/Kconfig @@ -84,7 +84,7 @@ config ACPI_PM1_BASE hex default 0x1000 help - ACPI Power Managment 1 (PM1) i/o-mapped base address. + ACPI Power Management 1 (PM1) i/o-mapped base address. This device is defined in ACPI specification, with 16 bytes in size. config ACPI_PBLK_BASE -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 10/10] lib: Kconfig: spelling fixes
Signed-off-by: Chris Packham --- lib/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/Kconfig b/lib/Kconfig index 0333ab172fa6..366d164cd760 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -147,7 +147,7 @@ config SPL_TINY_MEMSET The faster memset() is the arch-specific one (if available) enabled by CONFIG_USE_ARCH_MEMSET. If that is not enabled, we can still get better performance by writing a word at a time. But in very - size-constrained envrionments even this may be too big. Enable this + size-constrained environments even this may be too big. Enable this option to reduce code size slightly at the cost of some speed. config TPL_TINY_MEMSET @@ -156,7 +156,7 @@ config TPL_TINY_MEMSET The faster memset() is the arch-specific one (if available) enabled by CONFIG_USE_ARCH_MEMSET. If that is not enabled, we can still get better performance by writing a word at a time. But in very - size-constrained envrionments even this may be too big. Enable this + size-constrained environments even this may be too big. Enable this option to reduce code size slightly at the cost of some speed. config RBTREE -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 08/10] pinctrl: Kconfig: spelling fixes
Signed-off-by: Chris Packham --- drivers/pinctrl/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 30a6aa6ee8eb..fb441b3bf1bc 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -146,7 +146,7 @@ config PINCTRL_PIC32 Supports individual pin selection and configuration for each remappable peripheral available on Microchip PIC32 SoCs. This driver is controlled by a device tree node which - contains both GPIO defintion and pin control functions. + contains both GPIO definition and pin control functions. config PINCTRL_QCA953X bool "QCA/Athores qca953x pin control driver" -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 07/10] i2c: Kconfig: spelling fixes
Signed-off-by: Chris Packham --- drivers/i2c/Kconfig | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 1ef22e6bcde2..838500707071 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -157,9 +157,9 @@ config SYS_I2C_MESON config SYS_I2C_MXC bool "NXP MXC I2C driver" help - Add support for the NXP I2C driver. This supports upto for bus - channels and operating on standard mode upto 100 kbits/s and fast - mode upto 400 kbits/s. + Add support for the NXP I2C driver. This supports up to four bus + channels and operating on standard mode up to 100 kbits/s and fast + mode up to 400 kbits/s. if SYS_I2C_MXC config SYS_I2C_MXC_I2C1 @@ -363,7 +363,7 @@ config SYS_I2C_ROCKCHIP help Add support for the Rockchip I2C driver. This is used with various Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips - have several I2C ports and all are provided, controled by the + have several I2C ports and all are provided, controlled by the device tree. config SYS_I2C_SANDBOX -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 06/10] drivers: Kconfig: spelling fixes
Signed-off-by: Chris Packham --- drivers/core/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 046b87a33375..ddf2fb3fb828 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -232,7 +232,7 @@ config OF_ISA_BUS Is this option is enabled then support for the ISA bus will be included for addresses read from DT. This is something that should be known to be required or not based upon the board - being targetted, and whether or not it makes use of an ISA bus. + being targeted, and whether or not it makes use of an ISA bus. The bus is matched based upon its node name equalling "isa". The busses #address-cells should equal 2, with the first cell being -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 09/10] video: Kconfig: spelling fixes
Signed-off-by: Chris Packham --- drivers/video/rockchip/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig index b1d7c62fcade..10182d0b66c6 100644 --- a/drivers/video/rockchip/Kconfig +++ b/drivers/video/rockchip/Kconfig @@ -65,6 +65,6 @@ config DISPLAY_ROCKCHIP_MIPI help This enables Mobile Industry Processor Interface(MIPI) display support. The mipi controller and dphy on rk3288& rk3399 support - 16,18, 24 bits per pixel with upto 2k resolution ratio. + 16,18, 24 bits per pixel with up to 2k resolution ratio. endif -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 03/10] arm: Kconfig: spelling fixes
Signed-off-by: Chris Packham --- arch/arm/mach-bcm283x/Kconfig | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index 821caedbf7a7..3eb5a9a897b1 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -41,7 +41,7 @@ config TARGET_RPI support BCM2836/BCM2837-based Raspberry Pis such as the RPi 2 and RPi 3 due to different peripheral address maps. - This option creates a build targetting the ARM1176 ISA. + This option creates a build targeting the ARM1176 ISA. select BCM2835 config TARGET_RPI_0_W @@ -57,7 +57,7 @@ config TARGET_RPI_0_W This is required for U-Boot to operate correctly, even if you only care about the HDMI/usbkbd console. - This option creates a build targetting the ARMv7/AArch32 ISA. + This option creates a build targeting the ARMv7/AArch32 ISA. select BCM2835 config TARGET_RPI_2 @@ -80,7 +80,7 @@ config TARGET_RPI_2 arm_loader: emmc clock depends on core clock See: https://github.com/raspberrypi/firmware/issues/572;. - This option creates a build targetting the ARMv7/AArch32 ISA. + This option creates a build targeting the ARMv7/AArch32 ISA. select BCM2836 config TARGET_RPI_3_32B @@ -96,7 +96,7 @@ config TARGET_RPI_3_32B required for U-Boot to operate correctly, even if you only care about the HDMI/usbkbd console. - This option creates a build targetting the ARMv7/AArch32 ISA. + This option creates a build targeting the ARMv7/AArch32 ISA. select BCM2837_32B config TARGET_RPI_3 @@ -124,7 +124,7 @@ config TARGET_RPI_3 duplicated here. The VC FW enhancement is tracked in https://github.com/raspberrypi/firmware/issues/579. - This option creates a build targetting the ARMv8/AArch64 ISA. + This option creates a build targeting the ARMv8/AArch64 ISA. select BCM2837_64B endchoice -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 05/10] work_92105: Kconfig: spelling fixes
Signed-off-by: Chris Packham --- board/work-microwave/work_92105/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/work-microwave/work_92105/Kconfig b/board/work-microwave/work_92105/Kconfig index 32632f5ab529..380e2dfc2419 100644 --- a/board/work-microwave/work_92105/Kconfig +++ b/board/work-microwave/work_92105/Kconfig @@ -10,7 +10,7 @@ config SYS_CONFIG_NAME default "work_92105" config CMD_HD44760 - bool "Enable 'hd44780' LCD-control comand" + bool "Enable 'hd44780' LCD-control command" help This controls the LCD driver. -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 02/10] common: spl: Kconfig: spelling fixes
Signed-off-by: Chris Packham --- common/spl/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 35472f4a921c..4fbd7fbd8a3a 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -608,7 +608,7 @@ config SPL_PAYLOAD default "tpl/u-boot-with-tpl.bin" if TPL default "u-boot.bin" help - Payload for SPL boot. For backward compability, default to + Payload for SPL boot. For backward compatibility, default to u-boot.bin, i.e. RAW image without any header. In case of TPL, tpl/u-boot-with-tpl.bin. For new boards, suggest to use u-boot.img. -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 01/10] Kconfig: fix spelling
Signed-off-by: Chris Packham --- Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Kconfig b/Kconfig index aff7b2e00a05..a078f7b1b667 100644 --- a/Kconfig +++ b/Kconfig @@ -213,7 +213,7 @@ config PHYS_64BIT help Say Y here to support 64bit physical memory address. This can be used not only for 64bit SoCs, but also for - large physical address extention on 32bit SoCs. + large physical address extension on 32bit SoCs. config BUILD_ROM bool "Build U-Boot as BIOS replacement" -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
