[U-Boot] [PATCH v1 2/3] pci: pci.h: add missing maskbit
PCI_MSI_FLAGS_MASKBIT was missing from include file, add it. Signed-off-by: Ramon Fried --- include/pci.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/pci.h b/include/pci.h index 5fb212cab1..508f7bca81 100644 --- a/include/pci.h +++ b/include/pci.h @@ -405,6 +405,7 @@ #define PCI_MSI_FLAGS_QSIZE 0x70/* Message queue size configured */ #define PCI_MSI_FLAGS_QMASK 0x0e/* Maximum queue size available */ #define PCI_MSI_FLAGS_ENABLE 0x01/* MSI feature enabled */ +#define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */ #define PCI_MSI_RFU3 /* Rest of capability flags */ #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 1/3] drivers: pci_ep: Introduce UCLASS_PCI_EP uclass
Introduce new UCLASS_PCI_EP class for handling PCI endpoint
devices, allowing to set various attributes of the PCI endpoint
device, such as:
* configuration space header
* BAR definitions
* outband memory mapping
* start/stop PCI link
Signed-off-by: Ramon Fried
---
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/pci_endpoint/Kconfig | 16 ++
drivers/pci_endpoint/Makefile| 6 +
drivers/pci_endpoint/pci_ep-uclass.c | 192 ++
include/dm/uclass-id.h | 1 +
include/pci_ep.h | 375 +++
7 files changed, 593 insertions(+)
create mode 100644 drivers/pci_endpoint/Kconfig
create mode 100644 drivers/pci_endpoint/Makefile
create mode 100644 drivers/pci_endpoint/pci_ep-uclass.c
create mode 100644 include/pci_ep.h
diff --git a/drivers/Kconfig b/drivers/Kconfig
index f24351ac4f..59e2c22cc6 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -64,6 +64,8 @@ source "drivers/nvme/Kconfig"
source "drivers/pci/Kconfig"
+source "drivers/pci_endpoint/Kconfig"
+
source "drivers/pch/Kconfig"
source "drivers/pcmcia/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index a7bba3ed56..480b97ef58 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -85,6 +85,7 @@ obj-$(CONFIG_FPGA) += fpga/
obj-y += misc/
obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_NVME) += nvme/
+obj-$(CONFIG_PCI_ENDPOINT) += pci_endpoint/
obj-y += pcmcia/
obj-y += dfu/
obj-$(CONFIG_PCH) += pch/
diff --git a/drivers/pci_endpoint/Kconfig b/drivers/pci_endpoint/Kconfig
new file mode 100644
index 00..2c0a399a08
--- /dev/null
+++ b/drivers/pci_endpoint/Kconfig
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# PCI Endpoint Support
+#
+
+menu "PCI Endpoint"
+
+config PCI_ENDPOINT
+ bool "PCI Endpoint Support"
+ depends on DM
+ help
+ Enable this configuration option to support configurable PCI
+ endpoint. This should be enabled if the platform has a PCI
+ controller that can operate in endpoint mode.
+
+endmenu
diff --git a/drivers/pci_endpoint/Makefile b/drivers/pci_endpoint/Makefile
new file mode 100644
index 00..80a1066925
--- /dev/null
+++ b/drivers/pci_endpoint/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019
+# Ramon Fried
+
+obj-y += pci_ep-uclass.o
diff --git a/drivers/pci_endpoint/pci_ep-uclass.c
b/drivers/pci_endpoint/pci_ep-uclass.c
new file mode 100644
index 00..06fcfc5d14
--- /dev/null
+++ b/drivers/pci_endpoint/pci_ep-uclass.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PCI Endpoint uclass
+ *
+ * Based on Linux PCI-EP driver written by
+ * Kishon Vijay Abraham I
+ *
+ * Copyright (c) 2019
+ * Written by Ramon Fried
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dm_pci_ep_write_header(struct udevice *dev, u8 fn,
+ struct pci_ep_header *hdr)
+{
+ struct dm_pci_ep_ops *ops = pci_ep_get_ops(dev);
+
+ if (!ops->write_header)
+ return -ENODEV;
+
+ return ops->write_header(dev, fn, hdr);
+}
+
+int dm_pci_ep_read_header(struct udevice *dev, u8 fn,
+ struct pci_ep_header *hdr)
+{
+ struct dm_pci_ep_ops *ops = pci_ep_get_ops(dev);
+
+ if (!ops->read_header)
+ return -ENODEV;
+
+ return ops->read_header(dev, fn, hdr);
+}
+
+int dm_pci_ep_set_bar(struct udevice *dev, u8 func_no,
+ struct pci_bar *ep_bar)
+{
+ struct dm_pci_ep_ops *ops = pci_ep_get_ops(dev);
+ int flags = ep_bar->flags;
+
+ /* Some basic bar validity checks */
+ if ((ep_bar->barno == BAR_5 && flags &
+PCI_BASE_ADDRESS_MEM_TYPE_64) ||
+ (flags & PCI_BASE_ADDRESS_SPACE_IO &&
+flags & PCI_BASE_ADDRESS_IO_MASK) ||
+ (upper_32_bits(ep_bar->size) &&
+!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)))
+ return -EINVAL;
+
+ if (!ops->set_bar)
+ return -ENODEV;
+
+ return ops->set_bar(dev, func_no, ep_bar);
+}
+
+void pci_ep_clear_bar(struct udevice *dev, u8 func_num, enum pci_barno bar)
+{
+ struct dm_pci_ep_ops *ops = pci_ep_get_ops(dev);
+
+ if (!ops->clear_bar)
+ return;
+
+ ops->clear_bar(dev, func_num, bar);
+}
+
+int dm_pci_ep_map_addr(struct udevice *dev, u8 func_no, phys_addr_t addr,
+ u64 pci_addr, size_t size)
+{
+ struct dm_pci_ep_ops *ops = pci_ep_get_ops(dev);
+
+ if (!ops->map_addr)
+ return -ENODEV;
+
+ return ops->map_addr(dev, func_no, addr, pci_addr, size);
+}
+
+void dm_pci_ep_unmap_addr(struct udevice *dev, u8 func_no, phys_addr_t addr)
+{
+ struct dm_pci_ep_ops *ops = pci_ep_get_ops(dev);
+
+ if (!ops->unmap_addr)
+ return;
+
+ ops->unmap_addr(dev, func_no, addr);
+}
+
+int
[U-Boot] [PATCH v1 3/3] pci_ep: add Cadence PCIe endpoint driver
Add Cadence PCIe endpoint driver supporting configuration
of header, bars and MSI for device.
Signed-off-by: Ramon Fried
---
.../pci_endpoint/cdns,cdns-pcie-ep.txt| 18 +
drivers/pci_endpoint/Kconfig | 9 +
drivers/pci_endpoint/Makefile | 1 +
drivers/pci_endpoint/pcie-cadence-ep.c| 177 ++
drivers/pci_endpoint/pcie-cadence.h | 309 ++
5 files changed, 514 insertions(+)
create mode 100644 doc/device-tree-bindings/pci_endpoint/cdns,cdns-pcie-ep.txt
create mode 100644 drivers/pci_endpoint/pcie-cadence-ep.c
create mode 100644 drivers/pci_endpoint/pcie-cadence.h
diff --git a/doc/device-tree-bindings/pci_endpoint/cdns,cdns-pcie-ep.txt
b/doc/device-tree-bindings/pci_endpoint/cdns,cdns-pcie-ep.txt
new file mode 100644
index 00..7705430559
--- /dev/null
+++ b/doc/device-tree-bindings/pci_endpoint/cdns,cdns-pcie-ep.txt
@@ -0,0 +1,18 @@
+* Cadence PCIe endpoint controller
+
+Required properties:
+- compatible: Should contain "cdns,cdns-pcie-ep" to identify the IP used.
+- reg: Should contain the controller register base address.
+
+Optional properties:
+- max-functions: Maximum number of functions that can be configured (default
1).
+- cdns,max-outbound-regions: Set to maximum number of outbound regions
(default 8)
+
+Example:
+
+pcie_ep@fc00 {
+ compatible = "cdns,cdns-pcie-ep";
+ reg = <0x0 0xfc00 0x0 0x0100>;
+ cdns,max-outbound-regions = <16>;
+ max-functions = /bits/ 8 <8>;
+};
diff --git a/drivers/pci_endpoint/Kconfig b/drivers/pci_endpoint/Kconfig
index 2c0a399a08..d4cf4227df 100644
--- a/drivers/pci_endpoint/Kconfig
+++ b/drivers/pci_endpoint/Kconfig
@@ -13,4 +13,13 @@ config PCI_ENDPOINT
endpoint. This should be enabled if the platform has a PCI
controller that can operate in endpoint mode.
+config PCIE_CADENCE_EP
+ bool "Cadence PCIe endpoint controller"
+ depends on OF
+ depends on PCI_ENDPOINT
+ help
+ Say Y here if you want to support the Cadence PCIe controller in
+ endpoint mode. This PCIe controller may be embedded into many
+ different vendors SoCs.
+
endmenu
diff --git a/drivers/pci_endpoint/Makefile b/drivers/pci_endpoint/Makefile
index 80a1066925..0a849deb19 100644
--- a/drivers/pci_endpoint/Makefile
+++ b/drivers/pci_endpoint/Makefile
@@ -4,3 +4,4 @@
# Ramon Fried
obj-y += pci_ep-uclass.o
+obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o
diff --git a/drivers/pci_endpoint/pcie-cadence-ep.c
b/drivers/pci_endpoint/pcie-cadence-ep.c
new file mode 100644
index 00..2b669c3c7a
--- /dev/null
+++ b/drivers/pci_endpoint/pcie-cadence-ep.c
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019
+ * Written by Ramon Fried
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include "pcie-cadence.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int cdns_write_header(struct udevice *dev, u8 fn,
+struct pci_ep_header *hdr)
+{
+ struct cdns_pcie *pcie = dev_get_priv(dev);
+
+ cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
+ cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
+ cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG,
+ hdr->progif_code);
+ cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE,
+ hdr->subclass_code |
+ hdr->baseclass_code << 8);
+ cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
+ hdr->cache_line_size);
+ cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID,
+ hdr->subsys_id);
+ cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN,
+ hdr->interrupt_pin);
+
+ /*
+* Vendor ID can only be modified from function 0, all other functions
+* use the same vendor ID as function 0.
+*/
+ if (fn == 0) {
+ /* Update the vendor IDs. */
+ u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) |
+CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id);
+
+ cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
+ }
+
+ return 0;
+}
+
+static int cdns_set_bar(struct udevice *dev, u8 fn, struct pci_bar *ep_bar)
+{
+ struct cdns_pcie *pcie = dev_get_priv(dev);
+ dma_addr_t bar_phys = ep_bar->phys_addr;
+ enum pci_barno bar = ep_bar->barno;
+ int flags = ep_bar->flags;
+ u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
+ u64 sz;
+
+ /* BAR size is 2^(aperture + 7) */
+ sz = max_t(size_t, ep_bar->size, CDNS_PCIE_EP_MIN_APERTURE);
+ /*
+* roundup_pow_of_two() returns an unsigned long, which is not suited
+* for 64bit values.
+*/
+ sz = 1ULL << fls64(sz - 1);
+ aperture = ilog2(sz) - 7; /* 128B -> 0,
[U-Boot] [PATCH v1 0/3] Add Cadence PCIe endpoint driver with new uclass
This patchset adds support for new uclass, UCLASS_PCI_EP allowing new set of PCI endpoint drivers. Included in the patchset is also a driver for Cadence PCIe endpoint. Ramon Fried (3): drivers: pci_ep: Introduce UCLASS_PCI_EP uclass pci: pci.h: add missing maskbit pci_ep: add Cadence PCIe endpoint driver .../pci_endpoint/cdns,cdns-pcie-ep.txt| 18 + drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/pci_endpoint/Kconfig | 25 ++ drivers/pci_endpoint/Makefile | 7 + drivers/pci_endpoint/pci_ep-uclass.c | 192 + drivers/pci_endpoint/pcie-cadence-ep.c| 177 + drivers/pci_endpoint/pcie-cadence.h | 309 +++ include/dm/uclass-id.h| 1 + include/pci.h | 1 + include/pci_ep.h | 375 ++ 11 files changed, 1108 insertions(+) create mode 100644 doc/device-tree-bindings/pci_endpoint/cdns,cdns-pcie-ep.txt create mode 100644 drivers/pci_endpoint/Kconfig create mode 100644 drivers/pci_endpoint/Makefile create mode 100644 drivers/pci_endpoint/pci_ep-uclass.c create mode 100644 drivers/pci_endpoint/pcie-cadence-ep.c create mode 100644 drivers/pci_endpoint/pcie-cadence.h create mode 100644 include/pci_ep.h -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 28/40] x86: Add a sysreset driver for the Intel PCH
Hi Bin, On Wed, 3 Apr 2019 at 02:42, Bin Meng wrote: > > Hi Simon, > > On Wed, Apr 3, 2019 at 10:22 AM Simon Glass wrote: > > > > Hi Bin, > > > > On Fri, 22 Feb 2019 at 00:20, Bin Meng wrote: > > > > > > Hi Simon, > > > > > > On Wed, Jan 30, 2019 at 12:00 PM Simon Glass wrote: > > > > > > > > Intel SoCs support a fairly stardard reset mechanism which can support > > > > powering off the device. Add support for this and enable it by default > > > > on > > > > broadwell, which already has the necessary pm.h header file. > > > > > > > > This driver augments the standard x86 sysreset driver. > > > > > > > > > > I think we need update the existing sysreset_x86 driver to support > > > SYSRESET_POWER_OFF, instead of creating a new driver to do such. > > > > > > We can add a new PCH ioctl code to get the pmbase, and do the ACPI > > > power off in the sysreset_x86 driver. > > > > So are you saying that the registers are the same for all x86 chips? > > From what I can tell, the offsets vary. > > Yes, the offsets might be different, so instead of getting only the > pmbase, we need do something like getting ACPI PM register block > information from the PCH driver. That's how acpi_create_fadt() passes > ACPI register block information to the OS. That doesn't make a lot of sense to me. If the register layout is different, why not just use different drivers? I suppose we could put the common code (with parameters) in a separate file and call it from the driver. The parameters would presumably be: PMBASE GPE0_EN(0) PM1_STS PM1_CNT Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] cmd: add wdt command
Add a command to control the watchdog devices. This is useful if the
watchdog is rather long running (eg. seconds) and it should be
controlled by scripts. It is also handy during debugging.
Signed-off-by: Michael Walle
---
cmd/Kconfig | 6 +++
cmd/Makefile | 1 +
cmd/wdt.c| 174 +++
3 files changed, 181 insertions(+)
create mode 100644 cmd/wdt.c
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 0b07b3b9d7..2bdbfcb3d0 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1101,6 +1101,12 @@ config CMD_VIRTIO
help
VirtIO block device support
+config CMD_WDT
+ bool "wdt"
+ depends on WDT
+ help
+ This provides commands to control the watchdog timer devices.
+
config CMD_AXI
bool "axi"
depends on AXI
diff --git a/cmd/Makefile b/cmd/Makefile
index acb85f49fb..6b1c6b094e 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -142,6 +142,7 @@ obj-$(CONFIG_CMD_UBIFS) += ubifs.o
obj-$(CONFIG_CMD_UNIVERSE) += universe.o
obj-$(CONFIG_CMD_UNZIP) += unzip.o
obj-$(CONFIG_CMD_VIRTIO) += virtio.o
+obj-$(CONFIG_CMD_WDT) += wdt.o
obj-$(CONFIG_CMD_LZMADEC) += lzmadec.o
obj-$(CONFIG_CMD_USB) += usb.o disk.o
diff --git a/cmd/wdt.c b/cmd/wdt.c
new file mode 100644
index 00..647d9899b4
--- /dev/null
+++ b/cmd/wdt.c
@@ -0,0 +1,174 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Watchdog commands
+ *
+ * Copyright (c) 2019 Michael Walle
+ */
+
+#include
+#include
+#include
+#include
+
+static struct udevice *currdev;
+
+static int do_wdt_list(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret;
+
+ ret = uclass_get(UCLASS_WDT, );
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ uclass_foreach_dev(dev, uc)
+ printf("%s (%s)\n", dev->name, dev->driver->name);
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_wdt_dev(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int ret;
+
+ if (argc > 1) {
+ ret = uclass_get_device_by_name(UCLASS_WDT, argv[1], );
+ if (ret) {
+ printf("Can't get the watchdog timer: %s\n", argv[1]);
+ return CMD_RET_FAILURE;
+ }
+ } else {
+ if (!currdev) {
+ printf("No watchdog timer device set!\n");
+ return CMD_RET_FAILURE;
+ }
+ printf("dev: %s\n", currdev->name);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int check_currdev(void)
+{
+ if (!currdev) {
+ printf("No device set, use 'wdt dev' first\n");
+ return CMD_RET_FAILURE;
+ }
+ return 0;
+}
+
+static int do_wdt_start(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int ret;
+ u64 timeout;
+ ulong flags = 0;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ ret = check_currdev();
+ if (ret)
+ return ret;
+
+ timeout = simple_strtoull(argv[1], NULL, 0);
+ if (argc > 2)
+ flags = simple_strtoul(argv[2], NULL, 0);
+
+ ret = wdt_start(currdev, timeout, flags);
+ if (ret == -ENOSYS) {
+ printf("Starting watchdog timer not supported.\n");
+ return CMD_RET_FAILURE;
+ } else if (ret) {
+ printf("Starting watchdog timer failed (%d)\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_wdt_stop(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int ret;
+
+ ret = check_currdev();
+ if (ret)
+ return ret;
+
+ ret = wdt_stop(currdev);
+ if (ret == -ENOSYS) {
+ printf("Stopping watchdog timer not supported.\n");
+ return CMD_RET_FAILURE;
+ } else if (ret) {
+ printf("Stopping watchdog timer failed (%d)\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_wdt_reset(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int ret;
+
+ ret = check_currdev();
+ if (ret)
+ return ret;
+
+ ret = wdt_reset(currdev);
+ if (ret == -ENOSYS) {
+ printf("Resetting watchdog timer not supported.\n");
+ return CMD_RET_FAILURE;
+ } else if (ret) {
+ printf("Resetting watchdog timer failed (%d)\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_wdt_expire(cmd_tbl_t *cmdtp, int flag, int argc,
+char *const argv[])
+{
+ int ret;
+ ulong flags = 0;
+
+ ret = check_currdev();
+ if
[U-Boot] [sunxi/sun7i] ARMv7 SVC mode: PSCI not loaded and only 1st CPU core gets activated
Hi, when building u-boot for ARMv7 with these settings for SVC mode (ie. "Secure Mode"), instead of HYPervisor mode: ARM architecture ---> ... [*] Enable support for booting in non-secure mode [*] Boot in secure mode by default [ ] Enable support for hardware virtualization [*] Enable PSCI support (2) Maximum supported CPUs for PSCI [ ] Use LPAE page table format ... then only the first CPU core gets activated. How to bring the other core(s) online? I tried this from https://www.kernel.org/doc/html/v5.0/core-api/cpu_hotplug.html : # echo 1 > /sys/devices/system/cpu/cpu1/online bash: /sys/devices/system/cpu/cpu1/online: Permission denied (actually there is no "online" entry under cpu1, but also not under cpu0. Attached is the tree under /sys/devices/system/cpu/ ) # # Automatically generated file; DO NOT EDIT. # U-Boot 2019.04-rc4 Configuration ... CONFIG_SYS_ARCH="arm" CONFIG_SYS_CPU="armv7" CONFIG_SYS_SOC="sunxi" CONFIG_SYS_BOARD="sunxi" CONFIG_SYS_CONFIG_NAME="sun7i" ... CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1" ... # uname -a Linux r1-3 5.0.5 #1 SMP Sat Mar 30 05:34:40 CET 2019 armv7l GNU/Linux kernel conf has CONFIG_HOTPLUG_CPU=y # dmesg | grep -i "smp\|psci\|started in" [0.00] Linux version 5.0.5 (u-ps@c22-local) (gcc version 9.0.1 20190326 (experimental) [trunk revision 269955] (GCC)) #1 SMP Sat Mar 30 05:34:40 CET 2019 [0.004154] smp: Bringing up secondary CPUs ... [0.004753] smp: Brought up 1 node, 1 CPU [0.004766] SMP: Total of 1 processors activated (48.00 BogoMIPS). [0.004772] CPU: All CPU(s) started in SVC mode. (ie. this means that PSCI is not loaded b/c otherwise there would be some "psci" lines in the log) # lscpu Architecture: armv7l Byte Order:Little Endian CPU(s):2 On-line CPU(s) list: 0 Off-line CPU(s) list: 1 Thread(s) per core:1 Core(s) per socket:1 Socket(s): 1 Model name:ARMv7 Processor rev 4 (v7l) CPU max MHz: 960. CPU min MHz: 144. See also: - http://linux-sunxi.org/PSCI https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/psci.txt According to this page https://falstaff.agner.ch/2016/07/03/u-bootlinux-and-hyp-mode-on-armv7/ it seems in older u-boot versions it did activate all CPUs in SVC mode: " Brought up 2 CPUs SMP: Total of 2 processors activated (96.00 BogoMIPS). CPU: All CPU(s) started in SVC mode. " /sys/devices/system/cpu/ ├── cpu0 │ ├── cpu_capacity │ ├── cpufreq -> ../cpufreq/policy0 │ ├── hotplug │ │ ├── fail │ │ ├── state │ │ └── target │ ├── of_node -> ../../../../firmware/devicetree/base/cpus/cpu@0 │ ├── power │ │ ├── autosuspend_delay_ms │ │ ├── control │ │ ├── pm_qos_resume_latency_us │ │ ├── runtime_active_time │ │ ├── runtime_status │ │ └── runtime_suspended_time │ ├── subsystem -> ../../../../bus/cpu │ ├── topology │ │ ├── core_id │ │ ├── core_siblings │ │ ├── core_siblings_list │ │ ├── physical_package_id │ │ ├── thread_siblings │ │ └── thread_siblings_list │ └── uevent ├── cpu1 │ ├── cpu_capacity │ ├── cpufreq -> ../cpufreq/policy0 │ ├── hotplug │ │ ├── fail │ │ ├── state │ │ └── target │ ├── of_node -> ../../../../firmware/devicetree/base/cpus/cpu@1 │ ├── power │ │ ├── autosuspend_delay_ms │ │ ├── control │ │ ├── pm_qos_resume_latency_us │ │ ├── runtime_active_time │ │ ├── runtime_status │ │ └── runtime_suspended_time │ ├── subsystem -> ../../../../bus/cpu │ └── uevent ├── cpufreq │ ├── policy0 │ │ ├── affected_cpus │ │ ├── cpuinfo_cur_freq │ │ ├── cpuinfo_max_freq │ │ ├── cpuinfo_min_freq │ │ ├── cpuinfo_transition_latency │ │ ├── related_cpus │ │ ├── scaling_available_frequencies │ │ ├── scaling_available_governors │ │ ├── scaling_cur_freq │ │ ├── scaling_driver │ │ ├── scaling_governor │ │ ├── scaling_max_freq │ │ ├── scaling_min_freq │ │ ├── scaling_setspeed │ │ └── stats │ │ ├── reset │ │ ├── time_in_state │ │ ├── total_trans │ │ └── trans_table │ └── schedutil │ └── rate_limit_us ├── cpuidle │ ├── current_driver │ └── current_governor_ro ├── hotplug │ └── states ├── isolated ├── kernel_max ├── modalias ├── offline ├── online ├── possible ├── power │ ├── autosuspend_delay_ms │ ├── control │ ├── runtime_active_time │ ├── runtime_status │ └── runtime_suspended_time ├── present └── uevent 20 directories, 63 files ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] i2c: muxes: pca954x: update list of supported devices
Hi Michal, On 05/04/19 12:58, Michal Simek wrote: > On 05. 04. 19 12:32, Luca Ceresoli wrote: >> The Kconfig help has not been updated while adding PCA9547 and PCA9646. >> >> Signed-off-by: Luca Ceresoli >> --- >> drivers/i2c/muxes/Kconfig | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig >> index b0da67ce2c6b..26be78f685de 100644 >> --- a/drivers/i2c/muxes/Kconfig >> +++ b/drivers/i2c/muxes/Kconfig >> @@ -33,7 +33,7 @@ config I2C_MUX_PCA954x >>I2C mux/switch devices. It is x width I2C multiplexer which enables to >>partitioning I2C bus and connect multiple devices with the same >> address >>to the same I2C controller where driver handles proper routing to >> - target i2c device. PCA9544 and PCA9548 are supported. >> + target i2c device. PCA9544, PCA9547 PCA9548 and PCA9646 are supported. > > missing comma there. Thank you for your very prompt reviews. I'll wait a few more days in case of more comments and then resend with the fixes you suggested. -- Luca ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] rk3288 SPL size
Wadim, > On 05.04.2019, at 12:10, Wadim Egorov wrote: > > Hi, > > it seems the new common rockchip pinctrl driver does not really fit into > our phycore-rk3288 SPL setup. It works for every other rk3288 based > board because they don't need special power configurations at the SPL stage. I recommend to implement a simple-pinctrl for SPL, which is similar to what we’ve done for the RK3399 (not on the list yet, as it’s collocated with a bigger rework of the DMC initialisation that reads some data from an I2C EEPROM). As you’ll probably need to do this initialisation even at the TPL stage (if you use one on the RK3288), then the simple pinctrl will need to be available at TPL. Thanks, Phiilipp. > So my question is: is there any work going on to reduce the SPL size > even more? > > Besides that, I think I can remove the power stuff at the SPL stage from > our board. The SOM was redesigned and is equipped with an STM8 connected > to the RK818. The required setup we did before in the SPL is now done by > the ST controller. I know there are only a few SOMs without the STM8 out > in the wild. So if I remove it it will affect only a few people who > probably already have both boards. > > Regards, > Wadim > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] crypto: fsl: jr: Make job-rings assignment non-Secure dependent
Commit 22191ac35344 ("drivers/crypto/fsl: assign job-rings to
non-TrustZone") breaks HABv4 encrypted boot support in the
following i.MX devices:
- i.MX6UL
- i.MX7S
- i.MX7D
- i.MX7ULP
For preparing a HABv4 encrypted boot image it's necessary to
encapsulate the generated DEK in a blob. In devices listed
above the blob generation function takes into consideration
the Job Ring TrustZone ownership configuration (JROWN_NS)
and can be only decapsulated by the same configuration.
The ROM code expects DEK blobs encapsulated by the Secure World
environments which commonly have JROWN_NS = 0.
As U-Boot is running in Secure World we must have JROWN_NS = 0
so the blobs generated by dek_blob tool can be decapsulated
by the ROM code.
Linux Kernel is booting by default in TrustZone Secure World in
most of targets. Make job-rings assignment to non-Secure dependent
of CONFIG_OPTEE and CONFIG_ARMV7_BOOT_SEC_DEFAULT to avoid a Kernel
crash when booting Linux in non-Secure World.
OP-TEE users can still use dek_blob command as job ring assignment
is also dependent of CONFIG_CMD_DEKBLOB configuration.
Signed-off-by: Breno Lima
---
drivers/crypto/fsl/jr.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index cc8d3b02a5..23d5a64da0 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -635,11 +635,15 @@ int sec_init_idx(uint8_t sec_idx)
#endif
#endif
- /* Set ownership of job rings to non-TrustZone mode by default */
- for (i = 0; i < ARRAY_SIZE(sec->jrliodnr); i++) {
- jrown_ns = sec_in32(>jrliodnr[i].ms);
- jrown_ns |= JROWN_NS | JRMID_NS;
- sec_out32(>jrliodnr[i].ms, jrown_ns);
+ if ((IS_ENABLED(CONFIG_OPTEE) ||
+!IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT)) &&
+!IS_ENABLED(CONFIG_CMD_DEKBLOB)) {
+ /* Set ownership of job rings to non-TrustZone mode. */
+ for (i = 0; i < ARRAY_SIZE(sec->jrliodnr); i++) {
+ jrown_ns = sec_in32(>jrliodnr[i].ms);
+ jrown_ns |= JROWN_NS | JRMID_NS;
+ sec_out32(>jrliodnr[i].ms, jrown_ns);
+ }
}
ret = jr_init(sec_idx);
--
2.17.1
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Re: [U-Boot] [PATCH] watchdog: Implement generic watchdog_reset() version
On 05. 04. 19 15:24, Stefan Roese wrote:
> On 05.04.19 15:00, Stefan Roese wrote:
>
>
>
+ debug("Only one watchdog device used!\n");
+ return;
+ }
+
+ /*
+ * Init watchdog: This will call the probe function of the
+ * watchdog driver, enabling the use of the device
+ */
+ if (uclass_get_device(UCLASS_WDT, 0,
+ (struct udevice **)>watchdog_dev)) {
+ debug("Watchdog: Not found!\n");
+ return;
+ }
>>>
>>> I think you should c what I have done in zynq/zynqmp. It means check
>>> watchdog0 alias first because this is supposed to be the first primary
>>> watchdog.
>>>
>>> zynq/zynqmp/mb code
>>> if (uclass_get_device_by_seq(UCLASS_WDT, 0, _dev)) {
>>> debug("Watchdog: Not found by seq!\n");
>>> if (uclass_get_device(UCLASS_WDT, 0, _dev)) {
>>> puts("Watchdog: Not found!\n");
>>> return 0;
>>> }
>>> }
>>
>> In my (internal) first version, I had exactly this code included. I
>> removed the first part, as it makes no real sense to call it at this
>> stage (wdt_post_bind() for the first WDT found in the system). My
>> understanding is, that wdt_post_bind() will get called for all WDT
>> found in the system. My current logic here is, to only register the
>> first WDT found to the global watchdog_dev in GD. To prevent that
>> multiple WDT are used to service the U-Boot watchdog via WATCHDOG_RESET.
>>
>> Or does the DM subsystem automatically bind the watchdog0 alias first
>> in its binding sequence?
>>
>> I do not have a system with multiple watchdogs here, so its not that
>> easy to test this. I could simulate this though somehow...
>
> I just did some testing on this. One solution might be, to only use
> uclass_get_device_by_seq() (instead of uclass_get_device) and return
> if the alias is not found. This way, all watchdog devices will get
> probed (bound) and only the one referenced by the alias will get used.
>
> This means on the other hand, that an watchdog0 alias is needed in the
> DT to enable the WATCHDOG_RESET U-Boot servicing, which might be not
> backward compatible.
>
> Do you have any other thought on this?
As you see above this is what I used and strictly speaking using
different logic will break compatibility for xilinx platforms.
I forget details about logic seq/req_seq but maybe watchdog core should
adopt dev_read_alias_highest_id() which I added for i2c some time ago.
For example if you have two watchdogs and only one alias.
aliases {
watchdog1 =
}
wdt2: {};
wdt1: {};
Which one should be used by u-boot?
wdt1 because it has alias?
or wdt2 because it is listed first?
or none because there is no watchdog0 alias?
Maybe even solution with taking first alias is wrong and xlnx,watchdog
property in chosen node is a reasonable solution.
Thanks,
Michal
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Re: [U-Boot] [PATCH] watchdog: Implement generic watchdog_reset() version
On 05. 04. 19 17:23, Stefan Roese wrote:
> On 05.04.19 17:18, Michal Simek wrote:
>> On 05. 04. 19 15:00, Stefan Roese wrote:
>>> Hi Michal,
>>>
>>> On 05.04.19 14:07, Michal Simek wrote:
>>>
>>>
>>>
> +++ b/drivers/watchdog/wdt-uclass.c
> @@ -10,6 +10,12 @@
> #include
> #include
> +#ifndef WDT_DEFAULT_TIMEOUT
> +#define WDT_DEFAULT_TIMEOUT 60
> +#endif
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> int wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
> {
> const struct wdt_ops *ops = device_get_ops(dev);
> @@ -63,6 +69,67 @@ int wdt_expire_now(struct udevice *dev, ulong
> flags)
> return ret;
> }
> +#if defined(CONFIG_WATCHDOG)
This is not enough because you can enable it just for full u-boot but
not for SPL.
>>>
>>> Why not? CONFIG_WATCHDOG can be enabled with or without
>>> CONFIG_SPL_WATCHDOG_SUPPORT being enabled.
>>>
It means you should also handle CONFIG_SPL_WATCHDOG_SUPPORT
macros.
Just try to enable CADENCE_WDT, WDT and Watchdog for zcu100 and build
>>>
>>> I just tried this for xilinx_zynqmp_zcu100_revC_defconfig. Per default
>>> it has enabled:
>>
>> ah right. I have patch in my queue to disable it by default.
>>
>> Anyway this is what I am getting.
>>
>> [u-boot](mainline)$ git log -n 3 --oneline
>> 672eafbf08a0 watchdog: Implement generic watchdog_reset() version
>> 7b5b40e4858b watchdog: Move watchdog_dev to data section (BSS may not be
>> cleared)
>> 0e708abcbba1 Merge branch 'master' of git://git.denx.de/u-boot-usb
>> [u-boot](mainline)$ make xilinx_zynqmp_zcu100_revC_defconfig >/dev/null
>> && make -j >/dev/null
>> lib/built-in.o: In function `inflateReset':
>> /mnt/disk/u-boot/lib/zlib/inflate.c:28: undefined reference to
>> `watchdog_reset'
>> /mnt/disk/u-boot/lib/zlib/inflate.c:28:(.text.inflateReset+0x58):
>> relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
>> `watchdog_reset'
>> lib/built-in.o: In function `inflateEnd':
>> /mnt/disk/u-boot/lib/zlib/inflate.c:936: undefined reference to
>> `watchdog_reset'
>> /mnt/disk/u-boot/lib/zlib/inflate.c:936:(.text.inflateEnd+0x2c):
>> relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
>> `watchdog_reset'
>> lib/built-in.o: In function `inflate':
>> /mnt/disk/u-boot/lib/zlib/inflate.c:546: undefined reference to
>> `watchdog_reset'
>> /mnt/disk/u-boot/lib/zlib/inflate.c:546:(.text.inflate+0x7b4):
>> relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
>> `watchdog_reset'
>> /mnt/disk/u-boot/lib/zlib/inflate.c:724: undefined reference to
>> `watchdog_reset'
>> /mnt/disk/u-boot/lib/zlib/inflate.c:724:(.text.inflate+0xcc4):
>> relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
>> `watchdog_reset'
>> lib/built-in.o: In function `udelay':
>> /mnt/disk/u-boot/lib/time.c:167: undefined reference to `watchdog_reset'
>> /mnt/disk/u-boot/lib/time.c:167:(.text.udelay+0x1c): relocation
>> truncated to fit: R_AARCH64_CALL26 against undefined symbol
>> `watchdog_reset'
>> drivers/built-in.o:/mnt/disk/u-boot/drivers/serial/serial_zynq.c:230:
>> more undefined references to `watchdog_reset' follow
>> drivers/built-in.o: In function `_debug_uart_putc':
>> /mnt/disk/u-boot/drivers/serial/serial_zynq.c:230:(.text.printch+0x4c):
>> relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
>> `watchdog_reset'
>> /mnt/disk/u-boot/drivers/serial/serial_zynq.c:230:(.text.printch+0x54):
>> relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
>> `watchdog_reset'
>> /mnt/disk/u-boot/drivers/serial/serial_zynq.c:230:(.text.printascii+0x58):
>>
>> relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
>> `watchdog_reset'
>> /mnt/disk/u-boot/drivers/serial/serial_zynq.c:230:(.text.printascii+0x60):
>>
>> relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
>> `watchdog_reset'
>> make[1]: *** [spl/u-boot-spl] Error 1
>> make: *** [spl/u-boot-spl] Error 2
>
> Yes. You're probably missing this patch here, which I listed as
> dependencies in the commit text:
>
> [2] watchdog: Handle SPL build with watchdog disabled
> https://patchwork.ozlabs.org/patch/1074098/
>
> Please test again with this patch applied.
Good catch. I didn't read it fully. Thought that only that first one you
sent recently is that dependency.
M
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Re: [U-Boot] [PATCH] watchdog: Implement generic watchdog_reset() version
On 05.04.19 17:18, Michal Simek wrote:
On 05. 04. 19 15:00, Stefan Roese wrote:
Hi Michal,
On 05.04.19 14:07, Michal Simek wrote:
+++ b/drivers/watchdog/wdt-uclass.c
@@ -10,6 +10,12 @@
#include
#include
+#ifndef WDT_DEFAULT_TIMEOUT
+#define WDT_DEFAULT_TIMEOUT 60
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
int wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
{
const struct wdt_ops *ops = device_get_ops(dev);
@@ -63,6 +69,67 @@ int wdt_expire_now(struct udevice *dev, ulong flags)
return ret;
}
+#if defined(CONFIG_WATCHDOG)
This is not enough because you can enable it just for full u-boot but
not for SPL.
Why not? CONFIG_WATCHDOG can be enabled with or without
CONFIG_SPL_WATCHDOG_SUPPORT being enabled.
It means you should also handle CONFIG_SPL_WATCHDOG_SUPPORT
macros.
Just try to enable CADENCE_WDT, WDT and Watchdog for zcu100 and build
I just tried this for xilinx_zynqmp_zcu100_revC_defconfig. Per default
it has enabled:
ah right. I have patch in my queue to disable it by default.
Anyway this is what I am getting.
[u-boot](mainline)$ git log -n 3 --oneline
672eafbf08a0 watchdog: Implement generic watchdog_reset() version
7b5b40e4858b watchdog: Move watchdog_dev to data section (BSS may not be
cleared)
0e708abcbba1 Merge branch 'master' of git://git.denx.de/u-boot-usb
[u-boot](mainline)$ make xilinx_zynqmp_zcu100_revC_defconfig >/dev/null
&& make -j >/dev/null
lib/built-in.o: In function `inflateReset':
/mnt/disk/u-boot/lib/zlib/inflate.c:28: undefined reference to
`watchdog_reset'
/mnt/disk/u-boot/lib/zlib/inflate.c:28:(.text.inflateReset+0x58):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
`watchdog_reset'
lib/built-in.o: In function `inflateEnd':
/mnt/disk/u-boot/lib/zlib/inflate.c:936: undefined reference to
`watchdog_reset'
/mnt/disk/u-boot/lib/zlib/inflate.c:936:(.text.inflateEnd+0x2c):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
`watchdog_reset'
lib/built-in.o: In function `inflate':
/mnt/disk/u-boot/lib/zlib/inflate.c:546: undefined reference to
`watchdog_reset'
/mnt/disk/u-boot/lib/zlib/inflate.c:546:(.text.inflate+0x7b4):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
`watchdog_reset'
/mnt/disk/u-boot/lib/zlib/inflate.c:724: undefined reference to
`watchdog_reset'
/mnt/disk/u-boot/lib/zlib/inflate.c:724:(.text.inflate+0xcc4):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
`watchdog_reset'
lib/built-in.o: In function `udelay':
/mnt/disk/u-boot/lib/time.c:167: undefined reference to `watchdog_reset'
/mnt/disk/u-boot/lib/time.c:167:(.text.udelay+0x1c): relocation
truncated to fit: R_AARCH64_CALL26 against undefined symbol `watchdog_reset'
drivers/built-in.o:/mnt/disk/u-boot/drivers/serial/serial_zynq.c:230:
more undefined references to `watchdog_reset' follow
drivers/built-in.o: In function `_debug_uart_putc':
/mnt/disk/u-boot/drivers/serial/serial_zynq.c:230:(.text.printch+0x4c):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
`watchdog_reset'
/mnt/disk/u-boot/drivers/serial/serial_zynq.c:230:(.text.printch+0x54):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
`watchdog_reset'
/mnt/disk/u-boot/drivers/serial/serial_zynq.c:230:(.text.printascii+0x58):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
`watchdog_reset'
/mnt/disk/u-boot/drivers/serial/serial_zynq.c:230:(.text.printascii+0x60):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
`watchdog_reset'
make[1]: *** [spl/u-boot-spl] Error 1
make: *** [spl/u-boot-spl] Error 2
Yes. You're probably missing this patch here, which I listed as
dependencies in the commit text:
[2] watchdog: Handle SPL build with watchdog disabled
https://patchwork.ozlabs.org/patch/1074098/
Please test again with this patch applied.
snip
+static void watchdog_start(void)
+{
+ u32 timeout = WDT_DEFAULT_TIMEOUT;
+
+ /*
+ * Use only the first watchdog device in U-Boot to trigger the
+ * watchdog reset
+ */
+ if (gd->watchdog_dev) {
I hope that gd structure is cleared somewhere.
I had this also in mind with respect to BSS not being cleared very
early. Its cleared in board_init_f_init_reserve(), so quite early
before board_init_f() is called.
good.
+ debug("Only one watchdog device used!\n");
+ return;
+ }
+
+ /*
+ * Init watchdog: This will call the probe function of the
+ * watchdog driver, enabling the use of the device
+ */
+ if (uclass_get_device(UCLASS_WDT, 0,
+ (struct udevice **)>watchdog_dev)) {
+ debug("Watchdog: Not found!\n");
+ return;
+ }
I think you should c what I have done in zynq/zynqmp. It means check
watchdog0 alias first because this is supposed to be the first primary
watchdog.
zynq/zynqmp/mb code
if (uclass_get_device_by_seq(UCLASS_WDT, 0, _dev)) {
debug("Watchdog:
Re: [U-Boot] [PATCH] watchdog: Implement generic watchdog_reset() version
On 05. 04. 19 15:00, Stefan Roese wrote:
> Hi Michal,
>
> On 05.04.19 14:07, Michal Simek wrote:
>
>
>
>>> +++ b/drivers/watchdog/wdt-uclass.c
>>> @@ -10,6 +10,12 @@
>>> #include
>>> #include
>>> +#ifndef WDT_DEFAULT_TIMEOUT
>>> +#define WDT_DEFAULT_TIMEOUT 60
>>> +#endif
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> int wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
>>> {
>>> const struct wdt_ops *ops = device_get_ops(dev);
>>> @@ -63,6 +69,67 @@ int wdt_expire_now(struct udevice *dev, ulong flags)
>>> return ret;
>>> }
>>> +#if defined(CONFIG_WATCHDOG)
>>
>> This is not enough because you can enable it just for full u-boot but
>> not for SPL.
>
> Why not? CONFIG_WATCHDOG can be enabled with or without
> CONFIG_SPL_WATCHDOG_SUPPORT being enabled.
>
>> It means you should also handle CONFIG_SPL_WATCHDOG_SUPPORT
>> macros.
>>
>> Just try to enable CADENCE_WDT, WDT and Watchdog for zcu100 and build
>
> I just tried this for xilinx_zynqmp_zcu100_revC_defconfig. Per default
> it has enabled:
ah right. I have patch in my queue to disable it by default.
Anyway this is what I am getting.
[u-boot](mainline)$ git log -n 3 --oneline
672eafbf08a0 watchdog: Implement generic watchdog_reset() version
7b5b40e4858b watchdog: Move watchdog_dev to data section (BSS may not be
cleared)
0e708abcbba1 Merge branch 'master' of git://git.denx.de/u-boot-usb
[u-boot](mainline)$ make xilinx_zynqmp_zcu100_revC_defconfig >/dev/null
&& make -j >/dev/null
lib/built-in.o: In function `inflateReset':
/mnt/disk/u-boot/lib/zlib/inflate.c:28: undefined reference to
`watchdog_reset'
/mnt/disk/u-boot/lib/zlib/inflate.c:28:(.text.inflateReset+0x58):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
`watchdog_reset'
lib/built-in.o: In function `inflateEnd':
/mnt/disk/u-boot/lib/zlib/inflate.c:936: undefined reference to
`watchdog_reset'
/mnt/disk/u-boot/lib/zlib/inflate.c:936:(.text.inflateEnd+0x2c):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
`watchdog_reset'
lib/built-in.o: In function `inflate':
/mnt/disk/u-boot/lib/zlib/inflate.c:546: undefined reference to
`watchdog_reset'
/mnt/disk/u-boot/lib/zlib/inflate.c:546:(.text.inflate+0x7b4):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
`watchdog_reset'
/mnt/disk/u-boot/lib/zlib/inflate.c:724: undefined reference to
`watchdog_reset'
/mnt/disk/u-boot/lib/zlib/inflate.c:724:(.text.inflate+0xcc4):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
`watchdog_reset'
lib/built-in.o: In function `udelay':
/mnt/disk/u-boot/lib/time.c:167: undefined reference to `watchdog_reset'
/mnt/disk/u-boot/lib/time.c:167:(.text.udelay+0x1c): relocation
truncated to fit: R_AARCH64_CALL26 against undefined symbol `watchdog_reset'
drivers/built-in.o:/mnt/disk/u-boot/drivers/serial/serial_zynq.c:230:
more undefined references to `watchdog_reset' follow
drivers/built-in.o: In function `_debug_uart_putc':
/mnt/disk/u-boot/drivers/serial/serial_zynq.c:230:(.text.printch+0x4c):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
`watchdog_reset'
/mnt/disk/u-boot/drivers/serial/serial_zynq.c:230:(.text.printch+0x54):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
`watchdog_reset'
/mnt/disk/u-boot/drivers/serial/serial_zynq.c:230:(.text.printascii+0x58):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
`watchdog_reset'
/mnt/disk/u-boot/drivers/serial/serial_zynq.c:230:(.text.printascii+0x60):
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol
`watchdog_reset'
make[1]: *** [spl/u-boot-spl] Error 1
make: *** [spl/u-boot-spl] Error 2
snip
>>> +static void watchdog_start(void)
>>> +{
>>> + u32 timeout = WDT_DEFAULT_TIMEOUT;
>>> +
>>> + /*
>>> + * Use only the first watchdog device in U-Boot to trigger the
>>> + * watchdog reset
>>> + */
>>> + if (gd->watchdog_dev) {
>>
>> I hope that gd structure is cleared somewhere.
>
> I had this also in mind with respect to BSS not being cleared very
> early. Its cleared in board_init_f_init_reserve(), so quite early
> before board_init_f() is called.
good.
>
>>> + debug("Only one watchdog device used!\n");
>>> + return;
>>> + }
>>> +
>>> + /*
>>> + * Init watchdog: This will call the probe function of the
>>> + * watchdog driver, enabling the use of the device
>>> + */
>>> + if (uclass_get_device(UCLASS_WDT, 0,
>>> + (struct udevice **)>watchdog_dev)) {
>>> + debug("Watchdog: Not found!\n");
>>> + return;
>>> + }
>>
>> I think you should c what I have done in zynq/zynqmp. It means check
>> watchdog0 alias first because this is supposed to be the first primary
>> watchdog.
>>
>> zynq/zynqmp/mb code
>> if (uclass_get_device_by_seq(UCLASS_WDT, 0, _dev)) {
>> debug("Watchdog: Not found by seq!\n");
>> if
[U-Boot] [PATCH 1/1] colibri_imx6: use UUID for rootfs
Replace usage of "/dev/mmcblk*p*" with a proper UUID of rootfs partition.
This fixes the issue, when MMC controllers are probed in a different order
in U-boot and Linux kernel.
Signed-off-by: Igor Opaniuk
---
configs/colibri_imx6_defconfig | 1 +
include/configs/colibri_imx6.h | 55 +++---
2 files changed, 38 insertions(+), 18 deletions(-)
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index bf05c68807..083588e02d 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -40,6 +40,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_UUID=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index 803c9be064..6603698a66 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -115,16 +115,22 @@
"imx6dl-colibri-cam-eval-v3.dtb fat 0 1"
#define EMMC_BOOTCMD \
- "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext4 " \
+ "emmcdev=0\0" \
+ "emmcbootpart=1\0" \
+ "emmcrootpart=2\0" \
+ "emmcfinduuid=part uuid mmc ${mmcdev}:${emmcrootpart} uuid\0" \
+ "set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} "\
+ "rw,noatime rootfstype=ext4 " \
"rootwait\0" \
- "emmcboot=run setup; " \
+ "emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \
"setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
"${vidargs}; echo Booting from internal eMMC chip...; " \
- "run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \
- "${boot_file} && run fdt_fixup && " \
+ "run emmcdtbload; load mmc ${emmcdev}:${emmcbootpart} " \
+ "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
"bootz ${kernel_addr_r} ${dtbparam}\0" \
- "emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
- "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+ "emmcdtbload=setenv dtbparam; load mmc ${emmcdev}:${emmcbootpart} " \
+ "${fdt_addr_r} ${fdt_file} && " \
+ "setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x1000\0" \
@@ -147,26 +153,38 @@
"&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
#define SD_BOOTCMD \
- "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext4 " \
- "rootwait\0" \
- "sdboot=run setup; " \
+ "sddev=1\0" \
+ "sdbootpart=1\0" \
+ "sdrootpart=2\0" \
+ "sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \
+ "set_sdargs=setenv sdargs ip=off root=PARTUUID=${uuid} rw,noatime " \
+ "rootfstype=ext4 rootwait\0" \
+ "sdboot=run setup; run sdfinduuid; run set_sdargs; " \
"setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
"${vidargs}; echo Booting from SD card; " \
- "run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
- "${boot_file} && run fdt_fixup && " \
+ "run sddtbload; load mmc ${sddev}:${sdbootpart} "\
+ "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
"bootz ${kernel_addr_r} ${dtbparam}\0" \
- "sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
- "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+ "sddtbload=setenv dtbparam; load mmc ${sddev}:${sdbootpart} " \
+ "${fdt_addr_r} ${fdt_file} && setenv dtbparam \" - " \
+ "${fdt_addr_r}\" && true\0"
#define USB_BOOTCMD \
- "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext4 " \
- "rootwait\0" \
- "usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \
+ "usbdev=0\0" \
+ "usbbootpart=1\0" \
+ "usbrootpart=2\0" \
+ "usbfinduuid=part uuid usb ${usbdev}:${usbrootpart} uuid\0" \
+ "set_usbargs=setenv usbargs ip=off root=PARTUUID=${uuid} rw,noatime " \
+ "rootfstype=ext4 rootwait\0" \
+ "usbboot=run setup; usb start; run usbfinduuid; run set_usbargs; " \
+ "setenv bootargs ${defargs} ${setupargs} " \
"${usbargs} ${vidargs}; echo Booting from USB stick...; " \
- "usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \
+ "run usbdtbload; " \
+ "load usb ${usbdev}:${usbbootpart} ${kernel_addr_r} " \
"${boot_file} && run fdt_fixup && " \
"bootz ${kernel_addr_r} ${dtbparam}\0" \
- "usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
+ "usbdtbload=setenv dtbparam; load usb ${usbdev}:${usbbootpart} " \
+ "${fdt_addr_r} " \
"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" &&
Re: [U-Boot] [PATCH V2 0/5] Convert Pico i.MX7 to DM
Le ven. 5 avr. 2019 à 15:07, Fabio Estevam a écrit : > Hi Joris, > Hi Fabio, > On Thu, Apr 4, 2019 at 9:01 AM Joris Offouga > wrote: > > > > This series convert Pico i.MX7 and variant board to DM. > > The following options have been enabled: > > -CONFIG_DM_GPIO > > -CONFIG_DM_EMMC > > > > Signed-off-by: Joris Offouga > > --- > > > > Change in v2: > > - add missing dtb in Makefile > > Thanks for working on this series. > It was a pleasure I learned a lot > > My previous Tested-by tag still applies here as well :-) > > For the entire series: > > Tested-by: Fabio Estevam > Thanks Fabio, ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] watchdog: Implement generic watchdog_reset() version
On 05.04.19 15:00, Stefan Roese wrote:
+ debug("Only one watchdog device used!\n");
+ return;
+ }
+
+ /*
+* Init watchdog: This will call the probe function of the
+* watchdog driver, enabling the use of the device
+*/
+ if (uclass_get_device(UCLASS_WDT, 0,
+ (struct udevice **)>watchdog_dev)) {
+ debug("Watchdog: Not found!\n");
+ return;
+ }
I think you should c what I have done in zynq/zynqmp. It means check
watchdog0 alias first because this is supposed to be the first primary
watchdog.
zynq/zynqmp/mb code
if (uclass_get_device_by_seq(UCLASS_WDT, 0, _dev)) {
debug("Watchdog: Not found by seq!\n");
if (uclass_get_device(UCLASS_WDT, 0, _dev)) {
puts("Watchdog: Not found!\n");
return 0;
}
}
In my (internal) first version, I had exactly this code included. I
removed the first part, as it makes no real sense to call it at this
stage (wdt_post_bind() for the first WDT found in the system). My
understanding is, that wdt_post_bind() will get called for all WDT
found in the system. My current logic here is, to only register the
first WDT found to the global watchdog_dev in GD. To prevent that
multiple WDT are used to service the U-Boot watchdog via WATCHDOG_RESET.
Or does the DM subsystem automatically bind the watchdog0 alias first
in its binding sequence?
I do not have a system with multiple watchdogs here, so its not that
easy to test this. I could simulate this though somehow...
I just did some testing on this. One solution might be, to only use
uclass_get_device_by_seq() (instead of uclass_get_device) and return
if the alias is not found. This way, all watchdog devices will get
probed (bound) and only the one referenced by the alias will get used.
This means on the other hand, that an watchdog0 alias is needed in the
DT to enable the WATCHDOG_RESET U-Boot servicing, which might be not
backward compatible.
Do you have any other thought on this?
Thanks,
Stefan
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH V2 0/5] Convert Pico i.MX7 to DM
Hi Joris, On Thu, Apr 4, 2019 at 9:01 AM Joris Offouga wrote: > > This series convert Pico i.MX7 and variant board to DM. > The following options have been enabled: > -CONFIG_DM_GPIO > -CONFIG_DM_EMMC > > Signed-off-by: Joris Offouga > --- > > Change in v2: > - add missing dtb in Makefile Thanks for working on this series. My previous Tested-by tag still applies here as well :-) For the entire series: Tested-by: Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 2/4] imx: move BOARD_SIZE_CHECK to main Makefile
Hi Heinrich, On Tue, Apr 2, 2019 at 2:19 PM Heinrich Schuchardt wrote: > > We currently have duplicate definitions for BOARD_SIZE_CHECK in Makefile > and arch/arm/mach-imx/Makefile. > > Move the board size check from arch/arm/mach-imx/Makefile to Makefile. > > Depending on the value of CONFIG_BOARD_SIZE_LIMIT an error like an error > like the following is thrown: > > u-boot-dtb.imx exceeds file size limit: > limit: 503696 bytes > actual: 509720 bytes > excess: 6024 bytes > make: *** [Makefile:1051: u-boot-dtb.imx] Error 1 > > Signed-off-by: Heinrich Schuchardt Yes, it makes sense. No need for a imx specific size check: Reviewed-by: Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 06/18] usb: xhci: move xhci.h to include usb
The xhci.h header file is currently located under drivers/usb/xhci
Move it to the include/usb folder to make it available to drivers that
are not under drivers/usb/xhci
Signed-off-by: Jean-Jacques Hiblot
---
MAINTAINERS | 1 +
drivers/usb/host/xhci-dwc3.c | 2 +-
drivers/usb/host/xhci-exynos5.c | 2 +-
drivers/usb/host/xhci-fsl.c | 2 +-
drivers/usb/host/xhci-mem.c | 2 +-
drivers/usb/host/xhci-mvebu.c| 2 +-
drivers/usb/host/xhci-omap.c | 2 +-
drivers/usb/host/xhci-pci.c | 2 +-
drivers/usb/host/xhci-rcar.c | 2 +-
drivers/usb/host/xhci-ring.c | 2 +-
drivers/usb/host/xhci-rockchip.c | 2 +-
drivers/usb/host/xhci.c | 2 +-
drivers/usb/phy/omap_usb_phy.c | 2 +-
{drivers/usb/host => include/usb}/xhci.h | 0
14 files changed, 13 insertions(+), 12 deletions(-)
rename {drivers/usb/host => include/usb}/xhci.h (100%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8a4c5d4eab..77b435deb6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -758,6 +758,7 @@ M: Bin Meng
S: Maintained
T: git git://git.denx.de/u-boot-usb.git topic-xhci
F: drivers/usb/host/xhci*
+F: include/usb/xhci.h
VIDEO
M: Anatolij Gustschin
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index 83b9f119e7..051c4c12e7 100644
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -14,7 +14,7 @@
#include
#include
-#include "xhci.h"
+#include
#include
#include
#include
diff --git a/drivers/usb/host/xhci-exynos5.c b/drivers/usb/host/xhci-exynos5.c
index c150f520bd..25c30c24f0 100644
--- a/drivers/usb/host/xhci-exynos5.c
+++ b/drivers/usb/host/xhci-exynos5.c
@@ -27,7 +27,7 @@
#include
#include
-#include "xhci.h"
+#include
/* Declare global data pointer */
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index c0b98a8ec7..9e0c1b76e4 100644
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -13,7 +13,7 @@
#include
#include
#include
-#include "xhci.h"
+#include
#include
#include
#include
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 84c2c3344a..530e979bb7 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -21,7 +21,7 @@
#include
#include
-#include "xhci.h"
+#include
#define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
/**
diff --git a/drivers/usb/host/xhci-mvebu.c b/drivers/usb/host/xhci-mvebu.c
index b6c6aaf78e..2b871046ae 100644
--- a/drivers/usb/host/xhci-mvebu.c
+++ b/drivers/usb/host/xhci-mvebu.c
@@ -12,7 +12,7 @@
#include
#include
-#include "xhci.h"
+#include
struct mvebu_xhci_platdata {
fdt_addr_t hcd_base;
diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c
index db007af37f..25b195f7d1 100644
--- a/drivers/usb/host/xhci-omap.c
+++ b/drivers/usb/host/xhci-omap.c
@@ -19,7 +19,7 @@
#include
#include
-#include "xhci.h"
+#include
/* Declare global data pointer */
static struct omap_xhci omap;
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index b995aef997..c1f60da541 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -9,7 +9,7 @@
#include
#include
#include
-#include "xhci.h"
+#include
static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,
struct xhci_hcor **ret_hcor)
diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c
index f2e91ef0fe..c4d8811343 100644
--- a/drivers/usb/host/xhci-rcar.c
+++ b/drivers/usb/host/xhci-rcar.c
@@ -12,7 +12,7 @@
#include
#include
-#include "xhci.h"
+#include
#include "xhci-rcar-r8a779x_usb3_v3.h"
/* Register Offset */
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index b2cfd948f8..119b418487 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -19,7 +19,7 @@
#include
#include
-#include "xhci.h"
+#include
/**
* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
diff --git a/drivers/usb/host/xhci-rockchip.c b/drivers/usb/host/xhci-rockchip.c
index f19bea3a91..4f221a60f2 100644
--- a/drivers/usb/host/xhci-rockchip.c
+++ b/drivers/usb/host/xhci-rockchip.c
@@ -13,7 +13,7 @@
#include
#include
-#include "xhci.h"
+#include
struct rockchip_xhci_platdata {
fdt_addr_t hcd_base;
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 44c5f2d264..848721a49d 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -28,7 +28,7 @@
#include
#include
#include
-#include "xhci.h"
+#include
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
index 32e5bbb8d8..897e6f19f7 100644
---
Re: [U-Boot] [PATCH] watchdog: Implement generic watchdog_reset() version
Hi Michal,
On 05.04.19 14:07, Michal Simek wrote:
+++ b/drivers/watchdog/wdt-uclass.c
@@ -10,6 +10,12 @@
#include
#include
+#ifndef WDT_DEFAULT_TIMEOUT
+#define WDT_DEFAULT_TIMEOUT60
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
int wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
{
const struct wdt_ops *ops = device_get_ops(dev);
@@ -63,6 +69,67 @@ int wdt_expire_now(struct udevice *dev, ulong flags)
return ret;
}
+#if defined(CONFIG_WATCHDOG)
This is not enough because you can enable it just for full u-boot but
not for SPL.
Why not? CONFIG_WATCHDOG can be enabled with or without
CONFIG_SPL_WATCHDOG_SUPPORT being enabled.
It means you should also handle CONFIG_SPL_WATCHDOG_SUPPORT
macros.
Just try to enable CADENCE_WDT, WDT and Watchdog for zcu100 and build
I just tried this for xilinx_zynqmp_zcu100_revC_defconfig. Per default
it has enabled:
$ grep 'WATCHDOG\|WDT' .config
# CONFIG_SPL_WATCHDOG_SUPPORT is not set
# CONFIG_SYSRESET_WATCHDOG is not set
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_RESET_DISABLE is not set
# CONFIG_BCM2835_WDT is not set
# CONFIG_ULP_WATCHDOG is not set
CONFIG_WDT=y
# CONFIG_WDT_ASPEED is not set
# CONFIG_WDT_ORION is not set
CONFIG_WDT_CDNS=y
# CONFIG_XILINX_TB_WATCHDOG is not set
# CONFIG_IMX_WATCHDOG is not set
# CONFIG_WDT_AT91 is not set
I can also enable SPL_WATCHDOG_SUPPORT and it compiles without issues:
$ grep 'WATCHDOG\|WDT' .config
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_SYSRESET_WATCHDOG is not set
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_RESET_DISABLE is not set
# CONFIG_BCM2835_WDT is not set
# CONFIG_ULP_WATCHDOG is not set
CONFIG_WDT=y
# CONFIG_WDT_ASPEED is not set
# CONFIG_WDT_ORION is not set
CONFIG_WDT_CDNS=y
# CONFIG_XILINX_TB_WATCHDOG is not set
# CONFIG_IMX_WATCHDOG is not set
# CONFIG_WDT_AT91 is not set
What am I missing?
+/*
+ * Called by macro WATCHDOG_RESET. This function be called *very* early,
+ * so we need to make sure, that the watchdog driver is ready before using
+ * it in this function.
+ */
+void watchdog_reset(void)
+{
+ static ulong next_reset;
+ ulong now;
+
+ /* Exit if GD is not ready or watchdog is not initialized yet */
+ if (!gd || !(gd->flags & GD_FLG_WDT_READY))
+ return;
+
+ /* Do not reset the watchdog too often */
+ now = get_timer(0);
+ if (now > next_reset) {
+ next_reset = now + 1000;/* reset every 1000ms */
+ wdt_reset(gd->watchdog_dev);
+ }
+}
+
+static void watchdog_start(void)
+{
+ u32 timeout = WDT_DEFAULT_TIMEOUT;
+
+ /*
+* Use only the first watchdog device in U-Boot to trigger the
+* watchdog reset
+*/
+ if (gd->watchdog_dev) {
I hope that gd structure is cleared somewhere.
I had this also in mind with respect to BSS not being cleared very
early. Its cleared in board_init_f_init_reserve(), so quite early
before board_init_f() is called.
+ debug("Only one watchdog device used!\n");
+ return;
+ }
+
+ /*
+* Init watchdog: This will call the probe function of the
+* watchdog driver, enabling the use of the device
+*/
+ if (uclass_get_device(UCLASS_WDT, 0,
+ (struct udevice **)>watchdog_dev)) {
+ debug("Watchdog: Not found!\n");
+ return;
+ }
I think you should c what I have done in zynq/zynqmp. It means check
watchdog0 alias first because this is supposed to be the first primary
watchdog.
zynq/zynqmp/mb code
if (uclass_get_device_by_seq(UCLASS_WDT, 0, _dev)) {
debug("Watchdog: Not found by seq!\n");
if (uclass_get_device(UCLASS_WDT, 0, _dev)) {
puts("Watchdog: Not found!\n");
return 0;
}
}
In my (internal) first version, I had exactly this code included. I
removed the first part, as it makes no real sense to call it at this
stage (wdt_post_bind() for the first WDT found in the system). My
understanding is, that wdt_post_bind() will get called for all WDT
found in the system. My current logic here is, to only register the
first WDT found to the global watchdog_dev in GD. To prevent that
multiple WDT are used to service the U-Boot watchdog via WATCHDOG_RESET.
Or does the DM subsystem automatically bind the watchdog0 alias first
in its binding sequence?
I do not have a system with multiple watchdogs here, so its not that
easy to test this. I could simulate this though somehow...
+
+ if (CONFIG_IS_ENABLED(OF_CONTROL)) {
+ timeout = dev_read_u32_default(gd->watchdog_dev, "timeout-sec",
+ WDT_DEFAULT_TIMEOUT);
+ }
You should remove them from drivers.
drivers/watchdog/at91sam9_wdt.c:119:priv->timeout =
dev_read_u32_default(dev, "timeout-sec",
drivers/watchdog/cdns_wdt.c:238:priv->timeout =
[U-Boot] [PATCH v1 14/18] ARM: keystone: increase PSC timeout
Turning off the USB clocks may take longer than 100us. Increase the timeout to 100ms. Signed-off-by: Jean-Jacques Hiblot --- arch/arm/mach-keystone/include/mach/psc_defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-keystone/include/mach/psc_defs.h b/arch/arm/mach-keystone/include/mach/psc_defs.h index dfc22d5e90..f164f95bf2 100644 --- a/arch/arm/mach-keystone/include/mach/psc_defs.h +++ b/arch/arm/mach-keystone/include/mach/psc_defs.h @@ -94,7 +94,7 @@ static inline u32 boot_set_bitfield(u32 z, u32 f, u32 x, u32 y) * Timeout limit on checking PTSTAT. This is the number of times the * wait function will be called before giving up. */ -#define PSC_PTSTAT_TIMEOUT_LIMIT100 +#define PSC_PTSTAT_TIMEOUT_LIMIT10 u32 psc_get_domain_num(u32 mod_num); int psc_enable_module(u32 mod_num); -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 03/18] dm: Add a No-op uclass
This uclass is intended for devices that do not need any features from the
uclass, including binding children.
This will typically be used by devices that are used to bind child devices
but do not use dm_scan_fdt_dev() to do it. That is for example the case of
several USB wrappers that have 2 child devices (1 for device and 1 for
host) but bind only one at a any given time.
Signed-off-by: Jean-Jacques Hiblot
---
drivers/core/uclass.c | 5 +
include/dm/uclass-id.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index fc3157de39..dc9eb62893 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -757,3 +757,8 @@ int uclass_pre_remove_device(struct udevice *dev)
return 0;
}
#endif
+
+UCLASS_DRIVER(nop) = {
+ .id = UCLASS_NOP,
+ .name = "nop",
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 86e59781b0..3797cd48f6 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -61,6 +61,7 @@ enum uclass_id {
UCLASS_MMC, /* SD / MMC card or chip */
UCLASS_MOD_EXP, /* RSA Mod Exp device */
UCLASS_MTD, /* Memory Technology Device (MTD) device */
+ UCLASS_NOP, /* No-op devices */
UCLASS_NORTHBRIDGE, /* Intel Northbridge / SDRAM controller */
UCLASS_NVME,/* NVM Express device */
UCLASS_PANEL, /* Display panel, such as an LCD */
--
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[U-Boot] [PATCH v1 11/18] usb: dwc3-generic: if no max speed is specified in DT, assume super speed
There is no need to fail if the maximum speed is not specified.
If the speed is not specified, do the same as linux and assume super speed.
Signed-off-by: Jean-Jacques Hiblot
---
drivers/usb/dwc3/dwc3-generic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 4924d07553..3d008496f3 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -89,8 +89,8 @@ static int dwc3_generic_ofdata_to_platdata(struct udevice
*dev)
plat->maximum_speed = usb_get_maximum_speed(node);
if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
- pr_err("Invalid usb maximum speed\n");
- return -ENODEV;
+ pr_info("no usb maximum speed specified. use super speed\n");
+ plat->maximum_speed = USB_SPEED_SUPER;
}
plat->dr_mode = usb_get_dr_mode(node);
--
2.17.1
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[U-Boot] [PATCH v1 15/18] ARM: keystone: Do not enable the USB power domains at the board level
This breaks linux boot sequence.
Observed on k2e and k2l platforms.
Signed-off-by: Jean-Jacques Hiblot
---
board/ti/ks2_evm/board.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index eed62e9cac..c1ebce42b6 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -66,20 +66,7 @@ struct image_header *spl_get_load_buffer(ssize_t offset,
size_t size)
int board_init(void)
{
-#if CONFIG_IS_ENABLED(DM_USB)
- int rc = psc_enable_module(KS2_LPSC_USB);
-
- if (rc)
- puts("Cannot enable USB0 module");
-#ifdef KS2_LPSC_USB_1
- rc = psc_enable_module(KS2_LPSC_USB_1);
- if (rc)
- puts("Cannot enable USB1 module");
-#endif
-#endif
-
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
return 0;
}
--
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[U-Boot] [PATCH v1 00/18] Improvement for the DWC3 USB generic driver and fixes for the K2 platforms
The K2 platforms have shown boot issues after switching to the DWC3 generic
driver. Those are due to the fact that the USB domains are not turned off
before booting linux and the phy were not properly initialized. Fixing it
by improving the DWC3-generic driver and handling the USB power domain in
the PHY driver.
At the same time this series introduce a new uclass (UCLASS_NOP) to replace
usage of UCLASS_MISC in the USB wrapper because the MISC class now
automatically binds all the child devices.
Improvements to the DWC3 generic driver are:
- Fix it by switching to UCLASS_NOP
- core: read quirks properties from DT and apply the fixes.
- add a new host driver that uses the DWC3 core (more generic than
xhci-dwc3). This should enable most platforms to drop their own version
of the xhci-driver to use the generic one instead.
This series also removes the now unused xhci-zynqmp driver and tries to
better manage the Kconfig options related to DWC3 gadget/host mode
selection.
This has been tested with K2 and DRA7 platforms (host and device modes).
Travis build: https://travis-ci.org/jjhiblot/u-boot/builds/515282720
Jean-Jacques Hiblot (18):
usb: dwc3-generic: remove dm_scan_fdt_dev() from the remove() callback
usb: host: remove the xhci-zynqmp driver
dm: Add a No-op uclass
usb: dwc3: Use UCLASS_NOP instead of UCLASS_MISC for the DWC3 generic
glue
usb: dwc3: switch to peripheral mode when exiting
usb: xhci: move xhci.h to include usb
usb: dwc3: always use the inlined version of
dwc3_host_init/dwc3_host_exit
usb: dwc3-generic: use platdata
usb: dwc3-generic: factorize code
usb: dwc3-generic: add a new host driver that uses the dwc3 core
usb: dwc3-generic: if no max speed is specified in DT, assume super
speed
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT
usb: dwc3: Kconfig: get rid of obsolete mode selection
ARM: keystone: increase PSC timeout
ARM: keystone: Do not enable the USB power domains at the board level
phy: keystone-usb: handle the transition of the USB power domain
configs: k2g_evm_defconfig: disable XHCI_DWC3 and enable
KEYSTONE_USB_PHY
ARM: DTS: keystone: complete the description of the USB PHY devices
MAINTAINERS | 1 +
arch/arm/dts/keystone-k2e-evm-u-boot.dtsi | 32
arch/arm/dts/keystone-k2g-evm-u-boot.dtsi | 28
arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi| 14 ++
arch/arm/dts/keystone-k2l-evm-u-boot.dtsi | 18 +++
.../arm/mach-keystone/include/mach/psc_defs.h | 2 +-
board/ti/ks2_evm/board.c | 13 --
configs/avnet_ultra96_rev1_defconfig | 1 -
configs/evb-rk3328_defconfig | 1 +
configs/k2g_evm_defconfig | 3 +-
.../xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 -
.../xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 -
.../xilinx_zynqmp_zc1751_xm017_dc3_defconfig | 1 -
configs/xilinx_zynqmp_zcu100_revC_defconfig | 1 -
configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 -
configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 -
configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 -
configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 -
configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 -
configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 -
configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 -
drivers/core/uclass.c | 5 +
drivers/phy/keystone-usb-phy.c| 22 +++
drivers/usb/dwc3/Kconfig | 20 +--
drivers/usb/dwc3/core.c | 84 +-
drivers/usb/dwc3/core.h | 6 +-
drivers/usb/dwc3/dwc3-generic.c | 150 ++
drivers/usb/host/Kconfig | 7 -
drivers/usb/host/Makefile | 1 -
drivers/usb/host/xhci-dwc3.c | 2 +-
drivers/usb/host/xhci-exynos5.c | 2 +-
drivers/usb/host/xhci-fsl.c | 2 +-
drivers/usb/host/xhci-mem.c | 2 +-
drivers/usb/host/xhci-mvebu.c | 2 +-
drivers/usb/host/xhci-omap.c | 2 +-
drivers/usb/host/xhci-pci.c | 2 +-
drivers/usb/host/xhci-rcar.c | 2 +-
drivers/usb/host/xhci-ring.c | 2 +-
drivers/usb/host/xhci-rockchip.c | 2 +-
drivers/usb/host/xhci-zynqmp.c| 146 -
drivers/usb/host/xhci.c | 2 +-
drivers/usb/phy/omap_usb_phy.c| 2 +-
include/dm/uclass-id.h| 1 +
{drivers/usb/host => include/usb}/xhci.h | 0
44 files changed, 335 insertions(+), 255 deletions(-)
create mode 100644 arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
delete mode 100644 drivers/usb/host/xhci-zynqmp.c
rename {drivers/usb/host => include/usb}/xhci.h (100%)
--
2.17.1
___
[U-Boot] [PATCH v1 13/18] usb: dwc3: Kconfig: get rid of obsolete mode selection
The mode selection for the DWC3 is kind of obsolete. The driver does not have to be host only or gadget only. This choice is confusing. All the remaining callers of dwc3_uboot_init() explicitly set dr_mode before calling the function, so none rely on a default behavior. Remove the choice menu and keep only the USB_DWC3_GADGET option. Enable it by default if USB_GADGET and USB_DWC3 are enabled. It must be disabled for the evb-rk3328 as it uses DWC2 for the gadget and DWC3 for the host. Signed-off-by: Jean-Jacques Hiblot --- configs/evb-rk3328_defconfig | 1 + drivers/usb/dwc3/Kconfig | 20 ++-- drivers/usb/dwc3/core.c | 4 ++-- 3 files changed, 5 insertions(+), 20 deletions(-) diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 6783d5a29e..52df5bc46c 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -57,6 +57,7 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index bbd8105c06..58147c3d53 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -7,26 +7,10 @@ config USB_DWC3 if USB_DWC3 -choice - bool "DWC3 Mode Selection" - -config USB_DWC3_HOST - bool "Host only mode" - depends on USB - help - Select this when you want to use DWC3 in host mode only, - thereby the gadget feature will be regressed. - config USB_DWC3_GADGET - bool "Gadget only mode" + bool "USB Gadget support for DWC3" + default y depends on USB_GADGET - select USB_GADGET_DUALSPEED - help - Select this when you want to use DWC3 in gadget mode only, - thereby the host feature will be regressed. - -endchoice - comment "Platform Glue Driver Support" config USB_DWC3_OMAP diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 1baad39796..9f7f053265 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -707,9 +707,9 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev) return -ENOMEM; } - if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) + if (!IS_ENABLED(USB_DWC3_GADGET)) dwc->dr_mode = USB_DR_MODE_HOST; - else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) + else if (!IS_ENABLED(CONFIG_USB_HOST)) dwc->dr_mode = USB_DR_MODE_PERIPHERAL; if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 09/18] usb: dwc3-generic: factorize code
Factor code for re-usability.
This is another step toward adding host support.
Signed-off-by: Jean-Jacques Hiblot
---
drivers/usb/dwc3/dwc3-generic.c | 55 +
1 file changed, 35 insertions(+), 20 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index f29b93d191..d5c71d024f 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -28,27 +28,17 @@ struct dwc3_generic_plat {
enum usb_dr_mode dr_mode;
};
-#if CONFIG_IS_ENABLED(DM_USB_GADGET)
struct dwc3_generic_priv {
+ void *base;
struct dwc3 dwc3;
struct phy *phys;
int num_phys;
};
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
-{
- struct dwc3_generic_priv *priv = dev_get_priv(dev);
- struct dwc3 *dwc3 = >dwc3;
-
- dwc3_gadget_uboot_handle_interrupt(dwc3);
-
- return 0;
-}
-
-static int dwc3_generic_peripheral_probe(struct udevice *dev)
+static int dwc3_generic_probe(struct udevice *dev,
+ struct dwc3_generic_priv *priv)
{
int rc;
- struct dwc3_generic_priv *priv = dev_get_priv(dev);
struct dwc3_generic_plat *plat = dev_get_platdata(dev);
struct dwc3 *dwc3 = >dwc3;
@@ -59,22 +49,22 @@ static int dwc3_generic_peripheral_probe(struct udevice
*dev)
if (rc)
return rc;
- dwc3->regs = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
- dwc3->regs += DWC3_GLOBALS_REGS_START;
+ priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
+ dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
dwc3->dev = dev;
rc = dwc3_init(dwc3);
if (rc) {
- unmap_physmem(dwc3->regs, MAP_NOCACHE);
+ unmap_physmem(priv->base, MAP_NOCACHE);
return rc;
}
return 0;
}
-static int dwc3_generic_peripheral_remove(struct udevice *dev)
+static int dwc3_generic_remove(struct udevice *dev,
+ struct dwc3_generic_priv *priv)
{
- struct dwc3_generic_priv *priv = dev_get_priv(dev);
struct dwc3 *dwc3 = >dwc3;
dwc3_remove(dwc3);
@@ -84,7 +74,7 @@ static int dwc3_generic_peripheral_remove(struct udevice *dev)
return 0;
}
-static int dwc3_generic_peripheral_ofdata_to_platdata(struct udevice *dev)
+static int dwc3_generic_ofdata_to_platdata(struct udevice *dev)
{
struct dwc3_generic_plat *plat = dev_get_platdata(dev);
int node = dev_of_offset(dev);
@@ -106,10 +96,35 @@ static int
dwc3_generic_peripheral_ofdata_to_platdata(struct udevice *dev)
return 0;
}
+#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
+{
+ struct dwc3_generic_priv *priv = dev_get_priv(dev);
+ struct dwc3 *dwc3 = >dwc3;
+
+ dwc3_gadget_uboot_handle_interrupt(dwc3);
+
+ return 0;
+}
+
+static int dwc3_generic_peripheral_probe(struct udevice *dev)
+{
+ struct dwc3_generic_priv *priv = dev_get_priv(dev);
+
+ return dwc3_generic_probe(dev, priv);
+}
+
+static int dwc3_generic_peripheral_remove(struct udevice *dev)
+{
+ struct dwc3_generic_priv *priv = dev_get_priv(dev);
+
+ return dwc3_generic_remove(dev, priv);
+}
+
U_BOOT_DRIVER(dwc3_generic_peripheral) = {
.name = "dwc3-generic-peripheral",
.id = UCLASS_USB_GADGET_GENERIC,
- .ofdata_to_platdata = dwc3_generic_peripheral_ofdata_to_platdata,
+ .ofdata_to_platdata = dwc3_generic_ofdata_to_platdata,
.probe = dwc3_generic_peripheral_probe,
.remove = dwc3_generic_peripheral_remove,
.priv_auto_alloc_size = sizeof(struct dwc3_generic_priv),
--
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[U-Boot] [PATCH v1 10/18] usb: dwc3-generic: add a new host driver that uses the dwc3 core
Currently the host driver used by dwc3-generic is "xhci-dwc3". This is
a functional driver but it doesn't use the dwc3 core and, in particular,
it lacks some bits that may be important.
For example on the k2 platforms, it is important that the phy are properly
suspended when the USB is not used anymore. The dwc3 core also has a
partial support for quirks.
The new driver can be used as a drop-in replacement for "xhci-dwc3".
In terms of implementation, it may seem strange that 2 private structures
dwc3_generic_host_priv and dwc3_generic_priv) are used. The reason for this
is simply that the xhci layer expects a struct xhci_ctrl at the beginning
of the private data and it seemed wasteful to include it also for the
peripheral case.
Signed-off-by: Jean-Jacques Hiblot
---
drivers/usb/dwc3/core.c | 2 +-
drivers/usb/dwc3/dwc3-generic.c | 54 -
2 files changed, 54 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index ae01490306..653c874fa6 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -887,7 +887,7 @@ int dwc3_shutdown_phy(struct udevice *dev, struct phy
*usb_phys, int num_phys)
}
#endif
-#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+#if CONFIG_IS_ENABLED(DM_USB)
int dwc3_init(struct dwc3 *dwc)
{
int ret;
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index d5c71d024f..4924d07553 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -21,6 +21,7 @@
#include "gadget.h"
#include
#include
+#include
struct dwc3_generic_plat {
fdt_addr_t base;
@@ -35,6 +36,11 @@ struct dwc3_generic_priv {
int num_phys;
};
+struct dwc3_generic_host_priv {
+ struct xhci_ctrl xhci_ctrl;
+ struct dwc3_generic_priv gen_priv;
+};
+
static int dwc3_generic_probe(struct udevice *dev,
struct dwc3_generic_priv *priv)
{
@@ -132,6 +138,50 @@ U_BOOT_DRIVER(dwc3_generic_peripheral) = {
};
#endif
+#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
+static int dwc3_generic_host_probe(struct udevice *dev)
+{
+ struct xhci_hcor *hcor;
+ struct xhci_hccr *hccr;
+ struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
+ int rc;
+
+ rc = dwc3_generic_probe(dev, >gen_priv);
+ if (rc)
+ return rc;
+
+ hccr = (struct xhci_hccr *)priv->gen_priv.base;
+ hcor = (struct xhci_hcor *)(priv->gen_priv.base +
+ HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
+
+ return xhci_register(dev, hccr, hcor);
+}
+
+static int dwc3_generic_host_remove(struct udevice *dev)
+{
+ struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
+ int rc;
+
+ rc = xhci_deregister(dev);
+ if (rc)
+ return rc;
+
+ return dwc3_generic_remove(dev, >gen_priv);
+}
+
+U_BOOT_DRIVER(dwc3_generic_host) = {
+ .name = "dwc3-generic-host",
+ .id = UCLASS_USB,
+ .ofdata_to_platdata = dwc3_generic_ofdata_to_platdata,
+ .probe = dwc3_generic_host_probe,
+ .remove = dwc3_generic_host_remove,
+ .priv_auto_alloc_size = sizeof(struct dwc3_generic_host_priv),
+ .platdata_auto_alloc_size = sizeof(struct dwc3_generic_plat),
+ .ops = _usb_ops,
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif
+
struct dwc3_glue_data {
struct clk_bulk clks;
struct reset_ctl_bulk resets;
@@ -252,10 +302,12 @@ static int dwc3_glue_bind(struct udevice *parent)
driver = "dwc3-generic-peripheral";
#endif
break;
+#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
case USB_DR_MODE_HOST:
debug("%s: dr_mode: HOST\n", __func__);
- driver = "xhci-dwc3";
+ driver = "dwc3-generic-host";
break;
+#endif
default:
debug("%s: unsupported dr_mode\n", __func__);
return -ENODEV;
--
2.17.1
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[U-Boot] [PATCH v1 16/18] phy: keystone-usb: handle the transition of the USB power domain
There is no proper power domain support for the keystone platforms.
However we need to turn off the USB domains before jumping to linux or it
fail to boot (observed with k2e and k2l platforms).
This can be done in the PHY driver as it is dedicated only to the keystone
platforms and matches the required on/off sequence.
Signed-off-by: Jean-Jacques Hiblot
---
drivers/phy/keystone-usb-phy.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/phy/keystone-usb-phy.c b/drivers/phy/keystone-usb-phy.c
index e8146cabfa..14ac62 100644
--- a/drivers/phy/keystone-usb-phy.c
+++ b/drivers/phy/keystone-usb-phy.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
/* USB PHY control register offsets */
#define USB_PHY_CTL_UTMI 0x
@@ -22,15 +23,25 @@
#define PHY_REF_SSP_EN BIT(29)
struct keystone_usb_phy {
+ u32 psc_domain;
void __iomem *reg;
};
static int keystone_usb_init(struct phy *phy)
{
u32 val;
+ int rc;
struct udevice *dev = phy->dev;
struct keystone_usb_phy *keystone = dev_get_priv(dev);
+ /* Release USB from reset */
+ rc = psc_enable_module(keystone->psc_domain);
+ if (rc) {
+ debug("Cannot enable USB module");
+ return -rc;
+ }
+ mdelay(10);
+
/*
* VBUSVLDEXTSEL has a default value of 1 in BootCfg but shouldn't.
* It should always be cleared because our USB PHY has an onchip VBUS
@@ -72,13 +83,24 @@ static int keystone_usb_power_off(struct phy *phy)
static int keystone_usb_exit(struct phy *phy)
{
+ struct udevice *dev = phy->dev;
+ struct keystone_usb_phy *keystone = dev_get_priv(dev);
+
+ if (psc_disable_module(keystone->psc_domain))
+ debug("failed to disable USB module!\n");
+
return 0;
}
static int keystone_usb_phy_probe(struct udevice *dev)
{
+ int rc;
struct keystone_usb_phy *keystone = dev_get_priv(dev);
+ rc = dev_read_u32(dev, "psc-domain", >psc_domain);
+ if (rc)
+ return rc;
+
keystone->reg = dev_remap_addr_index(dev, 0);
if (!keystone->reg) {
pr_err("unable to remap usb phy\n");
--
2.17.1
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[U-Boot] [PATCH v1 18/18] ARM: DTS: keystone: complete the description of the USB PHY devices
As the PHY driver now handles the transitions of USB power domain, we
must add this information in the node of each PHY.
Also, the phy are expected in the "phys" property, not "usb-phys".
Also add the aliases for the USB ports on boards with more than a single
port.
Signed-off-by: Jean-Jacques Hiblot
---
arch/arm/dts/keystone-k2e-evm-u-boot.dtsi | 32 ++
arch/arm/dts/keystone-k2g-evm-u-boot.dtsi | 28 +++
arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi | 14 ++
arch/arm/dts/keystone-k2l-evm-u-boot.dtsi | 18
4 files changed, 92 insertions(+)
create mode 100644 arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
diff --git a/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi
b/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi
index aecb4dde68..c94165ffe7 100644
--- a/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi
@@ -7,8 +7,40 @@
soc {
u-boot,dm-pre-reloc;
};
+ aliases {
+ usb0 =
+ usb1 =
+ };
};
{
u-boot,dm-pre-reloc;
};
+
+_phy {
+ #phy-cells = <0>;
+ psc-domain = <2>;
+};
+
+ {
+ dwc3@269 {
+ phys = <_phy>;
+ dr_mode = "host";
+ snps,u2ss_inp3_quirk;
+ status = "okay";
+ };
+};
+
+_phy {
+ #phy-cells = <0>;
+ psc-domain = <1>;
+};
+
+ {
+ dwc3@2501 {
+ phys = <_phy>;
+ dr_mode = "peripheral";
+ snps,u2ss_inp3_quirk;
+ status = "okay";
+ };
+};
diff --git a/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
b/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
index 80f1f60045..e8e70096ea 100644
--- a/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
@@ -7,6 +7,10 @@
soc {
u-boot,dm-pre-reloc;
};
+ aliases {
+ usb0 =
+ usb1 =
+ };
};
{
@@ -16,3 +20,27 @@
{
u-boot,dm-pre-reloc;
};
+
+_phy {
+ compatible = "ti,keystone-usbphy";
+ #phy-cells = <0>;
+ reg = <0x2620738 24>;
+ psc-domain = <25>;
+};
+
+ {
+ phys = <_phy>;
+ snps,u2ss_inp3_quirk;
+};
+
+_phy {
+ compatible = "ti,keystone-usbphy";
+ #phy-cells = <0>;
+ reg = <0x2620750 24>;
+ psc-domain = <26>;
+};
+
+ {
+ phys = <_phy>;
+ snps,u2ss_inp3_quirk;
+};
diff --git a/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi
b/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi
index aecb4dde68..1c2f349f5c 100644
--- a/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi
@@ -12,3 +12,17 @@
{
u-boot,dm-pre-reloc;
};
+
+_phy {
+ #phy-cells = <0>;
+ psc-domain = <2>;
+};
+
+ {
+ dwc3@269 {
+ phys = <_phy>;
+ dr_mode = "host";
+ snps,u2ss_inp3_quirk;
+ status = "okay";
+ };
+};
diff --git a/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
b/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
new file mode 100644
index 00..0a507d0210
--- /dev/null
+++ b/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+_phy {
+ #phy-cells = <0>;
+ psc-domain = <2>;
+};
+
+ {
+ dwc3@269 {
+ phys = <_phy>;
+ dr_mode = "host";
+ snps,u2ss_inp3_quirk;
+ status = "okay";
+ };
+};
--
2.17.1
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[U-Boot] [PATCH v1 12/18] usb: dwc3: Add dwc3_of_parse() to get quirks information from DT
Add a new function that read quirk and configuration information from the
DT. The goal is to allow platforms using their own version of DWC3 driver
to migrate to the generic DWC3 driver.
The function is adapted from the linux dwc3 driver.
Signed-off-by: Jean-Jacques Hiblot
---
drivers/usb/dwc3/core.c | 65 +
drivers/usb/dwc3/core.h | 1 +
drivers/usb/dwc3/dwc3-generic.c | 6 ++-
3 files changed, 71 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 653c874fa6..1baad39796 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -888,6 +888,71 @@ int dwc3_shutdown_phy(struct udevice *dev, struct phy
*usb_phys, int num_phys)
#endif
#if CONFIG_IS_ENABLED(DM_USB)
+void dwc3_of_parse(struct dwc3 *dwc)
+{
+ const u8 *tmp;
+ struct udevice *dev = dwc->dev;
+ u8 lpm_nyet_threshold;
+ u8 tx_de_emphasis;
+ u8 hird_threshold;
+
+ /* default to highest possible threshold */
+ lpm_nyet_threshold = 0xff;
+
+ /* default to -3.5dB de-emphasis */
+ tx_de_emphasis = 1;
+
+ /*
+* default to assert utmi_sleep_n and use maximum allowed HIRD
+* threshold value of 0b1100
+*/
+ hird_threshold = 12;
+
+ dwc->has_lpm_erratum = dev_read_bool(dev,
+ "snps,has-lpm-erratum");
+ tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
+ if (tmp)
+ lpm_nyet_threshold = *tmp;
+
+ dwc->is_utmi_l1_suspend = dev_read_bool(dev,
+ "snps,is-utmi-l1-suspend");
+ tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1);
+ if (tmp)
+ hird_threshold = *tmp;
+
+ dwc->disable_scramble_quirk = dev_read_bool(dev,
+ "snps,disable_scramble_quirk");
+ dwc->u2exit_lfps_quirk = dev_read_bool(dev,
+ "snps,u2exit_lfps_quirk");
+ dwc->u2ss_inp3_quirk = dev_read_bool(dev,
+ "snps,u2ss_inp3_quirk");
+ dwc->req_p1p2p3_quirk = dev_read_bool(dev,
+ "snps,req_p1p2p3_quirk");
+ dwc->del_p1p2p3_quirk = dev_read_bool(dev,
+ "snps,del_p1p2p3_quirk");
+ dwc->del_phy_power_chg_quirk = dev_read_bool(dev,
+ "snps,del_phy_power_chg_quirk");
+ dwc->lfps_filter_quirk = dev_read_bool(dev,
+ "snps,lfps_filter_quirk");
+ dwc->rx_detect_poll_quirk = dev_read_bool(dev,
+ "snps,rx_detect_poll_quirk");
+ dwc->dis_u3_susphy_quirk = dev_read_bool(dev,
+ "snps,dis_u3_susphy_quirk");
+ dwc->dis_u2_susphy_quirk = dev_read_bool(dev,
+ "snps,dis_u2_susphy_quirk");
+ dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
+ "snps,tx_de_emphasis_quirk");
+ tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
+ if (tmp)
+ tx_de_emphasis = *tmp;
+
+ dwc->lpm_nyet_threshold = lpm_nyet_threshold;
+ dwc->tx_de_emphasis = tx_de_emphasis;
+
+ dwc->hird_threshold = hird_threshold
+ | (dwc->is_utmi_l1_suspend << 4);
+}
+
int dwc3_init(struct dwc3 *dwc)
{
int ret;
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 4c89dfcad9..be9672266a 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -991,6 +991,7 @@ struct dwc3_gadget_ep_cmd_params {
/* prototypes */
int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
+void dwc3_of_parse(struct dwc3 *dwc);
int dwc3_init(struct dwc3 *dwc);
void dwc3_remove(struct dwc3 *dwc);
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 3d008496f3..158d726623 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -48,8 +48,12 @@ static int dwc3_generic_probe(struct udevice *dev,
struct dwc3_generic_plat *plat = dev_get_platdata(dev);
struct dwc3 *dwc3 = >dwc3;
+ dwc3->dev = dev;
dwc3->maximum_speed = plat->maximum_speed;
dwc3->dr_mode = plat->dr_mode;
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ dwc3_of_parse(dwc3);
+#endif
rc = dwc3_setup_phy(dev, >phys, >num_phys);
if (rc)
@@ -57,7 +61,7 @@ static int dwc3_generic_probe(struct udevice *dev,
priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
- dwc3->dev = dev;
+
rc = dwc3_init(dwc3);
if (rc) {
--
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[U-Boot] [PATCH v1 04/18] usb: dwc3: Use UCLASS_NOP instead of UCLASS_MISC for the DWC3 generic glue
dwc3-generic has been broken since MISC uclass has been modified to scan DT
sub-nodes after bind.
Fixing it by a using the no-op uclass.
Signed-off-by: Jean-Jacques Hiblot
---
drivers/usb/dwc3/dwc3-generic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 70431facb3..406bf0b362 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -350,7 +350,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
U_BOOT_DRIVER(dwc3_generic_wrapper) = {
.name = "dwc3-generic-wrapper",
- .id = UCLASS_MISC,
+ .id = UCLASS_NOP,
.of_match = dwc3_glue_ids,
.bind = dwc3_glue_bind,
.probe = dwc3_glue_probe,
--
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[U-Boot] [PATCH v1 17/18] configs: k2g_evm_defconfig: disable XHCI_DWC3 and enable KEYSTONE_USB_PHY
KEYSTONE_USB_PHY is now required for proper USB operations. XHCI_DWC3 can be disabled as the xhci-dwc3 is not used anymore USB_DWC3_GADGET can also be removed, it is now selected automatically. Signed-off-by: Jean-Jacques Hiblot --- configs/k2g_evm_defconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 838b6f14b6..f04a56a71d 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -53,6 +53,7 @@ CONFIG_MII=y CONFIG_DRIVER_TI_KEYSTONE_NET=y CONFIG_PHY=y CONFIG_NOP_PHY=y +CONFIG_KEYSTONE_USB_PHY=y CONFIG_REMOTEPROC_TI_POWER=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y @@ -63,9 +64,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DOWNLOAD=y -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 02/18] usb: host: remove the xhci-zynqmp driver
This driver is not used anymore. Signed-off-by: Jean-Jacques Hiblot --- configs/avnet_ultra96_rev1_defconfig | 1 - .../xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - .../xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 - .../xilinx_zynqmp_zc1751_xm017_dc3_defconfig | 1 - configs/xilinx_zynqmp_zcu100_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 - drivers/usb/host/Kconfig | 7 - drivers/usb/host/Makefile | 1 - drivers/usb/host/xhci-zynqmp.c| 146 -- 15 files changed, 166 deletions(-) delete mode 100644 drivers/usb/host/xhci-zynqmp.c diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig index 15a6827893..003b936711 100644 --- a/configs/avnet_ultra96_rev1_defconfig +++ b/configs/avnet_ultra96_rev1_defconfig @@ -73,7 +73,6 @@ CONFIG_ZYNQ_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index bf141c5e16..3556f78674 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -84,7 +84,6 @@ CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index 01c29c0e70..e7b15ac8dd 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -76,7 +76,6 @@ CONFIG_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig index 439f89e50f..18d5a6c62d 100644 --- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig @@ -72,7 +72,6 @@ CONFIG_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig index 6e0767164c..11227ecd79 100644 --- a/configs/xilinx_zynqmp_zcu100_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig @@ -73,7 +73,6 @@ CONFIG_ZYNQ_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index 371e6363db..950712414c 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -100,7 +100,6 @@ CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index a0fb6c3586..084ab44b19 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -99,7 +99,6 @@ CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index db7c093d5e..2de0950bde 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -99,7 +99,6 @@ CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig index eacf75d9f8..f9e29d5677 100644 --- a/configs/xilinx_zynqmp_zcu104_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig @@ -84,7 +84,6 @@ CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git
[U-Boot] [PATCH v1 05/18] usb: dwc3: switch to peripheral mode when exiting
This allow the phy to enter idle and then suspend.
the K2 platforms require the PHY to be suspended before the USB domain
clock can be turned off.
Signed-off-by: Jean-Jacques Hiblot
---
drivers/usb/dwc3/core.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 56e2a046bf..ae01490306 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -581,6 +581,12 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
return 0;
}
+static void dwc3_gadget_run(struct dwc3 *dwc)
+{
+ dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
+ mdelay(100);
+}
+
static void dwc3_core_exit_mode(struct dwc3 *dwc)
{
switch (dwc->dr_mode) {
@@ -598,6 +604,13 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc)
/* do nothing */
break;
}
+
+ /*
+* switch back to peripheral mode
+* This enables the phy to enter idle and then, if enabled, suspend.
+*/
+ dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
+ dwc3_gadget_run(dwc);
}
#define DWC3_ALIGN_MASK(16 - 1)
--
2.17.1
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[U-Boot] [PATCH v1 08/18] usb: dwc3-generic: use platdata
Separate platform data from the private data.
This is one step toward adding host support.
Signed-off-by: Jean-Jacques Hiblot
---
drivers/usb/dwc3/dwc3-generic.c | 37 -
1 file changed, 23 insertions(+), 14 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 406bf0b362..f29b93d191 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -22,17 +22,22 @@
#include
#include
+struct dwc3_generic_plat {
+ fdt_addr_t base;
+ u32 maximum_speed;
+ enum usb_dr_mode dr_mode;
+};
+
#if CONFIG_IS_ENABLED(DM_USB_GADGET)
-struct dwc3_generic_peripheral {
+struct dwc3_generic_priv {
struct dwc3 dwc3;
struct phy *phys;
int num_phys;
- fdt_addr_t base;
};
int dm_usb_gadget_handle_interrupts(struct udevice *dev)
{
- struct dwc3_generic_peripheral *priv = dev_get_priv(dev);
+ struct dwc3_generic_priv *priv = dev_get_priv(dev);
struct dwc3 *dwc3 = >dwc3;
dwc3_gadget_uboot_handle_interrupt(dwc3);
@@ -43,14 +48,18 @@ int dm_usb_gadget_handle_interrupts(struct udevice *dev)
static int dwc3_generic_peripheral_probe(struct udevice *dev)
{
int rc;
- struct dwc3_generic_peripheral *priv = dev_get_priv(dev);
+ struct dwc3_generic_priv *priv = dev_get_priv(dev);
+ struct dwc3_generic_plat *plat = dev_get_platdata(dev);
struct dwc3 *dwc3 = >dwc3;
+ dwc3->maximum_speed = plat->maximum_speed;
+ dwc3->dr_mode = plat->dr_mode;
+
rc = dwc3_setup_phy(dev, >phys, >num_phys);
if (rc)
return rc;
- dwc3->regs = map_physmem(priv->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
+ dwc3->regs = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
dwc3->regs += DWC3_GLOBALS_REGS_START;
dwc3->dev = dev;
@@ -65,7 +74,7 @@ static int dwc3_generic_peripheral_probe(struct udevice *dev)
static int dwc3_generic_peripheral_remove(struct udevice *dev)
{
- struct dwc3_generic_peripheral *priv = dev_get_priv(dev);
+ struct dwc3_generic_priv *priv = dev_get_priv(dev);
struct dwc3 *dwc3 = >dwc3;
dwc3_remove(dwc3);
@@ -77,20 +86,19 @@ static int dwc3_generic_peripheral_remove(struct udevice
*dev)
static int dwc3_generic_peripheral_ofdata_to_platdata(struct udevice *dev)
{
- struct dwc3_generic_peripheral *priv = dev_get_priv(dev);
- struct dwc3 *dwc3 = >dwc3;
+ struct dwc3_generic_plat *plat = dev_get_platdata(dev);
int node = dev_of_offset(dev);
- priv->base = devfdt_get_addr(dev);
+ plat->base = devfdt_get_addr(dev);
- dwc3->maximum_speed = usb_get_maximum_speed(node);
- if (dwc3->maximum_speed == USB_SPEED_UNKNOWN) {
+ plat->maximum_speed = usb_get_maximum_speed(node);
+ if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
pr_err("Invalid usb maximum speed\n");
return -ENODEV;
}
- dwc3->dr_mode = usb_get_dr_mode(node);
- if (dwc3->dr_mode == USB_DR_MODE_UNKNOWN) {
+ plat->dr_mode = usb_get_dr_mode(node);
+ if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
pr_err("Invalid usb mode setup\n");
return -ENODEV;
}
@@ -104,7 +112,8 @@ U_BOOT_DRIVER(dwc3_generic_peripheral) = {
.ofdata_to_platdata = dwc3_generic_peripheral_ofdata_to_platdata,
.probe = dwc3_generic_peripheral_probe,
.remove = dwc3_generic_peripheral_remove,
- .priv_auto_alloc_size = sizeof(struct dwc3_generic_peripheral),
+ .priv_auto_alloc_size = sizeof(struct dwc3_generic_priv),
+ .platdata_auto_alloc_size = sizeof(struct dwc3_generic_plat),
};
#endif
--
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[U-Boot] [PATCH v1 07/18] usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit
No one is actually implementing those functions.
We could remove calls to these altogether, but it does not really hurt to
keep the empty inlined version at the moment and it satisfies a symmetry
with the gadget mode.
Signed-off-by: Jean-Jacques Hiblot
---
drivers/usb/dwc3/core.h | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index cfe29884e7..4c89dfcad9 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -994,15 +994,10 @@ int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
int dwc3_init(struct dwc3 *dwc);
void dwc3_remove(struct dwc3 *dwc);
-#ifdef CONFIG_USB_DWC3_HOST
-int dwc3_host_init(struct dwc3 *dwc);
-void dwc3_host_exit(struct dwc3 *dwc);
-#else
static inline int dwc3_host_init(struct dwc3 *dwc)
{ return 0; }
static inline void dwc3_host_exit(struct dwc3 *dwc)
{ }
-#endif
#ifdef CONFIG_USB_DWC3_GADGET
int dwc3_gadget_init(struct dwc3 *dwc);
--
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[U-Boot] [PATCH v1 01/18] usb: dwc3-generic: remove dm_scan_fdt_dev() from the remove() callback
There is simply no reason to do that here.
Signed-off-by: Jean-Jacques Hiblot
---
drivers/usb/dwc3/dwc3-generic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 3e6c494dc6..70431facb3 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -337,7 +337,7 @@ static int dwc3_glue_remove(struct udevice *dev)
clk_release_bulk(>clks);
- return dm_scan_fdt_dev(dev);
+ return 0;
}
static const struct udevice_id dwc3_glue_ids[] = {
--
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Re: [U-Boot] [PATCH] watchdog: Implement generic watchdog_reset() version
On 04. 04. 19 13:23, Stefan Roese wrote:
> This patch tries to implement a generic watchdog_reset() function that
> can be used by all boards that want to service the watchdog device in
> U-Boot. This watchdog servicing is enabled via CONFIG_WATCHDOG.
>
> Without this approach, new boards or platforms needed to implement a
> board specific version of this functionality, mostly copy'ing the same
> code over and over again into their board or platforms code base.
>
> With this new generic function, the scattered other functions are now
> removed to be replaced by the generic one. The new version also enables
> the configuration of the watchdog timeout via the DT "timeout-sec"
> property (if enabled via CONFIG_OF_CONTROL).
>
> This patch also adds a new flag to the GD flags, to flag that the
> watchdog is ready to use and adds the pointer to the watchdog device
> to the GD. This enables us to remove the global "watchdog_dev"
> variable, which was prone to cause problems because of its potentially
> very early use in watchdog_reset(), even before the BSS is cleared.
>
> Signed-off-by: Stefan Roese
> Cc: Tom Rini
> Cc: Simon Glass
> Cc: Heiko Schocher
> Cc: Michal Simek
> Cc: "Marek Behún"
> Cc: Daniel Schwierzeck
> ---
> This patch depends on the following patches:
>
> [1] watchdog: Move watchdog_dev to data section (BSS may not be cleared)
> https://patchwork.ozlabs.org/patch/1075500/
>
> [2] watchdog: Handle SPL build with watchdog disabled
> https://patchwork.ozlabs.org/patch/1074098/
>
> I would like to see [2] applied in this release, since its a real fix on
> some of the platforms with minimal chances of breakage.
>
> This patch now is a bigger rework and is intended for the next merge
> window. Please review and test if possible. Comments welcome.
>
> Thanks,
> Stefan
>
> arch/mips/mach-mt7620/cpu.c | 36 -
> board/CZ.NIC/turris_mox/turris_mox.c | 30
> board/CZ.NIC/turris_omnia/turris_omnia.c | 35 -
> .../microblaze-generic/microblaze-generic.c | 40 --
> board/xilinx/zynq/board.c | 39 --
> board/xilinx/zynqmp/zynqmp.c | 39 --
> drivers/watchdog/wdt-uclass.c | 74 +++
> include/asm-generic/global_data.h | 4 +
> 8 files changed, 78 insertions(+), 219 deletions(-)
>
> diff --git a/arch/mips/mach-mt7620/cpu.c b/arch/mips/mach-mt7620/cpu.c
> index fe74f26a54..fcd0484a6d 100644
> --- a/arch/mips/mach-mt7620/cpu.c
> +++ b/arch/mips/mach-mt7620/cpu.c
> @@ -69,28 +69,6 @@ int print_cpuinfo(void)
> return 0;
> }
>
> -#ifdef CONFIG_WATCHDOG
> -static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
> -
> -/* Called by macro WATCHDOG_RESET */
> -void watchdog_reset(void)
> -{
> - static ulong next_reset;
> - ulong now;
> -
> - if (!watchdog_dev)
> - return;
> -
> - now = get_timer(0);
> -
> - /* Do not reset the watchdog too often */
> - if (now > next_reset) {
> - next_reset = now + 1000;/* reset every 1000ms */
> - wdt_reset(watchdog_dev);
> - }
> -}
> -#endif
> -
> int arch_misc_init(void)
> {
> /*
> @@ -103,19 +81,5 @@ int arch_misc_init(void)
> flush_dcache_range(gd->bd->bi_memstart,
> gd->bd->bi_memstart + gd->ram_size - 1);
>
> -#ifdef CONFIG_WATCHDOG
> - /* Init watchdog */
> - if (uclass_get_device_by_seq(UCLASS_WDT, 0, _dev)) {
> - debug("Watchdog: Not found by seq!\n");
> - if (uclass_get_device(UCLASS_WDT, 0, _dev)) {
> - puts("Watchdog: Not found!\n");
> - return 0;
> - }
> - }
> -
> - wdt_start(watchdog_dev, 6, 0); /* 60 seconds */
> - printf("Watchdog: Started\n");
> -#endif
> -
> return 0;
> }
> diff --git a/board/CZ.NIC/turris_mox/turris_mox.c
> b/board/CZ.NIC/turris_mox/turris_mox.c
> index 96cb9c7e5c..8a4872343b 100644
> --- a/board/CZ.NIC/turris_mox/turris_mox.c
> +++ b/board/CZ.NIC/turris_mox/turris_mox.c
> @@ -119,41 +119,11 @@ int board_fix_fdt(void *blob)
> }
> #endif
>
> -#ifdef CONFIG_WDT_ARMADA_37XX
> -static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
> -
> -void watchdog_reset(void)
> -{
> - static ulong next_reset;
> - ulong now;
> -
> - if (!watchdog_dev)
> - return;
> -
> - now = timer_get_us();
> -
> - /* Do not reset the watchdog too often */
> - if (now > next_reset) {
> - wdt_reset(watchdog_dev);
> - next_reset = now + 10;
> - }
> -}
> -#endif
> -
> int board_init(void)
> {
> /* address of boot parameters */
> gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
>
> -#ifdef CONFIG_WDT_ARMADA_37XX
> - if (uclass_get_device(UCLASS_WDT, 0, _dev)) {
> - printf("Cannot find Armada 3720 watchdog!\n");
> - }
[U-Boot] [PATCH 1/2] phy: Add USB PHY driver for the MT76x8 (7628/7688) SoC
This driver is derived from this Linux driver:
linux/drivers/phy/ralink/phy-ralink-usb.c
The driver sets up power and host mode, but also needs to configure PHY
registers for the MT7628 and MT7688.
I removed the reset controller handling for the USB host and device, as
it does not seem to be necessary right now. The soft reset bits for both
devices are enabled by default and testing has shown (with hackish
reset handling added), that USB related commands work identical with
or without the reset handling.
Please note that the resulting USB support is tested only very minimal.
I was able to detect one of my 3 currently available USB sticks.
Perhaps some further work is needed to fully support the EHCI controller
integrated in the MT76x8 SoC.
Signed-off-by: Stefan Roese
Cc: Marek Vasut
Cc: Daniel Schwierzeck
---
drivers/phy/Kconfig | 8 ++
drivers/phy/Makefile | 1 +
drivers/phy/mt76x8-usb-phy.c | 161 +++
3 files changed, 170 insertions(+)
create mode 100644 drivers/phy/mt76x8-usb-phy.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 32bbf41dd1..102fb91fff 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -174,4 +174,12 @@ config KEYSTONE_USB_PHY
This PHY is found on some Keystone (K2) devices supporting USB.
+config MT76X8_USB_PHY
+ bool "MediaTek MT76x8 (7628/88) USB PHY support"
+ depends on PHY
+ help
+ Support the USB PHY in MT76x8 SoCs
+
+ This PHY is found on MT76x8 devices supporting USB.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 099551d693..b55917bce1 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o
meson-gxl-usb3.o
obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o
obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o
+obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o
diff --git a/drivers/phy/mt76x8-usb-phy.c b/drivers/phy/mt76x8-usb-phy.c
new file mode 100644
index 00..268da8ef6c
--- /dev/null
+++ b/drivers/phy/mt76x8-usb-phy.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Stefan Roese
+ *
+ * Derived from linux/drivers/phy/ralink/phy-ralink-usb.c
+ * Copyright (C) 2017 John Crispin
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define RT_SYSC_REG_SYSCFG10x014
+#define RT_SYSC_REG_CLKCFG10x030
+#define RT_SYSC_REG_USB_PHY_CFG0x05c
+
+#define OFS_U2_PHY_AC0 0x800
+#define OFS_U2_PHY_AC1 0x804
+#define OFS_U2_PHY_AC2 0x808
+#define OFS_U2_PHY_ACR00x810
+#define OFS_U2_PHY_ACR10x814
+#define OFS_U2_PHY_ACR20x818
+#define OFS_U2_PHY_ACR30x81C
+#define OFS_U2_PHY_ACR40x820
+#define OFS_U2_PHY_AMON0 0x824
+#define OFS_U2_PHY_DCR00x860
+#define OFS_U2_PHY_DCR10x864
+#define OFS_U2_PHY_DTM00x868
+#define OFS_U2_PHY_DTM10x86C
+
+#define RT_RSTCTRL_UDEVBIT(25)
+#define RT_RSTCTRL_UHSTBIT(22)
+#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
+
+#define MT7620_CLKCFG1_UPHY0_CLK_ENBIT(25)
+#define MT7620_CLKCFG1_UPHY1_CLK_ENBIT(22)
+#define RT_CLKCFG1_UPHY1_CLK_ENBIT(20)
+#define RT_CLKCFG1_UPHY0_CLK_ENBIT(18)
+
+#define USB_PHY_UTMI_8B60M BIT(1)
+#define UDEV_WAKEUPBIT(0)
+
+struct mt76x8_usb_phy {
+ u32 clk;
+ void __iomem*base;
+ struct regmap *sysctl;
+};
+
+static void u2_phy_w32(struct mt76x8_usb_phy *phy, u32 val, u32 reg)
+{
+ writel(val, phy->base + reg);
+}
+
+static u32 u2_phy_r32(struct mt76x8_usb_phy *phy, u32 reg)
+{
+ return readl(phy->base + reg);
+}
+
+static void mt76x8_usb_phy_init(struct mt76x8_usb_phy *phy)
+{
+ u2_phy_r32(phy, OFS_U2_PHY_AC2);
+ u2_phy_r32(phy, OFS_U2_PHY_ACR0);
+ u2_phy_r32(phy, OFS_U2_PHY_DCR0);
+
+ u2_phy_w32(phy, 0x0002, OFS_U2_PHY_DCR0);
+ u2_phy_r32(phy, OFS_U2_PHY_DCR0);
+ u2_phy_w32(phy, 0x0002, OFS_U2_PHY_DCR0);
+ u2_phy_r32(phy, OFS_U2_PHY_DCR0);
+ u2_phy_w32(phy, 0x0002, OFS_U2_PHY_DCR0);
+ u2_phy_r32(phy, OFS_U2_PHY_DCR0);
+ u2_phy_w32(phy, 0x0402, OFS_U2_PHY_DCR0);
+ u2_phy_r32(phy, OFS_U2_PHY_DCR0);
+ u2_phy_w32(phy, 0x0048086a, OFS_U2_PHY_AC0);
+ u2_phy_w32(phy, 0x441c, OFS_U2_PHY_AC1);
+ u2_phy_w32(phy, 0xc020, OFS_U2_PHY_ACR3);
+ u2_phy_w32(phy, 0x0200, OFS_U2_PHY_DTM0);
+}
+
+static int mt76x8_usb_phy_power_on(struct phy *_phy)
+{
+ struct
[U-Boot] [PATCH 2/2] mips: mt76xx: linkit-smart-7688: Enable USB and FS support
This patch enables USB and file-system support on the LinkIt smart MT7688 module for both, the normal and the RAM default config. Signed-off-by: Stefan Roese Cc: Daniel Schwierzeck --- configs/linkit-smart-7688-ram_defconfig | 14 +- configs/linkit-smart-7688_defconfig | 14 +- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/configs/linkit-smart-7688-ram_defconfig b/configs/linkit-smart-7688-ram_defconfig index 2d3ab7e35c..4cb1d7a603 100644 --- a/configs/linkit-smart-7688-ram_defconfig +++ b/configs/linkit-smart-7688-ram_defconfig @@ -20,17 +20,21 @@ CONFIG_CMD_MEMINFO=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set +CONFIG_CMD_PART=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_DOS_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set -CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_BLK=y CONFIG_CLK=y CONFIG_LED=y CONFIG_LED_BLINK=y @@ -46,6 +50,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_FIXED=y CONFIG_MT7628_ETH=y CONFIG_PHY=y +CONFIG_MT76X8_USB_PHY=y CONFIG_POWER_DOMAIN=y CONFIG_RAM=y CONFIG_DM_RESET=y @@ -54,5 +59,12 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_MT7621_SPI=y CONFIG_SYSRESET_SYSCON=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_FS_EXT4=y +CONFIG_FS_FAT=y CONFIG_LZMA=y CONFIG_LZO=y diff --git a/configs/linkit-smart-7688_defconfig b/configs/linkit-smart-7688_defconfig index ad34aaf640..dd157795bd 100644 --- a/configs/linkit-smart-7688_defconfig +++ b/configs/linkit-smart-7688_defconfig @@ -24,17 +24,21 @@ CONFIG_CMD_MEMINFO=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set +CONFIG_CMD_PART=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_DOS_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set -CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_BLK=y CONFIG_CLK=y CONFIG_LED=y CONFIG_LED_BLINK=y @@ -50,6 +54,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_FIXED=y CONFIG_MT7628_ETH=y CONFIG_PHY=y +CONFIG_MT76X8_USB_PHY=y CONFIG_POWER_DOMAIN=y CONFIG_RAM=y CONFIG_DM_RESET=y @@ -58,5 +63,12 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_MT7621_SPI=y CONFIG_SYSRESET_SYSCON=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_FS_EXT4=y +CONFIG_FS_FAT=y CONFIG_LZMA=y CONFIG_LZO=y -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1] dm: pinctrl: Remove obsolete function pinctrl_decode_pin_config_dm().
Hi Simon, any plans to get this merged? Thanks, Christoph > On 14.02.2019, at 02:54, Simon Glass wrote: > > On Tue, 12 Feb 2019 at 18:29, Christoph Muellner > wrote: >> >> This reverts commit 5ff776889212c080e3d1a33634ac904405ed6845. >> >> As noted in the comment, the function pinctrl_decode_pin_config_dm() >> only served as a temporary solution. >> >> Since the function has no users anymore, we can remove it again. >> >> Signed-off-by: Christoph Muellner >> >> --- >> >> drivers/pinctrl/pinctrl-uclass.c | 22 -- >> include/dm/pinctrl.h | 12 >> 2 files changed, 34 deletions(-) > > Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] How to enforce saveenv at boot
Hi Mark, On 05/04/19 13:13, Jonas Mark (BT-FIR/ENG1) wrote: > Hi, > > Our board stores the U-Boot environment in an MTD partition. I would like to > ensure that there is always an U-Boot environment stored in MTD so that the > userspace tool fw_setenv does not need to fall back on its built in default > environment or a default environment stored in a file (see > https://github.com/sbabic/libubootenv). > > When U-Boot starts up it checks whether the specified MTD partition contains > a valid environment and loads it. In case there is no valid environment it > will use the compiled in default. Is there already a feature in U-Boot which > would then also write that default to the MTD partition? > As far as I know, there is not (yet ?) a way to expose to the shell if the default environment is used, something like exporting gd->env_valid. > Alternatively a Hush script could help. Is there an easy way to detect that > U-Boot is using the compiled in environment? In that case I could simply do a > saveenv (?) which would then initialize the MTD environment partition. A trick (a hack ?) could be to have a variable in the default environment and you check and delete it if exists, maybe in your "preboot". if env_exists use_default;then setenv use_default;saveenv;fi I do not know if there is a better way to do this. Best regards, Stefano -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1] common: command: Add command execution tracer.
> On 05.04.2019, at 13:03, Christoph Muellner > wrote: > > When using boot scripts it can become quite hard to understand > which commands are actually executed during bootup (e.g. where > is a kernel image loaded from or which DTB is in use). > > Shell scripts suffer from a similar problem and many shells address > this problem with a command execution tracer (e.g. BASH has xtrace, > which can be enabled by "set -x"). > > This patch introduces a command tracer for U-Boot, which prints > every command with its arguments before it is executed. > > Signed-off-by: Christoph Muellner Reviewed-by: Philipp Tomsich ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] How to enforce saveenv at boot
Hi, Our board stores the U-Boot environment in an MTD partition. I would like to ensure that there is always an U-Boot environment stored in MTD so that the userspace tool fw_setenv does not need to fall back on its built in default environment or a default environment stored in a file (see https://github.com/sbabic/libubootenv). When U-Boot starts up it checks whether the specified MTD partition contains a valid environment and loads it. In case there is no valid environment it will use the compiled in default. Is there already a feature in U-Boot which would then also write that default to the MTD partition? Alternatively a Hush script could help. Is there an easy way to detect that U-Boot is using the compiled in environment? In that case I could simply do a saveenv (?) which would then initialize the MTD environment partition. Greetings, Mark Building Technologies, Panel Software Fire (BT-FIR/ENG1) Bosch Sicherheitssysteme GmbH | Postfach 11 11 | 85626 Grasbrunn | GERMANY | www.boschsecurity.com Sitz: Stuttgart, Registergericht: Amtsgericht Stuttgart HRB 23118 Aufsichtsratsvorsitzender: Christian Fischer; Geschäftsführung: Tanja Rückert, Andreas Bartz, Thomas Quante, Bernhard Schuster ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1] common: command: Add command execution tracer.
When using boot scripts it can become quite hard to understand
which commands are actually executed during bootup (e.g. where
is a kernel image loaded from or which DTB is in use).
Shell scripts suffer from a similar problem and many shells address
this problem with a command execution tracer (e.g. BASH has xtrace,
which can be enabled by "set -x").
This patch introduces a command tracer for U-Boot, which prints
every command with its arguments before it is executed.
Signed-off-by: Christoph Muellner
---
cmd/Kconfig | 11 +++
common/command.c | 14 ++
2 files changed, 25 insertions(+)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 0b07b3b9d77..eeadc3827cb 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -53,6 +53,17 @@ config SYS_PROMPT
This string is displayed in the command line to the left of the
cursor.
+config SYS_XTRACE
+ string "Command execution tracer"
+ depends on CMDLINE
+ default y if CMDLINE
+ help
+ This option enables the possiblity to print all commands before
+ executing them and after all variables are evaluated (similar
+ to Bash's xtrace/'set -x' feature).
+ To enable the tracer a variable "xtrace" needs to be defined in
+ the environment.
+
menu "Autoboot options"
config AUTOBOOT
diff --git a/common/command.c b/common/command.c
index e14d1fa1d6b..e192bb2a619 100644
--- a/common/command.c
+++ b/common/command.c
@@ -574,6 +574,20 @@ enum command_ret_t cmd_process(int flag, int argc, char *
const argv[],
enum command_ret_t rc = CMD_RET_SUCCESS;
cmd_tbl_t *cmdtp;
+#if defined(CONFIG_SYS_XTRACE)
+ char *xtrace;
+
+ xtrace = env_get("xtrace");
+ if (xtrace) {
+ puts("+");
+ for (int i = 0; i < argc; i++) {
+ puts(" ");
+ puts(argv[i]);
+ }
+ puts("\n");
+ }
+#endif
+
/* Look up command in command table */
cmdtp = find_cmd(argv[0]);
if (cmdtp == NULL) {
--
2.11.0
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Re: [U-Boot] [PATCH 1/3] i2c: muxes: pca954x: update list of supported devices
On 05. 04. 19 12:32, Luca Ceresoli wrote: > The Kconfig help has not been updated while adding PCA9547 and PCA9646. > > Signed-off-by: Luca Ceresoli > --- > drivers/i2c/muxes/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig > index b0da67ce2c6b..26be78f685de 100644 > --- a/drivers/i2c/muxes/Kconfig > +++ b/drivers/i2c/muxes/Kconfig > @@ -33,7 +33,7 @@ config I2C_MUX_PCA954x > I2C mux/switch devices. It is x width I2C multiplexer which enables to > partitioning I2C bus and connect multiple devices with the same > address > to the same I2C controller where driver handles proper routing to > - target i2c device. PCA9544 and PCA9548 are supported. > + target i2c device. PCA9544, PCA9547 PCA9548 and PCA9646 are supported. missing comma there. M > > config I2C_MUX_GPIO > tristate "GPIO-based I2C multiplexer" > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] i2c: muxes: pca954x: clarify enable field
On 05. 04. 19 12:32, Luca Ceresoli wrote:
> The chip_desc.enable field is used only for muxes, not tor switches.
typo tor.
M
> Document it and remove the unused values.
>
> Signed-off-by: Luca Ceresoli
> ---
> drivers/i2c/muxes/pca954x.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c
> index bd4e9abe5f3c..5669753ce14d 100644
> --- a/drivers/i2c/muxes/pca954x.c
> +++ b/drivers/i2c/muxes/pca954x.c
> @@ -22,7 +22,7 @@ enum pca_type {
> };
>
> struct chip_desc {
> - u8 enable;
> + u8 enable; /* Enable mask in ctl register (used for muxes only) */
> enum muxtype {
> pca954x_ismux = 0,
> pca954x_isswi,
> @@ -48,12 +48,10 @@ static const struct chip_desc chips[] = {
> .width = 8,
> },
> [PCA9548] = {
> - .enable = 0x8,
> .muxtype = pca954x_isswi,
> .width = 8,
> },
> [PCA9646] = {
> - .enable = 0x0,
> .muxtype = pca954x_isswi,
> .width = 4,
> },
>
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[U-Boot] [PATCH 3/3] i2c: muxes: pca954x: support PCA9543 I2C switch
The PCA9543 is a 2-channel I2C switch.
Signed-off-by: Luca Ceresoli
---
drivers/i2c/muxes/Kconfig | 10 +-
drivers/i2c/muxes/pca954x.c | 6 ++
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig
index 26be78f685de..7de4977c9c4a 100644
--- a/drivers/i2c/muxes/Kconfig
+++ b/drivers/i2c/muxes/Kconfig
@@ -29,11 +29,11 @@ config I2C_MUX_PCA954x
tristate "TI PCA954x I2C Mux/switches"
depends on I2C_MUX
help
- If you say yes here you get support for the TI PCA954x
- I2C mux/switch devices. It is x width I2C multiplexer which enables to
- partitioning I2C bus and connect multiple devices with the same
address
- to the same I2C controller where driver handles proper routing to
- target i2c device. PCA9544, PCA9547 PCA9548 and PCA9646 are supported.
+ If you say yes here you get support for the TI PCA954x I2C mux/switch
+ devices. It is x width I2C multiplexer which enables to partitioning
+ I2C bus and connect multiple devices with the same address to the same
+ I2C controller where driver handles proper routing to target i2c
+ device. PCA9543, PCA9544, PCA9547 PCA9548 and PCA9646 are supported.
config I2C_MUX_GPIO
tristate "GPIO-based I2C multiplexer"
diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c
index 5669753ce14d..a630ce991d04 100644
--- a/drivers/i2c/muxes/pca954x.c
+++ b/drivers/i2c/muxes/pca954x.c
@@ -15,6 +15,7 @@
DECLARE_GLOBAL_DATA_PTR;
enum pca_type {
+ PCA9543,
PCA9544,
PCA9547,
PCA9548,
@@ -37,6 +38,10 @@ struct pca954x_priv {
};
static const struct chip_desc chips[] = {
+ [PCA9543] = {
+ .muxtype = pca954x_isswi,
+ .width = 2,
+ },
[PCA9544] = {
.enable = 0x4,
.muxtype = pca954x_ismux,
@@ -87,6 +92,7 @@ static const struct i2c_mux_ops pca954x_ops = {
};
static const struct udevice_id pca954x_ids[] = {
+ { .compatible = "nxp,pca9543", .data = PCA9543 },
{ .compatible = "nxp,pca9544", .data = PCA9544 },
{ .compatible = "nxp,pca9547", .data = PCA9547 },
{ .compatible = "nxp,pca9548", .data = PCA9548 },
--
2.21.0
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[U-Boot] [PATCH 1/3] i2c: muxes: pca954x: update list of supported devices
The Kconfig help has not been updated while adding PCA9547 and PCA9646. Signed-off-by: Luca Ceresoli --- drivers/i2c/muxes/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig index b0da67ce2c6b..26be78f685de 100644 --- a/drivers/i2c/muxes/Kconfig +++ b/drivers/i2c/muxes/Kconfig @@ -33,7 +33,7 @@ config I2C_MUX_PCA954x I2C mux/switch devices. It is x width I2C multiplexer which enables to partitioning I2C bus and connect multiple devices with the same address to the same I2C controller where driver handles proper routing to - target i2c device. PCA9544 and PCA9548 are supported. + target i2c device. PCA9544, PCA9547 PCA9548 and PCA9646 are supported. config I2C_MUX_GPIO tristate "GPIO-based I2C multiplexer" -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/3] i2c: muxes: pca954x: clarify enable field
The chip_desc.enable field is used only for muxes, not tor switches.
Document it and remove the unused values.
Signed-off-by: Luca Ceresoli
---
drivers/i2c/muxes/pca954x.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c
index bd4e9abe5f3c..5669753ce14d 100644
--- a/drivers/i2c/muxes/pca954x.c
+++ b/drivers/i2c/muxes/pca954x.c
@@ -22,7 +22,7 @@ enum pca_type {
};
struct chip_desc {
- u8 enable;
+ u8 enable; /* Enable mask in ctl register (used for muxes only) */
enum muxtype {
pca954x_ismux = 0,
pca954x_isswi,
@@ -48,12 +48,10 @@ static const struct chip_desc chips[] = {
.width = 8,
},
[PCA9548] = {
- .enable = 0x8,
.muxtype = pca954x_isswi,
.width = 8,
},
[PCA9646] = {
- .enable = 0x0,
.muxtype = pca954x_isswi,
.width = 4,
},
--
2.21.0
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[U-Boot] Pull request: u-boot-imx u -boot-imx-201900405
Hi Tom, some fixes for release. Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/514637506 The following changes since commit 00102ae52055e294ac37ae1380f37620f4a8bb26: pico-imx7d: README: Recommend the usage of a USB hub (2019-03-31 20:19:19 +0200) are available in the Git repository at: git://www.denx.de/git/u-boot-imx.git tags/u-boot-imx-20190405 for you to fetch changes up to da60b4301c77fdc0ce16a4f6fb6dc04b69b6282c: DTS: Fix ETH PHY reset on HSC|DDC boards (imx53) (2019-04-02 13:44:18 +0200) Fixes for 2019.04 - fix bashism for MX8 - fix ethernet for MX53 - fix docs for i.MX8 Baruch Siach (1): tools/imx8m_image.sh: remove bashism Fabio Estevam (3): imx8mq_evk: README: Need to copy bl31.bin to U-Boot source tree imx8mq_evk: README: Fix a typo in the destination path imx8mq_evk: README: Make the underline marker fill the whole sentence Lukasz Majewski (3): cosmetic: config: Remove empty #ifdefs cosmetic: Remove not needed string from kp_imx53.h config DTS: Fix ETH PHY reset on HSC|DDC boards (imx53) arch/arm/dts/imx53-kp.dts | 2 +- board/freescale/imx8mq_evk/README | 15 --- include/configs/bg0900.h | 4 include/configs/dreamplug.h | 3 --- include/configs/ds109.h | 3 --- include/configs/km/km_arm.h | 3 --- include/configs/kp_imx53.h| 2 -- tools/imx8m_image.sh | 4 ++-- Best regards, Stefano -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] rk3288 SPL size
Hi, Am Freitag, 5. April 2019, 12:10:21 CEST schrieb Wadim Egorov: > it seems the new common rockchip pinctrl driver does not really fit into > our phycore-rk3288 SPL setup. It works for every other rk3288 based > board because they don't need special power configurations at the SPL stage. > > So my question is: is there any work going on to reduce the SPL size > even more? > > Besides that, I think I can remove the power stuff at the SPL stage from > our board. The SOM was redesigned and is equipped with an STM8 connected > to the RK818. The required setup we did before in the SPL is now done by > the ST controller. I know there are only a few SOMs without the STM8 out > in the wild. So if I remove it it will affect only a few people who > probably already have both boards. alternatively you could introduce a tpl-stage, similar to what Amarula does with their Vyasa board. With spl in ram there is obviously no size limitation anymore. But obviously if the power-fix isn't actually needed anymore, dropping it might be the easiest solution. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] rk3288 SPL size
Hi, it seems the new common rockchip pinctrl driver does not really fit into our phycore-rk3288 SPL setup. It works for every other rk3288 based board because they don't need special power configurations at the SPL stage. So my question is: is there any work going on to reduce the SPL size even more? Besides that, I think I can remove the power stuff at the SPL stage from our board. The SOM was redesigned and is equipped with an STM8 connected to the RK818. The required setup we did before in the SPL is now done by the ST controller. I know there are only a few SOMs without the STM8 out in the wild. So if I remove it it will affect only a few people who probably already have both boards. Regards, Wadim ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] spi: stm32_qspi: move to exec_op
We are facing issues in the driver since SPI NOR framework has moved
on SPI MEM framework, and SPI NAND framework is not running properly
with the current driver.
To be able to solve issues met on SPI NOR Flashes and to be able to
support SPI NAND Flashes, the driver has been reworked. We are now using
exec_op ops instead of using xfer ops.
Thanks to this rework, the driver has been successfully tested with:
- mx66l51235l SPI NOR Flash on stm32f746 SOC
- n25q128a SPI NOR Flash on stm32f769 SOC
- mx66l51235l SPI NOR Flash on stm32mp1 SOC
- mt29f2g01abagd SPI NAND Flash on stm32mp1 SOC
Signed-off-by: Christophe Kerello
---
drivers/spi/Kconfig | 3 +-
drivers/spi/stm32_qspi.c | 625 ++-
2 files changed, 245 insertions(+), 383 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 098372e..a700f24 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -222,8 +222,7 @@ config SPI_SUNXI
config STM32_QSPI
bool "STM32F7 QSPI driver"
- depends on STM32F7
- imply SPI_FLASH_BAR
+ depends on STM32F7 || ARCH_STM32MP
help
Enable the STM32F7 Quad-SPI (QSPI) driver. This driver can be
used to access the SPI NOR flash chips on platforms embedding
diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 8b60d7c..bb1067f 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -9,15 +9,11 @@
#include
#include
-#include
-#include
-#include
#include
-#include
-#include
-#include
-#include
+#include
+#include
#include
+#include
struct stm32_qspi_regs {
u32 cr; /* 0x00 */
@@ -45,8 +41,7 @@ struct stm32_qspi_regs {
#define STM32_QSPI_CR_SSHIFT BIT(4)
#define STM32_QSPI_CR_DFM BIT(6)
#define STM32_QSPI_CR_FSEL BIT(7)
-#define STM32_QSPI_CR_FTHRES_MASK GENMASK(4, 0)
-#define STM32_QSPI_CR_FTHRES_SHIFT (8)
+#define STM32_QSPI_CR_FTHRES_SHIFT 8
#define STM32_QSPI_CR_TEIE BIT(16)
#define STM32_QSPI_CR_TCIE BIT(17)
#define STM32_QSPI_CR_FTIE BIT(18)
@@ -55,16 +50,16 @@ struct stm32_qspi_regs {
#define STM32_QSPI_CR_APMS BIT(22)
#define STM32_QSPI_CR_PMM BIT(23)
#define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)
-#define STM32_QSPI_CR_PRESCALER_SHIFT (24)
+#define STM32_QSPI_CR_PRESCALER_SHIFT 24
/*
* QUADSPI device configuration register
*/
#define STM32_QSPI_DCR_CKMODE BIT(0)
#define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)
-#define STM32_QSPI_DCR_CSHT_SHIFT (8)
+#define STM32_QSPI_DCR_CSHT_SHIFT 8
#define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)
-#define STM32_QSPI_DCR_FSIZE_SHIFT (16)
+#define STM32_QSPI_DCR_FSIZE_SHIFT 16
/*
* QUADSPI status register
@@ -75,8 +70,6 @@ struct stm32_qspi_regs {
#define STM32_QSPI_SR_SMF BIT(3)
#define STM32_QSPI_SR_TOF BIT(4)
#define STM32_QSPI_SR_BUSY BIT(5)
-#define STM32_QSPI_SR_FLEVEL_MASK GENMASK(5, 0)
-#define STM32_QSPI_SR_FLEVEL_SHIFT (8)
/*
* QUADSPI flag clear register
@@ -92,388 +85,276 @@ struct stm32_qspi_regs {
#define STM32_QSPI_CCR_DDRMBIT(31)
#define STM32_QSPI_CCR_DHHCBIT(30)
#define STM32_QSPI_CCR_SIOOBIT(28)
-#define STM32_QSPI_CCR_FMODE_SHIFT (26)
-#define STM32_QSPI_CCR_DMODE_SHIFT (24)
-#define STM32_QSPI_CCR_DCYC_SHIFT (18)
-#define STM32_QSPI_CCR_DCYC_MASK GENMASK(4, 0)
-#define STM32_QSPI_CCR_ABSIZE_SHIFT(16)
-#define STM32_QSPI_CCR_ABMODE_SHIFT(14)
-#define STM32_QSPI_CCR_ADSIZE_SHIFT(12)
-#define STM32_QSPI_CCR_ADMODE_SHIFT(10)
-#define STM32_QSPI_CCR_IMODE_SHIFT (8)
-#define STM32_QSPI_CCR_INSTRUCTION_MASKGENMASK(7, 0)
-
-enum STM32_QSPI_CCR_IMODE {
- STM32_QSPI_CCR_IMODE_NONE = 0,
- STM32_QSPI_CCR_IMODE_ONE_LINE = 1,
- STM32_QSPI_CCR_IMODE_TWO_LINE = 2,
- STM32_QSPI_CCR_IMODE_FOUR_LINE = 3,
-};
-
-enum STM32_QSPI_CCR_ADMODE {
- STM32_QSPI_CCR_ADMODE_NONE = 0,
- STM32_QSPI_CCR_ADMODE_ONE_LINE = 1,
- STM32_QSPI_CCR_ADMODE_TWO_LINE = 2,
- STM32_QSPI_CCR_ADMODE_FOUR_LINE = 3,
-};
-
-enum STM32_QSPI_CCR_ADSIZE {
- STM32_QSPI_CCR_ADSIZE_8BIT = 0,
- STM32_QSPI_CCR_ADSIZE_16BIT = 1,
- STM32_QSPI_CCR_ADSIZE_24BIT = 2,
- STM32_QSPI_CCR_ADSIZE_32BIT = 3,
-};
-
-enum STM32_QSPI_CCR_ABMODE {
- STM32_QSPI_CCR_ABMODE_NONE = 0,
- STM32_QSPI_CCR_ABMODE_ONE_LINE = 1,
- STM32_QSPI_CCR_ABMODE_TWO_LINE = 2,
- STM32_QSPI_CCR_ABMODE_FOUR_LINE = 3,
-};
-
-enum STM32_QSPI_CCR_ABSIZE {
- STM32_QSPI_CCR_ABSIZE_8BIT = 0,
- STM32_QSPI_CCR_ABSIZE_16BIT = 1,
- STM32_QSPI_CCR_ABSIZE_24BIT = 2,
- STM32_QSPI_CCR_ABSIZE_32BIT = 3,
-};
-
-enum STM32_QSPI_CCR_DMODE {
- STM32_QSPI_CCR_DMODE_NONE = 0,
- STM32_QSPI_CCR_DMODE_ONE_LINE = 1,
-
[U-Boot] [PATCH v2 1/2] dt-bindings: mtd: stm32_fmc2: add STM32 FMC2 NAND controller documentation
This patch adds the documentation of the device tree bindings for the STM32
FMC2 NAND controller.
Signed-off-by: Christophe Kerello
---
Changes in v2: None
doc/device-tree-bindings/mtd/stm32-fmc2-nand.txt | 59
1 file changed, 59 insertions(+)
create mode 100644 doc/device-tree-bindings/mtd/stm32-fmc2-nand.txt
diff --git a/doc/device-tree-bindings/mtd/stm32-fmc2-nand.txt
b/doc/device-tree-bindings/mtd/stm32-fmc2-nand.txt
new file mode 100644
index 000..70e76be
--- /dev/null
+++ b/doc/device-tree-bindings/mtd/stm32-fmc2-nand.txt
@@ -0,0 +1,59 @@
+STMicroelectronics Flexible Memory Controller 2 (FMC2)
+NAND Interface
+
+Required properties:
+- compatible: Should be one of:
+ * st,stm32mp15-fmc2
+- reg: NAND flash controller memory areas.
+ First region contains the register location.
+ Regions 2 to 4 respectively contain the data, command,
+ and address space for CS0.
+ Regions 5 to 7 contain the same areas for CS1.
+- interrupts: The interrupt number
+- pinctrl-0: Standard Pinctrl phandle (see: pinctrl/pinctrl-bindings.txt)
+- clocks: The clock needed by the NAND flash controller
+
+Optional properties:
+- resets: Reference to a reset controller asserting the FMC controller
+- dmas: DMA specifiers (see: dma/stm32-mdma.txt)
+- dma-names: Must be "tx", "rx" and "ecc"
+
+Optional children nodes:
+Children nodes represent the available NAND chips.
+
+Optional properties:
+- nand-on-flash-bbt: see nand.txt
+- nand-ecc-strength: see nand.txt
+- nand-ecc-step-size: see nand.txt
+
+The following ECC strength and step size are currently supported:
+ - nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Hamming)
+ - nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4)
+ - nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8) (default)
+
+Example:
+
+ fmc: nand-controller@58002000 {
+ compatible = "st,stm32mp15-fmc2";
+ reg = <0x58002000 0x1000>,
+ <0x8000 0x1000>,
+ <0x8801 0x1000>,
+ <0x8802 0x1000>,
+ <0x8100 0x1000>,
+ <0x8901 0x1000>,
+ <0x8902 0x1000>;
+ interrupts = ;
+ clocks = < FMC_K>;
+ resets = < FMC_R>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
--
1.9.1
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[U-Boot] [PATCH v2 2/2] mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver
The driver adds the support for the STMicroelectronics FMC2 NAND Controller found on STM32MP SOCs. This patch adds the polling mode, a basic mode that do not need any DMA channels. Only NAND_ECC_HW mode is actually supported. The driver supports a maximum 8k page size. The following ECC strength and step size are currently supported: - nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8) - nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4) - nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Extended ECC based on Hamming) This patch has been tested on Micron MT29F8G08ABACAH4. Signed-off-by: Christophe Kerello --- Changes in v2: - fix oob free offset drivers/mtd/nand/raw/Kconfig | 11 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/stm32_fmc2_nand.c | 1092 3 files changed, 1104 insertions(+) create mode 100644 drivers/mtd/nand/raw/stm32_fmc2_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 7f76e5e..dc087ab 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -256,6 +256,17 @@ config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS This flag prevent U-boot reconfigure NAND flash controller and reuse the NAND timing from 1st stage bootloader. +config NAND_STM32_FMC2 + bool "Support for NAND controller on STM32MP SoCs" + depends on ARCH_STM32MP + select SYS_NAND_SELF_INIT + imply CMD_NAND + help + Enables support for NAND Flash chips on SoCs containing the FMC2 + NAND controller. This controller is found on STM32MP SoCs. + The controller supports a maximum 8k page size and supports + a maximum 8-bit correction error per sector of 512 bytes. + comment "Generic NAND options" config SYS_NAND_BLOCK_SIZE diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index c61e3f3..b10e718 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o obj-$(CONFIG_NAND_PLAT) += nand_plat.o obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o +obj-$(CONFIG_NAND_STM32_FMC2) += stm32_fmc2_nand.o else # minimal SPL drivers diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c new file mode 100644 index 000..2bb749d --- /dev/null +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -0,0 +1,1092 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) STMicroelectronics 2019 + * Author: Christophe Kerello + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Bad block marker length */ +#define FMC2_BBM_LEN 2 + +/* ECC step size */ +#define FMC2_ECC_STEP_SIZE 512 + +/* Command delay */ +#define FMC2_RB_DELAY_US 30 + +/* Max chip enable */ +#define FMC2_MAX_CE2 + +/* Timings */ +#define FMC2_THIZ 1 +#define FMC2_TIO 8000 +#define FMC2_TSYNC 3000 +#define FMC2_PCR_TIMING_MASK 0xf +#define FMC2_PMEM_PATT_TIMING_MASK 0xff + +/* FMC2 Controller Registers */ +#define FMC2_BCR1 0x0 +#define FMC2_PCR 0x80 +#define FMC2_SR0x84 +#define FMC2_PMEM 0x88 +#define FMC2_PATT 0x8c +#define FMC2_HECCR 0x94 +#define FMC2_BCHISR0x254 +#define FMC2_BCHICR0x258 +#define FMC2_BCHPBR1 0x260 +#define FMC2_BCHPBR2 0x264 +#define FMC2_BCHPBR3 0x268 +#define FMC2_BCHPBR4 0x26c +#define FMC2_BCHDSR0 0x27c +#define FMC2_BCHDSR1 0x280 +#define FMC2_BCHDSR2 0x284 +#define FMC2_BCHDSR3 0x288 +#define FMC2_BCHDSR4 0x28c + +/* Register: FMC2_BCR1 */ +#define FMC2_BCR1_FMC2EN BIT(31) + +/* Register: FMC2_PCR */ +#define FMC2_PCR_PWAITEN BIT(1) +#define FMC2_PCR_PBKEN BIT(2) +#define FMC2_PCR_PWID_MASK GENMASK(5, 4) +#define FMC2_PCR_PWID(x) (((x) & 0x3) << 4) +#define FMC2_PCR_PWID_BUSWIDTH_8 0 +#define FMC2_PCR_PWID_BUSWIDTH_16 1 +#define FMC2_PCR_ECCEN BIT(6) +#define FMC2_PCR_ECCALGBIT(8) +#define FMC2_PCR_TCLR_MASK GENMASK(12, 9) +#define FMC2_PCR_TCLR(x) (((x) & 0xf) << 9) +#define FMC2_PCR_TCLR_DEFAULT 0xf +#define FMC2_PCR_TAR_MASK GENMASK(16, 13) +#define FMC2_PCR_TAR(x)(((x) & 0xf) << 13) +#define FMC2_PCR_TAR_DEFAULT 0xf +#define FMC2_PCR_ECCSS_MASKGENMASK(19, 17) +#define FMC2_PCR_ECCSS(x) (((x) &
[U-Boot] [PATCH v2 0/2] mtd: rawnand: add STM32 FMC2 NAND flash controller driver
This patchset adds the support for the STMicroelectronics FMC2 NAND flash controller found on STM32MP SOCs. This patchset supports: - the polling mode feature - a maximum 8k page size - following ECC strength and step size - nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8) - nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4) - nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Extended ecc based on HAMMING) This patchset has been tested on Micron MT29F8G08ABACAH4 (8-bit SLC NAND). Changes in v2: - fix oob free offset Christophe Kerello (2): dt-bindings: mtd: stm32_fmc2: add STM32 FMC2 NAND controller documentation mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver doc/device-tree-bindings/mtd/stm32-fmc2-nand.txt | 59 ++ drivers/mtd/nand/raw/Kconfig | 11 + drivers/mtd/nand/raw/Makefile|1 + drivers/mtd/nand/raw/stm32_fmc2_nand.c | 1092 ++ 4 files changed, 1163 insertions(+) create mode 100644 doc/device-tree-bindings/mtd/stm32-fmc2-nand.txt create mode 100644 drivers/mtd/nand/raw/stm32_fmc2_nand.c -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] mtd: spi: Improve data write functionality
Incorporate write enable and status check in the write data
function itself.
Formerly, Write data function used to break the data to be
written into smaller chunks and used to send the smaller
chunks without write enable or status check for every iteration.
Signed-off-by: Rajat Srivastava
---
While writing any data to a SPI flash every write transaction
shall be preceded by a WRITE_ENABLE command and shall be
followed by a READ_STATUS process (to check if the flash is
not busy).
This sequence can be roughly represented as:
1. write_enable //issue write enable command
2. execute_write_operation //write data to flash or register
3. spi_nor_wait_till_ready //read status of flash
The current framework has two types of write operation:
1. write to register (nor->write_reg)
2. write data to flash memory (nor->write)
There seems to be an issue in writing data to flash memory for which
the framework uses spi_nor_write_data() function.
Before every call to spi_nor_write_data() function the framework
sends a WRITE_ENABLE command and later checks if the flash is busy.
However, the spi_nor_write_data() function which executes the data
write to flash, breaks the data into smaller chunks. For all of
these small transactions there is only a single WRITE_ENABLE
command issued and a single check made for status, which breaks
the write operation. Only the first chunk of the whole data is
successfully written on to the flash.
This patch fixes the bug making the spi_nor_write_data() function
issue WRITE_ENABLE command and status checks with every write
transactions.
Without this patch write in fsl_qspi.c driver is broken.
drivers/mtd/spi/spi-nor-core.c | 30 +-
1 file changed, 9 insertions(+), 21 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index c4e2f6a08f..757163369b 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -23,6 +23,9 @@
#include "sf_internal.h"
+static int spi_nor_wait_till_ready(struct spi_nor *nor);
+static int write_enable(struct spi_nor *nor);
+
/* Define max times to check status register before we give up. */
/*
@@ -128,6 +131,8 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor,
loff_t to, size_t len,
op.addr.nbytes = 0;
while (remaining) {
+ write_enable(nor);
+
op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
ret = spi_mem_adjust_op_size(nor->spi, );
if (ret)
@@ -137,6 +142,10 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor,
loff_t to, size_t len,
if (ret)
return ret;
+ ret = spi_nor_wait_till_ready(nor);
+ if (ret)
+ return ret;
+
op.addr.val += op.data.nbytes;
remaining -= op.data.nbytes;
op.data.buf.out += op.data.nbytes;
@@ -961,14 +970,10 @@ static int sst_write_byteprogram(struct spi_nor *nor,
loff_t to, size_t len,
for (actual = 0; actual < len; actual++) {
nor->program_opcode = SPINOR_OP_BP;
- write_enable(nor);
/* write one byte. */
ret = nor->write(nor, to, 1, buf + actual);
if (ret < 0)
goto sst_write_err;
- ret = spi_nor_wait_till_ready(nor);
- if (ret)
- goto sst_write_err;
to++;
}
@@ -989,8 +994,6 @@ static int sst_write(struct mtd_info *mtd, loff_t to,
size_t len,
if (spi->mode & SPI_TX_BYTE)
return sst_write_byteprogram(nor, to, len, retlen, buf);
- write_enable(nor);
-
nor->sst_write_second = false;
actual = to % 2;
@@ -1002,9 +1005,6 @@ static int sst_write(struct mtd_info *mtd, loff_t to,
size_t len,
ret = nor->write(nor, to, 1, buf);
if (ret < 0)
goto sst_write_err;
- ret = spi_nor_wait_till_ready(nor);
- if (ret)
- goto sst_write_err;
}
to += actual;
@@ -1016,9 +1016,6 @@ static int sst_write(struct mtd_info *mtd, loff_t to,
size_t len,
ret = nor->write(nor, to, 2, buf + actual);
if (ret < 0)
goto sst_write_err;
- ret = spi_nor_wait_till_ready(nor);
- if (ret)
- goto sst_write_err;
to += 2;
nor->sst_write_second = true;
}
@@ -1031,15 +1028,10 @@ static int sst_write(struct mtd_info *mtd, loff_t to,
size_t len,
/* Write out trailing byte if it exists. */
if (actual != len) {
- write_enable(nor);
-
nor->program_opcode = SPINOR_OP_BP;
ret = nor->write(nor, to, 1, buf + actual);
if (ret < 0)
goto
Re: [U-Boot] [PATCH v2 2/3] ARM: dts: dra71-evm: Correct evm_sd regulator max voltage
On 4/5/2019 2:18 PM, Faiz Abbas wrote:
Correct vpo_sd_1v8_3v3 regulator max voltage to 3.3V
Reviewed-by: Keerthy
Signed-off-by: Faiz Abbas
---
arch/arm/dts/dra71-evm.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/dra71-evm.dts b/arch/arm/dts/dra71-evm.dts
index 41c9132eb5..64363f75c0 100644
--- a/arch/arm/dts/dra71-evm.dts
+++ b/arch/arm/dts/dra71-evm.dts
@@ -24,13 +24,13 @@
regulator-name = "vddshv8";
regulator-min-microvolt = <180>;
- regulator-max-microvolt = <300>;
+ regulator-max-microvolt = <330>;
regulator-boot-on;
vin-supply = <_5v0>;
gpios = < 11 GPIO_ACTIVE_HIGH>;
states = <180 0x0
- 300 0x1>;
+ 330 0x1>;
};
evm_1v8_sw: fixedregulator-evm_1v8 {
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[U-Boot] [PATCH v2 3/3] mmc: omap_hsmmc: Set 3.3V for IO voltage
Pbias voltage should match the IO voltage set for the SD card. With the
latest pbias change to 3.3V, update the capabilities and IO voltages
settings to 3.3V.
Signed-off-by: Faiz Abbas
---
drivers/mmc/omap_hsmmc.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 826a39fad7..133cdc1352 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -264,7 +264,7 @@ static unsigned char mmc_board_init(struct mmc *mmc)
!CONFIG_IS_ENABLED(DM_REGULATOR)
/* PBIAS config needed for MMC1 only */
if (mmc_get_blk_desc(mmc)->devnum == 0)
- vmmc_pbias_config(LDO_VOLT_3V0);
+ vmmc_pbias_config(LDO_VOLT_3V3);
#endif
return 0;
@@ -418,7 +418,7 @@ static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint
signal_voltage)
switch (signal_voltage) {
case MMC_SIGNAL_VOLTAGE_330:
- hctl |= SDVS_3V0;
+ hctl |= SDVS_3V3;
break;
case MMC_SIGNAL_VOLTAGE_180:
hctl |= SDVS_1V8;
@@ -514,10 +514,9 @@ static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
return -EINVAL;
if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
- /* Use 3.0V rather than 3.3V */
- mv = 3000;
- capa_mask = VS30_3V0SUP;
- palmas_ldo_volt = LDO_VOLT_3V0;
+ mv = 3300;
+ capa_mask = VS33_3V3SUP;
+ palmas_ldo_volt = LDO_VOLT_3V3;
} else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
capa_mask = VS18_1V8SUP;
palmas_ldo_volt = LDO_VOLT_1V8;
@@ -556,13 +555,13 @@ static uint32_t omap_hsmmc_set_capabilities(struct mmc
*mmc)
val = readl(_base->capa);
if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
- val |= (VS30_3V0SUP | VS18_1V8SUP);
+ val |= (VS33_3V3SUP | VS18_1V8SUP);
} else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
- val |= VS30_3V0SUP;
+ val |= VS33_3V3SUP;
val &= ~VS18_1V8SUP;
} else {
val |= VS18_1V8SUP;
- val &= ~VS30_3V0SUP;
+ val &= ~VS33_3V3SUP;
}
writel(val, _base->capa);
@@ -842,11 +841,11 @@ static int omap_hsmmc_init_setup(struct mmc *mmc)
#if CONFIG_IS_ENABLED(DM_MMC)
reg_val = omap_hsmmc_set_capabilities(mmc);
- omap_hsmmc_conf_bus_power(mmc, (reg_val & VS30_3V0SUP) ?
+ omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
#else
writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, _base->hctl);
- writel(readl(_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
+ writel(readl(_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
_base->capa);
#endif
--
2.19.2
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[U-Boot] [PATCH v2 1/3] ARM: dts: dra7: Change pbias voltage to 3.3V
As per recent TRM[1], PBIAS cell on dra7 devices supports
3.3v and not 3.0v as documented earlier.
Update PBIAS regulator max voltage and the voltage written
in the driver to reflect this.
[1] http://www.ti.com/lit/pdf/sprui30
Signed-off-by: Faiz Abbas
---
arch/arm/dts/dra7.dtsi| 2 +-
drivers/power/regulator/pbias_regulator.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index 0f982d8b44..fd1aea0b1b 100644
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -170,7 +170,7 @@
pbias_mmc_reg: pbias_mmc_omap5 {
regulator-name =
"pbias_mmc_omap5";
regulator-min-microvolt
= <180>;
- regulator-max-microvolt
= <300>;
+ regulator-max-microvolt
= <330>;
};
};
diff --git a/drivers/power/regulator/pbias_regulator.c
b/drivers/power/regulator/pbias_regulator.c
index 4ed3c94e03..88dc9f273a 100644
--- a/drivers/power/regulator/pbias_regulator.c
+++ b/drivers/power/regulator/pbias_regulator.c
@@ -238,7 +238,7 @@ static int pbias_regulator_set_value(struct udevice *dev,
int uV)
if (rc)
return rc;
- if (uV == 300)
+ if (uV == 330)
reg |= p->vmode;
else if (uV == 180)
reg &= ~p->vmode;
--
2.19.2
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[U-Boot] [PATCH v2 2/3] ARM: dts: dra71-evm: Correct evm_sd regulator max voltage
Correct vpo_sd_1v8_3v3 regulator max voltage to 3.3V
Signed-off-by: Faiz Abbas
---
arch/arm/dts/dra71-evm.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/dra71-evm.dts b/arch/arm/dts/dra71-evm.dts
index 41c9132eb5..64363f75c0 100644
--- a/arch/arm/dts/dra71-evm.dts
+++ b/arch/arm/dts/dra71-evm.dts
@@ -24,13 +24,13 @@
regulator-name = "vddshv8";
regulator-min-microvolt = <180>;
- regulator-max-microvolt = <300>;
+ regulator-max-microvolt = <330>;
regulator-boot-on;
vin-supply = <_5v0>;
gpios = < 11 GPIO_ACTIVE_HIGH>;
states = <180 0x0
- 300 0x1>;
+ 330 0x1>;
};
evm_1v8_sw: fixedregulator-evm_1v8 {
--
2.19.2
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[U-Boot] [PATCH v2 0/3] Update pbias and IO voltage in dra7 and am57 devices
The following patches update pbias and IO voltages in TI's dra7 and am57 devices. Tested on: dra71x-evm, dra72x-evm, dra7xx-evm, dra76x-evm, am57xx-evm, am571-idk, am572-idk, am574-idk, am335x-evm. v2: Added patch for fixing voltage in dra71-evm. Faiz Abbas (3): ARM: dts: dra7: Change pbias voltage to 3.3V ARM: dts: dra71-evm: Correct evm_sd regulator max voltage mmc: omap_hsmmc: Set 3.3V for IO voltage arch/arm/dts/dra7.dtsi| 2 +- arch/arm/dts/dra71-evm.dts| 4 ++-- drivers/mmc/omap_hsmmc.c | 21 ++--- drivers/power/regulator/pbias_regulator.c | 2 +- 4 files changed, 14 insertions(+), 15 deletions(-) -- 2.19.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] drivers: net: mc: Report extra memory to Linux
MC firmware need to be aligned to 512M, so minimum 512MB DDR is reserved.
But MC support to work with 128MB or 256MB DDR memory also, in this
case, rest of the memory is not usable.
So reporting this extra memory to Linux through dtb memory fixup.
Signed-off-by: Meenakshi Aggarwal
---
board/freescale/ls1088a/ls1088a.c | 31 ---
board/freescale/ls2080ardb/ls2080ardb.c | 32 +---
board/freescale/lx2160a/lx2160a.c | 31 ---
drivers/net/fsl-mc/mc.c | 10 ++
include/fsl-mc/fsl_mc.h | 1 +
5 files changed, 96 insertions(+), 9 deletions(-)
diff --git a/board/freescale/ls1088a/ls1088a.c
b/board/freescale/ls1088a/ls1088a.c
index 6d11a13..96f0871 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -738,11 +738,26 @@ void fsl_fdt_fixup_flash(void *fdt)
int ft_board_setup(void *blob, bd_t *bd)
{
int i;
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
+ bool mc_memory_bank = false;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
ft_cpu_setup(blob, bd);
+ fdt_fixup_mc_ddr(_memory_base, _memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank = true;
+
+ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+ base = calloc(total_memory_banks, sizeof(u64));
+ size = calloc(total_memory_banks, sizeof(u64));
+
/* fixup DT for the two GPP DDR banks */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
base[i] = gd->bd->bi_dram[i].start;
@@ -759,7 +774,17 @@ int ft_board_setup(void *blob, bd_t *bd)
size[1] = gd->arch.resv_ram - base[1];
#endif
- fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+ if (mc_memory_base != 0) {
+ for (i = 0; i <= total_memory_banks; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = mc_memory_base;
+ size[i] = mc_memory_size;
+ break;
+ }
+ }
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
fdt_fsl_mc_fixup_iommu_map_entry(blob);
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c
b/board/freescale/ls2080ardb/ls2080ardb.c
index ce419df..3af83f9 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -409,11 +409,27 @@ void fsl_fdt_fixup_flash(void *fdt)
int ft_board_setup(void *blob, bd_t *bd)
{
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
+ int i;
+ bool mc_memory_bank = false;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
ft_cpu_setup(blob, bd);
+ fdt_fixup_mc_ddr(_memory_base, _memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank = true;
+
+ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+ base = calloc(total_memory_banks, sizeof(u64));
+ size = calloc(total_memory_banks, sizeof(u64));
+
/* fixup DT for the two GPP DDR banks */
base[0] = gd->bd->bi_dram[0].start;
size[0] = gd->bd->bi_dram[0].size;
@@ -430,7 +446,17 @@ int ft_board_setup(void *blob, bd_t *bd)
size[1] = gd->arch.resv_ram - base[1];
#endif
- fdt_fixup_memory_banks(blob, base, size, 2);
+ if (mc_memory_base != 0) {
+ for (i = 0; i <= total_memory_banks; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = mc_memory_base;
+ size[i] = mc_memory_size;
+ break;
+ }
+ }
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
fdt_fsl_mc_fixup_iommu_map_entry(blob);
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index 3875d04..93b5204 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -520,11 +520,26 @@ void board_quiesce_devices(void)
int ft_board_setup(void *blob, bd_t *bd)
{
int i;
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
+ bool mc_memory_bank = false;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
ft_cpu_setup(blob, bd);
+ fdt_fixup_mc_ddr(_memory_base, _memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank = true;
+
+ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+ base =
[U-Boot] [PATCH 2/8] spl: atf: add arm32 variant
ATF can also support arm32 socs with being a bl32 payload either
including optee or the minimal sp_min payload included in ATF itself.
So add the necessary infrasturcture to jump into ATF as bl32 from spl
which then will jump into the real u-boot.
We keep using the arm64 datastructures because, while they are named
bl31_*, the only difference is not populating the bl31-related fields
and making the bl32 ones mandatory, so there really is no need to
redefine all of them simply to drop the empty bl31 parts.
Signed-off-by: Heiko Stuebner
---
common/spl/Kconfig | 2 +-
common/spl/spl_atf.c | 86 ++--
include/atf_common.h | 52 +++
3 files changed, 137 insertions(+), 3 deletions(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 206c24076d..ba39c17cf2 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -886,7 +886,7 @@ config SPL_YMODEM_SUPPORT
config SPL_ATF
bool "Support ARM Trusted Firmware"
- depends on ARM64
+ depends on ARM || ARM64
help
ATF(ARM Trusted Firmware) is a component for ARM AArch64 which
is loaded by SPL (which is considered as BL2 in ATF terminology).
diff --git a/common/spl/spl_atf.c b/common/spl/spl_atf.c
index cddab6a735..2fbec29b73 100644
--- a/common/spl/spl_atf.c
+++ b/common/spl/spl_atf.c
@@ -17,6 +17,9 @@
static struct bl2_to_bl31_params_mem bl31_params_mem;
static struct bl31_params *bl2_to_bl31_params;
+typedef void (*atf_entry_t)(struct bl31_params *params, void *plat_params);
+
+#ifdef CONFIG_ARM64
/**
* bl2_plat_get_bl31_params() - prepare params for bl31.
*
@@ -83,8 +86,6 @@ static inline void raw_write_daif(unsigned int daif)
__asm__ __volatile__("msr DAIF, %0\n\t" : : "r" (daif) : "memory");
}
-typedef void (*atf_entry_t)(struct bl31_params *params, void *plat_params);
-
static void bl31_entry(uintptr_t bl31_entry, uintptr_t bl33_entry,
uintptr_t fdt_addr)
{
@@ -98,6 +99,83 @@ static void bl31_entry(uintptr_t bl31_entry, uintptr_t
bl33_entry,
atf_entry((void *)bl31_params, (void *)fdt_addr);
}
+#else /* CONFIG_ARM64 */
+static struct bl31_params *bl2_plat_get_bl32_params(uintptr_t bl33_entry)
+{
+ struct entry_point_info *bl33_ep_info;
+
+ /*
+* Initialise the memory for all the arguments that needs to
+* be passed to BL31
+*/
+ memset(_params_mem, 0, sizeof(struct bl2_to_bl31_params_mem));
+
+ /* Assign memory for TF related information */
+ bl2_to_bl31_params = _params_mem.bl31_params;
+ SET_PARAM_HEAD(bl2_to_bl31_params, ATF_PARAM_BL31, ATF_VERSION_1, 0);
+
+ /* Fill BL31 related information */
+ SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info,
+ ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0);
+
+ /* Fill BL32 related information */
+ bl2_to_bl31_params->bl32_ep_info = _params_mem.bl32_ep_info;
+ SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, ATF_PARAM_EP,
+ ATF_VERSION_1, 0);
+ bl2_to_bl31_params->bl32_image_info = _params_mem.bl32_image_info;
+ SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info,
+ ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0);
+
+ /* Fill BL33 related information */
+ bl2_to_bl31_params->bl33_ep_info = _params_mem.bl33_ep_info;
+ bl33_ep_info = _params_mem.bl33_ep_info;
+ SET_PARAM_HEAD(bl33_ep_info, ATF_PARAM_EP, ATF_VERSION_1,
+ ATF_EP_NON_SECURE);
+
+ /* BL33 expects to receive the primary CPU MPID (through r0) */
+ bl33_ep_info->args.arg0 = 0x & read_mpidr();
+ bl33_ep_info->pc = bl33_entry;
+ bl33_ep_info->spsr = SPSR_MODE32(MODE32_hyp,
+SPSR_T_ARM,
+#ifdef __ARMEB__
+SPSR_E_BIG,
+#else
+SPSR_E_LITTLE,
+#endif
+DISABLE_ALL_EXECPTIONS);
+
+ bl2_to_bl31_params->bl33_image_info = _params_mem.bl33_image_info;
+ SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info,
+ ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0);
+
+ return bl2_to_bl31_params;
+}
+
+static inline void raw_write_aif(unsigned int aif)
+{
+ unsigned int val;
+
+ val = get_cpsr();
+ val &= ~SPSR_EXCEPTION_MASK;
+ val |= aif;
+
+ __asm__ __volatile__("msr cpsr_c, %0\n\t" : : "r" (val) );
+}
+
+static void bl32_entry(uintptr_t bl32_entry, uintptr_t bl33_entry,
+ uintptr_t fdt_addr)
+{
+ struct bl31_params *bl31_params;
+ atf_entry_t atf_entry = (atf_entry_t)bl32_entry;
+
+ bl31_params = bl2_plat_get_bl32_params(bl33_entry);
+
+ raw_write_aif(SPSR_EXCEPTION_MASK);
+ dcache_disable();
+
+ atf_entry((void *)bl31_params, (void *)fdt_addr);
+}
+#endif /* CONFIG_ARM64 */
static int
[U-Boot] [PATCH 5/8] rockchip: rk3288: reserve first 2MB when build with ATF support
ATF resides in the first 2MB of ram and will also protect this
area from non-secure access.
So similar to other Rockchip socs keep this area from the usable ram.
Signed-off-by: Heiko Stuebner
---
arch/arm/mach-rockchip/rk3288/rk3288.c | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c
b/arch/arm/mach-rockchip/rk3288/rk3288.c
index a725abc5a5..678ab0de65 100644
--- a/arch/arm/mach-rockchip/rk3288/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
@@ -2,11 +2,27 @@
/*
* Copyright (c) 2016 Rockchip Electronics Co., Ltd
*/
+#include
#include
#include
+DECLARE_GLOBAL_DATA_PTR;
+
#define GRF_SOC_CON2 0xff77024c
+int dram_init_banksize(void)
+{
+#ifdef CONFIG_SPL_ATF
+ size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
+
+ /* Reserve 0x20 for ATF bl32 */
+ gd->bd->bi_dram[0].start = 0x020;
+ gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
+#endif
+
+ return 0;
+}
+
int arch_cpu_init(void)
{
/* We do some SoC one time setting here. */
--
2.20.1
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[U-Boot] [PATCH 1/8] arm: v7: add read_mpidr function for arm32
Function to get the contents of the mpidr register, similar to
its arm64 counterpart.
Signed-off-by: Heiko Stuebner
---
arch/arm/include/asm/system.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index aed2e3c51e..b5332f4347 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -364,6 +364,15 @@ static inline int is_hyp(void)
#endif
}
+static inline unsigned long read_mpidr(void)
+{
+ unsigned long val;
+
+ asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
+
+ return val;
+}
+
static inline unsigned int get_cr(void)
{
unsigned int val;
--
2.20.1
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[U-Boot] [PATCH 6/8] rockchip: rk3288: split evb into its two entities
There are actual 2 variants of the rk3288-evb in existence, mainly
differing by their pmic. The one currently in u-boot is using the
act8846 + syr827 ics for power regulation, while the other variant
uses Rockchip's own rk808.
To be able to use u-boot on both, add separate configs and sync down
the devicetrees from the Linux kernel for both variants.
As per [0] the SPDX license designation updated a bit as well
to match the actual licensing.
[0]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=fce152a63d9597c108c10a0eb7a71f1edfc9d42e
Signed-off-by: Heiko Stuebner
---
arch/arm/dts/Makefile | 3 +-
...evb.dts => rk3288-evb-act8846-u-boot.dtsi} | 33 +-
arch/arm/dts/rk3288-evb-act8846.dts | 188 +++
arch/arm/dts/rk3288-evb-rk808-u-boot.dtsi | 40 ++
arch/arm/dts/rk3288-evb-rk808.dts | 202 +++
arch/arm/dts/rk3288-evb.dtsi | 493 --
...defconfig => evb-rk3288-act8846_defconfig} | 4 +-
configs/evb-rk3288-rk808_defconfig| 87
8 files changed, 738 insertions(+), 312 deletions(-)
rename arch/arm/dts/{rk3288-evb.dts => rk3288-evb-act8846-u-boot.dtsi} (64%)
create mode 100644 arch/arm/dts/rk3288-evb-act8846.dts
create mode 100644 arch/arm/dts/rk3288-evb-rk808-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3288-evb-rk808.dts
rename configs/{evb-rk3288_defconfig => evb-rk3288-act8846_defconfig} (95%)
create mode 100644 configs/evb-rk3288-rk808_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0e2ffdb87f..edbfc34076 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -65,7 +65,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3128-evb.dtb \
rk3188-radxarock.dtb \
rk3229-evb.dtb \
- rk3288-evb.dtb \
+ rk3288-evb-act8846.dtb \
+ rk3288-evb-rk808.dtb \
rk3288-fennec.dtb \
rk3288-firefly.dtb \
rk3288-miqi.dtb \
diff --git a/arch/arm/dts/rk3288-evb.dts
b/arch/arm/dts/rk3288-evb-act8846-u-boot.dtsi
similarity index 64%
rename from arch/arm/dts/rk3288-evb.dts
rename to arch/arm/dts/rk3288-evb-act8846-u-boot.dtsi
index 575de44c05..ee49d3787d 100644
--- a/arch/arm/dts/rk3288-evb.dts
+++ b/arch/arm/dts/rk3288-evb-act8846-u-boot.dtsi
@@ -1,20 +1,8 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
+// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
*/
-/dts-v1/;
-#include "rk3288-evb.dtsi"
-
-/ {
- model = "Evb-RK3288";
- compatible = "evb-rk3288,evb-rk3288", "rockchip,rk3288";
-
- chosen {
- stdout-path =
- };
-};
-
{
rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
@@ -26,31 +14,26 @@
rockchip,sdram-params = <0x20d266a4 0x5b6 2 53300 6 9 0>;
};
- {
+ {
u-boot,dm-pre-reloc;
};
- {
- status = "okay";
-};
-
- {
+ {
u-boot,dm-pre-reloc;
- reg-shift = <2>;
};
- {
+ {
u-boot,dm-pre-reloc;
};
- {
+ {
u-boot,dm-pre-reloc;
};
- {
+ {
u-boot,dm-pre-reloc;
};
- {
+ {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/rk3288-evb-act8846.dts
b/arch/arm/dts/rk3288-evb-act8846.dts
new file mode 100644
index 00..6204f8ce8f
--- /dev/null
+++ b/arch/arm/dts/rk3288-evb-act8846.dts
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk3288-evb.dtsi"
+#include "rk3288-evb-act8846-u-boot.dtsi"
+
+/ {
+ compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288";
+
+ vcc_lcd: vcc-lcd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = < RK_PA3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_en>;
+ regulator-name = "vcc_lcd";
+ vin-supply = <_io>;
+ };
+
+ vcc_wl: vcc-wl {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = < RK_PB1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pwr>;
+ regulator-name = "vcc_wl";
+ vin-supply = <_18>;
+ };
+};
+
+ {
+ clock-frequency = <40>;
+
+ vdd_cpu: syr827@40 {
+ compatible = "silergy,syr827";
+ fcs,suspend-voltage-selector = <1>;
+ reg = <0x40>;
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <85>;
+ regulator-max-microvolt = <135>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <_sys>;
+ };
+
+ vdd_gpu: syr828@41 {
+ compatible = "silergy,syr828";
+ fcs,suspend-voltage-selector = <1>;
+ reg = <0x41>;
+
[U-Boot] [PATCH 3/8] rockchip: rk3288: move TPL options to generic position
Move the TPL-related options to the generic RK3288 config option protected by "if TPL" conditionals. This way board wanting TPL support just need to "select TPL" to get all necessary options instead of duplicating all of them. Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/Kconfig| 15 +++ arch/arm/mach-rockchip/rk3288/Kconfig | 15 --- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index b9a026abb5..ba11e8a497 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -63,6 +63,21 @@ config ROCKCHIP_RK3288 select SPL_BOARD_INIT if SPL select SUPPORT_SPL select SPL + select SUPPORT_TPL + select ROCKCHIP_BROM_HELPER if TPL + select TPL_BOOTROM_SUPPORT if TPL + select TPL_CLK if TPL + select TPL_DM if TPL + select TPL_DRIVERS_MISC_SUPPORT if TPL + select TPL_LIBCOMMON_SUPPORT if TPL + select TPL_LIBGENERIC_SUPPORT if TPL + select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL + select TPL_OF_CONTROL if TPL + select TPL_OF_PLATDATA if TPL + select TPL_RAM if TPL + select TPL_REGMAP if TPL + select TPL_SERIAL_SUPPORT if TPL + select TPL_SYSCON if TPL imply USB_FUNCTION_ROCKUSB imply CMD_ROCKUSB help diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index f540b8daec..936faf75ca 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -98,22 +98,7 @@ config TARGET_POPMETAL_RK3288 config TARGET_VYASA_RK3288 bool "Vyasa-RK3288" select BOARD_LATE_INIT - select ROCKCHIP_BROM_HELPER - select SUPPORT_TPL select TPL - select TPL_BOOTROM_SUPPORT - select TPL_CLK - select TPL_DM - select TPL_DRIVERS_MISC_SUPPORT - select TPL_LIBCOMMON_SUPPORT - select TPL_LIBGENERIC_SUPPORT - select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL - select TPL_OF_CONTROL - select TPL_OF_PLATDATA - select TPL_RAM - select TPL_REGMAP - select TPL_SERIAL_SUPPORT - select TPL_SYSCON help Vyasa is a RK3288-based development board with 2 USB ports, HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 7/8] rockchip: rk3288: convert rk3288-evb to use tpl
We want to use ATF loaded by the SPL, so need support for the itb FIT in SPL which therefore needs real mmc reading capabilities making it too big for the sram. So convert to use TPL for memory init beforehand similar to rk3288-vyasa. Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/rk3288/Kconfig | 1 + board/rockchip/evb_rk3288/evb-rk3288.c | 4 configs/evb-rk3288-act8846_defconfig | 3 +-- configs/evb-rk3288-rk808_defconfig | 3 +-- 5 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index ba11e8a497..bfcf12d1ab 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -188,6 +188,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM config TPL_ROCKCHIP_BACK_TO_BROM bool "TPL returns to bootrom" + default y if ROCKCHIP_RK3288 default y if ROCKCHIP_RK3368 select ROCKCHIP_BROM_HELPER depends on TPL diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 936faf75ca..800902a683 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -44,6 +44,7 @@ config TARGET_CHROMEBOOK_SPEEDY config TARGET_EVB_RK3288 bool "Evb-RK3288" select BOARD_LATE_INIT + select TPL help EVB-RK3288 is a RK3288-based development board with 2 USB ports, HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It diff --git a/board/rockchip/evb_rk3288/evb-rk3288.c b/board/rockchip/evb_rk3288/evb-rk3288.c index d6992a26ca..ec1d03c86c 100644 --- a/board/rockchip/evb_rk3288/evb-rk3288.c +++ b/board/rockchip/evb_rk3288/evb-rk3288.c @@ -3,6 +3,8 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ +#ifndef CONFIG_TPL_BUILD + #include #include @@ -12,3 +14,5 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[0] = BOOT_DEVICE_MMC2; spl_boot_list[1] = BOOT_DEVICE_MMC1; } + +#endif \ No newline at end of file diff --git a/configs/evb-rk3288-act8846_defconfig b/configs/evb-rk3288-act8846_defconfig index 878367dea9..9c7be78ad7 100644 --- a/configs/evb-rk3288-act8846_defconfig +++ b/configs/evb-rk3288-act8846_defconfig @@ -1,9 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y -CONFIG_SYS_TEXT_BASE=0x +CONFIG_SYS_TEXT_BASE=0x0010 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_EVB_RK3288=y CONFIG_DEBUG_UART_BASE=0xff69 CONFIG_DEBUG_UART_CLOCK=2400 diff --git a/configs/evb-rk3288-rk808_defconfig b/configs/evb-rk3288-rk808_defconfig index 0cc1b2f601..73d30c9958 100644 --- a/configs/evb-rk3288-rk808_defconfig +++ b/configs/evb-rk3288-rk808_defconfig @@ -1,9 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y -CONFIG_SYS_TEXT_BASE=0x +CONFIG_SYS_TEXT_BASE=0x0010 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_EVB_RK3288=y CONFIG_DEBUG_UART_BASE=0xff69 CONFIG_DEBUG_UART_CLOCK=2400 -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 4/8] rockchip: rk3288: adjust load addresses
The rk3288 by default uses memory areas for u-boot and runtime parts like pxe+scriptfile that we may want to use for secure firmware and thus mark secure later on. So move the relevant parts a bit away from that. Signed-off-by: Heiko Stuebner --- include/configs/rk3288_common.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 72a54bc0ab..a36aa96b87 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -20,7 +20,7 @@ #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM /* Bootrom will load u-boot binary to 0x0 once return from SPL */ #endif -#define CONFIG_SYS_INIT_SP_ADDR0x0010 +#define CONFIG_SYS_INIT_SP_ADDR0x0030 #define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0xff718000 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) @@ -48,9 +48,9 @@ /* usb host support */ #define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x\0" \ - "pxefile_addr_r=0x0010\0" \ - "fdt_addr_r=0x01f0\0" \ + "scriptaddr=0x0050\0" \ + "pxefile_addr_r=0x0060\0" \ + "fdt_addr_r=0x560\0" \ "kernel_addr_r=0x0200\0" \ "ramdisk_addr_r=0x0400\0" -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 0/8] arm-trusted-firmware support for rk3288
This adds support for jumping into aarch32 ATF from u-boot spl
similar to how it works on aarch64.
I guess the biggest question might be "why" ;-)
Right now the status quo on Rockchip arm32 socs is, that the linux
kernel itself does smp and suspend handling. This precludes us from
doing fance things like virtualization but also deep suspend with
the DDR in self refresh, due to at least 2 approaches for putting
generalized code into sram from the kernel side failed so far.
For Virtualization we need the kernel to start in hyp mode and hence
needing to use psci for smp handling as well.
So there are multiple ways for achieving that, we could do
- psci in uboot itself is bad for coreboot and barebox who would
need to reimplement the same
- psci in optee is the solution Rockchip themself choose but only
provides precompiled binaries for their arm32 socs and also
reimplmenting this in an open way is somewhat of a dead-end
because while aarch64 can use op-tee, psci itself is always
done in the atf
- atf using the somewhat new aarch32 port has the advantage of
being able to share a lot of platform code making maintenance
together with the aarch64 parts a lot easier
Not having to rely on binary components as part of the boot process
is way nicer not only for reproducible builds but also for future
proofing projects as binary blobs may not receive updates after
some time.
Also it is still possible to use this together with an optee
implementation for specific security foobar. The only difference
is that while aarch64 can has separate states for secure monitor
and secure-os, in aarch32 both need to share the bl32 space, so
optee needs to be a payload during the atf build. If no secure-os
is needed, atf can use the sp_min payload, which is part of atf.
This works nicely on my rk3288 evb and even virtualization worked
already. Full support will still need a modified devicetree to
actually make use of the new psci capabilites.
Heiko Stuebner (8):
arm: v7: add read_mpidr function for arm32
spl: atf: add arm32 variant
rockchip: rk3288: move TPL options to generic position
rockchip: rk3288: adjust load addresses
rockchip: rk3288: reserve first 2MB when build with ATF support
rockchip: rk3288: split evb into its two entities
rockchip: rk3288: convert rk3288-evb to use tpl
rockchip: rk3288: make both evb variants use atf
arch/arm/dts/Makefile | 3 +-
...evb.dts => rk3288-evb-act8846-u-boot.dtsi} | 33 +-
arch/arm/dts/rk3288-evb-act8846.dts | 188 +++
arch/arm/dts/rk3288-evb-rk808-u-boot.dtsi | 40 ++
arch/arm/dts/rk3288-evb-rk808.dts | 202 +++
arch/arm/dts/rk3288-evb.dtsi | 493 --
arch/arm/include/asm/system.h | 9 +
arch/arm/mach-rockchip/Kconfig| 16 +
arch/arm/mach-rockchip/rk3288/Kconfig | 16 +-
arch/arm/mach-rockchip/rk3288/rk3288.c| 16 +
board/rockchip/evb_rk3288/evb-rk3288.c| 14 +
board/rockchip/evb_rk3288/fit_spl_atf.its | 52 ++
common/spl/Kconfig| 2 +-
common/spl/spl_atf.c | 86 ++-
...defconfig => evb-rk3288-act8846_defconfig} | 14 +-
configs/evb-rk3288-rk808_defconfig| 91
include/atf_common.h | 52 ++
include/configs/rk3288_common.h | 8 +-
18 files changed, 998 insertions(+), 337 deletions(-)
rename arch/arm/dts/{rk3288-evb.dts => rk3288-evb-act8846-u-boot.dtsi} (64%)
create mode 100644 arch/arm/dts/rk3288-evb-act8846.dts
create mode 100644 arch/arm/dts/rk3288-evb-rk808-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3288-evb-rk808.dts
create mode 100644 board/rockchip/evb_rk3288/fit_spl_atf.its
rename configs/{evb-rk3288_defconfig => evb-rk3288-act8846_defconfig} (87%)
create mode 100644 configs/evb-rk3288-rk808_defconfig
--
2.20.1
___
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[U-Boot] [PATCH 8/8] rockchip: rk3288: make both evb variants use atf
Enable both rk3288-evb variants to load an ATF binary between
spl and u-boot proper.
Doing the regular spl->u-boot load of course still stays possible
with this change.
Signed-off-by: Heiko Stuebner
---
board/rockchip/evb_rk3288/evb-rk3288.c| 12 +-
board/rockchip/evb_rk3288/fit_spl_atf.its | 52 +++
configs/evb-rk3288-act8846_defconfig | 9 +++-
configs/evb-rk3288-rk808_defconfig| 9 +++-
4 files changed, 77 insertions(+), 5 deletions(-)
create mode 100644 board/rockchip/evb_rk3288/fit_spl_atf.its
diff --git a/board/rockchip/evb_rk3288/evb-rk3288.c
b/board/rockchip/evb_rk3288/evb-rk3288.c
index ec1d03c86c..05aea66db6 100644
--- a/board/rockchip/evb_rk3288/evb-rk3288.c
+++ b/board/rockchip/evb_rk3288/evb-rk3288.c
@@ -15,4 +15,14 @@ void board_boot_order(u32 *spl_boot_list)
spl_boot_list[1] = BOOT_DEVICE_MMC1;
}
-#endif
\ No newline at end of file
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
diff --git a/board/rockchip/evb_rk3288/fit_spl_atf.its
b/board/rockchip/evb_rk3288/fit_spl_atf.its
new file mode 100644
index 00..67aff095d6
--- /dev/null
+++ b/board/rockchip/evb_rk3288/fit_spl_atf.its
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR X11 */
+/*
+ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * Minimal dts for a SPL FIT image payload.
+ */
+
+/dts-v1/;
+
+/ {
+ description = "FIT image with U-Boot proper, ATF bl32, DTB";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ data = /incbin/("../../../u-boot-nodtb.bin");
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <0x0020>;
+ };
+ atf {
+ description = "ARM Trusted Firmware";
+ data = /incbin/("../../../bl32-rk3288.bin");
+ type = "firmware";
+ os = "arm-trusted-firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x0010>;
+ entry = <0x0010>;
+ };
+
+ fdt {
+ description = "RK3288-EVB flat device-tree";
+ data = /incbin/("../../../u-boot.dtb");
+ type = "flat_dt";
+ compression = "none";
+ };
+ };
+
+ configurations {
+ default = "conf";
+ conf {
+ description = "Rockchip RK3288-EVB";
+ firmware = "atf";
+ loadables = "uboot";
+ fdt = "fdt";
+ };
+ };
+};
diff --git a/configs/evb-rk3288-act8846_defconfig
b/configs/evb-rk3288-act8846_defconfig
index 9c7be78ad7..0fcdaaa697 100644
--- a/configs/evb-rk3288-act8846_defconfig
+++ b/configs/evb-rk3288-act8846_defconfig
@@ -1,21 +1,26 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_SYS_TEXT_BASE=0x0010
+CONFIG_SYS_TEXT_BASE=0x0020
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
CONFIG_TARGET_EVB_RK3288=y
CONFIG_DEBUG_UART_BASE=0xff69
CONFIG_DEBUG_UART_CLOCK=2400
-CONFIG_SPL_STACK_R_ADDR=0x8
+CONFIG_SPL_STACK_R_ADDR=0x60
CONFIG_DEBUG_UART=y
CONFIG_NR_DRAM_BANKS=1
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_SOURCE="board/rockchip/evb_rk3288/fit_spl_atf.its"
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-evb-act8846.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
diff --git a/configs/evb-rk3288-rk808_defconfig
b/configs/evb-rk3288-rk808_defconfig
index 73d30c9958..f6b9ce12a1 100644
--- a/configs/evb-rk3288-rk808_defconfig
+++ b/configs/evb-rk3288-rk808_defconfig
@@ -1,21 +1,26 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_SYS_TEXT_BASE=0x0010
+CONFIG_SYS_TEXT_BASE=0x0020
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
CONFIG_TARGET_EVB_RK3288=y
CONFIG_DEBUG_UART_BASE=0xff69
CONFIG_DEBUG_UART_CLOCK=2400
-CONFIG_SPL_STACK_R_ADDR=0x8
+CONFIG_SPL_STACK_R_ADDR=0x60
CONFIG_DEBUG_UART=y
CONFIG_NR_DRAM_BANKS=1
# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_SOURCE="board/rockchip/evb_rk3288/fit_spl_atf.its"
CONFIG_SILENT_CONSOLE=y
CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb"
#
Re: [U-Boot] [PATCH 10/13 v5] Makefile: Add Kconfig option CONFIG_SPL_IMAGE to select the SPL binary
On 03.04.2019 16:24, Stefan Roese wrote: > This patch adds the CONFIG_SPL_IMAGE option to select the SPL image that > shall be used to generate the combined SPL + U-Boot image. The default > value is the current value "spl/u-boot-spl.bin". > > This patch also sets CONFIG_SPL_IMAGE to "spl/boot.bin" for AT91 targets > which use SPL NAND support (boot from NAND). For these build targets the > combined image "u-boot-with-spl.bin" is now automatically generated and > can be programmed into NAND as one single image (vs. SPL image and U-Boot > as 2 separate images). > > Signed-off-by: Stefan Roese > Cc: Heiko Schocher > Cc: Andreas Bießmann > Cc: Eugen Hristev Applied this whole series to u-boot-atmel/next Thanks ! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
