Re: [U-Boot] [PATCH 04/14] arm: socfpga: agilex: Add reset manager support
On Fri, May 10, 2019 at 11:26 PM Dinh Nguyen wrote: > > > > On 5/10/19 12:54 AM, Ley Foon Tan wrote: > > Add reset manager support for Agilex. > > > > Signed-off-by: Ley Foon Tan > > --- > > .../mach-socfpga/include/mach/reset_manager.h | 5 ++- > > .../include/mach/reset_manager_agilex.h | 38 +++ > > AFAIK, there's really nothing different in Agilex reset manager from the > Stratix10, can you just re-use the Stratix10? > > Dinh There are some changes on the register mapping. Regards Ley Foon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 01/14] arm: socfpga: agilex: Add base address for Intel Agilex SoC
On Sat, May 11, 2019 at 2:11 AM Simon Goldschmidt wrote: > > Am 10.05.2019 um 16:59 schrieb Dinh Nguyen: > > > > > > On 5/10/19 12:54 AM, Ley Foon Tan wrote: > >> Add base address for Intel Agilex SoC. > >> > >> Signed-off-by: Ley Foon Tan > >> --- > >> .../include/mach/base_addr_agilex.h | 38 +++ > >> 1 file changed, 38 insertions(+) > >> create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_agilex.h > >> > >> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_agilex.h > >> b/arch/arm/mach-socfpga/include/mach/base_addr_agilex.h > >> new file mode 100644 > >> index 00..e90b61f29d > >> --- /dev/null > >> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_agilex.h > >> @@ -0,0 +1,38 @@ > >> +/* SPDX-License-Identifier: GPL-2.0 */ > >> +/* > >> + * Copyright (C) 2016-2017 Intel Corporation > >> + */ > >> + > >> +#ifndef _SOCFPGA_AGILEX_BASE_HARDWARE_H_ > >> +#define _SOCFPGA_AGILEX_BASE_HARDWARE_H_ > >> + > >> +#define SOCFPGA_CCU_ADDRESS 0xf700 > >> +#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 > >> +#define SOCFPGA_SMMU_ADDRESS0xfa00 > >> +#define SOCFPGA_MAILBOX_ADDRESS 0xffa3 > >> +#define SOCFPGA_SPTIMER0_ADDRESS0xffc03000 > >> +#define SOCFPGA_SPTIMER1_ADDRESS0xffc03100 > >> +#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd0 > >> +#define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100 > >> +#define SOCFPGA_L4WD0_ADDRESS 0xffd00200 > >> +#define SOCFPGA_L4WD1_ADDRESS 0xffd00300 > >> +#define SOCFPGA_L4WD2_ADDRESS 0xffd00400 > >> +#define SOCFPGA_L4WD3_ADDRESS 0xffd00500 > >> +#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000 > >> +#define SOCFPGA_GTIMER_NSEC_ADDRESS 0xffd02000 > >> +#define SOCFPGA_CLKMGR_ADDRESS 0xffd1 > >> +#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000 > >> +#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000 > >> +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000 > >> +#define SOCFPGA_FIREWALL_L4_PER 0xffd21000 > >> +#define SOCFPGA_FIREWALL_L4_SYS 0xffd21100 > >> +#define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200 > >> +#define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300 > >> +#define SOCFPGA_FIREWALL_TCU0xffd21400 > >> +#define SOCFPGA_DMANONSECURE_ADDRESS0xffda > >> +#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 > >> +#define SOCFPGA_OCRAM_ADDRESS 0xffe0 > >> +#define GICD_BASE 0xfffc1000 > >> +#define GICC_BASE 0xfffc2000 > >> + > >> +#endif /* _SOCFPGA_AGILEX_BASE_HARDWARE_H_ */ > >> > > > > All of these addresses are identical to the Stratix10, couldn't you just > > use the Stratix10 and any diffs, you can just use fdt? > > Would it make sense to only add the addresses that are actually needed > as constants? I'd expect that most (if not all) of them could come from > devicetree? > > Regards, > Simon Yes, these are only the requires #define. Those components that can get from DT already remove, eg: SDRAM base etc. Regards Ley Foon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 01/14] arm: socfpga: agilex: Add base address for Intel Agilex SoC
On Fri, May 10, 2019 at 10:59 PM Dinh Nguyen wrote: > > > > On 5/10/19 12:54 AM, Ley Foon Tan wrote: > > Add base address for Intel Agilex SoC. > > > > Signed-off-by: Ley Foon Tan > > --- > > .../include/mach/base_addr_agilex.h | 38 +++ > > 1 file changed, 38 insertions(+) > > create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_agilex.h > > > > diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_agilex.h > > b/arch/arm/mach-socfpga/include/mach/base_addr_agilex.h > > new file mode 100644 > > index 00..e90b61f29d > > --- /dev/null > > +++ b/arch/arm/mach-socfpga/include/mach/base_addr_agilex.h > > @@ -0,0 +1,38 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright (C) 2016-2017 Intel Corporation > > + */ > > + > > +#ifndef _SOCFPGA_AGILEX_BASE_HARDWARE_H_ > > +#define _SOCFPGA_AGILEX_BASE_HARDWARE_H_ > > + > > +#define SOCFPGA_CCU_ADDRESS 0xf700 > > +#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 > > +#define SOCFPGA_SMMU_ADDRESS 0xfa00 > > +#define SOCFPGA_MAILBOX_ADDRESS 0xffa3 > > +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000 > > +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100 > > +#define SOCFPGA_SYSTIMER0_ADDRESS0xffd0 > > +#define SOCFPGA_SYSTIMER1_ADDRESS0xffd00100 > > +#define SOCFPGA_L4WD0_ADDRESS0xffd00200 > > +#define SOCFPGA_L4WD1_ADDRESS0xffd00300 > > +#define SOCFPGA_L4WD2_ADDRESS0xffd00400 > > +#define SOCFPGA_L4WD3_ADDRESS0xffd00500 > > +#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000 > > +#define SOCFPGA_GTIMER_NSEC_ADDRESS 0xffd02000 > > +#define SOCFPGA_CLKMGR_ADDRESS 0xffd1 > > +#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000 > > +#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000 > > +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000 > > +#define SOCFPGA_FIREWALL_L4_PER 0xffd21000 > > +#define SOCFPGA_FIREWALL_L4_SYS 0xffd21100 > > +#define SOCFPGA_FIREWALL_SOC2FPGA0xffd21200 > > +#define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300 > > +#define SOCFPGA_FIREWALL_TCU 0xffd21400 > > +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda > > +#define SOCFPGA_DMASECURE_ADDRESS0xffda1000 > > +#define SOCFPGA_OCRAM_ADDRESS0xffe0 > > +#define GICD_BASE0xfffc1000 > > +#define GICC_BASE0xfffc2000 > > + > > +#endif /* _SOCFPGA_AGILEX_BASE_HARDWARE_H_ */ > > > > All of these addresses are identical to the Stratix10, couldn't you just > use the Stratix10 and any diffs, you can just use fdt? > > Dinh There is one different compare to S10. Can reuse base_address_s10.h file, but filename remain _s10.h. Regards Ley Foon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 05/14] arm: socfpga: Move Stratix10 and Agilex system manager common code
On Fri, May 10, 2019 at 8:17 PM Marek Vasut wrote: > > On 5/10/19 7:54 AM, Ley Foon Tan wrote: > > Move Stratix10 and Agilex system manager common code to system_manager.h. > > > > Signed-off-by: Ley Foon Tan > > This becomes quite a bit of ifdeffery . Why don't you have the > system_manager.h include system_manager_$soc.h like e.g. here? > > http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/mach-rmobile/include/mach/rmobile.h > > -- > Best regards, > Marek Vasut We already have similar thing for Gen5. A10 and S10 includes. But, S10 and Agilex share some common defines/functions. I can move S10 and Agilex common code to a separate file and include in their header file. Regards Ley Foon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled
From: Yangbo Lu
u-boot is trying to make CONFIG_BLK as a hard requirement
for DM_MMC. But now it's still not.
config BLK
bool "Support block devices"
depends on DM
default y if DM_MMC
When fsl_esdhc driver was reworked for DM_MMC support, DM_MMC
without CONFIG_BLK enabled wasn't considered. This patch is to
fix probe issue without CONFIG_BLK enabled.
Signed-off-by: Yangbo Lu
Signed-off-by: Yinbo Zhu
---
Change in v2:
use existing bit define instead of magic number
remove the spl patches
drivers/mmc/fsl_esdhc.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 9e34557d16..f1d67657fa 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -25,6 +25,10 @@
#include
#include
+#if !CONFIG_IS_ENABLED(BLK)
+#include "mmc_private.h"
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
@@ -34,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR
| \
IRQSTATEN_DINT)
#define MAX_TUNING_LOOP 40
+#define ESDHC_DRIVER_STAGE_VALUE 0x
struct fsl_esdhc {
uintdsaddr; /* SDMA system address register */
@@ -1448,6 +1453,9 @@ static int fsl_esdhc_probe(struct udevice *dev)
fdt_addr_t addr;
unsigned int val;
struct mmc *mmc;
+#if !CONFIG_IS_ENABLED(BLK)
+ struct blk_desc *bdesc;
+#endif
int ret;
addr = dev_read_addr(dev);
@@ -1576,6 +1584,26 @@ static int fsl_esdhc_probe(struct udevice *dev)
mmc = >mmc;
mmc->cfg = >cfg;
mmc->dev = dev;
+#if !CONFIG_IS_ENABLED(BLK)
+ mmc->priv = priv;
+
+ /* Setup dsr related values */
+ mmc->dsr_imp = 0;
+ mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
+ /* Setup the universal parts of the block interface just once */
+ bdesc = mmc_get_blk_desc(mmc);
+ bdesc->if_type = IF_TYPE_MMC;
+ bdesc->removable = 1;
+ bdesc->devnum = mmc_get_next_devnum();
+ bdesc->block_read = mmc_bread;
+ bdesc->block_write = mmc_bwrite;
+ bdesc->block_erase = mmc_berase;
+
+ /* setup initial part type */
+ bdesc->part_type = mmc->cfg->part_type;
+ mmc_list_add(mmc);
+#endif
+
upriv->mmc = mmc;
return esdhc_init_common(priv, mmc);
--
2.17.1
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Re: [U-Boot] [PATCH 07/14] arm: socfpga: agilex: Add clock manager support
On Fri, May 10, 2019 at 8:17 PM Marek Vasut wrote: > > On 5/10/19 7:54 AM, Ley Foon Tan wrote: > > Add clock manager support for Agilex. > > > > Signed-off-by: Chee Hong Ang > > Signed-off-by: Ley Foon Tan > > --- > > arch/arm/mach-socfpga/Makefile| 4 + > > arch/arm/mach-socfpga/clock_manager_agilex.c | 582 ++ > > .../mach-socfpga/include/mach/clock_manager.h | 2 + > > .../include/mach/clock_manager_agilex.h | 328 ++ > > 4 files changed, 916 insertions(+) > > create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex.c > > create mode 100644 > > arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h > > Can this be in drivers/clk instead ? > > -- Yes, it can. There is plan to move S10 clock driver to DM as well. Regards Ley Foon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 2/2] armv8: fsl-lsch3: add clock support for the second eSDHC
From: Yangbo Lu
Layerscape began to use two eSDHC controllers, for example,
LS1028A. They were same IP block with same reference clock.
This patch is to add clock support for the second eSDHC.
Signed-off-by: Yangbo Lu
Signed-off-by: Yinbo Zhu
---
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 1 +
arch/arm/include/asm/arch-fsl-layerscape/clock.h| 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index bc268e207c..7dbca1f06f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -214,6 +214,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
return get_i2c_freq(0);
#if defined(CONFIG_FSL_ESDHC)
case MXC_ESDHC_CLK:
+ case MXC_ESDHC2_CLK:
return get_sdhc_freq(0);
#endif
case MXC_DSPI_CLK:
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h
b/arch/arm/include/asm/arch-fsl-layerscape/clock.h
index cf058d22a9..ac4194b9aa 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/clock.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h
@@ -14,6 +14,7 @@ enum mxc_clock {
MXC_BUS_CLK,
MXC_UART_CLK,
MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
MXC_I2C_CLK,
MXC_DSPI_CLK,
};
--
2.17.1
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Re: [U-Boot] [PATCH 08/14] arm: socfpga: agilex: Add CCU support for Agilex
On Sat, May 11, 2019 at 2:40 AM Simon Goldschmidt
wrote:
>
> Am 10.05.2019 um 07:54 schrieb Ley Foon Tan:
> > Add CCU support for Agilex.
>
> This description could be a bit longer: what's CCU, and why do you add
> it or when/by what will it be used.
Will update description.
Thanks.
Regards
Ley Foon
>
> Regards,
> Simon
>
> >
> > Signed-off-by: Ley Foon Tan
> > ---
> > arch/arm/mach-socfpga/Makefile| 3 +
> > arch/arm/mach-socfpga/ccu_agilex.c| 99 +++
> > .../mach-socfpga/include/mach/ccu_agilex.h| 67 +
> > 3 files changed, 169 insertions(+)
> > create mode 100644 arch/arm/mach-socfpga/ccu_agilex.c
> > create mode 100644 arch/arm/mach-socfpga/include/mach/ccu_agilex.h
> >
> > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> > index 5bb36d07df..51355ad070 100644
> > --- a/arch/arm/mach-socfpga/Makefile
> > +++ b/arch/arm/mach-socfpga/Makefile
> > @@ -59,6 +59,9 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
> > obj-y += firewall.o
> > obj-y += spl_s10.o
> > endif
> > +ifdef CONFIG_TARGET_SOCFPGA_AGILEX
> > +obj-y += ccu_agilex.o
> > +endif
> > endif
> >
> > ifdef CONFIG_TARGET_SOCFPGA_GEN5
> > diff --git a/arch/arm/mach-socfpga/ccu_agilex.c
> > b/arch/arm/mach-socfpga/ccu_agilex.c
> > new file mode 100644
> > index 00..f27a48b523
> > --- /dev/null
> > +++ b/arch/arm/mach-socfpga/ccu_agilex.c
> > @@ -0,0 +1,99 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2019 Intel Corporation
> > + *
> > + */
> > +#include
> > +#include
> > +#include
> > +
> > +static void ccu_init_dirs(void)
> > +{
> > + ulong i, f;
> > + int ret;
> > + u32 num_of_dirs;
> > + u32 num_of_snoop_filters;
> > + u32 reg;
> > +
> > + num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(CCU_REG_ADDR(CSUIDR)));
> > + num_of_snoop_filters =
> > + CSIDR_NUMSFS_GET(readl(CCU_REG_ADDR(CSIDR))) + 1;
> > +
> > + /* Initialize each snoop filter in each directory */
> > + for (f = 0; f < num_of_snoop_filters; f++) {
> > + reg = f << DIRUSFMCR_SFID_SHIFT;
> > + for (i = 0; i < num_of_dirs; i++) {
> > + /* Initialize all entries */
> > + writel(reg, CCU_DIR_REG_ADDR(i, DIRUSFMCR));
> > +
> > + /* Poll snoop filter maintenance operation active
> > + * bit become 0.
> > + */
> > + ret = wait_for_bit_le32((const void *)
> > + CCU_DIR_REG_ADDR(i,
> > DIRUSFMAR),
> > + BIT(0), false, 1000, false);
> > + if (ret) {
> > + puts("CCU: Directory initialization
> > failed!\n");
> > + hang();
> > + }
> > +
> > + /* Enable snoop filter, a bit per snoop filter */
> > + setbits_le32((ulong)CCU_DIR_REG_ADDR(i, DIRUSFER),
> > + BIT(f));
> > + }
> > + }
> > +}
> > +
> > +void ccu_init_coh_agent_intf(void)
> > +{
> > + u32 num_of_coh_agent_intf;
> > + u32 num_of_dirs;
> > + u32 reg;
> > + u32 type;
> > + u32 i, dir;
> > +
> > + num_of_coh_agent_intf =
> > + CSUIDR_NUMCAIUS_GET(readl(CCU_REG_ADDR(CSUIDR)));
> > + num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(CCU_REG_ADDR(CSUIDR)));
> > +
> > + for (i = 0; i < num_of_coh_agent_intf; i++) {
> > + reg = readl((ulong)CCU_CAIU_REG_ADDR(i, CAIUIDR));
> > + if (CAIUIDR_CA_GET(reg)) {
> > + /* Caching agent bit is enabled, enable caching agent
> > + * snoop in each directory
> > + */
> > + for (dir = 0; dir < num_of_dirs; dir++) {
> > + setbits_le32((ulong)
> > + CCU_DIR_REG_ADDR(dir,
> > DIRUCASER0),
> > + BIT(i));
> > + }
> > + }
> > +
> > + type = CAIUIDR_TYPE_GET(reg);
> > + if (type == CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT ||
> > + type == CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT) {
> > + /* DVM support is enabled, enable ACE DVM snoop*/
> > + setbits_le32((ulong)(CCU_REG_ADDR(CSADSER0)),
> > + BIT(i));
> > + }
> > + }
> > +}
> > +
> > +static void ocram_bypass_firewall(void)
> > +{
> > + clrbits_le32((ulong)(COH_CPU0_BYPASS_REG_ADDR(OCRAM_BLK_CGF_01_REG)),
> > + OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
> > + clrbits_le32((ulong)(COH_CPU0_BYPASS_REG_ADDR(OCRAM_BLK_CGF_02_REG)),
> > + OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
> > +
Re: [U-Boot] [PATCH 10/14] ddr: altera: agilex: Add SDRAM driver for Agilex
On Fri, May 10, 2019 at 8:17 PM Marek Vasut wrote: > > On 5/10/19 7:54 AM, Ley Foon Tan wrote: > > Add SDRAM driver for Agilex SoC. > > > > Signed-off-by: Tien Fong Chee > > Signed-off-by: Ley Foon Tan > > --- > > drivers/ddr/altera/Kconfig| 6 +- > > drivers/ddr/altera/Makefile | 1 + > > drivers/ddr/altera/sdram_agilex.c | 158 ++ > > drivers/ddr/altera/sdram_common.c | 1 + > > drivers/ddr/altera/sdram_common.h | 1 + > > 5 files changed, 164 insertions(+), 3 deletions(-) > > create mode 100644 drivers/ddr/altera/sdram_agilex.c > > [...] > > > + /* This enables nonsecure access to DDR */ > > + /* mpuregion0addr_limit */ > > + FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1, > > + FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT); > > + FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT); > > Why is the function name in caps? They are macros, not function. > > > + > > + /* nonmpuregion0addr_limit */ > > + FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1, > > + FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); > > + > > + /* Enable mpuregion0enable and nonmpuregion0enable */ > > + FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE, > > + FW_MPU_DDR_SCR_EN_SET); > > + > > + u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1); > Doesn't the C compiler warn about variable defined in the middle of code ? > No compiler warning. Regards Ley Foon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 13/14] arm: dts: agilex: Add base dtsi and devkit dts
On Fri, May 10, 2019 at 8:17 PM Marek Vasut wrote: > > On 5/10/19 7:54 AM, Ley Foon Tan wrote: > > Add device tree files for Agilex SoC platform. > > > > Signed-off-by: Ley Foon Tan > > Are these from Linux ? If so, which version and commit ? > > -- Yes, but with minor changes. It is from linux-next branch. Will add commit id. Regards Ley Foon Regards Ley Foon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] cmd: env: print a message when setting UEFI variable failed
Error message will alert a user that setting/deleting a variable failed.
Signed-off-by: AKASHI Takahiro
---
cmd/nvedit_efi.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/cmd/nvedit_efi.c b/cmd/nvedit_efi.c
index 2805e8182b41..e0d8f578ac33 100644
--- a/cmd/nvedit_efi.c
+++ b/cmd/nvedit_efi.c
@@ -373,6 +373,7 @@ int do_env_set_efi(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
for ( ; argc > 0; argc--, argv++)
if (append_value(, , argv[0]) < 0) {
+ printf("## Failed to process arguments\n");
ret = CMD_RET_FAILURE;
goto out;
}
@@ -381,6 +382,7 @@ int do_env_set_efi(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
len = utf8_utf16_strnlen(var_name, strlen(var_name));
var_name16 = malloc((len + 1) * 2);
if (!var_name16) {
+ printf("## Can't malloc %ld bytes\n", (len + 1) * 2);
ret = CMD_RET_FAILURE;
goto out;
}
@@ -392,7 +394,13 @@ int do_env_set_efi(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS,
size, value));
- ret = (ret == EFI_SUCCESS ? CMD_RET_SUCCESS : CMD_RET_FAILURE);
+ if (ret == EFI_SUCCESS) {
+ ret = CMD_RET_SUCCESS;
+ } else {
+ printf("## Failed to set EFI variable (%ld)\n",
+ ret & ~EFI_ERROR_MASK);
+ ret = CMD_RET_FAILURE;
+ }
out:
free(value);
free(var_name16);
--
2.21.0
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[U-Boot] [PATCH] efi_loader: bootmgr: print a message when loading from BootNext failed
If a user defines BootNext but not BootOrder and loading from BootNext
fails, you will see only a message like this:
BootOrder not defined
This may confuse a user. Adding an error message will be helpful.
Signed-off-by: AKASHI Takahiro
---
lib/efi_loader/efi_bootmgr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index 7bf51874c1c1..6a4a478473c3 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -215,6 +215,8 @@ efi_status_t efi_bootmgr_load(efi_handle_t *handle)
ret = try_load_entry(bootnext, handle);
if (ret == EFI_SUCCESS)
return ret;
+ printf("Loading from Boot%04X failed, falling
back into BootOrder...\n",
+ bootnext);
}
} else {
printf("Deleting BootNext failed\n");
--
2.21.0
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[U-Boot] [PATCH] efi_loader: variable: attributes may not be changed if a variable exists
If a variable already exists, efi_set_variable() should not change
the variable's attributes. This patch enforces it.
Signed-off-by: AKASHI Takahiro
---
lib/efi_loader/efi_variable.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index 37728c3c165d..c4f3a5d2743d 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -450,6 +450,15 @@ efi_status_t EFIAPI efi_set_variable(u16 *variable_name,
ret = EFI_WRITE_PROTECTED;
goto out;
}
+
+ /*
+* attributes won't be changed
+* TODO: take care of APPEND_WRITE once supported
+*/
+ if (attr != attributes) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
}
val = malloc(2 * data_size + strlen("{ro,run,boot}(blob)") + 1);
--
2.21.0
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[U-Boot] [PATCH v3 4/5] configs: mt7629_rfb: change MTK_QSPI to MTK_SNFI_SPI
This patch replaces MTK_QSPI with MTK_SNFI_SPI to ensure mtk_snfi_spi driver is built by default. Signed-off-by: Weijie Gao --- Changes since v2: none --- configs/mt7629_rfb_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig index 0dceafdaa67..d8efba66201 100644 --- a/configs/mt7629_rfb_defconfig +++ b/configs/mt7629_rfb_defconfig @@ -63,7 +63,7 @@ CONFIG_DM_SERIAL=y CONFIG_MTK_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y -CONFIG_MTK_QSPI=y +CONFIG_MTK_SNFI_SPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_WATCHDOG=y -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 3/5] arm: dts: change MT7629 to use spi-mem rather than qspi
The original mtk_qspi driver has been removed. We change MT7629 to use
newly added mtk-spimem driver.
Signed-off-by: Weijie Gao
---
Changes since v1: rename node spimem to snfi. change pinctrl name and order.
Changes since v2: none
---
arch/arm/dts/mt7629-rfb.dts | 18 +-
arch/arm/dts/mt7629.dtsi| 14 ++
2 files changed, 23 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts
index 4612218a1eb..25f1344817d 100644
--- a/arch/arm/dts/mt7629-rfb.dts
+++ b/arch/arm/dts/mt7629-rfb.dts
@@ -13,7 +13,7 @@
compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
aliases {
- spi0 =
+ spi0 =
};
chosen {
@@ -34,7 +34,14 @@
};
{
- qspi_pins: qspi-pins {
+ snfi_pins: snfi-pins {
+ mux {
+ function = "flash";
+ groups = "snfi";
+ };
+ };
+
+ snor_pins: snor-pins {
mux {
function = "flash";
groups = "spi_nor";
@@ -56,9 +63,10 @@
};
};
- {
- pinctrl-names = "default";
- pinctrl-0 = <_pins>;
+ {
+ pinctrl-names = "default", "snfi";
+ pinctrl-0 = <_pins>;
+ pinctrl-1 = <_pins>;
status = "okay";
spi-flash@0{
diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi
index c87115e0fe4..135ac8ecfa2 100644
--- a/arch/arm/dts/mt7629.dtsi
+++ b/arch/arm/dts/mt7629.dtsi
@@ -215,10 +215,16 @@
status = "disabled";
};
- qspi: qspi@11014000 {
- compatible = "mediatek,mt7629-qspi";
- reg = <0x11014000 0xe0>, <0x3000 0x1000>;
- reg-names = "reg_base", "mem_base";
+ snfi: snfi@1100d000 {
+ compatible = "mediatek,mtk-snfi-spi";
+ reg = <0x1100d000 0x2000>;
+ clocks = < CLK_PERI_NFI_PD>,
+< CLK_PERI_SNFI_PD>;
+ clock-names = "nfi_clk", "pad_clk";
+ assigned-clocks = < CLK_TOP_AXI_SEL>,
+ < CLK_TOP_NFI_INFRA_SEL>;
+ assigned-clock-parents = < CLK_TOP_SYSPLL1_D2>,
+< CLK_TOP_UNIVPLL2_D8>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
--
2.18.0
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[U-Boot] [PATCH v3 5/5] MAINTAINERS: change spi driver entry
Change mtk_qspi.c to mtk_snfi_spi.c Signed-off-by: Weijie Gao --- Changes since v1: rename mtk_spimem.c to spi_snfi_spi.c Changes since v2: none --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 33fd4652a42..cb9f8e23bd7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -204,7 +204,7 @@ F: drivers/mmc/mtk-sd.c F: drivers/pinctrl/mediatek/ F: drivers/power/domain/mtk-power-domain.c F: drivers/ram/mediatek/ -F: drivers/spi/mtk_qspi.c +F: drivers/spi/mtk_snfi_spi.c F: drivers/timer/mtk_timer.c F: drivers/watchdog/mtk_wdt.c F: drivers/net/mtk_eth.c -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 2/5] spi: add spi-mem driver for MediaTek MT7629 SoC
This patch adds spi-mem driver for MediaTek MT7629 SoC to access SPI-NOR
and SPI-NAND flashes.
Cc: Jagan Teki
Signed-off-by: Weijie Gao
---
Changes since v1: rename mtk_spimem to spi_snfi_spi. change pinctrl name.
Changes since v2: remove udevice in mtk_snfi_priv.
---
drivers/spi/Kconfig| 9 ++
drivers/spi/Makefile | 1 +
drivers/spi/mtk_snfi_spi.c | 321 +
3 files changed, 331 insertions(+)
create mode 100644 drivers/spi/mtk_snfi_spi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 4f0f5d99953..8b6e0fb2d99 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -139,6 +139,15 @@ config MT7621_SPI
the SPI NOR flash on platforms embedding this Ralink / MediaTek
SPI core, like MT7621/7628/7688.
+config MTK_SNFI_SPI
+ bool "Mediatek SPI memory controller driver"
+ depends on SPI_MEM
+ help
+ Enable the Mediatek SPI memory controller driver. This driver is
+ originally based on the MediaTek SNFI IP core. It can only be
+ used to access SPI memory devices like SPI-NOR or SPI-NAND on
+ platforms embedding this IP core, like MT7622/M7629.
+
config MVEBU_A3700_SPI
bool "Marvell Armada 3700 SPI driver"
select CLK_ARMADA_3720
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index f1e3becd2b7..5c639634777 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
+obj-$(CONFIG_MTK_SNFI_SPI) += mtk_snfi_spi.o
obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
diff --git a/drivers/spi/mtk_snfi_spi.c b/drivers/spi/mtk_snfi_spi.c
new file mode 100644
index 000..0adc734a5c1
--- /dev/null
+++ b/drivers/spi/mtk_snfi_spi.c
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SNFI_MAC_CTL 0x500
+#define MAC_XIO_SELBIT(4)
+#define SF_MAC_EN BIT(3)
+#define SF_TRIGBIT(2)
+#define WIP_READY BIT(1)
+#define WIPBIT(0)
+
+#define SNFI_MAC_OUTL 0x504
+#define SNFI_MAC_INL 0x508
+
+#define SNFI_MISC_CTL 0x538
+#define SW_RST BIT(28)
+#define FIFO_RD_LTC_SHIFT 25
+#define FIFO_RD_LTCGENMASK(26, 25)
+#define LATCH_LAT_SHIFT8
+#define LATCH_LAT GENMASK(9, 8)
+#define CS_DESELECT_CYC_SHIFT 0
+#define CS_DESELECT_CYCGENMASK(4, 0)
+
+#define SNF_STA_CTL1 0x550
+#define SPI_STATE GENMASK(3, 0)
+
+#define SNFI_GPRAM_OFFSET 0x800
+#define SNFI_GPRAM_SIZE0x80
+
+#define SNFI_POLL_INTERVAL 50
+#define SNFI_RST_POLL_INTERVAL 100
+
+struct mtk_snfi_priv {
+ void __iomem *base;
+
+ struct clk nfi_clk;
+ struct clk pad_clk;
+};
+
+static int mtk_snfi_adjust_op_size(struct spi_slave *slave,
+ struct spi_mem_op *op)
+{
+ u32 nbytes;
+
+ /*
+* When there is input data, it will be appended after the output
+* data in the GPRAM. So the total size of either pure output data
+* or the output+input data must not exceed the GPRAM size.
+*/
+
+ nbytes = sizeof(op->cmd.opcode) + op->addr.nbytes +
+ op->dummy.nbytes;
+
+ if (nbytes + op->data.nbytes <= SNFI_GPRAM_SIZE)
+ return 0;
+
+ if (nbytes >= SNFI_GPRAM_SIZE)
+ return -ENOTSUPP;
+
+ op->data.nbytes = SNFI_GPRAM_SIZE - nbytes;
+
+ return 0;
+}
+
+static bool mtk_snfi_supports_op(struct spi_slave *slave,
+const struct spi_mem_op *op)
+{
+ if (op->cmd.buswidth > 1 || op->addr.buswidth > 1 ||
+ op->dummy.buswidth > 1 || op->data.buswidth > 1)
+ return false;
+
+ return true;
+}
+
+static int mtk_snfi_mac_trigger(struct mtk_snfi_priv *priv,
+ struct udevice *bus, u32 outlen, u32 inlen)
+{
+ int ret;
+ u32 val;
+
+#ifdef CONFIG_PINCTRL
+ pinctrl_select_state(bus, "snfi");
+#endif
+
+ writel(SF_MAC_EN, priv->base + SNFI_MAC_CTL);
+ writel(outlen, priv->base + SNFI_MAC_OUTL);
+ writel(inlen, priv->base + SNFI_MAC_INL);
+
+ writel(SF_MAC_EN | SF_TRIG, priv->base + SNFI_MAC_CTL);
+
+ ret =
[U-Boot] [PATCH v3 1/5] spi: remove obsolete mtk_qspi driver
Since u-boot has added the spi-mem framework and replaced the spi-nor
framework, the mtk_qspi is no longer compatible with the new spi-nor
driver.
Remove this driver, and a new driver will be added later.
Cc: Jagan Teki
Signed-off-by: Weijie Gao
---
Changes since v2: none
---
drivers/spi/Kconfig| 8 -
drivers/spi/Makefile | 1 -
drivers/spi/mtk_qspi.c | 359 -
3 files changed, 368 deletions(-)
delete mode 100644 drivers/spi/mtk_qspi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index dc3e23f353a..4f0f5d99953 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -139,14 +139,6 @@ config MT7621_SPI
the SPI NOR flash on platforms embedding this Ralink / MediaTek
SPI core, like MT7621/7628/7688.
-config MTK_QSPI
- bool "Mediatek QSPI driver"
- imply SPI_FLASH_BAR
- help
- Enable the Mediatek QSPI driver. This driver can be
- used to access the SPI NOR flash on platforms embedding this
- Mediatek QSPI IP core.
-
config MVEBU_A3700_SPI
bool "Marvell Armada 3700 SPI driver"
select CLK_ARMADA_3720
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 8be9a4baa24..f1e3becd2b7 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -36,7 +36,6 @@ obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
-obj-$(CONFIG_MTK_QSPI) += mtk_qspi.o
obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
diff --git a/drivers/spi/mtk_qspi.c b/drivers/spi/mtk_qspi.c
deleted file mode 100644
index b510733e92c..000
--- a/drivers/spi/mtk_qspi.c
+++ /dev/null
@@ -1,359 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2018 MediaTek, Inc.
- * Author : guochun@mediatek.com
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-/* Register Offset */
-struct mtk_qspi_regs {
- u32 cmd;
- u32 cnt;
- u32 rdsr;
- u32 rdata;
- u32 radr[3];
- u32 wdata;
- u32 prgdata[6];
- u32 shreg[10];
- u32 cfg[2];
- u32 shreg10;
- u32 mode_mon;
- u32 status[4];
- u32 flash_time;
- u32 flash_cfg;
- u32 reserved_0[3];
- u32 sf_time;
- u32 pp_dw_data;
- u32 reserved_1;
- u32 delsel_0[2];
- u32 intrstus;
- u32 intren;
- u32 reserved_2;
- u32 cfg3;
- u32 reserved_3;
- u32 chksum;
- u32 aaicmd;
- u32 wrprot;
- u32 radr3;
- u32 dual;
- u32 delsel_1[3];
-};
-
-struct mtk_qspi_platdata {
- fdt_addr_t reg_base;
- fdt_addr_t mem_base;
-};
-
-struct mtk_qspi_priv {
- struct mtk_qspi_regs *regs;
- unsigned long *mem_base;
- u8 op;
- u8 tx[3]; /* only record max 3 bytes paras, when it's address. */
- u32 txlen; /* dout buffer length - op code length */
- u8 *rx;
- u32 rxlen;
-};
-
-#define MTK_QSPI_CMD_POLLINGREG_US 50
-#define MTK_QSPI_WRBUF_SIZE256
-#define MTK_QSPI_COMMAND_ENABLE0x30
-
-/* NOR flash controller commands */
-#define MTK_QSPI_RD_TRIGGERBIT(0)
-#define MTK_QSPI_READSTATUSBIT(1)
-#define MTK_QSPI_PRG_CMD BIT(2)
-#define MTK_QSPI_WR_TRIGGERBIT(4)
-#define MTK_QSPI_WRITESTATUS BIT(5)
-#define MTK_QSPI_AUTOINC BIT(7)
-
-#define MTK_QSPI_MAX_RX_TX_SHIFT 0x6
-#define MTK_QSPI_MAX_SHIFT 0x8
-
-#define MTK_QSPI_WR_BUF_ENABLE 0x1
-#define MTK_QSPI_WR_BUF_DISABLE0x0
-
-static int mtk_qspi_execute_cmd(struct mtk_qspi_priv *priv, u8 cmd)
-{
- u8 tmp;
- u8 val = cmd & ~MTK_QSPI_AUTOINC;
-
- writeb(cmd, >regs->cmd);
-
- return readb_poll_timeout(>regs->cmd, tmp, !(val & tmp),
- MTK_QSPI_CMD_POLLINGREG_US);
-}
-
-static int mtk_qspi_tx_rx(struct mtk_qspi_priv *priv)
-{
- int len = 1 + priv->txlen + priv->rxlen;
- int i, ret, idx;
-
- if (len > MTK_QSPI_MAX_SHIFT)
- return -ERR_INVAL;
-
- writeb(len * 8, >regs->cnt);
-
- /* start at PRGDATA5, go down to PRGDATA0 */
- idx = MTK_QSPI_MAX_RX_TX_SHIFT - 1;
-
- /* opcode */
- writeb(priv->op, >regs->prgdata[idx]);
- idx--;
-
- /* program TX data */
- for (i = 0; i < priv->txlen; i++, idx--)
- writeb(priv->tx[i], >regs->prgdata[idx]);
-
- /* clear out rest of TX registers */
- while (idx >= 0) {
- writeb(0, >regs->prgdata[idx]);
- idx--;
- }
-
- ret = mtk_qspi_execute_cmd(priv, MTK_QSPI_PRG_CMD);
- if (ret)
- return ret;
-
- /* restart at first RX byte */
- idx = priv->rxlen - 1;
-
- /* read out RX data */
- for (i = 0; i < priv->rxlen; i++,
[U-Boot] [PATCH v3 0/5] Add spi-mem driver for MediaTek MT7629 SoC
Since u-boot has added the spi-mem framework and replaced the spi-nor framework, the mtk_qspi is no longer compatible with the new spi-nor driver. This patch series add a new spi-mem driver to replace the mtk_qspi driver. Weijie Gao (5): spi: remove obsolete mtk_qspi driver spi: add spi-mem driver for MediaTek MT7629 SoC arm: dts: change MT7629 to use spi-mem rather than qspi configs: mt7629_rfb: change MTK_QSPI to MTK_SNFI_SPI MAINTAINERS: change spi driver entry MAINTAINERS | 2 +- arch/arm/dts/mt7629-rfb.dts | 18 +- arch/arm/dts/mt7629.dtsi | 14 +- configs/mt7629_rfb_defconfig | 2 +- drivers/spi/Kconfig | 15 +- drivers/spi/Makefile | 2 +- drivers/spi/mtk_qspi.c | 359 --- drivers/spi/mtk_snfi_spi.c | 321 +++ 8 files changed, 355 insertions(+), 378 deletions(-) delete mode 100644 drivers/spi/mtk_qspi.c create mode 100644 drivers/spi/mtk_snfi_spi.c -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 2/2] fit: Support compat string property in configuration node
> Can you please add a change log, as this is a v3 patch. I didn't change anything in this one. (Should I have not called it v3 then? Sorry, I'm not familiar with the submission process here. I thought letting the individual patches in the series have different version numbers for the same set would be more confusing.) ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/2] fit: Support compression for non-kernel components (e.g. FDT)
> Is there a change log for this patch?I think we discussed having a test. Sorry, forgot that. Is it okay if I just put it here or do you need me to resend a v4? --- Changes for v2: - made decompression work for all non-kernel images, not just FDTs Changes for v3: - fixed up debug output that was still written for v1 - fixed a mistake with handling FIT_LOAD_OPTIONAL_NON_ZERO when 'load' was 0 (i.e. unset) - added compression test case to test_fit ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] imx8: cpu: fix warning for cpu_imx_get_temp
Hi Igor,
Not found your original mail, so reply Stefan's mail here.
> -Original Message-
> From: Stefan Agner [mailto:ste...@agner.ch]
> Sent: 2019年5月13日 21:56
> To: Igor Opaniuk
> Cc: u-boot@lists.denx.de; feste...@gmail.com; dl-uboot-imx
> ; albert.u.b...@aribaud.net; Peng Fan
> ; ag...@denx.de; Marcel Ziswiler
> ; mar...@ziswiler.com; Max Krummenacher
> ; sba...@denx.de
> Subject: Re: [PATCH 1/1] imx8: cpu: fix warning for cpu_imx_get_temp
>
> Hi Igor,
>
> On 13.05.2019 12:46, Igor Opaniuk wrote:
> > cpu_imx_get_temp() definition is wrapped with a ifdef macro, therefore
> > all function references should be also wrapped the same way instead
> > IS_ENABLED() usage.
Are you trying to fix https://patchwork.ozlabs.org/patch/1095430/ ?
Thanks,
Peng
> >
> > Fix warning:
> > arch/arm/mach-imx/imx8/cpu.c: In function ‘cpu_imx_get_desc’:
> > arch/arm/mach-imx/imx8/cpu.c:612:40: warning: implicit declaration of
> > function ‘cpu_imx_get_temp’; did you mean ‘cpu_imx_get_desc’?
> > [-Wimplicit-function-declaration]
> >ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp());
> > ^~~~
> > cpu_imx_get_desc
> > cpu_imx_get_desc
> >
>
> Using IS_ENABLED is typically preferred over ifdef since it assures that the
> code is compileable even if CONFIG_IMX_SCU_THERMAL is not enabled.
>
> I'd rather prefer we drop the the ifdef around cpu_imx_get_temp(). The linker
> will remove the function in case CONFIG_IMX_SCU_THERMAL is not enabled.
>
> --
> Stefan
>
> > Fixes: 82467cb217 ("imx8: cpu: get temperature when print cpu desc")
> > Signed-off-by: Igor Opaniuk
> > ---
> > arch/arm/mach-imx/imx8/cpu.c | 10 +-
> > 1 file changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/arch/arm/mach-imx/imx8/cpu.c
> > b/arch/arm/mach-imx/imx8/cpu.c index 12596c6387..616baed7cc 100644
> > --- a/arch/arm/mach-imx/imx8/cpu.c
> > +++ b/arch/arm/mach-imx/imx8/cpu.c
> > @@ -606,11 +606,11 @@ int cpu_imx_get_desc(struct udevice *dev, char
> > *buf, int size)
> > ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
> >plat->type, plat->rev, plat->name, plat->freq_mhz);
> >
> > - if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
> > - buf = buf + ret;
> > - size = size - ret;
> > - ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp());
> > - }
> > +#if defined(CONFIG_IMX_SCU_THERMAL)
> > + buf = buf + ret;
> > + size = size - ret;
> > + ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp()); #endif
> >
> > snprintf(buf + ret, size - ret, "\n");
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Re: [U-Boot] [PATCH v2 11/18] usb: dwc3-generic: if no max speed is specified in DT, assume super speed
On 5/13/19 4:30 PM, Jean-Jacques Hiblot wrote:
> There is no need to fail if the maximum speed is not specified.
> If the speed is not specified, do the same as linux and assume super speed.
>
> Signed-off-by: Jean-Jacques Hiblot
> ---
>
> Changes in v2: None
>
> drivers/usb/dwc3/dwc3-generic.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
> index 4924d07553..3d008496f3 100644
> --- a/drivers/usb/dwc3/dwc3-generic.c
> +++ b/drivers/usb/dwc3/dwc3-generic.c
> @@ -89,8 +89,8 @@ static int dwc3_generic_ofdata_to_platdata(struct udevice
> *dev)
>
> plat->maximum_speed = usb_get_maximum_speed(node);
> if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
> - pr_err("Invalid usb maximum speed\n");
> - return -ENODEV;
> + pr_info("no usb maximum speed specified. use super speed\n");
Nit: s/no usb/No USB/;s/use/Using/
> + plat->maximum_speed = USB_SPEED_SUPER;
> }
>
> plat->dr_mode = usb_get_dr_mode(node);
>
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] ARM: imx: cm_fx6: Drop ad-hoc SATA binding
On 5/14/19 12:28 AM, Christopher Spinrath wrote:
> Hi Marek,
Hi,
> thanks for the patch!
>
> Unfortunately, I am unable to test this patch right now, because both
> U-Boot v2019.04 and v2019.07-rc fail to boot on my (cm-fx6 based)
> Utilite Pro...
> I will debug this next weekend.
Good, please take over this patch as well. I don't even have the board.
> However, I already have one comment inline:
>
> On 5/12/19 10:43 PM, Marek Vasut wrote:
>> Drop the ad-hoc AHCI binding code, this is superseded by
>> CONFIG_DWC_AHSATA_AHCI=y resp. drivers/ata/dwc_ahsata.c
>>
>> Signed-off-by: Marek Vasut
>> Cc: Christopher Spinrath
>> Cc: Fabio Estevam
>> Cc: Igor Grinberg
>> Cc: Nikita Kiryanov
>> Cc: Stefano Babic
>> ---
>> board/compulab/cm_fx6/cm_fx6.c | 63 --
>> configs/cm_fx6_defconfig | 1 -
>> 2 files changed, 64 deletions(-)
>>
>> diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
>> index d42f57d4b7..b8f15cf3ab 100644
>> --- a/board/compulab/cm_fx6/cm_fx6.c
>> +++ b/board/compulab/cm_fx6/cm_fx6.c
>> @@ -724,66 +724,3 @@ U_BOOT_DEVICE(cm_fx6_serial) = {
>> .name = "serial_mxc",
>> .platdata = _fx6_mxc_serial_plat,
>> };
>> -
>> -#if CONFIG_IS_ENABLED(AHCI)
>> -static int sata_imx_probe(struct udevice *dev)
>> -{
>> -int i, err;
>> -
>> -/* Make sure this gpio has logical 0 value */
>> -gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
>> -udelay(100);
>> -cm_fx6_sata_power(1);
>
> The removal of this call to cm_fx6_sata_power (and the gpio
> configuration) worries me a bit.
>
> *To my understanding* the SATA controller pins on the cm-fx6 module can
> be routed either
>
> 1) directly to the daughterboard, which is then responsible for
> everything else (e.g. powering the drive); or
>
> 2) to a drive soldered on the cm-fx6 module itself. In this case the
> power sequence implemented in cm_fx6_data_power is necessary to power up
> the drive.
>
> While this patch is probably fine for modules using configuration 1), I
> think, it will cause a regression for modules using configuration 2).
>
> Can we move the call to cm_fx6_sata_power to somewhere else? (I have no
> idea, if there is a proper callback/hook/...)
>
> Optimally, we would also keep the call cm_fx6_sata_power(0) below, in
> case no drive is detected (to save some power), but well...
You probably want to describe a regulator in the boards' DT to handle
this special power sequencing requirement.
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v3 2/2] fit: Support compat string property in configuration node
Hi, > This patch adds support for an optional optimization to compatible > string matching where the compatible string property from the root node > of the kernel FDT can be copied into the configuration node of the FIT > image. This is most useful when using compressed FDTs or when using FDT > overlays, where the traditional extraction of the compatible string from > the kernel FDT itself is not easily possible. > > Signed-off-by: Julius Werner > --- > common/image-fit.c | 67 +++--- > 1 file changed, 39 insertions(+), 28 deletions(-) Can you please add a change log, as this is a v3 patch. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/2] fit: Support compression for non-kernel components (e.g. FDT)
Hi Julius, > This patch adds support for compressing non-kernel image nodes in a FIT > image (kernel nodes could already be compressed previously). This can > reduce the size of FIT images and therefore improve boot times > (especially when an image bundles many different kernel FDTs). The > images will automatically be decompressed on load. > > This patch does not support extracting compatible strings from > compressed FDTs, so it's not very helpful in conjunction with > CONFIG_FIT_BEST_MATCH yet, but it can already be used in environments > that select the configuration to load explicitly. > > Signed-off-by: Julius Werner > --- > common/image-fit.c| 86 +++ > test/py/tests/test_fit.py | 29 +++-- > 2 files changed, 77 insertions(+), 38 deletions(-) Is there a change log for this patch?I think we discussed having a test. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 5/5] rockchip: rk3328: add rock64-rk3328_defconfig
On 2019-05-13, Vagrant Cascadian wrote: > On 2019-05-13, Vagrant Cascadian wrote: >> On 2019-05-08, Matwey V. Kornilov wrote: >>> Signed-off-by: Matwey V. Kornilov >>> --- >>> configs/rock64-rk3328_defconfig | 91 >>> + >>> 1 file changed, 91 insertions(+) >>> create mode 100644 configs/rock64-rk3328_defconfig ... > Downloading the patch series from patchwork didn't include the cover > letter which explains what is needed... I'll test with that now; sorry > for the noise. > > Maybe those instructions should be included in doc/README.rockchip ? Works for me! Tested booting from microSD and PXE. Please CC me on updated patch series, if any. Tested-by: Vagrant Cascadian live well, vagrant signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 5/5] rockchip: rk3328: add rock64-rk3328_defconfig
On 2019-05-13, Vagrant Cascadian wrote: > On 2019-05-08, Matwey V. Kornilov wrote: >> Signed-off-by: Matwey V. Kornilov >> --- >> configs/rock64-rk3328_defconfig | 91 >> + >> 1 file changed, 91 insertions(+) >> create mode 100644 configs/rock64-rk3328_defconfig > > Thanks for submitting these patches upstream! > > Unfortunately, I wasn't able to get this to boot off of microSD. > > What process do you use to test this? Does it depend on patches not > present in 2019.07-rc1 or not yet merged? Downloading the patch series from patchwork didn't include the cover letter which explains what is needed... I'll test with that now; sorry for the noise. Maybe those instructions should be included in doc/README.rockchip ? live well, vagrant signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: imx: cm_fx6: Drop ad-hoc SATA binding
Hi Marek,
thanks for the patch!
Unfortunately, I am unable to test this patch right now, because both
U-Boot v2019.04 and v2019.07-rc fail to boot on my (cm-fx6 based)
Utilite Pro...
I will debug this next weekend.
However, I already have one comment inline:
On 5/12/19 10:43 PM, Marek Vasut wrote:
> Drop the ad-hoc AHCI binding code, this is superseded by
> CONFIG_DWC_AHSATA_AHCI=y resp. drivers/ata/dwc_ahsata.c
>
> Signed-off-by: Marek Vasut
> Cc: Christopher Spinrath
> Cc: Fabio Estevam
> Cc: Igor Grinberg
> Cc: Nikita Kiryanov
> Cc: Stefano Babic
> ---
> board/compulab/cm_fx6/cm_fx6.c | 63 --
> configs/cm_fx6_defconfig | 1 -
> 2 files changed, 64 deletions(-)
>
> diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
> index d42f57d4b7..b8f15cf3ab 100644
> --- a/board/compulab/cm_fx6/cm_fx6.c
> +++ b/board/compulab/cm_fx6/cm_fx6.c
> @@ -724,66 +724,3 @@ U_BOOT_DEVICE(cm_fx6_serial) = {
> .name = "serial_mxc",
> .platdata = _fx6_mxc_serial_plat,
> };
> -
> -#if CONFIG_IS_ENABLED(AHCI)
> -static int sata_imx_probe(struct udevice *dev)
> -{
> - int i, err;
> -
> - /* Make sure this gpio has logical 0 value */
> - gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
> - udelay(100);
> - cm_fx6_sata_power(1);
The removal of this call to cm_fx6_sata_power (and the gpio
configuration) worries me a bit.
*To my understanding* the SATA controller pins on the cm-fx6 module can
be routed either
1) directly to the daughterboard, which is then responsible for
everything else (e.g. powering the drive); or
2) to a drive soldered on the cm-fx6 module itself. In this case the
power sequence implemented in cm_fx6_data_power is necessary to power up
the drive.
While this patch is probably fine for modules using configuration 1), I
think, it will cause a regression for modules using configuration 2).
Can we move the call to cm_fx6_sata_power to somewhere else? (I have no
idea, if there is a proper callback/hook/...)
Optimally, we would also keep the call cm_fx6_sata_power(0) below, in
case no drive is detected (to save some power), but well...
Cheers,
Christopher
> -
> - for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
> - err = setup_sata();
> - if (err) {
> - printf("SATA setup failed: %d\n", err);
> - return err;
> - }
> -
> - udelay(100);
> -
> - err = dwc_ahsata_probe(dev);
> - if (!err)
> - break;
> -
> - /* There is no device on the SATA port */
> - if (sata_dm_port_status(0, 0) == 0)
> - break;
> -
> - /* There's a device, but link not established. Retry */
> - device_remove(dev, DM_REMOVE_NORMAL);
> - }
> -
> - return 0;
> -}
> -
> -static int sata_imx_remove(struct udevice *dev)
> -{
> - cm_fx6_sata_power(0);
> - mdelay(250);
> -
> - return 0;
> -}
> -
> -struct ahci_ops sata_imx_ops = {
> - .port_status = dwc_ahsata_port_status,
> - .reset = dwc_ahsata_bus_reset,
> - .scan = dwc_ahsata_scan,
> -};
> -
> -static const struct udevice_id sata_imx_ids[] = {
> - { .compatible = "fsl,imx6q-ahci" },
> - { }
> -};
> -
> -U_BOOT_DRIVER(sata_imx) = {
> - .name = "dwc_ahci",
> - .id = UCLASS_AHCI,
> - .of_match = sata_imx_ids,
> - .ops= _imx_ops,
> - .probe = sata_imx_probe,
> - .remove = sata_imx_remove, /* reset bus to stop it */
> -};
> -#endif /* AHCI */
> diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
> index ce3f9de3f9..e928cbc948 100644
> --- a/configs/cm_fx6_defconfig
> +++ b/configs/cm_fx6_defconfig
> @@ -52,7 +52,6 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6q-cm-fx6"
> CONFIG_ENV_IS_IN_SPI_FLASH=y
> CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> CONFIG_DWC_AHSATA=y
> -# CONFIG_DWC_AHSATA_AHCI is not set
> CONFIG_DM_KEYBOARD=y
> CONFIG_DM_MMC=y
> CONFIG_FSL_ESDHC=y
>
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Re: [U-Boot] [PATCH 3/7] warp7: include: configs: Differentiate bootscript address from loadaddr
On 09/05/2019 16:32, Bryan O'Donoghue wrote:
On 08/05/2019 20:33, Pierre-Jean Texier wrote:
Hi Bryan,
Le 08/05/2019 à 20:14, Bryan O'Donoghue a écrit :
Reusing the loadaddr to load the boot script breaks some of the logic we
want to have around the bootscript/FIT load addresses. Making a
dedicated
bootscript address allows us to differentiate the bootscript load
address
from the Linux Kernel or OPTEE load address, thus ensuring that no
matter
what the load sequence the bootscript and Kernel/OPTEE binary load
addresses do not conflict.
Signed-off-by: Bryan O'Donoghue
---
include/configs/warp7.h | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index 95955fd626..0c63050833 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -50,6 +50,7 @@
"script=boot.scr\0" \
"bootscr_fitimage_name=bootscr\0" \
"script_signed=boot.scr.imx-signed\0" \
+ "bootscriptaddr=0x8320\0" \
"image=zImage\0" \
"console=ttymxc0\0" \
"ethact=usb_ether\0" \
@@ -70,16 +71,16 @@
"warp7_auth_or_fail=hab_auth_img_or_fail ${hab_ivt_addr}
${filesize} 0;\0" \
"do_bootscript_hab=" \
"if test ${hab_enabled} -eq 1; then " \
- "setexpr hab_ivt_addr ${loadaddr} - ${ivt_offset}; " \
+ "setexpr hab_ivt_addr ${bootscriptaddr} - ${ivt_offset};
" \
"setenv script ${script_signed}; " \
"load mmc ${mmcdev}:${mmcpart} ${hab_ivt_addr}
${script}; " \
"run warp7_auth_or_fail; " \
"run bootscript; "\
"fi;\0" \
"loadbootscript=" \
- "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "load mmc ${mmcdev}:${mmcpart} ${bootscriptaddr}
${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
- "source\0" \
+ BOOT_SCR_STRING \
"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr}
${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
Instead of implementing a new variable (bootscriptaddr), I think
(IMHO) it's time to migrate
to distroboot for the WaRP7 (like pico imx7 for instance >
In fact, in this specific case, this allows to use the common
scriptaddr[1] variable.
FYI, this is a task I am currently working on [2] (work in progress).
Maybe we could integrate this migration into this series ?
Sure.
Let me give it a test later tonight/tomorrow
Hi Pierre,
I've applied your patch on-top of of a 3 day old master
* 60277e4bcc - (HEAD) warp7: add distroboot support (27 hours ago)
* 4ca7700d2c - imx: Use a convenient default value for SYS_MALLOC_F_LEN
(27 hours ago)
* 48372a5af6 - Remove whitelist entry for CONFIG_CRC32 (3 days ago)
* 4ad2c8953d - Remove #define CONFIG_CRC32 (3 days ago)
* 661bbc50d3 - mtd: ubi: Remove select for non existent option (3 days ago)
* 2b841dba5c - cmd: ubifs: Remove select for non-existent option (3 days
ago)
* b8de00c671 - Remove whitelist entry for CONFIG_GPIO (3 days ago)
* 26680b9f3a - sysreset: select DM_GPIO instead of GPIO (3 days ago)
* 927a37df9f - Merge branch '2019-05-09-master-imports' (3 days ago)
should this apply in isolation ?
I get a dead-loop on USB CDC ethernet...
=> reset
resetting ...
U-Boot 2019.07-rc1-00457-g60277e4bcc (May 13 2019 - 23:11:24 +0100)
CPU: Freescale i.MX7S rev1.2 800 MHz (running at 792 MHz)
CPU: Extended Commercial temperature grade (-20C to 105C) at 47C
Reset cause: POR
Model: Warp i.MX7 Board
Board: WARP7 in secure mode OPTEE DRAM 0x9d00-0xa000
DRAM: 464 MiB
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11
MMC: FSL_SDHC: 1, FSL_SDHC: 0
Loading Environment from MMC... *** Warning - bad CRC, using default
environment
In:serial@3086
Out: serial@3086
Err: serial@3086
SEC0: RNG instantiated
Net: usb_ether
Warning: usb_ether (eth0) using random MAC address - b6:5e:3c:03:d8:8e
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0(part 0) is current device
Scanning mmc 0:1...
Found U-Boot script /boot.scr
11090492 bytes read in 146 ms (72.4 MiB/s)
## Executing script at 8080
No FIT subimage unit name
SCRIPT FAILED: continuing...
28970 bytes read in 7 ms (3.9 MiB/s)
starting USB...
Bus usb@30b1: scanning bus usb@30b1 for devices... 1 USB
Device(s) found
using ci_udc, OUT ep2out-bulk IN ep1in-bulk STATUS ep3in-int
MAC de:ad:be:af:00:01
HOST MAC de:ad:be:af:00:00
high speed config #1: 2 mA, Ethernet Gadget, using CDC Ethernet
The remote end did not respond in time.missing environment variable: pxeuuid
missing environment variable: bootfile
Retrieving file: pxelinux.cfg/
using ci_udc, OUT ep2out-bulk IN ep1in-bulk STATUS ep3in-int
MAC de:ad:be:af:00:01
HOST MAC de:ad:be:af:00:00
high speed config #1: 2 mA, Ethernet Gadget, using CDC Ethernet
The remote end did not respond in time.missing environment variable:
[U-Boot] [PATCH 1/1] flash-kernel: Marvell 8040 MACCHIATOBin Double-shot
Package: flash-kernel Version: 3.98 Severity: normal Tags: patch The model property in armada-8040-mcbin.dtb has been changed to 'Marvell 8040 MACCHIATOBin Double-shot' in Linux kernel 5.0. A new board 'Marvell 8040 MACCHIATOBin Single-shot' has been added. Signed-off-by: Heinrich Schuchardt --- db/all.db | 8 1 file changed, 8 insertions(+) diff --git a/db/all.db b/db/all.db index 0839d50..f386b75 100644 --- a/db/all.db +++ b/db/all.db @@ -945,6 +945,7 @@ U-Boot-Script-Name: bootscr.uboot-generic Required-Packages: u-boot-tools Machine: Marvell 8040 MACCHIATOBin +Machine: Marvell 8040 MACCHIATOBin Double-shot Machine: Marvell 8040 MACHIATOBin Kernel-Flavors: arm64 DTB-Id: marvell/armada-8040-mcbin.dtb @@ -952,6 +953,13 @@ Boot-Script-Path: /boot/boot.scr U-Boot-Script-Name: bootscr.uboot-generic Required-Packages: u-boot-tools +Machine: Marvell 8040 MACCHIATOBin Single-shot +Kernel-Flavors: arm64 +DTB-Id: marvell/armada-8040-mcbin-singleshot.dtb +Boot-Script-Path: /boot/boot.scr +U-Boot-Script-Name: bootscr.uboot-generic +Required-Packages: u-boot-tools + # Marvell dev board has different names depending on how it's booted, # via DTB or older ATAGS Machine: Marvell Armada XP GP Board -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/2] arm: socfpga: remove re-added ad-hoc reset code
commit c5de2b7eae68 ("arm: socfpga: implement proper peripheral reset")
has removed the call to 'reset_deassert_peripherals_handoff()' from
socfpga gen5 SPL since the reset driver now handles resets. However,
commit c1d4b464c8b8 ("ARM: socfpga: Disable bridges in SPL unless booting from
FPGA")
has re-added this ad-hoc reset code, so that all peripherals were now
again enabled instead of letting the drivers enable them by request.
While at it, remove this function for gen5 as it should not be used.
Fixes: commit c1d4b464c8b8 ("ARM: socfpga: Disable bridges in SPL unless
booting from FPGA")
Signed-off-by: Simon Goldschmidt
---
arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h | 1 -
arch/arm/mach-socfpga/reset_manager_gen5.c | 8
arch/arm/mach-socfpga/spl_gen5.c| 3 +--
3 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
index 5e490d182e..f4dcb14623 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -8,7 +8,6 @@
#include
-void reset_deassert_peripherals_handoff(void);
void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
void socfpga_bridges_reset(int enable);
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c
b/arch/arm/mach-socfpga/reset_manager_gen5.c
index 89a384b59c..9a32f5abfe 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -61,14 +61,6 @@ void socfpga_per_reset_all(void)
writel(0x, _manager_base->per2_mod_reset);
}
-/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
-{
- writel(0, _manager_base->per_mod_reset);
-}
-
#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
#define L3REGS_REMAP_HPS2FPGA_MASK 0x08
#define L3REGS_REMAP_OCRAM_MASK0x01
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index bd2a9fe5ae..1a60cdc897 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -175,8 +175,7 @@ void board_init_f(ulong dummy)
sysmgr_pinmux_init();
sysmgr_config_warmrstcfgio(0);
- /* De-assert reset for peripherals and bridges based on handoff */
- reset_deassert_peripherals_handoff();
+ /* Set bridges handoff value */
socfpga_bridges_set_handoff_regs(true, true, true);
debug("Unfreezing/Thaw all I/O banks\n");
--
2.20.1
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[U-Boot] [PATCH 2/2] arm: sofcpga: s10: remove unused ad-hoc reset code
The stratix 10 reset manager ad-hoc code in arch/arm contains an unused
function 'reset_deassert_peripherals_handoff' that has been added from
the beginning. As this is probably a result of copying the gen5 reset
manager and this function has never been used, remove it.
Signed-off-by: Simon Goldschmidt
---
.../arm/mach-socfpga/include/mach/reset_manager_s10.h | 1 -
arch/arm/mach-socfpga/reset_manager_s10.c | 11 ---
2 files changed, 12 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
index b93bbaf537..452147b017 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -8,7 +8,6 @@
#define_RESET_MANAGER_S10_
void reset_cpu(ulong addr);
-void reset_deassert_peripherals_handoff(void);
int cpu_has_been_warmreset(void);
void socfpga_bridges_reset(int enable);
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
b/arch/arm/mach-socfpga/reset_manager_s10.c
index 39753a13c4..499a84aff5 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -94,17 +94,6 @@ void socfpga_bridges_reset(int enable)
}
}
-/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
-{
- writel(0, _manager_base->per1modrst);
- /* Enable OCP first */
- writel(~RSTMGR_PER0MODRST_OCP_MASK, _manager_base->per0modrst);
- writel(0, _manager_base->per0modrst);
-}
-
/*
* Return non-zero if the CPU has been warm reset
*/
--
2.20.1
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Re: [U-Boot] [PATCH 1/2] arm: socfpga: remove re-added ad-hoc reset code
Unfortunately, there's 2/2 (which removes this unused function from s10,
too) missing here since patman won't let me send the mail due to "Ang"
(from Ang, Chee Hong ) not being a well-formed
email address...
I'll work on that and re-send...
Regards,
Simon
Am 13.05.2019 um 21:09 schrieb Simon Goldschmidt:
commit c5de2b7eae68 ("arm: socfpga: implement proper peripheral reset")
has removed the call to 'reset_deassert_peripherals_handoff()' from
socfpga gen5 SPL since the reset driver now handles resets. However,
commit c1d4b464c8b8 ("ARM: socfpga: Disable bridges in SPL unless booting from
FPGA")
has re-added this ad-hoc reset code, so that all peripherals were now
again enabled instead of letting the drivers enable them by request.
While at it, remove this function for gen5 as it should not be used.
Fixes: commit c1d4b464c8b8 ("ARM: socfpga: Disable bridges in SPL unless booting
from FPGA")
Signed-off-by: Simon Goldschmidt
---
arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h | 1 -
arch/arm/mach-socfpga/reset_manager_gen5.c | 8
arch/arm/mach-socfpga/spl_gen5.c| 3 +--
3 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
index 5e490d182e..f4dcb14623 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -8,7 +8,6 @@
#include
-void reset_deassert_peripherals_handoff(void);
void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
void socfpga_bridges_reset(int enable);
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c
index 89a384b59c..9a32f5abfe 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -61,14 +61,6 @@ void socfpga_per_reset_all(void)
writel(0x, _manager_base->per2_mod_reset);
}
-/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
-{
- writel(0, _manager_base->per_mod_reset);
-}
-
#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
#define L3REGS_REMAP_HPS2FPGA_MASK0x08
#define L3REGS_REMAP_OCRAM_MASK 0x01
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index bd2a9fe5ae..1a60cdc897 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -175,8 +175,7 @@ void board_init_f(ulong dummy)
sysmgr_pinmux_init();
sysmgr_config_warmrstcfgio(0);
- /* De-assert reset for peripherals and bridges based on handoff */
- reset_deassert_peripherals_handoff();
+ /* Set bridges handoff value */
socfpga_bridges_set_handoff_regs(true, true, true);
debug("Unfreezing/Thaw all I/O banks\n");
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[U-Boot] [PATCH 1/2] arm: socfpga: remove re-added ad-hoc reset code
commit c5de2b7eae68 ("arm: socfpga: implement proper peripheral reset")
has removed the call to 'reset_deassert_peripherals_handoff()' from
socfpga gen5 SPL since the reset driver now handles resets. However,
commit c1d4b464c8b8 ("ARM: socfpga: Disable bridges in SPL unless booting from
FPGA")
has re-added this ad-hoc reset code, so that all peripherals were now
again enabled instead of letting the drivers enable them by request.
While at it, remove this function for gen5 as it should not be used.
Fixes: commit c1d4b464c8b8 ("ARM: socfpga: Disable bridges in SPL unless
booting from FPGA")
Signed-off-by: Simon Goldschmidt
---
arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h | 1 -
arch/arm/mach-socfpga/reset_manager_gen5.c | 8
arch/arm/mach-socfpga/spl_gen5.c| 3 +--
3 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
index 5e490d182e..f4dcb14623 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -8,7 +8,6 @@
#include
-void reset_deassert_peripherals_handoff(void);
void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
void socfpga_bridges_reset(int enable);
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c
b/arch/arm/mach-socfpga/reset_manager_gen5.c
index 89a384b59c..9a32f5abfe 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -61,14 +61,6 @@ void socfpga_per_reset_all(void)
writel(0x, _manager_base->per2_mod_reset);
}
-/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
-{
- writel(0, _manager_base->per_mod_reset);
-}
-
#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
#define L3REGS_REMAP_HPS2FPGA_MASK 0x08
#define L3REGS_REMAP_OCRAM_MASK0x01
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index bd2a9fe5ae..1a60cdc897 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -175,8 +175,7 @@ void board_init_f(ulong dummy)
sysmgr_pinmux_init();
sysmgr_config_warmrstcfgio(0);
- /* De-assert reset for peripherals and bridges based on handoff */
- reset_deassert_peripherals_handoff();
+ /* Set bridges handoff value */
socfpga_bridges_set_handoff_regs(true, true, true);
debug("Unfreezing/Thaw all I/O banks\n");
--
2.20.1
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Re: [U-Boot] [PATCH v2] include: android_bl_msg.h: Initial import
I subscribe to the license-related question raised by Akashi and Sam (thank you both)! Tom's feedback is required before I push the next revision of the BCB command. On Mon, May 13, 2019 at 4:12 PM Sam Protsenko wrote: [..] > > Which license, BSD-2 (in SPDX) or Apache v2, is applied to this file? > > If the latter, it is said incompatible with GPLv2, isn't it? > > > > This file was also published by Google under BSD-2 in AOSP > external/u-boot [1]. But it differs somehow from the file in this > patch. > > Tom, should we use this file from [1] to be on the safe side of the > road? Or it's ok to take it directly from [2], as it's done here? > > Thanks! > > [1] > https://android.googlesource.com/platform/external/u-boot/+/c7f85c5f75f95dbbd3cedcc3a399eee6dbb59cdc > [2] > https://android.googlesource.com/platform/bootable/recovery/+/refs/heads/master/bootloader_message/include/bootloader_message/bootloader_message.h > > > -Takahiro Akashi -- Best regards, Eugeniu. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] net: phy: ti: Fix clock output DT property
On 10.05.19 20:49, Trent Piepho wrote: > The code block reading the DT property for the clock output control was > before the phy's DT node pointer was set, so it could never work. Move > it after the node pointer is set. > > Also store the unsigned 32-bit property into an unsigned value, not a > signed value, as the former will cause a problem if value overflows. > For instance, if one were to add 0x as a code to mean the clock > output should be turned off. > > Cc: Joe Hershberger > Cc: Janine Hagemann > Cc: Grygorii Strashko > Signed-off-by: Trent Piepho > --- > drivers/net/phy/ti.c | 16 +--- > 1 file changed, 5 insertions(+), 11 deletions(-) > Reviewed-by: Grygorii Strashko -- Best regards, grygorii ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 10/11] evb-ast2500: Enable CONFIG_DM_MMC
Sounds good to me. Reviewed-by: Maksym Sloyko From: Simon Glass Date: Sat, May 11, 2019 at 12:26 PM To: U-Boot Mailing List Cc: Tom Rini, Marek Vasut, Simon Glass, Maxim Sloyko > This board builds with this option (although it may not work). Enable it > to stave off board removal for a bit. > > Signed-off-by: Simon Glass > --- > > configs/evb-ast2500_defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig > index 7fb52d2732..bf630df565 100644 > --- a/configs/evb-ast2500_defconfig > +++ b/configs/evb-ast2500_defconfig > @@ -20,6 +20,7 @@ CONFIG_REGMAP=y > CONFIG_CLK=y > CONFIG_DM_I2C=y > CONFIG_SYS_I2C_ASPEED=y > +CONFIG_DM_MMC=y > CONFIG_PHY_REALTEK=y > CONFIG_DM_ETH=y > CONFIG_FTGMAC100=y > -- > 2.21.0.1020.gf2820cf01a-goog > -- Maxim Sloyko ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 5/5] rockchip: rk3328: add rock64-rk3328_defconfig
On 2019-05-08, Matwey V. Kornilov wrote: > Signed-off-by: Matwey V. Kornilov > --- > configs/rock64-rk3328_defconfig | 91 > + > 1 file changed, 91 insertions(+) > create mode 100644 configs/rock64-rk3328_defconfig Thanks for submitting these patches upstream! Unfortunately, I wasn't able to get this to boot off of microSD. What process do you use to test this? Does it depend on patches not present in 2019.07-rc1 or not yet merged? The process I tried after building upstream arm-trusted-firmware 2.1: mkimage -T rksd -n rk3328 -d spl/u-boot-spl.bin u-boot-spl.rksd dd if=u-boot-spl.rksd of=/dev/sdb seek=64 dd if=u-boot.itb of=/dev/sdb seek=16384 There was no output on the serial console, either at 150 or 115200. live well, vagrant > diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig > new file mode 100644 > index 00..b278315035 > --- /dev/null > +++ b/configs/rock64-rk3328_defconfig > @@ -0,0 +1,91 @@ > +CONFIG_SMBIOS_MANUFACTURER="pine64" > +CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328" > +CONFIG_ARM=y > +CONFIG_ARCH_ROCKCHIP=y > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > +CONFIG_SYS_MALLOC_F_LEN=0x2000 > +CONFIG_SYS_TEXT_BASE=0x0020 > +CONFIG_ROCKCHIP_RK3328=y > +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 > +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y > +CONFIG_SPL_STACK_R_ADDR=0x60 > +CONFIG_DEBUG_UART_BASE=0xFF13 > +CONFIG_DEBUG_UART_CLOCK=2400 > +CONFIG_DEBUG_UART=y > +CONFIG_NR_DRAM_BANKS=1 > +# CONFIG_ANDROID_BOOT_IMAGE is not set > +CONFIG_FIT=y > +CONFIG_FIT_VERBOSE=y > +CONFIG_SPL_LOAD_FIT=y > +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" > +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" > +# CONFIG_DISPLAY_CPUINFO is not set > +CONFIG_DISPLAY_BOARDINFO_LATE=y > +CONFIG_SPL_STACK_R=y > +CONFIG_SPL_ATF=y > +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y > +CONFIG_FASTBOOT_BUF_ADDR=0x800800 > +CONFIG_FASTBOOT_FLASH=y > +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 > +CONFIG_CMD_BOOTZ=y > +CONFIG_CMD_GPT=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_SF=y > +CONFIG_CMD_USB=y > +# CONFIG_CMD_SETEXPR is not set > +CONFIG_CMD_TIME=y > +CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" > +CONFIG_SPL_OF_CONTROL=y > +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names > interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" > +CONFIG_ENV_IS_IN_MMC=y > +CONFIG_NET_RANDOM_ETHADDR=y > +CONFIG_REGMAP=y > +CONFIG_SPL_REGMAP=y > +CONFIG_SYSCON=y > +CONFIG_SPL_SYSCON=y > +CONFIG_CLK=y > +CONFIG_SPL_CLK=y > +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y > +CONFIG_ROCKCHIP_GPIO=y > +CONFIG_SYS_I2C_ROCKCHIP=y > +CONFIG_MMC_DW=y > +CONFIG_MMC_DW_ROCKCHIP=y > +CONFIG_SPI_FLASH=y > +CONFIG_SF_DEFAULT_SPEED=2000 > +CONFIG_DM_ETH=y > +CONFIG_ETH_DESIGNWARE=y > +CONFIG_GMAC_ROCKCHIP=y > +CONFIG_PHY=y > +CONFIG_PINCTRL=y > +CONFIG_SPL_PINCTRL=y > +CONFIG_PINCTRL_ROCKCHIP_RK3328=y > +CONFIG_DM_PMIC=y > +CONFIG_PMIC_RK8XX=y > +CONFIG_REGULATOR_PWM=y > +CONFIG_DM_REGULATOR_FIXED=y > +CONFIG_REGULATOR_RK8XX=y > +CONFIG_PWM_ROCKCHIP=y > +CONFIG_RAM=y > +CONFIG_SPL_RAM=y > +CONFIG_DM_RESET=y > +CONFIG_BAUDRATE=150 > +CONFIG_DEBUG_UART_SHIFT=2 > +CONFIG_SYSRESET=y > +CONFIG_USB=y > +CONFIG_USB_XHCI_HCD=y > +CONFIG_USB_XHCI_DWC3=y > +CONFIG_USB_EHCI_HCD=y > +CONFIG_USB_EHCI_GENERIC=y > +CONFIG_USB_OHCI_HCD=y > +CONFIG_USB_OHCI_GENERIC=y > +CONFIG_USB_DWC2=y > +CONFIG_USB_DWC3=y > +CONFIG_USB_GADGET=y > +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" > +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 > +CONFIG_USB_GADGET_PRODUCT_NUM=0x330a > +CONFIG_USB_GADGET_DWC2_OTG=y > +CONFIG_USE_TINY_PRINTF=y > +CONFIG_SPL_TINY_MEMSET=y > +CONFIG_ERRNO_STR=y signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 1/1] imx8: cpu: fix warning for cpu_imx_get_temp
cpu_imx_get_temp() definition is wrapped with a ifdef macro, which leads
to warnings if CONFIG_IMX_SCU_THERMAL isn't defined and there are still
references to this function, as, for example, in cpu_imx_get_desc().
Drop ifdef as linker will automatically remove the function
in case CONFIG_IMX_SCU_THERMAL is not enabled.
Fix warning:
arch/arm/mach-imx/imx8/cpu.c: In function ‘cpu_imx_get_desc’:
arch/arm/mach-imx/imx8/cpu.c:612:40: warning: implicit declaration of
function ‘cpu_imx_get_temp’; did you mean ‘cpu_imx_get_desc’?
[-Wimplicit-function-declaration]
ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp());
^~~~
cpu_imx_get_desc
cpu_imx_get_desc
Fixes: 82467cb217 ("imx8: cpu: get temperature when print cpu desc")
Signed-off-by: Igor Opaniuk
---
v2:
- address Stefan's comments and drop the ifdef instead
arch/arm/mach-imx/imx8/cpu.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 12596c6387..1be63af7f3 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -574,7 +574,6 @@ const char *get_core_name(void)
return "?";
}
-#if defined(CONFIG_IMX_SCU_THERMAL)
static int cpu_imx_get_temp(void)
{
struct udevice *thermal_dev;
@@ -593,7 +592,6 @@ static int cpu_imx_get_temp(void)
return cpu_tmp;
}
-#endif
int cpu_imx_get_desc(struct udevice *dev, char *buf, int size)
{
--
2.17.1
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[U-Boot] [PATCH v2 00/18] Improvement for the DWC3 USB generic driver and fixes for the K2 platforms
The K2 platforms have shown boot issues after switching to the DWC3 generic
driver. Those are due to the fact that the USB domains are not turned off
before booting linux and the phy were not properly initialized. Fixing it
by improving the DWC3-generic driver and handling the USB power domain in
the PHY driver.
At the same time this series introduce a new uclass (UCLASS_NOP) to replace
usage of UCLASS_MISC in the USB wrapper because the MISC class now
automatically binds all the child devices.
Improvements to the DWC3 generic driver are:
- Fix it by switching to UCLASS_NOP
- core: read quirks properties from DT and apply the fixes.
- add a new host driver that uses the DWC3 core (more generic than
xhci-dwc3). This should enable most platforms to drop their own version
of the xhci-driver to use the generic one instead.
This series also removes the now unused xhci-zynqmp driver and tries to
better manage the Kconfig options related to DWC3 gadget/host mode
selection.
This has been tested with K2 and DRA7 platforms (host and device modes).
Travis build: https://travis-ci.org/jjhiblot/u-boot/builds/515282720
Changes in v2:
- Add a test for the NOP uclass
- Update commit logs
- Select USB_GADGET_DUALSPEED if USB_DWC3_GADGET is selected
Jean-Jacques Hiblot (18):
usb: dwc3-generic: remove dm_scan_fdt_dev() from the remove() callback
usb: host: remove the xhci-zynqmp driver
dm: Add a No-op uclass
usb: dwc3: Use UCLASS_NOP instead of UCLASS_MISC for the DWC3 generic
glue
usb: dwc3: switch to peripheral mode when exiting
usb: xhci: move xhci.h to include usb
usb: dwc3: always use the inlined version of
dwc3_host_init/dwc3_host_exit
usb: dwc3-generic: use platdata
usb: dwc3-generic: factorize code
usb: dwc3-generic: add a new host driver that uses the dwc3 core
usb: dwc3-generic: if no max speed is specified in DT, assume super
speed
usb: dwc3: Add dwc3_of_parse() to get quirks information from DT
usb: dwc3: Kconfig: get rid of obsolete mode selection
ARM: keystone: increase PSC timeout
ARM: keystone: Do not enable the USB power domains at the board level
phy: keystone-usb: handle the transition of the USB power domain
configs: k2g_evm_defconfig: disable XHCI_DWC3 and enable
KEYSTONE_USB_PHY
ARM: DTS: keystone: complete the description of the USB PHY devices
MAINTAINERS | 1 +
arch/arm/dts/keystone-k2e-evm-u-boot.dtsi | 32
arch/arm/dts/keystone-k2g-evm-u-boot.dtsi | 28
arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi| 14 ++
arch/arm/dts/keystone-k2l-evm-u-boot.dtsi | 18 +++
.../arm/mach-keystone/include/mach/psc_defs.h | 2 +-
arch/sandbox/dts/test.dts | 12 ++
board/ti/ks2_evm/board.c | 13 --
configs/avnet_ultra96_rev1_defconfig | 1 -
configs/evb-rk3328_defconfig | 1 +
configs/k2g_evm_defconfig | 3 +-
.../xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 -
.../xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 -
.../xilinx_zynqmp_zc1751_xm017_dc3_defconfig | 1 -
configs/xilinx_zynqmp_zcu100_revC_defconfig | 1 -
configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 -
configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 -
configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 -
configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 -
configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 -
configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 -
configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 -
drivers/core/uclass.c | 5 +
drivers/phy/keystone-usb-phy.c| 22 +++
drivers/usb/dwc3/Kconfig | 18 +--
drivers/usb/dwc3/core.c | 84 +-
drivers/usb/dwc3/core.h | 6 +-
drivers/usb/dwc3/dwc3-generic.c | 150 ++
drivers/usb/host/Kconfig | 7 -
drivers/usb/host/Makefile | 1 -
drivers/usb/host/xhci-dwc3.c | 2 +-
drivers/usb/host/xhci-exynos5.c | 2 +-
drivers/usb/host/xhci-fsl.c | 2 +-
drivers/usb/host/xhci-mem.c | 2 +-
drivers/usb/host/xhci-mvebu.c | 2 +-
drivers/usb/host/xhci-omap.c | 2 +-
drivers/usb/host/xhci-pci.c | 2 +-
drivers/usb/host/xhci-rcar.c | 2 +-
drivers/usb/host/xhci-ring.c | 2 +-
drivers/usb/host/xhci-rockchip.c | 2 +-
drivers/usb/host/xhci-zynqmp.c| 146 -
drivers/usb/host/xhci.c | 2 +-
drivers/usb/phy/omap_usb_phy.c| 2 +-
include/dm/uclass-id.h| 1 +
{drivers/usb/host => include/usb}/xhci.h | 0
test/dm/Makefile | 1 +
test/dm/nop.c
[U-Boot] [PATCH v2 18/18] ARM: DTS: keystone: complete the description of the USB PHY devices
As the PHY driver now handles the transitions of USB power domain, we
must add this information in the node of each PHY.
Also, the phy are expected in the "phys" property, not "usb-phys".
Also add the aliases for the USB ports on boards with more than a single
port.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2: None
arch/arm/dts/keystone-k2e-evm-u-boot.dtsi | 32 ++
arch/arm/dts/keystone-k2g-evm-u-boot.dtsi | 28 +++
arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi | 14 ++
arch/arm/dts/keystone-k2l-evm-u-boot.dtsi | 18
4 files changed, 92 insertions(+)
create mode 100644 arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
diff --git a/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi
b/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi
index aecb4dde68..c94165ffe7 100644
--- a/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi
@@ -7,8 +7,40 @@
soc {
u-boot,dm-pre-reloc;
};
+ aliases {
+ usb0 =
+ usb1 =
+ };
};
{
u-boot,dm-pre-reloc;
};
+
+_phy {
+ #phy-cells = <0>;
+ psc-domain = <2>;
+};
+
+ {
+ dwc3@269 {
+ phys = <_phy>;
+ dr_mode = "host";
+ snps,u2ss_inp3_quirk;
+ status = "okay";
+ };
+};
+
+_phy {
+ #phy-cells = <0>;
+ psc-domain = <1>;
+};
+
+ {
+ dwc3@2501 {
+ phys = <_phy>;
+ dr_mode = "peripheral";
+ snps,u2ss_inp3_quirk;
+ status = "okay";
+ };
+};
diff --git a/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
b/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
index 80f1f60045..e8e70096ea 100644
--- a/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
@@ -7,6 +7,10 @@
soc {
u-boot,dm-pre-reloc;
};
+ aliases {
+ usb0 =
+ usb1 =
+ };
};
{
@@ -16,3 +20,27 @@
{
u-boot,dm-pre-reloc;
};
+
+_phy {
+ compatible = "ti,keystone-usbphy";
+ #phy-cells = <0>;
+ reg = <0x2620738 24>;
+ psc-domain = <25>;
+};
+
+ {
+ phys = <_phy>;
+ snps,u2ss_inp3_quirk;
+};
+
+_phy {
+ compatible = "ti,keystone-usbphy";
+ #phy-cells = <0>;
+ reg = <0x2620750 24>;
+ psc-domain = <26>;
+};
+
+ {
+ phys = <_phy>;
+ snps,u2ss_inp3_quirk;
+};
diff --git a/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi
b/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi
index aecb4dde68..1c2f349f5c 100644
--- a/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi
@@ -12,3 +12,17 @@
{
u-boot,dm-pre-reloc;
};
+
+_phy {
+ #phy-cells = <0>;
+ psc-domain = <2>;
+};
+
+ {
+ dwc3@269 {
+ phys = <_phy>;
+ dr_mode = "host";
+ snps,u2ss_inp3_quirk;
+ status = "okay";
+ };
+};
diff --git a/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
b/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
new file mode 100644
index 00..0a507d0210
--- /dev/null
+++ b/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+_phy {
+ #phy-cells = <0>;
+ psc-domain = <2>;
+};
+
+ {
+ dwc3@269 {
+ phys = <_phy>;
+ dr_mode = "host";
+ snps,u2ss_inp3_quirk;
+ status = "okay";
+ };
+};
--
2.17.1
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[U-Boot] [PATCH v2 11/18] usb: dwc3-generic: if no max speed is specified in DT, assume super speed
There is no need to fail if the maximum speed is not specified.
If the speed is not specified, do the same as linux and assume super speed.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2: None
drivers/usb/dwc3/dwc3-generic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 4924d07553..3d008496f3 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -89,8 +89,8 @@ static int dwc3_generic_ofdata_to_platdata(struct udevice
*dev)
plat->maximum_speed = usb_get_maximum_speed(node);
if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
- pr_err("Invalid usb maximum speed\n");
- return -ENODEV;
+ pr_info("no usb maximum speed specified. use super speed\n");
+ plat->maximum_speed = USB_SPEED_SUPER;
}
plat->dr_mode = usb_get_dr_mode(node);
--
2.17.1
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[U-Boot] [PATCH v2 14/18] ARM: keystone: increase PSC timeout
Turning off the USB clocks may take longer than 100us. Increase the timeout to 100ms. Signed-off-by: Jean-Jacques Hiblot --- Changes in v2: None arch/arm/mach-keystone/include/mach/psc_defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-keystone/include/mach/psc_defs.h b/arch/arm/mach-keystone/include/mach/psc_defs.h index dfc22d5e90..f164f95bf2 100644 --- a/arch/arm/mach-keystone/include/mach/psc_defs.h +++ b/arch/arm/mach-keystone/include/mach/psc_defs.h @@ -94,7 +94,7 @@ static inline u32 boot_set_bitfield(u32 z, u32 f, u32 x, u32 y) * Timeout limit on checking PTSTAT. This is the number of times the * wait function will be called before giving up. */ -#define PSC_PTSTAT_TIMEOUT_LIMIT100 +#define PSC_PTSTAT_TIMEOUT_LIMIT10 u32 psc_get_domain_num(u32 mod_num); int psc_enable_module(u32 mod_num); -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 17/18] configs: k2g_evm_defconfig: disable XHCI_DWC3 and enable KEYSTONE_USB_PHY
KEYSTONE_USB_PHY is now required for proper USB operations. XHCI_DWC3 can be disabled as the xhci-dwc3 is not used anymore USB_DWC3_GADGET can also be removed, it is now selected automatically. Signed-off-by: Jean-Jacques Hiblot --- Changes in v2: None configs/k2g_evm_defconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 0c554dfc7f..0b23837a80 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -57,6 +57,7 @@ CONFIG_MII=y CONFIG_DRIVER_TI_KEYSTONE_NET=y CONFIG_PHY=y CONFIG_NOP_PHY=y +CONFIG_KEYSTONE_USB_PHY=y CONFIG_REMOTEPROC_TI_POWER=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y @@ -67,9 +68,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DOWNLOAD=y -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 13/18] usb: dwc3: Kconfig: get rid of obsolete mode selection
The mode selection for the DWC3 is kind of obsolete. The driver does not have to be host only or gadget only. This choice is confusing. All the remaining callers of dwc3_uboot_init() explicitly set dr_mode before calling the function, so none rely on a default behavior. Remove the choice menu and keep only the USB_DWC3_GADGET option. Enable it by default if USB_GADGET and USB_DWC3 are enabled. It must be disabled for the evb-rk3328 as it uses DWC2 for the gadget and DWC3 for the host. Signed-off-by: Jean-Jacques Hiblot --- Changes in v2: Select USB_GADGET_DUALSPEED if USB_DWC3_GADGET is selected configs/evb-rk3328_defconfig | 1 + drivers/usb/dwc3/Kconfig | 18 ++ drivers/usb/dwc3/core.c | 4 ++-- 3 files changed, 5 insertions(+), 18 deletions(-) diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index aff9c32362..98929f220a 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -58,6 +58,7 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 25e1a38aee..c302486291 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -7,25 +7,11 @@ config USB_DWC3 if USB_DWC3 -choice - bool "DWC3 Mode Selection" - -config USB_DWC3_HOST - bool "Host only mode" - depends on USB - help - Select this when you want to use DWC3 in host mode only, - thereby the gadget feature will be regressed. - config USB_DWC3_GADGET - bool "Gadget only mode" + bool "USB Gadget support for DWC3" + default y depends on USB_GADGET select USB_GADGET_DUALSPEED - help - Select this when you want to use DWC3 in gadget mode only, - thereby the host feature will be regressed. - -endchoice comment "Platform Glue Driver Support" diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 1baad39796..9f7f053265 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -707,9 +707,9 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev) return -ENOMEM; } - if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) + if (!IS_ENABLED(USB_DWC3_GADGET)) dwc->dr_mode = USB_DR_MODE_HOST; - else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) + else if (!IS_ENABLED(CONFIG_USB_HOST)) dwc->dr_mode = USB_DR_MODE_PERIPHERAL; if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 10/18] usb: dwc3-generic: add a new host driver that uses the dwc3 core
Currently the host driver used by dwc3-generic is "xhci-dwc3". This is
a functional driver but it doesn't use the dwc3 core and, in particular,
it lacks some bits that may be important.
For example on the k2 platforms, it is important that the phy are properly
suspended when the USB is not used anymore. The dwc3 core also has a
partial support for quirks.
The new driver can be used as a drop-in replacement for "xhci-dwc3".
In terms of implementation, it may seem strange that 2 private structures
dwc3_generic_host_priv and dwc3_generic_priv) are used. The reason for this
is simply that the xhci layer expects a struct xhci_ctrl at the beginning
of the private data and it seemed wasteful to include it also for the
peripheral case.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2: None
drivers/usb/dwc3/core.c | 2 +-
drivers/usb/dwc3/dwc3-generic.c | 54 -
2 files changed, 54 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index ae01490306..653c874fa6 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -887,7 +887,7 @@ int dwc3_shutdown_phy(struct udevice *dev, struct phy
*usb_phys, int num_phys)
}
#endif
-#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+#if CONFIG_IS_ENABLED(DM_USB)
int dwc3_init(struct dwc3 *dwc)
{
int ret;
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index d5c71d024f..4924d07553 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -21,6 +21,7 @@
#include "gadget.h"
#include
#include
+#include
struct dwc3_generic_plat {
fdt_addr_t base;
@@ -35,6 +36,11 @@ struct dwc3_generic_priv {
int num_phys;
};
+struct dwc3_generic_host_priv {
+ struct xhci_ctrl xhci_ctrl;
+ struct dwc3_generic_priv gen_priv;
+};
+
static int dwc3_generic_probe(struct udevice *dev,
struct dwc3_generic_priv *priv)
{
@@ -132,6 +138,50 @@ U_BOOT_DRIVER(dwc3_generic_peripheral) = {
};
#endif
+#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
+static int dwc3_generic_host_probe(struct udevice *dev)
+{
+ struct xhci_hcor *hcor;
+ struct xhci_hccr *hccr;
+ struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
+ int rc;
+
+ rc = dwc3_generic_probe(dev, >gen_priv);
+ if (rc)
+ return rc;
+
+ hccr = (struct xhci_hccr *)priv->gen_priv.base;
+ hcor = (struct xhci_hcor *)(priv->gen_priv.base +
+ HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
+
+ return xhci_register(dev, hccr, hcor);
+}
+
+static int dwc3_generic_host_remove(struct udevice *dev)
+{
+ struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
+ int rc;
+
+ rc = xhci_deregister(dev);
+ if (rc)
+ return rc;
+
+ return dwc3_generic_remove(dev, >gen_priv);
+}
+
+U_BOOT_DRIVER(dwc3_generic_host) = {
+ .name = "dwc3-generic-host",
+ .id = UCLASS_USB,
+ .ofdata_to_platdata = dwc3_generic_ofdata_to_platdata,
+ .probe = dwc3_generic_host_probe,
+ .remove = dwc3_generic_host_remove,
+ .priv_auto_alloc_size = sizeof(struct dwc3_generic_host_priv),
+ .platdata_auto_alloc_size = sizeof(struct dwc3_generic_plat),
+ .ops = _usb_ops,
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif
+
struct dwc3_glue_data {
struct clk_bulk clks;
struct reset_ctl_bulk resets;
@@ -252,10 +302,12 @@ static int dwc3_glue_bind(struct udevice *parent)
driver = "dwc3-generic-peripheral";
#endif
break;
+#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
case USB_DR_MODE_HOST:
debug("%s: dr_mode: HOST\n", __func__);
- driver = "xhci-dwc3";
+ driver = "dwc3-generic-host";
break;
+#endif
default:
debug("%s: unsupported dr_mode\n", __func__);
return -ENODEV;
--
2.17.1
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[U-Boot] [PATCH v2 02/18] usb: host: remove the xhci-zynqmp driver
This driver is not used anymore. Signed-off-by: Jean-Jacques Hiblot --- Changes in v2: None configs/avnet_ultra96_rev1_defconfig | 1 - .../xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - .../xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 - .../xilinx_zynqmp_zc1751_xm017_dc3_defconfig | 1 - configs/xilinx_zynqmp_zcu100_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 - drivers/usb/host/Kconfig | 7 - drivers/usb/host/Makefile | 1 - drivers/usb/host/xhci-zynqmp.c| 146 -- 15 files changed, 166 deletions(-) delete mode 100644 drivers/usb/host/xhci-zynqmp.c diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig index b504332ff0..fcfebe9c78 100644 --- a/configs/avnet_ultra96_rev1_defconfig +++ b/configs/avnet_ultra96_rev1_defconfig @@ -75,7 +75,6 @@ CONFIG_ZYNQ_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index 7b1f5e9d0a..8d906fa364 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -86,7 +86,6 @@ CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index ae2554a8eb..198b92a18d 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -77,7 +77,6 @@ CONFIG_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig index 559a61e8d0..0d93f3ceb1 100644 --- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig @@ -74,7 +74,6 @@ CONFIG_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig index 4b3f72da74..3b0f81adf9 100644 --- a/configs/xilinx_zynqmp_zcu100_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig @@ -74,7 +74,6 @@ CONFIG_ZYNQ_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index ef291a7d38..7f10554594 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -101,7 +101,6 @@ CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index 975e9f5eb1..49f46dca09 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -100,7 +100,6 @@ CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 34918aa171..46ac6a3add 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -100,7 +100,6 @@ CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig index e4090dc281..1672a684ac 100644 --- a/configs/xilinx_zynqmp_zcu104_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig @@ -85,7 +85,6 @@ CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y
[U-Boot] [PATCH v2 06/18] usb: xhci: move xhci.h to include usb
The xhci.h header file is currently located under drivers/usb/xhci
Move it to the include/usb folder to make it available to drivers that
are not under drivers/usb/xhci
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2: None
MAINTAINERS | 1 +
drivers/usb/host/xhci-dwc3.c | 2 +-
drivers/usb/host/xhci-exynos5.c | 2 +-
drivers/usb/host/xhci-fsl.c | 2 +-
drivers/usb/host/xhci-mem.c | 2 +-
drivers/usb/host/xhci-mvebu.c| 2 +-
drivers/usb/host/xhci-omap.c | 2 +-
drivers/usb/host/xhci-pci.c | 2 +-
drivers/usb/host/xhci-rcar.c | 2 +-
drivers/usb/host/xhci-ring.c | 2 +-
drivers/usb/host/xhci-rockchip.c | 2 +-
drivers/usb/host/xhci.c | 2 +-
drivers/usb/phy/omap_usb_phy.c | 2 +-
{drivers/usb/host => include/usb}/xhci.h | 0
14 files changed, 13 insertions(+), 12 deletions(-)
rename {drivers/usb/host => include/usb}/xhci.h (100%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 33fd4652a4..e9a07bba6d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -781,6 +781,7 @@ M: Bin Meng
S: Maintained
T: git git://git.denx.de/u-boot-usb.git topic-xhci
F: drivers/usb/host/xhci*
+F: include/usb/xhci.h
VIDEO
M: Anatolij Gustschin
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index 83b9f119e7..051c4c12e7 100644
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -14,7 +14,7 @@
#include
#include
-#include "xhci.h"
+#include
#include
#include
#include
diff --git a/drivers/usb/host/xhci-exynos5.c b/drivers/usb/host/xhci-exynos5.c
index c150f520bd..25c30c24f0 100644
--- a/drivers/usb/host/xhci-exynos5.c
+++ b/drivers/usb/host/xhci-exynos5.c
@@ -27,7 +27,7 @@
#include
#include
-#include "xhci.h"
+#include
/* Declare global data pointer */
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index c0b98a8ec7..9e0c1b76e4 100644
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -13,7 +13,7 @@
#include
#include
#include
-#include "xhci.h"
+#include
#include
#include
#include
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 84c2c3344a..530e979bb7 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -21,7 +21,7 @@
#include
#include
-#include "xhci.h"
+#include
#define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
/**
diff --git a/drivers/usb/host/xhci-mvebu.c b/drivers/usb/host/xhci-mvebu.c
index b6c6aaf78e..2b871046ae 100644
--- a/drivers/usb/host/xhci-mvebu.c
+++ b/drivers/usb/host/xhci-mvebu.c
@@ -12,7 +12,7 @@
#include
#include
-#include "xhci.h"
+#include
struct mvebu_xhci_platdata {
fdt_addr_t hcd_base;
diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c
index db007af37f..25b195f7d1 100644
--- a/drivers/usb/host/xhci-omap.c
+++ b/drivers/usb/host/xhci-omap.c
@@ -19,7 +19,7 @@
#include
#include
-#include "xhci.h"
+#include
/* Declare global data pointer */
static struct omap_xhci omap;
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index b995aef997..c1f60da541 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -9,7 +9,7 @@
#include
#include
#include
-#include "xhci.h"
+#include
static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,
struct xhci_hcor **ret_hcor)
diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c
index f2e91ef0fe..c4d8811343 100644
--- a/drivers/usb/host/xhci-rcar.c
+++ b/drivers/usb/host/xhci-rcar.c
@@ -12,7 +12,7 @@
#include
#include
-#include "xhci.h"
+#include
#include "xhci-rcar-r8a779x_usb3_v3.h"
/* Register Offset */
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index b2cfd948f8..119b418487 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -19,7 +19,7 @@
#include
#include
-#include "xhci.h"
+#include
/**
* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
diff --git a/drivers/usb/host/xhci-rockchip.c b/drivers/usb/host/xhci-rockchip.c
index f19bea3a91..4f221a60f2 100644
--- a/drivers/usb/host/xhci-rockchip.c
+++ b/drivers/usb/host/xhci-rockchip.c
@@ -13,7 +13,7 @@
#include
#include
-#include "xhci.h"
+#include
struct rockchip_xhci_platdata {
fdt_addr_t hcd_base;
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 44c5f2d264..848721a49d 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -28,7 +28,7 @@
#include
#include
#include
-#include "xhci.h"
+#include
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
index 32e5bbb8d8..897e6f19f7 100644
[U-Boot] [PATCH v2 16/18] phy: keystone-usb: handle the transition of the USB power domain
There is no proper power domain support for the keystone platforms.
However we need to turn off the USB domains before jumping to linux or it
fail to boot (observed with k2e and k2l platforms).
This can be done in the PHY driver as it is dedicated only to the keystone
platforms and matches the required on/off sequence.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2: None
drivers/phy/keystone-usb-phy.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/phy/keystone-usb-phy.c b/drivers/phy/keystone-usb-phy.c
index e8146cabfa..14ac62 100644
--- a/drivers/phy/keystone-usb-phy.c
+++ b/drivers/phy/keystone-usb-phy.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
/* USB PHY control register offsets */
#define USB_PHY_CTL_UTMI 0x
@@ -22,15 +23,25 @@
#define PHY_REF_SSP_EN BIT(29)
struct keystone_usb_phy {
+ u32 psc_domain;
void __iomem *reg;
};
static int keystone_usb_init(struct phy *phy)
{
u32 val;
+ int rc;
struct udevice *dev = phy->dev;
struct keystone_usb_phy *keystone = dev_get_priv(dev);
+ /* Release USB from reset */
+ rc = psc_enable_module(keystone->psc_domain);
+ if (rc) {
+ debug("Cannot enable USB module");
+ return -rc;
+ }
+ mdelay(10);
+
/*
* VBUSVLDEXTSEL has a default value of 1 in BootCfg but shouldn't.
* It should always be cleared because our USB PHY has an onchip VBUS
@@ -72,13 +83,24 @@ static int keystone_usb_power_off(struct phy *phy)
static int keystone_usb_exit(struct phy *phy)
{
+ struct udevice *dev = phy->dev;
+ struct keystone_usb_phy *keystone = dev_get_priv(dev);
+
+ if (psc_disable_module(keystone->psc_domain))
+ debug("failed to disable USB module!\n");
+
return 0;
}
static int keystone_usb_phy_probe(struct udevice *dev)
{
+ int rc;
struct keystone_usb_phy *keystone = dev_get_priv(dev);
+ rc = dev_read_u32(dev, "psc-domain", >psc_domain);
+ if (rc)
+ return rc;
+
keystone->reg = dev_remap_addr_index(dev, 0);
if (!keystone->reg) {
pr_err("unable to remap usb phy\n");
--
2.17.1
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[U-Boot] [PATCH v2 15/18] ARM: keystone: Do not enable the USB power domains at the board level
This breaks linux boot sequence.
Observed on k2e and k2l platforms.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2: None
board/ti/ks2_evm/board.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index eed62e9cac..c1ebce42b6 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -66,20 +66,7 @@ struct image_header *spl_get_load_buffer(ssize_t offset,
size_t size)
int board_init(void)
{
-#if CONFIG_IS_ENABLED(DM_USB)
- int rc = psc_enable_module(KS2_LPSC_USB);
-
- if (rc)
- puts("Cannot enable USB0 module");
-#ifdef KS2_LPSC_USB_1
- rc = psc_enable_module(KS2_LPSC_USB_1);
- if (rc)
- puts("Cannot enable USB1 module");
-#endif
-#endif
-
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
return 0;
}
--
2.17.1
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[U-Boot] [PATCH v2 09/18] usb: dwc3-generic: factorize code
Factor code for re-usability.
This is another step toward adding host support.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2: None
drivers/usb/dwc3/dwc3-generic.c | 55 +
1 file changed, 35 insertions(+), 20 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index f29b93d191..d5c71d024f 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -28,27 +28,17 @@ struct dwc3_generic_plat {
enum usb_dr_mode dr_mode;
};
-#if CONFIG_IS_ENABLED(DM_USB_GADGET)
struct dwc3_generic_priv {
+ void *base;
struct dwc3 dwc3;
struct phy *phys;
int num_phys;
};
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
-{
- struct dwc3_generic_priv *priv = dev_get_priv(dev);
- struct dwc3 *dwc3 = >dwc3;
-
- dwc3_gadget_uboot_handle_interrupt(dwc3);
-
- return 0;
-}
-
-static int dwc3_generic_peripheral_probe(struct udevice *dev)
+static int dwc3_generic_probe(struct udevice *dev,
+ struct dwc3_generic_priv *priv)
{
int rc;
- struct dwc3_generic_priv *priv = dev_get_priv(dev);
struct dwc3_generic_plat *plat = dev_get_platdata(dev);
struct dwc3 *dwc3 = >dwc3;
@@ -59,22 +49,22 @@ static int dwc3_generic_peripheral_probe(struct udevice
*dev)
if (rc)
return rc;
- dwc3->regs = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
- dwc3->regs += DWC3_GLOBALS_REGS_START;
+ priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
+ dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
dwc3->dev = dev;
rc = dwc3_init(dwc3);
if (rc) {
- unmap_physmem(dwc3->regs, MAP_NOCACHE);
+ unmap_physmem(priv->base, MAP_NOCACHE);
return rc;
}
return 0;
}
-static int dwc3_generic_peripheral_remove(struct udevice *dev)
+static int dwc3_generic_remove(struct udevice *dev,
+ struct dwc3_generic_priv *priv)
{
- struct dwc3_generic_priv *priv = dev_get_priv(dev);
struct dwc3 *dwc3 = >dwc3;
dwc3_remove(dwc3);
@@ -84,7 +74,7 @@ static int dwc3_generic_peripheral_remove(struct udevice *dev)
return 0;
}
-static int dwc3_generic_peripheral_ofdata_to_platdata(struct udevice *dev)
+static int dwc3_generic_ofdata_to_platdata(struct udevice *dev)
{
struct dwc3_generic_plat *plat = dev_get_platdata(dev);
int node = dev_of_offset(dev);
@@ -106,10 +96,35 @@ static int
dwc3_generic_peripheral_ofdata_to_platdata(struct udevice *dev)
return 0;
}
+#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
+{
+ struct dwc3_generic_priv *priv = dev_get_priv(dev);
+ struct dwc3 *dwc3 = >dwc3;
+
+ dwc3_gadget_uboot_handle_interrupt(dwc3);
+
+ return 0;
+}
+
+static int dwc3_generic_peripheral_probe(struct udevice *dev)
+{
+ struct dwc3_generic_priv *priv = dev_get_priv(dev);
+
+ return dwc3_generic_probe(dev, priv);
+}
+
+static int dwc3_generic_peripheral_remove(struct udevice *dev)
+{
+ struct dwc3_generic_priv *priv = dev_get_priv(dev);
+
+ return dwc3_generic_remove(dev, priv);
+}
+
U_BOOT_DRIVER(dwc3_generic_peripheral) = {
.name = "dwc3-generic-peripheral",
.id = UCLASS_USB_GADGET_GENERIC,
- .ofdata_to_platdata = dwc3_generic_peripheral_ofdata_to_platdata,
+ .ofdata_to_platdata = dwc3_generic_ofdata_to_platdata,
.probe = dwc3_generic_peripheral_probe,
.remove = dwc3_generic_peripheral_remove,
.priv_auto_alloc_size = sizeof(struct dwc3_generic_priv),
--
2.17.1
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[U-Boot] [PATCH v2 08/18] usb: dwc3-generic: use platdata
Separate platform data from the private data.
This is one step toward adding host support.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2: None
drivers/usb/dwc3/dwc3-generic.c | 37 -
1 file changed, 23 insertions(+), 14 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 406bf0b362..f29b93d191 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -22,17 +22,22 @@
#include
#include
+struct dwc3_generic_plat {
+ fdt_addr_t base;
+ u32 maximum_speed;
+ enum usb_dr_mode dr_mode;
+};
+
#if CONFIG_IS_ENABLED(DM_USB_GADGET)
-struct dwc3_generic_peripheral {
+struct dwc3_generic_priv {
struct dwc3 dwc3;
struct phy *phys;
int num_phys;
- fdt_addr_t base;
};
int dm_usb_gadget_handle_interrupts(struct udevice *dev)
{
- struct dwc3_generic_peripheral *priv = dev_get_priv(dev);
+ struct dwc3_generic_priv *priv = dev_get_priv(dev);
struct dwc3 *dwc3 = >dwc3;
dwc3_gadget_uboot_handle_interrupt(dwc3);
@@ -43,14 +48,18 @@ int dm_usb_gadget_handle_interrupts(struct udevice *dev)
static int dwc3_generic_peripheral_probe(struct udevice *dev)
{
int rc;
- struct dwc3_generic_peripheral *priv = dev_get_priv(dev);
+ struct dwc3_generic_priv *priv = dev_get_priv(dev);
+ struct dwc3_generic_plat *plat = dev_get_platdata(dev);
struct dwc3 *dwc3 = >dwc3;
+ dwc3->maximum_speed = plat->maximum_speed;
+ dwc3->dr_mode = plat->dr_mode;
+
rc = dwc3_setup_phy(dev, >phys, >num_phys);
if (rc)
return rc;
- dwc3->regs = map_physmem(priv->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
+ dwc3->regs = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
dwc3->regs += DWC3_GLOBALS_REGS_START;
dwc3->dev = dev;
@@ -65,7 +74,7 @@ static int dwc3_generic_peripheral_probe(struct udevice *dev)
static int dwc3_generic_peripheral_remove(struct udevice *dev)
{
- struct dwc3_generic_peripheral *priv = dev_get_priv(dev);
+ struct dwc3_generic_priv *priv = dev_get_priv(dev);
struct dwc3 *dwc3 = >dwc3;
dwc3_remove(dwc3);
@@ -77,20 +86,19 @@ static int dwc3_generic_peripheral_remove(struct udevice
*dev)
static int dwc3_generic_peripheral_ofdata_to_platdata(struct udevice *dev)
{
- struct dwc3_generic_peripheral *priv = dev_get_priv(dev);
- struct dwc3 *dwc3 = >dwc3;
+ struct dwc3_generic_plat *plat = dev_get_platdata(dev);
int node = dev_of_offset(dev);
- priv->base = devfdt_get_addr(dev);
+ plat->base = devfdt_get_addr(dev);
- dwc3->maximum_speed = usb_get_maximum_speed(node);
- if (dwc3->maximum_speed == USB_SPEED_UNKNOWN) {
+ plat->maximum_speed = usb_get_maximum_speed(node);
+ if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
pr_err("Invalid usb maximum speed\n");
return -ENODEV;
}
- dwc3->dr_mode = usb_get_dr_mode(node);
- if (dwc3->dr_mode == USB_DR_MODE_UNKNOWN) {
+ plat->dr_mode = usb_get_dr_mode(node);
+ if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
pr_err("Invalid usb mode setup\n");
return -ENODEV;
}
@@ -104,7 +112,8 @@ U_BOOT_DRIVER(dwc3_generic_peripheral) = {
.ofdata_to_platdata = dwc3_generic_peripheral_ofdata_to_platdata,
.probe = dwc3_generic_peripheral_probe,
.remove = dwc3_generic_peripheral_remove,
- .priv_auto_alloc_size = sizeof(struct dwc3_generic_peripheral),
+ .priv_auto_alloc_size = sizeof(struct dwc3_generic_priv),
+ .platdata_auto_alloc_size = sizeof(struct dwc3_generic_plat),
};
#endif
--
2.17.1
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[U-Boot] [PATCH v2 12/18] usb: dwc3: Add dwc3_of_parse() to get quirks information from DT
Add a new function that read quirk and configuration information from the
DT. The goal is to allow platforms using their own version of DWC3 driver
to migrate to the generic DWC3 driver.
The function is adapted from the function dwc3_get_properties() in the
linux dwc3 driver introduced in commit c5ac6116db35d.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2:
- Update commit log
drivers/usb/dwc3/core.c | 65 +
drivers/usb/dwc3/core.h | 1 +
drivers/usb/dwc3/dwc3-generic.c | 6 ++-
3 files changed, 71 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 653c874fa6..1baad39796 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -888,6 +888,71 @@ int dwc3_shutdown_phy(struct udevice *dev, struct phy
*usb_phys, int num_phys)
#endif
#if CONFIG_IS_ENABLED(DM_USB)
+void dwc3_of_parse(struct dwc3 *dwc)
+{
+ const u8 *tmp;
+ struct udevice *dev = dwc->dev;
+ u8 lpm_nyet_threshold;
+ u8 tx_de_emphasis;
+ u8 hird_threshold;
+
+ /* default to highest possible threshold */
+ lpm_nyet_threshold = 0xff;
+
+ /* default to -3.5dB de-emphasis */
+ tx_de_emphasis = 1;
+
+ /*
+* default to assert utmi_sleep_n and use maximum allowed HIRD
+* threshold value of 0b1100
+*/
+ hird_threshold = 12;
+
+ dwc->has_lpm_erratum = dev_read_bool(dev,
+ "snps,has-lpm-erratum");
+ tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
+ if (tmp)
+ lpm_nyet_threshold = *tmp;
+
+ dwc->is_utmi_l1_suspend = dev_read_bool(dev,
+ "snps,is-utmi-l1-suspend");
+ tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1);
+ if (tmp)
+ hird_threshold = *tmp;
+
+ dwc->disable_scramble_quirk = dev_read_bool(dev,
+ "snps,disable_scramble_quirk");
+ dwc->u2exit_lfps_quirk = dev_read_bool(dev,
+ "snps,u2exit_lfps_quirk");
+ dwc->u2ss_inp3_quirk = dev_read_bool(dev,
+ "snps,u2ss_inp3_quirk");
+ dwc->req_p1p2p3_quirk = dev_read_bool(dev,
+ "snps,req_p1p2p3_quirk");
+ dwc->del_p1p2p3_quirk = dev_read_bool(dev,
+ "snps,del_p1p2p3_quirk");
+ dwc->del_phy_power_chg_quirk = dev_read_bool(dev,
+ "snps,del_phy_power_chg_quirk");
+ dwc->lfps_filter_quirk = dev_read_bool(dev,
+ "snps,lfps_filter_quirk");
+ dwc->rx_detect_poll_quirk = dev_read_bool(dev,
+ "snps,rx_detect_poll_quirk");
+ dwc->dis_u3_susphy_quirk = dev_read_bool(dev,
+ "snps,dis_u3_susphy_quirk");
+ dwc->dis_u2_susphy_quirk = dev_read_bool(dev,
+ "snps,dis_u2_susphy_quirk");
+ dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
+ "snps,tx_de_emphasis_quirk");
+ tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
+ if (tmp)
+ tx_de_emphasis = *tmp;
+
+ dwc->lpm_nyet_threshold = lpm_nyet_threshold;
+ dwc->tx_de_emphasis = tx_de_emphasis;
+
+ dwc->hird_threshold = hird_threshold
+ | (dwc->is_utmi_l1_suspend << 4);
+}
+
int dwc3_init(struct dwc3 *dwc)
{
int ret;
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 4c89dfcad9..be9672266a 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -991,6 +991,7 @@ struct dwc3_gadget_ep_cmd_params {
/* prototypes */
int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
+void dwc3_of_parse(struct dwc3 *dwc);
int dwc3_init(struct dwc3 *dwc);
void dwc3_remove(struct dwc3 *dwc);
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 3d008496f3..158d726623 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -48,8 +48,12 @@ static int dwc3_generic_probe(struct udevice *dev,
struct dwc3_generic_plat *plat = dev_get_platdata(dev);
struct dwc3 *dwc3 = >dwc3;
+ dwc3->dev = dev;
dwc3->maximum_speed = plat->maximum_speed;
dwc3->dr_mode = plat->dr_mode;
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ dwc3_of_parse(dwc3);
+#endif
rc = dwc3_setup_phy(dev, >phys, >num_phys);
if (rc)
@@ -57,7 +61,7 @@ static int dwc3_generic_probe(struct udevice *dev,
priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
- dwc3->dev = dev;
+
rc = dwc3_init(dwc3);
if (rc) {
--
2.17.1
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[U-Boot] [PATCH v2 04/18] usb: dwc3: Use UCLASS_NOP instead of UCLASS_MISC for the DWC3 generic glue
dwc3-generic has been broken since MISC uclass has been modified to scan DT
sub-nodes after bind.
Fixing it by a using the no-op uclass.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2: None
drivers/usb/dwc3/dwc3-generic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 70431facb3..406bf0b362 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -350,7 +350,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
U_BOOT_DRIVER(dwc3_generic_wrapper) = {
.name = "dwc3-generic-wrapper",
- .id = UCLASS_MISC,
+ .id = UCLASS_NOP,
.of_match = dwc3_glue_ids,
.bind = dwc3_glue_bind,
.probe = dwc3_glue_probe,
--
2.17.1
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[U-Boot] [PATCH v2 05/18] usb: dwc3: switch to peripheral mode when exiting
This allow the phy to enter idle and then suspend.
the K2 platforms require the PHY to be suspended before the USB domain
clock can be turned off.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2: None
drivers/usb/dwc3/core.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 56e2a046bf..ae01490306 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -581,6 +581,12 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
return 0;
}
+static void dwc3_gadget_run(struct dwc3 *dwc)
+{
+ dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
+ mdelay(100);
+}
+
static void dwc3_core_exit_mode(struct dwc3 *dwc)
{
switch (dwc->dr_mode) {
@@ -598,6 +604,13 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc)
/* do nothing */
break;
}
+
+ /*
+* switch back to peripheral mode
+* This enables the phy to enter idle and then, if enabled, suspend.
+*/
+ dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
+ dwc3_gadget_run(dwc);
}
#define DWC3_ALIGN_MASK(16 - 1)
--
2.17.1
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[U-Boot] [PATCH v2 07/18] usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit
No one is actually implementing those functions.
We could remove calls to these altogether, but it does not really hurt to
keep the empty inlined version at the moment and it satisfies a symmetry
with the gadget mode.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2: None
drivers/usb/dwc3/core.h | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index cfe29884e7..4c89dfcad9 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -994,15 +994,10 @@ int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
int dwc3_init(struct dwc3 *dwc);
void dwc3_remove(struct dwc3 *dwc);
-#ifdef CONFIG_USB_DWC3_HOST
-int dwc3_host_init(struct dwc3 *dwc);
-void dwc3_host_exit(struct dwc3 *dwc);
-#else
static inline int dwc3_host_init(struct dwc3 *dwc)
{ return 0; }
static inline void dwc3_host_exit(struct dwc3 *dwc)
{ }
-#endif
#ifdef CONFIG_USB_DWC3_GADGET
int dwc3_gadget_init(struct dwc3 *dwc);
--
2.17.1
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[U-Boot] [PATCH v2 03/18] dm: Add a No-op uclass
This uclass is intended for devices that do not need any features from the
uclass, including binding children.
This will typically be used by devices that are used to bind child devices
but do not use dm_scan_fdt_dev() to do it. That is for example the case of
several USB wrappers that have 2 child devices (1 for device and 1 for
host) but bind only one at a any given time.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2:
Add a test for the NOP uclass
arch/sandbox/dts/test.dts | 12 +++
drivers/core/uclass.c | 5 +++
include/dm/uclass-id.h| 1 +
test/dm/Makefile | 1 +
test/dm/nop.c | 73 +++
5 files changed, 92 insertions(+)
create mode 100644 test/dm/nop.c
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 8b2d6451c6..c328258901 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -400,6 +400,18 @@
sandbox,silent; /* Don't emit sounds while testing */
};
+ nop-test_0 {
+ compatible = "sandbox,nop_sandbox1";
+ nop-test_1 {
+ compatible = "sandbox,nop_sandbox2";
+ bind = "True";
+ };
+ nop-test_2 {
+ compatible = "sandbox,nop_sandbox2";
+ bind = "False";
+ };
+ };
+
misc-test {
compatible = "sandbox,misc_sandbox";
};
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index fc3157de39..dc9eb62893 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -757,3 +757,8 @@ int uclass_pre_remove_device(struct udevice *dev)
return 0;
}
#endif
+
+UCLASS_DRIVER(nop) = {
+ .id = UCLASS_NOP,
+ .name = "nop",
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 09e0ad5391..418392875c 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -62,6 +62,7 @@ enum uclass_id {
UCLASS_MMC, /* SD / MMC card or chip */
UCLASS_MOD_EXP, /* RSA Mod Exp device */
UCLASS_MTD, /* Memory Technology Device (MTD) device */
+ UCLASS_NOP, /* No-op devices */
UCLASS_NORTHBRIDGE, /* Intel Northbridge / SDRAM controller */
UCLASS_NVME,/* NVM Express device */
UCLASS_PANEL, /* Display panel, such as an LCD */
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 49857c5092..aeb3aa0ca7 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -3,6 +3,7 @@
# Copyright (c) 2013 Google, Inc
obj-$(CONFIG_UT_DM) += bus.o
+obj-$(CONFIG_UT_DM) += nop.o
obj-$(CONFIG_UT_DM) += test-driver.o
obj-$(CONFIG_UT_DM) += test-fdt.o
obj-$(CONFIG_UT_DM) += test-main.o
diff --git a/test/dm/nop.c b/test/dm/nop.c
new file mode 100644
index 00..2df29f3d15
--- /dev/null
+++ b/test/dm/nop.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test for the NOP uclass
+ *
+ * (C) Copyright 2019 - Texas Instruments Incorporated - http://www.ti.com/
+ * Jean-Jacques Hiblot
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static int noptest_bind(struct udevice *parent)
+{
+ ofnode ofnode = dev_read_first_subnode(parent);
+
+ while (ofnode_valid(ofnode)) {
+ struct udevice *dev;
+ const char *bind_flag = ofnode_read_string(ofnode, "bind");
+
+ if (bind_flag && (strcmp(bind_flag, "True") == 0))
+ lists_bind_fdt(parent, ofnode, , false);
+ ofnode = dev_read_next_subnode(ofnode);
+ }
+
+ return 0;
+}
+
+static const struct udevice_id noptest1_ids[] = {
+ {
+ .compatible = "sandbox,nop_sandbox1",
+ },
+ { }
+};
+
+U_BOOT_DRIVER(noptest_drv1) = {
+ .name = "noptest1_drv",
+ .of_match = noptest1_ids,
+ .id = UCLASS_NOP,
+ .bind = noptest_bind,
+};
+
+static const struct udevice_id noptest2_ids[] = {
+ {
+ .compatible = "sandbox,nop_sandbox2",
+ },
+ { }
+};
+
+U_BOOT_DRIVER(noptest_drv2) = {
+ .name = "noptest2_drv",
+ .of_match = noptest2_ids,
+ .id = UCLASS_NOP,
+};
+
+static int dm_test_nop(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_NOP, "nop-test_0", ));
+ ut_assertok(uclass_get_device_by_name(UCLASS_NOP, "nop-test_1", ));
+ ut_asserteq(-ENODEV,
+ uclass_get_device_by_name(UCLASS_NOP, "nop-test_2", ));
+
+ return 0;
+}
+
+DM_TEST(dm_test_nop, DM_TESTF_FLAT_TREE | DM_TESTF_SCAN_FDT);
--
2.17.1
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[U-Boot] [PATCH v2 01/18] usb: dwc3-generic: remove dm_scan_fdt_dev() from the remove() callback
There is simply no reason to do that here.
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2: None
drivers/usb/dwc3/dwc3-generic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 3e6c494dc6..70431facb3 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -337,7 +337,7 @@ static int dwc3_glue_remove(struct udevice *dev)
clk_release_bulk(>clks);
- return dm_scan_fdt_dev(dev);
+ return 0;
}
static const struct udevice_id dwc3_glue_ids[] = {
--
2.17.1
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Re: [U-Boot] [PATCH v2] include: android_bl_msg.h: Initial import
Hi Akashi,
On Mon, May 13, 2019 at 3:09 AM AKASHI Takahiro
wrote:
>
> On Fri, May 10, 2019 at 04:12:10PM +0300, Sam Protsenko wrote:
> > From: Eugeniu Rosca
> >
> > Import the bootloader_message.h (former bootloader.h) from AOSP.
> >
> > The bootloader_message.h basically defines the flash layout of a
> > dedicated partition (usually called 'misc') and is needed in U-Boot
> > in order to be able to implement a subset of Android Bootloader
> > Requirements [1], specifically dealing with:
> > - Communication between the bootloader and recovery
> > - Handling of A/B (Seamless) System Updates [2]
> > - Passing the reboot reason [3]
> >
> > With respect to the in-tree vs out-of-tree file differences:
> > - license matches https://patchwork.ozlabs.org/patch/1003998/
> > - filename is changed to android_bl_msg.h, as per Simon's comment [4]
> > - minimize the future integration/update efforts from the source.
> >Particularly, the __UBOOT__ macro helps with isolating the
> >U-Boot-unrelated parts (e.g. includes/function prototypes/etc)
> >
> > [1] https://source.android.com/devices/bootloader
> > [2] https://source.android.com/devices/tech/ota/ab/
> > [3] https://source.android.com/devices/bootloader/boot-reason
> > [4] https://patchwork.ozlabs.org/patch/1003998/#2046141
> >
> > Signed-off-by: Eugeniu Rosca
> > Signed-off-by: Sam Protsenko
> > ---
> > Changes in v2:
> > * Remove struct typedefs, as it breaks Linux kernel style outside of
> >this file, it bloats namespace (old struct names still remain in the
> >namespace) and increases the delta w.r.t. AOSP file version
> > * Add specific AOSP commit-id where this file was imported from
> >(as per Tom's comment)
> > * Update this file to the most recent version from AOSP
> >
> > include/android_bl_msg.h | 264 +++
> > 1 file changed, 264 insertions(+)
> > create mode 100644 include/android_bl_msg.h
> >
> > diff --git a/include/android_bl_msg.h b/include/android_bl_msg.h
> > new file mode 100644
> > index 00..7bb69ef431
> > --- /dev/null
> > +++ b/include/android_bl_msg.h
> > @@ -0,0 +1,264 @@
> > +// SPDX-License-Identifier: BSD-2-Clause
> > +/*
> > + * This file was taken from the AOSP Project.
> > + * Repository: https://android.googlesource.com/platform/bootable/recovery/
> > + * File: bootloader_message/include/bootloader_message/bootloader_message.h
> > + * Commit: 9423d2f6b7ef ("Merge "Track libziparchive API change."")
> > + *
> > + * Please keep this file with minimal changes with respect to AOSP version!
> > + *
> > + * Copyright (C) 2008 The Android Open Source Project
> > + *
> > + * Licensed under the Apache License, Version 2.0 (the "License");
>
> Which license, BSD-2 (in SPDX) or Apache v2, is applied to this file?
> If the latter, it is said incompatible with GPLv2, isn't it?
>
This file was also published by Google under BSD-2 in AOSP
external/u-boot [1]. But it differs somehow from the file in this
patch.
Tom, should we use this file from [1] to be on the safe side of the
road? Or it's ok to take it directly from [2], as it's done here?
Thanks!
[1]
https://android.googlesource.com/platform/external/u-boot/+/c7f85c5f75f95dbbd3cedcc3a399eee6dbb59cdc
[2]
https://android.googlesource.com/platform/bootable/recovery/+/refs/heads/master/bootloader_message/include/bootloader_message/bootloader_message.h
> -Takahiro Akashi
>
> > + * you may not use this file except in compliance with the License.
> > + * You may obtain a copy of the License at
> > + *
> > + * http://www.apache.org/licenses/LICENSE-2.0
> > + *
> > + * Unless required by applicable law or agreed to in writing, software
> > + * distributed under the License is distributed on an "AS IS" BASIS,
> > + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
> > + * See the License for the specific language governing permissions and
> > + * limitations under the License.
> > + */
> > +
> > +#ifndef _BOOTLOADER_MESSAGE_H
> > +#define _BOOTLOADER_MESSAGE_H
> > +
> > +#ifndef __UBOOT__
> > +#include
> > +#include
> > +#include
> > +#else
> > +#include
> > +#endif
> > +
> > +// Spaces used by misc partition are as below:
> > +// 0 - 2K For bootloader_message
> > +// 2K - 16KUsed by Vendor's bootloader (the 2K - 4K range may be
> > optionally used
> > +// as bootloader_message_ab struct)
> > +// 16K - 64KUsed by uncrypt and recovery to store wipe_package for A/B
> > devices
> > +// Note that these offsets are admitted by bootloader,recovery and
> > uncrypt, so they
> > +// are not configurable without changing all of them.
> > +static const size_t BOOTLOADER_MESSAGE_OFFSET_IN_MISC = 0;
> > +static const size_t WIPE_PACKAGE_OFFSET_IN_MISC = 16 * 1024;
> > +
> > +/* Bootloader Message (2-KiB)
> > + *
> > + * This structure describes the content of a block in flash
> > + * that is used for recovery and the bootloader to talk to
> > + * each other.
> > + *
> > +
[U-Boot] [PATCH v1] armv8: lx2160: Drop useless CONFIG_CMDLINE_EDITING from config.h
The commit
58c3e62040be ("armv8: lx2160ardb : Add support for LX2160ARDB platform")
brought a new boards support with redundancy in the config.h file.
One of them is CONFIG_CMDLINE_EDITING which is removed by this change.
Cc: Priyanka Jain
Cc: Peng Ma
Cc: Prabhakar Kushwaha
Signed-off-by: Andy Shevchenko
---
include/configs/lx2160a_common.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 637619cb55..eb0b1766aa 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -187,7 +187,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE /* Boot args buffer */
-#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_SYS_MAXARGS 64 /* max command args */
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
--
2.20.1
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[U-Boot] [PATCH] board: mediatek: Add pumpkin board support
The pumpkin board is made by Gossamer Engineering and is using
a MediaTek SoC. The board currently comes in two available version:
MT8516 SoC and MT8167 SoC.
The board provides the following IOs: eMMC, NAND, SD card, USB type-A,
Ethernet, Wi-Fi, Bluetooth, Audio (jack out, 2 PDM port, 1 analog in),
serial over USB, and an expansion header.
Additionally there is a HDMI port, DSI port, and camera port only
on the MT8167 version of the board.
The board can be powered by battery and/or via a USB Type-C port and
is using a PMIC MT6392.
The eMMC and NAND are sharing pins and cannot be used together.
This commit is adding the basic boot support for the Pumpkin MT8516
board on the eMMC.
Signed-off-by: Fabien Parent
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/mt8516-pumpkin.dts| 110 +
arch/arm/mach-mediatek/Kconfig | 1 +
board/mediatek/pumpkin/Kconfig | 13
board/mediatek/pumpkin/MAINTAINERS | 6 ++
board/mediatek/pumpkin/Makefile| 3 +
board/mediatek/pumpkin/pumpkin.c | 14
configs/pumpkin_defconfig | 64 +
include/configs/pumpkin.h | 58 +++
9 files changed, 271 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/mt8516-pumpkin.dts
create mode 100644 board/mediatek/pumpkin/Kconfig
create mode 100644 board/mediatek/pumpkin/MAINTAINERS
create mode 100644 board/mediatek/pumpkin/Makefile
create mode 100644 board/mediatek/pumpkin/pumpkin.c
create mode 100644 configs/pumpkin_defconfig
create mode 100644 include/configs/pumpkin.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 83058c4452..7b48e5e142 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -752,7 +752,8 @@ dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb
k3-am654-r5-base-board.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623n-bananapi-bpi-r2.dtb \
- mt7629-rfb.dtb
+ mt7629-rfb.dtb \
+ mt8516-pumpkin.dtb
dtb-$(CONFIG_TARGET_GE_BX50V3) += imx6q-bx50v3.dtb
dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
diff --git a/arch/arm/dts/mt8516-pumpkin.dts b/arch/arm/dts/mt8516-pumpkin.dts
new file mode 100644
index 00..cd43c1f5e3
--- /dev/null
+++ b/arch/arm/dts/mt8516-pumpkin.dts
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2019 BayLibre SAS.
+ * Author: Fabien Parent
+ */
+
+/dts-v1/;
+
+#include
+#include "mt8516.dtsi"
+
+/ {
+ model = "Pumpkin MT8516";
+
+ chosen {
+ stdout-path =
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x4000 0x2000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /* 128 KiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon@4300 {
+ no-map;
+ reg = <0 0x4300 0 0x2>;
+ };
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins_default>;
+ bus-width = <4>;
+ max-frequency = <2>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ vmmc-supply = <_3p3v>;
+ vqmmc-supply = <_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+ {
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "msdc";
+ groups = "msdc0";
+ };
+
+ conf-cmd-data {
+ pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1",
+ "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4",
+ "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7";
+ input-enable;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "MSDC0_CLK";
+ bias-pull-down;
+ };
+
+ conf-rst {
+ pins = "MSDC0_RSTB";
+ bias-pull-up;
+ };
+ };
+
+ uart0_pins: uart0 {
+ mux {
+ function = "uart";
+ groups = "uart0_0_rxd_txd";
+ };
+ };
+};
+
+ {
Re: [U-Boot] [PATCH 09/12] sh: mpr2: Remove the board
On 5/13/19 2:31 PM, Jonas Mark (BT-FIR/ENG1) wrote: > Hi Marek, Hi, >> Betreff: [PATCH 09/12] sh: mpr2: Remove the board >> >> Last change to this board was done in 2016, has no prospects of ever being >> converted to DM, drop it. >> >> Signed-off-by: Marek Vasut >> Cc: Chris Brandt >> Cc: Mark Jonas >> Cc: Nobuhiro Iwamatsu >> Cc: Vladimir Zapolskiy >> Cc: Yoshihiro Shimoda >> --- >> arch/sh/Kconfig| 5 -- >> board/mpr2/Kconfig | 9 --- >> board/mpr2/MAINTAINERS | 6 -- >> board/mpr2/Makefile| 19 - >> board/mpr2/lowlevel_init.S | 117 --- >> board/mpr2/mpr2.c | 137 - >> configs/mpr2_defconfig | 31 - >> include/configs/mpr2.h | 55 --- >> 8 files changed, 379 deletions(-) >> delete mode 100644 board/mpr2/Kconfig >> delete mode 100644 board/mpr2/MAINTAINERS delete mode 100644 >> board/mpr2/Makefile delete mode 100644 board/mpr2/lowlevel_init.S >> delete mode 100644 board/mpr2/mpr2.c delete mode 100644 >> configs/mpr2_defconfig delete mode 100644 include/configs/mpr2.h > > Sad but true: U-Boot is not supported on this board anymore. Oh well, I'll try to keep at least SH4 alive :) > Acked-by: Mark Jonas Thanks! -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] imx8: cpu: fix warning for cpu_imx_get_temp
Hi Igor,
On 13.05.2019 12:46, Igor Opaniuk wrote:
> cpu_imx_get_temp() definition is wrapped with a ifdef macro,
> therefore all function references should be also wrapped the same way
> instead IS_ENABLED() usage.
>
> Fix warning:
> arch/arm/mach-imx/imx8/cpu.c: In function ‘cpu_imx_get_desc’:
> arch/arm/mach-imx/imx8/cpu.c:612:40: warning: implicit declaration of
> function ‘cpu_imx_get_temp’; did you mean ‘cpu_imx_get_desc’?
> [-Wimplicit-function-declaration]
>ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp());
> ^~~~
> cpu_imx_get_desc
> cpu_imx_get_desc
>
Using IS_ENABLED is typically preferred over ifdef since it assures that
the code is compileable even if CONFIG_IMX_SCU_THERMAL is not enabled.
I'd rather prefer we drop the the ifdef around cpu_imx_get_temp(). The
linker will remove the function in case CONFIG_IMX_SCU_THERMAL is not
enabled.
--
Stefan
> Fixes: 82467cb217 ("imx8: cpu: get temperature when print cpu desc")
> Signed-off-by: Igor Opaniuk
> ---
> arch/arm/mach-imx/imx8/cpu.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
> index 12596c6387..616baed7cc 100644
> --- a/arch/arm/mach-imx/imx8/cpu.c
> +++ b/arch/arm/mach-imx/imx8/cpu.c
> @@ -606,11 +606,11 @@ int cpu_imx_get_desc(struct udevice *dev, char
> *buf, int size)
> ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
> plat->type, plat->rev, plat->name, plat->freq_mhz);
>
> - if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
> - buf = buf + ret;
> - size = size - ret;
> - ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp());
> - }
> +#if defined(CONFIG_IMX_SCU_THERMAL)
> + buf = buf + ret;
> + size = size - ret;
> + ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp());
> +#endif
>
> snprintf(buf + ret, size - ret, "\n");
___
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[U-Boot] [PATCH v2 3/3] configs: update rk3288 veyron defconfigs
Updates jerry, mickey, minnie and speedy defconfigs to: - fit the SPL in 32k - boot from SPI (only) - remove gadget support (these have no OTG port) Reviewed-by: Simon Glass Signed-off-by: Urja Rannikko --- v2: Rebase, include previous reviewed-by --- configs/chromebit_mickey_defconfig | 25 - configs/chromebook_jerry_defconfig | 25 - configs/chromebook_minnie_defconfig | 25 - configs/chromebook_speedy_defconfig | 25 ++--- 4 files changed, 62 insertions(+), 38 deletions(-) diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 1b2cca8812..12dc690bca 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +# CONFIG_SPL_USE_ARCH_MEMCPY is not set CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x0010 CONFIG_SYS_MALLOC_F_LEN=0x2000 @@ -17,8 +18,12 @@ CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff704000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_CRC32_SUPPORT is not set +CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -39,16 +44,15 @@ CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_OF_PLATDATA=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y # CONFIG_SPL_SIMPLE_BUS is not set +# CONFIG_SPL_BLK is not set CONFIG_CLK=y CONFIG_SPL_CLK=y -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -58,13 +62,18 @@ CONFIG_CROS_EC_KEYB=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_PWRSEQ=y +# CONFIG_SPL_DM_MMC is not set CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=2 CONFIG_SF_DEFAULT_SPEED=2000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_PINCTRL=y +CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINMUX is not set +CONFIG_SPL_PINCONF=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_RK8XX=y @@ -78,17 +87,15 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_USB_DWC2=y CONFIG_ROCKCHIP_USB2_PHY=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Rockchip" -CONFIG_USB_GADGET_VENDOR_NUM=0x2207 -CONFIG_USB_GADGET_PRODUCT_NUM=0x320a -CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index f8c9c5fd9a..f25fd73cc6 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +# CONFIG_SPL_USE_ARCH_MEMCPY is not set CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x0010 CONFIG_SYS_MALLOC_F_LEN=0x2000 @@ -20,8 +21,12 @@ CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-jerry.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_TEXT_BASE=0xff704000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_CRC32_SUPPORT is not set +CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -43,16 +48,15 @@ CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_OF_PLATDATA=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y # CONFIG_SPL_SIMPLE_BUS is not set +# CONFIG_SPL_BLK is not set CONFIG_CLK=y CONFIG_SPL_CLK=y -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -62,13 +66,18 @@ CONFIG_CROS_EC_KEYB=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_PWRSEQ=y +# CONFIG_SPL_DM_MMC is not set CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=2 CONFIG_SF_DEFAULT_SPEED=2000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_PINCTRL=y +CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINMUX is not set
[U-Boot] [PATCH v2 2/3] configs: Move CONFIG_CMD_USB_MASS_STORAGE properly into Kconfig
This affects RK3036, RK322X and RK3288 - the defconfig changes done by moveconfig.py for the veyrons were left out on purpose because they dont have an OTG port, and will get their config updated in the next commit. Signed-off-by: Urja Rannikko --- v2: Also cleanup now unrelevant comments about usb support from the headers (series v2: rebased) --- configs/evb-rk3036_defconfig | 2 +- configs/evb-rk3229_defconfig | 1 + configs/evb-rk3288_defconfig | 2 +- configs/fennec-rk3288_defconfig | 2 +- configs/firefly-rk3288_defconfig | 2 +- configs/kylin-rk3036_defconfig| 2 +- configs/miqi-rk3288_defconfig | 2 +- configs/phycore-rk3288_defconfig | 2 +- configs/popmetal-rk3288_defconfig | 2 +- configs/rock2_defconfig | 2 +- configs/tinker-rk3288_defconfig | 2 +- include/configs/rk3036_common.h | 5 - include/configs/rk322x_common.h | 5 - include/configs/rk3288_common.h | 5 - include/configs/vyasa-rk3288.h| 1 - 15 files changed, 11 insertions(+), 26 deletions(-) diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 1e00c37438..d9158d28ad 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y @@ -56,7 +57,6 @@ CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 CONFIG_USB_GADGET_PRODUCT_NUM=0x310a CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_SPL_TINY_MEMSET=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index 9ee9daa3af..e800d09409 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -29,6 +29,7 @@ CONFIG_SPL_OPTEE=y CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds" CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 843c59d30d..e181ccef28 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y @@ -77,7 +78,6 @@ CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 CONFIG_USB_GADGET_PRODUCT_NUM=0x320a CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig index 6dfaff50ff..98aa936ea0 100644 --- a/configs/fennec-rk3288_defconfig +++ b/configs/fennec-rk3288_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y @@ -76,7 +77,6 @@ CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 CONFIG_USB_GADGET_PRODUCT_NUM=0x320a CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 4cedb28d22..1272244260 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y @@ -81,7 +82,6 @@ CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 CONFIG_USB_GADGET_PRODUCT_NUM=0x320a CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index 6822311ae6..4c175b0a8a 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y @@ -59,7 +60,6 @@ CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 CONFIG_USB_GADGET_PRODUCT_NUM=0x310a CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 936192f547..bf6d2d7f2a 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y
[U-Boot] [PATCH v2 1/3] configs: Move CONFIG_SPI_FLASH_GIGADEVICE properly into Kconfig
Affects rk3288 veyrons and rk3036, this was mostly done by moveconfig.py. Reviewed-by: Simon Glass Signed-off-by: Urja Rannikko -- v2: Rebase, include previous reviewed-by --- configs/chromebit_mickey_defconfig | 1 + configs/chromebook_jerry_defconfig | 1 + configs/chromebook_minnie_defconfig | 1 + configs/chromebook_speedy_defconfig | 1 + configs/evb-rk3036_defconfig| 1 + configs/kylin-rk3036_defconfig | 1 + include/configs/rk3036_common.h | 2 -- include/configs/veyron.h| 2 -- 8 files changed, 6 insertions(+), 4 deletions(-) diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 1a343093c8..1b2cca8812 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -62,6 +62,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=2000 +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 7c7986e6ae..f8c9c5fd9a 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -66,6 +66,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=2000 +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 17c1ea6453..4f6750dcb2 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -64,6 +64,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=2000 +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index 0cc1eb6a0b..f1e258e1fb 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -64,6 +64,7 @@ CONFIG_PWRSEQ=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SF_DEFAULT_SPEED=2000 +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 5e6bb54551..1e00c37438 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -45,6 +45,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=2000 +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_PINCTRL=y # CONFIG_SPL_DM_SERIAL is not set CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index f6a18748a9..6822311ae6 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -46,6 +46,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=2000 +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_PINCTRL=y CONFIG_DM_REGULATOR_FIXED=y # CONFIG_SPL_DM_SERIAL is not set diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index f5d09d18e5..bff20c842f 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -27,8 +27,6 @@ #define SDRAM_BANK_SIZE(512UL << 20UL) #define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE) -#define CONFIG_SPI_FLASH_GIGADEVICE - #ifndef CONFIG_SPL_BUILD /* usb otg */ diff --git a/include/configs/veyron.h b/include/configs/veyron.h index 0761de3ad2..2ab6d6c6aa 100644 --- a/include/configs/veyron.h +++ b/include/configs/veyron.h @@ -13,8 +13,6 @@ #include -#define CONFIG_SPI_FLASH_GIGADEVICE - #define CONFIG_KEYBOARD #endif -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 00/13] System Firmware Loader for TI K3 family SoCs
On Wed, 2019-05-08 at 13:43 -0500, dannenb...@ti.com wrote:
> Hi TF,
> thanks for chiming in. Comments inlined...
>
> On Wed, May 08, 2019 at 04:31:35AM +, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-05-07 at 22:00 +0200, Simon Goldschmidt wrote:
> > >
> > >
> > > On 07.05.19 19:25, Andreas Dannenberg wrote:
> > > >
> > > >
> > [...]
> > >
> > > >
> > > >
> > > > While I also have a working solution based on the existing FS
> > > > loader
> > > > framework this has its own challenges, namely by its very
> > > > nature
> > > > only
> > > > addressing a subset of our use cases (no eMMC/SD RAW boot
> > > > support
> > > > for
> > > > example),
> > IMO, it's actually not that hard to enhance RAW support, i think
> > minimal changes are required. I have attached the patches about an
> > example of loading RAW from QSPI that i have done locally last few
> > week
> > ago.
> As your patches show, no it's not hard, it's more or less taking
> pieces
> from the SPL loader framework and refactoring them into the FS
> loader,
> creating a good and universal solution usable across SPL and U-Boot
> in
> environments that are not tightly constrained in terms of memory.
>
> What I was going after is finding a way to load from different media
> "pre-relocation" SPL (board_init_f), with almost no memory available,
> where I have to agonize over every single KB available.
This is just a simple "loader", provide user flexibility of loading
stuff in anywhere, from SPL to U-Boot. As long as DM is supported by
the time running at "pre-relocation" SPL, then FS loader should be able
to work.
> >
> > >
> > > >
> > > > being heavier on resource usage (needing to use ENV to pass
> > > > parameters),
> > ENV is optional, you can use DTS.
> Is it? I had to update the FS loader framework when I experimented
> with
> it, please see attached patch. I had refactored it such that I can
> pass
> in all relevant data via platform data for the intial boot mode I was
> going after, so that I can dynamically configure it on the fly from
> early SPL board_init_f() based on boot media / boot mode, etc.
Yes, you can tie up loader with target HW node for destination loading.
For example, tie up with FPGA manager node, loading bistream file from
MMC to FPGA manager.
Here is an example, but i put the fs loader phandle under chosen node
because most files and images are stored in the same storage.
http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=commit;h=0a42a132a4b8
46031df2c4a7d04692240ed34843
>
> >
> > For example loading FPGA bitstream from QSPI RAW:
> >
> > /* DTS */
> > / {
> > + aliases {
> > + spi0 =
> > + };
> > +
> > + fs_loader0: fs-loader {
> > + u-boot,dm-pre-reloc;
> > + compatible = "u-boot,fs-loader";
> > + sfconfig = <0 0 1 3>;
> > + };
> > +};
> > +
> > +_mgr {
> > + u-boot,dm-pre-reloc;
> > + firmware-loader = <_loader0>;
> > + altr,bitstream = "30";
> > +};
> The above hard-codes and duplicates information that is already known
> to
> U-Boot (CONFIG_SF_DEFAULT_*), and will do more of the same as this is
> being extended. How does one keep this consistent?
Current fs loader not support RAW loading yet, i'm not sure whether it
should support it by adding more specific storage API(much more messy),
or just fully support filesystem only with one generic filesystem
abstract interface.
This example codes provide user opportunity to override the spi setting
when running fs loader. CONFIG_SF_DEFAULT_* would be used by the
drivers which are not running the fs loader.
>
> And how does this scale to support like 5 different boot modes using
> a
> single DTB? I guess one could populate 5 nodes, and then pick one
> based
> on boot mode during SPL execution, by extending the probe function
> accordingly.
This is just a very simple fs loader. This is totally up to user how
they want to scale it up, may be adding the function to populate the fs
loader nodes, or loading the images based on boot storages ordering in
DTS?
>
> >
> >
> > >
> > > >
> > > > and not addressing the need to probe the boot peripheral.
> > You can add more different probing method in function called
> > "fs_loader_probe". Current fs_loader supports block(sdmmc, emmc,
> > etc...) probing, and with
> > the patches attached support QSPI probing.
> >
> > Another idea come to mind, we can use fs_loader for loading FIT
> > boot
> > image into RAM, and boot from RAM with existing SPL loader
> > framework,
> > but i'm not sure this implementation fit to your use case?
> Unfortunately for what I'm working on there is no space for this. It
> would be nice to be able to load our "System Firmware" alongside the
> next stage of U-Boot in a single FIT, and then just extact that
> firmware
> image similar to what CONFIG_SPL_FPGA_SUPPORT does in spl_fit.c.
> However I must load SYSFW and the U-Boot next stage as two steps
> (while bringing up DDR in-between).
>
> As I tried to
[U-Boot] [PATCH v3] dw_mmc: turn on the IO supply
Fixes the microSD slot on the ASUS C201.
Signed-off-by: Urja Rannikko
---
v2: use #if CONFIG_IS_ENABLED(DM_REGULATOR)
v3: Move ret variable inside the if block (only used there)
---
drivers/mmc/dw_mmc.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 1992d61182..22f6c7eefd 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#define PAGE_SIZE 4096
@@ -493,6 +494,21 @@ static int dwmci_set_ios(struct mmc *mmc)
if (host->clksel)
host->clksel(host);
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (mmc->vqmmc_supply) {
+ int ret;
+
+ if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
+ regulator_set_value(mmc->vqmmc_supply, 180);
+ else
+ regulator_set_value(mmc->vqmmc_supply, 330);
+
+ ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
+ if (ret)
+ return ret;
+ }
+#endif
+
return 0;
}
--
2.21.0
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Re: [U-Boot] [PATCH] ARM: socfpga: Fix FPGA bitstream loading code
On 5/13/19 2:58 PM, Chee, Tien Fong wrote:
> On Thu, 2019-05-09 at 10:34 +0200, Marek Vasut wrote:
>> On 5/9/19 5:57 AM, Chee, Tien Fong wrote:
>>>
>>> On Wed, 2019-05-08 at 14:55 +0200, Marek Vasut wrote:
On 5/8/19 12:17 PM, Chee, Tien Fong wrote:
>
>
> On Tue, 2019-05-07 at 21:44 +0200, Marek Vasut wrote:
>>
>>
>> On 5/7/19 9:43 PM, Simon Goldschmidt wrote:
>>>
>>>
>>>
>>>
>>>
>>> On 07.05.19 21:41, Marek Vasut wrote:
On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
>
>
>
>
>
> On 07.05.19 21:19, Marek Vasut wrote:
>>
>>
>>
>> According to SoCFPGA Cyclone V datasheet
>> rev.2018.01.26
>> page
>> 175
>> (Chapter 5, FPGA Manager, data register) and Arria10
>> datasheet
>> rev.2017.07.22 page 211 (Chapter 5.4.1.2, FPGA
>> Manager,
>> img_data_w
>> register), the FPGA data register must be written
>> with
>> writes
>> with
>> non-incrementing address.
>>
>> The current code increments the address in 32-byte
>> bursts.
>> Fix the
>> code so it does not increment the address and writes
>> the
>> register
>> repeatedly instead. >
>> Signed-off-by: Marek Vasut
>> Cc: Chin Liang See
>> Cc: Dinh Nguyen
>> Cc: Simon Goldschmidt > m>
>> Cc: Tien Fong Chee
>> ---
>> drivers/fpga/socfpga.c | 3 +--
>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/drivers/fpga/socfpga.c
>> b/drivers/fpga/socfpga.c
>> index 685957626b..6ecea771ce 100644
>> --- a/drivers/fpga/socfpga.c
>> +++ b/drivers/fpga/socfpga.c
>> @@ -55,8 +55,7 @@ void fpgamgr_program_write(const
>> void
>> *rbf_data,
>> size_t rbf_size)
>> " cmp %2, #0\n"
>> " beq 2f\n"
>> "1: ldmia %0!, {r0-r7}\n"
>> - " stmia %1!, {r0-r7}\n"
>> - " sub %1, #32\n"
>> + " stmia %1, {r0-r7}\n"
> Iirc, stmia without the "!" still stores the registers
> to
> different
> addresses, it just does not change %1 any more if you
> leave
> away the
> "!"? So this would save on opcode, but not change
> anything?
Uh oh, you're right. Do we have a bigger problem here
then ?
Or
is the
socfpga ignoring the bottom 5 bits of this register
address ?
>>> Well, bitsream programming works for me very well (we're
>>> loading
>>> all our
>>> FGPAs in U-Boot from a FIT image), so maybe it's the
>>> documentation
>>> that
>>> has a problem?
>> That could indeed be, maybe someone on the CC list can take a
>> look
>> into
>> it and crosscheck it with internal docs ?
> I can't find any doc mention about "FPGA data must be written
> in
> non-
> incremting address", but i saw there is a description about
> configuration data is buffered in a 64 deep x 32 bits wide FIFO
> in
> the
> FPGA Manager https://www.intel.com/content/dam/www/programmable
> /us/
> en/p
> dfs/literature/hb/arria-10/a10_5v4.pdf (pg. 204)
Well yes, it's a FIFO, but is the FIFO populated by writing to a
single
non-incrementing address or are we supposed to write to
subsequent
incrementing addresses ?
>
>
> Based on my understand through this register
> fpga_mgr_fpgamgrdata
> address map (0xFFCFE400-0xFFCFE7FF) on pg. 207 , the 256 bytes
> of
> FIFO
> buffer is mapping to above range addresses.
0xFFCFE7FF-0xFFCFE400 = 0x400 = 1024 Bytes , not 256 . Why ?
>>> Finally, i have connected all scattered dot information from few
>>> internal docs. The register fpga_mgr_fpgamgrdata is actually a
>>> space in
>>> memory, acting like a buffer for the FPGA data. Regardless of the
>>> programming mode, data input from this buffer is translated into a
>>> 32-
>>> bit wide data path used by the configuration logic.
>> Does that mean that a write anywhere in 0xFFCFE400..0xFFCFE7FF ends
>> up
>> in the same register / FIFO ? Does that mean that whole address range
>> ignores the bottom 0x3ff MSbits ? Does it matter to which address in
>> that range the CPU writes the data or not ?
>
> Sorry, that's all information i have. Anyway, i have already engaged
> the HW engineer in the loop, and i will update you once i have more
> details.
Thanks, let's wait and see ...
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] ARM: socfpga: Fix FPGA bitstream loading code
On Thu, 2019-05-09 at 10:34 +0200, Marek Vasut wrote:
> On 5/9/19 5:57 AM, Chee, Tien Fong wrote:
> >
> > On Wed, 2019-05-08 at 14:55 +0200, Marek Vasut wrote:
> > >
> > > On 5/8/19 12:17 PM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Tue, 2019-05-07 at 21:44 +0200, Marek Vasut wrote:
> > > > >
> > > > >
> > > > > On 5/7/19 9:43 PM, Simon Goldschmidt wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > On 07.05.19 21:41, Marek Vasut wrote:
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > > On 07.05.19 21:19, Marek Vasut wrote:
> > > > > > > > >
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > According to SoCFPGA Cyclone V datasheet
> > > > > > > > > rev.2018.01.26
> > > > > > > > > page
> > > > > > > > > 175
> > > > > > > > > (Chapter 5, FPGA Manager, data register) and Arria10
> > > > > > > > > datasheet
> > > > > > > > > rev.2017.07.22 page 211 (Chapter 5.4.1.2, FPGA
> > > > > > > > > Manager,
> > > > > > > > > img_data_w
> > > > > > > > > register), the FPGA data register must be written
> > > > > > > > > with
> > > > > > > > > writes
> > > > > > > > > with
> > > > > > > > > non-incrementing address.
> > > > > > > > >
> > > > > > > > > The current code increments the address in 32-byte
> > > > > > > > > bursts.
> > > > > > > > > Fix the
> > > > > > > > > code so it does not increment the address and writes
> > > > > > > > > the
> > > > > > > > > register
> > > > > > > > > repeatedly instead. >
> > > > > > > > > Signed-off-by: Marek Vasut
> > > > > > > > > Cc: Chin Liang See
> > > > > > > > > Cc: Dinh Nguyen
> > > > > > > > > Cc: Simon Goldschmidt > > > > > > > > m>
> > > > > > > > > Cc: Tien Fong Chee
> > > > > > > > > ---
> > > > > > > > > drivers/fpga/socfpga.c | 3 +--
> > > > > > > > > 1 file changed, 1 insertion(+), 2 deletions(-)
> > > > > > > > >
> > > > > > > > > diff --git a/drivers/fpga/socfpga.c
> > > > > > > > > b/drivers/fpga/socfpga.c
> > > > > > > > > index 685957626b..6ecea771ce 100644
> > > > > > > > > --- a/drivers/fpga/socfpga.c
> > > > > > > > > +++ b/drivers/fpga/socfpga.c
> > > > > > > > > @@ -55,8 +55,7 @@ void fpgamgr_program_write(const
> > > > > > > > > void
> > > > > > > > > *rbf_data,
> > > > > > > > > size_t rbf_size)
> > > > > > > > > " cmp %2, #0\n"
> > > > > > > > > " beq 2f\n"
> > > > > > > > > "1: ldmia %0!, {r0-r7}\n"
> > > > > > > > > - " stmia %1!, {r0-r7}\n"
> > > > > > > > > - " sub %1, #32\n"
> > > > > > > > > + " stmia %1, {r0-r7}\n"
> > > > > > > > Iirc, stmia without the "!" still stores the registers
> > > > > > > > to
> > > > > > > > different
> > > > > > > > addresses, it just does not change %1 any more if you
> > > > > > > > leave
> > > > > > > > away the
> > > > > > > > "!"? So this would save on opcode, but not change
> > > > > > > > anything?
> > > > > > > Uh oh, you're right. Do we have a bigger problem here
> > > > > > > then ?
> > > > > > > Or
> > > > > > > is the
> > > > > > > socfpga ignoring the bottom 5 bits of this register
> > > > > > > address ?
> > > > > > Well, bitsream programming works for me very well (we're
> > > > > > loading
> > > > > > all our
> > > > > > FGPAs in U-Boot from a FIT image), so maybe it's the
> > > > > > documentation
> > > > > > that
> > > > > > has a problem?
> > > > > That could indeed be, maybe someone on the CC list can take a
> > > > > look
> > > > > into
> > > > > it and crosscheck it with internal docs ?
> > > > I can't find any doc mention about "FPGA data must be written
> > > > in
> > > > non-
> > > > incremting address", but i saw there is a description about
> > > > configuration data is buffered in a 64 deep x 32 bits wide FIFO
> > > > in
> > > > the
> > > > FPGA Manager https://www.intel.com/content/dam/www/programmable
> > > > /us/
> > > > en/p
> > > > dfs/literature/hb/arria-10/a10_5v4.pdf (pg. 204)
> > > Well yes, it's a FIFO, but is the FIFO populated by writing to a
> > > single
> > > non-incrementing address or are we supposed to write to
> > > subsequent
> > > incrementing addresses ?
> > >
> > > >
> > > >
> > > > Based on my understand through this register
> > > > fpga_mgr_fpgamgrdata
> > > > address map (0xFFCFE400-0xFFCFE7FF) on pg. 207 , the 256 bytes
> > > > of
> > > > FIFO
> > > > buffer is mapping to above range addresses.
> > > 0xFFCFE7FF-0xFFCFE400 = 0x400 = 1024 Bytes , not 256 . Why ?
> > Finally, i have connected all scattered dot information from few
> > internal docs. The register fpga_mgr_fpgamgrdata is actually a
> > space in
> > memory, acting like a buffer for the FPGA data. Regardless of the
> > programming mode, data input from this buffer is translated into a
> > 32-
> > bit wide data path used by the configuration logic.
> Does that mean that a write
Re: [U-Boot] [PATCH v2] dw_mmc: turn on the IO supply
Am Montag, 1. April 2019, 19:44:22 CEST schrieb Urja Rannikko:
> Fixes the microSD slot on the ASUS C201.
>
> Signed-off-by: Urja Rannikko
> ---
> v2: use #if CONFIG_IS_ENABLED(DM_REGULATOR)
> -
> drivers/mmc/dw_mmc.c | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
> index 93a836eac3..b04c1f9f41 100644
> --- a/drivers/mmc/dw_mmc.c
> +++ b/drivers/mmc/dw_mmc.c
> @@ -13,6 +13,7 @@
> #include
> #include
> #include
> +#include
>
> #define PAGE_SIZE 4096
>
> @@ -440,6 +441,7 @@ static int dwmci_set_ios(struct mmc *mmc)
> #endif
> struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
> u32 ctype, regs;
> + int ret;
This produces a new warning about an unused variable in the !DM_REGULATOR
case. I guess either move the "ret" below or add a " __maybe_unused" if that
is possible for variables?
>
> debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
>
> @@ -469,6 +471,19 @@ static int dwmci_set_ios(struct mmc *mmc)
> if (host->clksel)
> host->clksel(host);
>
> +#if CONFIG_IS_ENABLED(DM_REGULATOR)
> + if (mmc->vqmmc_supply) {
> + if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
> + regulator_set_value(mmc->vqmmc_supply, 180);
> + else
> + regulator_set_value(mmc->vqmmc_supply, 330);
> +
> + ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
> + if (ret)
> + return ret;
> + }
> +#endif
> +
> return 0;
> }
>
>
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Re: [U-Boot] [PATCH v2] spl: add overall SPL size check
On Sat, May 11, 2019 at 3:55 AM Tom Rini wrote: > > On Mon, Apr 22, 2019 at 10:27:21PM +0200, Simon Goldschmidt wrote: > > > This adds a size check for SPL that can dynamically check generated > > SPL binaries (including devicetree) for a size limit that ensures > > this image plus global data, heap and stack fit in initial SRAM. > > > > Since some of these sizes are not available to make, a new host tool > > 'spl_size_limit' is added that dumps the resulting maximum size for > > an SPL binary to stdout. This tool is used in toplevel Makefile to > > implement the size check on SPL binaries. > > > > Signed-off-by: Simon Goldschmidt > > OK, this has a race / dependency problem: > https://travis-ci.org/trini/u-boot/jobs/530803338 Hmm, let me check that. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] arm: socfpga: Re-add support for Aries MCV SoM and MCVEV[KP] board
On Sun, May 12, 2019 at 7:25 PM Wolfgang Grandegger
wrote:
>
> Re-add support for Aries Embedded MCV SoM, which is CycloneV based
> and the associated MCVEVK and MCVEVP baseboard. The board can boot
> from eMMC. Ethernet and USB is supported.
>
> The Aries Embedded boards have been removed with commit 03b54997d568
> ("board/aries: Remove"). I will now take care of them.
>
> The device-tree files are from mainline Linux commit e93c9c99a629
> ("Linux v5.1)".
>
> Signed-off-by: Wolfgang Grandegger
> CC: Marek Vasut
> CC: Simon Goldschmidt
Reviewed-by: Simon Goldschmidt
> ---
>
> Changes in v2:
> - remove "aries" in .travis.yml
> - add "socfpga_legacy_reset_compat=1" and "bootm_size=0xa00" to
> the default environment
> - use PARTUUID to define the Linux root device
> - include "socfpga-common-u-boot.dtsi" also adding the missing
> "u-boot,dm-pre-reloc" for the "rst" odr "sdr" nodes
> - add supported DTS files to the MAINTAINERS file
>
> arch/arm/dts/Makefile| 1 +
> arch/arm/dts/socfpga_cyclone5_mcv.dtsi | 22 +
> arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi | 34 ++
> arch/arm/dts/socfpga_cyclone5_mcvevk.dts | 81 +++
> arch/arm/mach-socfpga/Kconfig| 7 +
> board/aries/mcvevk/MAINTAINERS | 9 +
> board/aries/mcvevk/Makefile | 7 +
> board/aries/mcvevk/qts/iocsr_config.h| 659
> +++
> board/aries/mcvevk/qts/pinmux_config.h | 218
> board/aries/mcvevk/qts/pll_config.h | 84 +++
> board/aries/mcvevk/qts/sdram_config.h| 343
> board/aries/mcvevk/socfpga.c | 5 +
> configs/socfpga_mcvevk_defconfig | 59 ++
> include/configs/socfpga_mcvevk.h | 103
> 14 files changed, 1632 insertions(+)
> create mode 100644 arch/arm/dts/socfpga_cyclone5_mcv.dtsi
> create mode 100644 arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi
> create mode 100644 arch/arm/dts/socfpga_cyclone5_mcvevk.dts
> create mode 100644 board/aries/mcvevk/MAINTAINERS
> create mode 100644 board/aries/mcvevk/Makefile
> create mode 100644 board/aries/mcvevk/qts/iocsr_config.h
> create mode 100644 board/aries/mcvevk/qts/pinmux_config.h
> create mode 100644 board/aries/mcvevk/qts/pll_config.h
> create mode 100644 board/aries/mcvevk/qts/sdram_config.h
> create mode 100644 board/aries/mcvevk/socfpga.c
> create mode 100644 configs/socfpga_mcvevk_defconfig
> create mode 100644 include/configs/socfpga_mcvevk.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 8e082f2..139c224 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -276,6 +276,7 @@ dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
> dtb-$(CONFIG_ARCH_SOCFPGA) += \
> socfpga_arria5_socdk.dtb\
> socfpga_arria10_socdk_sdmmc.dtb \
> + socfpga_cyclone5_mcvevk.dtb \
> socfpga_cyclone5_is1.dtb\
> socfpga_cyclone5_socdk.dtb \
> socfpga_cyclone5_dbm_soc1.dtb \
> diff --git a/arch/arm/dts/socfpga_cyclone5_mcv.dtsi
> b/arch/arm/dts/socfpga_cyclone5_mcv.dtsi
> new file mode 100644
> index 000..bd92806
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_cyclone5_mcv.dtsi
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2015 Marek Vasut
> + */
> +
> +#include "socfpga_cyclone5.dtsi"
> +
> +/ {
> + model = "Aries/DENX MCV";
> + compatible = "altr,socfpga-cyclone5", "altr,socfpga";
> +
> + memory@0 {
> + name = "memory";
> + device_type = "memory";
> + reg = <0x0 0x4000>; /* 1 GiB */
> + };
> +};
> +
> + {/* On-SoM eMMC */
> + bus-width = <8>;
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi
> b/arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi
> new file mode 100644
> index 000..79f5d92
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi
> @@ -0,0 +1,34 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * U-Boot additions
> + *
> + * Copyright (C) 2015 Marek Vasut
> + * Copyright (C) 2019 Wolfgang Grandegger
> + */
> +
> +#include "socfpga-common-u-boot.dtsi"
> +
> + {
> + status = "disabled";
> +};
> +
> + {
> + u-boot,dm-pre-reloc;
> +};
> +
> + {
> + clock-frequency = <1>;
> + u-boot,dm-pre-reloc;
> +};
> +
> + {
> + bank-name = "porta";
> +};
> +
> + {
> + bank-name = "portb";
> +};
> +
> + {
> + bank-name = "portc";
> +};
> diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts
> b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts
> new file mode 100644
> index 000..ceaec29
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts
> @@ -0,0 +1,81 @@
Re: [U-Boot] [PATCH 09/12] sh: mpr2: Remove the board
Hi Marek, > Betreff: [PATCH 09/12] sh: mpr2: Remove the board > > Last change to this board was done in 2016, has no prospects of ever being > converted to DM, drop it. > > Signed-off-by: Marek Vasut > Cc: Chris Brandt > Cc: Mark Jonas > Cc: Nobuhiro Iwamatsu > Cc: Vladimir Zapolskiy > Cc: Yoshihiro Shimoda > --- > arch/sh/Kconfig| 5 -- > board/mpr2/Kconfig | 9 --- > board/mpr2/MAINTAINERS | 6 -- > board/mpr2/Makefile| 19 - > board/mpr2/lowlevel_init.S | 117 --- > board/mpr2/mpr2.c | 137 - > configs/mpr2_defconfig | 31 - > include/configs/mpr2.h | 55 --- > 8 files changed, 379 deletions(-) > delete mode 100644 board/mpr2/Kconfig > delete mode 100644 board/mpr2/MAINTAINERS delete mode 100644 > board/mpr2/Makefile delete mode 100644 board/mpr2/lowlevel_init.S > delete mode 100644 board/mpr2/mpr2.c delete mode 100644 > configs/mpr2_defconfig delete mode 100644 include/configs/mpr2.h Sad but true: U-Boot is not supported on this board anymore. Acked-by: Mark Jonas Greetings, Mark ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/3] sysreset: switch to using SYSRESET_POWER_OFF for poweroff
It seems that SYSRESET_POWER_OFF was added recently, and all previous code
used SYSRESET_POWER for poweroff. SYSRESET_POWER is supposed to be a
PMIC-level power cycle, not a poweroff.
Signed-off-by: Urja Rannikko
---
Note: I didnt touch the test/dm/sysreset.c code yet, mostly because
I wanted to get feedback on this first and that i'd need to understand
the tests properly to do that (and i havent used them before at all).
---
arch/arm/mach-stm32mp/cmd_poweroff.c | 2 +-
arch/sandbox/cpu/state.c | 2 +-
drivers/power/pmic/stpmic1.c | 2 +-
drivers/sysreset/sysreset_psci.c | 2 +-
drivers/sysreset/sysreset_sandbox.c | 4 ++--
5 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-stm32mp/cmd_poweroff.c
b/arch/arm/mach-stm32mp/cmd_poweroff.c
index f54dd1daf2..62347425a0 100644
--- a/arch/arm/mach-stm32mp/cmd_poweroff.c
+++ b/arch/arm/mach-stm32mp/cmd_poweroff.c
@@ -14,7 +14,7 @@ int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
puts("poweroff ...\n");
mdelay(100);
- ret = sysreset_walk(SYSRESET_POWER);
+ ret = sysreset_walk(SYSRESET_POWER_OFF);
if (ret == -EINPROGRESS)
mdelay(1000);
diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c
index d3b9c05985..dee5fde4f7 100644
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c
@@ -355,7 +355,7 @@ void state_reset_for_test(struct sandbox_state *state)
{
/* No reset yet, so mark it as such. Always allow power reset */
state->last_sysreset = SYSRESET_COUNT;
- state->sysreset_allowed[SYSRESET_POWER] = true;
+ state->sysreset_allowed[SYSRESET_POWER_OFF] = true;
memset(>wdt, '\0', sizeof(state->wdt));
memset(state->spi, '\0', sizeof(state->spi));
diff --git a/drivers/power/pmic/stpmic1.c b/drivers/power/pmic/stpmic1.c
index 65296c5fc3..eb735f4fe3 100644
--- a/drivers/power/pmic/stpmic1.c
+++ b/drivers/power/pmic/stpmic1.c
@@ -221,7 +221,7 @@ static int stpmic1_sysreset_request(struct udevice *dev,
enum sysreset_t type)
struct udevice *pmic_dev;
int ret;
- if (type != SYSRESET_POWER)
+ if (type != SYSRESET_POWER_OFF)
return -EPROTONOSUPPORT;
ret = uclass_get_device_by_driver(UCLASS_PMIC,
diff --git a/drivers/sysreset/sysreset_psci.c b/drivers/sysreset/sysreset_psci.c
index de2ec8aeb1..c7907b3226 100644
--- a/drivers/sysreset/sysreset_psci.c
+++ b/drivers/sysreset/sysreset_psci.c
@@ -18,7 +18,7 @@ static int psci_sysreset_request(struct udevice *dev, enum
sysreset_t type)
case SYSRESET_COLD:
function_id = PSCI_0_2_FN_SYSTEM_RESET;
break;
- case SYSRESET_POWER:
+ case SYSRESET_POWER_OFF:
function_id = PSCI_0_2_FN_SYSTEM_OFF;
break;
default:
diff --git a/drivers/sysreset/sysreset_sandbox.c
b/drivers/sysreset/sysreset_sandbox.c
index 38e2a7e241..8bc9f4b4cc 100644
--- a/drivers/sysreset/sysreset_sandbox.c
+++ b/drivers/sysreset/sysreset_sandbox.c
@@ -57,13 +57,13 @@ static int sandbox_sysreset_request(struct udevice *dev,
enum sysreset_t type)
case SYSRESET_COLD:
state->last_sysreset = type;
break;
- case SYSRESET_POWER:
+ case SYSRESET_POWER_OFF:
state->last_sysreset = type;
if (!state->sysreset_allowed[type])
return -EACCES;
sandbox_exit();
break;
- case SYSRESET_POWER_OFF:
+ case SYSRESET_POWER:
if (!state->sysreset_allowed[type])
return -EACCES;
default:
--
2.21.0
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[U-Boot] [PATCH 3/3] rk8xx: add a sysreset driver for poweroff
Based on snooping around the linux kernel rk8xx driver.
Tested on an ASUS C201.
Signed-off-by: Urja Rannikko
---
drivers/power/pmic/Kconfig | 1 +
drivers/power/pmic/rk8xx.c | 62 +++---
include/power/rk8xx_pmic.h | 4 +++
3 files changed, 63 insertions(+), 4 deletions(-)
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 5c6c045fad..d95f9aeafb 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -124,6 +124,7 @@ config PMIC_PM8916
config PMIC_RK8XX
bool "Enable support for Rockchip PMIC RK8XX"
depends on DM_PMIC
+ select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
---help---
The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs,
an RTC and two low Rds (resistance (drain to source)) switches. It is
diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c
index 25c339ab12..52e41051ae 100644
--- a/drivers/power/pmic/rk8xx.c
+++ b/drivers/power/pmic/rk8xx.c
@@ -6,6 +6,9 @@
#include
#include
+#include
+#include
+#include
#include
#include
#include
@@ -49,9 +52,9 @@ static int rk8xx_read(struct udevice *dev, uint reg, uint8_t
*buff, int len)
return 0;
}
-#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
static int rk8xx_bind(struct udevice *dev)
{
+#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
ofnode regulators_node;
int children;
@@ -68,10 +71,15 @@ static int rk8xx_bind(struct udevice *dev)
if (!children)
debug("%s: %s - no child found\n", __func__, dev->name);
+#endif
+
+ if (CONFIG_IS_ENABLED(SYSRESET))
+ return device_bind_driver(dev, "rk8xx-sysreset",
+ "rk8xx-sysreset", NULL);
+
/* Always return success for this device */
return 0;
}
-#endif
static int rk8xx_probe(struct udevice *dev)
{
@@ -103,10 +111,56 @@ U_BOOT_DRIVER(pmic_rk8xx) = {
.name = "rk8xx pmic",
.id = UCLASS_PMIC,
.of_match = rk8xx_ids,
-#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
.bind = rk8xx_bind,
-#endif
.priv_auto_alloc_size = sizeof(struct rk8xx_priv),
.probe = rk8xx_probe,
.ops = _ops,
};
+
+#if IS_ENABLED(CONFIG_SYSRESET)
+/* NOTE: Should only enable this function if the rockchip,system-power-manager
+ * property is in the device tree node, but it is there in every board that has
+ * an rk8xx in u-boot currently, so this is left as an excercise for later.
+ */
+static int rk8xx_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct udevice *pmic_dev;
+ struct rk8xx_priv *priv;
+ int ret;
+ u8 bits;
+
+ if (type != SYSRESET_POWER_OFF)
+ return -EPROTONOSUPPORT;
+
+ ret = uclass_get_device_by_driver(UCLASS_PMIC,
+ DM_GET_DRIVER(pmic_rk8xx),
+ _dev);
+
+ if (ret)
+ return -EOPNOTSUPP;
+
+ priv = dev_get_priv(pmic_dev);
+
+ if (priv->variant == RK818_ID)
+ bits = DEV_OFF;
+ else
+ bits = DEV_OFF_RST;
+
+ ret = pmic_clrsetbits(pmic_dev, REG_DEVCTRL, 0, bits);
+
+ if (ret < 0)
+ return ret;
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops rk8xx_sysreset_ops = {
+ .request = rk8xx_sysreset_request,
+};
+
+U_BOOT_DRIVER(rk8xx_sysreset) = {
+ .name = "rk8xx-sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = _sysreset_ops,
+};
+#endif
diff --git a/include/power/rk8xx_pmic.h b/include/power/rk8xx_pmic.h
index c06248f751..565b35985e 100644
--- a/include/power/rk8xx_pmic.h
+++ b/include/power/rk8xx_pmic.h
@@ -177,6 +177,10 @@ enum {
#define RK8XX_ID_MSK 0xfff0
+/* DEVCTRL bits for poweroff */
+#define DEV_OFF_RSTBIT(3)
+#define DEV_OFFBIT(0)
+
struct rk8xx_reg_table {
char *name;
u8 reg_ctl;
--
2.21.0
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[U-Boot] [PATCH 2/3] sysreset: move stm32mp sysreset poweroff implementation to sysreset uclass
This is a generic implementation. Add CONFIG_SYSRESET_CMD_POWEROFF
to signal when we need it. Enable it from the STPMIC1 config and in
sandbox.
The config flag is transitionary, that is it can be removed after all
poweroff implementations use sysreset, and just have CMD_POWEROFF depend
on sysreset.
Signed-off-by: Urja Rannikko
---
Note: I cant test STM32MP, so I would really appreciate if someone could
test this series on that.
---
arch/Kconfig | 1 +
arch/arm/mach-stm32mp/Makefile | 3 ---
arch/arm/mach-stm32mp/cmd_poweroff.c | 24
drivers/power/pmic/Kconfig | 1 +
drivers/sysreset/Kconfig | 10 ++
drivers/sysreset/sysreset-uclass.c | 18 ++
6 files changed, 30 insertions(+), 27 deletions(-)
delete mode 100644 arch/arm/mach-stm32mp/cmd_poweroff.c
diff --git a/arch/Kconfig b/arch/Kconfig
index 239289b885..83ff21dfd7 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -91,6 +91,7 @@ config SANDBOX
select LZO
select SPI
select SUPPORT_OF_CONTROL
+ select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
imply BITREVERSE
select BLOBLIST
imply CMD_DM
diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile
index 1493914a11..f59ced5ee1 100644
--- a/arch/arm/mach-stm32mp/Makefile
+++ b/arch/arm/mach-stm32mp/Makefile
@@ -11,9 +11,6 @@ ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-y += bsec.o
-ifndef CONFIG_STM32MP1_TRUSTED
-obj-$(CONFIG_SYSRESET) += cmd_poweroff.o
-endif
endif
obj-$(CONFIG_ARMV7_PSCI) += psci.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR) += pwr_regulator.o
diff --git a/arch/arm/mach-stm32mp/cmd_poweroff.c
b/arch/arm/mach-stm32mp/cmd_poweroff.c
deleted file mode 100644
index 62347425a0..00
--- a/arch/arm/mach-stm32mp/cmd_poweroff.c
+++ /dev/null
@@ -1,24 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
- */
-
-#include
-#include
-#include
-
-int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int ret;
-
- puts("poweroff ...\n");
- mdelay(100);
-
- ret = sysreset_walk(SYSRESET_POWER_OFF);
-
- if (ret == -EINPROGRESS)
- mdelay(1000);
-
- /*NOTREACHED when power off*/
- return CMD_RET_FAILURE;
-}
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index b0cd260354..5c6c045fad 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -234,6 +234,7 @@ config DM_PMIC_TPS65910
config PMIC_STPMIC1
bool "Enable support for STMicroelectronics STPMIC1 PMIC"
depends on DM_PMIC && DM_I2C
+ select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
---help---
The STPMIC1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches.
It is accessed via an I2C interface. The device is used with STM32MP1
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 30aed2c4c1..4c883923bf 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -33,6 +33,16 @@ config TPL_SYSRESET
if SYSRESET
+if CMD_POWEROFF
+
+config SYSRESET_CMD_POWEROFF
+ bool "sysreset implementation of the poweroff command"
+ help
+ This should be selected by the appropriate PMIC driver if
+ the poweroff command is enabled.
+
+endif
+
config SYSRESET_GPIO
bool "Enable support for GPIO reset driver"
select DM_GPIO
diff --git a/drivers/sysreset/sysreset-uclass.c
b/drivers/sysreset/sysreset-uclass.c
index ad831c703a..39202588ae 100644
--- a/drivers/sysreset/sysreset-uclass.c
+++ b/drivers/sysreset/sysreset-uclass.c
@@ -118,6 +118,24 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
return 0;
}
+#if IS_ENABLED(CONFIG_SYSRESET_CMD_POWEROFF)
+int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int ret;
+
+ puts("poweroff ...\n");
+ mdelay(100);
+
+ ret = sysreset_walk(SYSRESET_POWER_OFF);
+
+ if (ret == -EINPROGRESS)
+ mdelay(1000);
+
+ /*NOTREACHED when power off*/
+ return CMD_RET_FAILURE;
+}
+#endif
+
static int sysreset_post_bind(struct udevice *dev)
{
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
--
2.21.0
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Re: [U-Boot] [PATCH v2] dw_mmc: turn on the IO supply
Hiya, On Thu, Apr 11, 2019 at 8:07 PM Urja Rannikko wrote: > > Hi, > > On Mon, Apr 1, 2019 at 5:44 PM Urja Rannikko wrote: > > > > Fixes the microSD slot on the ASUS C201. > > > > Signed-off-by: Urja Rannikko > > --- > > v2: use #if CONFIG_IS_ENABLED(DM_REGULATOR) > > Ping? Anything I should do wrt this? Ping number two. I think i'll resend this the next time so that the actual patch isnt lost in the depths of mailboxes... -- Urja Rannikko ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/2] spi: imx: work with cs greater 0
currently spi mxc driver can only handle cs 0.
Allow it to handle also cs > 0.
Signed-off-by: Heiko Schocher
---
drivers/spi/mxc_spi.c | 54 +--
1 file changed, 42 insertions(+), 12 deletions(-)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index fba76bf740..c65955d59b 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -38,6 +38,8 @@ __weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
#define CONFIG_SYS_SPI_MXC_WAIT(CONFIG_SYS_HZ/100) /* 10
ms */
#endif
+#define MAX_CS_COUNT 4
+
struct mxc_spi_slave {
struct spi_slave slave;
unsigned long base;
@@ -50,6 +52,8 @@ struct mxc_spi_slave {
unsigned intmax_hz;
unsigned intmode;
struct gpio_desc ss;
+ struct gpio_desc cs_gpios[MAX_CS_COUNT];
+ struct udevice *dev;
};
static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
@@ -59,8 +63,16 @@ static inline struct mxc_spi_slave *to_mxc_spi_slave(struct
spi_slave *slave)
static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
{
+ struct udevice *dev = mxcs->dev;
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+
+ u32 cs = slave_plat->cs;
+
if (CONFIG_IS_ENABLED(DM_SPI)) {
- dm_gpio_set_value(>ss, 1);
+ if (!dm_gpio_is_valid(>cs_gpios[cs]))
+ return;
+
+ dm_gpio_set_value(>cs_gpios[cs], 1);
} else {
if (mxcs->gpio > 0)
gpio_set_value(mxcs->gpio, mxcs->ss_pol);
@@ -69,8 +81,16 @@ static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
{
+ struct udevice *dev = mxcs->dev;
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+
+ u32 cs = slave_plat->cs;
+
if (CONFIG_IS_ENABLED(DM_SPI)) {
- dm_gpio_set_value(>ss, 0);
+ if (!dm_gpio_is_valid(>cs_gpios[cs]))
+ return;
+
+ dm_gpio_set_value(>cs_gpios[cs], 0);
} else {
if (mxcs->gpio > 0)
gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
@@ -492,23 +512,31 @@ static int mxc_spi_probe(struct udevice *bus)
int node = dev_of_offset(bus);
const void *blob = gd->fdt_blob;
int ret;
+ int i;
- if (gpio_request_by_name(bus, "cs-gpios", 0, >ss,
-GPIOD_IS_OUT)) {
- dev_err(bus, "No cs-gpios property\n");
- return -EINVAL;
+ ret = gpio_request_list_by_name(bus, "cs-gpios", mxcs->cs_gpios,
+ ARRAY_SIZE(mxcs->cs_gpios), 0);
+ if (ret < 0) {
+ pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
+ return ret;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(mxcs->cs_gpios); i++) {
+ if (!dm_gpio_is_valid(>cs_gpios[i]))
+ continue;
+
+ ret = dm_gpio_set_dir_flags(>cs_gpios[i],
+ GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
+ if (ret) {
+ dev_err(bus, "Setting cs %d error\n", i);
+ return ret;
+ }
}
mxcs->base = devfdt_get_addr(bus);
if (mxcs->base == FDT_ADDR_T_NONE)
return -ENODEV;
- ret = dm_gpio_set_value(>ss, 0);
- if (ret) {
- dev_err(bus, "Setting cs error\n");
- return ret;
- }
-
mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
2000);
@@ -529,6 +557,8 @@ static int mxc_spi_claim_bus(struct udevice *dev)
struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ mxcs->dev = dev;
+
return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
}
--
2.17.2
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[U-Boot] [PATCH 1/2] spi: imx: remove doubled pointer from mxc_spi_probe
in mxc_spi_probe() plat and mxcs pointer are created:
struct mxc_spi_slave *plat = bus->platdata;
struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
which have the same value. Remove plat pointer.
Signed-off-by: Heiko Schocher
---
drivers/spi/mxc_spi.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 6846762719..fba76bf740 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -488,7 +488,6 @@ void spi_release_bus(struct spi_slave *slave)
static int mxc_spi_probe(struct udevice *bus)
{
- struct mxc_spi_slave *plat = bus->platdata;
struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
int node = dev_of_offset(bus);
const void *blob = gd->fdt_blob;
@@ -500,11 +499,11 @@ static int mxc_spi_probe(struct udevice *bus)
return -EINVAL;
}
- plat->base = devfdt_get_addr(bus);
- if (plat->base == FDT_ADDR_T_NONE)
+ mxcs->base = devfdt_get_addr(bus);
+ if (mxcs->base == FDT_ADDR_T_NONE)
return -ENODEV;
- ret = dm_gpio_set_value(>ss, 0);
+ ret = dm_gpio_set_value(>ss, 0);
if (ret) {
dev_err(bus, "Setting cs error\n");
return ret;
--
2.17.2
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[U-Boot] [PATCH 0/2] mxc_spi: DM improvements
This series improves the mxc_spi DM support. builds clean on travis, see: https://travis-ci.org/hsdenx/u-boot-test/builds/531614870 Heiko Schocher (2): spi: imx: remove doubled pointer from mxc_spi_probe spi: imx: work with cs greater 0 drivers/spi/mxc_spi.c | 57 --- 1 file changed, 43 insertions(+), 14 deletions(-) -- 2.17.2 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] configs: ls1088aqds: Enable config to write aligned data to TxFIFO
Enable config in LS1088aqds board to send only 16 bytes aligned data to TxFIFO while writing to flash Signed-off-by: Kuldeep Singh --- configs/ls1088aqds_tfa_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index 863d9c3361..8921231132 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -17,7 +17,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x300 default_hugepagesz=2m hugepagesz=2m hugepages=256" # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_SPI_FLASH_BAR is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y @@ -45,6 +44,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_E1000=y @@ -57,6 +57,7 @@ CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y CONFIG_FSL_DSPI=y CONFIG_FSL_QSPI=y CONFIG_USB=y -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3] riscv: Add Microchip MPFS Icicle board support
This patch adds Microchip MPFS Icicle board support.
For now, NS16550 serial driver is only enabled.
The Microchip MPFS Icicle defconfig by default builds
U-Boot for M-Mode with SMP support.
Signed-off-by: Padmarao Begari
---
Changes in v3
- Fix some typos
- Remove CONFIG_DM, CONFIG_DM_SERIAL, CONFIG_BAUDRATE,
CONFIG_SYS_NS16550, CONFIG_SYS_TEXT_BASE and CONFIG_NR_DRAM_BANKS
from microchip_mpfs_icicle_defconfig
- Add config SYS_TEXT_BASE in board kconfig
- Imply SYS_NS16550 in BOARD_SPECIFIC_OPTIONS
- select BOARD_EARLY_INIT_F in BOARD_SPECIFIC_OPTIONS
Changes in v2
- Fix some typos
- Rename target board to TARGET_MICROCHIP_ICICLE
- select CONFIG_BOARD_EARLY_INIT_F in BOARD_SPECIFIC_OPTIONS
- Remove #ifdef CONFIG_BOARD_EARLY_INIT_F
---
arch/riscv/Kconfig| 4 ++
board/microchip/mpfs_icicle/Kconfig | 26 +
board/microchip/mpfs_icicle/MAINTAINERS | 7
board/microchip/mpfs_icicle/Makefile | 7
board/microchip/mpfs_icicle/mpfs_icicle.c | 30 +++
configs/microchip_mpfs_icicle_defconfig | 9 +
include/configs/microchip_mpfs_icicle.h | 63 +++
7 files changed, 146 insertions(+)
create mode 100644 board/microchip/mpfs_icicle/Kconfig
create mode 100644 board/microchip/mpfs_icicle/MAINTAINERS
create mode 100644 board/microchip/mpfs_icicle/Makefile
create mode 100644 board/microchip/mpfs_icicle/mpfs_icicle.c
create mode 100644 configs/microchip_mpfs_icicle_defconfig
create mode 100644 include/configs/microchip_mpfs_icicle.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 362f3cd..573d6d6 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -11,6 +11,9 @@ choice
config TARGET_AX25_AE350
bool "Support ax25-ae350"
+config TARGET_MICROCHIP_ICICLE
+ bool "Support Microchip PolarFire-SoC Icicle Board"
+
config TARGET_QEMU_VIRT
bool "Support QEMU Virt Board"
@@ -22,6 +25,7 @@ endchoice
# board-specific options below
source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
+source "board/microchip/mpfs_icicle/Kconfig"
source "board/sifive/fu540/Kconfig"
# platform-specific options below
diff --git a/board/microchip/mpfs_icicle/Kconfig
b/board/microchip/mpfs_icicle/Kconfig
new file mode 100644
index 000..bf8e1a1
--- /dev/null
+++ b/board/microchip/mpfs_icicle/Kconfig
@@ -0,0 +1,26 @@
+if TARGET_MICROCHIP_ICICLE
+
+config SYS_BOARD
+ default "mpfs_icicle"
+
+config SYS_VENDOR
+ default "microchip"
+
+config SYS_CPU
+ default "generic"
+
+config SYS_CONFIG_NAME
+ default "microchip_mpfs_icicle"
+
+config SYS_TEXT_BASE
+ default 0x8000 if !RISCV_SMODE
+ default 0x8020 if RISCV_SMODE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select GENERIC_RISCV
+ select BOARD_EARLY_INIT_F
+ imply SMP
+ imply SYS_NS16550
+
+endif
diff --git a/board/microchip/mpfs_icicle/MAINTAINERS
b/board/microchip/mpfs_icicle/MAINTAINERS
new file mode 100644
index 000..22f3b97
--- /dev/null
+++ b/board/microchip/mpfs_icicle/MAINTAINERS
@@ -0,0 +1,7 @@
+Microchip MPFS icicle
+M: Padmarao Begari
+M: Cyril Jean
+S: Maintained
+F: board/microchip/mpfs_icicle/
+F: include/configs/microchip_mpfs_icicle.h
+F: configs/microchip_mpfs_icicle_defconfig
diff --git a/board/microchip/mpfs_icicle/Makefile
b/board/microchip/mpfs_icicle/Makefile
new file mode 100644
index 000..72b0410
--- /dev/null
+++ b/board/microchip/mpfs_icicle/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019 Microchip Technology Inc.
+# Padmarao Begari
+#
+
+obj-y += mpfs_icicle.o
diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c
b/board/microchip/mpfs_icicle/mpfs_icicle.c
new file mode 100644
index 000..0ef2431
--- /dev/null
+++ b/board/microchip/mpfs_icicle/mpfs_icicle.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Microchip Technology Inc.
+ * Padmarao Begari
+ */
+
+#include
+#include
+#include
+
+#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
+
+int board_init(void)
+{
+ /* For now nothing to do here. */
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ unsigned int val;
+
+ /* Reset uart peripheral */
+ val = readl(MPFS_SYSREG_SOFT_RESET);
+ val = (val & ~(1u << 5u));
+ writel(val, MPFS_SYSREG_SOFT_RESET);
+
+ return 0;
+}
diff --git a/configs/microchip_mpfs_icicle_defconfig
b/configs/microchip_mpfs_icicle_defconfig
new file mode 100644
index 000..3fa900a
--- /dev/null
+++ b/configs/microchip_mpfs_icicle_defconfig
@@ -0,0 +1,9 @@
+CONFIG_RISCV=y
+CONFIG_ARCH_RV64I=y
+CONFIG_NR_CPUS=5
+CONFIG_TARGET_MICROCHIP_ICICLE=y
+CONFIG_BOOTDELAY=3
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_FIT=y
+CONFIG_OF_PRIOR_STAGE=y
diff --git a/include/configs/microchip_mpfs_icicle.h
[U-Boot] [PATCH 1/1] imx8: cpu: fix warning for cpu_imx_get_temp
cpu_imx_get_temp() definition is wrapped with a ifdef macro,
therefore all function references should be also wrapped the same way
instead IS_ENABLED() usage.
Fix warning:
arch/arm/mach-imx/imx8/cpu.c: In function ‘cpu_imx_get_desc’:
arch/arm/mach-imx/imx8/cpu.c:612:40: warning: implicit declaration of
function ‘cpu_imx_get_temp’; did you mean ‘cpu_imx_get_desc’?
[-Wimplicit-function-declaration]
ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp());
^~~~
cpu_imx_get_desc
cpu_imx_get_desc
Fixes: 82467cb217 ("imx8: cpu: get temperature when print cpu desc")
Signed-off-by: Igor Opaniuk
---
arch/arm/mach-imx/imx8/cpu.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 12596c6387..616baed7cc 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -606,11 +606,11 @@ int cpu_imx_get_desc(struct udevice *dev, char *buf, int
size)
ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
plat->type, plat->rev, plat->name, plat->freq_mhz);
- if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
- buf = buf + ret;
- size = size - ret;
- ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp());
- }
+#if defined(CONFIG_IMX_SCU_THERMAL)
+ buf = buf + ret;
+ size = size - ret;
+ ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp());
+#endif
snprintf(buf + ret, size - ret, "\n");
--
2.17.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 03/18] dm: Add a No-op uclass
Hi Simon, On 07/05/2019 05:52, Simon Glass wrote: Hi Jean-Jacques, On Fri, 5 Apr 2019 at 06:56, Jean-Jacques Hiblot wrote: This uclass is intended for devices that do not need any features from the uclass, including binding children. This will typically be used by devices that are used to bind child devices but do not use dm_scan_fdt_dev() to do it. That is for example the case of several USB wrappers that have 2 child devices (1 for device and 1 for host) but bind only one at a any given time. Signed-off-by: Jean-Jacques Hiblot --- drivers/core/uclass.c | 5 + include/dm/uclass-id.h | 1 + 2 files changed, 6 insertions(+) Is there a test for this somewhere? It will be part of the v2. JJ - Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 5/5] apalis-tk1: use UUID for rootfs
1. Replace usage of "/dev/mmcblk*p*" with a proper UUID of rootfs
partition. This fixes the issue, when MMC controllers are probed in
a different order in U-boot and Linux kernel.
2. Fix legacy USB command (both sdboot and usbboot can be used now).
Signed-off-by: Igor Opaniuk
---
include/configs/apalis-tk1.h | 62
1 file changed, 41 insertions(+), 21 deletions(-)
diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h
index 1d296ba51a..ff6c5e425d 100644
--- a/include/configs/apalis-tk1.h
+++ b/include/configs/apalis-tk1.h
@@ -51,15 +51,22 @@
"tegra124-apalis-eval.dtb fat 0 1 mmcpart 0"
#define EMMC_BOOTCMD \
- "emmcargs=ip=off root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait\0" \
- "emmcboot=run setup; setenv bootargs ${defargs} ${emmcargs} " \
- "${setupargs} ${vidargs}; echo Booting from internal eMMC " \
- "chip...; run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \
+ "set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} " \
+ "rw rootfstype=ext3 rootwait\0" \
+ "emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \
+ "setenv bootargs ${defargs} ${emmcargs} " \
+ "${setupargs} ${vidargs}; echo Booting from internal eMMC; " \
+ "run emmcdtbload; " \
+ "load mmc ${emmcdev}:${emmcbootpart} ${kernel_addr_r} " \
"${boot_file} && run fdt_fixup && " \
"bootm ${kernel_addr_r} - ${dtbparam}\0" \
- "emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
- "${soc}-apalis-${fdt_board}.dtb && " \
- "setenv dtbparam ${fdt_addr_r}\0"
+ "emmcbootpart=1\0" \
+ "emmcdev=0\0" \
+ "emmcdtbload=setenv dtbparam; load mmc ${emmcdev}:${emmcbootpart} " \
+ "${fdt_addr_r} ${soc}-apalis-${fdt_board}.dtb && " \
+ "setenv dtbparam ${fdt_addr_r}\0" \
+ "emmcfinduuid=part uuid mmc ${mmcdev}:${emmcrootpart} uuid\0" \
+ "emmcrootpart=2\0"
#define NFS_BOOTCMD \
"nfsargs=ip=:eth0:on root=/dev/nfs rw\0" \
@@ -72,26 +79,38 @@
"&& setenv dtbparam ${fdt_addr_r}\0"
#define SD_BOOTCMD \
- "sdargs=ip=off root=/dev/mmcblk1p2 rw rootfstype=ext4 rootwait\0" \
- "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
+ "set_sdargs=setenv sdargs ip=off root=PARTUUID=${uuid} rw " \
+ "rootfstype=ext4 rootwait\0" \
+ "sdboot=run setup; run sdfinduuid; run set_sdargs; " \
+ "setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
"${vidargs}; echo Booting from SD card in 8bit slot...; " \
- "run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
- "${boot_file} && run fdt_fixup && " \
+ "run sddtbload; load mmc ${sddev}:${sdbootpart} " \
+ "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
"bootm ${kernel_addr_r} - ${dtbparam}\0" \
- "sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
- "${soc}-apalis-${fdt_board}.dtb " \
- "&& setenv dtbparam ${fdt_addr_r}\0"
+ "sdbootpart=1\0" \
+ "sddev=1\0" \
+ "sddtbload=setenv dtbparam; load mmc ${sddev}:${sdbootpart} " \
+ "${fdt_addr_r} ${soc}-apalis-${fdt_board}.dtb " \
+ "&& setenv dtbparam ${fdt_addr_r}\0" \
+ "sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \
+ "sdrootpart=2\0"
#define USB_BOOTCMD \
- "usbargs=ip=off root=/dev/sda2 rw rootfstype=ext4 rootwait\0" \
- "usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \
+ "set_usbargs=setenv usbargs ip=off root=PARTUUID=${uuid} rw " \
+ "rootfstype=ext4 rootwait\0" \
+ "usbboot=run setup; usb start; run usbfinduuid; run set_usbargs; " \
+ "setenv bootargs ${defargs} ${setupargs} " \
"${usbargs} ${vidargs}; echo Booting from USB stick...; " \
- "usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \
- "${boot_file} && run fdt_fixup && " \
+ "run usbdtbload; load usb ${usbdev}:${usbbootpart} " \
+ "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
"bootm ${kernel_addr_r} - ${dtbparam}\0" \
- "usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
- "${soc}-apalis-${fdt_board}.dtb " \
- "&& setenv dtbparam ${fdt_addr_r}\0"
+ "usbbootpart=1\0" \
+ "usbdev=0\0" \
+ "usbdtbload=setenv dtbparam; load usb ${usbdev}:${usbbootpart} " \
+ "${fdt_addr_r} ${soc}-apalis-${fdt_board}.dtb " \
+ "&& setenv dtbparam ${fdt_addr_r}\0" \
+ "usbfinduuid=part uuid usb ${usbdev}:${usbrootpart} uuid\0" \
+ "usbrootpart=2\0"
#define BOARD_EXTRA_ENV_SETTINGS \
"boot_file=uImage\0" \
@@
[U-Boot] [PATCH 4/5] apalis_imx6: use UUID for rootfs
1. Replace usage of "/dev/mmcblk*p*" with a proper UUID of rootfs
partition. This fixes the issue, when MMC controllers are probed in
a different order in U-boot and Linux kernel.
2. Fix legacy USB command (both sdboot and usbboot can be used now).
Signed-off-by: Igor Opaniuk
---
include/configs/apalis_imx6.h | 62 ---
1 file changed, 42 insertions(+), 20 deletions(-)
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 96169f55f0..04b21a3128 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -125,16 +125,21 @@
"imx6q-apalis-cam-eval.dtb fat 0 1"
#define EMMC_BOOTCMD \
- "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext4 " \
- "rootwait\0" \
- "emmcboot=run setup; " \
+ "set_emmcargs emmcargs ip=off root=PARTUUID=${uuid} rw,noatime " \
+ "rootfstype=ext4 rootwait\0" \
+ "emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \
"setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
"${vidargs}; echo Booting from internal eMMC chip...; " \
- "run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \
- "${boot_file} && run fdt_fixup && " \
+ "run emmcdtbload; load mmc ${emmcdev}:${emmcbootpart} " \
+ "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
"bootz ${kernel_addr_r} ${dtbparam}\0" \
- "emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
- "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+ "emmcbootpart=1\0" \
+ "emmcdev=0\0" \
+ "emmcdtbload=setenv dtbparam; load mmc ${emmcdev}:${emmcbootpart} " \
+ "${fdt_addr_r} ${fdt_file} && " \
+ "setenv dtbparam \" - ${fdt_addr_r}\" && true\0" \
+ "emmcfinduuid=part uuid mmc ${mmcdev}:${emmcrootpart} uuid\0" \
+ "emmcrootpart=2\0"
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x2000\0" \
@@ -157,27 +162,43 @@
"&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
#define SD_BOOTCMD \
- "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext4 " \
- "rootwait\0" \
- "sdboot=run setup; " \
+ "set_sdargs=setenv sdargs ip=off root=PARTUUID=${uuid} rw,noatime " \
+ "rootfstype=ext4 rootwait\0" \
+ "sdboot=run setup; run sdfinduuid; run set_sdargs; " \
"setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
"${vidargs}; echo Booting from SD card; " \
- "run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
- "${boot_file} && run fdt_fixup && " \
+ "run sddtbload; load mmc ${sddev}:${sdbootpart} " \
+ "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
"bootz ${kernel_addr_r} ${dtbparam}\0" \
- "sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
- "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+ "sdbootpart=1\0" \
+ "sddev=1\0" \
+ "sddtbload=setenv dtbparam; load mmc ${sddev}:${sdbootpart} " \
+ "${fdt_addr_r} " \
+ "${fdt_file} && setenv dtbparam \" - " \
+ "${fdt_addr_r}\" && true\0" \
+ "sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \
+ "sdrootpart=2\0"
+
#define USB_BOOTCMD \
- "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext4 " \
- "rootwait\0" \
- "usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \
+ "set_usbargs=setenv usbargs ip=off root=PARTUUID=${uuid} rw,noatime " \
+ "rootfstype=ext4 rootwait\0" \
+ "usbboot=run setup; usb start; run usbfinduuid; run set_usbargs; " \
+ "setenv bootargs ${defargs} ${setupargs} " \
"${usbargs} ${vidargs}; echo Booting from USB stick...; " \
- "usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \
+ "run usbdtbload; load usb " \
+ "${usbdev}:${usbbootpart} ${kernel_addr_r} " \
"${boot_file} && run fdt_fixup && " \
"bootz ${kernel_addr_r} ${dtbparam}\0" \
- "usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
- "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+ "usbbootpart=1\0" \
+ "usbdev=0\0" \
+ "usbdtbload=setenv dtbparam; load usb ${usbdev}:${usbbootpart} "\
+ "${fdt_addr_r} " \
+ "${fdt_file} && setenv dtbparam \" - " \
+ "${fdt_addr_r}\" && true\0" \
+ "usbfinduuid=part uuid usb ${usbdev}:${usbrootpart} uuid\0" \
+ "usbrootpart=2\0"
+
#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
#define FDT_FILE "imx6q-apalis-eval.dtb"
@@ -201,6 +222,7 @@
MEM_LAYOUT_ENV_SETTINGS \
NFS_BOOTCMD \
SD_BOOTCMD \
+ USB_BOOTCMD \
[U-Boot] [PATCH 3/5] colibri_vf: use UUID for rootfs
Replace usage of "/dev/mmcblk*p*" with a proper UUID of rootfs
partition. This fixes the issue, when MMC controllers are probed in
a different order in U-boot and Linux kernel.
Signed-off-by: Igor Opaniuk
---
include/configs/colibri_vf.h | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 0d57e303a1..da9a8426ec 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -68,12 +68,19 @@
"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define SD_BOOTCMD \
- "sdargs=root=/dev/mmcblk0p2 ro rootwait\0" \
- "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \
+ "set_sdargs=setenv sdargs root=PARTUUID=${uuid} ro rootwait\0" \
+ "sdboot=run setup; run sdfinduuid; run set_sdargs; " \
+ "setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \
"${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
- "load mmc 0:1 ${kernel_addr_r} ${kernel_file} && " \
- "load mmc 0:1 ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
+ "load mmc ${sddev}:${sdbootpart} ${kernel_addr_r} ${kernel_file} && " \
+ "load mmc ${sddev}:${sdbootpart} ${fdt_addr_r} " \
+ "${soc}-colibri-${fdt_board}.dtb && " \
"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "sdbootpart=1\0" \
+ "sddev=0\0" \
+ "sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \
+ "sdrootpart=2\0"
+
#define UBI_BOOTCMD \
"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
--
2.17.1
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[U-Boot] [PATCH 1/5] colibri_imx7: use UUID for rootfs
Replace usage of "/dev/mmcblk*p*" with a proper UUID of rootfs
partition. This fixes the issue, when MMC controllers are probed in
a different order in U-boot and Linux kernel.
Signed-off-by: Igor Opaniuk
---
include/configs/colibri_imx7.h | 47 --
1 file changed, 28 insertions(+), 19 deletions(-)
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index 5a4b9801cb..8bc75aba59 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -51,14 +51,22 @@
#define CONFIG_SERVERIP192.168.10.1
#define EMMC_BOOTCMD \
- "emmcargs=ip=off root=/dev/mmcblk0p2 ro rootfstype=ext4 rootwait\0" \
- "emmcboot=run setup; " \
+ "set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} ro " \
+ "rootfstype=ext4 rootwait\0" \
+ "emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \
"setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
"${vidargs}; echo Booting from internal eMMC chip...; " \
"run m4boot && " \
- "load mmc 0:1 ${fdt_addr_r}
${soc}-colibri-emmc-${fdt_board}.dtb && " \
- "load mmc 0:1 ${kernel_addr_r} ${boot_file} && " \
- "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0"
+ "load mmc ${emmcdev}:${emmcbootpart} ${fdt_addr_r} " \
+ "${soc}-colibri-emmc-${fdt_board}.dtb && " \
+ "load mmc ${emmcdev}:${emmcbootpart} ${kernel_addr_r} " \
+ "${boot_file} && run fdt_fixup && " \
+ "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "emmcbootpart=1\0" \
+ "emmcdev=0\0" \
+ "emmcfinduuid=part uuid mmc ${emmcdev}:${emmcrootpart} uuid\0" \
+ "emmcrootpart=2\0"
+
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x1000\0" \
@@ -69,24 +77,25 @@
"ramdisk_addr_r=0x8210\0"
#if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND)
-#define SD_BOOTCMD \
- "sdargs=root=/dev/mmcblk0p2 ro rootwait\0" \
- "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} " \
- "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
- "run m4boot && " \
- "load mmc 0:1 ${kernel_addr_r} ${kernel_file} && " \
- "load mmc 0:1 ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
- "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0"
+#define SD_BOOTDEV 0
#elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC)
+#define SD_BOOTDEV 1
+#endif
+
#define SD_BOOTCMD \
- "sdargs=root=/dev/mmcblk1p2 ro rootwait\0" \
- "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} " \
+ "set_sdargs=setenv sdargs root=PARTUUID=${uuid} ro rootwait\0" \
+ "sdboot=run setup; run sdfinduuid; run set_sdargs; " \
+ "setenv bootargs ${defargs} ${sdargs} " \
"${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
"run m4boot && " \
- "load mmc 1:1 ${kernel_addr_r} ${kernel_file} && " \
- "load mmc 1:1 ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
- "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0"
-#endif
+ "load mmc ${sddev}:${sdbootpart} ${kernel_addr_r} ${kernel_file} && " \
+ "load mmc ${sddev}:${sdbootpart} ${fdt_addr_r} " \
+ "${soc}-colibri-${fdt_board}.dtb && " \
+ "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "sdbootpart=1\0" \
+ "sddev=" __stringify(SD_BOOTDEV) "\0" \
+ "sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \
+ "sdrootpart=2\0"
#define NFS_BOOTCMD \
--
2.17.1
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[U-Boot] [PATCH 2/5] colibri-imx6ull: use UUID for rootfs
Replace usage of "/dev/mmcblk*p*" with a proper UUID of rootfs
partition. This fixes the issue, when MMC controllers are probed in
a different order in U-boot and Linux kernel.
Signed-off-by: Igor Opaniuk
---
include/configs/colibri-imx6ull.h | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/include/configs/colibri-imx6ull.h
b/include/configs/colibri-imx6ull.h
index 7cf550cf9e..2ba0ce5b79 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -66,12 +66,17 @@
"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define SD_BOOTCMD \
- "sdargs=root=/dev/mmcblk0p2 ro rootwait\0" \
- "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} " \
+ "set_sdargs=setenv sdargs root=PARTUUID=${uuid} ro rootwait\0" \
+ "sdboot=run setup; run sdfinduuid; run set_sdargs; " \
+ "setenv bootargs ${defargs} ${sdargs} " \
"${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
- "load mmc 0:1 ${kernel_addr_r} ${kernel_file} && " \
- "load mmc 0:1 ${fdt_addr_r} " FDT_FILE " && " \
+ "load mmc ${sddev}:${sdbootpart} ${kernel_addr_r} ${kernel_file} && " \
+ "load mmc ${sddev}:${sdbootpart} ${fdt_addr_r} " FDT_FILE " && " \
"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "sdbootpart=1\0" \
+ "sddev=0\0" \
+ "sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \
+ "sdrootpart=2\0"
#define UBI_BOOTCMD \
"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rw rootfstype=ubifs " \
--
2.17.1
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[U-Boot] [PATCH 2/2] armv8: ls1028a: enable workaround for errarum A-009007
From: Yinbo Zhu This patch is to make usb erratum A-009007 applies to ls1028a Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Yinbo Zhu Signed-off-by: Ran Wang --- Depends: http://patchwork.ozlabs.org/patch/1083257/ http://patchwork.ozlabs.org/patch/1083258/ http://patchwork.ozlabs.org/patch/1083259/ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index f2392f0ebf..af2d86bb9d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -143,7 +143,8 @@ static void erratum_a008997(void) out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) -#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) +#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ + defined(CONFIG_ARCH_LS1028A) #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ @@ -167,7 +168,8 @@ static void erratum_a009007(void) usb_phy = (void __iomem *)SCFG_USB_PHY3; PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); #endif -#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) +#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ + defined(CONFIG_ARCH_LS1028A) void __iomem *dcsr = (void __iomem *)DCSR_BASE; PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1); -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/2] armv8: Workaround for USB erratum of LS1028A
This is suplement for patch which would handle A-008997 Signed-off-by: Ran Wang --- Depends: http://patchwork.ozlabs.org/patch/1083257/ http://patchwork.ozlabs.org/patch/1083258/ http://patchwork.ozlabs.org/patch/1083259/ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 + arch/arm/cpu/armv8/fsl-layerscape/soc.c| 4 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++ 3 files changed, 7 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 8ecd095c76..fc4e866f1e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -48,6 +48,7 @@ config ARCH_LS1028A select SYS_I2C_MXC_I2C6 select SYS_I2C_MXC_I2C7 select SYS_I2C_MXC_I2C8 + select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A008514 if !TFABOOT select SYS_FSL_ERRATUM_A009663 if !TFABOOT diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 06f3edb302..f2392f0ebf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -126,6 +126,10 @@ static void erratum_a008997(void) set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2); set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3); #endif +#elif defined(CONFIG_ARCH_LS1028A) + clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1, + 0x7F << 11, + DCSR_USB_PCSTXSWINGFULL << 11); #endif #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index dbf3215cb6..dd73de4a9a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -214,6 +214,8 @@ #define USB_PHY_RX_EQ_VAL_20x0080 #define USB_PHY_RX_EQ_VAL_30x0380 #define USB_PHY_RX_EQ_VAL_40x0b80 +#define DCSR_USB_IOCR1 0x108004 +#define DCSR_USB_PCSTXSWINGFULL0x71 #define TP_ITYP_AV 0x0001 /* Initiator available */ #define TP_ITYP_TYPE(x)(((x) & 0x6) >> 1) /* Initiator Type */ -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] Pull request for UEFI sub-system for v2019.07-rc3
The following changes since commit 82da478b8f8ed41ed8bdbd0269da36ef6aaef7e8: Merge branch '2019-05-10-master-imports' (2019-05-10 11:08:48 -0400) are available in the Git repository at: git://git.denx.de/u-boot-efi.git tags/efi-2019-07-rc3 for you to fetch changes up to e2d82f8b2a91fb3fa78345f935a93a6db575effa: efi_loader: comments for efi_install_fdt() (2019-05-12 20:54:23 +0200) Travis CI: https://travis-ci.org/xypron2/u-boot/builds/531491341 Primary key fingerprint: 6DC4 F9C7 1F29 A6FA 06B7 6D33 C481 DBBC 2C05 1AC4 Pull request for UEFI sub-system for v2019.07-rc3 The development target for the UEFI sub-system is EBBR compliance. We have already implemented some further protocols to enable running the UEFI Shell and the UEFI SCT test suite. As some boards are severely memory constrained make some of these extras customizable. Provide bug fixes. The most prominent ones let us pass the UEFI SCT memory allocation tests. Heinrich Schuchardt (19): lib: charset: correct utf8_utf16_strnlen() description MAINTAINERS: assign include/charset.h efi_loader: observe CONFIG_EFI_LOADER_HII efi_loader: format Kconfig efi_loader: reword the EFI_LOADER config option efi_loader: make Unicode collation protocol customizable efi_loader: make device path to text protocol customizable efi_loader: fix typo in efi_locate_handle() comment efi_loader: LocateDevicePath() incorrect parameter check efi_loader: superfluous check in efi_remove_protocol() efi_loader: error code in UninstallProtocolInterface() efi_loader: check memory address before freeing efi_loader: out of resources in AllocatePages() efi_loader: AllocateAdress error handling efi_loader: simplify efi_allocate_pages() efi_loader: infinite recursion notifying events efi_loader: ACPI device node to text efi_loader: deduplicate code in cmd/bootefi.c efi_loader: comments for efi_install_fdt() MAINTAINERS | 1 + cmd/Kconfig | 1 + cmd/bootefi.c| 110 +-- include/charset.h| 12 ++-- lib/efi_loader/Kconfig | 69 --- lib/efi_loader/Makefile | 6 +- lib/efi_loader/efi_boottime.c| 16 +++-- lib/efi_loader/efi_device_path_to_text.c | 6 +- lib/efi_loader/efi_memory.c | 92 ++ lib/efi_loader/efi_root_node.c | 4 ++ lib/efi_selftest/Makefile| 5 +- lib/vsprintf.c | 4 +- 12 files changed, 188 insertions(+), 138 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
