date:20191107

Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations

2019-11-07 Thread Rick Chen

Hi Atish

>
> Hi Atish
>
> >
> > On Thu, 2019-11-07 at 19:41 +0800, Rick Chen wrote:
> > > Hi Anup & Lukas
> > >
> > > Anup Patel  於 2019年11月7日 週四 下午6:44寫道：
> > > > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas
> > > >  wrote:
> > > > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote:
> > > > > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen  > > > > > > wrote:
> > > > > > > Hi Anup
> > > > > > >
> > > > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel <
> > > > > > > > a...@brainfault.org> wrote:
> > > > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen <
> > > > > > > > > rickche...@gmail.com> wrote:
> > > > > > > > > > Hi Anup
> > > > > > > > > >
> > > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen <
> > > > > > > > > > > rickche...@gmail.com> wrote:
> > > > > > > > > > > > Hi Anup
> > > > > > > > > > > >
> > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel <
> > > > > > > > > > > > > a...@brainfault.org> wrote:
> > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen <
> > > > > > > > > > > > > > rickche...@gmail.com> wrote:
> > > > > > > > > > > > > > > Hi Anup
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen <
> > > > > > > > > > > > > > > > rickche...@gmail.com> wrote:
> > > > > > > > > > > > > > > > > Hi Anup
> > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup
> > > > > > > > > > > > > > > > > > > Patel  wrote:
> > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM
> > > > > > > > > > > > > > > > > > > > Alan Kao 
> > > > > > > > > > > > > > > > > > > > wrote:
> > > > > > > > > > > > > > > > > > > > > Hi Bin,
> > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > Thanks for the critics.  Comments
> > > > > > > > > > > > > > > > > > > > > below.
> > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at
> > > > > > > > > > > > > > > > > > > > > 06:38:00PM +0800, Bin Meng wrote:
> > > > > > > > > > > > > > > > > > > > > > Hi Rick,
> > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50
> > > > > > > > > > > > > > > > > > > > > > AM Rick Chen <
> > > > > > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote:
> > > > > > > > > > > > > > > > > > > > > > > Hi Bin
> > > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > > > Hi Rick,
> > > > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at
> > > > > > > > > > > > > > > > > > > > > > > > 2:18 PM Andes <
> > > > > > > > > > > > > > > > > > > > > > > > ub...@andestech.com> wrote:
> > > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen <
> > > > > > > > > > > > > > > > > > > > > > > > > r...@andestech.com>
> > > > > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to
> > > > > > > > > > > > > > > > > > > > > > > > > hart 0 always will be
> > > > > > > > > > > > > > > > > > > > > > > > > main
> > > > > > > > > > > > > > > > > > > > > > > > > hart coincidentally. When
> > > > > > > > > > > > > > > > > > > > > > > > > develop SPL flow, I try
> > > > > > > > > > > > > > > > > > > > > > > > > to
> > > > > > > > > > > > > > > > > > > > > > > > > force other harts to be
> > > > > > > > > > > > > > > > > > > > > > > > > main hart. And it will go
> > > > > > > > > > > > > > > > > > > > > > > > > wrong in sending IPI
> > > > > > > > > > > > > > > > > > > > > > > > > flow. So fix it.
> > > > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit
> > > > > > > > > > > > > > > > > > > > > > > > contain 2 fixes, or just 1
> > > > > > > > > > > > > > > > > > > > > > > > fix?
> > > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But
> > > > > > > > > > > > > > > > > > > > > > > they will cause one negative
> > > > > > > > > > > > > > > > > > > > > > > result
> > > > > > > > > > > > > > > > > > > > > > > that only hart 0 can send ipi
> > > > > > > > > > > > > > > > > > > > > > > to other harts.
> > > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart
> > > > > > > > > > > > > > > > > > > > > > > > > can be main hart in U-
> > > > > > > > > > > > > > > > > > > > > > > > > Boot SPL
> > > > > > > > > > > > > > > > > > > > > > > > > theoretically, but it
> > > > > > > > > > > > > > > > > > > > > > > > > still fail somewhere.
> > > > > > > > > > > > > > > > > > > > > > > > > After dig in
> > > > > > > > > > > > > > > > > > > > > > > > > and found there is an
> > > > > > > > > > > > > > > > > > > > > > > > > assumption that hart 0
> > > > > > > > > > > > > > > > > > > > > > > > > shall be
> > > > > > > > > > > > > > > > > > > > > > > > > main hart in OpenSbi.
> >

[U-Boot] test: Coverage error tools/binman/etype/cbfs.py 97% on i686

2019-11-07 Thread Heinrich Schuchardt


Hello Simon,

make tests produces an error on i686

NameStmts   Miss  Cover

tools/binman/etype/cbfs.py 90  397%

TOTAL2639 1199%

Type 'python3-coverage html' to get a report in htmlcov/index.html
Coverage error: 99%, but should be 100%
ValueError: Test coverage failure
dtoc code coverage: 
100%
fdt code coverage: 
100%
Tests FAILED
make: *** [Makefile:2043: tests] Error 1

Best regards

Heinrich
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] xilinx: Do defconfig syncup

2019-11-07 Thread Michal Simek

On 07. 11. 19 20:20, Tom Rini wrote:
> On Thu, Nov 07, 2019 at 02:37:21PM +0100, Michal Simek wrote:
> 
>> Sync up defconfigs according to latest Kconfig dependencies.
>>
>> Signed-off-by: Michal Simek 
> 
> I'll take this as a reminder to moveconfig -s everyone, thanks!

Wonderful. Your patch looks good to me.

Thanks,
Michal

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] cmd: move down CONFIG_CMD_BOOTEFI after CONFIG_BOOTM_VXWORKS

2019-11-07 Thread Heinrich Schuchardt


On 11/8/19 2:32 AM, AKASHI Takahiro wrote:

Due to the commit 4b0bcfa7c4ec ("Kconfig: Migrate CONFIG_BOOTM_* options")
BOOTEFI and BOOTEFI_HELLO_COMPILE (and other BOOTEFI configs) are
displayed in a long distance. This will make it difficult for us to
understand that those configurations are closely related.

Signed-off-by: AKASHI Takahiro 


This is what the change looks like:

== BEFORE ==

[*] bootm
[ ] bootz
  -*- booti
[*] bootefi
[*] Support booting Linux OS images
[*] Support booting NetBSD (non-EFI) loader images
[ ] Support booting OPENRTOS / FreeRTOS images
[ ] Support booting Enea OSE images
[*] Support booting Plan9 OS images
[*] Support booting RTEMS OS images
[*] Support booting VxWorks OS images
[*] Compile a standard EFI hello world binary for testing
[ ]   Allow booting a standard EFI hello world for testing
[*] UEFI unit tests
[ ] bootmenu

== AFTER ==

[*] bootm
[ ] bootz
 -*- booti
[*] Support booting Linux OS images
[*] Support booting NetBSD (non-EFI) loader images
[ ] Support booting OPENRTOS / FreeRTOS images
[ ] Support booting Enea OSE images
[*] Support booting Plan9 OS images
[*] Support booting RTEMS OS images
[*] Support booting VxWorks OS images
[*] bootefi
[*]   Compile a standard EFI hello world binary for testing
[ ] Allow booting a standard EFI hello world for testing
[*]   UEFI unit tests
[ ] bootmenu

Reviewed-by: Heinrich Schuchardt 


---
  cmd/Kconfig | 14 +++---
  1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 395dedd34d00..d9bc1eb8bd2b 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -263,13 +263,6 @@ config CMD_BOOTI
help
  Boot an AArch64 Linux Kernel image from memory.

-config CMD_BOOTEFI
-   bool "bootefi"
-   depends on EFI_LOADER
-   default y
-   help
- Boot an EFI image from memory.
-
  config BOOTM_LINUX
bool "Support booting Linux OS images"
depends on CMD_BOOTM || CMD_BOOTZ || CMD_BOOTI
@@ -318,6 +311,13 @@ config BOOTM_VXWORKS
help
  Support booting VxWorks images via the bootm command.

+config CMD_BOOTEFI
+   bool "bootefi"
+   depends on EFI_LOADER
+   default y
+   help
+ Boot an EFI image from memory.
+
  config CMD_BOOTEFI_HELLO_COMPILE
bool "Compile a standard EFI hello world binary for testing"
depends on CMD_BOOTEFI && !CPU_V7M && !SANDBOX



___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] USB doesn't work on Rockpro64 in u-boot

2019-11-07 Thread Jagan Teki

Hi Vasily,

On Fri, Nov 8, 2019 at 9:18 AM Vasily Khoruzhick  wrote:
>
> I checked voltage on regulator enable pin and it's 1.5v in u-boot (and it's
> not enough to enable regulator!) and in linux it's 3v. That's why USB
> ports have no power in u-boot.
>
> Looks like u-boot doesn't switch GPIO voltage from 1.8v to 3.3v. Any
> ideas how to fix this?

I think I need to clock look of this, will look into it next week. I'm
travelling till that time.
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] armv8: layerscape: set HWCONFIG_BUFFER_SIZE

2019-11-07 Thread Priyanka Jain



>-Original Message-
>From: U-Boot  On Behalf Of Michael Walle
>Sent: Monday, October 21, 2019 11:04 PM
>To: u-boot@lists.denx.de
>Cc: Tom Rini 
>Subject: [U-Boot] [PATCH] armv8: layerscape: set HWCONFIG_BUFFER_SIZE
>
>Set the HWCONFIG_BUFFER_SIZE if it is not already set. Otherwise
>compilation will fail if CONFIG_HWCONFIG and HWCONFIG_BUFFER_SIZE are
>not set.
>
>Taken from arch/powerpc/include/asm/config.h.
>
>Signed-off-by: Michael Walle 
>---
> arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 
> 1 file changed, 4 insertions(+)
>
>diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
>b/arch/arm/include/asm/arch-fsl-layerscape/config.h
>index a83c70ece2..24bf854cbe 100644
>--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
>+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
>@@ -12,6 +12,10 @@
>
> #define CONFIG_STANDALONE_LOAD_ADDR   0x8030
>
>+#ifndef HWCONFIG_BUFFER_SIZE
>+  #define HWCONFIG_BUFFER_SIZE 256
>+#endif
>+
This breaks compilation for platform like lx2160ardb.
Error snippet:

include/configs/lx2160a_common.h:173: warning: "HWCONFIG_BUFFER_SIZE" redefined 

 #define HWCONFIG_BUFFER_SIZE  128
  
In file included from include/configs/lx2160a_common.h:10,
 from include/configs/lx2160ardb.h:9,
 from include/config.h:5,
 from include/common.h:23,
 from common/malloc_simple.c:10:
./arch/arm/include/asm/arch/config.h:16: note: this is the location of the 
previous definition  
   #define HWCONFIG_BUFFER_SIZE 256  

--priyankajain
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] mx6cuboxi: Add Baruch as maintainer

2019-11-07 Thread Baruch Siach


On Thu, Nov 07 2019, Fabio Estevam wrote:

> Add Baruch Siach as a mx6cuboxi maintainer.
>
> Signed-off-by: Fabio Estevam 

Acked-by: Baruch Siach 

Thanks,
baruch

> ---
>  board/solidrun/mx6cuboxi/MAINTAINERS | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/board/solidrun/mx6cuboxi/MAINTAINERS 
> b/board/solidrun/mx6cuboxi/MAINTAINERS
> index 81f82bc9b5..bd098b479f 100644
> --- a/board/solidrun/mx6cuboxi/MAINTAINERS
> +++ b/board/solidrun/mx6cuboxi/MAINTAINERS
> @@ -1,4 +1,5 @@
>  MX6CUBOXI BOARD
> +M:   Baruch Siach 
>  M:   Fabio Estevam 
>  S:   Maintained
>  F:   board/solidrun/mx6cuboxi/


-- 
 http://baruch.siach.name/blog/  ~. .~   Tk Open Systems
=}ooO--U--Ooo{=
   - bar...@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 19/19] arm: socfpga: agilex: Enable Agilex SoC build

2019-11-07 Thread Ley Foon Tan

Add build support for Agilex SoC.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v6:
- Include socfpga_soc64_common.h.

v5:
- Enable NCORE_CACHE

v3:
- Disable CONFIG_USE_TINY_PRINTF

v2:
- Remove IC_CLK define, use clock DM method to get i2c clock
- Change CONFIG_ENV_SIZE to 4KB since CONFIG_SPI_FLASH_USE_4K_SECTORS is 
enabled.
---
 arch/arm/Kconfig   |  4 +-
 arch/arm/mach-socfpga/Kconfig  | 16 +++
 arch/arm/mach-socfpga/Makefile |  9 
 configs/socfpga_agilex_defconfig   | 58 ++
 include/configs/socfpga_agilex_socdk.h | 15 +++
 5 files changed, 100 insertions(+), 2 deletions(-)
 create mode 100644 configs/socfpga_agilex_defconfig
 create mode 100644 include/configs/socfpga_agilex_socdk.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 629c5e8c2d..723bd5c619 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -905,7 +905,7 @@ config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select ARCH_EARLY_INIT_R
select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
-   select ARM64 if TARGET_SOCFPGA_STRATIX10
+   select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM
select DM_SERIAL
@@ -917,7 +917,7 @@ config ARCH_SOCFPGA
select SPL_LIBGENERIC_SUPPORT
select SPL_NAND_SUPPORT if SPL_NAND_DENALI
select SPL_OF_CONTROL
-   select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
+   select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || 
TARGET_SOCFPGA_AGILEX
select SPL_SERIAL_SUPPORT
select SPL_SYSRESET
select SPL_WATCHDOG_SUPPORT
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index fc0a54214f..922442a31f 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -26,6 +26,15 @@ config SYS_TEXT_BASE
default 0x0140 if TARGET_SOCFPGA_ARRIA10
default 0x0140 if TARGET_SOCFPGA_GEN5
 
+config TARGET_SOCFPGA_AGILEX
+   bool
+   select ARMV8_MULTIENTRY
+   select ARMV8_SET_SMPEN
+   select ARMV8_SPIN_TABLE
+   select CLK
+   select NCORE_CACHE
+   select SPL_CLK if SPL
+
 config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
@@ -72,6 +81,10 @@ choice
prompt "Altera SOCFPGA board select"
optional
 
+config TARGET_SOCFPGA_AGILEX_SOCDK
+   bool "Intel SOCFPGA SoCDK (Agilex)"
+   select TARGET_SOCFPGA_AGILEX
+
 config TARGET_SOCFPGA_ARIES_MCVEVK
bool "Aries MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -132,6 +145,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT
 endchoice
 
 config SYS_BOARD
+   default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -148,6 +162,7 @@ config SYS_BOARD
default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 
 config SYS_VENDOR
+   default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -165,6 +180,7 @@ config SYS_SOC
default "socfpga"
 
 config SYS_CONFIG_NAME
+   default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 81b6ffc675..418f543b20 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -41,6 +41,14 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_AGILEX
 obj-y  += clock_manager_agilex.o
+obj-y  += mailbox_s10.o
+obj-y  += misc_s10.o
+obj-y  += mmu-arm64_s10.o
+obj-y  += reset_manager_s10.o
+obj-y  += system_manager_s10.o
+obj-y  += timer_s10.o
+obj-y  += wrap_pinmux_config_s10.o
+obj-y  += wrap_pll_config_s10.o
 endif
 
 ifdef CONFIG_SPL_BUILD
@@ -59,6 +67,7 @@ obj-y += firewall.o
 obj-y  += spl_s10.o
 endif
 ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+obj-y  += firewall.o
 obj-y  += spl_agilex.o
 endif
 endif
diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
new file mode 100644
index 00..c221500155
--- /dev/null
+++ b/configs/socfpga_agilex_defconfig
@@ -0,0 +1,58 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_agilex"
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_BOOTDELAY=5
+CONFIG_SPL_CACHE=y
+CONFIG_SPL_SPI_LOAD=y

[U-Boot] [PATCH v6 09/19] clk: agilex: Add clock driver for Agilex

2019-11-07 Thread Ley Foon Tan

Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.

agilex-clock.h is from Linux commit ID cd2e1ad12247.

Signed-off-by: Chee Hong Ang 
Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v6:
- Use agilex-clock.h from Linux instead of using stratix10-clock.h.

v4:
- Get address from DT.

v3:
- Fixed clear PLL's lostlock bypass mode to ensure the clock manager provide 
glitchless clock
to downstream logic
- Changed CM_REG_CLRBITS(), CM_REG_SETBITS() and CM_REG_CLRSETBITS() macros
argument ordering, to match with clrbits_le32, setbits_le32 and clrsetbits_le32.
- Rename stratix10-clock.h to socfpga-soc64-clock.h.
- Convert struct to defines and move defines to clk-agilex.h

v2:
- Convert Clock driver to DM
---
 arch/arm/mach-socfpga/misc.c |   5 +
 drivers/clk/altera/Makefile  |   1 +
 drivers/clk/altera/clk-agilex.c  | 579 +++
 drivers/clk/altera/clk-agilex.h  | 237 ++
 include/dt-bindings/clock/agilex-clock.h |  70 +++
 5 files changed, 892 insertions(+)
 create mode 100644 drivers/clk/altera/clk-agilex.c
 create mode 100644 drivers/clk/altera/clk-agilex.h
 create mode 100644 include/dt-bindings/clock/agilex-clock.h

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 1c6a0032dd..c95d9f6f43 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -244,7 +244,12 @@ void socfpga_get_managers_addr(void)
if (ret)
hang();
 
+#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+   ret = socfpga_get_base_addr("intel,agilex-clkmgr",
+   _clkmgr_base);
+#else
ret = socfpga_get_base_addr("altr,clk-mgr", _clkmgr_base);
+#endif
if (ret)
hang();
 }
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index a3ae8b24b0..96215ad5c4 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -3,4 +3,5 @@
 # Copyright (C) 2018 Marek Vasut 
 #
 
+obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c
new file mode 100644
index 00..5fedec549d
--- /dev/null
+++ b/drivers/clk/altera/clk-agilex.c
@@ -0,0 +1,579 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_clk_platdata {
+   void __iomem *regs;
+};
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void clk_write_bypass_mainpll(struct socfpga_clk_platdata *plat, u32 
val)
+{
+   CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
+   cm_wait_for_fsm();
+}
+
+static void clk_write_bypass_perpll(struct socfpga_clk_platdata *plat, u32 val)
+{
+   CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
+   cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void clk_write_ctrl(struct socfpga_clk_platdata *plat, u32 val)
+{
+   CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
+   cm_wait_for_fsm();
+}
+
+#define MEMBUS_MAINPLL 0
+#define MEMBUS_PERPLL  1
+#define MEMBUS_TIMEOUT 1000
+#define MEMBUS_ADDR_CLKSLICE   0x27
+#define MEMBUS_CLKSLICE_SYNC_MODE_EN   0x80
+
+static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll,
+  int timeout)
+{
+   int cnt = 0;
+   u32 req_status;
+
+   if (pll == MEMBUS_MAINPLL)
+   req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM);
+   else
+   req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM);
+
+   while ((cnt < timeout) && (req_status & CLKMGR_MEM_REQ_SET_MSK)) {
+   if (pll == MEMBUS_MAINPLL)
+   req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM);
+   else
+   req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM);
+   cnt++;
+   }
+
+   if (cnt >= timeout)
+   return -ETIMEDOUT;
+
+   return 0;
+}
+
+static int membus_write_pll(struct socfpga_clk_platdata *plat, u32 pll,
+   u32 addr_offset, u32 wdat, int timeout)
+{
+   u32 addr;
+   u32 val;
+
+   addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK);
+
+   val = (CLKMGR_MEM_REQ_SET_MSK | CLKMGR_MEM_WR_SET_MSK |
+  (wdat << CLKMGR_MEM_WDAT_LSB_OFFSET) | addr);
+
+   if (pll == MEMBUS_MAINPLL)
+   CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM);
+   else
+   CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM);
+
+   debug("MEMBUS: Write 0x%08x to addr = 0x%08x\n", wdat, addr);
+
+   return

[U-Boot] [PATCH v6 08/19] arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz

2019-11-07 Thread Ley Foon Tan

CLKMGR_INTOSC_HZ should be 400MHz, instead of 460MHz.
Removed also unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ.

Signed-off-by: Ley Foon Tan 

---
v6:
- Remove unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ.
---
 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h 
b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
index 3b4bb62ca5..71fbaa7667 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
@@ -13,9 +13,7 @@ const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
 const unsigned int cm_get_intosc_clk_hz(void);
 const unsigned int cm_get_fpga_clk_hz(void);
 
-#define CLKMGR_EOSC1_HZ2500
-#define CLKMGR_INTOSC_HZ   46000
-#define CLKMGR_FPGA_CLK_HZ 5000
+#define CLKMGR_INTOSC_HZ   4
 
 /* Clock configuration accessors */
 const struct cm_config * const cm_get_default_config(void);
-- 
2.19.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 12/19] arm: agilex: Add clock handoff offset for Agilex

2019-11-07 Thread Ley Foon Tan

Add clock handoff offset for Agilex. Remove S10 prefix to avoid confusion.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 
---
 arch/arm/mach-socfpga/include/mach/handoff_s10.h | 9 +++--
 arch/arm/mach-socfpga/wrap_pll_config_s10.c  | 5 +++--
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h 
b/arch/arm/mach-socfpga/include/mach/handoff_s10.h
index ba0f1fd1b2..abf04d9b04 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_s10.h
@@ -26,8 +26,13 @@
 #define S10_HANDOFF_OFFSET_LENGTH  0x4
 #define S10_HANDOFF_OFFSET_DATA0x10
 
-#define S10_HANDOFF_CLOCK_OSC  (S10_HANDOFF_BASE + 0x608)
-#define S10_HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C)
+#ifdef TARGET_SOCFPGA_STRATIX10
+#define HANDOFF_CLOCK_OSC  (S10_HANDOFF_BASE + 0x608)
+#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C)
+#else
+#define HANDOFF_CLOCK_OSC  (S10_HANDOFF_BASE + 0x5fc)
+#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x600)
+#endif
 
 #define S10_HANDOFF_SIZE   4096
 
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c 
b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
index b266a5817b..3da85791a1 100644
--- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
@@ -33,7 +33,8 @@ const struct cm_config * const cm_get_default_config(void)
 const unsigned int cm_get_osc_clk_hz(void)
 {
 #ifdef CONFIG_SPL_BUILD
-   u32 clock = readl(S10_HANDOFF_CLOCK_OSC);
+
+   u32 clock = readl(HANDOFF_CLOCK_OSC);
 
writel(clock,
   socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
@@ -50,7 +51,7 @@ const unsigned int cm_get_intosc_clk_hz(void)
 const unsigned int cm_get_fpga_clk_hz(void)
 {
 #ifdef CONFIG_SPL_BUILD
-   u32 clock = readl(S10_HANDOFF_CLOCK_FPGA);
+   u32 clock = readl(HANDOFF_CLOCK_FPGA);
 
writel(clock,
   socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD2);
-- 
2.19.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 13/19] ddr: altera: Restructure Stratix 10 SDRAM driver

2019-11-07 Thread Ley Foon Tan

Restructure Stratix 10 SDRAM driver. Move common code to separate
file, in preparation to support SDRAM driver for Agilex.

Signed-off-by: Ley Foon Tan 

---
v6:
- Remove compatible "intel,sdr-ctl-agilex" from this patch.

v3:
- Change sdram_common.* to sdram_soc64.*
---
 drivers/ddr/altera/Makefile   |   2 +-
 drivers/ddr/altera/sdram_s10.c| 296 +
 drivers/ddr/altera/sdram_s10.h| 148 +
 drivers/ddr/altera/sdram_soc64.c  | 303 ++
 .../ddr/altera/{sdram_s10.h => sdram_soc64.h} |  70 ++--
 5 files changed, 340 insertions(+), 479 deletions(-)
 create mode 100644 drivers/ddr/altera/sdram_soc64.c
 copy drivers/ddr/altera/{sdram_s10.h => sdram_soc64.h} (79%)

diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index 341ac0d73b..eb8da13b7d 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -9,5 +9,5 @@
 ifdef CONFIG_$(SPL_)ALTERA_SDRAM
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
-obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o
+obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
 endif
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index d7e6371ddb..fcab3ae3e4 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -14,28 +14,14 @@
 #include "sdram_s10.h"
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
 
-struct altera_sdram_priv {
-   struct ram_info info;
-   struct reset_ctl_bulk resets;
-};
-
-struct altera_sdram_platdata {
-   void __iomem *hmc;
-   void __iomem *ddr_sch;
-   void __iomem *iomhc;
-};
-
 DECLARE_GLOBAL_DATA_PTR;
 
 #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
 
-#define PGTABLE_OFF0x4000
-
 /* The followring are the supported configurations */
 u32 ddr_config[] = {
/* DDR_CONFIG(Address order,Bank,Column,Row) */
@@ -62,28 +48,6 @@ u32 ddr_config[] = {
DDR_CONFIG(1, 4, 10, 17),
 };
 
-static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
-{
-   return readl(plat->iomhc + reg);
-}
-
-static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
-{
-   return readl(plat->hmc + reg);
-}
-
-static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
- u32 data, u32 reg)
-{
-   return writel(data, plat->hmc + reg);
-}
-
-static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
- u32 reg)
-{
-   return writel(data, plat->ddr_sch + reg);
-}
-
 int match_ddr_conf(u32 ddr_conf)
 {
int i;
@@ -95,193 +59,12 @@ int match_ddr_conf(u32 ddr_conf)
return 0;
 }
 
-static int emif_clear(struct altera_sdram_platdata *plat)
-{
-   hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
-
-   return wait_for_bit_le32((const void *)(plat->hmc +
-RSTHANDSHAKESTAT),
-DDR_HMC_RSTHANDSHAKE_MASK,
-false, 1000, false);
-}
-
-static int emif_reset(struct altera_sdram_platdata *plat)
-{
-   u32 c2s, s2c, ret;
-
-   c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
-   s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
-
-   debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
- c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
- hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
- hmc_readl(plat, DRAMSTS));
-
-   if (s2c && emif_clear(plat)) {
-   printf("DDR: emif_clear() failed\n");
-   return -1;
-   }
-
-   debug("DDR: Triggerring emif reset\n");
-   hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
-
-   /* if seq2core[3] = 0, we are good */
-   ret = wait_for_bit_le32((const void *)(plat->hmc +
-RSTHANDSHAKESTAT),
-DDR_HMC_SEQ2CORE_INT_RESP_MASK,
-false, 1000, false);
-   if (ret) {
-   printf("DDR: failed to get ack from EMIF\n");
-   return ret;
-   }
-
-   ret = emif_clear(plat);
-   if (ret) {
-   printf("DDR: emif_clear() failed\n");
-   return ret;
-   }
-
-   debug("DDR: %s triggered successly\n", __func__);
-   return 0;
-}
-
-static int poll_hmc_clock_status(void)
-{
-   return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
-SYSMGR_SOC64_HMC_CLK),
-SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
-}
-
-static void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
-{
-   phys_size_t i;
-
-   if (addr % CONFIG_SYS_CACHELINE_SIZE) {
-   printf("DDR: address 0x%llx is not

[U-Boot] [PATCH v6 18/19] configs: socfpga: Move Stratix10 and Agilex common CONFIGs

2019-11-07 Thread Ley Foon Tan

Move Stratix10 and Agilex common CONFIGs to socfpga_soc64_common.h.

Signed-off-by: Ley Foon Tan 
---
 ...ratix10_socdk.h => socfpga_soc64_common.h} |   8 +-
 include/configs/socfpga_stratix10_socdk.h | 202 +-
 2 files changed, 7 insertions(+), 203 deletions(-)
 copy include/configs/{socfpga_stratix10_socdk.h => socfpga_soc64_common.h} 
(96%)

diff --git a/include/configs/socfpga_stratix10_socdk.h 
b/include/configs/socfpga_soc64_common.h
similarity index 96%
copy from include/configs/socfpga_stratix10_socdk.h
copy to include/configs/socfpga_soc64_common.h
index 8e6ecf4bed..35b7a21a50 100644
--- a/include/configs/socfpga_stratix10_socdk.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -1,11 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0
  *
- * Copyright (C) 2017-2018 Intel Corporation 
+ * Copyright (C) 2017-2019 Intel Corporation 
  *
  */
 
-#ifndef __CONFIG_SOCFGPA_STRATIX10_H__
-#define __CONFIG_SOCFGPA_STRATIX10_H__
+#ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
+#define __CONFIG_SOCFPGA_SOC64_COMMON_H__
 
 #include 
 #include 
@@ -205,4 +205,4 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img"
 
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */
diff --git a/include/configs/socfpga_stratix10_socdk.h 
b/include/configs/socfpga_stratix10_socdk.h
index 8e6ecf4bed..09b46ba013 100644
--- a/include/configs/socfpga_stratix10_socdk.h
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -1,208 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0
  *
- * Copyright (C) 2017-2018 Intel Corporation 
+ * Copyright (C) 2017-2019 Intel Corporation 
  *
  */
 
 #ifndef __CONFIG_SOCFGPA_STRATIX10_H__
 #define __CONFIG_SOCFGPA_STRATIX10_H__
 
-#include 
-#include 
+#include 
 
-/*
- * U-Boot general configurations
- */
-#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE
-#define CONFIG_LOADADDR0x200
-#define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
-#define CONFIG_REMAKE_ELF
-/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
-#define CPU_RELEASE_ADDR   0xFFD12210
-#define CONFIG_SYS_CACHELINE_SIZE  64
-#define CONFIG_SYS_MEM_RESERVE_SECURE  0   /* using OCRAM, not DDR */
-
-/*
- * U-Boot console configurations
- */
-#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_SYS_CBSIZE  2048
-#define CONFIG_SYS_PBSIZE  (CONFIG_SYS_CBSIZE + \
-   sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE
-
-/* Extend size of kernel image for uncompression */
-#define CONFIG_SYS_BOOTM_LEN   (32 * 1024 * 1024)
-
-/*
- * U-Boot run time memory configurations
- */
-#define CONFIG_SYS_INIT_RAM_ADDR   0xFFE0
-#define CONFIG_SYS_INIT_RAM_SIZE   0x4
-#define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_INIT_RAM_ADDR  \
-   + CONFIG_SYS_INIT_RAM_SIZE \
-   - S10_HANDOFF_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET  (CONFIG_SYS_INIT_SP_ADDR)
-#define CONFIG_SYS_MALLOC_LEN  (5 * 1024 * 1024)
-
-/*
- * U-Boot environment configurations
- */
-#define CONFIG_ENV_SIZE0x1000
-#define CONFIG_SYS_MMC_ENV_DEV 0   /* device 0 */
-#define CONFIG_ENV_OFFSET  512 /* just after the MBR */
-
-/*
- * QSPI support
- */
- #ifdef CONFIG_CADENCE_QSPI
-/* Enable it if you want to use dual-stacked mode */
-/*#define CONFIG_QSPI_RBF_ADDR 0x72*/
-
-/* Flash device info */
-
-/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
-#undef CONFIG_ENV_OFFSET
-#undef CONFIG_ENV_SIZE
-#define CONFIG_ENV_OFFSET  0x71
-#define CONFIG_ENV_SIZE(4 * 1024)
-#define CONFIG_ENV_SECT_SIZE   (4 * 1024)
-#endif /* CONFIG_ENV_IS_IN_SPI_FLASH */
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
-#endif /* CONFIG_SPL_BUILD */
-
-#ifndef __ASSEMBLY__
-unsigned int cm_get_qspi_controller_clk_hz(void);
-#define CONFIG_CQSPI_REF_CLK   cm_get_qspi_controller_clk_hz()
-#endif
-
-#endif /* CONFIG_CADENCE_QSPI */
-
-/*
- * Boot arguments passed to the boot command. The value of
- * CONFIG_BOOTARGS goes into the environment value "bootargs".
- * Do note the value will override also the chosen node in FDT blob.
- */
-#define CONFIG_BOOTARGS "earlycon"
-#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" 
\
-  "run mmcboot"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-   "bootfile=Image\0" \
-   "fdt_addr=800\0" \
-   "fdtimage=socfpga_stratix10_socdk.dtb\0" \
-

[U-Boot] [PATCH v6 07/19] arm: socfpga: Move Stratix10 and Agilex clock manager common code

2019-11-07 Thread Ley Foon Tan

Move Stratix10 and Agilex clock manager common code to new header file.

Signed-off-by: Ley Foon Tan 

---
v6:
- Move #include  to top of header file.

v5:
- Revert CLKMGR_INTOSC_HZ to 460MHz.
---
 .../include/mach/clock_manager_s10.h  | 16 +++--
 .../include/mach/clock_manager_soc64.h| 23 +++
 2 files changed, 26 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h

diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h 
b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index 13eb23569c..e710aa2f94 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -1,12 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0
  *
- * Copyright (C) 2016-2018 Intel Corporation 
+ * Copyright (C) 2016-2019 Intel Corporation 
  *
  */
 
 #ifndef_CLOCK_MANAGER_S10_
 #define_CLOCK_MANAGER_S10_
 
+#include 
+
 /* Clock speed accessors */
 unsigned long cm_get_mpu_clk_hz(void);
 unsigned long cm_get_sdram_clk_hz(void);
@@ -14,18 +16,6 @@ unsigned int cm_get_l4_sp_clk_hz(void);
 unsigned int cm_get_mmc_controller_clk_hz(void);
 unsigned int cm_get_qspi_controller_clk_hz(void);
 unsigned int cm_get_spi_controller_clk_hz(void);
-const unsigned int cm_get_osc_clk_hz(void);
-const unsigned int cm_get_f2s_per_ref_clk_hz(void);
-const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
-const unsigned int cm_get_intosc_clk_hz(void);
-const unsigned int cm_get_fpga_clk_hz(void);
-
-#define CLKMGR_EOSC1_HZ2500
-#define CLKMGR_INTOSC_HZ   46000
-#define CLKMGR_FPGA_CLK_HZ 5000
-
-/* Clock configuration accessors */
-const struct cm_config * const cm_get_default_config(void);
 
 struct cm_config {
/* main group */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h 
b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
new file mode 100644
index 00..3b4bb62ca5
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2019 Intel Corporation 
+ *
+ */
+
+#ifndef _CLOCK_MANAGER_SOC64_
+#define _CLOCK_MANAGER_SOC64_
+
+const unsigned int cm_get_osc_clk_hz(void);
+const unsigned int cm_get_f2s_per_ref_clk_hz(void);
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
+const unsigned int cm_get_intosc_clk_hz(void);
+const unsigned int cm_get_fpga_clk_hz(void);
+
+#define CLKMGR_EOSC1_HZ2500
+#define CLKMGR_INTOSC_HZ   46000
+#define CLKMGR_FPGA_CLK_HZ 5000
+
+/* Clock configuration accessors */
+const struct cm_config * const cm_get_default_config(void);
+
+#endif /* _CLOCK_MANAGER_SOC64_ */
-- 
2.19.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 15/19] board: intel: agilex: Add socdk board support for Intel Agilex SoC

2019-11-07 Thread Ley Foon Tan

Add socdk board support for Intel Agilex SoC

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 
---
 board/intel/agilex-socdk/MAINTAINERS | 7 +++
 board/intel/agilex-socdk/Makefile| 7 +++
 board/intel/agilex-socdk/socfpga.c   | 7 +++
 3 files changed, 21 insertions(+)
 create mode 100644 board/intel/agilex-socdk/MAINTAINERS
 create mode 100644 board/intel/agilex-socdk/Makefile
 create mode 100644 board/intel/agilex-socdk/socfpga.c

diff --git a/board/intel/agilex-socdk/MAINTAINERS 
b/board/intel/agilex-socdk/MAINTAINERS
new file mode 100644
index 00..b8e28f0b24
--- /dev/null
+++ b/board/intel/agilex-socdk/MAINTAINERS
@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M: Ley Foon Tan 
+M: Chee Hong Ang 
+S: Maintained
+F: board/intel/agilex-socdk/
+F: include/configs/socfpga_agilex_socdk.h
+F: configs/socfpga_agilex_defconfig
diff --git a/board/intel/agilex-socdk/Makefile 
b/board/intel/agilex-socdk/Makefile
new file mode 100644
index 00..b86223a571
--- /dev/null
+++ b/board/intel/agilex-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2019 Intel Corporation 
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y  := socfpga.o
diff --git a/board/intel/agilex-socdk/socfpga.c 
b/board/intel/agilex-socdk/socfpga.c
new file mode 100644
index 00..72a3e0836d
--- /dev/null
+++ b/board/intel/agilex-socdk/socfpga.c
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ *
+ */
+
+#include 
-- 
2.19.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 14/19] ddr: altera: agilex: Add SDRAM driver for Agilex

2019-11-07 Thread Ley Foon Tan

Add SDRAM driver for Agilex SoC.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v6:
- Add compatible "intel,sdr-ctl-agilex".

v4:
- Fixed checkpatch warnings

v3:
- Use sdmmc_soc64.*
- Change compatible string to use "intel" (intel,sdr-ctl-agilex).
- Improve error handing if DDR size mismatched.
---
 drivers/ddr/altera/Kconfig|   6 +-
 drivers/ddr/altera/Makefile   |   1 +
 drivers/ddr/altera/sdram_agilex.c | 168 ++
 drivers/ddr/altera/sdram_soc64.c  |   1 +
 drivers/ddr/altera/sdram_soc64.h  |   1 +
 5 files changed, 174 insertions(+), 3 deletions(-)
 create mode 100644 drivers/ddr/altera/sdram_agilex.c

diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
index 2b1c1be3b5..8f590dc5f6 100644
--- a/drivers/ddr/altera/Kconfig
+++ b/drivers/ddr/altera/Kconfig
@@ -1,8 +1,8 @@
 config SPL_ALTERA_SDRAM
bool "SoCFPGA DDR SDRAM driver in SPL"
depends on SPL
-   depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || 
TARGET_SOCFPGA_STRATIX10
-   select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
-   select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
+   depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || 
TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
+   select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || 
TARGET_SOCFPGA_AGILEX
+   select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || 
TARGET_SOCFPGA_AGILEX
help
  Enable DDR SDRAM controller for the SoCFPGA devices.
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index eb8da13b7d..39dfee5d5a 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -10,4 +10,5 @@ ifdef CONFIG_$(SPL_)ALTERA_SDRAM
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
 obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
+obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o
 endif
diff --git a/drivers/ddr/altera/sdram_agilex.c 
b/drivers/ddr/altera/sdram_agilex.c
new file mode 100644
index 00..cc7679a6e4
--- /dev/null
+++ b/drivers/ddr/altera/sdram_agilex.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "sdram_soc64.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int sdram_mmr_init_full(struct udevice *dev)
+{
+   struct altera_sdram_platdata *plat = dev->platdata;
+   struct altera_sdram_priv *priv = dev_get_priv(dev);
+   u32 i;
+   int ret;
+   phys_size_t hw_size;
+   bd_t bd = {0};
+
+   /* Ensure HMC clock is running */
+   if (poll_hmc_clock_status()) {
+   debug("DDR: Error as HMC clock was not running\n");
+   return -EPERM;
+   }
+
+   /* Trying 3 times to do a calibration */
+   for (i = 0; i < 3; i++) {
+   ret = wait_for_bit_le32((const void *)(plat->hmc +
+   DDRCALSTAT),
+   DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
+   false);
+   if (!ret)
+   break;
+
+   emif_reset(plat);
+   }
+
+   if (ret) {
+   puts("DDR: Error as SDRAM calibration failed\n");
+   return -EPERM;
+   }
+   debug("DDR: Calibration success\n");
+
+   /*
+* Configure the DDR IO size
+* niosreserve0: Used to indicate DDR width &
+*  bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
+*  bit[8]   = 1 if user-mode OCT is present
+*  bit[9]   = 1 if warm reset compiled into EMIF Cal Code
+*  bit[10]  = 1 if warm reset is on during generation in EMIF Cal
+* niosreserve1: IP ADCDS version encoded as 16 bit value
+*  bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
+*  3=EAP, 4-6 are reserved)
+*  bit[5:3] = Service Pack # (e.g. 1)
+*  bit[9:6] = Minor Release #
+*  bit[14:10] = Major Release #
+*/
+   /* Configure DDR IO size x16, x32 and x64 mode */
+   u32 update_value;
+
+   update_value = hmc_readl(plat, NIOSRESERVED0);
+   update_value = (update_value & 0xFF) >> 5;
+
+   /* Configure DDR data rate 0-HAlf-rate 1-Quarter-rate */
+   update_value |= (hmc_readl(plat, CTRLCFG3) & 0x4);
+   hmc_ecc_writel(plat, update_value, DDRIOCTRL);
+
+   /* Copy values MMR IOHMC dramaddrw to HMC adp DRAMADDRWIDTH */
+   hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
+
+   /* assigning the SDRAM size */
+   phys_size_t size =

[U-Boot] [PATCH v6 17/19] arm: dts: agilex: Add base dtsi and devkit dts

2019-11-07 Thread Ley Foon Tan

Add device tree files for Agilex SoC platform.

Based on Linux Commit ID4b36daf9ada30.

Signed-off-by: Ley Foon Tan 

---
v6:
- Use new macro names from agilex-clock.h.

v5:
- Add CCU DT node.

v4:
- Add u-boot,dm-pre-reloc to sysmgr node.

v3:
- Fixed bank 1 memory alias base address to 0x28000.
- Rename STRATIX10_*_CLK to SOCFPGA_SOC64_*_CLK.
- Include socfpga-soc64-clock.h
- Change to "intel,sdr-ctl-agilex" for SDRAM node.

v2:
- Add clock property to device node.
- Change memory size to 8GB
- Enable i2c1

Signed-off-by: Ley Foon Tan 
---
 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/socfpga_agilex.dtsi  | 500 ++
 arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi |  79 +++
 arch/arm/dts/socfpga_agilex_socdk.dts | 138 +
 4 files changed, 718 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_agilex.dtsi
 create mode 100644 arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_agilex_socdk.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 47978e7685..d90ad835a4 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -319,6 +319,7 @@ dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=  \
+   socfpga_agilex_socdk.dtb\
socfpga_arria5_socdk.dtb\
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_mcvevk.dtb \
diff --git a/arch/arm/dts/socfpga_agilex.dtsi b/arch/arm/dts/socfpga_agilex.dtsi
new file mode 100644
index 00..9e578a0108
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex.dtsi
@@ -0,0 +1,500 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation
+ */
+
+/dts-v1/;
+#include 
+#include 
+#include 
+
+/ {
+   compatible = "intel,socfpga-agilex";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   compatible = "arm,cortex-a53";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x0>;
+   };
+
+   cpu1: cpu@1 {
+   compatible = "arm,cortex-a53";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x1>;
+   };
+
+   cpu2: cpu@2 {
+   compatible = "arm,cortex-a53";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x2>;
+   };
+
+   cpu3: cpu@3 {
+   compatible = "arm,cortex-a53";
+   device_type = "cpu";
+   enable-method = "psci";
+   reg = <0x3>;
+   };
+   };
+
+   pmu {
+   compatible = "arm,armv8-pmuv3";
+   interrupts = <0 120 8>,
+<0 121 8>,
+<0 122 8>,
+<0 123 8>;
+   interrupt-affinity = <>,
+<>,
+<>,
+<>;
+   interrupt-parent = <>;
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   intc: intc@fffc1000 {
+   compatible = "arm,gic-400", "arm,cortex-a15-gic";
+   #interrupt-cells = <3>;
+   interrupt-controller;
+   reg = <0x0 0xfffc1000 0x0 0x1000>,
+ <0x0 0xfffc2000 0x0 0x2000>,
+ <0x0 0xfffc4000 0x0 0x2000>,
+ <0x0 0xfffc6000 0x0 0x2000>;
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "simple-bus";
+   device_type = "soc";
+   interrupt-parent = <>;
+   ranges = <0 0 0 0x>;
+
+   ccu: cache-controller@f700 {
+   compatible = "arteris,ncore-ccu";
+   reg = <0xf700 0x100900>;
+   };
+
+   clkmgr: clock-controller@ffd1 {
+   compatible = "intel,agilex-clkmgr";
+   reg = <0xffd1 0x1000>;
+   #clock-cells = <1>;
+   };
+
+   gmac0: ethernet@ff80 {
+   compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", 
"snps,dwmac";
+   reg = <0xff80 0x2000>;
+   interrupts = <0 90 4>;
+   interrupt-names = "macirq";
+   mac-address = [00 00 00 00 00 00];

[U-Boot] [PATCH v6 05/19] arm: socfpga: Move Stratix10 and Agilex system manager common code

2019-11-07 Thread Ley Foon Tan

Move Stratix10 and Agilex system manager common code to
system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v5:
- Remove system_manager_s10.h and use system_manager_soc64.h.

v4:
- Change prefix from SYSMGR_S10* to SYSMGR_SOC64*.

v3:
- Change filename to system_manager_soc64.h
- Move to use defines instead of struct.

v2:
- Move common defines for Stratix 10 and Agilex to 
system_manager_s10_agilex_common.h
---
 arch/arm/mach-socfpga/clock_manager_s10.c |   3 +-
 arch/arm/mach-socfpga/firewall.c  |   4 +-
 .../include/mach/system_manager.h |   2 +-
 .../include/mach/system_manager_s10.h | 124 --
 .../include/mach/system_manager_soc64.h   | 123 +
 arch/arm/mach-socfpga/mailbox_s10.c   |   2 +-
 arch/arm/mach-socfpga/misc_s10.c  |   2 +-
 arch/arm/mach-socfpga/reset_manager_s10.c |  15 ++-
 arch/arm/mach-socfpga/spl_s10.c   |   2 +-
 arch/arm/mach-socfpga/system_manager_s10.c|  26 ++--
 arch/arm/mach-socfpga/wrap_pll_config_s10.c   |  10 +-
 drivers/ddr/altera/sdram_s10.c|   2 +-
 12 files changed, 159 insertions(+), 156 deletions(-)
 delete mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_soc64.h

diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c 
b/arch/arm/mach-socfpga/clock_manager_s10.c
index 5edeab1792..05e42127b5 100644
--- a/arch/arm/mach-socfpga/clock_manager_s10.c
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -385,7 +385,8 @@ unsigned int cm_get_l4_sp_clk_hz(void)
 
 unsigned int cm_get_qspi_controller_clk_hz(void)
 {
-   return readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_BOOT_SCRATCH_COLD0);
+   return readl(socfpga_get_sysmgr_addr() +
+SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
 }
 
 unsigned int cm_get_spi_controller_clk_hz(void)
diff --git a/arch/arm/mach-socfpga/firewall.c b/arch/arm/mach-socfpga/firewall.c
index 9a4111a931..69229dc651 100644
--- a/arch/arm/mach-socfpga/firewall.c
+++ b/arch/arm/mach-socfpga/firewall.c
@@ -101,7 +101,7 @@ void firewall_setup(void)
 
/* enable non-secure interface to DMA330 DMA and peripherals */
writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS,
-  socfpga_get_sysmgr_addr() + SYSMGR_S10_DMA);
+  socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA);
writel(SYSMGR_DMAPERIPH_ALL_NS,
-  socfpga_get_sysmgr_addr() + SYSMGR_S10_DMA_PERIPH);
+  socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA_PERIPH);
 }
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 7f05029a67..242ef2e8be 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -9,7 +9,7 @@
 phys_addr_t socfpga_get_sysmgr_addr(void);
 
 #if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
-#include 
+#include 
 #else
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUXBIT(0)
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIOBIT(1)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h 
b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
deleted file mode 100644
index 07dd19e06d..00
--- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2016-2018 Intel Corporation 
- *
- */
-
-#ifndef_SYSTEM_MANAGER_S10_
-#define_SYSTEM_MANAGER_S10_
-
-void sysmgr_pinmux_init(void);
-void populate_sysmgr_fpgaintf_module(void);
-void populate_sysmgr_pinmux(void);
-void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
-
-#define SYSMGR_S10_WDDBG   0x08
-#define SYSMGR_S10_DMA 0x20
-#define SYSMGR_S10_DMA_PERIPH  0x24
-#define SYSMGR_S10_SDMMC   0x28
-#define SYSMGR_S10_SDMMC_L3MASTER  0x2c
-#define SYSMGR_S10_EMAC_GLOBAL 0x40
-#define SYSMGR_S10_EMAC0   0x44
-#define SYSMGR_S10_EMAC1   0x48
-#define SYSMGR_S10_EMAC2   0x4c
-#define SYSMGR_S10_EMAC0_ACE   0x50
-#define SYSMGR_S10_EMAC1_ACE   0x54
-#define SYSMGR_S10_EMAC2_ACE   0x58
-#define SYSMGR_S10_NAND_AXUSER 0x5c
-#define SYSMGR_S10_FPGAINTF_EN10x68
-#define SYSMGR_S10_FPGAINTF_EN20x6c
-#define SYSMGR_S10_FPGAINTF_EN30x70
-#define SYSMGR_S10_DMA_L3MASTER0x74

[U-Boot] [PATCH v6 02/19] arm: socfpga: Move firewall code to firewall file

2019-11-07 Thread Ley Foon Tan

Move firewall related code to new firewall.c, to share
code in Stratix 10 and Agilex.

SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC
to allow DMA transfer to OCRAM.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v4:
- Move SYSMGR_DMA* to firewall.c

v3:
- Move SOCFPGA_FIREWALL_TCU to firewall.c
---
 arch/arm/mach-socfpga/Makefile|   1 +
 .../mach-socfpga/{spl_s10.c => firewall.c}| 120 +++---
 .../mach/{firewall_s10.h => firewall.h}   |  10 +-
 arch/arm/mach-socfpga/spl_s10.c   |  93 +-
 drivers/ddr/altera/sdram_s10.c|   2 +-
 5 files changed, 26 insertions(+), 200 deletions(-)
 copy arch/arm/mach-socfpga/{spl_s10.c => firewall.c} (56%)
 rename arch/arm/mach-socfpga/include/mach/{firewall_s10.h => firewall.h} (94%)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index fc1181cb27..dab34d0ef2 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -51,6 +51,7 @@ ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
 obj-y  += spl_a10.o
 endif
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y  += firewall.o
 obj-y  += spl_s10.o
 endif
 endif
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/firewall.c
similarity index 56%
copy from arch/arm/mach-socfpga/spl_s10.c
copy to arch/arm/mach-socfpga/firewall.c
index 028c5a177d..9a4111a931 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/firewall.c
@@ -1,45 +1,15 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2016-2018 Intel Corporation 
+ * Copyright (C) 2016-2019 Intel Corporation 
  *
  */
 
 #include 
-#include 
-#include 
 #include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
+#include 
 #include 
-#include 
-#include 
 
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 spl_boot_device(void)
-{
-   /* TODO: Get from SDM or handoff */
-   return BOOT_DEVICE_MMC1;
-}
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_boot_mode(const u32 boot_device)
-{
-#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
-   return MMCSD_MODE_FS;
-#else
-   return MMCSD_MODE_RAW;
-#endif
-}
-#endif
-
-void spl_disable_firewall_l4_per(void)
+static void firewall_l4_per_disable(void)
 {
const struct socfpga_firwall_l4_per *firwall_l4_per_base =
(struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
@@ -79,7 +49,7 @@ void spl_disable_firewall_l4_per(void)
writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
 }
 
-void spl_disable_firewall_l4_sys(void)
+static void firewall_l4_sys_disable(void)
 {
const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
(struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
@@ -113,83 +83,25 @@ void spl_disable_firewall_l4_sys(void)
writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
 }
 
-void board_init_f(ulong dummy)
+static void firewall_bridge_disable(void)
 {
-   const struct cm_config *cm_default_cfg = cm_get_default_config();
-   int ret;
-
-   ret = spl_early_init();
-   if (ret)
-   hang();
-
-   socfpga_get_managers_addr();
-
-#ifdef CONFIG_HW_WATCHDOG
-   /* Ensure watchdog is paused when debugging is happening */
-   writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
-  socfpga_get_sysmgr_addr() + SYSMGR_S10_WDDBG);
-
-   /* Enable watchdog before initializing the HW */
-   socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
-   socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
-   hw_watchdog_init();
-#endif
-
-   /* ensure all processors are not released prior Linux boot */
-   writeq(0, CPU_RELEASE_ADDR);
-
-   socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
-   timer_init();
-
-   sysmgr_pinmux_init();
-
-   /* configuring the HPS clocks */
-   cm_basic_init(cm_default_cfg);
+   /* disable lwsocf2fpga and soc2fpga bridge security */
+   writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);
+   writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);
+}
 
-#ifdef CONFIG_DEBUG_UART
-   socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
-   debug_uart_init();
-#endif
+void firewall_setup(void)
+{
+   firewall_l4_per_disable();
+   firewall_l4_sys_disable();
+   firewall_bridge_disable();
 
-   preloader_console_init();
-   cm_print_clock_quick_summary();
+   /* disable SMMU security */
+   writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
 
/* enable non-secure interface to DMA330 DMA and peripherals */
writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS,
   socfpga_get_sysmgr_addr() + SYSMGR_S10_DMA);
writel(SYSMGR_DMAPERIPH_ALL_NS,
   socfpga_get_sysmgr_addr() + SYSMGR_S10_DMA_PERIPH);
-
-   spl_disable_firewall_l4_per();
-
-   spl_disable_firewall_l4_sys();
-
-   /* disable lwsocf2fpga and soc2fpga bridge security */
-

[U-Boot] [PATCH v6 10/19] arm: socfpga: agilex: Add clock wrapper functions

2019-11-07 Thread Ley Foon Tan

Add clock wrapper functions call to clock DM functions to get clock
frequency and used in cm_print_clock_quick_summary().

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v6:
- Use new macro names from agilex-clock.h.

v4:
- Change to use SYSMGR_SOC64* prefix.

v3:
- Improved commit message.
- Rename STRATIX10_* to SOCFPGA_SOC64_*
- Include clock_manager_soc64.h and clk-agilex.h.

v2:
- Get clocks from clock DM.
---
 arch/arm/mach-socfpga/Makefile|  4 +
 arch/arm/mach-socfpga/clock_manager_agilex.c  | 85 +++
 .../mach-socfpga/include/mach/clock_manager.h |  2 +
 .../include/mach/clock_manager_agilex.h   | 14 +++
 4 files changed, 105 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index dab34d0ef2..a403b46b47 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -39,6 +39,10 @@ obj-y+= wrap_pinmux_config_s10.o
 obj-y  += wrap_pll_config_s10.o
 endif
 
+ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+obj-y  += clock_manager_agilex.o
+endif
+
 ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
 obj-y  += spl_gen5.o
diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c 
b/arch/arm/mach-socfpga/clock_manager_agilex.c
new file mode 100644
index 00..791066d25b
--- /dev/null
+++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong cm_get_rate_dm(u32 id)
+{
+   struct udevice *dev;
+   struct clk clk;
+   ulong rate;
+   int ret;
+
+   ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(socfpga_agilex_clk),
+ );
+   if (ret)
+   return 0;
+
+   clk.id = id;
+   ret = clk_request(dev, );
+   if (ret < 0)
+   return 0;
+
+   rate = clk_get_rate();
+
+   clk_free();
+
+   if ((rate == (unsigned long)-ENOSYS) ||
+   (rate == (unsigned long)-ENXIO) ||
+   (rate == (unsigned long)-EIO)) {
+   debug("%s id %u: clk_get_rate err: %ld\n",
+ __func__, id, rate);
+   return 0;
+   }
+
+   return rate;
+}
+
+static u32 cm_get_rate_dm_khz(u32 id)
+{
+   return cm_get_rate_dm(id) / 1000;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+   return cm_get_rate_dm(AGILEX_MPU_CLK);
+}
+
+unsigned int cm_get_l4_sys_free_clk_hz(void)
+{
+   return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
+}
+
+u32 cm_get_qspi_controller_clk_hz(void)
+{
+   return readl(socfpga_get_sysmgr_addr() +
+SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+}
+
+void cm_print_clock_quick_summary(void)
+{
+   printf("MPU   %10d kHz\n",
+  cm_get_rate_dm_khz(AGILEX_MPU_CLK));
+   printf("L4 Main %8d kHz\n",
+  cm_get_rate_dm_khz(AGILEX_L4_MAIN_CLK));
+   printf("L4 sys free %8d kHz\n",
+  cm_get_rate_dm_khz(AGILEX_L4_SYS_FREE_CLK));
+   printf("L4 MP   %8d kHz\n",
+  cm_get_rate_dm_khz(AGILEX_L4_MP_CLK));
+   printf("L4 SP   %8d kHz\n",
+  cm_get_rate_dm_khz(AGILEX_L4_SP_CLK));
+   printf("SDMMC   %8d kHz\n",
+  cm_get_rate_dm_khz(AGILEX_SDMMC_CLK));
+}
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h 
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 6de7caef19..c6830582a5 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -20,6 +20,8 @@ void cm_print_clock_quick_summary(void);
 #include 
 #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
 #include 
+#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
+#include 
 #endif
 
 #endif /* _CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h 
b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
new file mode 100644
index 00..386e82a4e3
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+#ifndef _CLOCK_MANAGER_AGILEX_
+#define _CLOCK_MANAGER_AGILEX_
+
+unsigned long cm_get_mpu_clk_hz(void);
+
+#include 
+#include "../../../../../drivers/clk/altera/clk-agilex.h"
+
+#endif /* _CLOCK_MANAGER_AGILEX_ */
-- 
2.19.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 11/19] cache: Add Arteris Ncore cache coherent unit driver

2019-11-07 Thread Ley Foon Tan

Add Cache Coherency Unit (CCU) driver.
CCU is to ensures consistency of shared data between multi masters
in the system.

Driver initializes CCU's directories and coherency agent
interfaces in CCU IP.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v5:
- Move CCU driver to DM.
---
 drivers/cache/Kconfig   |   8 ++
 drivers/cache/Makefile  |   1 +
 drivers/cache/cache-ncore.c | 164 
 3 files changed, 173 insertions(+)
 create mode 100644 drivers/cache/cache-ncore.c

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 629039e7a8..1e452ad6d9 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -31,4 +31,12 @@ config V5L2_CACHE
  It will configure tag and data ram timing control from the
  device tree and enable L2 cache.
 
+config NCORE_CACHE
+   bool "Arteris Ncore cache coherent unit driver"
+   select CACHE
+   help
+ This driver is for the Arteris Ncore cache coherent unit (CCU)
+ controller. The driver initializes cache directories and coherent
+ agent interfaces.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index c1f766cfca..6be895a5f7 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -2,4 +2,5 @@
 obj-$(CONFIG_$(SPL_)CACHE) += cache-uclass.o
 obj-$(CONFIG_SANDBOX) += sandbox_cache.o
 obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
+obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
 obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
diff --git a/drivers/cache/cache-ncore.c b/drivers/cache/cache-ncore.c
new file mode 100644
index 00..e3aca36071
--- /dev/null
+++ b/drivers/cache/cache-ncore.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ *
+ */
+#include 
+#include 
+
+#include 
+
+/* Directory */
+#define DIRUSFER   0x80010
+#define DIRUCASER0 0x80040
+#define DIRUSFMCR  0x80080
+#define DIRUSFMAR  0x80084
+
+#define DIRUSFMCR_SFID_SHIFT   16
+
+/* Coherent cache agent interface */
+#define CAIUIDR0x00ffc
+
+#define CAIUIDR_CA_GET(v)  (((v) & 0x8000) >> 15)
+#define CAIUIDR_TYPE_GET(v)(((v) & 0x000f) >> 16)
+#define CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT   0
+#define CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT   1
+
+/* Coherent subsystem */
+#define CSADSER0   0xff040
+#define CSUIDR 0x8
+#define CSIDR  0xc
+
+#define CSUIDR_NUMCAIUS_GET(v) (((v) & 0x007f) >> 0)
+#define CSUIDR_NUMDIRUS_GET(v) (((v) & 0x003f) >> 16)
+#define CSUIDR_NUMCMIUS_GET(v) (((v) & 0x3f00) >> 24)
+
+#define CSIDR_NUMSFS_GET(v)(((v) & 0x007c) >> 18)
+
+#define DIR_REG_SZ 0x1000
+#define CAIU_REG_SZ0x1000
+
+#define CCU_DIR_REG_ADDR(base, reg, dir)   \
+   ((base) + (reg) + ((dir) * DIR_REG_SZ))
+
+/* OCRAM firewall register */
+#define OCRAM_FW_010x100204
+#define OCRAM_SECURE_REGIONS   4
+
+#define OCRAM_PRIVILEGED_MASK  BIT(29)
+#define OCRAM_SECURE_MASK  BIT(30)
+
+static void ncore_ccu_init_dirs(void __iomem *base)
+{
+   ulong i, f;
+   int ret;
+   u32 num_of_dirs;
+   u32 num_of_snoop_filters;
+   u32 reg;
+
+   num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(base + CSUIDR));
+   num_of_snoop_filters =
+   CSIDR_NUMSFS_GET(readl(base + CSIDR)) + 1;
+
+   /* Initialize each snoop filter in each directory */
+   for (f = 0; f < num_of_snoop_filters; f++) {
+   reg = f << DIRUSFMCR_SFID_SHIFT;
+   for (i = 0; i < num_of_dirs; i++) {
+   /* Initialize all entries */
+   writel(reg, CCU_DIR_REG_ADDR(base, DIRUSFMCR, i));
+
+   /* Poll snoop filter maintenance operation active
+* bit become 0.
+*/
+   ret = wait_for_bit_le32((const void *)
+   CCU_DIR_REG_ADDR(base,
+DIRUSFMAR, i),
+   BIT(0), false, 1000, false);
+   if (ret) {
+   puts("CCU: Directory initialization failed!\n");
+   hang();
+   }
+
+   /* Enable snoop filter, a bit per snoop filter */
+   setbits_le32((ulong)CCU_DIR_REG_ADDR(base, DIRUSFER, i),
+BIT(f));
+   }
+   }
+}
+
+static void ncore_ccu_init_coh_agent(void __iomem *base)
+{
+   u32 num_of_coh_agent_intf;
+   u32 num_of_dirs;
+   u32 reg;
+   u32 type;
+   u32 i, dir;
+
+   num_of_coh_agent_intf =
+   CSUIDR_NUMCAIUS_GET(readl(base + CSUIDR));
+   num_of_dirs =

[U-Boot] [PATCH v6 16/19] arm: socfpga: agilex: Add SPL for Agilex SoC

2019-11-07 Thread Ley Foon Tan

Add SPL support for Agilex SoC.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v5:
- Probe CCU driver with DM method.

v4:
- Move spl_early_init() to entry of board_init_f
- Add socfpga_get_manager_addr().
- Remove SYSMGR_DMA and SYSMGR_DMA_PERIPH, already set in firewall_setup().

v2:
- Change clock driver probing to DM.
- Remove unused OSC1TIMER0 reset
- Remove debug_uart_init(). UART depends on clock driver setup, no point to call
  debug_uart_init() after spl_early_init() and clock driver initialization.
---
 arch/arm/mach-socfpga/Makefile |  3 +
 arch/arm/mach-socfpga/spl_agilex.c | 98 ++
 2 files changed, 101 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/spl_agilex.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index a403b46b47..81b6ffc675 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -58,6 +58,9 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y  += firewall.o
 obj-y  += spl_s10.o
 endif
+ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+obj-y  += spl_agilex.o
+endif
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/spl_agilex.c 
b/arch/arm/mach-socfpga/spl_agilex.c
new file mode 100644
index 00..c745d64114
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_agilex.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+   return BOOT_DEVICE_MMC1;
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(const u32 boot_device)
+{
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
+   return MMCSD_MODE_FS;
+#else
+   return MMCSD_MODE_RAW;
+#endif
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+   int ret;
+   struct udevice *dev;
+
+   ret = spl_early_init();
+   if (ret)
+   hang();
+
+   socfpga_get_managers_addr();
+
+#ifdef CONFIG_HW_WATCHDOG
+   /* Ensure watchdog is paused when debugging is happening */
+   writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
+  socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
+
+   /* Enable watchdog before initializing the HW */
+   socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
+   socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
+   hw_watchdog_init();
+#endif
+
+   /* ensure all processors are not released prior Linux boot */
+   writeq(0, CPU_RELEASE_ADDR);
+
+   timer_init();
+
+   sysmgr_pinmux_init();
+
+   ret = uclass_get_device(UCLASS_CLK, 0, );
+   if (ret) {
+   debug("Clock init failed: %d\n", ret);
+   hang();
+   }
+
+   preloader_console_init();
+   cm_print_clock_quick_summary();
+
+   firewall_setup();
+   ret = uclass_get_device(UCLASS_CACHE, 0, );
+   if (ret) {
+   debug("CCU init failed: %d\n", ret);
+   hang();
+   }
+
+#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
+   ret = uclass_get_device(UCLASS_RAM, 0, );
+   if (ret) {
+   debug("DRAM init failed: %d\n", ret);
+   hang();
+   }
+#endif
+
+   mbox_init();
+
+#ifdef CONFIG_CADENCE_QSPI
+   mbox_qspi_open();
+#endif
+}
-- 
2.19.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 03/19] arm: socfpga: Move Stratix10 and Agilex reset manager common code

2019-11-07 Thread Ley Foon Tan

Move Stratix10 and Agilex reset manager common code to
reset_manager_soc64.h. Changed macros to RSTMGR_SOC64_*.

Remove unused RSTMGR_XXX defines.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v5:
- Remove reset_manager_s10.h and use reset_manager_soc64.h directly.

v4:
- Change prefix from RSTMGR_S10* to RSTMGR_SOC64*.

v3:
- Add new reset_manager_soc64.h
- Convert to use defines instead of struct.
---
 .../mach-socfpga/include/mach/reset_manager.h |  2 +-
 .../include/mach/reset_manager_s10.h  | 95 ---
 .../include/mach/reset_manager_soc64.h| 38 
 arch/arm/mach-socfpga/reset_manager_s10.c | 20 ++--
 4 files changed, 49 insertions(+), 106 deletions(-)
 delete mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 96052d94b4..af57ab0a32 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -44,7 +44,7 @@ void socfpga_per_reset_all(void);
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #include 
 #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
-#include 
+#include 
 #endif
 
 #endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
deleted file mode 100644
index 611f7efa6e..00
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2016-2018 Intel Corporation 
- *
- */
-
-#ifndef_RESET_MANAGER_S10_
-#define_RESET_MANAGER_S10_
-
-void reset_cpu(ulong addr);
-int cpu_has_been_warmreset(void);
-
-void socfpga_bridges_reset(int enable);
-
-void socfpga_per_reset(u32 reset, int set);
-void socfpga_per_reset_all(void);
-
-#define RSTMGR_S10_STATUS  0x00
-#define RSTMGR_S10_MPUMODRST   0x20
-#define RSTMGR_S10_PER0MODRST  0x24
-#define RSTMGR_S10_PER1MODRST  0x28
-#define RSTMGR_S10_BRGMODRST   0x2c
-
-#define RSTMGR_MPUMODRST_CORE0 0
-#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
-#define RSTMGR_BRGMODRST_DDRSCH_MASK   0X0040
-#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x0004
-
-/* Watchdogs and MPU warm reset mask */
-#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00
-
-/*
- * Define a reset identifier, from which a permodrst bank ID
- * and reset ID can be extracted using the subsequent macros
- * RSTMGR_RESET() and RSTMGR_BANK().
- */
-#define RSTMGR_BANK_OFFSET 8
-#define RSTMGR_BANK_MASK   0x7
-#define RSTMGR_RESET_OFFSET0
-#define RSTMGR_RESET_MASK  0x1f
-#define RSTMGR_DEFINE(_bank, _offset)  \
-   ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
-
-/* Extract reset ID from the reset identifier. */
-#define RSTMGR_RESET(_reset)   \
-   (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
-
-/* Extract bank ID from the reset identifier. */
-#define RSTMGR_BANK(_reset)\
-   (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
-
-/*
- * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
- * 0 ... mpumodrst
- * 1 ... per0modrst
- * 2 ... per1modrst
- * 3 ... brgmodrst
- */
-#define RSTMGR_EMAC0   RSTMGR_DEFINE(1, 0)
-#define RSTMGR_EMAC1   RSTMGR_DEFINE(1, 1)
-#define RSTMGR_EMAC2   RSTMGR_DEFINE(1, 2)
-#define RSTMGR_USB0RSTMGR_DEFINE(1, 3)
-#define RSTMGR_USB1RSTMGR_DEFINE(1, 4)
-#define RSTMGR_NANDRSTMGR_DEFINE(1, 5)
-#define RSTMGR_SDMMC   RSTMGR_DEFINE(1, 7)
-#define RSTMGR_EMAC0_OCP   RSTMGR_DEFINE(1, 8)
-#define RSTMGR_EMAC1_OCP   RSTMGR_DEFINE(1, 9)
-#define RSTMGR_EMAC2_OCP   RSTMGR_DEFINE(1, 10)
-#define RSTMGR_USB0_OCPRSTMGR_DEFINE(1, 11)
-#define RSTMGR_USB1_OCPRSTMGR_DEFINE(1, 12)
-#define RSTMGR_NAND_OCPRSTMGR_DEFINE(1, 13)
-#define RSTMGR_SDMMC_OCP   RSTMGR_DEFINE(1, 15)
-#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
-#define RSTMGR_SPIM0   RSTMGR_DEFINE(1, 17)
-#define RSTMGR_SPIM1   RSTMGR_DEFINE(1, 18)
-#define RSTMGR_L4WD0   RSTMGR_DEFINE(2, 0)
-#define RSTMGR_L4WD1   RSTMGR_DEFINE(2, 1)
-#define RSTMGR_L4WD2   RSTMGR_DEFINE(2, 2)
-#define RSTMGR_L4WD3   RSTMGR_DEFINE(2, 3)
-#define RSTMGR_OSC1TIMER0  RSTMGR_DEFINE(2, 4)
-#define RSTMGR_I2C0RSTMGR_DEFINE(2, 8)
-#define RSTMGR_I2C1RSTMGR_DEFINE(2, 9)
-#define RSTMGR_I2C2RSTMGR_DEFINE(2, 10)
-#define RSTMGR_I2C3RSTMGR_DEFINE(2, 11)
-#define RSTMGR_I2C4RSTMGR_DEFINE(2, 12)
-#define RSTMGR_UART0   RSTMGR_DEFINE(2, 16)
-#define RSTMGR_UART1   RSTMGR_DEFINE(2, 17)
-#define RSTMGR_GPIO0

[U-Boot] [PATCH v6 06/19] arm: socfpga: agilex: Add system manager support

2019-11-07 Thread Ley Foon Tan

Add system manager support for Agilex.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v5:
- Remove system_manager_agilex.h and use system_manager_soc64.h directly.

v3:
- Change include filename to system_manager_soc64.h.
- Move to use defines instead of struct.

v2:
- Include system_manager_s10_agilex_common.h in system_manager_agilex.h
---
 arch/arm/mach-socfpga/include/mach/system_manager.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 242ef2e8be..6de0a08131 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -8,7 +8,8 @@
 
 phys_addr_t socfpga_get_sysmgr_addr(void);
 
-#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+   defined(CONFIG_TARGET_SOCFPGA_AGILEX)
 #include 
 #else
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUXBIT(0)
-- 
2.19.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 04/19] arm: socfpga: agilex: Add reset manager support

2019-11-07 Thread Ley Foon Tan

Add reset manager support for Agilex.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v5:
- Remove reset_reset_manager_agilex.h and use reset_manager_soc64.h.

v3:
- Add reset_manager_soc64.h
- Convert to use defines instead of struct.
---
 arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index af57ab0a32..7844ad14cb 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -43,7 +43,8 @@ void socfpga_per_reset_all(void);
 #include 
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #include 
-#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+   defined(CONFIG_TARGET_SOCFPGA_AGILEX)
 #include 
 #endif
 
-- 
2.19.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 00/19] Add Intel Agilex SoC support

2019-11-07 Thread Ley Foon Tan

This is 6th version of patchset to add Intel Agilex SoC[1] support.

Most of changes are related to use agilex-clock.h from Linux instead of
using stratix10-clock.h and rebase on top of patchset in [2].
Detail changelog can find in commit message.

This patchset needs to apply after patchset in [2] for manager driver
struct to defines conversion and [3] for enable cache driver build in SPL.

Patch status:
No change: Patch 1, 2, 3, 4, 5, 6, 11, 15, 16
Have changes: Patch 7, 8, 9, 10, 13, 14, 17, 19
New: Patch 18

Intel Agilex SoC is with a 64-bit quad core ARM Cortex-A53 MPCore
hard processor system (HPS). New IPs in Agilex are CCU, clock manager and SDRAM,
other IPs have minor changes compared to Stratix 10.

Intel Agilex HPS TRM:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/agilex/mnl-1100.pdf

v5->v6:
---
- Patch 7: Move #include  to top of header file.
- Patch 8: Remove unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ.
- Patch 9, 10, 17: Use agilex-clock.h from Linux instead of using 
stratix10-clock.h.
- Patch 13: Remove compatible "intel,sdr-ctl-agilex" from this patch.
- Patch 14: Add compatible "intel,sdr-ctl-agilex".
- Patch 19: Include socfpga_soc64_common.h.

History:
-
[v1]: https://patchwork.ozlabs.org/cover/1097830/
[v2]: https://patchwork.ozlabs.org/cover/1127440/
[v3]: https://patchwork.ozlabs.org/cover/1149863/
[v4]: https://patchwork.ozlabs.org/cover/1161483/
[v5]: https://patchwork.ozlabs.org/cover/1175076/

[1]: 
https://www.intel.com/content/www/us/en/products/programmable/fpga/agilex.html
[2]: https://patchwork.ozlabs.org/cover/1191562/ ("arm: socfpga: Convert 
drivers from struct to defines")
[3]: https://patchwork.ozlabs.org/patch/1191569/ ("spl: Allow cache drivers to 
be used in SPL")

Ley Foon Tan (19):
  arm: socfpga: agilex: Add base address for Intel Agilex SoC
  arm: socfpga: Move firewall code to firewall file
  arm: socfpga: Move Stratix10 and Agilex reset manager common code
  arm: socfpga: agilex: Add reset manager support
  arm: socfpga: Move Stratix10 and Agilex system manager common code
  arm: socfpga: agilex: Add system manager support
  arm: socfpga: Move Stratix10 and Agilex clock manager common code
  arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz
  clk: agilex: Add clock driver for Agilex
  arm: socfpga: agilex: Add clock wrapper functions
  cache: Add Arteris Ncore cache coherent unit driver
  arm: agilex: Add clock handoff offset for Agilex
  ddr: altera: Restructure Stratix 10 SDRAM driver
  ddr: altera: agilex: Add SDRAM driver for Agilex
  board: intel: agilex: Add socdk board support for Intel Agilex SoC
  arm: socfpga: agilex: Add SPL for Agilex SoC
  arm: dts: agilex: Add base dtsi and devkit dts
  configs: socfpga: Move Stratix10 and Agilex common CONFIGs
  arm: socfpga: agilex: Enable Agilex SoC build

 arch/arm/Kconfig  |   4 +-
 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/socfpga_agilex.dtsi  | 500 +++
 arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi |  79 +++
 arch/arm/dts/socfpga_agilex_socdk.dts | 138 +
 arch/arm/mach-socfpga/Kconfig |  16 +
 arch/arm/mach-socfpga/Makefile|  17 +
 arch/arm/mach-socfpga/clock_manager_agilex.c  |  85 +++
 arch/arm/mach-socfpga/clock_manager_s10.c |   3 +-
 .../mach-socfpga/{spl_s10.c => firewall.c}| 122 +---
 .../mach-socfpga/include/mach/base_addr_s10.h |   4 +
 .../mach-socfpga/include/mach/clock_manager.h |   2 +
 .../include/mach/clock_manager_agilex.h   |  14 +
 .../include/mach/clock_manager_s10.h  |  16 +-
 .../include/mach/clock_manager_soc64.h|  21 +
 .../mach/{firewall_s10.h => firewall.h}   |  10 +-
 .../mach-socfpga/include/mach/handoff_s10.h   |   9 +-
 .../mach-socfpga/include/mach/reset_manager.h |   5 +-
 .../include/mach/reset_manager_s10.h  |  95 ---
 .../include/mach/reset_manager_soc64.h|  38 ++
 .../include/mach/system_manager.h |   5 +-
 .../include/mach/system_manager_s10.h | 124 
 .../include/mach/system_manager_soc64.h   | 123 
 arch/arm/mach-socfpga/mailbox_s10.c   |   2 +-
 arch/arm/mach-socfpga/misc.c  |   5 +
 arch/arm/mach-socfpga/misc_s10.c  |   2 +-
 arch/arm/mach-socfpga/reset_manager_s10.c |  35 +-
 arch/arm/mach-socfpga/spl_agilex.c|  98 +++
 arch/arm/mach-socfpga/spl_s10.c   |  95 +--
 arch/arm/mach-socfpga/system_manager_s10.c|  26 +-
 arch/arm/mach-socfpga/wrap_pll_config_s10.c   |  15 +-
 board/intel/agilex-socdk/MAINTAINERS  |   7 +
 board/intel/agilex-socdk/Makefile |   7 +
 board/intel/agilex-socdk/socfpga.c|   7 +
 configs/socfpga_agilex_defconfig  |  58 ++
 drivers/cache/Kconfig |   8 +
 drivers/cache/Makefile|   1 +
 drivers/cache/cache-ncore.c   | 164 +

[U-Boot] [PATCH v6 01/19] arm: socfpga: agilex: Add base address for Intel Agilex SoC

2019-11-07 Thread Ley Foon Tan

Add base address for Intel Agilex SoC.

Reuse base_addr_s10.h for Agilex, only one base address is
different from S10.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v2:
- Reuse base_addr_s10.h and add #ifdef Agilex for SOCFPGA_FW_MPU_DDR_SCR_ADDRESS
---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
index 1f549d7e70..d3eca65e97 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -10,7 +10,11 @@
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS  0xf8000400
 #define SOCFPGA_HMC_MMR_IO48_ADDRESS   0xf801
 #define SOCFPGA_SDR_ADDRESS0xf8011000
+#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200
+#else
 #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100
+#endif
 #define SOCFPGA_SMMU_ADDRESS   0xfa00
 #define SOCFPGA_MAILBOX_ADDRESS0xffa3
 #define SOCFPGA_UART0_ADDRESS  0xffc02000
-- 
2.19.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] USB doesn't work on Rockpro64 in u-boot

2019-11-07 Thread Vasily Khoruzhick

I checked voltage on regulator enable pin and it's 1.5v in u-boot (and it's
not enough to enable regulator!) and in linux it's 3v. That's why USB
ports have no power in u-boot.

Looks like u-boot doesn't switch GPIO voltage from 1.8v to 3.3v. Any
ideas how to fix this?


On Wed, Nov 6, 2019 at 11:28 PM Vasily Khoruzhick  wrote:
>
> On Wed, Nov 6, 2019 at 7:48 PM Vasily Khoruzhick  wrote:
> >
> > On Wed, Nov 6, 2019 at 8:50 AM Jagan Teki  
> > wrote:
> > >
> > > Hi Vasily,
> > >
> > > On Wed, Nov 6, 2019 at 9:17 AM Vasily Khoruzhick  
> > > wrote:
> > > >
> > > > Hi Akash, Jagan,
> > > >
> > > > Looks like USB is not functional in u-boot on Rockpro64. u-boot is
> > > > from git, commit 680023c5fab6b1777c0c6f2e76e5d2effb7903a0.
> > > >
> > > > I'm using u-boot SPL and mainline ATF
> > > > (19adcb415c313d656324d54e7608cdc7d7a5c414 is ATF commit)
> > > >
> > > > 'usb start' doesn't detect anything but hubs and looks like there's no
> > > > power on USB ports:
> > > >
> > > > => usb start
> > > > starting USB...
> > > > Bus usb@fe38: USB EHCI 1.00
> > > > Bus usb@fe3c: USB EHCI 1.00
> > > > Bus dwc3: Register 2000140 NbrPorts 2
> > > > Starting the controller
> > > > USB XHCI 1.10
> > > > Bus dwc3: Register 2000140 NbrPorts 2
> > > > Starting the controller
> > > > USB XHCI 1.10
> > > > scanning bus usb@fe38 for devices... 1 USB Device(s) found
> > > > scanning bus usb@fe3c for devices... 1 USB Device(s) found
> > > > scanning bus dwc3 for devices... 1 USB Device(s) found
> > > > scanning bus dwc3 for devices... 1 USB Device(s) found
> > > >scanning usb for storage devices... 0 Storage Device(s) found
> > > >
> > > > => usb tree
> > > > USB device tree:
> > > >   1  Hub (480 Mb/s, 0mA)
> > > >  u-boot EHCI Host Controller
> > > >
> > > >   1  Hub (480 Mb/s, 0mA)
> > > >  u-boot EHCI Host Controller
> > > >
> > > >   1  Hub (5 Gb/s, 0mA)
> > > >  U-Boot XHCI Host Controller
> > > >
> > > >   1  Hub (5 Gb/s, 0mA)
> > > >  U-Boot XHCI Host Controller
> > > >
> > > > Regulators were probed correctly according to 'dm tree':
> > > >
> > > >  regulator14  [ + ]   fixed regulator   |-- vcc12v-dcin
> > > >  regulator15  [ + ]   fixed regulator   |-- vcc1v8-s3
> > > >  regulator16  [ + ]   fixed regulator   |-- 
> > > > vcc3v3-pcie-regulator
> > > >  regulator17  [ + ]   fixed regulator   |-- vcc3v3-sys
> > > >  regulator18  [ + ]   fixed regulator   |-- 
> > > > vcc5v0-host-regulator
> > > >  regulator19  [ + ]   fixed regulator   |-- 
> > > > vcc5v0-typec-regulator
> > > >  regulator20  [ + ]   fixed regulator   |-- vcc5v0-sys
> > > >  regulator21  [ + ]   fixed regulator   |-- vcc5v0-usb
> > > >  regulator22  [ + ]   pwm_regulator `-- vdd-log
> > > >
> > > > Any ideas what can be wrong? Have it worked before?
> > >
> > > I remember my last checking, give me sometime will check it on master
> > > and update you.
> >
> > Looks like gpio clock is not enabled anywhere in u-boot for rk3399, so
> > gpios just don't work.
>
> I was wrong about clock, it appears that set bin in CRU is disabled
> clock. Yet GPIOs don't work in u-boot, e.g.
>
> => gpio set 154
> gpio: pin 154 (gpio 154) value is 1
>Warning: value of pin is still 0
>
> 154 is vcc5v0-host-regulator.gpio.
>
> > rk3399 clock driver is very rudimentary and doesn't touch clock gates at 
> > all.
> >
> > Can anyone explain how it's supposed to work?
> >
> > >
> > > Jagan.
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [RFC PATCH] dm: core: Remove libfdt dependency when unnecessary

2019-11-07 Thread Walter Lozano


Hi Tom

On 7/11/19 15:27, Tom Rini wrote:

On Tue, Nov 05, 2019 at 01:56:00PM -0300, Ezequiel Garcia wrote:

Hello Walter,

Thanks for the patch.

On Tue, 5 Nov 2019 at 12:27, Walter Lozano  wrote:

The support of libfdt should only be needed when OF_CONTROL
is enabled and OF_PLATDATA is not, as in other cases there is no
DT file to query.

This patch fixes this dependency allowing to save some space.


Can you add some more information about the space saving?
The ./scripts/bloat-o-meter will help you get some info
on static footprint.

Note that in U-Boot, we can as good or better information via buildman.
The --bloat flag gives a lot of useful info about what functions
grew/shrunk in addition to a section size summary.


Thanks for sharing this information. I will check it.


Regards,


Walter

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 1/2] arm: dts: rk3399-rockpro64: sync dts from linux kernel

2019-11-07 Thread Kever Yang



On 2019/11/7 下午7:11, Soeren Moch wrote:

The most important change for u-boot is the fix for the vdd-log pwm
voltage regulator to avoid overvoltage for the VD_LOGIC power domain.

Signed-off-by: Soeren Moch 
=2D--
Cc: Kever Yang 
Cc: u-boot@lists.denx.de
=2D--


Why  is the "=2D- -" here?

Otherwise looks good to me.


Reviewed-by: Kever Yang

Thanks,
- Kever


  arch/arm/dts/rk3399-rockpro64.dts | 57 ++-
  1 file changed, 49 insertions(+), 8 deletions(-)

diff --git a/arch/arm/dts/rk3399-rockpro64.dts b/arch/arm/dts/rk3399-rockp=
ro64.dts
index 1f2394e058..e544deb61d 100644
=2D-- a/arch/arm/dts/rk3399-rockpro64.dts
+++ b/arch/arm/dts/rk3399-rockpro64.dts
@@ -58,6 +58,13 @@
};
};

+   fan: pwm-fan {
+   compatible =3D "pwm-fan";
+   #cooling-cells =3D <2>;
+   fan-supply =3D <_dcin>;
+   pwms =3D < 0 5 0>;
+   };
+
sdio_pwrseq: sdio-pwrseq {
compatible =3D "mmc-pwrseq-simple";
clocks =3D < 1>;
@@ -166,7 +173,7 @@
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt =3D <80>;
-   regulator-max-microvolt =3D <140>;
+   regulator-max-microvolt =3D <170>;
vin-supply =3D <_sys>;
};
  };
@@ -222,6 +229,10 @@
status =3D "okay";
  };

+_sound {
+   status =3D "okay";
+};
+
   {
mali-supply =3D <_gpu>;
status =3D "okay";
@@ -236,8 +247,8 @@
rk808: pmic@1b {
compatible =3D "rockchip,rk808";
reg =3D <0x1b>;
-   interrupt-parent =3D <>;
-   interrupts =3D <21 IRQ_TYPE_LEVEL_LOW>;
+   interrupt-parent =3D <>;
+   interrupts =3D <10 IRQ_TYPE_LEVEL_LOW>;
#clock-cells =3D <1>;
clock-output-names =3D "xin32k", "rk808-clkout2";
pinctrl-names =3D "default";
@@ -504,11 +515,25 @@
status =3D "okay";

bt656-supply =3D <_dvp>;
-   audio-supply =3D <_codec>;
+   audio-supply =3D <_3v0>;
sdmmc-supply =3D <_sdio>;
gpio1830-supply =3D <_3v0>;
  };

+ {
+   ep-gpios =3D < RK_PD4 GPIO_ACTIVE_HIGH>;
+   num-lanes =3D <4>;
+   pinctrl-names =3D "default";
+   pinctrl-0 =3D <_perst>;
+   vpcie12v-supply =3D <_dcin>;
+   vpcie3v3-supply =3D <_pcie>;
+   status =3D "okay";
+};
+
+_phy {
+   status =3D "okay";
+};
+
  _io_domains {
pmu1830-supply =3D <_3v0>;
status =3D "okay";
@@ -538,6 +563,10 @@
};

pcie {
+   pcie_perst: pcie-perst {
+   rockchip,pins =3D <2 RK_PD4 RK_FUNC_GPIO 
_pull_none>;
+   };
+
pcie_pwr_en: pcie-pwr-en {
rockchip,pins =3D <1 RK_PD0 RK_FUNC_GPIO 
_pull_none>;
};
@@ -545,7 +574,7 @@

pmic {
pmic_int_l: pmic-int-l {
-   rockchip,pins =3D <1 RK_PC5 RK_FUNC_GPIO _pull_up>;
+   rockchip,pins =3D <3 RK_PB2 RK_FUNC_GPIO _pull_up>;
};

vsel1_gpio: vsel1-gpio {
@@ -580,6 +609,10 @@
status =3D "okay";
  };

+ {
+   status =3D "okay";
+};
+
   {
status =3D "okay";
  };
@@ -591,7 +624,6 @@

   {
bus-width =3D <4>;
-   cap-mmc-highspeed;
cap-sd-highspeed;
cd-gpios =3D < 7 GPIO_ACTIVE_LOW>;
disable-wp;
@@ -603,12 +635,21 @@

   {
bus-width =3D <8>;
-   mmc-hs400-1_8v;
-   mmc-hs400-enhanced-strobe;
+   mmc-hs200-1_8v;
non-removable;
status =3D "okay";
  };

+ {
+   status =3D "okay";
+
+   flash@0 {
+   compatible =3D "jedec,spi-nor";
+   reg =3D <0>;
+   spi-max-frequency =3D <1000>;
+   };
+};
+
   {
status =3D "okay";
  };
=2D-
2.17.1





___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 2/2] arm: dts: rk3399-rockpro64: slightly increase center voltage

2019-11-07 Thread Kever Yang



On 2019/11/7 下午7:11, Soeren Moch wrote:

The rk3399 VD_CENTER voltage domain is not subject to dynamic voltage
scaling. So the regulator reset voltage of 0.9V is used on this board.
Let u-boot initialize the center voltage to 0.95V as it is done for the
VD_LOGIC domain. This avoids instability and occasional linux kernel
Opses on this board.

Signed-off-by: Soeren Moch 
=2D--
Cc: Kever Yang 
Cc: u-boot@lists.denx.de
=2D--
  arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 5 +


Reviewed-by: Kever Yang

Thanks,
- Kever

  1 file changed, 5 insertions(+)

diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk33=
99-rockpro64-u-boot.dtsi
index a073ea25f5..4648513ea9 100644
=2D-- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
@@ -11,6 +11,11 @@
};
  };

+_center {
+   regulator-min-microvolt =3D <95>;
+   regulator-max-microvolt =3D <95>;
+};
+
  _log {
regulator-init-microvolt =3D <95>;
  };
=2D-
2.17.1





___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] standalone application on odroid xu4

2019-11-07 Thread Michael Neises

Hi,

I'm working with the Odroid XU4 board. I want to execute a standalone
application, like the hello_world function that is included with u-boot
source. My steps to compile are:
1. clone the u-boot repo
2. `export ARCH=armv7a`
3. `export CROSS_COMPILE=arm-linux-gnueabi-`
4. `make`
5. Use sd_fusing.sh to write the sd card

After boot, I use `setenv loads_echo 1,` and then I am able to use the
"loads" command to transfer the file "hello_world.srec," but I am notified:

CACHE: Misaligned operation at range [0c10, 0c10027a]

and when I try to execute the application via `go 0c10 hello world,` it
hangs and becomes unresponsive. I've tried the other included srec file,
but it also fails in the same way. I've tried defining
CONFIG_SYS_DCACHE_OFF and the same with ICACHE, as per a blog post, but
that was not effective. I've tried abbreviating the file to include only
the app_startup() function and a return, but that also doesn't work.

Do you have any advice to help me with this?

Ultimately, I would like to write an application that runs automatically
before a kernel image is loaded, in order to take advantage of some system
hardware that gets locked when the OS boots. Is this possible?

Best,
Michael Neises
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] usb: xhci: support 1.1 or later version

2019-11-07 Thread Chunfeng Yun

The xHCI 1.1 version also need set Transfer Type field

Signed-off-by: Chunfeng Yun 
---
 drivers/usb/host/xhci-ring.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 119b418..6a469e1 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -827,7 +827,7 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long 
pipe,
field |= 0x1;
 
/* xHCI 1.0 6.4.1.2.1: Transfer Type field */
-   if (HC_VERSION(xhci_readl(>hccr->cr_capbase)) == 0x100) {
+   if (HC_VERSION(xhci_readl(>hccr->cr_capbase)) >= 0x100) {
if (length > 0) {
if (req->requesttype & USB_DIR_IN)
field |= (TRB_DATA_IN << TRB_TX_TYPE_SHIFT);
-- 
1.8.1.1.dirty

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] configs: Stratix10: Disable CONFIG_SPL_USE_TINY_PRINTF

2019-11-07 Thread Ley Foon Tan

Commit 2a51e16bd57a ("configs: Make USE_TINY_PRINTF depend on SPL||TPL and be 
default")
enable USE_TINY_PRINTF by default, disable it for Stratix10.

Resync with savedefconfig.

Signed-off-by: Ley Foon Tan 
---
 configs/socfpga_stratix10_defconfig | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/configs/socfpga_stratix10_defconfig 
b/configs/socfpga_stratix10_defconfig
index 5ae53a4db9..b7fbab4740 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -17,7 +17,6 @@ CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
@@ -39,7 +38,6 @@ CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_DW=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
-CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0x2003
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -56,3 +54,4 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
-- 
2.19.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] arm: dts: Stratix10: Fix memory node address and size cells

2019-11-07 Thread Ley Foon Tan

Add #address-cells and #size-cells to memory node to fix incorrect memory
size decoding in recent Uboot version.

Signed-off-by: Ley Foon Tan 
---
 arch/arm/dts/socfpga_stratix10_socdk.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts 
b/arch/arm/dts/socfpga_stratix10_socdk.dts
index c5409df026..ce07659602 100755
--- a/arch/arm/dts/socfpga_stratix10_socdk.dts
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -36,6 +36,8 @@
};
 
memory {
+   #address-cells = <2>;
+   #size-cells = <2>;
device_type = "memory";
/* 4GB */
reg = <0 0x 0 0x8000>,
-- 
2.19.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] spl: Allow cache drivers to be used in SPL

2019-11-07 Thread Ley Foon Tan

Add an option for building cache drivers in SPL.

Signed-off-by: Ley Foon Tan 
---
 common/spl/Kconfig | 5 +
 drivers/Makefile   | 1 +
 drivers/cache/Makefile | 2 +-
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index c661809923..6e095c33e1 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -714,6 +714,11 @@ config SPL_UBI
  README.ubispl for more info.
 
 if SPL_DM
+config SPL_CACHE
+   bool "Support cache drivers in SPL"
+   help
+ Enable support for cache drivers in SPL.
+
 config SPL_DM_SPI
bool "Support SPI DM drivers in SPL"
help
diff --git a/drivers/Makefile b/drivers/Makefile
index 0befeddfcb..0e42d006b9 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -31,6 +31,7 @@ ifndef CONFIG_TPL_BUILD
 ifdef CONFIG_SPL_BUILD
 
 obj-$(CONFIG_SPL_BOOTCOUNT_LIMIT) += bootcount/
+obj-$(CONFIG_SPL_CACHE) += cache/
 obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/
 obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
 obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 4a6458c602..c1f766cfca 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -1,5 +1,5 @@
 
-obj-$(CONFIG_CACHE) += cache-uclass.o
+obj-$(CONFIG_$(SPL_)CACHE) += cache-uclass.o
 obj-$(CONFIG_SANDBOX) += sandbox_cache.o
 obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
 obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
-- 
2.19.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 4/4] arm: socfpga: Convert clock manager from struct to defines

2019-11-07 Thread Ley Foon Tan

Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get clock manager base address from DT node instead of using
#define.

Signed-off-by: Ley Foon Tan 

---
v6:
- Call to socfpga_get_clkmgr_addr() function, instead of access to global
  variable directly.

v5:
- Change macro value to 0x** format.

v4:
- Update commit message about get base address from DT node.

v3:
- Remove "No functional change" in commit description.

v2:
- Revert to use writel(), readl() and etc.
- Get base address from DT.
- Add prefix to defines.
---
 arch/arm/mach-socfpga/clock_manager.c |  14 +-
 arch/arm/mach-socfpga/clock_manager_arria10.c | 155 +++--
 arch/arm/mach-socfpga/clock_manager_gen5.c| 211 +
 arch/arm/mach-socfpga/clock_manager_s10.c | 213 ++
 .../mach-socfpga/include/mach/clock_manager.h |   2 +
 .../include/mach/clock_manager_arria10.h  | 133 +--
 .../include/mach/clock_manager_gen5.h | 112 -
 .../include/mach/clock_manager_s10.h  | 115 --
 arch/arm/mach-socfpga/misc.c  |  10 +
 drivers/mmc/socfpga_dw_mmc.c  |  11 +-
 10 files changed, 501 insertions(+), 475 deletions(-)

diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index 9f3c643df8..dbb10ecb68 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -10,18 +10,17 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_clock_manager *clock_manager_base =
-   (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-
 void cm_wait_for_lock(u32 mask)
 {
u32 inter_val;
u32 retry = 0;
do {
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-   inter_val = readl(_manager_base->inter) & mask;
+   inter_val = readl(socfpga_get_clkmgr_addr() +
+ CLKMGR_INTER) & mask;
 #else
-   inter_val = readl(_manager_base->stat) & mask;
+   inter_val = readl(socfpga_get_clkmgr_addr() +
+ CLKMGR_STAT) & mask;
 #endif
/* Wait for stable lock */
if (inter_val == mask)
@@ -36,8 +35,9 @@ void cm_wait_for_lock(u32 mask)
 /* function to poll in the fsm busy bit */
 int cm_wait_for_fsm(void)
 {
-   return wait_for_bit_le32(_manager_base->stat,
-CLKMGR_STAT_BUSY, false, 2, false);
+   return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() +
+CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 2,
+false);
 }
 
 int set_cpu_clk_info(void)
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c 
b/arch/arm/mach-socfpga/clock_manager_arria10.c
index 334a79fd9c..392f2eb915 100644
--- a/arch/arm/mach-socfpga/clock_manager_arria10.c
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -231,9 +231,6 @@ static int of_get_clk_cfg(const void *blob, struct 
mainpll_cfg *main_cfg,
return 0;
 }
 
-static const struct socfpga_clock_manager *clock_manager_base =
-   (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-
 /* calculate the intended main VCO frequency based on handoff */
 static unsigned int cm_calc_handoff_main_vco_clk_hz
(struct mainpll_cfg *main_cfg)
@@ -551,12 +548,13 @@ static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
writel((main_cfg->vco1_denom <<
CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
-   _manager_base->main_pll.vco1);
+   socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
mdelay(1);
cm_wait_for_lock(LOCKED_MASK);
}
writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
-   main_cfg->vco1_numer, _manager_base->main_pll.vco1);
+   main_cfg->vco1_numer,
+   socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
mdelay(1);
cm_wait_for_lock(LOCKED_MASK);
 }
@@ -579,14 +577,18 @@ static void cm_pll_ramp_periph(struct mainpll_cfg 
*main_cfg,
/* execute the ramping here */
for (clk_hz = pll_ramp_periph_hz + clk_incr_hz;
 clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
-   writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
-   cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz),
-   _manager_base->per_pll.vco1);
+   writel((per_cfg->vco1_denom <<
+ CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+ cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
+clk_hz),
+ socfpga_get_clkmgr_addr() +
+

[U-Boot] [PATCH v6 3/4] arm: socfpga: Convert system manager from struct to defines

2019-11-07 Thread Ley Foon Tan

Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get system manager base address from DT node instead of
using #define.

Signed-off-by: Ley Foon Tan 

---
v6:
- Call to socfpga_get_sysmgr_addr() function, instead of access to global
  variable directly.

v5:
- Change macro value to 0x** format.

v4:
- Update commit message about get base address from DT node.

v3:
- Remove "No functional change" in commit description.

v2:
- Revert to use writel(), readl() and etc.
- Get base address from DT.
- Add prefix to defines.
---
 arch/arm/mach-socfpga/clock_manager_s10.c |   4 +-
 .../include/mach/system_manager.h |   2 +
 .../include/mach/system_manager_arria10.h |  94 +++--
 .../include/mach/system_manager_gen5.h| 123 +++-
 .../include/mach/system_manager_s10.h | 184 +++---
 arch/arm/mach-socfpga/mailbox_s10.c   |   6 +-
 arch/arm/mach-socfpga/misc.c  |  10 +
 arch/arm/mach-socfpga/misc_arria10.c  |  11 +-
 arch/arm/mach-socfpga/misc_gen5.c |  26 ++-
 arch/arm/mach-socfpga/misc_s10.c  |   9 +-
 arch/arm/mach-socfpga/reset_manager_arria10.c |  24 +--
 arch/arm/mach-socfpga/reset_manager_gen5.c|   9 +-
 arch/arm/mach-socfpga/reset_manager_s10.c |  20 +-
 arch/arm/mach-socfpga/scan_manager.c  |   6 +-
 arch/arm/mach-socfpga/spl_a10.c   |   5 +-
 arch/arm/mach-socfpga/spl_gen5.c  |  12 +-
 arch/arm/mach-socfpga/spl_s10.c   |  12 +-
 arch/arm/mach-socfpga/system_manager_gen5.c   |  42 ++--
 arch/arm/mach-socfpga/system_manager_s10.c|  42 ++--
 arch/arm/mach-socfpga/wrap_pll_config_s10.c   |  13 +-
 drivers/ddr/altera/sdram_gen5.c   |  12 +-
 drivers/ddr/altera/sdram_s10.c|   6 +-
 drivers/fpga/socfpga_arria10.c|   7 +-
 drivers/fpga/socfpga_gen5.c   |   4 +-
 drivers/mmc/socfpga_dw_mmc.c  |   6 +-
 25 files changed, 267 insertions(+), 422 deletions(-)

diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c 
b/arch/arm/mach-socfpga/clock_manager_s10.c
index 3ba2a00c02..88817030ab 100644
--- a/arch/arm/mach-socfpga/clock_manager_s10.c
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -14,8 +14,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-static const struct socfpga_system_manager *sysmgr_regs =
-   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 /*
  * function to write the bypass register which requires a poll of the
@@ -351,7 +349,7 @@ unsigned int cm_get_l4_sp_clk_hz(void)
 
 unsigned int cm_get_qspi_controller_clk_hz(void)
 {
-   return readl(_regs->boot_scratch_cold0);
+   return readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_BOOT_SCRATCH_COLD0);
 }
 
 unsigned int cm_get_spi_controller_clk_hz(void)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 7e76df74b7..7f05029a67 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -6,6 +6,8 @@
 #ifndef _SYSTEM_MANAGER_H_
 #define _SYSTEM_MANAGER_H_
 
+phys_addr_t socfpga_get_sysmgr_addr(void);
+
 #if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
 #include 
 #else
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
index 14052b957c..e4fc6d2e55 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
@@ -6,73 +6,33 @@
 #ifndef _SYSTEM_MANAGER_ARRIA10_H_
 #define _SYSTEM_MANAGER_ARRIA10_H_
 
-struct socfpga_system_manager {
-   u32  siliconid1;
-   u32  siliconid2;
-   u32  wddbg;
-   u32  bootinfo;
-   u32  mpu_ctrl_l2_ecc;
-   u32  _pad_0x14_0x1f[3];
-   u32  dma;
-   u32  dma_periph;
-   u32  sdmmcgrp_ctrl;
-   u32  sdmmc_l3master;
-   u32  nand_bootstrap;
-   u32  nand_l3master;
-   u32  usb0_l3master;
-   u32  usb1_l3master;
-   u32  emac_global;
-   u32  emac[3];
-   u32  _pad_0x50_0x5f[4];
-   u32  fpgaintf_en_global;
-   u32  fpgaintf_en_0;
-   u32  fpgaintf_en_1;
-   u32  fpgaintf_en_2;
-   u32  fpgaintf_en_3;
-   u32  _pad_0x74_0x7f[3];
-   u32  noc_addr_remap_value;
-   u32  noc_addr_remap_set;
-   u32  noc_addr_remap_clear;
-   u32  _pad_0x8c_0x8f;
-   u32  ecc_intmask_value;
-   u32  ecc_intmask_set;
-   u32  ecc_intmask_clr;
-   u32  ecc_intstatus_serr;
-   u32  ecc_intstatus_derr;
-   u32  mpu_status_l2_ecc;
-   u32  mpu_clear_l2_ecc;
-   u32  mpu_status_l1_parity;
-   u32  mpu_clear_l1_parity;
-   u32  mpu_set_l1_parity;
-   u32  _pad_0xb8_0xbf[2];
-   u32  noc_timeout;

[U-Boot] [PATCH v6 2/4] arm: socfpga: Convert reset manager from struct to defines

2019-11-07 Thread Ley Foon Tan

Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get reset manager base address from DT node instead of using
#define.

spl_early_init() initializes the DT setup. So, move spl_early_init() to
beginning of function and before get base address from DT.

Signed-off-by: Ley Foon Tan 

---
v6:
- Call to socfpga_get_rstmgr_addr() function, instead of access to global
  variable directly.
- Update socfpga_get_base_addr() to return error code,  instead of return 0.

v5:
- Change macro values with 0x** format.

v4:
- Update commit message about get base address from DT node.

v3:
- Remove "No functional change" in commit description.

v2:
- Get base address from DT
- Revert to use writel(), readl(), setbits_le32() and clrbits_le32().
- Add prefix to defines.
---
 arch/arm/mach-socfpga/include/mach/misc.h |  1 +
 .../mach-socfpga/include/mach/reset_manager.h |  2 +
 .../include/mach/reset_manager_arria10.h  | 43 
 .../include/mach/reset_manager_gen5.h | 22 -
 .../include/mach/reset_manager_s10.h  | 33 ++---
 arch/arm/mach-socfpga/misc.c  | 41 
 arch/arm/mach-socfpga/misc_gen5.c |  7 ++-
 arch/arm/mach-socfpga/reset_manager_arria10.c | 49 ++-
 arch/arm/mach-socfpga/reset_manager_gen5.c| 28 +--
 arch/arm/mach-socfpga/reset_manager_s10.c | 35 ++---
 arch/arm/mach-socfpga/spl_a10.c   |  7 ++-
 arch/arm/mach-socfpga/spl_gen5.c  | 14 +++---
 arch/arm/mach-socfpga/spl_s10.c   | 12 +++--
 drivers/sysreset/sysreset_socfpga.c   |  6 +--
 14 files changed, 150 insertions(+), 150 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/misc.h 
b/arch/arm/mach-socfpga/include/mach/misc.h
index 27d0b6a370..7310fd4c3a 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -41,5 +41,6 @@ void socfpga_sdram_remap_zero(void);
 
 void do_bridge_reset(int enable, unsigned int mask);
 void socfpga_pl310_clear(void);
+void socfpga_get_managers_addr(void);
 
 #endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6ad037e325..96052d94b4 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -6,6 +6,8 @@
 #ifndef _RESET_MANAGER_H_
 #define _RESET_MANAGER_H_
 
+phys_addr_t socfpga_get_rstmgr_addr(void);
+
 void reset_cpu(ulong addr);
 
 void socfpga_per_reset(u32 reset, int set);
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
index 6623ebee65..22e4eb33de 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -14,40 +14,15 @@ int socfpga_reset_deassert_bridges_handoff(void);
 void socfpga_reset_deassert_osc1wd0(void);
 int socfpga_bridges_reset(void);
 
-struct socfpga_reset_manager {
-   u32 stat;
-   u32 ramstat;
-   u32 miscstat;
-   u32 ctrl;
-   u32 hdsken;
-   u32 hdskreq;
-   u32 hdskack;
-   u32 counts;
-   u32 mpumodrst;
-   u32 per0modrst;
-   u32 per1modrst;
-   u32 brgmodrst;
-   u32 sysmodrst;
-   u32 coldmodrst;
-   u32 nrstmodrst;
-   u32 dbgmodrst;
-   u32 mpuwarmmask;
-   u32 per0warmmask;
-   u32 per1warmmask;
-   u32 brgwarmmask;
-   u32 syswarmmask;
-   u32 nrstwarmmask;
-   u32 l3warmmask;
-   u32 tststa;
-   u32 tstscratch;
-   u32 hdsktimeout;
-   u32 hmcintr;
-   u32 hmcintren;
-   u32 hmcintrens;
-   u32 hmcintrenr;
-   u32 hmcgpout;
-   u32 hmcgpin;
-};
+#define RSTMGR_A10_STATUS  0x00
+#define RSTMGR_A10_CTRL0x0c
+#define RSTMGR_A10_MPUMODRST   0x20
+#define RSTMGR_A10_PER0MODRST  0x24
+#define RSTMGR_A10_PER1MODRST  0x28
+#define RSTMGR_A10_BRGMODRST   0x2c
+#define RSTMGR_A10_SYSMODRST   0x30
+
+#define RSTMGR_CTRLRSTMGR_A10_CTRL
 
 /*
  * SocFPGA Arria10 reset IDs, bank mapping is as follows:
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
index f4dcb14623..d108eac1e2 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -11,19 +11,15 @@
 void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
 void socfpga_bridges_reset(int enable);
 
-struct socfpga_reset_manager {
-   u32 status;
-   u32 ctrl;
-   u32 counts;
-   u32 padding1;
-   u32 mpu_mod_reset;
-   u32 per_mod_reset;
-   u32 per2_mod_reset;
-

[U-Boot] [PATCH v6 1/4] arm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr nodes

2019-11-07 Thread Ley Foon Tan

Add u-boot,dm-pre-reloc for sysmgr and clkmgr nodes to use it in SPL.
In preparation to get base address from DT.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v3:
- Fix missing '0' in clkmgr@ffd1 node.
---
 arch/arm/dts/socfpga-common-u-boot.dtsi  | 8 
 arch/arm/dts/socfpga.dtsi| 2 +-
 arch/arm/dts/socfpga_arria10.dtsi| 2 +-
 arch/arm/dts/socfpga_arria10_socdk.dtsi  | 8 
 arch/arm/dts/socfpga_stratix10.dtsi  | 2 +-
 arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 8 
 6 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi 
b/arch/arm/dts/socfpga-common-u-boot.dtsi
index 322c858c4b..d55460755f 100644
--- a/arch/arm/dts/socfpga-common-u-boot.dtsi
+++ b/arch/arm/dts/socfpga-common-u-boot.dtsi
@@ -10,6 +10,10 @@
};
 };
 
+ {
+   u-boot,dm-pre-reloc;
+};
+
  {
u-boot,dm-pre-reloc;
 };
@@ -17,3 +21,7 @@
  {
u-boot,dm-pre-reloc;
 };
+
+ {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 51a6a51b53..eda558f2fe 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -114,7 +114,7 @@
status = "disabled";
};
 
-   clkmgr@ffd04000 {
+   clkmgr: clkmgr@ffd04000 {
compatible = "altr,clk-mgr";
reg = <0xffd04000 0x1000>;
 
diff --git a/arch/arm/dts/socfpga_arria10.dtsi 
b/arch/arm/dts/socfpga_arria10.dtsi
index c11a5c0cc1..cc529bcd11 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -96,7 +96,7 @@
fpga-mgr = <_mgr>;
};
 
-   clkmgr@ffd04000 {
+   clkmgr: clkmgr@ffd04000 {
compatible = "altr,clk-mgr";
reg = <0xffd04000 0x1000>;
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi 
b/arch/arm/dts/socfpga_arria10_socdk.dtsi
index 6e5578d7bd..ef10708ee8 100644
--- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
@@ -180,3 +180,11 @@
 _sp_clk {
u-boot,dm-pre-reloc;
 };
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi 
b/arch/arm/dts/socfpga_stratix10.dtsi
index bd68a78a37..a8e61cf728 100755
--- a/arch/arm/dts/socfpga_stratix10.dtsi
+++ b/arch/arm/dts/socfpga_stratix10.dtsi
@@ -82,7 +82,7 @@
ranges = <0 0 0 0x>;
u-boot,dm-pre-reloc;
 
-   clkmgr@ffd1000 {
+   clkmgr: clkmgr@ffd1 {
compatible = "altr,clk-mgr";
reg = <0xffd1 0x1000>;
};
diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi 
b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
index e1cfb522bf..38855aecd7 100755
--- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
@@ -11,6 +11,10 @@
};
 };
 
+ {
+   u-boot,dm-pre-reloc;
+};
+
  {
status = "okay";
u-boot,dm-pre-reloc;
@@ -23,3 +27,7 @@
spi-rx-bus-width = <4>;
u-boot,dm-pre-reloc;
 };
+
+ {
+   u-boot,dm-pre-reloc;
+};
-- 
2.19.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v6 0/4] arm: socfpga: Convert drivers from struct to defines

2019-11-07 Thread Ley Foon Tan

This is 6th version of patchset to convert reset, system and clock manager
drivers to use #define instead of struct.

Patch 1 unchanged, patch 2,3,4 have changes.

Tested on Cyclone 5, Arria 10 and Stratix 10 devices.

Changes in v6:
- Call to socfpga_get_*mgr_addr() function, instead of access to global
  variable directly.
- Update socfpga_get_base_addr() to return error code,  instead of return 0.

History:
v1: https://patchwork.ozlabs.org/cover/1149731/
v2: https://patchwork.ozlabs.org/cover/1160079/
v3: https://patchwork.ozlabs.org/cover/1174327/
v4: https://patchwork.ozlabs.org/cover/1174347/
v5: https://patchwork.ozlabs.org/cover/1190831/

Ley Foon Tan (4):
  arm: dts: socfpga: Add u-boot,dm-pre-reloc for sysmgr and clkmgr nodes
  arm: socfpga: Convert reset manager from struct to defines
  arm: socfpga: Convert system manager from struct to defines
  arm: socfpga: Convert clock manager from struct to defines

 arch/arm/dts/socfpga-common-u-boot.dtsi   |   8 +
 arch/arm/dts/socfpga.dtsi |   2 +-
 arch/arm/dts/socfpga_arria10.dtsi |   2 +-
 arch/arm/dts/socfpga_arria10_socdk.dtsi   |   8 +
 arch/arm/dts/socfpga_stratix10.dtsi   |   2 +-
 .../dts/socfpga_stratix10_socdk-u-boot.dtsi   |   8 +
 arch/arm/mach-socfpga/clock_manager.c |  14 +-
 arch/arm/mach-socfpga/clock_manager_arria10.c | 155 +++--
 arch/arm/mach-socfpga/clock_manager_gen5.c| 211 ++---
 arch/arm/mach-socfpga/clock_manager_s10.c | 217 ++
 .../mach-socfpga/include/mach/clock_manager.h |   2 +
 .../include/mach/clock_manager_arria10.h  | 133 ---
 .../include/mach/clock_manager_gen5.h | 112 -
 .../include/mach/clock_manager_s10.h  | 115 --
 arch/arm/mach-socfpga/include/mach/misc.h |   1 +
 .../mach-socfpga/include/mach/reset_manager.h |   2 +
 .../include/mach/reset_manager_arria10.h  |  43 +---
 .../include/mach/reset_manager_gen5.h |  22 +-
 .../include/mach/reset_manager_s10.h  |  33 +--
 .../include/mach/system_manager.h |   2 +
 .../include/mach/system_manager_arria10.h |  94 +++-
 .../include/mach/system_manager_gen5.h| 123 ++
 .../include/mach/system_manager_s10.h | 184 ++-
 arch/arm/mach-socfpga/mailbox_s10.c   |   6 +-
 arch/arm/mach-socfpga/misc.c  |  61 +
 arch/arm/mach-socfpga/misc_arria10.c  |  11 +-
 arch/arm/mach-socfpga/misc_gen5.c |  33 +--
 arch/arm/mach-socfpga/misc_s10.c  |   9 +-
 arch/arm/mach-socfpga/reset_manager_arria10.c |  73 +++---
 arch/arm/mach-socfpga/reset_manager_gen5.c|  37 ++-
 arch/arm/mach-socfpga/reset_manager_s10.c |  55 ++---
 arch/arm/mach-socfpga/scan_manager.c  |   6 +-
 arch/arm/mach-socfpga/spl_a10.c   |  12 +-
 arch/arm/mach-socfpga/spl_gen5.c  |  26 +--
 arch/arm/mach-socfpga/spl_s10.c   |  24 +-
 arch/arm/mach-socfpga/system_manager_gen5.c   |  42 ++--
 arch/arm/mach-socfpga/system_manager_s10.c|  42 ++--
 arch/arm/mach-socfpga/wrap_pll_config_s10.c   |  13 +-
 drivers/ddr/altera/sdram_gen5.c   |  12 +-
 drivers/ddr/altera/sdram_s10.c|   6 +-
 drivers/fpga/socfpga_arria10.c|   7 +-
 drivers/fpga/socfpga_gen5.c   |   4 +-
 drivers/mmc/socfpga_dw_mmc.c  |  17 +-
 drivers/sysreset/sysreset_socfpga.c   |   6 +-
 44 files changed, 945 insertions(+), 1050 deletions(-)

-- 
2.19.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] Pull request: u-boot-rockchip-20191026

2019-11-07 Thread Kever Yang

Hi Tom,

Please pull the rockchip update:
- Add support for rockchip pmic rk805,rk809, rk816, rk817
- Add rk3399 board Leez support
- Fix bug in rk3328 ram driver
- Adapt SPL to support ATF bl31 with entry at 0x4

Fix the u8 type comparision with '-1'.

Travis:
https://travis-ci.org/keveryang/u-boot/builds/608622183

Thanks,
- Kever

The following changes since commit 0f282c1876af26cc2c8c018ae6293a691561011e:

  Makefile: fix dependency for imx targets (2019-11-06 09:22:32 -0500)

are available in the Git repository at:

  https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip.git 
tags/u-boot-rockchip-20191108

for you to fetch changes up to 08d9fe749237267bc60188fe116eb2f4ae0b18e7:

  rockchip: firefly-rk3288: Enable TPL support (2019-11-07 16:39:57 +0800)


Andy Yan (1):
  rockchip: rk3399: Add Leez P710 support

Elaine Zhang (3):
  power: regulator: rk8xx: update the driver for rk808 and rk818
  power: pmic: rk816: support rk816 pmic
  power: pmic: rk805: support rk805 pmic

Emmanuel Vadot (1):
  rockchip: dts: rk3328: rock64: Add same-as-spl order

Heiko Stuebner (1):
  rockchip: make_fit_atf.py: allow inclusion of a tee binary

Joseph Chen (4):
  dm: regulator: support regulator more state
  power: pmic: rk817: support rk817 pmic
  power: pmic: rk809: support rk809 pmic
  common: spl: atf: support booting bl32 image

Kever Yang (6):
  rockchip: rk3399: defconfig: no need to reserve IRAM for SPL
  rockchip: rk3328: defconfig: no need to reserve IRAM for SPL
  rockchip: evb-px5: defconfig: no need to reserve IRAM for SPL
  rockchip: rk3399: update SPL_STACK_R_ADDR
  rockchip: config: update CONFIG_SPL_MAX_SIZE for 64bit CPUs
  rockchip: firefly-rk3288: Enable TPL support

Levin Du (1):
  rockchip: adding the missing "/" in entries of boot_devices

Simon South (3):
  clk: rockchip: rk3328: Configure CPU clock
  ram: rk3328: Use correct frequency units in function
  ram: rk3328: Fix loading of skew values

 arch/arm/dts/Makefile|   1 +
 arch/arm/dts/rk3328-rock64-u-boot.dtsi   |   5 +
 arch/arm/dts/rk3399-leez-p710-u-boot.dtsi|  13 +
 arch/arm/dts/rk3399-leez-p710.dts| 645 
 arch/arm/include/asm/arch-rockchip/cru_rk3328.h  |   3 +
 arch/arm/mach-rockchip/make_fit_atf.py   |  52 +-
 arch/arm/mach-rockchip/rk3188/rk3188.c   |   4 +-
 arch/arm/mach-rockchip/rk322x/rk322x.c   |   4 +-
 arch/arm/mach-rockchip/rk3288/Kconfig|   1 +
 arch/arm/mach-rockchip/rk3288/rk3288.c   |   4 +-
 arch/arm/mach-rockchip/rk3328/rk3328.c   |   4 +-
 arch/arm/mach-rockchip/rk3368/rk3368.c   |   4 +-
 arch/arm/mach-rockchip/rk3399/Kconfig|   3 +
 board/rockchip/evb_rk3399/MAINTAINERS|   6 +
 common/spl/spl_atf.c |  49 +-
 configs/chromebook_bob_defconfig |   1 -
 configs/evb-px5_defconfig|   1 -
 configs/evb-rk3328_defconfig |   1 -
 configs/evb-rk3399_defconfig |   2 -
 configs/ficus-rk3399_defconfig   |   1 -
 configs/firefly-rk3288_defconfig |   5 +-
 configs/firefly-rk3399_defconfig |   2 -
 configs/khadas-edge-captain-rk3399_defconfig |   2 -
 configs/khadas-edge-rk3399_defconfig |   2 -
 configs/khadas-edge-v-rk3399_defconfig   |   2 -
 configs/leez-rk3399_defconfig|  56 ++
 configs/nanopc-t4-rk3399_defconfig   |   2 -
 configs/nanopi-m4-rk3399_defconfig   |   2 -
 configs/nanopi-neo4-rk3399_defconfig |   2 -
 configs/orangepi-rk3399_defconfig|   2 -
 configs/puma-rk3399_defconfig|   1 -
 configs/roc-rk3399-pc_defconfig  |   2 -
 configs/rock-pi-4-rk3399_defconfig   |   2 -
 configs/rock64-rk3328_defconfig  |   1 -
 configs/rock960-rk3399_defconfig |   1 -
 configs/rockpro64-rk3399_defconfig   |   2 -
 doc/device-tree-bindings/regulator/regulator.txt |  27 +
 drivers/clk/rockchip/clk_rk3328.c|   2 +
 drivers/power/pmic/rk8xx.c   |  89 ++-
 drivers/power/regulator/regulator-uclass.c   |  70 ++
 drivers/power/regulator/rk8xx.c  | 939 +--
 drivers/ram/rockchip/sdram_rk3328.c  |   6 +-
 include/configs/rk3328_common.h  |   2 +-
 include/configs/rk3368_common.h  |   2 +-
 include/configs/rk3399_common.h  |   2 +-
 include/power/regulator.h|  64 ++
 include/power/rk8xx_pmic.h   |  42 +
 test/dm/regulator.c  |  57 ++
 48 files changed, 2034 insertions(+), 158 deletions(-)
 create

[U-Boot] [PATCH] cmd: move down CONFIG_CMD_BOOTEFI after CONFIG_BOOTM_VXWORKS

2019-11-07 Thread AKASHI Takahiro

Due to the commit 4b0bcfa7c4ec ("Kconfig: Migrate CONFIG_BOOTM_* options")
BOOTEFI and BOOTEFI_HELLO_COMPILE (and other BOOTEFI configs) are
displayed in a long distance. This will make it difficult for us to
understand that those configurations are closely related.

Signed-off-by: AKASHI Takahiro 
---
 cmd/Kconfig | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 395dedd34d00..d9bc1eb8bd2b 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -263,13 +263,6 @@ config CMD_BOOTI
help
  Boot an AArch64 Linux Kernel image from memory.
 
-config CMD_BOOTEFI
-   bool "bootefi"
-   depends on EFI_LOADER
-   default y
-   help
- Boot an EFI image from memory.
-
 config BOOTM_LINUX
bool "Support booting Linux OS images"
depends on CMD_BOOTM || CMD_BOOTZ || CMD_BOOTI
@@ -318,6 +311,13 @@ config BOOTM_VXWORKS
help
  Support booting VxWorks images via the bootm command.
 
+config CMD_BOOTEFI
+   bool "bootefi"
+   depends on EFI_LOADER
+   default y
+   help
+ Boot an EFI image from memory.
+
 config CMD_BOOTEFI_HELLO_COMPILE
bool "Compile a standard EFI hello world binary for testing"
depends on CMD_BOOTEFI && !CPU_V7M && !SANDBOX
-- 
2.21.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations

2019-11-07 Thread Rick Chen

Hi Anup

>
> On Thu, Nov 7, 2019 at 5:11 PM Rick Chen  wrote:
> >
> > Hi Anup & Lukas
> >
> > Anup Patel  於 2019年11月7日 週四 下午6:44寫道：
> > >
> > > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas
> > >  wrote:
> > > >
> > > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote:
> > > > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen  
> > > > > wrote:
> > > > > > Hi Anup
> > > > > >
> > > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel  
> > > > > > > wrote:
> > > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen  
> > > > > > > > wrote:
> > > > > > > > > Hi Anup
> > > > > > > > >
> > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen 
> > > > > > > > > >  wrote:
> > > > > > > > > > > Hi Anup
> > > > > > > > > > >
> > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel 
> > > > > > > > > > > >  wrote:
> > > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen 
> > > > > > > > > > > > >  wrote:
> > > > > > > > > > > > > > Hi Anup
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen 
> > > > > > > > > > > > > > >  wrote:
> > > > > > > > > > > > > > > > Hi Anup
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel 
> > > > > > > > > > > > > > > > > >  wrote:
> > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao 
> > > > > > > > > > > > > > > > > > >  wrote:
> > > > > > > > > > > > > > > > > > > > Hi Bin,
> > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > Thanks for the critics.  Comments below.
> > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 06:38:00PM 
> > > > > > > > > > > > > > > > > > > > +0800, Bin Meng wrote:
> > > > > > > > > > > > > > > > > > > > > Hi Rick,
> > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick 
> > > > > > > > > > > > > > > > > > > > > Chen  wrote:
> > > > > > > > > > > > > > > > > > > > > > Hi Bin
> > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > > Hi Rick,
> > > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM 
> > > > > > > > > > > > > > > > > > > > > > > Andes  wrote:
> > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen 
> > > > > > > > > > > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to hart 0 
> > > > > > > > > > > > > > > > > > > > > > > > always will be main
> > > > > > > > > > > > > > > > > > > > > > > > hart coincidentally. When 
> > > > > > > > > > > > > > > > > > > > > > > > develop SPL flow, I try to
> > > > > > > > > > > > > > > > > > > > > > > > force other harts to be main 
> > > > > > > > > > > > > > > > > > > > > > > > hart. And it will go
> > > > > > > > > > > > > > > > > > > > > > > > wrong in sending IPI flow. So 
> > > > > > > > > > > > > > > > > > > > > > > > fix it.
> > > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit 
> > > > > > > > > > > > > > > > > > > > > > > contain 2 fixes, or just 1 fix?
> > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But they 
> > > > > > > > > > > > > > > > > > > > > > will cause one negative result
> > > > > > > > > > > > > > > > > > > > > > that only hart 0 can send ipi to 
> > > > > > > > > > > > > > > > > > > > > > other harts.
> > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can 
> > > > > > > > > > > > > > > > > > > > > > > > be main hart in U-Boot SPL
> > > > > > > > > > > > > > > > > > > > > > > > theoretically, but it still 
> > > > > > > > > > > > > > > > > > > > > > > > fail somewhere. After dig in
> > > > > > > > > > > > > > > > > > > > > > > > and found there is an 
> > > > > > > > > > > > > > > > > > > > > > > > assumption that hart 0 shall be
> > > > > > > > > > > > > > > > > > > > > > > > main hart in OpenSbi.
> > > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > > So does this mean there is a bug 
> > > > > > > > > > > > > > > > > > > > > > > in OpenSBI too?
> > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > I am not sure if it is a bug. Maybe 
> > > > > > > > > > > > > > > > > > > > > > it is a compatible issue.
> > > > > > > > > > > > > > > > > > > > > > There is a limitation that only 
> > > > > > > > > > > > > > > > > > > > > > hart 0 can be main hart in OpenSBI.
> > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > I don't think OpenSBI has such 
> > > > > > > > > > > > > > > > > > > > > limitation.
> > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > Please check the source.
>

Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations

2019-11-07 Thread Rick Chen

Hi Atish

>
> On Thu, 2019-11-07 at 19:41 +0800, Rick Chen wrote:
> > Hi Anup & Lukas
> >
> > Anup Patel  於 2019年11月7日 週四 下午6:44寫道：
> > > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas
> > >  wrote:
> > > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote:
> > > > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen  > > > > > wrote:
> > > > > > Hi Anup
> > > > > >
> > > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel <
> > > > > > > a...@brainfault.org> wrote:
> > > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen <
> > > > > > > > rickche...@gmail.com> wrote:
> > > > > > > > > Hi Anup
> > > > > > > > >
> > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen <
> > > > > > > > > > rickche...@gmail.com> wrote:
> > > > > > > > > > > Hi Anup
> > > > > > > > > > >
> > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel <
> > > > > > > > > > > > a...@brainfault.org> wrote:
> > > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen <
> > > > > > > > > > > > > rickche...@gmail.com> wrote:
> > > > > > > > > > > > > > Hi Anup
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen <
> > > > > > > > > > > > > > > rickche...@gmail.com> wrote:
> > > > > > > > > > > > > > > > Hi Anup
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup
> > > > > > > > > > > > > > > > > > Patel  wrote:
> > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM
> > > > > > > > > > > > > > > > > > > Alan Kao 
> > > > > > > > > > > > > > > > > > > wrote:
> > > > > > > > > > > > > > > > > > > > Hi Bin,
> > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > Thanks for the critics.  Comments
> > > > > > > > > > > > > > > > > > > > below.
> > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at
> > > > > > > > > > > > > > > > > > > > 06:38:00PM +0800, Bin Meng wrote:
> > > > > > > > > > > > > > > > > > > > > Hi Rick,
> > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50
> > > > > > > > > > > > > > > > > > > > > AM Rick Chen <
> > > > > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote:
> > > > > > > > > > > > > > > > > > > > > > Hi Bin
> > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > > Hi Rick,
> > > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at
> > > > > > > > > > > > > > > > > > > > > > > 2:18 PM Andes <
> > > > > > > > > > > > > > > > > > > > > > > ub...@andestech.com> wrote:
> > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen <
> > > > > > > > > > > > > > > > > > > > > > > > r...@andestech.com>
> > > > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to
> > > > > > > > > > > > > > > > > > > > > > > > hart 0 always will be
> > > > > > > > > > > > > > > > > > > > > > > > main
> > > > > > > > > > > > > > > > > > > > > > > > hart coincidentally. When
> > > > > > > > > > > > > > > > > > > > > > > > develop SPL flow, I try
> > > > > > > > > > > > > > > > > > > > > > > > to
> > > > > > > > > > > > > > > > > > > > > > > > force other harts to be
> > > > > > > > > > > > > > > > > > > > > > > > main hart. And it will go
> > > > > > > > > > > > > > > > > > > > > > > > wrong in sending IPI
> > > > > > > > > > > > > > > > > > > > > > > > flow. So fix it.
> > > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit
> > > > > > > > > > > > > > > > > > > > > > > contain 2 fixes, or just 1
> > > > > > > > > > > > > > > > > > > > > > > fix?
> > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But
> > > > > > > > > > > > > > > > > > > > > > they will cause one negative
> > > > > > > > > > > > > > > > > > > > > > result
> > > > > > > > > > > > > > > > > > > > > > that only hart 0 can send ipi
> > > > > > > > > > > > > > > > > > > > > > to other harts.
> > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart
> > > > > > > > > > > > > > > > > > > > > > > > can be main hart in U-
> > > > > > > > > > > > > > > > > > > > > > > > Boot SPL
> > > > > > > > > > > > > > > > > > > > > > > > theoretically, but it
> > > > > > > > > > > > > > > > > > > > > > > > still fail somewhere.
> > > > > > > > > > > > > > > > > > > > > > > > After dig in
> > > > > > > > > > > > > > > > > > > > > > > > and found there is an
> > > > > > > > > > > > > > > > > > > > > > > > assumption that hart 0
> > > > > > > > > > > > > > > > > > > > > > > > shall be
> > > > > > > > > > > > > > > > > > > > > > > > main hart in OpenSbi.
> > > > > > > > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > > > > > > > So does this mean there is
> > > > > > > > > > > > > > > > > > > > > > > a bug in OpenSBI too?
> > > > >

Re: [U-Boot] [PATCH v3 1/3] fdt: fix bcm283x dm-pre-reloc definitions

2019-11-07 Thread Heinrich Schuchardt


On 11/7/19 6:18 PM, matthias@kernel.org wrote:

From: Matthias Brugger

In commmit
143256b353 ("fdt: update bcm283x device tree sources to Linux 5.1-rc6 state")
we delete the label for the node soc. As we don't need the to add the


%s/delete/deleted/

The sentence starting with "As we don't" seems to be incomplete.

Best regards

Heinrich


property dm-pre-reloc to this node, we can delete it fomr
bcm283x-uboot.dtsi

Tested-by: Tom Rini  [RPi 3, 32b and 64b modes]
Signed-off-by: Matthias Brugger


___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [RFC 1/1] efi_loader: support building UEFI binaries on sandbox

2019-11-07 Thread Heinrich Schuchardt

On the sandbox the UEFI binaries must match the host architectures.

Adjust the Makefiles. Provide the PE/COFF header and relocation files.

Allow building helloworld.efi on the sandbox.

Signed-off-by: Heinrich Schuchardt 
---
include/host_arch.h provokes some false positives in checkpatch.pl as this
include is also meant to be used in Makefile.
---
 Makefile | 19 +
 arch/sandbox/config.mk   | 28 
 arch/sandbox/lib/crt0_sandbox_efi.S  | 32 
 arch/sandbox/lib/reloc_sandbox_efi.c | 32 
 cmd/Kconfig  |  2 +-
 include/host_arch.h  | 24 +
 lib/efi_loader/Makefile  |  3 +++
 7 files changed, 139 insertions(+), 1 deletion(-)
 create mode 100644 arch/sandbox/lib/crt0_sandbox_efi.S
 create mode 100644 arch/sandbox/lib/reloc_sandbox_efi.c
 create mode 100644 include/host_arch.h

diff --git a/Makefile b/Makefile
index a94b538e4a..41fdbfdfce 100644
--- a/Makefile
+++ b/Makefile
@@ -17,6 +17,25 @@ NAME =
 # o Look for make include files relative to root of kernel src
 MAKEFLAGS += -rR --include-dir=$(CURDIR)

+# Determine host architecture
+include include/host_arch.h
+MK_ARCH="${shell uname -m}"
+unexport HOST_ARCH
+ifeq ("x86_64", $(MK_ARCH))
+  export HOST_ARCH=$(HOST_ARCH_X86_64)
+else ifneq (,$(findstring $(MK_ARCH), "i386" "i486" "i586" "i686"))
+  export HOST_ARCH=$(HOST_ARCH_X86)
+else ifneq (,$(findstring $(MK_ARCH), "aarch64" "armv8l"))
+  export HOST_ARCH=$(HOST_ARCH_AARCH64)
+else ifeq ("armv7l", $(MK_ARCH))
+  export HOST_ARCH=$(HOST_ARCH_ARM)
+else ifeq ("riscv32", $(MK_ARCH))
+  export HOST_ARCH=$(HOST_ARCH_RISCV32)
+else ifeq ("riscv64", $(MK_ARCH))
+  export HOST_ARCH=$(HOST_ARCH_RISCV64)
+endif
+undefine MK_ARCH
+
 # Avoid funny character set dependencies
 unexport LC_ALL
 LC_COLLATE=C
diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
index 05fbbd7bcc..a225c9cbfa 100644
--- a/arch/sandbox/config.mk
+++ b/arch/sandbox/config.mk
@@ -27,3 +27,31 @@ cmd_u-boot-spl = (cd $(obj) && $(CC) -o $(SPL_BIN) -Wl,-T 
u-boot-spl.lds \
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot-spl.map -Wl,--gc-sections)

 CONFIG_ARCH_DEVICE_TREE := sandbox
+
+ifeq ($(HOST_ARCH),$(HOST_ARCH_X86_64))
+EFI_LDS := ${SRCDIR}/../../../arch/x86/lib/elf_x86_64_efi.lds
+EFI_TARGET := --target=efi-app-x86_64
+else ifeq ($(HOST_ARCH),$(HOST_ARCH_X86))
+EFI_LDS := ${SRCDIR}/../../../arch/x86/lib/elf_ia32_efi.lds
+EFI_TARGET := --target=efi-app-ia32
+else ifeq ($(HOST_ARCH),$(HOST_ARCH_AARCH64))
+EFI_LDS := ${SRCDIR}/../../../arch/arm/lib/elf_aarch64_efi.lds
+OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
+   -j .u_boot_list -j .rela.dyn -j .got -j .got.plt \
+   -j .binman_sym_table -j .text_rest \
+   -j .efi_runtime -j .efi_runtime_rel
+else ifeq ($(HOST_ARCH),$(HOST_ARCH_ARM))
+EFI_LDS := ${SRCDIR}/../../../arch/arm/lib/elf_arm_efi.lds
+OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
+   -j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn \
+   -j .binman_sym_table -j .text_rest \
+   -j .efi_runtime -j .efi_runtime_rel
+else ifeq ($(HOST_ARCH),$(HOST_ARCH_RISCV32))
+EFI_LDS := ${SRCDIR}/../../../arch/riscv/lib/elf_riscv32_efi.lds
+else ifeq ($(HOST_ARCH),$(HOST_ARCH_RISCV64))
+EFI_LDS := ${SRCDIR}/../../../arch/riscv/lib/elf_riscv64_efi.lds
+endif
+EFI_CRT0 := crt0_sandbox_efi.o
+EFI_RELOC := reloc_sandbox_efi.o
+AFLAGS_crt0_sandbox_efi.o += -DHOST_ARCH="$(HOST_ARCH)"
+CFLAGS_reloc_sandbox_efi.o += -DHOST_ARCH="$(HOST_ARCH)"
diff --git a/arch/sandbox/lib/crt0_sandbox_efi.S 
b/arch/sandbox/lib/crt0_sandbox_efi.S
new file mode 100644
index 00..b15766c514
--- /dev/null
+++ b/arch/sandbox/lib/crt0_sandbox_efi.S
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PE/COFF header for EFI applications
+ *
+ * Copyright (c) 2019 Heinrich Schuchardt
+ */
+
+#include 
+
+#if HOST_ARCH == HOST_ARCH_X86_64
+#include "../../../arch/x86/lib/crt0_x86_64_efi.S"
+#endif
+
+#if HOST_ARCH == HOST_ARCH_X86
+#include "../../../arch/x86/lib/crt0_ia32_efi.S"
+#endif
+
+#if HOST_ARCH == HOST_ARCH_AARCH64
+#include "../../../arch/arm/lib/crt0_aarch64_efi.S"
+#endif
+
+#if HOST_ARCH == HOST_ARCH_ARM
+#include "../../../arch/arm/lib/crt0_arm_efi.S"
+#endif
+
+#if HOST_ARCH == HOST_ARCH_RISCV32
+#include "../../../arch/riscv/lib/crt0_riscv_efi.S"
+#endif
+
+#if HOST_ARCH == HOST_ARCH_RISCV64
+#include "../../../arch/riscv/lib/crt0_riscv_efi.S"
+#endif
diff --git a/arch/sandbox/lib/reloc_sandbox_efi.c 
b/arch/sandbox/lib/reloc_sandbox_efi.c
new file mode 100644
index 00..a21e6757c5
--- /dev/null
+++ b/arch/sandbox/lib/reloc_sandbox_efi.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * position independent shared object relocator
+ *
+ * Copyright (c) 2019 Heinrich

Re: [U-Boot] [PATCH] include/env.h: Ensure ulong is defined

2019-11-07 Thread Tom Rini

On Tue, Nov 05, 2019 at 11:30:45AM -0800, Alistair Francis wrote:

> To fix these failures when building with musl:
>include/env.h:166:1: error: unknown type name 'ulong'; did you mean 'long'?
> ensure that ulong is defined.
> 
> Signed-off-by: Alistair Francis 
> ---
>  include/env.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/include/env.h b/include/env.h
> index b72239f6a5..5ca49a3456 100644
> --- a/include/env.h
> +++ b/include/env.h
> @@ -13,6 +13,8 @@
>  #include 
>  #include 
>  
> +typedef unsigned long   ulong;
> +
>  struct environment_s;
>  
>  /* Value for environment validity */

What exactly is the case you're hitting this under?   is
where we have that typedef.  I'd almost rather spell out unsigned long
in a few more places than add a typedef here, if we can't solve this via
correcting some include order or some other underlying problem.

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v2] armv8: fsl-layerscape: fix warning if no hwconfig is defined

2019-11-07 Thread Michael Walle


Am 2019-10-31 06:41, schrieb Pankaj Bansal:

if no hwconfig variable is defined for a platform and we try to get the
subarg of hwconfig, we receive a warning:
WARNING: Calling __hwconfig without a buffer and before environment is 
ready


Therefore, if hwconfig is not found return without further processing.

Signed-off-by: Pankaj Bansal 


Tested-by: Michael Walle 
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [RFC/RFT PATCH v3 2/3] image: Add a common compression type detection function.

2019-11-07 Thread Tom Rini

On Wed, Nov 06, 2019 at 02:15:21PM -0800, Atish Patra wrote:

> Currently, there is no method that can detect compression types
> given a file. This is very useful where a compressed kernel image
> is loaded directly to the memory.
> 
> Inspect initial few bytes to figure out compression type of the
> image. It will be used in booti method for now but can be reused
> any other function in future as well.
> 
> Signed-off-by: Atish Patra 

Reviewed-by: Tom Rini 

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [RFC/RFT PATCH v3 1/3] lib: kconfig: Add option to set BZIP2 compression method

2019-11-07 Thread Tom Rini

On Wed, Nov 06, 2019 at 02:15:20PM -0800, Atish Patra wrote:

> There is no way to select BZIP2 compression method.
> Add it under library/compression config where all other
> compression related configs are present.
> 
> Signed-off-by: Atish Patra 

With the note that when applying I need to run moveconfig.py on
CONFIG_BZIP2:

Reviewed-by: Tom Rini 

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [RFC/RFT PATCH v3 3/3] image: Add compressed Image parsing support in booti.

2019-11-07 Thread Tom Rini

On Wed, Nov 06, 2019 at 02:15:22PM -0800, Atish Patra wrote:

> Add compressed Image parsing support so that booti can parse both
> flat and compressed Image to boot Linux. Currently, it is difficult
> to calculate a safe address for every board where the compressed
> image can be decompressed. It is also not possible to figure out the
> size of the compressed file as well. Thus, user need to set two
> additional environment variables kernel_comp_addr_r and filesize to
> make this work.
> 
> Following compression methods are supported for now.
> lzma, lzo, bzip2, gzip.
> 
> lz4 support is not added as ARM64 kernel generates a lz4 compressed
> image with legacy header which U-Boot doesn't know how to parse and
> decompress.
> 
> Tested on HiFive Unleashed and Qemu for RISC-V.
> Tested on Qemu for ARM64.
> 
> Signed-off-by: Atish Patra 

Reviewed-by: Tom Rini 

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] armv8: fsl-layerscape: fix hwconfig and prefetching

2019-11-07 Thread Tom Rini

On Tue, Nov 05, 2019 at 11:32:05PM +0100, Michael Walle wrote:
> Am 2019-11-05 11:23, schrieb Priyanka Jain:
> > > -Original Message-
> > > From: U-Boot  On Behalf Of Michael Walle
> > > Sent: Tuesday, October 22, 2019 2:07 AM
> > > To: u-boot@lists.denx.de
> > > Cc: Tom Rini 
> > > Subject: [U-Boot] [PATCH] armv8: fsl-layerscape: fix hwconfig and
> > > prefetching
> > > 
> > > If CONFIG_HWCONFIG is disabled, hwconfig_subarg_f() will return the
> > > empty
> > > string, ie. not NULL. Therefore, we have to check the returned
> > > argument
> > > length as well as the return value.
> > > 
> > > Signed-off-by: Michael Walle 
> > > ---
> > > arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > > 
> > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > > b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > > index a5d0b5370f..4bb73b524c 100644
> > > --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > > @@ -1073,7 +1073,7 @@ static void config_core_prefetch(void)
> > >   prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
> > >, buf);
> > > 
> > > - if (prefetch_arg) {
> > > + if (arglen && prefetch_arg) {
> > >   mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
> > >   if (mask & 0x1) {
> > >   printf("Core0 prefetch can't be disabled\n");
> > > --
> > > 2.20.1
> > > 
> > Please check similar patch at http://patchwork.ozlabs.org/patch/1187188/
> > Does this solve your issue?
> 
> Yes that works, too. So my patch can be dropped.

Please reply to that thread with a Tested-by as well, if you like,
thanks!

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 1/2] arm: dts: rk3399-rockpro64: sync dts from linux kernel

2019-11-07 Thread Vasily Khoruzhick

On Thu, Nov 7, 2019 at 12:26 PM Soeren Moch  wrote:
>
> On 07.11.19 21:04, Vasily Khoruzhick wrote:
> > On Thu, Nov 7, 2019 at 3:11 AM Soeren Moch  wrote:
> >> The most important change for u-boot is the fix for the vdd-log pwm
> >> voltage regulator to avoid overvoltage for the VD_LOGIC power domain.
> > I don't see any changes to vdd-log regulator in this patch that can
> > help avoiding overvoltage. It just bumps regulator-max-microvolt to
> > 170.
> The duty-cycle of this pwm regulator is calculated from the min and max
> values. And with a max value that is set too low for the actual
> circuitry, a wrong duty-cycle is calculated that results in a higher
> voltage that what is set in regulator-init-microvolt.
> I measured the voltage on the board, with the original setting it was
> far above the allowed 1.0V, this patch fixes this, also see [1].

Thanks for explanation!

> Regards,
> Soeren
>
> [1] https://patchwork.kernel.org/patch/11173465/
> >
> >> Signed-off-by: Soeren Moch 
> >> ---
> >> Cc: Kever Yang 
> >> Cc: u-boot@lists.denx.de
> >> ---
> >>  arch/arm/dts/rk3399-rockpro64.dts | 57 ++-
> >>  1 file changed, 49 insertions(+), 8 deletions(-)
> >>
> >> diff --git a/arch/arm/dts/rk3399-rockpro64.dts 
> >> b/arch/arm/dts/rk3399-rockpro64.dts
> >> index 1f2394e058..e544deb61d 100644
> >> --- a/arch/arm/dts/rk3399-rockpro64.dts
> >> +++ b/arch/arm/dts/rk3399-rockpro64.dts
> >> @@ -58,6 +58,13 @@
> >> };
> >> };
> >>
> >> +   fan: pwm-fan {
> >> +   compatible = "pwm-fan";
> >> +   #cooling-cells = <2>;
> >> +   fan-supply = <_dcin>;
> >> +   pwms = < 0 5 0>;
> >> +   };
> >> +
> >> sdio_pwrseq: sdio-pwrseq {
> >> compatible = "mmc-pwrseq-simple";
> >> clocks = < 1>;
> >> @@ -166,7 +173,7 @@
> >> regulator-always-on;
> >> regulator-boot-on;
> >> regulator-min-microvolt = <80>;
> >> -   regulator-max-microvolt = <140>;
> >> +   regulator-max-microvolt = <170>;
> >> vin-supply = <_sys>;
> >> };
> >>  };
> >> @@ -222,6 +229,10 @@
> >> status = "okay";
> >>  };
> >>
> >> +_sound {
> >> +   status = "okay";
> >> +};
> >> +
> >>   {
> >> mali-supply = <_gpu>;
> >> status = "okay";
> >> @@ -236,8 +247,8 @@
> >> rk808: pmic@1b {
> >> compatible = "rockchip,rk808";
> >> reg = <0x1b>;
> >> -   interrupt-parent = <>;
> >> -   interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
> >> +   interrupt-parent = <>;
> >> +   interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
> >> #clock-cells = <1>;
> >> clock-output-names = "xin32k", "rk808-clkout2";
> >> pinctrl-names = "default";
> >> @@ -504,11 +515,25 @@
> >> status = "okay";
> >>
> >> bt656-supply = <_dvp>;
> >> -   audio-supply = <_codec>;
> >> +   audio-supply = <_3v0>;
> >> sdmmc-supply = <_sdio>;
> >> gpio1830-supply = <_3v0>;
> >>  };
> >>
> >> + {
> >> +   ep-gpios = < RK_PD4 GPIO_ACTIVE_HIGH>;
> >> +   num-lanes = <4>;
> >> +   pinctrl-names = "default";
> >> +   pinctrl-0 = <_perst>;
> >> +   vpcie12v-supply = <_dcin>;
> >> +   vpcie3v3-supply = <_pcie>;
> >> +   status = "okay";
> >> +};
> >> +
> >> +_phy {
> >> +   status = "okay";
> >> +};
> >> +
> >>  _io_domains {
> >> pmu1830-supply = <_3v0>;
> >> status = "okay";
> >> @@ -538,6 +563,10 @@
> >> };
> >>
> >> pcie {
> >> +   pcie_perst: pcie-perst {
> >> +   rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO 
> >> _pull_none>;
> >> +   };
> >> +
> >> pcie_pwr_en: pcie-pwr-en {
> >> rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO 
> >> _pull_none>;
> >> };
> >> @@ -545,7 +574,7 @@
> >>
> >> pmic {
> >> pmic_int_l: pmic-int-l {
> >> -   rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO 
> >> _pull_up>;
> >> +   rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO 
> >> _pull_up>;
> >> };
> >>
> >> vsel1_gpio: vsel1-gpio {
> >> @@ -580,6 +609,10 @@
> >> status = "okay";
> >>  };
> >>
> >> + {
> >> +   status = "okay";
> >> +};
> >> +
> >>   {
> >> status = "okay";
> >>  };
> >> @@ -591,7 +624,6 @@
> >>
> >>   {
> >> bus-width = <4>;
> >> -   cap-mmc-highspeed;
> >> cap-sd-highspeed;
> >> cd-gpios = < 7 GPIO_ACTIVE_LOW>;
> >> disable-wp;
> >> @@ -603,12 +635,21 @@
> >>
> >>   {
> >> bus-width = <8>;
> >> -   mmc-hs400-1_8v;
> >> -   mmc-hs400-enhanced-strobe;
> >> +   mmc-hs200-1_8v;
> >> non-removable;
> >> status = "okay";
> >>  };
> >>
> >> + {
> >> +   status =

Re: [U-Boot] [PATCH 1/2] arm: dts: rk3399-rockpro64: sync dts from linux kernel

2019-11-07 Thread Soeren Moch

On 07.11.19 21:04, Vasily Khoruzhick wrote:
> On Thu, Nov 7, 2019 at 3:11 AM Soeren Moch  wrote:
>> The most important change for u-boot is the fix for the vdd-log pwm
>> voltage regulator to avoid overvoltage for the VD_LOGIC power domain.
> I don't see any changes to vdd-log regulator in this patch that can
> help avoiding overvoltage. It just bumps regulator-max-microvolt to
> 170.
The duty-cycle of this pwm regulator is calculated from the min and max
values. And with a max value that is set too low for the actual
circuitry, a wrong duty-cycle is calculated that results in a higher
voltage that what is set in regulator-init-microvolt.
I measured the voltage on the board, with the original setting it was
far above the allowed 1.0V, this patch fixes this, also see [1].

Regards,
Soeren

[1] https://patchwork.kernel.org/patch/11173465/
>
>> Signed-off-by: Soeren Moch 
>> ---
>> Cc: Kever Yang 
>> Cc: u-boot@lists.denx.de
>> ---
>>  arch/arm/dts/rk3399-rockpro64.dts | 57 ++-
>>  1 file changed, 49 insertions(+), 8 deletions(-)
>>
>> diff --git a/arch/arm/dts/rk3399-rockpro64.dts 
>> b/arch/arm/dts/rk3399-rockpro64.dts
>> index 1f2394e058..e544deb61d 100644
>> --- a/arch/arm/dts/rk3399-rockpro64.dts
>> +++ b/arch/arm/dts/rk3399-rockpro64.dts
>> @@ -58,6 +58,13 @@
>> };
>> };
>>
>> +   fan: pwm-fan {
>> +   compatible = "pwm-fan";
>> +   #cooling-cells = <2>;
>> +   fan-supply = <_dcin>;
>> +   pwms = < 0 5 0>;
>> +   };
>> +
>> sdio_pwrseq: sdio-pwrseq {
>> compatible = "mmc-pwrseq-simple";
>> clocks = < 1>;
>> @@ -166,7 +173,7 @@
>> regulator-always-on;
>> regulator-boot-on;
>> regulator-min-microvolt = <80>;
>> -   regulator-max-microvolt = <140>;
>> +   regulator-max-microvolt = <170>;
>> vin-supply = <_sys>;
>> };
>>  };
>> @@ -222,6 +229,10 @@
>> status = "okay";
>>  };
>>
>> +_sound {
>> +   status = "okay";
>> +};
>> +
>>   {
>> mali-supply = <_gpu>;
>> status = "okay";
>> @@ -236,8 +247,8 @@
>> rk808: pmic@1b {
>> compatible = "rockchip,rk808";
>> reg = <0x1b>;
>> -   interrupt-parent = <>;
>> -   interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
>> +   interrupt-parent = <>;
>> +   interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
>> #clock-cells = <1>;
>> clock-output-names = "xin32k", "rk808-clkout2";
>> pinctrl-names = "default";
>> @@ -504,11 +515,25 @@
>> status = "okay";
>>
>> bt656-supply = <_dvp>;
>> -   audio-supply = <_codec>;
>> +   audio-supply = <_3v0>;
>> sdmmc-supply = <_sdio>;
>> gpio1830-supply = <_3v0>;
>>  };
>>
>> + {
>> +   ep-gpios = < RK_PD4 GPIO_ACTIVE_HIGH>;
>> +   num-lanes = <4>;
>> +   pinctrl-names = "default";
>> +   pinctrl-0 = <_perst>;
>> +   vpcie12v-supply = <_dcin>;
>> +   vpcie3v3-supply = <_pcie>;
>> +   status = "okay";
>> +};
>> +
>> +_phy {
>> +   status = "okay";
>> +};
>> +
>>  _io_domains {
>> pmu1830-supply = <_3v0>;
>> status = "okay";
>> @@ -538,6 +563,10 @@
>> };
>>
>> pcie {
>> +   pcie_perst: pcie-perst {
>> +   rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO 
>> _pull_none>;
>> +   };
>> +
>> pcie_pwr_en: pcie-pwr-en {
>> rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO 
>> _pull_none>;
>> };
>> @@ -545,7 +574,7 @@
>>
>> pmic {
>> pmic_int_l: pmic-int-l {
>> -   rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO 
>> _pull_up>;
>> +   rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO 
>> _pull_up>;
>> };
>>
>> vsel1_gpio: vsel1-gpio {
>> @@ -580,6 +609,10 @@
>> status = "okay";
>>  };
>>
>> + {
>> +   status = "okay";
>> +};
>> +
>>   {
>> status = "okay";
>>  };
>> @@ -591,7 +624,6 @@
>>
>>   {
>> bus-width = <4>;
>> -   cap-mmc-highspeed;
>> cap-sd-highspeed;
>> cd-gpios = < 7 GPIO_ACTIVE_LOW>;
>> disable-wp;
>> @@ -603,12 +635,21 @@
>>
>>   {
>> bus-width = <8>;
>> -   mmc-hs400-1_8v;
>> -   mmc-hs400-enhanced-strobe;
>> +   mmc-hs200-1_8v;
>> non-removable;
>> status = "okay";
>>  };
>>
>> + {
>> +   status = "okay";
>> +
>> +   flash@0 {
>> +   compatible = "jedec,spi-nor";
>> +   reg = <0>;
>> +   spi-max-frequency = <1000>;
>> +   };
>> +};
>> +
>>   {
>> status = "okay";
>>  };
>> --
>> 2.17.1
>>
>> ___
>> U-Boot mailing list
>> U-Boot@lists.denx.de
>> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] mx6cuboxi: Add Baruch as maintainer

2019-11-07 Thread Fabio Estevam

Add Baruch Siach as a mx6cuboxi maintainer.

Signed-off-by: Fabio Estevam 
---
 board/solidrun/mx6cuboxi/MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/solidrun/mx6cuboxi/MAINTAINERS 
b/board/solidrun/mx6cuboxi/MAINTAINERS
index 81f82bc9b5..bd098b479f 100644
--- a/board/solidrun/mx6cuboxi/MAINTAINERS
+++ b/board/solidrun/mx6cuboxi/MAINTAINERS
@@ -1,4 +1,5 @@
 MX6CUBOXI BOARD
+M: Baruch Siach 
 M: Fabio Estevam 
 S: Maintained
 F: board/solidrun/mx6cuboxi/
-- 
2.17.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v4 2/5] omap: mmc: Avoid using libfdt with of-platdata

2019-11-07 Thread Tom Rini

On Thu, Nov 07, 2019 at 08:53:09AM -0700, Simon Glass wrote:

> At present this driver is enabled in SPL on omapl138_lcdk, which uses
> of-platdata. The driver needs to be ported to use of-platdata properly.
> For now, avoid a build error by returning an error.
> 
> Signed-off-by: Simon Glass 
> 
> ---
> 
> Changes in v4:
> - Add new patch for omap MMC build errors
> 
> Changes in v3: None
> 
>  drivers/mmc/davinci_mmc.c | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c
> index 0d63279db0..79a7f50d25 100644
> --- a/drivers/mmc/davinci_mmc.c
> +++ b/drivers/mmc/davinci_mmc.c
> @@ -507,6 +507,12 @@ static int davinci_mmc_probe(struct udevice *dev)
>   priv->version = data->version;
>   }
>  
> + /* FIXME: Cannot read from device tree with of-platdata */
> + if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
> + printf("Please fix this driver to use of-platdata");
> + return -ENOSYS;
> + }
> +
>   priv->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
>   priv->input_clk = clk_get(DAVINCI_MMCSD_CLKID);

Let me add the board maintainer here.  Peter, are we even using MMC in
SPL on the omapl138_lcdk?  If so, I believe we need to add platdata ala
other platforms like board/ti/am335x/board.c for example.  Thanks!

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] net/phy: Fix phy_connect() for phy addr 0

2019-11-07 Thread Joe Hershberger

On Thu, Nov 7, 2019 at 1:16 PM Tom Rini  wrote:
>
> On Tue, Nov 05, 2019 at 04:05:11AM +, Priyanka Jain wrote:
>
> > Fix 'mask' calculation in phy_connect() for phy addr '0'.
> > 'mask' is getting set to '0x' for phy addr '0'
> > in phy_connect() whereas expected value is '0'.
> >
> >
> > Signed-off-by: Priyanka Jain 
>
> Reported-by: tetsu-aoki via github

Acked-by: Joe Hershberger 
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 1/2] arm: dts: rk3399-rockpro64: sync dts from linux kernel

2019-11-07 Thread Vasily Khoruzhick

On Thu, Nov 7, 2019 at 3:11 AM Soeren Moch  wrote:
>
> The most important change for u-boot is the fix for the vdd-log pwm
> voltage regulator to avoid overvoltage for the VD_LOGIC power domain.

I don't see any changes to vdd-log regulator in this patch that can
help avoiding overvoltage. It just bumps regulator-max-microvolt to
170.

> Signed-off-by: Soeren Moch 
> ---
> Cc: Kever Yang 
> Cc: u-boot@lists.denx.de
> ---
>  arch/arm/dts/rk3399-rockpro64.dts | 57 ++-
>  1 file changed, 49 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/dts/rk3399-rockpro64.dts 
> b/arch/arm/dts/rk3399-rockpro64.dts
> index 1f2394e058..e544deb61d 100644
> --- a/arch/arm/dts/rk3399-rockpro64.dts
> +++ b/arch/arm/dts/rk3399-rockpro64.dts
> @@ -58,6 +58,13 @@
> };
> };
>
> +   fan: pwm-fan {
> +   compatible = "pwm-fan";
> +   #cooling-cells = <2>;
> +   fan-supply = <_dcin>;
> +   pwms = < 0 5 0>;
> +   };
> +
> sdio_pwrseq: sdio-pwrseq {
> compatible = "mmc-pwrseq-simple";
> clocks = < 1>;
> @@ -166,7 +173,7 @@
> regulator-always-on;
> regulator-boot-on;
> regulator-min-microvolt = <80>;
> -   regulator-max-microvolt = <140>;
> +   regulator-max-microvolt = <170>;
> vin-supply = <_sys>;
> };
>  };
> @@ -222,6 +229,10 @@
> status = "okay";
>  };
>
> +_sound {
> +   status = "okay";
> +};
> +
>   {
> mali-supply = <_gpu>;
> status = "okay";
> @@ -236,8 +247,8 @@
> rk808: pmic@1b {
> compatible = "rockchip,rk808";
> reg = <0x1b>;
> -   interrupt-parent = <>;
> -   interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
> +   interrupt-parent = <>;
> +   interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
> #clock-cells = <1>;
> clock-output-names = "xin32k", "rk808-clkout2";
> pinctrl-names = "default";
> @@ -504,11 +515,25 @@
> status = "okay";
>
> bt656-supply = <_dvp>;
> -   audio-supply = <_codec>;
> +   audio-supply = <_3v0>;
> sdmmc-supply = <_sdio>;
> gpio1830-supply = <_3v0>;
>  };
>
> + {
> +   ep-gpios = < RK_PD4 GPIO_ACTIVE_HIGH>;
> +   num-lanes = <4>;
> +   pinctrl-names = "default";
> +   pinctrl-0 = <_perst>;
> +   vpcie12v-supply = <_dcin>;
> +   vpcie3v3-supply = <_pcie>;
> +   status = "okay";
> +};
> +
> +_phy {
> +   status = "okay";
> +};
> +
>  _io_domains {
> pmu1830-supply = <_3v0>;
> status = "okay";
> @@ -538,6 +563,10 @@
> };
>
> pcie {
> +   pcie_perst: pcie-perst {
> +   rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO 
> _pull_none>;
> +   };
> +
> pcie_pwr_en: pcie-pwr-en {
> rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO 
> _pull_none>;
> };
> @@ -545,7 +574,7 @@
>
> pmic {
> pmic_int_l: pmic-int-l {
> -   rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO _pull_up>;
> +   rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO _pull_up>;
> };
>
> vsel1_gpio: vsel1-gpio {
> @@ -580,6 +609,10 @@
> status = "okay";
>  };
>
> + {
> +   status = "okay";
> +};
> +
>   {
> status = "okay";
>  };
> @@ -591,7 +624,6 @@
>
>   {
> bus-width = <4>;
> -   cap-mmc-highspeed;
> cap-sd-highspeed;
> cd-gpios = < 7 GPIO_ACTIVE_LOW>;
> disable-wp;
> @@ -603,12 +635,21 @@
>
>   {
> bus-width = <8>;
> -   mmc-hs400-1_8v;
> -   mmc-hs400-enhanced-strobe;
> +   mmc-hs200-1_8v;
> non-removable;
> status = "okay";
>  };
>
> + {
> +   status = "okay";
> +
> +   flash@0 {
> +   compatible = "jedec,spi-nor";
> +   reg = <0>;
> +   spi-max-frequency = <1000>;
> +   };
> +};
> +
>   {
> status = "okay";
>  };
> --
> 2.17.1
>
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v4 4/5] dm: core: Don't include ofnode functions with of-platdata

2019-11-07 Thread Walter Lozano


Hi Simon,

Thanks for your patch.

On 7/11/19 12:53, Simon Glass wrote:

These functions cannot work with of-platdata since libfdt is not
available. At present when dev_read_...() functions are used it produces
error messages about ofnode which is confusing.

Adjust the Makefile and header to produce an error message for the actual
dev_read...() function which is called. This makes it easier to see what
code needs to be converted for use with of-platdata.

Signed-off-by: Simon Glass 
---

Changes in v4: None
Changes in v3:
- Fix eth_dev_get_mac_address() call dev_read...() only when available

  drivers/core/Makefile | 4 +++-
  include/dm/read.h | 3 +--
  net/eth-uclass.c  | 2 +-
  3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/core/Makefile b/drivers/core/Makefile
index bce7467da1..b9e4a2aab1 100644
--- a/drivers/core/Makefile
+++ b/drivers/core/Makefile
@@ -13,6 +13,8 @@ obj-$(CONFIG_OF_LIVE) += of_access.o of_addr.o
  ifndef CONFIG_DM_DEV_READ_INLINE
  obj-$(CONFIG_OF_CONTROL) += read.o
  endif
-obj-$(CONFIG_OF_CONTROL) += of_extra.o ofnode.o read_extra.o
+ifdef CONFIG_$(SPL_TPL_)OF_LIBFDT
+obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += of_extra.o ofnode.o read_extra.o
+endif
  
  ccflags-$(CONFIG_DM_DEBUG) += -DDEBUG

diff --git a/include/dm/read.h b/include/dm/read.h
index d37fcb504d..4f02d07d00 100644
--- a/include/dm/read.h
+++ b/include/dm/read.h
@@ -43,8 +43,7 @@ static inline bool dev_of_valid(struct udevice *dev)
return ofnode_valid(dev_ofnode(dev));
  }
  
-#ifndef CONFIG_DM_DEV_READ_INLINE

-
+#if !defined(CONFIG_DM_DEV_READ_INLINE) || CONFIG_IS_ENABLED(OF_PLATDATA)
  /**
   * dev_read_u32() - read a 32-bit integer from a device's DT property
   *



I don't know if it has much sense, but as I understand it should be 
possible to use DM without OF_CONTROL by adding U_BOOT_DEVICE entries 
manually in a board file. Probably this won't be useful in mainline but 
still could be useful in some contexts. If this is true maybe this 
condition should be changed. In other words why not use 
!CONFIG_IS_ENABLED(CONFIG_OF_LIBFDT) instead of 
CONFIG_IS_ENABLED(OF_PLATDATA)?




diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index 3bd98b01ad..e3bfcdb6cc 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -462,7 +462,7 @@ static int eth_pre_unbind(struct udevice *dev)
  
  static bool eth_dev_get_mac_address(struct udevice *dev, u8 mac[ARP_HLEN])

  {
-#if IS_ENABLED(CONFIG_OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL)
const uint8_t *p;
  
  	p = dev_read_u8_array_ptr(dev, "mac-address", ARP_HLEN);



Should this kind of #if be changed to

#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)

Regards,

Walter

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH V2 2/3] watchdog: designware: Convert to DM and DT probing

2019-11-07 Thread Marek Vasut

On 11/7/19 8:30 PM, Simon Goldschmidt wrote:
[...]

>> diff --git a/include/configs/socfpga_stratix10_socdk.h
>> b/include/configs/socfpga_stratix10_socdk.h
>> index 353e08f982..0c0c27000a 100644
>> --- a/include/configs/socfpga_stratix10_socdk.h
>> +++ b/include/configs/socfpga_stratix10_socdk.h
>> @@ -161,6 +161,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>>    * L4 Watchdog
>>    */
>>   #ifdef CONFIG_SPL_BUILD
>> +#undef CONFIG_WATCHDOG
> 
> I somehow missed this series.
> Why is this line here?

To avoid using DM watchdog in SPL on S10.
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH V2 2/3] watchdog: designware: Convert to DM and DT probing

2019-11-07 Thread Simon Goldschmidt


Am 03.10.2019 um 14:59 schrieb Marek Vasut:

Convert the designware watchdog timer driver to DM and add DT probing
support. Perform minor coding style clean up, like drop superfluous
braces. There ought to be no functional change.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dalon Westergreen 
Cc: Dinh Nguyen 
Cc: Jagan Teki 
Cc: Ley Foon Tan 
Cc: Philipp Tomisch 
Cc: Simon Goldschmidt 
Cc: Tien Fong Chee 
---
V2: - Support both DM and non-DM probing
 - Fix watchdog stop handling by setting CR bit
---
  configs/socfpga_stratix10_defconfig   |   2 +
  configs/socfpga_vining_fpga_defconfig |   1 +
  drivers/watchdog/Kconfig  |   2 +-
  drivers/watchdog/designware_wdt.c | 122 ++
  include/configs/socfpga_stratix10_socdk.h |   1 +
  5 files changed, 104 insertions(+), 24 deletions(-)

diff --git a/configs/socfpga_stratix10_defconfig 
b/configs/socfpga_stratix10_defconfig
index 462082b67b..752fa545bd 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -57,3 +57,5 @@ CONFIG_DM_USB=y
  CONFIG_USB_DWC2=y
  CONFIG_USB_STORAGE=y
  CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_WDT=y
+# CONFIG_SPL_WDT is not set
diff --git a/configs/socfpga_vining_fpga_defconfig 
b/configs/socfpga_vining_fpga_defconfig
index 03c43fa8b9..def7a3eca7 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -91,4 +91,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
  CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
  CONFIG_USB_GADGET_DWC2_OTG=y
  CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_WDT=y
  CONFIG_DESIGNWARE_WATCHDOG=y
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 6fd9b0a177..bfb91af947 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -38,7 +38,7 @@ config ULP_WATCHDOG
  
  config DESIGNWARE_WATCHDOG

bool "Designware watchdog timer support"
-   select HW_WATCHDOG
+   select HW_WATCHDOG if !WDT
help
   Enable this to support Designware Watchdog Timer IP, present e.g.
   on Altera SoCFPGA SoCs.
diff --git a/drivers/watchdog/designware_wdt.c 
b/drivers/watchdog/designware_wdt.c
index c668567c66..a7b735979a 100644
--- a/drivers/watchdog/designware_wdt.c
+++ b/drivers/watchdog/designware_wdt.c
@@ -4,7 +4,8 @@
   */
  
  #include 

-#include 
+#include 
+#include 
  #include 
  #include 
  
@@ -17,46 +18,51 @@

  #define DW_WDT_CR_RMOD_VAL0x00
  #define DW_WDT_CRR_RESTART_VAL0x76
  
+struct designware_wdt_priv {

+   void __iomem*base;
+};
+
  /*
   * Set the watchdog time interval.
   * Counter is 32 bit.
   */
-static int designware_wdt_settimeout(unsigned int timeout)
+static int designware_wdt_settimeout(void __iomem *base, unsigned int clk_khz,
+unsigned int timeout)
  {
signed int i;
  
  	/* calculate the timeout range value */

-   i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16;
-   if (i > 15)
-   i = 15;
-   if (i < 0)
-   i = 0;
+   i = log_2_n_round_up(timeout * clk_khz) - 16;
+   i = clamp(i, 0, 15);
+
+   writel(i | (i << 4), base + DW_WDT_TORR);
  
-	writel((i | (i << 4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR));

return 0;
  }
  
-static void designware_wdt_enable(void)

+static void designware_wdt_enable(void __iomem *base)
  {
-   writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |
- (0x1 << DW_WDT_CR_EN_OFFSET)),
- (CONFIG_DW_WDT_BASE + DW_WDT_CR));
+   writel((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |
+   BIT(DW_WDT_CR_EN_OFFSET),
+   base + DW_WDT_CR);
  }
  
-static unsigned int designware_wdt_is_enabled(void)

+static unsigned int designware_wdt_is_enabled(void __iomem *base)
  {
-   unsigned long val;
-   val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));
-   return val & 0x1;
+   return readl(base + DW_WDT_CR) & BIT(0);
  }
  
-#if defined(CONFIG_HW_WATCHDOG)

-void hw_watchdog_reset(void)
+static void designware_wdt_reset_common(void __iomem *base)
  {
-   if (designware_wdt_is_enabled())
+   if (designware_wdt_is_enabled(base))
/* restart the watchdog counter */
-   writel(DW_WDT_CRR_RESTART_VAL,
-  (CONFIG_DW_WDT_BASE + DW_WDT_CRR));
+   writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
+}
+
+#if !CONFIG_IS_ENABLED(WDT)
+void hw_watchdog_reset(void)
+{
+   designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE);
  }
  
  void hw_watchdog_init(void)

@@ -64,10 +70,80 @@ void hw_watchdog_init(void)
/* reset to disable the watchdog */
hw_watchdog_reset();
/* set timer in miliseconds */
-   designware_wdt_settimeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
+   designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
+ CONFIG_DW_WDT_CLOCK_KHZ,
+

Re: [U-Boot] Issues when saving environment in RK399 RockPI 4

2019-11-07 Thread Fabio Estevam

Hi Ezequiel,

On Thu, Nov 7, 2019 at 3:45 PM Ezequiel Garcia
 wrote:
>
> I decided to test latest U-Boot, following instructions in
> doc/README.rockchip. The instructions seemed
> clear and I could build this easily.
>
> However, there seems to be an issue when I save the environment. Any ideas?
>
> => saveenv
> Saving Environment to MMC... Writing to MMC(0)... OK
> => reset
> resetting ...
> U-Boot TPL 2020.01-rc1-00213-g0f282c1876af-dirty (Nov 07 2019 - 15:21:44)
> Trying to boot from BOOTROM
> Returning to boot ROM...
>
> U-Boot SPL 2020.01-rc1-00213-g0f282c1876af-dirty (Nov 07 2019 - 15:21:44 
> -0300)
> Trying to boot from MMC2
>
>
> U-Boot 2020.01-rc1-00213-g0f282c1876af-dirty (Nov 07 2019 - 15:21:44 -0300)
>
> Model: Radxa ROCK Pi 4
> DRAM:  2 GiB
> Cannot find regulator pwm init_voltage
> MMC:   dwmmc@fe32: 1, sdhci@fe33: 0
> Loading Environment from MMC... OK
> In:serial@ff1a
> Out:   serial@ff1a
> Err:   serial@ff1a
> Model: Radxa ROCK Pi 4
> ## Error: Can't overwrite "serial#"
> ## Error inserting "serial#" variable, errno=1
> initcall sequence 7ffc10b8 failed at call 00202a20 (err=-1)
> ### ERROR ### Please RESET the board ###

I have observed issues like this with i.MX when U-Boot size grew and
overlapped the environment variable region.

Here is one commit that fixed the issue for mx53loco board:
https://gitlab.denx.de/u-boot/u-boot/commit/033f6ea5fa5fce63d52c8c2b63d8284144415b88

Try to investigate if this could be cause of the issue you are seeing.

Regards,

Fabio Estevam
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH V2 1/3] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig

2019-11-07 Thread Simon Goldschmidt


Am 03.10.2019 um 14:59 schrieb Marek Vasut:

Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig and update the headers
accordingly, no functional change. The S10 enables the WDT only in
SPL, but does not enable it in U-Boot itself, hence disable it in
the config again.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dalon Westergreen 
Cc: Dinh Nguyen 
Cc: Jagan Teki 
Cc: Ley Foon Tan 
Cc: Philipp Tomisch 
Cc: Simon Goldschmidt 
Cc: Tien Fong Chee 


Reviewed-by: Simon Goldschmidt 


---
V2: Use non-DM watchdog in SPL on S10
---
  configs/socfpga_stratix10_defconfig   | 1 +
  configs/socfpga_vining_fpga_defconfig | 1 +
  drivers/watchdog/Kconfig  | 7 +++
  include/configs/socfpga_common.h  | 3 ---
  include/configs/socfpga_stratix10_socdk.h | 6 --
  scripts/config_whitelist.txt  | 1 -
  6 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/configs/socfpga_stratix10_defconfig 
b/configs/socfpga_stratix10_defconfig
index ad83f50032..462082b67b 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -56,3 +56,4 @@ CONFIG_USB=y
  CONFIG_DM_USB=y
  CONFIG_USB_DWC2=y
  CONFIG_USB_STORAGE=y
+CONFIG_DESIGNWARE_WATCHDOG=y
diff --git a/configs/socfpga_vining_fpga_defconfig 
b/configs/socfpga_vining_fpga_defconfig
index 96f806ab5f..03c43fa8b9 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -91,3 +91,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
  CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
  CONFIG_USB_GADGET_DWC2_OTG=y
  CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DESIGNWARE_WATCHDOG=y
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index a66a9bcbe2..6fd9b0a177 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -36,6 +36,13 @@ config ULP_WATCHDOG
help
  Say Y here to enable i.MX7ULP watchdog driver.
  
+config DESIGNWARE_WATCHDOG

+   bool "Designware watchdog timer support"
+   select HW_WATCHDOG
+   help
+  Enable this to support Designware Watchdog Timer IP, present e.g.
+  on Altera SoCFPGA SoCs.
+
  config WDT
bool "Enable driver model for watchdog timer drivers"
depends on DM
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index b11fe021a7..32b9131be0 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -104,12 +104,9 @@
  /*
   * L4 Watchdog
   */
-#ifdef CONFIG_HW_WATCHDOG
-#define CONFIG_DESIGNWARE_WATCHDOG
  #define CONFIG_DW_WDT_BASESOCFPGA_L4WD0_ADDRESS
  #define CONFIG_DW_WDT_CLOCK_KHZ   25000
  #define CONFIG_WATCHDOG_TIMEOUT_MSECS 3
-#endif
  
  /*

   * MMC Driver
diff --git a/include/configs/socfpga_stratix10_socdk.h 
b/include/configs/socfpga_stratix10_socdk.h
index 7b55dd14da..353e08f982 100644
--- a/include/configs/socfpga_stratix10_socdk.h
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -162,14 +162,16 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
   */
  #ifdef CONFIG_SPL_BUILD
  #define CONFIG_HW_WATCHDOG
-#define CONFIG_DESIGNWARE_WATCHDOG
+#else
+#undef CONFIG_HW_WATCHDOG
+#undef CONFIG_DESIGNWARE_WATCHDOG
+#endif
  #define CONFIG_DW_WDT_BASESOCFPGA_L4WD0_ADDRESS
  #ifndef __ASSEMBLY__
  unsigned int cm_get_l4_sys_free_clk_hz(void);
  #define CONFIG_DW_WDT_CLOCK_KHZ   (cm_get_l4_sys_free_clk_hz() / 
1000)
  #endif
  #define CONFIG_WATCHDOG_TIMEOUT_MSECS 3000
-#endif
  
  /*

   * SPL memory layout
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index b18eab1707..839eda8c0f 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -320,7 +320,6 @@ CONFIG_DEFAULT_IMMR
  CONFIG_DEF_HWCONFIG
  CONFIG_DELAY_ENVIRONMENT
  CONFIG_DESIGNWARE_ETH
-CONFIG_DESIGNWARE_WATCHDOG
  CONFIG_DEVELOP
  CONFIG_DEVICE_TREE_LIST
  CONFIG_DFU_ALT



___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [RFC PATCH] dm: core: Remove libfdt dependency when unnecessary

2019-11-07 Thread Walter Lozano


Hi Simon,

On 7/11/19 13:42, Simon Glass wrote:

Hi Walter,

On Thu, 7 Nov 2019 at 06:30, Walter Lozano  wrote:

Hi Ezequiel,

On 5/11/19 20:30, Ezequiel Garcia wrote:

On Tue, 5 Nov 2019 at 15:12, Walter Lozano  wrote:

Hi Ezequiel,

On 5/11/19 13:56, Ezequiel Garcia wrote:

Hello Walter,

Thanks for the patch.

On Tue, 5 Nov 2019 at 12:27, Walter Lozano  wrote:

The support of libfdt should only be needed when OF_CONTROL
is enabled and OF_PLATDATA is not, as in other cases there is no
DT file to query.

This patch fixes this dependency allowing to save some space.


Can you add some more information about the space saving?

Sure, I will add some additional information about the static footprint.
However according to my understanding the impact depends on how well
different drivers supports features like OF_PLATDATA. For instance, in
my current configuration it saves 2 KB.


Not sure I follow you. This patch adds a condition which adds/removes code
based on some conditions. So, it should depend on the arch, but otherwise
the reduction is an invariant as it just depend on the size of the
code that is being
added/removed. Or am I missing something?


The idea behind this patch is to break the dependency of libfdt when it
is not needed. A specific example of this is found when building SPL
using OF_PLATDATA, which basically removes DT so there is no sense of
having libfdt present in SPL. Unfortunately as OF_PLATDATA has little
support, drivers tend to assume that there is a DT and try to query
different properties, which of course return no data. In this context,
the idea is to keep the same behavior but reducing the SPL size, while
trying to improve drivers.

I actually sent a similar patch in September but never fixed the
problems it caused. I just resent it as a series:

http://patchwork.ozlabs.org/project/uboot/list/?series=141416



Thanks for pointing to this patchset, it looks like the approach I was 
looking for to overcome the the issue with libfdt and other dependencies 
in a proper way. I'll try to use your same approach in other drivers.





[..]

Regards,
Simon



Regards,


Walter

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] xilinx: Do defconfig syncup

2019-11-07 Thread Tom Rini

On Thu, Nov 07, 2019 at 02:37:21PM +0100, Michal Simek wrote:

> Sync up defconfigs according to latest Kconfig dependencies.
> 
> Signed-off-by: Michal Simek 

I'll take this as a reminder to moveconfig -s everyone, thanks!

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] Buildman Kconfig issue with consecutive builds

2019-11-07 Thread Simon Glass

Hi Schrempf,

On Thu, 7 Nov 2019 at 12:14, Schrempf Frieder 
wrote:

> Hi Simon,
>
> On 07.11.19 17:23, Simon Glass wrote:
> > Hi Schrempf,
> >
> > On Thu, 7 Nov 2019 at 08:15, Schrempf Frieder
> >  wrote:
> >>
> >> On 07.11.19 15:02, Bin Meng wrote:
> >>> Hi Frieder,
> >>>
> >>> On Thu, Nov 7, 2019 at 9:28 PM Schrempf Frieder
> >>>  wrote:
> 
>  Hi Bin,
> 
>  On 07.11.19 13:41, Bin Meng wrote:
> > Hi Schrempf,
> >
> > On Thu, Nov 7, 2019 at 12:17 AM Schrempf Frieder
> >  wrote:
> >>
> >> Hi,
> >>
> >> I'm having some trouble using buildman to test the impact of some
> >> Kconfig cleanup patches ([1]).
> >>
> >> The patches introduce a new CONFIG_SPL_* option and I try to find
> out
> >> which defconfigs need to be fixed, by comparing build sizes.
> >>
> >> Now when I added a patch to fix a defconfig I noticed that buildman
> >> wouldn't report the expected size changes and upon looking more
> closely
> >> I found that the added Kconfig options are still missing in
> u-boot-spl.cfg.
> >>
> >> The strange thing is, that when I try to build only the last commit
> then
> >> the Kconfig options are there, which is why I suspect a bug in
> buildman
> >> not handling Kconfig changes correctly with consecutive builds.
> >>
> >> Can anyone have a look what is wrong or how I can debug this issue?
> >>
> >> The issue can be reproduced with the branch at [1], running:
> >>
> >> buildman -b spi_flash_kconfig_cleanup_3 --step 0 xilinx_zynqmp_virt
> >>
> >
> > Could you please add "-C" to the buildman command line and have a
> try?
> 
>  Indeed forcing the reconfig between the build steps with '-C' fixes
> the
>  issue.
> 
>  Is it a known problem, that buildman doesn't handle Kconfig changes
>  correctly without '-C' in some cases?
> >>>
> >>> AFAIK, this is an intended design of calling buildman w/o '-C' to save
> >>> some build time.
> >>
> >> Ok, if that's the case I will try to come up with a patch that adds a
> >> note to the README. This has cost me a few hours because I was thinking
> >> buildman does the right thing and Kconfig options are messed up
> somewhere.
> >
> > An incremental build means that it does not run 'make xxx_defconfig'
> > on every commit. Doing it this way saves *a lot* of time for large
> > builds and the main purpose of buildman is to validate that U-Boot
> > builds.
> >
> > However it might be possible to have it both ways...the code fragment
> > below compares the Kconfig files and configs/ directory against the
> > data of the 'u-boot' output file, and could trigger a full rebuild if
> > newer.
>
> Ok, thanks for the explanation.
>
> >
> > If you have time (sounds like you do!), you could incorporate that
> > into buildman.
>
> It's kind of funny that you got the impression, that I have time ;)
> Actually I do not have much time to work on U-Boot in general among all
> the other things.
>
> And now I went deep down into the rabbit hole from "I want to get some
> boards upstreamed" to "I need to port a QSPI controller driver first" to
> "the driver port affects existing CONFIG options that are a total mess
> and need to be fixed" to "I need to run buildman on my cleanup patches"
> to "buildman could need some tweaking".
>
> So unless there will be a lot of rainy weekends, I probably won't start
> working on optimizing buildman ;)
>

May you be plagued with downpours :-)

- Simon
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] net/phy: Fix phy_connect() for phy addr 0

2019-11-07 Thread Tom Rini

On Tue, Nov 05, 2019 at 04:05:11AM +, Priyanka Jain wrote:

> Fix 'mask' calculation in phy_connect() for phy addr '0'.
> 'mask' is getting set to '0x' for phy addr '0'
> in phy_connect() whereas expected value is '0'.
> 
> 
> Signed-off-by: Priyanka Jain 

Reported-by: tetsu-aoki via github

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] Buildman Kconfig issue with consecutive builds

2019-11-07 Thread Schrempf Frieder

Hi Simon,

On 07.11.19 17:23, Simon Glass wrote:
> Hi Schrempf,
> 
> On Thu, 7 Nov 2019 at 08:15, Schrempf Frieder
>  wrote:
>>
>> On 07.11.19 15:02, Bin Meng wrote:
>>> Hi Frieder,
>>>
>>> On Thu, Nov 7, 2019 at 9:28 PM Schrempf Frieder
>>>  wrote:

 Hi Bin,

 On 07.11.19 13:41, Bin Meng wrote:
> Hi Schrempf,
>
> On Thu, Nov 7, 2019 at 12:17 AM Schrempf Frieder
>  wrote:
>>
>> Hi,
>>
>> I'm having some trouble using buildman to test the impact of some
>> Kconfig cleanup patches ([1]).
>>
>> The patches introduce a new CONFIG_SPL_* option and I try to find out
>> which defconfigs need to be fixed, by comparing build sizes.
>>
>> Now when I added a patch to fix a defconfig I noticed that buildman
>> wouldn't report the expected size changes and upon looking more closely
>> I found that the added Kconfig options are still missing in 
>> u-boot-spl.cfg.
>>
>> The strange thing is, that when I try to build only the last commit then
>> the Kconfig options are there, which is why I suspect a bug in buildman
>> not handling Kconfig changes correctly with consecutive builds.
>>
>> Can anyone have a look what is wrong or how I can debug this issue?
>>
>> The issue can be reproduced with the branch at [1], running:
>>
>> buildman -b spi_flash_kconfig_cleanup_3 --step 0 xilinx_zynqmp_virt
>>
>
> Could you please add "-C" to the buildman command line and have a try?

 Indeed forcing the reconfig between the build steps with '-C' fixes the
 issue.

 Is it a known problem, that buildman doesn't handle Kconfig changes
 correctly without '-C' in some cases?
>>>
>>> AFAIK, this is an intended design of calling buildman w/o '-C' to save
>>> some build time.
>>
>> Ok, if that's the case I will try to come up with a patch that adds a
>> note to the README. This has cost me a few hours because I was thinking
>> buildman does the right thing and Kconfig options are messed up somewhere.
> 
> An incremental build means that it does not run 'make xxx_defconfig'
> on every commit. Doing it this way saves *a lot* of time for large
> builds and the main purpose of buildman is to validate that U-Boot
> builds.
> 
> However it might be possible to have it both ways...the code fragment
> below compares the Kconfig files and configs/ directory against the
> data of the 'u-boot' output file, and could trigger a full rebuild if
> newer.

Ok, thanks for the explanation.

> 
> If you have time (sounds like you do!), you could incorporate that
> into buildman.

It's kind of funny that you got the impression, that I have time ;)
Actually I do not have much time to work on U-Boot in general among all 
the other things.

And now I went deep down into the rabbit hole from "I want to get some 
boards upstreamed" to "I need to port a QSPI controller driver first" to 
"the driver port affects existing CONFIG options that are a total mess 
and need to be fixed" to "I need to run buildman on my cleanup patches" 
to "buildman could need some tweaking".

So unless there will be a lot of rainy weekends, I probably won't start 
working on optimizing buildman ;)

Regards,
Frieder

> 
> files = ['%s/u-boot' % outdir]
>if os.path.exists(files[0]):
>  if options.incremental:
>cmd = ['find', 'configs/', '-cnewer', files[0]]
>result = cros_build_lib.RunCommand(cmd, capture_output=True, **kwargs)
>if result.output:
>  logging.warning('config/ dir has changed - dropping -i')
>  options.incremental = False
> 
>  if options.incremental:
>cmd = ['find', '.', '-name', 'Kconfig', '-and', '-cnewer', files[0]]
>result = cros_build_lib.RunCommand(cmd, capture_output=True, **kwargs)
>if result.output:
>  logging.warning('Kconfig file(s) changed - dropping -i')
>  options.incremental = False
> 
> 
> The current logic is in RunJob() and do_config is the thing that
> causes a reconfig.
> 
> Regards,
> Simon
> 
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] Issues when saving environment in RK399 RockPI 4

2019-11-07 Thread Ezequiel Garcia

I decided to test latest U-Boot, following instructions in
doc/README.rockchip. The instructions seemed
clear and I could build this easily.

However, there seems to be an issue when I save the environment. Any ideas?

=> saveenv
Saving Environment to MMC... Writing to MMC(0)... OK
=> reset
resetting ...
U-Boot TPL 2020.01-rc1-00213-g0f282c1876af-dirty (Nov 07 2019 - 15:21:44)
Trying to boot from BOOTROM
Returning to boot ROM...

U-Boot SPL 2020.01-rc1-00213-g0f282c1876af-dirty (Nov 07 2019 - 15:21:44 -0300)
Trying to boot from MMC2


U-Boot 2020.01-rc1-00213-g0f282c1876af-dirty (Nov 07 2019 - 15:21:44 -0300)

Model: Radxa ROCK Pi 4
DRAM:  2 GiB
Cannot find regulator pwm init_voltage
MMC:   dwmmc@fe32: 1, sdhci@fe33: 0
Loading Environment from MMC... OK
In:serial@ff1a
Out:   serial@ff1a
Err:   serial@ff1a
Model: Radxa ROCK Pi 4
## Error: Can't overwrite "serial#"
## Error inserting "serial#" variable, errno=1
initcall sequence 7ffc10b8 failed at call 00202a20 (err=-1)
### ERROR ### Please RESET the board ###
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations

2019-11-07 Thread Atish Patra

On Thu, 2019-11-07 at 19:41 +0800, Rick Chen wrote:
> Hi Anup & Lukas
> 
> Anup Patel  於 2019年11月7日 週四 下午6:44寫道：
> > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas
> >  wrote:
> > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote:
> > > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen  > > > > wrote:
> > > > > Hi Anup
> > > > > 
> > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel <
> > > > > > a...@brainfault.org> wrote:
> > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen <
> > > > > > > rickche...@gmail.com> wrote:
> > > > > > > > Hi Anup
> > > > > > > > 
> > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen <
> > > > > > > > > rickche...@gmail.com> wrote:
> > > > > > > > > > Hi Anup
> > > > > > > > > > 
> > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel <
> > > > > > > > > > > a...@brainfault.org> wrote:
> > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen <
> > > > > > > > > > > > rickche...@gmail.com> wrote:
> > > > > > > > > > > > > Hi Anup
> > > > > > > > > > > > > 
> > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen <
> > > > > > > > > > > > > > rickche...@gmail.com> wrote:
> > > > > > > > > > > > > > > Hi Anup
> > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup
> > > > > > > > > > > > > > > > > Patel  wrote:
> > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM
> > > > > > > > > > > > > > > > > > Alan Kao 
> > > > > > > > > > > > > > > > > > wrote:
> > > > > > > > > > > > > > > > > > > Hi Bin,
> > > > > > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > > > > > Thanks for the critics.  Comments
> > > > > > > > > > > > > > > > > > > below.
> > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at
> > > > > > > > > > > > > > > > > > > 06:38:00PM +0800, Bin Meng wrote:
> > > > > > > > > > > > > > > > > > > > Hi Rick,
> > > > > > > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50
> > > > > > > > > > > > > > > > > > > > AM Rick Chen <
> > > > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote:
> > > > > > > > > > > > > > > > > > > > > Hi Bin
> > > > > > > > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > > > > > > > > Hi Rick,
> > > > > > > > > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at
> > > > > > > > > > > > > > > > > > > > > > 2:18 PM Andes <
> > > > > > > > > > > > > > > > > > > > > > ub...@andestech.com> wrote:
> > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen <
> > > > > > > > > > > > > > > > > > > > > > > r...@andestech.com>
> > > > > > > > > > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > > > > > > > > > It will work fine due to
> > > > > > > > > > > > > > > > > > > > > > > hart 0 always will be
> > > > > > > > > > > > > > > > > > > > > > > main
> > > > > > > > > > > > > > > > > > > > > > > hart coincidentally. When
> > > > > > > > > > > > > > > > > > > > > > > develop SPL flow, I try
> > > > > > > > > > > > > > > > > > > > > > > to
> > > > > > > > > > > > > > > > > > > > > > > force other harts to be
> > > > > > > > > > > > > > > > > > > > > > > main hart. And it will go
> > > > > > > > > > > > > > > > > > > > > > > wrong in sending IPI
> > > > > > > > > > > > > > > > > > > > > > > flow. So fix it.
> > > > > > > > > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit
> > > > > > > > > > > > > > > > > > > > > > contain 2 fixes, or just 1
> > > > > > > > > > > > > > > > > > > > > > fix?
> > > > > > > > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But
> > > > > > > > > > > > > > > > > > > > > they will cause one negative
> > > > > > > > > > > > > > > > > > > > > result
> > > > > > > > > > > > > > > > > > > > > that only hart 0 can send ipi
> > > > > > > > > > > > > > > > > > > > > to other harts.
> > > > > > > > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart
> > > > > > > > > > > > > > > > > > > > > > > can be main hart in U-
> > > > > > > > > > > > > > > > > > > > > > > Boot SPL
> > > > > > > > > > > > > > > > > > > > > > > theoretically, but it
> > > > > > > > > > > > > > > > > > > > > > > still fail somewhere.
> > > > > > > > > > > > > > > > > > > > > > > After dig in
> > > > > > > > > > > > > > > > > > > > > > > and found there is an
> > > > > > > > > > > > > > > > > > > > > > > assumption that hart 0
> > > > > > > > > > > > > > > > > > > > > > > shall be
> > > > > > > > > > > > > > > > > > > > > > > main hart in OpenSbi.
> > > > > > > > > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > > > > > > > > So does this mean there is
> > > > > > > > > > > > > > > > > > > > > > a bug in OpenSBI too?
> > > > > > > > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > > > > > > > I am not sure if it is a bug.
> > > > > > > > > > > > > > > > > > > > > Maybe it is a compatible
> > > >

Re: [U-Boot] [RFC PATCH] dm: core: Remove libfdt dependency when unnecessary

2019-11-07 Thread Tom Rini

On Tue, Nov 05, 2019 at 01:56:00PM -0300, Ezequiel Garcia wrote:
> Hello Walter,
> 
> Thanks for the patch.
> 
> On Tue, 5 Nov 2019 at 12:27, Walter Lozano  
> wrote:
> >
> > The support of libfdt should only be needed when OF_CONTROL
> > is enabled and OF_PLATDATA is not, as in other cases there is no
> > DT file to query.
> >
> > This patch fixes this dependency allowing to save some space.
> >
> 
> Can you add some more information about the space saving?
> The ./scripts/bloat-o-meter will help you get some info
> on static footprint.

Note that in U-Boot, we can as good or better information via buildman.
The --bloat flag gives a lot of useful info about what functions
grew/shrunk in addition to a section size summary.

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH V2 2/3] watchdog: designware: Convert to DM and DT probing

2019-11-07 Thread Marek Vasut

On 10/4/19 11:26 AM, Ley Foon Tan wrote:
> On Thu, Oct 3, 2019 at 9:00 PM Marek Vasut wrote:
>>
>> Convert the designware watchdog timer driver to DM and add DT probing
>> support. Perform minor coding style clean up, like drop superfluous
>> braces. There ought to be no functional change.
> 
> All watchdog DT nodes with compatible "snps,dw-wdt" need to add
> "u-boot,dm-pre-reloc;".

Only those boards which actually use the WDT, right ? That is, these two
boards below.

>> ---
>> V2: - Support both DM and non-DM probing
>> - Fix watchdog stop handling by setting CR bit
>> ---
>>  configs/socfpga_stratix10_defconfig   |   2 +
>>  configs/socfpga_vining_fpga_defconfig |   1 +
> 
> Same here. All socfpga defconfig files need to add CONFIG_WDT.

Only those two, since only those two boards enable the WDT, no ?

[...]

>>  void hw_watchdog_init(void)
>> @@ -64,10 +70,80 @@ void hw_watchdog_init(void)
>> /* reset to disable the watchdog */
>> hw_watchdog_reset();
>> /* set timer in miliseconds */
>> -   designware_wdt_settimeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
>> +   designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
>> + CONFIG_DW_WDT_CLOCK_KHZ,
>> + CONFIG_WATCHDOG_TIMEOUT_MSECS);
>> /* enable the watchdog */
>> -   designware_wdt_enable();
>> +   designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE);
>> /* reset the watchdog */
>> hw_watchdog_reset();
> 
> In my "arm: socfpga: Convert drivers from struct to defines" patch
> series, I have moved spl_early_init() to the beginning of
> spl_board_f().
> So, DM framework is initialized in early stage, you should able to use
> DM for watchdog in SPL too.
> But, maybe need to add a wrapper function to probe watchdog device and
> start watchdog. Something like this:
> 
> uclass_get_device(UCLASS_WDT, 0, );
> wdt_start(dev, CONFIG_WATCHDOG_TIMEOUT_MSECS, 0);

Except this driver is not used only on SoCFPGA.
So the question is, with your conversion series, will there be boards
left which use non-DM version of this WDT driver ?

>>  }
>> +#else
>> +static int designware_wdt_reset(struct udevice *dev)
>> +{
>> +   struct designware_wdt_priv *priv = dev_get_priv(dev);
>> +
>> +   designware_wdt_reset_common(priv->base);
>> +
>> +   return 0;
>> +}
>> +
>> +static int designware_wdt_stop(struct udevice *dev)
>> +{
>> +   struct designware_wdt_priv *priv = dev_get_priv(dev);
>> +
>> +   designware_wdt_reset(dev);
>> +   writel(DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET,
>> +   priv->base + DW_WDT_CR);
> 
> Still no fixing clear BIT(DW_WDT_CR_EN_OFFSET) in CR register to
> disable watchdog.

I guess we an just write 0 to the CR register and get rid of RMOD_VAL
altogether ?

>> +
>> +   return 0;
>> +}
>> +
>> +static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong 
>> flags)
>> +{
>> +   struct designware_wdt_priv *priv = dev_get_priv(dev);
>> +
>> +   designware_wdt_stop(dev);
>> +
>> +   /* set timer in miliseconds */
>> +   designware_wdt_settimeout(priv->base, CONFIG_DW_WDT_CLOCK_KHZ, 
>> timeout);
>> +
>> +   designware_wdt_enable(priv->base);
>> +
>> +   /* reset the watchdog */
>> +   return designware_wdt_reset(dev);
>> +}
>> +
>> +static int designware_wdt_probe(struct udevice *dev)
>> +{
>> +   struct designware_wdt_priv *priv = dev_get_priv(dev);
>> +
> 
> Need de-assert watchdog reset using reset framework function, 
> reset_get_bulk().

Ah yes, and make it presumably optional.

[...]
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH V2 1/3] watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig

2019-11-07 Thread Marek Vasut

On 10/11/19 11:51 AM, Ley Foon Tan wrote:
> On Thu, Oct 10, 2019 at 3:47 PM Marek Vasut wrote:
>>
>> On 10/10/19 8:28 AM, Ley Foon Tan wrote:
>>> On Fri, Oct 4, 2019 at 7:04 PM Marek Vasut wrote:

 On 10/4/19 10:59 AM, Ley Foon Tan wrote:
> On Thu, Oct 3, 2019 at 9:00 PM Marek Vasut wrote:
>>
>> Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig and update the headers
>> accordingly, no functional change. The S10 enables the WDT only in
>> SPL, but does not enable it in U-Boot itself, hence disable it in
>> the config again.
>> ---
>> V2: Use non-DM watchdog in SPL on S10
>> ---
>>  configs/socfpga_stratix10_defconfig   | 1 +
>>  configs/socfpga_vining_fpga_defconfig | 1 +
>
> All socfpga deconfig files need to add CONFIG_DESIGNWARE_WATCHDOG too.
> socfpga_common.h is used by Gen5 and A10 platform.

 Only those which defined CONFIG_HW_WATCHDOG need to enable the
 CONFIG_DESIGNWARE_WATCHDOG, right ? (see below)
>>>
>>> $ git grep socfpga_common.h
>>> include/configs/socfpga_arria10_socdk.h:#include 
>>> include/configs/socfpga_arria5_socdk.h:#include 
>>> include/configs/socfpga_cyclone5_socdk.h:#include 
>>> include/configs/socfpga_dbm_soc1.h:#include 
>>> include/configs/socfpga_de0_nano_soc.h:#include 
>>> include/configs/socfpga_de10_nano.h:#include 
>>> include/configs/socfpga_de1_soc.h:#include 
>>> include/configs/socfpga_is1.h:#include 
>>> include/configs/socfpga_mcvevk.h:#include 
>>> include/configs/socfpga_sockit.h:#include 
>>> include/configs/socfpga_socrates.h:#include 
>>> include/configs/socfpga_sr1500.h:#include 
>>> include/configs/socfpga_vining_fpga.h:#include 
>>>
>>> These platforms include socfpga_common.h file, so their _defconfig
>>> need to update too.
>>
>> They don't enable HW_WATCHDOG, so it doesn't ... or ?
> Sorry, I see wrongly. I thought HW_WATCHDOG is defined in socfpga_common.h.
> Then no problem now.

Sorry for the late reply.

Are we OK with this patch then ?
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] pull request u-boot-mpc85xx

2019-11-07 Thread Tom Rini

On Thu, Nov 07, 2019 at 04:01:45AM +, Priyanka Jain wrote:

> Dear Tom,
> 
> Please find my pull-request for u-boot-mpc85xx/master
> https://travis-ci.org/p-priyanka-jain/u-boot/builds/608129628
> 
> Summary
> mpc85xx,socrates:  Add dts, enable DM support,
> fix warnings, disable video
> 
> 
> priyankajain
> 

Applied to u-boot/master, thanks!

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] common/console.c: Fix unused warning with console_doenv()

2019-11-07 Thread Tom Rini

On Wed, Oct 30, 2019 at 09:18:43AM -0400, Tom Rini wrote:

> Newer versions of LLVM-7 will provide an unused function warning over
> console_doenv() in the case of SYS_CONSOLE_IS_IN_ENV not being enabled
> as can be the case in SPL.  Add guards around this function.
> 
> Signed-off-by: Tom Rini 

Applied to u-boot/master, thanks!

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] gitlab/azure: Enable LLVM tests

2019-11-07 Thread Tom Rini

On Wed, Nov 06, 2019 at 07:30:47PM -0500, Tom Rini wrote:

> Now that we have again fixed the problems that building with clang
> exposes, enable these tests on Azure and GitLab-CI as well.
> 
> Signed-off-by: Tom Rini 

Applied to u-boot/master, thanks!

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] travis: Fix the clang-7 test

2019-11-07 Thread Tom Rini

On Sat, Oct 26, 2019 at 01:48:41PM -0400, Tom Rini wrote:

> When using the OVERRIDE variable we need to pass -O to buildman as well
> to use the "override" option to buildman.
> 
> Fixed: e9500f49ea35 ("travis: Use buildman for building with clang")
> Signed-off-by: Tom Rini 

Applied to u-boot/master, thanks!

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v3 3/3] drivers: bcm283x: Set pre-location flag for OF_BOARD

2019-11-07 Thread matthias . bgg

From: Matthias Brugger 

U-Boot support on Raspberry Pi 4 relies on the device-tree
provided by the firmware. The blob does not contain the
U-Boot specific pre-loc-rel properties. The result is, that
the U-Boot banner is not printed.

We fix this by setting the DM_FLAG_PRE_RELOC flag in the driver,
if we rely on a device-tree provided by the firmware.

Reported-by: Heinrich Schuchardt 
Signed-off-by: Matthias Brugger 

---

Changes in v3: None
Changes in v2:
- add DM_FLAG_PRE_RELOC for RPi4 case

 drivers/pinctrl/broadcom/pinctrl-bcm283x.c | 2 +-
 drivers/serial/serial_bcm283x_mu.c | 2 +-
 drivers/serial/serial_bcm283x_pl011.c  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c 
b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
index 3be080d29e..1bb91d6eed 100644
--- a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
+++ b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
@@ -148,7 +148,7 @@ U_BOOT_DRIVER(pinctrl_bcm283x) = {
.priv_auto_alloc_size = sizeof(struct bcm283x_pinctrl_priv),
.ops= _pinctrl_ops,
.probe  = bcm283x_pinctl_probe,
-#if !CONFIG_IS_ENABLED(OF_CONTROL)
+#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD)
.flags  = DM_FLAG_PRE_RELOC,
 #endif
 };
diff --git a/drivers/serial/serial_bcm283x_mu.c 
b/drivers/serial/serial_bcm283x_mu.c
index bd1d89ec83..a6ffc84b96 100644
--- a/drivers/serial/serial_bcm283x_mu.c
+++ b/drivers/serial/serial_bcm283x_mu.c
@@ -199,7 +199,7 @@ U_BOOT_DRIVER(serial_bcm283x_mu) = {
.platdata_auto_alloc_size = sizeof(struct bcm283x_mu_serial_platdata),
.probe = bcm283x_mu_serial_probe,
.ops = _mu_serial_ops,
-#if !CONFIG_IS_ENABLED(OF_CONTROL)
+#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD)
.flags = DM_FLAG_PRE_RELOC,
 #endif
.priv_auto_alloc_size = sizeof(struct bcm283x_mu_priv),
diff --git a/drivers/serial/serial_bcm283x_pl011.c 
b/drivers/serial/serial_bcm283x_pl011.c
index 2527bb8b1c..7d8ab7b716 100644
--- a/drivers/serial/serial_bcm283x_pl011.c
+++ b/drivers/serial/serial_bcm283x_pl011.c
@@ -90,7 +90,7 @@ U_BOOT_DRIVER(bcm283x_pl011_uart) = {
.platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
.probe  = pl01x_serial_probe,
.ops= _pl011_serial_ops,
-#if !CONFIG_IS_ENABLED(OF_CONTROL)
+#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD)
.flags  = DM_FLAG_PRE_RELOC,
 #endif
.priv_auto_alloc_size = sizeof(struct pl01x_priv),
-- 
2.23.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v3 1/3] fdt: fix bcm283x dm-pre-reloc definitions

2019-11-07 Thread matthias . bgg

From: Matthias Brugger 

In commmit
143256b353 ("fdt: update bcm283x device tree sources to Linux 5.1-rc6 state")
we delete the label for the node soc. As we don't need the to add the
property dm-pre-reloc to this node, we can delete it fomr
bcm283x-uboot.dtsi

Tested-by: Tom Rini  [RPi 3, 32b and 64b modes]
Signed-off-by: Matthias Brugger 

---

Changes in v3:
- add tested-by tag

Changes in v2:
- node soc, does not need a label
- dm-pre-reloc not needed for node soc

 arch/arm/dts/bcm283x-uboot.dtsi | 4 
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/dts/bcm283x-uboot.dtsi b/arch/arm/dts/bcm283x-uboot.dtsi
index 6cc1aa3f93..36548dad62 100644
--- a/arch/arm/dts/bcm283x-uboot.dtsi
+++ b/arch/arm/dts/bcm283x-uboot.dtsi
@@ -6,10 +6,6 @@
  * (C) Copyright 2016 Fabian Vogt 
  */
 
- {
-   u-boot,dm-pre-reloc;
-};
-
  {
skip-init;
u-boot,dm-pre-reloc;
-- 
2.23.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v2 1/3] fdt: fix bcm283x dm-pre-reloc definitions

2019-11-07 Thread Tom Rini

On Thu, Nov 07, 2019 at 05:43:35PM +0100, matthias@kernel.org wrote:

> From: Matthias Brugger 
> 
> In commmit
> 143256b353 ("fdt: update bcm283x device tree sources to Linux 5.1-rc6 state")
> we delete the label for the node soc. As we don't need the to add the
> property dm-pre-reloc to this node, we can delete it fomr
> bcm283x-uboot.dtsi
> 
> Signed-off-by: Matthias Brugger 
> 

Tested-by: Tom Rini  [RPi 3, 32b and 64b modes]

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v2 3/3] drivers: bcm283x: Set pre-location flag for OF_BOARD

2019-11-07 Thread matthias . bgg

From: Matthias Brugger 

U-Boot support on Raspberry Pi 4 relies on the device-tree
provided by the firmware. The blob does not contain the
U-Boot specific pre-loc-rel properties. The result is, that
the U-Boot banner is not printed.

We fix this by setting the DM_FLAG_PRE_RELOC flag in the driver,
if we rely on a device-tree provided by the firmware.

Signed-off-by: Matthias Brugger 

---

Changes in v2:
- add DM_FLAG_PRE_RELOC for RPi4 case

 drivers/pinctrl/broadcom/pinctrl-bcm283x.c | 2 +-
 drivers/serial/serial_bcm283x_mu.c | 2 +-
 drivers/serial/serial_bcm283x_pl011.c  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c 
b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
index 3be080d29e..1bb91d6eed 100644
--- a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
+++ b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
@@ -148,7 +148,7 @@ U_BOOT_DRIVER(pinctrl_bcm283x) = {
.priv_auto_alloc_size = sizeof(struct bcm283x_pinctrl_priv),
.ops= _pinctrl_ops,
.probe  = bcm283x_pinctl_probe,
-#if !CONFIG_IS_ENABLED(OF_CONTROL)
+#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD)
.flags  = DM_FLAG_PRE_RELOC,
 #endif
 };
diff --git a/drivers/serial/serial_bcm283x_mu.c 
b/drivers/serial/serial_bcm283x_mu.c
index bd1d89ec83..a6ffc84b96 100644
--- a/drivers/serial/serial_bcm283x_mu.c
+++ b/drivers/serial/serial_bcm283x_mu.c
@@ -199,7 +199,7 @@ U_BOOT_DRIVER(serial_bcm283x_mu) = {
.platdata_auto_alloc_size = sizeof(struct bcm283x_mu_serial_platdata),
.probe = bcm283x_mu_serial_probe,
.ops = _mu_serial_ops,
-#if !CONFIG_IS_ENABLED(OF_CONTROL)
+#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD)
.flags = DM_FLAG_PRE_RELOC,
 #endif
.priv_auto_alloc_size = sizeof(struct bcm283x_mu_priv),
diff --git a/drivers/serial/serial_bcm283x_pl011.c 
b/drivers/serial/serial_bcm283x_pl011.c
index 2527bb8b1c..7d8ab7b716 100644
--- a/drivers/serial/serial_bcm283x_pl011.c
+++ b/drivers/serial/serial_bcm283x_pl011.c
@@ -90,7 +90,7 @@ U_BOOT_DRIVER(bcm283x_pl011_uart) = {
.platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
.probe  = pl01x_serial_probe,
.ops= _pl011_serial_ops,
-#if !CONFIG_IS_ENABLED(OF_CONTROL)
+#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD)
.flags  = DM_FLAG_PRE_RELOC,
 #endif
.priv_auto_alloc_size = sizeof(struct pl01x_priv),
-- 
2.23.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v2 1/3] fdt: fix bcm283x dm-pre-reloc definitions

2019-11-07 Thread matthias . bgg

From: Matthias Brugger 

In commmit
143256b353 ("fdt: update bcm283x device tree sources to Linux 5.1-rc6 state")
we delete the label for the node soc. As we don't need the to add the
property dm-pre-reloc to this node, we can delete it fomr
bcm283x-uboot.dtsi

Signed-off-by: Matthias Brugger 

---

Changes in v2:
- node soc, does not need a label
- dm-pre-reloc not needed for node soc

 arch/arm/dts/bcm283x-uboot.dtsi | 4 
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/dts/bcm283x-uboot.dtsi b/arch/arm/dts/bcm283x-uboot.dtsi
index 6cc1aa3f93..36548dad62 100644
--- a/arch/arm/dts/bcm283x-uboot.dtsi
+++ b/arch/arm/dts/bcm283x-uboot.dtsi
@@ -6,10 +6,6 @@
  * (C) Copyright 2016 Fabian Vogt 
  */
 
- {
-   u-boot,dm-pre-reloc;
-};
-
  {
skip-init;
u-boot,dm-pre-reloc;
-- 
2.23.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [RFC PATCH] dm: core: Remove libfdt dependency when unnecessary

2019-11-07 Thread Simon Glass

Hi Walter,

On Thu, 7 Nov 2019 at 06:30, Walter Lozano  wrote:
>
> Hi Ezequiel,
>
> On 5/11/19 20:30, Ezequiel Garcia wrote:
> > On Tue, 5 Nov 2019 at 15:12, Walter Lozano  
> > wrote:
> >> Hi Ezequiel,
> >>
> >> On 5/11/19 13:56, Ezequiel Garcia wrote:
> >>> Hello Walter,
> >>>
> >>> Thanks for the patch.
> >>>
> >>> On Tue, 5 Nov 2019 at 12:27, Walter Lozano  
> >>> wrote:
>  The support of libfdt should only be needed when OF_CONTROL
>  is enabled and OF_PLATDATA is not, as in other cases there is no
>  DT file to query.
> 
>  This patch fixes this dependency allowing to save some space.
> 
> >>> Can you add some more information about the space saving?
> >>
> >> Sure, I will add some additional information about the static footprint.
> >> However according to my understanding the impact depends on how well
> >> different drivers supports features like OF_PLATDATA. For instance, in
> >> my current configuration it saves 2 KB.
> >>
> > Not sure I follow you. This patch adds a condition which adds/removes code
> > based on some conditions. So, it should depend on the arch, but otherwise
> > the reduction is an invariant as it just depend on the size of the
> > code that is being
> > added/removed. Or am I missing something?
>
>
> The idea behind this patch is to break the dependency of libfdt when it
> is not needed. A specific example of this is found when building SPL
> using OF_PLATDATA, which basically removes DT so there is no sense of
> having libfdt present in SPL. Unfortunately as OF_PLATDATA has little
> support, drivers tend to assume that there is a DT and try to query
> different properties, which of course return no data. In this context,
> the idea is to keep the same behavior but reducing the SPL size, while
> trying to improve drivers.

I actually sent a similar patch in September but never fixed the
problems it caused. I just resent it as a series:

http://patchwork.ozlabs.org/project/uboot/list/?series=141416

[..]

Regards,
Simon
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] fdt: fix bcm283x dm-pre-reloc definitions

2019-11-07 Thread Matthias Brugger



On 07/11/2019 14:51, Tom Rini wrote:
> On Thu, Nov 07, 2019 at 02:30:13PM +0100, matthias@kernel.org wrote:
> 
>> From: Matthias Brugger 
>>
>> In commmit
>> 143256b353 ("fdt: update bcm283x device tree sources to Linux 5.1-rc6 state")
>> we accidently deleted the inclution of bcm283x-uboot.dtsi which
>> marks, soc, uarts and pincontroller as dm-pre-reloc
>>
>> Without this definitions the first call to
>> bcm283x_mu_serial_ofdata_to_platdata() fails as the pins are not set
>> correctly. As a result the U-Boot banner isn't shown on boot.
>>
>> Reported-by: Tom Rini 
>> Reported-by: Heinrich Schuchardt 
>> Signed-off-by: Matthias Brugger 
>>
>> ---
>>
>>  arch/arm/dts/bcm283x.dtsi | 4 +++-
>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/dts/bcm283x.dtsi b/arch/arm/dts/bcm283x.dtsi
>> index 9777644c6c..39d7bd600e 100644
>> --- a/arch/arm/dts/bcm283x.dtsi
>> +++ b/arch/arm/dts/bcm283x.dtsi
>> @@ -51,7 +51,7 @@
>>  };
>>  };
>>  
>> -soc {
>> +soc: soc {
>>  compatible = "simple-bus";
>>  #address-cells = <1>;
>>  #size-cells = <1>;
> 
> Is that part needed?
> 

I verified that this is not needed.
Will update in v2.

>> @@ -675,3 +675,5 @@
>>  #phy-cells = <0>;
>>  };
>>  };
>> +
>> +#include "bcm283x-uboot.dtsi"
> 
> This means one of the general rules we have in:
> u_boot_dtsi_options = $(strip $(wildcard $(dir $<)$(basename $(notdir 
> $<))-u-boot.dtsi) \
> $(wildcard $(dir $<)$(subst $\",,$(CONFIG_SYS_SOC))-u-boot.dtsi) \
> $(wildcard $(dir $<)$(subst $\",,$(CONFIG_SYS_CPU))-u-boot.dtsi) \
> $(wildcard $(dir $<)$(subst $\",,$(CONFIG_SYS_VENDOR))-u-boot.dtsi) \
> $(wildcard $(dir $<)u-boot.dtsi))
> 
> isn't being hit and we should probably rename the file (or set
> CONFIG_SYS_SOC differently?).
> 

Good catch. I'll send a v2 which fixes this by renaming the file.

Regards,
Matthias
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] Revert "binman: Correct symbol calculation with non-zero image base"

2019-11-07 Thread Stephen Warren


On 11/5/19 9:21 AM, Stephen Warren wrote:

From: Stephen Warren 

This reverts commit 15c981cc8adc26501e3a19ca7fb35705870ef597.
"binman: Correct symbol calculation with non-zero image base". This
was previously reported to break initial boot on Jetson TK1, and Simon
dropped the patch from his branch. However, it seems to have shown up
again in a pull request somehow. Revert it until the problem is fixed.


We can drop this and replace it with Simon's "[PATCH] binman: tegra: 
Adjust symbol calculation depending on end-at-4gb". That patch fixes the 
same bug, but without reverting the change.

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] binman: tegra: Adjust symbol calculation depending on end-at-4gb

2019-11-07 Thread Stephen Warren


On 11/6/19 5:22 PM, Simon Glass wrote:

A recent change adjusted the symbol calculation to work on x86 but broke
it for Tegra. In fact this is because they have different needs.

On x86 devices the code is linked to a ROM address and the end-at-4gb
property is used for the image. In this case there is no need to add the
base address of the image, since the base address is already built into
the offset and image-pos properties.

On other devices we must add the base address since the offsets start at
zero.

In addition the base address is currently added to the 'offset' and 'size'
values. It should in fact only be added to 'image-pos', since 'offset' is
relative to its parent and 'size' is not actually an address. This code
should have been adjusted when support for 'image-pos' and 'size' was
added, but it was not.

To correct these problems:
- move the code that handles adding the base address to section.py, which
   can check the end-at-4gb property and which property
   (offset/size/image-pos) is being read
- add the base address only when needed (only for image-pos and not if the
   image uses end-at-4gb)
- add a note to the documentation
- add a separate test to cover x86 behaviour

Fixes: 15c981cc (binman: Correct symbol calculation with non-zero image base)


Tested-by: Stephen Warren 
Thanks!
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] Buildman Kconfig issue with consecutive builds

2019-11-07 Thread Simon Glass

Hi Schrempf,

On Thu, 7 Nov 2019 at 08:15, Schrempf Frieder
 wrote:
>
> On 07.11.19 15:02, Bin Meng wrote:
> > Hi Frieder,
> >
> > On Thu, Nov 7, 2019 at 9:28 PM Schrempf Frieder
> >  wrote:
> >>
> >> Hi Bin,
> >>
> >> On 07.11.19 13:41, Bin Meng wrote:
> >>> Hi Schrempf,
> >>>
> >>> On Thu, Nov 7, 2019 at 12:17 AM Schrempf Frieder
> >>>  wrote:
> 
>  Hi,
> 
>  I'm having some trouble using buildman to test the impact of some
>  Kconfig cleanup patches ([1]).
> 
>  The patches introduce a new CONFIG_SPL_* option and I try to find out
>  which defconfigs need to be fixed, by comparing build sizes.
> 
>  Now when I added a patch to fix a defconfig I noticed that buildman
>  wouldn't report the expected size changes and upon looking more closely
>  I found that the added Kconfig options are still missing in 
>  u-boot-spl.cfg.
> 
>  The strange thing is, that when I try to build only the last commit then
>  the Kconfig options are there, which is why I suspect a bug in buildman
>  not handling Kconfig changes correctly with consecutive builds.
> 
>  Can anyone have a look what is wrong or how I can debug this issue?
> 
>  The issue can be reproduced with the branch at [1], running:
> 
>  buildman -b spi_flash_kconfig_cleanup_3 --step 0 xilinx_zynqmp_virt
> 
> >>>
> >>> Could you please add "-C" to the buildman command line and have a try?
> >>
> >> Indeed forcing the reconfig between the build steps with '-C' fixes the
> >> issue.
> >>
> >> Is it a known problem, that buildman doesn't handle Kconfig changes
> >> correctly without '-C' in some cases?
> >
> > AFAIK, this is an intended design of calling buildman w/o '-C' to save
> > some build time.
>
> Ok, if that's the case I will try to come up with a patch that adds a
> note to the README. This has cost me a few hours because I was thinking
> buildman does the right thing and Kconfig options are messed up somewhere.

An incremental build means that it does not run 'make xxx_defconfig'
on every commit. Doing it this way saves *a lot* of time for large
builds and the main purpose of buildman is to validate that U-Boot
builds.

However it might be possible to have it both ways...the code fragment
below compares the Kconfig files and configs/ directory against the
data of the 'u-boot' output file, and could trigger a full rebuild if
newer.

If you have time (sounds like you do!), you could incorporate that
into buildman.

files = ['%s/u-boot' % outdir]
  if os.path.exists(files[0]):
if options.incremental:
  cmd = ['find', 'configs/', '-cnewer', files[0]]
  result = cros_build_lib.RunCommand(cmd, capture_output=True, **kwargs)
  if result.output:
logging.warning('config/ dir has changed - dropping -i')
options.incremental = False

if options.incremental:
  cmd = ['find', '.', '-name', 'Kconfig', '-and', '-cnewer', files[0]]
  result = cros_build_lib.RunCommand(cmd, capture_output=True, **kwargs)
  if result.output:
logging.warning('Kconfig file(s) changed - dropping -i')
options.incremental = False


The current logic is in RunJob() and do_config is the thing that
causes a reconfig.

Regards,
Simon
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] patman: Fix cc-cmd option for Python 3

2019-11-07 Thread Simon Glass

The Python 3 conversion doesn't work correctly with the new patch to use
NUL as the separator in the CC file.

Fix this by avoiding encoding the CC list written to the file.

Signed-off-by: Simon Glass 
---

 tools/patman/patman.py | 2 +-
 tools/patman/series.py | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/patman/patman.py b/tools/patman/patman.py
index cf53e532dd..ca209c276d 100755
--- a/tools/patman/patman.py
+++ b/tools/patman/patman.py
@@ -107,7 +107,7 @@ elif options.test:
 # Called from git with a patch filename as argument
 # Printout a list of additional CC recipients for this patch
 elif options.cc_cmd:
-fd = open(options.cc_cmd, 'r')
+fd = open(options.cc_cmd, 'r', encoding='utf-8')
 re_line = re.compile('(\S*) (.*)')
 for line in fd.readlines():
 match = re_line.match(line)
diff --git a/tools/patman/series.py b/tools/patman/series.py
index 02a1113ad0..a15f7625ed 100644
--- a/tools/patman/series.py
+++ b/tools/patman/series.py
@@ -251,7 +251,7 @@ class Series(dict):
 cover_cc = [tools.FromUnicode(m) for m in cover_cc]
 cc_list = '\0'.join([tools.ToUnicode(x)
  for x in sorted(set(cover_cc + all_ccs))])
-print(cover_fname, cc_list.encode('utf-8'), file=fd)
+print(cover_fname, cc_list, file=fd)
 
 fd.close()
 return fname
-- 
2.24.0.rc1.363.gb1bccd3e3d-goog

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v2 2/2] freescale/powerpc: Rename the config CONFIG_SECURE_BOOT name.

2019-11-07 Thread Udit Agarwal

Renames the CONFIG_SECURE_BOOT name to CONFIG_NXP_ESBC to avoid
conflicts with UEFI secure boot.

Signed-off-by: Udit Agarwal 
---
Changes in V2:
Rebase on top of master branch.

 arch/powerpc/cpu/mpc85xx/Kconfig   |  4 ++--
 arch/powerpc/cpu/mpc85xx/cpu_init.c|  8 
 arch/powerpc/cpu/mpc85xx/start.S   | 10 +-
 arch/powerpc/cpu/mpc8xxx/law.c |  4 ++--
 arch/powerpc/include/asm/fsl_secure_boot.h |  4 ++--
 board/freescale/common/p_corenet/tlb.c |  2 +-
 board/freescale/t104xrdb/tlb.c |  4 ++--
 configs/B4860QDS_SECURE_BOOT_defconfig |  2 +-
 configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig |  2 +-
 configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig |  2 +-
 configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig  |  2 +-
 configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig  |  2 +-
 configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig   |  2 +-
 configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig   |  2 +-
 configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig |  2 +-
 configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig |  2 +-
 configs/C29XPCIE_NOR_SECBOOT_defconfig |  2 +-
 configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig|  2 +-
 configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig   |  2 +-
 configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig|  2 +-
 configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig   |  2 +-
 configs/P1010RDB-PA_NAND_SECBOOT_defconfig |  2 +-
 configs/P1010RDB-PA_NOR_SECBOOT_defconfig  |  2 +-
 configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig |  2 +-
 configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig   |  2 +-
 configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig|  2 +-
 configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig   |  2 +-
 configs/P1010RDB-PB_NAND_SECBOOT_defconfig |  2 +-
 configs/P1010RDB-PB_NOR_SECBOOT_defconfig  |  2 +-
 configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig |  2 +-
 configs/P2041RDB_SECURE_BOOT_defconfig |  2 +-
 configs/P3041DS_NAND_SECURE_BOOT_defconfig |  2 +-
 configs/P3041DS_SECURE_BOOT_defconfig  |  2 +-
 configs/P4080DS_SECURE_BOOT_defconfig  |  2 +-
 configs/P5020DS_NAND_SECURE_BOOT_defconfig |  2 +-
 configs/P5020DS_SECURE_BOOT_defconfig  |  2 +-
 configs/P5040DS_NAND_SECURE_BOOT_defconfig |  2 +-
 configs/P5040DS_SECURE_BOOT_defconfig  |  2 +-
 configs/T1023RDB_SECURE_BOOT_defconfig |  2 +-
 configs/T1024QDS_DDR4_SECURE_BOOT_defconfig|  2 +-
 configs/T1024QDS_SECURE_BOOT_defconfig |  2 +-
 configs/T1024RDB_SECURE_BOOT_defconfig |  2 +-
 configs/T1040D4RDB_SECURE_BOOT_defconfig   |  2 +-
 configs/T1040QDS_SECURE_BOOT_defconfig |  2 +-
 configs/T1040RDB_SECURE_BOOT_defconfig |  2 +-
 configs/T1042D4RDB_SECURE_BOOT_defconfig   |  2 +-
 configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig |  2 +-
 configs/T1042RDB_SECURE_BOOT_defconfig |  2 +-
 configs/T2080QDS_SECURE_BOOT_defconfig |  2 +-
 configs/T2080RDB_SECURE_BOOT_defconfig |  2 +-
 configs/T4160QDS_SECURE_BOOT_defconfig |  2 +-
 configs/T4240QDS_SECURE_BOOT_defconfig |  2 +-
 doc/README.mpc85xx |  8 
 include/configs/P1010RDB.h |  4 ++--
 include/configs/T104xRDB.h |  6 +++---
 include/configs/corenet_ds.h   |  2 +-
 56 files changed, 73 insertions(+), 73 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index c038a6ddb0..8cc82f80b4 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1208,8 +1208,8 @@ config FSL_LAW
help
Use Freescale common code for Local Access Window
 
-config SECURE_BOOT
-   bool"Secure Boot"
+config NXP_ESBC
+   bool"NXP_ESBC"
help
Enable Freescale Secure Boot feature. Normally selected
by defconfig. If unsure, do not change.
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index cac9280790..c2b2ef2041 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -38,7 +38,7 @@
 #ifdef CONFIG_FSL_CAAM
 #include 
 #endif
-#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
 #include 
 #include 
 #endif
@@ -440,7 +440,7 @@ ulong cpu_init_f(void)
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
-#if

[U-Boot] [PATCH v2 1/2] freescale/layerscape: Rename the config CONFIG_SECURE_BOOT name.

2019-11-07 Thread Udit Agarwal

Renames CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC to avoid conflict
with UEFI secure boot.

Signed-off-by: Udit Agarwal 
---
Changes in V2:
Rebase on top of master branch.

 arch/arm/cpu/armv7/ls102xa/Kconfig   | 4 ++--
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig| 4 ++--
 arch/arm/cpu/armv8/fsl-layerscape/spl.c  | 2 +-
 board/freescale/common/Kconfig   | 2 +-
 board/freescale/common/Makefile  | 2 +-
 board/freescale/ls1043ardb/ls1043ardb.c  | 2 +-
 board/freescale/ls1046afrwy/ls1046afrwy.c| 2 +-
 board/freescale/ls1046aqds/ls1046aqds.c  | 2 +-
 board/freescale/ls1046ardb/ls1046ardb.c  | 2 +-
 configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig   | 2 +-
 configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig| 2 +-
 configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 2 +-
 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig| 2 +-
 configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 2 +-
 configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 2 +-
 configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 2 +-
 configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig  | 2 +-
 configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 2 +-
 configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 2 +-
 configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 +-
 configs/ls1043ardb_SECURE_BOOT_defconfig | 2 +-
 configs/ls1043ardb_nand_SECURE_BOOT_defconfig| 2 +-
 configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig  | 2 +-
 configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 2 +-
 configs/ls1046aqds_SECURE_BOOT_defconfig | 2 +-
 configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 2 +-
 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig| 2 +-
 configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig  | 2 +-
 configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 2 +-
 configs/ls1088aqds_qspi_SECURE_BOOT_defconfig| 2 +-
 configs/ls1088ardb_qspi_SECURE_BOOT_defconfig| 2 +-
 configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 2 +-
 configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 2 +-
 configs/ls2080aqds_SECURE_BOOT_defconfig | 2 +-
 configs/ls2080ardb_SECURE_BOOT_defconfig | 2 +-
 configs/ls2088ardb_qspi_SECURE_BOOT_defconfig| 2 +-
 configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 2 +-
 configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 2 +-
 configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 2 +-
 include/configs/ls1021atwr.h | 4 ++--
 include/configs/ls1028a_common.h | 2 +-
 include/configs/ls1043a_common.h | 8 
 include/configs/ls1046a_common.h | 4 ++--
 include/configs/ls1088a_common.h | 4 ++--
 include/configs/ls1088aqds.h | 6 +++---
 include/configs/ls2080aqds.h | 4 ++--
 46 files changed, 57 insertions(+), 57 deletions(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 94fa68250d..b9511da3f3 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -50,8 +50,8 @@ config MAX_CPUS
  cores, count the reserved ports. This will allocate enough memory
  in spin table to properly handle all cores.
 
-config SECURE_BOOT
-   bool"Secure Boot"
+config NXP_ESBC
+   bool"NXP_ESBC"
help
Enable Freescale Secure Boot feature. Normally selected
by defconfig. If unsure, do not change.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 24c606a232..cca706089c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -375,8 +375,8 @@ config EMC2305
 Enable the EMC2305 fan controller for configuration of fan
 speed.
 
-config SECURE_BOOT
-   bool "Secure Boot"
+config NXP_ESBC
+   bool "NXP_ESBC"
help
Enable Freescale Secure Boot feature
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c 
b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 8f199b..3f6a5f6a42 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -34,7 +34,7 @@ u32 spl_boot_device(void)
 
 void spl_board_init(void)
 {
-#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_LSCH2)
+#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_LSCH2)
/*
 * In case of Secure Boot, the IBR configures the SMMU
 * to allow only Secure transactions.
diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig
index 8b89c10aba..1b1fd69cb2 100644
--- a/board/freescale/common/Kconfig
+++ b/board/freescale/common/Kconfig
@@ -1,5 +1,5 @@
 config CHAIN_OF_TRUST
-   depends on !FIT_SIGNATURE && SECURE_BOOT
+   depends

[U-Boot] [PATCH v4 4/5] dm: core: Don't include ofnode functions with of-platdata

2019-11-07 Thread Simon Glass

These functions cannot work with of-platdata since libfdt is not
available. At present when dev_read_...() functions are used it produces
error messages about ofnode which is confusing.

Adjust the Makefile and header to produce an error message for the actual
dev_read...() function which is called. This makes it easier to see what
code needs to be converted for use with of-platdata.

Signed-off-by: Simon Glass 
---

Changes in v4: None
Changes in v3:
- Fix eth_dev_get_mac_address() call dev_read...() only when available

 drivers/core/Makefile | 4 +++-
 include/dm/read.h | 3 +--
 net/eth-uclass.c  | 2 +-
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/core/Makefile b/drivers/core/Makefile
index bce7467da1..b9e4a2aab1 100644
--- a/drivers/core/Makefile
+++ b/drivers/core/Makefile
@@ -13,6 +13,8 @@ obj-$(CONFIG_OF_LIVE) += of_access.o of_addr.o
 ifndef CONFIG_DM_DEV_READ_INLINE
 obj-$(CONFIG_OF_CONTROL) += read.o
 endif
-obj-$(CONFIG_OF_CONTROL) += of_extra.o ofnode.o read_extra.o
+ifdef CONFIG_$(SPL_TPL_)OF_LIBFDT
+obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += of_extra.o ofnode.o read_extra.o
+endif
 
 ccflags-$(CONFIG_DM_DEBUG) += -DDEBUG
diff --git a/include/dm/read.h b/include/dm/read.h
index d37fcb504d..4f02d07d00 100644
--- a/include/dm/read.h
+++ b/include/dm/read.h
@@ -43,8 +43,7 @@ static inline bool dev_of_valid(struct udevice *dev)
return ofnode_valid(dev_ofnode(dev));
 }
 
-#ifndef CONFIG_DM_DEV_READ_INLINE
-
+#if !defined(CONFIG_DM_DEV_READ_INLINE) || CONFIG_IS_ENABLED(OF_PLATDATA)
 /**
  * dev_read_u32() - read a 32-bit integer from a device's DT property
  *
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index 3bd98b01ad..e3bfcdb6cc 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -462,7 +462,7 @@ static int eth_pre_unbind(struct udevice *dev)
 
 static bool eth_dev_get_mac_address(struct udevice *dev, u8 mac[ARP_HLEN])
 {
-#if IS_ENABLED(CONFIG_OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL)
const uint8_t *p;
 
p = dev_read_u8_array_ptr(dev, "mac-address", ARP_HLEN);
-- 
2.24.0.rc1.363.gb1bccd3e3d-goog

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v4 5/5] spl: Allow SPL/TPL to use of-platdata without libfdt

2019-11-07 Thread Simon Glass

At present libfdt is included in SPL/TPL if SPL/TPL_OF_CONTROL is enabled.
But if of-platdata is in use this is not required. Update the condition to
avoid building this extra code. This ensures that if a libfdt function is
used it will produce a link error rather than silently increasing the
build size.

Signed-off-by: Simon Glass 
---

Changes in v4:
- Pull out patches into a new series
- Add new patches to handle build failures

Changes in v3: None

 lib/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/Kconfig b/lib/Kconfig
index b8a8509d72..1cae2d5cc8 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -484,7 +484,7 @@ config OF_LIBFDT_OVERLAY
 
 config SPL_OF_LIBFDT
bool "Enable the FDT library for SPL"
-   default y if SPL_OF_CONTROL
+   default y if SPL_OF_CONTROL && !SPL_OF_PLATDATA
help
  This enables the FDT library (libfdt). It provides functions for
  accessing binary device tree images in memory, such as adding and
@@ -505,7 +505,7 @@ config SPL_OF_LIBFDT_ASSUME_MASK
 
 config TPL_OF_LIBFDT
bool "Enable the FDT library for TPL"
-   default y if TPL_OF_CONTROL
+   default y if TPL_OF_CONTROL && !TPL_OF_PLATDATA
help
  This enables the FDT library (libfdt). It provides functions for
  accessing binary device tree images in memory, such as adding and
-- 
2.24.0.rc1.363.gb1bccd3e3d-goog

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v4 1/5] rockchip: Avoid using libfdt with of-platdata

2019-11-07 Thread Simon Glass

At present a few of the clk and pinctrl drivers use libfdt routines (via
dev_read_..()) when of-platdata is enabled. This is not permitted.

Correct this by returning errors instead. The drivers may need to be
modified to add full support.

Signed-off-by: Simon Glass 
---

Changes in v4:
- Add new patch for rockchip build errors

Changes in v3: None

 drivers/clk/rockchip/clk_rk3328.c| 14 --
 drivers/pinctrl/rockchip/pinctrl-rockchip-core.c |  6 --
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3328.c 
b/drivers/clk/rockchip/clk_rk3328.c
index a89e2ecc4a..e86c17e6d6 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -669,6 +669,10 @@ static int rk3328_gmac2io_set_parent(struct clk *clk, 
struct clk *parent)
return 0;
}
 
+   /* FIXME: Device tree should be read in ofdata_to_platdata() */
+   if (CONFIG_IS_ENABLED(OF_PLATDATA))
+   return -EDEADLK;
+
/*
 * Otherwise, we need to check the clock-output-names of the
 * requested parent to see if the requested id is "gmac_clkin".
@@ -706,6 +710,10 @@ static int rk3328_gmac2io_ext_set_parent(struct clk *clk, 
struct clk *parent)
return 0;
}
 
+   /* FIXME: Device tree should be read in ofdata_to_platdata() */
+   if (CONFIG_IS_ENABLED(OF_PLATDATA))
+   return -EDEADLK;
+
/*
 * Otherwise, we need to check the clock-output-names of the
 * requested parent to see if the requested id is "gmac_clkin".
@@ -762,9 +770,11 @@ static int rk3328_clk_probe(struct udevice *dev)
 
 static int rk3328_clk_ofdata_to_platdata(struct udevice *dev)
 {
-   struct rk3328_clk_priv *priv = dev_get_priv(dev);
+   if (!CONFIG_IS_ENABLED(OF_PLATDATA)) {
+   struct rk3328_clk_priv *priv = dev_get_priv(dev);
 
-   priv->cru = dev_read_addr_ptr(dev);
+   priv->cru = dev_read_addr_ptr(dev);
+   }
 
return 0;
 }
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c 
b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
index 80dc431d20..dccc54e95f 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
@@ -383,8 +383,8 @@ static int rockchip_pinconf_prop_name_to_param(const char 
*property,
return -EPERM;
 }
 
-static int rockchip_pinctrl_set_state(struct udevice *dev,
- struct udevice *config)
+static int __maybe_unused rockchip_pinctrl_set_state(struct udevice *dev,
+struct udevice *config)
 {
struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
struct rockchip_pin_ctrl *ctrl = priv->ctrl;
@@ -474,7 +474,9 @@ static int rockchip_pinctrl_set_state(struct udevice *dev,
 }
 
 const struct pinctrl_ops rockchip_pinctrl_ops = {
+#if !CONFIG_IS_ENABLED(PLATDATA)
.set_state  = rockchip_pinctrl_set_state,
+#endif
.get_gpio_mux   = rockchip_pinctrl_get_gpio_mux,
 };
 
-- 
2.24.0.rc1.363.gb1bccd3e3d-goog

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v4 3/5] rockchip: pinctrl: Disable full pinctrl for SPL

2019-11-07 Thread Simon Glass

We don't need full pinctrl for SPL on these chrombook devices. Disable
it so that of-platdata can be used without calling libfdt routines.

Signed-off-by: Simon Glass 

---

Changes in v4:
- Add new patch for rockchip chromebook build errors

Changes in v3: None

 configs/chromebit_mickey_defconfig  | 1 +
 configs/chromebook_jerry_defconfig  | 1 +
 configs/chromebook_minnie_defconfig | 1 +
 configs/chromebook_speedy_defconfig | 1 +
 4 files changed, 4 insertions(+)

diff --git a/configs/chromebit_mickey_defconfig 
b/configs/chromebit_mickey_defconfig
index 6a1ea049f9..2e93344bda 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -72,6 +72,7 @@ CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_FULL is not set
 # CONFIG_SPL_PINMUX is not set
 CONFIG_SPL_PINCONF=y
 CONFIG_DM_PMIC=y
diff --git a/configs/chromebook_jerry_defconfig 
b/configs/chromebook_jerry_defconfig
index 1b7751cc6a..2ed9921e4e 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -75,6 +75,7 @@ CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_FULL is not set
 # CONFIG_SPL_PINMUX is not set
 CONFIG_SPL_PINCONF=y
 CONFIG_DM_PMIC=y
diff --git a/configs/chromebook_minnie_defconfig 
b/configs/chromebook_minnie_defconfig
index 28ae61847f..c62ebaca31 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -74,6 +74,7 @@ CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_FULL is not set
 # CONFIG_SPL_PINMUX is not set
 CONFIG_SPL_PINCONF=y
 CONFIG_DM_PMIC=y
diff --git a/configs/chromebook_speedy_defconfig 
b/configs/chromebook_speedy_defconfig
index 0284e31bcf..fd707e283d 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -74,6 +74,7 @@ CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_FULL is not set
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_PMIC_RK8XX=y
-- 
2.24.0.rc1.363.gb1bccd3e3d-goog

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v4 2/5] omap: mmc: Avoid using libfdt with of-platdata

2019-11-07 Thread Simon Glass

At present this driver is enabled in SPL on omapl138_lcdk, which uses
of-platdata. The driver needs to be ported to use of-platdata properly.
For now, avoid a build error by returning an error.

Signed-off-by: Simon Glass 

---

Changes in v4:
- Add new patch for omap MMC build errors

Changes in v3: None

 drivers/mmc/davinci_mmc.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c
index 0d63279db0..79a7f50d25 100644
--- a/drivers/mmc/davinci_mmc.c
+++ b/drivers/mmc/davinci_mmc.c
@@ -507,6 +507,12 @@ static int davinci_mmc_probe(struct udevice *dev)
priv->version = data->version;
}
 
+   /* FIXME: Cannot read from device tree with of-platdata */
+   if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
+   printf("Please fix this driver to use of-platdata");
+   return -ENOSYS;
+   }
+
priv->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
priv->input_clk = clk_get(DAVINCI_MMCSD_CLKID);
 
-- 
2.24.0.rc1.363.gb1bccd3e3d-goog

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v4 0/5] of-platdata: Avoid building libfdt

2019-11-07 Thread Simon Glass

The original patch of this series was sent in September but unfortunately
caused build problems on some boards, since they don't comply with the
of-platdata rules.

With of-platdata, the idea is to compile the device tree into C structures
to save space and avoid needing to use libfdt. But some boards use
of-platdata while also using libfdt in a few areas, thus defeating the
purpose of of-platdata.

This series includes the original two patches

   http://patchwork.ozlabs.org/patch/1167420/
   http://patchwork.ozlabs.org/patch/1167367/

as well as a few other patches to fix the build errors. Overall this
reduces code size and provides better error messages when unavailable
functions are used.

Board maintainers should still take a look at the result, adjusting the
of-platdata support as needed.

Changes in v4:
- Add new patch for rockchip build errors
- Add new patch for omap MMC build errors
- Add new patch for rockchip chromebook build errors
- Pull out patches into a new series
- Add new patches to handle build failures

Changes in v3:
- Fix eth_dev_get_mac_address() call dev_read...() only when available

Simon Glass (5):
  rockchip: Avoid using libfdt with of-platdata
  omap: mmc: Avoid using libfdt with of-platdata
  rockchip: pinctrl: Disable full pinctrl for SPL
  dm: core: Don't include ofnode functions with of-platdata
  spl: Allow SPL/TPL to use of-platdata without libfdt

 configs/chromebit_mickey_defconfig   |  1 +
 configs/chromebook_jerry_defconfig   |  1 +
 configs/chromebook_minnie_defconfig  |  1 +
 configs/chromebook_speedy_defconfig  |  1 +
 drivers/clk/rockchip/clk_rk3328.c| 14 --
 drivers/core/Makefile|  4 +++-
 drivers/mmc/davinci_mmc.c|  6 ++
 drivers/pinctrl/rockchip/pinctrl-rockchip-core.c |  6 --
 include/dm/read.h|  3 +--
 lib/Kconfig  |  4 ++--
 net/eth-uclass.c |  2 +-
 11 files changed, 33 insertions(+), 10 deletions(-)

-- 
2.24.0.rc1.363.gb1bccd3e3d-goog

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] Buildman Kconfig issue with consecutive builds

2019-11-07 Thread Schrempf Frieder

On 07.11.19 15:02, Bin Meng wrote:
> Hi Frieder,
> 
> On Thu, Nov 7, 2019 at 9:28 PM Schrempf Frieder
>  wrote:
>>
>> Hi Bin,
>>
>> On 07.11.19 13:41, Bin Meng wrote:
>>> Hi Schrempf,
>>>
>>> On Thu, Nov 7, 2019 at 12:17 AM Schrempf Frieder
>>>  wrote:

 Hi,

 I'm having some trouble using buildman to test the impact of some
 Kconfig cleanup patches ([1]).

 The patches introduce a new CONFIG_SPL_* option and I try to find out
 which defconfigs need to be fixed, by comparing build sizes.

 Now when I added a patch to fix a defconfig I noticed that buildman
 wouldn't report the expected size changes and upon looking more closely
 I found that the added Kconfig options are still missing in u-boot-spl.cfg.

 The strange thing is, that when I try to build only the last commit then
 the Kconfig options are there, which is why I suspect a bug in buildman
 not handling Kconfig changes correctly with consecutive builds.

 Can anyone have a look what is wrong or how I can debug this issue?

 The issue can be reproduced with the branch at [1], running:

 buildman -b spi_flash_kconfig_cleanup_3 --step 0 xilinx_zynqmp_virt

>>>
>>> Could you please add "-C" to the buildman command line and have a try?
>>
>> Indeed forcing the reconfig between the build steps with '-C' fixes the
>> issue.
>>
>> Is it a known problem, that buildman doesn't handle Kconfig changes
>> correctly without '-C' in some cases?
> 
> AFAIK, this is an intended design of calling buildman w/o '-C' to save
> some build time.

Ok, if that's the case I will try to come up with a patch that adds a 
note to the README. This has cost me a few hours because I was thinking 
buildman does the right thing and Kconfig options are messed up somewhere.
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 2/2] ARM: dts: imx6qdl: Add U-Boot specific device tree files for Cubox-i

2019-11-07 Thread Walter Lozano


Hi Fabio,

On 7/11/19 10:48, Fabio Estevam wrote:

Hi Walter,

On Wed, Oct 30, 2019 at 4:58 PM Walter Lozano
 wrote:


Thanks for the suggestion. I will wait for some SATA tests before re
sending these patches.

Just to let you know that Baruch has submitted a series that convert
imx6 cubox to use DM:
https://lists.denx.de/pipermail/u-boot/2019-November/389336.html



Thanks for the information. I'm glad to know that finally these boards 
will have DM support.





Regards,

Fabio Estevam



Regards,


Walter

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] Buildman Kconfig issue with consecutive builds

2019-11-07 Thread Bin Meng

Hi Frieder,

On Thu, Nov 7, 2019 at 9:28 PM Schrempf Frieder
 wrote:
>
> Hi Bin,
>
> On 07.11.19 13:41, Bin Meng wrote:
> > Hi Schrempf,
> >
> > On Thu, Nov 7, 2019 at 12:17 AM Schrempf Frieder
> >  wrote:
> >>
> >> Hi,
> >>
> >> I'm having some trouble using buildman to test the impact of some
> >> Kconfig cleanup patches ([1]).
> >>
> >> The patches introduce a new CONFIG_SPL_* option and I try to find out
> >> which defconfigs need to be fixed, by comparing build sizes.
> >>
> >> Now when I added a patch to fix a defconfig I noticed that buildman
> >> wouldn't report the expected size changes and upon looking more closely
> >> I found that the added Kconfig options are still missing in u-boot-spl.cfg.
> >>
> >> The strange thing is, that when I try to build only the last commit then
> >> the Kconfig options are there, which is why I suspect a bug in buildman
> >> not handling Kconfig changes correctly with consecutive builds.
> >>
> >> Can anyone have a look what is wrong or how I can debug this issue?
> >>
> >> The issue can be reproduced with the branch at [1], running:
> >>
> >> buildman -b spi_flash_kconfig_cleanup_3 --step 0 xilinx_zynqmp_virt
> >>
> >
> > Could you please add "-C" to the buildman command line and have a try?
>
> Indeed forcing the reconfig between the build steps with '-C' fixes the
> issue.
>
> Is it a known problem, that buildman doesn't handle Kconfig changes
> correctly without '-C' in some cases?

AFAIK, this is an intended design of calling buildman w/o '-C' to save
some build time.

Regards,
Bin
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

1 2 >

1 - 100 of 161 matches

Mail list logo