[PATCH 4/5] arm64: dts: k3-j721e-common-proc-board: Fully enable wkup_i2c0 use
From: Andreas Dannenberg
Make the wkup_i2c0 module usable across all stages of U-Boot by adding
the needed definitions including the associated pinmux definitions.
Signed-off-by: Andreas Dannenberg
Signed-off-by: Lokesh Vutla
---
.../dts/k3-j721e-common-proc-board-u-boot.dtsi| 8
arch/arm/dts/k3-j721e-common-proc-board.dts | 15 +++
2 files changed, 23 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 9291e57e25..e54b2a7e70 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -311,3 +311,11 @@
reg-names = "gmii-sel";
};
};
+
+_i2c0_pins_default {
+ u-boot,dm-spl;
+};
+
+_i2c0 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts
b/arch/arm/dts/k3-j721e-common-proc-board.dts
index c978cabd13..f4366f9f87 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -77,3 +77,18 @@
voltage-ranges = <1800 1800 3300 3300>;
ti,driver-strength-ohm = <50>;
};
+
+_pmx0 {
+ wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25)
WKUP_I2C0_SCL */
+ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24)
WKUP_I2C0_SDA */
+ >;
+ };
+};
+
+_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c0_pins_default>;
+ clock-frequency = <40>;
+};
--
2.23.0
[PATCH 2/5] board: ti: j721e: Use EEPROM-based board detection
From: Andreas Dannenberg
The TI J721E EVM system on module (SOM), the common processor board, and
the associated daughtercards have on-board I2C-based EEPROMs containing
board config data. Use the board detection infrastructure to do the
following:
1) Parse the J721E SOM EEPROM and populate items like board name, board
HW and SW revision as well as board serial number into the TI common
EEPROM data structure residing in SRAM scratch space
2) Check for presence of daughter card(s) by probing associated I2C
addresses used for on-board EEPROMs containing daughter card-specific
data. If such a card is found, parse the EEPROM data such as for
additional Ethernet MAC addresses and populate those into U-Boot
accordingly
3) Dynamically apply daughter card DTB overlays to the U-Boot (proper)
DTB during SPL execution
4) Dynamically create an U-Boot ENV variable called name_overlays
during U-Boot execution containing a list of daugherboard-specific
DTB overlays based on daughercards found to be used during Kernel
boot.
This patch adds support for the J721E system on module boards containing
the actual SoC ("J721EX-PM2-SOM", accessed via CONFIG_EEPROM_CHIP_ADDRESS),
the common processor board ("J7X-BASE-CPB"), the Quad-Port Ethernet
Expansion Board ("J7X-VSC8514-ETH"), the infotainment board
("J7X-INFOTAN-EXP") as well as for the gateway/Ethernet switch/industrial
expansion board ("J7X-GESI-EXP").
Signed-off-by: Andreas Dannenberg
Signed-off-by: Lokesh Vutla
---
.../arm/mach-k3/include/mach/j721e_hardware.h | 3 +
arch/arm/mach-k3/j721e_init.c | 3 +
board/ti/j721e/Kconfig| 7 +
board/ti/j721e/evm.c | 251 ++
4 files changed, 264 insertions(+)
diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h
b/arch/arm/mach-k3/include/mach/j721e_hardware.h
index 8d429772b5..ead136ed63 100644
--- a/arch/arm/mach-k3/include/mach/j721e_hardware.h
+++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h
@@ -46,4 +46,7 @@
#define CTRLMMR_LOCK_KICK1 0x0100c
#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
+/* MCU SCRATCHPAD usage */
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START
CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
+
#endif /* __ASM_ARCH_J721E_HARDWARE_H */
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 4758739266..8d562e4cbe 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -119,6 +119,9 @@ void board_init_f(ulong dummy)
preloader_console_init();
#endif
+ /* Perform EEPROM-based board detection */
+ do_board_detect();
+
#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
);
diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig
index 88097df653..e56dc53bfa 100644
--- a/board/ti/j721e/Kconfig
+++ b/board/ti/j721e/Kconfig
@@ -11,6 +11,8 @@ config TARGET_J721E_A72_EVM
bool "TI K3 based J721E EVM running on A72"
select ARM64
select SOC_K3_J721E
+ select BOARD_LATE_INIT
+ imply TI_I2C_BOARD_DETECT
select SYS_DISABLE_DCACHE_OPS
config TARGET_J721E_R5_EVM
@@ -23,6 +25,7 @@ config TARGET_J721E_R5_EVM
select SPL_RAM
select K3_J721E_DDRSS
imply SYS_K3_SPL_ATF
+ imply TI_I2C_BOARD_DETECT
endchoice
@@ -37,6 +40,8 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "j721e_evm"
+source "board/ti/common/Kconfig"
+
endif
if TARGET_J721E_R5_EVM
@@ -53,4 +58,6 @@ config SYS_CONFIG_NAME
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
+source "board/ti/common/Kconfig"
+
endif
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 51b121ce05..d822ac81db 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -9,10 +9,21 @@
#include
#include
+#include
+#include
+#include
#include
#include
#include
+#include "../common/board_detect.h"
+
+#define board_is_j721e_som() (board_ti_is("J721EX-PM1-SOM") || \
+board_ti_is("J721EX-PM2-SOM"))
+
+/* Max number of MAC addresses that are parsed/processed per daughter card */
+#define DAUGHTER_CARD_NO_OF_MAC_ADDR 8
+
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
@@ -81,3 +92,243 @@ int ft_board_setup(void *blob, bd_t *bd)
return ret;
}
#endif
+
+int do_board_detect(void)
+{
+ int ret;
+
+ ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
+CONFIG_EEPROM_CHIP_ADDRESS);
+ if (ret)
+ pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
+ CONFIG_EEPROM_CHIP_ADDRESS, ret);
+
+ return ret;
+}
+
+static void setup_board_eeprom_env(void)
+{
+ char *name = "j721e";
+
+ if (do_board_detect())
+ goto
[PATCH 5/5] configs: j721e_evm_a72_defconfig: Enable I2C and EEPROM support
From: Vignesh Raghavendra
Enable I2C and EEPROM related configs for A72 SPL/U-Boot.
Signed-off-by: Vignesh Raghavendra
Signed-off-by: Andreas Dannenberg
Signed-off-by: Lokesh Vutla
---
configs/j721e_evm_a72_defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index daa661384d..c92d49005e 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -21,6 +21,7 @@ CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run
get_overlay_${boot}; run run_kern"
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
@@ -34,6 +35,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x28
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_REMOTEPROC=y
@@ -65,6 +67,8 @@ CONFIG_CLK_TI_SCI=y
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_MISC=y
--
2.23.0
[PATCH 3/5] board: ti: j721e: Print board name and version during boot
Print the board name and ver along with the DT Model.
Signed-off-by: Lokesh Vutla
---
board/ti/j721e/evm.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index d822ac81db..101fe1be4e 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -106,6 +106,19 @@ int do_board_detect(void)
return ret;
}
+int checkboard(void)
+{
+ struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+ if (do_board_detect())
+ /* EEPROM not populated */
+ printf("Board: %s rev %s\n", "J721EX-PM1-SOM", "E2");
+ else
+ printf("Board: %s rev %s\n", ep->name, ep->version);
+
+ return 0;
+}
+
static void setup_board_eeprom_env(void)
{
char *name = "j721e";
--
2.23.0
[PATCH 1/5] ti: common: board_detect: Handle EEPROM probe more gracefully
From: Andreas Dannenberg Use dm_i2c_probe() rather than i2c_get_chip() when trying to access board-detection EEPROM devices. This has the advantage of more gracefully handling the case when the EEPROM is not present by allowing to exit the function early rather than failing and outputting an error message on the I2C transactions that follow. Signed-off-by: Andreas Dannenberg Signed-off-by: Lokesh Vutla --- board/ti/common/board_detect.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c index 564d2f7046..cf6bd02698 100644 --- a/board/ti/common/board_detect.c +++ b/board/ti/common/board_detect.c @@ -91,7 +91,7 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, rc = uclass_get_device_by_seq(UCLASS_I2C, bus_addr, ); if (rc) return rc; - rc = i2c_get_chip(bus, dev_addr, 1, ); + rc = dm_i2c_probe(bus, dev_addr, 0, ); if (rc) return rc; -- 2.23.0
[PATCH 0/5] board: ti: j721e: Enable I2C and EEPROM support
This series enable I2C and EEPROM support on J721e common processor board. Logs: https://pastebin.ubuntu.com/p/6YZtmZT9vQ/ Andreas Dannenberg (3): ti: common: board_detect: Handle EEPROM probe more gracefully board: ti: j721e: Use EEPROM-based board detection arm64: dts: k3-j721e-common-proc-board: Fully enable wkup_i2c0 use Lokesh Vutla (1): board: ti: j721e: Print board name and version during boot Vignesh Raghavendra (1): configs: j721e_evm_a72_defconfig: Enable I2C and EEPROM support .../k3-j721e-common-proc-board-u-boot.dtsi| 8 + arch/arm/dts/k3-j721e-common-proc-board.dts | 15 + .../arm/mach-k3/include/mach/j721e_hardware.h | 3 + arch/arm/mach-k3/j721e_init.c | 3 + board/ti/common/board_detect.c| 2 +- board/ti/j721e/Kconfig| 7 + board/ti/j721e/evm.c | 264 ++ configs/j721e_evm_a72_defconfig | 4 + 8 files changed, 305 insertions(+), 1 deletion(-) -- 2.23.0
Re: [PATCH] arm64: zynqmp: Fix emmc boot mode boot_target sequennce
út 17. 12. 2019 v 14:47 odesílatel Michal Simek
napsal:
>
> From: T Karthik Reddy
>
> Emmc boot devcie is mounted to mmc@ff16 controller on zynqmp.
> Detect mmc alias at run time for setting up proper boot_targets
> sequence instead of setting boot_targets manually.
> Removed setting "modeboot" variable as it not longer need as we
> switched to distro boot.
>
> Signed-off-by: T Karthik Reddy
> Signed-off-by: Michal Simek
> ---
>
> board/xilinx/zynqmp/zynqmp.c | 13 +++--
> 1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
> index aac2eb7bc1a2..b72eade43eea 100644
> --- a/board/xilinx/zynqmp/zynqmp.c
> +++ b/board/xilinx/zynqmp/zynqmp.c
> @@ -580,8 +580,17 @@ int board_late_init(void)
> break;
> case EMMC_MODE:
> puts("EMMC_MODE\n");
> - mode = "mmc0";
> - env_set("modeboot", "emmcboot");
> + if (uclass_get_device_by_name(UCLASS_MMC,
> + "mmc@ff16", ) &&
> + uclass_get_device_by_name(UCLASS_MMC,
> + "sdhci@ff16", )) {
> + puts("Boot from EMMC but without SD0 enabled!\n");
> + return -1;
> + }
> + debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
> +
> + mode = "mmc";
> + bootseq = dev->seq;
> break;
> case SD_MODE:
> puts("SD_MODE\n");
> --
> 2.24.0
>
Applied but with fixed subject.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
[PATCH 0/6] Add fastboot support for MediaTek mt8518
This patch series adds basic fastboot support for MediaTek MT8518 EMMC boards, including musb-new structure for gadget driver and fastboot related configs. mingming lee (6): usb: musb-new: mt85xx: add musb-new gadget driver. ARM: Mediatek: Add board_late_init to init usb gadget driver configs: mt8518: set global variables for fastboot configs: mt8518: enable usb gadget driver configs: mt8518: Enable fastboot related configs fastboot: mt85xx: add command to flash/erase emmc hwpart arch/arm/dts/mt8518.dtsi | 13 + board/mediatek/mt8518/mt8518_ap1.c | 18 ++ configs/mt8518_ap1_emmc_defconfig | 22 ++ drivers/fastboot/Kconfig | 30 +++ drivers/fastboot/fb_mmc.c | 98 ++- drivers/usb/musb-new/Kconfig | 11 +- drivers/usb/musb-new/Makefile | 1 + drivers/usb/musb-new/mt85xx.c | 417 + include/configs/mt8518.h | 10 +- 9 files changed, 614 insertions(+), 6 deletions(-) create mode 100644 drivers/usb/musb-new/mt85xx.c -- 2.24.1
[PATCH 1/6] usb: musb-new: mt85xx: add musb-new gadget driver.
Using musb-new structure for mt85xx gadget driver.
Add gadget driver dts for mt8518 SoCs.
Signed-off-by: mingming lee
---
arch/arm/dts/mt8518.dtsi | 13 ++
drivers/usb/musb-new/Kconfig | 11 +-
drivers/usb/musb-new/Makefile | 1 +
drivers/usb/musb-new/mt85xx.c | 417 ++
4 files changed, 441 insertions(+), 1 deletion(-)
create mode 100644 drivers/usb/musb-new/mt85xx.c
diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
index c2d17fda4a..56da91a9fe 100644
--- a/arch/arm/dts/mt8518.dtsi
+++ b/arch/arm/dts/mt8518.dtsi
@@ -74,6 +74,19 @@
};
};
+ usb0: usb@1110 {
+ compatible = "mediatek,mt8518-musb";
+ reg = <0x1110 0x1000>;
+ reg-names = "control";
+ clocks = < CLK_TOP_USB20_48M>,
+< CLK_TOP_USBIF>,
+< CLK_TOP_USB>;
+ clock-names = "usbpll", "usbmcu", "usb";
+ interrupts = ;
+ interrupt-names = "mc";
+ status = "okay";
+ };
+
mmc0: mmc@1112 {
compatible = "mediatek,mt8516-mmc";
reg = <0x1112 0x1000>;
diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index 79ad14ef66..6cf8a2b60b 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -47,6 +47,15 @@ config USB_MUSB_DSPS
bool "TI DSPS platforms"
if USB_MUSB_HOST || USB_MUSB_GADGET
+config USB_MUSB_MT85XX
+ bool "Enable Mediatek MT85XX DRC USB controller"
+ depends on DM_USB && ARCH_MEDIATEK
+ default n
+ help
+ Say y to enable Mediatek MT85XX USB DRC controller support
+ if it is available on your Mediatek MUSB IP based platform.
+ DMA controllers are ignored. This driver follow musb-new
+ driver and usb gadget framework.
config USB_MUSB_PIC32
bool "Enable Microchip PIC32 DRC USB controller"
@@ -76,7 +85,7 @@ endif
config USB_MUSB_PIO_ONLY
bool "Disable DMA (always use PIO)"
- default y if USB_MUSB_AM35X || USB_MUSB_PIC32 || USB_MUSB_OMAP2PLUS ||
USB_MUSB_DSPS || USB_MUSB_SUNXI
+ default y if USB_MUSB_AM35X || USB_MUSB_PIC32 || USB_MUSB_OMAP2PLUS ||
USB_MUSB_DSPS || USB_MUSB_SUNXI || USB_MUSB_MT85XX
help
All data is copied between memory and FIFO by the CPU.
DMA controllers are ignored.
diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile
index ec7852ce94..6355eb12dd 100644
--- a/drivers/usb/musb-new/Makefile
+++ b/drivers/usb/musb-new/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_USB_MUSB_HOST) += musb_host.o musb_core.o
musb_uboot.o
obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o
obj-$(CONFIG_USB_MUSB_DA8XX) += da8xx.o
obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o
+obj-$(CONFIG_USB_MUSB_MT85XX) += mt85xx.o
obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o
obj-$(CONFIG_USB_MUSB_PIC32) += pic32.o
obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
diff --git a/drivers/usb/musb-new/mt85xx.c b/drivers/usb/musb-new/mt85xx.c
new file mode 100644
index 00..131fd7dd79
--- /dev/null
+++ b/drivers/usb/musb-new/mt85xx.c
@@ -0,0 +1,417 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Mediatek "glue layer"
+ *
+ * Copyright (C) 2019-2021 by Mediatek
+ * Based on the AllWinner SUNXI "glue layer" code.
+ * Copyright (C) 2015 Hans de Goede
+ * Copyright (C) 2013 Jussi Kivilinna
+ *
+ * This file is part of the Inventra Controller Driver for Linux.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "linux-compat.h"
+#include "musb_core.h"
+#include "musb_uboot.h"
+
+#define DBG_I(fmt, ...) \
+ pr_info(fmt, ##__VA_ARGS__)
+
+struct mtk_musb_config {
+ struct musb_hdrc_config *config;
+};
+
+struct mtk_musb_glue {
+ struct musb_host_data mdata;
+ struct clk usbpllclk;
+ struct clk usbmcuclk;
+ struct clk usbclk;
+ struct mtk_musb_config *cfg;
+ struct device dev;
+};
+
+#define to_mtk_musb_glue(d)container_of(d, struct mtk_musb_glue, dev)
+
+/**
+ * phy settings
+
**/
+#define USB20_PHY_BASE 0x0800
+#define USBPHY_READ8(offset)\
+ readb((void *)(USB20_PHY_BASE + (offset)))
+#define USBPHY_WRITE8(offset, value) \
+ writeb(value, (void *)(USB20_PHY_BASE + (offset)))
+#define USBPHY_SET8(offset, mask) \
+ USBPHY_WRITE8(offset, (USBPHY_READ8(offset)) | (mask))
+#define USBPHY_CLR8(offset, mask) \
+ USBPHY_WRITE8(offset, (USBPHY_READ8(offset)) & (~(mask)))
+
+static void mt_usb_phy_poweron(void)
+{
+ /*
+* switch to USB function.
+* (system register, force ip into usb mode).
+*/
+ USBPHY_CLR8(0x6b, 0x04);
+ USBPHY_CLR8(0x6e, 0x01);
+
[PATCH 3/6] configs: mt8518: set global variables for fastboot
set common fastboot variables for mt8518 Signed-off-by: mingming lee --- include/configs/mt8518.h | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h index 8906245a62..9bc9c04e66 100644 --- a/include/configs/mt8518.h +++ b/include/configs/mt8518.h @@ -11,9 +11,6 @@ #include -#define CONFIG_ENV_SIZESZ_4K - -/* Machine ID */ #define CONFIG_SYS_NONCACHED_MEMORYSZ_1M #define CONFIG_CPU_ARMV8 @@ -39,7 +36,7 @@ /* ENV Setting */ #if defined(CONFIG_MMC_MTK) #define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_OFFSET 0x4E6 + #define CONFIG_ENV_OVERWRITE /* MMC offset in block unit,and block size is 0x200 */ @@ -58,10 +55,15 @@ #define ENV_BOOT_CMD \ "mtk_boot=run boot_rd_img;bootm;\0" +#define ENV_FASTBOOT \ + "serial#=1234567890ABCDEF\0" \ + "board=mt8518\0" + #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x6c00\0" \ ENV_DEVICE_SETTINGS \ ENV_BOOT_READ_IMAGE \ + ENV_FASTBOOT \ ENV_BOOT_CMD \ "bootcmd=run mtk_boot;\0" \ -- 2.24.1
[PATCH 6/6] fastboot: mt85xx: add command to flash/erase emmc hwpart
This patch includes the following:
1. Add fastboot command to erase the whole EMMC_USER
2. Add fastboot command to flash image at EMMC_BOOT1
3. Add fastboot command to erase the whole EMMC_BOOT1
4. Enale CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT for mt8518
Signed-off-by: mingming lee
---
configs/mt8518_ap1_emmc_defconfig | 1 +
drivers/fastboot/Kconfig | 30 ++
drivers/fastboot/fb_mmc.c | 98 ++-
3 files changed, 128 insertions(+), 1 deletion(-)
diff --git a/configs/mt8518_ap1_emmc_defconfig
b/configs/mt8518_ap1_emmc_defconfig
index 714fd8e087..e929d40d75 100644
--- a/configs/mt8518_ap1_emmc_defconfig
+++ b/configs/mt8518_ap1_emmc_defconfig
@@ -60,3 +60,4 @@ CONFIG_FASTBOOT_FLASH_MMC=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_BUF_ADDR=0x5600
CONFIG_FASTBOOT_BUF_SIZE=0x1E0
+CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT=y
\ No newline at end of file
diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
index 433ea0dc3b..a4cf52dc9a 100644
--- a/drivers/fastboot/Kconfig
+++ b/drivers/fastboot/Kconfig
@@ -104,6 +104,36 @@ config FASTBOOT_FLASH_NAND_TRIMFFS
When flashing NAND enable the DROP_FFS flag to drop trailing all-0xff
pages.
+config FASTBOOT_MMC_BOOT1_SUPPORT
+ bool "Enable EMMC_BOOT1 flash/erase"
+ depends on FASTBOOT_FLASH_MMC && EFI_PARTITION
+ help
+ The fastboot "flash" and "erase" commands normally does operations
+ on EMMC userdata. Define this to enable the special commands to
+ flash/erase EMMC_BOOT1.
+ The default target name for updating EMMC_BOOT1 is "mmc0boot0".
+
+config FASTBOOT_MMC_BOOT1_NAME
+ string "Target name for updating EMMC_BOOT1"
+ depends on FASTBOOT_MMC_BOOT1_SUPPORT
+ default "mmc0boot0"
+ help
+ The fastboot "flash" and "erase" commands support operations on
+ EMMC_BOOT1. This occurs when the specified "EMMC_BOOT1 name" on
+ the "fastboot flash" and "fastboot erase" commands match the value
+ defined here.
+ The default target name for updating EMMC_BOOT1 is "mmc0boot0".
+
+config FASTBOOT_MMC_USER_NAME
+ string "Target name for erasing EMMC_USER"
+ depends on FASTBOOT_FLASH_MMC && EFI_PARTITION
+ default "mmc0"
+ help
+ The fastboot "erase" command supports erasing EMMC_USER. This occurs
+ when the specified "EMMC_USER name" on the "fastboot erase" commands
+ match the value defined here.
+ The default target name for erasing EMMC_USER is "mmc0".
+
config FASTBOOT_GPT_NAME
string "Target name for updating GPT"
depends on FASTBOOT_FLASH_MMC && EFI_PARTITION
diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c
index b0b19c5762..4eabbfdf3d 100644
--- a/drivers/fastboot/fb_mmc.c
+++ b/drivers/fastboot/fb_mmc.c
@@ -129,6 +129,76 @@ static void write_raw_image(struct blk_desc *dev_desc,
disk_partition_t *info,
fastboot_okay(NULL, response);
}
+#ifdef CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT
+static int fb_mmc_erase_mmc_hwpart(struct blk_desc *dev_desc)
+{
+ lbaint_t blks;
+
+ debug("Start Erasing mmc hwpart[%u]...\n", dev_desc->hwpart);
+
+ blks = fb_mmc_blk_write(dev_desc, 0, dev_desc->lba, NULL);
+
+ if (blks != dev_desc->lba) {
+ pr_err("Failed to erase mmc hwpart[%u]\n", dev_desc->hwpart);
+ return 1;
+ }
+
+ printf(" erased %lu bytes from mmc hwpart[%u]\n",
+ dev_desc->lba * dev_desc->blksz, dev_desc->hwpart);
+
+ return 0;
+}
+
+static void fb_mmc_boot1_ops(struct blk_desc *dev_desc, void *buffer,
+u32 buff_sz, char *response)
+{
+ lbaint_t blkcnt;
+ lbaint_t blks;
+ unsigned long blksz;
+
+ // To operate on EMMC_BOOT1 (mmc0boot0), we first change the hwpart
+ if (blk_dselect_hwpart(dev_desc, 1)) {
+ pr_err("Failed to select hwpart\n");
+ fastboot_fail("Failed to select hwpart", response);
+ return;
+ }
+
+ if (buffer) { /* flash */
+
+ /* determine number of blocks to write */
+ blksz = dev_desc->blksz;
+ blkcnt = ((buff_sz + (blksz - 1)) & ~(blksz - 1));
+ blkcnt = lldiv(blkcnt, blksz);
+
+ if (blkcnt > dev_desc->lba) {
+ pr_err("Image size too large\n");
+ fastboot_fail("Image size too large", response);
+ return;
+ }
+
+ debug("Start Flashing Image to EMMC_BOOT1...\n");
+
+ blks = fb_mmc_blk_write(dev_desc, 0, blkcnt, buffer);
+
+ if (blks != blkcnt) {
+ pr_err("Failed to write EMMC_BOOT1\n");
+ fastboot_fail("Failed to write EMMC_BOOT1", response);
+ return;
+ }
+
+ printf(" wrote %lu bytes
[PATCH 4/6] configs: mt8518: enable usb gadget driver
Enable board_late_init and usb gadget for mt8518 Signed-off-by: mingming lee --- configs/mt8518_ap1_emmc_defconfig | 10 ++ 1 file changed, 10 insertions(+) diff --git a/configs/mt8518_ap1_emmc_defconfig b/configs/mt8518_ap1_emmc_defconfig index dd42076f4d..9857b7b776 100644 --- a/configs/mt8518_ap1_emmc_defconfig +++ b/configs/mt8518_ap1_emmc_defconfig @@ -39,3 +39,13 @@ CONFIG_DM_MMC=y CONFIG_MMC_MTK=y CONFIG_MMC_HS200_SUPPORT=y # CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOARD_LATE_INIT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_DM_USB=y +CONFIG_USB_MUSB_GADGET=y +CONFIG_USB_MUSB_MT85XX=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_VENDOR_NUM=0x0bb4 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0c01 +CONFIG_USB_GADGET_MANUFACTURER="Mediatek." \ No newline at end of file -- 2.24.1
[PATCH 5/6] configs: mt8518: Enable fastboot related configs
Enable EFI module. Enable fastboot. Signed-off-by: mingming lee --- configs/mt8518_ap1_emmc_defconfig | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/configs/mt8518_ap1_emmc_defconfig b/configs/mt8518_ap1_emmc_defconfig index 9857b7b776..714fd8e087 100644 --- a/configs/mt8518_ap1_emmc_defconfig +++ b/configs/mt8518_ap1_emmc_defconfig @@ -34,6 +34,7 @@ CONFIG_WDT_MTK=y CONFIG_CLK=y CONFIG_TIMER=y CONFIG_MTK_TIMER=y +CONFIG_MMC=y CONFIG_CMD_MMC=y CONFIG_DM_MMC=y CONFIG_MMC_MTK=y @@ -48,4 +49,14 @@ CONFIG_USB_MUSB_MT85XX=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_GADGET_VENDOR_NUM=0x0bb4 CONFIG_USB_GADGET_PRODUCT_NUM=0x0c01 -CONFIG_USB_GADGET_MANUFACTURER="Mediatek." \ No newline at end of file +CONFIG_USB_GADGET_MANUFACTURER="Mediatek." +CONFIG_EFI_PARTITION=y +CONFIG_FASTBOOT_GPT_NAME=GPT +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_BUF_ADDR=0x5600 +CONFIG_FASTBOOT_BUF_SIZE=0x1E0 -- 2.24.1
[PATCH 2/6] ARM: Mediatek: Add board_late_init to init usb gadget driver
Add board_late_init function to init usb gadget driver for mt8518
Signed-off-by: mingming lee
---
board/mediatek/mt8518/mt8518_ap1.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/board/mediatek/mt8518/mt8518_ap1.c
b/board/mediatek/mt8518/mt8518_ap1.c
index 9710907fe2..2ac7c6cd18 100644
--- a/board/mediatek/mt8518/mt8518_ap1.c
+++ b/board/mediatek/mt8518/mt8518_ap1.c
@@ -16,3 +16,21 @@ int board_init(void)
debug("gd->fdt_blob is %p\n", gd->fdt_blob);
return 0;
}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_USB_GADGET
+ struct udevice *dev;
+ int ret;
+#endif
+
+#ifdef CONFIG_USB_GADGET
+ ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, );
+ if (ret) {
+ pr_err("%s: Cannot find USB device\n", __func__);
+ return ret;
+ }
+#endif
+
+ return 0;
+}
--
2.24.1
Larger ramdisk Bad Trap error
Hello, I'm booting kernel on my board with u-boot ramdisk image which is 39.8 MB. It boots successfully. When I try another u-boot image which has 74.7 MB size, load adress of ramdisk changing and its giving 'Loading Ramdisk to ff8c, end 03fffd63... Bad Trap at PC:7fef8cb0' and board hangs with ###ERROR ### Please RESET the board ### How can I solve this? Thanks.
RE: [PATCH 00/22] imx: add i.MX8MP support
> Subject: Re: [PATCH 00/22] imx: add i.MX8MP support > > Hi Peng, > > On Mon, Dec 30, 2019 at 10:31 PM Peng Fan wrote: > > > This is no public AT-F and ddr firmware for this board now. We are at > > early stage currently. until NXP software release, there will be public AT-F > and ddr firmware. > > Ok, understood, but please add a README file when these components > become public. > > What about i.MX8MN EVK board? There is still a missing README there and > the AT-F and firmwares are public at this point. I'll add one, since we already have 8MN public release now. Regards, Peng. > > It is getting hard to find the combination of U-Boot mainline + AT-F + > firmware > for i.MX8 family if they are not documented. > > Thanks
RE: ATF + u-boot imx8mm combination
> Subject: ATF + u-boot imx8mm combination > > HI all > > I'm trying to work on some imx8mm mainline but I understand that I miss > some of the information needed. I would like to work and play with power > domain. Can I know where to find all the information to build a version with a > valid combination? Upstream ATF has all the power domain init on. Downstream ATF not have all the power domain init on. Upstream/downstream U-Boot use SIP to trap to ATF to power on domain. Downstream Linux use SIP for power domain Upstream Linux not have power domain support. We are thinking SCMI or others for upstream Linux. Regards, Peng. > > Michael > > > -- > | Michael Nazzareno Trimarchi Amarula Solutions > BV | > | COO - Founder > Cruquiuskade 47 | > | +31(0)851119172 Amsterdam 1018 > AM NL | > | [`as] > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.a > marulasolutions.comdata=02%7C01%7Cpeng.fan%40nxp.com%7Cb96 > 430a7858146add7bf08d78f9118b3%7C686ea1d3bc2b4c6fa92cd99c5c30163 > 5%7C0%7C1%7C637135725659060375sdata=rOacvR%2FffEjLx3vLvaAt > G%2FbHqj8LS03Spuvmyu3AVFM%3Dreserved=0 |
Re: [RFC PATCH 5/5] board: Add new Samsung "stemmy" board based on ST-Ericsson U8500
On Sat, Jan 4, 2020 at 6:48 PM Stephan Gerhold wrote: > The ST-Ericsson U8500 SoC has been used in mass-production for > some Android smartphones released around 2012. > In particular, Samsung has released more than 5 different > smartphones based on U8500, e.g. > > - Samsung Galaxy S III mini (GT-I8190) "golden" > - Samsung Galaxy S Advance (GT-I9070) "janice" > - Samsung Galaxy Xcover 2 (GT-S7710) "skomer" > > and a few others. > > Mainline Linux has great support for the Ux500 SoC, so these > smartphones can also run Linux mainline quite well. > > Unfortunately, the original Samsung bootloader used on these devices > has limitations that prevent booting Linux mainline directly. > It keeps the L2 cache enabled, which causes Linux to crash very early, > shortly after decompressing the kernel. > > Using U-Boot allows to circumvent these limitations. We can let the > Samsung bootloader chain-load U-Boot and U-Boot locks the L2 cache > before booting into Linux. U-Boot has several other advantages > - it supports device-trees directly and we are no longer limited to > flashing Android boot images through Samsung's proprietary download > mode. > > The Samsung "stemmy" board covers all Samsung devices based on U8500. > Add minimal support for "stemmy". For now only UART is supported but > this will be extended later. > > Signed-off-by: Stephan Gerhold Reviewed-by: Linus Walleij Yours, Linus Walleij
RE: [PATCH 20/22] clk: imx: add i.MX8MP clk driver
Hi Lukasz, > Subject: Re: [PATCH 20/22] clk: imx: add i.MX8MP clk driver > > Hi Peng, > > > Add i.MX8MP clk driver for i.MX8MP CLK driver model usage > > > > Signed-off-by: Peng Fan > > Cc: Lukasz Majewski > > --- > > > > V1: > > To align with linux coding style, the 80 chars warning is not fixed. > > Is this a new patch or has it been already accepted in the Linux kernel? No. Linux Kernel side patch was also just out for reviewing. Thanks, Peng. > > > Best regards, > > Lukasz Majewski > > -- > > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: > lu...@denx.de
Re: [RFC PATCH 4/5] MAINTAINERS: Add ARM U8500
On Sat, Jan 4, 2020 at 6:48 PM Stephan Gerhold wrote: > Add myself as maintainer for ST-Ericsson U8500 SoC to MAINTAINERS. > Linus Walleij usually reviews all Ux500 related patches, > so add him as a reviewer. > > Cc: Linus Walleij > Signed-off-by: Stephan Gerhold Reviewed-by: Linus Walleij Yours, Linus Walleij
Re: [RFC PATCH 3/5] arm: Add support for ST-Ericsson U8500 SoC
On Sat, Jan 4, 2020 at 6:48 PM Stephan Gerhold wrote:
> The NovaThor U8500 SoC was released by ST-Ericsson in 2011.
> It was used for some development boards like the CALAO Systems
> Snowball SBC, but mass production was primarily for Android
> smartphones like the Samsung Galaxy S III mini.
>
> Previous support for U8500 was removed in
> commit 68282f55b846 ("arm: Remove unused ST-Ericsson u8500 arch")
> since none of the boards were converted to generic boards
> before the deadline.
>
> The new code does not have much in common with the previous code.
> I have completely rewritten everything, embracing the Driver Model
> and device trees wherever possible.
>
> The U8500 support is a bit more minimal for now - my primary
> use case is to use U-Boot as alternative bootloader for some of the
> U8500 Samsung smartphones. At the moment U-Boot is chain-loaded from
> the original Samsung bootloader. A side effect of this is that we
> can (temporarily) get away without implementing some functionality
> - e.g. all clocks are already enabled by the original bootloader.
>
> More functionality will be added in future patches.
>
> Cc: Mathieu Poirier
> Cc: John Rigby
> Signed-off-by: Stephan Gerhold
Reviewed-by: Linus Walleij
Yours,
Linus Walleij
Re: [RFC PATCH 2/5] arm: dts: Import device tree for ST-Ericsson Ux500
On Sat, Jan 4, 2020 at 6:48 PM Stephan Gerhold wrote:
> from
> https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git/
> tag "ux500-armsoc-v5.6-2"
> commit 224bf0fe7292 ("ARM: dts: ux500: samsung-golden: Add Bluetooth")
>
> (queued for merge in Linux 5.6)
>
> Signed-off-by: Stephan Gerhold
Reviewed-by: Linus Walleij
Yours,
Linus Walleij
Re: [RFC PATCH 1/5] timer: Add driver for Nomadik Multi Timer Unit (MTU)
On Sat, Jan 4, 2020 at 6:48 PM Stephan Gerhold wrote: > The Nomadik Multi Timer Unit (MTU) provides 4 decrementing > free-running timers. It is used in ST-Ericsson Ux500 SoCs. > > The driver uses the first timer to implement UCLASS_TIMER. > > Signed-off-by: Stephan Gerhold Reviewed-by: Linus Walleij Yours, Linus Walleij
Re: [PATCH 0/9] efi_loader: rework bootefi/bootmgr
Heinrich, On Fri, Jan 03, 2020 at 01:17:05AM +0100, Heinrich Schuchardt wrote: > On 4/19/19 5:22 AM, AKASHI Takahiro wrote: > >There are several reasons that I want to rework/refactor bootefi command > >as well as bootmgr: > >* Some previous commits on bootefi.c have made the code complicated > > and a bit hard to understand. > > > >* do_bootefi_exec() would better be implemented using load_image() along > > with start_image() to be aligned with UEFI interfaces. > > > >* Contrary to the other part, efi_selftest part of the code is unusual > > in terms of loading/execution path in do_bootefi(). > > > >* When we will support "secure boot" in the future, EFI Boot Manager > > is expected to be invoked as a standalone command without any arguments > > to mitigate security surfaces. > > > >In this patch set, > >Patch#1 to #7 are preparatory patches for patch#8. > >Patch#8 is a core part of reworking. > >Patch#9 is for standalone boot manager. > > > ># Please note that some patches, say patch#2 and #3, can be combined into one > ># but I intentionally keep them separated to clarify my intentions of > >changes. > > > >Issues: > >* It would be better off to change the semantics of efi_dp_from_name(). > >no chance to free loaded_image_info->load_options. (see patch #8) > > > >-Takahiro Akashi > > Hello Takahiro, > > with the `efidebug boot add` command we can define load options for the > Boot variables. > > But in do_efibootmgr() we call do_bootefi_exec() which calls > set_load_options() and passes the value of environment variable bootargs > as load options or if the variable is not set an empty string. > > Here is an example console output: > > => setenv bootargs This is a value from bootargs > => efidebug boot add hello scsi 0:1 helloworld.efi 'This is a value > from efidebug' > => efidebug boot order > => bootefi bootmgr > Booting: hello > Hello, world! > Running on UEFI 2.8 > Have SMBIOS table > Have device tree > Load options: This is a value from bootargs > ## Application terminated, r = 0 > > Now the same after deleting variable bootargs: > > => setenv bootargs > => bootefi bootmgr > Booting: hello > Hello, world! > Running on UEFI 2.8 > Have SMBIOS table > Have device tree > Load options: > ## Application terminated, r = 0 > => Yeah, this is not what I intended. > What behavior would you expect: > > a) if the boot option has a load options value, > b) if the boot option has no load options value? > > One solution would be to define that bootargs is always ignored if the > boot manager is used. I agree. Basically, "bootargs" is only for "bootefi " command, while "Boot" should work in the exact same way as the UEFI specification defines. Thanks, -Takahiro Akashi > Best regards > > Heinrich
[PATCH 5/6] sunxi: SPL SPI: Add SPI boot support for the Allwinner H6 SoC
The Allwinner H6 SoC uses a quite different memory map, also changes the
clocks quite a bit. This requires some changes to the SPL SPI routine,
which hardcodes these values so far.
Using the just introduced helper functions to determine base address
and SPI controller generation, we can cover some of these differences
easily.
The clock setup is different, so requires some explicit code changes
there (reset and clock gate in one register at a different address).
Also we need to change the pinmux function to use a different set of
pins that the H6 uses for SPI0.
Eventually we can enable the H6 to use SPI booting in Kconfig.
Signed-off-by: Andre Przywara
---
arch/arm/mach-sunxi/Kconfig | 2 +-
arch/arm/mach-sunxi/spl_spi_sunxi.c | 41 +
2 files changed, 33 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 0e07be802f..364b81b24c 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -993,7 +993,7 @@ config SPL_STACK_R_ADDR
config SPL_SPI_SUNXI
bool "Support for SPI Flash on Allwinner SoCs in SPL"
- depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5
|| MACH_SUN50I || MACH_SUN8I_R40
+ depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5
|| MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6
help
Enable support for SPI Flash. This option allows SPL to read from
sunxi SPI Flash. It uses the same method as the boot ROM, so does
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c
b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index c0b5a204fd..edfc46f275 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -72,7 +72,12 @@
/*/
#define CCM_AHB_GATING0 (0x01C2 + 0x60)
+#define CCM_H6_SPI_BGR_REG (0x03001000 + 0x96c)
+#ifdef CONFIG_MACH_SUN50I_H6
+#define CCM_SPI0_CLK(0x03001000 + 0x940)
+#else
#define CCM_SPI0_CLK(0x01C2 + 0xA0)
+#endif
#define SUN6I_BUS_SOFT_RST_REG0 (0x01C2 + 0x2C0)
#define AHB_RESET_SPI0_SHIFT20
@@ -86,14 +91,21 @@
/*
* Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
* from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
+ * The H6 uses PC0, PC2, PC3, PC5.
*/
static void spi0_pinmux_setup(unsigned int pin_function)
{
- unsigned int pin;
+ /* All chips use PC0 and PC2. */
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function);
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function);
- for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++)
- sunxi_gpio_set_cfgpin(pin, pin_function);
+ /* All chips except H6 use PC1, and only H6 uses PC5. */
+ if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function);
+ else
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function);
+ /* Older generations use PC23 for CS, newer ones use PC3. */
if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) ||
IS_ENABLED(CONFIG_MACH_SUN8I_R40))
sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
@@ -103,7 +115,8 @@ static void spi0_pinmux_setup(unsigned int pin_function)
static bool is_new_gen_spi(void)
{
- return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I);
+ return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ||
+ IS_ENABLED(CONFIG_MACH_SUN50I_H6);
}
static uintptr_t spi0_base_address(void)
@@ -111,6 +124,9 @@ static uintptr_t spi0_base_address(void)
if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
return 0x01C05000;
+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
+ return 0x0501;
+
if (!is_new_gen_spi())
return 0x01C05000;
@@ -125,12 +141,15 @@ static void spi0_enable_clock(void)
uintptr_t base = spi0_base_address();
/* Deassert SPI0 reset on SUN6I */
- if (is_new_gen_spi())
+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
+ setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
+ else if (is_new_gen_spi())
setbits_le32(SUN6I_BUS_SOFT_RST_REG0,
(1 << AHB_RESET_SPI0_SHIFT));
/* Open the SPI0 gate */
- setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
+ if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
+ setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
/* Divide by 4 */
writel(SPI0_CLK_DIV_BY_4, base + (is_new_gen_spi() ?
@@ -170,10 +189,13 @@ static void spi0_disable_clock(void)
writel(0, CCM_SPI0_CLK);
/* Close the SPI0 gate */
- clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
+ if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
+
[PATCH 2/6] sunxi: SPL SPI: Split off SPI0 base address
So far on all supported Allwinner SoCs we find the old generation SPI
controller always at address 0x1c05000, and the new generation one at
0x1c68000. However the Allwinner R40 SoC has a new generation SPI at
the old address, and the H6 uses a completely different address.
So split off the base address from the respective SPI registers, by
changing the #defines to just contain offsets.
The base address is provided by a function, so it can easily be extended
later when support for those SoCs materialises.
This does not change the code size (since the toolchain is clever enough
to optimise this properly), also does not bring any functional change at
this point.
Signed-off-by: Andre Przywara
---
arch/arm/mach-sunxi/spl_spi_sunxi.c | 94 +
1 file changed, 53 insertions(+), 41 deletions(-)
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c
b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 043d9f6ead..5b4598a25b 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -36,13 +36,13 @@
/* SUN4I variant of the SPI controller */
/*/
-#define SUN4I_SPI0_CCTL (0x01C05000 + 0x1C)
-#define SUN4I_SPI0_CTL (0x01C05000 + 0x08)
-#define SUN4I_SPI0_RX (0x01C05000 + 0x00)
-#define SUN4I_SPI0_TX (0x01C05000 + 0x04)
-#define SUN4I_SPI0_FIFO_STA (0x01C05000 + 0x28)
-#define SUN4I_SPI0_BC (0x01C05000 + 0x20)
-#define SUN4I_SPI0_TC (0x01C05000 + 0x24)
+#define SUN4I_SPI0_CCTL 0x1C
+#define SUN4I_SPI0_CTL 0x08
+#define SUN4I_SPI0_RX 0x00
+#define SUN4I_SPI0_TX 0x04
+#define SUN4I_SPI0_FIFO_STA 0x28
+#define SUN4I_SPI0_BC 0x20
+#define SUN4I_SPI0_TC 0x24
#define SUN4I_CTL_ENABLEBIT(0)
#define SUN4I_CTL_MASTERBIT(1)
@@ -54,15 +54,15 @@
/* SUN6I variant of the SPI controller */
/*/
-#define SUN6I_SPI0_CCTL (0x01C68000 + 0x24)
-#define SUN6I_SPI0_GCR (0x01C68000 + 0x04)
-#define SUN6I_SPI0_TCR (0x01C68000 + 0x08)
-#define SUN6I_SPI0_FIFO_STA (0x01C68000 + 0x1C)
-#define SUN6I_SPI0_MBC (0x01C68000 + 0x30)
-#define SUN6I_SPI0_MTC (0x01C68000 + 0x34)
-#define SUN6I_SPI0_BCC (0x01C68000 + 0x38)
-#define SUN6I_SPI0_TXD (0x01C68000 + 0x200)
-#define SUN6I_SPI0_RXD (0x01C68000 + 0x300)
+#define SUN6I_SPI0_CCTL 0x24
+#define SUN6I_SPI0_GCR 0x04
+#define SUN6I_SPI0_TCR 0x08
+#define SUN6I_SPI0_FIFO_STA 0x1C
+#define SUN6I_SPI0_MBC 0x30
+#define SUN6I_SPI0_MTC 0x34
+#define SUN6I_SPI0_BCC 0x38
+#define SUN6I_SPI0_TXD 0x200
+#define SUN6I_SPI0_RXD 0x300
#define SUN6I_CTL_ENABLEBIT(0)
#define SUN6I_CTL_MASTERBIT(1)
@@ -100,11 +100,21 @@ static void spi0_pinmux_setup(unsigned int pin_function)
sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
}
+static uintptr_t spi0_base_address(void)
+{
+ if (!IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
+ return 0x01C05000;
+
+ return 0x01C68000;
+}
+
/*
* Setup 6 MHz from OSC24M (because the BROM is doing the same).
*/
static void spi0_enable_clock(void)
{
+ uintptr_t base = spi0_base_address();
+
/* Deassert SPI0 reset on SUN6I */
if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
setbits_le32(SUN6I_BUS_SOFT_RST_REG0,
@@ -114,36 +124,37 @@ static void spi0_enable_clock(void)
setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
/* Divide by 4 */
- writel(SPI0_CLK_DIV_BY_4, IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ?
- SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL);
+ writel(SPI0_CLK_DIV_BY_4, base + (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ?
+ SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
/* 24MHz from OSC24M */
writel((1 << 31), CCM_SPI0_CLK);
if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) {
/* Enable SPI in the master mode and do a soft reset */
- setbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
-SUN6I_CTL_ENABLE |
-SUN6I_CTL_SRST);
+ setbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
+SUN6I_CTL_ENABLE | SUN6I_CTL_SRST);
/* Wait for completion */
- while (readl(SUN6I_SPI0_GCR) & SUN6I_CTL_SRST)
+ while (readl(base + SUN6I_SPI0_GCR) & SUN6I_CTL_SRST)
;
} else {
[PATCH 6/6] sunxi: Pine H64: Enable SPI booting in defconfig
The Pine H64 board comes with some onboard SPI flash chip, which is perfect for loading SPL, ATF and U-Boot proper from there. Enable the functionality in the defconfig, so that we use sunxi-fel to transfer a bootable image to the NOR flash. Signed-off-by: Andre Przywara --- configs/pine_h64_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index b49dbea4d4..c0adbf3dd0 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -16,3 +16,4 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_SPL_SPI_SUNXI=y -- 2.14.5
Re: [PATCH v5 4/6] lib: rsa: generate additional parameters for public key
Simon, On Fri, Dec 27, 2019 at 07:26:40PM -0700, Simon Glass wrote: > On Tue, 17 Dec 2019 at 01:53, AKASHI Takahiro > wrote: > > > > In the current implementation of FIT_SIGNATURE, five parameters for > > a RSA public key are required while only two of them are essential. > > (See rsa-mod-exp.h and uImage.FIT/signature.txt) > > This is a result of considering relatively limited computer power > > and resources on embedded systems, while such a assumption may not > > be quite practical for other use cases. > > > > In this patch, added is a function, rsa_gen_key_prop(), which will > > generate additional parameters for other uses, in particular > > UEFI secure boot, on the fly. > > > > Note: the current code uses some "big number" routines from BearSSL > > for the calculation. > > > > Signed-off-by: AKASHI Takahiro > > --- > > include/u-boot/rsa-mod-exp.h | 23 ++ > > lib/rsa/Kconfig | 3 + > > lib/rsa/Makefile | 1 + > > lib/rsa/rsa-keyprop.c| 725 +++ > > 4 files changed, 752 insertions(+) > > create mode 100644 lib/rsa/rsa-keyprop.c > > Reviewed-by: Simon Glass > > I think it would help to have the change log in each patch as well as > the cover letter. If you use patman it will do this for you. Ah, I didn't know that. It will take some time to learn more about patman. Thanks, -Takahiro Akashi
[PATCH 4/6] sunxi: SPL SPI: Add SPI boot support for the Allwinner R40 SoC
Now that we can easily select an SoC specific SPI0 base address, adding
support for the Allwinner R40 is fairly trivial:
We set the base address, add this SoC to the ones that use PC23 and
enable it in Kconfig.
This allows booting from SPI flash on R40 boards.
Tested on a Bananapi M2 Berry with SPI flash connected to the header pins.
Signed-off-by: Andre Przywara
---
arch/arm/mach-sunxi/Kconfig | 2 +-
arch/arm/mach-sunxi/spl_spi_sunxi.c | 6 +-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 16d41b83af..0e07be802f 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -993,7 +993,7 @@ config SPL_STACK_R_ADDR
config SPL_SPI_SUNXI
bool "Support for SPI Flash on Allwinner SoCs in SPL"
- depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5
|| MACH_SUN50I
+ depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5
|| MACH_SUN50I || MACH_SUN8I_R40
help
Enable support for SPI Flash. This option allows SPL to read from
sunxi SPI Flash. It uses the same method as the boot ROM, so does
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c
b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index b19f1bf4af..c0b5a204fd 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -94,7 +94,8 @@ static void spi0_pinmux_setup(unsigned int pin_function)
for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++)
sunxi_gpio_set_cfgpin(pin, pin_function);
- if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I))
+ if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) ||
+ IS_ENABLED(CONFIG_MACH_SUN8I_R40))
sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
else
sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
@@ -107,6 +108,9 @@ static bool is_new_gen_spi(void)
static uintptr_t spi0_base_address(void)
{
+ if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
+ return 0x01C05000;
+
if (!is_new_gen_spi())
return 0x01C05000;
--
2.14.5
[PATCH 0/6] sunxi: SPL SPI booting: Enable R40 and H6 SoCs
This series enables the SPI booting feature for Allwinner R40 and H6 SoCs. To achieve this, we enable our spl_spi_sunxi.c driver to deal with those two SoCs. The R40 is pretty straightforward, as it just needs its base address adjusted. This is prepared in patch 2/6 and finalised in patch 4/6. For the H6, on top of yet another different base address, the new clocks and slightly different pinmux setup need to be cared for. Patch 3/6 and 5/6 take care of that. Patch 6/6 enables this feature for the Pine H64 board, which comes with soldered SPI flash. Patch 1/6 deals with some annoyance in enabling SPI boot on new boards. This has been tested on the Pine H64 board and a Bananapi M2 Berry (with SPI flash connected to the SPI0-PortC header pins). For the existing SPI boot platforms this does not change the code size, as the toolchain is clever enough to optimise this properly. There is a similar series to enable SPI support for the sunxi-fel tool, which was used to test this. I will post this ASAP. Cheers, Andre. Andre Przywara (6): sunxi: move CONFIG_SYS_SPI_U_BOOT_OFFS out of defconfig sunxi: SPL SPI: Split off SPI0 base address sunxi: SPL SPI: Introduce is_new_gen_spi() sunxi: SPL SPI: Add SPI boot support for the Allwinner R40 SoC sunxi: SPL SPI: Add SPI boot support for the Allwinner H6 SoC sunxi: Pine H64: Enable SPI booting in defconfig arch/arm/mach-sunxi/Kconfig| 2 +- arch/arm/mach-sunxi/spl_spi_sunxi.c| 153 +++-- common/spl/Kconfig | 1 + configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 - configs/oceanic_5205_5inmfd_defconfig | 1 - configs/orangepi_pc2_defconfig | 1 - configs/orangepi_r1_defconfig | 1 - configs/orangepi_win_defconfig | 1 - configs/orangepi_zero_defconfig| 1 - configs/pine64-lts_defconfig | 1 - configs/pine_h64_defconfig | 1 + configs/sopine_baseboard_defconfig | 1 - 12 files changed, 102 insertions(+), 63 deletions(-) -- 2.14.5
[PATCH 3/6] sunxi: SPL SPI: Introduce is_new_gen_spi()
So far we were using the CONFIG_SUNXI_GEN_SUN6I symbol to select between
the two SPI controller generations used on Allwinner SoCs. This is a
convenience symbol to roughly differentiate between "older" and "newer"
generation of SoCs.
The H6 SoCs is the newest SoC so far, but is sufficiently different to
not define this symbol. However it is using a SPI controller compatible
to the "new gen" SoCs.
To prepare for H6 support, we replace the check for this single symbol
with an explicit function, which can later be extended.
For now we just return CONFIG_SUNXI_GEN_SUN6I in there, so this does not
create a functional change.
Signed-off-by: Andre Przywara
---
arch/arm/mach-sunxi/spl_spi_sunxi.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c
b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 5b4598a25b..b19f1bf4af 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -100,9 +100,14 @@ static void spi0_pinmux_setup(unsigned int pin_function)
sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
}
+static bool is_new_gen_spi(void)
+{
+ return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I);
+}
+
static uintptr_t spi0_base_address(void)
{
- if (!IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
+ if (!is_new_gen_spi())
return 0x01C05000;
return 0x01C68000;
@@ -116,7 +121,7 @@ static void spi0_enable_clock(void)
uintptr_t base = spi0_base_address();
/* Deassert SPI0 reset on SUN6I */
- if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
+ if (is_new_gen_spi())
setbits_le32(SUN6I_BUS_SOFT_RST_REG0,
(1 << AHB_RESET_SPI0_SHIFT));
@@ -124,12 +129,12 @@ static void spi0_enable_clock(void)
setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
/* Divide by 4 */
- writel(SPI0_CLK_DIV_BY_4, base + (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ?
+ writel(SPI0_CLK_DIV_BY_4, base + (is_new_gen_spi() ?
SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
/* 24MHz from OSC24M */
writel((1 << 31), CCM_SPI0_CLK);
- if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) {
+ if (is_new_gen_spi()) {
/* Enable SPI in the master mode and do a soft reset */
setbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
SUN6I_CTL_ENABLE | SUN6I_CTL_SRST);
@@ -150,7 +155,7 @@ static void spi0_disable_clock(void)
uintptr_t base = spi0_base_address();
/* Disable the SPI0 controller */
- if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
+ if (is_new_gen_spi())
clrbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
SUN6I_CTL_ENABLE);
else
@@ -164,7 +169,7 @@ static void spi0_disable_clock(void)
clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
/* Assert SPI0 reset on SUN6I */
- if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
+ if (is_new_gen_spi())
clrbits_le32(SUN6I_BUS_SOFT_RST_REG0,
(1 << AHB_RESET_SPI0_SHIFT));
}
@@ -184,7 +189,8 @@ static void spi0_deinit(void)
{
/* New SoCs can disable pins, older could only set them as input */
unsigned int pin_function = SUNXI_GPIO_INPUT;
- if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
+
+ if (is_new_gen_spi())
pin_function = SUNXI_GPIO_DISABLE;
spi0_disable_clock();
@@ -245,7 +251,7 @@ static void spi0_read_data(void *buf, u32 addr, u32 len)
if (chunk_len > SPI_READ_MAX_SIZE)
chunk_len = SPI_READ_MAX_SIZE;
- if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) {
+ if (is_new_gen_spi()) {
sunxi_spi0_read_data(buf8, addr, chunk_len,
base + SUN6I_SPI0_TCR,
SUN6I_TCR_XCH,
--
2.14.5
[PATCH 1/6] sunxi: move CONFIG_SYS_SPI_U_BOOT_OFFS out of defconfig
For Allwinner SoCs the CONFIG_SYS_SPI_U_BOOT_OFFS value is not really a board choice: The boot ROM only loads the SPL from offset 0 of the SPI NOR flash, and loads at most 32KB. This is a similar situation as on MMC, so consequently we create our "joint" image (SPL + U-Boot proper) with that 32KB offset during the build. So define the value of this symbol to be 32KB by default for every Allwinner SoC. This removes the definition of this symbol from the _defconfig files, and avoids every board to define this over and over again. Signed-off-by: Andre Przywara --- common/spl/Kconfig | 1 + configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 - configs/oceanic_5205_5inmfd_defconfig | 1 - configs/orangepi_pc2_defconfig | 1 - configs/orangepi_r1_defconfig | 1 - configs/orangepi_win_defconfig | 1 - configs/orangepi_zero_defconfig| 1 - configs/pine64-lts_defconfig | 1 - configs/sopine_baseboard_defconfig | 1 - 9 files changed, 1 insertion(+), 8 deletions(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index a72412718b..d85a5a6e2e 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1078,6 +1078,7 @@ endif # SPL_SPI_FLASH_SUPPORT config SYS_SPI_U_BOOT_OFFS hex "address of u-boot payload in SPI flash" + default 0x8000 if ARCH_SUNXI default 0x0 depends on SPL_SPI_LOAD || SPL_SPI_SUNXI help diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig index 588758a8ca..7dc736e9e1 100644 --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig @@ -15,7 +15,6 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/oceanic_5205_5inmfd_defconfig b/configs/oceanic_5205_5inmfd_defconfig index caab5fdb19..f71be7f127 100644 --- a/configs/oceanic_5205_5inmfd_defconfig +++ b/configs/oceanic_5205_5inmfd_defconfig @@ -11,7 +11,6 @@ CONFIG_MMC0_CD_PIN="" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-oceanic-5205-5inmfd" diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index 3d65b87d33..20209ec41b 100644 --- a/configs/orangepi_pc2_defconfig +++ b/configs/orangepi_pc2_defconfig @@ -10,7 +10,6 @@ CONFIG_MACPWR="PD6" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2" diff --git a/configs/orangepi_r1_defconfig b/configs/orangepi_r1_defconfig index b253d7f87b..0431fecb52 100644 --- a/configs/orangepi_r1_defconfig +++ b/configs/orangepi_r1_defconfig @@ -9,7 +9,6 @@ CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-r1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig index ad74febe10..13bf266260 100644 --- a/configs/orangepi_win_defconfig +++ b/configs/orangepi_win_defconfig @@ -7,7 +7,6 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win" diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig index 6fb2fbbda2..51d8ec001e 100644 --- a/configs/orangepi_zero_defconfig +++ b/configs/orangepi_zero_defconfig @@ -9,7 +9,6 @@ CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SUN8I_EMAC=y diff --git a/configs/pine64-lts_defconfig b/configs/pine64-lts_defconfig index a1c2d4245d..6e2c247c1a 100644 --- a/configs/pine64-lts_defconfig +++ b/configs/pine64-lts_defconfig @@ -11,7 +11,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USE_PREBOOT=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-lts" diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig index f4ab9ba9ab..87ed55264d 100644 ---
[PATCH V2 1/2] pico-imx7d: Disable USB_ETHER support for bl33 defconfig
For DM_ETH support , it's require to disable this config. When this config is enable, This generate a error with spl in linker script Signed-off-by: Joris Offouga --- configs/pico-imx7d_bl33_defconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index e54f3b12d4..a32b4d680f 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -64,9 +64,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_ETHER=y -CONFIG_USB_ETH_CDC=y -CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00" CONFIG_DM_VIDEO=y CONFIG_VIDEO_BPP8=y CONFIG_VIDEO_BPP16=y -- 2.20.1
[PATCH V2 2/2] pico-imx7d: Convert to DM_ETH
Signed-off-by: Joris Offouga
---
Change v1 -> v2
Disable usb ethernet support with patch : pico-imx7d: Disable USB_ETHER
support for bl33
board/technexion/pico-imx7d/pico-imx7d.c | 46
configs/pico-dwarf-imx7d_defconfig | 5 +++
configs/pico-hobbit-imx7d_defconfig | 5 +++
configs/pico-imx7d_bl33_defconfig| 5 +++
configs/pico-imx7d_defconfig | 5 +++
configs/pico-nymph-imx7d_defconfig | 5 +++
configs/pico-pi-imx7d_defconfig | 5 +++
include/configs/pico-imx7d.h | 11 --
8 files changed, 30 insertions(+), 57 deletions(-)
diff --git a/board/technexion/pico-imx7d/pico-imx7d.c
b/board/technexion/pico-imx7d/pico-imx7d.c
index bcfc7d361e..b7ca2e1315 100644
--- a/board/technexion/pico-imx7d/pico-imx7d.c
+++ b/board/technexion/pico-imx7d/pico-imx7d.c
@@ -16,7 +16,6 @@
#include
#include
#include
-#include
#include
#include
#include "../../freescale/common/pfuze.h"
@@ -26,11 +25,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
-#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
-#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
-
-#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
-
#define I2C_PAD_CTRL(PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
@@ -123,44 +117,6 @@ static iomux_v3_cfg_t const uart5_pads[] = {
};
#ifdef CONFIG_FEC_MXC
-static iomux_v3_cfg_t const fec1_pads[] = {
- MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
- MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
- MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC |
MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 |
MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 |
MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 |
MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 |
MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL |
MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_SD3_STROBE__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-#define FEC1_RST_GPIO IMX_GPIO_NR(6, 11)
-
-static void setup_iomux_fec(void)
-{
- imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
- gpio_request(FEC1_RST_GPIO, "phy_rst");
- gpio_direction_output(FEC1_RST_GPIO, 0);
- udelay(500);
- gpio_set_value(FEC1_RST_GPIO, 1);
-}
-
-int board_eth_init(bd_t *bis)
-{
- setup_iomux_fec();
-
- return fecmxc_initialize_multi(bis, 0,
- CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
-}
-
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
@@ -235,9 +191,7 @@ int board_init(void)
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_DM_VIDEO
-
setup_lcd();
-
#endif
#ifdef CONFIG_FEC_MXC
setup_fec();
diff --git a/configs/pico-dwarf-imx7d_defconfig
b/configs/pico-dwarf-imx7d_defconfig
index 5416b4581b..f328b41b8f 100644
--- a/configs/pico-dwarf-imx7d_defconfig
+++ b/configs/pico-dwarf-imx7d_defconfig
@@ -59,6 +59,11 @@ CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
diff --git a/configs/pico-hobbit-imx7d_defconfig
b/configs/pico-hobbit-imx7d_defconfig
index 57b64c632f..ea127069e9 100644
--- a/configs/pico-hobbit-imx7d_defconfig
+++ b/configs/pico-hobbit-imx7d_defconfig
@@ -59,6 +59,11 @@ CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
diff --git a/configs/pico-imx7d_bl33_defconfig
b/configs/pico-imx7d_bl33_defconfig
index a32b4d680f..db9daf9d69 100644
--- a/configs/pico-imx7d_bl33_defconfig
+++ b/configs/pico-imx7d_bl33_defconfig
@@ -50,6 +50,11 @@ CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PINCTRL=y
Re: [PATCH 1/1] net: tftp: use correct printf codes
On Wed, Jan 1, 2020 at 4:16 PM Heinrich Schuchardt wrote: > > When printing unsigned numbers use %u. > > Signed-off-by: Heinrich Schuchardt Acked-by: Joe Hershberger
Re: [PATCH v3 3/9] cmd: abootimg: Add abootimg command
Hi,
With below nits, I have provided the Reviewed-by/Tested-by signatures.
On Tue, Dec 24, 2019 at 09:54:49PM +0200, Sam Protsenko wrote:
> This command can be used to extract fields and image payloads from
> Android Boot Image. It can be used for example to implement boot flow
> where dtb is taken from boot.img (as v2 incorporated dtb inside of
> boot.img). Using this command, one can obtain needed dtb blob from
> boot.img in scripting manner, and then apply needed dtbo's (from "dtbo"
FWIW, 'scripted manner' is more common, as suggested by Ngram:
https://tinyurl.com/rck3ysj
> diff --git a/cmd/abootimg.c b/cmd/abootimg.c
> +static int abootimg_get_dtb_by_index(int argc, char * const argv[])
> +{
> + u32 num;
> + char *endp;
> + ulong addr;
> + u32 size;
> +
> + if (argc < 1 || argc > 3)
> + return CMD_RET_USAGE;
> +
> + num = simple_strtoul(argv[0] + strlen("--index="), , 0);
> + if (*endp != '\0') {
> + printf("Error: Wrong num\n");
> + return CMD_RET_FAILURE;
> + }
The way '--index=' option is processed right now results in below
inconsistencies:
=> abootimg get dtb --index=0
1980
`- expected output
=> abootimg get dtb --index=
1980
`- unexpected output (expected error)
=> abootimg get dtb --index=0 --index=1
=>
`- unexpected output (expected error)
> +U_BOOT_CMD(
> + abootimg, CONFIG_SYS_MAXARGS, 0, do_abootimg,
> + "manipulate Android Boot Image",
> + "addr \n"
> + "- set the address in RAM where boot image is located\n"
> + " ($loadaddr is used by default)\n"
> + "abootimg dump dtb\n"
> + "- print info for all DT blobs in DTB area\n"
> + "abootimg get ver [varname]\n"
> + "- get header version\n"
> + "abootimg get recovery_dtbo [addr_var [size_var]]\n"
> + "- get address and size (hex) of recovery DTBO area in the image\n"
> + " [addr_var]: variable name to contain DTBO area address\n"
> + " [size_var]: variable name to contain DTBO area size\n"
> + "abootimg get dtb_load_addr [varname]\n"
> + "- get load address (hex) of DTB, from image header\n"
> + "abootimg get dtb --index= [addr_var [size_var]]\n"
> + "- get address and size (hex) of DT blob in the image by index\n"
> + " : index number of desired DT blob in DTB area\n"
> + " [addr_var]: variable name to contain DT blob address\n"
> + " [size_var]: variable name to contain DT blob size\n"
[minor] Superfluous blank line at the end of help.
Apart from the above, testing two Android v2 images containing the
DTB in so called "concat" and DTBO formats didn't reveal any issues.
Reviewed-by: Eugeniu Rosca
Tested-by: Eugeniu Rosca
--
Best Regards,
Eugeniu
Re: [PATCH] pico-imx7d: Convert to DM_ETH
On Sun, Jan 5, 2020 at 7:32 AM Stefano Babic wrote: > > On 04/01/20 13:03, Joris Offouga wrote: > > Hi Stefano, > > > > Sorry for the delay, > > > > Le 28/12/2019 à 12:31, Stefano Babic a écrit : > >> Hi Joris, > >> > >> > >> > >> On 08/12/19 18:02, Joris Offouga wrote: > >>> Signed-off-by: Joris Offouga > >>> --- > >>> board/technexion/pico-imx7d/pico-imx7d.c | 46 > >>> configs/pico-dwarf-imx7d_defconfig | 5 +++ > >>> configs/pico-hobbit-imx7d_defconfig | 5 +++ > >>> configs/pico-imx7d_bl33_defconfig| 5 +++ > >>> configs/pico-imx7d_defconfig | 5 +++ > >>> configs/pico-nymph-imx7d_defconfig | 5 +++ > >>> configs/pico-pi-imx7d_defconfig | 5 +++ > >>> include/configs/pico-imx7d.h | 11 -- > >>> 8 files changed, 30 insertions(+), 57 deletions(-) > >>> > >> I get build errors with pico-imx7d_bl33. > >> > >> https://travis-ci.org/sbabic/u-boot-imx/jobs/630056283 > >> > >> > >> Could you take a look, please ? > > > > I tried to correct the compilation error but I did not find good ways to > > do it, I suggest you remove the usb ethernet support from the > > configuration : > > > > -CONFIG_USB_ETHER=y > > -CONFIG_USB_ETH_CDC=y > > -CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00" > > > > If you agree I send V2 > > If the board maintainer (Otavio) agrees it, I am fine. I agree. However, do this as a commit prior to this one so if someone ever wants to revert it is easy. Also, explain the reasoning on the commit log. -- Otavio Salvador O.S. Systems http://www.ossystems.com.brhttp://code.ossystems.com.br Mobile: +55 (53) 9 9981-7854 Mobile: +1 (347) 903-9750
[PATCH] arm: Add arm handoff header file
Add an arch-specific handoff header so that we can use the HANDOFF feature
on arm devices.
Signed-off-by: Michael Trimarchi
---
arch/arm/include/asm/handoff.h | 21 +
1 file changed, 21 insertions(+)
create mode 100644 arch/arm/include/asm/handoff.h
diff --git a/arch/arm/include/asm/handoff.h b/arch/arm/include/asm/handoff.h
new file mode 100644
index 00..0790d2ab1e
--- /dev/null
+++ b/arch/arm/include/asm/handoff.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Architecture-specific SPL handoff information for ARM
+ *
+ * Copyright 2019 Amarula Solutions, BV
+ * Written by Michael Trimarchi
+ */
+
+#ifndef __asm_handoff_h
+#define __asm_handoff_h
+
+/**
+ * struct arch_spl_handoff - architecture-specific handoff info
+ *
+ * @usable_ram_top: Value returned by board_get_usable_ram_top() in SPL
+ */
+struct arch_spl_handoff {
+ ulong usable_ram_top;
+};
+
+#endif
--
2.17.1
[PATCH 2/2] mtd: nand: spi: add support for Toshiba TC58CVG2S0HRAIJ
Toshiba recently launched new revisions of their serial SLC NAND series.
TC58CVG2S0HRAIJ is a refresh of previous series with minor improvements.
Basic parameters are same so lets add support for this new revision.
Datasheet:
https://business.kioxia.com/info/docget.jsp?did=58601=TC58CVG2S0HRAIJ
Signed-off-by: Robert Marko
Tested-by: Luka Kovacic
Cc: Luka Perkov
---
drivers/mtd/nand/spi/toshiba.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c
index 29846cf4bd..f0524fa94f 100644
--- a/drivers/mtd/nand/spi/toshiba.c
+++ b/drivers/mtd/nand/spi/toshiba.c
@@ -126,6 +126,16 @@ static const struct spinand_info toshiba_spinand_table[] =
{
0,
SPINAND_ECCINFO(_ooblayout,
tc58cxgxsx_ecc_get_status)),
+ /* 3.3V 4Gb */
+ SPINAND_INFO("TC58CVG2S0", 0xED,
+NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
+NAND_ECCREQ(8, 512),
+SPINAND_INFO_OP_VARIANTS(_cache_variants,
+ _cache_variants,
+ _cache_variants),
+0,
+SPINAND_ECCINFO(_ooblayout,
+tc58cxgxsx_ecc_get_status)),
/* 1.8V 1Gb */
SPINAND_INFO("TC58CYG0S3", 0xB2,
NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
--
2.24.1
[PATCH 1/2] mtd: spi-nand: Import Toshiba SPI-NAND support
Linux has good support for Toshiba SPI-NAND, so lets import it.
Signed-off-by: Robert Marko
Tested-by: Luka Kovacic
Cc: Luka Perkov
---
drivers/mtd/nand/spi/Makefile | 2 +-
drivers/mtd/nand/spi/core.c| 1 +
drivers/mtd/nand/spi/toshiba.c | 190 +
include/linux/mtd/spinand.h| 1 +
4 files changed, 193 insertions(+), 1 deletion(-)
create mode 100644 drivers/mtd/nand/spi/toshiba.c
diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile
index dd6bacae34..6c65b187e8 100644
--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
@@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-spinand-objs := core.o gigadevice.o macronix.o micron.o winbond.o
+spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index cb8ffa3fa9..67ebbdcb08 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -833,6 +833,7 @@ static const struct spinand_manufacturer
*spinand_manufacturers[] = {
_spinand_manufacturer,
_spinand_manufacturer,
_spinand_manufacturer,
+ _spinand_manufacturer,
_spinand_manufacturer,
};
diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c
new file mode 100644
index 00..29846cf4bd
--- /dev/null
+++ b/drivers/mtd/nand/spi/toshiba.c
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 exceet electronics GmbH
+ * Copyright (c) 2018 Kontron Electronics GmbH
+ *
+ * Author: Frieder Schrempf
+ */
+
+#ifndef __UBOOT__
+#include
+#include
+#endif
+#include
+
+#define SPINAND_MFR_TOSHIBA0x98
+#define TOSH_STATUS_ECC_HAS_BITFLIPS_T (3 << 4)
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int tc58cxgxsx_ooblayout_ecc(struct mtd_info *mtd, int section,
+struct mtd_oob_region *region)
+{
+ if (section > 0)
+ return -ERANGE;
+
+ region->offset = mtd->oobsize / 2;
+ region->length = mtd->oobsize / 2;
+
+ return 0;
+}
+
+static int tc58cxgxsx_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 0)
+ return -ERANGE;
+
+ /* 2 bytes reserved for BBM */
+ region->offset = 2;
+ region->length = (mtd->oobsize / 2) - 2;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops tc58cxgxsx_ooblayout = {
+ .ecc = tc58cxgxsx_ooblayout_ecc,
+ .free = tc58cxgxsx_ooblayout_free,
+};
+
+static int tc58cxgxsx_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ struct nand_device *nand = spinand_to_nand(spinand);
+ u8 mbf = 0;
+ struct spi_mem_op op = SPINAND_GET_FEATURE_OP(0x30, );
+
+ switch (status & STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ case STATUS_ECC_HAS_BITFLIPS:
+ case TOSH_STATUS_ECC_HAS_BITFLIPS_T:
+ /*
+* Let's try to retrieve the real maximum number of bitflips
+* in order to avoid forcing the wear-leveling layer to move
+* data around if it's not necessary.
+*/
+ if (spi_mem_exec_op(spinand->slave, ))
+ return nand->eccreq.strength;
+
+ mbf >>= 4;
+
+ if (WARN_ON(mbf > nand->eccreq.strength || !mbf))
+ return nand->eccreq.strength;
+
+ return mbf;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static const struct spinand_info toshiba_spinand_table[] = {
+ /* 3.3V 1Gb */
+ SPINAND_INFO("TC58CVG0S3", 0xC2,
+NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+NAND_ECCREQ(8, 512),
+SPINAND_INFO_OP_VARIANTS(_cache_variants,
+ _cache_variants,
+ _cache_variants),
+0,
+SPINAND_ECCINFO(_ooblayout,
+tc58cxgxsx_ecc_get_status)),
+ /* 3.3V 2Gb */
+ SPINAND_INFO("TC58CVG1S3", 0xCB,
+NAND_MEMORG(1, 2048, 128,
Re: [PATCH] Revert "mmc: davinci: drop struct davinci_mmc_plat"
On Fri, Jan 03, 2020 at 01:17:07PM -0500, Tom Rini wrote: > Adam Ford reports that this change breaks booting on da850-evm and > Bartosz Golaszewski agrees that with the impending release we should > revert the change for now. With that noted: > > This reverts commit 21a4d80a710c79053ac1deaa65ff9b69e6c031d4. > > Cc: Bartosz Golaszewski > Tested-by: Adam Ford > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] pico-imx7d: Convert to DM_ETH
Hi Joris,
On 04/01/20 13:03, Joris Offouga wrote:
> Hi Stefano,
>
> Sorry for the delay,
>
> Le 28/12/2019 à 12:31, Stefano Babic a écrit :
>> Hi Joris,
>>
>>
>>
>> On 08/12/19 18:02, Joris Offouga wrote:
>>> Signed-off-by: Joris Offouga
>>> ---
>>> board/technexion/pico-imx7d/pico-imx7d.c | 46
>>> configs/pico-dwarf-imx7d_defconfig | 5 +++
>>> configs/pico-hobbit-imx7d_defconfig | 5 +++
>>> configs/pico-imx7d_bl33_defconfig | 5 +++
>>> configs/pico-imx7d_defconfig | 5 +++
>>> configs/pico-nymph-imx7d_defconfig | 5 +++
>>> configs/pico-pi-imx7d_defconfig | 5 +++
>>> include/configs/pico-imx7d.h | 11 --
>>> 8 files changed, 30 insertions(+), 57 deletions(-)
>>>
>> I get build errors with pico-imx7d_bl33.
>>
>> https://travis-ci.org/sbabic/u-boot-imx/jobs/630056283
>>
>>
>> Could you take a look, please ?
>
> I tried to correct the compilation error but I did not find good ways to
> do it, I suggest you remove the usb ethernet support from the
> configuration :
>
> -CONFIG_USB_ETHER=y
> -CONFIG_USB_ETH_CDC=y
> -CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
>
> If you agree I send V2
If the board maintainer (Otavio) agrees it, I am fine.
Best regards,
Stefano
>
> Best regards,
>
> Joris
>
>>
>> Best regards,
>> Stefano
>>
>>> diff --git a/board/technexion/pico-imx7d/pico-imx7d.c
>>> b/board/technexion/pico-imx7d/pico-imx7d.c
>>> index bcfc7d361e..b7ca2e1315 100644
>>> --- a/board/technexion/pico-imx7d/pico-imx7d.c
>>> +++ b/board/technexion/pico-imx7d/pico-imx7d.c
>>> @@ -16,7 +16,6 @@
>>> #include
>>> #include
>>> #include
>>> -#include
>>> #include
>>> #include
>>> #include "../../freescale/common/pfuze.h"
>>> @@ -26,11 +25,6 @@ DECLARE_GLOBAL_DATA_PTR;
>>> #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
>>> PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
>>> -#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM |
>>> PAD_CTL_DSE_3P3V_49OHM)
>>> -#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
>>> -
>>> -#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM |
>>> PAD_CTL_DSE_3P3V_49OHM)
>>> -
>>> #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
>>> PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
>>> @@ -123,44 +117,6 @@ static iomux_v3_cfg_t const uart5_pads[] = {
>>> };
>>> #ifdef CONFIG_FEC_MXC
>>> -static iomux_v3_cfg_t const fec1_pads[] = {
>>> - MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
>>> - MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
>>> - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC |
>>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 |
>>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 |
>>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 |
>>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 |
>>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL |
>>> MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC |
>>> MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>>> - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 |
>>> MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>>> - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 |
>>> MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>>> - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 |
>>> MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>>> - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 |
>>> MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>>> - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL |
>>> MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
>>> - MX7D_PAD_SD3_STROBE__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
>>> - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
>>> -};
>>> -
>>> -#define FEC1_RST_GPIO IMX_GPIO_NR(6, 11)
>>> -
>>> -static void setup_iomux_fec(void)
>>> -{
>>> - imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
>>> - gpio_request(FEC1_RST_GPIO, "phy_rst");
>>> - gpio_direction_output(FEC1_RST_GPIO, 0);
>>> - udelay(500);
>>> - gpio_set_value(FEC1_RST_GPIO, 1);
>>> -}
>>> -
>>> -int board_eth_init(bd_t *bis)
>>> -{
>>> - setup_iomux_fec();
>>> -
>>> - return fecmxc_initialize_multi(bis, 0,
>>> - CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
>>> -}
>>> -
>>> static int setup_fec(void)
>>> {
>>> struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
>>> @@ -235,9 +191,7 @@ int board_init(void)
>>> gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
>>> #ifdef CONFIG_DM_VIDEO
>>> -
>>> setup_lcd();
>>> -
>>> #endif
>>> #ifdef CONFIG_FEC_MXC
>>> setup_fec();
>>> diff --git a/configs/pico-dwarf-imx7d_defconfig
>>> b/configs/pico-dwarf-imx7d_defconfig
>>> index 94d73ee051..2437a64dd0 100644
>>> --- a/configs/pico-dwarf-imx7d_defconfig
>>> +++ b/configs/pico-dwarf-imx7d_defconfig
>>> @@ -59,6 +59,11 @@ CONFIG_SUPPORT_EMMC_BOOT=y
>>>
[PATCH v2 1/1] efi_loader: define all known warning status codes
Of all warning status codes up to now only EFI_WARN_DELETE_FAILURE is
defined.
The patch adds the missing definitions for later usage.
Signed-off-by: Heinrich Schuchardt
---
v2
Remove unrelated change
---
include/efi.h | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/include/efi.h b/include/efi.h
index 5f415a99cc..e12697a5d5 100644
--- a/include/efi.h
+++ b/include/efi.h
@@ -91,7 +91,13 @@ typedef struct {
#define EFI_IP_ADDRESS_CONFLICT(EFI_ERROR_MASK | 34)
#define EFI_HTTP_ERROR (EFI_ERROR_MASK | 35)
-#define EFI_WARN_DELETE_FAILURE2
+#define EFI_WARN_UNKNOWN_GLYPH 1
+#define EFI_WARN_DELETE_FAILURE2
+#define EFI_WARN_WRITE_FAILURE 3
+#define EFI_WARN_BUFFER_TOO_SMALL 4
+#define EFI_WARN_STALE_DATA5
+#define EFI_WARN_FILE_SYSTEM 6
+#define EFI_WARN_RESET_REQUIRED7
typedef unsigned long efi_status_t;
typedef u64 efi_physical_addr_t;
--
2.24.1
