[PATCH 2/2] efi_selftest: add selftests for loadfile2 used to load initramfs

[Ilias Apalodimas]

Provide a unit test loading an initial ramdisk using the
EFI_LOAD_FILE2_PROTOCOL. The test is only executed on request.

An example usage - given a file image with a file system in partition 1
holding file initrd - is:

* Configure the sandbox with

  CONFIG_EFI_SELFTEST=y
  CONFIG_EFI_LOAD_FILE2_INITRD=y
  CONFIG_EFI_INITRD_FILESPEC="host 0:1 initrd"

* Run ./u-boot and execute

host bind 0 image
setenv efi_selftest load initrd
bootefi selftest

This would provide a test output like:

Testing EFI API implementation

Selected test: 'load initrd'

Setting up 'load initrd'
Setting up 'load initrd' succeeded

Executing 'load initrd'
Loaded 12378613 bytes
CRC32 2997478465
Executing 'load initrd' succeeded

Now the size and CRC32 can be compared to the provided file.

Signed-off-by: Ilias Apalodimas 
Signed-off-by: Heinrich Schuchardt 
---
 lib/efi_selftest/Makefile   |   1 +
 lib/efi_selftest/efi_selftest_load_initrd.c | 220 
 2 files changed, 221 insertions(+)
 create mode 100644 lib/efi_selftest/efi_selftest_load_initrd.c

diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile
index 3ad96e1cbf08..cf132c372e17 100644
--- a/lib/efi_selftest/Makefile
+++ b/lib/efi_selftest/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_CPU_V7) += efi_selftest_unaligned.o
 obj-$(CONFIG_EFI_LOADER_HII) += efi_selftest_hii.o
 obj-$(CONFIG_EFI_RNG_PROTOCOL) += efi_selftest_rng.o
 obj-$(CONFIG_EFI_GET_TIME) += efi_selftest_rtc.o
+obj-$(CONFIG_EFI_LOAD_FILE2_INITRD) += efi_selftest_load_initrd.o
 
 ifeq ($(CONFIG_GENERATE_ACPI_TABLE),)
 obj-y += efi_selftest_fdt.o
diff --git a/lib/efi_selftest/efi_selftest_load_initrd.c 
b/lib/efi_selftest/efi_selftest_load_initrd.c
new file mode 100644
index ..e16163caca85
--- /dev/null
+++ b/lib/efi_selftest/efi_selftest_load_initrd.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_load_initrd
+ *
+ * Copyright (c) 2020 Ilias Apalodimas 
+ *
+ * This test checks the FileLoad2 protocol.
+ * A known file is read from the file system and verified.
+ *
+ * An example usage - given a file image with a file system in partition 1
+ * holding file initrd - is:
+ *
+ * * Configure the sandbox with
+ *
+ *   CONFIG_EFI_SELFTEST=y
+ *   CONFIG_EFI_LOAD_FILE2_INITRD=y
+ *   CONFIG_EFI_INITRD_FILESPEC="host 0:1 initrd"
+ *
+ * * Run ./u-boot and execute
+ *
+ *   host bind 0 image
+ *   setenv efi_selftest load initrd
+ *   bootefi selftest
+ *
+ * This would provide a test output like:
+ *
+ *   Testing EFI API implementation
+ *
+ *   Selected test: 'load initrd'
+ *
+ *   Setting up 'load initrd'
+ *   Setting up 'load initrd' succeeded
+ *
+ *   Executing 'load initrd'
+ *   Loaded 12378613 bytes
+ *   CRC32 2997478465
+ *
+ * Now the size and CRC32 can be compared to the provided file.
+ */
+
+#include 
+#include 
+#include 
+
+static struct efi_boot_services *boottime;
+
+static struct efi_initrd_dp dp = {
+   .vendor = {
+   {
+  DEVICE_PATH_TYPE_MEDIA_DEVICE,
+  DEVICE_PATH_SUB_TYPE_VENDOR_PATH,
+  sizeof(dp.vendor),
+   },
+   EFI_INITRD_MEDIA_GUID,
+   },
+   .end = {
+   DEVICE_PATH_TYPE_END,
+   DEVICE_PATH_SUB_TYPE_END,
+   sizeof(dp.end),
+   }
+};
+
+static struct efi_initrd_dp dp_invalid = {
+   .vendor = {
+   {
+  DEVICE_PATH_TYPE_MEDIA_DEVICE,
+  DEVICE_PATH_SUB_TYPE_VENDOR_PATH,
+  sizeof(dp.vendor),
+   },
+   EFI_INITRD_MEDIA_GUID,
+   },
+   .end = {
+   0x8f, /* invalid */
+   0xfe, /* invalid */
+   sizeof(dp.end),
+   }
+};
+
+static int setup(const efi_handle_t handle,
+const struct efi_system_table *systable)
+{
+   boottime = systable->boottime;
+
+   return EFI_ST_SUCCESS;
+}
+
+static int execute(void)
+{
+   efi_guid_t lf2_proto_guid = EFI_LOAD_FILE2_PROTOCOL_GUID;
+   struct efi_load_file_protocol *lf2;
+   struct efi_device_path *dp2, *dp2_invalid;
+   efi_status_t status;
+   efi_handle_t handle;
+   char buffer[64];
+   efi_uintn_t buffer_size;
+   void *buf;
+   u32 crc32;
+
+   memset(buffer, 0, sizeof(buffer));
+
+   dp2 = (struct efi_device_path *)
+   status = boottime->locate_device_path(_proto_guid, , );
+   if (status != EFI_SUCCESS) {
+   efi_st_error("Unable to locate device path\n");
+   return EFI_ST_FAILURE;
+   }
+
+   status = boottime->handle_protocol(handle, _proto_guid,
+  (void **));
+   if (status != EFI_SUCCESS) {
+   efi_st_error("Unable to locate protocol\n");
+   return EFI_ST_FAILURE;
+   }
+
+   /* Case 1:
+* buffer_size can't be NULL
+* protocol can't be NULL
+  

[PATCH 1/2] efi_loader: Implement FileLoad2 for initramfs loading

[Ilias Apalodimas]

Following kernel's proposal for an arch-agnostic initrd loading
mechanism [1] let's implement the U-boot counterpart.
This new approach has a number of advantages compared to what we did up
to now. The file is loaded into memory only when requested limiting the
area of TOCTOU attacks. Users will be allowed to place the initramfs
file on any u-boot accessible partition instead of just the ESP one.
Finally this is an attempt of a generic interface across architectures
in the linux kernel so it makes sense to support that.

The file location is intentionally only supported as a config option
argument(CONFIG_EFI_INITRD_FILESPEC), in an effort to enhance security.
Although U-boot is not responsible for verifying the integrity of the
initramfs, we can enhance the offered security by only accepting a
built-in option, which will be naturally verified by UEFI Secure Boot.
This can easily change in the future if needed and configure that via ENV
or UEFI variable.

[1] 
https://lore.kernel.org/linux-efi/20200207202637.ga3464...@rani.riverdale.lan/T/#m4a25eb33112fab7a22faa0fd65d4d663209af32f

Signed-off-by: Ilias Apalodimas 
Signed-off-by: Heinrich Schuchardt 
---
 cmd/efidebug.c   |   4 +
 include/efi_api.h|  17 +++
 include/efi_load_initrd.h|  25 
 include/efi_loader.h |   1 +
 lib/efi_loader/Kconfig   |  15 +++
 lib/efi_loader/Makefile  |   1 +
 lib/efi_loader/efi_load_initrd.c | 198 +++
 lib/efi_loader/efi_setup.c   |   5 +
 8 files changed, 266 insertions(+)
 create mode 100644 include/efi_load_initrd.h
 create mode 100644 lib/efi_loader/efi_load_initrd.c

diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index 576e95b395dc..f450518c9e83 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -264,6 +264,10 @@ static const struct {
"SMBIOS table",
SMBIOS_TABLE_GUID,
},
+   {
+   "Load File2",
+   EFI_LOAD_FILE2_PROTOCOL_GUID,
+   },
 };
 
 /**
diff --git a/include/efi_api.h b/include/efi_api.h
index 22396172e15f..8ffed1334b84 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -319,6 +319,14 @@ struct efi_runtime_services {
EFI_GUID(0xeb9d2d31, 0x2d88, 0x11d3,  \
 0x9a, 0x16, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
 
+#define EFI_LOAD_FILE_PROTOCOL_GUID \
+   EFI_GUID(0x56ec3091, 0x954c, 0x11d2, \
+0x8e, 0x3f, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
+
+#define EFI_LOAD_FILE2_PROTOCOL_GUID \
+   EFI_GUID(0x4006c0c1, 0xfcb3, 0x403e, \
+0x99, 0x6d, 0x4a, 0x6c, 0x87, 0x24, 0xe0, 0x6d)
+
 struct efi_configuration_table {
efi_guid_t guid;
void *table;
@@ -474,6 +482,7 @@ struct efi_device_path_nvme {
 #define DEVICE_PATH_TYPE_MEDIA_DEVICE  0x04
 #  define DEVICE_PATH_SUB_TYPE_HARD_DRIVE_PATH 0x01
 #  define DEVICE_PATH_SUB_TYPE_CDROM_PATH  0x02
+#  define DEVICE_PATH_SUB_TYPE_VENDOR_PATH 0x03
 #  define DEVICE_PATH_SUB_TYPE_FILE_PATH   0x04
 
 struct efi_device_path_hard_drive_path {
@@ -1607,6 +1616,14 @@ struct efi_unicode_collation_protocol {
char *supported_languages;
 };
 
+struct efi_load_file_protocol {
+   efi_status_t (EFIAPI *load_file)(struct efi_load_file_protocol *this,
+struct efi_device_path *file_path,
+bool boot_policy,
+efi_uintn_t *buffer_size,
+void *buffer);
+};
+
 /* Boot manager load options */
 #define LOAD_OPTION_ACTIVE 0x0001
 #define LOAD_OPTION_FORCE_RECONNECT0x0002
diff --git a/include/efi_load_initrd.h b/include/efi_load_initrd.h
new file mode 100644
index ..478ae807c685
--- /dev/null
+++ b/include/efi_load_initrd.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020, Linaro Limited
+ */
+
+#if !defined _EFI_LOAD_INITRD_H_
+#define _EFI_LOAD_INITRD_H_
+
+#include 
+#include 
+
+/*
+ * Vendor GUID used by Linux to identify the handle with the
+ * EFI_LOAD_FILE2_PROTOCOL and load an initial ramdisk.
+ */
+#define EFI_INITRD_MEDIA_GUID \
+   EFI_GUID(0x5568e427, 0x68fc, 0x4f3d, \
+0xac, 0x74, 0xca, 0x55, 0x52, 0x31, 0xcc, 0x68)
+
+struct efi_initrd_dp {
+   struct efi_device_path_vendor vendor;
+   struct efi_device_path end;
+} __packed;
+
+#endif
diff --git a/include/efi_loader.h b/include/efi_loader.h
index d4c59b54c48b..8e3437983391 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -378,6 +378,7 @@ efi_status_t efi_gop_register(void);
 efi_status_t efi_net_register(void);
 /* Called by bootefi to make the watchdog available */
 efi_status_t efi_watchdog_register(void);
+efi_status_t efi_initrd_register(void);
 /* Called by bootefi to make SMBIOS tables available */
 /**
  * efi_acpi_register() - write out ACPI tables
diff --git 

Re: [PATCH 0/3] Remove CONFIG_MMC_BROKEN_CD

[Jaehoon Chung]

On 2/21/20 10:07 AM, Jaehoon Chung wrote:
> Hi Tom,
> 
> On 2/21/20 4:57 AM, Tom Rini wrote:
>> On Thu, Feb 20, 2020 at 01:45:31PM +0900, Jaehoon Chung wrote:
>>
>>> CONFIG_MMC_BROKEN_CD needs not to define to Kconfig.
>>> broken-cd is already provide to dt-property.
>>> If want to poll card-detect, set to broken-cd instead of enabling 
>>> CONFIG_MMC_BROKEN_CD.
>>>
>>> When checked the boards that is eabled CONFIG_MMC_BROKEN_CD,
>>> it also used the value of dt as broken-cd.
>>>
>>> Jaehoon Chung (3):
>>>   mmc: jz_mmc; add MMC_CAP_NEEDS_POLL by default
>>>   mmc: check the flags of host_caps about broken-cd
>>>   mmc: Kconfig: remove MMC_BROKEN_CD configuration
>>>
>>>  configs/brppt2_defconfig|  1 -
>>>  configs/ci20_mmc_defconfig  |  1 -
>>>  configs/meerkat96_defconfig |  1 -
>>>  drivers/mmc/Kconfig |  5 -
>>>  drivers/mmc/jz_mmc.c|  6 --
>>>  drivers/mmc/mmc.c   | 10 +-
>>>  6 files changed, 9 insertions(+), 15 deletions(-)
>>
>> Did you size-test this change?  ci20 is extremely tight on space.
> 
> I didn't check size-test about this. Is there any check-tool?
> If there is check-tool, let me know, plz. Then i will check it. (In future, I 
> will check before sending patch.)
> I just checked this patch with CI.

u-boot.img  : 327573 -> 327625
u-boot-spl.bin : 10336 -> 10464

What is ci20's limitation size?

Best Regards,
Jaehoon Chung

> 
> Best Regards,
> Jaehoon Chung
> 
>>
> 
> 
> 

Re: [PATCH v3] dm: uclass: don't assign aliased seq numbers

[Michal Simek]

On 20. 02. 20 21:16, Michael Walle wrote:
> 
> Hi Michal,
> 
> Am 2020-02-20 11:14, schrieb Michal Simek:
>> On 20. 02. 20 10:52, Michael Walle wrote:
>>> Hi Michal,
>>>
>>> Am 2020-02-20 09:30, schrieb Michal Simek:
 On 03. 02. 20 18:11, Michael Walle wrote:
> If there are aliases for an uclass, set the base for the "dynamically"
> allocated numbers next to the highest alias.
>
> Please note, that this might lead to holes in the sequences, depending
> on the device tree. For example if there is only an alias "ethernet1",
> the next device seq number would be 2.
>
> In particular this fixes a problem with boards which are using
> ethernet
> aliases but also might have network add-in cards like the E1000. If
> the
> board is started with the add-in card and depending on the order of
> the
> drivers, the E1000 might occupy the first ethernet device and mess up
> all the hardware addresses, because the devices are now shifted by
> one.
>
> Also adapt the test cases to the new handling and add test cases
> checking the holes in the seq numbers.
>
> Signed-off-by: Michael Walle 
> Reviewed-by: Alex Marginean 
> Tested-by: Alex Marginean 
> Acked-by: Vladimir Oltean 
> ---
>
> Please note that I've kept the R-b, T-b, and A-b tags although they
> were
> for an older version. They only affects the drivers/core/uclass.c not
> the
> test/dm/ part. OTOH none of the actual implementation has changed.
>
> I couldn't split the patch, otherwise the tests would fail.
>
> As a side effect, this should also make the following commits
> superfluous:
>  - 7f3289bf6d ("dm: device: Request next sequence number")
>  - 61607225d1 ("i2c: Fill req_seq in i2c_post_bind()")
>    Although I don't understand the root cause of the said problem.
>
> Thomas, Michal, could you please test this and then I'd add a second
> patch removing the old code.
>
> changes since v2:
>  - adapt/new test cases, thanks Simon
>
> changes since v1:
>  - move notice about superfluous commits from commit message to this
>    section.
>  - fix the comment style
>
>  arch/sandbox/dts/test.dts |  4 ++--
>  drivers/core/uclass.c | 21 +++--
>  include/configs/sandbox.h |  6 +++---
>  test/dm/eth.c | 14 +++---
>  test/dm/test-fdt.c    | 22 +-
>  5 files changed, 44 insertions(+), 23 deletions(-)
>
> diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
> index e529c54d8d..d448892a65 100644
> --- a/arch/sandbox/dts/test.dts
> +++ b/arch/sandbox/dts/test.dts
> @@ -19,8 +19,8 @@
>  pci0 = 
>  pci1 = 
>  pci2 = 
> -    remoteproc1 = _1;
> -    remoteproc2 = _2;
> +    remoteproc0 = _1;
> +    remoteproc1 = _2;
>  rtc0 = _0;
>  rtc1 = _1;
>  spi0 = "/spi@0";
> diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
> index c520ef113a..3c216221e0 100644
> --- a/drivers/core/uclass.c
> +++ b/drivers/core/uclass.c
> @@ -675,13 +675,14 @@ int uclass_unbind_device(struct udevice *dev)
>
>  int uclass_resolve_seq(struct udevice *dev)
>  {
> +    struct uclass *uc = dev->uclass;
> +    struct uclass_driver *uc_drv = uc->uc_drv;
>  struct udevice *dup;
> -    int seq;
> +    int seq = 0;
>  int ret;
>
>  assert(dev->seq == -1);
> -    ret = uclass_find_device_by_seq(dev->uclass->uc_drv->id,
> dev->req_seq,
> -    false, );
> +    ret = uclass_find_device_by_seq(uc_drv->id, dev->req_seq, false,
> );
>  if (!ret) {
>  dm_warn("Device '%s': seq %d is in use by '%s'\n",
>  dev->name, dev->req_seq, dup->name);
> @@ -693,9 +694,17 @@ int uclass_resolve_seq(struct udevice *dev)
>  return ret;
>  }
>
> -    for (seq = 0; seq < DM_MAX_SEQ; seq++) {
> -    ret = uclass_find_device_by_seq(dev->uclass->uc_drv->id, seq,
> -    false, );
> +    if (CONFIG_IS_ENABLED(DM_SEQ_ALIAS) &&
> +    (uc_drv->flags & DM_UC_FLAG_SEQ_ALIAS)) {
> +    /*
> + * dev_read_alias_highest_id() will return -1 if there no
> + * alias. Thus we can always add one.
> + */
> +    seq = dev_read_alias_highest_id(uc_drv->name) + 1;
> +    }
> +
> +    for (; seq < DM_MAX_SEQ; seq++) {
> +    ret = uclass_find_device_by_seq(uc_drv->id, seq, false,
> );
>  if (ret == -ENODEV)
>  break;
>  if (ret)
> diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
> index 1c13055cdc..b02c362fed 100644
> --- a/include/configs/sandbox.h
> 

Re: [PATCH v1 1/2] fu540: prci: add request and free clock handlers

[Sean Anderson]

On 2/18/20 11:13 AM, Sagar Shrikant Kadam wrote:
> +static int sifive_fu540_prci_clk_free(struct clk *clk)
> +{
> + debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
> +   clk->id);
> +
> + if (clk->id >= ARRAY_SIZE(__prci_init_clocks))
> + return -EINVAL;
> +
> + return 0;
> +}
> +

I don't think this function is necessary, since no struct clk should be
passed to clk_free except one which was previously successfully
requested.

>  static int sifive_fu540_prci_probe(struct udevice *dev)
>  {
>   int i, err;
> @@ -611,6 +633,8 @@ static int sifive_fu540_prci_probe(struct udevice *dev)
>  static struct clk_ops sifive_fu540_prci_ops = {
>   .set_rate = sifive_fu540_prci_set_rate,
>   .get_rate = sifive_fu540_prci_get_rate,
> + .request  = sifive_fu540_prci_clk_request,
> + .rfree= sifive_fu540_prci_clk_free,
>  };
>  
>  static const struct udevice_id sifive_fu540_prci_ids[] = {
>

--Sean

Re: [PATCH v1 2/2] cpu: clk: riscv: populate proper CPU core clk frequency

[Sean Anderson]

On 2/21/20 12:59 AM, Sagar Kadam wrote:
>> What you were trying to do in this patch, I believe the following 2
>> patches already did it.
>>
>> http://patchwork.ozlabs.org/patch/1236177/
>> http://patchwork.ozlabs.org/patch/1236180/
>>
> 
> Thanks for sharing the links. Unfortunately I didn’t come across it.
> I applied these two patches within my repo  (assuming there are not
> extra dependencies) and would like to share my observation:
> The implementation in the patch links shared here read's clock dt property
> in clk_get_by_index. If the cpu dt node doesn't contain clock property it 
> return's 
> negative value and so the clk_get_rate here won't be be executed.
> 
> + ret = clk_get_by_index(dev, 0, );
> + if (!ret) {
> + ret = clk_get_rate();

This is working as designed. The idea is to use the clocks property if
it exists and to fall back on clock-frequency otherwise.

> Thus when I tested this on hifive unleashed the "cpu detail" showed frequency 
> as 0 Hz.

This is because the cpu nodes in the hifive/fu540 device tree have
neither a clock-frequency property or a clocks property.

> Please correct me if I am wrong, but IMHO here we can check for negative 
> return 
> code [if (ret < 0)] instead of (!ret) and if "clocks" is missing in dt 
> property then get the clock 
> driver using uclass_get_device_by_driver->request the clock -> and get clock 
> rate, just like below
> 
> -   if (!ret) {
> +   if (ret < 0) {
> +   ret = uclass_get_device_by_driver(UCLASS_CLK,
> + 
> DM_GET_DRIVER(sifive_fu540_prci),
> + );

This is again adding board-specific code to a generic driver. Add a
UCLASS_CLOCK driver if you want to support clocks. That way there is no
need for code like this.

> +   clk.id = 0;
> +   ret = clk_request(dev, );
> +   if (ret < 0) {
> +   pr_err("%s: request to clock device failed...\n", 
> __func__);

I belive pr_err is supported for linux compatibility. New code should
use log_*. This is also probably debug-level and not err-level.

> +   return ret;
> +   }
> +
> 
> Also there is missing "include linux/err.h" which is needed by IS_ERR_VALUE

Yes, I noticed that when rebasing. It will be fixed in the next version
of the series.

> Please let me know if I can rebase and update my patches above the two 
> patch's you
> pointed to.
> 
>> Regards,
>> Bin

--Sean

[PATCH v7 6/7] test: add rsa_verify() unit test

[AKASHI Takahiro]

In this patch, a very simple test is added to verify that rsa_verify()
using rsa_verify_with_pkey() work correctly.

To keep the code simple, all the test data, either public key and
verified binary data, are embedded in the source.

Signed-off-by: AKASHI Takahiro 
---
 test/Kconfig  |  10 +++
 test/lib/Makefile |   1 +
 test/lib/rsa.c| 206 ++
 3 files changed, 217 insertions(+)
 create mode 100644 test/lib/rsa.c

diff --git a/test/Kconfig b/test/Kconfig
index cb51b4672102..0157e0b060ad 100644
--- a/test/Kconfig
+++ b/test/Kconfig
@@ -28,6 +28,16 @@ config UT_LIB_ASN1
  Enables a test which exercises asn1 compiler and decoder function
  via various parsers.
 
+config UT_LIB_RSA
+   bool "Unit test for rsa_verify() function"
+   depends on RSA
+   depends on RSA_VERIFY_WITH_PKEY
+   select IMAGE_SIGN_INFO
+   default y
+   help
+ Enables rsa_verify() test, currently rsa_verify_with_pkey only()
+ only, at the 'ut lib' command.
+
 endif
 
 config UT_TIME
diff --git a/test/lib/Makefile b/test/lib/Makefile
index 230068d5a001..ce9ae4a9bed9 100644
--- a/test/lib/Makefile
+++ b/test/lib/Makefile
@@ -8,4 +8,5 @@ obj-y += lmb.o
 obj-y += string.o
 obj-$(CONFIG_ERRNO_STR) += test_errno_str.o
 obj-$(CONFIG_UT_LIB_ASN1) += asn1.o
+obj-$(CONFIG_UT_LIB_RSA) += rsa.o
 obj-$(CONFIG_AES) += test_aes.o
diff --git a/test/lib/rsa.c b/test/lib/rsa.c
new file mode 100644
index ..44f8ade226f4
--- /dev/null
+++ b/test/lib/rsa.c
@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Linaro Limited
+ * Author: AKASHI Takahiro
+ *
+ * Unit test for rsa_verify() function
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifdef CONFIG_RSA_VERIFY_WITH_PKEY
+/*
+ * openssl genrsa 2048 -out private.pem
+ * openssl rsa -in private.pem -pubout -outform der -out public.der
+ * dd if=public.der of=public.raw bs=24 skip=1
+ */
+static unsigned char public_key[] = {
+   0x30, 0x82, 0x01, 0x0a, 0x02, 0x82, 0x01, 0x01, 0x00, 0xca, 0x25, 0x23,
+   0xe0, 0x0a, 0x4d, 0x8f, 0x56, 0xfc, 0xc9, 0x06, 0x4c, 0xcc, 0x94, 0x43,
+   0xe0, 0x56, 0x44, 0x6e, 0x37, 0x54, 0x87, 0x12, 0x84, 0xf9, 0x07, 0x4f,
+   0xe4, 0x23, 0x40, 0xc3, 0x43, 0x84, 0x37, 0x86, 0xd3, 0x9d, 0x95, 0x1c,
+   0xe4, 0x8a, 0x66, 0x02, 0x09, 0xe2, 0x3d, 0xce, 0x2c, 0xc6, 0x02, 0x6a,
+   0xd4, 0x65, 0x61, 0xff, 0x85, 0x6f, 0x88, 0x63, 0xba, 0x31, 0x62, 0x1e,
+   0xb7, 0x95, 0xe9, 0x08, 0x3c, 0xe9, 0x35, 0xde, 0xfd, 0x65, 0x92, 0xb8,
+   0x9e, 0x71, 0xa4, 0xcd, 0x47, 0xfd, 0x04, 0x26, 0xb9, 0x78, 0xbf, 0x05,
+   0x0d, 0xfc, 0x00, 0x84, 0x08, 0xfc, 0xc4, 0x4b, 0xea, 0xf5, 0x97, 0x68,
+   0x0d, 0x97, 0xd7, 0xff, 0x4f, 0x92, 0x82, 0xd7, 0xbb, 0xef, 0xb7, 0x67,
+   0x8e, 0x72, 0x54, 0xe8, 0xc5, 0x9e, 0xfd, 0xd8, 0x38, 0xe9, 0xbe, 0x19,
+   0x37, 0x5b, 0x36, 0x8b, 0xbf, 0x49, 0xa1, 0x59, 0x3a, 0x9d, 0xad, 0x92,
+   0x08, 0x0b, 0xe3, 0xa4, 0xa4, 0x7d, 0xd3, 0x70, 0xc0, 0xb8, 0xfb, 0xc7,
+   0xda, 0xd3, 0x19, 0x86, 0x37, 0x9a, 0xcd, 0xab, 0x30, 0x96, 0xab, 0xa4,
+   0xa2, 0x31, 0xa0, 0x38, 0xfb, 0xbf, 0x85, 0xd3, 0x24, 0x39, 0xed, 0xbf,
+   0xe1, 0x31, 0xed, 0x6c, 0x39, 0xc1, 0xe5, 0x05, 0x2e, 0x12, 0x30, 0x36,
+   0x73, 0x5d, 0x62, 0xf3, 0x82, 0xaf, 0x38, 0xc8, 0xca, 0xfa, 0xa1, 0x99,
+   0x57, 0x3c, 0xe1, 0xc1, 0x7b, 0x05, 0x0b, 0xcc, 0x2e, 0xa9, 0x10, 0xc8,
+   0x68, 0xbd, 0x27, 0xb6, 0x19, 0x9c, 0xd2, 0xad, 0xb3, 0x1f, 0xca, 0x35,
+   0x6e, 0x84, 0x23, 0xa1, 0xe9, 0xa4, 0x4c, 0xab, 0x19, 0x09, 0x79, 0x6e,
+   0x3c, 0x7b, 0x74, 0xfc, 0x33, 0x05, 0xcf, 0xa4, 0x2e, 0xeb, 0x55, 0x60,
+   0x05, 0xc7, 0xcf, 0x3f, 0x92, 0xac, 0x2d, 0x69, 0x0b, 0x19, 0x16, 0x79,
+   0x75, 0x02, 0x03, 0x01, 0x00, 0x01
+};
+
+static unsigned int public_key_len = 270;
+
+/*
+ * dd if=/dev/urandom of=data.raw bs=512 count=1
+ */
+static unsigned char data_raw[] = {
+   0x3e, 0x48, 0x6e, 0xef, 0x83, 0xd1, 0x4c, 0xfd, 0x92, 0x47, 0x92, 0xd7,
+   0xf6, 0x16, 0x25, 0x0a, 0xdf, 0xe2, 0xb6, 0x6c, 0xe7, 0xe0, 0x55, 0xb2,
+   0x70, 0x66, 0xf0, 0xe5, 0xdc, 0xaf, 0xd3, 0x2e, 0xc1, 0x3e, 0x5c, 0x4b,
+   0xb5, 0xa7, 0x23, 0x1f, 0x2c, 0xce, 0xf8, 0x83, 0x00, 0x6d, 0xeb, 0xdd,
+   0x19, 0x71, 0x13, 0xb4, 0xae, 0x5c, 0xa8, 0xae, 0x52, 0xc8, 0xe1, 0x77,
+   0x9e, 0x98, 0x75, 0xbc, 0xef, 0x36, 0x9f, 0x0c, 0x14, 0xed, 0x1a, 0x0a,
+   0x4f, 0x6c, 0xa4, 0xb1, 0xbb, 0x0e, 0x43, 0x93, 0x12, 0xfc, 0x2e, 0x82,
+   0x93, 0x4e, 0xcb, 0xa2, 0xcd, 0x59, 0x3f, 0xc5, 0x11, 0x38, 0x3a, 0x88,
+   0xc3, 0xcf, 0xf9, 0x61, 0xa8, 0x9e, 0x96, 0xb6, 0xbf, 0xa6, 0x5b, 0x0d,
+   0xd9, 0xbd, 0x05, 0x4c, 0xbe, 0xed, 0x86, 0xca, 0x10, 0x63, 0x72, 0x75,
+   0x4b, 0xbd, 0x86, 0x42, 0x30, 0x9d, 0x54, 0x4e, 0x12, 0xda, 0xf4, 0xb4,
+   0xfd, 0xd9, 0x54, 0x95, 0x8f, 0x83, 0xc2, 0x63, 0x44, 0xdd, 0x96, 0x1a,
+   0xd0, 0x7c, 0xcf, 0xcb, 0x16, 0xd6, 

[PATCH v7 4/7] lib: rsa: generate additional parameters for public key

[AKASHI Takahiro]

In the current implementation of FIT_SIGNATURE, five parameters for
a RSA public key are required while only two of them are essential.
(See rsa-mod-exp.h and uImage.FIT/signature.txt)
This is a result of considering relatively limited computer power
and resources on embedded systems, while such a assumption may not
be quite practical for other use cases.

In this patch, added is a function, rsa_gen_key_prop(), which will
generate additional parameters for other uses, in particular
UEFI secure boot, on the fly.

Note: the current code uses some "big number" routines from BearSSL
for the calculation.

Signed-off-by: AKASHI Takahiro 
---
 include/u-boot/rsa-mod-exp.h |  23 ++
 lib/rsa/Kconfig  |   3 +
 lib/rsa/Makefile |   1 +
 lib/rsa/rsa-keyprop.c| 725 +++
 4 files changed, 752 insertions(+)
 create mode 100644 lib/rsa/rsa-keyprop.c

diff --git a/include/u-boot/rsa-mod-exp.h b/include/u-boot/rsa-mod-exp.h
index 8a428c4b6a1a..1da8af1bb83d 100644
--- a/include/u-boot/rsa-mod-exp.h
+++ b/include/u-boot/rsa-mod-exp.h
@@ -26,6 +26,29 @@ struct key_prop {
uint32_t exp_len;   /* Exponent length in number of uint8_t */
 };
 
+/**
+ * rsa_gen_key_prop() - Generate key properties of RSA public key
+ * @key:   Specifies key data in DER format
+ * @keylen:Length of @key
+ * @prop:  Generated key property
+ *
+ * This function takes a blob of encoded RSA public key data in DER
+ * format, parse it and generate all the relevant properties
+ * in key_prop structure.
+ * Return a pointer to struct key_prop in @prop on success.
+ *
+ * Return: 0 on success, negative on error
+ */
+int rsa_gen_key_prop(const void *key, uint32_t keylen, struct key_prop **proc);
+
+/**
+ * rsa_free_key_prop() - Free key properties
+ * @prop:  Pointer to struct key_prop
+ *
+ * This function frees all the memories allocated by rsa_gen_key_prop().
+ */
+void rsa_free_key_prop(struct key_prop *prop);
+
 /**
  * rsa_mod_exp_sw() - Perform RSA Modular Exponentiation in sw
  *
diff --git a/lib/rsa/Kconfig b/lib/rsa/Kconfig
index 89697219db2d..a90d67e5a87b 100644
--- a/lib/rsa/Kconfig
+++ b/lib/rsa/Kconfig
@@ -31,6 +31,9 @@ config RSA_VERIFY
 config RSA_VERIFY_WITH_PKEY
bool "Execute RSA verification without key parameters from FDT"
select RSA_VERIFY
+   select ASYMMETRIC_KEY_TYPE
+   select ASYMMETRIC_PUBLIC_KEY_SUBTYPE
+   select RSA_PUBLIC_KEY_PARSER
help
  The standard RSA-signature verification code (FIT_SIGNATURE) uses
  pre-calculated key properties, that are stored in fdt blob, in
diff --git a/lib/rsa/Makefile b/lib/rsa/Makefile
index c07305188e0c..14ed3cb4012b 100644
--- a/lib/rsa/Makefile
+++ b/lib/rsa/Makefile
@@ -6,4 +6,5 @@
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 
 obj-$(CONFIG_$(SPL_)RSA_VERIFY) += rsa-verify.o rsa-checksum.o
+obj-$(CONFIG_RSA_VERIFY_WITH_PKEY) += rsa-keyprop.o
 obj-$(CONFIG_RSA_SOFTWARE_EXP) += rsa-mod-exp.o
diff --git a/lib/rsa/rsa-keyprop.c b/lib/rsa/rsa-keyprop.c
new file mode 100644
index ..9464df009343
--- /dev/null
+++ b/lib/rsa/rsa-keyprop.c
@@ -0,0 +1,725 @@
+// SPDX-License-Identifier: GPL-2.0+ and MIT
+/*
+ * RSA library - generate parameters for a public key
+ *
+ * Copyright (c) 2019 Linaro Limited
+ * Author: AKASHI Takahiro
+ *
+ * Big number routines in this file come from BearSSL:
+ * Copyright (c) 2016 Thomas Pornin 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * br_dec16be() - Convert 16-bit big-endian integer to native
+ * @src:   Pointer to data
+ * Return: Native-endian integer
+ */
+static unsigned br_dec16be(const void *src)
+{
+   return be16_to_cpup(src);
+}
+
+/**
+ * br_dec32be() - Convert 32-bit big-endian integer to native
+ * @src:   Pointer to data
+ * Return: Native-endian integer
+ */
+static uint32_t br_dec32be(const void *src)
+{
+   return be32_to_cpup(src);
+}
+
+/**
+ * br_enc32be() - Convert native 32-bit integer to big-endian
+ * @dst:   Pointer to buffer to store big-endian integer in
+ * @x: Native 32-bit integer
+ */
+static void br_enc32be(void *dst, uint32_t x)
+{
+   __be32 tmp;
+
+   tmp = cpu_to_be32(x);
+   memcpy(dst, , sizeof(tmp));
+}
+
+/* from BearSSL's src/inner.h */
+
+/*
+ * Negate a boolean.
+ */
+static uint32_t NOT(uint32_t ctl)
+{
+   return ctl ^ 1;
+}
+
+/*
+ * Multiplexer: returns x if ctl == 1, y if ctl == 0.
+ */
+static uint32_t MUX(uint32_t ctl, uint32_t x, uint32_t y)
+{
+   return y ^ (-ctl & (x ^ y));
+}
+
+/*
+ * Equality check: returns 1 if x == y, 0 otherwise.
+ */
+static uint32_t EQ(uint32_t x, uint32_t y)
+{
+   uint32_t q;
+
+   q = x ^ y;
+   return NOT((q | -q) >> 31);
+}
+
+/*
+ * Inequality check: returns 1 if x != y, 0 otherwise.
+ */
+static uint32_t NEQ(uint32_t x, uint32_t y)
+{
+   uint32_t q;
+
+   q = x ^ y;
+   return (q | -q) >> 31;
+}

[PATCH v7 3/7] include: image.h: add key info to image_sign_info

[AKASHI Takahiro]

For FIT verification, all the properties of a public key come from
"control fdt" pointed to by fdt_blob. In UEFI secure boot, on the other
hand, a public key is located and retrieved from dedicated signature
database stored as UEFI variables.

Added two fields may hold values of a public key if fdt_blob is NULL, and
will be used in rsa_verify_with_pkey() to verify a signature in UEFI
sub-system.

Signed-off-by: AKASHI Takahiro 
Reviewed-by: Simon Glass 
---
 include/image.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/include/image.h b/include/image.h
index eb7aa5622aa3..ceede0d4385e 100644
--- a/include/image.h
+++ b/include/image.h
@@ -1170,6 +1170,13 @@ struct image_sign_info {
int required_keynode;   /* Node offset of key to use: -1=any */
const char *require_keys;   /* Value for 'required' property */
const char *engine_id;  /* Engine to use for signing */
+   /*
+* Note: the following two fields are always valid even w/o
+* RSA_VERIFY_WITH_PKEY in order to make sure this structure is
+* the same on target and host. Otherwise, vboot test may fail.
+*/
+   const void *key;/* Pointer to public key in DER */
+   int keylen; /* Length of public key */
 };
 
 /* A part of an image, used for hashing */
-- 
2.24.0

[PATCH v7 5/7] lib: rsa: add rsa_verify_with_pkey()

[AKASHI Takahiro]

This function, and hence rsa_verify(), will perform RSA verification
with two essential parameters for a RSA public key in contract of
rsa_verify_with_keynode(), which requires additional three parameters
stored in FIT image.

It will be used in implementing UEFI secure boot, i.e. image authentication
and variable authentication.

Signed-off-by: AKASHI Takahiro 
Reviewed-by: Simon Glass 
---
 lib/rsa/rsa-verify.c | 65 +++-
 1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c
index 3dd30c8b8bc7..80e817314b58 100644
--- a/lib/rsa/rsa-verify.c
+++ b/lib/rsa/rsa-verify.c
@@ -18,9 +18,22 @@
 #include "mkimage.h"
 #include 
 #endif
+#include 
 #include 
 #include 
 
+#ifndef __UBOOT__
+/*
+ * NOTE:
+ * Since host tools, like mkimage, make use of openssl library for
+ * RSA encryption, rsa_verify_with_pkey()/rsa_gen_key_prop() are
+ * of no use and should not be compiled in.
+ * So just turn off CONFIG_RSA_VERIFY_WITH_PKEY.
+ */
+
+#undef CONFIG_RSA_VERIFY_WITH_PKEY
+#endif
+
 /* Default public exponent for backward compatibility */
 #define RSA_DEFAULT_PUBEXP 65537
 
@@ -271,7 +284,7 @@ out:
 }
 #endif
 
-#if CONFIG_IS_ENABLED(FIT_SIGNATURE)
+#if CONFIG_IS_ENABLED(FIT_SIGNATURE) || IS_ENABLED(CONFIG_RSA_VERIFY_WITH_PKEY)
 /**
  * rsa_verify_key() - Verify a signature against some data using RSA Key
  *
@@ -345,6 +358,49 @@ static int rsa_verify_key(struct image_sign_info *info,
 }
 #endif
 
+#ifdef CONFIG_RSA_VERIFY_WITH_PKEY
+/**
+ * rsa_verify_with_pkey() - Verify a signature against some data using
+ * only modulus and exponent as RSA key properties.
+ * @info:  Specifies key information
+ * @hash:  Pointer to the expected hash
+ * @sig:   Signature
+ * @sig_len:   Number of bytes in signature
+ *
+ * Parse a RSA public key blob in DER format pointed to in @info and fill
+ * a key_prop structure with properties of the key. Then verify a RSA PKCS1.5
+ * signature against an expected hash using the calculated properties.
+ *
+ * Return  0 if verified, -ve on error
+ */
+static int rsa_verify_with_pkey(struct image_sign_info *info,
+   const void *hash, uint8_t *sig, uint sig_len)
+{
+   struct key_prop *prop;
+   int ret;
+
+   /* Public key is self-described to fill key_prop */
+   ret = rsa_gen_key_prop(info->key, info->keylen, );
+   if (ret) {
+   debug("Generating necessary parameter for decoding failed\n");
+   return ret;
+   }
+
+   ret = rsa_verify_key(info, prop, sig, sig_len, hash,
+info->crypto->key_len);
+
+   rsa_free_key_prop(prop);
+
+   return ret;
+}
+#else
+static int rsa_verify_with_pkey(struct image_sign_info *info,
+   const void *hash, uint8_t *sig, uint sig_len)
+{
+   return -EACCES;
+}
+#endif
+
 #if CONFIG_IS_ENABLED(FIT_SIGNATURE)
 /**
  * rsa_verify_with_keynode() - Verify a signature against some data using
@@ -435,6 +491,13 @@ int rsa_verify(struct image_sign_info *info,
return -EINVAL;
}
 
+   if (IS_ENABLED(CONFIG_RSA_VERIFY_WITH_PKEY) && !info->fdt_blob) {
+   /* don't rely on fdt properties */
+   ret = rsa_verify_with_pkey(info, hash, sig, sig_len);
+
+   return ret;
+   }
+
if (CONFIG_IS_ENABLED(FIT_SIGNATURE)) {
const void *blob = info->fdt_blob;
int ndepth, noffset;
-- 
2.24.0

[PATCH v7 7/7] test: enable RSA library test on sandbox

[AKASHI Takahiro]

We want to always run RSA library test on sandbox build in Travis CI.
Just adding CONFIG_RSA_VERIFY_WITH_PKEY would be good enough for this
purpose.

Signed-off-by: AKASHI Takahiro 
---
 configs/sandbox64_defconfig| 1 +
 configs/sandbox_defconfig  | 1 +
 configs/sandbox_flattree_defconfig | 1 +
 configs/sandbox_spl_defconfig  | 1 +
 4 files changed, 4 insertions(+)

diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 941b1fd2c745..e96982402ba6 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -200,6 +200,7 @@ CONFIG_WDT_SANDBOX=y
 CONFIG_FS_CBFS=y
 CONFIG_FS_CRAMFS=y
 CONFIG_CMD_DHRYSTONE=y
+CONFIG_RSA_VERIFY_WITH_PKEY=y
 CONFIG_TPM=y
 CONFIG_LZ4=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 7b02b8de7cce..4e001fc650dc 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -226,6 +226,7 @@ CONFIG_WDT_SANDBOX=y
 CONFIG_FS_CBFS=y
 CONFIG_FS_CRAMFS=y
 CONFIG_CMD_DHRYSTONE=y
+CONFIG_RSA_VERIFY_WITH_PKEY=y
 CONFIG_TPM=y
 CONFIG_LZ4=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/sandbox_flattree_defconfig 
b/configs/sandbox_flattree_defconfig
index 0049da3d4831..aaa916e077d4 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -175,6 +175,7 @@ CONFIG_VIDEO_SANDBOX_SDL=y
 CONFIG_OSD=y
 CONFIG_SANDBOX_OSD=y
 CONFIG_CMD_DHRYSTONE=y
+CONFIG_RSA_VERIFY_WITH_PKEY=y
 CONFIG_TPM=y
 CONFIG_LZ4=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index f55692c2b552..4d6ccd88bf12 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -198,6 +198,7 @@ CONFIG_FS_CBFS=y
 CONFIG_FS_CRAMFS=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 CONFIG_CMD_DHRYSTONE=y
+CONFIG_RSA_VERIFY_WITH_PKEY=y
 CONFIG_TPM=y
 CONFIG_LZ4=y
 CONFIG_ERRNO_STR=y
-- 
2.24.0

[PATCH v7 0/7] rsa: extend rsa_verify() for UEFI secure boot

[AKASHI Takahiro]

# This patch set is a prerequisite for UEFI secure boot.

The current rsa_verify() requires five parameters for a RSA public key
for efficiency while RSA, in theory, requires only two. In addition,
those parameters are expected to come from FIT image.

So this function won't fit very well when we want to use it for the purpose
of implementing UEFI secure boot, in particular, image authentication
as well as variable authentication, where the essential two parameters
are set to be retrieved from one of X509 certificates in signature
database.

So, in this patch, additional three parameters will be calculated
on the fly when rsa_verify() is called without fdt which should contain
parameters above.

This calculation heavily relies on "big-number (or multi-precision)
library." Therefore some routines from BearSSL[1] under MIT license are
imported in this implementation. See Patch#4.
# Please let me know if this is not appropriate.

Prerequisite:
* public key parser in my "import x509/pkcs7 parser" patch[2]

# Checkpatch will complain with lots of warnings/errors, but
# I intentionally don't fix them for maximum maintainability.

  [1] https://bearssl.org/
  [2] https://lists.denx.de/pipermail/u-boot/2019-November/390127.html

Changes in v7 (Feb 21, 2020)
* rebased to v2020.04-rc2
* no functional change

Changes in v6 (Jan 27, 2020)
* rebased to v2020.01
* change CONFIG_UT_LIB_RSA dependencies after Tom's suggestion (patch#6)
* add patch#7 to enable RSA library test on sandbox

Changes in v5 (Dec 17, 2019)
* modify RSA_VERIFY-related configuration to fix size growth problem
  on some platforms (T1042RDB_PI_NAND_SECURE_BOOT and else), adding
  IMAGE_SIGN_INFO config (patch #1, #2, #6)
* simplify kconfig dependencies;
  - RSA_VERIFY_WITH_PKEY *selects* RSA_VERIFY instead of "depends on"
(patch#2)
  - remove some implicit dependencies (patch#6)

Changes in v4 (Nov 21, 2019)
* rebased to v2020.01-rc3
* change a function prototype of rsa_gen_key_prop() to return an error
  code (patch#4,#5)
* re-order include files in alphabetical order (patch#6)
* add some comments per Simon's review comments

Changes in v3 (Nov 13, 2019)
* remove RSA_VERIFY_WITH_PKEY, which is to be added in patch#2 (patch#1)
* modify unit test Kconfg due to removal of test/lib/Kconfig (patch#6)

Changes in v2 (Oct 29, 2019)
* fix build errors at Travis CI
* not include linux/kconfig.h (patch#1)
* add a separate patch for adding CONFIG_RSA_VERIFY_WITH_PKEY (patch#2)
* take a prerequisite patch from my "secure boot patch" (patch#3)
* add a dependency on RSA_PUBLIC_KEY_PARSER (patch#4)
* remove "inline" directives (patch#4)
* add function descriptions, which mostly come from BearSSL's src/inner.h
  (patch#4)
* improve Kconfig help text after Simon's comment (patch#5)
* add function description of rsa_verify_with_pkey() (patch#5)
* modify rsa_verify() to use "if (CONFIG_IS_ENABLED(...) " style
  rather than "#ifdef CONFIG_..." (patch#5)
* add function tests (patch#6)

Changes in v1 (Oct 9, 2019)
* fix a build error on pine64-lts_defconfig (reported by Heinrich)
  by defining FIT_IMAGE_ENABLE_VERIFY flag and adding
  SPL_RSA_VERIFY config (patch#1)
* remove FIT-specific code from image-sig.c and put them to new
  image-fit-sig.c to allow us to disable CONFIG_FIT_SIGNATURE (patch#1)
* compile rsa-keyprop.c only if necessary (i.e. if
  CONFIG_RSA_VERIFY_WITH_PKEY) (patch#2)
* add SPDX license identifier in rsa-keyprop.c (patch#2)
* include  instead of  (patch#2)
* use U-Boot's byteorder helper functions instead of BearSSL's (patch#2)

AKASHI Takahiro (7):
  lib: rsa: decouple rsa from FIT image verification
  rsa: add CONFIG_RSA_VERIFY_WITH_PKEY config
  include: image.h: add key info to image_sign_info
  lib: rsa: generate additional parameters for public key
  lib: rsa: add rsa_verify_with_pkey()
  test: add rsa_verify() unit test
  test: enable RSA library test on sandbox

 Kconfig|   4 +
 common/Kconfig |   7 +
 common/Makefile|   3 +-
 common/image-fit-sig.c | 417 +
 common/image-fit.c |   6 +-
 common/image-sig.c | 396 
 configs/sandbox64_defconfig|   1 +
 configs/sandbox_defconfig  |   1 +
 configs/sandbox_flattree_defconfig |   1 +
 configs/sandbox_spl_defconfig  |   1 +
 include/image.h|  21 +-
 include/u-boot/rsa-mod-exp.h   |  23 +
 lib/rsa/Kconfig|  27 ++
 lib/rsa/Makefile   |   3 +-
 lib/rsa/rsa-keyprop.c  | 725 +
 lib/rsa/rsa-verify.c   | 137 --
 test/Kconfig   |  10 +
 test/lib/Makefile  |   1 +
 test/lib/rsa.c | 206 
 tools/Makefile |   2 +-
 20 files changed, 1556 insertions(+), 436 deletions(-)
 create mode 100644 common/image-fit-sig.c
 create mode 100644 

[PATCH v7 2/7] rsa: add CONFIG_RSA_VERIFY_WITH_PKEY config

[AKASHI Takahiro]

In the next couple of commits, under new CONFIG_RSA_VERIFY_WITH_PKEY,
rsa_verify() will be extended to be able to perform RSA decryption without
additional RSA key properties from FIT image, i.e. rr and n0inv.

Signed-off-by: AKASHI Takahiro 
Reviewed-by: Simon Glass 
---
 lib/rsa/Kconfig | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/lib/rsa/Kconfig b/lib/rsa/Kconfig
index 18a075c17478..89697219db2d 100644
--- a/lib/rsa/Kconfig
+++ b/lib/rsa/Kconfig
@@ -28,6 +28,20 @@ config RSA_VERIFY
help
  Add RSA signature verification support.
 
+config RSA_VERIFY_WITH_PKEY
+   bool "Execute RSA verification without key parameters from FDT"
+   select RSA_VERIFY
+   help
+ The standard RSA-signature verification code (FIT_SIGNATURE) uses
+ pre-calculated key properties, that are stored in fdt blob, in
+ decrypting a signature.
+ This does not suit the use case where there is no way defined to
+ provide such additional key properties in standardized form,
+ particularly UEFI secure boot.
+ This options enables RSA signature verification with a public key
+ directly specified in image_sign_info, where all the necessary
+ key properties will be calculated on the fly in verification code.
+
 config RSA_SOFTWARE_EXP
bool "Enable driver for RSA Modular Exponentiation in software"
depends on DM
-- 
2.24.0

[PATCH v7 1/7] lib: rsa: decouple rsa from FIT image verification

[AKASHI Takahiro]

Introduce new configuration, CONFIG_RSA_VERIFY which will decouple building
RSA functions from FIT verification and allow for adding a RSA-based
signature verification for other file formats, in particular PE file
for UEFI secure boot.

Signed-off-by: AKASHI Takahiro 
Reviewed-by: Simon Glass 
---
 Kconfig|   4 +
 common/Kconfig |   7 +
 common/Makefile|   3 +-
 common/image-fit-sig.c | 417 +
 common/image-fit.c |   6 +-
 common/image-sig.c | 396 --
 include/image.h|  14 +-
 lib/rsa/Kconfig|  10 +
 lib/rsa/Makefile   |   2 +-
 lib/rsa/rsa-verify.c   |  78 +---
 tools/Makefile |   2 +-
 11 files changed, 501 insertions(+), 438 deletions(-)
 create mode 100644 common/image-fit-sig.c

diff --git a/Kconfig b/Kconfig
index 66148ce47790..e2387b2ff8e7 100644
--- a/Kconfig
+++ b/Kconfig
@@ -354,6 +354,8 @@ config FIT_SIGNATURE
depends on DM
select HASH
select RSA
+   select RSA_VERIFY
+   select IMAGE_SIGN_INFO
help
  This option enables signature verification of FIT uImages,
  using a hash signed and verified using RSA. If
@@ -442,6 +444,8 @@ config SPL_FIT_SIGNATURE
depends on SPL_DM
select SPL_FIT
select SPL_RSA
+   select SPL_RSA_VERIFY
+   select IMAGE_SIGN_INFO
 
 config SPL_LOAD_FIT
bool "Enable SPL loading U-Boot as a FIT (basic fitImage features)"
diff --git a/common/Kconfig b/common/Kconfig
index 4bc3df4e1bb2..77746f747d49 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -1044,3 +1044,10 @@ config BLOBLIST_ADDR
 endmenu
 
 source "common/spl/Kconfig"
+
+config IMAGE_SIGN_INFO
+   bool
+   select SHA1
+   select SHA256
+   help
+ Enable image_sign_info helper functions.
diff --git a/common/Makefile b/common/Makefile
index 896e4af91d4c..702f2396cf46 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -112,7 +112,8 @@ obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o 
image-android-dt.o
 obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += image-fdt.o
 obj-$(CONFIG_$(SPL_TPL_)FIT) += image-fit.o
 obj-$(CONFIG_$(SPL_)MULTI_DTB_FIT) += boot_fit.o common_fit.o
-obj-$(CONFIG_$(SPL_TPL_)FIT_SIGNATURE) += image-sig.o
+obj-$(CONFIG_IMAGE_SIGN_INFO) += image-sig.o
+obj-$(CONFIG_$(SPL_TPL_)FIT_SIGNATURE) += image-fit-sig.o
 obj-$(CONFIG_$(SPL_TPL_)FIT_CIPHER) += image-cipher.o
 obj-$(CONFIG_IO_TRACE) += iotrace.o
 obj-y += memsize.o
diff --git a/common/image-fit-sig.c b/common/image-fit-sig.c
new file mode 100644
index ..f6caeb0c5901
--- /dev/null
+++ b/common/image-fit-sig.c
@@ -0,0 +1,417 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013, Google Inc.
+ */
+
+#ifdef USE_HOSTCC
+#include "mkimage.h"
+#include 
+#else
+#include 
+#include 
+DECLARE_GLOBAL_DATA_PTR;
+#endif /* !USE_HOSTCC*/
+#include 
+#include 
+#include 
+
+#define IMAGE_MAX_HASHED_NODES 100
+
+#ifdef USE_HOSTCC
+void *host_blob;
+
+void image_set_host_blob(void *blob)
+{
+   host_blob = blob;
+}
+
+void *image_get_host_blob(void)
+{
+   return host_blob;
+}
+#endif
+
+/**
+ * fit_region_make_list() - Make a list of image regions
+ *
+ * Given a list of fdt_regions, create a list of image_regions. This is a
+ * simple conversion routine since the FDT and image code use different
+ * structures.
+ *
+ * @fit: FIT image
+ * @fdt_regions: Pointer to FDT regions
+ * @count: Number of FDT regions
+ * @region: Pointer to image regions, which must hold @count records. If
+ * region is NULL, then (except for an SPL build) the array will be
+ * allocated.
+ * @return: Pointer to image regions
+ */
+struct image_region *fit_region_make_list(const void *fit,
+ struct fdt_region *fdt_regions,
+ int count,
+ struct image_region *region)
+{
+   int i;
+
+   debug("Hash regions:\n");
+   debug("%10s %10s\n", "Offset", "Size");
+
+   /*
+* Use malloc() except in SPL (to save code size). In SPL the caller
+* must allocate the array.
+*/
+#ifndef CONFIG_SPL_BUILD
+   if (!region)
+   region = calloc(sizeof(*region), count);
+#endif
+   if (!region)
+   return NULL;
+   for (i = 0; i < count; i++) {
+   debug("%10x %10x\n", fdt_regions[i].offset,
+ fdt_regions[i].size);
+   region[i].data = fit + fdt_regions[i].offset;
+   region[i].size = fdt_regions[i].size;
+   }
+
+   return region;
+}
+
+static int fit_image_setup_verify(struct image_sign_info *info,
+ const void *fit, int noffset,
+ int required_keynode, char **err_msgp)
+{
+   char *algo_name;
+   const char *padding_name;
+
+   if (fdt_totalsize(fit) > 

RE: [PATCH v1 2/2] cpu: clk: riscv: populate proper CPU core clk frequency

[Sagar Kadam]

Hello Bin,

> -Original Message-
> From: Bin Meng 
> Sent: Wednesday, February 19, 2020 9:40 PM
> To: Sagar Kadam ; Sean Anderson
> 
> Cc: U-Boot Mailing List ; Lukasz Majewski
> ; Anup Patel ; Paul Walmsley (
> Sifive) ; Vincent Chen
> 
> Subject: Re: [PATCH v1 2/2] cpu: clk: riscv: populate proper CPU core clk
> frequency
> 
> +Sean Anderson
> 
> Hi Sagar,
> 
> On Wed, Feb 19, 2020 at 12:13 AM Sagar Shrikant Kadam
>  wrote:
> >
> > Fetch core clock frequency from prci if clock-frequency for CPU nodes
> > is missing in device tree, so that the cmd "#cpu detail" will show the
> > correct CPU frequency.
> >
> > U-Boot command "#cpu detail" is showing wrong frequency values.
> > This patch fixes this issue by getting the core clock set in prci driver
> > if clock-frequency is not added to CPU nodes in device tree.
> > It is tested on HiFive Unleashed A00 board.
> >
> > Signed-off-by: Sagar Shrikant Kadam 
> > Tested-by: Vincent Chen 
> > ---
> >  drivers/cpu/riscv_cpu.c | 39
> ++-
> >  1 file changed, 38 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
> > index 28ad0aa..eb5491f 100644
> > --- a/drivers/cpu/riscv_cpu.c
> > +++ b/drivers/cpu/riscv_cpu.c
> > @@ -9,6 +9,8 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> > +#include 
> 
> It's wrong to include a SoC specific header file in a generic driver.
>
Thanks for review.
Ok. I will remove this.
> 
> >
> >  DECLARE_GLOBAL_DATA_PTR;
> >
> > @@ -25,11 +27,46 @@ static int riscv_cpu_get_desc(struct udevice *dev,
> char *buf, int size)
> > return 0;
> >  }
> >
> > +static ulong riscv_get_clkrate(int clk_index)
> > +{
> > +   int ret;
> > +   struct udevice *dev;
> > +   struct clk clk;
> > +   ulong rate;
> > +
> > +   ret = uclass_get_device_by_driver(UCLASS_CLK,
> > + DM_GET_DRIVER(sifive_fu540_prci),
> > + );
> > +   if (ret < 0) {
> > +   pr_err("%s: Could not get device driver\n", __func__);
> > +   return ret;
> > +   }
> > +
> > +   clk.id = clk_index;
> > +   ret = clk_request(dev, );
> > +   if (ret < 0) {
> > +   pr_err("%s: request to clock device failed...\n", __func__);
> > +   return ret;
> > +   }
> > +
> > +   rate = clk_get_rate();
> > +
> > +   clk_free();
> > +
> > +   return rate;
> > +}
> > +
> >  static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info)
> >  {
> > const char *mmu;
> > +   int ret;
> >
> > -   dev_read_u32(dev, "clock-frequency", (u32 *)>cpu_freq);
> > +   ret = dev_read_u32(dev, "clock-frequency", (u32 *)>cpu_freq);
> > +   if (ret) {
> > +   /* if clock-frequency is missing in DT, read it from prci */
> > +   debug("Fetch core clk configured by prci\n");
> > +   info->cpu_freq = riscv_get_clkrate(PRCI_CLK_COREPLL);
> > +   }
> >
> > mmu = dev_read_string(dev, "mmu-type");
> > if (!mmu)
> > --
> 
> What you were trying to do in this patch, I believe the following 2
> patches already did it.
> 
> http://patchwork.ozlabs.org/patch/1236177/
> http://patchwork.ozlabs.org/patch/1236180/
> 

Thanks for sharing the links. Unfortunately I didn’t come across it.
I applied these two patches within my repo  (assuming there are not
extra dependencies) and would like to share my observation:
The implementation in the patch links shared here read's clock dt property
in clk_get_by_index. If the cpu dt node doesn't contain clock property it 
return's 
negative value and so the clk_get_rate here won't be be executed.

+   ret = clk_get_by_index(dev, 0, );
+   if (!ret) {
+   ret = clk_get_rate();

Thus when I tested this on hifive unleashed the "cpu detail" showed frequency 
as 0 Hz.

Please correct me if I am wrong, but IMHO here we can check for negative return 
code [if (ret < 0)] instead of (!ret) and if "clocks" is missing in dt property 
then get the clock 
driver using uclass_get_device_by_driver->request the clock -> and get clock 
rate, just like below

-   if (!ret) {
+   if (ret < 0) {
+   ret = uclass_get_device_by_driver(UCLASS_CLK,
+ 
DM_GET_DRIVER(sifive_fu540_prci),
+ );
+   clk.id = 0;
+   ret = clk_request(dev, );
+   if (ret < 0) {
+   pr_err("%s: request to clock device failed...\n", 
__func__);
+   return ret;
+   }
+

Also there is missing "include linux/err.h" which is needed by IS_ERR_VALUE
Please let me know if I can rebase and update my patches above the two patch's 
you
pointed to.

> Regards,
> Bin

Re: [PATCH v2 2/3] mmc: sdhci: not return error when SDMA is not supported

[Minkyu Kang]

On 18/02/2020 10:25, Jaehoon Chung wrote:
> If Host controller doesn't support SDMA, it doesn't need to return
> error. Because it can be worked with PIO mode.
> 
> Signed-off-by: Jaehoon Chung 
> Reviewed-by: Peng Fan 
> ---
> Changelog on V2
> - Keep printf message instead of debug
> 
>  drivers/mmc/sdhci.c | 7 +++
>  1 file changed, 3 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
> index 93c9049c5d..40bf2a5b2c 100644
> --- a/drivers/mmc/sdhci.c
> +++ b/drivers/mmc/sdhci.c
> @@ -729,13 +729,12 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct 
> sdhci_host *host,
>   debug("%s, caps: 0x%x\n", __func__, caps);
>  
>  #ifdef CONFIG_MMC_SDHCI_SDMA
> - if (!(caps & SDHCI_CAN_DO_SDMA)) {
> + if ((caps & SDHCI_CAN_DO_SDMA)) {

seems to redundant braces

> + host->flags |= USE_SDMA;
> + } else {
>   printf("%s: Your controller doesn't support SDMA!!\n",
>  __func__);
> - return -EINVAL;
>   }
> -
> - host->flags |= USE_SDMA;
>  #endif
>  #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
>   if (!(caps & SDHCI_CAN_DO_ADMA2)) {
> 

Reviewed-by: Minkyu Kang 

Thanks,
Minkyu Kang.

Re: [PATCH v2 3/3] configs: rpi_4_32b_defconfig: enable SDHCI_SDMA config

[Minkyu Kang]

On 18/02/2020 10:25, Jaehoon Chung wrote:
> Enable SDHCI_SDMA configuration.
> 
> Signed-off-by: Jaehoon Chung 
> Reviewed-by: Peng Fan 
> ---
> Changelog on V2
> - None
> 
>  configs/rpi_4_32b_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
> index 72cda5d949..7189914606 100644
> --- a/configs/rpi_4_32b_defconfig
> +++ b/configs/rpi_4_32b_defconfig
> @@ -25,6 +25,7 @@ CONFIG_DFU_MMC=y
>  CONFIG_DM_KEYBOARD=y
>  CONFIG_DM_MMC=y
>  CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_SDMA=y
>  CONFIG_MMC_SDHCI_BCM2835=y
>  CONFIG_DM_ETH=y
>  CONFIG_BCMGENET=y
> 

Reviewed-by: Minkyu Kang 

Thanks,
Minkyu Kang.

Re: [PATCH v2 1/3] mmc: sdhci: use phys2bus macro when dma address is accessed

[Minkyu Kang]

On 18/02/2020 10:25, Jaehoon Chung wrote:
> Use phys2bus macro when dma address is accessed.
> Some targets need to use pyhs2bus macro. (e.g, RPI4)
> After applied it, SDMA mode can be used.
> 
> Signed-off-by: Jaehoon Chung 
> Reviewed-by: Peng Fan 
> ---
> Changelog on V2
> - None
> 
>  drivers/mmc/sdhci.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
> index 01fa5a9d4d..93c9049c5d 100644
> --- a/drivers/mmc/sdhci.c
> +++ b/drivers/mmc/sdhci.c
> @@ -15,6 +15,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
>  void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
> @@ -164,7 +165,8 @@ static void sdhci_prepare_dma(struct sdhci_host *host, 
> struct mmc_data *data,
>   if (data->flags != MMC_DATA_READ)
>   memcpy(aligned_buffer, data->src, trans_bytes);
>  #endif
> - sdhci_writel(host, host->start_addr, SDHCI_DMA_ADDRESS);
> + sdhci_writel(host, phys_to_bus((ulong)host->start_addr),
> + SDHCI_DMA_ADDRESS);
>  
>   } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
>   sdhci_prepare_adma_table(host, data);
> @@ -220,7 +222,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, 
> struct mmc_data *data)
>   start_addr &=
>   ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
>   start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
> - sdhci_writel(host, start_addr,
> + sdhci_writel(host, 
> phys_to_bus((ulong)start_addr),
>SDHCI_DMA_ADDRESS);
>   }
>   }
> 

Reviewed-by: Minkyu Kang 

Thanks,
Minkyu Kang.

[PATCH v3 20/21] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold()

[chee . hong . ang]

From: Chee Hong Ang 

mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).

Signed-off-by: Chee Hong Ang 
---
 arch/arm/mach-socfpga/mailbox_s10.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-socfpga/mailbox_s10.c 
b/arch/arm/mach-socfpga/mailbox_s10.c
index f30e7f8..6b39576 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -330,6 +330,9 @@ error:
 
 int mbox_reset_cold(void)
 {
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+   psci_system_reset();
+#else
int ret;
 
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
@@ -338,6 +341,7 @@ int mbox_reset_cold(void)
/* mailbox sent failure, wait for watchdog to kick in */
hang();
}
+#endif
return 0;
 }
 
-- 
2.7.4

[PATCH v3 19/21] arm: socfpga: stratix10: Add ATF support to FPGA reconfig driver

[chee . hong . ang]

From: Chee Hong Ang 

FPGA recpnfiguration driver will call the ATF's PSCI runtime
services if it's running in non-secure mode (EL2).

Signed-off-by: Chee Hong Ang 
---
 drivers/fpga/stratix10.c | 141 ++-
 1 file changed, 140 insertions(+), 1 deletion(-)

diff --git a/drivers/fpga/stratix10.c b/drivers/fpga/stratix10.c
index d8e3250..050a179 100644
--- a/drivers/fpga/stratix10.c
+++ b/drivers/fpga/stratix10.c
@@ -5,11 +5,148 @@
 
 #include 
 #include 
-#include 
 
 #define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS   6
 #define RECONFIG_STATUS_INTERVAL_DELAY_US  100
 
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+
+#include 
+#include 
+
+#define BITSTREAM_CHUNK_SIZE   0x0
+#define RECONFIG_STATUS_POLL_RETRY_MAX 100
+
+/*
+ * Polling the FPGA configuration status.
+ * Return 0 for success, non-zero for error.
+ */
+static int reconfig_status_polling_resp(void)
+{
+   int ret;
+   unsigned long start = get_timer(0);
+
+   while (1) {
+   ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
+NULL, 0);
+
+   if (!ret)
+   return 0;   /* configuration success */
+
+   if (ret != INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY)
+   return ret;
+
+   if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
+   break;  /* time out */
+
+   puts(".");
+   udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+   }
+
+   return -ETIMEDOUT;
+}
+
+static int send_bistream(const void *rbf_data, size_t rbf_size)
+{
+   int i;
+   u64 res_buf[3];
+   u64 args[2];
+   u32 xfer_count = 0;
+   int ret, wr_ret = 0, retry = 0;
+   size_t buf_size = (rbf_size > BITSTREAM_CHUNK_SIZE) ?
+   BITSTREAM_CHUNK_SIZE : rbf_size;
+
+   while (rbf_size || xfer_count) {
+   if (!wr_ret && rbf_size) {
+   args[0] = (u64)rbf_data;
+   args[1] = buf_size;
+   wr_ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_WRITE,
+   args, 2, NULL, 0);
+
+   debug("wr_ret = %d, rbf_data = %p, buf_size = %08lx\n",
+ wr_ret, rbf_data, buf_size);
+
+   if (wr_ret == INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED)
+   continue;
+
+   rbf_size -= buf_size;
+   rbf_data += buf_size;
+
+   if (buf_size >= rbf_size)
+   buf_size = rbf_size;
+
+   xfer_count++;
+   puts(".");
+   } else {
+   ret = invoke_smc(
+   INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE,
+   NULL, 0, res_buf, 3);
+   if (!ret) {
+   for (i = 0; i < 3; i++) {
+   if (!res_buf[i])
+   break;
+   xfer_count--;
+   wr_ret = 0;
+   retry = 0;
+   }
+   } else if (ret !=
+  INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY)
+   return ret;
+   else if (!xfer_count)
+   return INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR;
+
+   if (++retry >= RECONFIG_STATUS_POLL_RETRY_MAX)
+   return -ETIMEDOUT;
+
+   udelay(2);
+   }
+   }
+
+   return 0;
+}
+
+/*
+ * This is the interface used by FPGA driver.
+ * Return 0 for success, non-zero for error.
+ */
+int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+   int ret;
+
+   debug("Invoking FPGA_CONFIG_START...\n");
+
+   ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, NULL, 0, NULL, 0);
+
+   if (ret) {
+   puts("Failure in RECONFIG mailbox command!\n");
+   return ret;
+   }
+
+   ret = send_bistream(rbf_data, rbf_size);
+   if (ret) {
+   printf("Error sending bitstream!\n");
+   return ret;
+   }
+
+   /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
+   udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+
+   debug("Polling with MBOX_RECONFIG_STATUS...\n");
+   ret = reconfig_status_polling_resp();
+   if (ret) {
+   printf("FPGA reconfiguration failed!");
+   return ret;
+   }
+
+   puts("FPGA reconfiguration OK!\n");
+
+   return ret;
+}
+
+#else
+
+#include 
+
 static 

[PATCH v3 21/21] configs: socfpga: Add defconfig for Agilex and Stratix 10 without ATF support

[chee . hong . ang]

From: Chee Hong Ang 

Booting Agilex and Stratix 10 without ATF support.

SPL -> U-Boot proper -> OS (Linux)

Signed-off-by: Chee Hong Ang 
---
 configs/socfpga_agilex_nofw_defconfig| 59 ++
 configs/socfpga_stratix10_nofw_defconfig | 63 
 2 files changed, 122 insertions(+)
 create mode 100644 configs/socfpga_agilex_nofw_defconfig
 create mode 100644 configs/socfpga_stratix10_nofw_defconfig

diff --git a/configs/socfpga_agilex_nofw_defconfig 
b/configs/socfpga_agilex_nofw_defconfig
new file mode 100644
index 000..3d63f8b
--- /dev/null
+++ b/configs/socfpga_agilex_nofw_defconfig
@@ -0,0 +1,59 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x200
+CONFIG_DM_GPIO=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_agilex"
+CONFIG_SPL_FS_FAT=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_BOOTDELAY=5
+CONFIG_SPL_CACHE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c0
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_ALTERA_SDRAM=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_SF_DEFAULT_MODE=0x2003
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_DM_RESET=y
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
diff --git a/configs/socfpga_stratix10_nofw_defconfig 
b/configs/socfpga_stratix10_nofw_defconfig
new file mode 100644
index 000..22169a2
--- /dev/null
+++ b/configs/socfpga_stratix10_nofw_defconfig
@@ -0,0 +1,63 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x200
+CONFIG_DM_GPIO=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_stratix10"
+CONFIG_SPL_FS_FAT=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_BOOTDELAY=5
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C0
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_ALTERA_SDRAM=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_MTD=y
+CONFIG_SF_DEFAULT_MODE=0x2003
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_DM_RESET=y
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_WDT=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
-- 
2.7.4

[PATCH v3 15/21] net: designware: socfpga: Secure register access in MAC driver

[chee . hong . ang]

From: Chee Hong Ang 

Allow MAC driver to access System Manager's EMAC control
registers in non-secure mode.

Signed-off-by: Chee Hong Ang 
---
 drivers/net/dwmac_socfpga.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c
index e93561d..293c660 100644
--- a/drivers/net/dwmac_socfpga.c
+++ b/drivers/net/dwmac_socfpga.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 
+#include 
 #include 
 
 struct dwmac_socfpga_platdata {
@@ -98,8 +99,8 @@ static int dwmac_socfpga_probe(struct udevice *dev)
reset_assert_bulk(_bulk);
 
modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
-   clrsetbits_le32(pdata->phy_intf, modemask,
-   modereg << pdata->reg_shift);
+   socfpga_secure_reg_update32((phys_addr_t)pdata->phy_intf, modemask,
+   modereg << pdata->reg_shift);
 
reset_release_bulk(_bulk);
 
-- 
2.7.4

[PATCH v3 16/21] arm: socfpga: Secure register access in Reset Manager driver

[chee . hong . ang]

From: Chee Hong Ang 

Allow socfpga_bridges_reset() function in Reset Manager driver to
access System Manager's register in non-secure mode (EL2).

Signed-off-by: Chee Hong Ang 
---
 arch/arm/mach-socfpga/reset_manager_s10.c | 31 ++-
 1 file changed, 18 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c 
b/arch/arm/mach-socfpga/reset_manager_s10.c
index c743077..d03f121 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -56,34 +57,37 @@ void socfpga_bridges_reset(int enable)
 {
if (enable) {
/* clear idle request to all bridges */
-   setbits_le32(socfpga_get_sysmgr_addr() +
-SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0);
+   socfpga_secure_reg_update32(socfpga_get_sysmgr_addr() +
+   SYSMGR_SOC64_NOC_IDLEREQ_CLR,
+   ~0, ~0);
 
/* Release all bridges from reset state */
clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
 ~0);
 
/* Poll until all idleack to 0 */
-   while (readl(socfpga_get_sysmgr_addr() +
-SYSMGR_SOC64_NOC_IDLEACK))
+   while (socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
+SYSMGR_SOC64_NOC_IDLEACK))
;
} else {
/* set idle request to all bridges */
-   writel(~0,
-  socfpga_get_sysmgr_addr() +
-  SYSMGR_SOC64_NOC_IDLEREQ_SET);
+   socfpga_secure_reg_write32(~0, socfpga_get_sysmgr_addr() +
+  SYSMGR_SOC64_NOC_IDLEREQ_SET);
 
/* Enable the NOC timeout */
-   writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
+   socfpga_secure_reg_write32(1, socfpga_get_sysmgr_addr() +
+  SYSMGR_SOC64_NOC_TIMEOUT);
 
/* Poll until all idleack to 1 */
-   while ((readl(socfpga_get_sysmgr_addr() + 
SYSMGR_SOC64_NOC_IDLEACK) ^
-   (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
+   while ((socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
+  SYSMGR_SOC64_NOC_IDLEACK) ^ (SYSMGR_NOC_H2F_MSK |
+  SYSMGR_NOC_LWH2F_MSK)))
;
 
/* Poll until all idlestatus to 1 */
-   while ((readl(socfpga_get_sysmgr_addr() + 
SYSMGR_SOC64_NOC_IDLESTATUS) ^
-   (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
+   while ((socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
+  SYSMGR_SOC64_NOC_IDLESTATUS) ^ (SYSMGR_NOC_H2F_MSK |
+  SYSMGR_NOC_LWH2F_MSK)))
;
 
/* Reset all bridges (except NOR DDR scheduler & F2S) */
@@ -92,7 +96,8 @@ void socfpga_bridges_reset(int enable)
   RSTMGR_BRGMODRST_FPGA2SOC_MASK));
 
/* Disable NOC timeout */
-   writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
+   socfpga_secure_reg_write32(0, socfpga_get_sysmgr_addr() +
+  SYSMGR_SOC64_NOC_TIMEOUT);
}
 }
 
-- 
2.7.4

[PATCH v3 18/21] arm: socfpga: Bridge reset invokes SMC service calls in EL2

[chee . hong . ang]

From: Chee Hong Ang 

In EL3, do_bridge_reset() directly send mailbox commands to SDM to
query the FPGA configuration status. If running in non-secure
mode (EL2), it invokes SMC service calls to ATF (EL3) to perform the
query.

Signed-off-by: Chee Hong Ang 
---
 arch/arm/mach-socfpga/misc_s10.c | 16 +++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index 393b486..d93aaf5 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -154,11 +155,24 @@ void do_bridge_reset(int enable, unsigned int mask)
 {
/* Check FPGA status before bridge enable */
if (enable) {
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+   u64 arg = 1;
+
+   /* Send MBOX_RECONFIG_STATUS to SDM */
+   int ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
+NULL, 0);
+
+   if (ret && ret != INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY) {
+   /* Send MBOX_CONFIG_STATUS to SDM */
+   ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE,
+, 1, NULL, 0);
+   }
+#else
int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
 
if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
-
+#endif
if (ret)
return;
}
-- 
2.7.4

[PATCH v3 17/21] arm: socfpga: stratix10: Initialize timer in SPL

[chee . hong . ang]

From: Chee Hong Ang 

Initialize timer in SPL running in secure mode (EL3)
and skip timer initialization in U-Boot proper running in
non-secure mode (EL2).

Signed-off-by: Chee Hong Ang 
---
 arch/arm/mach-socfpga/timer_s10.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/timer_s10.c 
b/arch/arm/mach-socfpga/timer_s10.c
index 5723789..0fa56c3 100644
--- a/arch/arm/mach-socfpga/timer_s10.c
+++ b/arch/arm/mach-socfpga/timer_s10.c
@@ -13,6 +13,7 @@
  */
 int timer_init(void)
 {
+#ifdef CONFIG_SPL_BUILD
int enable = 0x3;   /* timer enable + output signal masked */
int loadval = ~0;
 
@@ -21,6 +22,6 @@ int timer_init(void)
/* enable processor pysical counter */
asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable));
asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval));
-
+#endif
return 0;
 }
-- 
2.7.4

[PATCH v3 14/21] mmc: dwmmc: socfpga: Secure register access in MMC driver

[chee . hong . ang]

From: Chee Hong Ang 

Allow MMC driver to access System Manager's SDMMC control
register in non-secure mode (EL2).

Signed-off-by: Chee Hong Ang 
---
 drivers/mmc/socfpga_dw_mmc.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 786cdc7..558f246 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -5,6 +5,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -57,10 +58,12 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
 
debug("%s: drvsel %d smplsel %d\n", __func__,
  priv->drvsel, priv->smplsel);
-   writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
+   socfpga_secure_reg_write32(sdmmc_mask, socfpga_get_sysmgr_addr() +
+  SYSMGR_SDMMC);
 
debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
-   readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
+ socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
+ SYSMGR_SDMMC));
 
/* Enable SDMMC clock */
setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
-- 
2.7.4

[PATCH v3 08/21] arm: socfpga: Add SMC helper function for Intel SOCFPGA (64bits)

[chee . hong . ang]

From: Chee Hong Ang 

Allow U-Boot proper running in non-secure mode (EL2) to invoke
SMC call to ATF's PSCI runtime services such as System Manager's
registers access, 2nd phase bitstream FPGA reconfiguration,
Remote System Update (RSU) and etc.

Signed-off-by: Chee Hong Ang 
---
 arch/arm/mach-socfpga/include/mach/misc.h |  3 +++
 arch/arm/mach-socfpga/misc_s10.c  | 20 
 2 files changed, 23 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/misc.h 
b/arch/arm/mach-socfpga/include/mach/misc.h
index f6de1cc..b5625e1 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -43,4 +43,7 @@ void do_bridge_reset(int enable, unsigned int mask);
 void socfpga_pl310_clear(void);
 void socfpga_get_managers_addr(void);
 
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len);
+#endif
 #endif /* _SOCFPGA_MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index a3f5b43..adfff82 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -164,3 +164,23 @@ void do_bridge_reset(int enable, unsigned int mask)
 
socfpga_bridges_reset(enable);
 }
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len)
+{
+   struct pt_regs regs;
+
+   memset(, 0, sizeof(regs));
+   regs.regs[0] = func_id;
+
+   if (args)
+   memcpy([1], [0], arg_len * sizeof(u64));
+
+   smc_call();
+
+   if (ret_arg)
+   memcpy(_arg[0], [1], ret_len * sizeof(u64));
+
+   return regs.regs[0];
+}
+#endif
-- 
2.7.4

[PATCH v3 11/21] arm: socfpga: Secure register access for clock manager (SoC 64bits)

[chee . hong . ang]

From: Chee Hong Ang 

Allow clock manager driver to access the System Manager's Boot
Scratch Register 0 in non-secure mode (EL2) on SoC 64bits platform.

Signed-off-by: Chee Hong Ang 
---
 arch/arm/mach-socfpga/clock_manager_agilex.c | 5 +++--
 arch/arm/mach-socfpga/clock_manager_s10.c| 5 +++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c 
b/arch/arm/mach-socfpga/clock_manager_agilex.c
index 4ee2b7b..e5a0998 100644
--- a/arch/arm/mach-socfpga/clock_manager_agilex.c
+++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -65,8 +66,8 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
 
 u32 cm_get_qspi_controller_clk_hz(void)
 {
-   return readl(socfpga_get_sysmgr_addr() +
-SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+   return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
+SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
 }
 
 void cm_print_clock_quick_summary(void)
diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c 
b/arch/arm/mach-socfpga/clock_manager_s10.c
index 05e4212..02578cc 100644
--- a/arch/arm/mach-socfpga/clock_manager_s10.c
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -385,8 +386,8 @@ unsigned int cm_get_l4_sp_clk_hz(void)
 
 unsigned int cm_get_qspi_controller_clk_hz(void)
 {
-   return readl(socfpga_get_sysmgr_addr() +
-SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+   return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
+SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
 }
 
 unsigned int cm_get_spi_controller_clk_hz(void)
-- 
2.7.4

[PATCH v3 12/21] arm: socfpga: Secure register access in PHY mode setup

[chee . hong . ang]

From: Chee Hong Ang 

Allow access to System Manager's EMAC control register from
non-secure mode during PHY mode setup.

Signed-off-by: Chee Hong Ang 
---
 arch/arm/mach-socfpga/misc_s10.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index adfff82..393b486 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -65,9 +66,9 @@ static u32 socfpga_phymode_setup(u32 gmac_index, const char 
*phymode)
else
return -EINVAL;
 
-   clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0 +
-   gmac_index,
-   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
+   socfpga_secure_reg_update32(socfpga_get_sysmgr_addr() +
+   SYSMGR_SOC64_EMAC0 + gmac_index,
+   SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
 
return 0;
 }
-- 
2.7.4

[PATCH v3 09/21] arm: socfpga: Define SMC function identifiers for PSCI SiP services

[chee . hong . ang]

From: Chee Hong Ang 

This header file defines the Secure Monitor Call (SMC) message
protocol for ATF (BL31) PSCI runtime services. It includes all
the PSCI SiP function identifiers for the secure runtime services
provided by ATF. The secure runtime services include System Manager's
registers access, 2nd phase bitstream FPGA reconfiguration, Remote
System Update (RSU) and etc.

Signed-off-by: Chee Hong Ang 
---
 include/linux/intel-smc.h | 374 ++
 1 file changed, 374 insertions(+)
 create mode 100644 include/linux/intel-smc.h

diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h
new file mode 100644
index 000..e3d3aa9
--- /dev/null
+++ b/include/linux/intel-smc.h
@@ -0,0 +1,374 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017-2020, Intel Corporation
+ */
+
+#ifndef __INTEL_SMC_H
+#define __INTEL_SMC_H
+
+#include 
+#include 
+
+/*
+ * This file defines the Secure Monitor Call (SMC) message protocol used for
+ * service layer driver in normal world (EL1) to communicate with secure
+ * monitor software in Secure Monitor Exception Level 3 (EL3).
+ *
+ * This file is shared with secure firmware (FW) which is out of kernel tree.
+ *
+ * An ARM SMC instruction takes a function identifier and up to 6 64-bit
+ * register values as arguments, and can return up to 4 64-bit register
+ * value. The operation of the secure monitor is determined by the parameter
+ * values passed in through registers.
+
+ * EL1 and EL3 communicates pointer as physical address rather than the
+ * virtual address.
+ */
+
+/*
+ * Functions specified by ARM SMC Calling convention:
+ *
+ * FAST call executes atomic operations, returns when the requested operation
+ * has completed.
+ * STD call starts a operation which can be preempted by a non-secure
+ * interrupt. The call can return before the requested operation has
+ * completed.
+ *
+ * a0..a7 is used as register names in the descriptions below, on arm32
+ * that translates to r0..r7 and on arm64 to w0..w7.
+ */
+
+#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \
+   ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \
+   ARM_SMCCC_OWNER_SIP, (func_num))
+
+#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \
+   ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \
+   ARM_SMCCC_OWNER_SIP, (func_num))
+
+/*
+ * Return values in INTEL_SIP_SMC_* call
+ *
+ * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION:
+ * Secure monitor software doesn't recognize the request.
+ *
+ * INTEL_SIP_SMC_STATUS_OK:
+ * FPGA configuration completed successfully,
+ * In case of FPGA configuration write operation, it means secure monitor
+ * software can accept the next chunk of FPGA configuration data.
+ *
+ * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY:
+ * In case of FPGA configuration write operation, it means secure monitor
+ * software is still processing previous data & can't accept the next chunk
+ * of data. Service driver needs to issue
+ * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the
+ * completed block(s).
+ *
+ * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR:
+ * There is error during the FPGA configuration process.
+ *
+ * INTEL_SIP_SMC_REG_ERROR:
+ * There is error during a read or write operation of the protected
+ * registers.
+ */
+#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION  0x
+#define INTEL_SIP_SMC_STATUS_OK0x0
+#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY  0x1
+#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED  0x2
+#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR 0x4
+#define INTEL_SIP_SMC_REG_ERROR0x5
+#define INTEL_SIP_SMC_RSU_ERROR0x7
+
+/*
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_START
+ *
+ * Sync call used by service driver at EL1 to request the FPGA in EL3 to
+ * be prepare to receive a new configuration.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_START.
+ * a1: flag for full or partial configuration
+ *0 full reconfiguration.
+ *1 partial reconfiguration.
+ * a2-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR.
+ * a1-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1
+#define INTEL_SIP_SMC_FPGA_CONFIG_START \
+   INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START)
+
+/*
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE
+ *
+ * Async call used by service driver at EL1 to provide FPGA configuration data
+ * to secure world.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE.
+ * a1: 64bit physical address of the configuration data memory block
+ * a2: Size of configuration data block.
+ * a3-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or
+ * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR.
+ * a1: 64bit physical address of 1st completed memory block if any completed

[PATCH v3 13/21] arm: socfpga: Secure register access for reading PLL frequency

[chee . hong . ang]

From: Chee Hong Ang 

Allow reading external oscillator and FPGA clock's frequency from
System Manager's Boot Scratch Register 1 and Boot Scratch Register 2
in non-secure mode (EL2) on SoC 64bits platform.

Signed-off-by: Chee Hong Ang 
---
 arch/arm/mach-socfpga/wrap_pll_config_s10.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c 
b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
index 3da8579..7bd92d0 100644
--- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 
 const struct cm_config * const cm_get_default_config(void)
 {
@@ -39,8 +40,8 @@ const unsigned int cm_get_osc_clk_hz(void)
writel(clock,
   socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
 #endif
-   return readl(socfpga_get_sysmgr_addr() +
-SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
+   return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
+SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
 }
 
 const unsigned int cm_get_intosc_clk_hz(void)
@@ -56,6 +57,6 @@ const unsigned int cm_get_fpga_clk_hz(void)
writel(clock,
   socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD2);
 #endif
-   return readl(socfpga_get_sysmgr_addr() +
-SYSMGR_SOC64_BOOT_SCRATCH_COLD2);
+   return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
+SYSMGR_SOC64_BOOT_SCRATCH_COLD2);
 }
-- 
2.7.4

[PATCH v3 10/21] arm: socfpga: Add secure register access helper functions for SoC 64bits

[chee . hong . ang]

From: Chee Hong Ang 

These secure register access functions allow U-Boot proper running
at EL2 (non-secure) to access System Manager's secure registers
by calling the ATF's PSCI runtime services (EL3/secure). If these
helper functions are called from secure mode (EL3), the helper
function will direct access the secure registers without calling
the ATF's PSCI runtime services.

Signed-off-by: Chee Hong Ang 
---
 arch/arm/mach-socfpga/Makefile |  4 ++
 .../mach-socfpga/include/mach/secure_reg_helper.h  | 20 
 arch/arm/mach-socfpga/secure_reg_helper.c  | 57 ++
 3 files changed, 81 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
 create mode 100644 arch/arm/mach-socfpga/secure_reg_helper.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 3758c0a..6ff0891 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -53,6 +53,10 @@ obj-y+= wrap_pinmux_config_s10.o
 obj-y  += wrap_pll_config_s10.o
 endif
 
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_ATF)  +=secure_reg_helper.o
+endif
+
 ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
 obj-y  += spl_gen5.o
diff --git a/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h 
b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
new file mode 100644
index 000..de581fc
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2019 Intel Corporation 
+ *
+ */
+
+#ifndef_SECURE_REG_HELPER_H_
+#define_SECURE_REG_HELPER_H_
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+u32 socfpga_secure_reg_read32(phys_addr_t reg_addr);
+void socfpga_secure_reg_write32(u32 val, phys_addr_t reg_addr);
+void socfpga_secure_reg_update32(phys_addr_t reg_addr, u32 mask, u32 val);
+#else
+#define socfpga_secure_reg_read32  readl
+#define socfpga_secure_reg_write32 writel
+#define socfpga_secure_reg_update32clrsetbits_le32
+#endif
+
+#endif /* _SECURE_REG_HELPER_H_ */
diff --git a/arch/arm/mach-socfpga/secure_reg_helper.c 
b/arch/arm/mach-socfpga/secure_reg_helper.c
new file mode 100644
index 000..46658a2
--- /dev/null
+++ b/arch/arm/mach-socfpga/secure_reg_helper.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+u32 socfpga_secure_reg_read32(phys_addr_t reg_addr)
+{
+   int ret;
+   u64 ret_arg;
+   u64 args[1];
+
+   args[0] = (u64)reg_addr;
+   ret = invoke_smc(INTEL_SIP_SMC_REG_READ, args, 1, _arg, 1);
+   if (ret) {
+   /* SMC call return error */
+   hang();
+   }
+
+   return ret_arg;
+}
+
+void socfpga_secure_reg_write32(u32 val, phys_addr_t reg_addr)
+{
+   int ret;
+   u64 args[2];
+
+   args[0] = (u64)reg_addr;
+   args[1] = val;
+   ret = invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0);
+   if (ret) {
+   /* SMC call return error */
+   hang();
+   }
+}
+
+void socfpga_secure_reg_update32(phys_addr_t reg_addr, u32 mask, u32 val)
+{
+   int ret;
+   u64 args[3];
+
+   args[0] = (u64)reg_addr;
+   args[1] = mask;
+   args[2] = val;
+   ret = invoke_smc(INTEL_SIP_SMC_REG_UPDATE, args, 3, NULL, 0);
+   if (ret) {
+   /* SMC call return error */
+   hang();
+   }
+}
-- 
2.7.4

[PATCH v3 04/21] arm: socfpga: Load FIT image with ATF support

[chee . hong . ang]

From: Chee Hong Ang 

Instead of loading u-boot proper image (u-boot.img), SPL
now loads FIT image (u-boot.itb) which includes u-boot
proper, ATF and u-boot proper's DTB.

Signed-off-by: Chee Hong Ang 
---
 include/configs/socfpga_soc64_common.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/include/configs/socfpga_soc64_common.h 
b/include/configs/socfpga_soc64_common.h
index 87c7345..f035381 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -197,6 +197,10 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
 
 /* SPL SDMMC boot support */
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#ifdef CONFIG_SPL_LOAD_FIT
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.itb"
+#else
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img"
+#endif
 
 #endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */
-- 
2.7.4

[PATCH v3 05/21] arm: socfpga: Override 'lowlevel_init' to support ATF

[chee . hong . ang]

From: Chee Hong Ang 

Override 'lowlevel_init' to support booting ATF from SPL
on Intel SOCFPGA (64bits) platforms.

Signed-off-by: Chee Hong Ang 
---
 arch/arm/mach-socfpga/Makefile   |  2 +
 arch/arm/mach-socfpga/lowlevel_init_64.S | 81 
 2 files changed, 83 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/lowlevel_init_64.S

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 418f543..3758c0a 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -29,6 +29,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y  += clock_manager_s10.o
+obj-y  += lowlevel_init_64.o
 obj-y  += mailbox_s10.o
 obj-y  += misc_s10.o
 obj-y  += mmu-arm64_s10.o
@@ -41,6 +42,7 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_AGILEX
 obj-y  += clock_manager_agilex.o
+obj-y  += lowlevel_init_64.o
 obj-y  += mailbox_s10.o
 obj-y  += misc_s10.o
 obj-y  += mmu-arm64_s10.o
diff --git a/arch/arm/mach-socfpga/lowlevel_init_64.S 
b/arch/arm/mach-socfpga/lowlevel_init_64.S
new file mode 100644
index 000..21402c0
--- /dev/null
+++ b/arch/arm/mach-socfpga/lowlevel_init_64.S
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019, Intel Corporation
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+ENTRY(lowlevel_init)
+   mov x29, lr /* Save LR */
+
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#ifdef CONFIG_SPL_ATF
+   branch_if_slave x0, 2f
+#else
+   branch_if_slave x0, 1f
+#endif
+
+   ldr x0, =GICD_BASE
+   bl  gic_init_secure
+   b   2f
+
+1:
+#if defined(CONFIG_GICV3)
+   ldr x0, =GICR_BASE
+   bl  gic_init_secure_percpu
+#elif defined(CONFIG_GICV2)
+   ldr x0, =GICD_BASE
+   ldr x1, =GICC_BASE
+   bl  gic_init_secure_percpu
+#endif
+#endif
+
+#ifdef CONFIG_ARMV8_MULTIENTRY
+   branch_if_master x0, x1, 3f
+
+   /*
+* Slave should wait for master clearing spin table.
+* This sync prevent slaves observing incorrect
+* value of spin table and jumping to wrong place.
+*/
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#ifdef CONFIG_GICV2
+   ldr x0, =GICC_BASE
+#endif
+   bl  gic_wait_for_interrupt
+#endif
+
+   /*
+* All slaves will enter EL2 and optionally EL1.
+*/
+   adr x4, lowlevel_in_el2
+   ldr x5, =ES_TO_AARCH64
+   bl  armv8_switch_to_el2
+
+lowlevel_in_el2:
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+   adr x4, lowlevel_in_el1
+   ldr x5, =ES_TO_AARCH64
+   bl  armv8_switch_to_el1
+
+lowlevel_in_el1:
+#endif
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
+2:
+#ifdef CONFIG_SPL_BUILD
+   ldr x4, =CPU_RELEASE_ADDR
+   ldr x5, [x4]
+   cbz x5, checkslavecpu
+   br  x5
+checkslavecpu:
+   branch_if_slave x0, 2b
+#endif
+
+3:
+   mov lr, x29 /* Restore LR */
+   ret
+ENDPROC(lowlevel_init)
-- 
2.7.4

[PATCH v3 06/21] configs: socfpga: Enable FIT image loading with ATF support

[chee . hong . ang]

From: Chee Hong Ang 

SPL now loads ATF (BL31), U-Boot proper and DTB from FIT
image. The new boot flow with ATF support is as follow:

SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux)

U-Boot proper now starts at 0x20 (CONFIG_SYS_TEXT_BASE).
ATF will occupy the address range starting from 0x1000.

Signed-off-by: Chee Hong Ang 
---
 configs/socfpga_agilex_defconfig| 7 ++-
 configs/socfpga_stratix10_defconfig | 7 ++-
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
index 693a774..2373f89 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_TEXT_BASE=0x20
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x200
@@ -10,10 +10,15 @@ CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
 CONFIG_IDENT_STRING="socfpga_agilex"
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_SOURCE="board/altera/soc64/its/fit_spl_atf.its"
 CONFIG_BOOTDELAY=5
 CONFIG_SPL_CACHE=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c0
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/socfpga_stratix10_defconfig 
b/configs/socfpga_stratix10_defconfig
index 26db40f..dc34357 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_TEXT_BASE=0x20
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x200
@@ -10,9 +10,14 @@ CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
 CONFIG_IDENT_STRING="socfpga_stratix10"
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_SOURCE="board/altera/soc64/its/fit_spl_atf.its"
 CONFIG_BOOTDELAY=5
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C0
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
 CONFIG_CMD_MEMTEST=y
-- 
2.7.4

[PATCH v3 02/21] arm: socfpga: add fit source file for pack itb with ATF

[chee . hong . ang]

From: Chee Hong Ang 

Generate a FIT image for Intel SOCFPGA(64bits) which
include U-boot proper, ATF and DTB for U-boot proper.

Signed-off-by: Chee Hong Ang 
---
 board/altera/soc64/its/fit_spl_atf.its | 52 ++
 1 file changed, 52 insertions(+)
 create mode 100644 board/altera/soc64/its/fit_spl_atf.its

diff --git a/board/altera/soc64/its/fit_spl_atf.its 
b/board/altera/soc64/its/fit_spl_atf.its
new file mode 100644
index 000..8296fc0
--- /dev/null
+++ b/board/altera/soc64/its/fit_spl_atf.its
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2019 Intel Corporation. All rights reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/dts-v1/;
+
+/ {
+   description = "FIT image with U-Boot proper, ATF bl31, DTB";
+   #address-cells = <1>;
+
+   images {
+   uboot {
+   description = "U-Boot (64-bit)";
+   data = /incbin/("../../../../u-boot-nodtb.bin");
+   type = "standalone";
+   os = "U-Boot";
+   arch = "arm64";
+   compression = "none";
+   load = <0x0020>;
+   };
+
+   atf {
+   description = "ARM Trusted Firmware";
+   data = /incbin/("../../../../bl31.bin");
+   type = "firmware";
+   os = "arm-trusted-firmware";
+   arch = "arm64";
+   compression = "none";
+   load = <0x1000>;
+   entry = <0x1000>;
+   };
+
+   fdt {
+   description = "Stratix 10 flat device-tree";
+   data = /incbin/("../../../../u-boot.dtb");
+   type = "flat_dt";
+   compression = "none";
+   };
+   };
+
+   configurations {
+   default = "conf";
+   conf {
+   description = "Intel Stratix 10";
+   firmware = "atf";
+   loadables = "uboot";
+   fdt = "fdt";
+   };
+   };
+};
-- 
2.7.4

[PATCH v3 03/21] arm: socfpga: Add function for checking description from FIT image

[chee . hong . ang]

From: Chee Hong Ang 

Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do nothing for now.
Users are allowed to override this 'weak' function in their
specific board implementation.

Signed-off-by: Chee Hong Ang 
---
 arch/arm/mach-socfpga/board.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 7c8c05c..5757041 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -86,3 +86,13 @@ int g_dnl_board_usb_cable_connected(void)
return 1;
 }
 #endif
+
+#ifdef CONFIG_SPL_BUILD
+__weak int board_fit_config_name_match(const char *name)
+{
+   /* Just empty function now - can't decide what to choose */
+   debug("%s: %s\n", __func__, name);
+
+   return 0;
+}
+#endif
-- 
2.7.4

[PATCH v3 07/21] arm: socfpga: Disable "spin-table" method for booting Linux

[chee . hong . ang]

From: Chee Hong Ang 

Standard PSCI function "CPU_ON" provided by ATF is now used
by Linux kernel to bring up the secondary CPUs to enable
SMP booting in Linux on SoC 64bits platform.

Signed-off-by: Chee Hong Ang 
---
 arch/arm/mach-socfpga/Kconfig | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 969698c..6549033 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -33,7 +33,6 @@ config TARGET_SOCFPGA_AGILEX
bool
select ARMV8_MULTIENTRY
select ARMV8_SET_SMPEN
-   select ARMV8_SPIN_TABLE
select CLK
select NCORE_CACHE
select SPL_CLK if SPL
@@ -77,7 +76,6 @@ config TARGET_SOCFPGA_STRATIX10
bool
select ARMV8_MULTIENTRY
select ARMV8_SET_SMPEN
-   select ARMV8_SPIN_TABLE
select FPGA_STRATIX10
 
 choice
-- 
2.7.4

[PATCH v3 01/21] configs: agilex: Remove CONFIG_OF_EMBED

[chee . hong . ang]

From: Chee Hong Ang 

CONFIG_OF_EMBED was primarily enabled to support the agilex
spl hex file requirements.  Since this option now produces a
warning during build, and the spl hex can be created using
alternate methods, CONFIG_OF_EMBED is no longer needed.

Signed-off-by: Chee Hong Ang 
---
 configs/socfpga_agilex_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
index 4fd84ad..693a774 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_defconfig
@@ -29,7 +29,6 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_NET_RANDOM_ETHADDR=y
-- 
2.7.4

[PATCH v3 00/21] Enable ARM Trusted Firmware for U-Boot

[chee . hong . ang]

From: "Ang, Chee Hong" 

v3 changes:

[v3 03/21] arm: socfpga: Add function for checking description from FIT image
- documented the 'weak' function in commit message

[v3 05/21] arm: socfpga: Override 'lowlevel_init' to support ATF
- changed the source file name to 'lowlevel_init_64.S'
- removed a redundant '#ifdef' in the 'lowlevel_init' function

[v3 06/21] configs: socfpga: Enable FIT image loading with ATF support
- removed CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y from defconfigs
- documented the change of address in CONFIG_SYS_TEXT_BASE in commit message
 
[v3 08/21] arm: socfpga: Add SMC helper function for Intel SOCFPGA (64bits)
- replaced for-loops with memcpys

[v3 09/21] arm: socfpga: Define SMC function identifiers for PSCI SiP services
- update the license header date to '2017-2020'
- fixed the indentations

[v3 10/21] arm: socfpga: Add secure register access helper functions for SoC 
64bits
- remove inner 'ifdef' in Makefile

v2:
https://lists.denx.de/pipermail/u-boot/2020-February/400704.html

These patchsets have dependency on:
https://lists.denx.de/pipermail/u-boot/2019-September/384906.html

Chee Hong Ang (21):
  configs: agilex: Remove CONFIG_OF_EMBED
  arm: socfpga: add fit source file for pack itb with ATF
  arm: socfpga: Add function for checking description from FIT image
  arm: socfpga: Load FIT image with ATF support
  arm: socfpga: Override 'lowlevel_init' to support ATF
  configs: socfpga: Enable FIT image loading with ATF support
  arm: socfpga: Disable "spin-table" method for booting Linux
  arm: socfpga: Add SMC helper function for Intel SOCFPGA (64bits)
  arm: socfpga: Define SMC function identifiers for PSCI SiP services
  arm: socfpga: Add secure register access helper functions for SoC
64bits
  arm: socfpga: Secure register access for clock manager (SoC 64bits)
  arm: socfpga: Secure register access in PHY mode setup
  arm: socfpga: Secure register access for reading PLL frequency
  mmc: dwmmc: socfpga: Secure register access in MMC driver
  net: designware: socfpga: Secure register access in MAC driver
  arm: socfpga: Secure register access in Reset Manager driver
  arm: socfpga: stratix10: Initialize timer in SPL
  arm: socfpga: Bridge reset invokes SMC service calls in EL2
  arm: socfpga: stratix10: Add ATF support to FPGA reconfig driver
  arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to
mbox_reset_cold()
  configs: socfpga: Add defconfig for Agilex and Stratix 10 without ATF
support

 arch/arm/mach-socfpga/Kconfig  |   2 -
 arch/arm/mach-socfpga/Makefile |   6 +
 arch/arm/mach-socfpga/board.c  |  10 +
 arch/arm/mach-socfpga/clock_manager_agilex.c   |   5 +-
 arch/arm/mach-socfpga/clock_manager_s10.c  |   5 +-
 arch/arm/mach-socfpga/include/mach/misc.h  |   3 +
 .../mach-socfpga/include/mach/secure_reg_helper.h  |  20 ++
 arch/arm/mach-socfpga/lowlevel_init_64.S   |  81 +
 arch/arm/mach-socfpga/mailbox_s10.c|   4 +
 arch/arm/mach-socfpga/misc_s10.c   |  43 ++-
 arch/arm/mach-socfpga/reset_manager_s10.c  |  31 +-
 arch/arm/mach-socfpga/secure_reg_helper.c  |  57 
 arch/arm/mach-socfpga/timer_s10.c  |   3 +-
 arch/arm/mach-socfpga/wrap_pll_config_s10.c|   9 +-
 board/altera/soc64/its/fit_spl_atf.its |  52 +++
 configs/socfpga_agilex_defconfig   |   8 +-
 ...lex_defconfig => socfpga_agilex_nofw_defconfig} |   2 +-
 configs/socfpga_stratix10_defconfig|   7 +-
 ..._defconfig => socfpga_stratix10_nofw_defconfig} |   2 +-
 drivers/fpga/stratix10.c   | 141 +++-
 drivers/mmc/socfpga_dw_mmc.c   |   7 +-
 drivers/net/dwmac_socfpga.c|   5 +-
 include/configs/socfpga_soc64_common.h |   4 +
 include/linux/intel-smc.h  | 374 +
 24 files changed, 843 insertions(+), 38 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/secure_reg_helper.h
 create mode 100644 arch/arm/mach-socfpga/lowlevel_init_64.S
 create mode 100644 arch/arm/mach-socfpga/secure_reg_helper.c
 create mode 100644 board/altera/soc64/its/fit_spl_atf.its
 copy configs/{socfpga_agilex_defconfig => socfpga_agilex_nofw_defconfig} (97%)
 copy configs/{socfpga_stratix10_defconfig => socfpga_stratix10_nofw_defconfig} 
(97%)
 create mode 100644 include/linux/intel-smc.h

-- 
2.7.4

[PATCH 1/1] azure: build HTML documentation

[Heinrich Schuchardt]

Several patches delivered incorrect restructured text as documentation. We
should be able to discover this in Azure CI.

Provide a build step for 'make htmldocs'.

Signed-off-by: Heinrich Schuchardt 
---
Hello Tom,

I have no Azure account to check if this actually works.

The patch depends on:

[PATCH 1/1] Dockerfile: add imagemagick
https://lists.denx.de/pipermail/u-boot/2020-February/400983.html

Best regards

Heinrich
---
 .azure-pipelines.yml | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index c22095830c..129035a1a5 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -54,6 +54,16 @@ jobs:
 steps:
   - script: cppcheck --force --quiet --inline-suppr .

+  - job: htmldocs
+displayName: 'Build HTML documentation'
+pool:
+  vmImage: $(ubuntu_vm)
+container:
+  image: $(ci_runner_image)
+  options: $(container_option)
+steps:
+  - script: make htmldocs
+
   - job: todo
 displayName: 'Search for TODO within source tree'
 pool:
--
2.25.0

[PATCH 1/1] gitlab: build HTML documentation

[Heinrich Schuchardt]

Several patches delivered incorrect restructured text as documentation. We
should be able to discover this in Gitlab CI.

Provide a build step for 'make htmldocs'.

Signed-off-by: Heinrich Schuchardt 
---
This patch requires a new Docker image. Cf.

[PATCH 1/1] Dockerfile: add imagemagick
https://lists.denx.de/pipermail/u-boot/2020-February/400983.html

If have tested successfully against Docker image
xypron/u-boot-gitlab-ci-runner:2020-02-20:
https://gitlab.denx.de/u-boot/custodians/u-boot-efi/-/jobs/60271
---
 .gitlab-ci.yml | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index d486e72042..652ed3b501 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -122,6 +122,13 @@ grep TODO/FIXME/HACK:
 # search for HACK within source tree and ignore HACKKIT board
 - grep -r HACK . | grep -v HACKKIT

+# build HTML documentation
+htmldocs:
+  tags: [ 'all' ]
+  stage: testsuites
+  script:
+- make htmldocs
+
 # some statistics about the code base
 sloccount:
   tags: [ 'all' ]
--
2.25.0

[PATCH 1/1] Dockerfile: add imagemagick

[Heinrich Schuchardt]

In reStructured text documentation we sometimes find formatting problems.
So we should add 'make htmldocs' to our Gitlab Ci steps and let all
warning result in a build failure.

For building the htmldocs target without warnings we need the ImageMagick
package.

Signed-off-by: Heinrich Schuchardt 
---
 Dockerfile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Dockerfile b/Dockerfile
index 1f8f7a4..32d43f7 100644
--- a/Dockerfile
+++ b/Dockerfile
@@ -53,6 +53,7 @@ RUN apt-get update && apt-get install -y \
grub-efi-amd64-bin \
grub-efi-ia32-bin \
iasl \
+   imagemagick \
iputils-ping \
libisl15 \
liblz4-tool \
--
2.25.0

Re: [PATCH 1/2] doc/Makefile: turn warnings into errors

[Heinrich Schuchardt]

On 2/21/20 5:31 AM, Heinrich Schuchardt wrote:

On 2/21/20 5:06 AM, Tom Rini wrote:

On Fri, Feb 21, 2020 at 04:26:36AM +0100, Heinrich Schuchardt wrote:


Several patches delivered incorrect restructured text as
documentation. We
should be able to discover this in Travis CI or Gitlab CI.

So let us turn all build warnings into errors.

We cannot add --keep-going as Gitlab does not use sphinx-build
version 1.8
or later yet.


Why can't we upgrade sphinx-build so that we then run these builds also
in Gitlab / Azure?  Thanks!


Maybe this was unclear to you: My choice was not to use --keep-going
because I want run the test in the current Gitlab Docker image. With the
patch as it is we can run on Gitlab.

But there is another package (imagemagick) missing in the Dockerimage. I
am currently testing if this is the only missing package. I will submit
the .gitlab-ci.yml patch thereafter.



This is what --keep-going does:

With -W option, keep going processing when getting warnings to the end
of build, and sphinx-build exits with exit status 1.

So for the purpose of checking if there is *any* error in the
documentation this flag does not make a difference.

If we put the --keep-going flag into our Makefile, we require everybody
in the U-Boot community to upgrade his Sphinx installation if he wants
to run 'make htmldocs'. Is this what we want?

Our Dockerfile is based on ubuntu:bionic-20200112. You could move to
ubuntu:eoan-20200114 to get Sphinx 1.8.5.

Best regards

Heinrich

Re: [PATCH 1/2] doc/Makefile: turn warnings into errors

[Heinrich Schuchardt]

On 2/21/20 5:06 AM, Tom Rini wrote:

On Fri, Feb 21, 2020 at 04:26:36AM +0100, Heinrich Schuchardt wrote:


Several patches delivered incorrect restructured text as documentation. We
should be able to discover this in Travis CI or Gitlab CI.

So let us turn all build warnings into errors.

We cannot add --keep-going as Gitlab does not use sphinx-build version 1.8
or later yet.


Why can't we upgrade sphinx-build so that we then run these builds also
in Gitlab / Azure?  Thanks!


This is what --keep-going does:

With -W option, keep going processing when getting warnings to the end
of build, and sphinx-build exits with exit status 1.

So for the purpose of checking if there is *any* error in the
documentation this flag does not make a difference.

If we put the --keep-going flag into our Makefile, we require everybody
in the U-Boot community to upgrade his Sphinx installation if he wants
to run 'make htmldocs'. Is this what we want?

Our Dockerfile is based on ubuntu:bionic-20200112. You could move to
ubuntu:eoan-20200114 to get Sphinx 1.8.5.

Best regards

Heinrich

[PATCH 1/1] .dockerignore: remove .git/ from build context

[Heinrich Schuchardt]

We do not need .git in the build context.

Signed-off-by: Heinrich Schuchardt 
---
 .dockerignore | 2 ++
 1 file changed, 2 insertions(+)
 create mode 100644 .dockerignore

diff --git a/.dockerignore b/.dockerignore
new file mode 100644
index 000..bbaab15
--- /dev/null
+++ b/.dockerignore
@@ -0,0 +1,2 @@
+# ignore .git folder
+.git
--
2.25.0

Re: [PATCH 1/2] doc/Makefile: turn warnings into errors

[Tom Rini]

On Fri, Feb 21, 2020 at 04:26:36AM +0100, Heinrich Schuchardt wrote:

> Several patches delivered incorrect restructured text as documentation. We
> should be able to discover this in Travis CI or Gitlab CI.
> 
> So let us turn all build warnings into errors.
> 
> We cannot add --keep-going as Gitlab does not use sphinx-build version 1.8
> or later yet.

Why can't we upgrade sphinx-build so that we then run these builds also
in Gitlab / Azure?  Thanks!

-- 
Tom


signature.asc
Description: PGP signature

[PATCH 0/2] doc: build HTML docs in CI

[Heinrich Schuchardt]

We are on the move to a restructured text based documentation for U-Boot.
Build target htmldocs is used to transform the restructured text into
HTML. We should avoid syntax errors in the restructured text documents
that may lead to incorrect HTML.

This patch series turns the 'make htmldocs' warnings into errors and adds
build steps for 'make htmldocs' to Travis CI scripts.

I am still working on Gitlab. At least imagemagick (/usr/bin/convert) is
missing in our Docker image.

Heinrich Schuchardt (2):
  doc/Makefile: turn warnings into errors
  travis: build HTML docs

 .travis.yml  | 5 +
 doc/Makefile | 1 +
 2 files changed, 6 insertions(+)

--
2.25.0

[PATCH 2/2] travis: build HTML docs

[Heinrich Schuchardt]

Several patches delivered incorrect restructured text as documentation.
We should be able to discover this in Travis CI.

Provide a build step for 'make htmldocs'.

Add required package graphviz.

Signed-off-by: Heinrich Schuchardt 
---
 .travis.yml | 5 +
 1 file changed, 5 insertions(+)

diff --git a/.travis.yml b/.travis.yml
index e6db9d6a72..a5918dd5d9 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -38,6 +38,7 @@ addons:
 - libisl15
 - clang-7
 - srecord
+- graphviz

 install:
  # Clone uboot-test-hooks
@@ -360,6 +361,10 @@ matrix:
 - name: "grep FIXME HACK"
   script:
 - grep -r FIXME .
+# build HTML documentation
+- name: "htmldocs"
+  script:
+- make htmldocs
 # search for HACK within source tree and ignore HACKKIT board
   script:
 - grep -r HACK . | grep -v HACKKIT
--
2.25.0

[PATCH 1/2] doc/Makefile: turn warnings into errors

[Heinrich Schuchardt]

Several patches delivered incorrect restructured text as documentation. We
should be able to discover this in Travis CI or Gitlab CI.

So let us turn all build warnings into errors.

We cannot add --keep-going as Gitlab does not use sphinx-build version 1.8
or later yet.

Signed-off-by: Heinrich Schuchardt 
---
 doc/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/doc/Makefile b/doc/Makefile
index 5135a96e88..0e0da5666f 100644
--- a/doc/Makefile
+++ b/doc/Makefile
@@ -56,6 +56,7 @@ quiet_cmd_sphinx = SPHINX  $@ --> file://$(abspath 
$(BUILDDIR)/$3/$4)
PYTHONDONTWRITEBYTECODE=1 \
BUILDDIR=$(abspath $(BUILDDIR)) SPHINX_CONF=$(abspath 
$(srctree)/$(src)/$5/$(SPHINX_CONF)) \
$(SPHINXBUILD) \
+   -W \
-b $2 \
-c $(abspath $(srctree)/$(src)) \
-d $(abspath $(BUILDDIR)/.doctrees/$3) \
--
2.25.0

[PATCH 1/2] mmc: ca_dw_mmc: add DesignWare based DM support for CAxxxx SoCs

[Alex Nemirovsky]

From: Arthur Li 

Initial DesignWare based DM support for Cortina Access CA SoCs.

Signed-off-by: Arthur Li 
Signed-off-by: Alex Nemirovsky 
---

 MAINTAINERS |   2 +
 drivers/mmc/Kconfig |  11 +++
 drivers/mmc/Makefile|   1 +
 drivers/mmc/ca_dw_mmc.c | 181 
 4 files changed, 195 insertions(+)
 create mode 100644 drivers/mmc/ca_dw_mmc.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 82e4159..bb45d3c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -180,6 +180,7 @@ F:  board/cortina/common/
 F: drivers/gpio/cortina_gpio.c
 F: drivers/watchdog/cortina_wdt.c
 F: drivers/serial/serial_cortina.c
+F: drivers/mmc/ca_dw_mmc.c
 
 ARM/CZ.NIC TURRIS MOX SUPPORT
 M: Marek Behun 
@@ -670,6 +671,7 @@ F:  board/cortina/common/
 F: drivers/gpio/cortina_gpio.c
 F: drivers/watchdog/cortina_wdt.c
 F: drivers/serial/serial_cortina.c
+F: drivers/mmc/ca_dw_mmc.c
 
 MIPS MSCC
 M: Gregory CLEMENT 
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 2f0eedc..bb38787 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -205,6 +205,17 @@ config MMC_DW
  block, this provides host support for SD and MMC interfaces, in both
  PIO, internal DMA mode and external DMA mode.
 
+config MMC_DW_CORTINA
+   bool "Cortina specific extensions for Synopsys DW Memory Card Interface"
+   depends on DM_MMC
+   depends on MMC_DW
+   depends on BLK
+   default n
+   help
+ This selects support for Cortina SoC specific extensions to the
+ Synopsys DesignWare Memory Card Interface driver. Select this option
+ for platforms based on Cortina CA Soc's.
+
 config MMC_DW_EXYNOS
bool "Exynos specific extensions for Synopsys DW Memory Card Interface"
depends on ARCH_EXYNOS
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 9c1f8e5..615b724 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -20,6 +20,7 @@ endif
 obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
 obj-$(CONFIG_MMC_DAVINCI)  += davinci_mmc.o
 obj-$(CONFIG_MMC_DW)   += dw_mmc.o
+obj-$(CONFIG_MMC_DW_CORTINA)   += ca_dw_mmc.o
 obj-$(CONFIG_MMC_DW_EXYNOS)+= exynos_dw_mmc.o
 obj-$(CONFIG_MMC_DW_K3)+= hi6220_dw_mmc.o
 obj-$(CONFIG_MMC_DW_ROCKCHIP)  += rockchip_dw_mmc.o
diff --git a/drivers/mmc/ca_dw_mmc.c b/drivers/mmc/ca_dw_mmc.c
new file mode 100644
index 000..acbc850
--- /dev/null
+++ b/drivers/mmc/ca_dw_mmc.c
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Cortina Access
+ * Arthur Li 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SD_CLK_SEL_MASK (0x3)
+#define SD_DLL_DEFAULT  (0x143000)
+#define SD_SCLK_MAX (2)
+
+#define SD_CLK_SEL_200MHZ (0x2)
+#define SD_CLK_SEL_100MHZ (0x1)
+
+#define IO_DRV_SD_DS_OFFSET (16)
+#define IO_DRV_SD_DS_MASK   (0xff << IO_DRV_SD_DS_OFFSET)
+
+#define MIN_FREQ (40)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ca_mmc_plat {
+   struct mmc_config cfg;
+   struct mmc mmc;
+};
+
+struct ca_dwmmc_priv_data {
+   struct dwmci_host host;
+   void __iomem *sd_dll_reg;
+   void __iomem *io_drv_reg;
+   u8 ds;
+};
+
+static void ca_dwmci_clksel(struct dwmci_host *host)
+{
+   struct ca_dwmmc_priv_data *priv = host->priv;
+   u32 val = readl(priv->sd_dll_reg);
+
+   if (host->bus_hz >= 2) {
+   val &= ~SD_CLK_SEL_MASK;
+   val |= SD_CLK_SEL_200MHZ;
+   } else if (host->bus_hz >= 1) {
+   val &= ~SD_CLK_SEL_MASK;
+   val |= SD_CLK_SEL_100MHZ;
+   } else {
+   val &= ~SD_CLK_SEL_MASK;
+   }
+
+   writel(val, priv->sd_dll_reg);
+}
+
+static void ca_dwmci_board_init(struct dwmci_host *host)
+{
+   struct ca_dwmmc_priv_data *priv = host->priv;
+   u32 val = readl(priv->io_drv_reg);
+
+   writel(SD_DLL_DEFAULT, priv->sd_dll_reg);
+
+   val &= ~IO_DRV_SD_DS_MASK;
+   if (priv && priv->ds)
+   val |= priv->ds << IO_DRV_SD_DS_OFFSET;
+   writel(val, priv->io_drv_reg);
+}
+
+unsigned int ca_dwmci_get_mmc_clock(struct dwmci_host *host, uint freq)
+{
+   struct ca_dwmmc_priv_data *priv = host->priv;
+   u8 sd_clk_sel = readl(priv->sd_dll_reg) & SD_CLK_SEL_MASK;
+   u8 clk_div;
+
+   switch (sd_clk_sel) {
+   case 2:
+   clk_div = 1;
+   break;
+   case 1:
+   clk_div = 2;
+   break;
+   default:
+   clk_div = 4;
+   }
+
+   return SD_SCLK_MAX / clk_div / (host->div + 1);
+}
+
+static int ca_dwmmc_ofdata_to_platdata(struct udevice *dev)
+{
+   struct ca_dwmmc_priv_data *priv = dev_get_priv(dev);
+   struct dwmci_host *host = >host;
+   u32 tmp;
+
+   host->name = dev->name;
+   host->dev_index = 0;
+
+ 

[PATCH 2/2] board: presidio-asic: Add eMMC board support

[Alex Nemirovsky]

Add initial eMMC support for Cortina Access Presidio
Engineering Board

Signed-off-by: Alex Nemirovsky 
---

 configs/cortina_presidio-asic-emmc_defconfig | 33 
 1 file changed, 33 insertions(+)
 create mode 100644 configs/cortina_presidio-asic-emmc_defconfig

diff --git a/configs/cortina_presidio-asic-emmc_defconfig 
b/configs/cortina_presidio-asic-emmc_defconfig
new file mode 100644
index 000..e10008a
--- /dev/null
+++ b/configs/cortina_presidio-asic-emmc_defconfig
@@ -0,0 +1,33 @@
+CONFIG_ARM=y
+# CONFIG_SYS_ARCH_TIMER is not set
+CONFIG_TARGET_PRESIDIO_ASIC=y
+CONFIG_SYS_TEXT_BASE=0x0400
+CONFIG_ENV_SIZE=0x2
+CONFIG_DM_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_IDENT_STRING="Presidio-SoC"
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SYS_PROMPT="G3#"
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_SMC=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
+# CONFIG_NET is not set
+CONFIG_DM=y
+CONFIG_CORTINA_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_CORTINA=y
+CONFIG_DM_SERIAL=y
+CONFIG_CORTINA_UART=y
+CONFIG_WDT=y
+CONFIG_WDT_CORTINA=y
-- 
2.7.4

[PATCH] configs: socfpga: cyclone5: Enable CONFIG_NET_RANDOM_ETHADDR

[Ley Foon Tan]

Enable random ethaddr CONFIG_NET_RANDOM_ETHADDR for Cyclone 5.

Ethernet failed to work if ethaddr is empty when Ethernet driver is probed.
Setting ethaddr in Uboot command prompt can't solve this.
Enable random ethaddr to solve it.

Fix issue below:
=> setenv ethaddr 00:07:ed:00:64:04
=> setenv ethaddr1 00:07:ed:00:78:04
=> setenv ethaddr2 00:07:ed:00:8c:04
=> dhcp
mdio_register: non unique device name 'ethernet@ff702000'
mdio_register: non unique device name 'ethernet@ff702000'
mdio_register: non unique device name 'ethernet@ff702000'
mdio_register: non unique device name 'ethernet@ff702000'
No ethernet found.

Signed-off-by: Ley Foon Tan 
---
 configs/socfpga_cyclone5_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/socfpga_cyclone5_defconfig 
b/configs/socfpga_cyclone5_defconfig
index b6220e4ae8..9021703e38 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -37,6 +37,7 @@ CONFIG_CMD_UBI=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DWAPB_GPIO=y
-- 
2.19.0

[PATCH 2/2] configs: socfpga: Add QSPI boot for Arria 10 SoCDK

[Ley Foon Tan]

Add QSPI boot settings for Arria 10 SoCDK.

Signed-off-by: Ley Foon Tan 
---
 include/configs/socfpga_arria10_socdk.h | 9 +
 1 file changed, 9 insertions(+)

diff --git a/include/configs/socfpga_arria10_socdk.h 
b/include/configs/socfpga_arria10_socdk.h
index 645e66e6b0..e1d01c095f 100644
--- a/include/configs/socfpga_arria10_socdk.h
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -39,6 +39,15 @@
 /* SPL memory allocation configuration, this is for FAT implementation */
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000
 
+#define KERNEL_FIT_ADDR__stringify(0x120)
+
+#define SOCFPGA_BOOT_SETTINGS \
+   "kernelfit_addr=" KERNEL_FIT_ADDR "\0" \
+   "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+   "root=/dev/mtdblock1 rw rootfstype=jffs2;" \
+   "bootm ${scriptaddr}\0" \
+   "qspiload=sf probe; sf read ${scriptaddr} ${kernelfit_addr}\0" \
+
 /* The rest of the configuration is shared */
 #include 
 
-- 
2.19.0

[PATCH 1/2] configs: socfpga: Add QSPI support for Cyclone 5

[Ley Foon Tan]

Add QSPI boot support to boot target devices list.
Platform can provide their own boot settings through SOCFPGA_BOOT_SETTINGS
macro if needed.

Add SOCFPGA_BOOT_SETTINGS for Cyclone 5.

Signed-off-by: Ley Foon Tan 
---
 include/configs/socfpga_common.h | 18 ++
 include/configs/socfpga_cyclone5_socdk.h | 18 ++
 2 files changed, 36 insertions(+)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 8d10469e7c..f3ddfca289 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -228,11 +228,28 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define BOOT_TARGET_DEVICES_MMC(func)
 #endif
 
+#ifdef CONFIG_CMD_SF
+#define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na)
+#else
+#define BOOT_TARGET_DEVICES_QSPI(func)
+#endif
+
+#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
+   "bootcmd_qspi=run qspiload; run qspiboot\0"
+
+#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
+   "qspi "
+
 #define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_DEVICES_MMC(func) \
+   BOOT_TARGET_DEVICES_QSPI(func) \
BOOT_TARGET_DEVICES_PXE(func) \
BOOT_TARGET_DEVICES_DHCP(func)
 
+#ifndef SOCFPGA_BOOT_SETTINGS
+#define SOCFPGA_BOOT_SETTINGS
+#endif
+
 #include 
 
 #ifndef CONFIG_EXTRA_ENV_SETTINGS
@@ -245,6 +262,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
"pxefile_addr_r=0x0220\0" \
"ramdisk_addr_r=0x0230\0" \
"socfpga_legacy_reset_compat=1\0" \
+   SOCFPGA_BOOT_SETTINGS \
BOOTENV
 
 #endif
diff --git a/include/configs/socfpga_cyclone5_socdk.h 
b/include/configs/socfpga_cyclone5_socdk.h
index 028db2a09e..62ad001c4b 100644
--- a/include/configs/socfpga_cyclone5_socdk.h
+++ b/include/configs/socfpga_cyclone5_socdk.h
@@ -14,6 +14,24 @@
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
+/* QSPI boot */
+#define FDT_SIZE   __stringify(0x0001)
+#define KERNEL_SIZE__stringify(0x005d)
+#define QSPI_FDT_ADDR  __stringify(0x0022)
+#define QSPI_KERNEL_ADDR   __stringify(0x0023)
+
+#define SOCFPGA_BOOT_SETTINGS \
+   "fdt_size=" FDT_SIZE "\0" \
+   "kernel_size=" KERNEL_SIZE "\0" \
+   "qspi_fdt_addr=" QSPI_FDT_ADDR "\0" \
+   "qspi_kernel_addr=" QSPI_KERNEL_ADDR "\0" \
+   "qspiboot=setenv bootargs earlycon " \
+   "root=/dev/mtdblock1 rw rootfstype=jffs2; " \
+   "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+   "qspiload=sf probe; " \
+   "sf read ${kernel_addr_r} ${qspi_kernel_addr} ${kernel_size}; " 
\
+   "sf read ${fdt_addr_r} ${qspi_fdt_addr} ${fdt_size}\0"
+
 /* The rest of the configuration is shared */
 #include 
 
-- 
2.19.0

Pull request: u-boot-rockchip-20200220

[Kever Yang]

Hi Tom,

Please pull the rockchip updates/fixes:
- rk3399: split roc-pc-rk3399 out of evb_rk3399
- sync dts from upstream kernel for rk3399,rk3288,px30
- boot_mode: find the saradc device name

Travis:
https://travis-ci.org/keveryang/u-boot/builds/652785865

Thanks,
- Kever

The following changes since commit f2a73d6867ef973fbb8471cc87058205999b5e5c:

  Merge tag 'u-boot-stm32-20200214' of 
https://gitlab.denx.de/u-boot/custodians/u-boot-stm (2020-02-14 07:31:47 -0500)

are available in the Git repository at:

  https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip.git 
tags/u-boot-rockchip-20200220

for you to fetch changes up to f9561d8e3671415c7780df4b5e70f0f1e2d2bf57:

  arch: arm: rockchip: order the rk3399 entries alphabetically (2020-02-20 
09:18:14 +0800)


Heiko Stuebner (3):
  rockchip: make_fit_atf: use correct fdt_x references in config nodes
  rockchip: make the global board_fit_config_name_match __weak
  rockchip: px30: sync the main px30 dtsi from mainline

Hugh Cole-Baker (1):
  rockchip: boot_mode: find the saradc device name

Jagan Teki (4):
  rockchip: rk3288: Enable pre console buffer
  ARM: dts: rockchip: Sync rk3288-vyasa dts from linux
  rk3288: tinker: Enable HDMI output
  rk3288: vyasa: Add console settings

Jared Baldridge (1):
  configs: fix typos in khadas-edge defconfigs

Kever Yang (1):
  rockchip: rk3399: add target type for evb based board

Peter Robinson (4):
  arm: dts: rockchip: Update EVB/Puma devices to upstream USB/dwc3 
conventions
  arm: dts: rockchip: rk3399: Move U-Boot specific bits to rk3399-u-boot
  arm: dts: rockchip: puma: move U-Boot specific bits to u-boot.dtsi
  arch: arm: rockchip: order the rk3399 entries alphabetically

Suniel Mahesh (2):
  rockchip: rk3399: split roc-pc-rk3399 out of evb_rk3399
  board: roc-pc-rk3399: Add support for onboard LED's and push button to 
indicate power mode

 arch/arm/dts/px30.dtsi   | 182 +--
 arch/arm/dts/rk3288-vyasa.dts|  79 +---
 arch/arm/dts/rk3399-evb.dts  |   4 +-
 arch/arm/dts/rk3399-puma-ddr1333-u-boot.dtsi |   4 +
 arch/arm/dts/rk3399-puma-ddr1333.dts |   2 -
 arch/arm/dts/rk3399-puma-ddr1600-u-boot.dtsi |   4 +
 arch/arm/dts/rk3399-puma-ddr1600.dts |   2 -
 arch/arm/dts/rk3399-puma-ddr1866-u-boot.dtsi |   4 +
 arch/arm/dts/rk3399-puma-ddr1866.dts |   2 -
 arch/arm/dts/rk3399-puma-u-boot.dtsi |  24 
 arch/arm/dts/rk3399-puma.dtsi|  23 +---
 arch/arm/dts/rk3399-u-boot.dtsi  |  55 ++--
 arch/arm/dts/rk3399.dtsi |  38 --
 arch/arm/mach-rockchip/Kconfig   |   1 +
 arch/arm/mach-rockchip/boot_mode.c   |  22 +++-
 arch/arm/mach-rockchip/make_fit_atf.py   |   2 +-
 arch/arm/mach-rockchip/rk3399/Kconfig|  42 +--
 arch/arm/mach-rockchip/spl.c |   2 +-
 arch/arm/mach-rockchip/tpl.c |   7 ++
 board/firefly/roc-pc-rk3399/Kconfig  |  16 +++
 board/firefly/roc-pc-rk3399/MAINTAINERS  |   6 +
 board/firefly/roc-pc-rk3399/Makefile |   7 ++
 board/firefly/roc-pc-rk3399/roc-pc-rk3399.c  |  61 +
 board/rockchip/evb_rk3399/MAINTAINERS|   6 -
 common/Kconfig   |   1 +
 configs/evb-rk3399_defconfig |   1 +
 configs/firefly-rk3399_defconfig |   1 +
 configs/khadas-edge-captain-rk3399_defconfig |   3 +-
 configs/khadas-edge-rk3399_defconfig |   1 +
 configs/khadas-edge-v-rk3399_defconfig   |   3 +-
 configs/leez-rk3399_defconfig|   1 +
 configs/nanopc-t4-rk3399_defconfig   |   1 +
 configs/nanopi-m4-rk3399_defconfig   |   1 +
 configs/nanopi-neo4-rk3399_defconfig |   1 +
 configs/orangepi-rk3399_defconfig|   1 +
 configs/roc-pc-rk3399_defconfig  |   2 +
 configs/rock-pi-4-rk3399_defconfig   |   1 +
 configs/tinker-rk3288_defconfig  |   6 +
 include/configs/roc-pc-rk3399.h  |  22 
 include/configs/tinker_rk3288.h  |   6 +-
 include/configs/vyasa-rk3288.h   |   6 +-
 41 files changed, 494 insertions(+), 159 deletions(-)
 create mode 100644 arch/arm/dts/rk3399-puma-ddr1333-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3399-puma-ddr1600-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3399-puma-ddr1866-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3399-puma-u-boot.dtsi
 create mode 100644 board/firefly/roc-pc-rk3399/Kconfig
 create mode 100644 board/firefly/roc-pc-rk3399/MAINTAINERS
 create mode 100644 board/firefly/roc-pc-rk3399/Makefile
 create mode 100644 board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
 create mode 100644 include/configs/roc-pc-rk3399.h

Re: [PATCH 0/3] Remove CONFIG_MMC_BROKEN_CD

[Jaehoon Chung]

Hi Tom,

On 2/21/20 4:57 AM, Tom Rini wrote:
> On Thu, Feb 20, 2020 at 01:45:31PM +0900, Jaehoon Chung wrote:
> 
>> CONFIG_MMC_BROKEN_CD needs not to define to Kconfig.
>> broken-cd is already provide to dt-property.
>> If want to poll card-detect, set to broken-cd instead of enabling 
>> CONFIG_MMC_BROKEN_CD.
>>
>> When checked the boards that is eabled CONFIG_MMC_BROKEN_CD,
>> it also used the value of dt as broken-cd.
>>
>> Jaehoon Chung (3):
>>   mmc: jz_mmc; add MMC_CAP_NEEDS_POLL by default
>>   mmc: check the flags of host_caps about broken-cd
>>   mmc: Kconfig: remove MMC_BROKEN_CD configuration
>>
>>  configs/brppt2_defconfig|  1 -
>>  configs/ci20_mmc_defconfig  |  1 -
>>  configs/meerkat96_defconfig |  1 -
>>  drivers/mmc/Kconfig |  5 -
>>  drivers/mmc/jz_mmc.c|  6 --
>>  drivers/mmc/mmc.c   | 10 +-
>>  6 files changed, 9 insertions(+), 15 deletions(-)
> 
> Did you size-test this change?  ci20 is extremely tight on space.

I didn't check size-test about this. Is there any check-tool?
If there is check-tool, let me know, plz. Then i will check it. (In future, I 
will check before sending patch.)
I just checked this patch with CI.

Best Regards,
Jaehoon Chung

> 

Re: [PATCH] bootcounter: add DM support for memory based bootcounter

[Simon Glass]

Hi Heiko,

On Thu, 20 Feb 2020 at 02:28, Heiko Schocher  wrote:
>
> add DM/DTS support for the memory based bootcounter
> in drivers/bootcount/bootcount.c.
>
> Let the old implementation in, so boards which have
> not yet convert to DM/DTS do not break.
>
> Signed-off-by: Heiko Schocher 
> ---
> Travis build:
>
> https://travis-ci.org/hsdenx/u-boot-test/builds/652839618
>
>  doc/device-tree-bindings/misc/bootcounter.txt | 21 +
>  drivers/bootcount/Kconfig |  5 ++
>  drivers/bootcount/Makefile|  1 +
>  drivers/bootcount/bootcount.c | 86 +++
>  4 files changed, 113 insertions(+)
>  create mode 100644 doc/device-tree-bindings/misc/bootcounter.txt
>
> diff --git a/doc/device-tree-bindings/misc/bootcounter.txt 
> b/doc/device-tree-bindings/misc/bootcounter.txt
> new file mode 100644
> index 00..f4a4a731b9
> --- /dev/null
> +++ b/doc/device-tree-bindings/misc/bootcounter.txt
> @@ -0,0 +1,21 @@
> +U-Boot bootcounter Devicetree Binding
> +=
> +
> +The device tree node describes the U-Boot bootcounter
> +memory based device binding.
> +
> +Required properties :
> +
> +- compatible : "uboot,bootcount";

I think we use u-boot in other bindings

> +- singleword : set this, if you have only one word space
> +for storing the bootcounter.

single-word

I think this is a boolean property, right?

What is a word? Is it 32 bits? Also, what does it actually mean/do?

> +
> +Example
> +---
> +
> +MPC83xx based board:
> +
> +bootcount@0x13ff8 {
> +   compatible = "uboot,bootcount";
> +   reg = <0x13ff8 0x08>;
> +};
> diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig
> index 0e506c9ea2..88203607a8 100644
> --- a/drivers/bootcount/Kconfig
> +++ b/drivers/bootcount/Kconfig
> @@ -106,6 +106,11 @@ config DM_BOOTCOUNT_I2C_EEPROM
>   pointing to the underlying i2c eeprom device) and an optional 
> 'offset'
>   property are supported.
>
> +config BOOTCOUNT_MEM
> +   bool "memory based bootcounter"
> +   help
> + Memory based bootcount, compatible = "uboot,bootcount";
> +
>  endmenu
>
>  endif
> diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile
> index 73ccfb5a08..059d40d16b 100644
> --- a/drivers/bootcount/Makefile
> +++ b/drivers/bootcount/Makefile
> @@ -1,6 +1,7 @@
>  # SPDX-License-Identifier: GPL-2.0+
>
>  obj-$(CONFIG_BOOTCOUNT_GENERIC)+= bootcount.o
> +obj-$(CONFIG_BOOTCOUNT_MEM)+= bootcount.o
>  obj-$(CONFIG_BOOTCOUNT_AT91)   += bootcount_at91.o
>  obj-$(CONFIG_BOOTCOUNT_AM33XX) += bootcount_davinci.o
>  obj-$(CONFIG_BOOTCOUNT_RAM)+= bootcount_ram.o
> diff --git a/drivers/bootcount/bootcount.c b/drivers/bootcount/bootcount.c
> index 7a6d03dcca..53bd416cf6 100644
> --- a/drivers/bootcount/bootcount.c
> +++ b/drivers/bootcount/bootcount.c
> @@ -8,6 +8,7 @@
>  #include 
>  #include 
>
> +#if !defined(CONFIG_DM_BOOTCOUNT)
>  /* Now implement the generic default functions */
>  __weak void bootcount_store(ulong a)
>  {
> @@ -49,3 +50,88 @@ __weak ulong bootcount_load(void)
> return raw_bootcount_load(reg);
>  #endif /* defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD) */
>  }
> +#else
> +#include 
> +

Comment for struct

> +struct bootcount_mem_priv {
> +   phys_addr_t base;
> +   u8 singleword;

bool?
> +};
> +
> +static int bootcount_mem_get(struct udevice *dev, u32 *a)
> +{
> +   struct bootcount_mem_priv *priv = dev_get_priv(dev);
> +   void *reg = (void *)priv->base;
> +   u32 magic = CONFIG_SYS_BOOTCOUNT_MAGIC;
> +
> +   if (priv->singleword) {
> +   u32 tmp = raw_bootcount_load(reg);
> +
> +   if ((tmp & 0x) != (magic & 0x))
> +   return -ENODEV;
> +
> +   *a = (tmp & 0x);
> +   } else {
> +   if (raw_bootcount_load(reg + 4) != magic)
> +   return -ENODEV;
> +
> +   *a = raw_bootcount_load(reg);
> +   }
> +
> +   return 0;
> +};
> +
> +static int bootcount_mem_set(struct udevice *dev, const u32 a)
> +{
> +   struct bootcount_mem_priv *priv = dev_get_priv(dev);
> +   void *reg = (void *)priv->base;
> +   u32 magic = CONFIG_SYS_BOOTCOUNT_MAGIC;
> +   uintptr_t flush_start = rounddown(priv->base,
> + CONFIG_SYS_CACHELINE_SIZE);
> +   uintptr_t flush_end;
> +
> +   if (priv->singleword) {
> +   raw_bootcount_store(reg, (magic & 0x) | a);
> +   flush_end = roundup(priv->base + 4,
> +   CONFIG_SYS_CACHELINE_SIZE);
> +   } else {
> +   raw_bootcount_store(reg, a);
> +   raw_bootcount_store(reg + 4, magic);
> +   flush_end = roundup(priv->base + 8,
> +   CONFIG_SYS_CACHELINE_SIZE);
> +   }
> +   flush_dcache_range(flush_start, flush_end);
> +
> +   

Re: [PATCH 5/5] Add support for i.MXRT1020-EVK board

[Lukasz Majewski]

On Tue, 18 Feb 2020 20:02:55 +0100
Giulio Benetti  wrote:

> Signed-off-by: Giulio Benetti 
> ---
>  arch/arm/dts/Makefile |   3 +-
>  arch/arm/dts/imxrt1020-evk-u-boot.dtsi|  44 
>  arch/arm/dts/imxrt1020-evk.dts| 198
> ++ arch/arm/mach-imx/imxrt/Kconfig   |
> 5 + board/freescale/imxrt1020-evk/Kconfig |  22 ++
>  board/freescale/imxrt1020-evk/MAINTAINERS |   6 +
>  board/freescale/imxrt1020-evk/Makefile|   6 +
>  board/freescale/imxrt1020-evk/README  |  31 +++
>  board/freescale/imxrt1020-evk/imximage.cfg|  36 
>  board/freescale/imxrt1020-evk/imxrt1020-evk.c |  81 +++
>  configs/imxrt1020-evk_defconfig   |  67 ++
>  include/configs/imxrt1020-evk.h   |  46 
>  12 files changed, 544 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/imxrt1020-evk-u-boot.dtsi
>  create mode 100644 arch/arm/dts/imxrt1020-evk.dts
>  create mode 100644 board/freescale/imxrt1020-evk/Kconfig
>  create mode 100644 board/freescale/imxrt1020-evk/MAINTAINERS
>  create mode 100644 board/freescale/imxrt1020-evk/Makefile
>  create mode 100644 board/freescale/imxrt1020-evk/README
>  create mode 100644 board/freescale/imxrt1020-evk/imximage.cfg
>  create mode 100644 board/freescale/imxrt1020-evk/imxrt1020-evk.c
>  create mode 100644 configs/imxrt1020-evk_defconfig
>  create mode 100644 include/configs/imxrt1020-evk.h
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index be4cf029d0..1116c44cf4 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -723,7 +723,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
>   imx8mq-evk.dtb \
>   imx8mp-evk.dtb
>  
> -dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb
> +dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
> + imxrt1020-evk.dtb
>  
>  dtb-$(CONFIG_RCAR_GEN2) += \
>   r8a7790-lager-u-boot.dtb \
> diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
> b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi new file mode 100644
> index 00..d32c98de9c
> --- /dev/null
> +++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) 2020
> + * Author(s): Giulio Benetti 
> + */
> +
> +/ {
> + chosen {
> + u-boot,dm-spl;
> + };
> +};
> +
> + { /* console */
> + u-boot,dm-spl;
> +};
> +
> + {
> + bank1: bank@0 {
> + u-boot,dm-spl;
> + };
> +};
> +
> + {
> + u-boot,dm-spl;
> +
> + imxrt1020-evk {
> + u-boot,dm-spl;
> + pinctrl_lpuart1: lpuart1grp {
> + u-boot,dm-spl;
> + };
> +
> + pinctrl_semc: semcgrp {
> + u-boot,dm-spl;
> + };
> +
> + pinctrl_usdhc0: usdhc0grp {
> + u-boot,dm-spl;
> + };
> + };
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> diff --git a/arch/arm/dts/imxrt1020-evk.dts
> b/arch/arm/dts/imxrt1020-evk.dts new file mode 100644
> index 00..ece13601bd
> --- /dev/null
> +++ b/arch/arm/dts/imxrt1020-evk.dts
> @@ -0,0 +1,198 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) 2020
> + * Author(s): Giulio Benetti 
> + */
> +
> +/dts-v1/;
> +#include "imxrt1020.dtsi"
> +#include "imxrt1020-evk-u-boot.dtsi"
> +#include 
> +
> +/ {
> + model = "NXP IMXRT1020-evk board";
> + compatible = "fsl,imxrt1020-evk", "fsl,imxrt1020";
> +
> + chosen {
> + bootargs = "root=/dev/ram";
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory {
> + reg = <0x8000 0x200>;
> + };
> +};
> +
> + { /* console */
> + pinctrl-names = "default";
> + pinctrl-0 = <_lpuart1>;
> + status = "okay";
> +};
> +
> + {
> + /*
> +  * Memory configuration from sdram datasheet IS42S16160J-6TLI
> +  */
> + fsl,sdram-mux = /bits/ 8  + MUX_CSX0_SDRAM_CS1
> + 0
> + 0
> + 0
> + 0>;
> + fsl,sdram-control = /bits/ 8  + BL_8
> + COL_9BITS
> + CL_3>;
> + fsl,sdram-timing = /bits/ 8 <0x2
> +  0x2
> +  0x9
> +  0x1
> +  0x5
> +  0x6
> +
> +  0x20
> +  0x09
> +  0x01
> +  0x00
> +
> +  0x04
> +  0x0A
> +  0x21
> +  0x50>;
> +
> + bank1: bank@0 {
> + 

Re: [PATCH 4/5] dt-bindings: pinctrl: add i.MXRT1020 pins definition

[Giulio Benetti]

Hi Lukasz,

On 2/20/20 11:51 PM, Lukasz Majewski wrote:

On Tue, 18 Feb 2020 20:02:54 +0100
Giulio Benetti  wrote:


Add i.MXRT1020 pins definition.


Are those definitions ported from Linux kernel?


No, this is the first implementation for U-Boot, I'll do it for Linux later.

Best regards
--
Giulio Benetti
Benetti Engineering sas



Signed-off-by: Giulio Benetti 
---
  include/dt-bindings/pinctrl/pins-imxrt1020.h | 763
+++ 1 file changed, 763 insertions(+)
  create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1020.h

diff --git a/include/dt-bindings/pinctrl/pins-imxrt1020.h
b/include/dt-bindings/pinctrl/pins-imxrt1020.h new file mode 100644
index 00..c6bacb7378
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pins-imxrt1020.h
@@ -0,0 +1,763 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020
+ * Author(s): Giulio Benetti 
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H
+#define _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H
+
+/* TODO: continue from LPI2C4_SDA_SELECT_INPUT */
+
+#define IMX_PAD_SION   0x4000
+
+/*
+ * The pin function ID is a tuple of
+ * 
+ */
+
+#define MXRT1020_IOMUXC_GPIO_EMC_00_SEMC_DA00
0x014 0x188 0x000 0x0 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_00_QTIMER2_TIMER0
0x014 0x188 0x420 0x1 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_00_LPUART4_CTS_B
0x014 0x188 0x3E0 0x2 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_00_SPDIF_SR_CLK0x014
0x188 0x000 0x3 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_00_LPSPI2_SCK
0x014 0x188 0x3B0 0x4 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_00_GPIO2_IO00
0x014 0x188 0x000 0x5 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_00_FLEXCAN1_TX
0x014 0x188 0x000 0x6 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_00_PIT_TRIGGER02
0x014 0x188 0x000 0x7 0x0 + +#define
MXRT1020_IOMUXC_GPIO_EMC_01_SEMC_DA01
0x018 0x18C 0x000 0x0 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_01_QTIMER2_TIMER1
0x018 0x18C 0x424 0x1 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_01_LPUART4_RTS_B
0x018 0x18C 0x000 0x2 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_01_SPDIF_OUT
0x018 0x18C 0x000 0x3 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0
0x018 0x18C 0x3AC 0x4 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_01_GPIO2_IO01
0x018 0x18C 0x000 0x5 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_01_FLEXCAN1_RX
0x018 0x18C 0x320 0x6 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_01_PIT_TRIGGER03
0x018 0x18C 0x000 0x7 0x0 + +#define
MXRT1020_IOMUXC_GPIO_EMC_02_SEMC_DA02
0x01C 0x190 0x000 0x0 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_02_QTIMER2_TIMER2
0x01C 0x190 0x428 0x1 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_02_LPUART4_TX
0x01C 0x190 0x3E8 0x2 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_02_SPDIF_LOCK
0x01C 0x190 0x000 0x3 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_02_LPSPI2_SDO
0x01C 0x190 0x3B8 0x4 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_02_GPIO2_IO02
0x01C 0x190 0x000 0x5 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_02_LPI2C1_SCL
0x01C 0x190 0x37C 0x6 0x0 + +#define
MXRT1020_IOMUXC_GPIO_EMC_03_SEMC_DA03
0x020 0x194 0x000 0x0 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_03_QTIMER2_TIMER3
0x020 0x194 0x42C 0x1 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_03_LPUART4_RX
0x020 0x194 0x3E4 0x2 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_03_SPDIF_EXT_CLK
0x020 0x194 0x000 0x3 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_03_LPSPI2_SDI
0x020 0x194 0x3B4 0x4 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_03_GPIO2_IO03
0x020 0x194 0x000 0x5 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_03_LPI2C1_SDA
0x020 0x194 0x380 0x6 0x1 + +#define
MXRT1020_IOMUXC_GPIO_EMC_04_SEMC_DA04
0x024 0x198 0x000 0x0 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_04_XBAR1_INOUT04
0x024 0x198 0x000 0x1 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_04_SPDIF_OUT
0x024 0x198 0x000 0x2 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK0x024
0x198 0x464 0x3 0x1 +#define
MXRT1020_IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16
0x024 0x198 0x000 0x4 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_04_GPIO2_IO04
0x024 0x198 0x000 0x5 0x0 + +#define
MXRT1020_IOMUXC_GPIO_EMC_05_SEMC_DA05
0x028 0x19C 0x000 0x0 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_05_XBAR1_INOUT05
0x028 0x19C 0x000 0x1 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_05_SPDIF_IN
0x028 0x19C 0x488 0x2 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC0x028
0x19C 0x468 0x3 0x1 +#define
MXRT1020_IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17
0x028 0x19C 0x000 0x4 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_05_GPIO2_IO05
0x028 0x19C 0x000 0x5 0x0 + +#define
MXRT1020_IOMUXC_GPIO_EMC_06_SEMC_DA06
0x02C 0x1A0 0x000 0x0 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_06_XBAR1_INOUT06
0x02C 0x1A0 0x000 0x1 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_06_LPUART3_TX
0x02C 0x1A0 0x3DC 0x2 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_06_SAI2_TX_DATA0x02C
0x1A0 0x000 0x3 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18
0x02C 0x1A0 0x000 0x4 0x0 +#define
MXRT1020_IOMUXC_GPIO_EMC_06_GPIO2_IO06
0x02C 0x1A0 0x000 0x5 0x0 + +#define
MXRT1020_IOMUXC_GPIO_EMC_07_SEMC_DA07
0x030 0x1A4 0x000 0x0 0x0 +#define

Re: [PATCH 4/5] dt-bindings: pinctrl: add i.MXRT1020 pins definition

[Lukasz Majewski]

On Tue, 18 Feb 2020 20:02:54 +0100
Giulio Benetti  wrote:

> Add i.MXRT1020 pins definition.

Are those definitions ported from Linux kernel?

> 
> Signed-off-by: Giulio Benetti 
> ---
>  include/dt-bindings/pinctrl/pins-imxrt1020.h | 763
> +++ 1 file changed, 763 insertions(+)
>  create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1020.h
> 
> diff --git a/include/dt-bindings/pinctrl/pins-imxrt1020.h
> b/include/dt-bindings/pinctrl/pins-imxrt1020.h new file mode 100644
> index 00..c6bacb7378
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/pins-imxrt1020.h
> @@ -0,0 +1,763 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2020
> + * Author(s): Giulio Benetti 
> + */
> +
> +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H
> +#define _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H
> +
> +/* TODO: continue from LPI2C4_SDA_SELECT_INPUT */
> +
> +#define IMX_PAD_SION 0x4000
> +
> +/*
> + * The pin function ID is a tuple of
> + * 
> + */
> +
> +#define MXRT1020_IOMUXC_GPIO_EMC_00_SEMC_DA00
>   0x014 0x188 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_00_QTIMER2_TIMER0
> 0x014 0x188 0x420 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_00_LPUART4_CTS_B
> 0x014 0x188 0x3E0 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_00_SPDIF_SR_CLK  0x014
> 0x188 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_00_LPSPI2_SCK
> 0x014 0x188 0x3B0 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_00_GPIO2_IO00
> 0x014 0x188 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_00_FLEXCAN1_TX
>   0x014 0x188 0x000 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_00_PIT_TRIGGER02
> 0x014 0x188 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_01_SEMC_DA01
> 0x018 0x18C 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_01_QTIMER2_TIMER1
> 0x018 0x18C 0x424 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_01_LPUART4_RTS_B
> 0x018 0x18C 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_01_SPDIF_OUT
> 0x018 0x18C 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0
>   0x018 0x18C 0x3AC 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_01_GPIO2_IO01
> 0x018 0x18C 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_01_FLEXCAN1_RX
>   0x018 0x18C 0x320 0x6 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_01_PIT_TRIGGER03
> 0x018 0x18C 0x000 0x7 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_02_SEMC_DA02
> 0x01C 0x190 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_02_QTIMER2_TIMER2
> 0x01C 0x190 0x428 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_02_LPUART4_TX
> 0x01C 0x190 0x3E8 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_02_SPDIF_LOCK
> 0x01C 0x190 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_02_LPSPI2_SDO
> 0x01C 0x190 0x3B8 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_02_GPIO2_IO02
> 0x01C 0x190 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_02_LPI2C1_SCL
> 0x01C 0x190 0x37C 0x6 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_03_SEMC_DA03
> 0x020 0x194 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_03_QTIMER2_TIMER3
> 0x020 0x194 0x42C 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_03_LPUART4_RX
> 0x020 0x194 0x3E4 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_03_SPDIF_EXT_CLK
> 0x020 0x194 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_03_LPSPI2_SDI
> 0x020 0x194 0x3B4 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_03_GPIO2_IO03
> 0x020 0x194 0x000 0x5 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_03_LPI2C1_SDA
> 0x020 0x194 0x380 0x6 0x1 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_04_SEMC_DA04
> 0x024 0x198 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_04_XBAR1_INOUT04
> 0x024 0x198 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_04_SPDIF_OUT
> 0x024 0x198 0x000 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_04_SAI2_TX_BCLK  0x024
> 0x198 0x464 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO16
> 0x024 0x198 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_04_GPIO2_IO04
> 0x024 0x198 0x000 0x5 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_05_SEMC_DA05
> 0x028 0x19C 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_05_XBAR1_INOUT05
> 0x028 0x19C 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_05_SPDIF_IN
> 0x028 0x19C 0x488 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC  0x028
> 0x19C 0x468 0x3 0x1 +#define
> MXRT1020_IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO17
> 0x028 0x19C 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_05_GPIO2_IO05
> 0x028 0x19C 0x000 0x5 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_06_SEMC_DA06
> 0x02C 0x1A0 0x000 0x0 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_06_XBAR1_INOUT06
> 0x02C 0x1A0 0x000 0x1 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_06_LPUART3_TX
> 0x02C 0x1A0 0x3DC 0x2 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_06_SAI2_TX_DATA  0x02C
> 0x1A0 0x000 0x3 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO18
> 0x02C 0x1A0 0x000 0x4 0x0 +#define
> MXRT1020_IOMUXC_GPIO_EMC_06_GPIO2_IO06
> 0x02C 0x1A0 0x000 0x5 0x0 + +#define
> MXRT1020_IOMUXC_GPIO_EMC_07_SEMC_DA07
> 0x030 0x1A4 0x000 0x0 

Re: [PATCH 3/5] ARM: dts: imxrt1020: add dtsi file

[Giulio Benetti]

Hi Lukasz,

On 2/20/20 11:45 PM, Lukasz Majewski wrote:

Hi Giulio,


Add dtsi file for i.MXRT1020.



Has this file been ported from Linux kernel? Or is it only available in
U-Boot?


Only available in U-Boot at the moment.

And thank you for reviewing!

Best regards
--
Giulio Benetti
Benetti Engineering sas


Reviewed-by: Lukasz Majewski 


Signed-off-by: Giulio Benetti 
---
  arch/arm/dts/imxrt1020.dtsi | 133
 1 file changed, 133 insertions(+)
  create mode 100644 arch/arm/dts/imxrt1020.dtsi

diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi
new file mode 100644
index 00..97f3cec9f3
--- /dev/null
+++ b/arch/arm/dts/imxrt1020.dtsi
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020
+ * Author(s): Giulio Benetti 
+ */
+
+#include "armv7-m.dtsi"
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   aliases {
+   gpio0 = 
+   gpio1 = 
+   gpio2 = 
+   mmc0 = 
+   serial0 = 
+   };
+
+   clocks {
+   u-boot,dm-spl;
+   ckil {
+   compatible = "fsl,imx-ckil", "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   };
+
+   ckih1 {
+   compatible = "fsl,imx-ckih1", "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   osc {
+   u-boot,dm-spl;
+   compatible = "fsl,imx-osc", "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <2400>;
+   };
+   };
+
+   soc {
+   u-boot,dm-spl;
+
+   semc: semc@402f {
+   u-boot,dm-spl;
+   compatible = "fsl,imxrt-semc";
+   reg = <0x402f 0x4000>;
+   clocks = < IMXRT1020_CLK_SEMC>;
+   pinctrl-0 = <_semc>;
+   pinctrl-names = "default";
+   status = "okay";
+   };
+
+   lpuart1: serial@40184000 {
+   compatible = "fsl,imxrt-lpuart";
+   reg = <0x40184000 0x4000>;
+   interrupts = ;
+   clocks = < IMXRT1020_CLK_LPUART1>;
+   clock-names = "per";
+   status = "disabled";
+   };
+
+   iomuxc: iomuxc@401f8000 {
+   compatible = "fsl,imxrt-iomuxc";
+   reg = <0x401f8000 0x4000>;
+   fsl,mux_mask = <0x7>;
+   };
+
+   clks: ccm@400fc000 {
+   u-boot,dm-spl;
+   compatible = "fsl,imxrt1020-ccm";
+   reg = <0x400fc000 0x4000>;
+   interrupts = ,
+;
+   #clock-cells = <1>;
+   };
+
+   usdhc1: usdhc@402c {
+   u-boot,dm-spl;
+   compatible = "fsl,imxrt-usdhc";
+   reg = <0x402c 0x1>;
+   interrupts = ;
+   clocks = < IMXRT1020_CLK_USDHC1>;
+   clock-names = "per";
+   bus-width = <4>;
+   fsl,tuning-start-tap = <20>;
+   fsl,tuning-step= <2>;
+   status = "disabled";
+   };
+
+   gpio1: gpio@401b8000 {
+   u-boot,dm-spl;
+   compatible = "fsl,imxrt-gpio",
"fsl,imx35-gpio";
+   reg = <0x401b8000 0x4000>;
+   interrupts = ,
+;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   };
+
+   gpio2: gpio@401bc000 {
+   u-boot,dm-spl;
+   compatible = "fsl,imxrt-gpio",
"fsl,imx35-gpio";
+   reg = <0x401bc000 0x4000>;
+   interrupts = ,
+   ;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   };
+
+   gpio3: gpio@401c {
+   u-boot,dm-spl;
+   compatible = "fsl,imxrt-gpio",
"fsl,imx35-gpio";
+   reg = <0x401c 0x4000>;
+   interrupts = ,
+   ;
+   

Re: [PATCH 3/5] ARM: dts: imxrt1020: add dtsi file

[Lukasz Majewski]

Hi Giulio,

> Add dtsi file for i.MXRT1020.
> 

Has this file been ported from Linux kernel? Or is it only available in
U-Boot?

Reviewed-by: Lukasz Majewski 

> Signed-off-by: Giulio Benetti 
> ---
>  arch/arm/dts/imxrt1020.dtsi | 133
>  1 file changed, 133 insertions(+)
>  create mode 100644 arch/arm/dts/imxrt1020.dtsi
> 
> diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi
> new file mode 100644
> index 00..97f3cec9f3
> --- /dev/null
> +++ b/arch/arm/dts/imxrt1020.dtsi
> @@ -0,0 +1,133 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) 2020
> + * Author(s): Giulio Benetti 
> + */
> +
> +#include "armv7-m.dtsi"
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + aliases {
> + gpio0 = 
> + gpio1 = 
> + gpio2 = 
> + mmc0 = 
> + serial0 = 
> + };
> +
> + clocks {
> + u-boot,dm-spl;
> + ckil {
> + compatible = "fsl,imx-ckil", "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + };
> +
> + ckih1 {
> + compatible = "fsl,imx-ckih1", "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <0>;
> + };
> +
> + osc {
> + u-boot,dm-spl;
> + compatible = "fsl,imx-osc", "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <2400>;
> + };
> + };
> +
> + soc {
> + u-boot,dm-spl;
> +
> + semc: semc@402f {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-semc";
> + reg = <0x402f 0x4000>;
> + clocks = < IMXRT1020_CLK_SEMC>;
> + pinctrl-0 = <_semc>;
> + pinctrl-names = "default";
> + status = "okay";
> + };
> +
> + lpuart1: serial@40184000 {
> + compatible = "fsl,imxrt-lpuart";
> + reg = <0x40184000 0x4000>;
> + interrupts =  IRQ_TYPE_LEVEL_HIGH>;
> + clocks = < IMXRT1020_CLK_LPUART1>;
> + clock-names = "per";
> + status = "disabled";
> + };
> +
> + iomuxc: iomuxc@401f8000 {
> + compatible = "fsl,imxrt-iomuxc";
> + reg = <0x401f8000 0x4000>;
> + fsl,mux_mask = <0x7>;
> + };
> +
> + clks: ccm@400fc000 {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt1020-ccm";
> + reg = <0x400fc000 0x4000>;
> + interrupts =  IRQ_TYPE_LEVEL_HIGH>,
> +   IRQ_TYPE_LEVEL_HIGH>;
> + #clock-cells = <1>;
> + };
> +
> + usdhc1: usdhc@402c {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-usdhc";
> + reg = <0x402c 0x1>;
> + interrupts =  IRQ_TYPE_LEVEL_HIGH>;
> + clocks = < IMXRT1020_CLK_USDHC1>;
> + clock-names = "per";
> + bus-width = <4>;
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step= <2>;
> + status = "disabled";
> + };
> +
> + gpio1: gpio@401b8000 {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-gpio",
> "fsl,imx35-gpio";
> + reg = <0x401b8000 0x4000>;
> + interrupts =  IRQ_TYPE_LEVEL_HIGH>,
> +   IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio2: gpio@401bc000 {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-gpio",
> "fsl,imx35-gpio";
> + reg = <0x401bc000 0x4000>;
> + interrupts =  IRQ_TYPE_LEVEL_HIGH>,
> + ;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio3: gpio@401c {
> + u-boot,dm-spl;
> + compatible = "fsl,imxrt-gpio",
> "fsl,imx35-gpio";
> + reg = <0x401c 0x4000>;
> + interrupts =  IRQ_TYPE_LEVEL_HIGH>,
> 

Re: [PATCH 2/5] Add i.MXRT1020 support

[Lukasz Majewski]

On Tue, 18 Feb 2020 20:02:52 +0100
Giulio Benetti  wrote:

> Signed-off-by: Giulio Benetti 
> ---
>  arch/arm/mach-imx/imxrt/Kconfig | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/mach-imx/imxrt/Kconfig
> b/arch/arm/mach-imx/imxrt/Kconfig index e3aff11d48..f28d52d3b7 100644
> --- a/arch/arm/mach-imx/imxrt/Kconfig
> +++ b/arch/arm/mach-imx/imxrt/Kconfig
> @@ -3,6 +3,10 @@ if ARCH_IMXRT
>  config IMXRT
>   bool
>  
> +config IMXRT1020
> + bool
> + select IMXRT
> +
>  config IMXRT1050
>   bool
>   select IMXRT

Reviewed-by: Lukasz Majewski 


Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de


pgp3aidMTT7YV.pgp
Description: OpenPGP digital signature

Re: [PATCH 1/5] clk: imx: add i.IMXRT1020 clk driver

[Lukasz Majewski]

On Tue, 18 Feb 2020 20:02:51 +0100
Giulio Benetti  wrote:

> Add i.MXRT1020 clk driver support.
> 
> Signed-off-by: Giulio Benetti 
> ---
>  drivers/clk/imx/Kconfig |  16 ++
>  drivers/clk/imx/Makefile|   1 +
>  drivers/clk/imx/clk-imxrt1020.c | 227
>  include/dt-bindings/clock/imxrt1020-clock.h |
> 52 + 4 files changed, 296 insertions(+)
>  create mode 100644 drivers/clk/imx/clk-imxrt1020.c
>  create mode 100644 include/dt-bindings/clock/imxrt1020-clock.h
> 
> diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
> index 059bc2fbb9..96721bcbf3 100644
> --- a/drivers/clk/imx/Kconfig
> +++ b/drivers/clk/imx/Kconfig
> @@ -69,6 +69,22 @@ config CLK_IMX8MP
>   help
> This enables support clock driver for i.MX8MP platforms.
>  
> +config SPL_CLK_IMXRT1020
> + bool "SPL clock support for i.MXRT1020"
> + depends on ARCH_IMXRT && SPL
> + select SPL_CLK
> + select SPL_CLK_CCF
> + help
> +   This enables SPL DM/DTS support for clock driver in
> i.MXRT1020 +
> +config CLK_IMXRT1020
> + bool "Clock support for i.MXRT1020"
> + depends on ARCH_IMXRT
> + select CLK
> + select CLK_CCF
> + help
> +   This enables support clock driver for i.MXRT1020 platforms.
> +
>  config SPL_CLK_IMXRT1050
>   bool "SPL clock support for i.MXRT1050"
>   depends on ARCH_IMXRT && SPL
> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> index 1e8a49d0f3..01bbbdf3ae 100644
> --- a/drivers/clk/imx/Makefile
> +++ b/drivers/clk/imx/Makefile
> @@ -17,4 +17,5 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o
> clk-pll14xx.o \ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o
> clk-pll14xx.o \ clk-composite-8m.o
>  
> +obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
>  obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
> diff --git a/drivers/clk/imx/clk-imxrt1020.c
> b/drivers/clk/imx/clk-imxrt1020.c new file mode 100644
> index 00..840f783940
> --- /dev/null
> +++ b/drivers/clk/imx/clk-imxrt1020.c
> @@ -0,0 +1,227 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright(C) 2020
> + * Author(s): Giulio Benetti 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "clk.h"
> +
> +static ulong imxrt1020_clk_get_rate(struct clk *clk)
> +{
> + struct clk *c;
> + int ret;
> +
> + debug("%s(#%lu)\n", __func__, clk->id);
> +
> + ret = clk_get_by_id(clk->id, );
> + if (ret)
> + return ret;
> +
> + return clk_get_rate(c);
> +}
> +
> +static ulong imxrt1020_clk_set_rate(struct clk *clk, unsigned long
> rate) +{
> + struct clk *c;
> + int ret;
> +
> + debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
> +
> + ret = clk_get_by_id(clk->id, );
> + if (ret)
> + return ret;
> +
> + return clk_set_rate(c, rate);
> +}
> +
> +static int __imxrt1020_clk_enable(struct clk *clk, bool enable)
> +{
> + struct clk *c;
> + int ret;
> +
> + debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
> +
> + ret = clk_get_by_id(clk->id, );
> + if (ret)
> + return ret;
> +
> + if (enable)
> + ret = clk_enable(c);
> + else
> + ret = clk_disable(c);
> +
> + return ret;
> +}
> +
> +static int imxrt1020_clk_disable(struct clk *clk)
> +{
> + return __imxrt1020_clk_enable(clk, 0);
> +}
> +
> +static int imxrt1020_clk_enable(struct clk *clk)
> +{
> + return __imxrt1020_clk_enable(clk, 1);
> +}
> +
> +static struct clk_ops imxrt1020_clk_ops = {
> + .set_rate = imxrt1020_clk_set_rate,
> + .get_rate = imxrt1020_clk_get_rate,
> + .enable = imxrt1020_clk_enable,
> + .disable = imxrt1020_clk_disable,
> +};
> +
> +static const char * const pll2_bypass_sels[] = {"pll2_sys", "osc", };
> +static const char * const pll3_bypass_sels[] = {"pll3_usb_otg",
> "osc", }; +
> +static const char *const pre_periph_sels[] = { "pll2_sys",
> "pll2_pfd3_297m", "pll3_pfd3_454_74m", "arm_podf", }; +static const
> char *const periph_sels[] = { "pre_periph_sel", "todo", }; +static
> const char *const usdhc_sels[] = { "pll2_pfd2_396m",
> "pll2_pfd0_352m", }; +static const char *const lpuart_sels[] = {
> "pll3_80m", "osc", }; +static const char *const semc_alt_sels[] = {
> "pll2_pfd2_396m", "pll3_pfd1_664_62m", }; +static const char *const
> semc_sels[] = { "periph_sel", "semc_alt_sel", }; + +static int
> imxrt1020_clk_probe(struct udevice *dev) +{
> + void *base;
> +
> + /* Anatop clocks */
> + base = (void *)ANATOP_BASE_ADDR;
> +
> + clk_dm(IMXRT1020_CLK_PLL2_SYS,
> +imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc",
> +  base + 0x30, 0x1));
> + clk_dm(IMXRT1020_CLK_PLL3_USB_OTG,
> +imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
> +  base + 0x10, 0x1));
> +
> + /* PLL bypass out 

Re: [PATCH 1/3] clk: imx: imx8mn: add enet clk

[Lukasz Majewski]

Hi Alifer,

> Add enet ref/timer/PHY_REF/root clk wich are required to make enet
> work properly

Why have you sent those patches twice?

> 
> Signed-off-by: Alifer Moraes 
> ---
>  drivers/clk/imx/clk-imx8mn.c | 19 +++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/drivers/clk/imx/clk-imx8mn.c
> b/drivers/clk/imx/clk-imx8mn.c index eb43971ae6..103ba770ed 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -80,6 +80,17 @@ static const char *imx8mn_ahb_sels[] =
> {"clock-osc-24m", "sys_pll1_133m", "sys_p static const char
> *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m",
> "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
> "video_pll1_out", "sys_pll3_out", }; +#ifndef CONFIG_SPL_BUILD
> +static const char *imx8mn_enet_ref_sels[] = {"clock-osc-24m",
> "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
> +  "sys_pll1_160m",
> "audio_pll1_out", "video_pll1_out", "clk_ext4", }; +
> +static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m",
> "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
> +"clk_ext3",
> "clk_ext4", "video_pll1_out", }; +
> +static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m",
> "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
> +  "sys_pll2_500m",
> "video_pll1_out", "audio_pll2_out", }; +#endif
> +
>  static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m",
> "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m",
> "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", }; 
> @@ -363,6 +374,14 @@ static int imx8mn_clk_probe(struct udevice *dev)
>   clk_dm(IMX8MN_CLK_USDHC3_ROOT,
>  imx_clk_gate4("usdhc3_root_clk", "usdhc3", base +
> 0x45e0, 0)); 
> +/* clks not needed in SPL stage */
> +#ifndef CONFIG_SPL_BUILD
> + clk_dm(IMX8MN_CLK_ENET_REF, imx8m_clk_composite("enet_ref",
> imx8mn_enet_ref_sels, base + 0xa980));
> + clk_dm(IMX8MN_CLK_ENET_TIMER,
> imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels, base +
> 0xaa00));
> + clk_dm(IMX8MN_CLK_ENET_PHY_REF,
> imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels, base + 0xaa80));
> + clk_dm(IMX8MN_CLK_ENET1_ROOT,
> imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0));
> +#endif +
>  #ifdef CONFIG_SPL_BUILD
>   struct clk *clkp, *clkp1;
>  




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de


pgpUFHuAD3lDV.pgp
Description: OpenPGP digital signature

Re: [U-Boot] [RFC/RFT PATCH v4 3/3] image: Add compressed Image parsing support in booti.

[Atish Patra]

On Thu, Feb 20, 2020 at 1:14 PM David Abdurachmanov
 wrote:
>
> On Tue, Feb 18, 2020 at 10:38 PM Tom Rini  wrote:
> >
> > On Sun, Feb 16, 2020 at 04:48:22PM -0800, Atish Patra wrote:
> > > On Fri, Feb 14, 2020 at 8:43 AM Tom Rini  wrote:
> > > >
> > > > On Thu, Feb 13, 2020 at 11:32:52PM +0200, David Abdurachmanov wrote:
> > > > > On Thu, Feb 13, 2020 at 6:17 PM Tom Rini  wrote:
> > > > > >
> > > > > > On Wed, Feb 05, 2020 at 12:01:38AM +, Atish Patra wrote:
> > > > > > > On Fri, 2019-11-22 at 18:19 -0800, Atish Patra wrote:
> > > > > > > > On Wed, 2019-11-13 at 11:47 -0800, Atish Patra wrote:
> > > > > > > > > On Wed, 2019-11-13 at 15:36 +0200, David Abdurachmanov wrote:
> > > > > > > > > > On Sat, Nov 9, 2019 at 2:14 AM Atish Patra 
> > > > > > > > > > 
> > > > > > > > > > wrote:
> > > > > > > > > > > Add compressed Image parsing support so that booti can 
> > > > > > > > > > > parse
> > > > > > > > > > > both
> > > > > > > > > > > flat and compressed Image to boot Linux. Currently, it is
> > > > > > > > > > > difficult
> > > > > > > > > > > to calculate a safe address for every board where the
> > > > > > > > > > > compressed
> > > > > > > > > > > image can be decompressed. It is also not possible to 
> > > > > > > > > > > figure
> > > > > > > > > > > out
> > > > > > > > > > > the
> > > > > > > > > > > size of the compressed file as well. Thus, user need to 
> > > > > > > > > > > set two
> > > > > > > > > > > additional environment variables kernel_comp_addr_r and
> > > > > > > > > > > filesize
> > > > > > > > > > > to
> > > > > > > > > > > make this work.
> > > > > > > > > > >
> > > > > > > > > > > Following compression methods are supported for now.
> > > > > > > > > > > lzma, lzo, bzip2, gzip.
> > > > > > > > > > >
> > > > > > > > > > > lz4 support is not added as ARM64 kernel generates a lz4
> > > > > > > > > > > compressed
> > > > > > > > > > > image with legacy header which U-Boot doesn't know how to 
> > > > > > > > > > > parse
> > > > > > > > > > > and
> > > > > > > > > > > decompress.
> > > > > > > > > > >
> > > > > > > > > > > Tested on HiFive Unleashed and Qemu for RISC-V.
> > > > > > > > > > > Tested on Qemu for ARM64.
> > > > > > > > > > >
> > > > > > > > > > > Signed-off-by: Atish Patra 
> > > > > > > > > > > ---
> > > > > > > > > > > I could not test this patch on any ARM64 boards due to 
> > > > > > > > > > > lack of
> > > > > > > > > > > access to any ARM64 board. If anybody can test it on 
> > > > > > > > > > > ARM64,
> > > > > > > > > > > that
> > > > > > > > > > > would be great.
> > > > > > > > > > > ---
> > > > > > > > > > >  cmd/booti.c| 40 
> > > > > > > > > > > ++-
> > > > > > > > > > >  doc/README.distro  | 12 +
> > > > > > > > > > >  doc/board/sifive/fu540.rst | 55
> > > > > > > > > > > ++
> > > > > > > > > > >  3 files changed, 106 insertions(+), 1 deletion(-)
> > > > > > > > > > >
> > > > > > > > > > > diff --git a/cmd/booti.c b/cmd/booti.c
> > > > > > > > > > > index c36b0235df8c..cd8670a9a8db 100644
> > > > > > > > > > > --- a/cmd/booti.c
> > > > > > > > > > > +++ b/cmd/booti.c
> > > > > > > > > > > @@ -13,6 +13,7 @@
> > > > > > > > > > >  #include 
> > > > > > > > > > >  #include 
> > > > > > > > > > >
> > > > > > > > > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > > > > > > > >  /*
> > > > > > > > > > >   * Image booting support
> > > > > > > > > > >   */
> > > > > > > > > > > @@ -23,6 +24,12 @@ static int booti_start(cmd_tbl_t 
> > > > > > > > > > > *cmdtp, int
> > > > > > > > > > > flag, int argc,
> > > > > > > > > > > ulong ld;
> > > > > > > > > > > ulong relocated_addr;
> > > > > > > > > > > ulong image_size;
> > > > > > > > > > > +   uint8_t *temp;
> > > > > > > > > > > +   ulong dest;
> > > > > > > > > > > +   ulong dest_end;
> > > > > > > > > > > +   unsigned long comp_len;
> > > > > > > > > > > +   unsigned long decomp_len;
> > > > > > > > > > > +   int ctype;
> > > > > > > > > > >
> > > > > > > > > > > ret = do_bootm_states(cmdtp, flag, argc, argv,
> > > > > > > > > > > BOOTM_STATE_START,
> > > > > > > > > > >   images, 1);
> > > > > > > > > > > @@ -37,6 +44,33 @@ static int booti_start(cmd_tbl_t 
> > > > > > > > > > > *cmdtp, int
> > > > > > > > > > > flag, int argc,
> > > > > > > > > > > debug("*  kernel: cmdline image address =
> > > > > > > > > > > 0x%08lx\n", ld);
> > > > > > > > > > > }
> > > > > > > > > > >
> > > > > > > > > > > +   temp = map_sysmem(ld, 0);
> > > > > > > > > > > +   ctype = image_decomp_type(temp, 2);
> > > > > > > > > > > +   if (ctype > 0) {
> > > > > > > > > > > +   dest = 
> > > > > > > > > > > env_get_ulong("kernel_comp_addr_r", 16,
> > > > > > > > > > > 0);
> > > > > > > > > > > +   comp_len = env_get_ulong("filesize", 16, 
> > > > > > > > > > > 0);
> > > > > > > > > > > +   if (!dest || 

Re: [PATCH v2 06/21] configs: socfpga: Enable FIT image loading with ATF support

[Westergreen, Dalon]

On Thu, 2020-02-20 at 21:00 +0100, Simon Goldschmidt wrote:

Am 20.02.2020 um 17:45 schrieb Marek Vasut:

On 2/20/20 3:15 AM, Ang, Chee Hong wrote:

On 2/19/20 1:25 PM,



chee.hong@intel.com

 wrote:

From: Chee Hong Ang <



chee.hong@intel.com

>


SPL now loads ATF (BL31), U-Boot proper and DTB from FIT image. The

new boot flow with ATF support is as follow:


SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux)


Signed-off-by: Chee Hong Ang <



chee.hong@intel.com

>

---

 configs/socfpga_agilex_defconfig| 8 +++-

 configs/socfpga_stratix10_defconfig | 8 +++-

 2 files changed, 14 insertions(+), 2 deletions(-)


diff --git a/configs/socfpga_agilex_defconfig

b/configs/socfpga_agilex_defconfig

index 693a774..0065ff0 100644

--- a/configs/socfpga_agilex_defconfig

+++ b/configs/socfpga_agilex_defconfig

@@ -1,6 +1,6 @@

 CONFIG_ARM=y

 CONFIG_ARCH_SOCFPGA=y

-CONFIG_SYS_TEXT_BASE=0x1000

+CONFIG_SYS_TEXT_BASE=0x20


Why did the text base change ?

This defconfig support ATF.

ATF will occupy from this address range (0x1000)

U-Boot now starts at 0x20.


Then please document it in the commit message.


Or even better, could we have 2 defconfigs, one for ATF, one for

non-ATF? That way, we get build coverage that this still works.

This patch set does already add a separate defconfig for non-ATF in 21/21

--dalon



Regards,

Simon



 CONFIG_SYS_MALLOC_F_LEN=0x2000

 CONFIG_ENV_SIZE=0x1000

 CONFIG_ENV_OFFSET=0x200

@@ -10,10 +10,16 @@ CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y

 CONFIG_IDENT_STRING="socfpga_agilex"

 CONFIG_SPL_FS_FAT=y

 CONFIG_SPL_TEXT_BASE=0xFFE0

+CONFIG_FIT=y

+CONFIG_SPL_LOAD_FIT=y

+CONFIG_SPL_FIT_SOURCE="board/altera/soc64/its/fit_spl_atf.its"

 CONFIG_BOOTDELAY=5

+CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y


Is legacy image support really needed ?

Let me check. Will get rid of this if it's not needed. Thanks.


Thanks

Re: [PATCH] board: nitrogen6x: migrate to CONFIG_DM_VIDEO

[Fabio Estevam]

On Thu, Feb 20, 2020 at 6:52 PM Troy Kisky
 wrote:

> Or I can just skip the dts changes. I don't think they are needed.

Yes, that's what I thought as well. Skipping the dts changes is fine.

> Do we have a policy for dead dts code ?

Not really. We try to keep the U-Boot dts in sync with upstream
whenever possible.

Re: [PATCH] board: nitrogen6x: migrate to CONFIG_DM_VIDEO

[Troy Kisky]

On 2/20/2020 1:43 PM, Fabio Estevam wrote:
> Hi Troy,
> 
> On Thu, Feb 20, 2020 at 6:37 PM Troy Kisky
>  wrote:
>>
>> Enable driver model for Video to remove compiler warning.
>> To enable display, issue
>>
>> setenv stdout serial,vidconsole;
>>
>> Add CONFIG_DM_VIDEO to all defconfigs whose board is
>> nitrogen6x.
>> mx6qsabrelite_defconfig
>> nitrogen6dl2g_defconfig
>> nitrogen6dl_defconfig
>> nitrogen6q2g_defconfig
>> nitrogen6q_defconfig
>> nitrogen6s1g_defconfig
>> nitrogen6s_defconfig
>>
>> Signed-off-by: Troy Kisky 
>>
>> diff --git a/arch/arm/dts/imx6qdl-sabrelite.dtsi 
>> b/arch/arm/dts/imx6qdl-sabrelite.dtsi
>> index 673a19c3df..86375156b9 100644
>> --- a/arch/arm/dts/imx6qdl-sabrelite.dtsi
>> +++ b/arch/arm/dts/imx6qdl-sabrelite.dtsi
>> @@ -195,6 +195,15 @@
>> pwm_lvds = 
>> };
>>
>> +   backlight_lvds: backlight-lvds {
>> +   brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>;
>> +   compatible = "pwm-backlight";
>> +   default-brightness-level = <8>;
>> +   power-supply = <_3p3v>;
>> +   pwms = < 0 500>;
>> +   status = "okay";
>> +   };
>> +
>> chosen {
>> stdout-path = 
>> };
>> @@ -219,6 +228,17 @@
>> gpio = GP_REG_USBOTG;
>> enable-active-high;
>> };
>> +
>> +   panel-lvds0 {
>> +   backlight = <_lvds>;
>> +   compatible = "hannstar,hsd100pxn1";
> 
> Instead of adding only the LVDS pieces here, what about resyncing the
> whole dts with the upstream kernel on a separate patch ?
> 

Or I can just skip the dts changes. I don't think they are needed.


Do we have a policy for dead dts code ?

Thanks
Troy

Re: [PATCH] board: nitrogen6x: migrate to CONFIG_DM_VIDEO

[Fabio Estevam]

Hi Troy,

On Thu, Feb 20, 2020 at 6:37 PM Troy Kisky
 wrote:
>
> Enable driver model for Video to remove compiler warning.
> To enable display, issue
>
> setenv stdout serial,vidconsole;
>
> Add CONFIG_DM_VIDEO to all defconfigs whose board is
> nitrogen6x.
> mx6qsabrelite_defconfig
> nitrogen6dl2g_defconfig
> nitrogen6dl_defconfig
> nitrogen6q2g_defconfig
> nitrogen6q_defconfig
> nitrogen6s1g_defconfig
> nitrogen6s_defconfig
>
> Signed-off-by: Troy Kisky 
>
> diff --git a/arch/arm/dts/imx6qdl-sabrelite.dtsi 
> b/arch/arm/dts/imx6qdl-sabrelite.dtsi
> index 673a19c3df..86375156b9 100644
> --- a/arch/arm/dts/imx6qdl-sabrelite.dtsi
> +++ b/arch/arm/dts/imx6qdl-sabrelite.dtsi
> @@ -195,6 +195,15 @@
> pwm_lvds = 
> };
>
> +   backlight_lvds: backlight-lvds {
> +   brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>;
> +   compatible = "pwm-backlight";
> +   default-brightness-level = <8>;
> +   power-supply = <_3p3v>;
> +   pwms = < 0 500>;
> +   status = "okay";
> +   };
> +
> chosen {
> stdout-path = 
> };
> @@ -219,6 +228,17 @@
> gpio = GP_REG_USBOTG;
> enable-active-high;
> };
> +
> +   panel-lvds0 {
> +   backlight = <_lvds>;
> +   compatible = "hannstar,hsd100pxn1";

Instead of adding only the LVDS pieces here, what about resyncing the
whole dts with the upstream kernel on a separate patch ?

[PATCH] board: nitrogen6x: migrate to CONFIG_DM_VIDEO

[Troy Kisky]

Enable driver model for Video to remove compiler warning.
To enable display, issue

setenv stdout serial,vidconsole;

Add CONFIG_DM_VIDEO to all defconfigs whose board is
nitrogen6x.
mx6qsabrelite_defconfig
nitrogen6dl2g_defconfig
nitrogen6dl_defconfig
nitrogen6q2g_defconfig
nitrogen6q_defconfig
nitrogen6s1g_defconfig
nitrogen6s_defconfig

Signed-off-by: Troy Kisky 

diff --git a/arch/arm/dts/imx6qdl-sabrelite.dtsi 
b/arch/arm/dts/imx6qdl-sabrelite.dtsi
index 673a19c3df..86375156b9 100644
--- a/arch/arm/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/dts/imx6qdl-sabrelite.dtsi
@@ -195,6 +195,15 @@
pwm_lvds = 
};
 
+   backlight_lvds: backlight-lvds {
+   brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>;
+   compatible = "pwm-backlight";
+   default-brightness-level = <8>;
+   power-supply = <_3p3v>;
+   pwms = < 0 500>;
+   status = "okay";
+   };
+
chosen {
stdout-path = 
};
@@ -219,6 +228,17 @@
gpio = GP_REG_USBOTG;
enable-active-high;
};
+
+   panel-lvds0 {
+   backlight = <_lvds>;
+   compatible = "hannstar,hsd100pxn1";
+
+   port {
+   panel_in: endpoint {
+   remote-endpoint = <_out>;
+   };
+   };
+   };
 };
 
  {
@@ -281,6 +301,11 @@
};
 };
 
+ {
+   ddc-i2c-bus = <>;
+   status = "okay";
+};
+
  {
clock-frequency = <10>;
pinctrl-names = "default", "gpio";
@@ -316,6 +341,22 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+
+   lvds-channel@0 {
+   status = "okay";
+
+   port@4 {
+   reg = <4>;
+
+   lvds0_out: endpoint {
+   remote-endpoint = <_in>;
+   };
+   };
+   };
+};
+
  {
status = "okay";
 };
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index a85bfe0769..1171192c33 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x1780
+CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x6
@@ -9,7 +10,6 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_CMD_HDMIDETECT=y
 CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_SYS_MALLOC_F is not set
 
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE"
 CONFIG_BOOTDELAY=3
 # CONFIG_USE_BOOTCOMMAND is not set
@@ -68,6 +68,6 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index d10162578a..07814f3ef4 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x1780
+CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x2000
@@ -9,7 +10,6 @@ CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_CMD_HDMIDETECT=y
 CONFIG_AHCI=y
-# CONFIG_SYS_MALLOC_F is not set
 
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048"
 CONFIG_BOOTDELAY=3
 CONFIG_USE_PREBOOT=y
@@ -72,6 +72,6 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index dd07ce0d58..7a0de9d0e0 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x1780
+CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_SECT_SIZE=0x2000
@@ -9,7 +10,6 @@ CONFIG_DM_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_CMD_HDMIDETECT=y
 CONFIG_AHCI=y
-# CONFIG_SYS_MALLOC_F is not set
 
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024"
 CONFIG_BOOTDELAY=3
 CONFIG_USE_PREBOOT=y
@@ -72,6 +72,6 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index 91b85ea708..69698d94a0 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -1,6 +1,7 @@
 

Re: [U-Boot] [RFC/RFT PATCH v4 3/3] image: Add compressed Image parsing support in booti.

[David Abdurachmanov]

On Tue, Feb 18, 2020 at 10:38 PM Tom Rini  wrote:
>
> On Sun, Feb 16, 2020 at 04:48:22PM -0800, Atish Patra wrote:
> > On Fri, Feb 14, 2020 at 8:43 AM Tom Rini  wrote:
> > >
> > > On Thu, Feb 13, 2020 at 11:32:52PM +0200, David Abdurachmanov wrote:
> > > > On Thu, Feb 13, 2020 at 6:17 PM Tom Rini  wrote:
> > > > >
> > > > > On Wed, Feb 05, 2020 at 12:01:38AM +, Atish Patra wrote:
> > > > > > On Fri, 2019-11-22 at 18:19 -0800, Atish Patra wrote:
> > > > > > > On Wed, 2019-11-13 at 11:47 -0800, Atish Patra wrote:
> > > > > > > > On Wed, 2019-11-13 at 15:36 +0200, David Abdurachmanov wrote:
> > > > > > > > > On Sat, Nov 9, 2019 at 2:14 AM Atish Patra 
> > > > > > > > > 
> > > > > > > > > wrote:
> > > > > > > > > > Add compressed Image parsing support so that booti can parse
> > > > > > > > > > both
> > > > > > > > > > flat and compressed Image to boot Linux. Currently, it is
> > > > > > > > > > difficult
> > > > > > > > > > to calculate a safe address for every board where the
> > > > > > > > > > compressed
> > > > > > > > > > image can be decompressed. It is also not possible to figure
> > > > > > > > > > out
> > > > > > > > > > the
> > > > > > > > > > size of the compressed file as well. Thus, user need to set 
> > > > > > > > > > two
> > > > > > > > > > additional environment variables kernel_comp_addr_r and
> > > > > > > > > > filesize
> > > > > > > > > > to
> > > > > > > > > > make this work.
> > > > > > > > > >
> > > > > > > > > > Following compression methods are supported for now.
> > > > > > > > > > lzma, lzo, bzip2, gzip.
> > > > > > > > > >
> > > > > > > > > > lz4 support is not added as ARM64 kernel generates a lz4
> > > > > > > > > > compressed
> > > > > > > > > > image with legacy header which U-Boot doesn't know how to 
> > > > > > > > > > parse
> > > > > > > > > > and
> > > > > > > > > > decompress.
> > > > > > > > > >
> > > > > > > > > > Tested on HiFive Unleashed and Qemu for RISC-V.
> > > > > > > > > > Tested on Qemu for ARM64.
> > > > > > > > > >
> > > > > > > > > > Signed-off-by: Atish Patra 
> > > > > > > > > > ---
> > > > > > > > > > I could not test this patch on any ARM64 boards due to lack 
> > > > > > > > > > of
> > > > > > > > > > access to any ARM64 board. If anybody can test it on ARM64,
> > > > > > > > > > that
> > > > > > > > > > would be great.
> > > > > > > > > > ---
> > > > > > > > > >  cmd/booti.c| 40 ++-
> > > > > > > > > >  doc/README.distro  | 12 +
> > > > > > > > > >  doc/board/sifive/fu540.rst | 55
> > > > > > > > > > ++
> > > > > > > > > >  3 files changed, 106 insertions(+), 1 deletion(-)
> > > > > > > > > >
> > > > > > > > > > diff --git a/cmd/booti.c b/cmd/booti.c
> > > > > > > > > > index c36b0235df8c..cd8670a9a8db 100644
> > > > > > > > > > --- a/cmd/booti.c
> > > > > > > > > > +++ b/cmd/booti.c
> > > > > > > > > > @@ -13,6 +13,7 @@
> > > > > > > > > >  #include 
> > > > > > > > > >  #include 
> > > > > > > > > >
> > > > > > > > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > > > > > > >  /*
> > > > > > > > > >   * Image booting support
> > > > > > > > > >   */
> > > > > > > > > > @@ -23,6 +24,12 @@ static int booti_start(cmd_tbl_t *cmdtp, 
> > > > > > > > > > int
> > > > > > > > > > flag, int argc,
> > > > > > > > > > ulong ld;
> > > > > > > > > > ulong relocated_addr;
> > > > > > > > > > ulong image_size;
> > > > > > > > > > +   uint8_t *temp;
> > > > > > > > > > +   ulong dest;
> > > > > > > > > > +   ulong dest_end;
> > > > > > > > > > +   unsigned long comp_len;
> > > > > > > > > > +   unsigned long decomp_len;
> > > > > > > > > > +   int ctype;
> > > > > > > > > >
> > > > > > > > > > ret = do_bootm_states(cmdtp, flag, argc, argv,
> > > > > > > > > > BOOTM_STATE_START,
> > > > > > > > > >   images, 1);
> > > > > > > > > > @@ -37,6 +44,33 @@ static int booti_start(cmd_tbl_t *cmdtp, 
> > > > > > > > > > int
> > > > > > > > > > flag, int argc,
> > > > > > > > > > debug("*  kernel: cmdline image address =
> > > > > > > > > > 0x%08lx\n", ld);
> > > > > > > > > > }
> > > > > > > > > >
> > > > > > > > > > +   temp = map_sysmem(ld, 0);
> > > > > > > > > > +   ctype = image_decomp_type(temp, 2);
> > > > > > > > > > +   if (ctype > 0) {
> > > > > > > > > > +   dest = env_get_ulong("kernel_comp_addr_r", 
> > > > > > > > > > 16,
> > > > > > > > > > 0);
> > > > > > > > > > +   comp_len = env_get_ulong("filesize", 16, 0);
> > > > > > > > > > +   if (!dest || !comp_len) {
> > > > > > > > > > +   puts("kernel_comp_addr_r or 
> > > > > > > > > > filesize is
> > > > > > > > > > not
> > > > > > > > > > provided!\n");
> > > > > > > > > > +   return -EINVAL;
> > > > > > > > > > +   }
> > > > > > > > > > +   if (dest < gd->ram_base || dest > 
> > > > > > > > > > gd->ram_top)
> > 

Re: [PATCH] env: ti: boot: Fix Android boot on AM57x EVM

[Sam Protsenko]

Hi Eugeniu,

On Thu, Feb 20, 2020 at 4:33 PM Eugeniu Rosca  wrote:
>
> Hi Sam,
>
> On Wed, Feb 19, 2020 at 08:27:52PM +0200, Sam Protsenko wrote:
> > When applying DTBO on top of DTB (with "fdt apply" command) on AM57x EVM
> > board, there is not enough memory reserved in RAM for DTB blob. Hence,
> > DTBO can't be merged in DTB. It leads to inability to boot Android with
> > next error message:
> >
> > failed on fdt_overlay_apply(): FDT_ERR_NOSPACE
> >
> > To overcome that issue let's provide 1 MiB of space to keep DTB and all
> > merged DTBO blobs. To do so, "length" parameter should be specified for
> > "fdt addr" command:
> >
> > => fdt addr $fdtaddr 0x10
>
> I am not an everyday user of this platform, hence curious what are the
> usual sizes of DTB and DTBO files employed in Android booting?
>

DTB/DTBO files are not big for AM57x EVM, the same order of magnitude
as yours. Actually it makes sense to reduce 1 MiB I used to 512 KiB,
because:

fdtaddr=0x8800

and next used address after this:

rdaddr=0x8808

so if I make the fdt size = 512 KiB, it gives us exactly the gap
between $fdtaddr and $rdaddr, which is 0x8.

Thanks for the review! I will send v2 soon.

> For comparison, below are the sizes of R-Car3 DTB (Linux v5.6-rc2):
>
> $ du -sh arch/arm64/boot/dts/renesas/r8a779*dtb | sort -n
> 32K arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dtb
> 32K arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dtb
> 44K arch/arm64/boot/dts/renesas/r8a77990-ebisu.dtb
> 52K arch/arm64/boot/dts/renesas/r8a77965-ulcb.dtb
> 60K arch/arm64/boot/dts/renesas/r8a77960-ulcb.dtb
> 60K arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dtb
> 60K arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dtb
> 60K arch/arm64/boot/dts/renesas/r8a77965-ulcb-kf.dtb
> 64K arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dtb
> 64K arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dtb
> 64K arch/arm64/boot/dts/renesas/r8a77960-ulcb-kf.dtb
> 68K arch/arm64/boot/dts/renesas/r8a77950-ulcb.dtb
> 68K arch/arm64/boot/dts/renesas/r8a77951-ulcb.dtb
> 72K arch/arm64/boot/dts/renesas/r8a77950-salvator-x.dtb
> 72K arch/arm64/boot/dts/renesas/r8a77950-ulcb-kf.dtb
> 72K arch/arm64/boot/dts/renesas/r8a77951-salvator-x.dtb
> 72K arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dtb
> 72K arch/arm64/boot/dts/renesas/r8a77951-ulcb-kf.dtb
>
> FWIW based on the above values, Renesas scripts reserve 512K for DTB.
>
> >
> > Also add size variables to 'adtimg' command invocations, to avoid
> > cluttering the console with DTBO blob sizes.
>
> Looks good to me.
>
> >
> > Signed-off-by: Sam Protsenko 
>
> Reviewed-by: Eugeniu Rosca 
>
> --
> Best Regards
> Eugeniu Rosca

Re: [PATCH v3] dm: uclass: don't assign aliased seq numbers

[Michael Walle]

Hi Michal,

Am 2020-02-20 11:14, schrieb Michal Simek:

On 20. 02. 20 10:52, Michael Walle wrote:

Hi Michal,

Am 2020-02-20 09:30, schrieb Michal Simek:

On 03. 02. 20 18:11, Michael Walle wrote:
If there are aliases for an uclass, set the base for the 
"dynamically"

allocated numbers next to the highest alias.

Please note, that this might lead to holes in the sequences, 
depending
on the device tree. For example if there is only an alias 
"ethernet1",

the next device seq number would be 2.

In particular this fixes a problem with boards which are using 
ethernet
aliases but also might have network add-in cards like the E1000. If 
the
board is started with the add-in card and depending on the order of 
the
drivers, the E1000 might occupy the first ethernet device and mess 
up
all the hardware addresses, because the devices are now shifted by 
one.


Also adapt the test cases to the new handling and add test cases
checking the holes in the seq numbers.

Signed-off-by: Michael Walle 
Reviewed-by: Alex Marginean 
Tested-by: Alex Marginean 
Acked-by: Vladimir Oltean 
---

Please note that I've kept the R-b, T-b, and A-b tags although they 
were
for an older version. They only affects the drivers/core/uclass.c 
not

the
test/dm/ part. OTOH none of the actual implementation has changed.

I couldn't split the patch, otherwise the tests would fail.

As a side effect, this should also make the following commits
superfluous:
 - 7f3289bf6d ("dm: device: Request next sequence number")
 - 61607225d1 ("i2c: Fill req_seq in i2c_post_bind()")
   Although I don't understand the root cause of the said problem.

Thomas, Michal, could you please test this and then I'd add a second
patch removing the old code.

changes since v2:
 - adapt/new test cases, thanks Simon

changes since v1:
 - move notice about superfluous commits from commit message to this
   section.
 - fix the comment style

 arch/sandbox/dts/test.dts |  4 ++--
 drivers/core/uclass.c | 21 +++--
 include/configs/sandbox.h |  6 +++---
 test/dm/eth.c | 14 +++---
 test/dm/test-fdt.c    | 22 +-
 5 files changed, 44 insertions(+), 23 deletions(-)

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index e529c54d8d..d448892a65 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -19,8 +19,8 @@
 pci0 = 
 pci1 = 
 pci2 = 
-    remoteproc1 = _1;
-    remoteproc2 = _2;
+    remoteproc0 = _1;
+    remoteproc1 = _2;
 rtc0 = _0;
 rtc1 = _1;
 spi0 = "/spi@0";
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index c520ef113a..3c216221e0 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -675,13 +675,14 @@ int uclass_unbind_device(struct udevice *dev)

 int uclass_resolve_seq(struct udevice *dev)
 {
+    struct uclass *uc = dev->uclass;
+    struct uclass_driver *uc_drv = uc->uc_drv;
 struct udevice *dup;
-    int seq;
+    int seq = 0;
 int ret;

 assert(dev->seq == -1);
-    ret = uclass_find_device_by_seq(dev->uclass->uc_drv->id,
dev->req_seq,
-    false, );
+    ret = uclass_find_device_by_seq(uc_drv->id, dev->req_seq, 
false,

);
 if (!ret) {
 dm_warn("Device '%s': seq %d is in use by '%s'\n",
 dev->name, dev->req_seq, dup->name);
@@ -693,9 +694,17 @@ int uclass_resolve_seq(struct udevice *dev)
 return ret;
 }

-    for (seq = 0; seq < DM_MAX_SEQ; seq++) {
-    ret = uclass_find_device_by_seq(dev->uclass->uc_drv->id, 
seq,

-    false, );
+    if (CONFIG_IS_ENABLED(DM_SEQ_ALIAS) &&
+    (uc_drv->flags & DM_UC_FLAG_SEQ_ALIAS)) {
+    /*
+ * dev_read_alias_highest_id() will return -1 if there no
+ * alias. Thus we can always add one.
+ */
+    seq = dev_read_alias_highest_id(uc_drv->name) + 1;
+    }
+
+    for (; seq < DM_MAX_SEQ; seq++) {
+    ret = uclass_find_device_by_seq(uc_drv->id, seq, false, 
);

 if (ret == -ENODEV)
 break;
 if (ret)
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 1c13055cdc..b02c362fed 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -97,9 +97,9 @@
 #endif

 #define SANDBOX_ETH_SETTINGS    "ethaddr=00:00:11:22:33:44\0" \
-    "eth1addr=00:00:11:22:33:45\0" \
-    "eth3addr=00:00:11:22:33:46\0" \
-    "eth5addr=00:00:11:22:33:47\0" \
+    "eth3addr=00:00:11:22:33:45\0" \
+    "eth5addr=00:00:11:22:33:46\0" \
+    "eth6addr=00:00:11:22:33:47\0" \
 "ipaddr=1.2.3.4\0"

 #define MEM_LAYOUT_ENV_SETTINGS \
diff --git a/test/dm/eth.c b/test/dm/eth.c
index ad5354b4bf..75315a0c6d 100644
--- a/test/dm/eth.c
+++ b/test/dm/eth.c
@@ -47,7 +47,7 @@ static int dm_test_eth_alias(struct 
unit_test_state

*uts)
 ut_assertok(net_loop(PING));
 

Re: [PATCH v2 06/21] configs: socfpga: Enable FIT image loading with ATF support

[Simon Goldschmidt]

Am 20.02.2020 um 17:45 schrieb Marek Vasut:
> On 2/20/20 3:15 AM, Ang, Chee Hong wrote:
>>> On 2/19/20 1:25 PM, chee.hong@intel.com wrote:
 From: Chee Hong Ang 

 SPL now loads ATF (BL31), U-Boot proper and DTB from FIT image. The
 new boot flow with ATF support is as follow:

 SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux)

 Signed-off-by: Chee Hong Ang 
 ---
  configs/socfpga_agilex_defconfig| 8 +++-
  configs/socfpga_stratix10_defconfig | 8 +++-
  2 files changed, 14 insertions(+), 2 deletions(-)

 diff --git a/configs/socfpga_agilex_defconfig
 b/configs/socfpga_agilex_defconfig
 index 693a774..0065ff0 100644
 --- a/configs/socfpga_agilex_defconfig
 +++ b/configs/socfpga_agilex_defconfig
 @@ -1,6 +1,6 @@
  CONFIG_ARM=y
  CONFIG_ARCH_SOCFPGA=y
 -CONFIG_SYS_TEXT_BASE=0x1000
 +CONFIG_SYS_TEXT_BASE=0x20
>>>
>>> Why did the text base change ?
>> This defconfig support ATF.
>> ATF will occupy from this address range (0x1000)
>> U-Boot now starts at 0x20.
> 
> Then please document it in the commit message.

Or even better, could we have 2 defconfigs, one for ATF, one for
non-ATF? That way, we get build coverage that this still works.

Regards,
Simon

> 
  CONFIG_SYS_MALLOC_F_LEN=0x2000
  CONFIG_ENV_SIZE=0x1000
  CONFIG_ENV_OFFSET=0x200
 @@ -10,10 +10,16 @@ CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
  CONFIG_IDENT_STRING="socfpga_agilex"
  CONFIG_SPL_FS_FAT=y
  CONFIG_SPL_TEXT_BASE=0xFFE0
 +CONFIG_FIT=y
 +CONFIG_SPL_LOAD_FIT=y
 +CONFIG_SPL_FIT_SOURCE="board/altera/soc64/its/fit_spl_atf.its"
  CONFIG_BOOTDELAY=5
 +CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
>>>
>>> Is legacy image support really needed ?
>> Let me check. Will get rid of this if it's not needed. Thanks.
> 
> Thanks
> 

Re: [PATCH 0/3] Remove CONFIG_MMC_BROKEN_CD

[Tom Rini]

On Thu, Feb 20, 2020 at 01:45:31PM +0900, Jaehoon Chung wrote:

> CONFIG_MMC_BROKEN_CD needs not to define to Kconfig.
> broken-cd is already provide to dt-property.
> If want to poll card-detect, set to broken-cd instead of enabling 
> CONFIG_MMC_BROKEN_CD.
> 
> When checked the boards that is eabled CONFIG_MMC_BROKEN_CD,
> it also used the value of dt as broken-cd.
> 
> Jaehoon Chung (3):
>   mmc: jz_mmc; add MMC_CAP_NEEDS_POLL by default
>   mmc: check the flags of host_caps about broken-cd
>   mmc: Kconfig: remove MMC_BROKEN_CD configuration
> 
>  configs/brppt2_defconfig|  1 -
>  configs/ci20_mmc_defconfig  |  1 -
>  configs/meerkat96_defconfig |  1 -
>  drivers/mmc/Kconfig |  5 -
>  drivers/mmc/jz_mmc.c|  6 --
>  drivers/mmc/mmc.c   | 10 +-
>  6 files changed, 9 insertions(+), 15 deletions(-)

Did you size-test this change?  ci20 is extremely tight on space.

-- 
Tom


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RE: [PATCH v2 05/21] arm: socfpga: Override 'lowlevel_init' to support ATF

[Ang, Chee Hong]

> On 2/20/20 3:27 AM, Ang, Chee Hong wrote:
> >> On 2/19/20 1:25 PM, chee.hong@intel.com wrote:
> >> [...]
> >>> diff --git a/arch/arm/mach-socfpga/lowlevel_init.S
> >>> b/arch/arm/mach-socfpga/lowlevel_init.S
> >>> new file mode 100644
> >>> index 000..68053a0
> >>> --- /dev/null
> >>> +++ b/arch/arm/mach-socfpga/lowlevel_init.S
> >>
> >> This should be some lowlevel_init_64.S to make it clear it's only for
> >> arm64 platforms.
> > OK. It makes sense. Thanks.
> >>
> >>> @@ -0,0 +1,85 @@
> >>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>> +/*
> >>> + * Copyright (C) 2019, Intel Corporation  */
> >>> +
> >>> +#include 
> >>> +#include 
> >>> +#include 
> >>> +#include 
> >>> +
> >>> +ENTRY(lowlevel_init)
> >>> + mov x29, lr /* Save LR */
> >>> +
> >>> +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) #ifdef
> >>> +CONFIG_SPL_ATF
> >>> + branch_if_slave x0, 2f
> >>> +#else
> >>> + branch_if_slave x0, 1f
> >>> +#endif
> >>> +
> >>> + ldr x0, =GICD_BASE
> >>> + bl  gic_init_secure
> >>> +#ifdef CONFIG_SPL_BUILD
> >>> + b   2f
> >>> +#else
> >>> + b   3f
> >>> +#endif
> >>
> >> Can't this be done in C code ? Can we reduce the ifdeffery ?
> > This lowlevel_init function is shared by SPL and U-Boot and they run
> > in slightly different flow.
> 
> What does this 'different flow' mean ?
This has something to with multi-cores CPU such as A53.
For SPL, we need to make sure the slave CPUs (CPU1/2/3) trapped in a 'place'
Where they could be 'activated' by kernel for multi-processor environment.
It means the kernel get to 'activate' the slave CPUs from master CPU (CPU0)
 U-Boot proper only run on master CPU (CPU0). The rest of slave CPUs
are trapped in the beginning of SPL waiting to be 'activated'
by kernel.

In U-Boot proper, only master CPU gets to run this code and it will just
do the basic GIC setup and skip the 'trap'. The 'trap' is to prevent the slave
CPUs from running the same SPL, ATF and U-Boot code as the master CPU in
parallel. Only single core (maser CPU) is needed for bootloaders and firmware.
> 
> > I don't think this can be done in C code but let me see what I can do
> > to further optimize the flow to reduce the ifdeffery.
> 
> That would be nice, thanks.

Re: [PATCH] net: bcmgenet: Don't set ID_MODE_DIS when not using RGMII

[Florian Fainelli]

On 2/20/20 8:36 AM, Nicolas Saenz Julienne wrote:
> As per Linux's driver, ID_MODE_DIS is only set when the PHY interface is
> RGMII. Don't enable it for the rest of setups.
> 
> This has been seen to misconfigure RPi4's PHY when booting Linux.
> 
> Signed-off-by: Nicolas Saenz Julienne 

Does the failure look like the following: you have a driver for the
Broadcom PHY used on the Pi4 in u-boot, and the phy_dev->interface value
is being used to configure the Ethernet PHY chip in a certain way.

Later when you boot Linux, you do not have CONFIG_BROADCOM_PHY enabled
so the Generic PHY driver gets used instead, and there is a disagreement
between the AMAC and PHY as to whom should be adding the delays?

At any rate:

Reviewed-by: Florian Fainelli 

> ---
>  drivers/net/bcmgenet.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c
> index 8f4848aec6..e971b556ac 100644
> --- a/drivers/net/bcmgenet.c
> +++ b/drivers/net/bcmgenet.c
> @@ -448,7 +448,10 @@ static int bcmgenet_adjust_link(struct bcmgenet_eth_priv 
> *priv)
>   }
>  
>   clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE,
> - RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS);
> + RGMII_LINK | RGMII_MODE_EN);
> +
> + if (phy_dev->interface == PHY_INTERFACE_MODE_RGMII)
> + setbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, ID_MODE_DIS);
>  
>   writel(speed << CMD_SPEED_SHIFT, (priv->mac_reg + UMAC_CMD));
>  
> 


-- 
Florian

Re: [PATCH] net: bcmgenet: Don't set ID_MODE_DIS when not using RGMII

[Matthias Brugger]

On 20/02/2020 17:36, Nicolas Saenz Julienne wrote:
> As per Linux's driver, ID_MODE_DIS is only set when the PHY interface is
> RGMII. Don't enable it for the rest of setups.
> 
> This has been seen to misconfigure RPi4's PHY when booting Linux.
> 
> Signed-off-by: Nicolas Saenz Julienne 
> ---
>  drivers/net/bcmgenet.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c
> index 8f4848aec6..e971b556ac 100644
> --- a/drivers/net/bcmgenet.c
> +++ b/drivers/net/bcmgenet.c
> @@ -448,7 +448,10 @@ static int bcmgenet_adjust_link(struct bcmgenet_eth_priv 
> *priv)
>   }
>  
>   clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE,
> - RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS);
> + RGMII_LINK | RGMII_MODE_EN);
> +
> + if (phy_dev->interface == PHY_INTERFACE_MODE_RGMII)
> + setbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, ID_MODE_DIS);

Is this given because by different DTS? Shouldn't that be uniform on the RPi4?

BTW Joe, will you take patches for this driver through your branch? For now I
delegated it to me, but I'm fine either way.

Regards,
Matthias

>  
>   writel(speed << CMD_SPEED_SHIFT, (priv->mac_reg + UMAC_CMD));
>  
> 

[PATCH 2/2] sunxi: Remove no longer needed default options from defconfigs

[Andre Przywara]

Now that those common Allwinner config symbols are defined automatically
for all boards in their Kconfig files, we can remove the now redundant
definitions from the boards' _defconfig files.

Some boards had a differing definiton for some of those symbols, it
looks like mostly to "merge races" when the symbol was introduced (new
board *_defconfig file missed the "add symbol to all files" patch).

Signed-off-by: Andre Przywara 
---
 configs/A10-OLinuXino-Lime_defconfig   | 6 --
 configs/A10s-OLinuXino-M_defconfig | 6 --
 configs/A13-OLinuXinoM_defconfig   | 6 --
 configs/A13-OLinuXino_defconfig| 5 -
 configs/A20-OLinuXino-Lime2-eMMC_defconfig | 5 -
 configs/A20-OLinuXino-Lime2_defconfig  | 5 -
 configs/A20-OLinuXino-Lime_defconfig   | 6 --
 configs/A20-OLinuXino_MICRO-eMMC_defconfig | 6 --
 configs/A20-OLinuXino_MICRO_defconfig  | 6 --
 configs/A20-Olimex-SOM-EVB_defconfig   | 6 --
 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig   | 5 -
 configs/A20-Olimex-SOM204-EVB_defconfig| 5 -
 configs/A33-OLinuXino_defconfig| 6 --
 configs/Ainol_AW1_defconfig| 6 --
 configs/Ampe_A76_defconfig | 6 --
 configs/Auxtek-T003_defconfig  | 6 --
 configs/Auxtek-T004_defconfig  | 6 --
 configs/Bananapi_M2_Ultra_defconfig| 4 
 configs/Bananapi_defconfig | 6 --
 configs/Bananapi_m2m_defconfig | 4 
 configs/Bananapro_defconfig| 6 --
 configs/CHIP_defconfig | 6 --
 configs/CHIP_pro_defconfig | 4 
 configs/CSQ_CS908_defconfig| 6 --
 configs/Chuwi_V7_CW0825_defconfig  | 6 --
 configs/Colombus_defconfig | 6 --
 configs/Cubieboard2_defconfig  | 6 --
 configs/Cubieboard4_defconfig  | 6 --
 configs/Cubieboard_defconfig   | 6 --
 configs/Cubietruck_defconfig   | 5 -
 configs/Cubietruck_plus_defconfig  | 6 --
 configs/Empire_electronix_d709_defconfig   | 6 --
 configs/Empire_electronix_m712_defconfig   | 6 --
 configs/Hummingbird_A31_defconfig  | 6 --
 configs/Hyundai_A7HD_defconfig | 6 --
 configs/Itead_Ibox_A20_defconfig   | 6 --
 configs/Lamobo_R1_defconfig| 6 --
 configs/LicheePi_Zero_defconfig| 6 --
 configs/Linksprite_pcDuino3_Nano_defconfig | 6 --
 configs/Linksprite_pcDuino3_defconfig  | 6 --
 configs/Linksprite_pcDuino_defconfig   | 6 --
 configs/MK808C_defconfig   | 6 --
 configs/MSI_Primo73_defconfig  | 6 --
 configs/MSI_Primo81_defconfig  | 6 --
 configs/Marsboard_A10_defconfig| 6 --
 configs/Mele_A1000G_quad_defconfig | 6 --
 configs/Mele_A1000_defconfig   | 6 --
 configs/Mele_I7_defconfig  | 6 --
 configs/Mele_M3_defconfig  | 6 --
 configs/Mele_M5_defconfig  | 6 --
 configs/Mele_M9_defconfig  | 6 --
 configs/Merrii_A80_Optimus_defconfig   | 6 --
 configs/Mini-X_defconfig   | 6 --
 configs/Nintendo_NES_Classic_Edition_defconfig | 6 --
 configs/Orangepi_defconfig | 6 --
 configs/Orangepi_mini_defconfig| 6 --
 configs/Sinlinx_SinA31s_defconfig  | 6 --
 configs/Sinlinx_SinA33_defconfig   | 5 -
 configs/Sinovoip_BPI_M2_defconfig  | 6 --
 configs/Sinovoip_BPI_M3_defconfig  | 6 --
 configs/Sunchip_CX-A99_defconfig   | 6 --
 configs/UTOO_P66_defconfig | 6 --
 configs/Wexler_TAB7200_defconfig   | 6 --
 configs/Wits_Pro_A20_DKT_defconfig | 6 --
 configs/Wobo_i5_defconfig  | 6 --
 configs/Yones_Toptech_BD1078_defconfig | 6 --
 configs/Yones_Toptech_BS1078_V2_defconfig  | 6 --
 configs/a64-olinuxino-emmc_defconfig   | 6 --
 configs/a64-olinuxino_defconfig| 6 --
 configs/amarula_a64_relic_defconfig| 6 --
 configs/ba10_tv_box_defconfig  | 6 --
 configs/bananapi_m1_plus_defconfig | 5 -
 configs/bananapi_m2_berry_defconfig| 4 
 configs/bananapi_m2_plus_h3_defconfig  | 6 --
 configs/bananapi_m2_plus_h5_defconfig  | 6 --
 configs/bananapi_m2_zero_defconfig | 4 
 configs/bananapi_m64_defconfig | 6 --
 configs/beelink_gs1_defconfig 

Re: [PATCH] net: bcmgenet: Don't set ID_MODE_DIS when not using RGMII

[Nicolas Saenz Julienne]

On Thu, 2020-02-20 at 17:36 +0100, Nicolas Saenz Julienne wrote:
> As per Linux's driver, ID_MODE_DIS is only set when the PHY interface is
> RGMII. Don't enable it for the rest of setups.
> 
> This has been seen to misconfigure RPi4's PHY when booting Linux.
> 
> Signed-off-by: Nicolas Saenz Julienne 

I forgot to add:

Fixes: d53e3fa385 ("net: Add support for Broadcom GENETv5 Ethernet controller")



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RE: [PATCH v2 11/21] arm: socfpga: Secure register access for clock manager (SoC 64bits)

[Ang, Chee Hong]

> -Original Message-
> From: Marek Vasut 
> Sent: Friday, February 21, 2020 12:48 AM
> To: Ang, Chee Hong ; u-boot@lists.denx.de
> Cc: Simon Goldschmidt ; See, Chin Liang
> ; Tan, Ley Foon ;
> Westergreen, Dalon ; Gong, Richard
> ; Tom Rini ; Michal Simek
> 
> Subject: Re: [PATCH v2 11/21] arm: socfpga: Secure register access for clock
> manager (SoC 64bits)
> 
> On 2/20/20 3:32 AM, Ang, Chee Hong wrote:
> >> On 2/19/20 1:25 PM, chee.hong@intel.com wrote:
> >>> From: Chee Hong Ang 
> >>>
> >>> Allow clock manager driver to access the System Manager's Boot
> >>> Scratch Register 0 in non-secure mode (EL2) on SoC 64bits platform.
> >>>
> >>> Signed-off-by: Chee Hong Ang 
> >>> ---
> >>>  arch/arm/mach-socfpga/clock_manager_agilex.c | 5 +++--
> >>>  arch/arm/mach-socfpga/clock_manager_s10.c| 5 +++--
> >>>  2 files changed, 6 insertions(+), 4 deletions(-)
> >>>
> >>> diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c
> >>> b/arch/arm/mach-socfpga/clock_manager_agilex.c
> >>> index 4ee2b7b..e5a0998 100644
> >>> --- a/arch/arm/mach-socfpga/clock_manager_agilex.c
> >>> +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
> >>> @@ -12,6 +12,7 @@
> >>>  #include   #include   #include
> >>> 
> >>> +#include 
> >>>
> >>>  DECLARE_GLOBAL_DATA_PTR;
> >>>
> >>> @@ -65,8 +66,8 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
> >>>
> >>>  u32 cm_get_qspi_controller_clk_hz(void)
> >>>  {
> >>> - return readl(socfpga_get_sysmgr_addr() +
> >>> -  SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> >>> + return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
> >>> +
> >> SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> >>>  }
> >>>
> >>>  void cm_print_clock_quick_summary(void)
> >>> diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c
> >>> b/arch/arm/mach-socfpga/clock_manager_s10.c
> >>> index 05e4212..02578cc 100644
> >>> --- a/arch/arm/mach-socfpga/clock_manager_s10.c
> >>> +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
> >>> @@ -9,6 +9,7 @@
> >>>  #include   #include
> >>>   #include 
> >>> +#include 
> >>>
> >>>  DECLARE_GLOBAL_DATA_PTR;
> >>>
> >>> @@ -385,8 +386,8 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> >>>
> >>>  unsigned int cm_get_qspi_controller_clk_hz(void)
> >>>  {
> >>> - return readl(socfpga_get_sysmgr_addr() +
> >>> -  SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> >>> + return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
> >>> +
> >> SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> >>>  }
> >>>
> >>>  unsigned int cm_get_spi_controller_clk_hz(void)
> >>
> >> Shouldn't the IO accessors already provide the necessary abstraction ?
> > This function accesses the system manager registers, therefore it is
> > required to call the secure register read function to make sure it
> > still can access the system manager register if it's running EL2 
> > (non-secure).
> 
> But shouldn't the standard IO accessors handle that transparently ?
Regarding this standard IO accessors, please refer to my reply in another email 
thread.
> What does Linux do ?
Currently, Linux run in EL1 (non-secure), it will crash if it's accessing
the secure zones directly with standard memory I/O functions provided
by kernel. 
It goes through the ATF by making SMC/PSCI calls to ATF to access the
secure zones. Just Like what we did in this patchset.
The only difference is kernel code always access those secure zones by making 
SMC/PSCI
calls but U-Boot code get to choose the SMC/PSCI calls or standard I/O 
accessors in compile
time because same code base in U-Boot may run in EL2 or EL3 depending on 
whether the
code is built for SPL (EL3) or U-Boot proper without ATF (EL2).

Re: [PATCH 0/2] sunxi: clean up defconfig files

[Maxime Ripard]

On Thu, Feb 20, 2020 at 05:51:13PM +, Andre Przywara wrote:
> With some recent additions and some old cruft, there are some config
> options that were defined in *almost* every board defconfig file for
> Allwinner SoCs.
> This "almost" seems to point to bugs, either those options were missed by
> mistake or failed to properly synchronise (when a new board defconfig
> comes into the tree and just missed some automatic update).
>
> This series defines those common symbols in their respective Kconfig
> files or in the ARCH_SUNXI definition, then removes them from all the
> defconfigs.
>
> This fixes those boards that suffered from a missing definition, also
> cleans up all board defconfigs by moving not-board-specific options out
> of there.
>
> Rationale for why those options are generic are given in the commit
> message of 1/2.

defconfig handling really is a pain, thanks for taking care of this

Acked-by: Maxime Ripard 
Maxime


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RE: [PATCH v2 10/21] arm: socfpga: Add secure register access helper functions for SoC 64bits

[Ang, Chee Hong]

> On 2/20/20 3:02 AM, Ang, Chee Hong wrote:
> [...]
> >>> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
> >>> +u32 socfpga_secure_reg_read32(phys_addr_t reg_addr); void
> >>> +socfpga_secure_reg_write32(u32 val, phys_addr_t reg_addr); void
> >>> +socfpga_secure_reg_update32(phys_addr_t reg_addr, u32 mask, u32
> >>> +val); #else
> >>> +#define socfpga_secure_reg_read32readl
> >>> +#define socfpga_secure_reg_write32   writel
> >>> +#define socfpga_secure_reg_update32  clrsetbits_le32
> >>> +#endif
> >>
> >> I think I don't understand how this is supposed to work. Would every
> >> place in U- Boot have to be patched to call these functions now ?
> >
> > Not every register access need this. Only those accessing registers in
> > secure zone such as 'System Manager' registers need to call this. It's
> > basically determine whether the driver should issue SMC/PSCI call if
> > it's running in EL2 (non-secure) or access the registers directly by simply 
> > using
> readl/writel and etc if it's running in EL3 (secure).
> > Accessing those registers in secure zone in non-secure mode (EL2) will cause
> SError exception.
> > So we can determine this behaviour in compile time:
> > SPL always running in EL3. So it just simply fallback to use
> readl/writel/clrsetbits_le32.
> >
> > For U-Boot proper (SSBL), there are 2 scenarios:
> > 1) If CONFIG_SPL_ATF is defined, it means ATF is supported. It implies
> > that U-Boot proper will be running in EL2 (non-secure), then it will use
> SMC/PSCI calls to access the secure registers.
> >
> > 2) CONFIG_SPL_ATF is not defined, no ATF support. U-Boot proper will
> > be running in EL3 which will fall back to simply using the direct access 
> > functions
> (readl/writel and etc).
> 
> I would expect the standard IO accessors would or should handle this stuff ?
Standard IO accessors are just general memory read/write functions designed to 
be
compatible with general hardware platforms. Not all platforms have 
secure/non-secure
hardware zones. I don't think they should handle this.

If it's running in EL3 (secure mode) the standard I/O accessors will work just 
fine because
EL3 can access to all secure/non-secure zones. In the header file, you can see 
the secure
I/O accessors will be replaced by the standard I/O accessors if it's built for 
SPL and U-Boot
proper without ATF. Because both are running in EL3 (secure).

If ATF is enabled, SPL will be still running in EL3 but U-Boot proper will be 
running in
EL2 (non-secure). If any code accessing those secure zones without going 
through ATF
(making SMC/PSCI calls to EL3), it will trigger 'SError' exceptions and crash 
the U-Boot.

[PATCH 1/2] sunxi: Move common defconfig options to Kconfig

[Andre Przywara]

Some config symbols are found in *almost* every _defconfig file for
Allwinner boards, because those options are actually a platform choice,
and not a per-board decision.
Some of these options are older, some have recently been added.

Move those options to be set for all Allwinner boards in their
respective Kconfig files.

The rationales are as follows:
- NR_DRAM_BANKS: All Allwinner SoC map DRAM at one contiguous region of
  address space only, starting at 1 GB. So it's always one bank.
- SPL_{DOS,EFI}_PARTITION: The Allwinner SPL does only support raw MMC
  accesses, we don't care about filesystems or partitions in there, so
  there is no need to define those symbols at all.
- USE_PREBOOT: We start USB early when a keyboard is configured, using the
  preboot env variable, so we need to set this variable.
- SYS_RELOC_GD_ENV_ADDR: We don't specify any ENV_ADDR, so need this
  symbol to be set (according to 8d8ee47e03e).
- SYS_USB_EVENT_POLL_VIA_INT_QUEUE: According to commit eab9433aa55428,
  specifying this reduces the latency of the USB keyboard handling, so
  this was formerly enabled in config headers for all Allwinner boards.

Signed-off-by: Andre Przywara 
---
 Kconfig | 1 +
 arch/arm/Kconfig| 2 ++
 disk/Kconfig| 2 ++
 drivers/usb/Kconfig | 1 +
 4 files changed, 6 insertions(+)

diff --git a/Kconfig b/Kconfig
index 66148ce477..b4864cdf8d 100644
--- a/Kconfig
+++ b/Kconfig
@@ -115,6 +115,7 @@ config ENV_VARS_UBOOT_CONFIG
 
 config NR_DRAM_BANKS
int "Number of DRAM banks"
+   default 1 if ARCH_SUNXI
default 4
help
  This defines the number of DRAM banks.
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8d9f7fcce7..02378b4fae 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -999,6 +999,8 @@ config ARCH_SUNXI
select USB_KEYBOARD if DISTRO_DEFAULTS
select USB_STORAGE if DISTRO_DEFAULTS
select SPL_USE_TINY_PRINTF
+   select USE_PREBOOT
+   select SYS_RELOC_GD_ENV_ADDR
imply CMD_DM
imply CMD_GPT
imply CMD_UBI if MTD_RAW_NAND
diff --git a/disk/Kconfig b/disk/Kconfig
index 28fb81c2ee..747275c2ba 100644
--- a/disk/Kconfig
+++ b/disk/Kconfig
@@ -46,6 +46,7 @@ config DOS_PARTITION
 config SPL_DOS_PARTITION
bool "Enable MS Dos partition table for SPL"
depends on SPL && PARTITIONS
+   default n if ARCH_SUNXI
default y if DOS_PARTITION
 
 config ISO_PARTITION
@@ -112,6 +113,7 @@ config EFI_PARTITION_ENTRIES_OFF
 config SPL_EFI_PARTITION
bool "Enable EFI GPT partition table for SPL"
depends on  SPL && PARTITIONS
+   default n if ARCH_SUNXI
default y if EFI_PARTITION
 
 config PARTITION_UUIDS
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index bea4a92b61..928a89133c 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -108,6 +108,7 @@ config USB_KEYBOARD_FN_KEYS
 
 choice
prompt "USB keyboard polling"
+   default SYS_USB_EVENT_POLL_VIA_INT_QUEUE if ARCH_SUNXI
default SYS_USB_EVENT_POLL
---help---
  Enable a polling mechanism for USB keyboard.
-- 
2.17.1

[PATCH 0/2] sunxi: clean up defconfig files

[Andre Przywara]

With some recent additions and some old cruft, there are some config
options that were defined in *almost* every board defconfig file for
Allwinner SoCs.
This "almost" seems to point to bugs, either those options were missed by
mistake or failed to properly synchronise (when a new board defconfig
comes into the tree and just missed some automatic update).

This series defines those common symbols in their respective Kconfig
files or in the ARCH_SUNXI definition, then removes them from all the
defconfigs.

This fixes those boards that suffered from a missing definition, also
cleans up all board defconfigs by moving not-board-specific options out
of there.

Rationale for why those options are generic are given in the commit
message of 1/2.

Cheers,
Andre

Andre Przywara (2):
  sunxi: Move common defconfig options to Kconfig
  sunxi: Remove no longer needed default options from defconfigs

 Kconfig| 1 +
 arch/arm/Kconfig   | 2 ++
 configs/A10-OLinuXino-Lime_defconfig   | 6 --
 configs/A10s-OLinuXino-M_defconfig | 6 --
 configs/A13-OLinuXinoM_defconfig   | 6 --
 configs/A13-OLinuXino_defconfig| 5 -
 configs/A20-OLinuXino-Lime2-eMMC_defconfig | 5 -
 configs/A20-OLinuXino-Lime2_defconfig  | 5 -
 configs/A20-OLinuXino-Lime_defconfig   | 6 --
 configs/A20-OLinuXino_MICRO-eMMC_defconfig | 6 --
 configs/A20-OLinuXino_MICRO_defconfig  | 6 --
 configs/A20-Olimex-SOM-EVB_defconfig   | 6 --
 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig   | 5 -
 configs/A20-Olimex-SOM204-EVB_defconfig| 5 -
 configs/A33-OLinuXino_defconfig| 6 --
 configs/Ainol_AW1_defconfig| 6 --
 configs/Ampe_A76_defconfig | 6 --
 configs/Auxtek-T003_defconfig  | 6 --
 configs/Auxtek-T004_defconfig  | 6 --
 configs/Bananapi_M2_Ultra_defconfig| 4 
 configs/Bananapi_defconfig | 6 --
 configs/Bananapi_m2m_defconfig | 4 
 configs/Bananapro_defconfig| 6 --
 configs/CHIP_defconfig | 6 --
 configs/CHIP_pro_defconfig | 4 
 configs/CSQ_CS908_defconfig| 6 --
 configs/Chuwi_V7_CW0825_defconfig  | 6 --
 configs/Colombus_defconfig | 6 --
 configs/Cubieboard2_defconfig  | 6 --
 configs/Cubieboard4_defconfig  | 6 --
 configs/Cubieboard_defconfig   | 6 --
 configs/Cubietruck_defconfig   | 5 -
 configs/Cubietruck_plus_defconfig  | 6 --
 configs/Empire_electronix_d709_defconfig   | 6 --
 configs/Empire_electronix_m712_defconfig   | 6 --
 configs/Hummingbird_A31_defconfig  | 6 --
 configs/Hyundai_A7HD_defconfig | 6 --
 configs/Itead_Ibox_A20_defconfig   | 6 --
 configs/Lamobo_R1_defconfig| 6 --
 configs/LicheePi_Zero_defconfig| 6 --
 configs/Linksprite_pcDuino3_Nano_defconfig | 6 --
 configs/Linksprite_pcDuino3_defconfig  | 6 --
 configs/Linksprite_pcDuino_defconfig   | 6 --
 configs/MK808C_defconfig   | 6 --
 configs/MSI_Primo73_defconfig  | 6 --
 configs/MSI_Primo81_defconfig  | 6 --
 configs/Marsboard_A10_defconfig| 6 --
 configs/Mele_A1000G_quad_defconfig | 6 --
 configs/Mele_A1000_defconfig   | 6 --
 configs/Mele_I7_defconfig  | 6 --
 configs/Mele_M3_defconfig  | 6 --
 configs/Mele_M5_defconfig  | 6 --
 configs/Mele_M9_defconfig  | 6 --
 configs/Merrii_A80_Optimus_defconfig   | 6 --
 configs/Mini-X_defconfig   | 6 --
 configs/Nintendo_NES_Classic_Edition_defconfig | 6 --
 configs/Orangepi_defconfig | 6 --
 configs/Orangepi_mini_defconfig| 6 --
 configs/Sinlinx_SinA31s_defconfig  | 6 --
 configs/Sinlinx_SinA33_defconfig   | 5 -
 configs/Sinovoip_BPI_M2_defconfig  | 6 --
 configs/Sinovoip_BPI_M3_defconfig  | 6 --
 configs/Sunchip_CX-A99_defconfig   | 6 --
 configs/UTOO_P66_defconfig | 6 --
 configs/Wexler_TAB7200_defconfig   | 6 --
 configs/Wits_Pro_A20_DKT_defconfig | 6 --
 configs/Wobo_i5_defconfig  | 6 --
 configs/Yones_Toptech_BD1078_defconfig | 6 --
 configs/Yones_Toptech_BS1078_V2_defconfig  | 6 --
 configs/a64-olinuxino-emmc_defconfig   | 

Re: [RFC PATCH 03/10] i2c: mmc: add nexell driver (gpio, i2c, mmc, pwm)

[Stefan B.]

Hello Heiko,

see below my feedback, please give me further advise where indicated.

Unfortunately there have been some Bugs in the i2c-driver and I learned 
that this driver has not been used at all ("i2c-gpio" has been used 
instead). So I have done several Bugfixes and improvements appart from 
your proposals.



Regards
Stefan


Am 04.02.20 um 07:58 schrieb Heiko Schocher:

Hello Stefan,

Am 03.02.2020 um 21:40 schrieb Stefan Bosch:

Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- i2c/nx_i2c.c: Some adaptions mainly because of changes in
   "struct udevice".
- mmc: nexell_dw_mmc.c changed to nexell_dw_mmc_dm.c (switched to DM).

Signed-off-by: Stefan Bosch 
---

  drivers/gpio/Kconfig   |   9 +
  drivers/gpio/Makefile  |   1 +
  drivers/gpio/nx_gpio.c | 252 +++
  drivers/i2c/Kconfig    |   9 +
  drivers/i2c/Makefile   |   1 +
  drivers/i2c/nx_i2c.c   | 537 
+

  drivers/mmc/Kconfig    |   6 +
  drivers/mmc/Makefile   |   1 +
  drivers/mmc/nexell_dw_mmc_dm.c | 350 +++
  drivers/pwm/Makefile   |   1 +
  drivers/pwm/pwm-nexell.c   | 252 +++
  drivers/pwm/pwm-nexell.h   |  54 +


Could you please split this patch into 4 parts (i2c, gpio, mmc and
pwm) ?

Thanks!


Ok, I will split this patch.


  12 files changed, 1473 insertions(+)
  create mode 100644 drivers/gpio/nx_gpio.c
  create mode 100644 drivers/i2c/nx_i2c.c
  create mode 100644 drivers/mmc/nexell_dw_mmc_dm.c
  create mode 100644 drivers/pwm/pwm-nexell.c
  create mode 100644 drivers/pwm/pwm-nexell.h


[...]

diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 449046b..e3340de 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -65,3 +65,4 @@ obj-$(CONFIG_PM8916_GPIO)    += pm8916_gpio.o
  obj-$(CONFIG_MT7621_GPIO)    += mt7621_gpio.o
  obj-$(CONFIG_MSCC_SGPIO)    += mscc_sgpio.o
  obj-$(CONFIG_SIFIVE_GPIO)    += sifive-gpio.o
+obj-$(CONFIG_NX_GPIO)    += nx_gpio.o


Please keep lists sorted.


The list is not sorted (at least in no alphabetical order), but I can 
e.g. move "... += nx_gpio.o" one line up?





diff --git a/drivers/gpio/nx_gpio.c b/drivers/gpio/nx_gpio.c
new file mode 100644
index 000..86472f6
--- /dev/null
+++ b/drivers/gpio/nx_gpio.c
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Nexell
+ * DeokJin, Lee 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct nx_gpio_regs {
+    u32    data;    /* Data register */
+    u32    outputenb;    /* Output Enable register */
+    u32    detmode[2];    /* Detect Mode Register */
+    u32    intenb;    /* Interrupt Enable Register */
+    u32    det;    /* Event Detect Register */
+    u32    pad;    /* Pad Status Register */
+};
+
+struct nx_alive_gpio_regs {
+    u32    pwrgate;    /* Power Gating Register */
+    u32    reserved0[28];    /* Reserved0 */
+    u32    outputenb_reset;/* Alive GPIO Output Enable Reset Register */
+    u32    outputenb;    /* Alive GPIO Output Enable Register */
+    u32    outputenb_read; /* Alive GPIO Output Read Register */
+    u32    reserved1[3];    /* Reserved1 */
+    u32    pad_reset;    /* Alive GPIO Output Reset Register */
+    u32    data;    /* Alive GPIO Output Register */
+    u32    pad_read;    /* Alive GPIO Pad Read Register */
+    u32    reserved2[33];    /* Reserved2 */
+    u32    pad;    /* Alive GPIO Input Value Register */
+};
+
+struct nx_gpio_platdata {
+    void *regs;
+    int gpio_count;
+    const char *bank_name;
+};
+
+static int nx_alive_gpio_is_check(struct udevice *dev)
+{
+    struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+    const char *bank_name = plat->bank_name;
+
+    if (!strcmp(bank_name, "gpio_alv"))
+    return 1;
+
+    return 0;
+}
+
+static int nx_alive_gpio_direction_input(struct udevice *dev, 
unsigned int pin)

+{
+    struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+    struct nx_alive_gpio_regs *const regs = plat->regs;
+
+    setbits_le32(>outputenb_reset, 1 << pin);
+
+    return 0;
+}
+
+static int nx_alive_gpio_direction_output(struct udevice *dev, 
unsigned int pin,

+  int val)
+{
+    struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+    struct nx_alive_gpio_regs *const regs = plat->regs;
+
+    if (val)
+    setbits_le32(>data, 1 << pin);
+    else
+    setbits_le32(>pad_reset, 1 << pin);
+
+    setbits_le32(>outputenb, 1 << pin);
+
+    return 0;
+}
+
+static int nx_alive_gpio_get_value(struct udevice *dev, unsigned int 
pin)

+{
+    struct nx_gpio_platdata *plat = dev_get_platdata(dev);
+    struct nx_alive_gpio_regs *const regs = plat->regs;
+    unsigned int mask = 1UL << pin;
+    unsigned int value;
+
+    value = (readl(>pad_read) & mask) >> pin;
+
+    return value;
+}
+
+static int 

[Patch v5 7/7] treewide: Update fsl qspi node dt properties as per spi-mem driver

[Kuldeep Singh]

According to new qspi driver, some properties like "bus-num, num-cs,
big-endian" are no longer used. Device endiannes can be determined from
device-type data in driver.

Now use board specific compatibles, generic node names and specific
labels to align with linux device-tree properties.

Also consolidate spi-max-frequency to 50Mhz treewide.

Signed-off-by: Kuldeep Singh 
---
v5: No change
v4: No change
v3: No change
v2: No change

 arch/arm/dts/fsl-ls1012a-2g5rdb.dts   | 5 ++---
 arch/arm/dts/fsl-ls1012a-frdm.dtsi| 5 ++---
 arch/arm/dts/fsl-ls1012a-qds.dtsi | 5 ++---
 arch/arm/dts/fsl-ls1012a-rdb.dtsi | 5 ++---
 arch/arm/dts/fsl-ls1012a.dtsi | 4 +---
 arch/arm/dts/fsl-ls1043a-qds.dtsi | 5 ++---
 arch/arm/dts/fsl-ls1043a.dtsi | 6 ++
 arch/arm/dts/fsl-ls1046a-frwy.dts | 5 ++---
 arch/arm/dts/fsl-ls1046a-qds.dtsi | 5 ++---
 arch/arm/dts/fsl-ls1046a-rdb.dts  | 5 ++---
 arch/arm/dts/fsl-ls1046a.dtsi | 4 +---
 arch/arm/dts/fsl-ls1088a-qds.dts  | 5 ++---
 arch/arm/dts/fsl-ls1088a-rdb.dts  | 5 ++---
 arch/arm/dts/fsl-ls1088a.dtsi | 2 +-
 arch/arm/dts/fsl-ls2080a-qds.dts  | 5 ++---
 arch/arm/dts/fsl-ls2080a.dtsi | 4 ++--
 arch/arm/dts/fsl-ls2088a-rdb-qspi.dts | 5 ++---
 arch/arm/dts/ls1021a-twr.dtsi | 5 ++---
 arch/arm/dts/ls1021a.dtsi | 6 ++
 19 files changed, 35 insertions(+), 56 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts 
b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
index fecef88..6402cf5 100644
--- a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
+++ b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
@@ -21,14 +21,13 @@
 };
 
  {
-   bus-num = <0>;
status = "okay";
 
-   qflash0: s25fl128s@0 {
+   s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
-   spi-max-frequency = <2000>;
+   spi-max-frequency = <5000>;
reg = <0>;
};
 };
diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dtsi 
b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
index a357793..88aa24a 100644
--- a/arch/arm/dts/fsl-ls1012a-frdm.dtsi
+++ b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
@@ -15,14 +15,13 @@
 };
 
  {
-   bus-num = <0>;
status = "okay";
 
-   qflash0: s25fl128s@0 {
+   s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
-   spi-max-frequency = <2000>;
+   spi-max-frequency = <5000>;
reg = <0>;
};
 };
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi 
b/arch/arm/dts/fsl-ls1012a-qds.dtsi
index a330597..910d2a5 100644
--- a/arch/arm/dts/fsl-ls1012a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi
@@ -43,14 +43,13 @@
 };
 
  {
-   bus-num = <0>;
status = "okay";
 
-   qflash0: s25fl128s@0 {
+   s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
-   spi-max-frequency = <2000>;
+   spi-max-frequency = <5000>;
reg = <0>;
};
 };
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi 
b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
index 55155fd..3757051 100644
--- a/arch/arm/dts/fsl-ls1012a-rdb.dtsi
+++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
@@ -19,14 +19,13 @@
 };
 
  {
-   bus-num = <0>;
status = "okay";
 
-   qflash0: s25fl128s@0 {
+   s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
-   spi-max-frequency = <2000>;
+   spi-max-frequency = <5000>;
reg = <0>;
};
 };
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 1125e57..2d70c82 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -107,14 +107,12 @@
};
 
qspi: quadspi@155 {
-   compatible = "fsl,vf610-qspi";
+   compatible = "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x155 0x0 0x1>,
<0x0 0x4000 0x0 0x400>;
reg-names = "QuadSPI", "QuadSPI-memory";
-   num-cs = <1>;
-   big-endian;
status = "disabled";
};
 
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi 
b/arch/arm/dts/fsl-ls1043a-qds.dtsi
index 70e1a6a..884bdad 100644
--- a/arch/arm/dts/fsl-ls1043a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi
@@ -53,14 +53,13 @@
 };
 
  {
-   bus-num = <0>;
status = "okay";
 
-   qflash0: s25fl128s@0 {
+   s25fl128s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
 

[Patch v5 5/7] configs: ls1012a: Enable CONFIG_SPI_FLASH_SPANSION in defconfigs

[Kuldeep Singh]

Since CONFIG_FSL_QSPI is already enabled for LS1012A in defconfigs. Also
enable CONFIG_SPI_FLASH_SPANSION for LS1012A boards having spansion
flashes.

Signed-off-by: Ashish Kumar 
Signed-off-by: Kuldeep Singh 
---
v5: No change
v4: Reword commit message. Add "in defconfigs"
v3: Reword commit message.
v2: No change

 configs/ls1012a2g5rdb_qspi_defconfig  | 1 +
 configs/ls1012a2g5rdb_tfa_defconfig   | 1 +
 configs/ls1012afrdm_qspi_defconfig| 1 +
 configs/ls1012afrdm_tfa_defconfig | 1 +
 configs/ls1012aqds_qspi_defconfig | 1 +
 configs/ls1012aqds_tfa_SECURE_BOOT_defconfig  | 1 +
 configs/ls1012aqds_tfa_defconfig  | 1 +
 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 1 +
 configs/ls1012ardb_qspi_defconfig | 1 +
 configs/ls1012ardb_tfa_SECURE_BOOT_defconfig  | 1 +
 configs/ls1012ardb_tfa_defconfig  | 1 +
 include/configs/ls1012a_common.h  | 1 -
 12 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/configs/ls1012a2g5rdb_qspi_defconfig 
b/configs/ls1012a2g5rdb_qspi_defconfig
index b1cf8ef..174084c 100644
--- a/configs/ls1012a2g5rdb_qspi_defconfig
+++ b/configs/ls1012a2g5rdb_qspi_defconfig
@@ -42,6 +42,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_FSL_PFE=y
 CONFIG_DM_ETH=y
diff --git a/configs/ls1012a2g5rdb_tfa_defconfig 
b/configs/ls1012a2g5rdb_tfa_defconfig
index a978580..3e954bd 100644
--- a/configs/ls1012a2g5rdb_tfa_defconfig
+++ b/configs/ls1012a2g5rdb_tfa_defconfig
@@ -42,6 +42,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_FSL_PFE=y
 CONFIG_DM_ETH=y
diff --git a/configs/ls1012afrdm_qspi_defconfig 
b/configs/ls1012afrdm_qspi_defconfig
index 11d0cee..fcb8367 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -38,6 +38,7 @@ CONFIG_DM_I2C=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_FSL_PFE=y
 CONFIG_DM_ETH=y
diff --git a/configs/ls1012afrdm_tfa_defconfig 
b/configs/ls1012afrdm_tfa_defconfig
index 2818bdf..08d08e9 100644
--- a/configs/ls1012afrdm_tfa_defconfig
+++ b/configs/ls1012afrdm_tfa_defconfig
@@ -38,6 +38,7 @@ CONFIG_DM_I2C=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_FSL_PFE=y
 CONFIG_DM_ETH=y
diff --git a/configs/ls1012aqds_qspi_defconfig 
b/configs/ls1012aqds_qspi_defconfig
index fd4fba5..081735b 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -58,6 +58,7 @@ CONFIG_SF_DEFAULT_BUS=1
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=1000
 # CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_FSL_PFE=y
 CONFIG_DM_ETH=y
diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig 
b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
index 23dea4c..df1e51a 100644
--- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
@@ -47,6 +47,7 @@ CONFIG_SF_DEFAULT_BUS=1
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=1000
 # CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_FSL_PFE=y
 CONFIG_DM_ETH=y
diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig
index 974cedc..9e942d1 100644
--- a/configs/ls1012aqds_tfa_defconfig
+++ b/configs/ls1012aqds_tfa_defconfig
@@ -58,6 +58,7 @@ CONFIG_SF_DEFAULT_BUS=1
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=1000
 # CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_FSL_PFE=y
 CONFIG_DM_ETH=y
diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig 
b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
index 5ad4e0d..2d661f8 100644
--- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
@@ -42,6 +42,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_E1000=y
 CONFIG_PCI=y
diff --git a/configs/ls1012ardb_qspi_defconfig 
b/configs/ls1012ardb_qspi_defconfig
index 98057a9..2f74226 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -44,6 +44,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_FSL_PFE=y
 CONFIG_DM_ETH=y
diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig 

[Patch v5 2/7] treewide: Remove unused FSL QSPI config options for Layerscape platforms

[Kuldeep Singh]

Some of these options are not used by the driver anymore and some of
them are obsolete as the information is gathered from the dt.
Also consolidating defines in common headers.

Signed-off-by: Frieder Schrempf 
Signed-off-by: Ashish Kumar 
Signed-off-by: Kuldeep Singh 
---
v5: Keep only layerscape changes. Splitting into 2 patches.
v4: Remove buildman failure by removing #endif in LS2080AQDS
v3: No change
v2: No change

 arch/arm/include/asm/arch-fsl-layerscape/config.h |  1 -
 arch/arm/include/asm/arch-ls102xa/config.h|  1 -
 include/configs/ls1012a_common.h  | 16 +---
 include/configs/ls1012afrwy.h |  3 ---
 include/configs/ls1012ardb.h  |  3 ---
 include/configs/ls1021aiot.h  |  6 --
 include/configs/ls1021aqds.h  | 11 ---
 include/configs/ls1021atwr.h  | 10 --
 include/configs/ls1043aqds.h  |  2 --
 include/configs/ls1046afrwy.h |  9 -
 include/configs/ls1046aqds.h  | 11 ---
 include/configs/ls1046ardb.h  | 13 -
 include/configs/ls1088a_common.h  |  6 --
 include/configs/ls1088aqds.h  |  8 
 include/configs/ls1088ardb.h  | 18 --
 include/configs/ls2080aqds.h  |  5 -
 include/configs/ls2080ardb.h  |  6 +-
 17 files changed, 2 insertions(+), 127 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index ddd9390..cf2abda 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -306,7 +306,6 @@
 #define CONFIG_SYS_FSL_ESDHC_BE
 #define CONFIG_SYS_FSL_WDOG_BE
 #define CONFIG_SYS_FSL_DSPI_BE
-#define CONFIG_SYS_FSL_QSPI_BE
 #define CONFIG_SYS_FSL_CCSR_GUR_BE
 #define CONFIG_SYS_FSL_PEX_LUT_BE
 
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index 9705378..3884948 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -94,7 +94,6 @@
 #define CONFIG_SYS_FSL_ESDHC_BE
 #define CONFIG_SYS_FSL_WDOG_BE
 #define CONFIG_SYS_FSL_DSPI_BE
-#define CONFIG_SYS_FSL_QSPI_BE
 #define CONFIG_SYS_FSL_DCU_BE
 #define CONFIG_SYS_FSL_SEC_MON_LE
 #define CONFIG_SYS_FSL_SFP_VER_3_2
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index e9baa2a..14d2483 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -37,23 +37,9 @@
 #define CONFIG_SYS_MALLOC_LEN  (CONFIG_ENV_SIZE + 128 * 1024)
 
 /*SPI device */
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_TFABOOT)
 #define CONFIG_SYS_FMAN_FW_ADDR0x400d
+#define CONFIG_SYS_FSL_QSPI_BASE   0x4000
 #define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_FSL_SPI_INTERFACE
-#define CONFIG_SF_DATAFLASH
-
-#define QSPI0_AMBA_BASE0x4000
-#define CONFIG_SPI_FLASH_SPANSION
-
-#define FSL_QSPI_FLASH_SIZESZ_64M
-#define FSL_QSPI_FLASH_NUM 2
-
-/*
- * Environment
- */
-#define CONFIG_ENV_OVERWRITE
-#endif
 
 /* SATA */
 #define CONFIG_SCSI_AHCI_PLAT
diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h
index dde4369..0442e34 100644
--- a/include/configs/ls1012afrwy.h
+++ b/include/configs/ls1012afrwy.h
@@ -33,9 +33,6 @@
func(USB, usb, 0)
 #endif
 
-#undef FSL_QSPI_FLASH_SIZE
-#define FSL_QSPI_FLASH_SIZESZ_16M
-
 /*  MMC  */
 #ifdef CONFIG_MMC
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index 0738b24..f335a64 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -17,9 +17,6 @@
 #define CONFIG_SYS_MEMTEST_START   0x8000
 #define CONFIG_SYS_MEMTEST_END 0x9fff
 
-
-/* ENV */
-#define CONFIG_SYS_FSL_QSPI_BASE   0x4000
 /*
  * I2C IO expander
  */
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
index 1d218aa..4176c36 100644
--- a/include/configs/ls1021aiot.h
+++ b/include/configs/ls1021aiot.h
@@ -138,12 +138,6 @@
 /* SPI */
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_SPI_FLASH_SPANSION
-
-/* QSPI */
-#define QSPI0_AMBA_BASE0x4000
-#define FSL_QSPI_FLASH_SIZE(1 << 24)
-#define FSL_QSPI_FLASH_NUM 2
-#define CONFIG_SPI_FLASH_SPANSION
 #endif
 
 /* DM SPI */
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 8bac2d2..e494355 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -363,20 +363,9 @@ unsigned long get_board_ddr_clk(void);
  * MMC
  */
 
-/* SPI */
-#if defined(CONFIG_QSPI_BOOT) || 

[Patch v5 1/7] spi: Transform the FSL QuadSPI driver to use the SPI MEM API

[Kuldeep Singh]

To support the SPI MEM API, instead of modifying the existing U-Boot
driver, this patch adds a port of the existing Linux driver.
This also has the advantage that porting changes and fixes from Linux will
be easier.
Porting of driver left most of the functions unchanged while few of the
changes are:
-Remove lock(mutexes) and irq handler as u-boot is a single core execution.
-Remove invalid masterid as it was required specially for multicore
execution in LS2088ARDB which is not the case in u-boot.
-Remove clock support as changing spi speed is not supported in uboot and
nor in linux.

Currently tested on LS1088ARDB, LS1012ARDB, LS1046ARDB, LS1046AFRWY,
LS1043AQDS, LS1021ATWR, LS2088ARDB, I.MX6ULL EVK.

Signed-off-by: Frieder Schrempf 
Signed-off-by: Ashish Kumar 
Signed-off-by: Kuldeep Singh 
Reviewed-by: Stefan Roese 
Tested-by: Stefan Roese 
Acked-by: Vignesh Raghavendra 
---
v5: Remove compilation warning/error. No other change.
v4: Add i.mx among tested boards
v3: Use 1k size to make driver independent of flash size.
v2: Merge removal of old driver and addition of new driver in single patch

 drivers/spi/fsl_qspi.c | 1577 +++-
 drivers/spi/fsl_qspi.h |  145 -
 2 files changed, 608 insertions(+), 1114 deletions(-)
 delete mode 100644 drivers/spi/fsl_qspi.h

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 8e2a09d..ee2c8b6 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -1,1142 +1,781 @@
 // SPDX-License-Identifier: GPL-2.0+
+
 /*
- * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ * Freescale QuadSPI driver.
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2018 Bootlin
+ * Copyright (C) 2018 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright 2019-2020 NXP
+ *
+ * This driver is a ported version of Linux Freescale QSPI driver taken from
+ * v5.5-rc1 tag having following information.
  *
- * Freescale Quad Serial Peripheral Interface (QSPI) driver
+ * Transition to SPI MEM interface:
+ * Authors:
+ * Boris Brezillon 
+ * Frieder Schrempf 
+ * Yogesh Gaur 
+ * Suresh Gupta 
+ *
+ * Based on the original fsl-quadspi.c spi-nor driver.
+ * Transition to spi-mem in spi-fsl-qspi.c
  */
 
 #include 
-#include 
-#include 
 #include 
-#include 
-#include 
 #include 
-#include 
-#include 
-#include 
-#include "fsl_qspi.h"
+#include 
+#include 
+#include 
+#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define OFFSET_BITS_MASK   GENMASK(23, 0)
-
-#define FLASH_STATUS_WEL   0x02
-
-/* SEQID */
-#define SEQID_WREN 1
-#define SEQID_FAST_READ2
-#define SEQID_RDSR 3
-#define SEQID_SE   4
-#define SEQID_CHIP_ERASE   5
-#define SEQID_PP   6
-#define SEQID_RDID 7
-#define SEQID_BE_4K8
-#ifdef CONFIG_SPI_FLASH_BAR
-#define SEQID_BRRD 9
-#define SEQID_BRWR 10
-#define SEQID_RDEAR11
-#define SEQID_WREAR12
-#endif
-#define SEQID_WRAR 13
-#define SEQID_RDAR 14
-
-/* QSPI CMD */
-#define QSPI_CMD_PP0x02/* Page program (up to 256 bytes) */
-#define QSPI_CMD_RDSR  0x05/* Read status register */
-#define QSPI_CMD_WREN  0x06/* Write enable */
-#define QSPI_CMD_FAST_READ 0x0b/* Read data bytes (high frequency) */
-#define QSPI_CMD_BE_4K 0x20/* 4K erase */
-#define QSPI_CMD_CHIP_ERASE0xc7/* Erase whole flash chip */
-#define QSPI_CMD_SE0xd8/* Sector erase (usually 64KiB) */
-#define QSPI_CMD_RDID  0x9f/* Read JEDEC ID */
-
-/* Used for Micron, winbond and Macronix flashes */
-#defineQSPI_CMD_WREAR  0xc5/* EAR register write */
-#defineQSPI_CMD_RDEAR  0xc8/* EAR reigster read */
-
-/* Used for Spansion flashes only. */
-#defineQSPI_CMD_BRRD   0x16/* Bank register read */
-#defineQSPI_CMD_BRWR   0x17/* Bank register write */
-
-/* Used for Spansion S25FS-S family flash only. */
-#define QSPI_CMD_RDAR  0x65/* Read any device register */
-#define QSPI_CMD_WRAR  0x71/* Write any device register */
-
-/* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
-#define QSPI_CMD_FAST_READ_4B  0x0c/* Read data bytes (high frequency) */
-#define QSPI_CMD_PP_4B 0x12/* Page program (up to 256 bytes) */
-#define QSPI_CMD_SE_4B 0xdc/* Sector erase (usually 64KiB) */
-
-/* fsl_qspi_platdata flags */
-#define QSPI_FLAG_REGMAP_ENDIAN_BIGBIT(0)
-
-/* default SCK frequency, unit: HZ */
-#define FSL_QSPI_DEFAULT_SCK_FREQ  5000
-
-/* QSPI max chipselect signals number */
-#define FSL_QSPI_MAX_CHIPSELECT_NUM 4
-
-/* Controller needs driver to swap endian */
+/*
+ * The driver only uses one single LUT entry, that is updated on
+ * each call of exec_op(). Index 0 is 

[Patch v5 6/7] configs: ls1046a: Move SPI_FLASH_SPANSION to defconfig

[Kuldeep Singh]

Enable CONFIG_SPI_FLASH_SPANSION in defconfigs of LS1046ARDB and
LS1046AQDS which have two spansion flases i.e s25fs512s each of size
64M.

Signed-off-by: Kuldeep Singh 
---
v5: No change
v4: No change
v3: No change
v2: No change

 configs/ls1046aqds_qspi_defconfig | 1 +
 configs/ls1046aqds_sdcard_qspi_defconfig  | 1 +
 configs/ls1046aqds_tfa_SECURE_BOOT_defconfig  | 1 +
 configs/ls1046aqds_tfa_defconfig  | 1 +
 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 1 +
 configs/ls1046ardb_qspi_defconfig | 1 +
 configs/ls1046ardb_tfa_SECURE_BOOT_defconfig  | 1 +
 configs/ls1046ardb_tfa_defconfig  | 1 +
 include/configs/ls1046aqds.h  | 8 
 include/configs/ls1046ardb.h  | 7 ---
 10 files changed, 8 insertions(+), 15 deletions(-)

diff --git a/configs/ls1046aqds_qspi_defconfig 
b/configs/ls1046aqds_qspi_defconfig
index d6253c7..22904a0 100644
--- a/configs/ls1046aqds_qspi_defconfig
+++ b/configs/ls1046aqds_qspi_defconfig
@@ -38,6 +38,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 # CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig 
b/configs/ls1046aqds_sdcard_qspi_defconfig
index 3571a6f..3d74bf0 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -54,6 +54,7 @@ CONFIG_FSL_CAAM=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 # CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig 
b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
index e173747..0edbac3 100644
--- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
@@ -43,6 +43,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig
index 824fc51..df85533 100644
--- a/configs/ls1046aqds_tfa_defconfig
+++ b/configs/ls1046aqds_tfa_defconfig
@@ -53,6 +53,7 @@ CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_SF_DEFAULT_BUS=1
 # CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig 
b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
index aff9bf8..d4e940c 100644
--- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
@@ -34,6 +34,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
 # CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
diff --git a/configs/ls1046ardb_qspi_defconfig 
b/configs/ls1046ardb_qspi_defconfig
index b482e73..d5e0f02 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -37,6 +37,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
 # CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig 
b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
index 1dde0ae..441cee7 100644
--- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
@@ -34,6 +34,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
 # CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig
index 280ca83..89f7b3f 100644
--- a/configs/ls1046ardb_tfa_defconfig
+++ b/configs/ls1046ardb_tfa_defconfig
@@ -39,6 +39,7 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
 # CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 437b6ac..8d74f32 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -41,14 +41,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SPI_FLASH_EON   /* cs2 */
 #endif
 
-/* QSPI */
-#if defined(CONFIG_TFABOOT) || \
-   defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
-#endif
-#endif
-
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 61a4a40..6db48f7 100644
--- a/include/configs/ls1046ardb.h
+++ 

[Patch v5 4/7] configs: ls1043a: Move CONFIG_FSL_QSPI and SPI_FLASH_SPANSION to defconfig

[Kuldeep Singh]

Move CONFIG_FSL_QSPI to the board defconfigs and while at it also move
CONFIG_SPI_FLASH_SPANSION for LS1043AQDS.

Signed-off-by: Frieder Schrempf 
Signed-off-by: Kuldeep Singh 
---
v5: No change
v4: Move SPI_FLASH_SPANSION to defconfig
v3: no change
v2: No change

 configs/ls1043aqds_qspi_defconfig| 1 +
 configs/ls1043aqds_sdcard_qspi_defconfig | 1 +
 configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 ++
 configs/ls1043aqds_tfa_defconfig | 1 +
 include/configs/ls1043aqds.h | 8 
 5 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/configs/ls1043aqds_qspi_defconfig 
b/configs/ls1043aqds_qspi_defconfig
index 86b2eb5..859db47 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -40,6 +40,7 @@ CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig 
b/configs/ls1043aqds_sdcard_qspi_defconfig
index 0449469..be24948 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -54,6 +54,7 @@ CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig 
b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
index 0ece698..5075436 100644
--- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
@@ -44,6 +44,7 @@ CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
@@ -55,6 +56,7 @@ CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig
index 24db72a..1e529be 100644
--- a/configs/ls1043aqds_tfa_defconfig
+++ b/configs/ls1043aqds_tfa_defconfig
@@ -54,6 +54,7 @@ CONFIG_MTD_RAW_NAND=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
 # CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 063e724..fef5a2e 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -379,14 +379,6 @@ unsigned long get_board_ddr_clk(void);
 #define VDD_MV_MIN 819
 #define VDD_MV_MAX 1212
 
-/* QSPI device */
-#if defined(CONFIG_TFABOOT) || \
-   (defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI))
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
-#endif
-#endif
-
 /*
  * Miscellaneous configurable options
  */
-- 
2.7.4

[Patch v5 3/7] treewide: Remove unused FSL QSPI config options for IMX platforms

[Kuldeep Singh]

Some of these options are not used by the driver anymore and some of them
are obsolete as the information is gathered from the dt.
So, remove the unused config options now.

Signed-off-by: Frieder Schrempf 
Signed-off-by: Ashish Kumar 
Signed-off-by: Kuldeep Singh 
---
v5: New patch. Only imx changes here from patch 2.

 include/configs/mx6sxsabreauto.h  |  6 --
 include/configs/mx6sxsabresd.h| 11 ---
 include/configs/mx6ul_14x14_evk.h |  6 --
 include/configs/mx6ullevk.h   |  6 --
 include/configs/mx7dsabresd.h |  8 
 include/configs/pcm052.h  |  7 ---
 include/configs/vf610twr.h|  8 
 7 files changed, 52 deletions(-)

diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index 0bcf031..16a4511 100644
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h
@@ -145,12 +145,6 @@
 
 #define CONFIG_IMX_THERMAL
 
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_FSL_QSPI_AHB
-#define FSL_QSPI_FLASH_SIZESZ_32M
-#define FSL_QSPI_FLASH_NUM 2
-#endif
-
 #define CONFIG_SYS_FSL_USDHC_NUM   2
 #if defined(CONFIG_ENV_IS_IN_MMC)
 #define CONFIG_SYS_MMC_ENV_DEV 0  /*USDHC3*/
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 55aace1..03816df 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -175,17 +175,6 @@
 
 #define CONFIG_IMX_THERMAL
 
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_FSL_QSPI_LE
-#define CONFIG_SYS_FSL_QSPI_AHB
-#ifdef CONFIG_MX6SX_SABRESD_REVA
-#define FSL_QSPI_FLASH_SIZESZ_16M
-#else
-#define FSL_QSPI_FLASH_SIZESZ_32M
-#endif
-#define FSL_QSPI_FLASH_NUM 2
-#endif
-
 #ifndef CONFIG_SPL_BUILD
 #ifdef CONFIG_VIDEO
 #define CONFIG_VIDEO_MXS
diff --git a/include/configs/mx6ul_14x14_evk.h 
b/include/configs/mx6ul_14x14_evk.h
index f347eeb..de6a279 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -157,12 +157,6 @@
 #define CONFIG_SYS_MMC_ENV_PART0   /* user area */
 #define CONFIG_MMCROOT "/dev/mmcblk1p2"  /* USDHC2 */
 
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_FSL_QSPI_AHB
-#define FSL_QSPI_FLASH_NUM 1
-#define FSL_QSPI_FLASH_SIZESZ_32M
-#endif
-
 /* USB Configs */
 #ifdef CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h
index 7cce911..425f391 100644
--- a/include/configs/mx6ullevk.h
+++ b/include/configs/mx6ullevk.h
@@ -160,10 +160,4 @@
 
 #define CONFIG_SOFT_SPI
 
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_FSL_QSPI_AHB
-#define FSL_QSPI_FLASH_NUM 1
-#define FSL_QSPI_FLASH_SIZESZ_32M
-#endif
-
 #endif
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index b1726b1..50a133d 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -154,12 +154,4 @@
 #define CONFIG_VIDEO_BMP_LOGO
 #endif
 
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_FSL_QSPI_AHB
-#define FSL_QSPI_FLASH_NUM 1
-#define FSL_QSPI_FLASH_SIZESZ_64M
-#define QSPI0_BASE_ADDRQSPI1_IPS_BASE_ADDR
-#define QSPI0_AMBA_BASEQSPI0_ARB_BASE_ADDR
-#endif
-
 #endif /* __CONFIG_H */
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index 72f8d08..d4d6ad2 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -26,13 +26,6 @@
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 
 #define CONFIG_SYS_MAX_NAND_DEVICE 1
-/* QSPI Configs*/
-#ifdef CONFIG_FSL_QSPI
-#define FSL_QSPI_FLASH_SIZE(SZ_16M)
-#define FSL_QSPI_FLASH_NUM 2
-#define CONFIG_SYS_FSL_QSPI_LE
-#endif
-
 
 #define CONFIG_LOADADDR0x8200
 
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 3ab3231..d52a5a7 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -43,14 +43,6 @@
 #define CONFIG_FEC_XCV_TYPERMII
 #define CONFIG_FEC_MXC_PHYADDR  0
 
-/* QSPI Configs*/
-
-#ifdef CONFIG_FSL_QSPI
-#define FSL_QSPI_FLASH_SIZE(1 << 24)
-#define FSL_QSPI_FLASH_NUM 2
-#define CONFIG_SYS_FSL_QSPI_LE
-#endif
-
 /* I2C Configs */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
-- 
2.7.4

[Patch v5 0/7] Transition of fsl qspi driver to spi-mem framework

[Kuldeep Singh]

This entire patch series migrate freescale qspi driver to spi-mem
framework.

Patch 1 adds new qspi driver incorporating spi-mem framework and also
removal of old driver which was based on spi-nor. The driver is a ported
version of linux qspi driver. Initial port was done by Frieder. Now, no
more direct memory access to spi-nor memory is possible i.e accessing flash
memory using absolute address is not possible.

Patch 2 removes unused qspi config options for layerscape platforms.

Patch 3 removes unused qspi config options for imx platforms.

Patch 4 moves FSL_QSPI to defconfig instead of defining it in header files.

Patch 5 enables SPI_FLASH_SPANSION in ls1012a defconfig as FSL_QSPI is
already enabled.

Patch 6 enables SPI_FLASH_SPANSION in defconfigs of LS1046a boards instead
of defining in header files.

Patch 7 updates the device-tree properties treewide for layerscape boards
by aligning with linux device-tree properties.

v5:
-Remove compilation warning/error in patch1(qspi driver).
-Split patch 2 into 2 patches as changes will go via different tree.
-Remove imx dts change(previusly patch 4) as superseeded by Fabio's patch.

v4:
-Removal of buildman failure on LS2080AQDS
-Reword commit message of patch 5.

v3:
-Correction of copyright in qspi driver(Patch 1).
-Move SPI_FLASH_SPANSION from header to defconfig in same patch.

v2:
-Incorporate 1k size to make driver independent of flash size.
-Add support for imx platforms to set TDH bits correctly.
-Reword commit messages.

Patch[1] is required to resolve booting crash observed in LS1012ARDB. Crash
was related to pfe driver as it was accessing flash memory directly.
[1] https://patchwork.ozlabs.org/patch/1219462/

Kuldeep Singh (7):
  spi: Transform the FSL QuadSPI driver to use the SPI MEM API
  treewide: Remove unused FSL QSPI config options for Layerscape
platforms
  treewide: Remove unused FSL QSPI config options for IMX platforms
  configs: ls1043a: Move CONFIG_FSL_QSPI and SPI_FLASH_SPANSION to
defconfig
  configs: ls1012a: Enable CONFIG_SPI_FLASH_SPANSION in defconfigs
  configs: ls1046a: Move SPI_FLASH_SPANSION to defconfig
  treewide: Update fsl qspi node dt properties as per spi-mem driver

 arch/arm/dts/fsl-ls1012a-2g5rdb.dts   |5 +-
 arch/arm/dts/fsl-ls1012a-frdm.dtsi|5 +-
 arch/arm/dts/fsl-ls1012a-qds.dtsi |5 +-
 arch/arm/dts/fsl-ls1012a-rdb.dtsi |5 +-
 arch/arm/dts/fsl-ls1012a.dtsi |4 +-
 arch/arm/dts/fsl-ls1043a-qds.dtsi |5 +-
 arch/arm/dts/fsl-ls1043a.dtsi |6 +-
 arch/arm/dts/fsl-ls1046a-frwy.dts |5 +-
 arch/arm/dts/fsl-ls1046a-qds.dtsi |5 +-
 arch/arm/dts/fsl-ls1046a-rdb.dts  |5 +-
 arch/arm/dts/fsl-ls1046a.dtsi |4 +-
 arch/arm/dts/fsl-ls1088a-qds.dts  |5 +-
 arch/arm/dts/fsl-ls1088a-rdb.dts  |5 +-
 arch/arm/dts/fsl-ls1088a.dtsi |2 +-
 arch/arm/dts/fsl-ls2080a-qds.dts  |5 +-
 arch/arm/dts/fsl-ls2080a.dtsi |4 +-
 arch/arm/dts/fsl-ls2088a-rdb-qspi.dts |5 +-
 arch/arm/dts/ls1021a-twr.dtsi |5 +-
 arch/arm/dts/ls1021a.dtsi |6 +-
 arch/arm/include/asm/arch-fsl-layerscape/config.h |1 -
 arch/arm/include/asm/arch-ls102xa/config.h|1 -
 configs/ls1012a2g5rdb_qspi_defconfig  |1 +
 configs/ls1012a2g5rdb_tfa_defconfig   |1 +
 configs/ls1012afrdm_qspi_defconfig|1 +
 configs/ls1012afrdm_tfa_defconfig |1 +
 configs/ls1012aqds_qspi_defconfig |1 +
 configs/ls1012aqds_tfa_SECURE_BOOT_defconfig  |1 +
 configs/ls1012aqds_tfa_defconfig  |1 +
 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig |1 +
 configs/ls1012ardb_qspi_defconfig |1 +
 configs/ls1012ardb_tfa_SECURE_BOOT_defconfig  |1 +
 configs/ls1012ardb_tfa_defconfig  |1 +
 configs/ls1043aqds_qspi_defconfig |1 +
 configs/ls1043aqds_sdcard_qspi_defconfig  |1 +
 configs/ls1043aqds_tfa_SECURE_BOOT_defconfig  |2 +
 configs/ls1043aqds_tfa_defconfig  |1 +
 configs/ls1046aqds_qspi_defconfig |1 +
 configs/ls1046aqds_sdcard_qspi_defconfig  |1 +
 configs/ls1046aqds_tfa_SECURE_BOOT_defconfig  |1 +
 configs/ls1046aqds_tfa_defconfig  |1 +
 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig |1 +
 configs/ls1046ardb_qspi_defconfig |1 +
 configs/ls1046ardb_tfa_SECURE_BOOT_defconfig  |1 +
 configs/ls1046ardb_tfa_defconfig  |1 +
 drivers/spi/fsl_qspi.c| 1577 -
 drivers/spi/fsl_qspi.h|  145 

Re: [PATCH v2 01/21] configs: agilex: Remove CONFIG_OF_EMBED

[Westergreen, Dalon]

On Thu, 2020-02-20 at 17:44 +0100, Marek Vasut wrote:

On 2/20/20 3:12 AM, Ang, Chee Hong wrote:

On 2/19/20 1:25 PM,



chee.hong@intel.com

 wrote:

From: Chee Hong Ang <



chee.hong@intel.com

>


CONFIG_OF_EMBED was primarily enabled to support the agilex spl hex

file requirements.  Since this option now produces a warning during

build, and the spl hex can be created using alternate methods,

CONFIG_OF_EMBED is no longer needed.


Signed-off-by: Chee Hong Ang <



chee.hong@intel.com

>


If I apply just this patch, is the platform still bootable ?

Yes. I tested on the platform.

There is a similar patch from Dalon for Stratix10 and it still yet to be applied

to mainline:



https://lists.denx.de/pipermail/u-boot/2019-September/384906.html



I hope the patch from Dalon get applied to mainline before these patchsets.


In fact, this "CONFIG_OF_EMBED" produce warning during build.

Better get rid of this.


If you just remove OF_EMBED, will the DT still be correctly passed in ?

The warning is there for a reason and just removing OF_EMBED to silence

the warning isn't the right approach. But if this works on Agilex, fine.

Yes, it is fine, the u-boot binary and dtb are just cat'ed together instead.

--dalon

[PATCH] net: bcmgenet: Don't set ID_MODE_DIS when not using RGMII

[Nicolas Saenz Julienne]

As per Linux's driver, ID_MODE_DIS is only set when the PHY interface is
RGMII. Don't enable it for the rest of setups.

This has been seen to misconfigure RPi4's PHY when booting Linux.

Signed-off-by: Nicolas Saenz Julienne 
---
 drivers/net/bcmgenet.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c
index 8f4848aec6..e971b556ac 100644
--- a/drivers/net/bcmgenet.c
+++ b/drivers/net/bcmgenet.c
@@ -448,7 +448,10 @@ static int bcmgenet_adjust_link(struct bcmgenet_eth_priv 
*priv)
}
 
clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE,
-   RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS);
+   RGMII_LINK | RGMII_MODE_EN);
+
+   if (phy_dev->interface == PHY_INTERFACE_MODE_RGMII)
+   setbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, ID_MODE_DIS);
 
writel(speed << CMD_SPEED_SHIFT, (priv->mac_reg + UMAC_CMD));
 
-- 
2.25.0

Re: [PATCH v2 10/21] arm: socfpga: Add secure register access helper functions for SoC 64bits

[Marek Vasut]

On 2/20/20 3:02 AM, Ang, Chee Hong wrote:
[...]
>>> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
>>> +u32 socfpga_secure_reg_read32(phys_addr_t reg_addr); void
>>> +socfpga_secure_reg_write32(u32 val, phys_addr_t reg_addr); void
>>> +socfpga_secure_reg_update32(phys_addr_t reg_addr, u32 mask, u32 val);
>>> +#else
>>> +#define socfpga_secure_reg_read32  readl
>>> +#define socfpga_secure_reg_write32 writel
>>> +#define socfpga_secure_reg_update32clrsetbits_le32
>>> +#endif
>>
>> I think I don't understand how this is supposed to work. Would every place 
>> in U-
>> Boot have to be patched to call these functions now ?
> 
> Not every register access need this. Only those accessing registers in secure 
> zone such
> as 'System Manager' registers need to call this. It's basically determine 
> whether the driver
> should issue SMC/PSCI call if it's running in EL2 (non-secure) or access the 
> registers directly
> by simply using readl/writel and etc if it's running in EL3 (secure).
> Accessing those registers in secure zone in non-secure mode (EL2) will cause 
> SError exception.
> So we can determine this behaviour in compile time:
> SPL always running in EL3. So it just simply fallback to use 
> readl/writel/clrsetbits_le32.
> 
> For U-Boot proper (SSBL), there are 2 scenarios:
> 1) If CONFIG_SPL_ATF is defined, it means ATF is supported. It implies that 
> U-Boot proper will be
> running in EL2 (non-secure), then it will use SMC/PSCI calls to access the 
> secure registers.
> 
> 2) CONFIG_SPL_ATF is not defined, no ATF support. U-Boot proper will be 
> running in EL3 which
> will fall back to simply using the direct access functions (readl/writel and 
> etc).

I would expect the standard IO accessors would or should handle this stuff ?

Re: [PATCH v2 11/21] arm: socfpga: Secure register access for clock manager (SoC 64bits)

[Marek Vasut]

On 2/20/20 3:32 AM, Ang, Chee Hong wrote:
>> On 2/19/20 1:25 PM, chee.hong@intel.com wrote:
>>> From: Chee Hong Ang 
>>>
>>> Allow clock manager driver to access the System Manager's Boot Scratch
>>> Register 0 in non-secure mode (EL2) on SoC 64bits platform.
>>>
>>> Signed-off-by: Chee Hong Ang 
>>> ---
>>>  arch/arm/mach-socfpga/clock_manager_agilex.c | 5 +++--
>>>  arch/arm/mach-socfpga/clock_manager_s10.c| 5 +++--
>>>  2 files changed, 6 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c
>>> b/arch/arm/mach-socfpga/clock_manager_agilex.c
>>> index 4ee2b7b..e5a0998 100644
>>> --- a/arch/arm/mach-socfpga/clock_manager_agilex.c
>>> +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
>>> @@ -12,6 +12,7 @@
>>>  #include 
>>>  #include 
>>>  #include 
>>> +#include 
>>>
>>>  DECLARE_GLOBAL_DATA_PTR;
>>>
>>> @@ -65,8 +66,8 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
>>>
>>>  u32 cm_get_qspi_controller_clk_hz(void)
>>>  {
>>> -   return readl(socfpga_get_sysmgr_addr() +
>>> -SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
>>> +   return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
>>> +
>> SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
>>>  }
>>>
>>>  void cm_print_clock_quick_summary(void)
>>> diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c
>>> b/arch/arm/mach-socfpga/clock_manager_s10.c
>>> index 05e4212..02578cc 100644
>>> --- a/arch/arm/mach-socfpga/clock_manager_s10.c
>>> +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
>>> @@ -9,6 +9,7 @@
>>>  #include 
>>>  #include 
>>>  #include 
>>> +#include 
>>>
>>>  DECLARE_GLOBAL_DATA_PTR;
>>>
>>> @@ -385,8 +386,8 @@ unsigned int cm_get_l4_sp_clk_hz(void)
>>>
>>>  unsigned int cm_get_qspi_controller_clk_hz(void)
>>>  {
>>> -   return readl(socfpga_get_sysmgr_addr() +
>>> -SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
>>> +   return socfpga_secure_reg_read32(socfpga_get_sysmgr_addr() +
>>> +
>> SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
>>>  }
>>>
>>>  unsigned int cm_get_spi_controller_clk_hz(void)
>>
>> Shouldn't the IO accessors already provide the necessary abstraction ?
> This function accesses the system manager registers, therefore it is required
> to call the secure register read function to make sure it still can access
> the system manager register if it's running EL2 (non-secure).

But shouldn't the standard IO accessors handle that transparently ?
What does Linux do ?