Re: [PATCH v2 06/10] drivers: spi: Add SPI controller driver for Octeon
Hi Daniel,
On 24.07.20 15:56, Daniel Schwierzeck wrote:
Am Donnerstag, den 23.07.2020, 12:17 +0200 schrieb Stefan Roese:
From: Suneel Garapati
Adds support for SPI controllers found on Octeon II/III and Octeon TX
TX2 SoC platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Suneel Garapati
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
Cc: Aaron Williams
Cc: Chandrakala Chavva
Cc: Jagan Teki
+static const struct dm_spi_ops octeon_spi_ops = {
+ .claim_bus = octeon_spi_claim_bus,
+ .release_bus= octeon_spi_release_bus,
+ .set_speed = octeon_spi_set_speed,
+ .set_mode = octeon_spi_set_mode,
+ .xfer = octeon_spi_xfer,
+};
+
+static const struct dm_spi_ops octeontx2_spi_ops = {
+ .claim_bus = octeon_spi_claim_bus,
+ .release_bus= octeon_spi_release_bus,
+ .set_speed = octeon_spi_set_speed,
+ .set_mode = octeon_spi_set_mode,
+ .xfer = octeontx2_spi_xfer,
+ .mem_ops= _spi_mem_ops,
+};
+
+static int octeon_spi_probe(struct udevice *dev)
+{
+ struct octeon_spi *priv = dev_get_priv(dev);
+ const struct octeon_spi_data *data;
+ int ret;
+
+ data = (const struct octeon_spi_data *)dev_get_driver_data(dev);
+ if (data->probe == PROBE_PCI) {
+ pci_dev_t bdf = dm_pci_get_bdf(dev);
+
+ debug("SPI PCI device: %x\n", bdf);
+ priv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0,
+ PCI_REGION_MEM);
+ } else {
+ priv->base = dev_remap_addr(dev);
+ }
+
+ priv->base += data->reg_offs;
+
+ /* Octeon TX2 needs a different ops struct */
+ if (device_is_compatible(dev, "cavium,thunderx-spi")) {
+ /*
+* "ops" is const and can't be written directly. So we need
+* to write the Octeon TX2 ops value using this trick
+*/
+ writeq((u64)_spi_ops, (void *)>driver->ops);
+ }
can't you simply add a xfer() function pointer to "struct
octeon_spi_data" and assign the according xfer function to it? Then
in octeon_spi_xfer() you can simply call that function pointer. With
this you only need one instance of "struct dm_spi_ops" and don't need
this ugly hack ;)
Unfortuantely its not that easy, as the Octeon TX2 ops struct also has
a " mem_ops" member, which the driver does not support for the other
Octeon models. I could clear this "mem_ops" member in the non Octeon
TX2 case, which is a bit better than the 2nd ops struct. But its still
not really elegent.
Or do you have some other idea on how to implement this in a "better
way"?
Thanks,
Stefan
[PATCH] mkimage: fit: fix import of external data
From: Patrick Oppenlander
The external data is located after the mmapped FDT pointed to by
'old_fdt', not in the newly created FDT we are importing into at 'fdt'.
Signed-off-by: Patrick Oppenlander
---
tools/fit_image.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/fit_image.c b/tools/fit_image.c
index df310b53da..793df54449 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -606,8 +606,8 @@ static int fit_import_data(struct image_tool_params
*params, const char *fname)
continue;
debug("Importing data size %x\n", len);
- ret = fdt_setprop(fdt, node, "data", fdt + data_base + buf_ptr,
- len);
+ ret = fdt_setprop(fdt, node, "data",
+ old_fdt + data_base + buf_ptr, len);
if (ret) {
debug("%s: Failed to write property: %s\n", __func__,
fdt_strerror(ret));
--
2.27.0
[PATCH] mkimage: fit: include image cipher in configuration signature
From: Patrick Oppenlander
This patch addresses issue #2 for signed configurations.
-8<-
Including the image cipher properties in the configuration signature
prevents an attacker from modifying cipher, key or iv properties.
Signed-off-by: Patrick Oppenlander
---
tools/image-host.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/tools/image-host.c b/tools/image-host.c
index e5417beee5..3d52593e36 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -744,6 +744,23 @@ static int fit_config_get_hash_list(void *fit, int
conf_noffset,
return -ENOMSG;
}
+ /* Add this image's cipher node if present */
+ noffset = fdt_subnode_offset(fit, image_noffset,
+FIT_CIPHER_NODENAME);
+ if (noffset != -FDT_ERR_NOTFOUND) {
+ if (noffset < 0) {
+ printf("Failed to get cipher node in
configuration '%s/%s' image '%s': %s\n",
+ conf_name, sig_name, iname,
+ fdt_strerror(noffset));
+ return -EIO;
+ }
+ ret = fdt_get_path(fit, noffset, path, sizeof(path));
+ if (ret < 0)
+ goto err_path;
+ if (strlist_add(node_inc, path))
+ goto err_mem;
+ }
+
image_count++;
}
--
2.27.0
[PATCH v2 3/3] mkimage: fit: don't cipher ciphered data
From: Patrick Oppenlander
Previously, mkimage -F could be run multiple times causing already
ciphered image data to be ciphered again.
Signed-off-by: Patrick Oppenlander
---
tools/image-host.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/tools/image-host.c b/tools/image-host.c
index b4603c5f01..e5417beee5 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -482,7 +482,7 @@ int fit_image_cipher_data(const char *keydir, void *keydest,
const char *image_name;
const void *data;
size_t size;
- int cipher_node_offset;
+ int cipher_node_offset, len;
/* Get image name */
image_name = fit_get_name(fit, image_noffset, NULL);
@@ -497,6 +497,19 @@ int fit_image_cipher_data(const char *keydir, void
*keydest,
return -1;
}
+ /*
+* Don't cipher ciphered data.
+*
+* If the data-size-unciphered property is present the data for this
+* image is already encrypted. This is important as 'mkimage -F' can be
+* run multiple times on a FIT image.
+*/
+ if (fdt_getprop(fit, image_noffset, "data-size-unciphered", ))
+ return 0;
+ if (len != -FDT_ERR_NOTFOUND) {
+ printf("Failure testing for data-size-unciphered\n");
+ return -1;
+ }
/* Process cipher node if present */
cipher_node_offset = fdt_subnode_offset(fit, image_noffset,
--
2.27.0
[PATCH v2] mkimage: FIT ciphering bug fixes
The v2 series addresses review comments from Philippe Reynes: * Use FIT_CIPHER_NODENAME instead of hard coding "cipher" * Simplify handling of FDT_ERR_NOSPACE * Simplify detection of previously ciphered data The last two points are possible as I overlooked that the retry loop handling ENOSPC in fit_handle_file() reloads the original FIT before retrying.
[PATCH v2 1/3] mkimage: fit: only process one cipher node
From: Patrick Oppenlander
Previously mkimage would process any node matching the regex cipher.*
and apply the ciphers to the image data in the order they appeared in
the FDT. This meant that data could be inadvertently ciphered multiple
times.
Switch to processing a single cipher node which exactly matches
FIT_CIPHER_NODENAME.
Signed-off-by: Patrick Oppenlander
Reviewed-by: Philippe Reynes
---
tools/image-host.c | 57 ++
1 file changed, 22 insertions(+), 35 deletions(-)
diff --git a/tools/image-host.c b/tools/image-host.c
index 9a83b7f675..dd7ecc4b60 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -323,15 +323,15 @@ err:
static int fit_image_setup_cipher(struct image_cipher_info *info,
const char *keydir, void *fit,
const char *image_name, int image_noffset,
- const char *node_name, int noffset)
+ int noffset)
{
char *algo_name;
char filename[128];
int ret = -1;
if (fit_image_cipher_get_algo(fit, noffset, _name)) {
- printf("Can't get algo name for cipher '%s' in image '%s'\n",
- node_name, image_name);
+ printf("Can't get algo name for cipher in image '%s'\n",
+ image_name);
goto out;
}
@@ -340,16 +340,16 @@ static int fit_image_setup_cipher(struct
image_cipher_info *info,
/* Read the key name */
info->keyname = fdt_getprop(fit, noffset, FIT_KEY_HINT, NULL);
if (!info->keyname) {
- printf("Can't get key name for cipher '%s' in image '%s'\n",
- node_name, image_name);
+ printf("Can't get key name for cipher in image '%s'\n",
+ image_name);
goto out;
}
/* Read the IV name */
info->ivname = fdt_getprop(fit, noffset, "iv-name-hint", NULL);
if (!info->ivname) {
- printf("Can't get iv name for cipher '%s' in image '%s'\n",
- node_name, image_name);
+ printf("Can't get iv name for cipher in image '%s'\n",
+ image_name);
goto out;
}
@@ -428,8 +428,7 @@ int fit_image_write_cipher(void *fit, int image_noffset,
int noffset,
static int
fit_image_process_cipher(const char *keydir, void *keydest, void *fit,
const char *image_name, int image_noffset,
-const char *node_name, int node_noffset,
-const void *data, size_t size,
+int node_noffset, const void *data, size_t size,
const char *cmdname)
{
struct image_cipher_info info;
@@ -440,7 +439,7 @@ fit_image_process_cipher(const char *keydir, void *keydest,
void *fit,
memset(, 0, sizeof(info));
ret = fit_image_setup_cipher(, keydir, fit, image_name,
-image_noffset, node_name, node_noffset);
+image_noffset, node_noffset);
if (ret)
goto out;
@@ -482,7 +481,7 @@ int fit_image_cipher_data(const char *keydir, void *keydest,
const char *image_name;
const void *data;
size_t size;
- int node_noffset;
+ int cipher_node_offset;
/* Get image name */
image_name = fit_get_name(fit, image_noffset, NULL);
@@ -497,32 +496,20 @@ int fit_image_cipher_data(const char *keydir, void
*keydest,
return -1;
}
- /* Process all hash subnodes of the component image node */
- for (node_noffset = fdt_first_subnode(fit, image_noffset);
-node_noffset >= 0;
-node_noffset = fdt_next_subnode(fit, node_noffset)) {
- const char *node_name;
- int ret = 0;
-
- node_name = fit_get_name(fit, node_noffset, NULL);
- if (!node_name) {
- printf("Can't get node name\n");
- return -1;
- }
- if (IMAGE_ENABLE_ENCRYPT && keydir &&
- !strncmp(node_name, FIT_CIPHER_NODENAME,
-strlen(FIT_CIPHER_NODENAME)))
- ret = fit_image_process_cipher(keydir, keydest,
- fit, image_name,
- image_noffset,
- node_name, node_noffset,
- data, size, cmdname);
- if (ret)
- return ret;
+ /* Process cipher node if present */
+ cipher_node_offset = fdt_subnode_offset(fit, image_noffset,
+ FIT_CIPHER_NODENAME);
+ if
[PATCH v2 2/3] mkimage: fit: handle FDT_ERR_NOSPACE when ciphering
From: Patrick Oppenlander
Also replace fdt_delprop/fdt_setprop with fdt_setprop as fdt_setprop can
replace an existing property value.
Signed-off-by: Patrick Oppenlander
---
tools/image-host.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/tools/image-host.c b/tools/image-host.c
index dd7ecc4b60..b4603c5f01 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -399,23 +399,24 @@ int fit_image_write_cipher(void *fit, int image_noffset,
int noffset,
{
int ret = -1;
- /* Remove unciphered data */
- ret = fdt_delprop(fit, image_noffset, FIT_DATA_PROP);
- if (ret) {
- printf("Can't remove data (err = %d)\n", ret);
- goto out;
- }
-
- /* Add ciphered data */
+ /* Replace data with ciphered data */
ret = fdt_setprop(fit, image_noffset, FIT_DATA_PROP,
data_ciphered, data_ciphered_len);
+ if (ret == -FDT_ERR_NOSPACE) {
+ ret = -ENOSPC;
+ goto out;
+ }
if (ret) {
- printf("Can't add ciphered data (err = %d)\n", ret);
+ printf("Can't replace data with ciphered data (err = %d)\n",
ret);
goto out;
}
/* add non ciphered data size */
ret = fdt_setprop_u32(fit, image_noffset, "data-size-unciphered", size);
+ if (ret == -FDT_ERR_NOSPACE) {
+ ret = -ENOSPC;
+ goto out;
+ }
if (ret) {
printf("Can't add unciphered data size (err = %d)\n", ret);
goto out;
--
2.27.0
Re: [PATCH v3 1/1] phy: add support for stingray PAXB PHY controller
Hi Tom, On Sat, Jun 27, 2020 at 1:31 AM Tom Rini wrote: > > On Thu, Jun 25, 2020 at 10:57:09PM +0530, Rayagonda Kokatanur wrote: > > Hi Tom, > > > > > > On Sun, Apr 12, 2020 at 8:46 PM Rayagonda Kokatanur > > wrote: > > > > > > On Thu, Apr 9, 2020 at 7:11 PM Tom Rini wrote: > > > > > > > > On Thu, Apr 02, 2020 at 04:08:12PM +0530, Rayagonda Kokatanur wrote: > > > > > > > > > From: Srinath Mannam > > > > > > > > > > Add support for stingray PAXB PHY controller driver. > > > > > This driver supports maximum 8 PAXB phys using pipemux data. > > > > > > > > > > Signed-off-by: Srinath Mannam > > > > > Signed-off-by: Rayagonda Kokatanur > > > > > Reviewed-by: Stefan Roese > > > > > --- > > > > > Changes from v2: > > > > > -Address review comments from Stefan Roese, > > > > > Rearrange the include files. > > > > > Remove dm/device.h as its included part of dm.h. > > > > > > > > > > Changes from v1: > > > > > -Address review comments from Stefan Roese, > > > > > Use GENMASK() instead of hard code value. > > > > > Remove unwanted struct declaration. > > > > > Get pr_err() into single line. > > > > > > > > > > drivers/phy/Kconfig | 7 ++ > > > > > drivers/phy/Makefile | 1 + > > > > > drivers/phy/phy-bcm-sr-pcie.c | 177 > > > > > ++ > > > > > > > > The patch itself is fine but I think shows another problem. Can you > > > > please add a patch that lists something relevant in the top-level > > > > MAINTAINERS file and list this and all of the other drivers, etc, that > > > > wouldn't just be listed in the board MAINATINERS file? Thanks! > > > > I have a plan to update the top level MAINTAINER file with all new > > driver and board files in a separate patch. > > Hope this is fine, please let me know. > > OK, thanks. I'll be picking up more patches again soon for -next. Could you please pick this patch. If any further review comments, please let me know. Best regards, Rayagonda > > -- > Tom
Re: [PATCH v1 2/3] configs: pico-imx6ul: convert DM_VIDEO
On 7/30/20 9:15 AM, Fabio Estevam wrote: On Tue, Jul 28, 2020 at 11:35 PM wrote: From: Wig Cheng Fix compile warning messages. Signed-off-by: Wig Cheng --- configs/pico-imx6ul_defconfig | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig index e8cbf3bc1e..f02d370b7d 100644 --- a/configs/pico-imx6ul_defconfig +++ b/configs/pico-imx6ul_defconfig @@ -75,4 +75,8 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y -CONFIG_VIDEO=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_PCI_DEFAULT_FB_SIZE=0x0 Why is this one needed? It shows warning messages after compiled: = WARNING == This board does not use CONFIG_DM_VIDEO Please update the board to use CONFIG_DM_VIDEO before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. Enable DM_VIDEO will be solved this warning although there's no difference no matter enable DM_VIDEO or not on runtime level, just for warning message. I'll improve the commit log if you think it's okay, thanks a lot.
Re: [PATCH v4 07/16] efi_loader: capsule: add capsule_on_disk support
Heinrich,
On Thu, Jul 23, 2020 at 05:50:09PM +0200, Heinrich Schuchardt wrote:
> On 22.07.20 08:05, AKASHI Takahiro wrote:
> > Capsule data can be loaded into the system either via UpdateCapsule
> > runtime service or files on a file system (of boot device).
> > The latter case is called "capsules on disk", and actual updates will
> > take place at the next boot time.
> >
> > In this commit, we will support capsule on disk mechanism.
> >
> > Please note that U-Boot itself has no notion of "boot device" and
> > all the capsule files to be executed will be detected only if they
> > are located in a specific directory, \EFI\UpdateCapsule, on a device
> > that is identified as a boot device by "Boot" variables.
> >
> > Signed-off-by: AKASHI Takahiro
> > ---
> > common/main.c| 4 +
> > include/efi_loader.h | 16 ++
> > lib/efi_loader/Kconfig | 22 ++
> > lib/efi_loader/efi_capsule.c | 510 +++
> > lib/efi_loader/efi_setup.c | 8 +
> > 5 files changed, 560 insertions(+)
> >
> > diff --git a/common/main.c b/common/main.c
> > index 62ab3344e529..71fb749be4f4 100644
> > --- a/common/main.c
> > +++ b/common/main.c
> > @@ -16,6 +16,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > static void run_preboot_environment_command(void)
> > {
> > @@ -50,6 +51,9 @@ void main_loop(void)
> > if (IS_ENABLED(CONFIG_USE_PREBOOT))
> > run_preboot_environment_command();
> >
> > + if (IS_ENABLED(CONFIG_EFI_CAPSULE_ON_DISK_EARLY))
> > + efi_launch_capsules();
> > +
> > s = bootdelay_process();
> > if (cli_process_fdt())
> > cli_secure_boot_cmd(s);
> > diff --git a/include/efi_loader.h b/include/efi_loader.h
> > index a754fb0ed460..7e00bf3b33f3 100644
> > --- a/include/efi_loader.h
> > +++ b/include/efi_loader.h
> > @@ -808,6 +808,18 @@ efi_status_t EFIAPI efi_query_capsule_caps(
> > u64 *maximum_capsule_size,
> > u32 *reset_type);
> >
> > +#ifdef CONFIG_EFI_CAPSULE_ON_DISK
>
> This #ifdef seems unnecessary. No code will invoke efi_launch_capsules()
> if CONFIG_EFI_CAPSULE_ON_DISK is not set.
Okay, I agree that this kind of #ifdef be removed from a header.
> > +#define EFI_CAPSULE_DIR L"\\EFI\\UpdateCapsule\\"
> > +
> > +/* Hook at initialization */
> > +efi_status_t efi_launch_capsules(void);
> > +#else
> > +static inline efi_status_t efi_launch_capsules(void)
> > +{
> > + return EFI_SUCCESS;
> > +}
> > +#endif /* CONFIG_EFI_CAPSULE_ON_DISK */
> > +
> > #else /* CONFIG_IS_ENABLED(EFI_LOADER) */
> >
> > /* Without CONFIG_EFI_LOADER we don't have a runtime section, stub it out
> > */
> > @@ -824,6 +836,10 @@ static inline void efi_set_bootdev(const char *dev,
> > const char *devnr,
> >const char *path) { }
> > static inline void efi_net_set_dhcp_ack(void *pkt, int len) { }
> > static inline void efi_print_image_infos(void *pc) { }
> > +static inline efi_status_t efi_launch_capsules(void)
> > +{
> > + return EFI_SUCCESS;
> > +}
> >
> > #endif /* CONFIG_IS_ENABLED(EFI_LOADER) */
> >
> > diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
> > index ee9ebe348ad9..6e35cbe64c7f 100644
> > --- a/lib/efi_loader/Kconfig
> > +++ b/lib/efi_loader/Kconfig
> > @@ -104,6 +104,28 @@ config EFI_RUNTIME_UPDATE_CAPSULE
> > Select this option if you want to use UpdateCapsule and
> > QueryCapsuleCapabilities API's.
> >
> > +config EFI_CAPSULE_ON_DISK
> > + bool "Enable capsule-on-disk support"
> > + select EFI_HAVE_CAPSULE_SUPPORT
> > + default n
> > + help
> > + Select this option if you want to use capsule-on-disk feature,
> > + that is, capsules can be fetched and executed from files
> > + under a specific directory on UEFI system partition instead of
> > + via UpdateCapsule API.
> > +
> > +config EFI_CAPSULE_ON_DISK_EARLY
> > + bool "Initiate capsule-on-disk at U-Boot boottime"
> > + depends on EFI_CAPSULE_ON_DISK
> > + default y
> > + select EFI_SETUP_EARLY
> > + help
> > + Normally, without this option enabled, capsules will be
> > + executed only at the first time of invoking one of efi command.
> > + If this option is enabled, capsules will be enforced to be
> > + executed as part of U-Boot initialisation so that they will
> > + surely take place whatever is set to distro_bootcmd.
> > +
> > config EFI_DEVICE_PATH_TO_TEXT
> > bool "Device path to text protocol"
> > default y
> > diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
> > index cfe422bee924..2a224546dd11 100644
> > --- a/lib/efi_loader/efi_capsule.c
> > +++ b/lib/efi_loader/efi_capsule.c
> > @@ -10,10 +10,16 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> >
> > const efi_guid_t efi_guid_capsule_report = EFI_CAPSULE_REPORT_GUID;
> >
> > +#ifdef CONFIG_EFI_CAPSULE_ON_DISK
> > +/* for file system access */
> > +static struct
Re: [RESEND PATCH] usb: max3420: add the gadget driver
On Wed, Jul 29, 2020 at 5:04 AM Sean Anderson wrote: > > On 6/24/20 1:09 AM, Jassi Brar wrote: > > On Tue, Jun 16, 2020 at 2:29 AM Lukasz Majewski wrote: > >> > >> Hi Jassi, > >> > >>> ... a polite ping, Lukasz. > >> > >> The only excuse for so long lack of my response are my personal issues > >> caused by the covid-19. > >> > > Sorry if I came across as pestering you. I hope all is well now. > > > > . > + > +#define MAX3420_REG_IOPINS 20 > +#define MAX3420_REG_IOPINS221 > +#define MAX3420_REG_GPINIRQ22 > +#define MAX3420_REG_GPINIEN23 > +#define MAX3420_REG_GPINPOL24 > +#define MAX3420_REG_HIRQ 25 > +#define MAX3420_REG_HIEN 26 > +#define MAX3420_REG_MODE 27 > +#define MAX3420_REG_PERADDR28 > +#define MAX3420_REG_HCTL 29 > +#define MAX3420_REG_HXFR 30 > +#define MAX3420_REG_HRSL 31 > + > >> > >> When I do look into drivers/usb/gadget/f_dfu.* the defines are placed > >> in the f_dfu.h file. > >> > > One school of thought is to contain all code in one file, especially > > when no other file should access it -- these defines are very max3420 > > specific and none else should need these. > > But I am fine if you want them in a separate file. > > > +#define field(val, bit)((val) << (bit)) > + > +#define msleep(a) udelay((a) * 1000) > + > >> > >> Aren't those two above already defined in some *.h files? > >> > > I replaced msleep with mdelay as Marek suggested. > > I couldn't find the simple shift op define as field. > > Perhaps check out ? I believe FIELD_PREP is similar to > what you have there. > One has to go two levels deep to see what FIELD_PREP, as compared to the simple (value << shift) needed in the code. But I am ok doing that, whatever floats the boat. Cheers!
[PATCHv3] usb: max3420: add the gadget driver
From: Jassi Brar
MAX3420 implements FullSpeed USB Device over SPI.
Another version MAX3421, also implements USB Host mode.
This driver should be good for the device mode of max3421 as well.
Signed-off-by: Jassi Brar
---
Changes since v2:
- used FIELD_PREP instead of simple left shift operation
---
drivers/usb/gadget/Kconfig| 6 +
drivers/usb/gadget/Makefile | 1 +
drivers/usb/gadget/gadget_chips.h | 8 +
drivers/usb/gadget/max3420_udc.c | 875 ++
4 files changed, 890 insertions(+)
create mode 100644 drivers/usb/gadget/max3420_udc.c
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 46aa3fe954..7c0df5c264 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -105,6 +105,12 @@ config CI_UDC
Say Y here to enable device controller functionality of the
ChipIdea driver.
+config USB_GADGET_MAX3420
+ bool "MAX3420 USB Over SPI"
+ depends on DM_SPI
+ help
+ MAX3420, from MAXIM, implements USB-over-SPI Full-Speed device
controller.
+
config USB_GADGET_VBUS_DRAW
int "Maximum VBUS Power usage (2-500 mA)"
range 2 500
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 70f3bf43e7..f560068b41 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_USB_GADGET_BCM_UDC_OTG_PHY) += bcm_udc_otg_phy.o
obj-$(CONFIG_USB_GADGET_DWC2_OTG) += dwc2_udc_otg.o
obj-$(CONFIG_USB_GADGET_DWC2_OTG_PHY) += dwc2_udc_otg_phy.o
obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o
+obj-$(CONFIG_USB_GADGET_MAX3420) += max3420_udc.o
obj-$(CONFIG_CI_UDC) += ci_udc.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_GADGET_DOWNLOAD) += g_dnl.o
diff --git a/drivers/usb/gadget/gadget_chips.h
b/drivers/usb/gadget/gadget_chips.h
index 91b0285244..587204cfb7 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -155,6 +155,12 @@
#define gadget_is_cdns3(g)0
#endif
+#ifdef CONFIG_USB_GADGET_MAX3420
+#define gadget_is_max3420(g)(!strcmp("max3420-udc", (g)->name))
+#else
+#define gadget_is_max3420(g)0
+#endif
+
/**
* usb_gadget_controller_number - support bcdDevice id convention
* @gadget: the controller being driven
@@ -216,5 +222,7 @@ static inline int usb_gadget_controller_number(struct
usb_gadget *gadget)
return 0x23;
else if (gadget_is_cdns3(gadget))
return 0x24;
+ else if (gadget_is_max3420(gadget))
+ return 0x25;
return -ENOENT;
}
diff --git a/drivers/usb/gadget/max3420_udc.c b/drivers/usb/gadget/max3420_udc.c
new file mode 100644
index 00..b38b9dc68f
--- /dev/null
+++ b/drivers/usb/gadget/max3420_udc.c
@@ -0,0 +1,875 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MAX3420_MAX_EPS4
+#define EP_MAX_PACKET 64 /* Same for all Endpoints */
+#define EPNAME_SIZE16 /* Buffer size for endpoint name */
+
+#define MAX3420_SPI_DIR_RD 0 /* read register from MAX3420 */
+#define MAX3420_SPI_DIR_WR 1 /* write register to MAX3420 */
+
+/* SPI commands: */
+#define MAX3420_SPI_ACK_MASK BIT(0)
+#define MAX3420_SPI_DIR_MASK BIT(1)
+#define MAX3420_SPI_REG_MASK GENMASK(7, 3)
+
+#define MAX3420_REG_EP0FIFO0
+#define MAX3420_REG_EP1FIFO1
+#define MAX3420_REG_EP2FIFO2
+#define MAX3420_REG_EP3FIFO3
+#define MAX3420_REG_SUDFIFO4
+#define MAX3420_REG_EP0BC 5
+#define MAX3420_REG_EP1BC 6
+#define MAX3420_REG_EP2BC 7
+#define MAX3420_REG_EP3BC 8
+
+#define MAX3420_REG_EPSTALLS 9
+ #define bACKSTATBIT(6)
+ #define bSTLSTATBIT(5)
+ #define bSTLEP3IN BIT(4)
+ #define bSTLEP2IN BIT(3)
+ #define bSTLEP1OUT BIT(2)
+ #define bSTLEP0OUT BIT(1)
+ #define bSTLEP0IN BIT(0)
+
+#define MAX3420_REG_CLRTOGS10
+ #define bEP3DISAB BIT(7)
+ #define bEP2DISAB BIT(6)
+ #define bEP1DISAB BIT(5)
+ #define bCTGEP3IN BIT(4)
+ #define bCTGEP2IN BIT(3)
+ #define bCTGEP1OUT BIT(2)
+
+#define MAX3420_REG_EPIRQ 11
+#define MAX3420_REG_EPIEN 12
+ #define bSUDAVIRQ BIT(5)
+ #define bIN3BAVIRQ BIT(4)
+ #define bIN2BAVIRQ BIT(3)
+ #define bOUT1DAVIRQ BIT(2)
+ #define bOUT0DAVIRQ BIT(1)
+ #define bIN0BAVIRQ BIT(0)
+
+#define MAX3420_REG_USBIRQ 13
+#define MAX3420_REG_USBIEN 14
+ #define bOSCOKIRQ BIT(0)
+ #define bRWUDNIRQ BIT(1)
+ #define bBUSACTIRQ BIT(2)
+ #define bURESIRQBIT(3)
+ #define bSUSPIRQBIT(4)
+ #define bNOVBUSIRQ BIT(5)
+ #define bVBUSIRQBIT(6)
+
Re: [PATCH 3/3] mkimage: fit: don't cipher ciphered data
On Thu, Jul 30, 2020 at 3:17 AM Philippe REYNES
wrote:
>
> As for the second patch, I think that the loop is not an issue because
> it always start with "fresh/clean" value (using a backup file).
>
> So I am not sure that changes in this function are needed.
>
OK, I overlooked this.
I will resubmit a simplified patch series.
>
> > static int
> > @@ -482,7 +492,7 @@ int fit_image_cipher_data(const char *keydir, void
> > *keydest,
> > const char *image_name;
> > const void *data;
> > size_t size;
> > - int cipher_node_offset;
> > + int cipher_node_offset, len;
> >
> > /* Get image name */
> > image_name = fit_get_name(fit, image_noffset, NULL);
> > @@ -497,6 +507,13 @@ int fit_image_cipher_data(const char *keydir, void
> > *keydest,
> > return -1;
> > }
> >
> > + /* Don't cipher ciphered data */
> > + if (fdt_getprop(fit, image_noffset, "data-size-unciphered", ))
> > + return 0;
> > + if (len != -FDT_ERR_NOTFOUND) {
> > + printf("Failure testing for data-size-unciphered\n");
> > + return -1;
> > + }
>
> From my point of view, it fixes an issue. But I see this solution more
> as "workaround" than a clean solution.
>
> As it fixes a real issue, we may start with it and then try to found a
> "clean" solution.
>
True, it's not ideal. But at least it fixes the bug :)
Thanks for the review,
Patrick
Re: [PATCH 2/3] mkimage: fit: handle FDT_ERR_NOSPACE when ciphering
On Thu, Jul 30, 2020 at 1:02 AM Philippe REYNES
wrote:
>
> Hi Patrick
>
> > From: Patrick Oppenlander
> >
> > This meant that the order of operations had to change. If we replace the
> > data property first then fail to add the data-size-unciphered property
> > the data will be ciphered again when retrying.
>
>
> This patch is good, but I disagree with the comment. It is not mandatory
> to change the order of operation because when signing/ciphering we always
> start from "fresh" file.
>
> This "trick" is done in the function fit_handle_file(...)
>
> Just before the loop, the tmpfile is rename in bakfile
>
> sprintf(bakfile, "%s%s", tmpfile, ".bak");
> rename(tmpfile, bakfile);
>
> And in the loop, the first operation is to copy bakfile to tmpfile:
>
> for (size_inc = 0; size_inc < 64 * 1024; size_inc += 1024) {
> if (copyfile(bakfile, tmpfile) < 0) {
> printf("Can't copy %s to %s\n", bakfile, tmpfile);
> ret = -EIO;
> break;
> }
> ret = fit_add_file_data(params, size_inc, tmpfile);
> if (!ret || ret != -ENOSPC)
> break;
> }
>
> So I think that we always cipher with unciphered data.
>
Hi Philip,
I don't think that is the case if you use "mkimage -F". The input can
already be ciphered.
Patrick
Re: [PATCH v1 2/3] configs: pico-imx6ul: convert DM_VIDEO
On Tue, Jul 28, 2020 at 11:35 PM wrote: > > From: Wig Cheng > > Fix compile warning messages. One more thing: you did a good job in writing the commit logs for the other patches, but this one needs to be improved.
Re: [PATCH v1 3/3] pico-imx6ul: convert ethernet function to DM_ETH
On Tue, Jul 28, 2020 at 11:36 PM wrote: > > From: Wig Cheng > > - Remove pinmux definition from pico-imx6ul.c > - Enable NET_RANDOM_ETHADDR for temporary solution, because micrel_ksz8xxx > driver does not support DM_ETH yet, so cannot read MAC address directly. > > Before enable DM_ETH: > Net: FEC [PRIME] > > After enable DM_ETH: > Net: > Warning: using random MAC address - ca:3f:43:8f:67:d4 > eth1: ethernet@20b4000 > > Here is the test commands: > => dhcp > BOOTP broadcast 1 > DHCP client bound to address 10.88.88.94 (139 ms) > *** ERROR: `serverip' not set > Cannot autoload with TFTPGET > => ping 8.8.8.8 > Using ethernet@20b4000 device > host 8.8.8.8 is alive > > Signed-off-by: Wig Cheng > --- > board/technexion/pico-imx6ul/pico-imx6ul.c | 53 -- > configs/pico-imx6ul_defconfig | 2 + > 2 files changed, 2 insertions(+), 53 deletions(-) > > diff --git a/board/technexion/pico-imx6ul/pico-imx6ul.c > b/board/technexion/pico-imx6ul/pico-imx6ul.c > index 5d6be26faa..126823fce0 100644 > --- a/board/technexion/pico-imx6ul/pico-imx6ul.c > +++ b/board/technexion/pico-imx6ul/pico-imx6ul.c > @@ -18,7 +18,6 @@ > #include > #include > #include This one could be also removed.
Re: [PULL] Pull request: u-boot-stm32 for v2020.10= u-boot-stm32-20200729
On Wed, Jul 29, 2020 at 07:56:09AM +, Patrice CHOTARD wrote: > Hi Tom, > > Please pull the STM32 related patches for v2020.10: u-boot-stm32-20200729 > > With the following changes: > - fix SPL boot issue due to early dbgmcu_init() call > - fix SPL boot issue due to dcache memory region configuration > - add support of CONFIG_ENV_IS_IN_MMC > - add specific SD/eMMC partition for U-Boot enviromnent > - enable env in SPL > - use "env info -q" to remove log during boot > - remove env location override for dh_stm32mp1 > - update management of misc_read > - check result of find_mmc_device in stm32prog > - use regulator_set_enable_if_allowed for disabling vdd supply in usbphyc > - enable CMD_ADTIMG flag to handle Android images > - device tree alignment with Linux Kernel v5.8-rc1 > - remove hnp-srp-disable for usbotg on dk1 > - add reset support to uart nodes on stm32mp15x > - use correct weak function name spl_board_prepare_for_linux > - use cd-gpios for ST and DHSOM boards > - add seeed studio odyssey-stm32mp157c board support > - move ethernet PHY into SoM DT > - add DHSOM based DRC02 board support > > CI status: > https://gitlab.denx.de/u-boot/custodians/u-boot-stm/pipelines/4229 > > > Thanks > Patrice > > The following changes since commit 1db942b67d00a3569efbbd3f36140470b0e59b2e: > > Prepare v2020.10-rc1 (2020-07-27 22:46:03 -0400) > > are available in the Git repository at: > > https://gitlab.denx.de/u-boot/custodians/u-boot-stm > > for you to fetch changes up to 0b263a905a02bd3ae7516149490a98462d966f55: > > ARM: dts: stm32: Add DHSOM based DRC02 board (2020-07-28 18:35:01 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v1 2/3] configs: pico-imx6ul: convert DM_VIDEO
On Tue, Jul 28, 2020 at 11:35 PM wrote: > > From: Wig Cheng > > Fix compile warning messages. > > Signed-off-by: Wig Cheng > --- > configs/pico-imx6ul_defconfig | 6 +- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig > index e8cbf3bc1e..f02d370b7d 100644 > --- a/configs/pico-imx6ul_defconfig > +++ b/configs/pico-imx6ul_defconfig > @@ -75,4 +75,8 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" > CONFIG_USB_GADGET_VENDOR_NUM=0x0525 > CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 > CONFIG_CI_UDC=y > -CONFIG_VIDEO=y > +CONFIG_DM_VIDEO=y > +CONFIG_VIDEO_PCI_DEFAULT_FB_SIZE=0x0 Why is this one needed?
Re: [PATCH v1 1/3] configs: pico-imx6ul: convert DM_USB
Hi Wig, On Tue, Jul 28, 2020 at 11:07 PM wrote: > > From: Wig Cheng > > Here is the test commands: > > => ums 0 mmc 0 > UMS: LUN 0, dev 0, hwpart 0, sector 0x0, count 0x71 > > Signed-off-by: Wig Cheng > --- > configs/pico-imx6ul_defconfig | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig > index 72d2af19f4..49e406316a 100644 > --- a/configs/pico-imx6ul_defconfig > +++ b/configs/pico-imx6ul_defconfig > @@ -67,6 +67,8 @@ CONFIG_DM_REGULATOR_FIXED=y > CONFIG_DM_REGULATOR_GPIO=y > CONFIG_MXC_UART=y > CONFIG_USB=y > +CONFIG_DM_USB=y > +# CONFIG_USB_STORAGE is not set It seems that CONFIG_USB_STORAGE is already unselected, so no need to explicitly unselect it.
Re: [PATCH v2] configs: pico-imx6: convert ethernet function to DM_ETH
On Tue, Jul 28, 2020 at 11:04 PM wrote: > > From: Wig Cheng > > Before enable _DM_ETH: > Net: FEC [PRIME] > > After enable DM_ETH: > Net: eth0: ethernet@2188000 > > Here is the test commands: > => dhcp > BOOTP broadcast 1 > DHCP client bound to address 10.88.88.152 (146 ms) > *** ERROR: `serverip' not set > Cannot autoload with TFTPGET > => ping 8.8.8.8 > Using ethernet@2188000 device > host 8.8.8.8 is alive > > Signed-off-by: Wig Cheng Reviewed-by: Fabio Estevam
Re: Please pull u-boot-dm
+Kever Yang too (for Rockchip) On Tue, 28 Jul 2020 at 20:38, Simon Glass wrote: > > Hi Tom, > > The following changes since commit 3b191c56c841596771b4120f09fb556adf958b5c: > > Merge branch '2020-07-28-Kconfig-migrations' (2020-07-28 18:27:34 -0400) > > are available in the Git repository at: > > git://git.denx.de/u-boot-dm.git tags/dm-pull-28jul20 > > for you to fetch changes up to b9390ce51cb46f4b4acda320e7ea8e0bd120e4b8: > > dm: remove superfluous comment for union ofnode_union (2020-07-28 > 19:30:39 -0600) > > > Use binman instead of one of the Rockchip build scripts > Refactor to allow any arch to create SPI-flash images > New button uclass > > > Dan Murphy (1): > dm: Fix build error when OF_CONTROL is not set > > Heinrich Schuchardt (2): > cmd: host: return value of do_host_bind() > dm: remove superfluous comment for union ofnode_union > > Patrick Oppenlander (1): > sandbox: enable FIT cipher support in defconfig > > Philippe Reynes (9): > sandbox, test: change hog gpio > dm: button: add an uclass for button > dm: button: add a driver for button driven by gpio > cmd: button: add a new 'button' command > sandbox: dtsi: add buttons > sandbox64: enable button > sandbox: enable button > test/py: add tests for the button commands > test: dm: add a test for class button > > Simon Glass (30): > buildman: Allow using older versions of genboardscfg.py > buildman: Correct the testOutputDir() unit test > buildman: Show the build rate at the end > x86: Change how selection of ROMs works > rockchip: Allow Bob to use SPI boot > Makefile: Allow building .rom files for non-x86 boards > rockchip: jerry: Add serial support > rockchip: bob: Support SPI-flash booting > rockchip: Enable building a SPI ROM image on jerry > rockchip: Enable building a SPI ROM image on bob > tegra: Drop the unused non-binman code > tegra: Don't enable binman on ARMv8 SoCs > Makefile: Rename ALL-y to INPUTS-y > powerpc: mpc85xx: Only enable binman when it is needed > x86: Makefile: Drop explicit targets built by binman > x86: Drop CONFIG_BUILD_ROM and repurpose BUILD_ROM > sunxi: Makefile: Drop explicit targets built by binman > tegra: Makefile: Drop explicit targets built by binman > mediatek: Makefile: Drop explicit targets built by binman > Makefile: Move CONFIG_TOOLS_DEBUG check to later > Makefile: Fix a long line in cmd_mkfitimage > Makefile: Allow CONFIG_SPL_FIT_GENERATOR to be empty > Makefile: Warn against using CONFIG_SPL_FIT_GENERATOR > rockchip: Convert evb-rk3288 over to use binman > rockchip: Convert evb-rk3229 over to use binman > rockchip: Drop the fit_spl_optee.sh script > x86: Move the fdtmap away from the binary blobs > x86: chromebook_link64: Correct the image layout > x86: chromebook_panther: Correct the image layout > x86: chromebook_samus_tpl: Correct the image layout > > Walter Lozano (4): > dtoc: add coverage test for unicode error > dtoc: look for compatible string aliases in driver list > drivers: avoid using aliases on drivers when OF_PLATDATA is enabled > dtoc: remove compatible string aliases support > > chenshuo (1): > find dtb in android boot image with header version 2 during bootm > > Kconfig | 29 +++- > Makefile | 169 > +- > arch/Kconfig | 1 + > arch/arm/config.mk| 10 +-- > arch/arm/dts/rk3288-u-boot.dtsi | 25 +++ > arch/arm/dts/rk3399-gru-u-boot.dtsi | 4 ++ > arch/arm/dts/rk3399-gru.dtsi | 2 +- > arch/arm/dts/rk3399-u-boot.dtsi | 27 > arch/arm/dts/rockchip-optee.dtsi | 64 ++ > arch/arm/dts/rockchip-u-boot.dtsi | 10 ++- > arch/arm/mach-at91/config.mk | 2 +- > arch/arm/mach-davinci/config.mk | 2 +- > arch/arm/mach-k3/config.mk| 10 +-- > arch/arm/mach-keystone/config.mk | 4 +- > arch/arm/mach-omap2/config.mk | 28 > arch/arm/mach-rmobile/Makefile| 2 +- > arch/arm/mach-rockchip/Kconfig| 9 +++ > arch/arm/mach-rockchip/fit_spl_optee.sh | 84 --- > arch/arm/mach-rockchip/rk3288/Kconfig | 3 + > arch/arm/mach-rockchip/rk3399/Kconfig | 2 + > arch/arm/mach-rockchip/spl.c | 3 +- > arch/arm/mach-stm32mp/config.mk | 4 +- > arch/arm/mach-tegra/Kconfig | 2 +- > arch/powerpc/Kconfig | 2 +- >
master u-boot broken for HiFive Unleashed
Hi, The latest master (423e08cb7701 (origin/master, origin/HEAD) Merge branch '2020-07-28-misc-soc-improvements') seems to be broken for HiFive Unleashed. It already has Bin's fix for unleashed. a0018fc8209c riscv: Make SiFive HiFive Unleashed board boot again dram start and size is corrupted for some reason. I have verified that it was initialized properly during DT parsing. However, it shows random values in the U-Boot console. => bdinfo boot_params = 0x memstart= 0x memsize = 0x flashstart = 0x flashsize = 0x flashoffset = 0x baudrate= 115200 bps relocaddr = 0xfff84000 reloc off = 0x7fd84000 Build = 64-bit => bdinfo boot_params = 0x9a26a361c16aa601 DRAM bank = 0x -> start= 0x974515c3bda965ef -> size = 0x79b6f0fb37923036 memstart= 0x574587c7f00570f9 memsize = 0xCFD8C0F4D42668AB flashstart = 0x67f9fbb06586658b flashsize = 0xf91aed913c99b9e1 flashoffset = 0x9ddbf00d69e870fa baudrate= 115200 bps v2020.07 seems to work fine. I couldn't bisect between those two as the number of commits didn't compile. -- Regards, Atish
[PATCH] riscv: additional crash information
If an exception occurs, the relocated program counter and return address
are required for an analysis.
With this patch you get:
=> exception undefined
Unhandled exception: Illegal instruction
EPC: 80595908 RA: 8059c0c6 TVAL: 8030c01e
EPC: 80007908 RA: 8000e0c6 reloc
We can use the relocated addresses to find the involved functions in
u.boot.map:
.text.do_undefined
0x800079080x8 cmd/built-in.o
.text.cmd_process
0x8000dfcc 0x11a common/built-in.o
0x8000dfcccmd_process
If an exception occurs in an UEFI binary additionally the load addresses of
the UEFI binaries are needed. With this patch:
=> setenv efi_selftest exception
=> bootefi selftest
Unhandled exception: Illegal instruction
EPC: 8042e18a RA: 8042e18a TVAL: 8030c01e
EPC: 7fea018a RA: 7fea018a reloc
UEFI image [0x:0x] '/\selftest'
UEFI image [0x8042e000:0x8042e43f] pc=0x18a '/bug.efi'
The value pc=0x18a matches the position of the illegal instruction in
efi_selftest_miniapp_exception.efi (loaded as /bug.efi);
asm volatile (".word 0x\n");
0180 93 85 C5 11 1C 64 22 85 82 97 FF FF FF FF 1C 64
Signed-off-by: Heinrich Schuchardt
---
arch/riscv/lib/interrupts.c | 57 +++--
1 file changed, 35 insertions(+), 22 deletions(-)
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index 074c70ee77..bcdfc5ea3a 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -10,36 +10,43 @@
*/
#include
+#include
#include
#include
#include
#include
#include
+DECLARE_GLOBAL_DATA_PTR;
+
+static void show_efi_loaded_images(uintptr_t epc)
+{
+ efi_print_image_infos((void *)epc);
+}
+
static void show_regs(struct pt_regs *regs)
{
#ifdef CONFIG_SHOW_REGS
- printf("RA: " REG_FMT " SP: " REG_FMT " GP: " REG_FMT "\n",
- regs->ra, regs->sp, regs->gp);
- printf("TP: " REG_FMT " T0: " REG_FMT " T1: " REG_FMT "\n",
- regs->tp, regs->t0, regs->t1);
- printf("T2: " REG_FMT " S0: " REG_FMT " S1: " REG_FMT "\n",
- regs->t2, regs->s0, regs->s1);
- printf("A0: " REG_FMT " A1: " REG_FMT " A2: " REG_FMT "\n",
- regs->a0, regs->a1, regs->a2);
- printf("A3: " REG_FMT " A4: " REG_FMT " A5: " REG_FMT "\n",
- regs->a3, regs->a4, regs->a5);
- printf("A6: " REG_FMT " A7: " REG_FMT " S2: " REG_FMT "\n",
- regs->a6, regs->a7, regs->s2);
- printf("S3: " REG_FMT " S4: " REG_FMT " S5: " REG_FMT "\n",
- regs->s3, regs->s4, regs->s5);
- printf("S6: " REG_FMT " S7: " REG_FMT " S8: " REG_FMT "\n",
- regs->s6, regs->s7, regs->s8);
- printf("S9: " REG_FMT " S10: " REG_FMT " S11: " REG_FMT "\n",
- regs->s9, regs->s10, regs->s11);
- printf("T3: " REG_FMT " T4: " REG_FMT " T5: " REG_FMT "\n",
- regs->t3, regs->t4, regs->t5);
- printf("T6: " REG_FMT "\n", regs->t6);
+ printf("SP: " REG_FMT " GP: " REG_FMT " TP: " REG_FMT "\n",
+ regs->sp, regs->gp, regs->tp);
+ printf("T0: " REG_FMT " T1: " REG_FMT " T2: " REG_FMT "\n",
+ regs->t0, regs->t1, regs->t2);
+ printf("S0: " REG_FMT " S1: " REG_FMT " A0: " REG_FMT "\n",
+ regs->s0, regs->s1, regs->a0);
+ printf("A1: " REG_FMT " A2: " REG_FMT " A3: " REG_FMT "\n",
+ regs->a1, regs->a2, regs->a3);
+ printf("A4: " REG_FMT " A5: " REG_FMT " A6: " REG_FMT "\n",
+ regs->a4, regs->a5, regs->a6);
+ printf("A7: " REG_FMT " S2: " REG_FMT " S3: " REG_FMT "\n",
+ regs->a7, regs->s2, regs->s3);
+ printf("S4: " REG_FMT " S5: " REG_FMT " S6: " REG_FMT "\n",
+ regs->s4, regs->s5, regs->s6);
+ printf("S7: " REG_FMT " S8: " REG_FMT " S9: " REG_FMT "\n",
+ regs->s7, regs->s8, regs->s9);
+ printf("S10: " REG_FMT " S11: " REG_FMT " T3: " REG_FMT "\n",
+ regs->s10, regs->s11, regs->t3);
+ printf("T4: " REG_FMT " T5: " REG_FMT " T6: " REG_FMT "\n\n",
+ regs->t4, regs->t5, regs->t6);
#endif
}
@@ -69,8 +76,14 @@ static void _exit_trap(ulong code, ulong epc, ulong tval,
struct pt_regs *regs)
else
printf("Unhandled exception code: %ld\n", code);
- printf("EPC: " REG_FMT " TVAL: " REG_FMT "\n", epc, tval);
+ printf("EPC: " REG_FMT " RA: " REG_FMT " TVAL: " REG_FMT "\n",
+ epc, regs->ra, tval);
+ if (gd->flags & GD_FLG_RELOC)
+ printf("EPC: " REG_FMT " RA: " REG_FMT " reloc\n\n",
+ epc - gd->reloc_off, regs->ra - gd->reloc_off);
+
show_regs(regs);
+
Re: [PATCH v4 3/3] board: ns3: add development keys used in FIT
On Wed, Jul 15, 2020 at 10:55:41PM +0530, Rayagonda Kokatanur wrote: > From: Pramod Kumar > > Add development keys used in FIT. > > Signed-off-by: Pramod Kumar > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 2/2] arch: arm: use dt and UCLASS_SYSCON to get gic lpi details
On Sun, Jul 26, 2020 at 10:37:33PM +0530, Rayagonda Kokatanur wrote: > Use device tree and UCLASS_SYSCON driver to get > Generic Interrupt Controller (GIC) lpi address and > maximum GIC redistributors count. > > Also update Kconfig to select REGMAP and SYSCON when > GIC_V3_ITS is enabled. > > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 1/2] drivers: tee: broadcom: add optee based bnxt fw load driver
On Wed, Jul 15, 2020 at 10:57:19PM +0530, Rayagonda Kokatanur wrote: > From: Vikas Gupta > > Add optee based bnxt fw load driver. > bnxt is Broadcom NetXtreme controller Ethernet card. > This driver is used to load bnxt firmware binary using OpTEE. > > Signed-off-by: Vikas Gupta > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 2/3] board: ns3: add FIT image its file
On Wed, Jul 15, 2020 at 10:55:40PM +0530, Rayagonda Kokatanur wrote: > From: Pramod Kumar > > Add FIT image its file. > > Signed-off-by: Pramod Kumar > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 2/2] configs: ns3: enable tee and optee driver
On Wed, Jul 15, 2020 at 10:57:20PM +0530, Rayagonda Kokatanur wrote: > Enable tee and optee drivers. > > Signed-off-by: Vikas Gupta > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 1/2] arch: arm: use dt and UCLASS_IRQ to get gic details
On Sun, Jul 26, 2020 at 10:37:32PM +0530, Rayagonda Kokatanur wrote: > Use device tree and UCLASS_IRQ driver to get following > Generic Interrupt Controller (GIC) details, > > -GIC Distributor interface (GICD) base address and > -GIC Redistributors (GICR) base address. > > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 1/3] configs: ns3: enable FIT config
On Wed, Jul 15, 2020 at 10:55:39PM +0530, Rayagonda Kokatanur wrote: > Enable FIT config for NS3. > > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 5/7] configs: ns3: enable gpt commands
On Wed, Jul 15, 2020 at 10:53:05PM +0530, Rayagonda Kokatanur wrote: > Enable gpt commands for ns3. > > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 7/7] configs: ns3: enable sp805 watchdog driver
On Wed, Jul 15, 2020 at 10:53:07PM +0530, Rayagonda Kokatanur wrote: > Enable sp805 watchdog driver for ns3. > > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 3/7] configs: ns3: enable BCM IPROC mmc driver
On Wed, Jul 15, 2020 at 10:53:03PM +0530, Rayagonda Kokatanur wrote: > Enable BCM IPROC mmc driver ns3. > Enable DMA for MMC Host to have better reads and writes. > > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 6/7] configs: ns3: enable EXT4 and FAT fs support
On Wed, Jul 15, 2020 at 10:53:06PM +0530, Rayagonda Kokatanur wrote: > Enable EXT4 and FAT fs support for ns3. > > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 2/7] dt-bindings: pinctrl: add ns3 pads definition
On Wed, Jul 15, 2020 at 10:53:02PM +0530, Rayagonda Kokatanur wrote: > Add NS3 pads definitions. > > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 4/7] configs: ns3: enable mmc commands
On Wed, Jul 15, 2020 at 10:53:04PM +0530, Rayagonda Kokatanur wrote: > Enable mmc commands for NS3. > > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 1/7] configs: ns3: enable pinctrl driver
On Wed, Jul 15, 2020 at 10:53:01PM +0530, Rayagonda Kokatanur wrote: > Enable pinctrl driver for ns3. > > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 15/15] MAINTAINERS: update maintainers for broadcom ns3 platform
On Wed, Jul 15, 2020 at 10:49:09PM +0530, Rayagonda Kokatanur wrote: > Update MAINTAINERS for broadcom ns3 platform (TARGET_NS3). > > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 13/15] include/configs: ns3: add support for flashing images
On Wed, Jul 15, 2020 at 10:49:07PM +0530, Rayagonda Kokatanur wrote: > From: Bharat Gooty > > Add support for flashing images into QSPI and eMMC. > > Signed-off-by: Bharat Gooty > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 14/15] doc: add README doc for bcmns3 platform
On Wed, Jul 15, 2020 at 10:49:08PM +0530, Rayagonda Kokatanur wrote: > Add README doc for bcmns3 platform. > > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 09/15] dt-bindings: memory: ns3: add ddr memory definition
On Wed, Jul 15, 2020 at 10:49:03PM +0530, Rayagonda Kokatanur wrote: > Add ddr memory definitions. > > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 12/15] include/configs: ns3: add env variables for Linux boot
On Wed, Jul 15, 2020 at 10:49:06PM +0530, Rayagonda Kokatanur wrote: > From: Bharat Gooty > > Add env variables and commands for booting Linux. > > Signed-off-by: Bharat Gooty > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 11/15] board: ns3: limit U-boot relocation within 16MB memory
On Wed, Jul 15, 2020 at 10:49:05PM +0530, Rayagonda Kokatanur wrote: > From: Bharat Kumar Reddy Gooty > > By default relocation happens to a higher address of DDR, > i.e, DDR start + DDR size. > > U-Boot shall be used to collect the ramdump. > Restrict U-Boot to use only the 16MB memory, so that this > memory can be reserved. Limit relocation to happen within > 16MB memory, start 0xFF00_ and end 0x1__ > > Signed-off-by: Bharat Kumar Reddy Gooty > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 10/15] board: ns3: define ddr memory layout
On Wed, Jul 15, 2020 at 10:49:04PM +0530, Rayagonda Kokatanur wrote: > Add both DRAM banks memory information and > the corresponding MMU page table mappings. > > Signed-off-by: Bharat Kumar Reddy Gooty > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 08/15] configs: ns3: enable GIC_V3 ITS
On Wed, Jul 15, 2020 at 10:49:02PM +0530, Rayagonda Kokatanur wrote: > Enables the Generic Interrupt Controller (GIC) V3 > Interrupt Translation Service (ITS) Locality-specific Peripheral > Interrupts (LPI) configuration table and LPI table. > > Signed-off-by: Rayagonda Kokatanur > Signed-off-by: Bharat Kumar Reddy Gooty > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 04/15] dt-bindings: memory: ns3: add memory definitions
On Wed, Jul 15, 2020 at 10:48:58PM +0530, Rayagonda Kokatanur wrote: > Add NS3 memory definitions. > > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 07/15] board: ns3: program GIC LPI tables
On Wed, Jul 15, 2020 at 10:49:01PM +0530, Rayagonda Kokatanur wrote: > U-boot programs the GIC LPI configuration tables and enables > the LPI table. > > Signed-off-by: Bharat Kumar Reddy Gooty > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 06/15] board: ns3: default reset type to L3
On Wed, Jul 15, 2020 at 10:49:00PM +0530, Rayagonda Kokatanur wrote: > Default "reset" from U-Boot to L3 reset. > "reset" command with argument will trigger L1 reset. > > Signed-off-by: Rajesh Ravi > Signed-off-by: Bharat Kumar Reddy Gooty > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 05/15] board: ns3: add api to save boot parameters passed from BL31
On Wed, Jul 15, 2020 at 10:48:59PM +0530, Rayagonda Kokatanur wrote: > From: Abhishek Shah > > Add API to save boot parameters passed from BL31 > > Use assembly implementation of save_boot_params instead of c function. > Because generally ATF does not set up SP_EL2 on exiting. > Thus, usage of a C function immediately after exiting with no stack > setup done by ATF explicitly, may cause SP_EL2 to be not sane, > which in turn causes a crash if this boot was not lucky to get > an SP_EL2 in valid range. Replace C implementation with assembly one > which does not use stack this early, and let u-boot to set up its stack > later. > > Signed-off-by: Abhishek Shah > Signed-off-by: Rajesh Ravi > Signed-off-by: Vladimir Olovyannikov > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 03/15] configs: ns3: enable clock subsystem
On Wed, Jul 15, 2020 at 10:48:57PM +0530, Rayagonda Kokatanur wrote: > Enable clock subsystem for ns3. > > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 02/15] arm: cpu: armv8: add L3 memory flush support
On Wed, Jul 15, 2020 at 10:48:56PM +0530, Rayagonda Kokatanur wrote: > Add L3 memory flush support for NS3. > > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v6 2/2] gpio: do not include on TARGET_BCMNS3
On Tue, May 05, 2020 at 11:26:47PM +0530, Rayagonda Kokatanur wrote: > As no gpio.h is defined for this architecture, to avoid > compilation failure, do not include for > arch bcmns3. > > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 01/15] board: ns3: add support for Broadcom Northstar 3
On Wed, Jul 15, 2020 at 10:48:55PM +0530, Rayagonda Kokatanur wrote: > Add support for Broadcom Northstar 3 SoC. > NS3 is a octo-core 64-bit ARMv8 Cortex-A72 processors > targeting a broad range of networking applications. > > Signed-off-by: Rayagonda Kokatanur > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v6 1/2] drivers: gpio: add broadcom iproc gpio driver support
On Tue, May 05, 2020 at 11:26:46PM +0530, Rayagonda Kokatanur wrote: > Add gpio driver support for Broadcom iproc-based socs. > > Signed-off-by: Rayagonda Kokatanur > Signed-off-by: Sheetal Tigadoli > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PATCH 09/22] clk: at91: move clock code to compat.c
Move clock code to compat.c to allow switching to CCF
without mixing CCF code with non CCF code. This prepares the
field for next commits.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Makefile | 13 +-
drivers/clk/at91/clk-generated.c | 178 ---
drivers/clk/at91/clk-h32mx.c | 56 --
drivers/clk/at91/clk-main.c | 54 --
drivers/clk/at91/clk-master.c | 33 --
drivers/clk/at91/clk-peripheral.c | 113
drivers/clk/at91/clk-plla.c | 54 --
drivers/clk/at91/clk-plladiv.c| 85 ---
drivers/clk/at91/clk-slow.c | 36 --
drivers/clk/at91/clk-system.c | 111
drivers/clk/at91/clk-usb.c| 147 --
drivers/clk/at91/clk-utmi.c | 142 -
drivers/clk/at91/compat.c | 1023 +
drivers/clk/at91/pmc.c| 114 +
drivers/clk/at91/pmc.h| 13 +-
drivers/clk/at91/sckc.c | 19 -
16 files changed, 1030 insertions(+), 1161 deletions(-)
delete mode 100644 drivers/clk/at91/clk-generated.c
delete mode 100644 drivers/clk/at91/clk-h32mx.c
delete mode 100644 drivers/clk/at91/clk-main.c
delete mode 100644 drivers/clk/at91/clk-master.c
delete mode 100644 drivers/clk/at91/clk-peripheral.c
delete mode 100644 drivers/clk/at91/clk-plla.c
delete mode 100644 drivers/clk/at91/clk-plladiv.c
delete mode 100644 drivers/clk/at91/clk-slow.c
delete mode 100644 drivers/clk/at91/clk-system.c
delete mode 100644 drivers/clk/at91/clk-usb.c
delete mode 100644 drivers/clk/at91/clk-utmi.c
create mode 100644 drivers/clk/at91/compat.c
delete mode 100644 drivers/clk/at91/sckc.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 8c197ff949a8..e2413af40360 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -2,11 +2,8 @@
# Makefile for at91 specific clk
#
-obj-y += pmc.o sckc.o
-obj-y += clk-slow.o clk-main.o clk-plla.o clk-plladiv.o clk-master.o
-obj-y += clk-system.o clk-peripheral.o
-
-obj-$(CONFIG_AT91_UTMI)+= clk-utmi.o
-obj-$(CONFIG_AT91_USB_CLK) += clk-usb.o
-obj-$(CONFIG_AT91_H32MX) += clk-h32mx.o
-obj-$(CONFIG_AT91_GENERIC_CLK) += clk-generated.o
+ifdef CONFIG_CLK_CCF
+obj-y += pmc.o
+else
+obj-y += compat.o
+endif
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
deleted file mode 100644
index c0610940c3be..
--- a/drivers/clk/at91/clk-generated.c
+++ /dev/null
@@ -1,178 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016 Atmel Corporation
- * Wenyou.Yang
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include "pmc.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define GENERATED_SOURCE_MAX 6
-#define GENERATED_MAX_DIV 255
-
-/**
- * generated_clk_bind() - for the generated clock driver
- * Recursively bind its children as clk devices.
- *
- * @return: 0 on success, or negative error code on failure
- */
-static int generated_clk_bind(struct udevice *dev)
-{
- return at91_clk_sub_device_bind(dev, "generic-clk");
-}
-
-static const struct udevice_id generated_clk_match[] = {
- { .compatible = "atmel,sama5d2-clk-generated" },
- {}
-};
-
-U_BOOT_DRIVER(generated_clk) = {
- .name = "generated-clk",
- .id = UCLASS_MISC,
- .of_match = generated_clk_match,
- .bind = generated_clk_bind,
-};
-
-/*-*/
-
-struct generic_clk_priv {
- u32 num_parents;
-};
-
-static ulong generic_clk_get_rate(struct clk *clk)
-{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
- struct at91_pmc *pmc = plat->reg_base;
- struct clk parent;
- ulong clk_rate;
- u32 tmp, gckdiv;
- u8 clock_source, parent_index;
- int ret;
-
- writel(clk->id & AT91_PMC_PCR_PID_MASK, >pcr);
- tmp = readl(>pcr);
- clock_source = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) &
- AT91_PMC_PCR_GCKCSS_MASK;
- gckdiv = (tmp >> AT91_PMC_PCR_GCKDIV_OFFSET) & AT91_PMC_PCR_GCKDIV_MASK;
-
- parent_index = clock_source - 1;
- ret = clk_get_by_index(dev_get_parent(clk->dev), parent_index, );
- if (ret)
- return 0;
-
- clk_rate = clk_get_rate() / (gckdiv + 1);
-
- clk_free();
-
- return clk_rate;
-}
-
-static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
-{
- struct pmc_platdata *plat = dev_get_platdata(clk->dev);
- struct at91_pmc *pmc = plat->reg_base;
- struct generic_clk_priv *priv = dev_get_priv(clk->dev);
- struct clk parent, best_parent;
- ulong tmp_rate, best_rate = rate, parent_rate;
- int tmp_diff, best_diff = -1;
- u32 div, best_div = 0;
- u8 best_parent_index, best_clock_source = 0;
- u8 i;
- u32 tmp;
- int ret;
-
- for (i = 0; i < priv->num_parents; i++) {
- ret =
[PATCH 15/22] clk: at91: clk-utmi: add driver compatible with ccf
Add clk-utmi driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-utmi.c | 165
drivers/clk/at91/pmc.h | 3 +
3 files changed, 169 insertions(+)
create mode 100644 drivers/clk/at91/clk-utmi.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index a4e397066e1e..9c38bda5e6b7 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -4,6 +4,7 @@
ifdef CONFIG_CLK_CCF
obj-y += pmc.o sckc.o clk-main.o clk-master.o
+obj-$(CONFIG_AT91_UTMI)+= clk-utmi.o
obj-$(CONFIG_AT91_SAM9X60_PLL) += clk-sam9x60-pll.o
else
obj-y += compat.o
diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c
new file mode 100644
index ..b60fd35b6b6a
--- /dev/null
+++ b/drivers/clk/at91/clk-utmi.c
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * UTMI clock support for AT91 architectures.
+ *
+ * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Claudiu Beznea
+ *
+ * Based on drivers/clk/at91/clk-utmi.c from Linux.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pmc.h"
+
+#define UBOOT_DM_CLK_AT91_UTMI "at91-utmi-clk"
+
+/*
+ * The purpose of this clock is to generate a 480 MHz signal. A different
+ * rate can't be configured.
+ */
+#define UTMI_RATE 48000
+
+struct clk_utmi {
+ void __iomem *base;
+ struct regmap *regmap_sfr;
+ struct clk clk;
+};
+
+#define to_clk_utmi(_clk) container_of(_clk, struct clk_utmi, clk)
+
+static inline bool clk_utmi_ready(struct regmap *regmap)
+{
+ unsigned int status;
+
+ pmc_read(regmap, AT91_PMC_SR, );
+
+ return !!(status & AT91_PMC_LOCKU);
+}
+
+static int clk_utmi_enable(struct clk *clk)
+{
+ struct clk_utmi *utmi = to_clk_utmi(clk);
+ unsigned int uckr = AT91_PMC_UPLLEN | AT91_PMC_UPLLCOUNT |
+ AT91_PMC_BIASEN;
+ unsigned int utmi_ref_clk_freq;
+ ulong parent_rate = clk_get_parent_rate(clk);
+
+ /*
+* If mainck rate is different from 12 MHz, we have to configure the
+* FREQ field of the SFR_UTMICKTRIM register to generate properly
+* the utmi clock.
+*/
+ switch (parent_rate) {
+ case 1200:
+ utmi_ref_clk_freq = 0;
+ break;
+ case 1600:
+ utmi_ref_clk_freq = 1;
+ break;
+ case 2400:
+ utmi_ref_clk_freq = 2;
+ break;
+ /*
+* Not supported on SAMA5D2 but it's not an issue since MAINCK
+* maximum value is 24 MHz.
+*/
+ case 4800:
+ utmi_ref_clk_freq = 3;
+ break;
+ default:
+ debug("UTMICK: unsupported mainck rate\n");
+ return -EINVAL;
+ }
+
+ if (utmi->regmap_sfr) {
+ regmap_update_bits(utmi->regmap_sfr, AT91_SFR_UTMICKTRIM,
+ AT91_UTMICKTRIM_FREQ, utmi_ref_clk_freq);
+ } else if (utmi_ref_clk_freq) {
+ debug("UTMICK: sfr node required\n");
+ return -EINVAL;
+ }
+
+ pmc_update_bits(utmi->base, AT91_CKGR_UCKR, uckr, uckr);
+
+ while (!clk_utmi_ready(utmi->base)) {
+ debug("waiting for utmi...\n");
+ cpu_relax();
+ }
+
+ return 0;
+}
+
+static int clk_utmi_disable(struct clk *clk)
+{
+ struct clk_utmi *utmi = to_clk_utmi(clk);
+
+ pmc_update_bits(utmi->base, AT91_CKGR_UCKR, AT91_PMC_UPLLEN, 0);
+
+ return 0;
+}
+
+static ulong clk_utmi_get_rate(struct clk *clk)
+{
+ /* UTMI clk rate is fixed. */
+ return UTMI_RATE;
+}
+
+static const struct clk_ops utmi_ops = {
+ .enable = clk_utmi_enable,
+ .disable = clk_utmi_disable,
+ .get_rate = clk_utmi_get_rate,
+};
+
+struct clk *at91_clk_register_utmi(void __iomem *base, struct udevice *dev,
+ const char *name, const char *parent_name)
+{
+ struct udevice *syscon;
+ struct clk_utmi *utmi;
+ struct clk *clk;
+ int ret;
+
+ if (!base || !dev || !name || !parent_name)
+ return ERR_PTR(-EINVAL);
+
+ ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
+ "regmap-sfr", );
+ if (ret)
+ return ERR_PTR(ret);
+
+ utmi = kzalloc(sizeof(*utmi), GFP_KERNEL);
+ if (!utmi)
+ return ERR_PTR(-ENOMEM);
+
+ utmi->base = base;
+ utmi->regmap_sfr = syscon_get_regmap(syscon);
+ if (!utmi->regmap_sfr) {
+ kfree(utmi);
+ return ERR_PTR(-ENODEV);
+ }
+
+ clk = >clk;
+ clk->flags = CLK_GET_RATE_NOCACHE;
+ ret = clk_register(clk, UBOOT_DM_CLK_AT91_UTMI, name,
[PATCH 22/22] clk: at91: sama7g5: add clock support
Add clock support for SAMA7G5.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Makefile |1 +
drivers/clk/at91/sama7g5.c | 1401
2 files changed, 1402 insertions(+)
create mode 100644 drivers/clk/at91/sama7g5.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 2cd840af3859..2453c38af1aa 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -9,6 +9,7 @@ obj-y += clk-peripheral.o
obj-$(CONFIG_AT91_GENERIC_CLK) += clk-generic.o
obj-$(CONFIG_AT91_UTMI)+= clk-utmi.o
obj-$(CONFIG_AT91_SAM9X60_PLL) += clk-sam9x60-pll.o
+obj-$(CONFIG_SAMA7G5) += sama7g5.o
else
obj-y += compat.o
endif
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
new file mode 100644
index ..b96937673bed
--- /dev/null
+++ b/drivers/clk/at91/sama7g5.c
@@ -0,0 +1,1401 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SAMA7G5 PMC clock support.
+ *
+ * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Claudiu Beznea
+ *
+ * Based on drivers/clk/at91/sama7g5.c from Linux.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "pmc.h"
+
+/**
+ * Clock identifiers to be used in conjunction with macros like
+ * AT91_TO_CLK_ID()
+ *
+ * @ID_MD_SLCK:TD slow clock identifier
+ * @ID_TD_SLCK:MD slow clock identifier
+ * @ID_MAIN_XTAL: Main Xtal clock identifier
+ * @ID_MAIN_RC:Main RC clock identifier
+ * @ID_MAIN_RC_OSC:Main RC Oscillator clock identifier
+ * @ID_MAIN_OSC: Main Oscillator clock identifier
+ * @ID_MAINCK: MAINCK clock identifier
+ * @ID_PLL_CPU_FRAC: CPU PLL fractional clock identifier
+ * @ID_PLL_CPU_DIV:CPU PLL divider clock identifier
+ * @ID_PLL_SYS_FRAC: SYS PLL fractional clock identifier
+ * @ID_PLL_SYS_DIV:SYS PLL divider clock identifier
+ * @ID_PLL_DDR_FRAC: DDR PLL fractional clock identifier
+ * @ID_PLL_DDR_DIV:DDR PLL divider clock identifier
+ * @ID_PLL_IMG_FRAC: IMC PLL fractional clock identifier
+ * @ID_PLL_IMG_DIV:IMG PLL divider clock identifier
+ * @ID_PLL_BAUD_FRAC: Baud PLL fractional clock identifier
+ * @ID_PLL_BAUD_DIV: Baud PLL divider clock identifier
+ * @ID_PLL_AUDIO_FRAC: Audio PLL fractional clock identifier
+ * @ID_PLL_AUDIO_DIVPMC: Audio PLL PMC divider clock identifier
+ * @ID_PLL_AUDIO_DIVIO:Audio PLL IO divider clock identifier
+ * @ID_PLL_ETH_FRAC: Ethernet PLL fractional clock identifier
+ * @ID_PLL_ETH_DIV:Ethernet PLL divider clock identifier
+
+ * @ID_MCK0: MCK0 clock identifier
+ * @ID_MCK1: MCK1 clock identifier
+ * @ID_MCK2: MCK2 clock identifier
+ * @ID_MCK3: MCK3 clock identifier
+ * @ID_MCK4: MCK4 clock identifier
+
+ * @ID_UTMI: UTMI clock identifier
+
+ * @ID_PROG0: Programmable 0 clock identifier
+ * @ID_PROG1: Programmable 1 clock identifier
+ * @ID_PROG2: Programmable 2 clock identifier
+ * @ID_PROG3: Programmable 3 clock identifier
+ * @ID_PROG4: Programmable 4 clock identifier
+ * @ID_PROG5: Programmable 5 clock identifier
+ * @ID_PROG6: Programmable 6 clock identifier
+ * @ID_PROG7: Programmable 7 clock identifier
+
+ * @ID_PCK0: System clock 0 clock identifier
+ * @ID_PCK1: System clock 1 clock identifier
+ * @ID_PCK2: System clock 2 clock identifier
+ * @ID_PCK3: System clock 3 clock identifier
+ * @ID_PCK4: System clock 4 clock identifier
+ * @ID_PCK5: System clock 5 clock identifier
+ * @ID_PCK6: System clock 6 clock identifier
+ * @ID_PCK7: System clock 7 clock identifier
+ */
+enum pmc_clk_ids {
+ ID_MD_SLCK = 0,
+ ID_TD_SLCK = 1,
+ ID_MAIN_XTAL= 2,
+ ID_MAIN_RC = 3,
+ ID_MAIN_RC_OSC = 4,
+ ID_MAIN_OSC = 5,
+ ID_MAINCK = 6,
+
+ ID_PLL_CPU_FRAC = 7,
+ ID_PLL_CPU_DIV = 8,
+ ID_PLL_SYS_FRAC = 9,
+ ID_PLL_SYS_DIV = 10,
+ ID_PLL_DDR_FRAC = 11,
+ ID_PLL_DDR_DIV = 12,
+ ID_PLL_IMG_FRAC = 13,
+ ID_PLL_IMG_DIV = 14,
+ ID_PLL_BAUD_FRAC= 15,
+ ID_PLL_BAUD_DIV = 16,
+ ID_PLL_AUDIO_FRAC = 17,
+ ID_PLL_AUDIO_DIVPMC = 18,
+ ID_PLL_AUDIO_DIVIO = 19,
+ ID_PLL_ETH_FRAC = 20,
+ ID_PLL_ETH_DIV = 21,
[PATCH 12/22] clk: at91: sam9x60-pll: add driver compatible with ccf
Add sam9x60-pll driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Kconfig | 7 +
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-sam9x60-pll.c | 442 +
drivers/clk/at91/pmc.h | 36 +++
4 files changed, 486 insertions(+)
create mode 100644 drivers/clk/at91/clk-sam9x60-pll.c
diff --git a/drivers/clk/at91/Kconfig b/drivers/clk/at91/Kconfig
index 8d482a275239..4abc8026b4da 100644
--- a/drivers/clk/at91/Kconfig
+++ b/drivers/clk/at91/Kconfig
@@ -54,3 +54,10 @@ config AT91_GENERIC_CLK
that may be different from the system clock. This second
clock is the generic clock (GCLK) and is managed by
the PMC via PMC_PCR register.
+
+config AT91_SAM9X60_PLL
+ bool "PLL support for SAM9X60 SoCs"
+ depends on CLK_AT91
+ help
+ This option is used to enable the AT91 SAM9X60's PLL clock
+ driver.
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 805f67677a9b..338582b88aee 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -4,6 +4,7 @@
ifdef CONFIG_CLK_CCF
obj-y += pmc.o sckc.o clk-main.o
+obj-$(CONFIG_AT91_SAM9X60_PLL) += clk-sam9x60-pll.o
else
obj-y += compat.o
endif
diff --git a/drivers/clk/at91/clk-sam9x60-pll.c
b/drivers/clk/at91/clk-sam9x60-pll.c
new file mode 100644
index ..1bfae5fd0165
--- /dev/null
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -0,0 +1,442 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SAM9X60's PLL clock support.
+ *
+ * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Claudiu Beznea
+ *
+ * Based on drivers/clk/at91/clk-sam9x60-pll.c from Linux.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pmc.h"
+
+#define UBOOT_DM_CLK_AT91_SAM9X60_DIV_PLL "at91-sam9x60-div-pll-clk"
+#define UBOOT_DM_CLK_AT91_SAM9X60_FRAC_PLL "at91-sam9x60-frac-pll-clk"
+
+#definePMC_PLL_CTRL0_DIV_MSK GENMASK(7, 0)
+#definePMC_PLL_CTRL1_MUL_MSK GENMASK(31, 24)
+#define PMC_PLL_CTRL1_FRACR_MSKGENMASK(21, 0)
+
+#define PLL_DIV_MAX(FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
+#define UPLL_DIV 2
+#define PLL_MUL_MAX(FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
+
+#define FCORE_MIN (6)
+#define FCORE_MAX (12)
+
+#define PLL_MAX_ID 7
+
+struct sam9x60_pll {
+ void __iomem *base;
+ const struct clk_pll_characteristics *characteristics;
+ const struct clk_pll_layout *layout;
+ struct clk clk;
+ u8 id;
+};
+
+#define to_sam9x60_pll(_clk) container_of(_clk, struct sam9x60_pll, clk)
+
+static inline bool sam9x60_pll_ready(void __iomem *base, int id)
+{
+ unsigned int status;
+
+ pmc_read(base, AT91_PMC_PLL_ISR0, );
+
+ return !!(status & BIT(id));
+}
+
+static long sam9x60_frac_pll_compute_mul_frac(u32 *mul, u32 *frac, ulong rate,
+ ulong parent_rate)
+{
+ unsigned long tmprate, remainder;
+ unsigned long nmul = 0;
+ unsigned long nfrac = 0;
+
+ if (rate < FCORE_MIN || rate > FCORE_MAX)
+ return -ERANGE;
+
+ /*
+* Calculate the multiplier associated with the current
+* divider that provide the closest rate to the requested one.
+*/
+ nmul = mult_frac(rate, 1, parent_rate);
+ tmprate = mult_frac(parent_rate, nmul, 1);
+ remainder = rate - tmprate;
+
+ if (remainder) {
+ nfrac = DIV_ROUND_CLOSEST_ULL((u64)remainder * (1 << 22),
+ parent_rate);
+
+ tmprate += DIV_ROUND_CLOSEST_ULL((u64)nfrac * parent_rate,
+(1 << 22));
+ }
+
+ /* Check if resulted rate is valid. */
+ if (tmprate < FCORE_MIN || tmprate > FCORE_MAX)
+ return -ERANGE;
+
+ *mul = nmul - 1;
+ *frac = nfrac;
+
+ return tmprate;
+}
+
+static ulong sam9x60_frac_pll_set_rate(struct clk *clk, ulong rate)
+{
+ struct sam9x60_pll *pll = to_sam9x60_pll(clk);
+ void __iomem *base = pll->base;
+ ulong parent_rate = clk_get_parent_rate(clk);
+ u32 nmul, cmul, nfrac, cfrac, val;
+ bool ready = sam9x60_pll_ready(base, pll->id);
+ long ret;
+
+ if (!parent_rate)
+ return 0;
+
+ ret = sam9x60_frac_pll_compute_mul_frac(, , rate,
+ parent_rate);
+ if (ret < 0)
+ return 0;
+
+ pmc_update_bits(base, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
+ pll->id);
+ pmc_read(base, AT91_PMC_PLL_CTRL1, );
+ cmul = (val & pll->layout->mul_mask) >> pll->layout->mul_shift;
+ cfrac = (val &
[PATCH 19/22] clk: at91: clk-peripheral: add driver compatible with ccf
Add clk-peripheral compatible with common clock framework.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Makefile | 2 +
drivers/clk/at91/clk-peripheral.c | 254 ++
drivers/clk/at91/pmc.h| 16 +++
3 files changed, 272 insertions(+)
create mode 100644 drivers/clk/at91/clk-peripheral.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 1d59531e0c42..b5529065b5c4 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -4,6 +4,8 @@
ifdef CONFIG_CLK_CCF
obj-y += pmc.o sckc.o clk-main.o clk-master.o clk-programmable.o clk-system.o
+obj-y += clk-peripheral.o
+
obj-$(CONFIG_AT91_UTMI)+= clk-utmi.o
obj-$(CONFIG_AT91_SAM9X60_PLL) += clk-sam9x60-pll.o
else
diff --git a/drivers/clk/at91/clk-peripheral.c
b/drivers/clk/at91/clk-peripheral.c
new file mode 100644
index ..52cbc520cef4
--- /dev/null
+++ b/drivers/clk/at91/clk-peripheral.c
@@ -0,0 +1,254 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Peripheral clock support for AT91 architectures.
+ *
+ * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Claudiu Beznea
+ *
+ * Based on drivers/clk/at91/clk-peripheral.c from Linux.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pmc.h"
+
+#define UBOOT_DM_CLK_AT91_PERIPH "at91-periph-clk"
+#define UBOOT_DM_CLK_AT91_SAM9X5_PERIPH"at91-sam9x5-periph-clk"
+
+#define PERIPHERAL_ID_MIN 2
+#define PERIPHERAL_ID_MAX 31
+#define PERIPHERAL_MASK(id)(1 << ((id) & PERIPHERAL_ID_MAX))
+
+#define PERIPHERAL_MAX_SHIFT 3
+
+struct clk_peripheral {
+ void __iomem *base;
+ struct clk clk;
+ u32 id;
+};
+
+#define to_clk_peripheral(_c) container_of(_c, struct clk_peripheral, clk)
+
+struct clk_sam9x5_peripheral {
+ const struct clk_pcr_layout *layout;
+ void __iomem *base;
+ struct clk clk;
+ struct clk_range range;
+ u32 id;
+ u32 div;
+ bool auto_div;
+};
+
+#define to_clk_sam9x5_peripheral(_c) \
+ container_of(_c, struct clk_sam9x5_peripheral, clk)
+
+static int clk_peripheral_enable(struct clk *clk)
+{
+ struct clk_peripheral *periph = to_clk_peripheral(clk);
+ int offset = AT91_PMC_PCER;
+ u32 id = periph->id;
+
+ if (id < PERIPHERAL_ID_MIN)
+ return 0;
+ if (id > PERIPHERAL_ID_MAX)
+ offset = AT91_PMC_PCER1;
+ pmc_write(periph->base, offset, PERIPHERAL_MASK(id));
+
+ return 0;
+}
+
+static int clk_peripheral_disable(struct clk *clk)
+{
+ struct clk_peripheral *periph = to_clk_peripheral(clk);
+ int offset = AT91_PMC_PCDR;
+ u32 id = periph->id;
+
+ if (id < PERIPHERAL_ID_MIN)
+ return -EINVAL;
+
+ if (id > PERIPHERAL_ID_MAX)
+ offset = AT91_PMC_PCDR1;
+ pmc_write(periph->base, offset, PERIPHERAL_MASK(id));
+
+ return 0;
+}
+
+static const struct clk_ops peripheral_ops = {
+ .enable = clk_peripheral_enable,
+ .disable = clk_peripheral_disable,
+ .get_rate = clk_generic_get_rate,
+};
+
+struct clk *
+at91_clk_register_peripheral(void __iomem *base, const char *name,
+const char *parent_name, u32 id)
+{
+ struct clk_peripheral *periph;
+ struct clk *clk;
+ int ret;
+
+ if (!base || !name || !parent_name || id > PERIPHERAL_ID_MAX)
+ return ERR_PTR(-EINVAL);
+
+ periph = kzalloc(sizeof(*periph), GFP_KERNEL);
+ if (!periph)
+ return ERR_PTR(-ENOMEM);
+
+ periph->id = id;
+ periph->base = base;
+
+ clk = >clk;
+ clk->flags = CLK_GET_RATE_NOCACHE;
+ ret = clk_register(clk, UBOOT_DM_CLK_AT91_PERIPH, name, parent_name);
+ if (ret) {
+ kfree(periph);
+ clk = ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(at91_periph_clk) = {
+ .name = UBOOT_DM_CLK_AT91_PERIPH,
+ .id = UCLASS_CLK,
+ .ops = _ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+static int clk_sam9x5_peripheral_enable(struct clk *clk)
+{
+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(clk);
+
+ if (periph->id < PERIPHERAL_ID_MIN)
+ return 0;
+
+ pmc_write(periph->base, periph->layout->offset,
+ (periph->id & periph->layout->pid_mask));
+ pmc_update_bits(periph->base, periph->layout->offset,
+ periph->layout->cmd | AT91_PMC_PCR_EN,
+ periph->layout->cmd | AT91_PMC_PCR_EN);
+
+ return 0;
+}
+
+static int clk_sam9x5_peripheral_disable(struct clk *clk)
+{
+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(clk);
+
+ if (periph->id < PERIPHERAL_ID_MIN)
+ return -EINVAL;
+
+ pmc_write(periph->base, periph->layout->offset,
+ (periph->id &
[PATCH 20/22] clk: at91: clk-generic: add driver compatible with ccf
Add clk-generic driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-generic.c | 202 +
drivers/clk/at91/pmc.h | 6 ++
3 files changed, 209 insertions(+)
create mode 100644 drivers/clk/at91/clk-generic.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index b5529065b5c4..2cd840af3859 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -6,6 +6,7 @@ ifdef CONFIG_CLK_CCF
obj-y += pmc.o sckc.o clk-main.o clk-master.o clk-programmable.o clk-system.o
obj-y += clk-peripheral.o
+obj-$(CONFIG_AT91_GENERIC_CLK) += clk-generic.o
obj-$(CONFIG_AT91_UTMI)+= clk-utmi.o
obj-$(CONFIG_AT91_SAM9X60_PLL) += clk-sam9x60-pll.o
else
diff --git a/drivers/clk/at91/clk-generic.c b/drivers/clk/at91/clk-generic.c
new file mode 100644
index ..87738b7b5bff
--- /dev/null
+++ b/drivers/clk/at91/clk-generic.c
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Generic clock support for AT91 architectures.
+ *
+ * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Claudiu Beznea
+ *
+ * Based on drivers/clk/at91/clk-generated.c from Linux.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pmc.h"
+
+#define UBOOT_DM_CLK_AT91_GCK "at91-gck-clk"
+
+#define GENERATED_MAX_DIV 255
+
+struct clk_gck {
+ void __iomem *base;
+ const u32 *clk_mux_table;
+ const u32 *mux_table;
+ const struct clk_pcr_layout *layout;
+ struct clk_range range;
+ struct clk clk;
+ u32 num_parents;
+ u32 id;
+};
+
+#define to_clk_gck(_c) container_of(_c, struct clk_gck, clk)
+
+static int clk_gck_enable(struct clk *clk)
+{
+ struct clk_gck *gck = to_clk_gck(clk);
+
+ pmc_write(gck->base, gck->layout->offset,
+ (gck->id & gck->layout->pid_mask));
+ pmc_update_bits(gck->base, gck->layout->offset,
+ gck->layout->cmd | AT91_PMC_PCR_GCKEN,
+ gck->layout->cmd | AT91_PMC_PCR_GCKEN);
+
+ return 0;
+}
+
+static int clk_gck_disable(struct clk *clk)
+{
+ struct clk_gck *gck = to_clk_gck(clk);
+
+ pmc_write(gck->base, gck->layout->offset,
+ (gck->id & gck->layout->pid_mask));
+ pmc_update_bits(gck->base, gck->layout->offset,
+ gck->layout->cmd | AT91_PMC_PCR_GCKEN,
+ gck->layout->cmd);
+
+ return 0;
+}
+
+static int clk_gck_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk_gck *gck = to_clk_gck(clk);
+ int index;
+
+ index = at91_clk_mux_val_to_index(gck->clk_mux_table, gck->num_parents,
+ parent->id);
+ if (index < 0)
+ return index;
+
+ index = at91_clk_mux_index_to_val(gck->mux_table, gck->num_parents,
+ index);
+ if (index < 0)
+ return index;
+
+ pmc_write(gck->base, gck->layout->offset,
+ (gck->id & gck->layout->pid_mask));
+ pmc_update_bits(gck->base, gck->layout->offset,
+ gck->layout->gckcss_mask | gck->layout->cmd,
+ (index << (ffs(gck->layout->gckcss_mask) - 1)) |
+ gck->layout->cmd);
+
+ return 0;
+}
+
+static ulong clk_gck_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk_gck *gck = to_clk_gck(clk);
+ ulong parent_rate = clk_get_parent_rate(clk);
+ u32 div;
+
+ if (!rate || !parent_rate)
+ return 0;
+
+ if (gck->range.max && rate > gck->range.max)
+ return 0;
+
+ div = DIV_ROUND_CLOSEST(parent_rate, rate);
+ if (div > GENERATED_MAX_DIV + 1 || !div)
+ return 0;
+
+ pmc_write(gck->base, gck->layout->offset,
+ (gck->id & gck->layout->pid_mask));
+ pmc_update_bits(gck->base, gck->layout->offset,
+ AT91_PMC_PCR_GCKDIV_MASK | gck->layout->cmd,
+ ((div - 1) << (ffs(AT91_PMC_PCR_GCKDIV_MASK) - 1)) |
+ gck->layout->cmd);
+
+ return parent_rate / div;
+}
+
+static ulong clk_gck_get_rate(struct clk *clk)
+{
+ struct clk_gck *gck = to_clk_gck(clk);
+ ulong parent_rate = clk_get_parent_rate(clk);
+ u32 val, div;
+
+ if (!parent_rate)
+ return 0;
+
+ pmc_write(gck->base, gck->layout->offset,
+ (gck->id & gck->layout->pid_mask));
+ pmc_read(gck->base, gck->layout->offset, );
+
+ div = (val & AT91_PMC_PCR_GCKDIV_MASK) >>
+ (ffs(AT91_PMC_PCR_GCKDIV_MASK) - 1);
+
+ return parent_rate / (div + 1);
+}
+
+static const struct clk_ops gck_ops = {
+ .enable = clk_gck_enable,
+ .disable = clk_gck_disable,
+ .set_parent =
[PATCH 21/22] clk: at91: pmc: add generic clock ops
Add generic clock ops to be used by every AT91 PMC driver
built on top of CCF.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/pmc.c | 71 ++
drivers/clk/at91/pmc.h | 2 ++
2 files changed, 73 insertions(+)
diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c
index 29c6452497b7..660e23192149 100644
--- a/drivers/clk/at91/pmc.c
+++ b/drivers/clk/at91/pmc.c
@@ -5,8 +5,79 @@
*/
#include
+#include
#include
+#include "pmc.h"
+
+static int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
+{
+ if (args->args_count != 2) {
+ debug("AT91: clk: Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ clk->id = AT91_TO_CLK_ID(args->args[0], args->args[1]);
+
+ return 0;
+}
+
+static ulong at91_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ return clk_get_rate(c);
+}
+
+static ulong at91_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk *c;
+ int ret;
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ return clk_set_rate(c, rate);
+}
+
+static int at91_clk_enable(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ return clk_enable(c);
+}
+
+static int at91_clk_disable(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ ret = clk_get_by_id(clk->id, );
+ if (ret)
+ return ret;
+
+ return clk_disable(c);
+}
+
+const struct clk_ops at91_clk_ops = {
+ .of_xlate = at91_clk_of_xlate,
+ .set_rate = at91_clk_set_rate,
+ .get_rate = at91_clk_get_rate,
+ .enable = at91_clk_enable,
+ .disable= at91_clk_disable,
+};
+
/**
* pmc_read() - read content at address base + off into val
*
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 176855e7a0ed..a6a714fd220b 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -75,6 +75,8 @@ extern const struct clk_programmable_layout
at91rm9200_programmable_layout;
extern const struct clk_programmable_layout at91sam9g45_programmable_layout;
extern const struct clk_programmable_layout at91sam9x5_programmable_layout;
+extern const struct clk_ops at91_clk_ops;
+
struct clk *at91_clk_main_rc(void __iomem *reg, const char *name,
const char *parent_name);
struct clk *at91_clk_main_osc(void __iomem *reg, const char *name,
--
2.7.4
[PATCH 18/22] clk: at91: clk-system: add driver compatible with ccf
Add clk-system driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/clk-system.c | 112 ++
drivers/clk/at91/pmc.h| 3 ++
3 files changed, 116 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/at91/clk-system.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 8951052eb0f3..1d59531e0c42 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -3,7 +3,7 @@
#
ifdef CONFIG_CLK_CCF
-obj-y += pmc.o sckc.o clk-main.o clk-master.o clk-programmable.o
+obj-y += pmc.o sckc.o clk-main.o clk-master.o clk-programmable.o clk-system.o
obj-$(CONFIG_AT91_UTMI)+= clk-utmi.o
obj-$(CONFIG_AT91_SAM9X60_PLL) += clk-sam9x60-pll.o
else
diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c
new file mode 100644
index ..82f79e74a190
--- /dev/null
+++ b/drivers/clk/at91/clk-system.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * System clock support for AT91 architectures.
+ *
+ * Copyright (C) Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Claudiu Beznea
+ *
+ * Based on drivers/clk/at91/clk-system.c from Linux.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pmc.h"
+
+#define UBOOT_DM_CLK_AT91_SYSTEM "at91-system-clk"
+
+#define SYSTEM_MAX_ID 31
+
+struct clk_system {
+ void __iomem *base;
+ struct clk clk;
+ u8 id;
+};
+
+#define to_clk_system(_c) container_of(_c, struct clk_system, clk)
+
+static inline int is_pck(int id)
+{
+ return (id >= 8) && (id <= 15);
+}
+
+static inline bool clk_system_ready(void __iomem *base, int id)
+{
+ unsigned int status;
+
+ pmc_read(base, AT91_PMC_SR, );
+
+ return !!(status & (1 << id));
+}
+
+static int clk_system_enable(struct clk *clk)
+{
+ struct clk_system *sys = to_clk_system(clk);
+
+ pmc_write(sys->base, AT91_PMC_SCER, 1 << sys->id);
+
+ if (!is_pck(sys->id))
+ return 0;
+
+ while (!clk_system_ready(sys->base, sys->id)) {
+ debug("waiting for pck%u\n", sys->id);
+ cpu_relax();
+ }
+
+ return 0;
+}
+
+static int clk_system_disable(struct clk *clk)
+{
+ struct clk_system *sys = to_clk_system(clk);
+
+ pmc_write(sys->base, AT91_PMC_SCDR, 1 << sys->id);
+
+ return 0;
+}
+
+static const struct clk_ops system_ops = {
+ .enable = clk_system_enable,
+ .disable = clk_system_disable,
+ .get_rate = clk_generic_get_rate,
+};
+
+struct clk *at91_clk_register_system(void __iomem *base, const char *name,
+const char *parent_name, u8 id)
+{
+ struct clk_system *sys;
+ struct clk *clk;
+ int ret;
+
+ if (!base || !name || !parent_name || id > SYSTEM_MAX_ID)
+ return ERR_PTR(-EINVAL);
+
+ sys = kzalloc(sizeof(*sys), GFP_KERNEL);
+ if (!sys)
+ return ERR_PTR(-ENOMEM);
+
+ sys->id = id;
+ sys->base = base;
+
+ clk = >clk;
+ clk->flags = CLK_GET_RATE_NOCACHE;
+ ret = clk_register(clk, UBOOT_DM_CLK_AT91_SYSTEM, name, parent_name);
+ if (ret) {
+ kfree(sys);
+ clk = ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(at91_system_clk) = {
+ .name = UBOOT_DM_CLK_AT91_SYSTEM,
+ .id = UCLASS_CLK,
+ .ops = _ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index a443b65257b9..c372f39fc9f6 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -108,6 +108,9 @@ at91_clk_register_programmable(void __iomem *base, const
char *name,
const char * const *parent_names, u8 num_parents, u8 id,
const struct clk_programmable_layout *layout,
const u32 *clk_mux_table, const u32 *mux_table);
+struct clk *
+at91_clk_register_system(void __iomem *base, const char *name,
+ const char *parent_name, u8 id);
int at91_clk_mux_val_to_index(const u32 *table, u32 num_parents, u32 val);
int at91_clk_mux_index_to_val(const u32 *table, u32 num_parents, u32 index);
--
2.7.4
[PATCH 14/22] clk: at91: clk-master: add support for sama7g5
Add master clock (MCK1..MCK4) support for SAMA7G5. SAMA7G5's PMC has
multiple master clocks feeding different subsystems.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/clk-master.c | 178 +-
drivers/clk/at91/pmc.h| 5 ++
2 files changed, 182 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
index 1d388b6b2519..759df93697d2 100644
--- a/drivers/clk/at91/clk-master.c
+++ b/drivers/clk/at91/clk-master.c
@@ -19,12 +19,25 @@
#include "pmc.h"
#define UBOOT_DM_CLK_AT91_MASTER "at91-master-clk"
+#define UBOOT_DM_CLK_AT91_SAMA7G5_MASTER "at91-sama7g5-master-clk"
#define MASTER_PRES_MASK 0x7
#define MASTER_PRES_MAXMASTER_PRES_MASK
#define MASTER_DIV_SHIFT 8
#define MASTER_DIV_MASK0x3
+#define PMC_MCR0x30
+#define PMC_MCR_ID_MSK GENMASK(3, 0)
+#define PMC_MCR_CMDBIT(7)
+#define PMC_MCR_DIVGENMASK(10, 8)
+#define PMC_MCR_CSSGENMASK(20, 16)
+#define PMC_MCR_CSS_SHIFT (16)
+#define PMC_MCR_EN BIT(28)
+
+#define PMC_MCR_ID(x) ((x) & PMC_MCR_ID_MSK)
+
+#define MASTER_MAX_ID 4
+
struct clk_master {
void __iomem *base;
const struct clk_master_layout *layout;
@@ -40,11 +53,12 @@ struct clk_master {
static inline bool clk_master_ready(struct clk_master *master)
{
+ unsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY;
unsigned int status;
pmc_read(master->base, AT91_PMC_SR, );
- return !!(status & AT91_PMC_MCKRDY);
+ return !!(status & bit);
}
static int clk_master_enable(struct clk *clk)
@@ -143,6 +157,168 @@ U_BOOT_DRIVER(at91_master_clk) = {
.flags = DM_FLAG_PRE_RELOC,
};
+static int clk_sama7g5_master_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk_master *master = to_clk_master(clk);
+ int index;
+
+ index = at91_clk_mux_val_to_index(master->clk_mux_table,
+ master->num_parents, parent->id);
+ if (index < 0)
+ return index;
+
+ index = at91_clk_mux_index_to_val(master->mux_table,
+ master->num_parents, index);
+ if (index < 0)
+ return index;
+
+ pmc_write(master->base, PMC_MCR, PMC_MCR_ID(master->id));
+ pmc_update_bits(master->base, PMC_MCR,
+ PMC_MCR_CSS | PMC_MCR_CMD | PMC_MCR_ID_MSK,
+ (index << PMC_MCR_CSS_SHIFT) | PMC_MCR_CMD |
+ PMC_MCR_ID(master->id));
+ return 0;
+}
+
+static int clk_sama7g5_master_enable(struct clk *clk)
+{
+ struct clk_master *master = to_clk_master(clk);
+
+ pmc_write(master->base, PMC_MCR, PMC_MCR_ID(master->id));
+ pmc_update_bits(master->base, PMC_MCR,
+ PMC_MCR_EN | PMC_MCR_CMD | PMC_MCR_ID_MSK,
+ PMC_MCR_EN | PMC_MCR_CMD | PMC_MCR_ID(master->id));
+
+ return 0;
+}
+
+static int clk_sama7g5_master_disable(struct clk *clk)
+{
+ struct clk_master *master = to_clk_master(clk);
+
+ pmc_write(master->base, PMC_MCR, master->id);
+ pmc_update_bits(master->base, PMC_MCR,
+ PMC_MCR_EN | PMC_MCR_CMD | PMC_MCR_ID_MSK,
+ PMC_MCR_CMD | PMC_MCR_ID(master->id));
+
+ return 0;
+}
+
+static ulong clk_sama7g5_master_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk_master *master = to_clk_master(clk);
+ ulong parent_rate = clk_get_parent_rate(clk);
+ ulong div, rrate;
+
+ if (!parent_rate)
+ return 0;
+
+ div = DIV_ROUND_CLOSEST(parent_rate, rate);
+ if ((div > (1 << (MASTER_PRES_MAX - 1))) || (div & (div - 1))) {
+ return 0;
+ } else if (div == 3) {
+ rrate = DIV_ROUND_CLOSEST(parent_rate, MASTER_PRES_MAX);
+ div = MASTER_PRES_MAX;
+ } else {
+ rrate = DIV_ROUND_CLOSEST(parent_rate, div);
+ div = ffs(div) - 1;
+ }
+
+ pmc_write(master->base, PMC_MCR, master->id);
+ pmc_update_bits(master->base, PMC_MCR,
+ PMC_MCR_DIV | PMC_MCR_CMD | PMC_MCR_ID_MSK,
+ (div << MASTER_DIV_SHIFT) | PMC_MCR_CMD |
+ PMC_MCR_ID(master->id));
+
+ return rrate;
+}
+
+static ulong clk_sama7g5_master_get_rate(struct clk *clk)
+{
+ struct clk_master *master = to_clk_master(clk);
+ ulong parent_rate = clk_get_parent_rate(clk);
+ unsigned int val;
+ ulong div;
+
+ if (!parent_rate)
+ return 0;
+
+ pmc_write(master->base, PMC_MCR, master->id);
+ pmc_read(master->base, PMC_MCR, );
+
+ div = (val >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
+
+ if (div == MASTER_PRES_MAX)
+ div = 3;
+
[PATCH 17/22] clk: at91: clk-programmable: add driver compatible with ccf
Add clk-programmable driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/clk-programmable.c | 208
drivers/clk/at91/pmc.h | 17 +++
3 files changed, 226 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/at91/clk-programmable.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 9c38bda5e6b7..8951052eb0f3 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -3,7 +3,7 @@
#
ifdef CONFIG_CLK_CCF
-obj-y += pmc.o sckc.o clk-main.o clk-master.o
+obj-y += pmc.o sckc.o clk-main.o clk-master.o clk-programmable.o
obj-$(CONFIG_AT91_UTMI)+= clk-utmi.o
obj-$(CONFIG_AT91_SAM9X60_PLL) += clk-sam9x60-pll.o
else
diff --git a/drivers/clk/at91/clk-programmable.c
b/drivers/clk/at91/clk-programmable.c
new file mode 100644
index ..868de4b1774b
--- /dev/null
+++ b/drivers/clk/at91/clk-programmable.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Programmable clock support for AT91 architectures.
+ *
+ * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Claudiu Beznea
+ *
+ * Based on drivers/clk/at91/clk-programmable.c from Linux.
+ */
+#include
+#include
+#include
+#include
+#include
+
+#include "pmc.h"
+
+#define UBOOT_DM_CLK_AT91_PROG "at91-prog-clk"
+
+#define PROG_ID_MAX7
+
+#define PROG_STATUS_MASK(id) (1 << ((id) + 8))
+#define PROG_PRES(_l, _p) (((_p) >> (_l)->pres_shift) & (_l)->pres_mask)
+#define PROG_MAX_RM9200_CSS3
+
+struct clk_programmable {
+ void __iomem *base;
+ const u32 *clk_mux_table;
+ const u32 *mux_table;
+ const struct clk_programmable_layout *layout;
+ u32 num_parents;
+ struct clk clk;
+ u8 id;
+};
+
+#define to_clk_programmable(_c) container_of(_c, struct clk_programmable, clk)
+
+static ulong clk_programmable_get_rate(struct clk *clk)
+{
+ struct clk_programmable *prog = to_clk_programmable(clk);
+ const struct clk_programmable_layout *layout = prog->layout;
+ ulong rate, parent_rate = clk_get_parent_rate(clk);
+ unsigned int pckr;
+
+ pmc_read(prog->base, AT91_PMC_PCKR(prog->id), );
+
+ if (layout->is_pres_direct)
+ rate = parent_rate / (PROG_PRES(layout, pckr) + 1);
+ else
+ rate = parent_rate >> PROG_PRES(layout, pckr);
+
+ return rate;
+}
+
+static int clk_programmable_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk_programmable *prog = to_clk_programmable(clk);
+ const struct clk_programmable_layout *layout = prog->layout;
+ unsigned int mask = layout->css_mask;
+ int index;
+
+ index = at91_clk_mux_val_to_index(prog->clk_mux_table,
+ prog->num_parents, parent->id);
+ if (index < 0)
+ return index;
+
+ index = at91_clk_mux_index_to_val(prog->mux_table, prog->num_parents,
+ index);
+ if (index < 0)
+ return index;
+
+ if (layout->have_slck_mck)
+ mask |= AT91_PMC_CSSMCK_MCK;
+
+ if (index > layout->css_mask) {
+ if (index > PROG_MAX_RM9200_CSS && !layout->have_slck_mck)
+ return -EINVAL;
+
+ index |= AT91_PMC_CSSMCK_MCK;
+ }
+
+ pmc_update_bits(prog->base, AT91_PMC_PCKR(prog->id), mask, index);
+
+ return 0;
+}
+
+static ulong clk_programmable_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk_programmable *prog = to_clk_programmable(clk);
+ const struct clk_programmable_layout *layout = prog->layout;
+ ulong parent_rate = clk_get_parent_rate(clk);
+ ulong div = parent_rate / rate;
+ int shift = 0;
+
+ if (!parent_rate || !div)
+ return -EINVAL;
+
+ if (layout->is_pres_direct) {
+ shift = div - 1;
+
+ if (shift > layout->pres_mask)
+ return -EINVAL;
+ } else {
+ shift = fls(div) - 1;
+
+ if (div != (1 << shift))
+ return -EINVAL;
+
+ if (shift >= layout->pres_mask)
+ return -EINVAL;
+ }
+
+ pmc_update_bits(prog->base, AT91_PMC_PCKR(prog->id),
+ layout->pres_mask << layout->pres_shift,
+ shift << layout->pres_shift);
+
+ if (layout->is_pres_direct)
+ return (parent_rate / shift + 1);
+
+ return parent_rate >> shift;
+}
+
+static const struct clk_ops programmable_ops = {
+ .get_rate = clk_programmable_get_rate,
+ .set_parent = clk_programmable_set_parent,
+ .set_rate = clk_programmable_set_rate,
+};
+
+struct clk *at91_clk_register_programmable(void __iomem *base, const char
*name,
+
[PATCH 16/22] clk: at91: clk-utmi: add support for sama7g5
Add UTMI support for SAMA7G5. SAMA7G5's UTMI control is done via
XTALF register. Values written at bits 2..0 in this register
correspond to the on board crystal oscillator frequency.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/clk-utmi.c | 71 -
drivers/clk/at91/pmc.h | 3 ++
2 files changed, 73 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c
index b60fd35b6b6a..7c8bcfb51dba 100644
--- a/drivers/clk/at91/clk-utmi.c
+++ b/drivers/clk/at91/clk-utmi.c
@@ -20,7 +20,8 @@
#include "pmc.h"
-#define UBOOT_DM_CLK_AT91_UTMI "at91-utmi-clk"
+#define UBOOT_DM_CLK_AT91_UTMI "at91-utmi-clk"
+#define UBOOT_DM_CLK_AT91_SAMA7G5_UTMI "at91-sama7g5-utmi-clk"
/*
* The purpose of this clock is to generate a 480 MHz signal. A different
@@ -163,3 +164,71 @@ U_BOOT_DRIVER(at91_utmi_clk) = {
.ops = _ops,
.flags = DM_FLAG_PRE_RELOC,
};
+
+static int clk_utmi_sama7g5_enable(struct clk *clk)
+{
+ struct clk_utmi *utmi = to_clk_utmi(clk);
+ ulong parent_rate = clk_get_parent_rate(clk);
+ unsigned int val;
+
+ switch (parent_rate) {
+ case 1600:
+ val = 0;
+ break;
+ case 2000:
+ val = 2;
+ break;
+ case 2400:
+ val = 3;
+ break;
+ case 3200:
+ val = 5;
+ break;
+ default:
+ debug("UTMICK: unsupported main_xtal rate\n");
+ return -EINVAL;
+ }
+
+ pmc_write(utmi->base, AT91_PMC_XTALF, val);
+
+ return 0;
+}
+
+static const struct clk_ops sama7g5_utmi_ops = {
+ .enable = clk_utmi_sama7g5_enable,
+ .get_rate = clk_utmi_get_rate,
+};
+
+struct clk *at91_clk_sama7g5_register_utmi(void __iomem *base,
+ const char *name, const char *parent_name)
+{
+ struct clk_utmi *utmi;
+ struct clk *clk;
+ int ret;
+
+ if (!base || !name || !parent_name)
+ return ERR_PTR(-EINVAL);
+
+ utmi = kzalloc(sizeof(*utmi), GFP_KERNEL);
+ if (!utmi)
+ return ERR_PTR(-ENOMEM);
+
+ utmi->base = base;
+
+ clk = >clk;
+ ret = clk_register(clk, UBOOT_DM_CLK_AT91_SAMA7G5_UTMI, name,
+ parent_name);
+ if (ret) {
+ kfree(utmi);
+ clk = ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(at91_sama7g5_utmi_clk) = {
+ .name = UBOOT_DM_CLK_AT91_SAMA7G5_UTMI,
+ .id = UCLASS_CLK,
+ .ops = _utmi_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 264b36c7b4f5..d34005f6986c 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -88,6 +88,9 @@ at91_clk_sama7g5_register_master(void __iomem *base, const
char *name,
struct clk *
at91_clk_register_utmi(void __iomem *base, struct udevice *dev,
const char *name, const char *parent_name);
+struct clk *
+at91_clk_sama7g5_register_utmi(void __iomem *base, const char *name,
+ const char *parent_name);
int at91_clk_mux_val_to_index(const u32 *table, u32 num_parents, u32 val);
int at91_clk_mux_index_to_val(const u32 *table, u32 num_parents, u32 index);
--
2.7.4
[PATCH 10/22] clk: at91: sckc: add driver compatible with ccf
Add sckc driver compatible with common clock framework. Driver
implements slow clock support for SAM9X60 compatible IPs (in this
list it is also present SAMA7G5's slow clock IP).
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/sckc.c | 172 ++
2 files changed, 173 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/at91/sckc.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index e2413af40360..7083ce2890d6 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -3,7 +3,7 @@
#
ifdef CONFIG_CLK_CCF
-obj-y += pmc.o
+obj-y += pmc.o sckc.o
else
obj-y += compat.o
endif
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
new file mode 100644
index ..dd62dc5510e4
--- /dev/null
+++ b/drivers/clk/at91/sckc.c
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Slow clock support for AT91 architectures.
+ *
+ * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Claudiu Beznea
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "pmc.h"
+
+#define UBOOT_DM_CLK_AT91_SAM9X60_TD_SLCK "at91-sam9x60-td-slck"
+#define UBOOT_DM_CLK_AT91_SCKC "at91-sckc"
+
+#define AT91_OSC_SEL BIT(24)
+#define AT91_OSC_SEL_SHIFT (24)
+
+struct sam9x60_sckc {
+ void __iomem *reg;
+ const char **parent_names;
+ unsigned int num_parents;
+ struct clk clk;
+};
+
+#define to_sam9x60_sckc(c) container_of(c, struct sam9x60_sckc, clk)
+
+static int sam9x60_sckc_of_xlate(struct clk *clk,
+struct ofnode_phandle_args *args)
+{
+ if (args->args_count != 1) {
+ debug("AT91: SCKC: Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ clk->id = AT91_TO_CLK_ID(PMC_TYPE_SLOW, args->args[0]);
+
+ return 0;
+}
+
+static const struct clk_ops sam9x60_sckc_ops = {
+ .of_xlate = sam9x60_sckc_of_xlate,
+ .get_rate = clk_generic_get_rate,
+};
+
+static int sam9x60_td_slck_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct sam9x60_sckc *sckc = to_sam9x60_sckc(clk);
+ u32 i;
+
+ for (i = 0; i < sckc->num_parents; i++) {
+ if (!strcmp(parent->dev->name, sckc->parent_names[i]))
+ break;
+ }
+ if (i == sckc->num_parents)
+ return -EINVAL;
+
+ pmc_update_bits(sckc->reg, 0, AT91_OSC_SEL, (i << AT91_OSC_SEL_SHIFT));
+
+ return 0;
+}
+
+static const struct clk_ops sam9x60_td_slck_ops = {
+ .get_rate = clk_generic_get_rate,
+ .set_parent = sam9x60_td_slck_set_parent,
+};
+
+static struct clk *at91_sam9x60_clk_register_td_slck(struct sam9x60_sckc *sckc,
+ const char *name, const char * const *parent_names,
+ int num_parents)
+{
+ struct clk *clk;
+ int ret = -ENOMEM;
+ u32 val, i;
+
+ if (!sckc || !name || !parent_names || num_parents != 2)
+ return ERR_PTR(-EINVAL);
+
+ sckc->parent_names = kzalloc(sizeof(*sckc->parent_names) * num_parents,
+GFP_KERNEL);
+ if (!sckc->parent_names)
+ return ERR_PTR(ret);
+
+ for (i = 0; i < num_parents; i++) {
+ sckc->parent_names[i] = kmemdup(parent_names[i],
+ strlen(parent_names[i]) + 1, GFP_KERNEL);
+ if (!sckc->parent_names[i])
+ goto free;
+ }
+ sckc->num_parents = num_parents;
+
+ pmc_read(sckc->reg, 0, );
+ val = (val & AT91_OSC_SEL) >> AT91_OSC_SEL_SHIFT;
+
+ clk = >clk;
+ ret = clk_register(clk, UBOOT_DM_CLK_AT91_SAM9X60_TD_SLCK, name,
+ parent_names[val]);
+ if (ret)
+ goto free;
+
+ return clk;
+
+free:
+ for (; i >= 0; i--)
+ kfree(sckc->parent_names[i]);
+ kfree(sckc->parent_names);
+
+ return ERR_PTR(ret);
+}
+
+U_BOOT_DRIVER(at91_sam9x60_td_slck) = {
+ .name = UBOOT_DM_CLK_AT91_SAM9X60_TD_SLCK,
+ .id = UCLASS_CLK,
+ .ops = _td_slck_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+static int at91_sam9x60_sckc_probe(struct udevice *dev)
+{
+ struct sam9x60_sckc *sckc = dev_get_priv(dev);
+ void __iomem *base = (void *)devfdt_get_addr(dev);
+ const char *slow_rc_osc, *slow_osc;
+ const char *parents[2];
+ struct clk *clk, c;
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, );
+ if (ret)
+ return ret;
+ slow_rc_osc = clk_hw_get_name();
+
+ ret = clk_get_by_index(dev, 1, );
+ if (ret)
+ return ret;
+ slow_osc = clk_hw_get_name();
+
+ clk = clk_register_fixed_factor(NULL, "md_slck", slow_rc_osc, 0, 1, 1);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
[PATCH 08/22] clk: at91: pmc: add helpers for clock drivers
Add helper for clock drivers. These will be used by following
commits in the process of switching AT91 clock drivers to CCF.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/pmc.c | 91 ++
drivers/clk/at91/pmc.h | 13
2 files changed, 104 insertions(+)
diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c
index 9d9d77d861d7..0984dc321578 100644
--- a/drivers/clk/at91/pmc.c
+++ b/drivers/clk/at91/pmc.c
@@ -118,3 +118,94 @@ int at91_clk_probe(struct udevice *dev)
return 0;
}
+
+/**
+ * pmc_read() - read content at address base + off into val
+ *
+ * @base: base address
+ * @off: offset to read from
+ * @val: where the content of base + off is stored
+ *
+ * @return: void
+ */
+void pmc_read(void __iomem *base, unsigned int off, unsigned int *val)
+{
+ *val = readl(base + off);
+}
+
+/**
+ * pmc_write() - write content of val at address base + off
+ *
+ * @base: base address
+ * @off: offset to write to
+ * @val: content to be written at base + off
+ *
+ * @return: void
+ */
+void pmc_write(void __iomem *base, unsigned int off, unsigned int val)
+{
+ writel(val, base + off);
+}
+
+/**
+ * pmc_update_bits() - update a set of bits at address base + off
+ *
+ * @base: base address
+ * @off: offset to be updated
+ * @mask: mask of bits to be updated
+ * @bits: the new value to be updated
+ *
+ * @return: void
+ */
+void pmc_update_bits(void __iomem *base, unsigned int off,
+unsigned int mask, unsigned int bits)
+{
+ unsigned int tmp;
+
+ tmp = readl(base + off);
+ tmp &= ~mask;
+ writel(tmp | (bits & mask), base + off);
+}
+
+/**
+ * at91_clk_mux_val_to_index() - get parent index in mux table
+ *
+ * @table: clock mux table
+ * @num_parents: clock number of parents
+ * @val: clock id who's mux index should be retrieved
+ *
+ * @return: clock index in mux table or a negative error number in case of
+ * failure
+ */
+int at91_clk_mux_val_to_index(const u32 *table, u32 num_parents, u32 val)
+{
+ int i;
+
+ if (!table || !num_parents)
+ return -EINVAL;
+
+ for (i = 0; i < num_parents; i++) {
+ if (table[i] == val)
+ return i;
+ }
+
+ return -EINVAL;
+}
+
+/**
+ * at91_clk_mux_index_to_val() - get parent ID corresponding to an entry in
+ * clock's mux table
+ *
+ * @table: clock's mux table
+ * @num_parents: clock's number of parents
+ * @index: index in mux table which clock's ID should be retrieved
+ *
+ * @return: clock ID or a negative error number in case of failure
+ */
+int at91_clk_mux_index_to_val(const u32 *table, u32 num_parents, u32 index)
+{
+ if (!table || !num_parents || index < 0 || index > num_parents)
+ return -EINVAL;
+
+ return table[index];
+}
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 517ba1d6b452..b1ab0a95c855 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -8,6 +8,12 @@
#define __AT91_PMC_H__
#include
+#include
+#include
+
+/* Keep a range of 256 available clocks for every clock type. */
+#define AT91_TO_CLK_ID(_t, _i) (((_t) << 8) | ((_i) & 0xff))
+#define AT91_CLK_ID_TO_DID(_i) ((_i) & 0xff)
struct pmc_platdata {
struct at91_pmc *reg_base;
@@ -20,4 +26,11 @@ int at91_clk_sub_device_bind(struct udevice *dev, const char
*drv_name);
int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args);
int at91_clk_probe(struct udevice *dev);
+int at91_clk_mux_val_to_index(const u32 *table, u32 num_parents, u32 val);
+int at91_clk_mux_index_to_val(const u32 *table, u32 num_parents, u32 index);
+
+void pmc_read(void __iomem *base, unsigned int off, unsigned int *val);
+void pmc_write(void __iomem *base, unsigned int off, unsigned int val);
+void pmc_update_bits(void __iomem *base, unsigned int off, unsigned int mask,
+ unsigned int bits);
#endif
--
2.7.4
[PATCH 06/22] clk: get clock pointer before proceeding
clk_get_by_indexed_prop() retrieves a clock with dev member being set
with the pointer to the udevice for the clock controller driver. But
in case of CCF each struct clk object has set in dev member the reference
to its parent (the root of the clock tree is a fixed clock, every
node in clock tree is a clock registered with clk_register()). In this
case the subsequent operations like dev_get_clk_ptr() on clocks
retrieved by clk_get_by_indexed_prop() will fail. For this, get the
pointer to the proper clock registered (with clk_register()) using
clk_get_by_id() before proceeding.
Fixes: 1d7993d1d0ef ("clk: Port Linux common clock framework [CCF] for imx6q to
U-boot (tag: v5.1.12)")
Signed-off-by: Claudiu Beznea
---
drivers/clk/clk-uclass.c | 41 +
1 file changed, 37 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 958a9490bee2..8f926aad12cf 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -186,7 +186,7 @@ bulk_get_err:
static int clk_set_default_parents(struct udevice *dev, int stage)
{
- struct clk clk, parent_clk;
+ struct clk clk, parent_clk, *c, *p;
int index;
int num_parents;
int ret;
@@ -212,6 +212,17 @@ static int clk_set_default_parents(struct udevice *dev,
int stage)
return ret;
}
+ if (CONFIG_IS_ENABLED(CLK_CCF)) {
+ ret = clk_get_by_id(parent_clk.id, );
+ if (ret) {
+ debug("%s(): could not get parent clock
pointer, id %lu, for %s\n",
+ __func__, parent_clk.id,
dev_read_name(dev));
+ return ret;
+ }
+ } else {
+ p = _clk;
+ }
+
ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
index, );
if (ret) {
@@ -231,7 +242,18 @@ static int clk_set_default_parents(struct udevice *dev,
int stage)
/* do not setup twice the parent clocks */
continue;
- ret = clk_set_parent(, _clk);
+ if (CONFIG_IS_ENABLED(CLK_CCF)) {
+ ret = clk_get_by_id(clk.id, );
+ if (ret) {
+ debug("%s(): could not get clock pointer, id
%lu, for %s\n",
+ __func__, clk.id, dev_read_name(dev));
+ return ret;
+ }
+ } else {
+ c =
+ }
+
+ ret = clk_set_parent(c, p);
/*
* Not all drivers may support clock-reparenting (as of now).
* Ignore errors due to this.
@@ -251,7 +273,7 @@ static int clk_set_default_parents(struct udevice *dev, int
stage)
static int clk_set_default_rates(struct udevice *dev, int stage)
{
- struct clk clk;
+ struct clk clk, *c;
int index;
int num_rates;
int size;
@@ -295,7 +317,18 @@ static int clk_set_default_rates(struct udevice *dev, int
stage)
/* do not setup twice the parent clocks */
continue;
- ret = clk_set_rate(, rates[index]);
+ if (CONFIG_IS_ENABLED(CLK_CCF)) {
+ ret = clk_get_by_id(clk.id, );
+ if (ret) {
+ debug("%s(): could not get clock pointer, id
%lu, for %s\n",
+ __func__, clk.id, dev_read_name(dev));
+ return ret;
+ }
+ } else {
+ c =
+ }
+
+ ret = clk_set_rate(c, rates[index]);
if (ret < 0) {
debug("%s: failed to set rate on clock index %d (%ld)
for %s\n",
--
2.7.4
[PATCH 07/22] clk: at91: add pre-requisite headers for AT91 clock architecture
Add pre-requisite headers for AT91 clock architecture. These are based on already present files on Linux and will be used by following commits for AT91 CCF clock drivers. Signed-off-by: Claudiu Beznea --- include/dt-bindings/clk/at91.h | 22 include/linux/clk/at91_pmc.h | 247 + 2 files changed, 269 insertions(+) create mode 100644 include/dt-bindings/clk/at91.h create mode 100644 include/linux/clk/at91_pmc.h diff --git a/include/dt-bindings/clk/at91.h b/include/dt-bindings/clk/at91.h new file mode 100644 index ..e30756b2804a --- /dev/null +++ b/include/dt-bindings/clk/at91.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * This header provides constants for AT91 pmc status. + * The constants defined in this header are being used in dts and PMC code. + * + * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries + * + * Author: Claudiu Beznea + * + * Based on include/dt-bindings/clock/at91.h on Linux. + */ + +#ifndef _DT_BINDINGS_CLK_AT91_H +#define _DT_BINDINGS_CLK_AT91_H + +#define PMC_TYPE_CORE 1 +#define PMC_TYPE_SYSTEM2 +#define PMC_TYPE_PERIPHERAL3 +#define PMC_TYPE_GCK 4 +#define PMC_TYPE_SLOW 5 + +#endif diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h new file mode 100644 index ..ee39e72e2b39 --- /dev/null +++ b/include/linux/clk/at91_pmc.h @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Power Management Controller (PMC) - System peripherals registers. + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Based on AT91RM9200 datasheet revision E. + * Based on include/linux/clk/at91_pmc.h on Linux. + */ + +#ifndef AT91_PMC_H_ +#define AT91_PMC_H_ + +#define AT91_PMC_V1(1) /* PMC version 1 */ +#define AT91_PMC_V2(2) /* PMC version 2 [SAM9X60] */ + +#defineAT91_PMC_SCER 0x00/* System Clock Enable Register */ +#defineAT91_PMC_SCDR 0x04/* System Clock Disable Register */ + +#defineAT91_PMC_SCSR 0x08/* System Clock Status Register */ +#defineAT91_PMC_PCK(1 << 0) /* Processor Clock */ +#defineAT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ +#defineAT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ +#defineAT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ +#defineAT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ +#defineAT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ +#defineAT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ +#defineAT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ +#defineAT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ +#defineAT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ +#defineAT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */ +#defineAT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ +#defineAT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ + +#define AT91_PMC_PLL_CTRL0 0x0C/* PLL Control Register 0 [for SAM9X60] */ +#defineAT91_PMC_PLL_CTRL0_ENPLL(1 << 28) /* Enable PLL */ +#defineAT91_PMC_PLL_CTRL0_ENPLLCK (1 << 29) /* Enable PLL clock for PMC */ +#defineAT91_PMC_PLL_CTRL0_ENLOCK (1 << 31) /* Enable PLL lock */ + +#define AT91_PMC_PLL_CTRL1 0x10/* PLL Control Register 1 [for SAM9X60] */ + +#defineAT91_PMC_PCER 0x10/* Peripheral Clock Enable Register */ +#defineAT91_PMC_PCDR 0x14/* Peripheral Clock Disable Register */ +#defineAT91_PMC_PCSR 0x18/* Peripheral Clock Status Register */ + +#define AT91_PMC_PLL_ACR 0x18/* PLL Analog Control Register [for SAM9X60] */ +#defineAT91_PMC_PLL_ACR_DEFAULT_UPLL 0x12020010UL/* Default PLL ACR value for UPLL */ +#defineAT91_PMC_PLL_ACR_DEFAULT_PLLA 0x00020010UL/* Default PLL ACR value for PLLA */ +#defineAT91_PMC_PLL_ACR_UTMIVR (1 << 12) /* UPLL Voltage
[PATCH 13/22] clk: at91: clk-master: add driver compatible with ccf
Add clk-master driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/clk-master.c | 156 ++
drivers/clk/at91/pmc.h| 21 ++
3 files changed, 178 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/at91/clk-master.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 338582b88aee..a4e397066e1e 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -3,7 +3,7 @@
#
ifdef CONFIG_CLK_CCF
-obj-y += pmc.o sckc.o clk-main.o
+obj-y += pmc.o sckc.o clk-main.o clk-master.o
obj-$(CONFIG_AT91_SAM9X60_PLL) += clk-sam9x60-pll.o
else
obj-y += compat.o
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
new file mode 100644
index ..1d388b6b2519
--- /dev/null
+++ b/drivers/clk/at91/clk-master.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Master clock support for AT91 architectures.
+ *
+ * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Claudiu Beznea
+ *
+ * Based on drivers/clk/at91/clk-master.c from Linux.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pmc.h"
+
+#define UBOOT_DM_CLK_AT91_MASTER "at91-master-clk"
+
+#define MASTER_PRES_MASK 0x7
+#define MASTER_PRES_MAXMASTER_PRES_MASK
+#define MASTER_DIV_SHIFT 8
+#define MASTER_DIV_MASK0x3
+
+struct clk_master {
+ void __iomem *base;
+ const struct clk_master_layout *layout;
+ const struct clk_master_characteristics *characteristics;
+ const u32 *mux_table;
+ const u32 *clk_mux_table;
+ u32 num_parents;
+ struct clk clk;
+ u8 id;
+};
+
+#define to_clk_master(_clk) container_of(_clk, struct clk_master, clk)
+
+static inline bool clk_master_ready(struct clk_master *master)
+{
+ unsigned int status;
+
+ pmc_read(master->base, AT91_PMC_SR, );
+
+ return !!(status & AT91_PMC_MCKRDY);
+}
+
+static int clk_master_enable(struct clk *clk)
+{
+ struct clk_master *master = to_clk_master(clk);
+
+ while (!clk_master_ready(master)) {
+ debug("waiting for mck %d\n", master->id);
+ cpu_relax();
+ }
+
+ return 0;
+}
+
+static ulong clk_master_get_rate(struct clk *clk)
+{
+ struct clk_master *master = to_clk_master(clk);
+ const struct clk_master_layout *layout = master->layout;
+ const struct clk_master_characteristics *characteristics =
+ master->characteristics;
+ ulong rate = clk_get_parent_rate(clk);
+ unsigned int mckr;
+ u8 pres, div;
+
+ if (!rate)
+ return 0;
+
+ pmc_read(master->base, master->layout->offset, );
+ mckr &= layout->mask;
+
+ pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK;
+ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
+
+ if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX)
+ rate /= 3;
+ else
+ rate >>= pres;
+
+ rate /= characteristics->divisors[div];
+
+ if (rate < characteristics->output.min)
+ pr_warn("master clk is underclocked");
+ else if (rate > characteristics->output.max)
+ pr_warn("master clk is overclocked");
+
+ return rate;
+}
+
+static const struct clk_ops master_ops = {
+ .enable = clk_master_enable,
+ .get_rate = clk_master_get_rate,
+};
+
+struct clk *at91_clk_register_master(void __iomem *base,
+ const char *name, const char * const *parent_names,
+ int num_parents, const struct clk_master_layout *layout,
+ const struct clk_master_characteristics *characteristics,
+ const u32 *mux_table)
+{
+ struct clk_master *master;
+ struct clk *clk;
+ unsigned int val;
+ int ret;
+
+ if (!base || !name || !num_parents || !parent_names ||
+ !layout || !characteristics || !mux_table)
+ return ERR_PTR(-EINVAL);
+
+ master = kzalloc(sizeof(*master), GFP_KERNEL);
+ if (!master)
+ return ERR_PTR(-ENOMEM);
+
+ master->layout = layout;
+ master->characteristics = characteristics;
+ master->base = base;
+ master->num_parents = num_parents;
+ master->mux_table = mux_table;
+
+ pmc_read(master->base, master->layout->offset, );
+ clk = >clk;
+ clk->flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL;
+ ret = clk_register(clk, UBOOT_DM_CLK_AT91_MASTER, name,
+ parent_names[val & AT91_PMC_CSS]);
+ if (ret) {
+ kfree(master);
+ clk = ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(at91_master_clk) = {
+ .name = UBOOT_DM_CLK_AT91_MASTER,
+ .id = UCLASS_CLK,
+
[PATCH 11/22] clk: at91: clk-main: add driver compatible with ccf
Add clk-main driver compatible with common clock framework.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/clk-main.c | 387
drivers/clk/at91/pmc.h | 10 ++
3 files changed, 398 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/at91/clk-main.c
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 7083ce2890d6..805f67677a9b 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -3,7 +3,7 @@
#
ifdef CONFIG_CLK_CCF
-obj-y += pmc.o sckc.o
+obj-y += pmc.o sckc.o clk-main.o
else
obj-y += compat.o
endif
diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
new file mode 100644
index ..b52d926f3390
--- /dev/null
+++ b/drivers/clk/at91/clk-main.c
@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Main clock support for AT91 architectures.
+ *
+ * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Claudiu Beznea
+ *
+ * Based on drivers/clk/at91/clk-main.c from Linux.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "pmc.h"
+
+#define UBOOT_DM_CLK_AT91_MAIN_RC "at91-main-rc-clk"
+#define UBOOT_DM_CLK_AT91_MAIN_OSC "at91-main-osc-clk"
+#define UBOOT_DM_CLK_AT91_RM9200_MAIN "at91-rm9200-main-clk"
+#define UBOOT_DM_CLK_AT91_SAM9X5_MAIN "at91-sam9x5-main-clk"
+
+#define MOR_KEY_MASK GENMASK(23, 16)
+#define USEC_PER_SEC 100UL
+#define SLOW_CLOCK_FREQ32768
+
+#define clk_main_parent_select(s) (((s) & \
+ (AT91_PMC_MOSCEN | \
+ AT91_PMC_OSCBYPASS)) ? 1 : 0)
+
+struct clk_main_rc {
+ void __iomem*reg;
+ struct clk clk;
+};
+
+#define to_clk_main_rc(_clk) container_of(_clk, struct clk_main_rc, clk)
+
+struct clk_main_osc {
+ void __iomem*reg;
+ struct clk clk;
+};
+
+#define to_clk_main_osc(_clk) container_of(_clk, struct clk_main_osc, clk)
+
+struct clk_main {
+ void __iomem*reg;
+ const unsigned int *clk_mux_table;
+ const char * const *parent_names;
+ unsigned intnum_parents;
+ int type;
+ struct clk clk;
+};
+
+#define to_clk_main(_clk) container_of(_clk, struct clk_main, clk)
+
+static int main_rc_enable(struct clk *clk)
+{
+ struct clk_main_rc *main_rc = to_clk_main_rc(clk);
+ void __iomem *reg = main_rc->reg;
+ unsigned int val;
+
+ pmc_read(reg, AT91_CKGR_MOR, );
+
+ if (!(val & AT91_PMC_MOSCRCEN)) {
+ pmc_update_bits(reg, AT91_CKGR_MOR,
+ MOR_KEY_MASK | AT91_PMC_MOSCRCEN,
+ AT91_PMC_KEY | AT91_PMC_MOSCRCEN);
+ }
+
+ pmc_read(reg, AT91_PMC_SR, );
+ while (!(val & AT91_PMC_MOSCRCS)) {
+ pmc_read(reg, AT91_PMC_SR, );
+ debug("waiting for main rc...\n");
+ cpu_relax();
+ }
+
+ return 0;
+}
+
+static int main_rc_disable(struct clk *clk)
+{
+ struct clk_main_rc *main_rc = to_clk_main_rc(clk);
+ struct reg *reg = main_rc->reg;
+ unsigned int val;
+
+ pmc_read(reg, AT91_CKGR_MOR, );
+
+ if (!(val & AT91_PMC_MOSCRCEN))
+ return 0;
+
+ pmc_update_bits(reg, AT91_CKGR_MOR, MOR_KEY_MASK | AT91_PMC_MOSCRCEN,
+ AT91_PMC_KEY);
+
+ return 0;
+}
+
+static const struct clk_ops main_rc_clk_ops = {
+ .enable = main_rc_enable,
+ .disable = main_rc_disable,
+ .get_rate = clk_generic_get_rate,
+};
+
+struct clk *at91_clk_main_rc(void __iomem *reg, const char *name,
+const char *parent_name)
+{
+ struct clk_main_rc *main_rc;
+ struct clk *clk;
+ int ret;
+
+ if (!reg || !name || !parent_name)
+ return ERR_PTR(-EINVAL);
+
+ main_rc = kzalloc(sizeof(*main_rc), GFP_KERNEL);
+ if (!main_rc)
+ return ERR_PTR(-ENOMEM);
+
+ main_rc->reg = reg;
+ clk = _rc->clk;
+
+ ret = clk_register(clk, UBOOT_DM_CLK_AT91_MAIN_RC, name,
+ parent_name);
+ if (ret) {
+ kfree(main_rc);
+ clk = ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
+U_BOOT_DRIVER(at91_main_rc_clk) = {
+ .name = UBOOT_DM_CLK_AT91_MAIN_RC,
+ .id = UCLASS_CLK,
+ .ops = _rc_clk_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+static int clk_main_osc_enable(struct clk *clk)
+{
+ struct clk_main_osc *main = to_clk_main_osc(clk);
+ void __iomem *reg = main->reg;
+ unsigned int val;
+
+ pmc_read(reg, AT91_CKGR_MOR, );
+ val &= ~MOR_KEY_MASK;
+
+ if (val & AT91_PMC_OSCBYPASS)
+ return 0;
+
+ if (!(val &
[PATCH 04/22] clk: bind clk to new parent device
Clock re-parenting is not binding the clock's device to its new
parent device, it only calls the clock's ops->set_parent() API. The
changes in this commit re-parent the clock device to its new parent
so that subsequent operations like clk_get_parent() to point to the
proper parent.
Signed-off-by: Claudiu Beznea
---
drivers/clk/clk-uclass.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index aa1f11a27c41..b390a6b01c06 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -511,6 +512,7 @@ ulong clk_set_rate(struct clk *clk, ulong rate)
int clk_set_parent(struct clk *clk, struct clk *parent)
{
const struct clk_ops *ops;
+ int ret;
debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
if (!clk_valid(clk))
@@ -520,7 +522,14 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
if (!ops->set_parent)
return -ENOSYS;
- return ops->set_parent(clk, parent);
+ ret = ops->set_parent(clk, parent);
+ if (ret)
+ return ret;
+
+ if (CONFIG_IS_ENABLED(CLK_CCF))
+ ret = device_reparent(clk->dev, parent->dev);
+
+ return ret;
}
int clk_enable(struct clk *clk)
--
2.7.4
[PATCH 03/22] dm: core: add support for device re-parenting
In common clock framework the relation b/w parent and child clocks is
determined based on the udevice parent/child information. A clock
parent could be changed based on devices needs. In case this is happen
the functionalities for clock who's parent is changed are broken. Add
a function that reparent a device. This will be used in clk-uclass.c
to reparent a clock device.
Signed-off-by: Claudiu Beznea
---
drivers/core/device.c| 26 ++
include/dm/device-internal.h | 9 +
2 files changed, 35 insertions(+)
diff --git a/drivers/core/device.c b/drivers/core/device.c
index a7408d9c76c6..f149d55ac1e1 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -267,6 +267,32 @@ int device_bind_by_name(struct udevice *parent, bool
pre_reloc_only,
devp);
}
+int device_reparent(struct udevice *dev, struct udevice *new_parent)
+{
+ struct udevice *cparent;
+ struct udevice *pos, *n;
+
+ if (!dev || !new_parent)
+ return -EINVAL;
+
+ if (!dev->parent)
+ return -ENODEV;
+
+ list_for_each_entry_safe(pos, n, >parent->child_head,
+sibling_node) {
+ if (pos->driver != dev->driver)
+ continue;
+
+ list_del(>sibling_node);
+ list_add_tail(>sibling_node, _parent->child_head);
+ dev->parent = new_parent;
+
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
static void *alloc_priv(int size, uint flags)
{
void *priv;
diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h
index 294d6c18105a..c5d7ec0650f9 100644
--- a/include/dm/device-internal.h
+++ b/include/dm/device-internal.h
@@ -84,6 +84,15 @@ int device_bind_by_name(struct udevice *parent, bool
pre_reloc_only,
const struct driver_info *info, struct udevice **devp);
/**
+ * device_reparent: reparent the device to a new parent
+ *
+ * @dev: pointer to device to be reparented
+ * @new_parent: pointer to new parent device
+ * @return 0 if OK, -ve on error
+ */
+int device_reparent(struct udevice *dev, struct udevice *new_parent);
+
+/**
* device_ofdata_to_platdata() - Read platform data for a device
*
* Read platform data for a device (typically from the device tree) so that
--
2.7.4
[PATCH 00/22] clk: at91: add sama7g5 support
The purpose of this series is to add clock support for SAMA7G5. Allong with this, clock drivers were switched to CCF and aligned with their corresponding versions present in Linux. Some changes were done for CCF, patches 1, 2, 4, 5, 6 (I don't know if they were as is by intention of a fixes tag is needed in there). Also patch 3/22 has been added to support clock re-reparenting (this is minimal support and hope it doesn't break anything if used). Thank you, Claudiu Beznea Claudiu Beznea (22): clk: check hw and hw->dev before dereference it clk: check pointer returned by dev_get_parent() dm: core: add support for device re-parenting clk: bind clk to new parent device clk: do not disable clock if it is critical clk: get clock pointer before proceeding clk: at91: add pre-requisite headers for AT91 clock architecture clk: at91: pmc: add helpers for clock drivers clk: at91: move clock code to compat.c clk: at91: sckc: add driver compatible with ccf clk: at91: clk-main: add driver compatible with ccf clk: at91: sam9x60-pll: add driver compatible with ccf clk: at91: clk-master: add driver compatible with ccf clk: at91: clk-master: add support for sama7g5 clk: at91: clk-utmi: add driver compatible with ccf clk: at91: clk-utmi: add support for sama7g5 clk: at91: clk-programmable: add driver compatible with ccf clk: at91: clk-system: add driver compatible with ccf clk: at91: clk-peripheral: add driver compatible with ccf clk: at91: clk-generic: add driver compatible with ccf clk: at91: pmc: add generic clock ops clk: at91: sama7g5: add clock support drivers/clk/at91/Kconfig|7 + drivers/clk/at91/Makefile | 15 +- drivers/clk/at91/clk-generated.c| 178 - drivers/clk/at91/clk-generic.c | 202 + drivers/clk/at91/clk-h32mx.c| 56 -- drivers/clk/at91/clk-main.c | 381 +- drivers/clk/at91/clk-master.c | 331 - drivers/clk/at91/clk-peripheral.c | 291 ++-- drivers/clk/at91/clk-plla.c | 54 -- drivers/clk/at91/clk-plladiv.c | 85 --- drivers/clk/at91/clk-programmable.c | 208 ++ drivers/clk/at91/clk-sam9x60-pll.c | 442 +++ drivers/clk/at91/clk-slow.c | 36 - drivers/clk/at91/clk-system.c | 143 ++-- drivers/clk/at91/clk-usb.c | 147 drivers/clk/at91/clk-utmi.c | 234 -- drivers/clk/at91/compat.c | 1023 + drivers/clk/at91/pmc.c | 218 +++--- drivers/clk/at91/pmc.h | 140 +++- drivers/clk/at91/sama7g5.c | 1401 +++ drivers/clk/at91/sckc.c | 169 - drivers/clk/clk-uclass.c| 58 +- drivers/clk/clk.c |3 + drivers/core/device.c | 26 + include/dm/device-internal.h|9 + include/dt-bindings/clk/at91.h | 22 + include/linux/clk/at91_pmc.h| 247 ++ 27 files changed, 5202 insertions(+), 924 deletions(-) delete mode 100644 drivers/clk/at91/clk-generated.c create mode 100644 drivers/clk/at91/clk-generic.c delete mode 100644 drivers/clk/at91/clk-h32mx.c delete mode 100644 drivers/clk/at91/clk-plla.c delete mode 100644 drivers/clk/at91/clk-plladiv.c create mode 100644 drivers/clk/at91/clk-programmable.c create mode 100644 drivers/clk/at91/clk-sam9x60-pll.c delete mode 100644 drivers/clk/at91/clk-slow.c delete mode 100644 drivers/clk/at91/clk-usb.c create mode 100644 drivers/clk/at91/compat.c create mode 100644 drivers/clk/at91/sama7g5.c create mode 100644 include/dt-bindings/clk/at91.h create mode 100644 include/linux/clk/at91_pmc.h -- 2.7.4
[PATCH 02/22] clk: check pointer returned by dev_get_parent()
Check pointer returned by dev_get_parent(). Signed-off-by: Claudiu Beznea --- drivers/clk/clk-uclass.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 70df9d410f4c..aa1f11a27c41 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -459,6 +459,9 @@ struct clk *clk_get_parent(struct clk *clk) return NULL; pdev = dev_get_parent(clk->dev); + if (!pdev) + return ERR_PTR(-ENOMEM); + pclk = dev_get_clk_ptr(pdev); if (!pclk) return ERR_PTR(-ENODEV); -- 2.7.4
[PATCH 05/22] clk: do not disable clock if it is critical
Do not disable clock if it is a critical one.
Signed-off-by: Claudiu Beznea
---
drivers/clk/clk-uclass.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index b390a6b01c06..958a9490bee2 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -605,6 +605,9 @@ int clk_disable(struct clk *clk)
if (CONFIG_IS_ENABLED(CLK_CCF)) {
if (clk->id && !clk_get_by_id(clk->id, )) {
+ if (clkp->flags & CLK_IS_CRITICAL)
+ return 0;
+
if (clkp->enable_count == 0) {
printf("clk %s already disabled\n",
clkp->dev->name);
--
2.7.4
[PATCH 01/22] clk: check hw and hw->dev before dereference it
Check hw and hw->dev before dereference it.
Signed-off-by: Claudiu Beznea
---
drivers/clk/clk.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 0f55ba751c0f..9fa18e342eaf 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -57,6 +57,9 @@ ulong clk_generic_get_rate(struct clk *clk)
const char *clk_hw_get_name(const struct clk *hw)
{
+ if (!hw || !hw->dev)
+ return NULL;
+
return hw->dev->name;
}
--
2.7.4
[PATCH v2] board: ti: am65x: Update fdt fixup logic for interconnect nodes
The DT nodes on AM65x SoCs currently use a node name "interconnect" for
the various interconnects. This name is not following the DT schema, and
should simply be "bus". Update the fdt fixup logic to use both the
current and the expected corrected path names so that this logic won't
be broken with newer kernels.
The logic also corrects the crypto node name as the DT node
unit-addresses are all expected to be lower case.
Signed-off-by: Suman Anna
---
v2: dropped the local variable due to its usage only in the conditional
CONFIG_TI_SECURE_DEVICE compilation path
v1:
https://patchwork.ozlabs.org/project/uboot/patch/20200723225609.29404-1-s-a...@ti.com/
board/ti/am65x/evm.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index 2eb8235c6988..36063b11383d 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -101,7 +101,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)
{
int ret;
- ret = fdt_fixup_msmc_ram(blob, "/interconnect@10", "sram@7000");
+ ret = fdt_fixup_msmc_ram(blob, "/bus@10", "sram@7000");
+ if (ret < 0)
+ ret = fdt_fixup_msmc_ram(blob, "/interconnect@10",
+"sram@7000");
if (ret) {
printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
return ret;
@@ -109,7 +112,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)
#if defined(CONFIG_TI_SECURE_DEVICE)
/* Make Crypto HW reserved for secure world use */
- ret = fdt_disable_node(blob, "/interconnect@10/crypto@4E0");
+ ret = fdt_disable_node(blob, "/bus@10/crypto@4e0");
+ if (ret < 0)
+ ret = fdt_disable_node(blob,
+ "/interconnect@10/crypto@4E0");
if (ret)
printf("%s: disabling SA2UL failed %d\n", __func__, ret);
#endif
--
2.26.0
Re: [PATCH 1/1] doc: riscv: debug UART for MAIX
On 7/29/20 1:23 PM, Heinrich Schuchardt wrote: > Provide the required settings for the debug UART. > > Signed-off-by: Heinrich Schuchardt > --- > doc/board/sipeed/maix.rst | 10 ++ > 1 file changed, 10 insertions(+) > > diff --git a/doc/board/sipeed/maix.rst b/doc/board/sipeed/maix.rst > index c235cb44a8..b1894f3a6f 100644 > --- a/doc/board/sipeed/maix.rst > +++ b/doc/board/sipeed/maix.rst > @@ -262,6 +262,16 @@ Boot Sequence > stage. > 8. The boot hart jumps to ``0x8000``. > > +Debug UART > +^^ > + > +The Debug UART is provided with the following settings:: > + > +CONFIG_DEBUG_UART=y > +CONFIG_DEBUG_UART_SIFIVE=y > +CONFIG_DEBUG_UART_BASE=0x3800 > +CONFIG_DEBUG_UART_CLOCK=39000 > + > Resetting the board > ^^^ > > -- > 2.27.0 > Reviewed-by: Sean Anderson
[PATCH 1/1] doc: riscv: debug UART for MAIX
Provide the required settings for the debug UART. Signed-off-by: Heinrich Schuchardt --- doc/board/sipeed/maix.rst | 10 ++ 1 file changed, 10 insertions(+) diff --git a/doc/board/sipeed/maix.rst b/doc/board/sipeed/maix.rst index c235cb44a8..b1894f3a6f 100644 --- a/doc/board/sipeed/maix.rst +++ b/doc/board/sipeed/maix.rst @@ -262,6 +262,16 @@ Boot Sequence stage. 8. The boot hart jumps to ``0x8000``. +Debug UART +^^ + +The Debug UART is provided with the following settings:: + +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_SIFIVE=y +CONFIG_DEBUG_UART_BASE=0x3800 +CONFIG_DEBUG_UART_CLOCK=39000 + Resetting the board ^^^ -- 2.27.0
Re: [PATCH 3/3] mkimage: fit: don't cipher ciphered data
Hi Patrick,
> From: Patrick Oppenlander
>
> Previously, mkimage -F could be run multiple times causing already
> ciphered image data to be ciphered again.
Good catch, mkimage -F cipher data that are already ciphered,
generating a broken FIT image.
> Signed-off-by: Patrick Oppenlander
> ---
> tools/image-host.c | 47 +++---
> 1 file changed, 32 insertions(+), 15 deletions(-)
>
> diff --git a/tools/image-host.c b/tools/image-host.c
> index 87ef79ef53..12de9b5ec0 100644
> --- a/tools/image-host.c
> +++ b/tools/image-host.c
> @@ -397,33 +397,43 @@ int fit_image_write_cipher(void *fit, int image_noffset,
> int noffset,
> const void *data, size_t size,
> unsigned char *data_ciphered, int data_ciphered_len)
> {
> - int ret = -1;
> + /*
> + * fit_image_cipher_data() uses the presence of the data-size-unciphered
> + * property as a sentinel to detect whether the data for this image is
> + * already encrypted. This is important as:
> + * - 'mkimage -F' can be run multiple times on a FIT image
> + * - This function is in a retry loop to handle ENOSPC
> + */
>
> - /* add non ciphered data size */
> + int ret;
> +
> + /* Add unciphered data size */
> ret = fdt_setprop_u32(fit, image_noffset, "data-size-unciphered", size);
> - if (ret == -FDT_ERR_NOSPACE) {
> - ret = -ENOSPC;
> - goto out;
> - }
> + if (ret == -FDT_ERR_NOSPACE)
> + return -ENOSPC;
> if (ret) {
> printf("Can't add unciphered data size (err = %d)\n", ret);
> - goto out;
> + return -EIO;
> }
>
> - /* Add ciphered data */
> + /* Replace contents of data property with data_ciphered */
> ret = fdt_setprop(fit, image_noffset, FIT_DATA_PROP,
> data_ciphered, data_ciphered_len);
> if (ret == -FDT_ERR_NOSPACE) {
> - ret = -ENOSPC;
> - goto out;
> + /* Remove data-size-unciphered; data is not ciphered */
> + ret = fdt_delprop(fit, image_noffset, "data-size-unciphered");
> + if (ret) {
> + printf("Can't remove unciphered data size (err = %d)\n", ret);
> + return -EIO;
> + }
> + return -ENOSPC;
> }
> if (ret) {
> - printf("Can't add ciphered data (err = %d)\n", ret);
> - goto out;
> + printf("Can't replace data with ciphered data (err = %d)\n", ret);
> + return -EIO;
> }
>
> - out:
> - return ret;
> + return 0;
> }
As for the second patch, I think that the loop is not an issue because
it always start with "fresh/clean" value (using a backup file).
So I am not sure that changes in this function are needed.
> static int
> @@ -482,7 +492,7 @@ int fit_image_cipher_data(const char *keydir, void
> *keydest,
> const char *image_name;
> const void *data;
> size_t size;
> - int cipher_node_offset;
> + int cipher_node_offset, len;
>
> /* Get image name */
> image_name = fit_get_name(fit, image_noffset, NULL);
> @@ -497,6 +507,13 @@ int fit_image_cipher_data(const char *keydir, void
> *keydest,
> return -1;
> }
>
> + /* Don't cipher ciphered data */
> + if (fdt_getprop(fit, image_noffset, "data-size-unciphered", ))
> + return 0;
> + if (len != -FDT_ERR_NOTFOUND) {
> + printf("Failure testing for data-size-unciphered\n");
> + return -1;
> + }
>From my point of view, it fixes an issue. But I see this solution more
as "workaround" than a clean solution.
As it fixes a real issue, we may start with it and then try to found a
"clean" solution.
> /* Process cipher node if present */
> cipher_node_offset = fdt_subnode_offset(fit, image_noffset, "cipher");
> --
> 2.27.0
Regards,
Philippe
Re: [PATCH v3 3/5] include/u-boot, lib/zlib: add sources for zlib decompression
On Wed, Jul 29, 2020 at 06:00:57PM +0200, Joao Marcos Costa wrote: > On Wed, 29 Jul 2020 11:27:45 -0400 > Tom Rini wrote: > > > On Tue, Jul 21, 2020 at 11:22:57AM +0200, Joao Marcos Costa wrote: > > > > > Add zlib (v1.2.11) uncompr() function to U-Boot. SquashFS depends on > > > this function to decompress data from a raw disk image. The actual > > > support for zlib into SquashFS sources will be added in a follow-up > > > commit. > > > > > > Signed-off-by: Joao Marcos Costa > > > --- > > > Changes in v3: > > > - No changes since v2. > > > Changes in v2: > > > - Changed commit title and message, which were wrong and/or > > > misleading in v1. > > > include/u-boot/zlib.h | 32 ++ > > > lib/zlib/uncompr.c| 97 > > > +++ lib/zlib/zlib.c > > > | 1 + 3 files changed, 130 insertions(+) > > > create mode 100644 lib/zlib/uncompr.c > > > > Can you confirm that on a platform where we aren't enabling squashfs > > the new zlib functionality ends up being discarded at link time? > > Thanks! > > > > I dumped lib/zlib/zlib.o with readelf and the new functionality is not > discarded, even though the SquashFS support is not enabled, but this > issue will be fixed in the next version (v4). Thank you! Well, don't dump lib/zlib/zlib.o, that won't say. Check u-boot.map :) -- Tom signature.asc Description: PGP signature
[PATCH 0/2] drivers: use of_match_ptr to avoid references when OF_PLATDATA is used
In order to save extra bytes when OF_PLATDATA is enabled avoid referencing compatible strings and additional functions by extending the use of of_match_ptr taking into account this configuration. Walter Lozano (2): core: improve of_match_ptr with OF_PLATDATA drivers: use of_match_ptr to avoid references when OF_PLATDATA is used drivers/clk/clk_fixed_factor.c| 2 +- drivers/clk/clk_fixed_rate.c | 2 +- drivers/clk/rockchip/clk_px30.c | 4 ++-- drivers/clk/rockchip/clk_rk3188.c | 2 +- drivers/clk/rockchip/clk_rk3288.c | 2 +- drivers/clk/rockchip/clk_rk3308.c | 2 +- drivers/clk/rockchip/clk_rk3368.c | 2 +- drivers/clk/rockchip/clk_rk3399.c | 4 ++-- drivers/core/simple-bus.c | 2 +- drivers/core/syscon-uclass.c | 2 +- drivers/gpio/mxs_gpio.c | 6 ++ drivers/mmc/ftsdc010_mci.c| 2 +- drivers/mmc/mxsmmc.c | 6 ++ drivers/mmc/rockchip_dw_mmc.c | 4 ++-- drivers/mmc/rockchip_sdhci.c | 2 +- drivers/pinctrl/intel/pinctrl_apl.c | 2 +- drivers/pinctrl/rockchip/pinctrl-px30.c | 2 +- drivers/pinctrl/rockchip/pinctrl-rk3328.c | 2 +- drivers/pinctrl/rockchip/pinctrl-rk3399.c | 2 +- drivers/ram/rockchip/dmc-rk3368.c | 2 +- drivers/ram/rockchip/sdram_rk3188.c | 2 +- drivers/ram/rockchip/sdram_rk322x.c | 2 +- drivers/ram/rockchip/sdram_rk3288.c | 2 +- drivers/ram/rockchip/sdram_rk3328.c | 2 +- drivers/ram/rockchip/sdram_rk3399.c | 2 +- drivers/spi/ich.c | 2 +- drivers/spi/mxs_spi.c | 6 ++ drivers/spi/rk_spi.c | 2 +- drivers/timer/rockchip_timer.c| 2 +- include/dm/device.h | 2 +- 30 files changed, 36 insertions(+), 42 deletions(-) -- 2.20.1
[PATCH 1/2] core: improve of_match_ptr with OF_PLATDATA
Currently of_match_ptr is used to avoid referencing compatible strings
when OF_CONTROL is not enabled. This behaviour could be improved by
taking into account also OF_PLATDATA, as when this configuration is
enabled the compatible strings are not used at all.
Signed-off-by: Walter Lozano
---
include/dm/device.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/dm/device.h b/include/dm/device.h
index 953706cf52..ac3b6c1b8a 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -197,7 +197,7 @@ struct udevice_id {
ulong data;
};
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
#define of_match_ptr(_ptr) (_ptr)
#else
#define of_match_ptr(_ptr) NULL
--
2.20.1
[PATCH 2/2] drivers: use of_match_ptr to avoid references when OF_PLATDATA is used
As when OF_PLATDATA is used compatible strings are not used at all
remove their reference to save extra bytes. Also in the cases where this
was done with #define change to of_match_ptr to improve readability.
Signed-off-by: Walter Lozano
---
drivers/clk/clk_fixed_factor.c| 2 +-
drivers/clk/clk_fixed_rate.c | 2 +-
drivers/clk/rockchip/clk_px30.c | 4 ++--
drivers/clk/rockchip/clk_rk3188.c | 2 +-
drivers/clk/rockchip/clk_rk3288.c | 2 +-
drivers/clk/rockchip/clk_rk3308.c | 2 +-
drivers/clk/rockchip/clk_rk3368.c | 2 +-
drivers/clk/rockchip/clk_rk3399.c | 4 ++--
drivers/core/simple-bus.c | 2 +-
drivers/core/syscon-uclass.c | 2 +-
drivers/gpio/mxs_gpio.c | 6 ++
drivers/mmc/ftsdc010_mci.c| 2 +-
drivers/mmc/mxsmmc.c | 6 ++
drivers/mmc/rockchip_dw_mmc.c | 4 ++--
drivers/mmc/rockchip_sdhci.c | 2 +-
drivers/pinctrl/intel/pinctrl_apl.c | 2 +-
drivers/pinctrl/rockchip/pinctrl-px30.c | 2 +-
drivers/pinctrl/rockchip/pinctrl-rk3328.c | 2 +-
drivers/pinctrl/rockchip/pinctrl-rk3399.c | 2 +-
drivers/ram/rockchip/dmc-rk3368.c | 2 +-
drivers/ram/rockchip/sdram_rk3188.c | 2 +-
drivers/ram/rockchip/sdram_rk322x.c | 2 +-
drivers/ram/rockchip/sdram_rk3288.c | 2 +-
drivers/ram/rockchip/sdram_rk3328.c | 2 +-
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
drivers/spi/ich.c | 2 +-
drivers/spi/mxs_spi.c | 6 ++
drivers/spi/rk_spi.c | 2 +-
drivers/timer/rockchip_timer.c| 2 +-
29 files changed, 35 insertions(+), 41 deletions(-)
diff --git a/drivers/clk/clk_fixed_factor.c b/drivers/clk/clk_fixed_factor.c
index cf9c4ae367..f4171464f6 100644
--- a/drivers/clk/clk_fixed_factor.c
+++ b/drivers/clk/clk_fixed_factor.c
@@ -65,7 +65,7 @@ static const struct udevice_id clk_fixed_factor_match[] = {
U_BOOT_DRIVER(clk_fixed_factor) = {
.name = "fixed_factor_clock",
.id = UCLASS_CLK,
- .of_match = clk_fixed_factor_match,
+ .of_match = of_match_ptr(clk_fixed_factor_match),
.ofdata_to_platdata = clk_fixed_factor_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct clk_fixed_factor),
.ops = _fixed_factor_ops,
diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 2c20eddb0b..cfffb18553 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -49,7 +49,7 @@ static const struct udevice_id clk_fixed_rate_match[] = {
U_BOOT_DRIVER(clk_fixed_rate) = {
.name = "fixed_rate_clock",
.id = UCLASS_CLK,
- .of_match = clk_fixed_rate_match,
+ .of_match = of_match_ptr(clk_fixed_rate_match),
.ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
.ops = _fixed_rate_ops,
diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c
index 71916dbf3b..014ff51bad 100644
--- a/drivers/clk/rockchip/clk_px30.c
+++ b/drivers/clk/rockchip/clk_px30.c
@@ -1479,7 +1479,7 @@ static const struct udevice_id px30_clk_ids[] = {
U_BOOT_DRIVER(rockchip_px30_cru) = {
.name = "rockchip_px30_cru",
.id = UCLASS_CLK,
- .of_match = px30_clk_ids,
+ .of_match = of_match_ptr(px30_clk_ids),
.priv_auto_alloc_size = sizeof(struct px30_clk_priv),
.ofdata_to_platdata = px30_clk_ofdata_to_platdata,
.ops= _clk_ops,
@@ -1626,7 +1626,7 @@ static const struct udevice_id px30_pmuclk_ids[] = {
U_BOOT_DRIVER(rockchip_px30_pmucru) = {
.name = "rockchip_px30_pmucru",
.id = UCLASS_CLK,
- .of_match = px30_pmuclk_ids,
+ .of_match = of_match_ptr(px30_pmuclk_ids),
.priv_auto_alloc_size = sizeof(struct px30_pmuclk_priv),
.ofdata_to_platdata = px30_pmuclk_ofdata_to_platdata,
.ops= _pmuclk_ops,
diff --git a/drivers/clk/rockchip/clk_rk3188.c
b/drivers/clk/rockchip/clk_rk3188.c
index aacc8cf2d1..3c9049ad67 100644
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -615,7 +615,7 @@ static const struct udevice_id rk3188_clk_ids[] = {
U_BOOT_DRIVER(rockchip_rk3188_cru) = {
.name = "rockchip_rk3188_cru",
.id = UCLASS_CLK,
- .of_match = rk3188_clk_ids,
+ .of_match = of_match_ptr(rk3188_clk_ids),
.priv_auto_alloc_size = sizeof(struct rk3188_clk_priv),
.platdata_auto_alloc_size = sizeof(struct rk3188_clk_plat),
.ops= _clk_ops,
diff --git a/drivers/clk/rockchip/clk_rk3288.c
b/drivers/clk/rockchip/clk_rk3288.c
index a1dd642eef..6914c31e66 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++
Re: [PATCH v3 0/5] Add support for the SquashFS filesystem
On Wed, 29 Jul 2020 11:21:26 -0400 Tom Rini wrote: > On Wed, Jul 29, 2020 at 02:54:56PM +0200, Joao Marcos Costa wrote: > > On Tue, 21 Jul 2020 11:22:54 +0200 > > Joao Marcos Costa wrote: > > > > > Hello! > > > > > > This series adds support for the SquashFS filesystem. For now, > > > zlib is the only supported compression type. This is my first > > > contribution to U-Boot as well as to a major Open Source project. > > > > > > Changes in v3: > > > - Replace CONFIG_IS_ENABLED by IS_ENABLED in fs/fs.c > > > Changes in v2: > > > - Replace sqfs_ls() by U-Boot's fs_ls_generic() > > > - Add info. to MAINTAINERS > > > - Fix build failures > > > - Fix style problems > > > > > > Best regards, > > > Joao Marcos Costa > > > > > > Joao Marcos Costa (5): > > > fs/squashfs: new filesystem > > > fs/squashfs: add filesystem commands > > > include/u-boot, lib/zlib: add sources for zlib decompression > > > fs/squashfs: add support for zlib decompression > > > fs/fs.c: add symbolic link case to fs_ls_generic() > > > > > > MAINTAINERS |7 + > > > cmd/Kconfig |6 + > > > cmd/Makefile|1 + > > > cmd/sqfs.c | 42 + > > > common/spl/Kconfig |9 + > > > fs/Kconfig |2 + > > > fs/Makefile |2 + > > > fs/fs.c | 18 + > > > fs/squashfs/Kconfig | 10 + > > > fs/squashfs/Makefile|7 + > > > fs/squashfs/sqfs.c | 1521 > > > +++ fs/squashfs/sqfs_decompressor.c | > > > 53 ++ fs/squashfs/sqfs_decompressor.h | 58 ++ > > > fs/squashfs/sqfs_dir.c | 107 +++ > > > fs/squashfs/sqfs_filesystem.h | 300 ++ > > > fs/squashfs/sqfs_inode.c| 142 +++ > > > fs/squashfs/sqfs_utils.h| 49 + > > > include/fs.h|1 + > > > include/squashfs.h | 25 + > > > include/u-boot/zlib.h | 32 + > > > lib/zlib/uncompr.c | 97 ++ > > > lib/zlib/zlib.c |1 + > > > 22 files changed, 2490 insertions(+) > > > create mode 100644 cmd/sqfs.c > > > create mode 100644 fs/squashfs/Kconfig > > > create mode 100644 fs/squashfs/Makefile > > > create mode 100644 fs/squashfs/sqfs.c > > > create mode 100644 fs/squashfs/sqfs_decompressor.c > > > create mode 100644 fs/squashfs/sqfs_decompressor.h > > > create mode 100644 fs/squashfs/sqfs_dir.c > > > create mode 100644 fs/squashfs/sqfs_filesystem.h > > > create mode 100644 fs/squashfs/sqfs_inode.c > > > create mode 100644 fs/squashfs/sqfs_utils.h > > > create mode 100644 include/squashfs.h > > > create mode 100644 lib/zlib/uncompr.c > > > > > > > Hello again, > > > > I am currently writing tests for the SquashFS support. I wrote two > > Python scripts to test 'ls' and 'load' commands, but I need a > > SquashFS image to do so, and I would like to know what is the > > better approach for this: > > - Add a compiled SquashFS image into the same directory as the > > tests, i.e.: test/py/tests/test_fs/test_squashfs. This is a +-7MB > > sized binary file. > > - Use the scripts to generate an image, with mksquashfs. However, > > mksquashfs becomes a dependency. > > We should dynamically make the images, just like ext* and fat. The > tests should skip when the required tools aren't found, in the same > manner we do for other fs tests. Thanks! > Ok, thank you! Best regards, Joao Marcos
Re: [PATCH 0/6] efi_selftest: allow UEFI testing on MAIX
On 29.07.20 17:42, Heinrich Schuchardt wrote: > For RISC-V testing on real hardware the Sipeed MAIX boards provides an > affordable solution. > > UEFI testing fails on the MAIX BiT with Mic because the UEFI sub-system > reserves 16 MiB for the stack though the board only has 8 MiB. > > The first two patches make the size of the memory reserved for the stack > customizable on all boards defaulting to 16 MiB. > > The value on the the MAIX BiT with Mic is set to 1 MiB. > > Missing default load addresses for the MAIX BiT with Mic are added. > > The sysreset driver is fixed to output the full reset message. > > The UEFI network and block device unit tests are only built if the > configuration provides the prerequisites. > > > Heinrich Schuchardt (6): > efi_loader: use CONFIG_STACK_SIZE in the UEFI sub-system > configs: reduce stack size of Sipeed MAIX > riscv: load addresses for Sipeed MAIX > dm: sysreset: wait after reset message > efi_selftest: SNP test depends on network > efi_selftest: block device test requires CONFIG_DOS_PARTITION This patch is prerequisite for the series: https://lists.denx.de/pipermail/u-boot/2020-July/421925.html x86: rename CONFIG_STACK_SIZE Best regards Heinrich > > Kconfig| 10 ++ > arch/arm/Kconfig | 17 - > arch/microblaze/Kconfig| 8 > configs/sipeed_maix_bitm_defconfig | 1 + > drivers/sysreset/sysreset-uclass.c | 1 + > include/configs/sipeed-maix.h | 9 + > lib/efi_loader/efi_memory.c| 2 +- > lib/efi_selftest/Kconfig | 2 ++ > lib/efi_selftest/Makefile | 5 +++-- > 9 files changed, 27 insertions(+), 28 deletions(-) > > -- > 2.27.0 >
Re: [PATCH v3 3/5] include/u-boot, lib/zlib: add sources for zlib decompression
On Wed, 29 Jul 2020 11:27:45 -0400 Tom Rini wrote: > On Tue, Jul 21, 2020 at 11:22:57AM +0200, Joao Marcos Costa wrote: > > > Add zlib (v1.2.11) uncompr() function to U-Boot. SquashFS depends on > > this function to decompress data from a raw disk image. The actual > > support for zlib into SquashFS sources will be added in a follow-up > > commit. > > > > Signed-off-by: Joao Marcos Costa > > --- > > Changes in v3: > > - No changes since v2. > > Changes in v2: > > - Changed commit title and message, which were wrong and/or > > misleading in v1. > > include/u-boot/zlib.h | 32 ++ > > lib/zlib/uncompr.c| 97 > > +++ lib/zlib/zlib.c > > | 1 + 3 files changed, 130 insertions(+) > > create mode 100644 lib/zlib/uncompr.c > > Can you confirm that on a platform where we aren't enabling squashfs > the new zlib functionality ends up being discarded at link time? > Thanks! > I dumped lib/zlib/zlib.o with readelf and the new functionality is not discarded, even though the SquashFS support is not enabled, but this issue will be fixed in the next version (v4). Thank you!
Re: [RFC 3/4] dtoc: add support for generate stuct udevice_id
Hi Simon,
On 28/7/20 23:42, Simon Glass wrote:
Hi Walter,
On Sun, 26 Jul 2020 at 20:16, Walter Lozano wrote:
Hi Simon,
On 26/7/20 11:53, Simon Glass wrote:
Hi Walter,
On Tue, 7 Jul 2020 at 08:08, Walter Lozano wrote:
Hi Simon
On 6/7/20 16:21, Simon Glass wrote:
Hi Walter,
On Fri, 19 Jun 2020 at 15:12, Walter Lozano wrote:
Based on several reports there is an increasing concern in the impact
of adding additional features to drivers based on compatible strings.
A good example of this situation is found in [1].
In order to reduce this impact and as an initial step for further
reduction, propose a new way to declare compatible strings, which allows
to only include the useful ones.
What are the useful ones?
The useful ones would be those that are used by the selected DTB by the
current configuration. The idea of this patch is to declare all the
possible compatible strings in a way that dtoc can generate code for
only those which are going to be used, and in this way avoid lots of
#ifdef like the ones shows in
http://patchwork.ozlabs.org/project/uboot/patch/20200525202429.2146-1-ag...@denx.de/
The idea is to define compatible strings in a way to be easily parsed by
dtoc, which will be responsible to build struct udevice_id [] based on
the compatible strings present in the dtb.
Additional features can be easily added, such as define constants
depending on the presence of compatible strings, which allows to enable
code blocks only in such cases without the need of adding additional
configuration options.
[1]
http://patchwork.ozlabs.org/project/uboot/patch/20200525202429.2146-1-ag...@denx.de/
Signed-off-by: Walter Lozano
---
tools/dtoc/dtb_platdata.py | 32
1 file changed, 32 insertions(+)
I think dtoc should be able to parse the compatible strings as they
are today - e.g. see the tiny-dm stuff.
Yes, I agree. My idea is that dtoc parses compatible strings as they are
today but also in this new way. The reason for this is to allow dtoc to
generate the code to include the useful compatible strings. Of course,
this only makes sense if the idea of generating the compatible string
associated code is accepted.
What do you think?
I think this is useful and better than using #ifdef in the source code
for this sort of thing. We need a way to specify the driver_data value
as well, right?
Yes, I agree, it is better than #ifdef and c/ould give us some extra
functionality.
What doe you mean by driver_data value? Are you referring to the data
field? like
static struct esdhc_soc_data usdhc_imx7d_data = {
.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
| ESDHC_FLAG_HS400,
};
Actually I was talking about the .data member in struct udevice_id.
So my example is correct, as usdhc_imx7d_data is the value for .data in
one case as shown bellow.
If that is the case, I was thinking in defining a constant when specific
compatible strings are enabled by dtoc, based in the above case
#ifdef FSL_ESDHC_IMX_V2
static struct esdhc_soc_data usdhc_imx7d_data = {
.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
| ESDHC_FLAG_HS400,
};
#endif
COMPATIBLE(FSL_ESDHC, "fsl,imx7d-usdhc", _imx7d_data, FSL_ESDHC_IMX_V2)
So when dtoc parses COMPATIBLE and determines that compatible
"fsl,imx7d-usdhc" should be added it also defines FSL_ESDHC_IMX_V2.
I think we can put that data in the dt-platdata.c file perhaps.
I thought the same at the beginning, but then I changed my mind, because
1- in order to work dt-platdata.c will need to include several different
.h, in this example, only for fsl_esdhc_imx to work, we will need to
include fsl_esdhc_imx.h where all the flags are defined.
2- it case we use #define to avoid having to include several different
.h probably the errors will be more difficult to catch/debug
What do you think?
This is alsoAs I comment you in the tread about tiny-dm I think that we
can save some space following your suggestions, and for instance implement
Re naming, perhaps DT_COMPAT() might be better than COMPATIBLE()? Or
even a name that indicates that it is optional, like DT_OPT_COMPAT() ?
I totally agree, naming is very important, and DT_COMPAT() is much better.
What I don't fully understand is what are the cases for DT_OPT_COMPAT(),
could you please clarify?
It's just an alternative name, with OPT meaning optional. But I think
we can leave out the OPT.
Thanks for clarifying.
Regards,
Walter
[PATCH 1/1] x86: rename CONFIG_STACK_SIZE
Configuration variables should have the same meaning independent of the architecture. x86 and ARM both use CONFIG_STACK_SIZE: * x86: U-Boot's runtime stack size during reboot * ARM: max stack size that can be used by U-Boot Rename the x86 configuration variable to CONFIG_STACK_SIZE_REBOOT Signed-off-by: Heinrich Schuchardt --- arch/x86/Kconfig| 2 +- arch/x86/lib/fsp/fsp_dram.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index ff4f06ed79..f677472501 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -802,7 +802,7 @@ config S3_VGA_ROM_RUN graphics console won't work without VGA options ROMs. Set it to N if your kernel is only on a serial console. -config STACK_SIZE +config STACK_SIZE_RESUME hex depends on HAVE_ACPI_RESUME default 0x1000 diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 01d498c21e..faa819fab4 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -121,7 +121,7 @@ unsigned int install_e820_map(unsigned int max_entries, ulong stack_size; stack_size = CONFIG_IS_ENABLED(HAVE_ACPI_RESUME, - (CONFIG_STACK_SIZE), (0)); + (CONFIG_STACK_SIZE_RESUME), (0)); /* * Everything between U-Boot's stack and ram top needs to be * reserved in order for ACPI S3 resume to work. -- 2.27.0
[PATCH 4/6] dm: sysreset: wait after reset message
In our Python tests we expect to see the word "resetting". It may be
truncated if we reset before the serial console buffer is transferred.
Wait for 100 ms between the "resetting ..." message and the actual reset
like we do when powering off.
Signed-off-by: Heinrich Schuchardt
---
drivers/sysreset/sysreset-uclass.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/sysreset/sysreset-uclass.c
b/drivers/sysreset/sysreset-uclass.c
index 995240f0cb..3f5414ed1f 100644
--- a/drivers/sysreset/sysreset-uclass.c
+++ b/drivers/sysreset/sysreset-uclass.c
@@ -117,6 +117,7 @@ void reset_cpu(ulong addr)
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
printf("resetting ...\n");
+ mdelay(100);
sysreset_walk_halt(SYSRESET_COLD);
--
2.27.0
[PATCH 3/6] riscv: load addresses for Sipeed MAIX
Define default load addresses and the device tree name for the Sipeed MAIX. Signed-off-by: Heinrich Schuchardt --- include/configs/sipeed-maix.h | 9 + 1 file changed, 9 insertions(+) diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h index a46473fc78..978db6fb00 100644 --- a/include/configs/sipeed-maix.h +++ b/include/configs/sipeed-maix.h @@ -21,4 +21,13 @@ /* For early init */ #define K210_SYSCTL_BASE 0x5044 +#ifndef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x8004\0" \ + "fdt_addr_r=0x8001\0" \ + "scriptaddr=0x80008000\0" \ + "kernel_addr_r=0x8004\0" \ + "fdtfile=kendryte/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" +#endif + #endif /* CONFIGS_SIPEED_MAIX_H */ -- 2.27.0
[PATCH 2/6] configs: reduce stack size of Sipeed MAIX
The K210 has only 8 MiB RAM thereof 2 MiB reserved for AI. Allow only 1 MiB for the stack. Signed-off-by: Heinrich Schuchardt --- configs/sipeed_maix_bitm_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig index 96651f0268..459bf0d530 100644 --- a/configs/sipeed_maix_bitm_defconfig +++ b/configs/sipeed_maix_bitm_defconfig @@ -1,6 +1,7 @@ CONFIG_RISCV=y CONFIG_TARGET_SIPEED_MAIX=y CONFIG_ARCH_RV64I=y +CONFIG_STACK_SIZE=0x10 # CONFIG_NET is not set # CONFIG_INPUT is not set # CONFIG_DM_ETH is not set -- 2.27.0
[PATCH 6/6] efi_selftest: block device test requires CONFIG_DOS_PARTITION
Do not execute the block device test if CONFIG_DOS_PARTITION=n. Imply CONFIG_DOS_PARTITION in Kconfig. Signed-off-by: Heinrich Schuchardt --- lib/efi_selftest/Kconfig | 2 ++ lib/efi_selftest/Makefile | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/efi_selftest/Kconfig b/lib/efi_selftest/Kconfig index 478140330b..ca62436108 100644 --- a/lib/efi_selftest/Kconfig +++ b/lib/efi_selftest/Kconfig @@ -1,6 +1,8 @@ config CMD_BOOTEFI_SELFTEST bool "UEFI unit tests" depends on CMD_BOOTEFI + imply PARTITIONS + imply DOS_PARTITION imply FAT imply FAT_WRITE imply CMD_POWEROFF if PSCI_RESET || SYSRESET_PSCI diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile index 7f849032ed..45ce6859b8 100644 --- a/lib/efi_selftest/Makefile +++ b/lib/efi_selftest/Makefile @@ -57,7 +57,7 @@ ifeq ($(CONFIG_GENERATE_ACPI_TABLE),) obj-y += efi_selftest_fdt.o endif -ifeq ($(CONFIG_BLK)$(CONFIG_PARTITIONS),yy) +ifeq ($(CONFIG_BLK)$(CONFIG_DOS_PARTITION),yy) obj-y += efi_selftest_block_device.o endif -- 2.27.0
[PATCH 5/6] efi_selftest: SNP test depends on network
If CONFIG_NET=n, testing the simple network protocol makes no sense. Signed-off-by: Heinrich Schuchardt --- lib/efi_selftest/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile index e9baa64135..7f849032ed 100644 --- a/lib/efi_selftest/Makefile +++ b/lib/efi_selftest/Makefile @@ -32,7 +32,6 @@ efi_selftest_memory.o \ efi_selftest_open_protocol.o \ efi_selftest_register_notify.o \ efi_selftest_set_virtual_address_map.o \ -efi_selftest_snp.o \ efi_selftest_textinput.o \ efi_selftest_textinputex.o \ efi_selftest_textoutput.o \ @@ -42,6 +41,8 @@ efi_selftest_variables.o \ efi_selftest_variables_runtime.o \ efi_selftest_watchdog.o +obj-$(CONFIG_NET) += efi_selftest_snp.o + obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_selftest_devicepath.o obj-$(CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2) += \ efi_selftest_unicode_collation.o -- 2.27.0
[PATCH 0/6] efi_selftest: allow UEFI testing on MAIX
For RISC-V testing on real hardware the Sipeed MAIX boards provides an affordable solution. UEFI testing fails on the MAIX BiT with Mic because the UEFI sub-system reserves 16 MiB for the stack though the board only has 8 MiB. The first two patches make the size of the memory reserved for the stack customizable on all boards defaulting to 16 MiB. The value on the the MAIX BiT with Mic is set to 1 MiB. Missing default load addresses for the MAIX BiT with Mic are added. The sysreset driver is fixed to output the full reset message. The UEFI network and block device unit tests are only built if the configuration provides the prerequisites. Heinrich Schuchardt (6): efi_loader: use CONFIG_STACK_SIZE in the UEFI sub-system configs: reduce stack size of Sipeed MAIX riscv: load addresses for Sipeed MAIX dm: sysreset: wait after reset message efi_selftest: SNP test depends on network efi_selftest: block device test requires CONFIG_DOS_PARTITION Kconfig| 10 ++ arch/arm/Kconfig | 17 - arch/microblaze/Kconfig| 8 configs/sipeed_maix_bitm_defconfig | 1 + drivers/sysreset/sysreset-uclass.c | 1 + include/configs/sipeed-maix.h | 9 + lib/efi_loader/efi_memory.c| 2 +- lib/efi_selftest/Kconfig | 2 ++ lib/efi_selftest/Makefile | 5 +++-- 9 files changed, 27 insertions(+), 28 deletions(-) -- 2.27.0
[PATCH 1/6] efi_loader: use CONFIG_STACK_SIZE in the UEFI sub-system
The Kconfig symbol CONFIG_STACK_SIZE is used both by ARM and Microblaze with the same meaning. Move it to menu 'General setup' so that we can use it for all architectures. Use the value of CONFIG_STACK_SIZE instead of a hard coded 16 MiB value for reserving memory in the UEFI sub-system. Signed-off-by: Heinrich Schuchardt --- Kconfig | 10 ++ arch/arm/Kconfig| 17 - arch/microblaze/Kconfig | 8 lib/efi_loader/efi_memory.c | 2 +- 4 files changed, 11 insertions(+), 26 deletions(-) diff --git a/Kconfig b/Kconfig index e6308f30e5..fda35f9e45 100644 --- a/Kconfig +++ b/Kconfig @@ -350,6 +350,16 @@ config PLATFORM_ELFENTRY default "__start" if MIPS default "_start" +config STACK_SIZE + hex "Define max stack size that can be used by U-Boot" + default 0x400 if ARCH_VERSAL || ARCH_ZYNQMP + default 0x20 if MICROBLAZE + default 0x100 + help + Define Max stack size that can be used by U-Boot. This value is used + by the UEFI sub-system. On some boards initrd_high is calculated as + base stack pointer minus this stack size. + endmenu# General setup menu "Boot images" diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ded8cfee09..e01196e724 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -501,23 +501,6 @@ config TPL_USE_ARCH_MEMSET Such an implementation may be faster under some conditions but may increase the binary size. -config SET_STACK_SIZE - bool "Enable an option to set max stack size that can be used" - default y if ARCH_VERSAL || ARCH_ZYNQMP || ARCH_ZYNQ - help - This will enable an option to set max stack size that can be - used by U-Boot. - -config STACK_SIZE - hex "Define max stack size that can be used by U-Boot" - depends on SET_STACK_SIZE - default 0x400 if ARCH_VERSAL || ARCH_ZYNQMP - default 0x100 if ARCH_ZYNQ - help - Define Max stack size that can be used by U-Boot so that the - initrd_high will be calculated as base stack pointer minus this - stack size. - config ARM64_SUPPORT_AARCH32 bool "ARM64 system support AArch32 execution state" depends on ARM64 diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 2bd260e5d7..ff6b3c7e3d 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -20,14 +20,6 @@ config TARGET_MICROBLAZE_GENERIC endchoice -config STACK_SIZE - hex "Define max stack size that can be used by u-boot" - default 0x20 - help - Defines Max stack size that can be used by u-boot so that the - initrd_high will be calculated as base stack pointer minus this - stack size. - source "board/xilinx/microblaze-generic/Kconfig" endmenu diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 44b8a2e09f..7be756e370 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -762,7 +762,7 @@ static void add_u_boot_and_runtime(void) unsigned long runtime_start, runtime_end, runtime_pages; unsigned long runtime_mask = EFI_PAGE_MASK; unsigned long uboot_start, uboot_pages; - unsigned long uboot_stack_size = 16 * 1024 * 1024; + unsigned long uboot_stack_size = CONFIG_STACK_SIZE; /* Add U-Boot */ uboot_start = ((uintptr_t)map_sysmem(gd->start_addr_sp, 0) - -- 2.27.0
[PATCH v3 4/6] mmc: fsl_esdhc_imx: add CD support when OF_PLATDATA is enabled
After enabling OF_PLATDATA support to both MMC and GPIO drivers add the
support for card detection.
Signed-off-by: Walter Lozano
Reviewed-by: Simon Glass
---
Changes in v3:
- Change #ifdef to if when possible
drivers/mmc/fsl_esdhc_imx.c | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 2713682cf7..788677984b 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -1498,7 +1498,30 @@ static int fsl_esdhc_probe(struct udevice *dev)
priv->bus_width = 4;
else
priv->bus_width = 1;
- priv->non_removable = 1;
+
+ if (dtplat->non_removable)
+ priv->non_removable = 1;
+ else
+ priv->non_removable = 0;
+
+ if (CONFIG_IS_ENABLED(DM_GPIO) && !priv->non_removable) {
+ struct udevice *gpiodev;
+ struct driver_info *info;
+
+ info = (struct driver_info *)dtplat->cd_gpios->node;
+
+ ret = device_get_by_driver_info(info, );
+
+ if (ret)
+ return ret;
+
+ ret = gpio_dev_request_index(gpiodev, gpiodev->name, "cd-gpios",
+dtplat->cd_gpios->arg[0],
GPIOD_IS_IN,
+dtplat->cd_gpios->arg[1],
>cd_gpio);
+
+ if (ret)
+ return ret;
+ }
#endif
if (data)
--
2.20.1
Re: [PATCH v2 3/6] gpio: mxc_gpio: add OF_PLATDATA support
Hi Stefano,
On 27/7/20 09:10, Stefano Babic wrote:
Hi Walter,
On 22.07.20 15:14, Walter Lozano wrote:
Continuing with the OF_PLATADATA support for iMX6 to reduce SPL
footprint, add it to mxc_gpio. Thanks to this, it will be possible to
enable card detection on MMC driver.
Signed-off-by: Walter Lozano
---
This conflicts with commit 6103e570cdd0d0e854b071ee17b14589356a82bd
Author: Ye Li
Date: Tue Jun 9 20:29:51 2020 -0700
gpio: mxc_gpio: Improve to use ofdata_to_platdata
already mainlined. Can you take a look ? Thanks !
Sure, thanks for pointing at the issue. I've already sent a new version.
Regards,
Walter
(no changes since v1)
drivers/gpio/mxc_gpio.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 316dcc757b..fc49b5b577 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -13,6 +13,8 @@
#include
#include
#include
+#include
+#include
enum mxc_gpio_direction {
MXC_GPIO_DIRECTION_IN,
@@ -22,6 +24,10 @@ enum mxc_gpio_direction {
#define GPIO_PER_BANK 32
struct mxc_gpio_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ /* Put this first since driver model will copy the data here */
+ struct dtd_gpio_mxc dtplat;
+#endif
int bank_index;
struct gpio_regs *regs;
};
@@ -306,8 +312,16 @@ static int mxc_gpio_bind(struct udevice *dev)
* is statically initialized in U_BOOT_DEVICES.Here
* will return.
*/
- if (plat)
+
+ if (plat) {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_gpio_mxc *dtplat = >dtplat;
+
+ plat->regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
+ plat->bank_index = dev->req_seq;
+#endif
return 0;
+ }
addr = devfdt_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
@@ -350,6 +364,8 @@ U_BOOT_DRIVER(gpio_mxc) = {
.bind = mxc_gpio_bind,
};
+U_BOOT_DRIVER_ALIAS(gpio_mxc, fsl_imx6q_gpio)
+
#if !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct mxc_gpio_plat mxc_plat[] = {
{ 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
[PATCH v3 5/6] drivers: rename more drivers to match compatible string
Continuing with the approach in commit rename
additional drivers to allow the OF_PLATDATA support.
Signed-off-by: Walter Lozano
Reviewed-by: Simon Glass
---
(no changes since v1)
drivers/pinctrl/nxp/pinctrl-imx6.c | 6 --
drivers/video/imx/mxc_ipuv3_fb.c | 4 ++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c
b/drivers/pinctrl/nxp/pinctrl-imx6.c
index aafa3057ad..84004e5921 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx6.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx6.c
@@ -41,8 +41,8 @@ static const struct udevice_id imx6_pinctrl_match[] = {
{ /* sentinel */ }
};
-U_BOOT_DRIVER(imx6_pinctrl) = {
- .name = "imx6-pinctrl",
+U_BOOT_DRIVER(fsl_imx6q_iomuxc) = {
+ .name = "fsl_imx6q_iomuxc",
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(imx6_pinctrl_match),
.probe = imx6_pinctrl_probe,
@@ -51,3 +51,5 @@ U_BOOT_DRIVER(imx6_pinctrl) = {
.ops = _pinctrl_ops,
.flags = DM_FLAG_PRE_RELOC,
};
+
+U_BOOT_DRIVER_ALIAS(fsl_imx6q_iomuxc, fsl_imx6dl_iomuxc)
diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c
index 587d62f2d8..492bc3e829 100644
--- a/drivers/video/imx/mxc_ipuv3_fb.c
+++ b/drivers/video/imx/mxc_ipuv3_fb.c
@@ -660,8 +660,8 @@ static const struct udevice_id ipuv3_video_ids[] = {
{ }
};
-U_BOOT_DRIVER(ipuv3_video) = {
- .name = "ipuv3_video",
+U_BOOT_DRIVER(fsl_imx6q_ipu) = {
+ .name = "fsl_imx6q_ipu",
.id = UCLASS_VIDEO,
.of_match = ipuv3_video_ids,
.bind = ipuv3_video_bind,
--
2.20.1
