[PATCH] mmc: meson_gx_mmc: control ddr_mode bit
EMMC_CFG register has a cfg_ddr bit(BIT[2]). It needs to set when mmc is running to ddr mode. Otherwise, its bit should be cleared. CFG_DDR[2] - 1: DDR mode, 0: SDR mode Signed-off-by: Jaehoon Chung --- arch/arm/include/asm/arch-meson/sd_emmc.h | 1 + drivers/mmc/meson_gx_mmc.c| 5 + 2 files changed, 6 insertions(+) diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h index 1e9f8cf498b4..c2f77c7308ec 100644 --- a/arch/arm/include/asm/arch-meson/sd_emmc.h +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h @@ -38,6 +38,7 @@ #define CFG_BUS_WIDTH_1 0 #define CFG_BUS_WIDTH_4 1 #define CFG_BUS_WIDTH_8 2 +#define CFG_DDR_MODE BIT(2) #define CFG_BL_LEN_MASK GENMASK(7, 4) #define CFG_BL_LEN_SHIFT 4 #define CFG_BL_LEN_512 (9 << 4) diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 7c60e0566560..6fcf6c2ced27 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -90,6 +90,11 @@ static int meson_dm_mmc_set_ios(struct udevice *dev) else return -EINVAL; + if (mmc->ddr_mode) + meson_mmc_cfg |= CFG_DDR_MODE; + else + meson_mmc_cfg &= ~CFG_DDR_MODE; + /* 512 bytes block length */ meson_mmc_cfg &= ~CFG_BL_LEN_MASK; meson_mmc_cfg |= CFG_BL_LEN_512; -- 2.29.0
[PATCH 1/2 v3] tpm: Add some headers from the spec
A following patch introduces EFI_TCG2_PROTOCOL.
Add the required TPMv2 headers to support it.
Signed-off-by: Ilias Apalodimas
---
changes since v2:
- Added description and pointers to TCG specs
- updated copyright info
include/tpm-v2.h | 77
1 file changed, 77 insertions(+)
diff --git a/include/tpm-v2.h b/include/tpm-v2.h
index f6c045d35480..c75cd5d8dfe8 100644
--- a/include/tpm-v2.h
+++ b/include/tpm-v2.h
@@ -1,6 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
+ * Defines APIs and structures that allow software to interact with a
+ * TPM2 device
+ *
+ * Copyright (c) 2020 Linaro
* Copyright (c) 2018 Bootlin
+ *
+ *
https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/
+ *
* Author: Miquel Raynal
*/
@@ -11,6 +18,74 @@
#define TPM2_DIGEST_LEN32
+#define TPM2_MAX_PCRS 32
+#define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8)
+#define TPM2_MAX_CAP_BUFFER 1024
+#define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /*
TPM2_CAP */ - \
+sizeof(u32)) / sizeof(struct
tpms_tagged_property))
+
+/*
+ * We deviate from this draft of the specification by increasing the value of
+ * TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2
+ * implementations that have enabled a larger than typical number of PCR
+ * banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included
+ * in a future revision of the specification.
+ */
+#define TPM2_NUM_PCR_BANKS 16
+
+/* Definition of (UINT32) TPM2_CAP Constants */
+#define TPM2_CAP_PCRS 0x0005U
+#define TPM2_CAP_TPM_PROPERTIES 0x0006U
+
+/* Definition of (UINT32) TPM2_PT Constants */
+#define PT_GROUP (u32)(0x0100)
+#define PT_FIXED (u32)(PT_GROUP * 1)
+#define TPM2_PT_MANUFACTURER(u32)(PT_FIXED + 5)
+#define TPM2_PT_PCR_COUNT (u32)(PT_FIXED + 18)
+#define TPM2_PT_MAX_COMMAND_SIZE(u32)(PT_FIXED + 30)
+#define TPM2_PT_MAX_RESPONSE_SIZE (u32)(PT_FIXED + 31)
+
+/* TPMS_TAGGED_PROPERTY Structure */
+struct tpms_tagged_property {
+ u32 property;
+ u32 value;
+} __packed;
+
+/* TPMS_PCR_SELECTION Structure */
+struct tpms_pcr_selection {
+ u16 hash;
+ u8 size_of_select;
+ u8 pcr_select[TPM2_PCR_SELECT_MAX];
+} __packed;
+
+/* TPML_PCR_SELECTION Structure */
+struct tpml_pcr_selection {
+ u32 count;
+ struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS];
+} __packed;
+
+/* TPML_TAGGED_TPM_PROPERTY Structure */
+struct tpml_tagged_tpm_property {
+ u32 count;
+ struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES];
+} __packed;
+
+/* TPMU_CAPABILITIES Union */
+union tpmu_capabilities {
+ /*
+* Non exhaustive. Only added the structs needed for our
+* current code
+*/
+ struct tpml_pcr_selection assigned_pcr;
+ struct tpml_tagged_tpm_property tpm_properties;
+} __packed;
+
+/* TPMS_CAPABILITY_DATA Structure */
+struct tpms_capability_data {
+ u32 capability;
+ union tpmu_capabilities data;
+} __packed;
+
/**
* TPM2 Structure Tags for command/response buffers.
*
@@ -123,11 +198,13 @@ enum tpm2_return_codes {
* TPM2 algorithms.
*/
enum tpm2_algorithms {
+ TPM2_ALG_SHA1 = 0x04,
TPM2_ALG_XOR= 0x0A,
TPM2_ALG_SHA256 = 0x0B,
TPM2_ALG_SHA384 = 0x0C,
TPM2_ALG_SHA512 = 0x0D,
TPM2_ALG_NULL = 0x10,
+ TPM2_ALG_SM3_256= 0x12,
};
/* NV index attributes */
--
2.29.2
[PATCH 2/2 v3] efi: Add basic EFI_TCG2_PROTOCOL support
Since U-boot EFI implementation is getting richer it makes sense to
add support for EFI_TCG2_PROTOCOL taking advantage of any hardware TPM
available on the device.
This is the initial implementation of the protocol which only adds
support for GetCapability(). It's limited in the newer and safer
TPMv2 devices.
Signed-off-by: Ilias Apalodimas
---
* changes since v2:
- added description about include/efi_tcg2.h
- switch bool to u8 for tpm_present_flag
- removed superfluous 'default n' from Kconfig
- use 'goto 'tag' when possible
* changes since v1:
- change return variable of platform_get_tpm2_device() when used
- since more headers were included in patch #2 use them in offset
calculations for all tpm commands
- change the size of the response buffer regardless of what
tpm2_get_capability() is doing
include/efi_loader.h | 2 +
include/efi_tcg2.h | 94 +++
lib/efi_loader/Kconfig | 7 +
lib/efi_loader/Makefile| 1 +
lib/efi_loader/efi_setup.c | 7 +
lib/efi_loader/efi_tcg2.c | 528 +
6 files changed, 639 insertions(+)
create mode 100644 include/efi_tcg2.h
create mode 100644 lib/efi_loader/efi_tcg2.c
diff --git a/include/efi_loader.h b/include/efi_loader.h
index f550ced56876..e5015d865ec9 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -405,6 +405,8 @@ efi_status_t efi_console_register(void);
efi_status_t efi_disk_register(void);
/* Called by efi_init_obj_list() to install EFI_RNG_PROTOCOL */
efi_status_t efi_rng_register(void);
+/* Called by efi_init_obj_list() to install EFI_TCG2_PROTOCOL */
+efi_status_t efi_tcg2_register(void);
/* Create handles and protocols for the partitions of a block device */
int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc,
const char *if_typename, int diskid,
diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h
new file mode 100644
index ..4214f767eaba
--- /dev/null
+++ b/include/efi_tcg2.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Defines data structures and APIs that allow an OS to interact with UEFI
+ * firmware to query information about the device
+ *
+ * Copyright (c) 2020, Linaro Limited
+ */
+
+#if !defined _EFI_TCG2_PROTOCOL_H_
+#define _EFI_TCG2_PROTOCOL_H_
+
+#include
+
+#define EFI_TCG2_PROTOCOL_GUID \
+ EFI_GUID(0x607f766c, 0x7455, 0x42be, 0x93, \
+0x0b, 0xe4, 0xd7, 0x6d, 0xb2, 0x72, 0x0f)
+
+/* TPMV2 only */
+#define TCG2_EVENT_LOG_FORMAT_TCG_2 0x0002
+
+/* SHA1, SHA256, SHA384, SHA512, TPM_ALG_SM3_256 */
+#define MAX_HASH_COUNT 5
+/* Algorithm Registry */
+#define EFI_TCG2_BOOT_HASH_ALG_SHA10x0001
+#define EFI_TCG2_BOOT_HASH_ALG_SHA256 0x0002
+#define EFI_TCG2_BOOT_HASH_ALG_SHA384 0x0004
+#define EFI_TCG2_BOOT_HASH_ALG_SHA512 0x0008
+#define EFI_TCG2_BOOT_HASH_ALG_SM3_256 0x0010
+
+typedef u32 efi_tcg_event_log_bitmap;
+typedef u32 efi_tcg_event_log_format;
+typedef u32 efi_tcg_event_algorithm_bitmap;
+
+struct efi_tcg2_version {
+ u8 major;
+ u8 minor;
+};
+
+struct efi_tcg2_event_header {
+ u32 header_size;
+ u16 header_version;
+ u32 pcr_index;
+ u32 event_type;
+} __packed;
+
+struct efi_tcg2_event {
+ u32 size;
+ struct efi_tcg2_event_header header;
+ u8 event[];
+} __packed;
+
+struct efi_tcg2_boot_service_capability {
+ u8 size;
+ struct efi_tcg2_version structure_version;
+ struct efi_tcg2_version protocol_version;
+ efi_tcg_event_algorithm_bitmap hash_algorithm_bitmap;
+ efi_tcg_event_log_bitmap supported_event_logs;
+ u8 tpm_present_flag;
+ u16 max_command_size;
+ u16 max_response_size;
+ u32 manufacturer_id;
+ u32 number_of_pcr_banks;
+ efi_tcg_event_algorithm_bitmap active_pcr_banks;
+};
+
+#define boot_service_capability_min \
+ sizeof(struct efi_tcg2_boot_service_capability) - \
+ offsetof(struct efi_tcg2_boot_service_capability, number_of_pcr_banks)
+
+struct efi_tcg2_protocol {
+ efi_status_t (EFIAPI * get_capability)(struct efi_tcg2_protocol *this,
+ struct
efi_tcg2_boot_service_capability *capability);
+ efi_status_t (EFIAPI * get_eventlog)(struct efi_tcg2_protocol *this,
+efi_tcg_event_log_format
log_format,
+u64 *event_log_location, u64
*event_log_last_entry,
+bool *event_log_truncated);
+ efi_status_t (EFIAPI * hash_log_extend_event)(struct efi_tcg2_protocol
*this,
+ u64 flags, u64
data_to_hash,
+ u64 data_to_hash_len,
+ struct efi_tcg2_event
*efi_tcg_event);
+ efi_status_t (EFIAPI * submit_command)(struct efi_tcg
Re: [PATCH] usb: xhci: fix event trb handling missed
Hi Ran,
On Tue, Nov 10, 2020 at 3:36 PM Ran Wang wrote:
>
> Hi Bin,
>
> On Tuesday, November 10, 2020 1:43 PM Bin Meng wrote:
> >
> > Hi Ran,
> >
> > On Tue, Nov 10, 2020 at 1:30 PM Bin Meng wrote:
> > >
> > > Hi Ran,
> > >
> > > On Tue, Sep 22, 2020 at 1:02 PM Ran Wang wrote:
> > > >
> > > > In functiion xhci_bulk_tx(), when buffer cross 64KB boundary, it
> > > > will
> > >
> > > typo: function
>
> Got it.
>
> > > > send request in more than 1 Transfer TRB by chaining them, but then
> > > > handle only 1 event TRB to mark request completed.
> > > >
> > > > However, on Layerscape platforms (LS1028A, LS1088A, etc), we observe
> > > > xhci controller will generated more than 1 event TRB sometimes, this
> > > > cause that
> > >
> > > I am not sure if it's fair to say this is Layerscape specific
> > > behavior. Based on the xHCI spec, the spec indicates 1 event trb
> > > should be generated when IOC/ISP flag is set to 1 or an error occurs.
> >
> > Ah, ISP flag is set if the pipe is from an IN endpoint. Currently we have:
> >
> > /* Only set interrupt on short packet for IN endpoints */
> > if (usb_pipein(pipe))
> > field |= TRB_ISP;
> >
> > Can you verify that if removing the above codes, and without your changes in
> > this patch, the original issue can be resolved on LS1028?
>
> Bingo, removing above codes can resolve my issue, too
Thank you for your testing.
>
> > > I will see if I can reproduce your issue on an x86 board.
> > >
> >
> > Note this patch does not apply on top of u-boot/master. Please rebase.
>
> Sure, I can rebase my patch, but I am nor sure my solution is still worth:
> xHCI says "The detection of a USB Short Packet (i.e. the actual number of
> bytes received was less than the expected number of bytes defined by the
> Transfer TRB) during a transfer does not necessarily generate an Event. "
>
Yes, that's what the spec says. So in your case, can you add some logs
to verify that there is a transfer event trb generated by the xHC and
the completion code is 13 (short packet)? You can add some debug
output in record_transfer_result().
> So does it mean above workaround you suggest would not violate spec, either
> (although current Linux kernel driver still set ISP for this case, but may
> have
> a more robust mechanism for event TRB handling)?
I need to do more testing to see if this is a LS1028 behavior or
generic xHCI behavior, ie: on an x86 board. Do you happen to know if
there is any errata document for LS1028 that is related to this?
>
>
> > > > function mishandle event TRB in next round call, then system hang
> > > > due to
> > > > BUG() checking.
> > > >
> > > > This patch adds a loop to make sure the event TRB for last Transfer
> > > > TRB has to be handled in time.
> > > >
> > > > Signed-off-by: Ran Wang
> > > > ---
> > > > drivers/usb/host/xhci-ring.c | 17 ++---
> > > > 1 file changed, 14 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/drivers/usb/host/xhci-ring.c
> > > > b/drivers/usb/host/xhci-ring.c index 092ed6e..d77e058 100644
> > > > --- a/drivers/usb/host/xhci-ring.c
> > > > +++ b/drivers/usb/host/xhci-ring.c
> > > > @@ -578,10 +578,13 @@ int xhci_bulk_tx(struct usb_device *udev,
> > unsigned long pipe,
> > > > int ret;
> > > > u32 trb_fields[4];
> > > > u64 val_64 = virt_to_phys(buffer);
> > > > + void *last_transfer_trb_addr;
> > > > + int available_length;
> > > >
> > > > debug("dev=%p, pipe=%lx, buffer=%p, length=%d\n",
> > > > udev, pipe, buffer, length);
> > > >
> > > > + available_length = length;
> > > > ep_index = usb_pipe_ep_index(pipe);
> > > > virt_dev = ctrl->devs[slot_id];
> > > >
> > > > @@ -701,7 +704,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned
> > long pipe,
> > > > trb_fields[2] = length_field;
> > > > trb_fields[3] = field | (TRB_NORMAL <<
> > > > TRB_TYPE_SHIFT);
> > > >
> > > > - queue_trb(ctrl, ring, (num_trbs > 1), trb_fields);
> > > > + last_transfer_trb_addr = queue_trb(ctrl, ring,
> > > > + (num_trbs > 1), trb_fields);
> > > >
> > > > --num_trbs;
> > > >
> > > > @@ -714,6 +717,7 @@ int xhci_bulk_tx(struct usb_device *udev,
> > > > unsigned long pipe,
> > > >
> > > > giveback_first_trb(udev, ep_index, start_cycle, start_trb);
> > > >
> > > > +again:
> > > > event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
> > > > if (!event) {
> > > > debug("XHCI bulk transfer timed out,
> > > > aborting...\n"); @@ -722,14 +726,21 @@ int xhci_bulk_tx(struct
> > usb_device *udev, unsigned long pipe,
> > > > udev->act_len = 0;
> > > > return -ETIMEDOUT;
> > > > }
> > > > - field = le32_to_cpu(event->trans_event.flags);
> > > >
> > > > + if ((void *)event->trans_event.buffer !=
> > > > + last_transfer_trb_addr) {
> > >
> > > This should be:
> > >
> > > i
Re: [RESEND,PATCH v2 1/1] riscv: Add timer_get_us() for tracing
Hi Pragnesh
> Hi Rick,
>
> >-Original Message-
> >From: Rick Chen
> >Sent: 09 November 2020 13:44
> >To: Pragnesh Patel
> >Cc: U-Boot Mailing List ; Atish Patra
> >; Bin Meng ; Paul Walmsley (
> >Sifive) ; Anup Patel ; Sagar
> >Kadam ; Simon Glass ; Sean
> >Anderson ; palmerdabb...@google.com; rick
> >; Alan Kao
> >Subject: Re: [RESEND,PATCH v2 1/1] riscv: Add timer_get_us() for tracing
> >
> >[External Email] Do not click links or attachments unless you recognize the
> >sender and know the content is safe
> >
> >> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
> >> Sent: Thursday, November 05, 2020 7:31 PM
> >> To: u-boot@lists.denx.de
> >> Cc: atish.pa...@wdc.com; palmerdabb...@google.com;
> >bmeng...@gmail.com;
> >> paul.walms...@sifive.com; anup.pa...@wdc.com; sagar.ka...@sifive.com;
> >> Rick Jian-Zhi Chen(陳建志); Pragnesh Patel; Sean Anderson; Claudiu
> >> Beznea; Simon Glass
> >> Subject: [RESEND,PATCH v2 1/1] riscv: Add timer_get_us() for tracing
> >>
> >> Add timer_get_us() which is useful for tracing.
> >> For S-mode U-Boot, CSR_TIMEH and CSR_TIME will provide a timer ticks
> >> and For M-mode U-Boot, mtime register will provide the same.
> >>
> >> Signed-off-by: Pragnesh Patel
> >> ---
> >> drivers/timer/andes_plmt_timer.c | 16 +++-
> >> drivers/timer/riscv_timer.c| 14 +-
> >> drivers/timer/sifive_clint_timer.c | 16 +++-
> >> 3 files changed, 43 insertions(+), 3 deletions(-)
> >>
> >
> >I verify it fail as below:
> >
> >U-Boot 2020.10-20532-g0910882 (Nov 09 2020 - 15:51:31 +0800)
> >
> >DRAM: 1 GiB
> >trace: enabled
> >
> >Do you have any suggestion ?
>
> On which platform ?
>
> Do you follow this
> https://patchwork.ozlabs.org/project/uboot/cover/20201105113032.26234-1-pragnesh.pa...@sifive.com/
> ?
>
I verify on AE350 platform with the following configurations:
CONFIG_TRACE=y
CONFIG_TRACE_BUFFER_SIZE=0x0100
CONFIG_TRACE_CALL_DEPTH_LIMIT=15
CONFIG_CMD_TRACE=y
make FTRACE=1 ae350_rv64_defconfig
make FTRACE=1
After dig in and I found the root cause.
You can't use gd->arch.plic to record plmt base.
It conflicts with andes plic.
Thanks,
Rick
> >
> >Thanks,
> >Rick
> >
> >
> >> diff --git a/drivers/timer/andes_plmt_timer.c
> >> b/drivers/timer/andes_plmt_timer.c
> >> index cec86718c7..9d663e036e 100644
> >> --- a/drivers/timer/andes_plmt_timer.c
> >> +++ b/drivers/timer/andes_plmt_timer.c
> >> @@ -13,11 +13,12 @@
> >> #include
> >> #include
> >> #include
> >> +#include
> >>
> >> /* mtime register */
> >> #define MTIME_REG(base)((ulong)(base))
> >>
> >> -static u64 andes_plmt_get_count(struct udevice *dev)
> >> +static u64 notrace andes_plmt_get_count(struct udevice *dev)
> >> {
> >> return readq((void __iomem *)MTIME_REG(dev->priv)); } @@
> >> -26,12 +27,25 @@ static const struct timer_ops andes_plmt_ops = {
> >> .get_count = andes_plmt_get_count, };
> >>
> >> +#if CONFIG_IS_ENABLED(RISCV_MMODE)
> >> +unsigned long notrace timer_get_us(void) {
> >> + u64 ticks;
> >> +
> >> + /* FIXME: gd->arch.plic should contain valid base address */
> >> + ticks = andes_plmt_get_count(gd->arch.plic);
>
> Here andes_plmt_get_count() should be replaced with MTIME_REG() macro. Will
> update in v3.
>
> >> + do_div(ticks, CONFIG_SYS_HZ);
> >> + return ticks;
> >> +}
> >> +#endif
> >> +
> >> static int andes_plmt_probe(struct udevice *dev) {
> >> dev->priv = dev_read_addr_ptr(dev);
> >> if (!dev->priv)
> >> return -EINVAL;
> >>
> >> + gd->arch.plic = dev->priv;
> >> return timer_timebase_fallback(dev); }
> >>
> >> diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
> >> index 21ae184057..7fa8773da3 100644
> >> --- a/drivers/timer/riscv_timer.c
> >> +++ b/drivers/timer/riscv_timer.c
> >> @@ -15,8 +15,9 @@
> >> #include
> >> #include
> >> #include
> >> +#include
> >>
> >> -static u64 riscv_timer_get_count(struct udevice *dev)
> >> +static u64 notrace riscv_timer_get_count(struct udevice *dev)
> >> {
> >> __maybe_unused u32 hi, lo;
> >>
> >> @@ -31,6 +32,17 @@ static u64 riscv_timer_get_count(struct udevice *dev)
> >> return ((u64)hi << 32) | lo;
> >> }
> >>
> >> +#if CONFIG_IS_ENABLED(RISCV_SMODE)
> >> +unsigned long notrace timer_get_us(void) {
> >> + u64 ticks;
> >> +
> >> + ticks = riscv_timer_get_count(NULL);
> >> + do_div(ticks, CONFIG_SYS_HZ);
> >> + return ticks;
> >> +}
> >> +#endif
> >> +
> >> static int riscv_timer_probe(struct udevice *dev) {
> >> struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> >> diff --git a/drivers/timer/sifive_clint_timer.c
> >> b/drivers/timer/sifive_clint_timer.c
> >> index 00ce0f08d6..166655e99d 100644
> >> --- a/drivers/timer/sifive_clint_timer.c
> >> +++ b/drivers/timer/sifive_clint_timer.c
> >> @@ -10,11 +10,12 @@
> >> #include
> >> #include
> >> #include
> >> +#include
> >>
>
Re: [PATCH] rockchip: rockpro64: fix boot from SPI flash on spi1
On 2020/11/8 下午10:00, Hugh Cole-Baker wrote:
Commit c4cea2bbf995 ("rockchip: Enable building a SPI ROM image on bob")
added an alias spi1 referring to spi@ff1d, however there was already
an alias spi0 referring to the same node in rockpro64's u-boot.dtsi, and
having both aliases present broke booting from SPI flash for this board.
Remove the spi0 alias, set the default bus for SPI flash to 1, and
enable support for numbered aliases in SPL so that it uses the same bus
numbering as U-Boot proper. This fixes booting from U-Boot in SPI flash
on the rockpro64 board.
Signed-off-by: Hugh Cole-Baker
Suggested-by: Simon Glass
Fixes: c4cea2bbf995 ("rockchip: Enable building a SPI ROM image on bob")
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 4
configs/rockpro64-rk3399_defconfig| 2 ++
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
index cb8991aa253..6317b47e41a 100644
--- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
@@ -6,10 +6,6 @@
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"
/ {
- aliases {
- spi0 = &spi1;
- };
-
chosen {
u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdmmc,
&sdhci;
};
diff --git a/configs/rockpro64-rk3399_defconfig
b/configs/rockpro64-rk3399_defconfig
index bfba8704072..575b7a20d50 100644
--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig
@@ -32,6 +32,7 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent
assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_DM_KEYBOARD=y
@@ -41,6 +42,7 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
RE: [PATCH] usb: xhci: fix event trb handling missed
Hi Bin,
On Tuesday, November 10, 2020 1:43 PM Bin Meng wrote:
>
> Hi Ran,
>
> On Tue, Nov 10, 2020 at 1:30 PM Bin Meng wrote:
> >
> > Hi Ran,
> >
> > On Tue, Sep 22, 2020 at 1:02 PM Ran Wang wrote:
> > >
> > > In functiion xhci_bulk_tx(), when buffer cross 64KB boundary, it
> > > will
> >
> > typo: function
Got it.
> > > send request in more than 1 Transfer TRB by chaining them, but then
> > > handle only 1 event TRB to mark request completed.
> > >
> > > However, on Layerscape platforms (LS1028A, LS1088A, etc), we observe
> > > xhci controller will generated more than 1 event TRB sometimes, this
> > > cause that
> >
> > I am not sure if it's fair to say this is Layerscape specific
> > behavior. Based on the xHCI spec, the spec indicates 1 event trb
> > should be generated when IOC/ISP flag is set to 1 or an error occurs.
>
> Ah, ISP flag is set if the pipe is from an IN endpoint. Currently we have:
>
> /* Only set interrupt on short packet for IN endpoints */
> if (usb_pipein(pipe))
> field |= TRB_ISP;
>
> Can you verify that if removing the above codes, and without your changes in
> this patch, the original issue can be resolved on LS1028?
Bingo, removing above codes can resolve my issue, too
> > I will see if I can reproduce your issue on an x86 board.
> >
>
> Note this patch does not apply on top of u-boot/master. Please rebase.
Sure, I can rebase my patch, but I am nor sure my solution is still worth:
xHCI says "The detection of a USB Short Packet (i.e. the actual number of
bytes received was less than the expected number of bytes defined by the
Transfer TRB) during a transfer does not necessarily generate an Event. "
So does it mean above workaround you suggest would not violate spec, either
(although current Linux kernel driver still set ISP for this case, but may have
a more robust mechanism for event TRB handling)?
> > > function mishandle event TRB in next round call, then system hang
> > > due to
> > > BUG() checking.
> > >
> > > This patch adds a loop to make sure the event TRB for last Transfer
> > > TRB has to be handled in time.
> > >
> > > Signed-off-by: Ran Wang
> > > ---
> > > drivers/usb/host/xhci-ring.c | 17 ++---
> > > 1 file changed, 14 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/usb/host/xhci-ring.c
> > > b/drivers/usb/host/xhci-ring.c index 092ed6e..d77e058 100644
> > > --- a/drivers/usb/host/xhci-ring.c
> > > +++ b/drivers/usb/host/xhci-ring.c
> > > @@ -578,10 +578,13 @@ int xhci_bulk_tx(struct usb_device *udev,
> unsigned long pipe,
> > > int ret;
> > > u32 trb_fields[4];
> > > u64 val_64 = virt_to_phys(buffer);
> > > + void *last_transfer_trb_addr;
> > > + int available_length;
> > >
> > > debug("dev=%p, pipe=%lx, buffer=%p, length=%d\n",
> > > udev, pipe, buffer, length);
> > >
> > > + available_length = length;
> > > ep_index = usb_pipe_ep_index(pipe);
> > > virt_dev = ctrl->devs[slot_id];
> > >
> > > @@ -701,7 +704,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned
> long pipe,
> > > trb_fields[2] = length_field;
> > > trb_fields[3] = field | (TRB_NORMAL <<
> > > TRB_TYPE_SHIFT);
> > >
> > > - queue_trb(ctrl, ring, (num_trbs > 1), trb_fields);
> > > + last_transfer_trb_addr = queue_trb(ctrl, ring,
> > > + (num_trbs > 1), trb_fields);
> > >
> > > --num_trbs;
> > >
> > > @@ -714,6 +717,7 @@ int xhci_bulk_tx(struct usb_device *udev,
> > > unsigned long pipe,
> > >
> > > giveback_first_trb(udev, ep_index, start_cycle, start_trb);
> > >
> > > +again:
> > > event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
> > > if (!event) {
> > > debug("XHCI bulk transfer timed out,
> > > aborting...\n"); @@ -722,14 +726,21 @@ int xhci_bulk_tx(struct
> usb_device *udev, unsigned long pipe,
> > > udev->act_len = 0;
> > > return -ETIMEDOUT;
> > > }
> > > - field = le32_to_cpu(event->trans_event.flags);
> > >
> > > + if ((void *)event->trans_event.buffer !=
> > > + last_transfer_trb_addr) {
> >
> > This should be:
> >
> > if ((void *)le64_to_cpu(event->trans_event.buffer) !=
> > last_transfer_trb_addr)
Got it, will update this in next version (if you think my solution is still
acceptable for this issue).
Thanks & regards,
Ran
> > > + available_length -=
> > > +
> (int)EVENT_TRB_LEN(le32_to_cpu(event->trans_event.transfer_len));
> > > + xhci_acknowledge_event(ctrl);
> > > + goto again;
> > > + }
> > > +
> > > + field = le32_to_cpu(event->trans_event.flags);
> > > BUG_ON(TRB_TO_SLOT_ID(field) != slot_id);
> > > BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
> > > BUG_ON(*(void
> **)(uintptr_t)le64_to_cpu(event->trans_event.buffer) -
> > > buffer > (size_t)length);
> > >
> > > -
Re: [PATCH] rockchip: Move Bob specific bits to it's specific u-boot.dtsi
Hi Peter,
On 2020/11/9 上午7:02, Peter Robinson wrote:
Move the bits that are device specific to the -u-boot.dtsi as the
bits may be different on other devices and hence breaks SPI on
those devices such as the Pinebook Pro.
Signed-off-by: Peter Robinson
Fixes: c4cea2bbf995 ("rockchip: Enable building a SPI ROM image on bob")
Cc: Simon Glass
---
arch/arm/dts/rk3399-gru-u-boot.dtsi | 30 +
arch/arm/dts/rk3399-u-boot.dtsi | 25
2 files changed, 30 insertions(+), 25 deletions(-)
diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi
b/arch/arm/dts/rk3399-gru-u-boot.dtsi
index 390ac2bb5a..5e95cacfea 100644
--- a/arch/arm/dts/rk3399-gru-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi
@@ -5,6 +5,36 @@
#include "rk3399-u-boot.dtsi"
+/ {
+ aliases {
+ spi1 = &spi1;
+ };
+};
Does this still need to remove from common code after your another patch
applied? It look reasonable and
not likely to break others.
https://patchwork.ozlabs.org/project/uboot/patch/20201108140023.32501-1-sigma...@gmail.com/
+
+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+&binman {
+ rom {
+ filename = "u-boot.rom";
+ size = <0x40>;
+ pad-byte = <0xff>;
+
+ mkimage {
+ args = "-n rk3399 -T rkspi";
+ u-boot-spl {
+ };
+ };
+ u-boot-img {
+ offset = <0x4>;
+ };
+ u-boot {
+ offset = <0x30>;
+ };
+ fdtmap {
+ };
+ };
+};
+#endif
What's the image space mapping for Pinebook Pro do you using?
I think there should be another binman config if this is not common .
Thanks,
- Kever
+
&spi_flash {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index ecd230c720..26b0a34e64 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -11,7 +11,6 @@
mmc0 = &sdhci;
mmc1 = &sdmmc;
pci0 = &pcie0;
- spi1 = &spi1;
};
cic: syscon@ff62 {
@@ -60,30 +59,6 @@
};
-#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
-&binman {
- rom {
- filename = "u-boot.rom";
- size = <0x40>;
- pad-byte = <0xff>;
-
- mkimage {
- args = "-n rk3399 -T rkspi";
- u-boot-spl {
- };
- };
- u-boot-img {
- offset = <0x4>;
- };
- u-boot {
- offset = <0x30>;
- };
- fdtmap {
- };
- };
-};
-#endif
-
&cru {
u-boot,dm-pre-reloc;
};
[v1 5/5] configs: socfpga: Add defconfig for Agilex and Diamond Mesa with VAB support
Booting Agilex and Diamond Mesa with Vendor Authorized Boot.
Signed-off-by: Siew Chin Lim
---
configs/{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig} | 3 ++-
configs/{socfpga_dm_atf_defconfig => socfpga_dm_vab_defconfig} | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
copy configs/{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig}
(96%)
copy configs/{socfpga_dm_atf_defconfig => socfpga_dm_vab_defconfig} (96%)
diff --git a/configs/socfpga_agilex_atf_defconfig
b/configs/socfpga_agilex_vab_defconfig
similarity index 96%
copy from configs/socfpga_agilex_atf_defconfig
copy to configs/socfpga_agilex_vab_defconfig
index ad87a8098f..d437f49ce0 100644
--- a/configs/socfpga_agilex_atf_defconfig
+++ b/configs/socfpga_agilex_vab_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-CONFIG_ARM_SMCCC=y
CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x20
@@ -8,6 +7,7 @@ CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
CONFIG_DM_GPIO=y
CONFIG_NR_DRAM_BANKS=2
+CONFIG_SECURE_VAB_AUTH=y
CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
CONFIG_IDENT_STRING="socfpga_agilex"
CONFIG_SPL_FS_FAT=y
@@ -15,6 +15,7 @@ CONFIG_SPL_TEXT_BASE=0xFFE0
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200
+# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
diff --git a/configs/socfpga_dm_atf_defconfig b/configs/socfpga_dm_vab_defconfig
similarity index 96%
copy from configs/socfpga_dm_atf_defconfig
copy to configs/socfpga_dm_vab_defconfig
index 975f20c752..97dc269057 100644
--- a/configs/socfpga_dm_atf_defconfig
+++ b/configs/socfpga_dm_vab_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-CONFIG_ARM_SMCCC=y
CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_TEXT_BASE=0x20
@@ -8,6 +7,7 @@ CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x200
CONFIG_DM_GPIO=y
CONFIG_NR_DRAM_BANKS=2
+CONFIG_SECURE_VAB_AUTH=y
CONFIG_TARGET_SOCFPGA_DM_SOCDK=y
CONFIG_IDENT_STRING="socfpga_dm"
CONFIG_SPL_FS_FAT=y
@@ -15,6 +15,7 @@ CONFIG_SPL_TEXT_BASE=0xFFE0
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200
+# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
--
2.13.0
[v1 4/5] configs: socfpga: soc64: Remove 'run linux_qspi_enable' from bootcommand
Remove 'run linux_qspi_enable' from bootcommand. When using FIT for OS boot, 'run linux_qspi_enable' will be called 'board_prep_linux' function. Signed-off-by: Siew Chin Lim --- include/configs/socfpga_soc64_common.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 194df5940d..911c3a91fd 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -86,8 +86,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #ifdef CONFIG_FIT #define CONFIG_BOOTFILE "kernel.itb" -#define CONFIG_BOOTCOMMAND "run fatscript; run mmcfitload;run linux_qspi_enable;" \ - "run mmcfitboot" +#define CONFIG_BOOTCOMMAND "run fatscript; run mmcfitload; run mmcfitboot" #else #define CONFIG_BOOTFILE "Image" #define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \ -- 2.13.0
[v1 3/5] arm: socfpga: dts: soc64: Update filename in binman node of FIT image with VAB support
FIT image of Vendor Authentication Coot (VAB) contains signed images.
Signed-off-by: Siew Chin Lim
---
arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
index 2d4d56a6df..a23b45575a 100644
--- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
@@ -117,4 +117,26 @@
};
};
+#if defined(CONFIG_SECURE_VAB_AUTH)
+&uboot_blob {
+ filename = "signed-u-boot-nodtb.bin";
+};
+
+&atf_blob {
+ filename = "signed-bl31.bin";
+};
+
+&uboot_fdt_blob {
+ filename = "signed-u-boot.dtb";
+};
+
+&kernel_blob {
+ filename = "signed-Image";
+};
+
+&kernel_fdt_blob {
+ filename = "signed-linux.dtb";
+};
+#endif
+
#endif
--
2.13.0
[v1 1/5] arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
Vendor Authorized Boot is a security feature for authenticating
the images such as U-Boot, ARM trusted Firmware, Linux kernel,
device tree blob and etc loaded from FIT. After those images are
loaded from FIT, the VAB certificate and signature block appended
at the end of each image are sent to Secure Device Manager (SDM)
for authentication. U-Boot will validate the SHA384 of the image
against the SHA384 hash stored in the VAB certificate before
sending the image to SDM for authentication.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Kconfig| 15 ++
arch/arm/mach-socfpga/Makefile | 2 +
arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 1 +
arch/arm/mach-socfpga/include/mach/secure_vab.h | 63
arch/arm/mach-socfpga/secure_vab.c | 188 +++
common/Kconfig.boot | 2 +-
6 files changed, 270 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-socfpga/include/mach/secure_vab.h
create mode 100644 arch/arm/mach-socfpga/secure_vab.c
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 5dee193b31..1dfe08ec86 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -6,6 +6,21 @@ config ERR_PTR_OFFSET
config NR_DRAM_BANKS
default 1
+config SECURE_VAB_AUTH
+ bool "Enable boot image authentication with Secure Device Manager"
+ depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_DM
+ select FIT_IMAGE_POST_PROCESS
+ select SHA512_ALGO
+ select SHA384
+ select SPL_FIT_IMAGE_POST_PROCESS
+ help
+All images loaded from FIT will be authenticated by Secure Device
+Manager.
+
+config SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE
+ bool "Allow non-FIT VAB signed images"
+ depends on SECURE_VAB_AUTH
+
config SPL_SIZE_LIMIT
default 0x1 if TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b88bb515d0..6ec4fcff73 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -48,6 +48,7 @@ obj-y += mailbox_s10.o
obj-y += misc_s10.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
+obj-$(CONFIG_SECURE_VAB_AUTH) += secure_vab.o
obj-y += system_manager_soc64.o
obj-y += timer_s10.o
obj-y += wrap_handoff_soc64.o
@@ -61,6 +62,7 @@ obj-y += mailbox_s10.o
obj-y += misc_s10.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
+obj-$(CONFIG_SECURE_VAB_AUTH) += secure_vab.o
obj-y += system_manager_soc64.o
obj-y += timer_s10.o
obj-y += wrap_handoff_soc64.o
diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
index 4d783119ea..fbaf11597e 100644
--- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -118,6 +118,7 @@ enum ALT_SDM_MBOX_RESP_CODE {
#define MBOX_RECONFIG_MSEL 7
#define MBOX_RECONFIG_DATA 8
#define MBOX_RECONFIG_STATUS 9
+#define MBOX_VAB_SRC_CERT 11
#define MBOX_QSPI_OPEN 50
#define MBOX_QSPI_CLOSE51
#define MBOX_QSPI_DIRECT 59
diff --git a/arch/arm/mach-socfpga/include/mach/secure_vab.h
b/arch/arm/mach-socfpga/include/mach/secure_vab.h
new file mode 100644
index 00..42588588e8
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/secure_vab.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#ifndef_SECURE_VAB_H_
+#define_SECURE_VAB_H_
+
+#include
+#include
+#include
+
+#define VAB_DATA_SZ64
+
+#define SDM_CERT_MAGIC_NUM 0x25D04E7F
+#define FCS_HPS_VAB_MAGIC_NUM 0xD0564142
+
+#define MAX_CERT_SIZE (SZ_4K)
+
+/*
+ * struct fcs_hps_vab_certificate_data
+ * @vab_cert_magic_num: VAB Certificate Magic Word (0xD0564142)
+ * @flags: TBD
+ * @fcs_data: Data words being certificate signed.
+ * @cert_sign_keychain: Certificate Signing Keychain
+ */
+struct fcs_hps_vab_certificate_data {
+ u32 vab_cert_magic_num; /* offset 0x10 */
+ u32 flags;
+ u8 rsvd0_1[8];
+ u8 fcs_sha384[SHA384_SUM_LEN]; /* offset 0x20 */
+};
+
+/*
+ * struct fcs_hps_vab_certificate_header
+ * @cert_magic_num: Certificate Magic Word (0x25D04E7F)
+ * @cert_data_sz: size of this certificate header (0x80)
+ * Includes magic number all the way to the certificate
+ * signing keychain (excludes cert. signing keychain)
+ * @cert_ver: Certificate Version
+ * @cert_type: Certificate Type
+ * @data: VAB HPS Image Certificate data
+ */
+struct fcs_hps_vab_certificate_header {
+ u32 cert_magic_num; /* offset 0 */
+ u32 cert_data_sz;
+ u32 cert_ver;
+ u32 cert_type;
+ struct fcs_hps_vab_certificate_data d; /* offset 0x10 */
+ /* keychain starts at offset 0x50 */
+};
+
+#define VAB_CERT_HEADER
[v1 2/5] arm: socfpga: cmd: Support 'vab' command
Support 'vab' command to perform vendor authentication.
Command format: vab addr len
Authorize 'len' bytes starting at 'addr' via vendor public key
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 2 ++
arch/arm/mach-socfpga/vab.c| 37 +
2 files changed, 39 insertions(+)
create mode 100644 arch/arm/mach-socfpga/vab.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 6ec4fcff73..697367bfdc 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -51,6 +51,7 @@ obj-y += reset_manager_s10.o
obj-$(CONFIG_SECURE_VAB_AUTH) += secure_vab.o
obj-y += system_manager_soc64.o
obj-y += timer_s10.o
+obj-$(CONFIG_SECURE_VAB_AUTH) += vab.o
obj-y += wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
endif
@@ -65,6 +66,7 @@ obj-y += reset_manager_s10.o
obj-$(CONFIG_SECURE_VAB_AUTH) += secure_vab.o
obj-y += system_manager_soc64.o
obj-y += timer_s10.o
+obj-$(CONFIG_SECURE_VAB_AUTH) += vab.o
obj-y += wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
endif
diff --git a/arch/arm/mach-socfpga/vab.c b/arch/arm/mach-socfpga/vab.c
new file mode 100644
index 00..4c592a87cf
--- /dev/null
+++ b/arch/arm/mach-socfpga/vab.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+static int do_vab(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ unsigned long addr, len;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+ len = simple_strtoul(argv[2], NULL, 16);
+
+ if (socfpga_vendor_authentication((void *)&addr, (size_t *)&len) == 0)
+ printf("%s 0x%016lx (%ld bytes)\n",
+ "Image Authentication passed at address", addr, len);
+ else
+ return CMD_RET_FAILURE;
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ vab,3, 2, do_vab,
+ "perform vendor authorization",
+ "addr len - authorize 'len' bytes starting at\n"
+ " 'addr' via vendor public key"
+);
--
2.13.0
[v1 0/5] Add Vendor Authorized Boot (VAB) support
This patchset add Vendor Authorized Boot (VAB) support for
Intel Agilex and Diamond Mesa SoC devices.
Vendor Authorized Boot is a security feature for authenticating
the images such as U-Boot, ARM trusted Firmware, Linux kernel,
device tree blob and etc loaded from FIT. After those images are
loaded from FIT, the VAB certificate and signature block appended
at the end of each image are sent to Secure Device Manager (SDM)
for authentication. U-Boot will validate the SHA384 of the image
against the SHA384 hash stored in the VAB certificate before
sending the image to SDM for authentication.
These patchsets have dependency on:
Enable ARM Trusted Firmware for U-Boot
https://patchwork.ozlabs.org/project/uboot/cover/20201015122955.10259-1-elly.siew.chin@intel.com/
Add Intel Diamond Mesa SoC support
https://patchwork.ozlabs.org/project/uboot/cover/20201110064439.9683-1-elly.siew.chin@intel.com/
Siew Chin Lim (5):
arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
arm: socfpga: cmd: Support 'vab' command
arm: socfpga: dts: soc64: Update filename in binman node of FIT image
with VAB support
configs: socfpga: soc64: Remove 'run linux_qspi_enable' from
bootcommand
configs: socfpga: Add defconfig for Agilex and Diamond Mesa with VAB
support
arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 22 +++
arch/arm/mach-socfpga/Kconfig | 15 ++
arch/arm/mach-socfpga/Makefile | 4 +
arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 1 +
arch/arm/mach-socfpga/include/mach/secure_vab.h| 63 +++
arch/arm/mach-socfpga/secure_vab.c | 188 +
arch/arm/mach-socfpga/vab.c| 37
common/Kconfig.boot| 2 +-
..._atf_defconfig => socfpga_agilex_vab_defconfig} | 3 +-
...a_dm_atf_defconfig => socfpga_dm_vab_defconfig} | 3 +-
include/configs/socfpga_soc64_common.h | 3 +-
11 files changed, 336 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/mach-socfpga/include/mach/secure_vab.h
create mode 100644 arch/arm/mach-socfpga/secure_vab.c
create mode 100644 arch/arm/mach-socfpga/vab.c
copy configs/{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig}
(96%)
copy configs/{socfpga_dm_atf_defconfig => socfpga_dm_vab_defconfig} (96%)
--
2.13.0
[RESEND v2 20/22] arm: dts: dm: Add base dtsi and devkit dts for Diamond Mesa
Add device tree for Diamond Mesa.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_dm-u-boot.dtsi | 102 +
arch/arm/dts/socfpga_dm.dtsi | 640 ++
arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi | 50 +++
arch/arm/dts/socfpga_dm_socdk.dts | 144 +++
5 files changed, 937 insertions(+)
create mode 100644 arch/arm/dts/socfpga_dm-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_dm.dtsi
create mode 100644 arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_dm_socdk.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5308713df7..0d9384f77b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -376,6 +376,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
\
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
socfpga_cyclone5_vining_fpga.dtb\
+ socfpga_dm_socdk.dtb\
socfpga_stratix10_socdk.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
diff --git a/arch/arm/dts/socfpga_dm-u-boot.dtsi
b/arch/arm/dts/socfpga_dm-u-boot.dtsi
new file mode 100644
index 00..c8638a0840
--- /dev/null
+++ b/arch/arm/dts/socfpga_dm-u-boot.dtsi
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#include "socfpga_soc64_fit-u-boot.dtsi"
+
+/{
+ memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ auto-size;
+ u-boot,dm-pre-reloc;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+
+ ccu: cache-controller@f700 {
+ compatible = "arteris,ncore-ccu";
+ reg = <0xf700 0x100900>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
+&clkmgr {
+ u-boot,dm-pre-reloc;
+};
+
+&gmac1 {
+ altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+};
+
+&gmac2 {
+ altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
+};
+
+&i2c0 {
+ reset-names = "i2c";
+};
+
+&i2c1 {
+ reset-names = "i2c";
+};
+
+&i2c2 {
+ reset-names = "i2c";
+};
+
+&i2c3 {
+ reset-names = "i2c";
+};
+
+&memclkmgr {
+ u-boot,dm-pre-reloc;
+};
+
+&mmc {
+ resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+};
+
+&rst {
+ compatible = "altr,rst-mgr";
+ altr,modrst-offset = <0x20>;
+ u-boot,dm-pre-reloc;
+};
+
+&sdr {
+ compatible = "intel,sdr-ctl-dm";
+ resets = <&rst DDRSCH_RESET>;
+ clocks = <&memclkmgr>;
+ clock-names = "mem_clk";
+ u-boot,dm-pre-reloc;
+};
+
+&sysmgr {
+ compatible = "altr,sys-mgr", "syscon";
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&watchdog0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_dm.dtsi b/arch/arm/dts/socfpga_dm.dtsi
new file mode 100644
index 00..49de6f4a5c
--- /dev/null
+++ b/arch/arm/dts/socfpga_dm.dtsi
@@ -0,0 +1,640 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020, Intel Corporation
+ */
+
+/dts-v1/;
+#include
+#include
+#include
+
+/ {
+ compatible = "intel,socfpga-dm";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ service_reserved: svcbuffer@0 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x0 0x0 0x100>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x1>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x2>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x3>;
+
[RESEND v2 22/22] arm: socfpga: dm: Enable Intel Diamond Mesa build
Add defconfig for Diamond Mesa to support both legacy boot flow and ATF boot flow. Legacy boot: SPL -> U-Boot proper -> OS (Linux) ATF boot flow: SPL -> ATF(BL31) -> U-Boot proper -> OS (Linux) Signed-off-by: Siew Chin Lim --- arch/arm/mach-socfpga/Kconfig| 19 ++ arch/arm/mach-socfpga/Makefile | 18 ++ configs/socfpga_dm_atf_defconfig | 76 configs/socfpga_dm_defconfig | 69 4 files changed, 182 insertions(+) create mode 100644 configs/socfpga_dm_atf_defconfig create mode 100644 configs/socfpga_dm_defconfig diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 4d061a9d0d..5dee193b31 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -66,6 +66,22 @@ config TARGET_SOCFPGA_CYCLONE5 bool select TARGET_SOCFPGA_GEN5 +config TARGET_SOCFPGA_DM + bool + select TARGET_SOCFPGA_SOC64 + select ARMV8_MULTIENTRY + select ARMV8_SET_SMPEN + select CLK + select FPGA_INTEL_SDM_MAILBOX + select NCORE_CACHE + select SPL_ALTERA_SDRAM + select SPL_CLK if SPL + select BINMAN + +config TARGET_SOCFPGA_DM_SOCDK + bool "Intel SOCFPGA SoCDK (Diamond Mesa)" + select TARGET_SOCFPGA_DM + config TARGET_SOCFPGA_GEN5 bool select SPL_ALTERA_SDRAM @@ -165,6 +181,7 @@ config SYS_BOARD default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 + default "dm-socdk" if TARGET_SOCFPGA_DM_SOCDK default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO @@ -179,6 +196,7 @@ config SYS_BOARD config SYS_VENDOR default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK + default "intel" if TARGET_SOCFPGA_DM_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK @@ -203,6 +221,7 @@ config SYS_CONFIG_NAME default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 + default "socfpga_dm_socdk" if TARGET_SOCFPGA_DM_SOCDK default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 57dc1e730d..b88bb515d0 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -54,6 +54,19 @@ obj-y+= wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o endif +ifdef CONFIG_TARGET_SOCFPGA_DM +obj-y += clock_manager_dm.o +obj-y += lowlevel_init_soc64.o +obj-y += mailbox_s10.o +obj-y += misc_s10.o +obj-y += mmu-arm64_s10.o +obj-y += reset_manager_s10.o +obj-y += system_manager_soc64.o +obj-y += timer_s10.o +obj-y += wrap_handoff_soc64.o +obj-y += wrap_pll_config_soc64.o +endif + ifdef CONFIG_SPL_BUILD ifdef CONFIG_TARGET_SOCFPGA_GEN5 obj-y += spl_gen5.o @@ -75,6 +88,11 @@ obj-y+= firewall.o obj-y += spl_agilex.o obj-y += spl_soc64.o endif +ifdef CONFIG_TARGET_SOCFPGA_DM +obj-y += firewall.o +obj-y += spl_dm.o +obj-y += spl_soc64.o +endif else obj-$(CONFIG_SPL_ATF) += smc_api.o endif diff --git a/configs/socfpga_dm_atf_defconfig b/configs/socfpga_dm_atf_defconfig new file mode 100644 index 00..975f20c752 --- /dev/null +++ b/configs/socfpga_dm_atf_defconfig @@ -0,0 +1,76 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x20 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x200 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_SOCFPGA_DM_SOCDK=y +CONFIG_IDENT_STRING="socfpga_dm" +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_TEXT_BASE=0xFFE0 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200 +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon" +CONFIG_SPL_CACHE=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x0200 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_DM # " +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_GPIO is not set +# CONFIG_CMD_I2C is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_MTD is not set +CONFIG_CMD_SPI=y +# CONFIG_CMD_USB is not set +# CONFIG_CMD_DHCP is not set +# CONFIG_CMD_MII is not set +# CONFIG_CMD_PING is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONF
[RESEND v2 05/22] arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c
Rename to common file name to used by all SOC64 devices.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile| 4 ++--
.../mach-socfpga/{wrap_pll_config_s10.c => wrap_pll_config_soc64.c} | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
rename arch/arm/mach-socfpga/{wrap_pll_config_s10.c =>
wrap_pll_config_soc64.c} (96%)
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 0b05283a7a..fc3b809afd 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -37,7 +37,7 @@ obj-y += reset_manager_s10.o
obj-y += system_manager_s10.o
obj-y += timer_s10.o
obj-y += wrap_pinmux_config_s10.o
-obj-y += wrap_pll_config_s10.o
+obj-y += wrap_pll_config_soc64.o
endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX
@@ -50,7 +50,7 @@ obj-y += reset_manager_s10.o
obj-y += system_manager_s10.o
obj-y += timer_s10.o
obj-y += wrap_pinmux_config_s10.o
-obj-y += wrap_pll_config_s10.o
+obj-y += wrap_pll_config_soc64.o
endif
ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c
similarity index 96%
rename from arch/arm/mach-socfpga/wrap_pll_config_s10.c
rename to arch/arm/mach-socfpga/wrap_pll_config_soc64.c
index 6a0d6b5ead..a3087cd0eb 100644
--- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation
+ * Copyright (C) 2016-2020 Intel Corporation
*
*/
--
2.13.0
[RESEND v2 21/22] configs: dm: Add Diamond Mesa CONFIGs
Add CONFIGs for Diamond Mesa.
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_dm_socdk.h | 46 ++
1 file changed, 46 insertions(+)
create mode 100644 include/configs/socfpga_dm_socdk.h
diff --git a/include/configs/socfpga_dm_socdk.h
b/include/configs/socfpga_dm_socdk.h
new file mode 100644
index 00..f0082b8d1d
--- /dev/null
+++ b/include/configs/socfpga_dm_socdk.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#ifndef __CONFIG_SOCFGPA_DM_H__
+#define __CONFIG_SOCFGPA_DM_H__
+
+#include
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTARGS "earlycon panic=-1 earlyprintk=ttyS0,4800"
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "bootfile=Image\0" \
+ "fdt_addr=110\0" \
+ "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "mmcvabboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootm ${loadaddr}\0" \
+ "mmcvabload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS";" \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "linux_qspi_enable=if sf probe; then " \
+ "echo Enabling QSPI at Linux DTB...;" \
+ "fdt addr ${fdt_addr}; fdt resize;" \
+ "fdt set /soc/spi@ff8d2000 status okay;" \
+ "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
+ " ${qspi_clock}; fi; \0" \
+ "scriptaddr=0x0210\0" \
+ "scriptfile=u-boot.scr\0" \
+ "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
+ "then source ${scriptaddr}; fi\0"
+
+#endif /* __CONFIG_SOCFGPA_DM_H__ */
--
2.13.0
[RESEND v2 16/22] ddr: altera: dm: Add SDRAM driver for Diamond Mesa
The DDR subsystem in Diamond Mesa is consisted of controller, PHY,
memory reset manager and memory clock manager.
Configuration settings of controller, PHY and memory reset manager
is come from DDR handoff data in bitstream, which contain the register
base addresses and user settings from Quartus.
Configuration settings of memory clock manager is come from the HPS
handoff data in bitstream, however the register base address is defined
in device tree.
The calibration is fully done in HPS, which requires IMEM and DMEM
binaries loading to PHY SRAM for running this calibration, both
IMEM and DMEM binaries are also part of bitstream, this bitstream
would be loaded to OCRAM by SDM, and configured by DDR driver.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/firewall.h |1 +
.../include/mach/system_manager_soc64.h|4 +
drivers/ddr/altera/Makefile|1 +
drivers/ddr/altera/sdram_dm.c | 1294
drivers/ddr/altera/sdram_soc64.c |6 +
5 files changed, 1306 insertions(+)
create mode 100644 drivers/ddr/altera/sdram_dm.c
diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h
b/arch/arm/mach-socfpga/include/mach/firewall.h
index a2face0570..06c941937b 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -121,6 +121,7 @@ struct socfpga_firwall_l4_sys {
#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0x1c
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD0xff
/* Firewall MPFE SCR Registers */
#define FW_MPFE_SCR_HMC0x00
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index 1e2289e5f8..4fc1a158b7 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -94,6 +94,10 @@ void populate_sysmgr_pinmux(void);
* storing qspi ref clock(kHz)
*/
#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0)
+#define SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASKBIT(31)
+#define SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK BIT(30)
+#define SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28))
+#define SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28
#define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index 39dfee5d5a..0f3b786c43 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -11,4 +11,5 @@ obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o
+obj-$(CONFIG_TARGET_SOCFPGA_DM) += sdram_soc64.o sdram_dm.o
endif
diff --git a/drivers/ddr/altera/sdram_dm.c b/drivers/ddr/altera/sdram_dm.c
new file mode 100644
index 00..0eb19ea082
--- /dev/null
+++ b/drivers/ddr/altera/sdram_dm.c
@@ -0,0 +1,1294 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "sdram_soc64.h"
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Memory reset manager */
+#define MEM_RST_MGR_STATUS 0x8
+
+/* Register and bit in memory reset manager */
+#define MEM_RST_MGR_STATUS_RESET_COMPLETE BIT(0)
+#define MEM_RST_MGR_STATUS_PWROKIN_STATUS BIT(1)
+#define MEM_RST_MGR_STATUS_CONTROLLER_RST BIT(2)
+#define MEM_RST_MGR_STATUS_AXI_RST BIT(3)
+
+#define TIMEOUT_200MS 200
+#define TIMEOUT_5000MS5000
+
+/* DDR4 umctl2 */
+#define DDR4_STAT_OFFSET 0x4
+#define DDR4_STAT_SELFREF_TYPE (BIT(5) | BIT(4))
+#define DDR4_STAT_SELFREF_TYPE_SHIFT 4
+#define DDR4_STAT_OPERATING_MODE (BIT(2) | BIT(1) | BIT(0))
+
+#define DDR4_MRCTRL0_OFFSET0x10
+#define DDR4_MRCTRL0_MR_TYPE BIT(0)
+#define DDR4_MRCTRL0_MPR_ENBIT(1)
+#define DDR4_MRCTRL0_MR_RANK (BIT(5) | BIT(4))
+#define DDR4_MRCTRL0_MR_RANK_SHIFT 4
+#define DDR4_MRCTRL0_MR_ADDR (BIT(15) | BIT(14) | BIT(13) | BIT(12))
+#define DDR4_MRCTRL0_MR_ADDR_SHIFT 12
+#define DDR4_MRCTRL0_MR_WR BIT(31)
+
+#define DDR4_MRCTRL1_OFFSET0x14
+#define DDR4_MRCTRL1_MR_DATA 0x3
+
+#define DDR4_MRSTAT_OFFSET 0x18
+#define DDR4_MRSTAT_MR_WR_BUSY BIT(0)
+
+#define DDR4_MRCTRL2_OFFSET0x1C
+
+#d
[RESEND v2 17/22] arm: socfpga: Move Stratix10 and Agilex SPL common code
Move Stratix10 and Agilex SPL common code to spl_soc64.c
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 2 ++
arch/arm/mach-socfpga/spl_agilex.c | 16
arch/arm/mach-socfpga/spl_s10.c| 17 -
arch/arm/mach-socfpga/spl_soc64.c | 26 ++
4 files changed, 28 insertions(+), 33 deletions(-)
create mode 100644 arch/arm/mach-socfpga/spl_soc64.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 96fef50a12..57dc1e730d 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -68,10 +68,12 @@ endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
obj-y += firewall.o
obj-y += spl_s10.o
+obj-y += spl_soc64.o
endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += firewall.o
obj-y += spl_agilex.o
+obj-y += spl_soc64.o
endif
else
obj-$(CONFIG_SPL_ATF) += smc_api.o
diff --git a/arch/arm/mach-socfpga/spl_agilex.c
b/arch/arm/mach-socfpga/spl_agilex.c
index 78b5d7c8d9..e65bf6360c 100644
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_agilex.c
@@ -24,22 +24,6 @@
DECLARE_GLOBAL_DATA_PTR;
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_MMC1;
-}
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_mmc_boot_mode(const u32 boot_device)
-{
-#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
- return MMCSD_MODE_FS;
-#else
- return MMCSD_MODE_RAW;
-#endif
-}
-#endif
-
void board_init_f(ulong dummy)
{
int ret;
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index daed05653a..1512b1ace3 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -25,23 +25,6 @@
DECLARE_GLOBAL_DATA_PTR;
-u32 spl_boot_device(void)
-{
- /* TODO: Get from SDM or handoff */
- return BOOT_DEVICE_MMC1;
-}
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_mmc_boot_mode(const u32 boot_device)
-{
-#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
- return MMCSD_MODE_FS;
-#else
- return MMCSD_MODE_RAW;
-#endif
-}
-#endif
-
void board_init_f(ulong dummy)
{
const struct cm_config *cm_default_cfg = cm_get_default_config();
diff --git a/arch/arm/mach-socfpga/spl_soc64.c
b/arch/arm/mach-socfpga/spl_soc64.c
new file mode 100644
index 00..53e5f6998c
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_soc64.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved
+ *
+ */
+
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_MMC1;
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(const u32 boot_device)
+{
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
+ return MMCSD_MODE_FS;
+#else
+ return MMCSD_MODE_RAW;
+#endif
+}
+#endif
--
2.13.0
[RESEND v2 18/22] arm: socfpga: dm: Add SPL for Diamond Mesa
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/spl_dm.c | 93 ++
1 file changed, 93 insertions(+)
create mode 100644 arch/arm/mach-socfpga/spl_dm.c
diff --git a/arch/arm/mach-socfpga/spl_dm.c b/arch/arm/mach-socfpga/spl_dm.c
new file mode 100644
index 00..ef664f4426
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_dm.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+ struct udevice *dev;
+
+ ret = spl_early_init();
+ if (ret)
+ hang();
+
+ socfpga_get_managers_addr();
+
+ /* Ensure watchdog is paused when debugging is happening */
+ writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
+ socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
+
+#ifdef CONFIG_HW_WATCHDOG
+ /* Enable watchdog before initializing the HW */
+ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
+ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
+ hw_watchdog_init();
+#endif
+
+ /* ensure all processors are not released prior Linux boot */
+ writeq(0, CPU_RELEASE_ADDR);
+
+ timer_init();
+
+ sysmgr_pinmux_init();
+
+ preloader_console_init();
+
+ ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+ if (ret) {
+ printf("Clock init failed: %d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device(UCLASS_CLK, 1, &dev);
+ if (ret) {
+ printf("Memory clock init failed: %d\n", ret);
+ hang();
+ }
+
+ print_reset_info();
+ cm_print_clock_quick_summary();
+
+ firewall_setup();
+
+ ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
+ if (ret) {
+ printf("CCU init failed: %d\n", ret);
+ hang();
+ }
+
+#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ printf("DRAM init failed: %d\n", ret);
+ hang();
+ }
+#endif
+
+ mbox_init();
+
+#ifdef CONFIG_CADENCE_QSPI
+ mbox_qspi_open();
+#endif
+}
--
2.13.0
[RESEND v2 19/22] board: intel: dm: Add socdk board support for Diamond Mesa
Add Diamond Mesa SoC devkit board. Signed-off-by: Siew Chin Lim --- board/intel/dm-socdk/MAINTAINERS | 7 +++ board/intel/dm-socdk/Makefile| 7 +++ board/intel/dm-socdk/socfpga.c | 7 +++ 3 files changed, 21 insertions(+) create mode 100644 board/intel/dm-socdk/MAINTAINERS create mode 100644 board/intel/dm-socdk/Makefile create mode 100644 board/intel/dm-socdk/socfpga.c diff --git a/board/intel/dm-socdk/MAINTAINERS b/board/intel/dm-socdk/MAINTAINERS new file mode 100644 index 00..f41bbcf2d5 --- /dev/null +++ b/board/intel/dm-socdk/MAINTAINERS @@ -0,0 +1,7 @@ +SOCFPGA BOARD +M: Chee Tien Fong +M: Lim Siew Chin +S: Maintained +F: board/intel/dm-socdk/ +F: include/configs/socfpga_dm_socdk.h +F: configs/socfpga_dm_atf_defconfig diff --git a/board/intel/dm-socdk/Makefile b/board/intel/dm-socdk/Makefile new file mode 100644 index 00..09f07b8b2f --- /dev/null +++ b/board/intel/dm-socdk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2020 Intel Corporation +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := socfpga.o diff --git a/board/intel/dm-socdk/socfpga.c b/board/intel/dm-socdk/socfpga.c new file mode 100644 index 00..ce87e2307d --- /dev/null +++ b/board/intel/dm-socdk/socfpga.c @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Intel Corporation + * + */ + +#include -- 2.13.0
[RESEND v2 15/22] arm: socfpga: dm: Add clock manager for Diamond Mesa
Add clock manager for Diamond Mesa.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/clock_manager_dm.c | 79 ++
arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 +
.../mach-socfpga/include/mach/clock_manager_dm.h | 14
3 files changed, 95 insertions(+)
create mode 100644 arch/arm/mach-socfpga/clock_manager_dm.c
create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_dm.h
diff --git a/arch/arm/mach-socfpga/clock_manager_dm.c
b/arch/arm/mach-socfpga/clock_manager_dm.c
new file mode 100644
index 00..cdf096cd8b
--- /dev/null
+++ b/arch/arm/mach-socfpga/clock_manager_dm.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong cm_get_rate_dm(u32 id)
+{
+ struct udevice *dev;
+ struct clk clk;
+ ulong rate;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(socfpga_dm_clk),
+ &dev);
+ if (ret)
+ return 0;
+
+ clk.id = id;
+ ret = clk_request(dev, &clk);
+ if (ret < 0)
+ return 0;
+
+ rate = clk_get_rate(&clk);
+
+ clk_free(&clk);
+
+ if ((rate == (unsigned long)-ENXIO) ||
+ (rate == (unsigned long)-EIO)) {
+ debug("%s id %u: clk_get_rate err: %ld\n",
+ __func__, id, rate);
+ return 0;
+ }
+
+ return rate;
+}
+
+static u32 cm_get_rate_dm_khz(u32 id)
+{
+ return cm_get_rate_dm(id) / 1000;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+ return cm_get_rate_dm(DM_MPU_CLK);
+}
+
+unsigned int cm_get_l4_sys_free_clk_hz(void)
+{
+ return cm_get_rate_dm(DM_L4_SYS_FREE_CLK);
+}
+
+void cm_print_clock_quick_summary(void)
+{
+ printf("MPU %10d kHz\n",
+ cm_get_rate_dm_khz(DM_MPU_CLK));
+ printf("L4 Main %8d kHz\n",
+ cm_get_rate_dm_khz(DM_L4_MAIN_CLK));
+ printf("L4 sys free %8d kHz\n",
+ cm_get_rate_dm_khz(DM_L4_SYS_FREE_CLK));
+ printf("L4 MP %8d kHz\n",
+ cm_get_rate_dm_khz(DM_L4_MP_CLK));
+ printf("L4 SP %8d kHz\n",
+ cm_get_rate_dm_khz(DM_L4_SP_CLK));
+ printf("SDMMC %8d kHz\n",
+ cm_get_rate_dm_khz(DM_SDMMC_CLK));
+}
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 0f0cb230fa..a164f47bda 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -26,6 +26,8 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#include
#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
#include
+#elif defined(CONFIG_TARGET_SOCFPGA_DM)
+#include
#endif
#endif /* _CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h
new file mode 100644
index 00..a355fda692
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#ifndef _CLOCK_MANAGER_DM_
+#define _CLOCK_MANAGER_DM_
+
+unsigned long cm_get_mpu_clk_hz(void);
+
+#include
+#include "../../../../../drivers/clk/altera/clk-dm.h"
+
+#endif /* _CLOCK_MANAGER_DM_ */
--
2.13.0
[RESEND v2 13/22] arm: socfpga: Move Stratix10 and Agilex clock manager common code
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/clock_manager.c | 10 ++
arch/arm/mach-socfpga/clock_manager_agilex.c | 6 --
arch/arm/mach-socfpga/clock_manager_s10.c | 6 --
arch/arm/mach-socfpga/include/mach/clock_manager.h | 4
arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 1 -
5 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager.c
b/arch/arm/mach-socfpga/clock_manager.c
index a4a97b6a0f..2d0cc19f7a 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -62,6 +63,15 @@ int set_cpu_clk_info(void)
return 0;
}
+#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
+unsigned int cm_get_qspi_controller_clk_hz(void)
+{
+ return readl(socfpga_get_sysmgr_addr() +
+SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+}
+
+#endif
+
#ifndef CONFIG_SPL_BUILD
static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c
b/arch/arm/mach-socfpga/clock_manager_agilex.c
index 6188a8c3d2..86e00d7611 100644
--- a/arch/arm/mach-socfpga/clock_manager_agilex.c
+++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
@@ -64,12 +64,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
}
-u32 cm_get_qspi_controller_clk_hz(void)
-{
- return readl(socfpga_get_sysmgr_addr() +
-SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
-}
-
void cm_print_clock_quick_summary(void)
{
printf("MPU %10d kHz\n",
diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c
b/arch/arm/mach-socfpga/clock_manager_s10.c
index 431794e082..ef62c56ad9 100644
--- a/arch/arm/mach-socfpga/clock_manager_s10.c
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -383,12 +383,6 @@ unsigned int cm_get_l4_sp_clk_hz(void)
return clock;
}
-unsigned int cm_get_qspi_controller_clk_hz(void)
-{
- return readl(socfpga_get_sysmgr_addr() +
-SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
-}
-
unsigned int cm_get_spi_controller_clk_hz(void)
{
u32 clock = cm_get_l3_main_clk_hz();
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 1f734bcd65..0f0cb230fa 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -12,6 +12,10 @@ phys_addr_t socfpga_get_clkmgr_addr(void);
void cm_wait_for_lock(u32 mask);
int cm_wait_for_fsm(void);
void cm_print_clock_quick_summary(void);
+
+#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
+unsigned int cm_get_qspi_controller_clk_hz(void);
+#endif
#endif
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index cb7923baef..98c3bf1b03 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -15,7 +15,6 @@ unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
-unsigned int cm_get_qspi_controller_clk_hz(void);
unsigned int cm_get_spi_controller_clk_hz(void);
struct cm_config {
--
2.13.0
[RESEND v2 09/22] arm: socfpga: Add handoff data support for Diamond Mesa
Diamond Mesa support both HPS handoff data and DDR handoff data.
HPS handoff data support re-use Straix10 and Agilex code. DDR
handoff data is newly introduced in Diamond Mesa.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 19 ++
arch/arm/mach-socfpga/wrap_handoff_soc64.c | 40 ++
2 files changed, 59 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index 68e0278384..c38b232065 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -23,8 +23,27 @@
#define SOC64_HANDOFF_OFFSET_DATA 0x10
#define SOC64_HANDOFF_SIZE 4096
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+ defined(CONFIG_TARGET_SOCFPGA_AGILEX)
#define SOC64_HANDOFF_BASE 0xFFE3F000
#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610)
+#elif defined(CONFIG_TARGET_SOCFPGA_DM)
+#define SOC64_HANDOFF_BASE 0xFFE5F000
+#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x630)
+
+/* DDR handoff */
+#define SOC64_HANDOFF_DDR_BASE 0xFFE5C000
+
+#define SOC64_HANDOFF_DDR_MAGIC0x4852
+#define SOC64_HANDOFF_DDR_UMCTL2_MAGIC 0x4C54434D
+#define SOC64_HANDOFF_DDR_MEMRESET_BASE(SOC64_HANDOFF_DDR_BASE
+ 0xC)
+#define SOC64_HANDOFF_DDR_UMCTL2_SECTION (SOC64_HANDOFF_DDR_BASE + 0x10)
+#define SOC64_HANDOFF_DDR_UMCTL2_BASE (SOC64_HANDOFF_DDR_BASE + 0x1C)
+#define SOC64_HANDOFF_DDR_PHY_MAGIC0x43594850
+#define SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC0x45594850
+#define SOC64_HANDOFF_DDR_PHY_BASE_OFFSET 0x8
+#endif
+
#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10)
#define SOC64_HANDOFF_IOCTL(SOC64_HANDOFF_BASE + 0x1A0)
#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330)
diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
index 672bdd5230..aea384897e 100644
--- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
+++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
@@ -67,6 +67,46 @@ int socfpga_handoff_read(void *handoff_address, void *table,
u32 table_len,
debug("at addr 0x%p\n", (u32 *)handoff_address);
return -EPERM;
}
+ } else {
+#ifdef CONFIG_TARGET_SOCFPGA_DM
+ temp = readl(handoff_address);
+ if (temp == SOC64_HANDOFF_DDR_UMCTL2_MAGIC) {
+ debug("%s: umctl2 handoff data =\n{\n",
+ __func__);
+ } else if (temp == SOC64_HANDOFF_DDR_PHY_MAGIC) {
+ debug("%s: PHY handoff data =\n{\n",
+ __func__);
+ } else if (temp == SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC) {
+ debug("%s: PHY engine handoff data =\n{\n",
+ __func__);
+ }
+
+ debug("handoff table address = 0x%p table length = 0x%x\n",
+ table_x32, table_len);
+
+ if (temp == SOC64_HANDOFF_DDR_UMCTL2_MAGIC ||
+ temp == SOC64_HANDOFF_DDR_PHY_MAGIC ||
+ temp == SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC) {
+ /* Using handoff from Quartus tools if exists */
+ for (i = 0; i < table_len; i++) {
+ *table_x32 = readl(handoff_address +
+ SOC64_HANDOFF_OFFSET_DATA + (i
* 4));
+
+ if (!(i % 2))
+ debug(" No.%d Addr 0x%08x: ", i,
+ *table_x32);
+ else
+ debug(" 0x%08x\n", *table_x32);
+
+ table_x32++;
+ }
+ debug("\n}\n");
+ } else {
+ debug("%s: Cannot find HANDOFF MAGIC ", __func__);
+ debug("at addr 0x%p\n", (u32 *)handoff_address);
+ return -EPERM;
+ }
+#endif
}
return 0;
--
2.13.0
[RESEND v2 14/22] arm: socfpga: Changed to store QSPI reference clock in kHz
Changed to store QSPI reference clock in kHz instead of Hz in
boot scratch cold0 register for Stratix10 and Agilex.
This patch is in preparation for Diamond Mesa SDRAM driver
support. Reserved 4 bits for Diamond Mesa SDRAM driver,
and there will be 28 bits to store QSPI reference clock.
Due to limited bits, QSPI reference clock frequency is
converted to kHz from Hz.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/clock_manager.c | 5 ++--
.../include/mach/system_manager_soc64.h| 12 +-
arch/arm/mach-socfpga/mailbox_s10.c| 28 +++---
3 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager.c
b/arch/arm/mach-socfpga/clock_manager.c
index 2d0cc19f7a..8299d0956d 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -66,8 +66,9 @@ int set_cpu_clk_info(void)
#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
unsigned int cm_get_qspi_controller_clk_hz(void)
{
- return readl(socfpga_get_sysmgr_addr() +
-SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+ return (readl(socfpga_get_sysmgr_addr() +
+SYSMGR_SOC64_BOOT_SCRATCH_COLD0) &
+SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) * 1000;
}
#endif
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index 1eb8e7a904..1e2289e5f8 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -42,7 +42,10 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_SOC64_GPO 0xe4
#define SYSMGR_SOC64_GPI 0xe8
#define SYSMGR_SOC64_MPU 0xf0
-/* store qspi ref clock */
+/*
+ * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC
64-bit
+ * storing qspi ref clock(kHz)
+ */
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD00x200
/* store osc1 clock freq */
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD10x204
@@ -85,6 +88,13 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_SOC64_HPS_OSC_CLK 0x1358
#define SYSMGR_SOC64_IODELAY0 0x1400
+/*
+ * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0
+ * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC
64-bit
+ * storing qspi ref clock(kHz)
+ */
+#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0)
+
#define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUXBIT(0)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga/mailbox_s10.c
index 429444f069..2e43131c5d 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -359,7 +359,7 @@ int mbox_qspi_open(void)
{
int ret;
u32 resp_buf[1];
- u32 resp_buf_len;
+ u32 resp_buf_len, temp;
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN, MBOX_CMD_DIRECT,
0, NULL, 0, 0, NULL);
@@ -384,8 +384,30 @@ int mbox_qspi_open(void)
goto error;
/* We are getting QSPI ref clock and set into sysmgr boot register */
- printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
- writel(resp_buf[0],
+ /*
+* Only clock freq in kHz degree is accepted due to limited bits[27:0]
+* is reserved for storing the QSPI clock freq into boot scratch cold0
+* register
+*/
+ if (resp_buf[0] < 1000) {
+ ret = -EINVAL;
+ goto error;
+ } else {
+ resp_buf[0] /= 1000;
+ }
+
+ printf("QSPI: Reference clock at %d kHz\n", resp_buf[0]);
+
+ /*
+* DDR retention bit, SHA comparison bit and reset type bits sharing the
+* same scratch register in DM, ensure the content inside register is
+* not overwritten by QSPI ref clock(kHz)
+*/
+ temp = readl(socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_BOOT_SCRATCH_COLD0) &
+ ~(SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK);
+
+ writel((resp_buf[0] & SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) | temp,
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
return 0;
--
2.13.0
[RESEND v2 12/22] drivers: clk: dm: Add memory clock driver for Diamond Mesa
Add memory clock manager driver for Diamond Mesa. Provides
clock initialization and enable functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 2 +-
drivers/clk/altera/clk-mem-dm.c | 135
drivers/clk/altera/clk-mem-dm.h | 80
3 files changed, 216 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/altera/clk-mem-dm.c
create mode 100644 drivers/clk/altera/clk-mem-dm.h
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index 08f16fd7cd..ad4ad5fb3d 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -5,4 +5,4 @@
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
-obj-$(CONFIG_TARGET_SOCFPGA_DM) += clk-dm.o
+obj-$(CONFIG_TARGET_SOCFPGA_DM) += clk-dm.o clk-mem-dm.o
diff --git a/drivers/clk/altera/clk-mem-dm.c b/drivers/clk/altera/clk-mem-dm.c
new file mode 100644
index 00..827b8d3e95
--- /dev/null
+++ b/drivers/clk/altera/clk-mem-dm.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include "clk-mem-dm.h"
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_mem_clk_platdata {
+ void __iomem *regs;
+};
+
+void clk_mem_wait_for_lock(struct socfpga_mem_clk_platdata *plat, u32 mask)
+{
+ u32 inter_val;
+ u32 retry = 0;
+
+ do {
+ inter_val = CM_REG_READL(plat, MEMCLKMGR_STAT) & mask;
+
+ /* Wait for stable lock */
+ if (inter_val == mask)
+ retry++;
+ else
+ retry = 0;
+
+ if (retry >= 10)
+ return;
+ } while (1);
+}
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+void clk_mem_write_bypass_mempll(struct socfpga_mem_clk_platdata *plat, u32
val)
+{
+ CM_REG_WRITEL(plat, val, MEMCLKMGR_MEMPLL_BYPASS);
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+static void clk_mem_basic_init(struct udevice *dev,
+ const struct cm_config * const cfg)
+{
+ struct socfpga_mem_clk_platdata *plat = dev_get_platdata(dev);
+
+ if (!cfg)
+ return;
+
+ /* Put PLLs in bypass */
+ clk_mem_write_bypass_mempll(plat, MEMCLKMGR_BYPASS_MEMPLL_ALL);
+
+ /* Put PLLs in Reset */
+ CM_REG_SETBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
+ MEMCLKMGR_PLLCTRL_BYPASS_MASK);
+
+ /* setup mem PLL */
+ CM_REG_WRITEL(plat, cfg->mem_memdiv, MEMCLKMGR_MEMPLL_MEMDIV);
+ CM_REG_WRITEL(plat, cfg->mem_pllglob, MEMCLKMGR_MEMPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->mem_plldiv, MEMCLKMGR_MEMPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->mem_plloutdiv, MEMCLKMGR_MEMPLL_PLLOUTDIV);
+
+ /* Take PLL out of reset and power up */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
+ MEMCLKMGR_PLLCTRL_BYPASS_MASK);
+}
+
+static int socfpga_mem_clk_enable(struct clk *clk)
+{
+ const struct cm_config *cm_default_cfg = cm_get_default_config();
+ struct socfpga_mem_clk_platdata *plat = dev_get_platdata(clk->dev);
+
+ clk_mem_basic_init(clk->dev, cm_default_cfg);
+
+ clk_mem_wait_for_lock(plat, MEMCLKMGR_STAT_ALLPLL_LOCKED_MASK);
+
+ CM_REG_WRITEL(plat, CM_REG_READL(plat, MEMCLKMGR_MEMPLL_PLLGLOB) |
+ MEMCLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
+ MEMCLKMGR_MEMPLL_PLLGLOB);
+
+ /* Take all PLLs out of bypass */
+ clk_mem_write_bypass_mempll(plat, 0);
+
+ /* Clear the loss of lock bits (write 1 to clear) */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_INTRCLR,
+ MEMCLKMGR_INTER_MEMPLLLOST_MASK);
+
+ /* Take all ping pong counters out of reset */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_EXTCNTRST,
+ MEMCLKMGR_EXTCNTRST_ALLCNTRST);
+
+ return 0;
+}
+
+static int socfpga_mem_clk_ofdata_to_platdata(struct udevice *dev)
+{
+ struct socfpga_mem_clk_platdata *plat = dev_get_platdata(dev);
+ fdt_addr_t addr;
+
+ addr = devfdt_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ plat->regs = (void __iomem *)addr;
+
+ return 0;
+}
+
+static struct clk_ops socfpga_mem_clk_ops = {
+ .enable = socfpga_mem_clk_enable
+};
+
+static const struct udevice_id socfpga_mem_clk_match[] = {
+ { .compatible = "intel,dm-mem-clkmgr" },
+ {}
+};
+
+U_BOOT_DRIVER(socfpga_dm_mem_clk) = {
+ .name = "mem-clk-dm",
+ .id = UCLASS_CLK,
+ .of_match = socfpga_mem_clk_match,
+ .ops= &socfpga_mem_clk_ops,
+ .ofdata_to_platdata = socfpga_mem_clk_ofdata_to_platdat
[RESEND v2 10/22] drivers: clk: dm: Add clock driver for Diamond Mesa
Add clock manager driver for Diamond Mesa. Provides clock
initialization and get_rate functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 3 +-
drivers/clk/altera/clk-dm.c | 504 +++
drivers/clk/altera/clk-dm.h | 213 +++
include/dt-bindings/clock/dm-clock.h | 71 +
4 files changed, 790 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/altera/clk-dm.c
create mode 100644 drivers/clk/altera/clk-dm.h
create mode 100644 include/dt-bindings/clock/dm-clock.h
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index 96215ad5c4..08f16fd7cd 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2018 Marek Vasut
+# Copyright (C) 2018-2020 Marek Vasut
#
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_DM) += clk-dm.o
diff --git a/drivers/clk/altera/clk-dm.c b/drivers/clk/altera/clk-dm.c
new file mode 100644
index 00..c8421ed20b
--- /dev/null
+++ b/drivers/clk/altera/clk-dm.c
@@ -0,0 +1,504 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_clk_platdata {
+ void __iomem *regs;
+};
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void clk_write_bypass_mainpll(struct socfpga_clk_platdata *plat, u32
val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
+ cm_wait_for_fsm();
+}
+
+static void clk_write_bypass_perpll(struct socfpga_clk_platdata *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
+ cm_wait_for_fsm();
+}
+
+#ifndef CONFIG_TARGET_SOCFPGA_DM
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void clk_write_ctrl(struct socfpga_clk_platdata *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
+ cm_wait_for_fsm();
+}
+#endif
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+static void clk_basic_init(struct udevice *dev,
+ const struct cm_config * const cfg)
+{
+ struct socfpga_clk_platdata *plat = dev_get_platdata(dev);
+
+ if (!cfg)
+ return;
+
+#ifndef CONFIG_TARGET_SOCFPGA_DM
+#ifdef CONFIG_SPL_BUILD
+ /* Always force clock manager into boot mode before any configuration */
+ clk_write_ctrl(plat,
+ CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);
+#else
+ /* Skip clock configuration in SSBL if it's not in boot mode */
+ if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE))
+ return;
+#endif
+#endif
+
+ /* Put both PLLs in bypass */
+ clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
+ clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
+
+ /* Put both PLLs in Reset */
+ CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+ CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+
+#ifndef CONFIG_TARGET_SOCFPGA_DM
+ /* setup main PLL */
+ CM_REG_WRITEL(plat, cfg->main_pll_pllglob, CLKMGR_MAINPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->main_pll_plldiv, CLKMGR_MAINPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->main_pll_plloutdiv, CLKMGR_MAINPLL_PLLOUTDIV);
+ CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK);
+ CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK);
+ CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV);
+
+ /* setup peripheral */
+ CM_REG_WRITEL(plat, cfg->per_pll_pllglob, CLKMGR_PERPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->per_pll_plldiv, CLKMGR_PERPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->per_pll_plloutdiv, CLKMGR_PERPLL_PLLOUTDIV);
+ CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL);
+ CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV);
+#endif
+
+ /* Take both PLL out of reset and power up */
+ CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+ CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+
+ cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
+
+#ifndef CONFIG_TARGET_SOCFPGA_DM
+ CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR);
+ CM_REG_WRITEL(plat, cfg->alt_emacbctr, CLKMGR_ALTR_EMACBCTR);
+ CM_REG_WRITEL(plat, cfg->alt_emacptpctr, CLKMGR_ALTR_EMACPTPCTR);
+ CM_REG_WRITEL(plat, cfg->alt_gpiodbctr, CLKMGR_ALTR_GPIODBCTR);
+ CM_REG_WRITEL(plat, cf
[RESEND v2 08/22] arm: socfpga: Restructure Stratix10 and Agilex handoff code
Restructure Stratix10 and Agilex handoff code to used by
all SOC64 devices, in preparation to support handoff for
Diamond Mesa.
Remove wrap_pinmux_config_s10.c. Add wrap_handoff_soc64.c
which contains the generic function to parse the handoff
data.
Update system_manager_soc64.c to use generic handoff
function in wrap_handoff_soc64.c.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 4 +-
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 21 +++
.../include/mach/system_manager_soc64.h| 4 --
arch/arm/mach-socfpga/system_manager_soc64.c | 53 ++--
arch/arm/mach-socfpga/wrap_handoff_soc64.c | 73 ++
arch/arm/mach-socfpga/wrap_pinmux_config_s10.c | 56 -
6 files changed, 131 insertions(+), 80 deletions(-)
create mode 100644 arch/arm/mach-socfpga/wrap_handoff_soc64.c
delete mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index ff82a64d18..96fef50a12 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -37,7 +37,7 @@ obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-y += system_manager_soc64.o
obj-y += timer_s10.o
-obj-y += wrap_pinmux_config_s10.o
+obj-y += wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
endif
@@ -50,7 +50,7 @@ obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-y += system_manager_soc64.o
obj-y += timer_s10.o
-obj-y += wrap_pinmux_config_s10.o
+obj-y += wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
endif
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index dbd19f602c..68e0278384 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -11,6 +11,7 @@
* Offset for HW handoff from Quartus tools
*/
/* HPS handoff */
+#define SOC64_HANDOFF_MAGIC_BOOT 0x424F4F54
#define SOC64_HANDOFF_MAGIC_MUX0x504D5558
#define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354
#define SOC64_HANDOFF_MAGIC_FPGA 0x46504741
@@ -38,4 +39,24 @@
#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600)
#endif
+#define SOC64_HANDOFF_MUX_LEN 96
+#define SOC64_HANDOFF_IOCTL_LEN96
+#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+#define SOC64_HANDOFF_FPGA_LEN 42
+#else
+#define SOC64_HANDOFF_FPGA_LEN 40
+#endif
+#define SOC64_HANDOFF_DELAY_LEN96
+
+#ifndef __ASSEMBLY__
+#include
+enum endianness {
+ little_endian,
+ big_endian
+};
+
+int socfpga_get_handoff_size(void *handoff_address, enum endianness endian);
+int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len,
+enum endianness big_endian);
+#endif
#endif /* _HANDOFF_SOC64_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index 4949cae97a..1eb8e7a904 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -10,10 +10,6 @@
void sysmgr_pinmux_init(void);
void populate_sysmgr_fpgaintf_module(void);
void populate_sysmgr_pinmux(void);
-void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
#define SYSMGR_SOC64_WDDBG 0x08
#define SYSMGR_SOC64_DMA 0x20
diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c
b/arch/arm/mach-socfpga/system_manager_soc64.c
index cdda881efd..f94bf5ecd6 100644
--- a/arch/arm/mach-socfpga/system_manager_soc64.c
+++ b/arch/arm/mach-socfpga/system_manager_soc64.c
@@ -1,12 +1,13 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation
+ * Copyright (C) 2016-2020 Intel Corporation
*
*/
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -63,39 +64,55 @@ void populate_sysmgr_fpgaintf_module(void)
*/
void populate_sysmgr_pinmux(void)
{
- const u32 *sys_mgr_table_u32;
- unsigned int len, i;
+ u32 len, i;
+ u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX,
big_endian);
+ u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL,
big_endian);
+ u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA,
big_endian);
+ u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY,
big_endian);
+
+ len = (len_mux > len_ioctl) ? len_mux : len_ioctl;
+ len = (len > len_fpga) ? le
[RESEND v2 07/22] arm: socfpga: Rearrange sequence of macros in handoff_soc64.h
No functionality change. In preparation for Stratix10 and Agilex handoff function restructuring. Signed-off-by: Siew Chin Lim --- arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 46 +++--- 1 file changed, 24 insertions(+), 22 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index 6c84abe324..dbd19f602c 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2016-2018 Intel Corporation + * Copyright (C) 2016-2020 Intel Corporation * */ @@ -10,30 +10,32 @@ /* * Offset for HW handoff from Quartus tools */ -#define SOC64_HANDOFF_BASE 0xFFE3F000 -#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10) -#define SOC64_HANDOFF_IOCTL(SOC64_HANDOFF_BASE + 0x1A0) -#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330) -#define SOC64_HANDOFF_DELAY(SOC64_HANDOFF_BASE + 0x3F0) -#define SOC64_HANDOFF_CLOCK(SOC64_HANDOFF_BASE + 0x580) -#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) -#define SOC64_HANDOFF_MAGIC_MUX0x504D5558 -#define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354 -#define SOC64_HANDOFF_MAGIC_FPGA 0x46504741 -#define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159 -#define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53 -#define SOC64_HANDOFF_MAGIC_MISC 0x4D495343 -#define SOC64_HANDOFF_OFFSET_LENGTH0x4 -#define SOC64_HANDOFF_OFFSET_DATA 0x10 +/* HPS handoff */ +#define SOC64_HANDOFF_MAGIC_MUX0x504D5558 +#define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354 +#define SOC64_HANDOFF_MAGIC_FPGA 0x46504741 +#define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159 +#define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53 +#define SOC64_HANDOFF_MAGIC_MISC 0x4D495343 + +#define SOC64_HANDOFF_OFFSET_LENGTH0x4 +#define SOC64_HANDOFF_OFFSET_DATA 0x10 +#define SOC64_HANDOFF_SIZE 4096 + +#define SOC64_HANDOFF_BASE 0xFFE3F000 +#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) +#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10) +#define SOC64_HANDOFF_IOCTL(SOC64_HANDOFF_BASE + 0x1A0) +#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330) +#define SOC64_HANDOFF_DELAY(SOC64_HANDOFF_BASE + 0x3F0) +#define SOC64_HANDOFF_CLOCK(SOC64_HANDOFF_BASE + 0x580) #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 -#define SOC64_HANDOFF_CLOCK_OSC(SOC64_HANDOFF_BASE + 0x608) -#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C) +#define SOC64_HANDOFF_CLOCK_OSC(SOC64_HANDOFF_BASE + 0x608) +#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C) #else -#define SOC64_HANDOFF_CLOCK_OSC(SOC64_HANDOFF_BASE + 0x5fc) -#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600) +#define SOC64_HANDOFF_CLOCK_OSC(SOC64_HANDOFF_BASE + 0x5fc) +#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600) #endif -#define SOC64_HANDOFF_SIZE 4096 - #endif /* _HANDOFF_SOC64_H_ */ -- 2.13.0
[RESEND v2 03/22] arm: socfpga: dm: Add firewall support for Agilex and Diamond Mesa
Disable the MPFE firewall for SMMU and HMC adapter for
Agilex and Diamond Mesa.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/firewall.c | 10 ++
arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 1 +
arch/arm/mach-socfpga/include/mach/firewall.h | 6 ++
3 files changed, 17 insertions(+)
diff --git a/arch/arm/mach-socfpga/firewall.c b/arch/arm/mach-socfpga/firewall.c
index 69229dc651..b87cc8aa69 100644
--- a/arch/arm/mach-socfpga/firewall.c
+++ b/arch/arm/mach-socfpga/firewall.c
@@ -104,4 +104,14 @@ void firewall_setup(void)
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA);
writel(SYSMGR_DMAPERIPH_ALL_NS,
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA_PERIPH);
+
+#if defined(CONFIG_TARGET_SOCFPGA_AGILEX) || defined(CONFIG_TARGET_SOCFPGA_DM)
+ /* Disable the MPFE Firewall for SMMU */
+ writel(FIREWALL_MPFE_SCR_DISABLE_ALL, SOCFPGA_FW_MPFE_SCR_ADDRESS +
+ FW_MPFE_SCR_HMC);
+ /* Disable MPFE Firewall for HMC adapter (ECC) */
+ writel(FIREWALL_MPFE_SCR_DISABLE_MPU, SOCFPGA_FW_MPFE_SCR_ADDRESS +
+ FW_MPFE_SCR_HMC_ADAPTOR);
+#endif
+
}
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
index eef88a7fc3..26bd52c907 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -10,6 +10,7 @@
#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400
#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf801
#define SOCFPGA_SDR_ADDRESS0xf8011000
+#define SOCFPGA_FW_MPFE_SCR_ADDRESS0xf802
#if defined(CONFIG_TARGET_SOCFPGA_AGILEX) || defined(CONFIG_TARGET_SOCFPGA_DM)
#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200
#else
diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h
b/arch/arm/mach-socfpga/include/mach/firewall.h
index adab65bc96..a2face0570 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -75,6 +75,8 @@ struct socfpga_firwall_l4_sys {
};
#define FIREWALL_L4_DISABLE_ALL(BIT(0) | BIT(24) | BIT(16))
+#define FIREWALL_MPFE_SCR_DISABLE_ALL (BIT(0) | BIT(8) | BIT(16))
+#define FIREWALL_MPFE_SCR_DISABLE_MPU BIT(0)
#define FIREWALL_BRIDGE_DISABLE_ALL(~0)
/* Cache coherency unit (CCU) registers */
@@ -120,6 +122,10 @@ struct socfpga_firwall_l4_sys {
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c
+/* Firewall MPFE SCR Registers */
+#define FW_MPFE_SCR_HMC0x00
+#define FW_MPFE_SCR_HMC_ADAPTOR0x04
+
#define MPUREGION0_ENABLE BIT(0)
#define NONMPUREGION0_ENABLE BIT(8)
--
2.13.0
[RESEND v2 11/22] arm: socfpga: dm: Get clock manager base address for Diamond Mesa
Add Diamond Mesa clock manager to socfpga_get_managers_addr
function.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/misc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index ac2b891fad..b63eec779a 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -253,6 +253,9 @@ void socfpga_get_managers_addr(void)
#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
ret = socfpga_get_base_addr("intel,agilex-clkmgr",
&socfpga_clkmgr_base);
+#elif defined(CONFIG_TARGET_SOCFPGA_DM)
+ ret = socfpga_get_base_addr("intel,dm-clkmgr",
+ &socfpga_clkmgr_base);
#else
ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
#endif
--
2.13.0
[RESEND v2 04/22] arm: socfpga: Rename Stratix10 and Agilex handoff common macros
Rename handoff_s10.h to handoff_soc64.h. Changed macros prefix from
S10_HANDOFF to SOC64_HANDOFF.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/clock_manager_s10.c | 2 +-
arch/arm/mach-socfpga/include/mach/handoff_s10.h | 39 --
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 39 ++
arch/arm/mach-socfpga/wrap_pinmux_config_s10.c | 18 +-
arch/arm/mach-socfpga/wrap_pll_config_s10.c| 16 -
include/configs/socfpga_soc64_common.h | 4 +--
6 files changed, 59 insertions(+), 59 deletions(-)
delete mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h
create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_soc64.h
diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c
b/arch/arm/mach-socfpga/clock_manager_s10.c
index 05e42127b5..431794e082 100644
--- a/arch/arm/mach-socfpga/clock_manager_s10.c
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -7,7 +7,7 @@
#include
#include
#include
-#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h
b/arch/arm/mach-socfpga/include/mach/handoff_s10.h
deleted file mode 100644
index 3e9b606ce2..00
--- a/arch/arm/mach-socfpga/include/mach/handoff_s10.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2016-2018 Intel Corporation
- *
- */
-
-#ifndef _HANDOFF_S10_H_
-#define _HANDOFF_S10_H_
-
-/*
- * Offset for HW handoff from Quartus tools
- */
-#define S10_HANDOFF_BASE 0xFFE3F000
-#define S10_HANDOFF_MUX(S10_HANDOFF_BASE + 0x10)
-#define S10_HANDOFF_IOCTL (S10_HANDOFF_BASE + 0x1A0)
-#define S10_HANDOFF_FPGA (S10_HANDOFF_BASE + 0x330)
-#define S10_HANODFF_DELAY (S10_HANDOFF_BASE + 0x3F0)
-#define S10_HANDOFF_CLOCK (S10_HANDOFF_BASE + 0x580)
-#define S10_HANDOFF_MISC (S10_HANDOFF_BASE + 0x610)
-#define S10_HANDOFF_MAGIC_MUX 0x504D5558
-#define S10_HANDOFF_MAGIC_IOCTL0x494F4354
-#define S10_HANDOFF_MAGIC_FPGA 0x46504741
-#define S10_HANDOFF_MAGIC_DELAY0x444C4159
-#define S10_HANDOFF_MAGIC_CLOCK0x434C4B53
-#define S10_HANDOFF_MAGIC_MISC 0x4D495343
-#define S10_HANDOFF_OFFSET_LENGTH 0x4
-#define S10_HANDOFF_OFFSET_DATA0x10
-
-#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
-#define HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x608)
-#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C)
-#else
-#define HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x5fc)
-#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x600)
-#endif
-
-#define S10_HANDOFF_SIZE 4096
-
-#endif /* _HANDOFF_S10_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
new file mode 100644
index 00..6c84abe324
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2018 Intel Corporation
+ *
+ */
+
+#ifndef _HANDOFF_SOC64_H_
+#define _HANDOFF_SOC64_H_
+
+/*
+ * Offset for HW handoff from Quartus tools
+ */
+#define SOC64_HANDOFF_BASE 0xFFE3F000
+#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10)
+#define SOC64_HANDOFF_IOCTL(SOC64_HANDOFF_BASE + 0x1A0)
+#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330)
+#define SOC64_HANDOFF_DELAY(SOC64_HANDOFF_BASE + 0x3F0)
+#define SOC64_HANDOFF_CLOCK(SOC64_HANDOFF_BASE + 0x580)
+#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610)
+#define SOC64_HANDOFF_MAGIC_MUX0x504D5558
+#define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354
+#define SOC64_HANDOFF_MAGIC_FPGA 0x46504741
+#define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159
+#define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53
+#define SOC64_HANDOFF_MAGIC_MISC 0x4D495343
+#define SOC64_HANDOFF_OFFSET_LENGTH0x4
+#define SOC64_HANDOFF_OFFSET_DATA 0x10
+
+#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+#define SOC64_HANDOFF_CLOCK_OSC(SOC64_HANDOFF_BASE + 0x608)
+#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C)
+#else
+#define SOC64_HANDOFF_CLOCK_OSC(SOC64_HANDOFF_BASE + 0x5fc)
+#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600)
+#endif
+
+#define SOC64_HANDOFF_SIZE 4096
+
+#endif /* _HANDOFF_SOC64_H_ */
diff --git a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
index 0b497ec30c..d10fb5e454 100644
--- a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
+++ b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
@@ -7,23 +7,23 @@
#include
#include
#include
-#include
+#include
static void sysmgr_pinmux_handoff_read(void *handoff_address,
const u32 **table,
unsigned int *table_len)
{
[RESEND v2 02/22] arm: socfpga: dm: Add base address for Intel Diamond Mesa
Reuse base_addr_s10.h for Diamond Mesa, the address is the same as Agilex. Signed-off-by: Siew Chin Lim --- arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h index d3eca65e97..eef88a7fc3 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h @@ -10,7 +10,7 @@ #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf801 #define SOCFPGA_SDR_ADDRESS0xf8011000 -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX +#if defined(CONFIG_TARGET_SOCFPGA_AGILEX) || defined(CONFIG_TARGET_SOCFPGA_DM) #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 -- 2.13.0
[RESEND v2 01/22] arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64
Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim --- arch/arm/Kconfig| 6 +++--- arch/arm/mach-socfpga/Kconfig | 5 + arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 +-- arch/arm/mach-socfpga/include/mach/system_manager.h | 3 +-- drivers/ddr/altera/Kconfig | 6 +++--- drivers/fpga/Kconfig| 2 +- drivers/sysreset/Kconfig| 2 +- 7 files changed, 15 insertions(+), 12 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b2f7fcbd6e..663ea07341 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -974,7 +974,7 @@ config ARCH_SOCFPGA bool "Altera SOCFPGA family" select ARCH_EARLY_INIT_R select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 - select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX + select ARM64 if TARGET_SOCFPGA_SOC64 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select DM select DM_SERIAL @@ -986,7 +986,7 @@ config ARCH_SOCFPGA select SPL_LIBGENERIC_SUPPORT select SPL_NAND_SUPPORT if SPL_NAND_DENALI select SPL_OF_CONTROL - select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX + select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64 select SPL_SERIAL_SUPPORT select SPL_SYSRESET select SPL_WATCHDOG_SUPPORT @@ -995,7 +995,7 @@ config ARCH_SOCFPGA select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 - select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX + select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64 imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 7fdb52dd83..4d061a9d0d 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -31,6 +31,7 @@ config SYS_TEXT_BASE config TARGET_SOCFPGA_AGILEX bool + select TARGET_SOCFPGA_SOC64 select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN select CLK @@ -75,8 +76,12 @@ config TARGET_SOCFPGA_GEN5 imply SPL_SYS_MALLOC_SIMPLE imply SPL_USE_TINY_PRINTF +config TARGET_SOCFPGA_SOC64 + bool + config TARGET_SOCFPGA_STRATIX10 bool + select TARGET_SOCFPGA_SOC64 select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN select FPGA_INTEL_SDM_MAILBOX diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 7844ad14cb..8c25325e45 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -43,8 +43,7 @@ void socfpga_per_reset_all(void); #include #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #include -#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ - defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#elif defined(CONFIG_TARGET_SOCFPGA_SOC64) #include #endif diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index f816954717..5603eaa3d0 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -8,8 +8,7 @@ phys_addr_t socfpga_get_sysmgr_addr(void); -#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ - defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#if defined(CONFIG_TARGET_SOCFPGA_SOC64) #include #else #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUXBIT(0) diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig index 8f590dc5f6..4660d20def 100644 --- a/drivers/ddr/altera/Kconfig +++ b/drivers/ddr/altera/Kconfig @@ -1,8 +1,8 @@ config SPL_ALTERA_SDRAM bool "SoCFPGA DDR SDRAM driver in SPL" depends on SPL - depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX - select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX - select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX + depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_SOC64 + select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64 + select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64 help Enable DDR SDRAM controller for the SoCFPGA devices. diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 425b52a926..dc0b3dd31b 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -33,7 +33,7 @@ config FPGA_CYCLON2 config FPGA_INTEL_SDM_MAILBOX bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver
[RESEND v2 06/22] arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 5 +++--
.../mach-socfpga/{system_manager_s10.c => system_manager_soc64.c}| 0
2 files changed, 3 insertions(+), 2 deletions(-)
rename arch/arm/mach-socfpga/{system_manager_s10.c => system_manager_soc64.c}
(100%)
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index fc3b809afd..ff82a64d18 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -4,6 +4,7 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
#
# Copyright (C) 2012-2017 Altera Corporation
+# Copyright (C) 2017-2020 Intel Corporation
obj-y += board.o
obj-y += clock_manager.o
@@ -34,7 +35,7 @@ obj-y += mailbox_s10.o
obj-y += misc_s10.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
-obj-y += system_manager_s10.o
+obj-y += system_manager_soc64.o
obj-y += timer_s10.o
obj-y += wrap_pinmux_config_s10.o
obj-y += wrap_pll_config_soc64.o
@@ -47,7 +48,7 @@ obj-y += mailbox_s10.o
obj-y += misc_s10.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
-obj-y += system_manager_s10.o
+obj-y += system_manager_soc64.o
obj-y += timer_s10.o
obj-y += wrap_pinmux_config_s10.o
obj-y += wrap_pll_config_soc64.o
diff --git a/arch/arm/mach-socfpga/system_manager_s10.c
b/arch/arm/mach-socfpga/system_manager_soc64.c
similarity index 100%
rename from arch/arm/mach-socfpga/system_manager_s10.c
rename to arch/arm/mach-socfpga/system_manager_soc64.c
--
2.13.0
[RESEND v2 00/22] Add Intel Diamond Mesa SoC support
This is the 2nd version of patchset add Intel Diamond Mesa SoC[1] support.
Intel Diamond Mesa SoC is with a 64-bit quad core ARM Cortex-A53 MPCore
hard processor system (HPS). New IPs in Diamond Mesa are clock manager
and DDR subsystem, other IPs have minor changes compared to Agilex.
Patch status:
Have changes: Patch 20, 22
Other patches unchanged.
Detail changelog can find in commit message.
v1->v2:
Patch 20:
- Include binman node device tree object (socfpga_soc64_fit-u-boot.dtsi_ in
socfpga_dm-u-boot.dtsi
Patch 22:
- Add "CONFIG_USE_SPL_FIT_GENERATE is not set" to socfpga_dm_atf_defconfig. Use
binman to generate
FIT image instead of local script.
History:
[v1]:
https://patchwork.ozlabs.org/project/uboot/cover/20200922094930.100855-1-elly.siew.chin@intel.com/
These patchsets have dependency on:
Enable ARM Trusted Firmware for U-Boot
https://patchwork.ozlabs.org/project/uboot/cover/20201015122955.10259-1-elly.siew.chin@intel.com/
Note:
[1]:
https://www.intel.com/content/www/us/en/products/programmable/asic/easic-devices/diamond-mesa-soc-devices.html
Siew Chin Lim (22):
arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64
arm: socfpga: dm: Add base address for Intel Diamond Mesa
arm: socfpga: dm: Add firewall support for Agilex and Diamond Mesa
arm: socfpga: Rename Stratix10 and Agilex handoff common macros
arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c
arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c
arm: socfpga: Rearrange sequence of macros in handoff_soc64.h
arm: socfpga: Restructure Stratix10 and Agilex handoff code
arm: socfpga: Add handoff data support for Diamond Mesa
drivers: clk: dm: Add clock driver for Diamond Mesa
arm: socfpga: dm: Get clock manager base address for Diamond Mesa
drivers: clk: dm: Add memory clock driver for Diamond Mesa
arm: socfpga: Move Stratix10 and Agilex clock manager common code
arm: socfpga: Changed to store QSPI reference clock in kHz
arm: socfpga: dm: Add clock manager for Diamond Mesa
ddr: altera: dm: Add SDRAM driver for Diamond Mesa
arm: socfpga: Move Stratix10 and Agilex SPL common code
arm: socfpga: dm: Add SPL for Diamond Mesa
board: intel: dm: Add socdk board support for Diamond Mesa
arm: dts: dm: Add base dtsi and devkit dts for Diamond Mesa
configs: dm: Add Diamond Mesa CONFIGs
arm: socfpga: dm: Enable Intel Diamond Mesa build
arch/arm/Kconfig |6 +-
arch/arm/dts/Makefile |1 +
arch/arm/dts/socfpga_dm-u-boot.dtsi| 102 ++
arch/arm/dts/socfpga_dm.dtsi | 640 ++
arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi | 50 +
arch/arm/dts/socfpga_dm_socdk.dts | 144 +++
arch/arm/mach-socfpga/Kconfig | 24 +
arch/arm/mach-socfpga/Makefile | 33 +-
arch/arm/mach-socfpga/clock_manager.c | 11 +
arch/arm/mach-socfpga/clock_manager_agilex.c |6 -
.../{clock_manager_agilex.c => clock_manager_dm.c} | 32 +-
arch/arm/mach-socfpga/clock_manager_s10.c |8 +-
arch/arm/mach-socfpga/firewall.c | 10 +
arch/arm/mach-socfpga/include/mach/base_addr_s10.h |3 +-
arch/arm/mach-socfpga/include/mach/clock_manager.h |6 +
.../mach-socfpga/include/mach/clock_manager_dm.h | 14 +
.../mach-socfpga/include/mach/clock_manager_s10.h |1 -
arch/arm/mach-socfpga/include/mach/firewall.h |7 +
arch/arm/mach-socfpga/include/mach/handoff_s10.h | 39 -
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 81 ++
arch/arm/mach-socfpga/include/mach/reset_manager.h |3 +-
.../arm/mach-socfpga/include/mach/system_manager.h |3 +-
.../include/mach/system_manager_soc64.h| 20 +-
arch/arm/mach-socfpga/mailbox_s10.c| 28 +-
arch/arm/mach-socfpga/misc.c |3 +
arch/arm/mach-socfpga/spl_agilex.c | 16 -
arch/arm/mach-socfpga/{spl_agilex.c => spl_dm.c} | 37 +-
arch/arm/mach-socfpga/spl_s10.c| 17 -
arch/arm/mach-socfpga/spl_soc64.c | 26 +
...system_manager_s10.c => system_manager_soc64.c} | 53 +-
arch/arm/mach-socfpga/wrap_handoff_soc64.c | 113 ++
arch/arm/mach-socfpga/wrap_pinmux_config_s10.c | 56 -
...ap_pll_config_s10.c => wrap_pll_config_soc64.c} | 18 +-
board/intel/dm-socdk/MAINTAINERS |7 +
board/intel/dm-socdk/Makefile |7 +
board/intel/dm-socdk/socfpga.c |7 +
configs/socfpga_dm_atf_defconfig | 76 ++
configs/socfpga_dm_defconfig | 69 ++
drivers/clk/altera/Makefile|3 +-
drivers/clk/altera/clk-dm.c| 504
drivers/clk/altera/clk-dm.h
RE: [v2, 0/2] mmc: fsl_esdhc: fix up for eMMC HS400
Hi Peng, Any comments on the patches. Thanks. Best regards, Yangbo Lu > -Original Message- > From: Yangbo Lu > Sent: Tuesday, October 20, 2020 11:05 AM > To: u-boot@lists.denx.de; Peng Fan ; 'Jaehoon Chung' > > Cc: Y.b. Lu > Subject: [v2, 0/2] mmc: fsl_esdhc: fix up for eMMC HS400 > > This patch-set provides fix up for eMMC HS400 for a potential > DLL lock issue during mmc rescan. > > Changes for v2: > - Added "Reviewed-by". > - Explained more in patch 2 commit message. > > Yangbo Lu (2): > mmc: fsl_esdhc: set sysctl register for clock initialization > mmc: fsl_esdhc: make sure delay chain locked for HS400 > > drivers/mmc/fsl_esdhc.c | 30 ++ > include/fsl_esdhc.h | 4 > 2 files changed, 30 insertions(+), 4 deletions(-) > > -- > 2.7.4
RE: [v2 00/22] Add Intel Diamond Mesa SoC support
Hi All, Kindly ignore "[v2,00/22] Add Intel Diamond Mesa SoC support" series of patches. Sorry that I make some mistake when send for review. I will resend this series. I sincerely apologize for the inconvenience caused Thanks, Siew Chin > -Original Message- > From: Lim, Elly Siew Chin > Sent: Tuesday, November 10, 2020 1:55 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut ; Tan, Ley Foon ; > See, Chin Liang ; Simon Goldschmidt > ; Chee, Tien Fong > ; Westergreen, Dalon > ; Simon Glass ; Gan, Yau > Wai ; Lim, Elly Siew Chin > > Subject: [v2 00/22] Add Intel Diamond Mesa SoC support > > This is the 2nd version of patchset add Intel Diamond Mesa SoC[1] support. > > Intel Diamond Mesa SoC is with a 64-bit quad core ARM Cortex-A53 MPCore > hard processor system (HPS). New IPs in Diamond Mesa are clock manager and > DDR subsystem, other IPs have minor changes compared to Agilex. > > Patch status: > Have changes: Patch 20, 22 > Other patches unchanged. > > Detail changelog can find in commit message. > > v1->v2: > > Patch 20: > - Include binman node device tree object (socfpga_soc64_fit-u-boot.dtsi_ in > socfpga_dm-u-boot.dtsi > > Patch 22: > - Add "CONFIG_USE_SPL_FIT_GENERATE is not set" to > socfpga_dm_atf_defconfig. Use binman to generate > FIT image instead of local script. > > > History: > > [v1]: > https://patchwork.ozlabs.org/project/uboot/cover/20200922094930.100855- > 1-elly.siew.chin@intel.com/ > > > These patchsets have dependency on: > > Enable ARM Trusted Firmware for U-Boot > https://patchwork.ozlabs.org/project/uboot/cover/20201015122955.10259- > 1-elly.siew.chin@intel.com/ > > > [1]: > https://www.intel.com/content/www/us/en/products/programmable/asic/easi > c-devices/diamond-mesa-soc-devices.html > > > Chee Hong Ang (14): > arm: socfpga: Add function for checking description from FIT image > arm: socfpga: soc64: Load FIT image with ATF support > arm: socfpga: soc64: Override 'lowlevel_init' to support ATF > arm: socfpga: Disable "spin-table" method for booting Linux > arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA > (64bits) > arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP > services > mmc: dwmmc: socfpga: Add ATF support for MMC driver > net: designware: socfpga: Add ATF support for MAC driver > arm: socfpga: soc64: Add ATF support for Reset Manager driver > arm: socfpga: soc64: Add ATF support for FPGA reconfig driver > arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to > mbox_reset_cold() > arm: socfpga: soc64: SSBL shall not setup stack on OCRAM > arm: socfpga: soc64: Skip handoff data access in SSBL > configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF > support > > Pali Rohár (1): > Makefile: Fix calling make with V=1 > > Siew Chin Lim (2): > arm: socfpga: dts: soc64: Add binman node of FIT image with ATF > support > arm: socfpga: soc64: Enable FIT image generation using binman > > Simon Glass (5): > odroid-c2: Use devicetree for SMBIOS settings > arm64: mvebu: Use devicetree for SMBIOS settings on uDPU > x86: galileo: Use devicetree for SMBIOS settings > x86: Provide default SMBIOS manufacturer/product > smbios: Drop the unused Kconfig options > > -- > 2.13.0
Re: [v2 00/22] Add Intel Diamond Mesa SoC support
Hi Siew, On Tue, Nov 10, 2020 at 1:56 PM Siew Chin Lim wrote: > > This is the 2nd version of patchset add Intel Diamond Mesa SoC[1] support. > > Intel Diamond Mesa SoC is with a 64-bit quad core ARM Cortex-A53 MPCore > hard processor system (HPS). New IPs in Diamond Mesa are clock manager > and DDR subsystem, other IPs have minor changes compared to Agilex. > > Patch status: > Have changes: Patch 20, 22 > Other patches unchanged. > > Detail changelog can find in commit message. > > v1->v2: > > Patch 20: > - Include binman node device tree object (socfpga_soc64_fit-u-boot.dtsi_ in > socfpga_dm-u-boot.dtsi > > Patch 22: > - Add "CONFIG_USE_SPL_FIT_GENERATE is not set" to socfpga_dm_atf_defconfig. > Use binman to generate > FIT image instead of local script. > > > History: > > [v1]: > https://patchwork.ozlabs.org/project/uboot/cover/20200922094930.100855-1-elly.siew.chin@intel.com/ > > > These patchsets have dependency on: > > Enable ARM Trusted Firmware for U-Boot > https://patchwork.ozlabs.org/project/uboot/cover/20201015122955.10259-1-elly.siew.chin@intel.com/ > > > [1]: > https://www.intel.com/content/www/us/en/products/programmable/asic/easic-devices/diamond-mesa-soc-devices.html > > > Chee Hong Ang (14): > arm: socfpga: Add function for checking description from FIT image > arm: socfpga: soc64: Load FIT image with ATF support > arm: socfpga: soc64: Override 'lowlevel_init' to support ATF > arm: socfpga: Disable "spin-table" method for booting Linux > arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA > (64bits) > arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP > services > mmc: dwmmc: socfpga: Add ATF support for MMC driver > net: designware: socfpga: Add ATF support for MAC driver > arm: socfpga: soc64: Add ATF support for Reset Manager driver > arm: socfpga: soc64: Add ATF support for FPGA reconfig driver > arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to > mbox_reset_cold() > arm: socfpga: soc64: SSBL shall not setup stack on OCRAM > arm: socfpga: soc64: Skip handoff data access in SSBL > configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF > support > > Pali Rohár (1): > Makefile: Fix calling make with V=1 > > Siew Chin Lim (2): > arm: socfpga: dts: soc64: Add binman node of FIT image with ATF > support > arm: socfpga: soc64: Enable FIT image generation using binman > > Simon Glass (5): > odroid-c2: Use devicetree for SMBIOS settings > arm64: mvebu: Use devicetree for SMBIOS settings on uDPU > x86: galileo: Use devicetree for SMBIOS settings > x86: Provide default SMBIOS manufacturer/product > smbios: Drop the unused Kconfig options The above patches are already in u-boot/master now. You can drop these patches. Regards, Bin
[v2 20/22] arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support
Add binman node to device tree to generate the FIT image for u-boot
(u-boot.itb) and OS kernel (kernel.itb).
u-boot.itb contains arm trusted firmware (ATF), u-boot proper and
u-boot device tree for ATF u-boot flow.
kernel.itb contains Linux Image and Linux device tree.
Signed-off-by: Siew Chin Lim
---
arch/arm/dts/socfpga_agilex-u-boot.dtsi | 4 +-
arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 120 +++
arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 8 ++
arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 4 +-
4 files changed, 134 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_stratix10-u-boot.dtsi
diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
index f0528a9ad9..08f7cf7f7a 100644
--- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
@@ -2,9 +2,11 @@
/*
* U-Boot additions
*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2019-2020 Intel Corporation
*/
+#include "socfpga_soc64_fit-u-boot.dtsi"
+
/{
memory {
#address-cells = <2>;
diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
new file mode 100644
index 00..2d4d56a6df
--- /dev/null
+++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#if defined(CONFIG_FIT)
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+&binman {
+ u-boot {
+ filename = "u-boot.itb";
+ fit {
+ fit,external-offset = ;
+ description = "FIT with firmware and bootloader";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ description = "U-Boot SoC64";
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <0x0020>;
+
+ uboot_blob: blob {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ os = "arm-trusted-firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x1000>;
+ entry = <0x1000>;
+
+ atf_blob: blob {
+ filename = "bl31.bin";
+ };
+ };
+
+ fdt {
+ description = "U-Boot SoC64 flat
device-tree";
+ type = "flat_dt";
+ compression = "none";
+
+ uboot_fdt_blob: blob {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf";
+ conf {
+ description = "Intel SoC64 FPGA";
+ firmware = "atf";
+ loadables = "uboot";
+ fdt = "fdt";
+ };
+ };
+ };
+ };
+
+ kernel {
+ filename = "kernel.itb";
+ fit {
+ description = "FIT with Linux kernel image and FDT
blob";
+ #address-cells = <1>;
+
+ images {
+ kernel {
+ description = "Linux Kernel";
+ type = "kernel";
+ arch = "arm64";
+ os = "linux";
+ compression = "none";
+ load = <0x408>;
+ entry = <0x408>;
+
+ kernel_bl
[v2 22/22] configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support
From: Chee Hong Ang Booting Agilex and Stratix 10 with ATF support. SPL now loads ATF (BL31), U-Boot proper and DTB from FIT image. The new boot flow with ATF support is as follow: SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux) U-Boot proper now starts at 0x20 (CONFIG_SYS_TEXT_BASE). ATF will occupy the address range starting from 0x1000. Signed-off-by: Chee Hong Ang Signed-off-by: Siew Chin Lim --- configs/socfpga_agilex_atf_defconfig| 72 configs/socfpga_stratix10_atf_defconfig | 74 + 2 files changed, 146 insertions(+) create mode 100644 configs/socfpga_agilex_atf_defconfig create mode 100644 configs/socfpga_stratix10_atf_defconfig diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig new file mode 100644 index 00..ad87a8098f --- /dev/null +++ b/configs/socfpga_agilex_atf_defconfig @@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x20 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x200 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y +CONFIG_IDENT_STRING="socfpga_agilex" +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_TEXT_BASE=0xFFE0 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200 +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon" +CONFIG_SPL_CACHE=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x0200 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_MTD=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig new file mode 100644 index 00..1005ba979e --- /dev/null +++ b/configs/socfpga_stratix10_atf_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x20 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x200 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y +CONFIG_IDENT_STRING="socfpga_stratix10" +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_TEXT_BASE=0xFFE0 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200 +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon" +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x0200 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_FPGA_INTEL_PR=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_MTD=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y -- 2.13.0
[v2 21/22] arm: socfpga: soc64: Enable FIT image generation using binman
Add new build target "fit-itb" for FIT image generation. In preparation to support Vendor Authorized Boot (VAB) for Intel SOC64 device in near future. With VAB, u-boot proper, dtb and arm trusted firmware need to be signed before FIT image generation. To align user experience for ATF boot with and without VAB feature, we skip binman for ARCH_SOCFPGA in default Makefile flow. User always use 'make fit-itb' to generate FIT image after successfully compile u-boot. Signed-off-by: Siew Chin Lim --- Makefile | 7 +++ arch/arm/mach-socfpga/Kconfig | 2 ++ 2 files changed, 9 insertions(+) diff --git a/Makefile b/Makefile index 59ba3330cd..b37aaa9561 100644 --- a/Makefile +++ b/Makefile @@ -1021,8 +1021,10 @@ inputs: $(INPUTS-y) all: .binman_stamp inputs ifeq ($(CONFIG_BINMAN),y) +ifneq ($(CONFIG_ARCH_SOCFPGA),y) $(call if_changed,binman) endif +endif # Timestamp file to make sure that binman always runs .binman_stamp: FORCE @@ -1608,6 +1610,11 @@ cmd_socnandboot = catu-boot-spl-padx4.sfp u-boot.img > $@ || rm -f $@ u-boot-with-nand-spl.sfp: u-boot-spl-padx4.sfp u-boot.img FORCE $(call if_changed,socnandboot) +ifeq ($(CONFIG_FIT),y) +fit-itb: + $(call if_changed,binman) +endif + endif ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 01f5a1fc41..7fdb52dd83 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -37,6 +37,7 @@ config TARGET_SOCFPGA_AGILEX select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE select SPL_CLK if SPL + select BINMAN config TARGET_SOCFPGA_ARRIA5 bool @@ -79,6 +80,7 @@ config TARGET_SOCFPGA_STRATIX10 select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN select FPGA_INTEL_SDM_MAILBOX + select BINMAN choice prompt "Altera SOCFPGA board select" -- 2.13.0
[v2 17/22] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold()
From: Chee Hong Ang
mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga/mailbox_s10.c
index 18d44924e6..429444f069 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -398,6 +399,9 @@ error:
int mbox_reset_cold(void)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ psci_system_reset();
+#else
int ret;
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
@@ -406,6 +410,7 @@ int mbox_reset_cold(void)
/* mailbox sent failure, wait for watchdog to kick in */
hang();
}
+#endif
return 0;
}
--
2.13.0
[v2 19/22] arm: socfpga: soc64: Skip handoff data access in SSBL
From: Chee Hong Ang
SPL already setup the Clock Manager with the handoff data
from OCRAM. When the Clock Manager's driver get probed again
in SSBL, it shall skip the handoff data access in OCRAM.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
index 3da85791a1..049c5711a8 100644
--- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
@@ -12,6 +12,7 @@
const struct cm_config * const cm_get_default_config(void)
{
+#ifdef CONFIG_SPL_BUILD
struct cm_config *cm_handoff_cfg = (struct cm_config *)
(S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA);
u32 *conversion = (u32 *)cm_handoff_cfg;
@@ -26,7 +27,7 @@ const struct cm_config * const cm_get_default_config(void)
} else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) {
return cm_handoff_cfg;
}
-
+#endif
return NULL;
}
--
2.13.0
[v2 18/22] arm: socfpga: soc64: SSBL shall not setup stack on OCRAM
From: Chee Hong Ang Since SSBL is running in DRAM, it shall setup the stack in DRAM instead of OCRAM which is occupied by SPL and handoff data. Signed-off-by: Chee Hong Ang --- include/configs/socfpga_soc64_common.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 990f879b07..fdcd7d3e9a 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -40,9 +40,14 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE0 #define CONFIG_SYS_INIT_RAM_SIZE 0x4 +#ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_INIT_RAM_ADDR \ + CONFIG_SYS_INIT_RAM_SIZE \ - S10_HANDOFF_SIZE) +#else +#define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_TEXT_BASE \ + + 0x10) +#endif #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) #define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) -- 2.13.0
[v2 16/22] arm: socfpga: soc64: Add ATF support for FPGA reconfig driver
From: Chee Hong Ang
In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.
Signed-off-by: Chee Hong Ang
---
drivers/fpga/intel_sdm_mb.c | 139
1 file changed, 139 insertions(+)
diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c
index 9a1dc2c0c8..f5fd9a14c2 100644
--- a/drivers/fpga/intel_sdm_mb.c
+++ b/drivers/fpga/intel_sdm_mb.c
@@ -8,11 +8,149 @@
#include
#include
#include
+#include
#include
+#include
#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 6
#define RECONFIG_STATUS_INTERVAL_DELAY_US 100
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+
+#define BITSTREAM_CHUNK_SIZE 0x0
+#define RECONFIG_STATUS_POLL_RETRY_MAX 100
+
+/*
+ * Polling the FPGA configuration status.
+ * Return 0 for success, non-zero for error.
+ */
+static int reconfig_status_polling_resp(void)
+{
+ int ret;
+ unsigned long start = get_timer(0);
+
+ while (1) {
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
+NULL, 0);
+
+ if (!ret)
+ return 0; /* configuration success */
+
+ if (ret != INTEL_SIP_SMC_STATUS_BUSY)
+ return ret;
+
+ if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
+ return -ETIMEDOUT; /* time out */
+
+ puts(".");
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+ WATCHDOG_RESET();
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int send_bitstream(const void *rbf_data, size_t rbf_size)
+{
+ int i;
+ u64 res_buf[3];
+ u64 args[2];
+ u32 xfer_count = 0;
+ int ret, wr_ret = 0, retry = 0;
+ size_t buf_size = (rbf_size > BITSTREAM_CHUNK_SIZE) ?
+ BITSTREAM_CHUNK_SIZE : rbf_size;
+
+ while (rbf_size || xfer_count) {
+ if (!wr_ret && rbf_size) {
+ args[0] = (u64)rbf_data;
+ args[1] = buf_size;
+ wr_ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_WRITE,
+ args, 2, NULL, 0);
+
+ debug("wr_ret = %d, rbf_data = %p, buf_size = %08lx\n",
+ wr_ret, rbf_data, buf_size);
+
+ if (wr_ret)
+ continue;
+
+ rbf_size -= buf_size;
+ rbf_data += buf_size;
+
+ if (buf_size >= rbf_size)
+ buf_size = rbf_size;
+
+ xfer_count++;
+ puts(".");
+ } else {
+ ret = invoke_smc(
+ INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE,
+ NULL, 0, res_buf, ARRAY_SIZE(res_buf));
+ if (!ret) {
+ for (i = 0; i < ARRAY_SIZE(res_buf); i++) {
+ if (!res_buf[i])
+ break;
+ xfer_count--;
+ wr_ret = 0;
+ retry = 0;
+ }
+ } else if (ret !=
+ INTEL_SIP_SMC_STATUS_BUSY)
+ return ret;
+ else if (!xfer_count)
+ return INTEL_SIP_SMC_STATUS_ERROR;
+
+ if (++retry >= RECONFIG_STATUS_POLL_RETRY_MAX)
+ return -ETIMEDOUT;
+
+ udelay(2);
+ }
+ WATCHDOG_RESET();
+ }
+
+ return 0;
+}
+
+/*
+ * This is the interface used by FPGA driver.
+ * Return 0 for success, non-zero for error.
+ */
+int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+ int ret;
+ u64 arg = 1;
+
+ debug("Invoking FPGA_CONFIG_START...\n");
+
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0);
+
+ if (ret) {
+ puts("Failure in RECONFIG mailbox command!\n");
+ return ret;
+ }
+
+ ret = send_bitstream(rbf_data, rbf_size);
+ if (ret) {
+ puts("Error sending bitstream!\n");
+ return ret;
+ }
+
+ /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+
+ debug("Polling with MBOX_RECONFIG_STATUS...\n");
+ ret = reconfig_status_polling_resp();
+ if (ret) {
+ puts("FPGA reconfiguration failed!");
+ return ret;
+ }
+
+ puts("FPGA recon
[v2 13/22] mmc: dwmmc: socfpga: Add ATF support for MMC driver
From: Chee Hong Ang
In non-secure mode (EL2), MMC driver calls the SMC/PSCI services
provided by ATF to set SDMMC's DRVSEL and SMPLSEL.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
drivers/mmc/socfpga_dw_mmc.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 0022f943bd..e5f68fa7fb 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -13,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -48,6 +50,10 @@ static void socfpga_dwmci_reset(struct udevice *dev)
static void socfpga_dwmci_clksel(struct dwmci_host *host)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ u64 args[2];
+#endif
+
struct dwmci_socfpga_priv_data *priv = host->priv;
u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
@@ -58,10 +64,21 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ /* drvsel */
+ args[0] = (sdmmc_mask >> SYSMGR_SDMMC_DRVSEL_SHIFT) & 0x7;
+ /* smplsel */
+ args[1] = (sdmmc_mask >> SYSMGR_SDMMC_SMPLSEL_SHIFT) & 0x7;
+ if (invoke_smc(INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK, args, 2, NULL, 0))
+ dev_err(host->mmc->dev, "SMC call failed in %s\n", __func__);
+
+#else
writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
+#endif
/* Enable SDMMC clock */
setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
--
2.13.0
[v2 15/22] arm: socfpga: soc64: Add ATF support for Reset Manager driver
From: Chee Hong Ang
In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI service provided by ATF to enable/disable the
SOCFPGA bridges.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/reset_manager_s10.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
b/arch/arm/mach-socfpga/reset_manager_s10.c
index 3746e6a60c..af8f2c0873 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -5,11 +5,14 @@
*/
#include
+#include
#include
#include
+#include
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -55,6 +58,15 @@ void socfpga_per_reset_all(void)
void socfpga_bridges_reset(int enable)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ u64 arg = enable;
+
+ int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0);
+ if (ret) {
+ printf("SMC call failed with error %d in %s.\n", ret, __func__);
+ return;
+ }
+#else
u32 reg;
if (enable) {
@@ -101,6 +113,7 @@ void socfpga_bridges_reset(int enable)
/* Disable NOC timeout */
writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
}
+#endif
}
/*
--
2.13.0
[v2 12/22] arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services
From: Chee Hong Ang This header file defines the Secure Monitor Call (SMC) message protocol for ATF (BL31) PSCI runtime services. It includes all the PSCI SiP function identifiers for the secure runtime services provided by ATF. The secure runtime services include System Manager's registers access, 2nd phase bitstream FPGA reconfiguration, Remote System Update (RSU) and etc. Signed-off-by: Chee Hong Ang Signed-off-by: Siew Chin Lim --- include/linux/intel-smc.h | 573 ++ 1 file changed, 573 insertions(+) create mode 100644 include/linux/intel-smc.h diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h new file mode 100644 index 00..cacb410691 --- /dev/null +++ b/include/linux/intel-smc.h @@ -0,0 +1,573 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017-2018, Intel Corporation + */ + +#ifndef __INTEL_SMC_H +#define __INTEL_SMC_H + +#include +#include + +/* + * This file defines the Secure Monitor Call (SMC) message protocol used for + * service layer driver in normal world (EL1) to communicate with secure + * monitor software in Secure Monitor Exception Level 3 (EL3). + * + * This file is shared with secure firmware (FW) which is out of u-boot tree. + * + * An ARM SMC instruction takes a function identifier and up to 6 64-bit + * register values as arguments, and can return up to 4 64-bit register + * values. The operation of the secure monitor is determined by the parameter + * values passed in through registers. + + * EL1 and EL3 communicates pointer as physical address rather than the + * virtual address. + */ + +/* + * Functions specified by ARM SMC Calling convention: + * + * FAST call executes atomic operations, returns when the requested operation + * has completed. + * STD call starts a operation which can be preempted by a non-secure + * interrupt. The call can return before the requested operation has + * completed. + * + * a0..a7 is used as register names in the descriptions below, on arm32 + * that translates to r0..r7 and on arm64 to w0..w7. + */ + +#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + +/* + * Return values in INTEL_SIP_SMC_* call + * + * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION: + * Secure monitor software doesn't recognize the request. + * + * INTEL_SIP_SMC_STATUS_OK: + * SMC call completed successfully, + * In case of FPGA configuration write operation, it means secure monitor + * software can accept the next chunk of FPGA configuration data. + * + * INTEL_SIP_SMC_STATUS_BUSY: + * In case of FPGA configuration write operation, it means secure monitor + * software is still processing previous data & can't accept the next chunk + * of data. Service driver needs to issue + * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the + * completed block(s). + * + * INTEL_SIP_SMC_STATUS_ERROR: + * There is error during the SMC call process. + * + * INTEL_SIP_SMC_REG_ERROR: + * There is error during a read or write operation of the protected + * registers. + */ +#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0x +#define INTEL_SIP_SMC_STATUS_OK0x0 +#define INTEL_SIP_SMC_STATUS_BUSY 0x1 +#define INTEL_SIP_SMC_STATUS_REJECTED 0x2 +#define INTEL_SIP_SMC_STATUS_ERROR 0x4 +#define INTEL_SIP_SMC_REG_ERROR0x5 +#define INTEL_SIP_SMC_RSU_ERROR0x7 + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_START + * + * Sync call used by service driver at EL1 to request the FPGA in EL3 to + * be prepare to receive a new configuration. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_START. + * a1: flag for full or partial configuration + *0 full reconfiguration. + *1 partial reconfiguration. + * a2-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR. + * a1-3: not used. + */ +#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1 +#define INTEL_SIP_SMC_FPGA_CONFIG_START \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START) + +/* + * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE + * + * Async call used by service driver at EL1 to provide FPGA configuration data + * to secure world. + * + * Call register usage: + * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE. + * a1: 64bit physical address of the configuration data memory block + * a2: Size of configuration data block. + * a3-7: not used. + * + * Return status: + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY, + * INTEL_SIP_SMC_STATUS_REJECTED or INTEL_SIP_SMC_STATUS_ERROR. + * a1: 64bit physical address of 1st completed memory block if any completed + * block, o
[v2 14/22] net: designware: socfpga: Add ATF support for MAC driver
From: Chee Hong Ang
In non-secure mode (EL2), MAC driver calls the SMC/PSCI services
provided by ATF to setup the PHY interface.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
drivers/net/dwmac_socfpga.c | 30 ++
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c
index e93561dffa..a2d09d5c4a 100644
--- a/drivers/net/dwmac_socfpga.c
+++ b/drivers/net/dwmac_socfpga.c
@@ -17,7 +17,9 @@
#include
#include
+#include
#include
+#include
struct dwmac_socfpga_platdata {
struct dw_eth_pdata dw_eth_pdata;
@@ -64,6 +66,27 @@ static int dwmac_socfpga_ofdata_to_platdata(struct udevice
*dev)
return designware_eth_ofdata_to_platdata(dev);
}
+static int dwmac_socfpga_do_setphy(struct udevice *dev, u32 modereg)
+{
+ struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ u64 args[2];
+
+ args[0] = ((u64)pdata->phy_intf - socfpga_get_sysmgr_addr() -
+ SYSMGR_SOC64_EMAC0) >> 2;
+ args[1] = modereg;
+
+ if (invoke_smc(INTEL_SIP_SMC_HPS_SET_PHYINTF, args, 2, NULL, 0))
+ return -EIO;
+#else
+ clrsetbits_le32(pdata->phy_intf, SYSMGR_EMACGRP_CTRL_PHYSEL_MASK <<
+ pdata->reg_shift, modereg << pdata->reg_shift);
+#endif
+
+ return 0;
+}
+
static int dwmac_socfpga_probe(struct udevice *dev)
{
struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
@@ -71,7 +94,6 @@ static int dwmac_socfpga_probe(struct udevice *dev)
struct reset_ctl_bulk reset_bulk;
int ret;
u32 modereg;
- u32 modemask;
switch (edata->phy_interface) {
case PHY_INTERFACE_MODE_MII:
@@ -97,9 +119,9 @@ static int dwmac_socfpga_probe(struct udevice *dev)
reset_assert_bulk(&reset_bulk);
- modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
- clrsetbits_le32(pdata->phy_intf, modemask,
- modereg << pdata->reg_shift);
+ ret = dwmac_socfpga_do_setphy(dev, modereg);
+ if (ret)
+ return ret;
reset_release_bulk(&reset_bulk);
--
2.13.0
[v2 11/22] arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits)
From: Chee Hong Ang
invoke_smc() allow U-Boot proper running in non-secure mode (EL2)
to invoke SMC call to ATF's PSCI runtime services such as
System Manager's registers access, 2nd phase bitstream FPGA
reconfiguration, Remote System Update (RSU) and etc.
smc_send_mailbox() is a send mailbox command helper function which invokes
the ATF's PSCI runtime service (function ID: INTEL_SIP_SMC_MBOX_SEND_CMD)
to send mailbox messages to Secure Device Manager (SDM).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/Makefile | 2 +
arch/arm/mach-socfpga/include/mach/smc_api.h | 13 +++
arch/arm/mach-socfpga/smc_api.c | 56
3 files changed, 71 insertions(+)
create mode 100644 arch/arm/mach-socfpga/include/mach/smc_api.h
create mode 100644 arch/arm/mach-socfpga/smc_api.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index c63162a5c6..0b05283a7a 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -72,6 +72,8 @@ ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += firewall.o
obj-y += spl_agilex.o
endif
+else
+obj-$(CONFIG_SPL_ATF) += smc_api.o
endif
ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/include/mach/smc_api.h
b/arch/arm/mach-socfpga/include/mach/smc_api.h
new file mode 100644
index 00..bbefdd8dd9
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/smc_api.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#ifndef _SMC_API_H_
+#define _SMC_API_H_
+
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len);
+int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
+u32 *resp_buf);
+
+#endif /* _SMC_API_H_ */
diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c
new file mode 100644
index 00..085daba162
--- /dev/null
+++ b/arch/arm/mach-socfpga/smc_api.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len)
+{
+ struct pt_regs regs;
+
+ memset(®s, 0, sizeof(regs));
+ regs.regs[0] = func_id;
+
+ if (args)
+ memcpy(®s.regs[1], args, arg_len * sizeof(*args));
+
+ smc_call(®s);
+
+ if (ret_arg)
+ memcpy(ret_arg, ®s.regs[1], ret_len * sizeof(*ret_arg));
+
+ return regs.regs[0];
+}
+
+int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
+u32 *resp_buf)
+{
+ int ret;
+ u64 args[6];
+ u64 resp[3];
+
+ args[0] = cmd;
+ args[1] = (u64)arg;
+ args[2] = len;
+ args[3] = urgent;
+ args[4] = (u64)resp_buf;
+ if (resp_buf_len)
+ args[5] = *resp_buf_len;
+ else
+ args[5] = 0;
+
+ ret = invoke_smc(INTEL_SIP_SMC_MBOX_SEND_CMD, args, ARRAY_SIZE(args),
+resp, ARRAY_SIZE(resp));
+
+ if (ret == INTEL_SIP_SMC_STATUS_OK && resp_buf && resp_buf_len) {
+ if (!resp[0])
+ *resp_buf_len = resp[1];
+ }
+
+ return (int)resp[0];
+}
--
2.13.0
[v2 09/22] arm: socfpga: soc64: Override 'lowlevel_init' to support ATF
From: Chee Hong Ang Override 'lowlevel_init' to make sure secondary CPUs trapped in ATF instead of SPL. After ATF is initialized, it will signal the secondary CPUs to jump from SPL to ATF waiting to be 'activated' by Linux OS via PSCI call. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/Makefile | 2 + arch/arm/mach-socfpga/lowlevel_init_soc64.S | 76 + 2 files changed, 78 insertions(+) create mode 100644 arch/arm/mach-socfpga/lowlevel_init_soc64.S diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 418f543b20..c63162a5c6 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -29,6 +29,7 @@ endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o +obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o @@ -41,6 +42,7 @@ endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += clock_manager_agilex.o +obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S new file mode 100644 index 00..612ea8a037 --- /dev/null +++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#include +#include +#include +#include + +ENTRY(lowlevel_init) + mov x29, lr /* Save LR */ + +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +wait_for_atf: + ldr x4, =CPU_RELEASE_ADDR + ldr x5, [x4] + cbz x5, slave_wait_atf + br x5 +slave_wait_atf: + branch_if_slave x0, wait_for_atf +#else + branch_if_slave x0, 1f +#endif + ldr x0, =GICD_BASE + bl gic_init_secure +1: +#if defined(CONFIG_GICV3) + ldr x0, =GICR_BASE + bl gic_init_secure_percpu +#elif defined(CONFIG_GICV2) + ldr x0, =GICD_BASE + ldr x1, =GICC_BASE + bl gic_init_secure_percpu +#endif +#endif + +#ifdef CONFIG_ARMV8_MULTIENTRY + branch_if_master x0, x1, 2f + + /* +* Slave should wait for master clearing spin table. +* This sync prevent slaves observing incorrect +* value of spin table and jumping to wrong place. +*/ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#ifdef CONFIG_GICV2 + ldr x0, =GICC_BASE +#endif + bl gic_wait_for_interrupt +#endif + + /* +* All slaves will enter EL2 and optionally EL1. +*/ + adr x4, lowlevel_in_el2 + ldr x5, =ES_TO_AARCH64 + bl armv8_switch_to_el2 + +lowlevel_in_el2: +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + adr x4, lowlevel_in_el1 + ldr x5, =ES_TO_AARCH64 + bl armv8_switch_to_el1 + +lowlevel_in_el1: +#endif + +#endif /* CONFIG_ARMV8_MULTIENTRY */ + +2: + mov lr, x29 /* Restore LR */ + ret +ENDPROC(lowlevel_init) -- 2.13.0
[v2 08/22] arm: socfpga: soc64: Load FIT image with ATF support
From: Chee Hong Ang
Instead of loading u-boot proper image (u-boot.img), SPL
now loads FIT image (u-boot.itb) which includes u-boot
proper, ATF and u-boot proper's DTB.
For OS, u-boot now loads FIT images (kernel.itb) which
includes Linux Image and Linux's DTB.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_soc64_common.h | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/include/configs/socfpga_soc64_common.h
b/include/configs/socfpga_soc64_common.h
index fb5e2e8aaf..990f879b07 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -78,12 +78,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
* CONFIG_BOOTARGS goes into the environment value "bootargs".
* Do note the value will override also the chosen node in FDT blob.
*/
+
+#ifdef CONFIG_FIT
+#define CONFIG_BOOTFILE "kernel.itb"
+#define CONFIG_BOOTCOMMAND "run fatscript; run mmcfitload;run
linux_qspi_enable;" \
+ "run mmcfitboot"
+#else
+#define CONFIG_BOOTFILE "Image"
#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;"
\
"run mmcboot"
+#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
- "bootfile=Image\0" \
+ "bootfile=" CONFIG_BOOTFILE "\0" \
"fdt_addr=800\0" \
"fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"mmcroot=/dev/mmcblk0p2\0" \
@@ -93,6 +101,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
"mmcload=mmc rescan;" \
"load mmc 0:1 ${loadaddr} ${bootfile};" \
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootm ${loadaddr}\0" \
+ "mmcfitload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
"linux_qspi_enable=if sf probe; then " \
"echo Enabling QSPI at Linux DTB...;" \
"fdt addr ${fdt_addr}; fdt resize;" \
@@ -193,6 +206,10 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
- CONFIG_SYS_SPL_MALLOC_SIZE)
/* SPL SDMMC boot support */
+#ifdef CONFIG_SPL_LOAD_FIT
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.itb"
+#else
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img"
+#endif
#endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */
--
2.13.0
[v2 10/22] arm: socfpga: Disable "spin-table" method for booting Linux
From: Chee Hong Ang Standard PSCI function "CPU_ON" provided by ATF is now used by Linux kernel to bring up the secondary CPUs to enable SMP booting in Linux on SoC 64bits platform. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 26f2cf8e47..01f5a1fc41 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -33,7 +33,6 @@ config TARGET_SOCFPGA_AGILEX bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN - select ARMV8_SPIN_TABLE select CLK select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE @@ -79,7 +78,6 @@ config TARGET_SOCFPGA_STRATIX10 bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN - select ARMV8_SPIN_TABLE select FPGA_INTEL_SDM_MAILBOX choice -- 2.13.0
[v2 07/22] arm: socfpga: Add function for checking description from FIT image
From: Chee Hong Ang
Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do nothing for now.
Users are allowed to override this 'weak' function in their
specific board implementation.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/board.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 340abf9305..7993c27646 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -13,7 +13,7 @@
#include
#include
#include
-
+#include
#include
#include
@@ -87,3 +87,13 @@ int g_dnl_board_usb_cable_connected(void)
return 1;
}
#endif
+
+#ifdef CONFIG_SPL_BUILD
+__weak int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
--
2.13.0
[v2 05/22] smbios: Drop the unused Kconfig options
From: Simon Glass Now that we can use devicetree to specify this information, drop the old CONFIG options. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- configs/clearfog_gt_8k_defconfig| 2 -- configs/mt7622_rfb_defconfig| 1 - configs/mvebu_db_armada8k_defconfig | 2 -- configs/r8a774a1_beacon_defconfig | 2 -- configs/r8a77970_eagle_defconfig| 2 -- configs/r8a77980_condor_defconfig | 2 -- configs/r8a77990_ebisu_defconfig| 2 -- configs/r8a77995_draak_defconfig| 2 -- configs/rcar3_salvator-x_defconfig | 2 -- configs/rcar3_ulcb_defconfig| 2 -- lib/Kconfig | 16 - lib/smbios.c| 46 +++-- 12 files changed, 13 insertions(+), 68 deletions(-) diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig index 552df3a8b8..9bb1f212a7 100644 --- a/configs/clearfog_gt_8k_defconfig +++ b/configs/clearfog_gt_8k_defconfig @@ -12,7 +12,6 @@ CONFIG_DM_GPIO=y CONFIG_DEBUG_UART_BASE=0xf0512000 CONFIG_DEBUG_UART_CLOCK=2 CONFIG_DEFAULT_DEVICE_TREE="armada-8040-clearfog-gt-8k" -CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y @@ -78,4 +77,3 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SMBIOS_MANUFACTURER="" diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig index a6089d6cf6..ccf926e104 100644 --- a/configs/mt7622_rfb_defconfig +++ b/configs/mt7622_rfb_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_TEXT_BASE=0x41e0 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 CONFIG_DEFAULT_DEVICE_TREE="mt7622-rfb" -CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_FIT=y CONFIG_DEFAULT_FDT_FILE="mt7622-rfb" CONFIG_LOGLEVEL=7 diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig index a88d5cc98b..5d8a1b655c 100644 --- a/configs/mvebu_db_armada8k_defconfig +++ b/configs/mvebu_db_armada8k_defconfig @@ -11,7 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x1 CONFIG_DEBUG_UART_BASE=0xf0512000 CONFIG_DEBUG_UART_CLOCK=2 CONFIG_DEFAULT_DEVICE_TREE="armada-8040-db" -CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y @@ -72,4 +71,3 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SMBIOS_MANUFACTURER="" diff --git a/configs/r8a774a1_beacon_defconfig b/configs/r8a774a1_beacon_defconfig index 5d564d82c2..2f45edd92e 100644 --- a/configs/r8a774a1_beacon_defconfig +++ b/configs/r8a774a1_beacon_defconfig @@ -8,7 +8,6 @@ CONFIG_RCAR_GEN3=y CONFIG_TARGET_BEACON_RZG2M=y # CONFIG_SPL is not set CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-beacon-rzg2m-kit" -CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set @@ -64,4 +63,3 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SMBIOS_MANUFACTURER="" diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig index a777484235..9dbe0e1d5b 100644 --- a/configs/r8a77970_eagle_defconfig +++ b/configs/r8a77970_eagle_defconfig @@ -11,7 +11,6 @@ CONFIG_SPL_TEXT_BASE=0xe6318000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_EAGLE=y CONFIG_DEFAULT_DEVICE_TREE="r8a77970-eagle-u-boot" -CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y @@ -74,4 +73,3 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SMBIOS_MANUFACTURER="" diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig index 4e457234ed..dbe2912779 100644 --- a/configs/r8a77980_condor_defconfig +++ b/configs/r8a77980_condor_defconfig @@ -11,7 +11,6 @@ CONFIG_SPL_TEXT_BASE=0xe6318000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_CONDOR=y CONFIG_DEFAULT_DEVICE_TREE="r8a77980-condor-u-boot" -CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y @@ -75,4 +74,3 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SMBIOS_MANUFACTURER="" diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index 4667284bb3..cb75b5c3a6 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -10,7 +10,6 @@ CONFIG_SPL_TEXT_BASE=0xe6318000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_EBISU=y CONFIG_DEFAULT_DEVICE_TREE="r8a77990-ebisu-u-boot" -CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y @@ -84,4 +83,3 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SMBIOS_MANUFACTURER="" diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index 5cc0f608da..46a7314fa9 100644 --- a/configs/r8a77995_draak_defconfig +++ b/confi
[v2 04/22] x86: Provide default SMBIOS manufacturer/product
From: Simon Glass
Add a file containing defaults for these, using the existing CONFIG
options. This file must be included with #include since it needs to
be passed through the C preprocessor.
Enable the driver for all x86 boards that generate SMBIOS tables.
Disable it for coral since it has its own driver.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
[bmeng: reword the commit message a little bit]
Signed-off-by: Bin Meng
---
arch/Kconfig | 2 ++
arch/x86/dts/bayleybay.dts| 2 ++
arch/x86/dts/baytrail_som-db5800-som-6867.dts | 2 ++
arch/x86/dts/cherryhill.dts | 2 ++
arch/x86/dts/chromebook_link.dts | 2 ++
arch/x86/dts/chromebook_samus.dts | 2 ++
arch/x86/dts/chromebox_panther.dts| 2 ++
arch/x86/dts/conga-qeval20-qa3-e3845.dts | 2 ++
arch/x86/dts/cougarcanyon2.dts| 2 ++
arch/x86/dts/crownbay.dts | 2 ++
arch/x86/dts/dfi-bt700.dtsi | 2 ++
arch/x86/dts/edison.dts | 2 ++
arch/x86/dts/minnowmax.dts| 2 ++
arch/x86/dts/qemu-x86_i440fx.dts | 2 ++
arch/x86/dts/qemu-x86_q35.dts | 2 ++
arch/x86/dts/smbios.dtsi | 32 +++
configs/chromebook_coral_defconfig| 2 +-
17 files changed, 63 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/dts/smbios.dtsi
diff --git a/arch/Kconfig b/arch/Kconfig
index 3b9fcce980..041e179256 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -198,6 +198,8 @@ config X86
imply RTC_MC146818
imply IRQ
imply ACPIGEN if !QEMU
+ imply SYSINFO if GENERATE_SMBIOS_TABLE
+ imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
# Thing to enable for when SPL/TPL are enabled: SPL
imply SPL_DM
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index d0168e88db..70e5798403 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -16,6 +16,8 @@
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+#include "smbios.dtsi"
+
/ {
model = "Intel Bayley Bay";
compatible = "intel,bayleybay", "intel,baytrail";
diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts
b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
index 5abbc66ce9..a7dc03b645 100644
--- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts
+++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
@@ -16,6 +16,8 @@
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+#include "smbios.dtsi"
+
/ {
model = "Advantech SOM-DB5800-SOM-6867";
compatible = "advantech,som-db5800-som-6867", "intel,baytrail";
diff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts
index 37146fde2b..2ce7f1aa91 100644
--- a/arch/x86/dts/cherryhill.dts
+++ b/arch/x86/dts/cherryhill.dts
@@ -14,6 +14,8 @@
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+#include "smbios.dtsi"
+
/ {
model = "Intel Cherry Hill";
compatible = "intel,cherryhill", "intel,braswell";
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 09488f13b5..e529c4b63e 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -11,6 +11,8 @@
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+#include "smbios.dtsi"
+
/ {
model = "Google Link";
compatible = "google,link", "intel,celeron-ivybridge";
diff --git a/arch/x86/dts/chromebook_samus.dts
b/arch/x86/dts/chromebook_samus.dts
index d8e04a6698..adaeb1ea35 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -9,6 +9,8 @@
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+#include "smbios.dtsi"
+
#ifdef CONFIG_CHROMEOS_VBOOT
#include "chromeos-x86.dtsi"
#include "flashmap-x86-ro.dtsi"
diff --git a/arch/x86/dts/chromebox_panther.dts
b/arch/x86/dts/chromebox_panther.dts
index bcd4c4d9c1..77b6ac9ab9 100644
--- a/arch/x86/dts/chromebox_panther.dts
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -6,6 +6,8 @@
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+#include "smbios.dtsi"
+
/ {
model = "Google Panther";
compatible = "google,panther", "intel,haswell";
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index 70b8c04519..bbea99da2c 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -16,6 +16,8 @@
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+#include "smbios.dtsi"
+
/ {
model = "congatec-QEVAL20-QA3-E3845";
compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail";
diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts
index c6ba811e05..60252e 100644
--- a/arch/x86/dts/cougarcanyon2.dts
+++ b/arch/x86/dts/cougarcanyon2.dts
@@ -14,6 +14,8 @@
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+#include "smbios
[v2 03/22] x86: galileo: Use devicetree for SMBIOS settings
From: Simon Glass
Add settings and enable the default sysinfo driver so that these can come
from the device tree.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
arch/x86/dts/galileo.dts| 28
board/intel/galileo/Kconfig | 11 ---
2 files changed, 28 insertions(+), 11 deletions(-)
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index 5de4568679..501047124e 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -164,4 +164,32 @@
};
};
+ smbios {
+ compatible = "u-boot,sysinfo-smbios";
+
+ /*
+* Override the default product name U-Boot reports in the
+* SMBIOS table, to be compatible with the Intel provided UEFI
+* BIOS, as Linux kernel drivers
+* (drivers/mfd/intel_quark_i2c_gpio.c and
+* drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of
+* it to do different board level configuration.
+*
+* This can be "Galileo" for GEN1 Galileo board.
+*/
+ smbios {
+ system {
+ product = "GalileoGen2";
+ };
+
+ baseboard {
+ product = "GalileoGen2";
+ };
+
+ chassis {
+ product = "GalileoGen2";
+ };
+ };
+ };
+
};
diff --git a/board/intel/galileo/Kconfig b/board/intel/galileo/Kconfig
index 1416c891e8..fb8d94fb5b 100644
--- a/board/intel/galileo/Kconfig
+++ b/board/intel/galileo/Kconfig
@@ -22,15 +22,4 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_1024
select SPI_FLASH_WINBOND
-config SMBIOS_PRODUCT_NAME
- default "GalileoGen2"
- help
- Override the default product name U-Boot reports in the SMBIOS
- table, to be compatible with the Intel provided UEFI BIOS, as
- Linux kernel drivers (drivers/mfd/intel_quark_i2c_gpio.c and
- drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of
- it to do different board level configuration.
-
- This can be "Galileo" for GEN1 Galileo board.
-
endif
--
2.13.0
[v2 00/22] Add Intel Diamond Mesa SoC support
This is the 2nd version of patchset add Intel Diamond Mesa SoC[1] support. Intel Diamond Mesa SoC is with a 64-bit quad core ARM Cortex-A53 MPCore hard processor system (HPS). New IPs in Diamond Mesa are clock manager and DDR subsystem, other IPs have minor changes compared to Agilex. Patch status: Have changes: Patch 20, 22 Other patches unchanged. Detail changelog can find in commit message. v1->v2: Patch 20: - Include binman node device tree object (socfpga_soc64_fit-u-boot.dtsi_ in socfpga_dm-u-boot.dtsi Patch 22: - Add "CONFIG_USE_SPL_FIT_GENERATE is not set" to socfpga_dm_atf_defconfig. Use binman to generate FIT image instead of local script. History: [v1]: https://patchwork.ozlabs.org/project/uboot/cover/20200922094930.100855-1-elly.siew.chin@intel.com/ These patchsets have dependency on: Enable ARM Trusted Firmware for U-Boot https://patchwork.ozlabs.org/project/uboot/cover/20201015122955.10259-1-elly.siew.chin@intel.com/ [1]: https://www.intel.com/content/www/us/en/products/programmable/asic/easic-devices/diamond-mesa-soc-devices.html Chee Hong Ang (14): arm: socfpga: Add function for checking description from FIT image arm: socfpga: soc64: Load FIT image with ATF support arm: socfpga: soc64: Override 'lowlevel_init' to support ATF arm: socfpga: Disable "spin-table" method for booting Linux arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits) arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services mmc: dwmmc: socfpga: Add ATF support for MMC driver net: designware: socfpga: Add ATF support for MAC driver arm: socfpga: soc64: Add ATF support for Reset Manager driver arm: socfpga: soc64: Add ATF support for FPGA reconfig driver arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold() arm: socfpga: soc64: SSBL shall not setup stack on OCRAM arm: socfpga: soc64: Skip handoff data access in SSBL configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support Pali Rohár (1): Makefile: Fix calling make with V=1 Siew Chin Lim (2): arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support arm: socfpga: soc64: Enable FIT image generation using binman Simon Glass (5): odroid-c2: Use devicetree for SMBIOS settings arm64: mvebu: Use devicetree for SMBIOS settings on uDPU x86: galileo: Use devicetree for SMBIOS settings x86: Provide default SMBIOS manufacturer/product smbios: Drop the unused Kconfig options -- 2.13.0
[v2 02/22] arm64: mvebu: Use devicetree for SMBIOS settings on uDPU
From: Simon Glass
Add settings and enable the default sysinfo driver so that these can come
from the device tree.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
arch/arm/dts/armada-3720-uDPU-u-boot.dtsi | 20
configs/uDPU_defconfig| 3 ++-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/armada-3720-uDPU-u-boot.dtsi
b/arch/arm/dts/armada-3720-uDPU-u-boot.dtsi
index ef178bdc86..fdad90ad12 100644
--- a/arch/arm/dts/armada-3720-uDPU-u-boot.dtsi
+++ b/arch/arm/dts/armada-3720-uDPU-u-boot.dtsi
@@ -1,5 +1,25 @@
// SPDX-License-Identifier: GPL-2.0+
+/ {
+ smbios {
+ compatible = "u-boot,sysinfo-smbios";
+
+ smbios {
+ system {
+ product = "uDPU";
+ };
+
+ baseboard {
+ product = "uDPU";
+ };
+
+ chassis {
+ product = "uDPU";
+ };
+ };
+ };
+};
+
&spi0 {
u-boot,dm-pre-reloc;
diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig
index dfab2b306b..ec97489523 100644
--- a/configs/uDPU_defconfig
+++ b/configs/uDPU_defconfig
@@ -11,7 +11,6 @@ CONFIG_DM_GPIO=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=25804800
CONFIG_DEFAULT_DEVICE_TREE="armada-3720-uDPU"
-CONFIG_SMBIOS_PRODUCT_NAME="uDPU"
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
@@ -97,3 +96,5 @@ CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_LZO=y
CONFIG_SPL_LZO=y
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
--
2.13.0
[v2 06/22] Makefile: Fix calling make with V=1
From: Pali Rohár
Calling 'make V=1 all' on Ubuntu 18.04 with gcc version 9.2.1 and GNU Make
version 4.1 fails on error:
scripts/Kbuild.include:220: *** Recursive variable 'echo-cmd' references
itself (eventually). Stop.
As a workaround expand 'echo-cmd' variable via 'call' construction instead
of expanding it directly.
Signed-off-by: Pali Rohár
Reported-by: Patrick Delaunay
Reviewed-by: Patrick Delaunay
Fixes: ae897022d7bd ("Makefile: Fix u-boot-nodtb.bin target")
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index 89c42c1024..59ba3330cd 100644
--- a/Makefile
+++ b/Makefile
@@ -1309,7 +1309,7 @@ init_sp_bss_offset_check: u-boot.dtb FORCE
fi
endif
-shell_cmd = { $(echo-cmd) $(cmd_$(1)); }
+shell_cmd = { $(call echo-cmd,$(1)) $(cmd_$(1)); }
quiet_cmd_objcopy_uboot = OBJCOPY $@
cmd_objcopy_uboot = $(cmd_objcopy) && $(call
shell_cmd,static_rela,$<,$@,$(CONFIG_SYS_TEXT_BASE)) || rm -f $@
--
2.13.0
[v2 01/22] odroid-c2: Use devicetree for SMBIOS settings
From: Simon Glass
Add settings and enable the default sysinfo driver so that these can come
from the device tree.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi | 23 +++
configs/odroid-c2_defconfig | 4 ++--
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi
b/arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi
index 484b40504d..90087b00db 100644
--- a/arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi
+++ b/arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi
@@ -6,6 +6,29 @@
#include "meson-gx-u-boot.dtsi"
+/ {
+ smbios {
+ compatible = "u-boot,sysinfo-smbios";
+
+ smbios {
+ system {
+ manufacturer = "Hardkernel Co., Ltd.";
+ product = "ODROID-C2";
+ };
+
+ baseboard {
+ manufacturer = "Hardkernel Co., Ltd.";
+ product = "ODROID-C2";
+ };
+
+ chassis {
+ manufacturer = "Hardkernel Co., Ltd.";
+ product = "ODROID-C2";
+ };
+ };
+ };
+};
+
&usb0 {
status = "disabled";
};
diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
index 5fdce3b463..f2c9fa7277 100644
--- a/configs/odroid-c2_defconfig
+++ b/configs/odroid-c2_defconfig
@@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=2400
CONFIG_IDENT_STRING=" odroid-c2"
CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
-CONFIG_SMBIOS_PRODUCT_NAME="ODROID-C2"
CONFIG_DEBUG_UART=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
@@ -64,4 +63,5 @@ CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y
CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_SMBIOS_MANUFACTURER="Hardkernel Co., Ltd."
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
--
2.13.0
Re: [PATCH] usb: xhci: fix event trb handling missed
Hi Ran,
On Tue, Nov 10, 2020 at 1:30 PM Bin Meng wrote:
>
> Hi Ran,
>
> On Tue, Sep 22, 2020 at 1:02 PM Ran Wang wrote:
> >
> > In functiion xhci_bulk_tx(), when buffer cross 64KB boundary, it will
>
> typo: function
>
> > send request in more than 1 Transfer TRB by chaining them, but then handle
> > only 1 event TRB to mark request completed.
> >
> > However, on Layerscape platforms (LS1028A, LS1088A, etc), we observe xhci
> > controller will generated more than 1 event TRB sometimes, this cause that
>
> I am not sure if it's fair to say this is Layerscape specific
> behavior. Based on the xHCI spec, the spec indicates 1 event trb
> should be generated when IOC/ISP flag is set to 1 or an error occurs.
Ah, ISP flag is set if the pipe is from an IN endpoint. Currently we have:
/* Only set interrupt on short packet for IN endpoints */
if (usb_pipein(pipe))
field |= TRB_ISP;
Can you verify that if removing the above codes, and without your
changes in this patch, the original issue can be resolved on LS1028?
> I will see if I can reproduce your issue on an x86 board.
>
Note this patch does not apply on top of u-boot/master. Please rebase.
> > function mishandle event TRB in next round call, then system hang due to
> > BUG() checking.
> >
> > This patch adds a loop to make sure the event TRB for last Transfer TRB has
> > to be handled in time.
> >
> > Signed-off-by: Ran Wang
> > ---
> > drivers/usb/host/xhci-ring.c | 17 ++---
> > 1 file changed, 14 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
> > index 092ed6e..d77e058 100644
> > --- a/drivers/usb/host/xhci-ring.c
> > +++ b/drivers/usb/host/xhci-ring.c
> > @@ -578,10 +578,13 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned
> > long pipe,
> > int ret;
> > u32 trb_fields[4];
> > u64 val_64 = virt_to_phys(buffer);
> > + void *last_transfer_trb_addr;
> > + int available_length;
> >
> > debug("dev=%p, pipe=%lx, buffer=%p, length=%d\n",
> > udev, pipe, buffer, length);
> >
> > + available_length = length;
> > ep_index = usb_pipe_ep_index(pipe);
> > virt_dev = ctrl->devs[slot_id];
> >
> > @@ -701,7 +704,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long
> > pipe,
> > trb_fields[2] = length_field;
> > trb_fields[3] = field | (TRB_NORMAL << TRB_TYPE_SHIFT);
> >
> > - queue_trb(ctrl, ring, (num_trbs > 1), trb_fields);
> > + last_transfer_trb_addr = queue_trb(ctrl, ring, (num_trbs >
> > 1), trb_fields);
> >
> > --num_trbs;
> >
> > @@ -714,6 +717,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long
> > pipe,
> >
> > giveback_first_trb(udev, ep_index, start_cycle, start_trb);
> >
> > +again:
> > event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
> > if (!event) {
> > debug("XHCI bulk transfer timed out, aborting...\n");
> > @@ -722,14 +726,21 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned
> > long pipe,
> > udev->act_len = 0;
> > return -ETIMEDOUT;
> > }
> > - field = le32_to_cpu(event->trans_event.flags);
> >
> > + if ((void *)event->trans_event.buffer != last_transfer_trb_addr) {
>
> This should be:
>
> if ((void *)le64_to_cpu(event->trans_event.buffer) != last_transfer_trb_addr)
>
> > + available_length -=
> > +
> > (int)EVENT_TRB_LEN(le32_to_cpu(event->trans_event.transfer_len));
> > + xhci_acknowledge_event(ctrl);
> > + goto again;
> > + }
> > +
> > + field = le32_to_cpu(event->trans_event.flags);
> > BUG_ON(TRB_TO_SLOT_ID(field) != slot_id);
> > BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
> > BUG_ON(*(void **)(uintptr_t)le64_to_cpu(event->trans_event.buffer) -
> > buffer > (size_t)length);
> >
> > - record_transfer_result(udev, event, length);
> > + record_transfer_result(udev, event, available_length);
> > xhci_acknowledge_event(ctrl);
> > xhci_inval_cache((uintptr_t)buffer, length);
> >
Regards,
Bin
Re: [PATCH] usb: xhci: fix event trb handling missed
Hi Ran,
On Tue, Sep 22, 2020 at 1:02 PM Ran Wang wrote:
>
> In functiion xhci_bulk_tx(), when buffer cross 64KB boundary, it will
typo: function
> send request in more than 1 Transfer TRB by chaining them, but then handle
> only 1 event TRB to mark request completed.
>
> However, on Layerscape platforms (LS1028A, LS1088A, etc), we observe xhci
> controller will generated more than 1 event TRB sometimes, this cause that
I am not sure if it's fair to say this is Layerscape specific
behavior. Based on the xHCI spec, the spec indicates 1 event trb
should be generated when IOC/ISP flag is set to 1 or an error occurs.
I will see if I can reproduce your issue on an x86 board.
> function mishandle event TRB in next round call, then system hang due to
> BUG() checking.
>
> This patch adds a loop to make sure the event TRB for last Transfer TRB has
> to be handled in time.
>
> Signed-off-by: Ran Wang
> ---
> drivers/usb/host/xhci-ring.c | 17 ++---
> 1 file changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
> index 092ed6e..d77e058 100644
> --- a/drivers/usb/host/xhci-ring.c
> +++ b/drivers/usb/host/xhci-ring.c
> @@ -578,10 +578,13 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long
> pipe,
> int ret;
> u32 trb_fields[4];
> u64 val_64 = virt_to_phys(buffer);
> + void *last_transfer_trb_addr;
> + int available_length;
>
> debug("dev=%p, pipe=%lx, buffer=%p, length=%d\n",
> udev, pipe, buffer, length);
>
> + available_length = length;
> ep_index = usb_pipe_ep_index(pipe);
> virt_dev = ctrl->devs[slot_id];
>
> @@ -701,7 +704,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long
> pipe,
> trb_fields[2] = length_field;
> trb_fields[3] = field | (TRB_NORMAL << TRB_TYPE_SHIFT);
>
> - queue_trb(ctrl, ring, (num_trbs > 1), trb_fields);
> + last_transfer_trb_addr = queue_trb(ctrl, ring, (num_trbs >
> 1), trb_fields);
>
> --num_trbs;
>
> @@ -714,6 +717,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long
> pipe,
>
> giveback_first_trb(udev, ep_index, start_cycle, start_trb);
>
> +again:
> event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
> if (!event) {
> debug("XHCI bulk transfer timed out, aborting...\n");
> @@ -722,14 +726,21 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long
> pipe,
> udev->act_len = 0;
> return -ETIMEDOUT;
> }
> - field = le32_to_cpu(event->trans_event.flags);
>
> + if ((void *)event->trans_event.buffer != last_transfer_trb_addr) {
This should be:
if ((void *)le64_to_cpu(event->trans_event.buffer) != last_transfer_trb_addr)
> + available_length -=
> +
> (int)EVENT_TRB_LEN(le32_to_cpu(event->trans_event.transfer_len));
> + xhci_acknowledge_event(ctrl);
> + goto again;
> + }
> +
> + field = le32_to_cpu(event->trans_event.flags);
> BUG_ON(TRB_TO_SLOT_ID(field) != slot_id);
> BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
> BUG_ON(*(void **)(uintptr_t)le64_to_cpu(event->trans_event.buffer) -
> buffer > (size_t)length);
>
> - record_transfer_result(udev, event, length);
> + record_transfer_result(udev, event, available_length);
> xhci_acknowledge_event(ctrl);
> xhci_inval_cache((uintptr_t)buffer, length);
>
Regards,
Bin
[PATCH] rockchip: Enable BINMAN for boards enable SPL_OPTEE
Rockchip has many 32bit SoCs and some of them are support SPL_OPTEE now,
only boards with SPL_OPTEE support can fit BINMAN well, other boards
will fail at initr_binman() in U-Boot proper after below patch,
eg. rv1108 board.
83187546ae binman: Support multiple images in the library
Fixes: 79030a4861 ("rockchip: Add Single boot image (with binman, pad_cat)")
Signed-off-by: Kever Yang
---
arch/arm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b2f7fcbd6e..5903c09370 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1721,7 +1721,7 @@ config ARCH_STM32MP
config ARCH_ROCKCHIP
bool "Support Rockchip SoCs"
select BLK
- select BINMAN if !ARM64
+ select BINMAN if SPL_OPTEE
select DM
select DM_GPIO
select DM_I2C
--
2.25.1
Please pull u-boot-x86
Hi Tom, This PR includes the following x86 changes for v2021.01 release: - Avoid using hardcoded number of variable range MTRRs in mtrr_commit() - coral: Correct max98357 file - coral: Update smbios tables to latest definition Azure results: PASS https://dev.azure.com/bmeng/GitHub/_build/results?buildId=300&view=results The following changes since commit 1ae955e3a58f46918ef99b0b6c562967ba1bf39e: Prepare v2021.01-rc2 (2020-11-09 17:20:05 -0500) are available in the git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-x86 for you to fetch changes up to ca010674edb289b1f623e83b4529b6d9ae5e5c0d: x86: coral: Update smbios tables to latest definition (2020-11-10 09:44:20 +0800) Bin Meng (1): x86: Avoid using hardcoded number of variable range MTRRs in mtrr_commit() Simon Glass (2): x86: coral: Correct max98357 file x86: coral: Update smbios tables to latest definition arch/x86/cpu/mtrr.c | 2 +- arch/x86/dts/chromebook_coral.dts | 27 +-- board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat | Bin 0 -> 116 bytes 3 files changed, 22 insertions(+), 7 deletions(-) Regards, Bin
Re: [PATCH 1/3] x86: coral: Update smbios tables to latest definition
On Tue, Nov 10, 2020 at 9:43 AM Bin Meng wrote: > > On Mon, Nov 9, 2020 at 10:12 PM Simon Glass wrote: > > > > The accepted binding uses multiple nodes, one for each table type. Update > > coral accordingly. > > > > Signed-off-by: Simon Glass > > --- > > > > arch/x86/dts/chromebook_coral.dts | 27 +-- > > 1 file changed, 21 insertions(+), 6 deletions(-) > > > > Reviewed-by: Bin Meng applied to u-boot-x86, thanks!
Re: [PATCH 1/3] x86: coral: Update smbios tables to latest definition
On Mon, Nov 9, 2020 at 10:12 PM Simon Glass wrote: > > The accepted binding uses multiple nodes, one for each table type. Update > coral accordingly. > > Signed-off-by: Simon Glass > --- > > arch/x86/dts/chromebook_coral.dts | 27 +-- > 1 file changed, 21 insertions(+), 6 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH] x86: coral: Correct max98357 file
On Tue, Nov 10, 2020 at 9:34 AM Bin Meng wrote: > > Hi Simon, > > On Mon, Nov 9, 2020 at 9:41 PM Simon Glass wrote: > > > > This somehow ended up as an empty file. Fix it. > > > > Signed-off-by: Simon Glass > > --- > > > > .../max98357-render-2ch-48khz-24b.dat | Bin 0 -> 116 bytes > > 1 file changed, 0 insertions(+), 0 deletions(-) > > > > Acked-by: Bin Meng applied to u-boot-x86, thanks!
Re: [PATCH] x86: coral: Correct max98357 file
Hi Simon, On Mon, Nov 9, 2020 at 9:41 PM Simon Glass wrote: > > This somehow ended up as an empty file. Fix it. > > Signed-off-by: Simon Glass > --- > > .../max98357-render-2ch-48khz-24b.dat | Bin 0 -> 116 bytes > 1 file changed, 0 insertions(+), 0 deletions(-) > Acked-by: Bin Meng It seems that this patch did not arrive on patchwork, just as last time in v3. That's probably why it was missed last time. Regards, Bin
Re: [PATCH] x86: Avoid using hardcoded number of variable range MTRRs in mtrr_commit()
On Tue, Nov 10, 2020 at 12:05 AM Simon Glass wrote:
>
> Hi Bin,
>
> On Mon, 9 Nov 2020 at 01:05, Bin Meng wrote:
> >
> > Since commit 29d2d64ed55f ("x86: Add support for more than 8 MTRRs"),
> > the maximum number of variable range MTRRs was increased from 8 to 10,
> > which caused a #GP exception during VESA video driver probe.
> >
> > On the BayTrail platform there are only 8 variable range MTRRs. In
> > mtrr_commit() it still uses MTRR_MAX_COUNT which should have been
> > updated to use dynamically probed number.
> >
> > This fixes the boot failure seen on Intel Minnow Max board.
> >
> > Fixes: 29d2d64ed55f ("x86: Add support for more than 8 MTRRs")
> > Signed-off-by: Bin Meng
> > ---
> >
> > arch/x86/cpu/mtrr.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
>
> Reviewed-by: Simon Glass
applied to u-boot-x86, thanks!
Re: [PATCH] x86: Avoid using hardcoded number of variable range MTRRs in mtrr_commit()
Hi Simon,
On Tue, Nov 10, 2020 at 12:05 AM Simon Glass wrote:
>
> Hi Bin,
>
> On Mon, 9 Nov 2020 at 01:05, Bin Meng wrote:
> >
> > Since commit 29d2d64ed55f ("x86: Add support for more than 8 MTRRs"),
> > the maximum number of variable range MTRRs was increased from 8 to 10,
> > which caused a #GP exception during VESA video driver probe.
> >
> > On the BayTrail platform there are only 8 variable range MTRRs. In
> > mtrr_commit() it still uses MTRR_MAX_COUNT which should have been
> > updated to use dynamically probed number.
> >
> > This fixes the boot failure seen on Intel Minnow Max board.
> >
> > Fixes: 29d2d64ed55f ("x86: Add support for more than 8 MTRRs")
> > Signed-off-by: Bin Meng
> > ---
> >
> > arch/x86/cpu/mtrr.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
>
> Reviewed-by: Simon Glass
>
> I don't actually see the boot failure in my lab, but this looks right to me.
That's weird :)
Regards,
Bin
Re: [PATCH] cros_ec: Support keyboard scanning with EC_CMD_GET_NEXT_EVENT
On 09/11/2020 22:37, Simon Glass wrote:
> Hi Heinrich,
>
> On Mon, 9 Nov 2020 at 12:34, Heinrich Schuchardt wrote:
>>
>> On 10/30/20 6:25 PM, Alper Nebi Yasak wrote:
>>> The cros_ec_keyb driver currently uses EC_CMD_MKBP_STATE to scan the
>>> keyboard, but this host command was superseded by EC_CMD_GET_NEXT_EVENT
>>
>> This patch has been applied to origin/master.
>>
>> Now when I compile sandbox_defconfig and run './u-boot -D' it spits out
>> zillions of
>>
>>** Unknown EC command 0x67
>>** Unknown EC command 0x67
>>** Unknown EC command 0x67
>>** Unknown EC command 0x67
>>** Unknown EC command 0x67
>>** Unknown EC command 0x67
>>** Unknown EC command 0x67
>>** Unknown EC command 0x67
>>
>> When I revert the patch the messages are gone.
>>
>> So something is really missing in this patch.
>
> Test coverage, for a start!
>
> I think the EC emulator needs to be updated for the new command.
>
> Alper, can you please take a look?
>
I can get the messages to stop with the following, does it look good to
you?
case EC_CMD_ENTERING_MODE:
len = 0;
break;
+ case EC_CMD_GET_NEXT_EVENT: {
+ struct ec_response_get_next_event *resp = resp_data;
+ resp->event_type = EC_MKBP_EVENT_KEY_MATRIX;
+ cros_ec_keyscan(ec, resp->data.key_matrix);
+ len = sizeof(*resp);
+ break;
+ }
default:
printf(" ** Unknown EC command %#02x\n", req_hdr->command);
return -1;
That's more or less only what the cros-ec-keyb counterpart expects. But
it doesn't test the -EC_RES_UNAVAILABLE thing or the fallback to the old
method.
Re: [PATCH v3] sunxi: a64: Add a defconfig for the PinePhone
On 03/11/2020 03:32, Samuel Holland wrote: > The PinePhone is a smartphone produced by Pine64, with an A64 SoC, > 2 or 3 GiB LPDDR3 RAM, 16 or 32 GiB eMMC, 720x1440 MIPI-DSI panel, > and Quectel EG25-G modem. > > There are two main board revisions: 1.1 for early adopters, and 1.2 > for mass production. Since there is code to detect the board revision > at boot, one config/image can support both boards. > > Acked-by: Maxime Ripard > Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Thanks, Andre > --- > > Changes v2->v3: > - All other patches merged > - Added entry to MAINTAINERS > > Changes v1->v2: > - Regenerated defconfig with `make savedefconfig` > - Added Acked-by tag > > board/sunxi/MAINTAINERS | 5 + > configs/pinephone_defconfig | 12 > 2 files changed, 17 insertions(+) > create mode 100644 configs/pinephone_defconfig > > diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS > index 1180b86db3..d3755ae41a 100644 > --- a/board/sunxi/MAINTAINERS > +++ b/board/sunxi/MAINTAINERS > @@ -451,6 +451,11 @@ M: Icenowy Zheng > S: Maintained > F: configs/pine_h64_defconfig > > +PINEPHONE BOARD > +M: Samuel Holland > +S: Maintained > +F: configs/pinephone_defconfig > + > R16 EVB PARROT BOARD > M: Quentin Schulz > S: Maintained > diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig > new file mode 100644 > index 00..64ecef59c9 > --- /dev/null > +++ b/configs/pinephone_defconfig > @@ -0,0 +1,12 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_SUNXI=y > +CONFIG_SPL=y > +CONFIG_MACH_SUN50I=y > +CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y > +CONFIG_DRAM_CLK=552 > +CONFIG_DRAM_ZQ=3881949 > +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 > +CONFIG_PINEPHONE_DT_SELECTION=y > +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinephone-1.2" > +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set > +CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.2" >
Re: [PATCH] mmc: meson_gx_mmc: change a clock phase to stable value
Dear Anand, On 11/10/20 4:02 AM, Anand Moon wrote: > Hi Neil, > > On Mon, 9 Nov 2020 at 19:56, Neil Armstrong wrote: >> >> On 09/11/2020 15:10, Mark Kettenis wrote: From: Neil Armstrong Date: Mon, 9 Nov 2020 14:37:09 +0100 Hi, On 09/11/2020 04:12, Jaehoon Chung wrote: > Core clock phase value is changed from 180' to 270'. > It's more stable than before. > - Odroidn-N2/C4 : Working fine with 52MHz > - VIM3 : Working fine with 52MHz > > Before this patch, Odroid-C4 doesn't work fine with 52MHz. > > Signed-off-by: Jaehoon Chung > --- > drivers/mmc/meson_gx_mmc.c | 14 ++ > 1 file changed, 10 insertions(+), 4 deletions(-) > > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c > index 719dd1e5e570..7c60e0566560 100644 > --- a/drivers/mmc/meson_gx_mmc.c > +++ b/drivers/mmc/meson_gx_mmc.c > @@ -52,10 +52,16 @@ static void meson_mmc_config_clock(struct mmc *mmc) > } > clk_div = DIV_ROUND_UP(clk, mmc->clock); > > - /* 180 phase core clock */ > - meson_mmc_clk |= CLK_CO_PHASE_180; > - > - /* 180 phase tx clock */ > + /* > +* Clock Phase needs to set a proper value. > +* It can be changed to other value. > +* Because CORE : 270' Phase and TX : 0' Phase are stable, > +* set to them by default. > +*/ > + /* Core Clock Phase */ > + meson_mmc_clk |= CLK_CO_PHASE_270; > + > + /* TX Clock Phase */ > meson_mmc_clk |= CLK_TX_PHASE_000; > > /* clock settings */ > The previous values were aligned on the Linux driver, which is functional. >>> >>> Actually the Linux driver isn't really functional; the 52 MHz >>> high-speed mode doesn't work. But since HS200 does work in Linux, >>> probably nobody noticed this. >>> >>> That said, I'm not confident a single clock phase setting will work >>> across all Amlogic SoCs and across different boards. Maybe we need >>> something in the device tree such that we can control the values on a >>> per-board level. >>> >> >> So this is specific to SM1 SoCs then, because others families doesn't have >> such issues >> at 52MHz. >> >> So the Linux must be fixes, including the bindings to introduce a new >> compatible, then >> ported to U-Boot. >> >> So in the meantime, it's right to limit to 26MHz on SM1 in U-boot until we >> have all this >> clarified. >> >> Neil > > Earlier I had a similar approach for this FIX but somehow it did not get > merged. > > Please add my > Tested-by: Anand Moon Thanks for testing! Best Regards, Jaehoon Chung > > Best Regards > -Anand >
Re: Fail to reset on Odroid-C4
On 11/9/20 10:38 PM, Neil Armstrong wrote: > On 09/11/2020 09:37, Jaehoon Chung wrote: >> On 11/6/20 7:01 PM, Neil Armstrong wrote: >>> On 06/11/2020 10:59, Jaehoon Chung wrote: Hi, On 11/6/20 6:28 PM, Neil Armstrong wrote: > Hi, > > On 06/11/2020 03:10, Jaehoon Chung wrote: >> Hi, >> >> I have checked U-boot on Odroid-C4 with v2020.10. >> I found a problem about reset behavior. >> >> In my environment, >> - Boot to SD-card, >> - built u-boot v2020.10 with ordoid-c4_defconfig >> - Referred to doc/board/amlogic/odroid-c4.rst >> >> >> If do "reset" command after run command "mmcinfo", it didn't work >> anymore. >> - After something to do operation relevant to MMC. (read/write or ls >> mmc, etc..) >> >> >> U-Boot 2020.10-00383-g2f27fb20151b-dirty (Nov 06 2020 - 10:37:09 +0900) >> odroid-c4 >> >> Model: Hardkernel ODROID-C4 >> SoC: Amlogic Meson SM1 (Unknown) Revision 2b:c (10:2) >> DRAM: 3.8 GiB >> MMC: sd@ffe05000: 0, mmc@ffe07000: 1 >> In:serial >> Out: serial >> Err: serial >> Net: eth0: ethernet@ff3f >> Hit any key to stop autoboot: 0 >> Odroid N2> >> Odroid N2> >> Odroid N2> >> Odroid N2> >> Odroid N2> >> Odroid N2> mmcinfo >> Device: sd@ffe05000 >> Manufacturer ID: 3 >> OEM: 5344 >> Name: SB16G >> Bus Speed: 5000 >> Mode: SD High Speed (50MHz) >> Rd Block Len: 512 >> SD version 3.0 >> High Capacity: Yes >> Capacity: 14.8 GiB >> Bus Width: 4-bit >> Erase Group Size: 512 Bytes >> Odroid N2> reset >> resetting ... >> bl31 reboot reason: 0xd >> bl31 reboot reason: 0x0 >> system cmd 1. >> SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;READ:0;0.0;CHK:0; >> bl2_stage_init 0x01 >> bl2_stage_init 0x81 >> hw >> id:?M1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:800;USB:8; > > It's a new one ! > >> >> >> I didn't analyze it in more detail. I will do. But it seems that >> relevant to BL2 binary. >> If nothing to do before reset, it's working fine. > > Is this the same with SDCard ? Yes. I had tested with same SD-card. (I can't test with eMMC, because eMMC doesn't initialize.) 1) After boot, reset -> fine 2) After boot, run some mmc operation -> reset -> fail. > > The SDCard & eMMC regulators doesn't reset to default when resetting, > causing issues > with the boot ROM... maybe you'll need to reset the regulators in a reset > for the > Odroid C4 board. Actually, i hope that it works fine after building mainline u-boot with odroid-c4_defconfig. Because it seems that supports Odroid-c4. But it doesn't work well. :( For checking, i'm using with u-boot-amlogic with 2021.01-rc1 But eMMC doesn't work.. I'm analyzing this problem..it doesn't work higher mode than 26MHz speed mode. How did you check for eMMC card? I will fix it but i don't have any information about meson_gx_mmc. >>> >>> I did my test on the Khadas VIM3L, but we have the exact same issues on the >>> SEI610, VIM3L and now C4 boards. >>> If i find how to fix it, i will send patch. > >> >> If someone already fixed this or I missed something to do, let me know, >> plz. > > AFAIK no, I just pushed a fix for the eMMC/SDCard clock causing read > issues at 50MHz. Is it relevant to IO error (-5)? >>> >>> Yes, over 26MHz the eMMC fails, the clock management is in cause and needs >>> to be >>> reworked, but this fix should be fine. >> >> This issue is fixed after applied my patch. Also "reset" is working fine. >> >> https://protect2.fireeye.com/v1/url?k=e6aba439-b9309d23-e6aa2f76-000babff24ad-8b52d9e3f1eaaaba&q=1&e=cfbd62d7-66fc-460f-bb62-f49289448de5&u=https%3A%2F%2Fpatchwork.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20201109031233.25320-1-jh80.chung%40samsung.com%2F > > I don't understand why a different clock phase would make reset work here. Sorry. It's my mistake. It's not fixed. Best Regards, Jaehoon CHung > > Neil > >> >> Best Regards, >> Jaehoon Chung >> >>> >>> Neil >>> Best Regards, Jaehoon Chung > > Thanks for the patches & reports ! > > Neil > >> >> Best Regards, >> Jaehoon Chung >> > > >>> >>> >> > >
[ANN] U-Boot v2021.01-rc2 released
Hey all, It's regular release day and I'm back on schedule, so here's -rc2. There's a few small'ish things outstanding in my queue, and a queue of things building up for -next already. I'm going to try and make sure what I pull in, even when a clean-up, is as close as can be to the obviously correct side of things. Yes, this should always be the case, I'm just going to try and hold myself to expectations a bit harder. In terms of a changelog, git log --merges v2021.01-rc1..v2021.01-rc2 contains what I've pulled but as always, better PR messages and tags will provide better results here. I do have my reminders setup for doing -rc releases every other Monday from here on out and final release on January 11th, 2021. Thanks all! -- Tom signature.asc Description: PGP signature
Re: [PATCH] net: ks8851: Implement EEPROM MAC address readout
On Thu, Oct 08, 2020 at 03:14:17PM +0200, Marek Vasut wrote: > In case there is an EEPROM attached to the KS8851 MAC and the EEPROM > contains a valid MAC address, the MAC address is loaded into the NIC > registers on power on. Read the MAC address out of the NIC registers > and provide it to U-Boot. > > Signed-off-by: Marek Vasut > Cc: Eugen Hristev > Cc: Joe Hershberger Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] arm: actions: increase SYS_MALLOC_F_LEN
On Mon, Nov 09, 2020 at 07:31:08PM +0530, Amit Singh Tomar wrote:
> after commit 4ab3817ff16a ("clk: fixed-rate: Enable DM_FLAG_PRE_RELOC flag")
> Cubieboard7 (based on actions S700 SoC) fails to boot.
>
> It is due to the fact that the default value of CONFIG_SYS_MALLOC_F_LEN
> (0x400)
> would not provide enough memory for clock device to probe (before relocation)
> well.
>
> This commit fixes it, by increasing SYS_MALLOC_F_LEN to value 0x2000.
>
> Suggested-by: Andre Przywara
> Signed-off-by: Amit Singh Tomar
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
Re: Pull request for UEFI sub-system for efi-2021-01-rc2 (2)
On Mon, Nov 09, 2020 at 07:54:38PM +0100, Heinrich Schuchardt wrote: > The following changes since commit 22ad69b7987eb4b10221330661db4427e40174fb: > > Merge tag 'dm-pull5nov20' of git://git.denx.de/u-boot-dm (2020-11-06 > 11:27:14 -0500) > > are available in the Git repository at: > > https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git > tags/efi-2021-01-rc2-2 > > for you to fetch changes up to a322f54f50cfb2e8e7a68968c060b2fd3dbd934d: > > tpm: Change response length of tpm2_get_capability() (2020-11-09 > 17:28:18 +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] mmc: meson_gx_mmc: change a clock phase to stable value
On 11/9/20 11:23 PM, Neil Armstrong wrote: > On 09/11/2020 15:10, Mark Kettenis wrote: >>> From: Neil Armstrong >>> Date: Mon, 9 Nov 2020 14:37:09 +0100 >>> >>> Hi, >>> >>> On 09/11/2020 04:12, Jaehoon Chung wrote: Core clock phase value is changed from 180' to 270'. It's more stable than before. - Odroidn-N2/C4 : Working fine with 52MHz - VIM3 : Working fine with 52MHz Before this patch, Odroid-C4 doesn't work fine with 52MHz. Signed-off-by: Jaehoon Chung --- drivers/mmc/meson_gx_mmc.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 719dd1e5e570..7c60e0566560 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -52,10 +52,16 @@ static void meson_mmc_config_clock(struct mmc *mmc) } clk_div = DIV_ROUND_UP(clk, mmc->clock); - /* 180 phase core clock */ - meson_mmc_clk |= CLK_CO_PHASE_180; - - /* 180 phase tx clock */ + /* + * Clock Phase needs to set a proper value. + * It can be changed to other value. + * Because CORE : 270' Phase and TX : 0' Phase are stable, + * set to them by default. + */ + /* Core Clock Phase */ + meson_mmc_clk |= CLK_CO_PHASE_270; + + /* TX Clock Phase */ meson_mmc_clk |= CLK_TX_PHASE_000; /* clock settings */ >>> >>> The previous values were aligned on the Linux driver, which is functional. >> >> Actually the Linux driver isn't really functional; the 52 MHz >> high-speed mode doesn't work. But since HS200 does work in Linux, >> probably nobody noticed this. >> >> That said, I'm not confident a single clock phase setting will work >> across all Amlogic SoCs and across different boards. Maybe we need >> something in the device tree such that we can control the values on a >> per-board level. >> > > So this is specific to SM1 SoCs then, because others families doesn't have > such issues > at 52MHz. I don't have much knowledge of SM1 SoCs. But how did its phase value select them on Linux driver? > > So the Linux must be fixes, including the bindings to introduce a new > compatible, then > ported to U-Boot. > > So in the meantime, it's right to limit to 26MHz on SM1 in U-boot until we > have all this > clarified. If you want to limit to 26MHz, I don't have any objection about your opinion. But I wonder how to clarify all. And I also wonder that values what is used on Linux kernel are really right. Best Regards, Jaehoon Chung > > Neil >
RE: [dwi2c PATCH v1] dwi2c add offsets to reads
-Original Message-
From: Simon Glass
Sent: Saturday, November 7, 2020 1:33 PM
To: Duffin, CooperX
Cc: U-Boot Mailing List ; uboot-snps-...@synopsys.com;
Tom Rini ; Robert Beckett ;
Heiko Schocher ; Wolgang Denk ; Ian Ray
Subject: Re: [dwi2c PATCH v1] dwi2c add offsets to reads
Hi CooperX,
On Fri, 6 Nov 2020 at 16:08, Duffin, CooperX wrote:
>
> Hello Simon,
>
> I wasn’t using the test/dm/i2c I this was tested using hardware where I was
> using the dm_i2c_read() function. I just tried to use the test/dm/i2c where I
> am following the README but I keep getting "sdl2-config: Command not found".
> I suspect it would also fail where it is trying to read but I will have to
> get test/dm/i2c working before I know for sure.
>
> Essentially my test was
>
> int uboot_app (int argc, char * const argv[]) {
> uint8_t buf[10];
> uint8_t read_buf[5];
> uint8_t dev_addr;
> uint32_t bus_speed;
> //i2c_bus device pointer
> struct udevice *i2c_led;
> struct udevice *bus;
> app_startup(argv);
> /* Print the ABI version */
> printf ("Example expects ABI version %d\n", XF_VERSION);
> printf ("Actual U-Boot ABI version %d\n", (int)get_version());
>
> dev_addr = 0x60;
> bus_speed = 10; //100KHz
> printf("starting test i2c\n");
> buf[0] = 'b';
> buf[1] = 'o';
> buf[2] = 'o';
> buf[3] = 't';
> //Get i2c chip, init the code
> printf("init starting\n");
> if(i2c_get_chip_for_busnum(0 , 0x60, 1, &i2c_led)!=0){
> printf("ERROR: no device found at %x \n",dev_addr);
> return (0);
> }
> uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
> printf("Setting bus speed to %d\n", bus_speed);
> if(dm_i2c_set_bus_speed(bus,bus_speed)!=0){
> printf("ERROR: Cannot set buspeed\n");
> return (0);
> }
> printf("i2c_led name is %s\n",i2c_led->name);
> if(i2c_led == NULL){
> printf("ERROR i2c_led 0 is null\n");
> return (0);
> }
> printf("Writing\n");
> for(unsigned int a =0; a< 4; a++){
> if(dm_i2c_write(i2c_led,a,&buf[a],1)!=0){
> printf("ERROR writing\n");
> return (0);
> }
> }
>
> printf("Reading\n");
> for(unsigned int a =0; a< 4; a++){
> if(dm_i2c_read(i2c_led,a,&read_buf[a],1)!=0){
> printf("ERROR writing\n");
> return (0);
> }
> }
> printf("read buffer is %c, %c, %c, %c \n",read_buf[0],read_buf[1],
> read_buf[2],read_buf[3]);
> printf ("\n\n");
> return (0);
> }
>
> ## Starting application at 0x0C10 ...
> Example expects ABI version 10
> Actual U-Boot ABI version 10
> starting test i2c
> init starting
> Setting bus speed to 10
> i2c_led name is generic_60
> Writing
> Reading
> read buffer is o, o, o, o
>
> with the fix I get:
>
> ## Starting application at 0x0C10 ...
> Example expects ABI version 10
> Actual U-Boot ABI version 10
> starting test i2c
> init starting
> Setting bus speed to 10
> i2c_led name is generic_60
> Writing
> Reading
> read buffer is b, o, o, t
>
> which is correct. Similarly if I stop auto boot I get a similar result:
>
> Hit any key to stop autoboot: 0
> device # i2c
> i2c - I2C sub-system
>
> Assuming I write "boot" to the device
> device # i2c dev 0
> Setting bus to 0
> device # i2c md 0x60 0 4
> : 6f 6f 6f 6f
>
> With the fix/patch I get:
>
> device# i2c md 0x60 0 4
> : 62 6f 6f 74boot
>
> Which is correct. Also the reads were working in linux leading to my original
> suspicion that there might be something going on in the driver. Hopefully
> that answers your question let me know if you have anymore.
I had a bit of a look at this. If you look at dm_i2c_read() it actually builds
the address into the buffer it sends. So when it gets to __dw_i2c_write() the
alen parameter is always 0. That function is actually a holdover from before
driver model, so one day the alen and addr parameters will go away.
I wonder if your device does not support multiple-byte reads or writes? Can you
try the i2c md with a single byte? There is a DM_I2C_CHIP_WR_ADDRESS option to
handle this - see the 'i2c flags'
command.
In the designware_i2c_xfer(), try printing out the bytes that it gets in each
message using i2c_dump_msgs().
Also check the i2c_get_chip() function which you are using. See if
chip->offset_len is set to 1 as it should be, for your device. If not,
perhaps something is missing.
In short I am not really sure what is going on, but I think it needs more
investigation.
BTW with this mailing list we like people to reply inline or at the bottom, not
at the top.
Regards,
Simon
>
> Best regards,
>
> -Cooper Duff
Re: [PATCH] mmc: meson_gx_mmc: change a clock phase to stable value
Hi, On 11/9/20 11:10 PM, Mark Kettenis wrote: >> From: Neil Armstrong >> Date: Mon, 9 Nov 2020 14:37:09 +0100 >> >> Hi, >> >> On 09/11/2020 04:12, Jaehoon Chung wrote: >>> Core clock phase value is changed from 180' to 270'. >>> It's more stable than before. >>> - Odroidn-N2/C4 : Working fine with 52MHz >>> - VIM3 : Working fine with 52MHz >>> >>> Before this patch, Odroid-C4 doesn't work fine with 52MHz. >>> >>> Signed-off-by: Jaehoon Chung >>> --- >>> drivers/mmc/meson_gx_mmc.c | 14 ++ >>> 1 file changed, 10 insertions(+), 4 deletions(-) >>> >>> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c >>> index 719dd1e5e570..7c60e0566560 100644 >>> --- a/drivers/mmc/meson_gx_mmc.c >>> +++ b/drivers/mmc/meson_gx_mmc.c >>> @@ -52,10 +52,16 @@ static void meson_mmc_config_clock(struct mmc *mmc) >>> } >>> clk_div = DIV_ROUND_UP(clk, mmc->clock); >>> >>> - /* 180 phase core clock */ >>> - meson_mmc_clk |= CLK_CO_PHASE_180; >>> - >>> - /* 180 phase tx clock */ >>> + /* >>> +* Clock Phase needs to set a proper value. >>> +* It can be changed to other value. >>> +* Because CORE : 270' Phase and TX : 0' Phase are stable, >>> +* set to them by default. >>> +*/ >>> + /* Core Clock Phase */ >>> + meson_mmc_clk |= CLK_CO_PHASE_270; >>> + >>> + /* TX Clock Phase */ >>> meson_mmc_clk |= CLK_TX_PHASE_000; >>> >>> /* clock settings */ >>> >> >> The previous values were aligned on the Linux driver, which is functional. > > Actually the Linux driver isn't really functional; the 52 MHz > high-speed mode doesn't work. But since HS200 does work in Linux, > probably nobody noticed this. Well, i didn't check Linux driver. but i can also check on Linux side. > > That said, I'm not confident a single clock phase setting will work > across all Amlogic SoCs and across different boards. Maybe we need > something in the device tree such that we can control the values on a > per-board level. Agreed. I can't mention that "it's working fine about all Amlogic SoCs". In exynos's case, there are sdr and ddr timing about mmc/sd IP. sdr/ddr timing are trying to get from dt's property, because it's possible that all Exynos SoCs have different values. I think that Amlogic SoCs also needs to apply similar approach. Best Regards, Jaehoon Chung >
Re: [PATCH] mmc: meson_gx_mmc: change a clock phase to stable value
On 11/9/20 10:37 PM, Neil Armstrong wrote: > Hi, > > On 09/11/2020 04:12, Jaehoon Chung wrote: >> Core clock phase value is changed from 180' to 270'. >> It's more stable than before. >> - Odroidn-N2/C4 : Working fine with 52MHz >> - VIM3 : Working fine with 52MHz >> >> Before this patch, Odroid-C4 doesn't work fine with 52MHz. >> >> Signed-off-by: Jaehoon Chung >> --- >> drivers/mmc/meson_gx_mmc.c | 14 ++ >> 1 file changed, 10 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c >> index 719dd1e5e570..7c60e0566560 100644 >> --- a/drivers/mmc/meson_gx_mmc.c >> +++ b/drivers/mmc/meson_gx_mmc.c >> @@ -52,10 +52,16 @@ static void meson_mmc_config_clock(struct mmc *mmc) >> } >> clk_div = DIV_ROUND_UP(clk, mmc->clock); >> >> -/* 180 phase core clock */ >> -meson_mmc_clk |= CLK_CO_PHASE_180; >> - >> -/* 180 phase tx clock */ >> +/* >> + * Clock Phase needs to set a proper value. >> + * It can be changed to other value. >> + * Because CORE : 270' Phase and TX : 0' Phase are stable, >> + * set to them by default. >> + */ >> +/* Core Clock Phase */ >> +meson_mmc_clk |= CLK_CO_PHASE_270; >> + >> +/* TX Clock Phase */ >> meson_mmc_clk |= CLK_TX_PHASE_000; >> >> /* clock settings */ >> > > The previous values were aligned on the Linux driver, which is functional. > > How did you test these ? Actually, i have tested about all cases on targets what i have. (VIM3/Odroid-N2/Odroid-C4) I also have VIM3L, but i didn't test on VIM3L. (I can test with VIM3L) If check with oscilloscope, it will be a good way to find what's wrong. When i have enabled MMC_DEBUG, it was always returned -5 (IO) error during switching mode. In meson_gx_mmc.c, meson_dm_mmc_send_cmd() is returned to -5. When i have checked status register, CRC error status bit (BIT[10]) is set. It means that clock timing is wrong. In my experiment, my debugging about CRC error is 1) GPIO setting 2) clock value 3) Driver strength 4) clock phase value I assume that 1~3) are correct. So checked PHASE values. I didn't check yet how to set value on Linux driver. Best Regards, Jaehoon Chung > > Neil >
Re: [PATCH 1/1] cros_ec: Handling EC_CMD_GET_NEXT_EVENT
On 11/9/20 10:13 PM, Alper Nebi Yasak wrote:
> On 09/11/2020 23:34, Heinrich Schuchardt wrote:
>> With commit 690079767803 ("cros_ec: Support keyboard scanning with
>> EC_CMD_GET_NEXT_EVENT") check_for_keys() tries to read keyboard
>> strokes using EC_CMD_GET_NEXT_EVENT. But the sandbox driver does
>> not understand this command. We need to reply with
>> -EC_RES_INVALID_COMMAND to force check_for_keys() to fall back to
>> use EC_CMD_MKBP_STATE. Currently the driver prints
>>
>> ** Unknown EC command 0x67
>>
>> in this case. With the patch the message is suppressed.
>>
>> In a future patch we should upgrade the sandbox driver to provide
>> EC_CMD_GET_NEXT_EVENT support.
>>
>> Fixes: 690079767803 ("cros_ec: Support keyboard scanning with
>> EC_CMD_GET_NEXT_EVENT")
>> Signed-off-by: Heinrich Schuchardt
>> ---
>> process_cmd() should always return an appropriate negative enum ec_status
>> in case of an error and not simply -1. But fixing the return values is
>> beyond the scope of this patch.
>
> (Looks to me like -1 is already == -EC_RES_INVALID_COMMAND from
> include/ec_commands.h definitions, but I'd agree the latter form should
> be preferred.)
If you look at the complete function, you will find other "return -1;"
statements where return codes other than -EC_RES_INVALID_COMMAND make
more sense. E.g. after
printf("** Unknown flash region %d\n", req->region);
it would be reasonable to return EC_RES_INVALID_PARAM.
Best regards
Heinrich
>
>> ---
>> drivers/misc/cros_ec_sandbox.c | 10 ++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c
>> index a191f061b8..ff7f782742 100644
>> --- a/drivers/misc/cros_ec_sandbox.c
>> +++ b/drivers/misc/cros_ec_sandbox.c
>> @@ -460,6 +460,16 @@ static int process_cmd(struct ec_state *ec,
>> case EC_CMD_ENTERING_MODE:
>> len = 0;
>> break;
>> +case EC_CMD_GET_NEXT_EVENT:
>> +/*
>> + * TODO:
>> + * This driver emulates an old keyboard device supporting
>> + * EC_CMD_MKBP_STATE. Current Chrome OS keyboards use
>> + * EC_CMD_GET_NEXT_EVENT. Cf.
>> + * "mkbp: Add support for buttons and switches"
>> + *
>> https://chromium.googlesource.com/chromiumos/platform/ec/+/87a071941b89e3f7fd3eb329b682e60b3fbd6c73
>> + */
>> +return -EC_RES_INVALID_COMMAND;
>
> I'll try implementing the TODO, sorry for the fallout.
>
>> default:
>> printf(" ** Unknown EC command %#02x\n", req_hdr->command);
>> return -1;
>> --
>> 2.28.0
>>
Re: [PATCH 1/1] cros_ec: Handling EC_CMD_GET_NEXT_EVENT
On 09/11/2020 23:34, Heinrich Schuchardt wrote:
> With commit 690079767803 ("cros_ec: Support keyboard scanning with
> EC_CMD_GET_NEXT_EVENT") check_for_keys() tries to read keyboard
> strokes using EC_CMD_GET_NEXT_EVENT. But the sandbox driver does
> not understand this command. We need to reply with
> -EC_RES_INVALID_COMMAND to force check_for_keys() to fall back to
> use EC_CMD_MKBP_STATE. Currently the driver prints
>
> ** Unknown EC command 0x67
>
> in this case. With the patch the message is suppressed.
>
> In a future patch we should upgrade the sandbox driver to provide
> EC_CMD_GET_NEXT_EVENT support.
>
> Fixes: 690079767803 ("cros_ec: Support keyboard scanning with
> EC_CMD_GET_NEXT_EVENT")
> Signed-off-by: Heinrich Schuchardt
> ---
> process_cmd() should always return an appropriate negative enum ec_status
> in case of an error and not simply -1. But fixing the return values is
> beyond the scope of this patch.
(Looks to me like -1 is already == -EC_RES_INVALID_COMMAND from
include/ec_commands.h definitions, but I'd agree the latter form should
be preferred.)
> ---
> drivers/misc/cros_ec_sandbox.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c
> index a191f061b8..ff7f782742 100644
> --- a/drivers/misc/cros_ec_sandbox.c
> +++ b/drivers/misc/cros_ec_sandbox.c
> @@ -460,6 +460,16 @@ static int process_cmd(struct ec_state *ec,
> case EC_CMD_ENTERING_MODE:
> len = 0;
> break;
> + case EC_CMD_GET_NEXT_EVENT:
> + /*
> + * TODO:
> + * This driver emulates an old keyboard device supporting
> + * EC_CMD_MKBP_STATE. Current Chrome OS keyboards use
> + * EC_CMD_GET_NEXT_EVENT. Cf.
> + * "mkbp: Add support for buttons and switches"
> + *
> https://chromium.googlesource.com/chromiumos/platform/ec/+/87a071941b89e3f7fd3eb329b682e60b3fbd6c73
> + */
> + return -EC_RES_INVALID_COMMAND;
I'll try implementing the TODO, sorry for the fallout.
> default:
> printf(" ** Unknown EC command %#02x\n", req_hdr->command);
> return -1;
> --
> 2.28.0
>
[PATCH 1/1] cros_ec: Handling EC_CMD_GET_NEXT_EVENT
With commit 690079767803 ("cros_ec: Support keyboard scanning with
EC_CMD_GET_NEXT_EVENT") check_for_keys() tries to read keyboard
strokes using EC_CMD_GET_NEXT_EVENT. But the sandbox driver does
not understand this command. We need to reply with
-EC_RES_INVALID_COMMAND to force check_for_keys() to fall back to
use EC_CMD_MKBP_STATE. Currently the driver prints
** Unknown EC command 0x67
in this case. With the patch the message is suppressed.
In a future patch we should upgrade the sandbox driver to provide
EC_CMD_GET_NEXT_EVENT support.
Fixes: 690079767803 ("cros_ec: Support keyboard scanning with
EC_CMD_GET_NEXT_EVENT")
Signed-off-by: Heinrich Schuchardt
---
process_cmd() should always return an appropriate negative enum ec_status
in case of an error and not simply -1. But fixing the return values is
beyond the scope of this patch.
---
drivers/misc/cros_ec_sandbox.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c
index a191f061b8..ff7f782742 100644
--- a/drivers/misc/cros_ec_sandbox.c
+++ b/drivers/misc/cros_ec_sandbox.c
@@ -460,6 +460,16 @@ static int process_cmd(struct ec_state *ec,
case EC_CMD_ENTERING_MODE:
len = 0;
break;
+ case EC_CMD_GET_NEXT_EVENT:
+ /*
+* TODO:
+* This driver emulates an old keyboard device supporting
+* EC_CMD_MKBP_STATE. Current Chrome OS keyboards use
+* EC_CMD_GET_NEXT_EVENT. Cf.
+* "mkbp: Add support for buttons and switches"
+*
https://chromium.googlesource.com/chromiumos/platform/ec/+/87a071941b89e3f7fd3eb329b682e60b3fbd6c73
+*/
+ return -EC_RES_INVALID_COMMAND;
default:
printf(" ** Unknown EC command %#02x\n", req_hdr->command);
return -1;
--
2.28.0
Re: [PATCH 2/3 v2] tpm: Add some headers from the spec
Hi Heinrich, [...] > > > > + */ > > > +#define TPM2_NUM_PCR_BANKS 16 > > > + > > > +/* Definition of (UINT32) TPM2_CAP Constants */ > > > +#define TPM2_CAP_PCRS 0x0005U > > > +#define TPM2_CAP_TPM_PROPERTIES 0x0006U > > > + > > > +/* Definition of (UINT32) TPM2_PT Constants */ > > > +#define PT_GROUP (u32)(0x0100) > > > +#define PT_FIXED (u32)(PT_GROUP * 1) > > > +#define TPM2_PT_MANUFACTURER(u32)(PT_FIXED + 5) > > > +#define TPM2_PT_PCR_COUNT (u32)(PT_FIXED + 18) > > > +#define TPM2_PT_MAX_COMMAND_SIZE(u32)(PT_FIXED + 30) > > > +#define TPM2_PT_MAX_RESPONSE_SIZE (u32)(PT_FIXED + 31) > > > > All these definitions are all copied from the "TCG TSS2.0 Overview and > > Common Structures Specification". I am missing a reference to the > > copyright notice of the spec. I think the best thing to do would be > > placing the TCG copyrighted code into a separate include that is > > included in tpm_v2.h. Please, check with Tom if the license contradicts > > GPL. Especially the following sentence seems problematic: > > > > "THE COPYRIGHT LICENSES SET FORTH ABOVE DO NOT REPRESENT ANY FORM OF > > LICENSE OR WAIVER, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, WITH > > RESPECT TO PATENT RIGHTS HELD BY TCG MEMBERS (OR OTHER THIRD PARTIES) > > THAT MAY BE NECESSARY TO IMPLEMENT THIS SPECIFICATION OR OTHERWISE." > > > > Cf. https://fedoraproject.org/wiki/Licensing/TCGL > > > > Ok will do So I talked to Tom and he suggested we have a look at linux, or any other project that uses those. I can't find any copyright claims in include/linux/tpm.h, apart from a pointer to the spec. I don't think splitting the changes to a new file is a good idea. Most of the existing definitions of the file are part of the same document. Maybe just updating the copyright properly is the right thing to do? [...] Regards /Ilias
Re: Pull request for UEFI sub-system for efi-2021-01-rc2 (2)
On 11/9/20 8:18 PM, Tom Rini wrote:
> On Mon, Nov 09, 2020 at 08:15:43PM +0100, Heinrich Schuchardt wrote:
>
>> On 11/9/20 7:54 PM, Heinrich Schuchardt wrote:
>>> The following changes since commit 22ad69b7987eb4b10221330661db4427e40174fb:
>>>
>>> Merge tag 'dm-pull5nov20' of git://git.denx.de/u-boot-dm (2020-11-06
>>> 11:27:14 -0500)
>>>
>>> are available in the Git repository at:
>>>
>>> https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git
>>> tags/efi-2021-01-rc2-2
>>>
>>> for you to fetch changes up to a322f54f50cfb2e8e7a68968c060b2fd3dbd934d:
>>>
>>> tpm: Change response length of tpm2_get_capability() (2020-11-09
>>> 17:28:18 +0100)
>>
>> Hello Tom,
>>
>> something strange happens with the crosswire keyboard driver on current
>> origin/master which I did not see when the patch was written and when
>> Simon reviewed it:
>>
>> The sandbox spits out
>>
>>** Unknown EC command 0x67
>>
>>** Unknown EC command 0x67
>>
>>** Unknown EC command 0x67
>>
>>** Unknown EC command 0x67
>>
>> Please, disregard this pull request.
>
> OK, thanks. Note that there were some cros_ec changes that just came in
> via the DM tree.
>
Yes and the problem is created by
690079767803c7 ("cros_ec: Support keyboard scanning with
EC_CMD_GET_NEXT_EVENT").
But probably we should first fix that patch before putting other cros_ec
changes on top.
Best regards
Heinrich
Re: [PATCH] cros_ec: Support keyboard scanning with EC_CMD_GET_NEXT_EVENT
Hi Heinrich,
On Mon, 9 Nov 2020 at 12:34, Heinrich Schuchardt wrote:
>
> On 10/30/20 6:25 PM, Alper Nebi Yasak wrote:
> > The cros_ec_keyb driver currently uses EC_CMD_MKBP_STATE to scan the
> > keyboard, but this host command was superseded by EC_CMD_GET_NEXT_EVENT
> > and unavailable on more recent devices (including gru-kevin), as it was
> > removed in cros-ec commit 87a071941b89 ("mkbp: Add support for buttons
> > and switches.") dated 2016-07-06.
> >
> > The EC_CMD_GET_NEXT_EVENT has been available since cros-ec commit
> > d1ed75815efe ("MKBP event signalling implementation") dated 2014-10-20,
> > but it looks like it isn't included in firmware-* branches for at least
> > link, nyan-big, samus, snow, spring, panther and peach-pit which have
> > defconfigs in U-Boot. So this patch falls back to the old method if the
> > EC doesn't recognize the newer command.
> >
> > The implementation is mostly adapted from Depthcharge commit
> > f88af26b44fc ("cros_ec: Change keyboard scanning method.").
> >
> > On a gru-kevin, the current driver before this patch fails to read the
> > pressed keys with:
> >
> > out: cmd=0x60: 03 9d 60 00 00 00 00 00
> > in-header: 03 fc 01 00 00 00 00 00
> > in-data:
> > ec_command_inptr: len=-1, din=
> > check_for_keys: keyboard scan failed
> >
> > However the keyboard works fine with the newer command:
> >
> > out: cmd=0x67: 03 96 67 00 00 00 00 00
> > in-header: 03 ef 00 00 0e 00 00 00
> > in-data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> > ec_command_inptr: len=14, din=f412df30
> > key_matrix_decode: num_keys = 0
> > 0 valid keycodes found
> > out: cmd=0x67: 03 96 67 00 00 00 00 00
> > in-header: 03 df 00 00 0e 00 00 00
> > in-data: 00 00 00 00 00 00 00 00 00 00 00 00 10 00
> > ec_command_inptr: len=14, din=f412df30
> > key_matrix_decode: num_keys = 1
> > valid=1, row=4, col=11
> > keycode=28
> > 1 valid keycodes found
> > {0d}
> >
> > Signed-off-by: Alper Nebi Yasak
> > Reviewed-by: Simon Glass
>
> This patch has been applied to origin/master.
>
> Now when I compile sandbox_defconfig and run './u-boot -D' it spits out
> zillions of
>
>** Unknown EC command 0x67
>** Unknown EC command 0x67
>** Unknown EC command 0x67
>** Unknown EC command 0x67
>** Unknown EC command 0x67
>** Unknown EC command 0x67
>** Unknown EC command 0x67
>** Unknown EC command 0x67
>
> When I revert the patch the messages are gone.
>
> So something is really missing in this patch.
Test coverage, for a start!
I think the EC emulator needs to be updated for the new command.
Alper, can you please take a look?
Regards,
SImon
>
> Best regards
>
> Heinrich
>
> > ---
> >
> > drivers/input/cros_ec_keyb.c | 32 ++--
> > drivers/misc/cros_ec.c | 15 +++
> > include/cros_ec.h| 11 +++
> > 3 files changed, 52 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/input/cros_ec_keyb.c b/drivers/input/cros_ec_keyb.c
> > index 00bf58f2b5d2..0c0f52205b28 100644
> > --- a/drivers/input/cros_ec_keyb.c
> > +++ b/drivers/input/cros_ec_keyb.c
> > @@ -47,15 +47,35 @@ static int check_for_keys(struct udevice *dev, struct
> > key_matrix_key *keys,
> > struct key_matrix_key *key;
> > static struct mbkp_keyscan last_scan;
> > static bool last_scan_valid;
> > - struct mbkp_keyscan scan;
> > + struct ec_response_get_next_event event;
> > + struct mbkp_keyscan *scan = (struct mbkp_keyscan *)
> > + &event.data.key_matrix;
> > unsigned int row, col, bit, data;
> > int num_keys;
> > + int ret;
> >
> > - if (cros_ec_scan_keyboard(dev->parent, &scan)) {
> > - debug("%s: keyboard scan failed\n", __func__);
> > + /* Get pending MKBP event. It may not be a key matrix event. */
> > + do {
> > + ret = cros_ec_get_next_event(dev->parent, &event);
> > + /* The EC has no events for us at this time. */
> > + if (ret == -EC_RES_UNAVAILABLE)
> > + return -EIO;
> > + else if (ret)
> > + break;
> > + } while (event.event_type != EC_MKBP_EVENT_KEY_MATRIX);
> > +
> > + /* Try the old command if the EC doesn't support the above. */
> > + if (ret == -EC_RES_INVALID_COMMAND) {
> > + if (cros_ec_scan_keyboard(dev->parent, scan)) {
> > + debug("%s: keyboard scan failed\n", __func__);
> > + return -EIO;
> > + }
> > + } else if (ret) {
> > + debug("%s: Error getting next MKBP event. (%d)\n",
> > + __func__, ret);
> > return -EIO;
> > }
> > - *samep = last_scan_valid && !memcmp(&last_scan, &scan, sizeof(scan));
> > + *samep = last_scan_valid && !memcmp(&last_scan, scan, sizeof(*scan));
> >
> > /*
> >
[PATCH] ARM: dts: at91: sam9x60: enable slewrate/high drive for sdhci0 pinout
Align the pin setup for sdhci0 with linux kernel.
This means to have slew rate enable and high drive strength.
Signed-off-by: Eugen Hristev
---
arch/arm/dts/sam9x60.dtsi | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
index 7f3eae3f5d..007646fcb4 100644
--- a/arch/arm/dts/sam9x60.dtsi
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -153,12 +153,18 @@
sdhci0 {
pinctrl_sdhci0: sdhci0 {
atmel,pins =
- ; /* PA20 DAT3 periph A with
pullup */
+ ; /* PA20 DAT3
periph A with pullup */
};
};
};
--
2.25.1
Re: [PATCH] cros_ec: Support keyboard scanning with EC_CMD_GET_NEXT_EVENT
On 10/30/20 6:25 PM, Alper Nebi Yasak wrote:
> The cros_ec_keyb driver currently uses EC_CMD_MKBP_STATE to scan the
> keyboard, but this host command was superseded by EC_CMD_GET_NEXT_EVENT
> and unavailable on more recent devices (including gru-kevin), as it was
> removed in cros-ec commit 87a071941b89 ("mkbp: Add support for buttons
> and switches.") dated 2016-07-06.
>
> The EC_CMD_GET_NEXT_EVENT has been available since cros-ec commit
> d1ed75815efe ("MKBP event signalling implementation") dated 2014-10-20,
> but it looks like it isn't included in firmware-* branches for at least
> link, nyan-big, samus, snow, spring, panther and peach-pit which have
> defconfigs in U-Boot. So this patch falls back to the old method if the
> EC doesn't recognize the newer command.
>
> The implementation is mostly adapted from Depthcharge commit
> f88af26b44fc ("cros_ec: Change keyboard scanning method.").
>
> On a gru-kevin, the current driver before this patch fails to read the
> pressed keys with:
>
> out: cmd=0x60: 03 9d 60 00 00 00 00 00
> in-header: 03 fc 01 00 00 00 00 00
> in-data:
> ec_command_inptr: len=-1, din=
> check_for_keys: keyboard scan failed
>
> However the keyboard works fine with the newer command:
>
> out: cmd=0x67: 03 96 67 00 00 00 00 00
> in-header: 03 ef 00 00 0e 00 00 00
> in-data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> ec_command_inptr: len=14, din=f412df30
> key_matrix_decode: num_keys = 0
> 0 valid keycodes found
> out: cmd=0x67: 03 96 67 00 00 00 00 00
> in-header: 03 df 00 00 0e 00 00 00
> in-data: 00 00 00 00 00 00 00 00 00 00 00 00 10 00
> ec_command_inptr: len=14, din=f412df30
> key_matrix_decode: num_keys = 1
> valid=1, row=4, col=11
> keycode=28
> 1 valid keycodes found
> {0d}
>
> Signed-off-by: Alper Nebi Yasak
> Reviewed-by: Simon Glass
This patch has been applied to origin/master.
Now when I compile sandbox_defconfig and run './u-boot -D' it spits out
zillions of
** Unknown EC command 0x67
** Unknown EC command 0x67
** Unknown EC command 0x67
** Unknown EC command 0x67
** Unknown EC command 0x67
** Unknown EC command 0x67
** Unknown EC command 0x67
** Unknown EC command 0x67
When I revert the patch the messages are gone.
So something is really missing in this patch.
Best regards
Heinrich
> ---
>
> drivers/input/cros_ec_keyb.c | 32 ++--
> drivers/misc/cros_ec.c | 15 +++
> include/cros_ec.h| 11 +++
> 3 files changed, 52 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/input/cros_ec_keyb.c b/drivers/input/cros_ec_keyb.c
> index 00bf58f2b5d2..0c0f52205b28 100644
> --- a/drivers/input/cros_ec_keyb.c
> +++ b/drivers/input/cros_ec_keyb.c
> @@ -47,15 +47,35 @@ static int check_for_keys(struct udevice *dev, struct
> key_matrix_key *keys,
> struct key_matrix_key *key;
> static struct mbkp_keyscan last_scan;
> static bool last_scan_valid;
> - struct mbkp_keyscan scan;
> + struct ec_response_get_next_event event;
> + struct mbkp_keyscan *scan = (struct mbkp_keyscan *)
> + &event.data.key_matrix;
> unsigned int row, col, bit, data;
> int num_keys;
> + int ret;
>
> - if (cros_ec_scan_keyboard(dev->parent, &scan)) {
> - debug("%s: keyboard scan failed\n", __func__);
> + /* Get pending MKBP event. It may not be a key matrix event. */
> + do {
> + ret = cros_ec_get_next_event(dev->parent, &event);
> + /* The EC has no events for us at this time. */
> + if (ret == -EC_RES_UNAVAILABLE)
> + return -EIO;
> + else if (ret)
> + break;
> + } while (event.event_type != EC_MKBP_EVENT_KEY_MATRIX);
> +
> + /* Try the old command if the EC doesn't support the above. */
> + if (ret == -EC_RES_INVALID_COMMAND) {
> + if (cros_ec_scan_keyboard(dev->parent, scan)) {
> + debug("%s: keyboard scan failed\n", __func__);
> + return -EIO;
> + }
> + } else if (ret) {
> + debug("%s: Error getting next MKBP event. (%d)\n",
> + __func__, ret);
> return -EIO;
> }
> - *samep = last_scan_valid && !memcmp(&last_scan, &scan, sizeof(scan));
> + *samep = last_scan_valid && !memcmp(&last_scan, scan, sizeof(*scan));
>
> /*
>* This is a bit odd. The EC has no way to tell us that it has run
> @@ -64,14 +84,14 @@ static int check_for_keys(struct udevice *dev, struct
> key_matrix_key *keys,
>* that this scan is the same as the last.
>*/
> last_scan_valid = true;
> - memcpy(&last_scan, &scan, sizeof(last_scan));
> + memcpy(&last_scan, scan, sizeof(last_scan));
>
> for (col = num_keys = bit = 0; col < priv->matrix.num_cols;
>
Re: Pull request for UEFI sub-system for efi-2021-01-rc2 (2)
On Mon, Nov 09, 2020 at 08:15:43PM +0100, Heinrich Schuchardt wrote: > On 11/9/20 7:54 PM, Heinrich Schuchardt wrote: > > The following changes since commit 22ad69b7987eb4b10221330661db4427e40174fb: > > > > Merge tag 'dm-pull5nov20' of git://git.denx.de/u-boot-dm (2020-11-06 > > 11:27:14 -0500) > > > > are available in the Git repository at: > > > > https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git > > tags/efi-2021-01-rc2-2 > > > > for you to fetch changes up to a322f54f50cfb2e8e7a68968c060b2fd3dbd934d: > > > > tpm: Change response length of tpm2_get_capability() (2020-11-09 > > 17:28:18 +0100) > > Hello Tom, > > something strange happens with the crosswire keyboard driver on current > origin/master which I did not see when the patch was written and when > Simon reviewed it: > > The sandbox spits out > >** Unknown EC command 0x67 > >** Unknown EC command 0x67 > >** Unknown EC command 0x67 > >** Unknown EC command 0x67 > > Please, disregard this pull request. OK, thanks. Note that there were some cros_ec changes that just came in via the DM tree. -- Tom signature.asc Description: PGP signature
Re: Pull request for UEFI sub-system for efi-2021-01-rc2 (2)
On 11/9/20 7:54 PM, Heinrich Schuchardt wrote: > The following changes since commit 22ad69b7987eb4b10221330661db4427e40174fb: > > Merge tag 'dm-pull5nov20' of git://git.denx.de/u-boot-dm (2020-11-06 > 11:27:14 -0500) > > are available in the Git repository at: > > https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git > tags/efi-2021-01-rc2-2 > > for you to fetch changes up to a322f54f50cfb2e8e7a68968c060b2fd3dbd934d: > > tpm: Change response length of tpm2_get_capability() (2020-11-09 > 17:28:18 +0100) Hello Tom, something strange happens with the crosswire keyboard driver on current origin/master which I did not see when the patch was written and when Simon reviewed it: The sandbox spits out ** Unknown EC command 0x67 ** Unknown EC command 0x67 ** Unknown EC command 0x67 ** Unknown EC command 0x67 Please, disregard this pull request. Best regards Heinrich
Re: [PATCH] mmc: meson_gx_mmc: change a clock phase to stable value
Hi Neil, On Mon, 9 Nov 2020 at 19:56, Neil Armstrong wrote: > > On 09/11/2020 15:10, Mark Kettenis wrote: > >> From: Neil Armstrong > >> Date: Mon, 9 Nov 2020 14:37:09 +0100 > >> > >> Hi, > >> > >> On 09/11/2020 04:12, Jaehoon Chung wrote: > >>> Core clock phase value is changed from 180' to 270'. > >>> It's more stable than before. > >>> - Odroidn-N2/C4 : Working fine with 52MHz > >>> - VIM3 : Working fine with 52MHz > >>> > >>> Before this patch, Odroid-C4 doesn't work fine with 52MHz. > >>> > >>> Signed-off-by: Jaehoon Chung > >>> --- > >>> drivers/mmc/meson_gx_mmc.c | 14 ++ > >>> 1 file changed, 10 insertions(+), 4 deletions(-) > >>> > >>> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c > >>> index 719dd1e5e570..7c60e0566560 100644 > >>> --- a/drivers/mmc/meson_gx_mmc.c > >>> +++ b/drivers/mmc/meson_gx_mmc.c > >>> @@ -52,10 +52,16 @@ static void meson_mmc_config_clock(struct mmc *mmc) > >>> } > >>> clk_div = DIV_ROUND_UP(clk, mmc->clock); > >>> > >>> - /* 180 phase core clock */ > >>> - meson_mmc_clk |= CLK_CO_PHASE_180; > >>> - > >>> - /* 180 phase tx clock */ > >>> + /* > >>> +* Clock Phase needs to set a proper value. > >>> +* It can be changed to other value. > >>> +* Because CORE : 270' Phase and TX : 0' Phase are stable, > >>> +* set to them by default. > >>> +*/ > >>> + /* Core Clock Phase */ > >>> + meson_mmc_clk |= CLK_CO_PHASE_270; > >>> + > >>> + /* TX Clock Phase */ > >>> meson_mmc_clk |= CLK_TX_PHASE_000; > >>> > >>> /* clock settings */ > >>> > >> > >> The previous values were aligned on the Linux driver, which is functional. > > > > Actually the Linux driver isn't really functional; the 52 MHz > > high-speed mode doesn't work. But since HS200 does work in Linux, > > probably nobody noticed this. > > > > That said, I'm not confident a single clock phase setting will work > > across all Amlogic SoCs and across different boards. Maybe we need > > something in the device tree such that we can control the values on a > > per-board level. > > > > So this is specific to SM1 SoCs then, because others families doesn't have > such issues > at 52MHz. > > So the Linux must be fixes, including the bindings to introduce a new > compatible, then > ported to U-Boot. > > So in the meantime, it's right to limit to 26MHz on SM1 in U-boot until we > have all this > clarified. > > Neil Earlier I had a similar approach for this FIX but somehow it did not get merged. Please add my Tested-by: Anand Moon Best Regards -Anand
Pull request for UEFI sub-system for efi-2021-01-rc2 (2)
The following changes since commit 22ad69b7987eb4b10221330661db4427e40174fb: Merge tag 'dm-pull5nov20' of git://git.denx.de/u-boot-dm (2020-11-06 11:27:14 -0500) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git tags/efi-2021-01-rc2-2 for you to fetch changes up to a322f54f50cfb2e8e7a68968c060b2fd3dbd934d: tpm: Change response length of tpm2_get_capability() (2020-11-09 17:28:18 +0100) Pull request for UEFI sub-system for efi-2021-01-rc2 (2) The following bugs are fixed: * The conitrace command failed to build. * Non-volatile UEFI variables were not delete form the file store. The following features are added: * Support for the FN1 - FN10 keys on crosswire keyboards is added. * An EFI binary is provided to dump the binary device tree. tpm2_get_capability() is adjusted in preparation of the implementation of the EFI_TCG2_PROTOCOL. Gitlab CI showed no problems: https://gitlab.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/5301 Heinrich Schuchardt (4): cmd: conitrace: replace getc() by getchar() input: add support for FN1 - FN10 on crosswire kbd efi_loader: non-volatile variable not deleted from file efi_selftest: add tool to download dtb Ilias Apalodimas (1): tpm: Change response length of tpm2_get_capability() cmd/conitrace.c | 4 +- cmd/tpm-v2.c | 4 +- drivers/input/input.c | 35 +-- lib/efi_loader/efi_variable.c | 1 + lib/efi_selftest/Makefile | 5 + lib/efi_selftest/dtbdump.c| 215 ++ lib/tpm-v2.c | 4 +- 7 files changed, 252 insertions(+), 16 deletions(-) create mode 100644 lib/efi_selftest/dtbdump.c
Re: [PATCH] efi_loader: improve detection of ESP for storing UEFI variables
> From: Heinrich Schuchardt
> Date: Mon, 9 Nov 2020 15:36:33 +0100
>
> On 09.11.20 14:51, Mark Kettenis wrote:
> >> From: Paulo Alcantara
> >> Date: Mon, 09 Nov 2020 10:24:08 -0300
> >>
> >> Heinrich Schuchardt writes:
> >>
> >>> On 09.11.20 00:58, Paulo Alcantara wrote:
> The UEFI specification does not restrict on the number and location of
> ESPs in a system. They are discovered as required by looking at the
> partition type, but firmware implementations are allowed to support
> ESPs which do not contain a valid partition type.
> >>>
> >>> I guess you refer to chapter "13.3.3 Number and Location of System
> >>> Partitions" of the UEFI spec saying: "Further, UEFI implementations
> >>> may allow the use of conforming FAT partitions which do not use the
> >>> ESP GUID."
> >>
> >> Yep, sorry. Thanks for pointing it out!
> >>
> >>> Why should U-Boot support FAT partitions that are not of type FAT 0xef
> >>> and GPT partition that do not use the ESP GUID?
> >>
> >> In most UEFI (EDK2-based) systems I used, I could boot my OSes and
> >> diagnostic tools by simply having a supported filesystem (FAT12/16/32)
> >> and /EFI/BOOT/BOOT{ARCH}.EFI file and never cared about setting the
> >> partition type at all. It took me a while for figuring out why I
> >> couldn't get my UEFI variables loaded from my FAT partition that
> >> contained /ubootefi.var and /EFI/BOOT/BOOTAA64.efi files.
> >
> > The OpenBSD installation media for armv7 and arm64 use a FAT partition
> > of type 0x0c because the Raspberry Pi firmware doesn't support 0xef.
> > This allows us to have a single FAT partition with the Raspberry Pi
> > firmware, U-Boot and /EFI/BOOT/BOOT{ARCH}.EFI.
> >
> > So far this works on all UEFI firmware I've tried (EDK2, U-Boot and
> > AMI AptioV UEFI).
> >
>
> The issue Paulo was addressing is that U-Boot only persists non-volatile
> UEFI variables if it can find a partition indicated as ESP by the
> partition type.
>
> This becomes interesting if you want to have both Linux and OpenBSD on
> the same device and you want to use UEFI boot variables to decide which
> operating system to boot or if you want to use secure boot.
>
> On Debian the ESP is an 0xef partition mounted at /boot/efi.
>
> SUSE recommends the same:
> https://www.suse.com/support/kb/doc/?id=17007
> https://documentation.suse.com/sles/15-SP1/html/SLES-all/cha-uefi.html
>
> For a Raspberry I typically would have the following partitions:
>
> / - root file system
> /boot/firmware - *first* FAT partition
> /boot/efi - ESP, FAT formatted
>
> As /boot/firmware and /boot/efi can be separate partitions with
> different partition type why does OpenBSD not use this scheme?
Two reasons:
1. The installer and the scripts that build the installer image only
support creating a single FAT partition.
2. Adding another FAT partition would consume another slot in the
disklabel[1] which doesn't have a lot of empty slots left for a
default install.
Cheers,
Mark
[1] A disklabel is the platform-independent partition table that is
used by BSD systems and for example Solaris on SPARC.
Re: [PATCH] x86: Avoid using hardcoded number of variable range MTRRs in mtrr_commit()
Hi Bin,
On Mon, 9 Nov 2020 at 01:05, Bin Meng wrote:
>
> Since commit 29d2d64ed55f ("x86: Add support for more than 8 MTRRs"),
> the maximum number of variable range MTRRs was increased from 8 to 10,
> which caused a #GP exception during VESA video driver probe.
>
> On the BayTrail platform there are only 8 variable range MTRRs. In
> mtrr_commit() it still uses MTRR_MAX_COUNT which should have been
> updated to use dynamically probed number.
>
> This fixes the boot failure seen on Intel Minnow Max board.
>
> Fixes: 29d2d64ed55f ("x86: Add support for more than 8 MTRRs")
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/mtrr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Simon Glass
I don't actually see the boot failure in my lab, but this looks right to me.
Regards,
Simon
[PATCH v2] mmc: atmel-sdhci: fix the clk_enable call in case of no ops
If the clock driver does not offer a clk_enable ops, then the system will
return -ENOSYS.
The clk_enable works with CCF (common clock framework).
Some clocks in some cases (like the generic clock for some products: sama5d2)
do not have the clk_enable primitive, and in this case probing of the driver
will fail.
This patch changes the behavior to return an error in case there is really
an error, and not a missing primitive.
If the clock driver does not have an enable primitive, most likely clocks
are always enabled or enabled in the set_rate primitives.
Fixes: 81f16438d4 ("mmc: atmel-sdhci: enable the required generic clock")
Signed-off-by: Eugen Hristev
---
Changes in v2:
- fixed issue with ret being 0, it was going to return ret;, when in fact
there was no error. Have to check for both ret != 0 and ret != -ENOSYS.
drivers/mmc/atmel_sdhci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c
index f56ae63bc2..ca7a98bf1d 100644
--- a/drivers/mmc/atmel_sdhci.c
+++ b/drivers/mmc/atmel_sdhci.c
@@ -86,7 +86,8 @@ static int atmel_sdhci_probe(struct udevice *dev)
return -EINVAL;
ret = clk_enable(&clk);
- if (ret)
+ /* return error only if the clock really has a clock enable func */
+ if (ret && ret != -ENOSYS)
return ret;
ret = mmc_of_parse(dev, &plat->cfg);
--
2.25.1
