[PATCH 1/1] doc: move README.commands to HTML doc
Reformat README.commands as reStructured text and add it to the HTML
documentation as develop/commands.rst.
Signed-off-by: Heinrich Schuchardt
---
doc/README.commands | 186
doc/develop/commands.rst | 226 +++
doc/develop/index.rst| 1 +
3 files changed, 227 insertions(+), 186 deletions(-)
delete mode 100644 doc/README.commands
create mode 100644 doc/develop/commands.rst
diff --git a/doc/README.commands b/doc/README.commands
deleted file mode 100644
index 22ab063fdc..00
--- a/doc/README.commands
+++ /dev/null
@@ -1,186 +0,0 @@
-Command definition
---
-
-Commands are added to U-Boot by creating a new command structure.
-This is done by first including command.h, then using the U_BOOT_CMD() or the
-U_BOOT_CMD_COMPLETE macro to fill in a struct cmd_tbl struct.
-
-U_BOOT_CMD(name, maxargs, repeatable, command, "usage", "help")
-U_BOOT_CMD_COMPLETE(name, maxargs, repeatable, command, "usage, "help", comp)
-
-name: The name of the command. THIS IS NOT a string.
-
-maxargs: The maximum number of arguments this function takes including
- the command itself.
-
-repeatable:Either 0 or 1 to indicate if autorepeat is allowed.
-
-command: Pointer to the command function. This is the function that is
- called when the command is issued.
-
-usage: Short description. This is a string.
-
-help: Long description. This is a string. The long description is
- only available if CONFIG_SYS_LONGHELP is defined.
-
-comp: Pointer to the completion function. May be NULL.
- This function is called if the user hits the TAB key while
- entering the command arguments to complete the entry. Command
- completion is only available if CONFIG_AUTO_COMPLETE is defined.
-
-Sub-command definition
---
-
-Likewise an array of struct cmd_tbl holding sub-commands can be created using
either
-of the following macros:
-
-* U_BOOT_CMD_MKENT(name, maxargs, repeatable, command, "usage", "help")
-* U_BOOT_CMD_MKENTCOMPLETE(name, maxargs, repeatable, command, "usage, "help",
- comp)
-
-This table has to be evaluated in the command function of the main command,
e.g.
-
-static struct cmd_tbl cmd_sub[] = {
-U_BOOT_CMD_MKENT(foo, CONFIG_SYS_MAXARGS, 1, do_foo, "", ""),
-U_BOOT_CMD_MKENT(bar, CONFIG_SYS_MAXARGS, 1, do_bar, "", ""),
-};
-
-static int do_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const
argv[])
-{
-struct cmd_tbl *cp;
-
-if (argc < 2)
-return CMD_RET_USAGE;
-
-/* drop sub-command argument */
-argc--;
-argv++;
-
-cp = find_cmd_tbl(argv[0], cmd_ut_sub, ARRAY_SIZE(cmd_sub));
-
-if (cp)
-return cp->cmd(cmdtp, flag, argc, argv);
-
-return CMD_RET_USAGE;
-}
-
-Command function
-
-
-The command function pointer has to be of type
-int (*cmd)(struct cmd_tbl *cmdtp, int flag, int argc, const char *argv[]);
-
-cmdtp: Table entry describing the command (see above).
-
-flag: A bitmap which may contain the following bit:
- CMD_FLAG_REPEAT - The last command is repeated.
- CMD_FLAG_BOOTD - The command is called by the bootd command.
- CMD_FLAG_ENV- The command is called by the run command.
-
-argc: Number of arguments including the command.
-
-argv: Arguments.
-
-Allowable return value are:
-
-CMD_RET_SUCCESSThe command was successfully executed.
-
-CMD_RET_FAILUREThe command failed.
-
-CMD_RET_USAGE The command was called with invalid parameters. This value
- leads to the display of the usage string.
-
-Completion function
-
-The completion function pointer has to be of type
-int (*complete)(int argc, char *const argv[], char last_char,
- int maxv, char *cmdv[]);
-
-argc: Number of arguments including the command.
-
-argv: Arguments.
-
-last_char: The last character in the command line buffer.
-
-maxv: Maximum number of possible completions that may be returned by
- the function.
-
-cmdv: Used to return possible values for the last argument. The last
- possible completion must be followed by NULL.
-
-The function returns the number of possible completions (without the
terminating
-NULL value).
-
-Behind the scene
-
-
-The structure created is named with a special prefix and placed by
-the linker in a special section using the linker lists mechanism
-(see include/linker_lists.h)
-
-This makes it possible for the final link to extract all commands
-compiled into any object code and construct a static array so the
-command array can be iterated over using the linker lists macros.
-
-The linker lists feature ensures
Re: [PATCH 2/2] board: presidio: Add Parallel NAND support
Hi Tom, after this NAND driver is in master, we can look at reducing the number of defconfigs for this board and send out a new patch. Thanks -Alex > On Dec 11, 2020, at 12:54 PM, Tom Rini wrote: > > On Tue, Dec 08, 2020 at 11:37:37AM -0800, Alex Nemirovsky wrote: > >> From: Kate Liu >> >> Set environment for Nand flash (U-boot 2020.04): >> - add nand flash in the device tree >> - add new default configuration file for G3 using parallel Nand >> - set nand parameters in presidio_asic.h >> >> Signed-off-by: Kate Liu >> Signed-off-by: Alex Nemirovsky >> CC: Tom Rini >> --- >> >> MAINTAINERS | 1 + >> arch/arm/dts/ca-presidio-engboard.dts | 14 +++ >> configs/cortina_presidio-asic-pnand_defconfig | 34 >> +++ > > A small thing, the defconfig being added here (and aside, I gather we > can't have a single defconfig for all variants?) needs to be > re-generated with savedefconfig. There's a blank line in it which > implies that it wasn't. Thanks. > > -- > Tom
[PATCH v2 1/2] mtd: rawnand: cortina_nand: Add Cortina CAxxxx SoC support
From: Kate Liu
Add Cortina Access parallel Nand support for CA SOCs
Signed-off-by: Kate Liu
Signed-off-by: Alex Nemirovsky
CC: Tom Rini
CC: Scott Wood
---
Changes in v2:
- Cleanup nand_ctrl struct offset comments
MAINTAINERS |2 +
drivers/mtd/nand/raw/Kconfig| 12 +
drivers/mtd/nand/raw/Makefile |1 +
drivers/mtd/nand/raw/cortina_nand.c | 1390 +++
drivers/mtd/nand/raw/cortina_nand.h | 293
5 files changed, 1698 insertions(+)
create mode 100644 drivers/mtd/nand/raw/cortina_nand.c
create mode 100644 drivers/mtd/nand/raw/cortina_nand.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 2625fc6..a002263 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -197,6 +197,8 @@ F: drivers/led/led_cortina.c
F: drivers/mmc/ca_dw_mmc.c
F: drivers/i2c/i2c-cortina.c
F: drivers/i2c/i2c-cortina.h
+F: drivers/mtd/nand/raw/cortina_nand.c
+F: drivers/mtd/nand/raw/cortina_nand.h
ARM/CZ.NIC TURRIS MOX SUPPORT
M: Marek Behun
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 3cf3b14..ed151ee 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -321,6 +321,18 @@ config NAND_STM32_FMC2
The controller supports a maximum 8k page size and supports
a maximum 8-bit correction error per sector of 512 bytes.
+config CORTINA_NAND
+ bool "Support for NAND controller on Cortina-Access SoCs"
+ depends on CORTINA_PLATFORM
+ select SYS_NAND_SELF_INIT
+ select DM_MTD
+ imply CMD_NAND
+ help
+ Enables support for NAND Flash chips on Coartina-Access SoCs platform
+ This controller is found on Presidio/Venus SoCs.
+ The controller supports a maximum 8k page size and supports
+ a maximum 40-bit error correction per sector of 1024 bytes.
+
comment "Generic NAND options"
config SYS_NAND_BLOCK_SIZE
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index 24c51b6..f3f0e15 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_NAND_PLAT) += nand_plat.o
obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o
obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o
obj-$(CONFIG_NAND_STM32_FMC2) += stm32_fmc2_nand.o
+obj-$(CONFIG_CORTINA_NAND) += cortina_nand.o
else # minimal SPL drivers
diff --git a/drivers/mtd/nand/raw/cortina_nand.c
b/drivers/mtd/nand/raw/cortina_nand.c
new file mode 100644
index 000..480ef63
--- /dev/null
+++ b/drivers/mtd/nand/raw/cortina_nand.c
@@ -0,0 +1,1390 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020, Cortina Access Inc..
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "cortina_nand.h"
+
+static unsigned int *pread, *pwrite;
+
+static const struct udevice_id cortina_nand_dt_ids[] = {
+ {
+.compatible = "cortina,ca-nand",
+},
+ { /* sentinel */ }
+};
+
+static struct nand_ecclayout eccoob;
+
+/* Information about an attached NAND chip */
+struct fdt_nand {
+ int enabled;/* 1 to enable, 0 to disable */
+ s32 width; /* bit width, must be 8 */
+ u32 nand_ecc_strength;
+};
+
+struct nand_drv {
+ u32 fifo_index;
+ struct nand_ctlr *reg;
+ struct dma_global *dma_glb;
+ struct dma_ssp *dma_nand;
+ struct tx_descriptor_t *tx_desc;
+ struct rx_descriptor_t *rx_desc;
+ struct fdt_nand config;
+ unsigned int flash_base;
+};
+
+struct ca_nand_info {
+ struct udevice *dev;
+ struct nand_drv nand_ctrl;
+ struct nand_chip nand_chip;
+};
+
+/**
+ * Wait for command completion
+ *
+ * @param reg nand_ctlr structure
+ * @return
+ * 1 - Command completed
+ * 0 - Timeout
+ */
+static int nand_waitfor_cmd_completion(struct nand_ctlr *reg, unsigned int
mask)
+{
+ unsigned int reg_v = 0;
+
+ if (readl_poll_timeout(>flash_flash_access_start, reg_v,
+ !(reg_v & mask), (FLASH_LONG_DELAY << 2))) {
+ pr_err("Nand CMD timeout!\n");
+ return 0;
+ }
+
+ return 1;
+}
+
+/**
+ * Read one byte from the chip
+ *
+ * @param mtd MTD device structure
+ * @return data byte
+ *
+ * Read function for 8bit bus-width
+ */
+static uint8_t read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct nand_drv *info;
+ u8 ret_v;
+
+ info = (struct nand_drv *)nand_get_controller_data(chip);
+
+ clrsetbits_le32(>reg->flash_flash_access_start, GENMASK(31, 0),
+ NFLASH_GO | NFLASH_RD);
+
+ if (!nand_waitfor_cmd_completion(info->reg, NFLASH_GO))
+ printf("%s: Command timeout\n", __func__);
+
+ ret_v = readl(>reg->flash_nf_data) >> (8 *
[PATCH v2 2/2] board: presidio: Add Parallel NAND support
From: Kate Liu
Set environment for Nand flash (U-boot 2020.04):
- add nand flash in the device tree
- add new default configuration file for G3 using parallel Nand
- set nand parameters in presidio_asic.h
Signed-off-by: Kate Liu
Signed-off-by: Alex Nemirovsky
CC: Tom Rini
---
Changes in v2:
- auto generate defconfig with savedefconfig
MAINTAINERS | 1 +
arch/arm/dts/ca-presidio-engboard.dts | 14
configs/cortina_presidio-asic-pnand_defconfig | 33 +++
include/configs/presidio_asic.h | 9
4 files changed, 57 insertions(+)
create mode 100644 configs/cortina_presidio-asic-pnand_defconfig
diff --git a/MAINTAINERS b/MAINTAINERS
index a002263..a4d5f30 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -199,6 +199,7 @@ F: drivers/i2c/i2c-cortina.c
F: drivers/i2c/i2c-cortina.h
F: drivers/mtd/nand/raw/cortina_nand.c
F: drivers/mtd/nand/raw/cortina_nand.h
+F: configs/cortina_presidio-asic-pnand_defconfig
ARM/CZ.NIC TURRIS MOX SUPPORT
M: Marek Behun
diff --git a/arch/arm/dts/ca-presidio-engboard.dts
b/arch/arm/dts/ca-presidio-engboard.dts
index eef433e..0ab52fd 100644
--- a/arch/arm/dts/ca-presidio-engboard.dts
+++ b/arch/arm/dts/ca-presidio-engboard.dts
@@ -52,6 +52,20 @@
clock-frequency = <40>;
};
+ nand: nand-controller@f4324000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "cortina,ca-nand";
+ reg = <0 0xf4324000 0x3b0>, /* NAND controller */
+ <0 0xf7001000 0xb4>, /* DMA_GLOBAL */
+ <0 0xf7001a00 0x80>; /* DMA channel0 for FLASH */
+ status = "okay";
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <16>;
+ nand-ecc-step-size = <1024>;/* Must be 1024 */
+ nand_flash_base_addr = <0xe000>;
+ };
+
sflash: sflash-controller@f4324000 {
#address-cells = <2>;
#size-cells = <1>;
diff --git a/configs/cortina_presidio-asic-pnand_defconfig
b/configs/cortina_presidio-asic-pnand_defconfig
new file mode 100644
index 000..e85cdc5
--- /dev/null
+++ b/configs/cortina_presidio-asic-pnand_defconfig
@@ -0,0 +1,33 @@
+CONFIG_ARM=y
+# CONFIG_SYS_ARCH_TIMER is not set
+CONFIG_TARGET_PRESIDIO_ASIC=y
+CONFIG_SYS_TEXT_BASE=0x0400
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2
+CONFIG_DM_GPIO=y
+CONFIG_IDENT_STRING="Presidio-SoC"
+CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="earlycon=serial,0xf4329148 console=ttyS0,115200
root=/dev/ram0"
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SYS_PROMPT="G3#"
+CONFIG_CMD_MTD=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_SMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+# CONFIG_NET is not set
+CONFIG_DM=y
+CONFIG_CORTINA_GPIO=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_CORTINA_NAND=y
+CONFIG_DM_SERIAL=y
+CONFIG_CORTINA_UART=y
+CONFIG_WDT=y
+CONFIG_WDT_CORTINA=y
diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h
index 34235b5..710731e 100644
--- a/include/configs/presidio_asic.h
+++ b/include/configs/presidio_asic.h
@@ -67,4 +67,13 @@
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0"
+/* nand driver parameters */
+#ifdef CONFIG_TARGET_PRESIDIO_ASIC
+ #define CONFIG_SYS_NAND_ONFI_DETECTION
+ #define CONFIG_SYS_MAX_NAND_DEVICE 1
+ #define CONFIG_SYS_NAND_MAX_CHIPS 1
+ #define CONFIG_SYS_NAND_BASECONFIG_SYS_FLASH_BASE
+ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#endif
+
#endif /* __PRESIDIO_ASIC_H */
--
2.7.4
Re: [PATCH 0/9] dm: treewide: Tidy up and adjust driver model naming
Hi, On Thu, 3 Dec 2020 at 16:55, Simon Glass wrote: > > There are several naming problems in driver model which I think are worth > sorting out. > > FIrstly, the _auto_alloc_size suffix is widely used but is quite > long-winded. In earlier days it made some sense since auto allocation was > a strange concept. But with driver model now used pretty universally, we > can shorten this to 'auto'. This reduces verbosity and makes the code > easier to read. > > Secondly, in newer code we use 'priv' (rather than privdata) and 'plat' > for private data but this is not consistent. In many places 'platdata' is > used for platform data. We can't really use 'pdata' since that is > ambiguous (it could mean private or platform data). So this series > standardises on 'plat'. > > Finally, ofdata_to_platdata is shortened to of_to_plat since the 'data' > bits are redundant. > > These changes apply tree-wide. The series is available at u-boot-dm/auto > > > Simon Glass (9): > dtoc: Tidy up more Python style in dtb_platdata > dm: treewide: Rename auto_alloc_size members to be shorter > dm: treewide: Rename 'platdata' variables to just 'plat' > dm: Rename 'platdata_size' to 'plat_size' > dm: treewide: Rename dev_get_platdata() to dev_get_plat() > dm: treewide: Rename ofdata_to_platdata() to of_to_plat() > dm: treewide: Update 'auto' declarations to be on one line > dm: treewide: Rename ..._platdata variables to just ..._plat > checkpatch: Add warnings for unexpected struct names Any thoughts on this rename? I'd like to apply it before it gets too stale. Regards, Simon
Re: [PATCH 1/2] mtd: rawnand: cortina_nand: Add Cortina CAxxxx SoC support
On Tue, Dec 08, 2020 at 11:37:36AM -0800, Alex Nemirovsky wrote:
> From: Kate Liu
>
> Add Cortina Access parallel Nand support for CA SOCs
>
> Signed-off-by: Kate Liu
> Signed-off-by: Alex Nemirovsky
> CC: Tom Rini
> CC: Scott Wood
A one small things:
[snip]
> +struct nand_ctlr {
> + /* Cortina NAND controller register */
> + u32 flash_id;// offset 0x000
> + u32 flash_timeout; // offset 0x004
> + u32 flash_status;// offset 0x008
> + u32 flash_type;// offset 0x00c
> + u32 flash_flash_access_start; // offset 0x010
> + u32 flash_flash_interrupt; // offset 0x014
> + u32 flash_flash_mask;// offset 0x018
> + u32 flash_fifo_control;// offset 0x01c
> + u32 flash_fifo_status; // offset 0x020
> + u32 flash_fifo_address;// offset 0x024
> + u32 flash_fifo_match_address; // offset 0x028
> + u32 flash_fifo_data; // offset 0x02c
> + u32 flash_sf_access; // offset 0x030
> + u32 flash_sf_ext_access; // offset 0x034
> + u32 flash_sf_address;// offset 0x038
> + u32 flash_sf_data; // offset 0x03c
> + u32 flash_sf_timing; // offset 0x040
> + u32 resv[3];
> + u32 flash_pf_access; // offset 0x050
We don't need the offset commented on every member. Typically it's not
done (which is annoying in debug / verification), but it is nice to see
after a reserved block. Can you remove most of them so it's just
showing the post-resv offsets? Thanks.
--
Tom
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Re: [PATCH 2/2] board: presidio: Add Parallel NAND support
On Tue, Dec 08, 2020 at 11:37:37AM -0800, Alex Nemirovsky wrote: > From: Kate Liu > > Set environment for Nand flash (U-boot 2020.04): > - add nand flash in the device tree > - add new default configuration file for G3 using parallel Nand > - set nand parameters in presidio_asic.h > > Signed-off-by: Kate Liu > Signed-off-by: Alex Nemirovsky > CC: Tom Rini > --- > > MAINTAINERS | 1 + > arch/arm/dts/ca-presidio-engboard.dts | 14 +++ > configs/cortina_presidio-asic-pnand_defconfig | 34 > +++ A small thing, the defconfig being added here (and aside, I gather we can't have a single defconfig for all variants?) needs to be re-generated with savedefconfig. There's a blank line in it which implies that it wasn't. Thanks. -- Tom signature.asc Description: PGP signature
Re: Pull request for UEFI sub-system for next
On Thu, Dec 10, 2020 at 07:34:56PM +0100, Heinrich Schuchardt wrote: > Dear Tom, > > The following changes since commit 03f1f78a9b44b5fd6fc09faf81639879d2d0f85f: > > spl: fit: Prefer a malloc()'d buffer for loading images (2020-12-07 > 17:40:34 -0500) > > are available in the Git repository at: > > https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git tags/efi-next > > for you to fetch changes up to 264485131c59c1c8fa17fe742bbca65cef868d94: > > efi_loader: link partition to block device (2020-12-10 09:15:33 +0100) > Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: pull request of u-boot-fsl-qoriq for v2021.01
On Fri, Dec 11, 2020 at 07:44:52AM +, Priyanka Jain wrote: > Dear Tom, > > Please find my pull-request for u-boot-fsl-qoriq/master > https://github.com/u-boot/u-boot/pull/42/checks > > Summary > Add lx2162 soc, lx2162qds support. > Bug-fixes related ls102x-usb, ifc, bootcmd, secure-boot header, > rgmii, vid, fdt, env variable, pci for Layerscape products > > Thanks > Priyanka Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-atmel-fixes-2021.01-b
Hello Tom, Please pull tag u-boot-atmel-fixes-2021.01-b , the second set of atmel fixes for 2021.01 cycle. This set includes very important fixes for: MMC booting on several boards, drive strength on sam9x60ek mmc lines, compile issues for timer.c old driver, removal of unwanted access to sam9x60 bit for oscillator bypass mode, and eeproms read on sama5d2_icp. Thanks ! Eugen The following changes since commit 1ae955e3a58f46918ef99b0b6c562967ba1bf39e: Prepare v2021.01-rc2 (2020-11-09 17:20:05 -0500) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-atmel.git tags/u-boot-atmel-fixes-2021.01-b for you to fetch changes up to bb5eedbc7fbddc7849bb10a239facac29b615c1c: ARM: dts: at91: sama5d2_icp: fix i2c eeprom compatible (2020-12-11 17:47:21 +0200) Second set of u-boot-atmel fixes for 2021.01 cycle Claudiu Beznea (1): clk: at91: sam9x60: remove the parsing of atmel, main-osc-bypass Eugen Hristev (4): mmc: atmel-sdhci: fix the clk_enable call in case of no ops ARM: dts: at91: sam9x60: enable slewrate/high drive for sdhci0 pinout ARM: mach-at91: fix timer.o compile condition ARM: dts: at91: sama5d2_icp: fix i2c eeprom compatible Nicolas Ferre (1): ARM: at91: armv7: sama7g5 uses CCF clock driver arch/arm/dts/at91-sama5d2_icp.dts | 6 +++--- arch/arm/dts/sam9x60.dtsi | 18 -- arch/arm/mach-at91/armv7/Makefile | 12 +++- arch/arm/mach-at91/armv7/cpu.c| 4 drivers/clk/at91/sam9x60.c| 5 + drivers/mmc/atmel_sdhci.c | 3 ++- 6 files changed, 29 insertions(+), 19 deletions(-)
Re: [PATCH v4 0/4] Add Renesas SoC identification driver support
On Mon, Nov 30, 2020 at 3:18 AM Biju Das wrote: > > Hi All, > > Gentle Ping. Please let me know, are we happy with this patch series? > I have a series pending this as well. thank you, adam > The patch series[1] is blocked by this. > [1] > http://u-boot.10912.n7.nabble.com/PATCH-v7-0-4-Add-CPU-identification-support-for-RZ-G2-SoC-s-tt433694.html#a433807 > > Cheers, > Biju > > > -Original Message- > > From: Biju Das > > Sent: 16 November 2020 13:04 > > To: Simon Glass ; Marek Vasut > > > > Cc: Biju Das ; Dave Gerlach > gerl...@ti.com>; Prabhakar Mahadev Lad > lad...@bp.renesas.com>; u-boot@lists.denx.de; Nobuhiro Iwamatsu > > ; Chris Paterson > > Subject: [PATCH v4 0/4] Add Renesas SoC identification driver support > > > > This patch series aims to support Renesas SoC identification driver. > > > > Added a helper function of_match_node to find the matching of_match > > structure. This helper function can be used to replace the following code > > in u-boot [1] and [2] > > > > [1] > > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Felixir.b > > ootlin.com%2Fu- > > boot%2Flatest%2Fsource%2Fdrivers%2Fserial%2Fserial_uniphier.c%23L129d > > ata=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7Ccc01f2630adf48bdb3c408d88a306 > > 996%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637411287820999264%7CUnkn > > own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJX > > VCI6Mn0%3D%7C1000sdata=YmZ52jZrOQqXhvbflvy5XWnXsfb7FIRgxpY1XhBI6YE%3D > > reserved=0 > > [2] > > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Felixir.b > > ootlin.com%2Fu- > > boot%2Flatest%2Fsource%2Fdrivers%2Fusb%2Fphy%2Frockchip_usb2_phy.c%23L77 > > mp;data=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7Ccc01f2630adf48bdb3c408d88 > > a306996%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637411287820999264%7C > > Unknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwi > > LCJXVCI6Mn0%3D%7C1000sdata=N2wF3aZNCkN7TQlA%2FbhV3ggDjZdYVjjS%2F0tOFf > > j%2BkOE%3Dreserved=0 > > > > Also added soc_id attribute support in UCLASS_SOC which is required for > > Renesas SoC identification driver similar to mainline linux. > > > > v3->v4 > > * Added Simon's Rb tag > > * Updated patch description for SoC identification using soc_id > > * Updated probe function of Renesas SoC identification driver. > > > > Biju Das (4): > > dm: core: Add of_match_node helper function > > soc: Fix comments from SOC to SoC > > dm: soc: Add SoC id for attribute matching > > dm: soc: SoC identification driver for Renesas SoC's > > > > drivers/core/device.c | 21 > > drivers/soc/Kconfig | 7 ++ > > drivers/soc/Makefile | 1 + > > drivers/soc/soc-uclass.c | 19 ++- > > drivers/soc/soc_renesas.c | 244 ++ > > drivers/soc/soc_sandbox.c | 8 ++ > > include/dm/device.h | 13 ++ > > include/soc.h | 39 +- > > test/dm/core.c| 31 + > > test/dm/soc.c | 8 ++ > > 10 files changed, 384 insertions(+), 7 deletions(-) create mode 100644 > > drivers/soc/soc_renesas.c > > > > -- > > 2.17.1 >
Re: [PATCH] ARM: dts: at91: sama5d2_icp: fix i2c eeprom compatible
On 07.12.2020 10:39, Eugen Hristev wrote: > The correct compatible for this eeproms is microchip,24aa02e48 > The previous compatible string was working up to U-boot 2020.04. > > Signed-off-by: Eugen Hristev > Tested-by: Codrin Ciubotariu > --- Applied to u-boot-atmel/master
[PATCH] bootcount: allow to use this feature on TPL
This commit add an option TPL_BOOTCOUNT_LIMIT to
use bootcount on TPL.
Signed-off-by: Philippe Reynes
---
common/spl/Kconfig | 9 -
common/spl/spl.c| 4 +++-
drivers/Makefile| 1 +
include/bootcount.h | 6 +++---
4 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index d8086bd9e8..29c64ebb80 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -177,7 +177,7 @@ config SPL_BOOTROM_SUPPORT
config SPL_BOOTCOUNT_LIMIT
bool "Support bootcount in SPL"
- depends on SPL_ENV_SUPPORT
+ depends on SPL_ENV_SUPPORT && !TPL_BOOTCOUNT_LIMIT
help
On some boards, which use 'falcon' mode, it is necessary to check
and increment the number of boot attempts. Such boards do not
@@ -1363,6 +1363,13 @@ config TPL_BOARD_INIT
spl_board_init() from board_init_r(). This function should be
provided by the board.
+config TPL_BOOTCOUNT_LIMIT
+ bool "Support bootcount in TPL"
+ depends on TPL_ENV_SUPPORT
+ help
+ If this option is enabled, the TPL will support bootcount.
+ For example, it may be useful to choose the device to boot.
+
config TPL_LDSCRIPT
string "Linker script for the TPL stage"
depends on TPL
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 63c48fbf33..c432f14c29 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -833,7 +833,9 @@ ulong spl_relocate_stack_gd(void)
#endif
}
-#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_SPL_BOOTCOUNT_LIMIT)
+#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
+ ((!defined(CONFIG_TPL_BUILD) && !defined(CONFIG_SPL_BOOTCOUNT_LIMIT))
|| \
+(defined(CONFIG_TPL_BUILD) && !defined(CONFIG_TPL_BOOTCOUNT_LIMIT)))
void bootcount_store(ulong a)
{
}
diff --git a/drivers/Makefile b/drivers/Makefile
index e371bc32bb..c562a719f7 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -69,6 +69,7 @@ endif
ifdef CONFIG_TPL_BUILD
+obj-$(CONFIG_TPL_BOOTCOUNT_LIMIT) += bootcount/
obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
endif
diff --git a/include/bootcount.h b/include/bootcount.h
index cd30403984..b1d1fe53d1 100644
--- a/include/bootcount.h
+++ b/include/bootcount.h
@@ -69,7 +69,7 @@ void bootcount_store(ulong);
*/
ulong bootcount_load(void);
-#if defined(CONFIG_SPL_BOOTCOUNT_LIMIT) || defined(CONFIG_BOOTCOUNT_LIMIT)
+#if defined(CONFIG_SPL_BOOTCOUNT_LIMIT) || defined(CONFIG_TPL_BOOTCOUNT_LIMIT)
|| defined(CONFIG_BOOTCOUNT_LIMIT)
#if !defined(CONFIG_SYS_BOOTCOUNT_LE) && !defined(CONFIG_SYS_BOOTCOUNT_BE)
# if __BYTE_ORDER == __LITTLE_ENDIAN
@@ -130,7 +130,7 @@ static inline void bootcount_inc(void)
#ifndef CONFIG_SPL_BUILD
/* Only increment bootcount when no bootcount support in SPL */
-#ifndef CONFIG_SPL_BOOTCOUNT_LIMIT
+#if !defined(CONFIG_SPL_BOOTCOUNT_LIMIT) &&
!defined(CONFIG_TPL_BOOTCOUNT_LIMIT)
bootcount_store(++bootcount);
#endif
env_set_ulong("bootcount", bootcount);
@@ -140,5 +140,5 @@ static inline void bootcount_inc(void)
#else
static inline int bootcount_error(void) { return 0; }
static inline void bootcount_inc(void) {}
-#endif /* CONFIG_SPL_BOOTCOUNT_LIMIT || CONFIG_BOOTCOUNT_LIMIT */
+#endif /* CONFIG_SPL_BOOTCOUNT_LIMIT || CONFIG_TPL_BOOTCOUNT_LIMIT ||
CONFIG_BOOTCOUNT_LIMIT */
#endif /* _BOOTCOUNT_H__ */
--
2.17.1
Re: [PATCH 4/8] dm: Introduce xxx_get_dma_range()
Hi Nicolas, > > > Add the follwing functions to get a specific device's DMA ranges: > > > - dev_get_dma_range() > > > - ofnode_get_dma_range() > > > - of_get_dma_range() > > > - fdt_get_dma_range() > > > They are specially useful in oder to be able validate a physical address > > > space range into a bus's and to convert addresses from and to address > > > spaces. > > > > I'm seeing issues with this patch, with the just posted v2 as well > > (it's not arrived in my inbox as yet). > > I think didn't directly CC you, sorry for that. I'll keep it in mind for the > next round. > > > I get the following linking error when building across a number of devices > > such as Jetson boards like jetson-tk1, p3450-, as well as puma-rk3399, > > marsboard, udoo, udoo_neo. The error is: > > Thanks for having a lookg at this. I've been strugling to test my series > against all posible configurations. What are you using catch the regressions? > Is something I can run locally? It's just the list of configs we build for Fedora. > > /usr/bin/arm-linux-gnu-ld.bfd -pie --gc-sections -Bstatic > > --no-dynamic-linker -Ttext 0x8780 -o u-boot -T u-boot.lds > > arch/arm/cpu/armv7/start.o --start-group arch/arm/cpu/built-in.o > > arch/arm/cpu/armv7/built-in.o arch/arm/lib/built-in.o > > arch/arm/mach-imx/built-in.o board/udoo/neo/built-in.o > > cmd/built-in.o common/built-in.o disk/built-in.o drivers/built-in.o > > drivers/dma/built-in.o drivers/gpio/built-in.o > > drivers/i2c/built-in.o drivers/net/built-in.o > > drivers/net/phy/built-in.o drivers/power/built-in.o > > drivers/power/battery/built-in.o drivers/power/domain/built-in.o > > drivers/power/fuel_gauge/built-in.o drivers/power/mfd/built-in.o > > drivers/power/pmic/built-in.o drivers/power/regulator/built-in.o > > drivers/serial/built-in.o drivers/spi/built-in.o > > drivers/usb/cdns3/built-in.o drivers/usb/common/built-in.o > > drivers/usb/dwc3/built-in.o drivers/usb/emul/built-in.o > > drivers/usb/eth/built-in.o drivers/usb/host/built-in.o > > drivers/usb/mtu3/built-in.o drivers/usb/musb-new/built-in.o > > drivers/usb/musb/built-in.o drivers/usb/phy/built-in.o > > drivers/usb/ulpi/built-in.o env/built-in.o fs/built-in.o > > lib/built-in.o net/built-in.o --end-group arch/arm/lib/eabi_compat.o > > arch/arm/lib/lib.a -Map u-boot.map; true > > /usr/bin/arm-linux-gnu-ld.bfd: drivers/built-in.o: in function > > `dev_get_dma_range': > > /home/perobins/fedora/packages/uboot-tools/u-boot-2021.01-rc3/include/dm/read.h:1025: > > undefined reference to `ofnode_get_dma_range' > > make[1]: *** > > [/home/perobins/fedora/packages/uboot-tools/u-boot-2021.01-rc3/Makefile:1757: > > u-boot] Error 1 > > make[1]: Leaving directory > > '/home/perobins/fedora/packages/uboot-tools/u-boot-2021.01-rc3/builds/udoo_neo' > > I reproduced it locally, thanks! I'll fit it. > > Regards, > Nicolas >
Re: [PATCH] arm: mvebu: armada-xp-gp.dts: Add spi0 alias
Tested-by: Dennis Gilmore
On Fri, 2020-12-11 at 05:47 +0100, Stefan Roese wrote:
> For correct spi bus detection the spi0 alias is needed in the DT.
> Otherwise this error will ocurr in U-Boot:
>
> Invalid bus 0 (err=-19)
> Failed to initialize SPI flash at 0:0 (error -19)
>
> Signed-off-by: Stefan Roese
> Cc: Dennis Gilmore
> ---
> arch/arm/dts/armada-xp-gp.dts | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/dts/armada-xp-gp.dts b/arch/arm/dts/armada-xp-
> gp.dts
> index 1139e9469a..d46475fe22 100644
> --- a/arch/arm/dts/armada-xp-gp.dts
> +++ b/arch/arm/dts/armada-xp-gp.dts
> @@ -31,6 +31,10 @@
> stdout-path = "serial0:115200n8";
> };
>
> + aliases {
> + spi0 =
> + };
> +
> memory@0 {
> device_type = "memory";
> /*
Re: [PATCH] arm: mvebu: Add armada-xp-gp-u-boot.dtsi for U-Boot properties
Tested-by: Dennis Gilmore
On Thu, 2020-12-10 at 06:40 +0100, Stefan Roese wrote:
> Add some missing "u-boot,dm-pre-reloc;" properties to UART0, SPI
> controller and SPI NOR flash node to enable usage in SPL. Otherwise
> these devices will not be available.
>
> Signed-off-by: Stefan Roese
> Cc: Dennis Gilmore
> ---
> arch/arm/dts/armada-xp-gp-u-boot.dtsi | 19 +++
> 1 file changed, 19 insertions(+)
> create mode 100644 arch/arm/dts/armada-xp-gp-u-boot.dtsi
>
> diff --git a/arch/arm/dts/armada-xp-gp-u-boot.dtsi
> b/arch/arm/dts/armada-xp-gp-u-boot.dtsi
> new file mode 100644
> index 00..2422856616
> --- /dev/null
> +++ b/arch/arm/dts/armada-xp-gp-u-boot.dtsi
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +/ {
> + soc {
> + internal-regs {
> + serial@12000 {
> + u-boot,dm-pre-reloc;
> + };
> + };
> + };
> +};
> +
> + {
> + u-boot,dm-pre-reloc;
> +
> + spi-flash@0 {
> + u-boot,dm-pre-reloc;
> + };
> +};
Re: [PATCH 00/27] dm: Change the way sequence numbers are implemented
Hi Michal, Heinrich,
On Fri, 11 Dec 2020 at 00:54, Michal Simek wrote:
>
>
>
> On 11. 12. 20 8:42, Heinrich Schuchardt wrote:
> > On 12/11/20 8:28 AM, Michal Simek wrote:
> >> Hi Simon,
> >>
> >> On 10. 12. 20 18:46, Simon Glass wrote:
> >>> Hi Michal,
> >>>
> >>> On Thu, 10 Dec 2020 at 10:33, Michal Simek
> >>> wrote:
>
> Hi Simon,
>
> On 10. 12. 20 18:27, Simon Glass wrote:
> > Hi Michal,
> >
> > On Thu, 10 Dec 2020 at 00:34, Michal Simek
> > wrote:
> >>
> >> Hi,
> >>
> >> On 09. 12. 20 17:30, Michael Walle wrote:
> >>> Hi Simon,
> >>>
> >>> Am 2020-12-09 17:23, schrieb Simon Glass:
> On Tue, 8 Dec 2020 at 15:52, Michael Walle
> wrote:
> > Am 2020-11-30 02:53, schrieb Simon Glass:
> >> At present each device has two sequence numbers, with
> >> 'req_seq' being
> >> set up at bind time and 'seq' at probe time. The idea is that
> >> devices
> >> can 'request' a sequence number and then the conflicts are
> >> resolved
> >> when
> >> the device is probed.
> >>
> >> This makes things complicated in a few cases, since we don't
> >> really
> >> know
> >> (at bind time) what the sequence number will end up being. We
> >> want to
> >> honour the bind-time requests if at all possible, but in fact
> >> the only
> >> source of these at present is the devicetree aliases.
> >>
> >> Apart from the obvious need for sequence numbers to supports
> >> U-Boot's
> >> numbering on devices on the command line, the current scheme was
> >> designed to:
> >>
> >> - avoid calculating the sequence number until it is needed, to
> >> save
> >>execution time
> >> - allow multiple devices to obtain a particular sequence
> >> number as
> > they
> >>are probed and removed
> >> - retain a record of the 'requested' sequence number even if
> >> it turns
> >> out
> >>that a device could not get it (to allow debugging and
> >> retrying)
> >>
> >> After some years using the current scheme it seems on balance
> >> that
> >> these
> >> goals don't have as much merit as first thought. The first
> >> point would
> >> be persuasive except that we end up reading the devicetree
> >> aliases at
> >> bind-time anyway. So the work of resolving the sequence
> >> numbers during
> >> probing is not that great. The second point hasn't really been an
> >> issue,
> >> as there is typically no contention for sequence numbers
> >> (boards tend
> >> to
> >> allocate them statically in the devicetree). Re the third
> >> point, we
> > can
> >> often figure out what was requested by looking at aliases, and
> >> in the
> >> cases where we can't, it doesn't seem to matter much.
> >>
> >> Since we have the devicetree available at bind time, we may as
> >> well
> >> just
> >> use it, in the hope that the required processing will turn out
> >> to be
> >> useful later (i.e. the device actually gets used). In
> >> addition, it is
> >> simpler to use a single sequence number, since it avoids
> >> confusion and
> >> some extra code.
> >>
> >> This series moves U-Boot to use a single, bind-time sequence
> >> number.
> >> All
> >> uclasses with the DM_UC_FLAG_SEQ_ALIAS flag enabled will assign
> >> sequence
> >> numbers to their devices, so that as soon as a device is
> >> bound, it has
> >> a
> >> sequence number. If a devicetree alias provides the number, it
> >> will be
> >> used. Otherwise, during initial binding, the first free number is
> > used.
> >
> > What does "first free number mean"?
> >
> > I have a device tree with the following aliases for network:
> >
> > aliases {
> > ethernet0 =
> > ethernet1 =
> > ethernet2 =
> > ethernet3 =
> > };
> >
> > The individual devices might be disabled, depending on the
> > board variant
> > (which might also be dynamically determined during startup).
>
> By disabled, do you mean that they are marked 'status =
> "disabled"'?
> >>>
> >>> yes
> >>>
> If so, then they are ignored by DM and will not claim their number.
>
> >
> > My first smoke test with this series show the following:
> >
> > uclass 32: eth
> > 0 * enetc-0 @ ffd40e60,
Re: [PATCH 00/27] dm: Change the way sequence numbers are implemented
On 11. 12. 20 8:42, Heinrich Schuchardt wrote:
> On 12/11/20 8:28 AM, Michal Simek wrote:
>> Hi Simon,
>>
>> On 10. 12. 20 18:46, Simon Glass wrote:
>>> Hi Michal,
>>>
>>> On Thu, 10 Dec 2020 at 10:33, Michal Simek
>>> wrote:
Hi Simon,
On 10. 12. 20 18:27, Simon Glass wrote:
> Hi Michal,
>
> On Thu, 10 Dec 2020 at 00:34, Michal Simek
> wrote:
>>
>> Hi,
>>
>> On 09. 12. 20 17:30, Michael Walle wrote:
>>> Hi Simon,
>>>
>>> Am 2020-12-09 17:23, schrieb Simon Glass:
On Tue, 8 Dec 2020 at 15:52, Michael Walle
wrote:
> Am 2020-11-30 02:53, schrieb Simon Glass:
>> At present each device has two sequence numbers, with
>> 'req_seq' being
>> set up at bind time and 'seq' at probe time. The idea is that
>> devices
>> can 'request' a sequence number and then the conflicts are
>> resolved
>> when
>> the device is probed.
>>
>> This makes things complicated in a few cases, since we don't
>> really
>> know
>> (at bind time) what the sequence number will end up being. We
>> want to
>> honour the bind-time requests if at all possible, but in fact
>> the only
>> source of these at present is the devicetree aliases.
>>
>> Apart from the obvious need for sequence numbers to supports
>> U-Boot's
>> numbering on devices on the command line, the current scheme was
>> designed to:
>>
>> - avoid calculating the sequence number until it is needed, to
>> save
>> execution time
>> - allow multiple devices to obtain a particular sequence
>> number as
> they
>> are probed and removed
>> - retain a record of the 'requested' sequence number even if
>> it turns
>> out
>> that a device could not get it (to allow debugging and
>> retrying)
>>
>> After some years using the current scheme it seems on balance
>> that
>> these
>> goals don't have as much merit as first thought. The first
>> point would
>> be persuasive except that we end up reading the devicetree
>> aliases at
>> bind-time anyway. So the work of resolving the sequence
>> numbers during
>> probing is not that great. The second point hasn't really been an
>> issue,
>> as there is typically no contention for sequence numbers
>> (boards tend
>> to
>> allocate them statically in the devicetree). Re the third
>> point, we
> can
>> often figure out what was requested by looking at aliases, and
>> in the
>> cases where we can't, it doesn't seem to matter much.
>>
>> Since we have the devicetree available at bind time, we may as
>> well
>> just
>> use it, in the hope that the required processing will turn out
>> to be
>> useful later (i.e. the device actually gets used). In
>> addition, it is
>> simpler to use a single sequence number, since it avoids
>> confusion and
>> some extra code.
>>
>> This series moves U-Boot to use a single, bind-time sequence
>> number.
>> All
>> uclasses with the DM_UC_FLAG_SEQ_ALIAS flag enabled will assign
>> sequence
>> numbers to their devices, so that as soon as a device is
>> bound, it has
>> a
>> sequence number. If a devicetree alias provides the number, it
>> will be
>> used. Otherwise, during initial binding, the first free number is
> used.
>
> What does "first free number mean"?
>
> I have a device tree with the following aliases for network:
>
> aliases {
> ethernet0 =
> ethernet1 =
> ethernet2 =
> ethernet3 =
> };
>
> The individual devices might be disabled, depending on the
> board variant
> (which might also be dynamically determined during startup).
By disabled, do you mean that they are marked 'status =
"disabled"'?
>>>
>>> yes
>>>
If so, then they are ignored by DM and will not claim their number.
>
> My first smoke test with this series show the following:
>
> uclass 32: eth
> 0 * enetc-0 @ ffd40e60, seq 0
> 1 * ax88179_eth @ ffd51f50, seq 1
>
> Looks like the usb ethernet device will get seq 1 assigned
> (after "usb
> start"). Is this intended?
>
> If so, this is a problem, because for ethernet devices, the MAC
> address
> is assigned according to the ethNaddr
Re: [PATCH 00/27] dm: Change the way sequence numbers are implemented
Hi Simon,
On 10. 12. 20 18:46, Simon Glass wrote:
> Hi Michal,
>
> On Thu, 10 Dec 2020 at 10:33, Michal Simek wrote:
>>
>> Hi Simon,
>>
>> On 10. 12. 20 18:27, Simon Glass wrote:
>>> Hi Michal,
>>>
>>> On Thu, 10 Dec 2020 at 00:34, Michal Simek wrote:
Hi,
On 09. 12. 20 17:30, Michael Walle wrote:
> Hi Simon,
>
> Am 2020-12-09 17:23, schrieb Simon Glass:
>> On Tue, 8 Dec 2020 at 15:52, Michael Walle wrote:
>>> Am 2020-11-30 02:53, schrieb Simon Glass:
At present each device has two sequence numbers, with 'req_seq' being
set up at bind time and 'seq' at probe time. The idea is that devices
can 'request' a sequence number and then the conflicts are resolved
when
the device is probed.
This makes things complicated in a few cases, since we don't really
know
(at bind time) what the sequence number will end up being. We want to
honour the bind-time requests if at all possible, but in fact the only
source of these at present is the devicetree aliases.
Apart from the obvious need for sequence numbers to supports U-Boot's
numbering on devices on the command line, the current scheme was
designed to:
- avoid calculating the sequence number until it is needed, to save
execution time
- allow multiple devices to obtain a particular sequence number as
>>> they
are probed and removed
- retain a record of the 'requested' sequence number even if it turns
out
that a device could not get it (to allow debugging and retrying)
After some years using the current scheme it seems on balance that
these
goals don't have as much merit as first thought. The first point would
be persuasive except that we end up reading the devicetree aliases at
bind-time anyway. So the work of resolving the sequence numbers during
probing is not that great. The second point hasn't really been an
issue,
as there is typically no contention for sequence numbers (boards tend
to
allocate them statically in the devicetree). Re the third point, we
>>> can
often figure out what was requested by looking at aliases, and in the
cases where we can't, it doesn't seem to matter much.
Since we have the devicetree available at bind time, we may as well
just
use it, in the hope that the required processing will turn out to be
useful later (i.e. the device actually gets used). In addition, it is
simpler to use a single sequence number, since it avoids confusion and
some extra code.
This series moves U-Boot to use a single, bind-time sequence number.
All
uclasses with the DM_UC_FLAG_SEQ_ALIAS flag enabled will assign
sequence
numbers to their devices, so that as soon as a device is bound, it has
a
sequence number. If a devicetree alias provides the number, it will be
used. Otherwise, during initial binding, the first free number is
>>> used.
>>>
>>> What does "first free number mean"?
>>>
>>> I have a device tree with the following aliases for network:
>>>
>>> aliases {
>>> ethernet0 =
>>> ethernet1 =
>>> ethernet2 =
>>> ethernet3 =
>>> };
>>>
>>> The individual devices might be disabled, depending on the board variant
>>> (which might also be dynamically determined during startup).
>>
>> By disabled, do you mean that they are marked 'status = "disabled"'?
>
> yes
>
>> If so, then they are ignored by DM and will not claim their number.
>>
>>>
>>> My first smoke test with this series show the following:
>>>
>>>uclass 32: eth
>>>0 * enetc-0 @ ffd40e60, seq 0
>>>1 * ax88179_eth @ ffd51f50, seq 1
>>>
>>> Looks like the usb ethernet device will get seq 1 assigned (after "usb
>>> start"). Is this intended?
>>>
>>> If so, this is a problem, because for ethernet devices, the MAC address
>>> is assigned according to the ethNaddr variable. And at least for this
>>> board (kontron_sl28) the first four are reserved for the ones with the
>>> alias entries. Thus I'd have expected that the usb device will get seq 4
>>> assigned.
>>
>> OK, so you mean after all existing aliases, even if they did not bind.
>> I think we can do that.
>
> Great, that will also match the current behavior. See
> be1a6e94254af205bd67d69e3bdb26b161ccd72f ("dm: uclass: don't assign
> aliased seq numbers")
Also take a look at 83e4c7e9ffa57fe4116967999c223c952a46a78a
which is more or less the same things as is done in linux
[PATCH v1 05/50] mips: octeon: Add cvmx-bgxx-defs.h header file
From: Aaron Williams Import cvmx-bgxx-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- .../mach-octeon/include/mach/cvmx-bgxx-defs.h | 4106 + 1 file changed, 4106 insertions(+) create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-bgxx-defs.h diff --git a/arch/mips/mach-octeon/include/mach/cvmx-bgxx-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-bgxx-defs.h new file mode 100644 index 00..7bcf805827 --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/cvmx-bgxx-defs.h @@ -0,0 +1,4106 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Marvell International Ltd. + * + * Configuration and status register (CSR) type definitions for + * Octeon bgxx. + */ + +#ifndef __CVMX_BGXX_DEFS_H__ +#define __CVMX_BGXX_DEFS_H__ + +#define CVMX_BGXX_CMRX_CONFIG(offset, block_id) \ + (0x00011800E000ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576) +#define CVMX_BGXX_CMRX_INT(offset, block_id) \ + (0x00011800E020ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576) +#define CVMX_BGXX_CMRX_PRT_CBFC_CTL(offset, block_id) \ + (0x00011800E408ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576) +#define CVMX_BGXX_CMRX_RX_ADR_CTL(offset, block_id) \ + (0x00011800E0A0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576) +#define CVMX_BGXX_CMRX_RX_BP_DROP(offset, block_id) \ + (0x00011800E080ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576) +#define CVMX_BGXX_CMRX_RX_BP_OFF(offset, block_id) \ + (0x00011800E090ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576) +#define CVMX_BGXX_CMRX_RX_BP_ON(offset, block_id) \ + (0x00011800E088ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576) +#define CVMX_BGXX_CMRX_RX_BP_STATUS(offset, block_id) \ + (0x00011800E0A8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576) +#define CVMX_BGXX_CMRX_RX_FIFO_LEN(offset, block_id) \ + (0x00011800E0C0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576) +#define CVMX_BGXX_CMRX_RX_ID_MAP(offset, block_id) \ + (0x00011800E028ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576) +#define CVMX_BGXX_CMRX_RX_LOGL_XOFF(offset, block_id) \ + (0x00011800E0B0ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576) +#define CVMX_BGXX_CMRX_RX_LOGL_XON(offset, block_id) \ + (0x00011800E0B8ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576) +#define CVMX_BGXX_CMRX_RX_PAUSE_DROP_TIME(offset, block_id) \ + (0x00011800E030ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576) +#define CVMX_BGXX_CMRX_RX_STAT0(offset, block_id) \ + (0x00011800E038ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576) +#define CVMX_BGXX_CMRX_RX_STAT1(offset, block_id) \ + (0x00011800E040ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576) +#define CVMX_BGXX_CMRX_RX_STAT2(offset, block_id) \ + (0x00011800E048ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576) +#define CVMX_BGXX_CMRX_RX_STAT3(offset, block_id) \ + (0x00011800E050ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576) +#define CVMX_BGXX_CMRX_RX_STAT4(offset, block_id) \ + (0x00011800E058ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576) +#define CVMX_BGXX_CMRX_RX_STAT5(offset, block_id) \ + (0x00011800E060ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576) +#define CVMX_BGXX_CMRX_RX_STAT6(offset, block_id) \ + (0x00011800E068ull + (((offset) & 3) + ((block_id) & 7) * 0x10ull) * 1048576) +#define CVMX_BGXX_CMRX_RX_STAT7(offset, block_id) \ + (0x00011800E070ull + (((offset) & 3) + ((block_id) & 7)
[PATCH v1 03/50] mips: octeon: Add cvmx-agl-defs.h header file
From: Aaron Williams Import cvmx-agl-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- .../mach-octeon/include/mach/cvmx-agl-defs.h | 3135 + 1 file changed, 3135 insertions(+) create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-agl-defs.h diff --git a/arch/mips/mach-octeon/include/mach/cvmx-agl-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-agl-defs.h new file mode 100644 index 00..bbf1f5936b --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/cvmx-agl-defs.h @@ -0,0 +1,3135 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Marvell International Ltd. + * + * Configuration and status register (CSR) type definitions for + * Octeon agl. + * + */ + +#ifndef __CVMX_AGL_DEFS_H__ +#define __CVMX_AGL_DEFS_H__ + +#define CVMX_AGL_GMX_BAD_REG (0x00011800E518ull) +#define CVMX_AGL_GMX_BIST (0x00011800E400ull) +#define CVMX_AGL_GMX_DRV_CTL (0x00011800E7F0ull) +#define CVMX_AGL_GMX_INF_MODE (0x00011800E7F8ull) +#define CVMX_AGL_GMX_PRTX_CFG(offset) (0x00011800E010ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) (0x00011800E180ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) (0x00011800E188ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) (0x00011800E190ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) (0x00011800E198ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) (0x00011800E1A0ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) (0x00011800E1A8ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset)(0x00011800E108ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) (0x00011800E100ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_DECISION(offset) (0x00011800E040ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) (0x00011800E020ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) (0x00011800E018ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) (0x00011800E030ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) (0x00011800E028ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_IFG(offset) (0x00011800E058ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_INT_EN(offset) (0x00011800E008ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_INT_REG(offset) (0x00011800E000ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_JABBER(offset) (0x00011800E038ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset)(0x00011800E068ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_RX_INBND(offset) (0x00011800E060ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) (0x00011800E050ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset)(0x00011800E088ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) (0x00011800E098ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset)(0x00011800E0A8ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) (0x00011800E0B8ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset)(0x00011800E080ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) (0x00011800E0C0ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) (0x00011800E090ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset)(0x00011800E0A0ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) (0x00011800E0B0ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) (0x00011800E048ull + ((offset) & 1) * 2048) +#define CVMX_AGL_GMX_RX_BP_DROPX(offset) (0x00011800E420ull + ((offset) & 1) * 8) +#define CVMX_AGL_GMX_RX_BP_OFFX(offset) (0x00011800E460ull + ((offset) & 1) * 8) +#define CVMX_AGL_GMX_RX_BP_ONX(offset) (0x00011800E440ull + ((offset) & 1) * 8) +#define CVMX_AGL_GMX_RX_PRT_INFO (0x00011800E4E8ull) +#define CVMX_AGL_GMX_RX_TX_STATUS (0x00011800E7E8ull) +#define CVMX_AGL_GMX_SMACX(offset) (0x00011800E230ull + ((offset) & 1) * 2048)
Re: [PATCH 00/27] dm: Change the way sequence numbers are implemented
On 12/11/20 8:28 AM, Michal Simek wrote:
Hi Simon,
On 10. 12. 20 18:46, Simon Glass wrote:
Hi Michal,
On Thu, 10 Dec 2020 at 10:33, Michal Simek wrote:
Hi Simon,
On 10. 12. 20 18:27, Simon Glass wrote:
Hi Michal,
On Thu, 10 Dec 2020 at 00:34, Michal Simek wrote:
Hi,
On 09. 12. 20 17:30, Michael Walle wrote:
Hi Simon,
Am 2020-12-09 17:23, schrieb Simon Glass:
On Tue, 8 Dec 2020 at 15:52, Michael Walle wrote:
Am 2020-11-30 02:53, schrieb Simon Glass:
At present each device has two sequence numbers, with 'req_seq' being
set up at bind time and 'seq' at probe time. The idea is that devices
can 'request' a sequence number and then the conflicts are resolved
when
the device is probed.
This makes things complicated in a few cases, since we don't really
know
(at bind time) what the sequence number will end up being. We want to
honour the bind-time requests if at all possible, but in fact the only
source of these at present is the devicetree aliases.
Apart from the obvious need for sequence numbers to supports U-Boot's
numbering on devices on the command line, the current scheme was
designed to:
- avoid calculating the sequence number until it is needed, to save
execution time
- allow multiple devices to obtain a particular sequence number as
they
are probed and removed
- retain a record of the 'requested' sequence number even if it turns
out
that a device could not get it (to allow debugging and retrying)
After some years using the current scheme it seems on balance that
these
goals don't have as much merit as first thought. The first point would
be persuasive except that we end up reading the devicetree aliases at
bind-time anyway. So the work of resolving the sequence numbers during
probing is not that great. The second point hasn't really been an
issue,
as there is typically no contention for sequence numbers (boards tend
to
allocate them statically in the devicetree). Re the third point, we
can
often figure out what was requested by looking at aliases, and in the
cases where we can't, it doesn't seem to matter much.
Since we have the devicetree available at bind time, we may as well
just
use it, in the hope that the required processing will turn out to be
useful later (i.e. the device actually gets used). In addition, it is
simpler to use a single sequence number, since it avoids confusion and
some extra code.
This series moves U-Boot to use a single, bind-time sequence number.
All
uclasses with the DM_UC_FLAG_SEQ_ALIAS flag enabled will assign
sequence
numbers to their devices, so that as soon as a device is bound, it has
a
sequence number. If a devicetree alias provides the number, it will be
used. Otherwise, during initial binding, the first free number is
used.
What does "first free number mean"?
I have a device tree with the following aliases for network:
aliases {
ethernet0 =
ethernet1 =
ethernet2 =
ethernet3 =
};
The individual devices might be disabled, depending on the board variant
(which might also be dynamically determined during startup).
By disabled, do you mean that they are marked 'status = "disabled"'?
yes
If so, then they are ignored by DM and will not claim their number.
My first smoke test with this series show the following:
uclass 32: eth
0 * enetc-0 @ ffd40e60, seq 0
1 * ax88179_eth @ ffd51f50, seq 1
Looks like the usb ethernet device will get seq 1 assigned (after "usb
start"). Is this intended?
If so, this is a problem, because for ethernet devices, the MAC address
is assigned according to the ethNaddr variable. And at least for this
board (kontron_sl28) the first four are reserved for the ones with the
alias entries. Thus I'd have expected that the usb device will get seq 4
assigned.
OK, so you mean after all existing aliases, even if they did not bind.
I think we can do that.
Great, that will also match the current behavior. See
be1a6e94254af205bd67d69e3bdb26b161ccd72f ("dm: uclass: don't assign
aliased seq numbers")
Also take a look at 83e4c7e9ffa57fe4116967999c223c952a46a78a
which is more or less the same things as is done in linux
by351d224f64afc1b3b359a1738b7d4600c7e64061
And we are using it for i2c subsystem.
If you look at Linux kernel i2c/spi subsystems they are using it for
quite a while. Recently mmc subsystem starts to use it.
On the other hand we had similar discussion around networking and it has
never started to be used.
In general make sense if you have uclass that it is recorded(based on
aliases) the first highest free ID and start to use it for devices which
are not listed or don't have record in aliases.
That's IMHO the best predictable behavior we could reach. If you care
about numbering scheme then your device should have alias.
Also if there are devices which doesn't have alias keyword we should
work with DT guys to get it listed in the spec.
Do you mean the root of the name (e.g. i2c for i2c1)?
yes assigned the root of the name to
Re: patman regression?
Hi Bin,
On Thu, 10 Dec 2020 at 21:37, Bin Meng wrote:
>
> On Fri, Dec 11, 2020 at 12:32 PM Sean Anderson wrote:
> >
> > On 12/10/20 11:27 PM, Bin Meng wrote:
> > > On Fri, Dec 11, 2020 at 12:08 PM Bin Meng wrote:
> > >>
> > >> Hi Simon,
> > >>
> > >> The following command no longer works. They used to work.
> > >>
> > >> $ ./tools/patman/patman -n -c1
> > >> usage: patman [-h] [-b BRANCH] [-c COUNT] [-e END] [-D] [-p PROJECT]
> > >>[-P PATCHWORK_URL] [-s START] [-v] [-H]
> > >>{send,test,status} ...
> > >> patman: error: unrecognized arguments: -n
> > >> $ ./tools/patman/patman -n -c 1
> > >> usage: patman [-h] [-b BRANCH] [-c COUNT] [-e END] [-D] [-p PROJECT]
> > >>[-P PATCHWORK_URL] [-s START] [-v] [-H]
> > >>{send,test,status} ...
> > >> patman: error: argument -c/--count: invalid int value: 'send'
> > >>
> > >> I did not run a bisect to locate which commit introduced this. Do you
> > >> have any idea?
> > >
> > > Resetting to v2020.10, patman works again with the above 2 commands.
> > >
> > > Note the latest patman also throws an exception about commit tags
> > > while the v2020.10 version did not.
> > >
> > > Traceback (most recent call last):
> > >File "./tools/patman/patman", line 177, in
> > > control.send(args)
> > >File "./tools/patman/control.py", line 177, in send
> > > args.smtp_server)
> > >File "./tools/patman/control.py", line 136, in email_patches
> > > add_maintainers, limit)
> > >File "./tools//patman/series.py", line 264, in MakeCcFile
> > > raise_on_error=raise_on_error)
> > >File "./tools//patman/gitutil.py", line 383, in BuildEmailList
> > > raw += LookupEmail(item, alias, raise_on_error=raise_on_error)
> > >File "./tools//patman/gitutil.py", line 588, in LookupEmail
> > > raise ValueError(msg)
> > > ValueError: Alias 'doc' not found
> >
> > I also get this error even with process_tags=False.
>
> Yep, here is my patman settings:
>
> [settings]
> ignore_errors: True
> process_tags: False
> verbose: True
That error has always been, or nearly. Use -t to drop it. I have been
thinking about changing it to a warning, since even I am not that
strict about adding tags to my .patman file these days.
Re the problem you reported, I changed patman to accept a subcommand
at some point, so you need:
patman -c1 send -n
I know this is pretty annoying, so if you have any ideas on how to get
patman to do the right thing when 'send' is missing, let me know.
Regards,
Simon
[PATCH v1 40/50] mips: octeon: Add cvmx-helper.c
From: Aaron Williams
Import cvmx-helper.c from 2013 U-Boot. It will be used by the later
added drivers to support PCIe and networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-helper.c | 2611 +++
1 file changed, 2611 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-helper.c
diff --git a/arch/mips/mach-octeon/cvmx-helper.c
b/arch/mips/mach-octeon/cvmx-helper.c
new file mode 100644
index 00..529e03a147
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-helper.c
@@ -0,0 +1,2611 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Helper functions for common, but complicated tasks.
+ */
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * @INTERNAL
+ * This structure specifies the interface methods used by an interface.
+ *
+ * @param mode Interface mode.
+ *
+ * @param enumerateMethod the get number of interface ports.
+ *
+ * @param probeMethod to probe an interface to get the number
of
+ * connected ports.
+ *
+ * @param enable Method to enable an interface
+ *
+ * @param link_get Method to get the state of an interface link.
+ *
+ * @param link_set Method to configure an interface link to the specified
+ * state.
+ *
+ * @param loopback Method to configure a port in loopback.
+ */
+struct iface_ops {
+ cvmx_helper_interface_mode_t mode;
+ int (*enumerate)(int xiface);
+ int (*probe)(int xiface);
+ int (*enable)(int xiface);
+ cvmx_helper_link_info_t (*link_get)(int ipd_port);
+ int (*link_set)(int ipd_port, cvmx_helper_link_info_t link_info);
+ int (*loopback)(int ipd_port, int en_in, int en_ex);
+};
+
+/**
+ * @INTERNAL
+ * This structure is used by disabled interfaces.
+ */
+static const struct iface_ops iface_ops_dis = {
+ .mode = CVMX_HELPER_INTERFACE_MODE_DISABLED,
+};
+
+/**
+ * @INTERNAL
+ * This structure specifies the interface methods used by interfaces
+ * configured as gmii.
+ */
+static const struct iface_ops iface_ops_gmii = {
+ .mode = CVMX_HELPER_INTERFACE_MODE_GMII,
+ .enumerate = __cvmx_helper_rgmii_probe,
+ .probe = __cvmx_helper_rgmii_probe,
+ .enable = __cvmx_helper_rgmii_enable,
+ .link_get = __cvmx_helper_gmii_link_get,
+ .link_set = __cvmx_helper_rgmii_link_set,
+ .loopback = __cvmx_helper_rgmii_configure_loopback,
+};
+
+/**
+ * @INTERNAL
+ * This structure specifies the interface methods used by interfaces
+ * configured as rgmii.
+ */
+static const struct iface_ops iface_ops_rgmii = {
+ .mode = CVMX_HELPER_INTERFACE_MODE_RGMII,
+ .enumerate = __cvmx_helper_rgmii_probe,
+ .probe = __cvmx_helper_rgmii_probe,
+ .enable = __cvmx_helper_rgmii_enable,
+ .link_get = __cvmx_helper_rgmii_link_get,
+ .link_set = __cvmx_helper_rgmii_link_set,
+ .loopback = __cvmx_helper_rgmii_configure_loopback,
+};
+
+/**
+ * @INTERNAL
+ * This structure specifies the interface methods used by interfaces
+ * configured as sgmii that use the gmx mac.
+ */
+static const struct iface_ops iface_ops_sgmii = {
+ .mode = CVMX_HELPER_INTERFACE_MODE_SGMII,
+ .enumerate = __cvmx_helper_sgmii_enumerate,
+ .probe = __cvmx_helper_sgmii_probe,
+ .enable = __cvmx_helper_sgmii_enable,
+ .link_get = __cvmx_helper_sgmii_link_get,
+ .link_set = __cvmx_helper_sgmii_link_set,
+ .loopback = __cvmx_helper_sgmii_configure_loopback,
+};
+
+/**
+ * @INTERNAL
+ * This structure specifies the interface methods used by interfaces
+ * configured as sgmii that use the bgx mac.
+ */
+static const struct iface_ops iface_ops_bgx_sgmii = {
+ .mode = CVMX_HELPER_INTERFACE_MODE_SGMII,
+ .enumerate = __cvmx_helper_bgx_enumerate,
+ .probe = __cvmx_helper_bgx_probe,
+ .enable = __cvmx_helper_bgx_sgmii_enable,
+ .link_get = __cvmx_helper_bgx_sgmii_link_get,
+ .link_set = __cvmx_helper_bgx_sgmii_link_set,
+ .loopback = __cvmx_helper_bgx_sgmii_configure_loopback,
+};
+
+/**
+ * @INTERNAL
+ * This structure specifies the interface methods used by interfaces
+ * configured as qsgmii.
+ */
+static const struct iface_ops iface_ops_qsgmii = {
+ .mode = CVMX_HELPER_INTERFACE_MODE_QSGMII,
+ .enumerate = __cvmx_helper_sgmii_enumerate,
+ .probe = __cvmx_helper_sgmii_probe,
+ .enable =
[PATCH v1 41/50] mips: octeon: Add cvmx-pcie.c
From: Aaron Williams
Import cvmx-pcie.c from 2013 U-Boot. It will be used by the later
added drivers to support PCIe and networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-pcie.c | 2487 +
1 file changed, 2487 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-pcie.c
diff --git a/arch/mips/mach-octeon/cvmx-pcie.c
b/arch/mips/mach-octeon/cvmx-pcie.c
new file mode 100644
index 00..f42d44cbec
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-pcie.c
@@ -0,0 +1,2487 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Interface to PCIe as a host(RC) or target(EP)
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MRRS_CN6XXX 3 /* 1024 byte Max Read Request Size */
+#define MPS_CN6XXX 0 /* 128 byte Max Packet Size (Limit of most PCs) */
+
+/* Endian swap mode. */
+#define _CVMX_PCIE_ES 1
+
+#define CVMX_READ_CSR(addr) csr_rd_node(node, addr)
+#define CVMX_WRITE_CSR(addr, val) csr_wr_node(node, addr, val)
+#define CVMX_PCIE_CFGX_READ(p, addr) cvmx_pcie_cfgx_read_node(node, p,
addr)
+#define CVMX_PCIE_CFGX_WRITE(p, addr, val) cvmx_pcie_cfgx_write_node(node, p,
addr, val)
+
+/* #define DEBUG_PCIE */
+
+/* Delay after link up, before issuing first configuration read */
+#define PCIE_DEVICE_READY_WAIT_DELAY_MICROSECONDS 70
+
+/* Recommended Preset Vector: Drop Preset 10*/
+int pcie_preset_vec[4] = { 0x593, 0x593, 0x593, 0x593 };
+
+/* Number of LTSSM transitions to record, must be a power of 2 */
+#define LTSSM_HISTORY_SIZE 64
+#define MAX_RETRIES 2
+
+bool pcie_link_initialized[CVMX_MAX_NODES][CVMX_PCIE_MAX_PORTS];
+int cvmx_primary_pcie_bus_number = 1;
+
+static uint32_t __cvmx_pcie_config_read32(int node, int pcie_port, int bus,
int dev, int func,
+ int reg, int lst);
+
+/**
+ * Return the Core virtual base address for PCIe IO access. IOs are
+ * read/written as an offset from this address.
+ *
+ * @param pcie_port PCIe port the IO is for
+ *
+ * @return 64bit Octeon IO base address for read/write
+ */
+uint64_t cvmx_pcie_get_io_base_address(int pcie_port)
+{
+ cvmx_pcie_address_t pcie_addr;
+
+ pcie_addr.u64 = 0;
+ pcie_addr.io.upper = 0;
+ pcie_addr.io.io = 1;
+ pcie_addr.io.did = 3;
+ pcie_addr.io.subdid = 2;
+ pcie_addr.io.node = (pcie_port >> 4) & 0x3;
+ pcie_addr.io.es = _CVMX_PCIE_ES;
+ pcie_addr.io.port = (pcie_port & 0x3);
+ return pcie_addr.u64;
+}
+
+/**
+ * Size of the IO address region returned at address
+ * cvmx_pcie_get_io_base_address()
+ *
+ * @param pcie_port PCIe port the IO is for
+ *
+ * @return Size of the IO window
+ */
+uint64_t cvmx_pcie_get_io_size(int pcie_port)
+{
+ return 1ull << 32;
+}
+
+/**
+ * Return the Core virtual base address for PCIe MEM access. Memory is
+ * read/written as an offset from this address.
+ *
+ * @param pcie_port PCIe port the IO is for
+ *
+ * @return 64bit Octeon IO base address for read/write
+ */
+uint64_t cvmx_pcie_get_mem_base_address(int pcie_port)
+{
+ cvmx_pcie_address_t pcie_addr;
+
+ pcie_addr.u64 = 0;
+ pcie_addr.mem.upper = 0;
+ pcie_addr.mem.io = 1;
+ pcie_addr.mem.did = 3;
+ pcie_addr.mem.subdid = 3 + (pcie_port & 0x3);
+ pcie_addr.mem.node = (pcie_port >> 4) & 0x3;
+ return pcie_addr.u64;
+}
+
+/**
+ * Size of the Mem address region returned at address
+ * cvmx_pcie_get_mem_base_address()
+ *
+ * @param pcie_port PCIe port the IO is for
+ *
+ * @return Size of the Mem window
+ */
+uint64_t cvmx_pcie_get_mem_size(int pcie_port)
+{
+ return 1ull << 36;
+}
+
+/**
+ * @INTERNAL
+ * Return the QLM number for the PCIE port.
+ *
+ * @param pcie_port QLM number to return for.
+ *
+ * @return QLM number.
+ */
+static int __cvmx_pcie_get_qlm(int node, int pcie_port)
+{
+ if (OCTEON_IS_MODEL(OCTEON_CN73XX)) {
+ cvmx_pemx_cfg_t pem_cfg;
+ cvmx_pemx_qlm_t pem_qlm;
+ cvmx_gserx_cfg_t gserx_cfg;
+
+ switch (pcie_port) {
+ case 0: /* PEM0 */
+ gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(0));
+ if (gserx_cfg.s.pcie)
+ return 0; /* PEM0 is on QLM0 and possibly QLM1
*/
+ else
+ return -1; /* PEM0 is disabled */
+ case 1:/* PEM1 */
+
[PATCH v1 42/50] mips: octeon: Add cvmx-qlm.c
From: Aaron Williams
Import cvmx-qlm.c from 2013 U-Boot. It will be used by the later
added drivers to support PCIe and networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-qlm.c | 2350 ++
1 file changed, 2350 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-qlm.c
diff --git a/arch/mips/mach-octeon/cvmx-qlm.c b/arch/mips/mach-octeon/cvmx-qlm.c
new file mode 100644
index 00..970e34aaff
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-qlm.c
@@ -0,0 +1,2350 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Helper utilities for qlm.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Their is a copy of this in bootloader qlm configuration, make sure
+ * to update both the places till i figure out
+ */
+#define R_25G_REFCLK100 0x0
+#define R_5G_REFCLK100 0x1
+#define R_8G_REFCLK100 0x2
+#define R_125G_REFCLK15625_KX 0x3
+#define R_3125G_REFCLK15625_XAUI 0x4
+#define R_103125G_REFCLK15625_KR 0x5
+#define R_125G_REFCLK15625_SGMII 0x6
+#define R_5G_REFCLK15625_QSGMII 0x7
+#define R_625G_REFCLK15625_RXAUI 0x8
+#define R_25G_REFCLK125 0x9
+#define R_5G_REFCLK125 0xa
+#define R_8G_REFCLK125 0xb
+
+static const int REF_100MHZ = 1;
+static const int REF_125MHZ = 12500;
+static const int REF_156MHZ = 15625;
+
+static qlm_jtag_uint32_t *__cvmx_qlm_jtag_xor_ref;
+
+/**
+ * Return the number of QLMs supported by the chip
+ *
+ * @return Number of QLMs
+ */
+int cvmx_qlm_get_num(void)
+{
+ if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+ return 5;
+ else if (OCTEON_IS_MODEL(OCTEON_CN66XX))
+ return 3;
+ else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+ return 3;
+ else if (OCTEON_IS_MODEL(OCTEON_CN61XX))
+ return 3;
+ else if (OCTEON_IS_MODEL(OCTEON_CNF71XX))
+ return 2;
+ else if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return 8;
+ else if (OCTEON_IS_MODEL(OCTEON_CN73XX))
+ return 7;
+ else if (OCTEON_IS_MODEL(OCTEON_CNF75XX))
+ return 9;
+ return 0;
+}
+
+/**
+ * Return the qlm number based on the interface
+ *
+ * @param xiface interface to look up
+ *
+ * @return the qlm number based on the xiface
+ */
+int cvmx_qlm_interface(int xiface)
+{
+ struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
+
+ if (OCTEON_IS_MODEL(OCTEON_CN61XX)) {
+ return (xi.interface == 0) ? 2 : 0;
+ } else if (OCTEON_IS_MODEL(OCTEON_CN63XX) ||
OCTEON_IS_MODEL(OCTEON_CN66XX)) {
+ return 2 - xi.interface;
+ } else if (OCTEON_IS_MODEL(OCTEON_CNF71XX)) {
+ if (xi.interface == 0)
+ return 0;
+
+ debug("Warning: %s: Invalid interface %d\n",
+ __func__, xi.interface);
+ } else if (octeon_has_feature(OCTEON_FEATURE_BGX)) {
+ debug("Warning: not supported\n");
+ return -1;
+ }
+
+ /* Must be cn68XX */
+ switch (xi.interface) {
+ case 1:
+ return 0;
+ default:
+ return xi.interface;
+ }
+
+ return -1;
+}
+
+/**
+ * Return the qlm number based for a port in the interface
+ *
+ * @param xiface interface to look up
+ * @param index index in an interface
+ *
+ * @return the qlm number based on the xiface
+ */
+int cvmx_qlm_lmac(int xiface, int index)
+{
+ struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
+
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX)) {
+ cvmx_bgxx_cmr_global_config_t gconfig;
+ cvmx_gserx_phy_ctl_t phy_ctl;
+ cvmx_gserx_cfg_t gserx_cfg;
+ int qlm;
+
+ if (xi.interface < 6) {
+ if (xi.interface < 2) {
+ gconfig.u64 =
+ csr_rd_node(xi.node,
+
CVMX_BGXX_CMR_GLOBAL_CONFIG(xi.interface));
+ if (gconfig.s.pmux_sds_sel)
+ qlm = xi.interface + 2; /* QLM 2 or 3 */
+ else
+ qlm = xi.interface; /* QLM 0 or 1 */
+ } else {
+ qlm = xi.interface + 2; /* QLM 4-7 */
+ }
+
+ /* make sure the QLM is powered up and out of reset */
+
[PATCH v1 39/50] mips: octeon: Add cvmx-helper-util.c
From: Aaron Williams
Import cvmx-helper-util.c from 2013 U-Boot. It will be used by the later
added drivers to support PCIe and networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-helper-util.c | 1225 ++
1 file changed, 1225 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-helper-util.c
diff --git a/arch/mips/mach-octeon/cvmx-helper-util.c
b/arch/mips/mach-octeon/cvmx-helper-util.c
new file mode 100644
index 00..4625b4591b
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-helper-util.c
@@ -0,0 +1,1225 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Small helper utilities.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * @INTERNAL
+ * These are the interface types needed to convert interface numbers to ipd
+ * ports.
+ *
+ * @param GMII
+ * This type is used for sgmii, rgmii, xaui and rxaui interfaces.
+ * @param ILK
+ * This type is used for ilk interfaces.
+ * @param SRIO
+ * This type is used for serial-RapidIo interfaces.
+ * @param NPI
+ * This type is used for npi interfaces.
+ * @param LB
+ * This type is used for loopback interfaces.
+ * @param INVALID_IF_TYPE
+ * This type indicates the interface hasn't been configured.
+ */
+enum port_map_if_type { INVALID_IF_TYPE = 0, GMII, ILK, SRIO, NPI, LB };
+
+/**
+ * @INTERNAL
+ * This structure is used to map interface numbers to ipd ports.
+ *
+ * @param type
+ * Interface type
+ * @param first_ipd_port
+ * First IPD port number assigned to this interface.
+ * @param last_ipd_port
+ * Last IPD port number assigned to this interface.
+ * @param ipd_port_adj
+ * Different octeon chips require different ipd ports for the
+ * same interface port/mode configuration. This value is used
+ * to account for that difference.
+ */
+struct ipd_port_map {
+ enum port_map_if_type type;
+ int first_ipd_port;
+ int last_ipd_port;
+ int ipd_port_adj;
+};
+
+/**
+ * @INTERNAL
+ * Interface number to ipd port map for the octeon 68xx.
+ */
+static const struct ipd_port_map ipd_port_map_68xx[CVMX_HELPER_MAX_IFACE] = {
+ { GMII, 0x800, 0x8ff, 0x40 }, /* Interface 0 */
+ { GMII, 0x900, 0x9ff, 0x40 }, /* Interface 1 */
+ { GMII, 0xa00, 0xaff, 0x40 }, /* Interface 2 */
+ { GMII, 0xb00, 0xbff, 0x40 }, /* Interface 3 */
+ { GMII, 0xc00, 0xcff, 0x40 }, /* Interface 4 */
+ { ILK, 0x400, 0x4ff, 0x00 }, /* Interface 5 */
+ { ILK, 0x500, 0x5ff, 0x00 }, /* Interface 6 */
+ { NPI, 0x100, 0x120, 0x00 }, /* Interface 7 */
+ { LB, 0x000, 0x008, 0x00 }, /* Interface 8 */
+};
+
+/**
+ * @INTERNAL
+ * Interface number to ipd port map for the octeon 78xx.
+ *
+ * This mapping corresponds to WQE(CHAN) enumeration in
+ * HRM Sections 11.15, PKI_CHAN_E, Section 11.6
+ *
+ */
+static const struct ipd_port_map ipd_port_map_78xx[CVMX_HELPER_MAX_IFACE] = {
+ { GMII, 0x800, 0x83f, 0x00 }, /* Interface 0 - BGX0 */
+ { GMII, 0x900, 0x93f, 0x00 }, /* Interface 1 -BGX1 */
+ { GMII, 0xa00, 0xa3f, 0x00 }, /* Interface 2 -BGX2 */
+ { GMII, 0xb00, 0xb3f, 0x00 }, /* Interface 3 - BGX3 */
+ { GMII, 0xc00, 0xc3f, 0x00 }, /* Interface 4 - BGX4 */
+ { GMII, 0xd00, 0xd3f, 0x00 }, /* Interface 5 - BGX5 */
+ { ILK, 0x400, 0x4ff, 0x00 }, /* Interface 6 - ILK0 */
+ { ILK, 0x500, 0x5ff, 0x00 }, /* Interface 7 - ILK1 */
+ { NPI, 0x100, 0x13f, 0x00 }, /* Interface 8 - DPI */
+ { LB, 0x000, 0x03f, 0x00 }, /* Interface 9 - LOOPBACK */
+};
+
+/**
+ * @INTERNAL
+ * Interface number to ipd port map for the octeon 73xx.
+ */
+static const struct ipd_port_map ipd_port_map_73xx[CVMX_HELPER_MAX_IFACE] = {
+ { GMII, 0x800, 0x83f, 0x00 }, /* Interface 0 - BGX(0,0-3) */
+ { GMII, 0x900, 0x93f, 0x00 }, /* Interface 1 -BGX(1,0-3) */
+ { GMII, 0xa00, 0xa3f, 0x00 }, /* Interface 2 -BGX(2,0-3) */
+ { NPI, 0x100, 0x17f, 0x00 }, /* Interface 3 - DPI */
+ { LB, 0x000, 0x03f, 0x00 }, /* Interface 4 - LOOPBACK */
+};
+
+/**
+ * @INTERNAL
+ * Interface number to ipd port map for the octeon 75xx.
+ */
+static const struct ipd_port_map ipd_port_map_75xx[CVMX_HELPER_MAX_IFACE] = {
+ { GMII, 0x800, 0x83f, 0x00 }, /* Interface 0 - BGX0 */
+ { SRIO, 0x240, 0x241, 0x00 }, /* Interface 1 - SRIO 0 */
+ { SRIO, 0x242, 0x243, 0x00 }, /* Interface 2 - SRIO 1 */
+ { NPI, 0x100, 0x13f, 0x00 }, /* Interface 3 - DPI */
+ { LB, 0x000, 0x03f, 0x00 }, /* Interface 4 - LOOPBACK */
+};
+
+/**
+ * Convert a interface mode into a human readable string
+ *
+ * @param mode Mode to convert
+ *
+ * @return String
+ */
+const char
[PATCH v1 48/50] mips: octeon: octeon_ebb7304: Add board specific QLM init code
From: Aaron Williams
This patch adds the board specific QLM/DLM init code to the Octeon 3
EBB7304 board. The configuration of each port is read from the
environment exactly as done in the 2013 U-Boot version to keep the
board and it's configuration compatible.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
board/Marvell/octeon_ebb7304/board.c | 732 ++-
1 file changed, 730 insertions(+), 2 deletions(-)
diff --git a/board/Marvell/octeon_ebb7304/board.c
b/board/Marvell/octeon_ebb7304/board.c
index 611b18fa6a..9aac5f0b09 100644
--- a/board/Marvell/octeon_ebb7304/board.c
+++ b/board/Marvell/octeon_ebb7304/board.c
@@ -3,20 +3,32 @@
* Copyright (C) 2020 Stefan Roese
*/
-#include
#include
+#include
#include
+#include
#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
#include "board_ddr.h"
+#define MAX_MIX_ENV_VARS 4
+
#define EBB7304_DEF_DRAM_FREQ 800
static struct ddr_conf board_ddr_conf[] = {
-OCTEON_EBB7304_DDR_CONFIGURATION
+ OCTEON_EBB7304_DDR_CONFIGURATION
};
+static int no_phy[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
+
struct ddr_conf *octeon_ddr_conf_table_get(int *count, int *def_ddr_freq)
{
*count = ARRAY_SIZE(board_ddr_conf);
@@ -24,3 +36,719 @@ struct ddr_conf *octeon_ddr_conf_table_get(int *count, int
*def_ddr_freq)
return board_ddr_conf;
}
+
+/*
+ * parse_env_var: Parse the environment variable ("bgx_for_mix%d") to
+ * extract the lmac it is set to.
+ *
+ * index: Index of environment variable to parse.
+ * environment variable.
+ * env_bgx: Updated with the bgx of the lmac in the environment
+ * variable.
+ * env_lmac: Updated with the index of lmac in the environment
+ * variable.
+ *
+ * returns: Zero on success, error otherwise.
+ */
+static int parse_env_var(int index, int *env_bgx, int *env_lmac)
+{
+ char env_var[20];
+ ulong xipd_port;
+
+ sprintf(env_var, "bgx_for_mix%d", index);
+ xipd_port = env_get_ulong(env_var, 0, 0x);
+ if (xipd_port != 0x) {
+ int xiface;
+ struct cvmx_xiface xi;
+ struct cvmx_xport xp;
+
+ /*
+* The environemt variable is set to the xipd port. Convert the
+* xipd port to numa node, bgx, and lmac.
+*/
+ xiface = cvmx_helper_get_interface_num(xipd_port);
+ xi = cvmx_helper_xiface_to_node_interface(xiface);
+ xp = cvmx_helper_ipd_port_to_xport(xipd_port);
+ *env_bgx = xi.interface;
+ *env_lmac = cvmx_helper_get_interface_index_num(xp.port);
+ return 0;
+ }
+
+ return -1;
+}
+
+/*
+ * get_lmac_fdt_node: Search the device tree for the node corresponding to
+ * a given bgx lmac.
+ *
+ * fdt: Pointer to flat device tree
+ * search_node: Numa node of the lmac to search for.
+ * search_bgx:Bgx of the lmac to search for.
+ * search_lmac: Lmac index to search for.
+ * compat:Compatible string to search for.
+
+ * returns: The device tree node of the lmac if found,
+ * or -1 otherwise.
+ */
+static int get_lmac_fdt_node(const void *fdt, int search_node, int search_bgx,
int search_lmac,
+const char *compat)
+{
+ int node;
+ const fdt32_t *reg;
+ u64 addr;
+ int fdt_node = -1;
+ int fdt_bgx = -1;
+ int fdt_lmac = -1;
+ int len;
+ int parent;
+
+ /* Iterate through all bgx ports */
+ node = -1;
+ while ((node = fdt_node_offset_by_compatible((void *)fdt, node,
+compat)) >= 0) {
+ /* Get the node and bgx from the physical address */
+ parent = fdt_parent_offset(fdt, node);
+ reg = fdt_getprop(fdt, parent, "reg", );
+ if (parent < 0 || !reg)
+ continue;
+
+ addr = fdt_translate_address((void *)fdt, parent, reg);
+ fdt_node = (addr >> 36) & 0x7;
+ fdt_bgx = (addr >> 24) & 0xf;
+
+ /* Get the lmac index from the reg property */
+ reg = fdt_getprop(fdt, node, "reg", );
+ if (reg)
+ fdt_lmac = *reg;
+
+ /* Check for a match */
+ if (search_node == fdt_node && search_bgx == fdt_bgx &&
+ search_lmac == fdt_lmac)
+ return node;
+ }
+
+ return -1;
+}
+
+/*
+ * get_mix_fdt_node: Search the device tree for the node corresponding to
+ * a given mix.
+ *
+ * fdt: Pointer to flat device tree
+ * search_node: Mix numa node to search
[PATCH v1 50/50] mips: octeon: octeon_ebb7304_defconfig: Enable Octeon PCIe and E1000
This patch changes the MIPS Octeon defconfig to enable some features for PCIe enablement. This includes CONFIG_BOARD_LATE_INIT to call the board specific serdes init code. With these features enabled, the serdes and PCIe driver including the Intel E1000 driver can be tested on the Octeon EBB7304. Signed-off-by: Stefan Roese --- configs/octeon_ebb7304_defconfig | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig index a98d73a268..b2ddb4f684 100644 --- a/configs/octeon_ebb7304_defconfig +++ b/configs/octeon_ebb7304_defconfig @@ -10,7 +10,9 @@ CONFIG_ARCH_OCTEON=y # CONFIG_MIPS_CACHE_SETUP is not set # CONFIG_MIPS_CACHE_DISABLE is not set CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_FIXUP=y CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_BOARD_LATE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -42,9 +44,10 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_NETDEVICES is not set +CONFIG_E1000=y CONFIG_PCI=y CONFIG_DM_PCI=y +CONFIG_PCIE_OCTEON=y CONFIG_RAM=y CONFIG_RAM_OCTEON=y CONFIG_RAM_OCTEON_DDR4=y -- 2.29.2
[PATCH v1 43/50] mips: octeon: Add octeon_fdt.c
From: Aaron Williams
Import octeon_fdt.c from 2013 U-Boot. It will be used by the later
added drivers to support PCIe and networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/octeon_fdt.c | 1040
1 file changed, 1040 insertions(+)
create mode 100644 arch/mips/mach-octeon/octeon_fdt.c
diff --git a/arch/mips/mach-octeon/octeon_fdt.c
b/arch/mips/mach-octeon/octeon_fdt.c
new file mode 100644
index 00..199f692516
--- /dev/null
+++ b/arch/mips/mach-octeon/octeon_fdt.c
@@ -0,0 +1,1040 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#ifdef CONFIG_PCA953X
+#include
+#endif
+#ifdef CONFIG_PCF857X
+#include
+#endif
+#ifdef CONFIG_PCA9698
+#include
+#endif
+#ifdef CONFIG_PCA9554
+#include
+#endif
+#ifdef CONFIG_PCA9555
+#include
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_PCA9554
+static const char * const pca9554_gpio_list[] = {
+ "pca9554",
+ "nxp,pca9554",
+ "ti,pca9554",
+ NULL,
+};
+#endif
+
+#ifdef CONFIG_PCA9555
+static const char * const pca9555_gpio_list[] = {
+ "pca9535","nxp,pca9535", "pca9539", "nxp,pca9539", "pca9555",
+ "nxp,pca9555", "ti,pca9555", "max7312", "maxim,max7312", "max7313",
+ "maxim,max7313", "tca6416", "tca9539",NULL,
+};
+#endif
+
+#ifdef CONFIG_PCA9698
+/** List of compatible strings supported by pca9698 driver */
+static const char * const pca9698_gpio_list[] = {
+ "nxp,pca9505", "pca9505", "nxp,pca9698", "pca9698", NULL,
+};
+#endif
+
+#ifdef CONFIG_PCA953X
+/** List of compatible strings supported by pca953x driver */
+static const char * const pca953x_gpio_list[] = {
+ "nxp,pca9534", "nxp,pca9535", "nxp,pca9536", "nxp,pca9537",
"nxp,pca9538", "nxp,pca9539",
+ "nxp,pca953x", "nxp,pca9554", "nxp,pca9555", "nxp,pca9556",
"nxp,pca9557", "nxp,pca6107",
+ "pca9534", "pca9535", "pca9536", "pca9537", "pca9538",
"pca9539",
+ "pca953x", "pca9554", "pca9555", "pca9556", "pca9557",
"max7310",
+ "max7312", "max7313", "max7315", "pca6107", "tca6408",
"tca6416",
+ "tca9555", NULL
+};
+#endif
+
+#ifdef CONFIG_PHY_VITESSE
+static const char * const vitesse_vsc8488_gpio_list[] = {
+ "vitesse,vsc8486", "microsemi,vsc8486", "vitesse,vsc8488",
+ "microsemi,vsc8488", "vitesse,vsc8489", "microsemi,vsc8489",
+ "vitesse,vsc8490", "microsemi,vsc8490", NULL
+};
+#endif
+
+/** List of compatible strings supported by Octeon driver */
+static const char * const octeon_gpio_list[] = {
+ "cavium,octeon-7890-gpio",
+ "cavium,octeon-3860-gpio",
+ NULL
+};
+
+/**
+ * Trims nodes from the flat device tree.
+ *
+ * @param fdt - pointer to working FDT, usually in gd->fdt_blob
+ * @param fdt_key - key to preserve. All non-matching keys are removed
+ * @param trim_name - name of property to look for. If NULL use
+ * 'cavium,qlm-trim'
+ *
+ * The key should look something like device #, type where device # is a
+ * number from 0-9 and type is a string describing the type. For QLM
+ * operations this would typically contain the QLM number followed by
+ * the type in the device tree, like "0,xaui", "0,sgmii", etc. This function
+ * will trim all items in the device tree which match the device number but
+ * have a type which does not match. For example, if a QLM has a xaui module
+ * installed on QLM 0 and "0,xaui" is passed as a key, then all FDT nodes that
+ * have "0,xaui" will be preserved but all others, i.e. "0,sgmii" will be
+ * removed.
+ *
+ * Note that the trim_name must also match. If trim_name is NULL then it
+ * looks for the property "cavium,qlm-trim".
+ *
+ * Also, when the trim_name is "cavium,qlm-trim" or NULL that the interfaces
+ * will also be renamed based on their register values.
+ *
+ * For example, if a PIP interface is named "interface@W" and has the property
+ * reg = <0> then the interface will be renamed after this function to
+ * interface@0.
+ *
+ * @return 0 for success.
+ */
+int __octeon_fdt_patch(void *fdt, const char *fdt_key, const char *trim_name)
+{
+ bool rename = !trim_name || !strcmp(trim_name, "cavium,qlm-trim");
+
+ return octeon_fdt_patch_rename(fdt, fdt_key, trim_name, rename, NULL,
NULL);
+}
+
+int octeon_fdt_patch(void *fdt, const char *fdt_key, const char *trim_name)
+ __attribute__((weak, alias("__octeon_fdt_patch")));
+
+/**
+ * Trims nodes from the flat device tree.
+ *
+ * @param fdt - pointer to working FDT, usually in gd->fdt_blob
+ * @param fdt_key - key to preserve. All non-matching keys are removed
+ * @param trim_name - name
[PATCH v1 49/50] mips: octeon: Add Octeon PCIe host controller driver
This patch adds the PCIe host controller driver for MIPS Octeon II/III.
The driver mainly consist of the PCI config functions, as all of the
complex serdes related port / lane setup, is done in the serdes / pcie
code available in the "arch/mips/mach-octeon" directory.
Signed-off-by: Stefan Roese
---
drivers/pci/Kconfig | 6 ++
drivers/pci/Makefile | 1 +
drivers/pci/pcie_octeon.c | 159 ++
3 files changed, 166 insertions(+)
create mode 100644 drivers/pci/pcie_octeon.c
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index af92784950..bea36144e1 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -158,6 +158,12 @@ config PCI_OCTEONTX
These controllers provide PCI configuration access to all on-board
peripherals so it should only be disabled for testing purposes
+config PCIE_OCTEON
+ bool "MIPS Octeon PCIe support"
+ depends on ARCH_OCTEON
+ help
+ Enable support for the MIPS Octeon SoC family PCIe controllers.
+
config PCI_XILINX
bool "Xilinx AXI Bridge for PCI Express"
depends on DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 8b4d49a590..c8cc8272e1 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -50,3 +50,4 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o
obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
+obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
diff --git a/drivers/pci/pcie_octeon.c b/drivers/pci/pcie_octeon.c
new file mode 100644
index 00..1a76d0c429
--- /dev/null
+++ b/drivers/pci/pcie_octeon.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Stefan Roese
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+struct octeon_pcie {
+ void *base;
+ int first_busno;
+ u32 port;
+ struct udevice *dev;
+ int pcie_port;
+};
+
+static bool octeon_bdf_invalid(pci_dev_t bdf, int first_busno)
+{
+ /*
+* In PCIe only a single device (0) can exist on the local bus.
+* Beyound the local bus, there might be a switch and everything
+* is possible.
+*/
+ if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
+ return true;
+
+ return false;
+}
+
+static int pcie_octeon_write_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ struct octeon_pcie *pcie = dev_get_priv(bus);
+ struct pci_controller *hose = dev_get_uclass_priv(bus);
+ int busno;
+ int port;
+
+ debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+ debug("(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", offset, size, value);
+
+ port = pcie->pcie_port;
+ busno = PCI_BUS(bdf) - hose->first_busno + 1;
+
+ switch (size) {
+ case PCI_SIZE_8:
+ cvmx_pcie_config_write8(port, busno, PCI_DEV(bdf),
+ PCI_FUNC(bdf), offset, value);
+ break;
+ case PCI_SIZE_16:
+ cvmx_pcie_config_write16(port, busno, PCI_DEV(bdf),
+PCI_FUNC(bdf), offset, value);
+ break;
+ case PCI_SIZE_32:
+ cvmx_pcie_config_write32(port, busno, PCI_DEV(bdf),
+PCI_FUNC(bdf), offset, value);
+ break;
+ default:
+ printf("Invalid size\n");
+ };
+
+ return 0;
+}
+
+static int pcie_octeon_read_config(const struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ struct octeon_pcie *pcie = dev_get_priv(bus);
+ struct pci_controller *hose = dev_get_uclass_priv(bus);
+ int busno;
+ int port;
+
+ port = pcie->pcie_port;
+ busno = PCI_BUS(bdf) - hose->first_busno + 1;
+ if (octeon_bdf_invalid(bdf, pcie->first_busno)) {
+ *valuep = pci_get_ff(size);
+ return 0;
+ }
+
+ switch (size) {
+ case PCI_SIZE_8:
+ *valuep = cvmx_pcie_config_read8(port, busno, PCI_DEV(bdf),
+PCI_FUNC(bdf), offset);
+ break;
+ case PCI_SIZE_16:
+ *valuep = cvmx_pcie_config_read16(port, busno, PCI_DEV(bdf),
+ PCI_FUNC(bdf), offset);
+ break;
+ case PCI_SIZE_32:
+ *valuep = cvmx_pcie_config_read32(port, busno, PCI_DEV(bdf),
+ PCI_FUNC(bdf), offset);
+ break;
+ default:
+
[PATCH v1 47/50] mips: octeon: mrvl, cn73xx.dtsi: Add PCIe controller DT node
This patch adds the PCIe controller node to the MIPS Octeon 73xx dtsi
file.
Signed-off-by: Stefan Roese
---
arch/mips/dts/mrvl,cn73xx.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi
index 40eb85ee0c..461ed07969 100644
--- a/arch/mips/dts/mrvl,cn73xx.dtsi
+++ b/arch/mips/dts/mrvl,cn73xx.dtsi
@@ -203,5 +203,21 @@
dr_mode = "host";
};
};
+
+ /* PCIe 0 */
+ pcie0: pcie@118006900 {
+ compatible = "marvell,pcie-host-octeon";
+ reg = <0 0xf260 0 0x1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+
+ bus-range = <0 0xff>;
+ marvell,pcie-port = <0>;
+ ranges = <0x8100 0x 0xd000 0x00011a00
0xd000 0x 0x0100 /* IO */
+ 0x0200 0x 0xe000 0x00011b00
0xe000 0x 0x1000 /* non-prefetchable memory */
+ 0x4300 0x00011c00 0x 0x00011c00
0x 0x0010 0x>;/* prefetchable memory */
+ };
};
};
--
2.29.2
[PATCH v1 36/50] mips: octeon: Add cvmx-helper-cfg.c
From: Aaron Williams
Import cvmx-helper-cfg.c from 2013 U-Boot. It will be used by the later
added drivers to support PCIe and networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-helper-cfg.c | 1914 +++
1 file changed, 1914 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-helper-cfg.c
diff --git a/arch/mips/mach-octeon/cvmx-helper-cfg.c
b/arch/mips/mach-octeon/cvmx-helper-cfg.c
new file mode 100644
index 00..6b7dd8ac4d
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-helper-cfg.c
@@ -0,0 +1,1914 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Helper Functions for the Configuration Framework
+ */
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int cvmx_npi_max_pknds;
+static bool port_cfg_data_initialized;
+
+struct cvmx_cfg_port_param cvmx_cfg_port[CVMX_MAX_NODES][CVMX_HELPER_MAX_IFACE]
+ [CVMX_HELPER_CFG_MAX_PORT_PER_IFACE];
+/*
+ * Indexed by the pko_port number
+ */
+static int __cvmx_cfg_pko_highest_queue;
+struct cvmx_cfg_pko_port_param
+cvmx_pko_queue_table[CVMX_HELPER_CFG_MAX_PKO_PORT] = {
+ [0 ... CVMX_HELPER_CFG_MAX_PKO_PORT - 1] = {
+ CVMX_HELPER_CFG_INVALID_VALUE,
+ CVMX_HELPER_CFG_INVALID_VALUE
+ }
+};
+
+cvmx_user_static_pko_queue_config_t
+__cvmx_pko_queue_static_config[CVMX_MAX_NODES];
+
+struct cvmx_cfg_pko_port_map
+cvmx_cfg_pko_port_map[CVMX_HELPER_CFG_MAX_PKO_PORT] = {
+ [0 ... CVMX_HELPER_CFG_MAX_PKO_PORT - 1] = {
+ CVMX_HELPER_CFG_INVALID_VALUE,
+ CVMX_HELPER_CFG_INVALID_VALUE,
+ CVMX_HELPER_CFG_INVALID_VALUE
+ }
+};
+
+/*
+ * This array assists translation from ipd_port to pko_port.
+ * The ``16'' is the rounded value for the 3rd 4-bit value of
+ * ipd_port, used to differentiate ``interfaces.''
+ */
+static struct cvmx_cfg_pko_port_pair
+ipd2pko_port_cache[16][CVMX_HELPER_CFG_MAX_PORT_PER_IFACE] = {
+ [0 ... 15] = {
+ [0 ... CVMX_HELPER_CFG_MAX_PORT_PER_IFACE - 1] = {
+ CVMX_HELPER_CFG_INVALID_VALUE,
+ CVMX_HELPER_CFG_INVALID_VALUE
+ }
+ }
+};
+
+/*
+ * Options
+ *
+ * Each array-elem's initial value is also the option's default value.
+ */
+static u64 cvmx_cfg_opts[CVMX_HELPER_CFG_OPT_MAX] = {
+ [0 ... CVMX_HELPER_CFG_OPT_MAX - 1] = 1
+};
+
+/*
+ * MISC
+ */
+
+static int cvmx_cfg_max_pko_engines; /* # of PKO DMA engines allocated */
+static int cvmx_pko_queue_alloc(u64 port, int count);
+static void cvmx_init_port_cfg(void);
+static const int dbg;
+
+int __cvmx_helper_cfg_pknd(int xiface, int index)
+{
+ struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
+ int pkind;
+
+ if (!port_cfg_data_initialized)
+ cvmx_init_port_cfg();
+
+ /*
+* Only 8 PKNDs are assigned to ILK channels. The channels are wrapped
+* if more than 8 channels are configured, fix the index accordingly.
+*/
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX)) {
+ if (cvmx_helper_interface_get_mode(xiface) ==
+ CVMX_HELPER_INTERFACE_MODE_ILK)
+ index %= 8;
+ }
+
+ pkind = cvmx_cfg_port[xi.node][xi.interface][index].ccpp_pknd;
+ return pkind;
+}
+
+int __cvmx_helper_cfg_bpid(int xiface, int index)
+{
+ struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
+
+ if (!port_cfg_data_initialized)
+ cvmx_init_port_cfg();
+
+ /*
+* Only 8 BIDs are assigned to ILK channels. The channels are wrapped
+* if more than 8 channels are configured, fix the index accordingly.
+*/
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX)) {
+ if (cvmx_helper_interface_get_mode(xiface) ==
+ CVMX_HELPER_INTERFACE_MODE_ILK)
+ index %= 8;
+ }
+
+ return cvmx_cfg_port[xi.node][xi.interface][index].ccpp_bpid;
+}
+
+int __cvmx_helper_cfg_pko_port_base(int xiface, int index)
+{
+ struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
+
+ if (!port_cfg_data_initialized)
+ cvmx_init_port_cfg();
+
+ return cvmx_cfg_port[xi.node][xi.interface][index].ccpp_pko_port_base;
+}
+
+int __cvmx_helper_cfg_pko_port_num(int xiface, int index)
+{
+ struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
+
+ if (!port_cfg_data_initialized)
+ cvmx_init_port_cfg();
+
+ return
[PATCH v1 32/50] mips: octeon: Add cvmx-sso-defs.h header file
From: Aaron Williams Import cvmx-sso-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- .../mach-octeon/include/mach/cvmx-sso-defs.h | 2904 + 1 file changed, 2904 insertions(+) create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-sso-defs.h diff --git a/arch/mips/mach-octeon/include/mach/cvmx-sso-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-sso-defs.h new file mode 100644 index 00..4fc69079ac --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/cvmx-sso-defs.h @@ -0,0 +1,2904 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Marvell International Ltd. + * + * Configuration and status register (CSR) type definitions for + * Octeon sso. + */ + +#ifndef __CVMX_SSO_DEFS_H__ +#define __CVMX_SSO_DEFS_H__ + +#define CVMX_SSO_ACTIVE_CYCLES (0x0001670010E8ull) +#define CVMX_SSO_ACTIVE_CYCLESX(offset) (0x000167001100ull + ((offset) & 3) * 8) +#define CVMX_SSO_AW_ADD(0x000167002080ull) +#define CVMX_SSO_AW_CFG(0x0001670010F0ull) +#define CVMX_SSO_AW_ECO(0x000167001030ull) +#define CVMX_SSO_AW_READ_ARB (0x000167002090ull) +#define CVMX_SSO_AW_STATUS (0x0001670010E0ull) +#define CVMX_SSO_AW_TAG_LATENCY_PC (0x0001670020A8ull) +#define CVMX_SSO_AW_TAG_REQ_PC (0x0001670020A0ull) +#define CVMX_SSO_AW_WE (0x000167001080ull) +#define CVMX_SSO_BIST_STAT (0x000167001078ull) +#define CVMX_SSO_BIST_STATUS0 (0x000167001200ull) +#define CVMX_SSO_BIST_STATUS1 (0x000167001208ull) +#define CVMX_SSO_BIST_STATUS2 (0x000167001210ull) +#define CVMX_SSO_CFG (0x000167001088ull) +#define CVMX_SSO_DS_PC (0x000167001070ull) +#define CVMX_SSO_ECC_CTL0 (0x000167001280ull) +#define CVMX_SSO_ECC_CTL1 (0x000167001288ull) +#define CVMX_SSO_ECC_CTL2 (0x000167001290ull) +#define CVMX_SSO_ERR (0x000167001038ull) +#define CVMX_SSO_ERR0 (0x000167001240ull) +#define CVMX_SSO_ERR1 (0x000167001248ull) +#define CVMX_SSO_ERR2 (0x000167001250ull) +#define CVMX_SSO_ERR_ENB (0x000167001030ull) +#define CVMX_SSO_FIDX_ECC_CTL (0x0001670010D0ull) +#define CVMX_SSO_FIDX_ECC_ST (0x0001670010D8ull) +#define CVMX_SSO_FPAGE_CNT (0x000167001090ull) +#define CVMX_SSO_GRPX_AQ_CNT(offset) (0x000167002700ull + ((offset) & 255) * 0x1ull) +#define CVMX_SSO_GRPX_AQ_THR(offset) (0x000167002800ull + ((offset) & 255) * 0x1ull) +#define CVMX_SSO_GRPX_DS_PC(offset)(0x0001670020001400ull + ((offset) & 255) * 0x1ull) +#define CVMX_SSO_GRPX_EXT_PC(offset) (0x0001670020001100ull + ((offset) & 255) * 0x1ull) +#define CVMX_SSO_GRPX_IAQ_THR(offset) (0x000167002000ull + ((offset) & 255) * 0x1ull) +#define CVMX_SSO_GRPX_INT(offset) (0x000167002400ull + ((offset) & 255) * 0x1ull) +#define CVMX_SSO_GRPX_INT_CNT(offset) (0x000167002600ull + ((offset) & 255) * 0x1ull) +#define CVMX_SSO_GRPX_INT_THR(offset) (0x000167002500ull + ((offset) & 255) * 0x1ull) +#define CVMX_SSO_GRPX_PRI(offset) (0x000167002200ull + ((offset) & 255) * 0x1ull) +#define CVMX_SSO_GRPX_TAQ_THR(offset) (0x000167002100ull + ((offset) & 255) * 0x1ull) +#define CVMX_SSO_GRPX_TS_PC(offset)(0x0001670020001300ull + ((offset) & 255) * 0x1ull) +#define CVMX_SSO_GRPX_WA_PC(offset)(0x0001670020001200ull + ((offset) & 255) * 0x1ull) +#define CVMX_SSO_GRPX_WS_PC(offset)(0x0001670020001000ull + ((offset) & 255) * 0x1ull) +#define CVMX_SSO_GWE_CFG (0x000167001098ull) +#define CVMX_SSO_GWE_RANDOM(0x0001670010B0ull) +#define CVMX_SSO_GW_ECO(0x000167001038ull) +#define CVMX_SSO_IDX_ECC_CTL (0x0001670010C0ull) +#define CVMX_SSO_IDX_ECC_ST(0x0001670010C8ull) +#define CVMX_SSO_IENTX_LINKS(offset) (0x00016700A006ull + ((offset) & 4095) * 8) +#define CVMX_SSO_IENTX_PENDTAG(offset) (0x00016700A004ull + ((offset) & 4095) * 8) +#define CVMX_SSO_IENTX_QLINKS(offset) (0x00016700A008ull + ((offset) & 4095) * 8) +#define CVMX_SSO_IENTX_TAG(offset) (0x00016700A000ull + ((offset) & 4095) * 8) +#define CVMX_SSO_IENTX_WQPGRP(offset) (0x00016700A002ull + ((offset) & 4095) * 8) +#define CVMX_SSO_IPL_CONFX(offset) (0x000167008008ull + ((offset) & 255) * 8) +#define CVMX_SSO_IPL_DESCHEDX(offset) (0x000167008006ull + ((offset) & 255) * 8) +#define CVMX_SSO_IPL_FREEX(offset) (0x000167008000ull + ((offset)
[PATCH v1 46/50] mips: octeon: Kconfig: Enable CONFIG_SYS_PCI_64BIT
Setting CONFIG_SYS_PCI_64BIT is needed for correct PCIe functionality on MIPS Octeon. Signed-off-by: Stefan Roese --- arch/mips/mach-octeon/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig index e8596ed99a..d69408cc27 100644 --- a/arch/mips/mach-octeon/Kconfig +++ b/arch/mips/mach-octeon/Kconfig @@ -55,6 +55,10 @@ config SYS_ICACHE_SIZE config SYS_ICACHE_LINE_SIZE default 128 +config SYS_PCI_64BIT + bool + default y + source "board/Marvell/octeon_ebb7304/Kconfig" endmenu -- 2.29.2
[PATCH v1 45/50] mips: octeon: Makefile: Enable building of the newly added C files
This patch adds the newly added C files to the Makefile to enable compilation. This is done in a separate step, to not introduce build breakage while adding the single files with potentially missing externals. Signed-off-by: Stefan Roese --- arch/mips/mach-octeon/Makefile | 11 +++ 1 file changed, 11 insertions(+) diff --git a/arch/mips/mach-octeon/Makefile b/arch/mips/mach-octeon/Makefile index 3486aa9d8b..40ddab27ea 100644 --- a/arch/mips/mach-octeon/Makefile +++ b/arch/mips/mach-octeon/Makefile @@ -11,3 +11,14 @@ obj-y += dram.o obj-y += cvmx-coremask.o obj-y += cvmx-bootmem.o obj-y += bootoctlinux.o + +# QLM related code +obj-y += cvmx-helper-cfg.o +obj-y += cvmx-helper-fdt.o +obj-y += cvmx-helper-jtag.o +obj-y += cvmx-helper-util.o +obj-y += cvmx-helper.o +obj-y += cvmx-pcie.o +obj-y += cvmx-qlm.o +obj-y += octeon_fdt.o +obj-y += octeon_qlm.o -- 2.29.2
[PATCH v1 23/50] mips: octeon: Add cvmx-pki-defs.h header file
From: Aaron Williams Import cvmx-pki-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- .../mach-octeon/include/mach/cvmx-pki-defs.h | 2353 + 1 file changed, 2353 insertions(+) create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pki-defs.h diff --git a/arch/mips/mach-octeon/include/mach/cvmx-pki-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-pki-defs.h new file mode 100644 index 00..4465872e87 --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/cvmx-pki-defs.h @@ -0,0 +1,2353 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Marvell International Ltd. + * + * Configuration and status register (CSR) type definitions for + * Octeon pki. + */ + +#ifndef __CVMX_PKI_DEFS_H__ +#define __CVMX_PKI_DEFS_H__ + +#define CVMX_PKI_ACTIVE0(0x0001180044000220ull) +#define CVMX_PKI_ACTIVE1(0x0001180044000230ull) +#define CVMX_PKI_ACTIVE2(0x0001180044000240ull) +#define CVMX_PKI_AURAX_CFG(offset) (0x000118004490ull + ((offset) & 1023) * 8) +#define CVMX_PKI_BIST_STATUS0 (0x000118004480ull) +#define CVMX_PKI_BIST_STATUS1 (0x000118004488ull) +#define CVMX_PKI_BIST_STATUS2 (0x000118004490ull) +#define CVMX_PKI_BPIDX_STATE(offset) (0x0001180044B0ull + ((offset) & 1023) * 8) +#define CVMX_PKI_BUF_CTL(0x0001180044000100ull) +#define CVMX_PKI_CHANX_CFG(offset) (0x0001180044A0ull + ((offset) & 4095) * 8) +#define CVMX_PKI_CLKEN (0x0001180044000410ull) +#define CVMX_PKI_CLX_ECC_CTL(offset) (0x000118004400C020ull + ((offset) & 3) * 0x1ull) +#define CVMX_PKI_CLX_ECC_INT(offset) (0x000118004400C010ull + ((offset) & 3) * 0x1ull) +#define CVMX_PKI_CLX_INT(offset) (0x000118004400C000ull + ((offset) & 3) * 0x1ull) +#define CVMX_PKI_CLX_PCAMX_ACTIONX(a, b, c) \ + (0x0001180044708000ull + ((a) << 16) + ((b) << 12) + ((c) << 3)) +#define CVMX_PKI_CLX_PCAMX_MATCHX(a, b, c) \ + (0x0001180044704000ull + ((a) << 16) + ((b) << 12) + ((c) << 3)) +#define CVMX_PKI_CLX_PCAMX_TERMX(a, b, c) \ + (0x000118004470ull + ((a) << 16) + ((b) << 12) + ((c) << 3)) +#define CVMX_PKI_CLX_PKINDX_CFG(offset, block_id) \ + (0x0001180044300040ull + (((offset) & 63) + ((block_id) & 3) * 0x100ull) * 256) +#define CVMX_PKI_CLX_PKINDX_KMEMX(a, b, c) \ + (0x000118004420ull + ((a) << 16) + ((b) << 8) + ((c) << 3)) +#define CVMX_PKI_CLX_PKINDX_L2_CUSTOM(offset, block_id) \ + (0x0001180044300058ull + (((offset) & 63) + ((block_id) & 3) * 0x100ull) * 256) +#define CVMX_PKI_CLX_PKINDX_LG_CUSTOM(offset, block_id) \ + (0x0001180044300060ull + (((offset) & 63) + ((block_id) & 3) * 0x100ull) * 256) +#define CVMX_PKI_CLX_PKINDX_SKIP(offset, block_id) \ + (0x0001180044300050ull + (((offset) & 63) + ((block_id) & 3) * 0x100ull) * 256) +#define CVMX_PKI_CLX_PKINDX_STYLE(offset, block_id) \ + (0x0001180044300048ull + (((offset) & 63) + ((block_id) & 3) * 0x100ull) * 256) +#define CVMX_PKI_CLX_SMEMX(offset, block_id) \ + (0x000118004440ull + (((offset) & 2047) + ((block_id) & 3) * 0x2000ull) * 8) +#define CVMX_PKI_CLX_START(offset) (0x000118004400C030ull + ((offset) & 3) * 0x1ull) +#define CVMX_PKI_CLX_STYLEX_ALG(offset, block_id) \ + (0x0001180044501000ull + (((offset) & 63) + ((block_id) & 3) * 0x2000ull) * 8) +#define CVMX_PKI_CLX_STYLEX_CFG(offset, block_id) \ + (0x000118004450ull + (((offset) & 63) + ((block_id) & 3) * 0x2000ull) * 8) +#define CVMX_PKI_CLX_STYLEX_CFG2(offset, block_id) \ + (0x0001180044500800ull + (((offset) & 63) + ((block_id) & 3) * 0x2000ull) * 8) +#define CVMX_PKI_DSTATX_STAT0(offset) (0x0001180044C0ull + ((offset) & 1023) * 64) +#define CVMX_PKI_DSTATX_STAT1(offset) (0x0001180044C8ull + ((offset) & 1023) * 64) +#define CVMX_PKI_DSTATX_STAT2(offset) (0x0001180044C00010ull + ((offset) & 1023) * 64) +#define CVMX_PKI_DSTATX_STAT3(offset) (0x0001180044C00018ull + ((offset) & 1023) * 64) +#define CVMX_PKI_DSTATX_STAT4(offset) (0x0001180044C00020ull + ((offset) & 1023) * 64) +#define CVMX_PKI_ECC_CTL0
[PATCH v1 37/50] mips: octeon: Add cvmx-helper-fdt.c
From: Aaron Williams
Import cvmx-helper-fdt.c from 2013 U-Boot. It will be used by the later
added drivers to support PCIe and networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-helper-fdt.c | 970
1 file changed, 970 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-helper-fdt.c
diff --git a/arch/mips/mach-octeon/cvmx-helper-fdt.c
b/arch/mips/mach-octeon/cvmx-helper-fdt.c
new file mode 100644
index 00..87bc6d2adc
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-helper-fdt.c
@@ -0,0 +1,970 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * FDT Helper functions similar to those provided to U-Boot.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/** Structure used to get type of GPIO from device tree */
+struct gpio_compat {
+ char *compatible; /** Compatible string */
+ enum cvmx_gpio_type type; /** Type */
+ int8_t size; /** (max) Number of pins */
+};
+
+#define GPIO_REG_PCA953X_IN0
+#define GPIO_REG_PCA953X_OUT 1
+#define GPIO_REG_PCA953X_INVERT 2
+#define GPIO_REG_PCA953X_DIR 3
+
+#define GPIO_REG_PCA957X_IN0
+#define GPIO_REG_PCA957X_INVERT 1
+#define GPIO_REG_PCA957X_CFG 4
+#define GPIO_REG_PCA957X_OUT 5
+
+enum cvmx_i2c_mux_type { I2C_MUX, I2C_SWITCH };
+
+/** Structure used to get type of GPIO from device tree */
+struct mux_compat {
+ char *compatible;/** Compatible string */
+ enum cvmx_i2c_bus_type type; /** Mux chip type */
+ enum cvmx_i2c_mux_type mux_type; /** Type of mux */
+ u8 enable; /** Enable bit for mux */
+ u8 size; /** (max) Number of channels */
+};
+
+/**
+ * Local allocator to handle both SE and U-Boot that also zeroes out memory
+ *
+ * @param sizenumber of bytes to allocate
+ *
+ * @return pointer to allocated memory or NULL if out of memory.
+ * Alignment is set to 8-bytes.
+ */
+void *__cvmx_fdt_alloc(size_t size)
+{
+ return calloc(size, 1);
+}
+
+/**
+ * Free allocated memory.
+ *
+ * @param ptr pointer to memory to free
+ *
+ * NOTE: This only works in U-Boot since SE does not really have a freeing
+ * mechanism. In SE the memory is zeroed out.
+ */
+void __cvmx_fdt_free(void *ptr, size_t size)
+{
+ free(ptr);
+}
+
+/**
+ * Look up a phandle and follow it to its node then return the offset of that
+ * node.
+ *
+ * @param[in] fdt_addrpointer to FDT blob
+ * @param nodenode to read phandle from
+ * @param[in] prop_name name of property to find
+ * @param[in,out] lenp Number of phandles, input max number
+ * @param[out] nodes Array of phandle nodes
+ *
+ * @return -ve error code on error or 0 for success
+ */
+int cvmx_fdt_lookup_phandles(const void *fdt_addr, int node,
+const char *prop_name, int *lenp,
+int *nodes)
+{
+ const u32 *phandles;
+ int count;
+ int i;
+
+ phandles = fdt_getprop(fdt_addr, node, prop_name, );
+ if (!phandles || count < 0)
+ return -FDT_ERR_NOTFOUND;
+
+ count /= 4;
+ if (count > *lenp)
+ count = *lenp;
+
+ for (i = 0; i < count; i++)
+ nodes[i] = fdt_node_offset_by_phandle(fdt_addr,
+
fdt32_to_cpu(phandles[i]));
+ *lenp = count;
+ return 0;
+}
+
+/**
+ * Given a FDT node return the CPU node number
+ *
+ * @param[in] fdt_addrAddress of FDT
+ * @param nodeFDT node number
+ *
+ * @return CPU node number or error if negative
+ */
+int cvmx_fdt_get_cpu_node(const void *fdt_addr, int node)
+{
+ int parent = node;
+ const u32 *ranges;
+ int len = 0;
+
+ while (fdt_node_check_compatible(fdt_addr, parent, "simple-bus") != 0) {
+ parent = fdt_parent_offset(fdt_addr, parent);
+ if (parent < 0)
+ return parent;
+ }
+ ranges = fdt_getprop(fdt_addr, parent, "ranges", );
+ if (!ranges)
+ return len;
+
+ if (len == 0)
+ return 0;
+
+ if (len < 24)
+ return -FDT_ERR_TRUNCATED;
+
+ return fdt32_to_cpu(ranges[2]) / 0x10;
+}
+
+/**
+ * Get the total size of the flat device tree
+ *
+ * @param[in] fdt_addrAddress of FDT
+ *
+ * @return Size of flat device tree in bytes or error if negative.
+ */
+int cvmx_fdt_get_fdt_size(const void *fdt_addr)
+{
+ int rc;
+
+ rc = fdt_check_header(fdt_addr);
+ if (rc)
+ return rc;
+ return fdt_totalsize(fdt_addr);
+}
+
+/**
+ * Returns if a
[PATCH v1 38/50] mips: octeon: Add cvmx-helper-jtag.c
From: Aaron Williams
Import cvmx-helper-jtag.c from 2013 U-Boot. It will be used by the later
added drivers to support PCIe and networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-helper-jtag.c | 172 +++
1 file changed, 172 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-helper-jtag.c
diff --git a/arch/mips/mach-octeon/cvmx-helper-jtag.c
b/arch/mips/mach-octeon/cvmx-helper-jtag.c
new file mode 100644
index 00..a6fa69b4c5
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-helper-jtag.c
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Helper utilities for qlm_jtag.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * Initialize the internal QLM JTAG logic to allow programming
+ * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
+ * These functions should only be used at the direction of Cavium
+ * Networks. Programming incorrect values into the JTAG chain
+ * can cause chip damage.
+ */
+void cvmx_helper_qlm_jtag_init(void)
+{
+ union cvmx_ciu_qlm_jtgc jtgc;
+ int clock_div = 0;
+ int divisor;
+
+ divisor = gd->bus_clk / (100 * (OCTEON_IS_MODEL(OCTEON_CN68XX) ? 10
: 25));
+
+ divisor = (divisor - 1) >> 2;
+ /* Convert the divisor into a power of 2 shift */
+ while (divisor) {
+ clock_div++;
+ divisor >>= 1;
+ }
+
+ /*
+* Clock divider for QLM JTAG operations. sclk is divided by
+* 2^(CLK_DIV + 2)
+*/
+ jtgc.u64 = 0;
+ jtgc.s.clk_div = clock_div;
+ jtgc.s.mux_sel = 0;
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))
+ jtgc.s.bypass = 0x7;
+ else
+ jtgc.s.bypass = 0xf;
+ if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+ jtgc.s.bypass_ext = 1;
+ csr_wr(CVMX_CIU_QLM_JTGC, jtgc.u64);
+ csr_rd(CVMX_CIU_QLM_JTGC);
+}
+
+/**
+ * Write up to 32bits into the QLM jtag chain. Bits are shifted
+ * into the MSB and out the LSB, so you should shift in the low
+ * order bits followed by the high order bits. The JTAG chain for
+ * CN52XX and CN56XX is 4 * 268 bits long, or 1072. The JTAG chain
+ * for CN63XX is 4 * 300 bits long, or 1200.
+ *
+ * @param qlmQLM to shift value into
+ * @param bits Number of bits to shift in (1-32).
+ * @param data Data to shift in. Bit 0 enters the chain first, followed by
+ * bit 1, etc.
+ *
+ * @return The low order bits of the JTAG chain that shifted out of the
+ * circle.
+ */
+uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
+{
+ union cvmx_ciu_qlm_jtgc jtgc;
+ union cvmx_ciu_qlm_jtgd jtgd;
+
+ jtgc.u64 = csr_rd(CVMX_CIU_QLM_JTGC);
+ jtgc.s.mux_sel = qlm;
+ csr_wr(CVMX_CIU_QLM_JTGC, jtgc.u64);
+ csr_rd(CVMX_CIU_QLM_JTGC);
+
+ jtgd.u64 = 0;
+ jtgd.s.shift = 1;
+ jtgd.s.shft_cnt = bits - 1;
+ jtgd.s.shft_reg = data;
+ jtgd.s.select = 1 << qlm;
+ csr_wr(CVMX_CIU_QLM_JTGD, jtgd.u64);
+ do {
+ jtgd.u64 = csr_rd(CVMX_CIU_QLM_JTGD);
+ } while (jtgd.s.shift);
+ return jtgd.s.shft_reg >> (32 - bits);
+}
+
+/**
+ * Shift long sequences of zeros into the QLM JTAG chain. It is
+ * common to need to shift more than 32 bits of zeros into the
+ * chain. This function is a convience wrapper around
+ * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
+ * zeros at a time.
+ *
+ * @param qlmQLM to shift zeros into
+ * @param bits
+ */
+void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits)
+{
+ while (bits > 0) {
+ int n = bits;
+
+ if (n > 32)
+ n = 32;
+ cvmx_helper_qlm_jtag_shift(qlm, n, 0);
+ bits -= n;
+ }
+}
+
+/**
+ * Program the QLM JTAG chain into all lanes of the QLM. You must
+ * have already shifted in the proper number of bits into the
+ * JTAG chain. Updating invalid values can possibly cause chip damage.
+ *
+ * @param qlmQLM to program
+ */
+void cvmx_helper_qlm_jtag_update(int qlm)
+{
+ union cvmx_ciu_qlm_jtgc jtgc;
+ union cvmx_ciu_qlm_jtgd jtgd;
+
+ jtgc.u64 = csr_rd(CVMX_CIU_QLM_JTGC);
+ jtgc.s.mux_sel = qlm;
+
+ csr_wr(CVMX_CIU_QLM_JTGC, jtgc.u64);
+ csr_rd(CVMX_CIU_QLM_JTGC);
+
+ /* Update the new data */
+ jtgd.u64 = 0;
+ jtgd.s.update = 1;
+ jtgd.s.select = 1 << qlm;
+ csr_wr(CVMX_CIU_QLM_JTGD, jtgd.u64);
+ do {
+ jtgd.u64 = csr_rd(CVMX_CIU_QLM_JTGD);
+ } while (jtgd.s.update);
+}
+
+/**
+ * Load the QLM JTAG chain with data from all lanes of the QLM.
+ *
+ * @param qlmQLM to program
+ */
+void
[PATCH v1 34/50] mips: octeon: Misc changes required because of the newly added headers
With the newly added headers and their restructuring (which macro is
defined where), some changes in the already existing Octeon files are
necessary. This patch makes the necessary changes.
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/bootoctlinux.c | 1 +
arch/mips/mach-octeon/cvmx-bootmem.c | 6 -
arch/mips/mach-octeon/cvmx-coremask.c | 1 +
.../mips/mach-octeon/include/mach/cvmx-regs.h | 330 +-
.../mach-octeon/include/mach/octeon-feature.h | 2 +
.../mach-octeon/include/mach/octeon-model.h | 2 +
.../mach-octeon/include/mach/octeon_ddr.h | 187 +-
drivers/ram/octeon/octeon3_lmc.c | 28 +-
drivers/ram/octeon/octeon_ddr.c | 22 +-
9 files changed, 343 insertions(+), 236 deletions(-)
diff --git a/arch/mips/mach-octeon/bootoctlinux.c
b/arch/mips/mach-octeon/bootoctlinux.c
index 26136902f3..e6eefc6103 100644
--- a/arch/mips/mach-octeon/bootoctlinux.c
+++ b/arch/mips/mach-octeon/bootoctlinux.c
@@ -24,6 +24,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/mips/mach-octeon/cvmx-bootmem.c
b/arch/mips/mach-octeon/cvmx-bootmem.c
index 80bb7ac6c8..4b10effefb 100644
--- a/arch/mips/mach-octeon/cvmx-bootmem.c
+++ b/arch/mips/mach-octeon/cvmx-bootmem.c
@@ -21,12 +21,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#define CVMX_MIPS32_SPACE_KSEG01L
-#define CVMX_MIPS_SPACE_XKPHYS 2LL
-
-#define CVMX_ADD_SEG(seg, add) u64)(seg)) << 62) | (add))
-#define CVMX_ADD_SEG32(seg, add) (((u32)(seg) << 31) | (u32)(add))
-
/**
* This is the physical location of a struct cvmx_bootmem_desc
* structure in Octeon's memory. Note that dues to addressing
diff --git a/arch/mips/mach-octeon/cvmx-coremask.c
b/arch/mips/mach-octeon/cvmx-coremask.c
index cff8c08b97..ed673e4993 100644
--- a/arch/mips/mach-octeon/cvmx-coremask.c
+++ b/arch/mips/mach-octeon/cvmx-coremask.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
struct cvmx_coremask *get_coremask_override(struct cvmx_coremask *pcm)
{
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-regs.h
b/arch/mips/mach-octeon/include/mach/cvmx-regs.h
index b84fc9fd57..56528bc1bf 100644
--- a/arch/mips/mach-octeon/include/mach/cvmx-regs.h
+++ b/arch/mips/mach-octeon/include/mach/cvmx-regs.h
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
/* General defines */
#define CVMX_MAX_CORES 48
@@ -26,48 +27,116 @@
#define MAX_CORE_TADS 8
-#define CAST_ULL(v)((unsigned long long)(v))
#define CASTPTR(type, v) ((type *)(long)(v))
+#define CAST64(v) ((long long)(long)(v))
/* Regs */
-#define CVMX_CIU_PP_RST0x000101000100ULL
#define CVMX_CIU3_NMI 0x000101000160ULL
-#define CVMX_CIU_FUSE 0x0001010001a0ULL
-#define CVMX_CIU_NMI 0x000107000718ULL
#define CVMX_MIO_BOOT_LOC_CFGX(x) (0x00011880ULL + ((x) & 1) * 8)
-#define MIO_BOOT_LOC_CFG_BASE GENMASK_ULL(27, 3)
-#define MIO_BOOT_LOC_CFG_ENBIT_ULL(31)
+#define MIO_BOOT_LOC_CFG_BASE GENMASK_ULL(27, 3)
+#define MIO_BOOT_LOC_CFG_ENBIT_ULL(31)
#define CVMX_MIO_BOOT_LOC_ADR 0x00011890ULL
-#define MIO_BOOT_LOC_ADR_ADR GENMASK_ULL(7, 3)
+#define MIO_BOOT_LOC_ADR_ADR GENMASK_ULL(7, 3)
#define CVMX_MIO_BOOT_LOC_DAT 0x00011898ULL
#define CVMX_MIO_FUS_DAT2 0x000118001410ULL
-#define MIO_FUS_DAT2_NOCRYPTO BIT_ULL(26)
-#define MIO_FUS_DAT2_NOMUL BIT_ULL(27)
-#define MIO_FUS_DAT2_DORM_CRYPTO BIT_ULL(34)
+#define MIO_FUS_DAT2_NOCRYPTO BIT_ULL(26)
+#define MIO_FUS_DAT2_NOMUL BIT_ULL(27)
+#define MIO_FUS_DAT2_DORM_CRYPTO BIT_ULL(34)
#define CVMX_MIO_FUS_RCMD 0x000118001500ULL
-#define MIO_FUS_RCMD_ADDR GENMASK_ULL(7, 0)
-#define MIO_FUS_RCMD_PEND BIT_ULL(12)
-#define MIO_FUS_RCMD_DAT GENMASK_ULL(23, 16)
+#define MIO_FUS_RCMD_ADDR GENMASK_ULL(7, 0)
+#define MIO_FUS_RCMD_PEND BIT_ULL(12)
+#define MIO_FUS_RCMD_DAT GENMASK_ULL(23, 16)
#define CVMX_RNM_CTL_STATUS0x000118004000ULL
-#define RNM_CTL_STATUS_EER_VAL BIT_ULL(9)
+#define RNM_CTL_STATUS_EER_VAL BIT_ULL(9)
+
+#define CVMX_IOBDMA_ORDERED_IO_ADDR 0xa200ull
/* turn the variable name into a string */
#define CVMX_TMP_STR(x)CVMX_TMP_STR2(x)
#define CVMX_TMP_STR2(x) #x
+#define CVMX_RDHWR(result, regstr) \
+ asm volatile("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d"(result))
#define CVMX_RDHWRNV(result, regstr) \
- asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
+ asm("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d"(result))
+#define CVMX_POP(result, input)
\
+ asm("pop %[rd],%[rs]" :
[PATCH v1 22/50] mips: octeon: Add cvmx-pip-defs.h header file
From: Aaron Williams Import cvmx-pip-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- .../mach-octeon/include/mach/cvmx-pip-defs.h | 3040 + 1 file changed, 3040 insertions(+) create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pip-defs.h diff --git a/arch/mips/mach-octeon/include/mach/cvmx-pip-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-pip-defs.h new file mode 100644 index 00..574e80b6f2 --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/cvmx-pip-defs.h @@ -0,0 +1,3040 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Marvell International Ltd. + * + * Configuration and status register (CSR) type definitions for + * Octeon pip. + */ + +#ifndef __CVMX_PIP_DEFS_H__ +#define __CVMX_PIP_DEFS_H__ + +#define CVMX_PIP_ALT_SKIP_CFGX(offset) (0x00011800A0002A00ull + ((offset) & 3) * 8) +#define CVMX_PIP_BCK_PRS(0x00011800A038ull) +#define CVMX_PIP_BIST_STATUS(0x00011800A000ull) +#define CVMX_PIP_BSEL_EXT_CFGX(offset) (0x00011800A0002800ull + ((offset) & 3) * 16) +#define CVMX_PIP_BSEL_EXT_POSX(offset) (0x00011800A0002808ull + ((offset) & 3) * 16) +#define CVMX_PIP_BSEL_TBL_ENTX(offset) (0x00011800A0003000ull + ((offset) & 511) * 8) +#define CVMX_PIP_CLKEN (0x00011800A040ull) +#define CVMX_PIP_CRC_CTLX(offset) (0x00011800A040ull + ((offset) & 1) * 8) +#define CVMX_PIP_CRC_IVX(offset)(0x00011800A050ull + ((offset) & 1) * 8) +#define CVMX_PIP_DEC_IPSECX(offset) (0x00011800A080ull + ((offset) & 3) * 8) +#define CVMX_PIP_DSA_SRC_GRP(0x00011800A190ull) +#define CVMX_PIP_DSA_VID_GRP(0x00011800A198ull) +#define CVMX_PIP_FRM_LEN_CHKX(offset) (0x00011800A180ull + ((offset) & 1) * 8) +#define CVMX_PIP_GBL_CFG(0x00011800A028ull) +#define CVMX_PIP_GBL_CTL(0x00011800A020ull) +#define CVMX_PIP_HG_PRI_QOS (0x00011800A1A0ull) +#define CVMX_PIP_INT_EN (0x00011800A010ull) +#define CVMX_PIP_INT_REG(0x00011800A008ull) +#define CVMX_PIP_IP_OFFSET (0x00011800A060ull) +#define CVMX_PIP_PRI_TBLX(offset) (0x00011800A0004000ull + ((offset) & 255) * 8) +#define CVMX_PIP_PRT_CFGBX(offset) (0x00011800A0008000ull + ((offset) & 63) * 8) +#define CVMX_PIP_PRT_CFGX(offset) (0x00011800A200ull + ((offset) & 63) * 8) +#define CVMX_PIP_PRT_TAGX(offset) (0x00011800A400ull + ((offset) & 63) * 8) +#define CVMX_PIP_QOS_DIFFX(offset) (0x00011800A600ull + ((offset) & 63) * 8) +#define CVMX_PIP_QOS_VLANX(offset) (0x00011800A0C0ull + ((offset) & 7) * 8) +#define CVMX_PIP_QOS_WATCHX(offset) (0x00011800A100ull + ((offset) & 7) * 8) +#define CVMX_PIP_RAW_WORD (0x00011800A0B0ull) +#define CVMX_PIP_SFT_RST(0x00011800A030ull) +#define CVMX_PIP_STAT0_PRTX(offset) (0x00011800A800ull + ((offset) & 63) * 80) +#define CVMX_PIP_STAT0_X(offset)(0x00011800A004ull + ((offset) & 63) * 128) +#define CVMX_PIP_STAT10_PRTX(offset)(0x00011800A0001480ull + ((offset) & 63) * 16) +#define CVMX_PIP_STAT10_X(offset) (0x00011800A0040050ull + ((offset) & 63) * 128) +#define CVMX_PIP_STAT11_PRTX(offset)(0x00011800A0001488ull + ((offset) & 63) * 16) +#define CVMX_PIP_STAT11_X(offset) (0x00011800A0040058ull + ((offset) & 63) * 128) +#define CVMX_PIP_STAT1_PRTX(offset) (0x00011800A808ull + ((offset) & 63) * 80) +#define CVMX_PIP_STAT1_X(offset)(0x00011800A0040008ull + ((offset) & 63) * 128) +#define CVMX_PIP_STAT2_PRTX(offset) (0x00011800A810ull + ((offset) & 63) * 80) +#define CVMX_PIP_STAT2_X(offset)(0x00011800A0040010ull + ((offset) & 63) * 128) +#define CVMX_PIP_STAT3_PRTX(offset) (0x00011800A818ull + ((offset) & 63) * 80) +#define CVMX_PIP_STAT3_X(offset)(0x00011800A0040018ull + ((offset) & 63) * 128) +#define CVMX_PIP_STAT4_PRTX(offset) (0x00011800A820ull + ((offset) & 63) * 80) +#define CVMX_PIP_STAT4_X(offset)(0x00011800A0040020ull + ((offset) & 63) * 128) +#define CVMX_PIP_STAT5_PRTX(offset) (0x00011800A828ull + ((offset) & 63) * 80) +#define CVMX_PIP_STAT5_X(offset)(0x00011800A0040028ull + ((offset) & 63) * 128) +#define CVMX_PIP_STAT6_PRTX(offset) (0x00011800A830ull + ((offset) & 63) * 80) +#define CVMX_PIP_STAT6_X(offset)(0x00011800A0040030ull + ((offset) & 63) * 128) +#define CVMX_PIP_STAT7_PRTX(offset) (0x00011800A838ull + ((offset) & 63) * 80)
[PATCH v1 25/50] mips: octeon: Add cvmx-pow-defs.h header file
From: Aaron Williams
Import cvmx-pow-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mach-octeon/include/mach/cvmx-pow-defs.h | 1135 +
1 file changed, 1135 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pow-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-pow-defs.h
b/arch/mips/mach-octeon/include/mach/cvmx-pow-defs.h
new file mode 100644
index 00..92e3723eb3
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-pow-defs.h
@@ -0,0 +1,1135 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon pow.
+ */
+
+#ifndef __CVMX_POW_DEFS_H__
+#define __CVMX_POW_DEFS_H__
+
+#define CVMX_POW_BIST_STAT (0x0001670003F8ull)
+#define CVMX_POW_DS_PC (0x000167000398ull)
+#define CVMX_POW_ECC_ERR(0x000167000218ull)
+#define CVMX_POW_IQ_CNTX(offset) (0x000167000340ull + ((offset) & 7) *
8)
+#define CVMX_POW_IQ_COM_CNT (0x000167000388ull)
+#define CVMX_POW_IQ_INT (0x000167000238ull)
+#define CVMX_POW_IQ_INT_EN (0x000167000240ull)
+#define CVMX_POW_IQ_THRX(offset) (0x0001670003A0ull + ((offset) & 7) *
8)
+#define CVMX_POW_NOS_CNT(0x000167000228ull)
+#define CVMX_POW_NW_TIM (0x000167000210ull)
+#define CVMX_POW_PF_RST_MSK (0x000167000230ull)
+#define CVMX_POW_PP_GRP_MSKX(offset) (0x00016700ull + ((offset) & 15)
* 8)
+#define CVMX_POW_QOS_RNDX(offset)(0x0001670001C0ull + ((offset) & 7) *
8)
+#define CVMX_POW_QOS_THRX(offset)(0x000167000180ull + ((offset) & 7) *
8)
+#define CVMX_POW_TS_PC (0x000167000390ull)
+#define CVMX_POW_WA_COM_PC (0x000167000380ull)
+#define CVMX_POW_WA_PCX(offset) (0x000167000300ull + ((offset)
& 7) * 8)
+#define CVMX_POW_WQ_INT (0x000167000200ull)
+#define CVMX_POW_WQ_INT_CNTX(offset) (0x000167000100ull + ((offset) & 15)
* 8)
+#define CVMX_POW_WQ_INT_PC (0x000167000208ull)
+#define CVMX_POW_WQ_INT_THRX(offset) (0x00016780ull + ((offset) & 15)
* 8)
+#define CVMX_POW_WS_PCX(offset) (0x000167000280ull + ((offset)
& 15) * 8)
+
+/**
+ * cvmx_pow_bist_stat
+ *
+ * Contains the BIST status for the POW memories ('0' = pass, '1' = fail).
+ *
+ */
+union cvmx_pow_bist_stat {
+ u64 u64;
+ struct cvmx_pow_bist_stat_s {
+ u64 reserved_32_63 : 32;
+ u64 pp : 16;
+ u64 reserved_0_15 : 16;
+ } s;
+ struct cvmx_pow_bist_stat_cn30xx {
+ u64 reserved_17_63 : 47;
+ u64 pp : 1;
+ u64 reserved_9_15 : 7;
+ u64 cam : 1;
+ u64 nbt1 : 1;
+ u64 nbt0 : 1;
+ u64 index : 1;
+ u64 fidx : 1;
+ u64 nbr1 : 1;
+ u64 nbr0 : 1;
+ u64 pend : 1;
+ u64 adr : 1;
+ } cn30xx;
+ struct cvmx_pow_bist_stat_cn31xx {
+ u64 reserved_18_63 : 46;
+ u64 pp : 2;
+ u64 reserved_9_15 : 7;
+ u64 cam : 1;
+ u64 nbt1 : 1;
+ u64 nbt0 : 1;
+ u64 index : 1;
+ u64 fidx : 1;
+ u64 nbr1 : 1;
+ u64 nbr0 : 1;
+ u64 pend : 1;
+ u64 adr : 1;
+ } cn31xx;
+ struct cvmx_pow_bist_stat_cn38xx {
+ u64 reserved_32_63 : 32;
+ u64 pp : 16;
+ u64 reserved_10_15 : 6;
+ u64 cam : 1;
+ u64 nbt : 1;
+ u64 index : 1;
+ u64 fidx : 1;
+ u64 nbr1 : 1;
+ u64 nbr0 : 1;
+ u64 pend1 : 1;
+ u64 pend0 : 1;
+ u64 adr1 : 1;
+ u64 adr0 : 1;
+ } cn38xx;
+ struct cvmx_pow_bist_stat_cn38xx cn38xxp2;
+ struct cvmx_pow_bist_stat_cn31xx cn50xx;
+ struct cvmx_pow_bist_stat_cn52xx {
+ u64 reserved_20_63 : 44;
+ u64 pp : 4;
+ u64 reserved_9_15 : 7;
+ u64 cam : 1;
+ u64 nbt1 : 1;
+ u64 nbt0 : 1;
+ u64 index : 1;
+ u64 fidx : 1;
+ u64 nbr1 : 1;
+ u64 nbr0 : 1;
+ u64 pend : 1;
+ u64 adr : 1;
+ } cn52xx;
+ struct cvmx_pow_bist_stat_cn52xx cn52xxp1;
+ struct cvmx_pow_bist_stat_cn56xx {
+ u64 reserved_28_63 : 36;
+ u64 pp : 12;
+ u64 reserved_10_15 : 6;
+ u64 cam : 1;
+ u64 nbt
[PATCH v1 35/50] mips: octeon: Move cvmx-lmcx-defs.h from mach/cvmx to mach
To match all other cvmx-* header, this patch moves the already existing
cvmx-lmcx-defs.h header one directory up.
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/include/mach/{cvmx => }/cvmx-lmcx-defs.h | 0
arch/mips/mach-octeon/include/mach/octeon_ddr.h| 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
rename arch/mips/mach-octeon/include/mach/{cvmx => }/cvmx-lmcx-defs.h (100%)
diff --git a/arch/mips/mach-octeon/include/mach/cvmx/cvmx-lmcx-defs.h
b/arch/mips/mach-octeon/include/mach/cvmx-lmcx-defs.h
similarity index 100%
rename from arch/mips/mach-octeon/include/mach/cvmx/cvmx-lmcx-defs.h
rename to arch/mips/mach-octeon/include/mach/cvmx-lmcx-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/octeon_ddr.h
b/arch/mips/mach-octeon/include/mach/octeon_ddr.h
index e630dc5ae3..97e7b554ff 100644
--- a/arch/mips/mach-octeon/include/mach/octeon_ddr.h
+++ b/arch/mips/mach-octeon/include/mach/octeon_ddr.h
@@ -11,7 +11,7 @@
#include
#include
#include
-#include
+#include
#include
#include
--
2.29.2
[PATCH v1 12/50] mips: octeon: Add cvmx-gserx-defs.h header file
From: Aaron Williams
Import cvmx-gserx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../include/mach/cvmx-gserx-defs.h| 2191 +
1 file changed, 2191 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-gserx-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-gserx-defs.h
b/arch/mips/mach-octeon/include/mach/cvmx-gserx-defs.h
new file mode 100644
index 00..832a592dba
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-gserx-defs.h
@@ -0,0 +1,2191 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef __CVMX_GSERX_DEFS_H__
+#define __CVMX_GSERX_DEFS_H__
+
+#define CVMX_GSERX_DLMX_TX_AMPLITUDE(offset, block_id) (0x0001180090003008ull)
+#define CVMX_GSERX_DLMX_TX_PREEMPH(offset, block_id) (0x0001180090003028ull)
+#define CVMX_GSERX_DLMX_MPLL_EN(offset, block_id) (0x0001180090001020ull)
+#define CVMX_GSERX_DLMX_REF_SSP_EN(offset, block_id) (0x0001180090001048ull)
+#define CVMX_GSERX_DLMX_TX_RATE(offset, block_id) (0x0001180090003030ull)
+#define CVMX_GSERX_DLMX_TX_EN(offset, block_id)
(0x0001180090003020ull)
+#define CVMX_GSERX_DLMX_TX_CM_EN(offset, block_id) (0x0001180090003010ull)
+#define CVMX_GSERX_DLMX_TX_RESET(offset, block_id) (0x0001180090003038ull)
+#define CVMX_GSERX_DLMX_TX_DATA_EN(offset, block_id) (0x0001180090003018ull)
+#define CVMX_GSERX_DLMX_RX_RATE(offset, block_id) (0x0001180090002028ull)
+#define CVMX_GSERX_DLMX_RX_PLL_EN(offset, block_id)(0x0001180090002020ull)
+#define CVMX_GSERX_DLMX_RX_DATA_EN(offset, block_id) (0x0001180090002008ull)
+#define CVMX_GSERX_DLMX_RX_RESET(offset, block_id) (0x0001180090002030ull)
+
+#define CVMX_GSERX_DLMX_TX_STATUS(offset, block_id)
\
+ (0x0001180090003000ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) *
524288)
+#define CVMX_GSERX_DLMX_RX_STATUS(offset, block_id)
\
+ (0x0001180090002000ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) *
524288)
+
+static inline u64 CVMX_GSERX_SATA_STATUS(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ return 0x0001180090100200ull + (offset) * 0x100ull;
+ case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+ return 0x0001180090100900ull + (offset) * 0x100ull;
+ case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+ return 0x0001180090100900ull + (offset) * 0x100ull;
+ }
+ return 0x0001180090100900ull + (offset) * 0x100ull;
+}
+
+#define CVMX_GSERX_DLMX_RX_EQ(offset, block_id)
\
+ (0x0001180090002010ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) *
524288)
+#define CVMX_GSERX_DLMX_REF_USE_PAD(offset, block_id)
\
+ (0x0001180090001050ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) *
524288)
+#define CVMX_GSERX_DLMX_REFCLK_SEL(offset, block_id)
\
+ (0x000118009008ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) *
524288)
+#define CVMX_GSERX_DLMX_PHY_RESET(offset, block_id)
\
+ (0x0001180090001038ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) *
524288)
+#define CVMX_GSERX_DLMX_TEST_POWERDOWN(offset, block_id)
\
+ (0x0001180090001060ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) *
524288)
+#define CVMX_GSERX_DLMX_REF_CLKDIV2(offset, block_id)
\
+ (0x0001180090001040ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) *
524288)
+#define CVMX_GSERX_DLMX_MPLL_MULTIPLIER(offset, block_id)
\
+ (0x0001180090001030ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) *
524288)
+#define CVMX_GSERX_DLMX_MPLL_STATUS(offset, block_id)
\
+ (0x0001180090001000ull + (((offset) & 3) + ((block_id) & 0) * 0x0ull) *
524288)
+
+#define CVMX_GSERX_BR_RXX_CTL(offset, block_id)
\
+ (0x000118009400ull + (((offset) & 3) + ((block_id) & 15) *
0x2ull) * 128)
+#define CVMX_GSERX_BR_RXX_EER(offset, block_id)
\
+ (0x000118009418ull + (((offset) & 3) + ((block_id) & 15) *
0x2ull) * 128)
+
+#define CVMX_GSERX_PCIE_PIPE_PORT_SEL(offset) (0x0001180090080460ull)
+#define CVMX_GSERX_PCIE_PIPE_RST(offset) (0x0001180090080448ull)
+
+#define CVMX_GSERX_SATA_CFG(offset) (0x0001180090100208ull)
[PATCH v1 19/50] mips: octeon: Add cvmx-pcsx-defs.h header file
From: Aaron Williams
Import cvmx-pcsx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mach-octeon/include/mach/cvmx-pcsx-defs.h | 1005 +
1 file changed, 1005 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pcsx-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-pcsx-defs.h
b/arch/mips/mach-octeon/include/mach/cvmx-pcsx-defs.h
new file mode 100644
index 00..e534b6711d
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-pcsx-defs.h
@@ -0,0 +1,1005 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon pcsx.
+ */
+
+#ifndef __CVMX_PCSX_DEFS_H__
+#define __CVMX_PCSX_DEFS_H__
+
+static inline u64 CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long
block_id)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B0001010ull + ((offset) + (block_id) *
0x2ull) * 1024;
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B0001010ull + ((offset) + (block_id) *
0x2ull) * 1024;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B0001010ull + ((offset) + (block_id) *
0x4000ull) * 1024;
+ }
+ return 0x00011800B0001010ull + ((offset) + (block_id) * 0x2ull) *
1024;
+}
+
+static inline u64 CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long
block_id)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B0001028ull + ((offset) + (block_id) *
0x2ull) * 1024;
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B0001028ull + ((offset) + (block_id) *
0x2ull) * 1024;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B0001028ull + ((offset) + (block_id) *
0x4000ull) * 1024;
+ }
+ return 0x00011800B0001028ull + ((offset) + (block_id) * 0x2ull) *
1024;
+}
+
+static inline u64 CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned
long block_id)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B0001018ull + ((offset) + (block_id) *
0x2ull) * 1024;
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B0001018ull + ((offset) + (block_id) *
0x2ull) * 1024;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B0001018ull + ((offset) + (block_id) *
0x4000ull) * 1024;
+ }
+ return 0x00011800B0001018ull + ((offset) + (block_id) * 0x2ull) *
1024;
+}
+
+static inline u64 CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned
long block_id)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B0001020ull + ((offset) + (block_id) *
0x2ull) * 1024;
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B0001020ull + ((offset) + (block_id) *
0x2ull) * 1024;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B0001020ull + ((offset) + (block_id) *
0x4000ull) * 1024;
+ }
+ return 0x00011800B0001020ull + ((offset) + (block_id) * 0x2ull) *
1024;
+}
+
+static inline u64 CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long
block_id)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B0001088ull + ((offset) + (block_id) *
0x2ull) * 1024;
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B0001088ull + ((offset) + (block_id) *
0x2ull) * 1024;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B0001088ull + ((offset) + (block_id) *
0x4000ull) * 1024;
+ }
+ return 0x00011800B0001088ull + ((offset) + (block_id) * 0x2ull) *
1024;
+}
+
[PATCH v1 31/50] mips: octeon: Add cvmx-sriox-defs.h header file
From: Aaron Williams
Import cvmx-sriox-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../include/mach/cvmx-sriox-defs.h| 44 +++
1 file changed, 44 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-sriox-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-sriox-defs.h
b/arch/mips/mach-octeon/include/mach/cvmx-sriox-defs.h
new file mode 100644
index 00..ac988609a1
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-sriox-defs.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef __CVMX_SRIOX_DEFS_H__
+#define __CVMX_SRIOX_DEFS_H__
+
+#define CVMX_SRIOX_STATUS_REG(offset) (0x00011800C8000100ull + ((offset) & 3)
* 0x100ull)
+
+/**
+ * cvmx_srio#_status_reg
+ *
+ * The SRIO field displays if the port has been configured for SRIO operation.
This register
+ * can be read regardless of whether the SRIO is selected or being reset.
Although some other
+ * registers can be accessed while the ACCESS bit is zero (see individual
registers for details),
+ * the majority of SRIO registers and all the SRIOMAINT registers can be used
only when the
+ * ACCESS bit is asserted.
+ *
+ * This register is reset by the coprocessor-clock reset.
+ */
+union cvmx_sriox_status_reg {
+ u64 u64;
+ struct cvmx_sriox_status_reg_s {
+ u64 reserved_9_63 : 55;
+ u64 host : 1;
+ u64 spd : 4;
+ u64 run_type : 2;
+ u64 access : 1;
+ u64 srio : 1;
+ } s;
+ struct cvmx_sriox_status_reg_cn63xx {
+ u64 reserved_2_63 : 62;
+ u64 access : 1;
+ u64 srio : 1;
+ } cn63xx;
+ struct cvmx_sriox_status_reg_cn63xx cn63xxp1;
+ struct cvmx_sriox_status_reg_cn63xx cn66xx;
+ struct cvmx_sriox_status_reg_s cnf75xx;
+};
+
+typedef union cvmx_sriox_status_reg cvmx_sriox_status_reg_t;
+
+#endif
--
2.29.2
[PATCH v1 29/50] mips: octeon: Add cvmx-smix-defs.h header file
From: Aaron Williams
Import cvmx-smix-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mach-octeon/include/mach/cvmx-smix-defs.h | 360 ++
1 file changed, 360 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-smix-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-smix-defs.h
b/arch/mips/mach-octeon/include/mach/cvmx-smix-defs.h
new file mode 100644
index 00..c51d71b38f
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-smix-defs.h
@@ -0,0 +1,360 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon smix.
+ */
+
+#ifndef __CVMX_SMIX_DEFS_H__
+#define __CVMX_SMIX_DEFS_H__
+
+static inline u64 CVMX_SMIX_CLK(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ return 0x000118001818ull + (offset) * 256;
+ case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
+ return 0x000118003818ull + (offset) * 128;
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return 0x000118003818ull + (offset) * 128;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x000118003818ull + (offset) * 128;
+ case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+ return 0x000118003818ull + (offset) * 128;
+ }
+ return 0x000118003818ull + (offset) * 128;
+}
+
+static inline u64 CVMX_SMIX_CMD(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ return 0x000118001800ull + (offset) * 256;
+ case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
+ return 0x000118003800ull + (offset) * 128;
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return 0x000118003800ull + (offset) * 128;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x000118003800ull + (offset) * 128;
+ case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+ return 0x000118003800ull + (offset) * 128;
+ }
+ return 0x000118003800ull + (offset) * 128;
+}
+
+static inline u64 CVMX_SMIX_EN(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ return 0x000118001820ull + (offset) * 256;
+ case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
+ return 0x000118003820ull + (offset) * 128;
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return 0x000118003820ull + (offset) * 128;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x000118003820ull + (offset) * 128;
+ case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+ return 0x000118003820ull + (offset) * 128;
+ }
+ return 0x000118003820ull + (offset) * 128;
+}
+
+static inline u64 CVMX_SMIX_RD_DAT(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ return 0x000118001810ull + (offset) * 256;
+ case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
+ return 0x000118003810ull + (offset) * 128;
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return 0x000118003810ull + (offset) * 128;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x000118003810ull + (offset) * 128;
+ case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+
[PATCH v1 21/50] mips: octeon: Add cvmx-pepx-defs.h header file
From: Aaron Williams Import cvmx-pepx-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- .../mach-octeon/include/mach/cvmx-pexp-defs.h | 1382 + 1 file changed, 1382 insertions(+) create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pexp-defs.h diff --git a/arch/mips/mach-octeon/include/mach/cvmx-pexp-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-pexp-defs.h new file mode 100644 index 00..333c2caee1 --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/cvmx-pexp-defs.h @@ -0,0 +1,1382 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Marvell International Ltd. + * + * Configuration and status register (CSR) definitions for + * OCTEON PEXP. + */ + +#ifndef __CVMX_PEXP_DEFS_H__ +#define __CVMX_PEXP_DEFS_H__ + +#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (0x00011F008000ull + ((offset) & 31) * 16) +#define CVMX_PEXP_NPEI_BIST_STATUS (0x00011F008580ull) +#define CVMX_PEXP_NPEI_BIST_STATUS2(0x00011F008680ull) +#define CVMX_PEXP_NPEI_CTL_PORT0 (0x00011F008250ull) +#define CVMX_PEXP_NPEI_CTL_PORT1 (0x00011F008260ull) +#define CVMX_PEXP_NPEI_CTL_STATUS (0x00011F008570ull) +#define CVMX_PEXP_NPEI_CTL_STATUS2 (0x00011F00BC00ull) +#define CVMX_PEXP_NPEI_DATA_OUT_CNT(0x00011F0085F0ull) +#define CVMX_PEXP_NPEI_DBG_DATA(0x00011F008510ull) +#define CVMX_PEXP_NPEI_DBG_SELECT (0x00011F008500ull) +#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL (0x00011F0085C0ull) +#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL (0x00011F0085D0ull) +#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (0x00011F008450ull + ((offset) & 7) * 16) +#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (0x00011F0083B0ull + ((offset) & 7) * 16) +#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (0x00011F008400ull + ((offset) & 7) * 16) +#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (0x00011F0084A0ull + ((offset) & 7) * 16) +#define CVMX_PEXP_NPEI_DMA_CNTS(0x00011F0085E0ull) +#define CVMX_PEXP_NPEI_DMA_CONTROL (0x00011F0083A0ull) +#define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM(0x00011F0085B0ull) +#define CVMX_PEXP_NPEI_DMA_STATE1 (0x00011F0086C0ull) +#define CVMX_PEXP_NPEI_DMA_STATE1_P1 (0x00011F008680ull) +#define CVMX_PEXP_NPEI_DMA_STATE2 (0x00011F0086D0ull) +#define CVMX_PEXP_NPEI_DMA_STATE2_P1 (0x00011F008690ull) +#define CVMX_PEXP_NPEI_DMA_STATE3_P1 (0x00011F0086A0ull) +#define CVMX_PEXP_NPEI_DMA_STATE4_P1 (0x00011F0086B0ull) +#define CVMX_PEXP_NPEI_DMA_STATE5_P1 (0x00011F0086C0ull) +#define CVMX_PEXP_NPEI_INT_A_ENB (0x00011F008560ull) +#define CVMX_PEXP_NPEI_INT_A_ENB2 (0x00011F00BCE0ull) +#define CVMX_PEXP_NPEI_INT_A_SUM (0x00011F008550ull) +#define CVMX_PEXP_NPEI_INT_ENB (0x00011F008540ull) +#define CVMX_PEXP_NPEI_INT_ENB2(0x00011F00BCD0ull) +#define CVMX_PEXP_NPEI_INT_INFO(0x00011F008590ull) +#define CVMX_PEXP_NPEI_INT_SUM (0x00011F008530ull) +#define CVMX_PEXP_NPEI_INT_SUM2(0x00011F00BCC0ull) +#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 (0x00011F008600ull) +#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 (0x00011F008610ull) +#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL (0x00011F0084F0ull) +#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) \ + (0x00011F008280ull + ((offset) & 31) * 16 - 16 * 12) +#define CVMX_PEXP_NPEI_MSI_ENB0 (0x00011F00BC50ull) +#define CVMX_PEXP_NPEI_MSI_ENB1 (0x00011F00BC60ull) +#define CVMX_PEXP_NPEI_MSI_ENB2 (0x00011F00BC70ull) +#define CVMX_PEXP_NPEI_MSI_ENB3 (0x00011F00BC80ull) +#define CVMX_PEXP_NPEI_MSI_RCV0 (0x00011F00BC10ull) +#define CVMX_PEXP_NPEI_MSI_RCV1 (0x00011F00BC20ull) +#define CVMX_PEXP_NPEI_MSI_RCV2 (0x00011F00BC30ull) +#define CVMX_PEXP_NPEI_MSI_RCV3 (0x00011F00BC40ull) +#define CVMX_PEXP_NPEI_MSI_RD_MAP(0x00011F00BCA0ull) +#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 (0x00011F00BCF0ull) +#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 (0x00011F00BD00ull) +#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 (0x00011F00BD10ull) +#define CVMX_PEXP_NPEI_MSI_W1C_ENB3
[PATCH v1 30/50] mips: octeon: Add cvmx-sriomaintx-defs.h header file
From: Aaron Williams
Import cvmx-sriomaintx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../include/mach/cvmx-sriomaintx-defs.h | 61 +++
1 file changed, 61 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-sriomaintx-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-sriomaintx-defs.h
b/arch/mips/mach-octeon/include/mach/cvmx-sriomaintx-defs.h
new file mode 100644
index 00..2558e7b2fd
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-sriomaintx-defs.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef __CVMX_SRIOMAINTX_DEFS_H__
+#define __CVMX_SRIOMAINTX_DEFS_H__
+
+static inline u64 CVMX_SRIOMAINTX_PORT_0_CTL2(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+ return 0x01000154ull + (offset) * 0x1ull;
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ return 0x0154ull;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ return 0x0154ull + (offset) * 0x1ull;
+ }
+ return 0x01000154ull + (offset) * 0x1ull;
+}
+
+/**
+ * cvmx_sriomaint#_port_0_ctl2
+ *
+ * These registers are accessed when a local processor or an external
+ * device wishes to examine the port baudrate information. The automatic
+ * baud rate feature is not available on this device. The SUP_* and ENB_*
+ * fields are set directly by the SRIO()_STATUS_REG[SPD] bits as a
+ * reference but otherwise have no effect.
+ *
+ * WARNING!! Writes to this register will reinitialize the SRIO link.
+ */
+union cvmx_sriomaintx_port_0_ctl2 {
+ u32 u32;
+ struct cvmx_sriomaintx_port_0_ctl2_s {
+ u32 sel_baud : 4;
+ u32 baud_sup : 1;
+ u32 baud_enb : 1;
+ u32 sup_125g : 1;
+ u32 enb_125g : 1;
+ u32 sup_250g : 1;
+ u32 enb_250g : 1;
+ u32 sup_312g : 1;
+ u32 enb_312g : 1;
+ u32 sub_500g : 1;
+ u32 enb_500g : 1;
+ u32 sup_625g : 1;
+ u32 enb_625g : 1;
+ u32 reserved_2_15 : 14;
+ u32 tx_emph : 1;
+ u32 emph_en : 1;
+ } s;
+ struct cvmx_sriomaintx_port_0_ctl2_s cn63xx;
+ struct cvmx_sriomaintx_port_0_ctl2_s cn63xxp1;
+ struct cvmx_sriomaintx_port_0_ctl2_s cn66xx;
+ struct cvmx_sriomaintx_port_0_ctl2_s cnf75xx;
+};
+
+typedef union cvmx_sriomaintx_port_0_ctl2 cvmx_sriomaintx_port_0_ctl2_t;
+
+#endif
--
2.29.2
[PATCH v1 27/50] mips: octeon: Add cvmx-sata-defs.h header file
From: Aaron Williams
Import cvmx-sata-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mach-octeon/include/mach/cvmx-sata-defs.h | 311 ++
1 file changed, 311 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-sata-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-sata-defs.h
b/arch/mips/mach-octeon/include/mach/cvmx-sata-defs.h
new file mode 100644
index 00..77af0e3f83
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-sata-defs.h
@@ -0,0 +1,311 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef __CVMX_SATA_DEFS_H__
+#define __CVMX_SATA_DEFS_H__
+
+#define CVMX_SATA_UCTL_CTL(0x000118006C00ull)
+#define CVMX_SATA_UCTL_SHIM_CFG (0x000118006CE8ull)
+#define CVMX_SATA_UCTL_BIST_STATUS (0x000118006C08ull)
+
+#define CVMX_SATA_UAHC_GBL_PI (0x00016C0Cull)
+#define CVMX_SATA_UAHC_GBL_TIMER1MS (0x00016CE0ull)
+#define CVMX_SATA_UAHC_GBL_CAP (0x00016C00ull)
+
+#define CVMX_SATA_UAHC_PX_CMD(offset) (0x00016C000118ull + ((offset) & 1)
* 128)
+#define CVMX_SATA_UAHC_PX_SCTL(offset) (0x00016C00012Cull + ((offset) & 1)
* 128)
+#define CVMX_SATA_UAHC_PX_SERR(offset) (0x00016C000130ull + ((offset) & 1)
* 128)
+#define CVMX_SATA_UAHC_PX_IS(offset) (0x00016C000110ull + ((offset) & 1)
* 128)
+#define CVMX_SATA_UAHC_PX_SSTS(offset) (0x00016C000128ull + ((offset) & 1)
* 128)
+#define CVMX_SATA_UAHC_PX_TFD(offset) (0x00016C000120ull + ((offset) & 1)
* 128)
+
+/**
+ * cvmx_sata_uctl_ctl
+ *
+ * This register controls clocks, resets, power, and BIST for the SATA.
+ *
+ * Accessible always.
+ *
+ * Reset by IOI reset.
+ */
+union cvmx_sata_uctl_ctl {
+ u64 u64;
+ struct cvmx_sata_uctl_ctl_s {
+ u64 clear_bist : 1;
+ u64 start_bist : 1;
+ u64 reserved_31_61 : 31;
+ u64 a_clk_en : 1;
+ u64 a_clk_byp_sel : 1;
+ u64 a_clkdiv_rst : 1;
+ u64 reserved_27_27 : 1;
+ u64 a_clkdiv_sel : 3;
+ u64 reserved_5_23 : 19;
+ u64 csclk_en : 1;
+ u64 reserved_2_3 : 2;
+ u64 sata_uahc_rst : 1;
+ u64 sata_uctl_rst : 1;
+ } s;
+ struct cvmx_sata_uctl_ctl_s cn70xx;
+ struct cvmx_sata_uctl_ctl_s cn70xxp1;
+ struct cvmx_sata_uctl_ctl_s cn73xx;
+};
+
+typedef union cvmx_sata_uctl_ctl cvmx_sata_uctl_ctl_t;
+
+/**
+ * cvmx_sata_uctl_bist_status
+ *
+ * Results from BIST runs of SATA's memories.
+ * Wait for NDONE==0, then look at defect indication.
+ *
+ * Accessible always.
+ *
+ * Reset by IOI reset.
+ */
+union cvmx_sata_uctl_bist_status {
+ u64 u64;
+ struct cvmx_sata_uctl_bist_status_s {
+ u64 reserved_42_63 : 22;
+ u64 uctl_xm_r_bist_ndone : 1;
+ u64 uctl_xm_w_bist_ndone : 1;
+ u64 reserved_36_39 : 4;
+ u64 uahc_p0_rxram_bist_ndone : 1;
+ u64 uahc_p1_rxram_bist_ndone : 1;
+ u64 uahc_p0_txram_bist_ndone : 1;
+ u64 uahc_p1_txram_bist_ndone : 1;
+ u64 reserved_10_31 : 22;
+ u64 uctl_xm_r_bist_status : 1;
+ u64 uctl_xm_w_bist_status : 1;
+ u64 reserved_4_7 : 4;
+ u64 uahc_p0_rxram_bist_status : 1;
+ u64 uahc_p1_rxram_bist_status : 1;
+ u64 uahc_p0_txram_bist_status : 1;
+ u64 uahc_p1_txram_bist_status : 1;
+ } s;
+ struct cvmx_sata_uctl_bist_status_s cn70xx;
+ struct cvmx_sata_uctl_bist_status_s cn70xxp1;
+ struct cvmx_sata_uctl_bist_status_s cn73xx;
+};
+
+typedef union cvmx_sata_uctl_bist_status cvmx_sata_uctl_bist_status_t;
+
+/**
+ * cvmx_sata_uctl_shim_cfg
+ *
+ * This register allows configuration of various shim (UCTL) features.
+ *
+ * Fields XS_NCB_OOB_* are captured when there are no outstanding OOB errors
indicated in INTSTAT
+ * and a new OOB error arrives.
+ *
+ * Fields XS_BAD_DMA_* are captured when there are no outstanding DMA errors
indicated in INTSTAT
+ * and a new DMA error arrives.
+ *
+ * Accessible only when SATA_UCTL_CTL[A_CLK_EN].
+ *
+ * Reset by IOI reset or SATA_UCTL_CTL[SATA_UCTL_RST].
+ */
+union cvmx_sata_uctl_shim_cfg {
+ u64 u64;
+ struct cvmx_sata_uctl_shim_cfg_s {
+ u64 xs_ncb_oob_wrn : 1;
+ u64 reserved_60_62 : 3;
+ u64 xs_ncb_oob_osrc : 12;
+ u64 xm_bad_dma_wrn : 1;
+ u64 reserved_44_46 : 3;
+ u64 xm_bad_dma_type : 4;
+ u64 reserved_14_39 : 26;
+ u64 dma_read_cmd : 2;
+ u64 reserved_11_11 : 1;
+ u64
[PATCH v1 26/50] mips: octeon: Add cvmx-rst-defs.h header file
From: Aaron Williams
Import cvmx-rst-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mach-octeon/include/mach/cvmx-rst-defs.h | 77 +++
1 file changed, 77 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-rst-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-rst-defs.h
b/arch/mips/mach-octeon/include/mach/cvmx-rst-defs.h
new file mode 100644
index 00..943e160105
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-rst-defs.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef __CVMX_RST_DEFS_H__
+#define __CVMX_RST_DEFS_H__
+
+#define CVMX_RST_CTLX(offset) (0x0001180006001640ull + ((offset) & 3) * 8)
+#define CVMX_RST_SOFT_PRSTX(offset) (0x00011800060016C0ull + ((offset) & 3) *
8)
+
+/**
+ * cvmx_rst_ctl#
+ */
+union cvmx_rst_ctlx {
+ u64 u64;
+ struct cvmx_rst_ctlx_s {
+ u64 reserved_10_63 : 54;
+ u64 prst_link : 1;
+ u64 rst_done : 1;
+ u64 rst_link : 1;
+ u64 host_mode : 1;
+ u64 reserved_4_5 : 2;
+ u64 rst_drv : 1;
+ u64 rst_rcv : 1;
+ u64 rst_chip : 1;
+ u64 rst_val : 1;
+ } s;
+ struct cvmx_rst_ctlx_s cn70xx;
+ struct cvmx_rst_ctlx_s cn70xxp1;
+ struct cvmx_rst_ctlx_s cn73xx;
+ struct cvmx_rst_ctlx_s cn78xx;
+ struct cvmx_rst_ctlx_s cn78xxp1;
+ struct cvmx_rst_ctlx_s cnf75xx;
+};
+
+typedef union cvmx_rst_ctlx cvmx_rst_ctlx_t;
+
+/**
+ * cvmx_rst_soft_prst#
+ */
+union cvmx_rst_soft_prstx {
+ u64 u64;
+ struct cvmx_rst_soft_prstx_s {
+ u64 reserved_1_63 : 63;
+ u64 soft_prst : 1;
+ } s;
+ struct cvmx_rst_soft_prstx_s cn70xx;
+ struct cvmx_rst_soft_prstx_s cn70xxp1;
+ struct cvmx_rst_soft_prstx_s cn73xx;
+ struct cvmx_rst_soft_prstx_s cn78xx;
+ struct cvmx_rst_soft_prstx_s cn78xxp1;
+ struct cvmx_rst_soft_prstx_s cnf75xx;
+};
+
+typedef union cvmx_rst_soft_prstx cvmx_rst_soft_prstx_t;
+
+/**
+ * cvmx_rst_soft_rst
+ */
+union cvmx_rst_soft_rst {
+ u64 u64;
+ struct cvmx_rst_soft_rst_s {
+ u64 reserved_1_63 : 63;
+ u64 soft_rst : 1;
+ } s;
+ struct cvmx_rst_soft_rst_s cn70xx;
+ struct cvmx_rst_soft_rst_s cn70xxp1;
+ struct cvmx_rst_soft_rst_s cn73xx;
+ struct cvmx_rst_soft_rst_s cn78xx;
+ struct cvmx_rst_soft_rst_s cn78xxp1;
+ struct cvmx_rst_soft_rst_s cnf75xx;
+};
+
+typedef union cvmx_rst_soft_rst cvmx_rst_soft_rst_t;
+
+#endif
--
2.29.2
[PATCH v1 20/50] mips: octeon: Add cvmx-pemx-defs.h header file
From: Aaron Williams
Import cvmx-pemx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mach-octeon/include/mach/cvmx-pemx-defs.h | 2028 +
1 file changed, 2028 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pemx-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-pemx-defs.h
b/arch/mips/mach-octeon/include/mach/cvmx-pemx-defs.h
new file mode 100644
index 00..9ec7a4b67c
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-pemx-defs.h
@@ -0,0 +1,2028 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon pemx.
+ */
+
+#ifndef __CVMX_PEMX_DEFS_H__
+#define __CVMX_PEMX_DEFS_H__
+
+static inline u64 CVMX_PEMX_BAR1_INDEXX(unsigned long offset, unsigned long
block_id)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ return 0x00011800C100ull + ((offset) + (block_id) *
0x20ull) * 8;
+ case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+ return 0x00011800C100ull + ((offset) + (block_id) *
0x20ull) * 8;
+ case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
+ return 0x00011800C100ull + ((offset) + (block_id) *
0x20ull) * 8;
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return 0x00011800C100ull + ((offset) + (block_id) *
0x20ull) * 8;
+ case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+ return 0x00011800C100ull + ((offset) + (block_id) *
0x20ull) * 8;
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x00011800C0A8ull + ((offset) + (block_id) *
0x20ull) * 8;
+ }
+ return 0x00011800C100ull + ((offset) + (block_id) * 0x20ull) *
8;
+}
+
+static inline u64 CVMX_PEMX_BAR2_MASK(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ return 0x00011800C0B0ull + (offset) * 0x100ull;
+ case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+ return 0x00011800C0B0ull + (offset) * 0x100ull;
+ case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
+ return 0x00011800C0B0ull + (offset) * 0x100ull;
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return 0x00011800C0B0ull + (offset) * 0x100ull;
+ case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+ return 0x00011800C1B0ull + (offset) * 0x100ull -
16777216 * 1;
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x00011800C130ull + (offset) * 0x100ull;
+ }
+ return 0x00011800C0B0ull + (offset) * 0x100ull;
+}
+
+static inline u64 CVMX_PEMX_BAR_CTL(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ return 0x00011800C0A8ull + (offset) * 0x100ull;
+ case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+ return 0x00011800C0A8ull + (offset) * 0x100ull;
+ case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
+ return 0x00011800C0A8ull + (offset) * 0x100ull;
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return 0x00011800C0A8ull + (offset) * 0x100ull;
+ case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+ return 0x00011800C1A8ull + (offset) * 0x100ull -
16777216 * 1;
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x00011800C128ull + (offset) * 0x100ull;
+ }
+ return 0x00011800C0A8ull + (offset) * 0x100ull;
+}
+
+static inline u64 CVMX_PEMX_BIST_STATUS(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN68XX &
[PATCH v1 16/50] mips: octeon: Add cvmx-npi-defs.h header file
From: Aaron Williams Import cvmx-npi-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- .../mach-octeon/include/mach/cvmx-npi-defs.h | 1953 + 1 file changed, 1953 insertions(+) create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-npi-defs.h diff --git a/arch/mips/mach-octeon/include/mach/cvmx-npi-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-npi-defs.h new file mode 100644 index 00..f23ed78ee4 --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/cvmx-npi-defs.h @@ -0,0 +1,1953 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Marvell International Ltd. + * + * Configuration and status register (CSR) type definitions for + * Octeon npi. + */ + +#ifndef __CVMX_NPI_DEFS_H__ +#define __CVMX_NPI_DEFS_H__ + +#define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0) +#define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1) +#define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2) +#define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3) +#define CVMX_NPI_BASE_ADDR_INPUTX(offset) (0x00011F70ull + ((offset) & 3) * 16) +#define CVMX_NPI_BASE_ADDR_OUTPUT0CVMX_NPI_BASE_ADDR_OUTPUTX(0) +#define CVMX_NPI_BASE_ADDR_OUTPUT1CVMX_NPI_BASE_ADDR_OUTPUTX(1) +#define CVMX_NPI_BASE_ADDR_OUTPUT2CVMX_NPI_BASE_ADDR_OUTPUTX(2) +#define CVMX_NPI_BASE_ADDR_OUTPUT3CVMX_NPI_BASE_ADDR_OUTPUTX(3) +#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (0x00011FB8ull + ((offset) & 3) * 8) +#define CVMX_NPI_BIST_STATUS (0x00011F0003F8ull) +#define CVMX_NPI_BUFF_SIZE_OUTPUT0CVMX_NPI_BUFF_SIZE_OUTPUTX(0) +#define CVMX_NPI_BUFF_SIZE_OUTPUT1CVMX_NPI_BUFF_SIZE_OUTPUTX(1) +#define CVMX_NPI_BUFF_SIZE_OUTPUT2CVMX_NPI_BUFF_SIZE_OUTPUTX(2) +#define CVMX_NPI_BUFF_SIZE_OUTPUT3CVMX_NPI_BUFF_SIZE_OUTPUTX(3) +#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (0x00011FE0ull + ((offset) & 3) * 8) +#define CVMX_NPI_COMP_CTL (0x00011F000218ull) +#define CVMX_NPI_CTL_STATUS (0x00011F10ull) +#define CVMX_NPI_DBG_SELECT (0x00011F08ull) +#define CVMX_NPI_DMA_CONTROL (0x00011F000128ull) +#define CVMX_NPI_DMA_HIGHP_COUNTS (0x00011F000148ull) +#define CVMX_NPI_DMA_HIGHP_NADDR (0x00011F000158ull) +#define CVMX_NPI_DMA_LOWP_COUNTS (0x00011F000140ull) +#define CVMX_NPI_DMA_LOWP_NADDR (0x00011F000150ull) +#define CVMX_NPI_HIGHP_DBELL (0x00011F000120ull) +#define CVMX_NPI_HIGHP_IBUFF_SADDR(0x00011F000110ull) +#define CVMX_NPI_INPUT_CONTROL(0x00011F000138ull) +#define CVMX_NPI_INT_ENB (0x00011F20ull) +#define CVMX_NPI_INT_SUM (0x00011F18ull) +#define CVMX_NPI_LOWP_DBELL (0x00011F000118ull) +#define CVMX_NPI_LOWP_IBUFF_SADDR (0x00011F000108ull) +#define CVMX_NPI_MEM_ACCESS_SUBID3CVMX_NPI_MEM_ACCESS_SUBIDX(3) +#define CVMX_NPI_MEM_ACCESS_SUBID4CVMX_NPI_MEM_ACCESS_SUBIDX(4) +#define CVMX_NPI_MEM_ACCESS_SUBID5CVMX_NPI_MEM_ACCESS_SUBIDX(5) +#define CVMX_NPI_MEM_ACCESS_SUBID6CVMX_NPI_MEM_ACCESS_SUBIDX(6) +#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (0x00011F28ull + ((offset) & 7) * 8 - 8 * 3) +#define CVMX_NPI_MSI_RCV (0x0190ull) +#define CVMX_NPI_NPI_MSI_RCV (0x00011F001190ull) +#define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0) +#define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1) +#define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2) +#define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3) +#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (0x00011F50ull + ((offset) & 3) * 8) +#define CVMX_NPI_OUTPUT_CONTROL (0x00011F000100ull) +#define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0) +#define CVMX_NPI_P0_INSTR_ADDRCVMX_NPI_PX_INSTR_ADDR(0) +#define CVMX_NPI_P0_INSTR_CNTSCVMX_NPI_PX_INSTR_CNTS(0) +#define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0) +#define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1) +#define CVMX_NPI_P1_INSTR_ADDRCVMX_NPI_PX_INSTR_ADDR(1) +#define CVMX_NPI_P1_INSTR_CNTSCVMX_NPI_PX_INSTR_CNTS(1) +#define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1) +#define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2) +#define CVMX_NPI_P2_INSTR_ADDRCVMX_NPI_PX_INSTR_ADDR(2) +#define CVMX_NPI_P2_INSTR_CNTSCVMX_NPI_PX_INSTR_CNTS(2) +#define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2)
[PATCH v1 13/50] mips: octeon: Add cvmx-ipd-defs.h header file
From: Aaron Williams Import cvmx-ipd-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- .../mach-octeon/include/mach/cvmx-ipd-defs.h | 1925 + 1 file changed, 1925 insertions(+) create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-ipd-defs.h diff --git a/arch/mips/mach-octeon/include/mach/cvmx-ipd-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-ipd-defs.h new file mode 100644 index 00..ad860fc7db --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/cvmx-ipd-defs.h @@ -0,0 +1,1925 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Marvell International Ltd. + * + * Configuration and status register (CSR) type definitions for + * Octeon ipd. + */ + +#ifndef __CVMX_IPD_DEFS_H__ +#define __CVMX_IPD_DEFS_H__ + +#define CVMX_IPD_1ST_MBUFF_SKIP(0x00014F00ull) +#define CVMX_IPD_1st_NEXT_PTR_BACK (0x00014F000150ull) +#define CVMX_IPD_2nd_NEXT_PTR_BACK (0x00014F000158ull) +#define CVMX_IPD_BIST_STATUS (0x00014F0007F8ull) +#define CVMX_IPD_BPIDX_MBUF_TH(offset) (0x00014F002000ull + ((offset) & 63) * 8) +#define CVMX_IPD_BPID_BP_COUNTERX(offset) (0x00014F003000ull + ((offset) & 63) * 8) +#define CVMX_IPD_BP_PRT_RED_END(0x00014F000328ull) +#define CVMX_IPD_CLK_COUNT (0x00014F000338ull) +#define CVMX_IPD_CREDITS (0x00014F004410ull) +#define CVMX_IPD_CTL_STATUS(0x00014F18ull) +#define CVMX_IPD_ECC_CTL (0x00014F004408ull) +#define CVMX_IPD_FREE_PTR_FIFO_CTL (0x00014F000780ull) +#define CVMX_IPD_FREE_PTR_VALUE(0x00014F000788ull) +#define CVMX_IPD_HOLD_PTR_FIFO_CTL (0x00014F000790ull) +#define CVMX_IPD_INT_ENB (0x00014F000160ull) +#define CVMX_IPD_INT_SUM (0x00014F000168ull) +#define CVMX_IPD_NEXT_PKT_PTR (0x00014F0007A0ull) +#define CVMX_IPD_NEXT_WQE_PTR (0x00014F0007A8ull) +#define CVMX_IPD_NOT_1ST_MBUFF_SKIP(0x00014F08ull) +#define CVMX_IPD_ON_BP_DROP_PKTX(offset)(0x00014F004100ull) +#define CVMX_IPD_PACKET_MBUFF_SIZE (0x00014F10ull) +#define CVMX_IPD_PKT_ERR (0x00014F0003F0ull) +#define CVMX_IPD_PKT_PTR_VALID (0x00014F000358ull) +#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (0x00014F28ull + ((offset) & 63) * 8) +#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (0x00014F000368ull + ((offset) & 63) * 8 - 8 * 36) +#define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (0x00014F0003D0ull + ((offset) & 63) * 8 - 8 * 40) +#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) \ + (0x00014F000388ull + ((offset) & 63) * 8 - 8 * 36) +#define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) \ + (0x00014F0003B0ull + ((offset) & 63) * 8 - 8 * 40) +#define CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(offset) \ + (0x00014F000410ull + ((offset) & 63) * 8 - 8 * 44) +#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (0x00014F0001B8ull + ((offset) & 63) * 8) +#define CVMX_IPD_PORT_PTR_FIFO_CTL (0x00014F000798ull) +#define CVMX_IPD_PORT_QOS_INTX(offset) (0x00014F000808ull + ((offset) & 7) * 8) +#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (0x00014F000848ull + ((offset) & 7) * 8) +#define CVMX_IPD_PORT_QOS_X_CNT(offset)(0x00014F000888ull + ((offset) & 511) * 8) +#define CVMX_IPD_PORT_SOPX(offset) (0x00014F004400ull) +#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (0x00014F000348ull) +#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (0x00014F000350ull) +#define CVMX_IPD_PTR_COUNT (0x00014F000320ull) +#define CVMX_IPD_PWP_PTR_FIFO_CTL (0x00014F000340ull) +#define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0) +#define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1) +#define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2) +#define CVMX_IPD_QOS3_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(3) +#define CVMX_IPD_QOS4_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(4) +#define CVMX_IPD_QOS5_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(5) +#define CVMX_IPD_QOS6_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(6) +#define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7) +#define CVMX_IPD_QOSX_RED_MARKS(offset)(0x00014F000178ull + ((offset) & 7) * 8) +#define CVMX_IPD_QUE0_FREE_PAGE_CNT
[PATCH v1 10/50] mips: octeon: Add cvmx-fpa-defs.h header file
From: Aaron Williams
Import cvmx-fpa-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mach-octeon/include/mach/cvmx-fpa-defs.h | 1866 +
1 file changed, 1866 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-fpa-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-fpa-defs.h
b/arch/mips/mach-octeon/include/mach/cvmx-fpa-defs.h
new file mode 100644
index 00..13ce7d8c96
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-fpa-defs.h
@@ -0,0 +1,1866 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon fpa.
+ */
+
+#ifndef __CVMX_FPA_DEFS_H__
+#define __CVMX_FPA_DEFS_H__
+
+#define CVMX_FPA_ADDR_RANGE_ERROR CVMX_FPA_ADDR_RANGE_ERROR_FUNC()
+static inline u64 CVMX_FPA_ADDR_RANGE_ERROR_FUNC(void)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x0001180028000458ull;
+ case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
+ return 0x000128000458ull;
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return 0x000128000458ull;
+ case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+ return 0x000128000458ull;
+ }
+ return 0x000128000458ull;
+}
+
+#define CVMX_FPA_AURAX_CFG(offset) (0x000128002010ull + ((offset)
& 1023) * 8)
+#define CVMX_FPA_AURAX_CNT(offset) (0x000128002020ull + ((offset)
& 1023) * 8)
+#define CVMX_FPA_AURAX_CNT_ADD(offset) (0x000128002030ull + ((offset)
& 1023) * 8)
+#define CVMX_FPA_AURAX_CNT_LEVELS(offset)(0x000128002080ull +
((offset) & 1023) * 8)
+#define CVMX_FPA_AURAX_CNT_LIMIT(offset) (0x000128002040ull +
((offset) & 1023) * 8)
+#define CVMX_FPA_AURAX_CNT_THRESHOLD(offset) (0x000128002050ull +
((offset) & 1023) * 8)
+#define CVMX_FPA_AURAX_INT(offset) (0x000128002060ull + ((offset)
& 1023) * 8)
+#define CVMX_FPA_AURAX_POOL(offset) (0x000128002000ull + ((offset)
& 1023) * 8)
+#define CVMX_FPA_AURAX_POOL_LEVELS(offset) (0x000128002070ull +
((offset) & 1023) * 8)
+#define CVMX_FPA_BIST_STATUSCVMX_FPA_BIST_STATUS_FUNC()
+static inline u64 CVMX_FPA_BIST_STATUS_FUNC(void)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x0001180028E8ull;
+ case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
+ return 0x000128E8ull;
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return 0x000128E8ull;
+ case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+ return 0x000128E8ull;
+ }
+ return 0x000128E8ull;
+}
+
+#ifndef CVMX_FPA_CLK_COUNT // test-only (also in octeon_ddr.h)
+#define CVMX_FPA_CLK_COUNT (0x000128F0ull)
+#endif
+#define CVMX_FPA_CTL_STATUS (0x000118002850ull)
+#define CVMX_FPA_ECC_CTL(0x00012858ull)
+#define CVMX_FPA_ECC_INT(0x00012868ull)
+#define CVMX_FPA_ERR_INT(0x00012840ull)
+#define CVMX_FPA_FPF0_MARKS (0x000118002800ull)
+#define CVMX_FPA_FPF0_SIZE (0x000118002858ull)
+#define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1)
+#define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2)
+#define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3)
+#define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4)
+#define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5)
+#define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6)
+#define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7)
+#define CVMX_FPA_FPF8_MARKS (0x0001180028000240ull)
+#define CVMX_FPA_FPF8_SIZE (0x0001180028000248ull)
+#define CVMX_FPA_FPFX_MARKS(offset) (0x000118002808ull + ((offset) &
7) * 8 - 8 * 1)
+#define CVMX_FPA_FPFX_SIZE(offset) (0x000118002860ull + ((offset) &
7) * 8 - 8 * 1)
+#define
[PATCH v1 08/50] mips: octeon: Add cvmx-dpi-defs.h header file
From: Aaron Williams
Import cvmx-dpi-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mach-octeon/include/mach/cvmx-dpi-defs.h | 1460 +
1 file changed, 1460 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-dpi-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-dpi-defs.h
b/arch/mips/mach-octeon/include/mach/cvmx-dpi-defs.h
new file mode 100644
index 00..680989463b
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-dpi-defs.h
@@ -0,0 +1,1460 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon dpi.
+ */
+
+#ifndef __CVMX_DPI_DEFS_H__
+#define __CVMX_DPI_DEFS_H__
+
+#define CVMX_DPI_BIST_STATUS(0x0001DF00ull)
+#define CVMX_DPI_CTL(0x0001DF40ull)
+#define CVMX_DPI_DMAX_COUNTS(offset)(0x0001DF000300ull + ((offset)
& 7) * 8)
+#define CVMX_DPI_DMAX_DBELL(offset) (0x0001DF000200ull + ((offset)
& 7) * 8)
+#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (0x0001DF000A80ull +
((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_IBUFF_SADDR(offset)(0x0001DF000280ull +
((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_IFLIGHT(offset) (0x0001DF000A00ull + ((offset)
& 7) * 8)
+#define CVMX_DPI_DMAX_NADDR(offset) (0x0001DF000380ull + ((offset)
& 7) * 8)
+#define CVMX_DPI_DMAX_REQBNK0(offset) (0x0001DF000400ull + ((offset)
& 7) * 8)
+#define CVMX_DPI_DMAX_REQBNK1(offset) (0x0001DF000480ull + ((offset)
& 7) * 8)
+#define CVMX_DPI_DMAX_REQQ_CTL(offset) (0x0001DF000180ull + ((offset)
& 7) * 8)
+#define CVMX_DPI_DMA_CONTROL(0x0001DF48ull)
+#define CVMX_DPI_DMA_ENGX_EN(offset)(0x0001DF80ull + ((offset)
& 7) * 8)
+static inline u64 CVMX_DPI_DMA_PPX_CNT(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ return 0x0001DF000B00ull + (offset) * 8;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x0001DF000B00ull + (offset) * 8;
+ case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+ return 0x0001DF000C00ull + (offset) * 8;
+ case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
+ return 0x0001DF000C00ull + (offset) * 8;
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return 0x0001DF000C00ull + (offset) * 8;
+ }
+ return 0x0001DF000C00ull + (offset) * 8;
+}
+
+#define CVMX_DPI_DMA_PP_INT (0x0001DF38ull)
+#define CVMX_DPI_ECC_CTL (0x0001DF18ull)
+#define CVMX_DPI_ECC_INT (0x0001DF20ull)
+#define CVMX_DPI_ENGX_BUF(offset) (0x0001DF000880ull + ((offset) & 7)
* 8)
+#define CVMX_DPI_INFO_REG(0x0001DF000980ull)
+#define CVMX_DPI_INT_EN (0x0001DF10ull)
+#define CVMX_DPI_INT_REG (0x0001DF08ull)
+#define CVMX_DPI_NCBX_CFG(offset) (0x0001DF000800ull)
+#define CVMX_DPI_NCB_CTL (0x0001DF28ull)
+#define CVMX_DPI_PINT_INFO (0x0001DF000830ull)
+#define CVMX_DPI_PKT_ERR_RSP (0x0001DF78ull)
+#define CVMX_DPI_REQ_ERR_RSP (0x0001DF58ull)
+#define CVMX_DPI_REQ_ERR_RSP_EN (0x0001DF68ull)
+#define CVMX_DPI_REQ_ERR_RST (0x0001DF60ull)
+#define CVMX_DPI_REQ_ERR_RST_EN (0x0001DF70ull)
+#define CVMX_DPI_REQ_ERR_SKIP_COMP(0x0001DF000838ull)
+#define CVMX_DPI_REQ_GBL_EN (0x0001DF50ull)
+#define CVMX_DPI_SLI_PRTX_CFG(offset) (0x0001DF000900ull + ((offset) & 3)
* 8)
+static inline u64 CVMX_DPI_SLI_PRTX_ERR(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
+ return 0x0001DF000920ull + (offset) * 8;
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return 0x0001DF000920ull + (offset) * 8;
+ return 0x0001DF000920ull + (offset) * 8;
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+
+ if
[PATCH v1 15/50] mips: octeon: Add cvmx-mio-defs.h header file
From: Aaron Williams
Import cvmx-mio-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mach-octeon/include/mach/cvmx-mio-defs.h | 353 ++
1 file changed, 353 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-mio-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-mio-defs.h
b/arch/mips/mach-octeon/include/mach/cvmx-mio-defs.h
new file mode 100644
index 00..23a18be54e
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-mio-defs.h
@@ -0,0 +1,353 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef __CVMX_MIO_DEFS_H__
+#define __CVMX_MIO_DEFS_H__
+
+#define CVMX_MIO_PTP_CLOCK_CFG (0x000107000F00ull)
+#define CVMX_MIO_PTP_EVT_CNT (0x000107000F28ull)
+#define CVMX_MIO_RST_BOOT(0x000118001600ull)
+#define CVMX_MIO_RST_CTLX(offset) (0x000118001618ull + ((offset) & 1))
+#define CVMX_MIO_QLMX_CFG(offset) (0x000118001590ull + ((offset) & 7) * 8)
+
+/**
+ * cvmx_mio_ptp_clock_cfg
+ *
+ * This register configures the timestamp architecture.
+ *
+ */
+union cvmx_mio_ptp_clock_cfg {
+ u64 u64;
+ struct cvmx_mio_ptp_clock_cfg_s {
+ u64 reserved_40_63 : 24;
+ u64 ext_clk_edge : 2;
+ u64 ckout_out4 : 1;
+ u64 pps_out : 5;
+ u64 pps_inv : 1;
+ u64 pps_en : 1;
+ u64 ckout_out : 4;
+ u64 ckout_inv : 1;
+ u64 ckout_en : 1;
+ u64 evcnt_in : 6;
+ u64 evcnt_edge : 1;
+ u64 evcnt_en : 1;
+ u64 tstmp_in : 6;
+ u64 tstmp_edge : 1;
+ u64 tstmp_en : 1;
+ u64 ext_clk_in : 6;
+ u64 ext_clk_en : 1;
+ u64 ptp_en : 1;
+ } s;
+ struct cvmx_mio_ptp_clock_cfg_cn61xx {
+ u64 reserved_42_63 : 22;
+ u64 pps : 1;
+ u64 ckout : 1;
+ u64 ext_clk_edge : 2;
+ u64 ckout_out4 : 1;
+ u64 pps_out : 5;
+ u64 pps_inv : 1;
+ u64 pps_en : 1;
+ u64 ckout_out : 4;
+ u64 ckout_inv : 1;
+ u64 ckout_en : 1;
+ u64 evcnt_in : 6;
+ u64 evcnt_edge : 1;
+ u64 evcnt_en : 1;
+ u64 tstmp_in : 6;
+ u64 tstmp_edge : 1;
+ u64 tstmp_en : 1;
+ u64 ext_clk_in : 6;
+ u64 ext_clk_en : 1;
+ u64 ptp_en : 1;
+ } cn61xx;
+ struct cvmx_mio_ptp_clock_cfg_cn63xx {
+ u64 reserved_24_63 : 40;
+ u64 evcnt_in : 6;
+ u64 evcnt_edge : 1;
+ u64 evcnt_en : 1;
+ u64 tstmp_in : 6;
+ u64 tstmp_edge : 1;
+ u64 tstmp_en : 1;
+ u64 ext_clk_in : 6;
+ u64 ext_clk_en : 1;
+ u64 ptp_en : 1;
+ } cn63xx;
+ struct cvmx_mio_ptp_clock_cfg_cn63xx cn63xxp1;
+ struct cvmx_mio_ptp_clock_cfg_s cn66xx;
+ struct cvmx_mio_ptp_clock_cfg_cn61xx cn68xx;
+ struct cvmx_mio_ptp_clock_cfg_cn63xx cn68xxp1;
+ struct cvmx_mio_ptp_clock_cfg_cn70xx {
+ u64 reserved_42_63 : 22;
+ u64 ckout : 1;
+ u64 pps : 1;
+ u64 ext_clk_edge : 2;
+ u64 reserved_32_37 : 6;
+ u64 pps_inv : 1;
+ u64 pps_en : 1;
+ u64 reserved_26_29 : 4;
+ u64 ckout_inv : 1;
+ u64 ckout_en : 1;
+ u64 evcnt_in : 6;
+ u64 evcnt_edge : 1;
+ u64 evcnt_en : 1;
+ u64 tstmp_in : 6;
+ u64 tstmp_edge : 1;
+ u64 tstmp_en : 1;
+ u64 ext_clk_in : 6;
+ u64 ext_clk_en : 1;
+ u64 ptp_en : 1;
+ } cn70xx;
+ struct cvmx_mio_ptp_clock_cfg_cn70xx cn70xxp1;
+ struct cvmx_mio_ptp_clock_cfg_cn70xx cn73xx;
+ struct cvmx_mio_ptp_clock_cfg_cn70xx cn78xx;
+ struct cvmx_mio_ptp_clock_cfg_cn70xx cn78xxp1;
+ struct cvmx_mio_ptp_clock_cfg_cn61xx cnf71xx;
+ struct cvmx_mio_ptp_clock_cfg_cn70xx cnf75xx;
+};
+
+typedef union cvmx_mio_ptp_clock_cfg cvmx_mio_ptp_clock_cfg_t;
+
+/**
+ * cvmx_mio_ptp_evt_cnt
+ *
+ * This register contains the PTP event counter.
+ *
+ */
+union cvmx_mio_ptp_evt_cnt {
+ u64 u64;
+ struct cvmx_mio_ptp_evt_cnt_s {
+ u64 cntr : 64;
+ } s;
+ struct cvmx_mio_ptp_evt_cnt_s cn61xx;
+ struct cvmx_mio_ptp_evt_cnt_s cn63xx;
+ struct cvmx_mio_ptp_evt_cnt_s cn63xxp1;
+ struct cvmx_mio_ptp_evt_cnt_s cn66xx;
+ struct cvmx_mio_ptp_evt_cnt_s cn68xx;
+ struct
[PATCH v1 14/50] mips: octeon: Add cvmx-l2c-defs.h header file
From: Aaron Williams
Import cvmx-l2c-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mach-octeon/include/mach/cvmx-l2c-defs.h | 172 ++
1 file changed, 172 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-l2c-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-l2c-defs.h
b/arch/mips/mach-octeon/include/mach/cvmx-l2c-defs.h
new file mode 100644
index 00..7fddcd6dfb
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-l2c-defs.h
@@ -0,0 +1,172 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef __CVMX_L2C_DEFS_H_
+#define __CVMX_L2C_DEFS_H_
+
+#define CVMX_L2C_CFG 0x000118008000ull
+#define CVMX_L2C_CTL 0x000118008080ull
+
+/*
+ * Mapping is done starting from 0x11800.8000
+ * Use _REL for relative mapping
+ */
+#define CVMX_L2C_CTL_REL0x0080
+#define CVMX_L2C_BIG_CTL_REL0x00800030
+#define CVMX_L2C_TADX_INT_REL(i) (0x00a00028 + (((i) & 7) * 0x4))
+#define CVMX_L2C_MCIX_INT_REL(i) (0x00c00028 + (((i) & 3) * 0x4))
+
+/**
+ * cvmx_l2c_cfg
+ *
+ * Specify the RSL base addresses for the block
+ *
+ * L2C_CFG = L2C Configuration
+ *
+ * Description:
+ */
+union cvmx_l2c_cfg {
+ u64 u64;
+ struct cvmx_l2c_cfg_s {
+ u64 reserved_20_63 : 44;
+ u64 bstrun : 1;
+ u64 lbist : 1;
+ u64 xor_bank : 1;
+ u64 dpres1 : 1;
+ u64 dpres0 : 1;
+ u64 dfill_dis : 1;
+ u64 fpexp : 4;
+ u64 fpempty : 1;
+ u64 fpen : 1;
+ u64 idxalias : 1;
+ u64 mwf_crd : 4;
+ u64 rsp_arb_mode : 1;
+ u64 rfb_arb_mode : 1;
+ u64 lrf_arb_mode : 1;
+ } s;
+};
+
+/**
+ * cvmx_l2c_ctl
+ *
+ * L2C_CTL = L2C Control
+ *
+ *
+ * Notes:
+ * (1) If MAXVAB is != 0, VAB_THRESH should be less than MAXVAB.
+ *
+ * (2) L2DFDBE and L2DFSBE allows software to generate L2DSBE, L2DDBE, VBFSBE,
+ * and VBFDBE errors for the purposes of testing error handling code. When
+ * one (or both) of these bits are set a PL2 which misses in the L2 will fill
+ * with the appropriate error in the first 2 OWs of the fill. Software can
+ * determine which OW pair gets the error by choosing the desired fill order
+ * (address<6:5>). A PL2 which hits in the L2 will not inject any errors.
+ * Therefore sending a WBIL2 prior to the PL2 is recommended to make a miss
+ * likely (if multiple processors are involved software must be careful to be
+ * sure no other processor or IO device can bring the block into the L2).
+ *
+ * To generate a VBFSBE or VBFDBE, software must first get the cache block
+ * into the cache with an error using a PL2 which misses the L2. Then a
+ * store partial to a portion of the cache block without the error must
+ * change the block to dirty. Then, a subsequent WBL2/WBIL2/victim will
+ * trigger the VBFSBE/VBFDBE error.
+ */
+union cvmx_l2c_ctl {
+ u64 u64;
+ struct cvmx_l2c_ctl_s {
+ u64 reserved_29_63 : 35;
+ u64 rdf_fast : 1;
+ u64 disstgl2i : 1;
+ u64 l2dfsbe : 1;
+ u64 l2dfdbe : 1;
+ u64 discclk : 1;
+ u64 maxvab : 4;
+ u64 maxlfb : 4;
+ u64 rsp_arb_mode : 1;
+ u64 xmc_arb_mode : 1;
+ u64 reserved_2_13 : 12;
+ u64 disecc : 1;
+ u64 disidxalias : 1;
+ } s;
+
+ struct cvmx_l2c_ctl_cn73xx {
+ u64 reserved_32_63 : 32;
+ u64 ocla_qos : 3;
+ u64 reserved_28_28 : 1;
+ u64 disstgl2i : 1;
+ u64 reserved_25_26 : 2;
+ u64 discclk : 1;
+ u64 reserved_16_23 : 8;
+ u64 rsp_arb_mode : 1;
+ u64 xmc_arb_mode : 1;
+ u64 rdf_cnt : 8;
+ u64 reserved_4_5 : 2;
+ u64 disldwb : 1;
+ u64 dissblkdty : 1;
+ u64 disecc : 1;
+ u64 disidxalias : 1;
+ } cn73xx;
+
+ struct cvmx_l2c_ctl_cn73xx cn78xx;
+};
+
+/**
+ * cvmx_l2c_big_ctl
+ *
+ * L2C_BIG_CTL = L2C Big memory control register
+ *
+ *
+ * Notes:
+ * (1) BIGRD interrupts can occur during normal operation as the PP's are
+ * allowed to prefetch to non-existent memory locations. Therefore,
+ * BIGRD is for informational purposes only.
+ *
+ * (2) When HOLEWR/BIGWR blocks a store L2C_VER_ID, L2C_VER_PP, L2C_VER_IOB,
+ * and L2C_VER_MSC will be loaded just like a store which is blocked by VRTWR.
+ * Additionally, L2C_ERR_XMC will be loaded.
+ */
+union cvmx_l2c_big_ctl {
+ u64 u64;
+ struct cvmx_l2c_big_ctl_s {
+
[PATCH v1 04/50] mips: octeon: Add cvmx-asxx-defs.h header file
From: Aaron Williams
Import cvmx-asxx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mach-octeon/include/mach/cvmx-asxx-defs.h | 709 ++
1 file changed, 709 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-asxx-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-asxx-defs.h
b/arch/mips/mach-octeon/include/mach/cvmx-asxx-defs.h
new file mode 100644
index 00..2af1a29d63
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-asxx-defs.h
@@ -0,0 +1,709 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon asxx.
+ */
+
+#ifndef __CVMX_ASXX_DEFS_H__
+#define __CVMX_ASXX_DEFS_H__
+
+#define CVMX_ASXX_GMII_RX_CLK_SET(offset)(0x00011800B180ull)
+#define CVMX_ASXX_GMII_RX_DAT_SET(offset)(0x00011800B188ull)
+#define CVMX_ASXX_INT_EN(offset)(0x00011800B018ull + ((offset)
& 1) * 0x800ull)
+#define CVMX_ASXX_INT_REG(offset) (0x00011800B010ull + ((offset)
& 1) * 0x800ull)
+#define CVMX_ASXX_MII_RX_DAT_SET(offset) (0x00011800B190ull)
+#define CVMX_ASXX_PRT_LOOP(offset) (0x00011800B040ull + ((offset)
& 1) * 0x800ull)
+#define CVMX_ASXX_RLD_BYPASS(offset)(0x00011800B248ull + ((offset)
& 1) * 0x800ull)
+#define CVMX_ASXX_RLD_BYPASS_SETTING(offset) (0x00011800B250ull +
((offset) & 1) * 0x800ull)
+#define CVMX_ASXX_RLD_COMP(offset) (0x00011800B220ull + ((offset)
& 1) * 0x800ull)
+#define CVMX_ASXX_RLD_DATA_DRV(offset) (0x00011800B218ull + ((offset)
& 1) * 0x800ull)
+#define CVMX_ASXX_RLD_FCRAM_MODE(offset) (0x00011800B210ull +
((offset) & 1) * 0x800ull)
+#define CVMX_ASXX_RLD_NCTL_STRONG(offset)(0x00011800B230ull +
((offset) & 1) * 0x800ull)
+#define CVMX_ASXX_RLD_NCTL_WEAK(offset) (0x00011800B240ull +
((offset) & 1) * 0x800ull)
+#define CVMX_ASXX_RLD_PCTL_STRONG(offset)(0x00011800B228ull +
((offset) & 1) * 0x800ull)
+#define CVMX_ASXX_RLD_PCTL_WEAK(offset) (0x00011800B238ull +
((offset) & 1) * 0x800ull)
+#define CVMX_ASXX_RLD_SETTING(offset) (0x00011800B258ull + ((offset)
& 1) * 0x800ull)
+#define CVMX_ASXX_RX_CLK_SETX(offset, block_id)
\
+ (0x00011800B020ull + (((offset) & 3) + ((block_id) & 1) *
0x100ull) * 8)
+#define CVMX_ASXX_RX_PRT_EN(offset)(0x00011800B000ull + ((offset) & 1)
* 0x800ull)
+#define CVMX_ASXX_RX_WOL(offset) (0x00011800B100ull + ((offset) & 1)
* 0x800ull)
+#define CVMX_ASXX_RX_WOL_MSK(offset) (0x00011800B108ull + ((offset) & 1)
* 0x800ull)
+#define CVMX_ASXX_RX_WOL_POWOK(offset) (0x00011800B118ull + ((offset) & 1)
* 0x800ull)
+#define CVMX_ASXX_RX_WOL_SIG(offset) (0x00011800B110ull + ((offset) & 1)
* 0x800ull)
+#define CVMX_ASXX_TX_CLK_SETX(offset, block_id)
\
+ (0x00011800B048ull + (((offset) & 3) + ((block_id) & 1) *
0x100ull) * 8)
+#define CVMX_ASXX_TX_COMP_BYP(offset) (0x00011800B068ull + ((offset) & 1)
* 0x800ull)
+#define CVMX_ASXX_TX_HI_WATERX(offset, block_id)
\
+ (0x00011800B080ull + (((offset) & 3) + ((block_id) & 1) *
0x100ull) * 8)
+#define CVMX_ASXX_TX_PRT_EN(offset) (0x00011800B008ull + ((offset) & 1) *
0x800ull)
+
+/**
+ * cvmx_asx#_gmii_rx_clk_set
+ *
+ * ASX_GMII_RX_CLK_SET = GMII Clock delay setting
+ *
+ */
+union cvmx_asxx_gmii_rx_clk_set {
+ u64 u64;
+ struct cvmx_asxx_gmii_rx_clk_set_s {
+ u64 reserved_5_63 : 59;
+ u64 setting : 5;
+ } s;
+ struct cvmx_asxx_gmii_rx_clk_set_s cn30xx;
+ struct cvmx_asxx_gmii_rx_clk_set_s cn31xx;
+ struct cvmx_asxx_gmii_rx_clk_set_s cn50xx;
+};
+
+typedef union cvmx_asxx_gmii_rx_clk_set cvmx_asxx_gmii_rx_clk_set_t;
+
+/**
+ * cvmx_asx#_gmii_rx_dat_set
+ *
+ * ASX_GMII_RX_DAT_SET = GMII Clock delay setting
+ *
+ */
+union cvmx_asxx_gmii_rx_dat_set {
+ u64 u64;
+ struct cvmx_asxx_gmii_rx_dat_set_s {
+ u64 reserved_5_63 : 59;
+ u64 setting : 5;
+ } s;
+ struct cvmx_asxx_gmii_rx_dat_set_s cn30xx;
+ struct cvmx_asxx_gmii_rx_dat_set_s cn31xx;
+ struct cvmx_asxx_gmii_rx_dat_set_s cn50xx;
+};
+
+typedef union cvmx_asxx_gmii_rx_dat_set cvmx_asxx_gmii_rx_dat_set_t;
+
+/**
+ * cvmx_asx#_int_en
+ *
+ * ASX_INT_EN = Interrupt Enable
+ *
+ */
+union cvmx_asxx_int_en {
+ u64 u64;
+ struct cvmx_asxx_int_en_s {
+ u64 reserved_12_63 : 52;
+ u64
[PATCH v1 07/50] mips: octeon: Add cvmx-dbg-defs.h header file
From: Aaron Williams
Import cvmx-dbg-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mach-octeon/include/mach/cvmx-dbg-defs.h | 33 +++
1 file changed, 33 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-dbg-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-dbg-defs.h
b/arch/mips/mach-octeon/include/mach/cvmx-dbg-defs.h
new file mode 100644
index 00..9f91feec18
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-dbg-defs.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon dbg.
+ */
+
+#ifndef __CVMX_DBG_DEFS_H__
+#define __CVMX_DBG_DEFS_H__
+
+#define CVMX_DBG_DATA (0x00011F0001E8ull)
+
+/**
+ * cvmx_dbg_data
+ *
+ * DBG_DATA = Debug Data Register
+ *
+ * Value returned on the debug-data lines from the RSLs
+ */
+union cvmx_dbg_data {
+ u64 u64;
+ struct cvmx_dbg_data_s {
+ u64 reserved_23_63 : 41;
+ u64 c_mul : 5;
+ u64 dsel_ext : 1;
+ u64 data : 17;
+ } s;
+};
+
+typedef union cvmx_dbg_data cvmx_dbg_data_t;
+
+#endif
--
2.29.2
[PATCH v1 00/50] mips: octeon: Add serdes and device helper support incl. DM PCIe driver
This patchset adds the serdes and (mostly networking) device helper macros and functions, needed to support the still missing Octeon II / III devices in mainline U-Boot. Please excuse the massive amount of files in this patch series. Also the sometimes huge files (mostly headers with register definitions) that I needed to include. The infrastructure code with all the headers is ported without any intended functional changes from the 2013 Cavium / Marvell U-Boot version. It has undergone many hours of extensive code cleanup and reformatting. Some of it done by using tools (checkpatch, Lindent, clang format etc) and also some of it done manually, as I couldn't find some tools that could do the needed work in a reliable and functional way. The result is that checkpatch now only throws a "few" warnings that are left. Some of those can't be removed without an even more extensive cleanup / rewrite of the code, like the addition of typedefs. The added headers and helper functions will be used by the upcoming support for the Octeon II / III networking drivers, including PHY & switch support. It was not easily possible to split these infrastructure files into a separate patchset, as it is heavily interconnected in the common QLM/DLM serdes interface initialization. The result is, that the upcoming ethernet driver support will be much smaller (this is at least my current assumption). The added PCIe RC support with the included DM PCIe driver is the first driver making use of this Octeon serdes infrastructure. This has been tested with an Intel E1000 PCIe network card in the Octeon 7304 EBB. Thanks, Stefan Aaron Williams (42): mips: octeon: Add misc cvmx-helper header files mips: octeon: Add cvmx-agl-defs.h header file mips: octeon: Add cvmx-asxx-defs.h header file mips: octeon: Add cvmx-bgxx-defs.h header file mips: octeon: Add cvmx-ciu-defs.h header file mips: octeon: Add cvmx-dbg-defs.h header file mips: octeon: Add cvmx-dpi-defs.h header file mips: octeon: Add cvmx-dtx-defs.h header file mips: octeon: Add cvmx-fpa-defs.h header file mips: octeon: Add cvmx-gmxx-defs.h header file mips: octeon: Add cvmx-gserx-defs.h header file mips: octeon: Add cvmx-ipd-defs.h header file mips: octeon: Add cvmx-l2c-defs.h header file mips: octeon: Add cvmx-mio-defs.h header file mips: octeon: Add cvmx-npi-defs.h header file mips: octeon: Add cvmx-pcieepx-defs.h header file mips: octeon: Add cvmx-pciercx-defs.h header file mips: octeon: Add cvmx-pcsx-defs.h header file mips: octeon: Add cvmx-pemx-defs.h header file mips: octeon: Add cvmx-pepx-defs.h header file mips: octeon: Add cvmx-pip-defs.h header file mips: octeon: Add cvmx-pki-defs.h header file mips: octeon: Add cvmx-pko-defs.h header file mips: octeon: Add cvmx-pow-defs.h header file mips: octeon: Add cvmx-rst-defs.h header file mips: octeon: Add cvmx-sata-defs.h header file mips: octeon: Add cvmx-sli-defs.h header file mips: octeon: Add cvmx-smix-defs.h header file mips: octeon: Add cvmx-sriomaintx-defs.h header file mips: octeon: Add cvmx-sriox-defs.h header file mips: octeon: Add cvmx-sso-defs.h header file mips: octeon: Add misc remaining header files mips: octeon: Add cvmx-helper-cfg.c mips: octeon: Add cvmx-helper-fdt.c mips: octeon: Add cvmx-helper-jtag.c mips: octeon: Add cvmx-helper-util.c mips: octeon: Add cvmx-helper.c mips: octeon: Add cvmx-pcie.c mips: octeon: Add cvmx-qlm.c mips: octeon: Add octeon_fdt.c mips: octeon: Add octeon_qlm.c mips: octeon: octeon_ebb7304: Add board specific QLM init code Stefan Roese (8): mips: global_data.h: Add Octeon specific data to arch_global_data struct mips: octeon: Misc changes required because of the newly added headers mips: octeon: Move cvmx-lmcx-defs.h from mach/cvmx to mach mips: octeon: Makefile: Enable building of the newly added C files mips: octeon: Kconfig: Enable CONFIG_SYS_PCI_64BIT mips: octeon: mrvl,cn73xx.dtsi: Add PCIe controller DT node mips: octeon: Add Octeon PCIe host controller driver mips: octeon: octeon_ebb7304_defconfig: Enable Octeon PCIe and E1000 arch/mips/dts/mrvl,cn73xx.dtsi| 16 + arch/mips/include/asm/global_data.h |9 + arch/mips/mach-octeon/Kconfig |4 + arch/mips/mach-octeon/Makefile| 11 + arch/mips/mach-octeon/bootoctlinux.c |1 + arch/mips/mach-octeon/cvmx-bootmem.c |6 - arch/mips/mach-octeon/cvmx-coremask.c |1 + arch/mips/mach-octeon/cvmx-helper-cfg.c | 1914 arch/mips/mach-octeon/cvmx-helper-fdt.c | 970 ++ arch/mips/mach-octeon/cvmx-helper-jtag.c | 172 + arch/mips/mach-octeon/cvmx-helper-util.c | 1225 +++ arch/mips/mach-octeon/cvmx-helper.c | 2611 + arch/mips/mach-octeon/cvmx-pcie.c | 2487 + arch/mips/mach-octeon/cvmx-qlm.c | 2350 + .../mach-octeon/include/mach/cvmx-address.h | 209
[PATCH v1 01/50] mips: global_data.h: Add Octeon specific data to arch_global_data struct
This will be used by the upcoming Serdes and driver code ported from
the original 2013 U-Boot code to mainline.
Signed-off-by: Stefan Roese
---
arch/mips/include/asm/global_data.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/mips/include/asm/global_data.h
b/arch/mips/include/asm/global_data.h
index 4c30fab871..f0d3b07bf1 100644
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@@ -8,6 +8,12 @@
#define __ASM_GBL_DATA_H
#include
+#include
+
+struct octeon_eeprom_mac_addr {
+ u8 mac_addr_base[6];
+ u8 count;
+};
/* Architecture-specific global data */
struct arch_global_data {
@@ -30,6 +36,9 @@ struct arch_global_data {
#ifdef CONFIG_ARCH_MTMIPS
unsigned long timer_freq;
#endif
+#ifdef CONFIG_ARCH_OCTEON
+ struct octeon_eeprom_mac_addr mac_desc;
+#endif
};
#include
--
2.29.2
[PATCH] configs: stm32mp1: activate OF_LIVE for DT live support
Activate the live DT to reduce the DT parsing time. For example the boot time is reduced by 200ms on STM32MP157C-EV1 board for stm32mp15_basic_defconfig (boot with SPL) or stm32mp15_trusted_defconfig (boot with TF-A). Signed-off-by: Patrick Delaunay --- Commit for u-boot/next = v2021.04 The result on v2020.10 is: 1/stm32mp15_trusted_defconfig After the activation MarkElapsed Stage 0 0 reset 594,115594,115 board_init_f 764,062169,947 board_init_r 1,025,234261,172 id=64 1,025,493259 id=65 1,027,413 1,920 main_loop 3,545,057 2,517,644 id=175 Accumulated time: 1,430 dm_r 15,112 of_live 54,715 dm_f Before the activation MarkElapsed Stage 0 0 reset 596,882596,882 board_init_f 766,787169,905 board_init_r 1,228,988462,201 id=64 1,251,699 22,711 id=65 1,252,401702 main_loop 4,028,952 2,776,551 id=175 Accumulated time: 54,671 dm_f 66,176 dm_r 2/stm32mp15_basic_defconfig After the activation STM32MP> bootstage report Timer summary in microseconds (13 records): MarkElapsed Stage 0 0 reset 223,315223,315 SPL 1,093,158869,843 end SPL 1,095,947 2,789 board_init_f 1,317,473221,526 board_init_r 1,580,003262,530 id=64 1,580,265262 id=65 1,582,181 1,916 main_loop 4,465,148 2,882,967 id=175 Accumulated time: 1,405 dm_r 15,107 of_live 54,606 dm_f 89,236 dm_spl Before the activation STM32MP> bootstage report Timer summary in microseconds (12 records): MarkElapsed Stage 0 0 reset 223,304223,304 SPL 1,083,749860,445 end SPL 1,086,755 3,006 board_init_f 1,309,658222,903 board_init_r 1,771,209461,551 id=64 1,794,252 23,043 id=65 1,794,953701 main_loop 4,348,874 2,553,921 id=175 Accumulated time: 55,045 dm_f 66,755 dm_r 87,872 dm_spl This patch depends on 2 patches already merged in u-boot/next branch: [1] gpio: Convert to use APIs which support live DT http://patchwork.ozlabs.org/project/uboot/patch/20200909162617.31576-1-patrick.delau...@st.com/ [2] power: regulator: gpio-regulator: Convert to use APIs which support live DT http://patchwork.ozlabs.org/project/uboot/patch/20200910161817.27535-2-patrick.delau...@st.com/ configs/stm32mp15_basic_defconfig | 1 + configs/stm32mp15_trusted_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 1843bbcc78..9d3d40c4c4 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -56,6 +56,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y # CONFIG_SPL_DOS_PARTITION is not set +CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 964f4c2885..4cd7d1265d 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y +CONFIG_OF_LIVE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -- 2.17.1
[PATCH v2] string: Use memcpy() within memmove() when we can
A common use of memmove() can be handled by memcpy(). Also memcpy()
includes an optimization for large sizes: it copies a word at a time. So
we can get a speed-up by calling memcpy() to handle our move in this case.
Update memmove() to call also memcpy() if the source don't overlap
the destination (src + count <= dest).
Signed-off-by: Patrick Delaunay
---
Hi,
V2 of http://patchwork.ozlabs.org/project/uboot/list/?series=216620
This patch allows to save 38ms for Kernel Image extraction (7327624 Bytes)
from FIT loaded at 0xC200 for ARMV7 board STM32MP157C-EV1,
and with kernel destination = Load Address: 0xc400,
located after the FIT without overlap, compared with
destination = Load Address: 0xc0008000.
-> 14,332 us vs 52,239 in bootstage report
In this case the memmove funtion is called in common/image.c::memmove_wd()
to handle overlap.
Patrick
Changes in v2:
- Add a comment on potential issue if the memcpy is not doing a
forward-copying
lib/string.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/lib/string.c b/lib/string.c
index ae7835f600..73b984123d 100644
--- a/lib/string.c
+++ b/lib/string.c
@@ -567,7 +567,19 @@ void * memmove(void * dest,const void *src,size_t count)
{
char *tmp, *s;
- if (dest <= src) {
+ if (dest <= src || (src + count) <= dest) {
+ /*
+* Use the fast memcpy implementation (ARCH optimized or lib/string.c)
when it is possible:
+* - when dest is before src (assuming that memcpy is doing
forward-copying)
+* - when destination don't overlap the source buffer (src + count <=
dest)
+*
+* WARNING: the first optimisation cause an issue, when
__HAVE_ARCH_MEMCPY is defined,
+* __HAVE_ARCH_MEMMOVE is not defined and if the memcpy
ARCH-specific
+* implementation is not doing a forward-copying.
+*
+* No issue today because memcpy is doing a forward-copying in
lib/string.c and for ARM32
+* architecture; no other arches use __HAVE_ARCH_MEMCPY without
__HAVE_ARCH_MEMMOVE.
+*/
memcpy(dest, src, count);
} else {
tmp = (char *) dest + count;
--
2.17.1
Re: [PATCH v5 2/7] net: macb: Add DMA 64-bit address support for macb
Hi Padmarao,
On Fri, Dec 11, 2020 at 8:07 PM Padmarao Begari wrote:
>
> Hi Bin,
>
> On Fri, Dec 11, 2020 at 2:59 PM Bin Meng wrote:
>>
>> Hi Padmarao,
>>
>> On Fri, Dec 11, 2020 at 4:49 PM Padmarao Begari wrote:
>> >
>> > Hi Bin,
>> >
>> > On Thu, Dec 10, 2020 at 4:08 PM Bin Meng wrote:
>> >>
>> >> Hi Padmarao,
>> >>
>> >> On Thu, Dec 10, 2020 at 6:33 PM Bin Meng wrote:
>> >> >
>> >> > Hi Padmarao,
>> >> >
>> >> > On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
>> >> > wrote:
>> >> > >
>> >> > > Enable 32-bit or 64-bit DMA in the macb driver based on the macb
>> >> > > compatible string of the device tree node.
>> >> > >
>> >> > > Signed-off-by: Padmarao Begari
>> >> > > Reviewed-by: Anup Patel
>> >> > > ---
>> >> > > drivers/net/macb.c | 131
>> >> > > +++--
>> >> > > drivers/net/macb.h | 6 +++
>> >> > > 2 files changed, 120 insertions(+), 17 deletions(-)
>> >> > >
>> >> > > diff --git a/drivers/net/macb.c b/drivers/net/macb.c
>> >> > > index b80a259ff7..e7c93d4747 100644
>> >> > > --- a/drivers/net/macb.c
>> >> > > +++ b/drivers/net/macb.c
>> >> > > @@ -83,7 +83,16 @@ struct macb_dma_desc {
>> >> > > u32 ctrl;
>> >> > > };
>> >> > >
>> >> > > -#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
>> >> > > +struct macb_dma_desc_64 {
>> >> > > + u32 addrh;
>> >> > > + u32 unused;
>> >> > > +};
>> >> > > +
>> >> > > +#define HW_DMA_CAP_32B 0
>> >> > > +#define HW_DMA_CAP_64B 1
>> >> > > +
>> >> > > +#define DMA_DESC_SIZE 16
>> >> > > +#define DMA_DESC_BYTES(n) ((n) * DMA_DESC_SIZE)
>> >> > > #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
>> >> > > #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
>> >> > > #define MACB_TX_DUMMY_DMA_DESC_SIZE(DMA_DESC_BYTES(1))
>> >> > > @@ -133,6 +142,7 @@ struct macb_device {
>> >> > > #endif
>> >> > > phy_interface_t phy_interface;
>> >> > > #endif
>> >> > > + unsigned short hw_dma_cap;
>> >> > > };
>> >> > >
>> >> > > struct macb_config {
>> >> > > @@ -307,6 +317,24 @@ static inline void
>> >> > > macb_invalidate_rx_buffer(struct macb_device *macb)
>> >> > >
>> >> > > #if defined(CONFIG_CMD_NET)
>> >> > >
>> >> > > +static struct macb_dma_desc_64 *macb_64b_desc(struct macb_dma_desc
>> >> > > *desc)
>> >> > > +{
>> >> > > + return (struct macb_dma_desc_64 *)((void *)desc
>> >> > > + + sizeof(struct macb_dma_desc));
>> >> > > +}
>> >> > > +
>> >> > > +static void macb_set_addr(struct macb_device *macb, struct
>> >> > > macb_dma_desc *desc,
>> >> > > + ulong addr)
>> >> > > +{
>> >> > > + struct macb_dma_desc_64 *desc_64;
>> >> > > +
>> >> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B) {
>> >> > > + desc_64 = macb_64b_desc(desc);
>> >> > > + desc_64->addrh = upper_32_bits(addr);
>> >> > > + }
>> >> > > + desc->addr = lower_32_bits(addr);
>> >> > > +}
>> >> > > +
>> >> > > static int _macb_send(struct macb_device *macb, const char *name,
>> >> > > void *packet,
>> >> > > int length)
>> >> > > {
>> >> > > @@ -325,8 +353,12 @@ static int _macb_send(struct macb_device *macb,
>> >> > > const char *name, void *packet,
>> >> > > macb->tx_head++;
>> >> > > }
>> >> > >
>> >> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
>> >> > > + tx_head = tx_head * 2;
>> >> > > +
>> >> > > macb->tx_ring[tx_head].ctrl = ctrl;
>> >> > > - macb->tx_ring[tx_head].addr = paddr;
>> >> > > + macb_set_addr(macb, >tx_ring[tx_head], paddr);
>> >> > > +
>> >> > > barrier();
>> >> > > macb_flush_ring_desc(macb, TX);
>> >> > > macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) |
>> >> > > MACB_BIT(TSTART));
>> >> > > @@ -363,19 +395,28 @@ static void reclaim_rx_buffers(struct
>> >> > > macb_device *macb,
>> >> > >unsigned int new_tail)
>> >> > > {
>> >> > > unsigned int i;
>> >> > > + unsigned int count;
>> >> > >
>> >> > > i = macb->rx_tail;
>> >> > >
>> >> > > macb_invalidate_ring_desc(macb, RX);
>> >> > > while (i > new_tail) {
>> >> > > - macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
>> >> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
>> >> > > + count = i * 2;
>> >> > > + else
>> >> > > + count = i;
>> >> > > + macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
>> >> > > i++;
>> >> > > if (i > MACB_RX_RING_SIZE)
>> >> > > i = 0;
>> >> > > }
>> >> > >
>> >> > > while (i < new_tail) {
>> >> > > - macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
>> >> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
>> >> > > + count = i * 2;
Re: [PATCH v5 5/7] riscv: dts: Add device tree for Microchip Icicle Kit
Hi Padmarao,
On Fri, Dec 11, 2020 at 7:37 PM Padmarao Begari wrote:
>
> Hi Bin,
>
> On Fri, Dec 11, 2020 at 2:55 PM Bin Meng wrote:
>>
>> Hi Padmarao,
>>
>> On Fri, Dec 11, 2020 at 4:32 PM Padmarao Begari wrote:
>> >
>> > Hi Bin,
>> >
>> > On Fri, Dec 11, 2020 at 1:31 PM Bin Meng wrote:
>> >>
>> >> Hi Padmarao,
>> >>
>> >> On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
>> >> wrote:
>> >> >
>> >> > Add device tree for Microchip PolarFire SoC Icicle Kit.
>> >> >
>> >> > Signed-off-by: Padmarao Begari
>> >> > Reviewed-by: Anup Patel
>> >>
>> >> Sorry 2 more warnings, please check below:
>> >>
>> >> > ---
>> >> > arch/riscv/dts/Makefile | 1 +
>> >> > .../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
>> >> > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 ++
>> >> > 3 files changed, 436 insertions(+)
>> >> > create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
>> >> > create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts
>> >> >
>> >> > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
>> >> > index 3a6f96c67d..01331b0aa1 100644
>> >> > --- a/arch/riscv/dts/Makefile
>> >> > +++ b/arch/riscv/dts/Makefile
>> >> > @@ -3,6 +3,7 @@
>> >> > dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
>> >> > dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
>> >> > dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
>> >> > +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
>> >> >
>> >> > targets += $(dtb-y)
>> >> >
>> >> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
>> >> > b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
>> >> > new file mode 100644
>> >> > index 00..f60283fb6b
>> >> > --- /dev/null
>> >> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
>> >> > @@ -0,0 +1,14 @@
>> >> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> >> > +/*
>> >> > + * Copyright (C) 2020 Microchip Technology Inc.
>> >> > + * Padmarao Begari
>> >> > + */
>> >> > +
>> >> > +/ {
>> >> > + aliases {
>> >> > + cpu1 =
>> >> > + cpu2 =
>> >> > + cpu3 =
>> >> > + cpu4 =
>> >> > + };
>> >> > +};
>> >> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
>> >> > b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
>> >> > new file mode 100644
>> >> > index 00..f5478bf201
>> >> > --- /dev/null
>> >> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
>> >> > @@ -0,0 +1,421 @@
>> >> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> >> > +/* Copyright (c) 2020 Microchip Technology Inc */
>> >> > +
>> >> > +/dts-v1/;
>> >> > +#include "dt-bindings/clock/microchip,mpfs-clock.h"
>> >> > +
>> >> > +/* Clock frequency (in Hz) of the rtcclk */
>> >> > +#define RTCCLK_FREQ100
>> >> > +
>> >> > +/ {
>> >> > + #address-cells = <2>;
>> >> > + #size-cells = <2>;
>> >> > + model = "Microchip MPFS Icicle Kit";
>> >> > + compatible = "microchip,mpfs-icicle-kit";
>> >> > +
>> >> > + aliases {
>> >> > + serial0 =
>> >> > + ethernet0 =
>> >> > + };
>> >> > +
>> >> > + chosen {
>> >> > + stdout-path = "serial0";
>> >> > + };
>> >> > +
>> >> > + cpucomplex: cpus {
>> >> > + #address-cells = <1>;
>> >> > + #size-cells = <0>;
>> >> > + timebase-frequency = ;
>> >> > + cpu0: cpu@0 {
>> >> > + clocks = < CLK_CPU>;
>> >> > + compatible = "sifive,e51", "sifive,rocket0",
>> >> > "riscv";
>> >> > + device_type = "cpu";
>> >> > + i-cache-block-size = <64>;
>> >> > + i-cache-sets = <128>;
>> >> > + i-cache-size = <16384>;
>> >> > + reg = <0>;
>> >> > + riscv,isa = "rv64imac";
>> >> > + status = "disabled";
>> >> > + operating-points = <
>> >> > + /* kHz uV */
>> >> > + 60 110
>> >> > + 30 95
>> >> > + 15 75
>> >> > + >;
>> >> > + cpu0intc: interrupt-controller {
>> >> > + #interrupt-cells = <1>;
>> >> > + compatible = "riscv,cpu-intc";
>> >> > + interrupt-controller;
>> >> > + };
>> >> > + };
>> >> > + cpu1: cpu@1 {
>> >> > + clocks = < CLK_CPU>;
>> >> > + compatible = "sifive,u54-mc", "sifive,rocket0",
>> >> > "riscv";
>> >> > + d-cache-block-size = <64>;
>> >> > + d-cache-sets = <64>;
>> >> > +
[PATCH] arm: stm32mp: stm32prog: always flush DFU on start command for uart
From: Patrick Delaunay
Remove the test on data->dfu_seq, because dfu_seq=0 not only when
the DFU is not started (mask with 0x). This flush is mandatory
as the final treatment, common with USB, is done in DFU callback.
This patch avoids issue if the received length is a multiple of
the DFU packet.
For example if size of bootfs partition is egual to 0x400,
data->dfu_seq=0 at the end of the partition, the flush it not
requested and the phase is not increased in the callback.
U-Boot continue to request the bootfs in the next GetPhase command.
Fixes: 468f0508b58b ("stm32mp: stm32prog: add serial link support")
Signed-off-by: Patrick Delaunay
Signed-off-by: Patrick Delaunay
---
.../mach-stm32mp/cmd_stm32prog/stm32prog_serial.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
index 8aad4be467..8fba92b2b5 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
@@ -397,14 +397,13 @@ static u8 stm32prog_start(struct stm32prog_data *data,
u32 address)
if (!dfu_entity)
return -ENODEV;
- if (data->dfu_seq) {
- ret = dfu_flush(dfu_entity, NULL, 0, data->dfu_seq);
- data->dfu_seq = 0;
- if (ret) {
- stm32prog_err("DFU flush failed [%d]", ret);
- return ret;
- }
+ ret = dfu_flush(dfu_entity, NULL, 0, data->dfu_seq);
+ if (ret) {
+ stm32prog_err("DFU flush failed [%d]", ret);
+ return ret;
}
+ data->dfu_seq = 0;
+
printf("\n received length = 0x%x\n", data->cursor);
if (data->header.present) {
if (data->cursor !=
--
2.17.1
Re: [PATCH v5 1/7] riscv: Add DMA 64-bit address support
Hi Bin, On Fri, Dec 11, 2020 at 2:57 PM Bin Meng wrote: > HI Padmarao, > > On Fri, Dec 11, 2020 at 4:23 PM Padmarao Begari > wrote: > > > > Hi Bin, > > > > On Fri, Dec 11, 2020 at 1:22 PM Bin Meng wrote: > >> > >> Hi Padmarao, > >> > >> On Fri, Dec 11, 2020 at 3:10 PM Padmarao Begari > wrote: > >> > > >> > Hi Bin, > >> > > >> > On Thu, Dec 10, 2020 at 4:11 PM Bin Meng wrote: > >> >> > >> >> Hi Padmarao, > >> >> > >> >> On Thu, Dec 3, 2020 at 4:43 AM Padmarao Begari > >> >> wrote: > >> >> > > >> >> > dma_addr_t holds any valid DMA address. If the DMA API only uses > 32/64-bit > >> >> > addresses, dma_addr_t need only be 32/64 bits wide. > >> >> > > >> >> > Signed-off-by: Padmarao Begari > >> >> > Reviewed-by: Anup Patel > >> >> > --- > >> >> > arch/riscv/Kconfig | 4 > >> >> > arch/riscv/include/asm/types.h | 4 > >> >> > 2 files changed, 8 insertions(+) > >> >> > > >> >> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > >> >> > index 30b05408b1..55eaee2da6 100644 > >> >> > --- a/arch/riscv/Kconfig > >> >> > +++ b/arch/riscv/Kconfig > >> >> > @@ -152,6 +152,10 @@ config 32BIT > >> >> > config 64BIT > >> >> > bool > >> >> > > >> >> > +config DMA_ADDR_T_64BIT > >> >> > + bool > >> >> > + default y if 64BIT > >> >> > + > >> >> > config SIFIVE_CLINT > >> >> > bool > >> >> > depends on RISCV_MMODE || SPL_RISCV_MMODE > >> >> > diff --git a/arch/riscv/include/asm/types.h > b/arch/riscv/include/asm/types.h > >> >> > index 403cf9a48f..b800b2d221 100644 > >> >> > --- a/arch/riscv/include/asm/types.h > >> >> > +++ b/arch/riscv/include/asm/types.h > >> >> > @@ -29,7 +29,11 @@ typedef unsigned short umode_t; > >> >> > > >> >> > #include > >> >> > > >> >> > +#ifdef CONFIG_DMA_ADDR_T_64BIT > >> >> > +typedef u64 dma_addr_t; > >> >> > +#else > >> >> > typedef u32 dma_addr_t; > >> >> > +#endif > >> >> > >> >> Why is this patch needed for U-Boot? > >> >> > >> > > >> > Initially this patch was created for the MACB driver dependency and > now the MACB driver is not dependent on CONFIG_DMA_ADDR_T_64BIT. > >> > But We created this patch the same as the ARM 64-bit kconfig and the > 'CONFIG_DMA_ADDR_T_64BIT' is used when the MMC driver is configured with > DMA. > >> > > >> > >> But in U-Boot there is no 64-bit address. The DMA address should be > >> under 4G. Both MACB and MMC driver should work with the 32-bit DMA > >> addresses, no? > >> > > > > We will use 64-bit addresses in the future. > > But U-Boot does not generate 64-bit addresses for DMA at present. > > PolarFire SoC GEM uses 64-bit DMA not 32-bit DMA Regards Padmarao > > Both MACB and MMC drivers work with 64-bit DMA addresses in the > PolarFire SoC. > > So I think the patch to enable 64-bit DMA in U-Boot is not necessary. > > Regards, > Bin >
Re: [PATCH v5 2/7] net: macb: Add DMA 64-bit address support for macb
Hi Bin,
On Fri, Dec 11, 2020 at 2:59 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Fri, Dec 11, 2020 at 4:49 PM Padmarao Begari
> wrote:
> >
> > Hi Bin,
> >
> > On Thu, Dec 10, 2020 at 4:08 PM Bin Meng wrote:
> >>
> >> Hi Padmarao,
> >>
> >> On Thu, Dec 10, 2020 at 6:33 PM Bin Meng wrote:
> >> >
> >> > Hi Padmarao,
> >> >
> >> > On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
> >> > wrote:
> >> > >
> >> > > Enable 32-bit or 64-bit DMA in the macb driver based on the macb
> >> > > compatible string of the device tree node.
> >> > >
> >> > > Signed-off-by: Padmarao Begari
> >> > > Reviewed-by: Anup Patel
> >> > > ---
> >> > > drivers/net/macb.c | 131
> +++--
> >> > > drivers/net/macb.h | 6 +++
> >> > > 2 files changed, 120 insertions(+), 17 deletions(-)
> >> > >
> >> > > diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> >> > > index b80a259ff7..e7c93d4747 100644
> >> > > --- a/drivers/net/macb.c
> >> > > +++ b/drivers/net/macb.c
> >> > > @@ -83,7 +83,16 @@ struct macb_dma_desc {
> >> > > u32 ctrl;
> >> > > };
> >> > >
> >> > > -#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
> >> > > +struct macb_dma_desc_64 {
> >> > > + u32 addrh;
> >> > > + u32 unused;
> >> > > +};
> >> > > +
> >> > > +#define HW_DMA_CAP_32B 0
> >> > > +#define HW_DMA_CAP_64B 1
> >> > > +
> >> > > +#define DMA_DESC_SIZE 16
> >> > > +#define DMA_DESC_BYTES(n) ((n) * DMA_DESC_SIZE)
> >> > > #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
> >> > > #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
> >> > > #define MACB_TX_DUMMY_DMA_DESC_SIZE(DMA_DESC_BYTES(1))
> >> > > @@ -133,6 +142,7 @@ struct macb_device {
> >> > > #endif
> >> > > phy_interface_t phy_interface;
> >> > > #endif
> >> > > + unsigned short hw_dma_cap;
> >> > > };
> >> > >
> >> > > struct macb_config {
> >> > > @@ -307,6 +317,24 @@ static inline void
> macb_invalidate_rx_buffer(struct macb_device *macb)
> >> > >
> >> > > #if defined(CONFIG_CMD_NET)
> >> > >
> >> > > +static struct macb_dma_desc_64 *macb_64b_desc(struct macb_dma_desc
> *desc)
> >> > > +{
> >> > > + return (struct macb_dma_desc_64 *)((void *)desc
> >> > > + + sizeof(struct macb_dma_desc));
> >> > > +}
> >> > > +
> >> > > +static void macb_set_addr(struct macb_device *macb, struct
> macb_dma_desc *desc,
> >> > > + ulong addr)
> >> > > +{
> >> > > + struct macb_dma_desc_64 *desc_64;
> >> > > +
> >> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B) {
> >> > > + desc_64 = macb_64b_desc(desc);
> >> > > + desc_64->addrh = upper_32_bits(addr);
> >> > > + }
> >> > > + desc->addr = lower_32_bits(addr);
> >> > > +}
> >> > > +
> >> > > static int _macb_send(struct macb_device *macb, const char *name,
> void *packet,
> >> > > int length)
> >> > > {
> >> > > @@ -325,8 +353,12 @@ static int _macb_send(struct macb_device
> *macb, const char *name, void *packet,
> >> > > macb->tx_head++;
> >> > > }
> >> > >
> >> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
> >> > > + tx_head = tx_head * 2;
> >> > > +
> >> > > macb->tx_ring[tx_head].ctrl = ctrl;
> >> > > - macb->tx_ring[tx_head].addr = paddr;
> >> > > + macb_set_addr(macb, >tx_ring[tx_head], paddr);
> >> > > +
> >> > > barrier();
> >> > > macb_flush_ring_desc(macb, TX);
> >> > > macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) |
> MACB_BIT(TSTART));
> >> > > @@ -363,19 +395,28 @@ static void reclaim_rx_buffers(struct
> macb_device *macb,
> >> > >unsigned int new_tail)
> >> > > {
> >> > > unsigned int i;
> >> > > + unsigned int count;
> >> > >
> >> > > i = macb->rx_tail;
> >> > >
> >> > > macb_invalidate_ring_desc(macb, RX);
> >> > > while (i > new_tail) {
> >> > > - macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
> >> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
> >> > > + count = i * 2;
> >> > > + else
> >> > > + count = i;
> >> > > + macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
> >> > > i++;
> >> > > if (i > MACB_RX_RING_SIZE)
> >> > > i = 0;
> >> > > }
> >> > >
> >> > > while (i < new_tail) {
> >> > > - macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
> >> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
> >> > > + count = i * 2;
> >> > > + else
> >> > > + count = i;
> >> > > + macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
> >> > > i++;
> >> > > }
> >> > >
> >> > > @@ -390,16 +431,25 @@ static int _macb_recv(struct
[PATCH V2] imx: Add support for i.MX8MN Beacon EmbeddedWorks devkit.
Beacon EmbeddedWorks is releasing a devkit based on the i.MX8M
Nano SoC consisting of baseboard + SOM.
The kit is based on the same design as the Beacon dev kit with
the i.MX8M Mini.
Signed-off-by: Adam Ford
---
V2: Update README file to reference newer DDR firmware
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 02d04f5a8c..0ca895815c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -773,6 +773,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mn-ddr4-evk.dtb \
imx8mq-evk.dtb \
imx8mm-beacon-kit.dtb \
+ imx8mn-beacon-kit.dtb \
imx8mq-phanbell.dtb \
imx8mp-evk.dtb \
imx8mq-pico-pi.dtb
diff --git a/arch/arm/dts/imx8mn-beacon-baseboard.dtsi
b/arch/arm/dts/imx8mn-beacon-baseboard.dtsi
new file mode 100644
index 00..49bff19a78
--- /dev/null
+++ b/arch/arm/dts/imx8mn-beacon-baseboard.dtsi
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+/ {
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "gen_led0";
+ gpios = <_1 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-1 {
+ label = "gen_led1";
+ gpios = <_1 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-2 {
+ label = "gen_led2";
+ gpios = <_1 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <_led3>;
+ label = "heartbeat";
+ gpios = < 28 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vsd_3v3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = < 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usb_otg_vbus: regulator-usb {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <_reg_usb_otg>;
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ gpio = < 29 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_espi2>;
+ cs-gpios = < 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ eeprom@0 {
+ compatible = "microchip,at25160bn", "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <500>;
+ spi-cpha;
+ spi-cpol;
+ pagesize = <32>;
+ size = <2048>;
+ address-width = <16>;
+ };
+};
+
+ {
+ clock-frequency = <40>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c4>;
+ status = "okay";
+
+ pca6416_0: gpio@20 {
+ compatible = "nxp,pcal6416";
+ reg = <0x20>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pcal6414>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pca6416_1: gpio@21 {
+ compatible = "nxp,pcal6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+_pwrkey {
+ status = "okay";
+};
+
+ { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <_uart2>;
+ status = "okay";
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_uart3>;
+ assigned-clocks = < IMX8MN_CLK_UART3>;
+ assigned-clock-parents = < IMX8MN_SYS_PLL1_80M>;
+ status = "okay";
+};
+
+ {
+ vbus-supply = <_usb_otg_vbus>;
+ disable-over-current;
+ dr_mode="otg";
+ status = "okay";
+};
+
+ {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <_usdhc2>, <_usdhc2_gpio>;
+ pinctrl-1 = <_usdhc2_100mhz>;
+ pinctrl-2 = <_usdhc2_200mhz>;
+ bus-width = <4>;
+ vmmc-supply = <_usdhc2_vmmc>;
+ status = "okay";
+};
+
+ {
+ pinctrl_espi2: espi2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK0x82
+ MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI0x82
+
Re: [PATCH v5 5/7] riscv: dts: Add device tree for Microchip Icicle Kit
Hi Bin,
On Fri, Dec 11, 2020 at 2:55 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Fri, Dec 11, 2020 at 4:32 PM Padmarao Begari
> wrote:
> >
> > Hi Bin,
> >
> > On Fri, Dec 11, 2020 at 1:31 PM Bin Meng wrote:
> >>
> >> Hi Padmarao,
> >>
> >> On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
> >> wrote:
> >> >
> >> > Add device tree for Microchip PolarFire SoC Icicle Kit.
> >> >
> >> > Signed-off-by: Padmarao Begari
> >> > Reviewed-by: Anup Patel
> >>
> >> Sorry 2 more warnings, please check below:
> >>
> >> > ---
> >> > arch/riscv/dts/Makefile | 1 +
> >> > .../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
> >> > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421
> ++
> >> > 3 files changed, 436 insertions(+)
> >> > create mode 100644
> arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> >> > create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> >> >
> >> > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> >> > index 3a6f96c67d..01331b0aa1 100644
> >> > --- a/arch/riscv/dts/Makefile
> >> > +++ b/arch/riscv/dts/Makefile
> >> > @@ -3,6 +3,7 @@
> >> > dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
> >> > dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
> >> > dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
> >> > +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) +=
> microchip-mpfs-icicle-kit.dtb
> >> >
> >> > targets += $(dtb-y)
> >> >
> >> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> >> > new file mode 100644
> >> > index 00..f60283fb6b
> >> > --- /dev/null
> >> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> >> > @@ -0,0 +1,14 @@
> >> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >> > +/*
> >> > + * Copyright (C) 2020 Microchip Technology Inc.
> >> > + * Padmarao Begari
> >> > + */
> >> > +
> >> > +/ {
> >> > + aliases {
> >> > + cpu1 =
> >> > + cpu2 =
> >> > + cpu3 =
> >> > + cpu4 =
> >> > + };
> >> > +};
> >> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> >> > new file mode 100644
> >> > index 00..f5478bf201
> >> > --- /dev/null
> >> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> >> > @@ -0,0 +1,421 @@
> >> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >> > +/* Copyright (c) 2020 Microchip Technology Inc */
> >> > +
> >> > +/dts-v1/;
> >> > +#include "dt-bindings/clock/microchip,mpfs-clock.h"
> >> > +
> >> > +/* Clock frequency (in Hz) of the rtcclk */
> >> > +#define RTCCLK_FREQ100
> >> > +
> >> > +/ {
> >> > + #address-cells = <2>;
> >> > + #size-cells = <2>;
> >> > + model = "Microchip MPFS Icicle Kit";
> >> > + compatible = "microchip,mpfs-icicle-kit";
> >> > +
> >> > + aliases {
> >> > + serial0 =
> >> > + ethernet0 =
> >> > + };
> >> > +
> >> > + chosen {
> >> > + stdout-path = "serial0";
> >> > + };
> >> > +
> >> > + cpucomplex: cpus {
> >> > + #address-cells = <1>;
> >> > + #size-cells = <0>;
> >> > + timebase-frequency = ;
> >> > + cpu0: cpu@0 {
> >> > + clocks = < CLK_CPU>;
> >> > + compatible = "sifive,e51", "sifive,rocket0",
> "riscv";
> >> > + device_type = "cpu";
> >> > + i-cache-block-size = <64>;
> >> > + i-cache-sets = <128>;
> >> > + i-cache-size = <16384>;
> >> > + reg = <0>;
> >> > + riscv,isa = "rv64imac";
> >> > + status = "disabled";
> >> > + operating-points = <
> >> > + /* kHz uV */
> >> > + 60 110
> >> > + 30 95
> >> > + 15 75
> >> > + >;
> >> > + cpu0intc: interrupt-controller {
> >> > + #interrupt-cells = <1>;
> >> > + compatible = "riscv,cpu-intc";
> >> > + interrupt-controller;
> >> > + };
> >> > + };
> >> > + cpu1: cpu@1 {
> >> > + clocks = < CLK_CPU>;
> >> > + compatible = "sifive,u54-mc",
> "sifive,rocket0", "riscv";
> >> > + d-cache-block-size = <64>;
> >> > + d-cache-sets = <64>;
> >> > + d-cache-size = <32768>;
> >> > + d-tlb-sets = <1>;
> >> > + d-tlb-size = <32>;
> >> > + device_type = "cpu";
> >> > +
Re: [PATCH 00/13] Nokia RX-51: Fix USB TTY console and enable it
Hi Pali, On 11/12/20 1:31 am, Pali Rohár wrote: > Hello Lokesh, could you please process this patch series? USB serial > console on Nokia N900 is really useful for debugging and currently in > U-Boot master code is broken. Pavel has already reviewed patches and > also CI tests passed. I am out of office from past 3 weeks and will be back on Monday. Will try to get to this series early next week. Sorry for the delayed response. Thanks and regards, Lokesh > > On Sunday 29 November 2020 17:46:05 Pali Rohár wrote: >> This patch series fix usbtty code (serial console via USB peripheral >> mode), fix underlying musb peripheral code, fix compilation of >> CONFIG_USB_DEVICE (used by usbtty), remove unused Nokia RX-51 code to >> decrease size of U-Boot binary and finally enable usbtty serial console >> for Nokia RX-51. >> >> With this patch series debugging of Nokia RX-51 can be done also via USB >> serial console. >> >> On computer this serial console is accessible via /dev/ttyACM0 device. >> >> With current implementation there is an issue in musb driver that it >> loose receiving bytes from USB bus when too many a characters are send >> over USB tty from computer. Typing on keyboard to kermit terminal >> connected to /dev/ttyACM0 is working fine. But pasting more more bytes >> to terminal cause data lost on receiving side. I do not know where is >> the issue or how to fix it (it looks like that data are lost at low >> level when reading them from msub FIFO hardware) but typing on keyboard >> is working fine. This is rather issue for sending files via x/y/z-modem >> or kermit protocol. Currently U-Boot is not able to receive any file >> via usbtty with musb driver due to this issue. >> >> Pali Rohár (13): >> serial: usbtty: Fix puts function >> usb: musb: Fix compilation of gadget code >> usb: musb: Always clear the data toggle bit when configuring ep >> usb: musb: Fix configuring FIFO for endpoints >> usb: musb: Read value of PERI_RXCSR to 16bit variable >> usb: musb: Fix transmission of bigger buffers >> usb: gadget: Do not export usbd_device_* arrays >> usb: gadget: Use dbg_ep0() macro instead of serial_printf() >> arm: omap3: Compile lowlevel_init() function only when it is used >> arm: omap3: Compile s_init() function only when it is used >> Nokia RX-51: Remove function set_muxconf_regs() >> Nokia RX-51: Move content of rx51.h to rx51.c >> Nokia RX-51: Enable usbtty serial console by default >> >> Makefile | 1 + >> arch/arm/mach-omap2/omap3/board.c | 3 + >> arch/arm/mach-omap2/omap3/lowlevel_init.S | 6 +- >> board/nokia/rx51/rx51.c | 28 +- >> board/nokia/rx51/rx51.h | 377 -- >> configs/nokia_rx51_defconfig | 6 +- >> doc/README.nokia_rx51 | 15 +- >> drivers/serial/usbtty.c | 4 +- >> drivers/usb/gadget/core.c | 38 +-- >> drivers/usb/gadget/ep0.c | 47 ++- >> drivers/usb/musb/musb_core.c | 10 +- >> drivers/usb/musb/musb_udc.c | 19 +- >> include/configs/nokia_rx51.h | 16 +- >> include/usbdevice.h | 15 - >> 14 files changed, 92 insertions(+), 493 deletions(-) >> delete mode 100644 board/nokia/rx51/rx51.h >> >> -- >> 2.20.1 >>
Re: [PATC 1/2H] board: fsl: ls2088ardb: Program GIC LPI configuration table
On 2020-12-07 07:14, Priyanka Jain wrote:
From: Nikhil Gupta
Add programming of GIC LPI configuration table:
1. Program Redistributor PROCBASER configuration table
The register name is GICR_PROPBASER.
which is common for all redistributors.
2. Program Redistributor pending table (PENDBASER), for
all the available redistributors.
3. Reserve DDR memory region used for GIC LPI configuration table.
I'm not convinced that's a good idea, but hey, why not.
Signed-off-by: Nikhil Gupta
Signed-off-by: Priyanka Jain
---
board/freescale/ls2080ardb/ls2080ardb.c | 27 -
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c
b/board/freescale/ls2080ardb/ls2080ardb.c
index c7e9c1dacf..1c54bac529 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*/
#include
#include
@@ -24,7 +24,10 @@
#include
#include
#include
+#include
+#include
+#define GIC_LPI_SIZE 0x20
Shouldn't you probe this from the HW instead of hardcoding it?
#ifdef CONFIG_FSL_QIXIS
#include "../common/qixis.h"
#include "ls2080ardb_qixis.h"
@@ -352,6 +355,21 @@ void board_quiesce_devices(void)
}
#endif
+#ifdef CONFIG_GIC_V3_ITS
+void fdt_fixup_gic_lpi_memory(void *blob, u64 gic_lpi_base)
+{
+ u32 phandle;
+ int err;
+ struct fdt_memory gic_lpi;
+
+ gic_lpi.start = gic_lpi_base;
+ gic_lpi.end = gic_lpi_base + GIC_LPI_SIZE - 1;
+ err = fdtdec_add_reserved_memory(blob, "gic-lpi", _lpi,
);
+ if (err < 0)
+ debug("failed to add reserved memory: %d\n", err);
+}
+#endif
+
#ifdef CONFIG_OF_BOARD_SETUP
void fsl_fdt_fixup_flash(void *fdt)
{
@@ -426,6 +444,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
u64 mc_memory_base = 0;
u64 mc_memory_size = 0;
u16 total_memory_banks;
+ u64 gic_lpi_base;
ft_cpu_setup(blob, bd);
@@ -445,6 +464,12 @@ int ft_board_setup(void *blob, struct bd_info *bd)
base[1] = gd->bd->bi_dram[1].start;
size[1] = gd->bd->bi_dram[1].size;
+#ifdef CONFIG_GIC_V3_ITS
+ gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE;
+ gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
+ fdt_fixup_gic_lpi_memory(blob, gic_lpi_base);
+#endif
+
#ifdef CONFIG_RESV_RAM
/* reduce size if reserved memory is within this bank */
if (gd->arch.resv_ram >= base[0] &&
M.
--
Jazz is not dead. It just smells funny...
[PATCH] fsp: Move and rename fsp_types.h file
The fsp_types.h header file contains macros for building signatures of different widths. These signature macros are architecture agnostic, and can be used in all places which use signatures in a data structure. Move and rename the fsp_types.h under the common include header. Signed-off-by: Sughosh Ganu --- Build tested for cougarcanyon2 board which builds the relevant fsp code. arch/x86/include/asm/fsp/fsp_support.h | 3 ++- .../asm/fsp/fsp_types.h => include/signature_types.h| 6 +++--- 2 files changed, 5 insertions(+), 4 deletions(-) rename arch/x86/include/asm/fsp/fsp_types.h => include/signature_types.h (94%) diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h index 29e511415c..7651a0dac0 100644 --- a/arch/x86/include/asm/fsp/fsp_support.h +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -11,10 +11,11 @@ #include #include #include -#include #include #include +#include + #define FSP_LOWMEM_BASE0x10UL #define FSP_HIGHMEM_BASE 0x1ULL #define UPD_TERMINATOR 0x55AA diff --git a/arch/x86/include/asm/fsp/fsp_types.h b/include/signature_types.h similarity index 94% rename from arch/x86/include/asm/fsp/fsp_types.h rename to include/signature_types.h index 3d5b17ecf1..9b8c0543f6 100644 --- a/arch/x86/include/asm/fsp/fsp_types.h +++ b/include/signature_types.h @@ -4,8 +4,8 @@ * Copyright (C) 2014, Bin Meng */ -#ifndef __FSP_TYPES_H__ -#define __FSP_TYPES_H__ +#ifndef __SIGNATURE_TYPES_H__ +#define __SIGNATURE_TYPES_H__ /** * Returns a 16-bit signature built from 2 ASCII characters. @@ -59,4 +59,4 @@ #define SIGNATURE_64(A, B, C, D, E, F, G, H) \ (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32)) -#endif +#endif /* __SIGNATURE_TYPES_H__ */ -- 2.17.1
Re: [PATCH v5 2/7] net: macb: Add DMA 64-bit address support for macb
Hi Padmarao,
On Fri, Dec 11, 2020 at 4:49 PM Padmarao Begari wrote:
>
> Hi Bin,
>
> On Thu, Dec 10, 2020 at 4:08 PM Bin Meng wrote:
>>
>> Hi Padmarao,
>>
>> On Thu, Dec 10, 2020 at 6:33 PM Bin Meng wrote:
>> >
>> > Hi Padmarao,
>> >
>> > On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
>> > wrote:
>> > >
>> > > Enable 32-bit or 64-bit DMA in the macb driver based on the macb
>> > > compatible string of the device tree node.
>> > >
>> > > Signed-off-by: Padmarao Begari
>> > > Reviewed-by: Anup Patel
>> > > ---
>> > > drivers/net/macb.c | 131 +++--
>> > > drivers/net/macb.h | 6 +++
>> > > 2 files changed, 120 insertions(+), 17 deletions(-)
>> > >
>> > > diff --git a/drivers/net/macb.c b/drivers/net/macb.c
>> > > index b80a259ff7..e7c93d4747 100644
>> > > --- a/drivers/net/macb.c
>> > > +++ b/drivers/net/macb.c
>> > > @@ -83,7 +83,16 @@ struct macb_dma_desc {
>> > > u32 ctrl;
>> > > };
>> > >
>> > > -#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
>> > > +struct macb_dma_desc_64 {
>> > > + u32 addrh;
>> > > + u32 unused;
>> > > +};
>> > > +
>> > > +#define HW_DMA_CAP_32B 0
>> > > +#define HW_DMA_CAP_64B 1
>> > > +
>> > > +#define DMA_DESC_SIZE 16
>> > > +#define DMA_DESC_BYTES(n) ((n) * DMA_DESC_SIZE)
>> > > #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
>> > > #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
>> > > #define MACB_TX_DUMMY_DMA_DESC_SIZE(DMA_DESC_BYTES(1))
>> > > @@ -133,6 +142,7 @@ struct macb_device {
>> > > #endif
>> > > phy_interface_t phy_interface;
>> > > #endif
>> > > + unsigned short hw_dma_cap;
>> > > };
>> > >
>> > > struct macb_config {
>> > > @@ -307,6 +317,24 @@ static inline void macb_invalidate_rx_buffer(struct
>> > > macb_device *macb)
>> > >
>> > > #if defined(CONFIG_CMD_NET)
>> > >
>> > > +static struct macb_dma_desc_64 *macb_64b_desc(struct macb_dma_desc
>> > > *desc)
>> > > +{
>> > > + return (struct macb_dma_desc_64 *)((void *)desc
>> > > + + sizeof(struct macb_dma_desc));
>> > > +}
>> > > +
>> > > +static void macb_set_addr(struct macb_device *macb, struct
>> > > macb_dma_desc *desc,
>> > > + ulong addr)
>> > > +{
>> > > + struct macb_dma_desc_64 *desc_64;
>> > > +
>> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B) {
>> > > + desc_64 = macb_64b_desc(desc);
>> > > + desc_64->addrh = upper_32_bits(addr);
>> > > + }
>> > > + desc->addr = lower_32_bits(addr);
>> > > +}
>> > > +
>> > > static int _macb_send(struct macb_device *macb, const char *name, void
>> > > *packet,
>> > > int length)
>> > > {
>> > > @@ -325,8 +353,12 @@ static int _macb_send(struct macb_device *macb,
>> > > const char *name, void *packet,
>> > > macb->tx_head++;
>> > > }
>> > >
>> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
>> > > + tx_head = tx_head * 2;
>> > > +
>> > > macb->tx_ring[tx_head].ctrl = ctrl;
>> > > - macb->tx_ring[tx_head].addr = paddr;
>> > > + macb_set_addr(macb, >tx_ring[tx_head], paddr);
>> > > +
>> > > barrier();
>> > > macb_flush_ring_desc(macb, TX);
>> > > macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) |
>> > > MACB_BIT(TSTART));
>> > > @@ -363,19 +395,28 @@ static void reclaim_rx_buffers(struct macb_device
>> > > *macb,
>> > >unsigned int new_tail)
>> > > {
>> > > unsigned int i;
>> > > + unsigned int count;
>> > >
>> > > i = macb->rx_tail;
>> > >
>> > > macb_invalidate_ring_desc(macb, RX);
>> > > while (i > new_tail) {
>> > > - macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
>> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
>> > > + count = i * 2;
>> > > + else
>> > > + count = i;
>> > > + macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
>> > > i++;
>> > > if (i > MACB_RX_RING_SIZE)
>> > > i = 0;
>> > > }
>> > >
>> > > while (i < new_tail) {
>> > > - macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
>> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
>> > > + count = i * 2;
>> > > + else
>> > > + count = i;
>> > > + macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
>> > > i++;
>> > > }
>> > >
>> > > @@ -390,16 +431,25 @@ static int _macb_recv(struct macb_device *macb,
>> > > uchar **packetp)
>> > > void *buffer;
>> > > int length;
>> > > u32 status;
>> > > + u8 flag = false;
>> > >
>> > > macb->wrapped = false;
>> > > for (;;) {
>> > >
Re: [PATCH v5 1/7] riscv: Add DMA 64-bit address support
HI Padmarao, On Fri, Dec 11, 2020 at 4:23 PM Padmarao Begari wrote: > > Hi Bin, > > On Fri, Dec 11, 2020 at 1:22 PM Bin Meng wrote: >> >> Hi Padmarao, >> >> On Fri, Dec 11, 2020 at 3:10 PM Padmarao Begari wrote: >> > >> > Hi Bin, >> > >> > On Thu, Dec 10, 2020 at 4:11 PM Bin Meng wrote: >> >> >> >> Hi Padmarao, >> >> >> >> On Thu, Dec 3, 2020 at 4:43 AM Padmarao Begari >> >> wrote: >> >> > >> >> > dma_addr_t holds any valid DMA address. If the DMA API only uses >> >> > 32/64-bit >> >> > addresses, dma_addr_t need only be 32/64 bits wide. >> >> > >> >> > Signed-off-by: Padmarao Begari >> >> > Reviewed-by: Anup Patel >> >> > --- >> >> > arch/riscv/Kconfig | 4 >> >> > arch/riscv/include/asm/types.h | 4 >> >> > 2 files changed, 8 insertions(+) >> >> > >> >> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig >> >> > index 30b05408b1..55eaee2da6 100644 >> >> > --- a/arch/riscv/Kconfig >> >> > +++ b/arch/riscv/Kconfig >> >> > @@ -152,6 +152,10 @@ config 32BIT >> >> > config 64BIT >> >> > bool >> >> > >> >> > +config DMA_ADDR_T_64BIT >> >> > + bool >> >> > + default y if 64BIT >> >> > + >> >> > config SIFIVE_CLINT >> >> > bool >> >> > depends on RISCV_MMODE || SPL_RISCV_MMODE >> >> > diff --git a/arch/riscv/include/asm/types.h >> >> > b/arch/riscv/include/asm/types.h >> >> > index 403cf9a48f..b800b2d221 100644 >> >> > --- a/arch/riscv/include/asm/types.h >> >> > +++ b/arch/riscv/include/asm/types.h >> >> > @@ -29,7 +29,11 @@ typedef unsigned short umode_t; >> >> > >> >> > #include >> >> > >> >> > +#ifdef CONFIG_DMA_ADDR_T_64BIT >> >> > +typedef u64 dma_addr_t; >> >> > +#else >> >> > typedef u32 dma_addr_t; >> >> > +#endif >> >> >> >> Why is this patch needed for U-Boot? >> >> >> > >> > Initially this patch was created for the MACB driver dependency and now >> > the MACB driver is not dependent on CONFIG_DMA_ADDR_T_64BIT. >> > But We created this patch the same as the ARM 64-bit kconfig and the >> > 'CONFIG_DMA_ADDR_T_64BIT' is used when the MMC driver is configured with >> > DMA. >> > >> >> But in U-Boot there is no 64-bit address. The DMA address should be >> under 4G. Both MACB and MMC driver should work with the 32-bit DMA >> addresses, no? >> > > We will use 64-bit addresses in the future. But U-Boot does not generate 64-bit addresses for DMA at present. > Both MACB and MMC drivers work with 64-bit DMA addresses in the PolarFire SoC. So I think the patch to enable 64-bit DMA in U-Boot is not necessary. Regards, Bin
Re: [PATCH v5 5/7] riscv: dts: Add device tree for Microchip Icicle Kit
Hi Padmarao,
On Fri, Dec 11, 2020 at 4:32 PM Padmarao Begari wrote:
>
> Hi Bin,
>
> On Fri, Dec 11, 2020 at 1:31 PM Bin Meng wrote:
>>
>> Hi Padmarao,
>>
>> On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
>> wrote:
>> >
>> > Add device tree for Microchip PolarFire SoC Icicle Kit.
>> >
>> > Signed-off-by: Padmarao Begari
>> > Reviewed-by: Anup Patel
>>
>> Sorry 2 more warnings, please check below:
>>
>> > ---
>> > arch/riscv/dts/Makefile | 1 +
>> > .../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
>> > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 ++
>> > 3 files changed, 436 insertions(+)
>> > create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
>> > create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts
>> >
>> > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
>> > index 3a6f96c67d..01331b0aa1 100644
>> > --- a/arch/riscv/dts/Makefile
>> > +++ b/arch/riscv/dts/Makefile
>> > @@ -3,6 +3,7 @@
>> > dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
>> > dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
>> > dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
>> > +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
>> >
>> > targets += $(dtb-y)
>> >
>> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
>> > b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
>> > new file mode 100644
>> > index 00..f60283fb6b
>> > --- /dev/null
>> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
>> > @@ -0,0 +1,14 @@
>> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> > +/*
>> > + * Copyright (C) 2020 Microchip Technology Inc.
>> > + * Padmarao Begari
>> > + */
>> > +
>> > +/ {
>> > + aliases {
>> > + cpu1 =
>> > + cpu2 =
>> > + cpu3 =
>> > + cpu4 =
>> > + };
>> > +};
>> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
>> > b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
>> > new file mode 100644
>> > index 00..f5478bf201
>> > --- /dev/null
>> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
>> > @@ -0,0 +1,421 @@
>> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> > +/* Copyright (c) 2020 Microchip Technology Inc */
>> > +
>> > +/dts-v1/;
>> > +#include "dt-bindings/clock/microchip,mpfs-clock.h"
>> > +
>> > +/* Clock frequency (in Hz) of the rtcclk */
>> > +#define RTCCLK_FREQ100
>> > +
>> > +/ {
>> > + #address-cells = <2>;
>> > + #size-cells = <2>;
>> > + model = "Microchip MPFS Icicle Kit";
>> > + compatible = "microchip,mpfs-icicle-kit";
>> > +
>> > + aliases {
>> > + serial0 =
>> > + ethernet0 =
>> > + };
>> > +
>> > + chosen {
>> > + stdout-path = "serial0";
>> > + };
>> > +
>> > + cpucomplex: cpus {
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>> > + timebase-frequency = ;
>> > + cpu0: cpu@0 {
>> > + clocks = < CLK_CPU>;
>> > + compatible = "sifive,e51", "sifive,rocket0",
>> > "riscv";
>> > + device_type = "cpu";
>> > + i-cache-block-size = <64>;
>> > + i-cache-sets = <128>;
>> > + i-cache-size = <16384>;
>> > + reg = <0>;
>> > + riscv,isa = "rv64imac";
>> > + status = "disabled";
>> > + operating-points = <
>> > + /* kHz uV */
>> > + 60 110
>> > + 30 95
>> > + 15 75
>> > + >;
>> > + cpu0intc: interrupt-controller {
>> > + #interrupt-cells = <1>;
>> > + compatible = "riscv,cpu-intc";
>> > + interrupt-controller;
>> > + };
>> > + };
>> > + cpu1: cpu@1 {
>> > + clocks = < CLK_CPU>;
>> > + compatible = "sifive,u54-mc", "sifive,rocket0",
>> > "riscv";
>> > + d-cache-block-size = <64>;
>> > + d-cache-sets = <64>;
>> > + d-cache-size = <32768>;
>> > + d-tlb-sets = <1>;
>> > + d-tlb-size = <32>;
>> > + device_type = "cpu";
>> > + i-cache-block-size = <64>;
>> > + i-cache-sets = <64>;
>> > + i-cache-size = <32768>;
>> > + i-tlb-sets = <1>;
>> > + i-tlb-size = <32>;
>> > + mmu-type = "riscv,sv39";
>> > +
RE: [Patch v2] armv8: dts: fsl-lx2162a: add dspi node into qds dts
> -Original Message- > From: Priyanka Jain > Sent: 2020年12月11日 16:15 > To: Qiang Zhao ; Meenakshi Aggarwal > > Cc: u-boot@lists.denx.de; Qiang Zhao > Subject: RE: [Patch v2] armv8: dts: fsl-lx2162a: add dspi node into qds dts > > >-Original Message- > >From: Qiang Zhao > >Sent: Friday, October 9, 2020 10:48 AM > >To: Priyanka Jain ; Meenakshi Aggarwal > > > >Cc: u-boot@lists.denx.de; Qiang Zhao > >Subject: [Patch v2] armv8: dts: fsl-lx2162a: add dspi node into qds dts > > > >From: Zhao Qiang > > > >Add dspi node into lx2162aqds device tree > > > >Signed-off-by: Zhao Qiang > >--- > LX2162QDS base support is now merged in fsl-qoriq tree. > https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq > > Kindly rebase this patch. Rebased Best Regards, Qiang Zhao
[Patch v3] armv8: dts: fsl-lx2162a: add dspi node into qds dts
From: Zhao Qiang
Add dspi node into lx2162aqds device tree
Signed-off-by: Zhao Qiang
---
changes for v2:
- add alias part
changes for v3:
- rebase
arch/arm/dts/fsl-lx2162a-qds.dts | 102 +++
1 file changed, 102 insertions(+)
diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts
index b165265..5eb3441 100644
--- a/arch/arm/dts/fsl-lx2162a-qds.dts
+++ b/arch/arm/dts/fsl-lx2162a-qds.dts
@@ -15,6 +15,9 @@
compatible = "fsl,lx2162aqds", "fsl,lx2160a";
aliases {
+ spi1 =
+ spi2 =
+ spi3 =
pcie@350 {
status = "disabled";
};
@@ -32,3 +35,102 @@
{
status = "disabled";
};
+
+ {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash0: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <300>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+ dflash1: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <300>;
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ };
+ dflash2: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <300>;
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ };
+};
+
+ {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash3: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <300>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+ dflash4: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <300>;
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ };
+ dflash5: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <300>;
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ };
+};
+
+ {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash6: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <300>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+ dflash7: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <300>;
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ };
+ dflash8: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <300>;
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ };
+};
--
2.7.4
RE: [PATCH] armv8: lx2162aqds: disable non existing pcie controllers
> -Original Message- > From: Priyanka Jain > Sent: Friday, December 11, 2020 1:49 PM > To: Wasim Khan ; u-boot@lists.denx.de; Priyanka Jain > (OSS) ; Varun Sethi ; > Meenakshi Aggarwal > Cc: Wasim Khan > Subject: RE: [PATCH] armv8: lx2162aqds: disable non existing pcie controllers > > >-Original Message- > >From: U-Boot On Behalf Of Wasim Khan > >Sent: Tuesday, September 29, 2020 12:09 PM > >To: u-boot@lists.denx.de; Priyanka Jain (OSS) > >; Varun Sethi ; Meenakshi > >Aggarwal > >Cc: Wasim Khan > >Subject: [PATCH] armv8: lx2162aqds: disable non existing pcie > >controllers > > > >disable non existing pcie controllers on lx2162aqds > > > >Signed-off-by: Wasim Khan > >--- > LX2162QDS base support is now merged in fsl-qoriq tree. > https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq > > Kindly rebase this patch. https://patchwork.ozlabs.org/project/uboot/patch/1607677011-15059-1-git-send-email-wasim.k...@nxp.com/ > > Regards > Priyanka
RE: [PATCH] imx: Add support for i.MX8MN Beacon EmbeddedWorks devkit.
Hello Adam, > -Original Message- > From: U-Boot On Behalf Of Adam Ford > Sent: Thursday, December 10, 2020 5:08 PM > To: u-boot@lists.denx.de > Cc: af...@beaconembedded.com; Adam Ford ; Stefano > Babic ; Fabio Estevam ; NXP i.MX U- > Boot Team > Subject: [PATCH] imx: Add support for i.MX8MN Beacon EmbeddedWorks devkit. > > > Beacon EmbeddedWorks is releasing a devkit based on the i.MX8M > Nano SoC consisting of baseboard + SOM. > > The kit is based on the same design as the Beacon dev kit with > the i.MX8M Mini. > > Signed-off-by: Adam Ford > > diff --git a/board/beacon/imx8mn/README b/board/beacon/imx8mn/README > new file mode 100644 > index 00..b1d7a19a39 > --- /dev/null > +++ b/board/beacon/imx8mn/README > @@ -0,0 +1,39 @@ > +U-Boot for the Beacon EmbeddedWorks i.MX8M Nano Devkit > + > +Quick Start > +=== > +- Build the ARM Trusted firmware binary > +- Get ddr firmware > +- Build U-Boot > +- Boot > + > +Get and Build the ARM Trusted firmware > +== > +Note: $(srctree) is U-Boot source directory > + > +$ git clone https://source.codeaurora.org/external/imx/imx-atf > +$ git checkout imx_5.4.47_2.2.0 > +$ make PLAT=imx8mn bl31 CROSS_COMPILE=aarch64-linux-gnu- > +$ cp build/imx8mm/release/bl31.bin $(srctree) > + > +Get the DDR firmware > + > +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.5.bin There is a newer version of DDR firmware available from NXP: https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin It is also aligned with imx_5.4.47_2.2.0 ATF release, so for completeness purposes I would recommend you to include the updated link into README file. Yocto meta-freescale layer is already using this firmware version for mx8m series [1], and it is operable. I believe it would be beneficial to recommend users to pull the latest version available. > +$ chmod +x firmware-imx-8.5.bin > +$ ./firmware-imx-8.5 > +$ cp firmware-imx-8.5/firmware/ddr/synopsys/lpddr4*.bin $(srctree) > + > +Build U-Boot > + > +$ make imx8mn_beacon_defconfig > +$ make flash.bin CROSS_COMPILE=aarch64-linux-gnu- > ATF_LOAD_ADDR=0x96 > + > +Burn U-Boot to microSD Card > +=== > +$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 > + > +Boot > + > +Set baseboard DIP switch: > +S17: 1100 > + > 2.25.1 Link: [1]: https://github.com/Freescale/meta-freescale/blob/master/recipes-bsp/firmware-imx/firmware-imx-8m_8.9.bb -- andrey
[PATCH v2] armv8: lx2162aqds: disable non existing pcie controllers
disable non existing pcie controllers on lx2162aqds
Signed-off-by: Wasim Khan
---
Changes in v2:
- Rebased to u-boot-fsl-qoriq
arch/arm/dts/fsl-lx2162a-qds.dts | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts
index b165265..a2592c9 100644
--- a/arch/arm/dts/fsl-lx2162a-qds.dts
+++ b/arch/arm/dts/fsl-lx2162a-qds.dts
@@ -13,22 +13,20 @@
/ {
model = "NXP Layerscape LX2162AQDS Board";
compatible = "fsl,lx2162aqds", "fsl,lx2160a";
+};
- aliases {
- pcie@350 {
- status = "disabled";
- };
+ {
+ status = "disabled";
+};
- pcie@380 {
- status = "disabled";
- };
+ {
+ status = "disabled";
+};
- pcie@390 {
- status = "disabled";
- };
- };
+ {
+ status = "disabled";
};
- {
+ {
status = "disabled";
};
--
2.7.4
Re: [PATCH v2 00/26] dm: Change the way sequence numbers are implemented
Hi Simon, Am 2020-12-11 02:31, schrieb Simon Glass: At present each device has two sequence numbers, with 'req_seq' being set up at bind time and 'seq' at probe time. The idea is that devices can 'request' a sequence number and then the conflicts are resolved when the device is probed. This makes things complicated in a few cases, since we don't really know (at bind time) what the sequence number will end up being. We want to honour the bind-time requests if at all possible, but in fact the only source of these at present is the devicetree aliases. Apart from the obvious need for sequence numbers to supports U-Boot's numbering on devices on the command line, the current scheme was designed to: - avoid calculating the sequence number until it is needed, to save execution time - allow multiple devices to obtain a particular sequence number as they are probed and removed - retain a record of the 'requested' sequence number even if it turns out that a device could not get it (to allow debugging and retrying) After some years using the current scheme it seems on balance that these goals don't have as much merit as first thought. The first point would be persuasive except that we end up reading the devicetree aliases at bind-time anyway. So the work of resolving the sequence numbers during probing is not that great. The second point hasn't really been an issue, as there is typically no contention for sequence numbers (boards tend to allocate them statically in the devicetree). Re the third point, we can often figure out what was requested by looking at aliases, and in the cases where we can't, it doesn't seem to matter much. Since we have the devicetree available at bind time, we may as well just use it, in the hope that the required processing will turn out to be useful later (i.e. the device actually gets used). In addition, it is simpler to use a single sequence number, since it avoids confusion and some extra code. This series moves U-Boot to use a single, bind-time sequence number. All uclasses assign sequence numbers to their devices, so that as soon as a device is bound, it has a sequence number. If the uclass flag DM_UC_FLAG_SEQ_ALIAS is enabled (as well as the CONFIG option), a devicetree alias provides the number. Otherwise, the next available number (after the last alias and avoiding existing devices) is used. Apart from the simplicity gains, overall these changes seem to reduce the number of tweaks and workarounds needed to get the desired behaviour. However there will certainly be some problems created, so board maintainers should test this out. This series is available at u-boot-dm/seq-working Changes in v2: - Give all devices a sequence number - Drop uclass_alloc_all_seqs() and GD_FLG_DM_NO_SEQ flag - Drop the GD_FLG_DM_NO_SEQ flag - Use the sequence number directly instead of max bus - Adjust the tests to handle the new allocation scheme - Drop the networking changes which are no-longer needed - Update for new logic - Adjust commit message - Drop pointless check for max == -1 - Adjust the tests to handle the new allocation scheme - Simplify the logic so auto_seq is positive - Update the docs to indicate all devices get a sequence number - Update the docs to explain how aliases reserve sequence numbers - Drop commit changing efi_uc_destroy() Sequence numbers looks good, but PCI still doesnt work on my board. -michael
Re: [PATCH v5 2/7] net: macb: Add DMA 64-bit address support for macb
Hi Bin,
On Thu, Dec 10, 2020 at 4:08 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Thu, Dec 10, 2020 at 6:33 PM Bin Meng wrote:
> >
> > Hi Padmarao,
> >
> > On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
> > wrote:
> > >
> > > Enable 32-bit or 64-bit DMA in the macb driver based on the macb
> > > compatible string of the device tree node.
> > >
> > > Signed-off-by: Padmarao Begari
> > > Reviewed-by: Anup Patel
> > > ---
> > > drivers/net/macb.c | 131 +++--
> > > drivers/net/macb.h | 6 +++
> > > 2 files changed, 120 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> > > index b80a259ff7..e7c93d4747 100644
> > > --- a/drivers/net/macb.c
> > > +++ b/drivers/net/macb.c
> > > @@ -83,7 +83,16 @@ struct macb_dma_desc {
> > > u32 ctrl;
> > > };
> > >
> > > -#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
> > > +struct macb_dma_desc_64 {
> > > + u32 addrh;
> > > + u32 unused;
> > > +};
> > > +
> > > +#define HW_DMA_CAP_32B 0
> > > +#define HW_DMA_CAP_64B 1
> > > +
> > > +#define DMA_DESC_SIZE 16
> > > +#define DMA_DESC_BYTES(n) ((n) * DMA_DESC_SIZE)
> > > #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
> > > #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
> > > #define MACB_TX_DUMMY_DMA_DESC_SIZE(DMA_DESC_BYTES(1))
> > > @@ -133,6 +142,7 @@ struct macb_device {
> > > #endif
> > > phy_interface_t phy_interface;
> > > #endif
> > > + unsigned short hw_dma_cap;
> > > };
> > >
> > > struct macb_config {
> > > @@ -307,6 +317,24 @@ static inline void
> macb_invalidate_rx_buffer(struct macb_device *macb)
> > >
> > > #if defined(CONFIG_CMD_NET)
> > >
> > > +static struct macb_dma_desc_64 *macb_64b_desc(struct macb_dma_desc
> *desc)
> > > +{
> > > + return (struct macb_dma_desc_64 *)((void *)desc
> > > + + sizeof(struct macb_dma_desc));
> > > +}
> > > +
> > > +static void macb_set_addr(struct macb_device *macb, struct
> macb_dma_desc *desc,
> > > + ulong addr)
> > > +{
> > > + struct macb_dma_desc_64 *desc_64;
> > > +
> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B) {
> > > + desc_64 = macb_64b_desc(desc);
> > > + desc_64->addrh = upper_32_bits(addr);
> > > + }
> > > + desc->addr = lower_32_bits(addr);
> > > +}
> > > +
> > > static int _macb_send(struct macb_device *macb, const char *name,
> void *packet,
> > > int length)
> > > {
> > > @@ -325,8 +353,12 @@ static int _macb_send(struct macb_device *macb,
> const char *name, void *packet,
> > > macb->tx_head++;
> > > }
> > >
> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
> > > + tx_head = tx_head * 2;
> > > +
> > > macb->tx_ring[tx_head].ctrl = ctrl;
> > > - macb->tx_ring[tx_head].addr = paddr;
> > > + macb_set_addr(macb, >tx_ring[tx_head], paddr);
> > > +
> > > barrier();
> > > macb_flush_ring_desc(macb, TX);
> > > macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) |
> MACB_BIT(TSTART));
> > > @@ -363,19 +395,28 @@ static void reclaim_rx_buffers(struct
> macb_device *macb,
> > >unsigned int new_tail)
> > > {
> > > unsigned int i;
> > > + unsigned int count;
> > >
> > > i = macb->rx_tail;
> > >
> > > macb_invalidate_ring_desc(macb, RX);
> > > while (i > new_tail) {
> > > - macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
> > > + count = i * 2;
> > > + else
> > > + count = i;
> > > + macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
> > > i++;
> > > if (i > MACB_RX_RING_SIZE)
> > > i = 0;
> > > }
> > >
> > > while (i < new_tail) {
> > > - macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
> > > + count = i * 2;
> > > + else
> > > + count = i;
> > > + macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
> > > i++;
> > > }
> > >
> > > @@ -390,16 +431,25 @@ static int _macb_recv(struct macb_device *macb,
> uchar **packetp)
> > > void *buffer;
> > > int length;
> > > u32 status;
> > > + u8 flag = false;
> > >
> > > macb->wrapped = false;
> > > for (;;) {
> > > macb_invalidate_ring_desc(macb, RX);
> > >
> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
> > > + next_rx_tail = next_rx_tail * 2;
> > > +
> > > if (!(macb->rx_ring[next_rx_tail].addr &
> MACB_BIT(RX_USED)))
> > >
Re: [PATCH v5 2/7] net: macb: Add DMA 64-bit address support for macb
Hi Bin,
On Thu, Dec 10, 2020 at 4:08 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Thu, Dec 10, 2020 at 6:33 PM Bin Meng wrote:
> >
> > Hi Padmarao,
> >
> > On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
> > wrote:
> > >
> > > Enable 32-bit or 64-bit DMA in the macb driver based on the macb
> > > compatible string of the device tree node.
> > >
> > > Signed-off-by: Padmarao Begari
> > > Reviewed-by: Anup Patel
> > > ---
> > > drivers/net/macb.c | 131 +++--
> > > drivers/net/macb.h | 6 +++
> > > 2 files changed, 120 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> > > index b80a259ff7..e7c93d4747 100644
> > > --- a/drivers/net/macb.c
> > > +++ b/drivers/net/macb.c
> > > @@ -83,7 +83,16 @@ struct macb_dma_desc {
> > > u32 ctrl;
> > > };
> > >
> > > -#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
> > > +struct macb_dma_desc_64 {
> > > + u32 addrh;
> > > + u32 unused;
> > > +};
> > > +
> > > +#define HW_DMA_CAP_32B 0
> > > +#define HW_DMA_CAP_64B 1
> > > +
> > > +#define DMA_DESC_SIZE 16
> > > +#define DMA_DESC_BYTES(n) ((n) * DMA_DESC_SIZE)
> > > #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
> > > #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
> > > #define MACB_TX_DUMMY_DMA_DESC_SIZE(DMA_DESC_BYTES(1))
> > > @@ -133,6 +142,7 @@ struct macb_device {
> > > #endif
> > > phy_interface_t phy_interface;
> > > #endif
> > > + unsigned short hw_dma_cap;
> > > };
> > >
> > > struct macb_config {
> > > @@ -307,6 +317,24 @@ static inline void
> macb_invalidate_rx_buffer(struct macb_device *macb)
> > >
> > > #if defined(CONFIG_CMD_NET)
> > >
> > > +static struct macb_dma_desc_64 *macb_64b_desc(struct macb_dma_desc
> *desc)
> > > +{
> > > + return (struct macb_dma_desc_64 *)((void *)desc
> > > + + sizeof(struct macb_dma_desc));
> > > +}
> > > +
> > > +static void macb_set_addr(struct macb_device *macb, struct
> macb_dma_desc *desc,
> > > + ulong addr)
> > > +{
> > > + struct macb_dma_desc_64 *desc_64;
> > > +
> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B) {
> > > + desc_64 = macb_64b_desc(desc);
> > > + desc_64->addrh = upper_32_bits(addr);
> > > + }
> > > + desc->addr = lower_32_bits(addr);
> > > +}
> > > +
> > > static int _macb_send(struct macb_device *macb, const char *name,
> void *packet,
> > > int length)
> > > {
> > > @@ -325,8 +353,12 @@ static int _macb_send(struct macb_device *macb,
> const char *name, void *packet,
> > > macb->tx_head++;
> > > }
> > >
> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
> > > + tx_head = tx_head * 2;
> > > +
> > > macb->tx_ring[tx_head].ctrl = ctrl;
> > > - macb->tx_ring[tx_head].addr = paddr;
> > > + macb_set_addr(macb, >tx_ring[tx_head], paddr);
> > > +
> > > barrier();
> > > macb_flush_ring_desc(macb, TX);
> > > macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) |
> MACB_BIT(TSTART));
> > > @@ -363,19 +395,28 @@ static void reclaim_rx_buffers(struct
> macb_device *macb,
> > >unsigned int new_tail)
> > > {
> > > unsigned int i;
> > > + unsigned int count;
> > >
> > > i = macb->rx_tail;
> > >
> > > macb_invalidate_ring_desc(macb, RX);
> > > while (i > new_tail) {
> > > - macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
> > > + count = i * 2;
> > > + else
> > > + count = i;
> > > + macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
> > > i++;
> > > if (i > MACB_RX_RING_SIZE)
> > > i = 0;
> > > }
> > >
> > > while (i < new_tail) {
> > > - macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
> > > + count = i * 2;
> > > + else
> > > + count = i;
> > > + macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
> > > i++;
> > > }
> > >
> > > @@ -390,16 +431,25 @@ static int _macb_recv(struct macb_device *macb,
> uchar **packetp)
> > > void *buffer;
> > > int length;
> > > u32 status;
> > > + u8 flag = false;
> > >
> > > macb->wrapped = false;
> > > for (;;) {
> > > macb_invalidate_ring_desc(macb, RX);
> > >
> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
> > > + next_rx_tail = next_rx_tail * 2;
> > > +
> > > if (!(macb->rx_ring[next_rx_tail].addr &
> MACB_BIT(RX_USED)))
> > >
Re: [PATCH v5 5/7] riscv: dts: Add device tree for Microchip Icicle Kit
Hi Bin,
On Fri, Dec 11, 2020 at 1:31 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
> wrote:
> >
> > Add device tree for Microchip PolarFire SoC Icicle Kit.
> >
> > Signed-off-by: Padmarao Begari
> > Reviewed-by: Anup Patel
>
> Sorry 2 more warnings, please check below:
>
> > ---
> > arch/riscv/dts/Makefile | 1 +
> > .../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
> > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 ++
> > 3 files changed, 436 insertions(+)
> > create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> > create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> >
> > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> > index 3a6f96c67d..01331b0aa1 100644
> > --- a/arch/riscv/dts/Makefile
> > +++ b/arch/riscv/dts/Makefile
> > @@ -3,6 +3,7 @@
> > dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
> > dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
> > dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
> > +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
> >
> > targets += $(dtb-y)
> >
> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> > new file mode 100644
> > index 00..f60283fb6b
> > --- /dev/null
> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> > @@ -0,0 +1,14 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2020 Microchip Technology Inc.
> > + * Padmarao Begari
> > + */
> > +
> > +/ {
> > + aliases {
> > + cpu1 =
> > + cpu2 =
> > + cpu3 =
> > + cpu4 =
> > + };
> > +};
> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > new file mode 100644
> > index 00..f5478bf201
> > --- /dev/null
> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > @@ -0,0 +1,421 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/* Copyright (c) 2020 Microchip Technology Inc */
> > +
> > +/dts-v1/;
> > +#include "dt-bindings/clock/microchip,mpfs-clock.h"
> > +
> > +/* Clock frequency (in Hz) of the rtcclk */
> > +#define RTCCLK_FREQ100
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + model = "Microchip MPFS Icicle Kit";
> > + compatible = "microchip,mpfs-icicle-kit";
> > +
> > + aliases {
> > + serial0 =
> > + ethernet0 =
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0";
> > + };
> > +
> > + cpucomplex: cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = ;
> > + cpu0: cpu@0 {
> > + clocks = < CLK_CPU>;
> > + compatible = "sifive,e51", "sifive,rocket0",
> "riscv";
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <128>;
> > + i-cache-size = <16384>;
> > + reg = <0>;
> > + riscv,isa = "rv64imac";
> > + status = "disabled";
> > + operating-points = <
> > + /* kHz uV */
> > + 60 110
> > + 30 95
> > + 15 75
> > + >;
> > + cpu0intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + cpu1: cpu@1 {
> > + clocks = < CLK_CPU>;
> > + compatible = "sifive,u54-mc", "sifive,rocket0",
> "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > + mmu-type = "riscv,sv39";
> > + reg = <1>;
> > + riscv,isa = "rv64imafdc";
> > + tlb-split;
> > + status = "okay";
> > + operating-points = <
> > +
Re: [PATCH v5 1/7] riscv: Add DMA 64-bit address support
Hi Bin, On Fri, Dec 11, 2020 at 1:22 PM Bin Meng wrote: > Hi Padmarao, > > On Fri, Dec 11, 2020 at 3:10 PM Padmarao Begari > wrote: > > > > Hi Bin, > > > > On Thu, Dec 10, 2020 at 4:11 PM Bin Meng wrote: > >> > >> Hi Padmarao, > >> > >> On Thu, Dec 3, 2020 at 4:43 AM Padmarao Begari > >> wrote: > >> > > >> > dma_addr_t holds any valid DMA address. If the DMA API only uses > 32/64-bit > >> > addresses, dma_addr_t need only be 32/64 bits wide. > >> > > >> > Signed-off-by: Padmarao Begari > >> > Reviewed-by: Anup Patel > >> > --- > >> > arch/riscv/Kconfig | 4 > >> > arch/riscv/include/asm/types.h | 4 > >> > 2 files changed, 8 insertions(+) > >> > > >> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > >> > index 30b05408b1..55eaee2da6 100644 > >> > --- a/arch/riscv/Kconfig > >> > +++ b/arch/riscv/Kconfig > >> > @@ -152,6 +152,10 @@ config 32BIT > >> > config 64BIT > >> > bool > >> > > >> > +config DMA_ADDR_T_64BIT > >> > + bool > >> > + default y if 64BIT > >> > + > >> > config SIFIVE_CLINT > >> > bool > >> > depends on RISCV_MMODE || SPL_RISCV_MMODE > >> > diff --git a/arch/riscv/include/asm/types.h > b/arch/riscv/include/asm/types.h > >> > index 403cf9a48f..b800b2d221 100644 > >> > --- a/arch/riscv/include/asm/types.h > >> > +++ b/arch/riscv/include/asm/types.h > >> > @@ -29,7 +29,11 @@ typedef unsigned short umode_t; > >> > > >> > #include > >> > > >> > +#ifdef CONFIG_DMA_ADDR_T_64BIT > >> > +typedef u64 dma_addr_t; > >> > +#else > >> > typedef u32 dma_addr_t; > >> > +#endif > >> > >> Why is this patch needed for U-Boot? > >> > > > > Initially this patch was created for the MACB driver dependency and now > the MACB driver is not dependent on CONFIG_DMA_ADDR_T_64BIT. > > But We created this patch the same as the ARM 64-bit kconfig and the > 'CONFIG_DMA_ADDR_T_64BIT' is used when the MMC driver is configured with > DMA. > > > > But in U-Boot there is no 64-bit address. The DMA address should be > under 4G. Both MACB and MMC driver should work with the 32-bit DMA > addresses, no? > > We will use 64-bit addresses in the future. Both MACB and MMC drivers work with 64-bit DMA addresses in the PolarFire SoC. Regards Padmarao > Regards, > Bin >
RE: [PATCH] armv8: lx2162aqds: disable non existing pcie controllers
>-Original Message- >From: U-Boot On Behalf Of Wasim Khan >Sent: Tuesday, September 29, 2020 12:09 PM >To: u-boot@lists.denx.de; Priyanka Jain (OSS) ; >Varun Sethi ; Meenakshi Aggarwal > >Cc: Wasim Khan >Subject: [PATCH] armv8: lx2162aqds: disable non existing pcie controllers > >disable non existing pcie controllers on lx2162aqds > >Signed-off-by: Wasim Khan >--- LX2162QDS base support is now merged in fsl-qoriq tree. https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq Kindly rebase this patch. Regards Priyanka
RE: [PATCH] configs: lx2162a: Enable OPTEE support
>-Original Message- >From: Gaurav Jain >Sent: Monday, September 28, 2020 6:22 PM >To: u-boot@lists.denx.de; Priyanka Jain >Cc: Ruchika Gupta ; Gaurav Jain > >Subject: [PATCH] configs: lx2162a: Enable OPTEE support > >From: Ruchika Gupta > >Enable support to compile OPTEE driver, access AVB TA and RPMB API's access >via RPC from OPTEE for lx2162 > >Signed-off-by: Ruchika Gupta >Signed-off-by: Gaurav Jain >--- Applied to fsl-qoriq. Awaiting upstream Thanks Priyanka
RE: configs: lx2162aqds: enable CONFIG_BOARD_EARLY_INIT_R
>-Original Message- >From: Yangbo Lu >Sent: Friday, September 11, 2020 3:57 PM >To: u-boot@lists.denx.de; Priyanka Jain >Cc: Y.b. Lu >Subject: configs: lx2162aqds: enable CONFIG_BOARD_EARLY_INIT_R > >From: Guanhua Gao > >From: Yangbo Lu > >Enable CONFIG_BOARD_EARLY_INIT_R for SDHC adapter card identification >and configuration. > >Signed-off-by: Yangbo Lu > Applied to fsl-qoriq after rebase. Awaiting upstream Thanks Priyanka
RE: [Patch v2] armv8: dts: fsl-lx2162a: add dspi node into qds dts
>-Original Message- >From: Qiang Zhao >Sent: Friday, October 9, 2020 10:48 AM >To: Priyanka Jain ; Meenakshi Aggarwal > >Cc: u-boot@lists.denx.de; Qiang Zhao >Subject: [Patch v2] armv8: dts: fsl-lx2162a: add dspi node into qds dts > >From: Zhao Qiang > >Add dspi node into lx2162aqds device tree > >Signed-off-by: Zhao Qiang >--- LX2162QDS base support is now merged in fsl-qoriq tree. https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq Kindly rebase this patch. Regards Priyanka
RE: [v2] configs: lx2162aqds: enable eMMC HS400 mode support
>-Original Message- >From: Yangbo Lu >Sent: Tuesday, October 13, 2020 11:48 AM >To: u-boot@lists.denx.de; Priyanka Jain >Cc: Y.b. Lu >Subject: [v2] configs: lx2162aqds: enable eMMC HS400 mode support > >Enable eMMC HS400 mode support on LX2162AQDS. > >Signed-off-by: Yangbo Lu >--- >Depends on >https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatchwork. >ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D199900%26state%3D*& >amp;data=02%7C01%7Cpriyanka.jain%40nxp.com%7Ca3e07e0024624535c7ff08 >d86f40e9c0%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637381671 >873431875sdata=nmMqCLpJnlugBHshyNEbwmoP%2Ft1CcNhgoFWp5jvdq >H0%3Dreserved=0 > >Changes for v2: > - Fix typo. >--- Applied to fsl-qoriq. Awaiting upstream Thanks Priyanka
RE: [PATCH] pci: layerscape: fix a dead loop issue
>-Original Message-
>From: Z.q. Hou
>Sent: Monday, October 26, 2020 9:28 AM
>To: u-boot@lists.denx.de; Priyanka Jain
>Cc: Wasim Khan ; Z.q. Hou
>Subject: [PATCH] pci: layerscape: fix a dead loop issue
>
>From: Hou Zhiqiang
>
>The commit 8ec619f8fd84 added the PCIe EP nodes fixup of LX2160A, but it
>didn't update the condition value when there isn't a property 'apio-wins'.
>
>Fixes: 8ec619f8fd84 ("pci: layerscape: Fixup PCIe EP mode DT nodes for
>LX2160A rev2")
>Signed-off-by: Hou Zhiqiang
>---
Applied to fsl-qoriq after fixing checkpatch errors/warnings.
Please run checkpatch test and fix warnings/errors before submitting the patch
next time.
Awaiting upstream.
Thanks
Priyanka
RE: [PATCH] board/freescale/common: fix a bug that failed to read/write eeprom on ls1021atsn
>-Original Message- >From: Biwen Li >Sent: Monday, October 26, 2020 12:44 PM >To: Priyanka Jain >Cc: Jiafei Pan ; u-boot@lists.denx.de; Biwen Li > >Subject: [PATCH] board/freescale/common: fix a bug that failed to read/write >eeprom on ls1021atsn > >From: Biwen Li > >Fix a bug that failed to read/write eeprom on ls1021atsn > >Signed-off-by: Biwen Li >--- Applied to fsl-qoriq. Awaiting upstream Thanks Priyanka
RE: [v2] include/configs: ls1012aqds: add default environment variable
>-Original Message- >From: Biwen Li >Sent: Monday, October 26, 2020 2:23 PM >To: Priyanka Jain >Cc: Jiafei Pan ; u-boot@lists.denx.de; Biwen Li > >Subject: [v2] include/configs: ls1012aqds: add default environment variable > >From: Biwen Li > >This adds default environment variable for ls1012aqds > >Signed-off-by: Biwen Li >--- Applied to fsl-qoriq. Awaiting upstream Thanks Priyanka
RE: [PATCH 1/1] board: freescale: vid.c: Initialize variable 'i2caddress'
>-Original Message- >From: Priyanka Singh >Sent: Tuesday, October 27, 2020 3:50 PM >To: u-boot@lists.denx.de >Cc: Priyanka Jain ; Priyanka Singh > >Subject: [PATCH 1/1] board: freescale: vid.c: Initialize variable 'i2caddress' > >Initialize variable 'i2caddress' in adjust_vdd() to zero > >Signed-off-by: Priyanka Singh >--- Applied to fsl-qoriq. Awaiting upstream Thanks Priyanka
RE: [PATCH 1/2] armv8: ls1043/ls1046aqds: add support for all RGMII modes
>-Original Message- >From: Madalin Bucur >Sent: Wednesday, November 4, 2020 6:39 PM >To: s...@chromium.org; u-boot@lists.denx.de >Cc: Priyanka Jain ; Shengzhou Liu >; masahi...@kernel.org; Madalin Bucur (OSS) > >Subject: [PATCH 1/2] armv8: ls1043/ls1046aqds: add support for all RGMII modes > >Make sure all RGMII internal delay modes are covered. > >Signed-off-by: Madalin Bucur >--- Applied to fsl-qoriq. Awaiting upstream Thanks Priyanka
RE: [PATCH 1/1] layerscape: fdt.c: Check for NULL return value from fdt_getprop()
>-Original Message- >From: Priyanka Singh >Sent: Monday, November 2, 2020 11:39 AM >To: u-boot@lists.denx.de >Cc: Priyanka Jain ; Priyanka Singh > >Subject: [PATCH 1/1] layerscape: fdt.c: Check for NULL return value from >fdt_getprop() > >Check for NULL return value from fdt_getprop() in fdt_fixup_remove_jr() > >Signed-off-by: Priyanka Singh >--- Applied to fsl-qoriq after fixing checkpatch errors/warnings. Please run checkpatch test and fix warnings/errors before submitting the patch next time. Awaiting upstream. Thanks Priyanka
RE: [PATCH 2/2] lx2160a: Fix address for secure boot headers
>-Original Message- >From: Manish Tomar >Sent: Thursday, November 5, 2020 2:09 PM >To: u-boot@lists.denx.de >Cc: Priyanka Jain ; Manish Tomar > >Subject: [PATCH 2/2] lx2160a: Fix address for secure boot headers > >Update kernel_size_sd variable with correct value for lx2160a. > >Signed-off-by: Manish Tomar >--- Series applied to fsl-qoriq. Awaiting upstream Thanks Priyanka
RE: [v3] net: pfe_eth: read PFE ESBC header flash with spi_flash_read API
>-Original Message- >From: Biwen Li >Sent: Thursday, November 5, 2020 4:58 PM >To: Priyanka Jain ; Kuldeep Singh > >Cc: Jiafei Pan ; u-boot@lists.denx.de; Xiaobo Xie >; Biwen Li >Subject: [v3] net: pfe_eth: read PFE ESBC header flash with spi_flash_read >API > >From: Biwen Li > >Read PFE ESBC header flash with spi_flash_read API >- logs as follows, > Net: SF: Detected s25fs512s with page size 256 Bytes, erase size 256 > KiB, total 64 MiB > "Synchronous Abort" handler, esr 0x96000210 > elr: 8206db44 lr : 82004ea0 (reloc) > elr: b7ba6b44 lr : b7b3dea0 > x0 : b79407e8 x1 : 4064 > x2 : 0050 x3 : > x4 : 000a x5 : 0050 > x6 : 0366 x7 : b7942308 > x8 : b76407c0 x9 : 0008 > x10: 0044 x11: b7634d1c > x12: 004f x13: 0044 > x14: b7634d98 x15: b76407c0 > x16: x17: > x18: b7636dd8 x19: > x20: b79407d0 x21: b79407e8 > x22: 4064 x23: b7634e58 > x24: x25: 0380 > x26: b7bdd000 x27: > x28: x29: b7634d10 > > Code: d283 eb03005f 54000101 d65f03c0 (f8636826) > Resetting CPU ... > >Signed-off-by: Biwen Li >--- Applied to fsl-qoriq. Awaiting upstream Thanks Priyanka
