[RFC] efi_loader: improve firmware capsule authentication
Heinrich,
I'm currently thinking of improving capsule authentication
that Sughosh has made, particularly around mkeficapsule command:
1) Add a signing feature to the command
This will allow us to create a *signed* capsule file solely
with mkeficapsule. We will no longer rely on EDK2's script.
2) Delete "-K" and "-D" option
Specifically, revert 322c813f4bec ("mkeficapsule: Add support
for embedding public key in a dtb")
As I said, this feature doesn't have anything to do with
creating a capsule file. Above all, we can do the same thing
with the existing commands (dtc and fdtoverlay).
3) Add pytest for capsule authentication with sandbox
Now I have done all of them above although some cleanup work is
still needed. I think that (2) should be done in 2021.04.
I plan to send patches for 1-3 (and maybe 5 and 7 below) if you agree.
Other concerns:
4) Documentation
Currently, "doc/board/emulation/qemu_capsule_update.rst" is
the only document about the usage of UEFI capsule on U-Boot.
Unfortunately, it contains some errors and more importantly,
most of the content are generic, not qemu-specific.
5) Certificate (public key) in dtb
That's fine, but again "board/emulation/common/qemu_capsule.c"
is naturally generic. It should be available for other platforms
with a new Kconfig option.
# IMHO, I don't understand why the data in dtb needs be in
efi-signature-list structure. A single key (cert) would be enough.
6) "capsule_authentication_enabled"
I think that we have agreed with deleting this variable.
But I don't see any patch.
Moreover, capsule authentication must be enforced only
if the attribute, IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED,
is set. But there is no code to check the flag.
7) Pytest is broken
Due to your and Ilias' recent patches, existing pytests for
secure boot as well as capsule update are now broken.
I'm not sure why you have not yet noticed.
Presumably, Travis CI now skips those tests?
If I have some time in the future, I will address them.
But Sughosh can do as well.
-Takahiro Akashi
Re: [PATCH v7 0/8] Add FU740 chip and HiFive Unmatched board support
On Thu, 22 Apr 2021 20:40:43 PDT (-0700), Palmer Dabbelt wrote: On Thu, 22 Apr 2021 02:11:51 PDT (-0700), green@sifive.com wrote: This patch set is to add SiFive fu740 chip and HiFive Unmatched board support. Patches are split into several parts: - [PATCH v7 1/8] support for fu740 cpu - [PATCH v7 2/8] support for fu740 clk driver - [PATCH v7 3/8] rename and support for fu740 ram driver - [PATCH v7 4/8] add pcie driver - [PATCH v7 5/8] dts for SiFive fu740 - [PATCH v7 6/8] dts for SiFive Unmatched board - [PATCH v7 7/8] add Unmatched board support - [PATCH v7 8/8] add fu740 support to macb driver I've got a bunch of versions of this in my inbox, but I always have an arbitrary subset of the patches. This generally LGTM, but it's kind of hard to figure out what goes where when patch sets are split between trees like this. IMO the drivers don't need to be in my tree for the DTS files to get merged, we just need the bindings to be agreed upon. Can you send a version of this with just the patches that haven't otherwise been merged and are relevant for the RISC-V tree? Ah, sorry, I'm lost here -- I thought this was a Linux patch set. That probably explains why I can't follow the thread... ;) Description - For fu740 cpu support, reuse most of fu540 cpu. - For prci driver, add one abstract layer to separate fu540 and fu740. Move orignal fu540 code to separate files. - For pcie driver, it depends on gpio, prci, clk and reset drivers to do init works. Also based on pcie_dw_common.c - Align with Linux DT file. Tests and patch checks - Able to boot both unmatched and unleashed boards. - PCIe tests . M.2 NVMe SSD . e1000 compatibale ethernet adapter (ping) . pci-to-usb adapter(usb mass storage) - checkpatch is performed. To keep code derived from other boards the same, ignore some warnings/errors in [PATCH 7/8]. Changlogs - V7 . Rebase to latest master branch . Moved dts for fu740 patch [v6 1/7] to [v7 5/8] and seperate dts of Unmatched board from [v6 6/7] into [v7 6/8] . Applied PCIe refactoring patch to base on the common code in pcie_dw_common.c - V6 . Remove redundant DT string for 1.2GHz CPU clock and squash to [1/7] - V5 . Fix unleashed build error in patch [6/8] . Append one more set for 1.2GHz CPU speed . Add "#include " back to sifive_ddr.c . Add Reviewed-by to [4/8] and [7/8] - V4 . fixed incorrect file name in ./board/sifive/unmatched/Makefile . fixed link in doc/board/sifive/index.rst, passed 'make htmldocs' - V3 . Rebase to unleashed rename v2 patch . Rename doc/board/sifive/unmatched.rst board/sifive/unmatched/unmatched.c . Fix tail whitespace . Add 'git mv' info to ram driver and merge patch back to one . Add comment to macb driver for PLL hardware quirk . Add reviewed-by to patch [6/7] . Add 'gpio-poweroff' node for upcoming opensbi integration - V2 . Rebase to unleashed rename patch . remove unnessaary fu540 changes . split ram driver patch into 2 to keep 'git mv' info . use a shorter name for unmatched support . Remove redundant temperature-sensor in DT . Remove unnecessary USB EHCI & OHCI from defconfig . Revised fu740 doc . Fixed year of copyright . Add reviewed-by received in v1 patch David Abdurachmanov (1): drivers: net: macb: add fu740 support Green Wan (7): riscv: cpu: fu740: Add support for cpu fu740 drivers: clk: add fu740 support drivers: ram: sifive: rename fu540_ddr and add fu740 support drivers: pci: add pcie support for fu740 riscv: dts: add fu740 support riscv: dts: add SiFive Unmatched board support board: sifive: add HiFive Unmatched board support arch/riscv/Kconfig|5 + arch/riscv/cpu/fu740/Kconfig | 37 + arch/riscv/cpu/fu740/Makefile | 12 + arch/riscv/cpu/fu740/cache.c | 55 + arch/riscv/cpu/fu740/cpu.c| 22 + arch/riscv/cpu/fu740/dram.c | 38 + arch/riscv/cpu/fu740/spl.c| 23 + arch/riscv/dts/Makefile |1 + arch/riscv/dts/fu740-c000-u-boot.dtsi | 105 ++ arch/riscv/dts/fu740-c000.dtsi| 329 .../dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489 + .../dts/hifive-unmatched-a00-u-boot.dtsi | 40 + arch/riscv/dts/hifive-unmatched-a00.dts | 259 +++ arch/riscv/include/asm/arch-fu740/cache.h | 14 + arch/riscv/include/asm/arch-fu740/clk.h | 14 + arch/riscv/include/asm/arch-fu740/gpio.h | 38 + arch/riscv/include/asm/arch-fu740/reset.h | 13 + arch/riscv/include/asm/arch-fu740/spl.h | 14 + arch/riscv/lib/sifive_clint.c |1 - board/sifive/unleashed/Kconfig|1 + board/sifive/unmatched/Kconfig| 50 +
Re: [PATCH v7 0/8] Add FU740 chip and HiFive Unmatched board support
On Thu, 22 Apr 2021 02:11:51 PDT (-0700), green@sifive.com wrote: This patch set is to add SiFive fu740 chip and HiFive Unmatched board support. Patches are split into several parts: - [PATCH v7 1/8] support for fu740 cpu - [PATCH v7 2/8] support for fu740 clk driver - [PATCH v7 3/8] rename and support for fu740 ram driver - [PATCH v7 4/8] add pcie driver - [PATCH v7 5/8] dts for SiFive fu740 - [PATCH v7 6/8] dts for SiFive Unmatched board - [PATCH v7 7/8] add Unmatched board support - [PATCH v7 8/8] add fu740 support to macb driver I've got a bunch of versions of this in my inbox, but I always have an arbitrary subset of the patches. This generally LGTM, but it's kind of hard to figure out what goes where when patch sets are split between trees like this. IMO the drivers don't need to be in my tree for the DTS files to get merged, we just need the bindings to be agreed upon. Can you send a version of this with just the patches that haven't otherwise been merged and are relevant for the RISC-V tree? Description - For fu740 cpu support, reuse most of fu540 cpu. - For prci driver, add one abstract layer to separate fu540 and fu740. Move orignal fu540 code to separate files. - For pcie driver, it depends on gpio, prci, clk and reset drivers to do init works. Also based on pcie_dw_common.c - Align with Linux DT file. Tests and patch checks - Able to boot both unmatched and unleashed boards. - PCIe tests . M.2 NVMe SSD . e1000 compatibale ethernet adapter (ping) . pci-to-usb adapter(usb mass storage) - checkpatch is performed. To keep code derived from other boards the same, ignore some warnings/errors in [PATCH 7/8]. Changlogs - V7 . Rebase to latest master branch . Moved dts for fu740 patch [v6 1/7] to [v7 5/8] and seperate dts of Unmatched board from [v6 6/7] into [v7 6/8] . Applied PCIe refactoring patch to base on the common code in pcie_dw_common.c - V6 . Remove redundant DT string for 1.2GHz CPU clock and squash to [1/7] - V5 . Fix unleashed build error in patch [6/8] . Append one more set for 1.2GHz CPU speed . Add "#include " back to sifive_ddr.c . Add Reviewed-by to [4/8] and [7/8] - V4 . fixed incorrect file name in ./board/sifive/unmatched/Makefile . fixed link in doc/board/sifive/index.rst, passed 'make htmldocs' - V3 . Rebase to unleashed rename v2 patch . Rename doc/board/sifive/unmatched.rst board/sifive/unmatched/unmatched.c . Fix tail whitespace . Add 'git mv' info to ram driver and merge patch back to one . Add comment to macb driver for PLL hardware quirk . Add reviewed-by to patch [6/7] . Add 'gpio-poweroff' node for upcoming opensbi integration - V2 . Rebase to unleashed rename patch . remove unnessaary fu540 changes . split ram driver patch into 2 to keep 'git mv' info . use a shorter name for unmatched support . Remove redundant temperature-sensor in DT . Remove unnecessary USB EHCI & OHCI from defconfig . Revised fu740 doc . Fixed year of copyright . Add reviewed-by received in v1 patch David Abdurachmanov (1): drivers: net: macb: add fu740 support Green Wan (7): riscv: cpu: fu740: Add support for cpu fu740 drivers: clk: add fu740 support drivers: ram: sifive: rename fu540_ddr and add fu740 support drivers: pci: add pcie support for fu740 riscv: dts: add fu740 support riscv: dts: add SiFive Unmatched board support board: sifive: add HiFive Unmatched board support arch/riscv/Kconfig|5 + arch/riscv/cpu/fu740/Kconfig | 37 + arch/riscv/cpu/fu740/Makefile | 12 + arch/riscv/cpu/fu740/cache.c | 55 + arch/riscv/cpu/fu740/cpu.c| 22 + arch/riscv/cpu/fu740/dram.c | 38 + arch/riscv/cpu/fu740/spl.c| 23 + arch/riscv/dts/Makefile |1 + arch/riscv/dts/fu740-c000-u-boot.dtsi | 105 ++ arch/riscv/dts/fu740-c000.dtsi| 329 .../dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489 + .../dts/hifive-unmatched-a00-u-boot.dtsi | 40 + arch/riscv/dts/hifive-unmatched-a00.dts | 259 +++ arch/riscv/include/asm/arch-fu740/cache.h | 14 + arch/riscv/include/asm/arch-fu740/clk.h | 14 + arch/riscv/include/asm/arch-fu740/gpio.h | 38 + arch/riscv/include/asm/arch-fu740/reset.h | 13 + arch/riscv/include/asm/arch-fu740/spl.h | 14 + arch/riscv/lib/sifive_clint.c |1 - board/sifive/unleashed/Kconfig|1 + board/sifive/unmatched/Kconfig| 50 + board/sifive/unmatched/MAINTAINERS|9 + board/sifive/unmatched/Makefile |9 + board/sifive/unmatched/spl.c | 85 + board/sifive/unmatched/unmatched.c
Re: [PATCH] smbios: Fix calculating BIOS Release Date
Hi Pali, On Fri, Apr 23, 2021 at 12:10 AM Pali Rohár wrote: > > BIOS Release Date must be in format mm/dd/ and must be release date. > U-Boot currently sets BIOS Release Date from U_BOOT_DMI_DATE macro which is > generated from current build timestamp. > > Fix this issue by setting U_BOOT_DMI_DATE macro to U-Boot version which is > better approximation of U-Boot release date than current build timestamp. > Current U-Boot versioning is in format .mm so as a day choose 01. > > Some operating systems are using BIOS Release Date for detecting when was > SMBIOS table filled or if it could support some feature (e.g. BIOS from > 1990 cannot support features invented in 2000). So this change also ensures > that recompiling U-Boot from same sources but in different year does not > change behavior of some operating systems. > > Macro U_BOOT_DMI_DATE is not used in other file than lib/smbios.c > so remove it from global autogenerated files and also from Makefile. > > Signed-off-by: Pali Rohár > --- > Makefile| 2 -- > doc/develop/version.rst | 1 - > lib/smbios.c| 23 +++ > 3 files changed, 23 insertions(+), 3 deletions(-) > With this change the U-Boot date is only the release date, so one cannot tell exact BIOS date on which U-Boot was built from. Regards, Bin
Re: [PATCH] atcspi200: Add timeout mechanism in spi_xfer()
> From: Dylan Dai-Rong Jhong(鍾岱融) > Sent: Thursday, April 01, 2021 4:49 PM > To: ja...@amarulasolutions.com; u-boot@lists.denx.de > Cc: Rick Jian-Zhi Chen(陳建志) ; Ruinland Chuan-Tzu Tsa(蔡傳資) > ; Alan Quey-Liang Kao(高魁良) ; > Leo Yu-Chi Liang(梁育齊) ; x57109...@gmail.com; Dylan > Dai-Rong Jhong(鍾岱融) > Subject: [PATCH] atcspi200: Add timeout mechanism in spi_xfer() > > Adding timeout mechanism to avoid spi driver from stucking in the while loop > in __atcspi200_spi_xfer(). > > Signed-off-by: Dylan Jhong > --- > drivers/spi/atcspi200_spi.c | 10 -- > 1 file changed, 8 insertions(+), 2 deletions(-) Reviewed-by: Rick Chen
Re: [PATCH v4 2/6] lib: ecdsa: Add skeleton to implement ecdsa verification in u-boot
On Fri, Apr 23, 2021 at 11:55:57AM +1200, Simon Glass wrote: > Hi Alex, > > On Thu, 22 Apr 2021 at 07:30, Alex G. wrote: > > > > On 4/21/21 2:15 AM, Simon Glass wrote: > > > Hi Alexandru, > > > > > > On Fri, 16 Apr 2021 at 08:07, Alexandru Gagniuc > > > wrote: > > >> > > >> Prepare the source tree for accepting implementations of the ECDSA > > >> algorithm. This patch deals with the boring aspects of Makefiles and > > >> Kconfig files. > > >> > > >> Signed-off-by: Alexandru Gagniuc > > >> --- > > >> include/image.h | 10 +- > > >> include/u-boot/rsa.h | 2 +- > > >> lib/Kconfig | 1 + > > >> lib/Makefile | 1 + > > >> lib/ecdsa/Kconfig| 23 +++ > > >> lib/ecdsa/Makefile | 1 + > > >> lib/ecdsa/ecdsa-verify.c | 13 + > > >> 7 files changed, 45 insertions(+), 6 deletions(-) > > >> create mode 100644 lib/ecdsa/Kconfig > > >> create mode 100644 lib/ecdsa/Makefile > > >> create mode 100644 lib/ecdsa/ecdsa-verify.c > > > > > > Reviewed-by: Simon Glass > > > > > > nit below > > > > > >> > > >> diff --git a/include/image.h b/include/image.h > > >> index 3ff3c035a7..9b95f6783b 100644 > > >> --- a/include/image.h > > >> +++ b/include/image.h > > >> @@ -1224,20 +1224,20 @@ int calculate_hash(const void *data, int > > >> data_len, const char *algo, > > >> #if defined(USE_HOSTCC) > > >> # if defined(CONFIG_FIT_SIGNATURE) > > >> # define IMAGE_ENABLE_SIGN1 > > >> -# define IMAGE_ENABLE_VERIFY 1 > > >> +# define IMAGE_ENABLE_VERIFY_RSA 1 > > >> # define IMAGE_ENABLE_VERIFY_ECDSA1 > > >> # define FIT_IMAGE_ENABLE_VERIFY 1 > > >> # include > > >> # else > > >> # define IMAGE_ENABLE_SIGN0 > > >> -# define IMAGE_ENABLE_VERIFY 0 > > >> +# define IMAGE_ENABLE_VERIFY_RSA 0 > > >> # define IMAGE_ENABLE_VERIFY_ECDSA 0 > > >> # define FIT_IMAGE_ENABLE_VERIFY 0 > > >> # endif > > >> #else > > >> # define IMAGE_ENABLE_SIGN 0 > > >> -# define IMAGE_ENABLE_VERIFY CONFIG_IS_ENABLED(RSA_VERIFY) > > >> -# define IMAGE_ENABLE_VERIFY_ECDSA 0 > > >> +# define IMAGE_ENABLE_VERIFY_RSA CONFIG_IS_ENABLED(RSA_VERIFY) > > >> +# define IMAGE_ENABLE_VERIFY_ECDSA CONFIG_IS_ENABLED(ECDSA_VERIFY) > > > > > > Since we are using Kconfig now, can we drop this IMAGE_... stuff and > > > just use CONFIG_IS_ENABLED() in the code? > > > > CONFIG_IS_ENABLED() doesn't work for host tools. > > I wonder if that and IS_ENABLED() can be fixed? Not super easily? Some sort of seeing about cleaning up the code we share with userspace would be nice, yes. But it should also probably means that for the user side of things we always enable a bunch of stuff so that in the end we end up with (nearly) target-agnostic tools. -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 09/13] net: synquacer: Add netsec driver
On Sat, Apr 17, 2021 at 2:38 AM Masami Hiramatsu wrote: > > From: Jassi Brar > > Add SynQuacer's NETSEC GbE controller driver. > Since this driver will load the firmware from SPI NOR flash, > this depends on CONFIG_SYNQUACER_SPI=y. > > Signed-off-by: Jassi Brar > --- > drivers/net/Kconfig |8 > drivers/net/Makefile |1 > drivers/net/sni_netsec.c | 1134 > ++ > 3 files changed, 1143 insertions(+) > create mode 100644 drivers/net/sni_netsec.c > > diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig > index 0e84c22b50..e7c6814c31 100644 > --- a/drivers/net/Kconfig > +++ b/drivers/net/Kconfig > @@ -649,6 +649,14 @@ config SNI_AVE > This driver implements support for the Socionext AVE Ethernet > controller, as found on the Socionext UniPhier family. > > +config SNI_NETSEC > + bool "Socionext NETSEC Ethernet support" > + depends on DM_ETH && SYNQUACER_SPI > + select PHYLIB > + help > + This driver implements support for the Socionext SynQuacer NETSEC > + ethernet controller, as found on the Socionext SynQuacer family. > + > source "drivers/net/mscc_eswitch/Kconfig" > > config ETHER_ON_FEC1 > diff --git a/drivers/net/Makefile b/drivers/net/Makefile > index a19511aaa7..30e1c9baab 100644 > --- a/drivers/net/Makefile > +++ b/drivers/net/Makefile > @@ -86,6 +86,7 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o > obj-$(CONFIG_FSL_PFE) += pfe_eth/ > obj-y += qe/ > obj-$(CONFIG_SNI_AVE) += sni_ave.o > +obj-$(CONFIG_SNI_NETSEC) += sni_netsec.o > obj-y += ti/ > obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o > obj-y += mscc_eswitch/ > diff --git a/drivers/net/sni_netsec.c b/drivers/net/sni_netsec.c > new file mode 100644 > index 00..a9ebf6af9c > --- /dev/null > +++ b/drivers/net/sni_netsec.c > @@ -0,0 +1,1134 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/** > + * netsec.c - Socionext Synquacer Netsec driver > + * Copyright 2021 Linaro Ltd. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define NETSEC_REG_SOFT_RST0x104 > +#define NETSEC_REG_COM_INIT0x120 > + > +#define NETSEC_REG_TOP_STATUS 0x200 > +#define NETSEC_IRQ_RX BIT(1) > +#define NETSEC_IRQ_TX BIT(0) > + > +#define NETSEC_REG_TOP_INTEN 0x204 > +#define NETSEC_REG_INTEN_SET 0x234 > +#define NETSEC_REG_INTEN_CLR 0x238 > + > +#define NETSEC_REG_NRM_TX_STATUS 0x400 > +#define NETSEC_REG_NRM_TX_INTEN0x404 > +#define NETSEC_REG_NRM_TX_INTEN_SET0x428 > +#define NETSEC_REG_NRM_TX_INTEN_CLR0x42c > +#define NRM_TX_ST_NTOWNR BIT(17) > +#define NRM_TX_ST_TR_ERR BIT(16) > +#define NRM_TX_ST_TXDONE BIT(15) > +#define NRM_TX_ST_TMREXP BIT(14) > + > +#define NETSEC_REG_NRM_RX_STATUS 0x440 > +#define NETSEC_REG_NRM_RX_INTEN0x444 > +#define NETSEC_REG_NRM_RX_INTEN_SET0x468 > +#define NETSEC_REG_NRM_RX_INTEN_CLR0x46c > +#define NRM_RX_ST_RC_ERR BIT(16) > +#define NRM_RX_ST_PKTCNT BIT(15) > +#define NRM_RX_ST_TMREXP BIT(14) > + > +#define NETSEC_REG_PKT_CMD_BUF 0xd0 > + > +#define NETSEC_REG_CLK_EN 0x100 > + > +#define NETSEC_REG_PKT_CTRL0x140 > + > +#define NETSEC_REG_DMA_TMR_CTRL0x20c > +#define NETSEC_REG_F_TAIKI_MC_VER 0x22c > +#define NETSEC_REG_F_TAIKI_VER 0x230 > +#define NETSEC_REG_DMA_HM_CTRL 0x214 > +#define NETSEC_REG_DMA_MH_CTRL 0x220 > +#define NETSEC_REG_ADDR_DIS_CORE 0x218 > +#define NETSEC_REG_DMAC_HM_CMD_BUF 0x210 > +#define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c > + > +#define NETSEC_REG_NRM_TX_PKTCNT 0x410 > + > +#define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414 > +#define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT0x418 > + > +#define NETSEC_REG_NRM_TX_TMR 0x41c > + > +#define NETSEC_REG_NRM_RX_PKTCNT 0x454 > +#define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458 > +#define NETSEC_REG_NRM_TX_TXINT_TMR0x420 > +#define NETSEC_REG_NRM_RX_RXINT_TMR0x460 > + > +#define NETSEC_REG_NRM_RX_TMR 0x45c > + > +#define NETSEC_REG_NRM_TX_DESC_START_UP0x434 > +#define NETSEC_REG_NRM_TX_DESC_START_LW0x408 > +#define NETSEC_REG_NRM_RX_DESC_START_UP0x474 > +#define NETSEC_REG_NRM_RX_DESC_START_LW0x448 > + > +#define NETSEC_REG_NRM_TX_CONFIG 0x430 > +#define
Re: [PATCH 2/8] net: designware: meson8b: add g12a compatible
On Wed, Apr 21, 2021 at 12:18 PM Neil Armstrong wrote:
>
> Add support for the Meson G12A dwmac glue compatible needed after Linux 5.12
> sync.
>
> Signed-off-by: Neil Armstrong
> ---
> drivers/net/dwmac_meson8b.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/net/dwmac_meson8b.c b/drivers/net/dwmac_meson8b.c
> index c0b6ef4994..069bf1724d 100644
> --- a/drivers/net/dwmac_meson8b.c
> +++ b/drivers/net/dwmac_meson8b.c
> @@ -133,6 +133,7 @@ static int dwmac_meson8b_probe(struct udevice *dev)
>
> static const struct udevice_id dwmac_meson8b_ids[] = {
> { .compatible = "amlogic,meson-gxbb-dwmac", .data =
> (ulong)dwmac_setup_gx },
> + { .compatible = "amlogic,meson-g12a-dwmac", .data =
> (ulong)dwmac_setup_axg },
> { .compatible = "amlogic,meson-axg-dwmac", .data =
> (ulong)dwmac_setup_axg },
> { }
> };
> --
> 2.25.1
>
Reviewed-by: Ramon Fried
Re: [PATCH] net: designware: fix PHY reset with DM_MDIO
On Wed, Apr 21, 2021 at 11:58 AM Neil Armstrong wrote:
>
> The dw_eth_pdata is not accessible from the mdio device, it gets the mdio bus
> plat
> leading to random sleeps (-10174464 on Odroid-HC4).
>
> This moves the dw_mdio_reset function to a common one taking the ethernet
> device as parameter and use it from the dw_mdio_reset and dm_mdio variant
> functions.
>
> Fixes: 5160b4567c net: designware: add DM_MDIO support
> Reported-by: Mark Kettenis
> Signed-off-by: Neil Armstrong
> ---
> drivers/net/designware.c | 15 +++
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/net/designware.c b/drivers/net/designware.c
> index b8ba00b7c0..5d92257e74 100644
> --- a/drivers/net/designware.c
> +++ b/drivers/net/designware.c
> @@ -91,9 +91,8 @@ static int dw_mdio_write(struct mii_dev *bus, int addr, int
> devad, int reg,
> }
>
> #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
> -static int dw_mdio_reset(struct mii_dev *bus)
> +static int __dw_mdio_reset(struct udevice *dev)
> {
> - struct udevice *dev = bus->priv;
> struct dw_eth_dev *priv = dev_get_priv(dev);
> struct dw_eth_pdata *pdata = dev_get_plat(dev);
> int ret;
> @@ -122,6 +121,13 @@ static int dw_mdio_reset(struct mii_dev *bus)
>
> return 0;
> }
> +
> +static int dw_mdio_reset(struct mii_dev *bus)
> +{
> + struct udevice *dev = bus->priv;
> +
> + return __dw_mdio_reset(dev);
> +}
> #endif
>
> #if IS_ENABLED(CONFIG_DM_MDIO)
> @@ -142,9 +148,10 @@ int designware_eth_mdio_write(struct udevice *mdio_dev,
> int addr, int devad, int
> #if CONFIG_IS_ENABLED(DM_GPIO)
> int designware_eth_mdio_reset(struct udevice *mdio_dev)
> {
> - struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev);
> + struct mdio_perdev_priv *mdio_pdata = dev_get_uclass_priv(mdio_dev);
> + struct udevice *dev = mdio_pdata->mii_bus->priv;
>
> - return dw_mdio_reset(pdata->mii_bus);
> + return __dw_mdio_reset(dev->parent);
> }
> #endif
>
> --
> 2.25.1
>
Reviewed-by: Ramon Fried
Re: [PATCH] net: e1000: do not attempt to set hwaddr for i210 without FLASH
On Fri, Apr 16, 2021 at 11:25 PM Tim Harvey wrote:
>
> commit f1bcad22dd19 ("net: e1000: add support for writing to EEPROM")
> adds support for storing hwaddr in EEPROM however i210 devices do not
> support this and thus results in errors such as:
> Warning: e1000#0 failed to set MAC address'
>
> Check if a flash device is present and if not return -ENOSYS indicating
> this is not supported.
>
> Signed-off-by: Tim Harvey
> ---
> drivers/net/e1000.c | 4
> drivers/net/e1000.h | 1 +
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
> index 694114eca7..60613b7df0 100644
> --- a/drivers/net/e1000.c
> +++ b/drivers/net/e1000.c
> @@ -5673,6 +5673,10 @@ static int e1000_write_hwaddr(struct eth_device *dev)
>
> DEBUGOUT("%s: mac=%pM\n", __func__, mac);
>
> + if ((hw->eeprom.type == e1000_eeprom_invm) &&
> + !(E1000_READ_REG(hw, EECD) & E1000_EECD_FLASH_DETECTED_I210))
> + return -ENOSYS;
> +
> memset(current_mac, 0, 6);
>
> /* Read from EEPROM, not from registers, to make sure
> diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
> index 072851ba31..082154a997 100644
> --- a/drivers/net/e1000.h
> +++ b/drivers/net/e1000.h
> @@ -1245,6 +1245,7 @@ struct e1000_hw {
> #define E1000_EECD_FLUPD 0x0008 /* Update FLASH */
> #define E1000_EECD_FLUPD_I210 0x0080 /* Update FLASH */
> #define E1000_EECD_FLUDONE_I210 0x0400 /* Update FLASH done*/
> +#define E1000_EECD_FLASH_DETECTED_I210 0x0008 /* FLASH detected */
> #define E1000_FLUDONE_ATTEMPTS 2
> #define E1000_EECD_AUPDEN0x0010 /* Enable Autonomous FLASH update */
> #define E1000_EECD_SHADV 0x0020 /* Shadow RAM Data Valid */
> --
> 2.17.1
>
Reviewed-by: Ramon Fried
Re: [PATCH v4 2/6] lib: ecdsa: Add skeleton to implement ecdsa verification in u-boot
Hi Alex, On Thu, 22 Apr 2021 at 07:30, Alex G. wrote: > > On 4/21/21 2:15 AM, Simon Glass wrote: > > Hi Alexandru, > > > > On Fri, 16 Apr 2021 at 08:07, Alexandru Gagniuc > > wrote: > >> > >> Prepare the source tree for accepting implementations of the ECDSA > >> algorithm. This patch deals with the boring aspects of Makefiles and > >> Kconfig files. > >> > >> Signed-off-by: Alexandru Gagniuc > >> --- > >> include/image.h | 10 +- > >> include/u-boot/rsa.h | 2 +- > >> lib/Kconfig | 1 + > >> lib/Makefile | 1 + > >> lib/ecdsa/Kconfig| 23 +++ > >> lib/ecdsa/Makefile | 1 + > >> lib/ecdsa/ecdsa-verify.c | 13 + > >> 7 files changed, 45 insertions(+), 6 deletions(-) > >> create mode 100644 lib/ecdsa/Kconfig > >> create mode 100644 lib/ecdsa/Makefile > >> create mode 100644 lib/ecdsa/ecdsa-verify.c > > > > Reviewed-by: Simon Glass > > > > nit below > > > >> > >> diff --git a/include/image.h b/include/image.h > >> index 3ff3c035a7..9b95f6783b 100644 > >> --- a/include/image.h > >> +++ b/include/image.h > >> @@ -1224,20 +1224,20 @@ int calculate_hash(const void *data, int data_len, > >> const char *algo, > >> #if defined(USE_HOSTCC) > >> # if defined(CONFIG_FIT_SIGNATURE) > >> # define IMAGE_ENABLE_SIGN1 > >> -# define IMAGE_ENABLE_VERIFY 1 > >> +# define IMAGE_ENABLE_VERIFY_RSA 1 > >> # define IMAGE_ENABLE_VERIFY_ECDSA1 > >> # define FIT_IMAGE_ENABLE_VERIFY 1 > >> # include > >> # else > >> # define IMAGE_ENABLE_SIGN0 > >> -# define IMAGE_ENABLE_VERIFY 0 > >> +# define IMAGE_ENABLE_VERIFY_RSA 0 > >> # define IMAGE_ENABLE_VERIFY_ECDSA 0 > >> # define FIT_IMAGE_ENABLE_VERIFY 0 > >> # endif > >> #else > >> # define IMAGE_ENABLE_SIGN 0 > >> -# define IMAGE_ENABLE_VERIFY CONFIG_IS_ENABLED(RSA_VERIFY) > >> -# define IMAGE_ENABLE_VERIFY_ECDSA 0 > >> +# define IMAGE_ENABLE_VERIFY_RSA CONFIG_IS_ENABLED(RSA_VERIFY) > >> +# define IMAGE_ENABLE_VERIFY_ECDSA CONFIG_IS_ENABLED(ECDSA_VERIFY) > > > > Since we are using Kconfig now, can we drop this IMAGE_... stuff and > > just use CONFIG_IS_ENABLED() in the code? > > CONFIG_IS_ENABLED() doesn't work for host tools. I wonder if that and IS_ENABLED() can be fixed? Regards, Simon
Re: [PATCH 1/5] lib: add crypt subsystem
Hi Steffen, On Wed, 21 Apr 2021 at 20:21, Steffen Jaeckel wrote: > > Hi Simon, > > thanks for taking the time to review. > > On 4/21/21 9:14 AM, Simon Glass wrote: > > On Tue, 13 Apr 2021 at 10:16, Steffen Jaeckel > > wrote: > >> > >> Add the basic functionality required to support the standard crypt > >> format. > >> The files crypt-sha256.c and crypt-sha512.c originate from libxcrypt and > >> their formatting is therefor retained. > >> The integration is done via a crypt_compare() function in crypt.c. > >> > >> ``` > >> libxcrypt $ git describe --long --always --all > >> tags/v4.4.17-0-g6b110bc > >> ``` > >> > >> Signed-off-by: Steffen Jaeckel > >> --- > >> > >> include/crypt.h | 13 ++ > >> lib/Kconfig | 1 + > >> lib/Makefile | 1 + > >> lib/crypt/Kconfig| 29 > >> lib/crypt/Makefile | 10 ++ > >> lib/crypt/alg-sha256.h | 17 ++ > >> lib/crypt/alg-sha512.h | 17 ++ > >> lib/crypt/crypt-port.h | 28 > >> lib/crypt/crypt-sha256.c | 313 + > >> lib/crypt/crypt-sha512.c | 328 +++ > >> lib/crypt/crypt.c| 73 + > >> 11 files changed, 830 insertions(+) > >> create mode 100644 include/crypt.h > >> create mode 100644 lib/crypt/Kconfig > >> create mode 100644 lib/crypt/Makefile > >> create mode 100644 lib/crypt/alg-sha256.h > >> create mode 100644 lib/crypt/alg-sha512.h > >> create mode 100644 lib/crypt/crypt-port.h > >> create mode 100644 lib/crypt/crypt-sha256.c > >> create mode 100644 lib/crypt/crypt-sha512.c > >> create mode 100644 lib/crypt/crypt.c > > > > This seems to use errno - is that necessary? Also are there any simple > > unit tests we could usefully bring over? > > Regarding errno - that's the way how libxcrypt works internally, I'm not > sure whether we should really touch this ... the default crypt_alg_rn() > function has a void return type, so either we have to keep using errno > or we have to change the return type... Well you could add a wrapper function for U-Boot which returns errno, then make errno a static int in the library. > > Regarding unit tests - good idea, I'll have a look. Regards, Simon
ERROR: v7_outer_cache_inval_range - stop address is not aligned - 0x3bf73010
Hello, I'm trying to get an NVMe device to work in u-boot with Cyclone V SX SOC. I posted before, but perhaps it didn't get through moderation? I've made good progress reverse engineering u-boot. I believe I have the pci drivers working. I had to hack the code a bit, but I think I know the proper fix for it. After I run the command, 'pci', I run nvme scan and get a cache alignment error: (please note I have a bunch of printfs active to figure out where things are going awry) pci-uclass: pci_bus_addr = 0xc000 _dm_pci_bus_to_phys: hose->region_count = 3 Looking for address: 0xc000 loop: 0: Section: 0, bus_start = 0x0, size = 0x10 loop: 1: Section: 1, bus_start = 0xc000, size = 0x10 assigning pa = 0x3bf6b9f0 back from dm_pci_map_bar back from malloc queues back from queues memset back from nvme_readq calling nvme_configure_admin_queue calling memalign calling nvme_setup_io_queues entering nvme_setup_io_queues calling nvme_set_queue_count Calling nvme_set_features running memset on nvme_command struct loading nvme_command struct running nvme_submit_sync_cmd running nvme_submit_cmd doing the memcpy from cmd to nvmeq->sq_cmd[tail] flushing cache writing nvmeq->q_db to tail ERROR: v7_outer_cache_inval_range - stop address is not aligned - 0x3bf73010 calling nvme_free_queues calling nvme_create_io_queues running nvme_submit_sync_cmd running nvme_submit_cmd doing the memcpy from cmd to nvmeq->sq_cmd[tail] flushing cache writing nvmeq->q_db to tail ERROR: v7_outer_cache_inval_range - start address is not aligned - 0x3bf73010 ERROR: v7_outer_cache_inval_range - start address is not aligned - 0x3bf73010 ERROR: v7_outer_cache_inval_range - start address is not aligned - 0x3bf73010 ERROR: v7_outer_cache_inval_range - start address is not aligned - 0x3bf73010 ERROR: v7_outer_cache_inval_range - start address is not aligned - 0x3bf73010 ERROR: v7_outer_cache_inval_range - start address is not aligned - 0x3bf73010 I'm running the socfpga fork of 2020.10. I have tried the master 2021.04, but it has other issues, which I haven't tracked down. The alignment errors continue for some time, and then the NVMe does not work. 'nvme info' returns nothing. I found a thread in the u-boot mailing list about a similar problem with the ide device, that indicates the calloc for the queues needs to be change to a malloc_cache_aligned call. I changed the call, but the problem did not go away. I would appreciate some advice on how to attack this issue. Thanks in advance.
[PATCH v2] pinctrl: single: fix a never true comparison
As reported by Coverity Scan for Das U-Boot, the 'less-than-zero'
comparison of an unsigned value is never true.
Signed-off-by: Dario Binacchi
Reviewed-by: Pratyush Yadav
---
Changes in v2:
- Balance quote in commit message
- Add review tag
drivers/pinctrl/pinctrl-single.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 48bdd0f6f5..7e1c5bb0a5 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -295,7 +295,7 @@ static int single_configure_pins(struct udevice *dev,
func->npins = 0;
for (n = 0; n < count; n++, pins++) {
offset = fdt32_to_cpu(pins->reg);
- if (offset < 0 || offset > pdata->offset) {
+ if (offset > pdata->offset) {
dev_err(dev, " invalid register offset 0x%x\n",
offset);
continue;
@@ -344,7 +344,7 @@ static int single_configure_bits(struct udevice *dev,
func->npins = 0;
for (n = 0; n < count; n++, pins++) {
offset = fdt32_to_cpu(pins->reg);
- if (offset < 0 || offset > pdata->offset) {
+ if (offset > pdata->offset) {
dev_dbg(dev, " invalid register offset 0x%x\n",
offset);
continue;
--
2.17.1
Re: [PATCH] sunxi: DT: A64: update devicetree files
Dne sreda, 21. april 2021 ob 11:27:12 CEST je Andre Przywara napisal(a): > Import updated devicetree file from Linux v5.12-rc8. > > Besides some node and audio port renames this changes the PHY modes to > either rgmii-id or rgmii-txid. From the board files the Pinephone sees > a lot of updates. > > This also adds the long missing USB PHY property for controller 0, which > allows the U-Boot PHY driver to eventually use port 0 in host mode > (pending another U-Boot patch). > > Signed-off-by: Andre Przywara > --- > arch/arm/dts/sun50i-a64-bananapi-m64.dts | 16 ++-- > arch/arm/dts/sun50i-a64-nanopi-a64.dts| 2 +- > arch/arm/dts/sun50i-a64-orangepi-win.dts | 10 +-- > arch/arm/dts/sun50i-a64-pine64-lts.dts| 15 > arch/arm/dts/sun50i-a64-pine64-plus.dts | 2 +- > arch/arm/dts/sun50i-a64-pine64.dts| 8 +- > arch/arm/dts/sun50i-a64-pinebook.dts | 13 ++- > arch/arm/dts/sun50i-a64-pinephone-1.0.dts | 7 +- > arch/arm/dts/sun50i-a64-pinephone-1.1.dts | 7 +- > arch/arm/dts/sun50i-a64-pinephone-1.2.dts | 16 +++- > arch/arm/dts/sun50i-a64-pinephone.dtsi| 90 +++ > .../dts/sun50i-a64-pinetab-early-adopter.dts | 26 ++ > arch/arm/dts/sun50i-a64-pinetab.dts | 13 ++- > arch/arm/dts/sun50i-a64-sopine-baseboard.dts | 11 +-- > arch/arm/dts/sun50i-a64-sopine.dtsi | 3 +- > arch/arm/dts/sun50i-a64-teres-i.dts | 12 +-- > arch/arm/dts/sun50i-a64.dtsi | 40 ++--- > 17 files changed, 215 insertions(+), 76 deletions(-) > create mode 100644 arch/arm/dts/sun50i-a64-pinetab-early-adopter.dts Files are identical, so: Reviewed-by: Jernej Skrabec Best regards, Jernej
[PULL] u-boot-mips
Hi Tom, please pull some updates and fixes for MIPS. Gitlab CI: https://source.denx.de/u-boot/custodians/u-boot-mips/-/pipelines/7255 Azure: https://dev.azure.com/danielschwierzeck/u-boot/_build/results?buildId=22=results The following changes since commit 842d049be23976ebcbb2522fa8d752d3aae8631a: Merge branch '2021-04-20-assorted-improvements' (2021-04-20 07:32:04 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-mips.git/ tags/mips-pull-2021-04-22 for you to fetch changes up to 91ce06ad340ef12fc3fd0ee3a5d040cc0bba731e: mips: octeon: octeon_ebb7304_defconfig: Enable USB storage support (2021-04-22 03:02:37 +0200) - net: fix traffic problems in MSCC Jaguar 2 network driver - MIPS: mt7628: fix DDR memory init - MIPS: octeon: add MMC and USB support Horatiu Vultur (2): net: jr2: Reset switch net: jr2: Fix Serdes6G configuration Stefan Roese (5): mmc: octeontx_hsmmc: Add support for MIPS Octeon mips: octeon: mrvl,cn73xx.dtsi: Add MMC DT node mips: octeon: mrvl,octeon_ebb7304.dts: Add MMC DT node mips: octeon: octeon_ebb7304_defconfig: Enable MMC support mips: octeon: octeon_ebb7304_defconfig: Enable USB storage support Weijie Gao (2): mips: mt7628: fix ddr_type for MT7688KN mips: mt7628: fix the displayed DDR type of mt7628 arch/mips/dts/mrvl,cn73xx.dtsi | 27 + arch/mips/dts/mrvl,octeon-ebb7304.dts | 57 ++ arch/mips/dts/mscc,jr2.dtsi| 6 +- arch/mips/mach-mtmips/mt7628/ddr.c | 6 +- arch/mips/mach-mtmips/mt7628/init.c| 3 + .../mach-octeon/include/mach/cvmx-mio-emm-defs.h | 614 + configs/octeon_ebb7304_defconfig | 13 +- drivers/mmc/Kconfig| 10 +- drivers/mmc/octeontx_hsmmc.c | 195 +-- drivers/net/mscc_eswitch/jr2_switch.c | 43 +- 10 files changed, 906 insertions(+), 68 deletions(-) create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-mio-emm-defs.h
Re: [PATCH] Revert "usb: kbd: destroy device after console is stopped"
On 4/22/21 1:30 PM, Andy Shevchenko wrote: On Thu, Apr 22, 2021 at 12:11:44PM +0100, Peter Robinson wrote: On Thu, Apr 22, 2021 at 11:52 AM Andy Shevchenko wrote: On Thu, Apr 22, 2021 at 10:19:10AM +0100, Peter Robinson wrote: Thanks for the report. Reverts commit eb5fd9e46c1, it causes ARMv7 devices to stop booting Linux when a USB keyboard is attached. The kernels starts but there's no output. Reverting it makes things work again. It's not good. When we revert, we introduce another (I consider more serious) bug. Sure, looking at the fixes tags I figured as much, but it also causes regressions itself. I figured sending a revert would at least start the discussion off. Signed-off-by: Peter Robinson Cc: Nicolas Saenz Julienne Cc: Andy Shevchenko --- This has caused us issues on a number of ARMv7 deviices. I'm not sure why specifically ARMv7 because it happens on a RPi3 running Fedora armhfp, but doesn't happen on aarch64. Issue seen on RPis, Cubietruck, and others. Can we conduct a bit of investigation here? Is it using ATAGs or command line? How Linux kernel gets its parameters? I believe command line, I've been testing booting using UEFI. TBH I'm unsure why I see the problem on ARMv7 and not using aarchc64 on the same device. And what is the U-Boot environment in both cases? (Can you share it somewhere?) Could it be related to CONFIG_SYS_DEVICE_NULLDEV / CONFIG_NULLDEV_SERIAL not being set in one of the cases ?
Re: [PATCH V2 24/24] ARM: imx8m: verdin-imx8mm: Enable USB Host support
On 4/20/21 2:33 AM, Tim Harvey wrote: [...] +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + #endif /*_VERDIN_IMX8MM_H */ -- 2.30.2 Marek, Thanks for your work on USB support for IMX8M! I'm attempting to add USB support to the venice board following this example but I think there are still some things missing from the dt to make this work. I find that mx6_parse_dt_adds failes; Looks like it is required to have an alias that points to the phy but then it fails because the phy doesn't have a reg. Also, it would see the CONFIG_MXC_USB_PORTSC is no longer needed as that is now the default. Have a look at this patch: https://source.denx.de/u-boot/custodians/u-boot-usb/-/commit/8203ee09275c30766a1fd1cf19c60a904ee72f8c That should fix it for you. It would be good however if you could take the mx6 ventana and test the driver there, and possibly submit fixes in case the USB is still broken there. What would be even better is if you could implement the MXS PHY driver, so all the !CONFIG_PHY stuff can be removed for MX6 too. That shouldn't be much effort.
Re: [PATCH] pinctrl: single: fix a never true comparison
On 22/04/21 06:37PM, Dario Binacchi wrote: > As reported by Coverity Scan for Das U-Boot, the 'less-than-zero > comparison of an unsigned value is never true. Unbalanced quote. > > Signed-off-by: Dario Binacchi Reviewed-by: Pratyush Yadav -- Regards, Pratyush Yadav Texas Instruments Inc.
Re: [PATCH] lib: Move selection of SPL hash algorithms from common/
On Mon, Mar 22, 2021 at 08:33:31AM -0500, Alexandru Gagniuc wrote: > When God said, "May there be FIT signature verification in SPL", > Chuck Norris said "SPL image too big". And then there was this patch. > > Enabling SPL_FIT_SIGNATURE increased the code size (armv7 platform) by > about 16KiB, just enough to go over the SPL image limit. Of that: > * .text.sha256_process 3.8 KiB > * SHA1 implementation 4.4 KiB > Although SHA1 wasn't required, it could not be disabled. > > The hash algorithms are implemented in lib/, as is their Kconfig > selection for u-boot main. However, Kconfig selection for SPL is > implemented in common/. To put it mildly, this is inconsistent. > MD5 selection, on the other hand, does not have this problem. > > Moving the SPL hash switches to lib/ solves half the problem. They > have to be renamed from SPL__SUPPORT to SPL_ to make > them work elegantly with the CONFIG_IS_ENABLED() macro. > > The second half of the problem is not referencing the symbols > when is disabled. Unfortunately, this requires some more > > The above #ifdef problem could be solved in several ways. One way > could be to move the hash handlers to linker lists. This, however, > won't work for userspace tools (mkimage), as they don't implement > custom linker scripts. One could implement a _register() > function for this case, and manually register all hashes. However, > this is beyond the scope of this patch. > > Signed-off-by: Alexandru Gagniuc > --- > > This is designed to apply on top of the following series: > * [PATCH v6 00/11] Add support for ECDSA image signing > > common/hash.c | 4 ++-- > common/image-sig.c | 8 +-- > common/spl/Kconfig | 54 -- > include/image.h| 12 +-- > lib/Kconfig| 39 + > lib/Makefile | 6 +++--- > 6 files changed, 56 insertions(+), 67 deletions(-) I like this idea. As-is, there's a few problems. socfpga_agilex_vab and imx8mm_venice now fail to build due to missing sha384 support for the former and sram overflow for the latter. ls1046ardb_qspi_spl now also grows SPL a bit by adding sha1 support. Can you look in to these please? Thanks. -- Tom signature.asc Description: PGP signature
[PATCH] pinctrl: single: fix a never true comparison
As reported by Coverity Scan for Das U-Boot, the 'less-than-zero
comparison of an unsigned value is never true.
Signed-off-by: Dario Binacchi
---
drivers/pinctrl/pinctrl-single.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 48bdd0f6f5..7e1c5bb0a5 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -295,7 +295,7 @@ static int single_configure_pins(struct udevice *dev,
func->npins = 0;
for (n = 0; n < count; n++, pins++) {
offset = fdt32_to_cpu(pins->reg);
- if (offset < 0 || offset > pdata->offset) {
+ if (offset > pdata->offset) {
dev_err(dev, " invalid register offset 0x%x\n",
offset);
continue;
@@ -344,7 +344,7 @@ static int single_configure_bits(struct udevice *dev,
func->npins = 0;
for (n = 0; n < count; n++, pins++) {
offset = fdt32_to_cpu(pins->reg);
- if (offset < 0 || offset > pdata->offset) {
+ if (offset > pdata->offset) {
dev_dbg(dev, " invalid register offset 0x%x\n",
offset);
continue;
--
2.17.1
[PATCH] pinctrl: single: check function mask to be non-zero
Otherwise it can generate a division by zero, which has an undefined
behavior.
Signed-off-by: Dario Binacchi
---
drivers/pinctrl/pinctrl-single.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 7e1c5bb0a5..ebb7602dde 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -335,6 +335,10 @@ static int single_configure_bits(struct udevice *dev,
phys_addr_t reg;
u32 offset, val, mask, bit_pos, val_pos, mask_pos, submask;
+ /* If function mask is null, needn't enable it. */
+ if (!pdata->mask)
+ return 0;
+
npins_in_reg = pdata->width / priv->bits_per_pin;
func = single_allocate_function(dev, count * npins_in_reg);
if (IS_ERR(func))
@@ -469,6 +473,11 @@ static int single_probe(struct udevice *dev)
priv->npins = size / (pdata->width / BITS_PER_BYTE);
if (pdata->bits_per_mux) {
+ if (!pdata->mask) {
+ dev_err(dev, "function mask needs to be non-zero\n");
+ return -EINVAL;
+ }
+
priv->bits_per_pin = fls(pdata->mask);
priv->npins *= (pdata->width / priv->bits_per_pin);
}
--
2.17.1
[PATCH] smbios: Fix calculating BIOS Release Date
BIOS Release Date must be in format mm/dd/ and must be release date.
U-Boot currently sets BIOS Release Date from U_BOOT_DMI_DATE macro which is
generated from current build timestamp.
Fix this issue by setting U_BOOT_DMI_DATE macro to U-Boot version which is
better approximation of U-Boot release date than current build timestamp.
Current U-Boot versioning is in format .mm so as a day choose 01.
Some operating systems are using BIOS Release Date for detecting when was
SMBIOS table filled or if it could support some feature (e.g. BIOS from
1990 cannot support features invented in 2000). So this change also ensures
that recompiling U-Boot from same sources but in different year does not
change behavior of some operating systems.
Macro U_BOOT_DMI_DATE is not used in other file than lib/smbios.c
so remove it from global autogenerated files and also from Makefile.
Signed-off-by: Pali Rohár
---
Makefile| 2 --
doc/develop/version.rst | 1 -
lib/smbios.c| 23 +++
3 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/Makefile b/Makefile
index e423f6de7468..4cd28bce237b 100644
--- a/Makefile
+++ b/Makefile
@@ -1832,7 +1832,6 @@ define filechk_timestamp.h
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define
U_BOOT_DATE "%b %d %C%y"'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define
U_BOOT_TIME "%T"'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define
U_BOOT_TZ "%z"'; \
- LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define
U_BOOT_DMI_DATE "%m/%d/%Y"'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define
U_BOOT_BUILD_DATE 0x%Y%m%d'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define
U_BOOT_EPOCH %s'; \
else \
@@ -1842,7 +1841,6 @@ define filechk_timestamp.h
LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \
LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \
LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \
- LC_ALL=C date +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
LC_ALL=C date +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
LC_ALL=C date +'#define U_BOOT_EPOCH %s'; \
fi)
diff --git a/doc/develop/version.rst b/doc/develop/version.rst
index a7797db41bb2..066901bcd2d9 100644
--- a/doc/develop/version.rst
+++ b/doc/develop/version.rst
@@ -84,7 +84,6 @@ fields. For example::
#define U_BOOT_DATE "Jan 06 2021" (US format only)
#define U_BOOT_TIME "08:50:36"(24-hour clock)
#define U_BOOT_TZ "-0700" (Time zone in hours)
- #define U_BOOT_DMI_DATE "01/06/2021" (US format only)
#define U_BOOT_BUILD_DATE 0x20210106 (hex mmdd format)
#define U_BOOT_EPOCH 1609948236
diff --git a/lib/smbios.c b/lib/smbios.c
index 9eb226ec9fbd..e5cf05073543 100644
--- a/lib/smbios.c
+++ b/lib/smbios.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -18,6 +19,28 @@
#include
#endif
+/* Safeguard for checking that U_BOOT_VERSION_NUM macros are compatible with
U_BOOT_DMI */
+#if U_BOOT_VERSION_NUM < 2000 || U_BOOT_VERSION_NUM > 2099 || \
+U_BOOT_VERSION_NUM_PATCH < 1 || U_BOOT_VERSION_NUM_PATCH > 12
+#error U_BOOT_VERSION_NUM macros are not compatible with DMI, fix U_BOOT_DMI
macros
+#endif
+
+/*
+ * U_BOOT_DMI_DATE contains BIOS Release Date in format mm/dd/.
+ * BIOS Release Date is calculated from U-Boot version and fixed day 01.
+ * So for U-Boot version 2021.04 it is calculated as "04/01/2021".
+ * BIOS Release Date should contain date when code was released
+ * and not when it was built or compiled.
+ */
+#if U_BOOT_VERSION_NUM_PATCH < 10
+#define U_BOOT_DMI_MONTH "0" __stringify(U_BOOT_VERSION_NUM_PATCH)
+#else
+#define U_BOOT_DMI_MONTH __stringify(U_BOOT_VERSION_NUM_PATCH)
+#endif
+#define U_BOOT_DMI_DAY "01"
+#define U_BOOT_DMI_YEAR __stringify(U_BOOT_VERSION_NUM)
+#define U_BOOT_DMI_DATE U_BOOT_DMI_MONTH "/" U_BOOT_DMI_DAY "/" U_BOOT_DMI_YEAR
+
DECLARE_GLOBAL_DATA_PTR;
/**
--
2.20.1
Re: [PATCH 4/4] ARM: imx: udoo_neo: Convert to ethernet DM
On Thu, Apr 01, 2021 at 09:08:13PM +0100, Peter Robinson wrote: > Convert the UDOO Neo to ethernet DM support. > > Signed-off-by: Peter Robinson > Cc: Francesco Montefoschi > Cc: Breno Lima > Cc: Fabio Estevam > Cc: Stefano Babic Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 3/4] ARM: imx: udoo_neo: convert to DM_MMC
On Thu, Apr 01, 2021 at 09:08:12PM +0100, Peter Robinson wrote: > Convert UDOO Neo to use DM MMC. > > Signed-off-by: Peter Robinson > Cc: Francesco Montefoschi > Cc: Breno Lima > Cc: Fabio Estevam > Cc: Stefano Babic Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/4] ARM: imx: udoo_neo: Enable OF_CONTROL and DM gpio/pin control
On Thu, Apr 01, 2021 at 09:08:11PM +0100, Peter Robinson wrote: > Enable OF_CONTROL and DM for gpio and pin control support > on the i.MX6SX based Udoo Neo. > > Signed-off-by: Peter Robinson > Cc: Francesco Montefoschi > Cc: Breno Lima > Cc: Fabio Estevam > Cc: Stefano Babic Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/4] ARM: board: udoo_neo: Import UDOO Neo dts files
On Thu, Apr 01, 2021 at 09:08:10PM +0100, Peter Robinson wrote: > Import the i.MX6SX based UDOO Neo dts files from Linux 5.12-rc1 > and sync the i.MX6SX pinfunc.h > > Signed-off-by: Peter Robinson > Cc: Francesco Montefoschi > Cc: Breno Lima > Cc: Fabio Estevam > Cc: Stefano Babic > Reviewed-by: Fabio Estevam Note that Stefano said this was applied to u-boot-imx/master, but it wasn't there and I think got missed with udoo and udoo_neo being separate series. So, I've picked this up directly. Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH V2 24/24] ARM: imx8m: verdin-imx8mm: Enable USB Host support
On Thu, Apr 22, 2021 at 3:34 AM Ying-Chun Liu (PaulLiu) wrote: > > Hi Marek, > > I have the same issue on my iMX8MM based board. > Are you continue working on the patch for iMX8MM or should I dig into > this problem? > > I'm asking this just for not duplicating efforts. > So if you are not working on this then I'll see if I can properly > retrieve the necessary patches to make this work. > > > I think something is missing from previous patch set > > https://lists.denx.de/pipermail/u-boot/2020-September/426757.html > > Paul, It's not something missing from Peng's previous patchset since that didn't support DM. Marek added the dm bits but it requires some dt changes that are still not present to make mx6_parse_dt_addrs work (or some changes are needed to that func). The way mx6_parse_dt_addrs is written you need to have a 'usb0' alias for example that points to the phy node (compatible 'fsl,usbmisc') but that is not what has typically been done for USB as typically the alias points to the host controller instead. I'm still interested in what Marek tested with and also think there's a dt patch missing. The aliases should be added to imx8mm.dtsi, but I also think they should point to the controller and not the phy so there may be a code change needed as well. Also, I wasn't aware that the power-domain dt bindings were accepted upstream to Linux as there has been quite a bit of controversy there. cc'ing some others that are probably interested in mainline USB on IMX8M and likely know what's going on with IMX8M power domain. I regret missing this patchset when it was submitted or I would have asked these questions then... I just can't keep up with Linux and U-Boot mailing lists with my work-load in other areas. Best regards, Tim
Re: [PATCH v2 3/3] test: Add test for partitions
On 4/21/21 3:14 AM, Simon Glass wrote:
> Hi Sean,
>
> On Fri, 16 Apr 2021 at 02:36, Sean Anderson wrote:
>>
>>
>>
>> On 4/14/21 3:37 PM, Simon Glass wrote:
>> > Hi Sean,
>> >
>> > On Mon, 12 Apr 2021 at 23:53, Sean Anderson
wrote:
>> >>
>> >> This is technically a library function, but we use MMCs for testing, so
>> >> it is easier to do it with DM. At the moment, the only block devices in
>> >> sandbox are MMCs (AFAIK) so we just test with those.
>> >>
>> >> Signed-off-by: Sean Anderson
>> >> ---
>> >>
>> >> Changes in v2:
>> >> - New
>> >>
>> >> test/dm/Makefile | 1 +
>> >> test/dm/part.c | 76
>> >> 2 files changed, 77 insertions(+)
>> >> create mode 100644 test/dm/part.c
>> >>
>> >> diff --git a/test/dm/Makefile b/test/dm/Makefile
>> >> index f5cc5540e8..7d017f8750 100644
>> >> --- a/test/dm/Makefile
>> >> +++ b/test/dm/Makefile
>> >> @@ -98,5 +98,6 @@ endif
>> >> ifneq ($(CONFIG_EFI_PARTITION),)
>> >> obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fastboot.o
>> >> endif
>> >> +obj-$(CONFIG_EFI_PARTITION) += part.o
>> >> endif
>> >> endif # !SPL
>> >> diff --git a/test/dm/part.c b/test/dm/part.c
>> >> new file mode 100644
>> >> index 00..051e9010b6
>> >> --- /dev/null
>> >> +++ b/test/dm/part.c
>> >> @@ -0,0 +1,76 @@
>> >> +// SPDX-License-Identifier: GPL-2.0+
>> >> +/*
>> >> + * Copyright (C) 2020 Sean Anderson
>> >> + */
>> >> +
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +
>> >> +static int dm_test_part(struct unit_test_state *uts)
>> >> +{
>> >> + char str_disk_guid[UUID_STR_LEN + 1];
>> >> + struct blk_desc *mmc_dev_desc;
>> >> + struct disk_partition part_info;
>> >> + struct disk_partition parts[2] = {
>> >> + {
>> >> + .start = 48, /* GPT data takes up the first 34
blocks or so */
>> >> + .size = 1,
>> >> + .name = "test1",
>> >> + },
>> >> + {
>> >> + .start = 49,
>> >> + .size = 1,
>> >> + .name = "test2",
>> >> + },
>> >> + };
>> >> +
>> >> + ut_asserteq(1, blk_get_device_by_str("mmc", "1",
_dev_desc));
>> >> + if (CONFIG_IS_ENABLED(RANDOM_UUID)) {
>> >> + gen_rand_uuid_str(parts[0].uuid, UUID_STR_FORMAT_STD);
>> >> + gen_rand_uuid_str(parts[1].uuid, UUID_STR_FORMAT_STD);
>> >> + gen_rand_uuid_str(str_disk_guid, UUID_STR_FORMAT_STD);
>> >> + }
>> >> + ut_assertok(gpt_restore(mmc_dev_desc, str_disk_guid, parts,
>> >> + ARRAY_SIZE(parts)));
>> >> +
>> >> +#define test(expected, part_str, whole) \
>> >
>> > Can this be a function instead of a macro?
>>
>> Not one-to-one because ut-asserteq returns on error. This could be
>> changed to
>>
>> ut_asserteq(-ENODEV, test("", true));
>>
>> but I think a macro is the simplest option.
>
> Well you are using ut_asserteq() in the macro so I don't see why the
> macro is better than what you have above, with the code in a function?
> That is what we normally do.
I suppose. It doesn't really matter too much IMO, but I will change it
for v3.
--Sean
>
>
>>
>> --Sean
>>
>> >
>> >> + ut_asserteq(expected, \
>> >> + part_get_info_by_dev_and_name_or_num("mmc",
part_str, \
>> >> +_dev_desc,
\
>> >> +_info,
whole))
>> >> +
>> >> + test(-ENODEV, "", true);
>> >> + env_set("bootdevice", "0");
>> >> + test(0, "", true);
>> >> + env_set("bootdevice", "1");
>> >> + test(1, "", false);
>> >> + test(1, "-", false);
>> >> + env_set("bootdevice", "");
>> >> + test(-EPROTONOSUPPORT, "0", false);
>> >> + test(0, "0", true);
>> >> + test(0, ":0", true);
>> >> + test(0, ".0", true);
>> >> + test(0, ".0:0", true);
>> >> + test(-EINVAL, "#test1", true);
>> >> + test(1, "1", false);
>> >> + test(1, "1", true);
>> >> + test(-ENOENT, "1:0", false);
>> >> + test(0, "1:0", true);
>> >> + test(1, "1:1", false);
>> >> + test(2, "1:2", false);
>> >> + test(1, "1.0", false);
>> >> + test(0, "1.0:0", true);
>> >> + test(1, "1.0:1", false);
>> >> + test(2, "1.0:2", false);
>> >> + test(-EINVAL, "1#bogus", false);
>> >> + test(1, "1#test1", false);
>> >> + test(2, "1#test2", false);
>> >> +
>> >> + return 0;
>> >> +}
>> >> +DM_TEST(dm_test_part, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
>> >>
[PATCH] arm: a37xx: pci: Fix processing PIO transfers
Trying to clear PIO_START register when it is non-zero (which indicates
that previous PIO transfer has not finished yet) causes an External
Abort with SError 0xbf02.
This bug is currently worked around in TF-A by handling External Aborts
in EL3 and ignoring this particular SError.
This workaround was also discussed at:
https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50
https://lore.kernel.org/linux-pci/20190316161243.29517-1-r...@triplefau.lt/
https://lore.kernel.org/linux-pci/971be151d24312cc533989a64bd45...@www.loen.fr/
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1541
Implement a proper fix to prevent this External Abort. As it is not
possible to cancel a pending PIO transfer, simply do not start a new one
if previous has not finished yet. In this case return an error to the
caller.
In most cases this SError happens when there is no PCIe card connected
or when PCIe link is down. The reason is that in these cases a PIO
transfer takes about 1.44 seconds. For this reason we also increase the
wait timeout in pcie_advk_wait_pio() to 1.5 seconds.
If PIO read transfer for PCI_VENDOR_ID register times out, or if it
isn't possible to read it yet because previous transfer is not finished,
return Completion Retry Status value instead of failing, to give the
caller a chance to send a new read request.
Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
---
drivers/pci/pci-aardvark.c | 42 +-
1 file changed, 28 insertions(+), 14 deletions(-)
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 3b9309f52c..c43d4f309b 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -132,8 +132,9 @@
PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
/* PCIe Retries & Timeout definitions */
-#define MAX_RETRIES10
-#define PIO_WAIT_TIMEOUT 100
+#define PIO_MAX_RETRIES1500
+#define PIO_WAIT_TIMEOUT 1000
+#define LINK_MAX_RETRIES 10
#define LINK_WAIT_TIMEOUT 10
#define CFG_RD_UR_VAL 0x
@@ -192,7 +193,7 @@ static int pcie_advk_addr_valid(pci_dev_t bdf, int
first_busno)
*
* @pcie: The PCI device to access
*
- * Wait up to 1 micro second for PIO access to be accomplished.
+ * Wait up to 1.5 seconds for PIO access to be accomplished.
*
* Return 1 (true) if PIO access is accomplished.
* Return 0 (false) if PIO access is timed out.
@@ -202,7 +203,7 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie)
uint start, isr;
uint count;
- for (count = 0; count < MAX_RETRIES; count++) {
+ for (count = 0; count < PIO_MAX_RETRIES; count++) {
start = advk_readl(pcie, PIO_START);
isr = advk_readl(pcie, PIO_ISR);
if (!start && isr)
@@ -214,7 +215,7 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie)
udelay(PIO_WAIT_TIMEOUT);
}
- dev_err(pcie->dev, "config read/write timed out\n");
+ dev_err(pcie->dev, "PIO read/write transfer time out\n");
return 0;
}
@@ -323,9 +324,14 @@ static int pcie_advk_read_config(const struct udevice
*bus, pci_dev_t bdf,
return 0;
}
- /* Start PIO */
- advk_writel(pcie, 0, PIO_START);
- advk_writel(pcie, 1, PIO_ISR);
+ if (advk_readl(pcie, PIO_START)) {
+ dev_err(pcie->dev,
+ "Previous PIO read/write transfer is still running\n");
+ if (offset != PCI_VENDOR_ID)
+ return -EINVAL;
+ *valuep = CFG_RD_CRS_VAL;
+ return 0;
+ }
/* Program the control register */
reg = advk_readl(pcie, PIO_CTRL);
@@ -342,10 +348,15 @@ static int pcie_advk_read_config(const struct udevice
*bus, pci_dev_t bdf,
advk_writel(pcie, 0, PIO_ADDR_MS);
/* Start the transfer */
+ advk_writel(pcie, 1, PIO_ISR);
advk_writel(pcie, 1, PIO_START);
- if (!pcie_advk_wait_pio(pcie))
- return -EINVAL;
+ if (!pcie_advk_wait_pio(pcie)) {
+ if (offset != PCI_VENDOR_ID)
+ return -EINVAL;
+ *valuep = CFG_RD_CRS_VAL;
+ return 0;
+ }
/* Check PIO status and get the read result */
ret = pcie_advk_check_pio_status(pcie, true, );
@@ -420,9 +431,11 @@ static int pcie_advk_write_config(struct udevice *bus,
pci_dev_t bdf,
return 0;
}
- /* Start PIO */
- advk_writel(pcie, 0, PIO_START);
- advk_writel(pcie, 1, PIO_ISR);
+ if (advk_readl(pcie, PIO_START)) {
+ dev_err(pcie->dev,
+ "Previous PIO read/write transfer is still running\n");
+ return -EINVAL;
+ }
/* Program the
[PATCH v2 18/18] am335x, guardian: configs: Enable bootcount nvmem support
From: Gireesh Hiremath include bootcount nvmem support Signed-off-by: Gireesh Hiremath --- configs/am335x_guardian_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index 6056b78991..65a3c23e9c 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -71,6 +71,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_SPL_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_AM33XX_NVMEM=y CONFIG_CLK=y CONFIG_CLK_CCF=y CONFIG_CLK_TI_AM3_DPLL=y -- 2.20.1
[PATCH v2 17/18] am335x, guardian: software update available status is stored in AM3352 RTC scracth register
From: Gireesh Hiremath RTC second scratch register[32-bit]: -zero byte hold boot count value -first byte hold update available state -second byte hold version -third byte hold magic number Signed-off-by: Gireesh Hiremath Gbp-Pq: Topic apertis/guardian Gbp-Pq: Name am335x-guardian-software-update-available-status-is-store.patch --- On 06/01/21 9:02 pm, gireesh.hirem...@in.bosch.com wrote: > From: Gireesh Hiremath > > RTC second scratch register[32-bit]: > -zero byte hold boot count value > -first byte hold update available state > -second byte hold version > -third byte hold magic number > > Signed-off-by: Gireesh Hiremath > > Gbp-Pq: Topic apertis/guardian > Gbp-Pq: Name > am335x-guardian-software-update-available-status-is-store.patch Hmm..not sure what this is.. Cover letter is not needed for a single patch btw. > --- > configs/am335x_guardian_defconfig | 1 + > drivers/bootcount/Kconfig | 27 -- > drivers/bootcount/Makefile | 1 + > drivers/bootcount/bootcount_nvmem.c | 57 > + Please split driver and defconfig changes. Isn't it possible to re-use drivers/bootcount/bootcount_davinci.c? Thanks and regards, Lokesh Hi Lokesh Splited driver and defconfig changes. We are using the update manager on an AM3352 where we have only the RTC Scratch registers to store the data in. Unfortunately the drivers/bootcount/bootcount_davinci.c is only handling the bootcount itself and not dealing with update_available and version. The consequence is that rollbacks could always happen, not just after an update. This can e.g. be triggered if the user tries to start up the device with a weak accu pack where the device bootloader might be executed and then the battery dies off during Linux startup. Then bootcount would be incremented, but not reset by the Linux process. If that happens several times in a row, the device will roll back, even if the update was done years ago. Other backends, like drivers/bootcount/bootcount_ext.c handle this properly, by only incrementing boot count if update_available==1. We thought of modifying bootcount_davinci.c but we concerned about backwards compatibility and breakage of other user space update managers. Therefore we think to introduce an alternative backend. Thanks and regards, Gireesh Hiremath drivers/bootcount/Kconfig | 27 -- drivers/bootcount/Makefile | 1 + drivers/bootcount/bootcount_nvmem.c | 57 + 3 files changed, 82 insertions(+), 3 deletions(-) create mode 100644 drivers/bootcount/bootcount_nvmem.c diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index b5ccea0d9c..d543061233 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -42,6 +42,25 @@ config BOOTCOUNT_AM33XX This requires the RTC clocks, etc, to be enabled prior to use and not all boards with this IP block on it will have the RTC in use. +config BOOTCOUNT_AM33XX_NVMEM + bool "Boot counter in AM33XX RTC IP block with upgrade_available flag" + depends on AM33XX +select SPL_AM33XX_ENABLE_RTC32K_OSC if AM33XX + help + Add support for maintaining bootcount,upgrade_available, + version and BOOTMAGIC in a AM33xx RTC IP block + scratch register2. + + A bootcount driver for the RTC IP block found on many TI platforms. + This requires the RTC clocks, etc, to be enabled prior to use and + not all boards with this IP block on it will have the RTC in use. + + If there is upgrade in software then "upgrade_available" is 1, + "bootcount" is incremented otherwise "upgrade_available" and + "bootcount" is always 0. So the Userspace Application must set + the "upgrade_available" and "bootcount" variable to 0, if a boot + was successfully. + config BOOTCOUNT_ENV bool "Boot counter in environment" help @@ -177,16 +196,18 @@ config SYS_BOOTCOUNT_EXT_NAME config SYS_BOOTCOUNT_ADDR hex "RAM address used for reading and writing the boot counter" - default 0x44E3E000 if BOOTCOUNT_AM33XX + default 0x44E3E000 if BOOTCOUNT_AM33XX || BOOTCOUNT_AM33XX_NVMEM default 0xE0115FF8 if ARCH_LS1043A || ARCH_LS1021A depends on BOOTCOUNT_AM33XX || BOOTCOUNT_GENERIC || BOOTCOUNT_EXT || \ - BOOTCOUNT_I2C + BOOTCOUNT_I2C || BOOTCOUNT_AM33XX_NVMEM help Set the address used for reading and writing the boot counter. config SYS_BOOTCOUNT_MAGIC hex "Magic value for the boot counter" - default 0xB001C041 + default 0xB001C041 if BOOTCOUNT_AM33XX + default 0xB0 if BOOTCOUNT_AM33XX_NVMEM + depends on BOOTCOUNT_AM33XX || BOOTCOUNT_AM33XX_NVMEM help Set the magic value used for the boot counter. diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile index
[PATCH v2 15/18] drivers: video: hx8238 fix build bug
From: Gireesh Hiremath
update panel driver hx8238
fix build bug
Signed-off-by: Gireesh Hiremath
---
drivers/video/Makefile | 2 +-
drivers/video/hx8238d.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 933f06e9d8..1c534a6f9a 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi-host-uclass.o
obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o
obj-$(CONFIG_DM_VIDEO) += video_bmp.o
obj-$(CONFIG_PANEL) += panel-uclass.o
-obj-$(CONFIG_PANEL_HX8238D) += hx8238d.o
+obj-$(CONFIG_DM_PANEL_HX8238D) += hx8238d.o
obj-$(CONFIG_SIMPLE_PANEL) += simple_panel.o
endif
diff --git a/drivers/video/hx8238d.c b/drivers/video/hx8238d.c
index f7e7753a53..6ee97cb4ff 100644
--- a/drivers/video/hx8238d.c
+++ b/drivers/video/hx8238d.c
@@ -191,7 +191,7 @@ U_BOOT_DRIVER(hx8238d) = {
.name = "hx8238d",
.id = UCLASS_PANEL,
.of_match = hx8238d_ids,
- .ofdata_to_platdata = hx8238d_ofdata_to_platdata,
+ .of_to_plat = hx8238d_ofdata_to_platdata,
.probe = hx8238d_probe,
- .priv_auto_alloc_size = sizeof(struct hx8238d_priv),
+ .priv_auto = sizeof(struct hx8238d_priv),
};
--
2.20.1
[PATCH v2 14/18] am335x, guardian: configs: Enable display config
From: Gireesh Hiremath -Enable configuration for display driver -Disable support for SPL GPIO, CMD LED & SPL GPIO Signed-off-by: Gireesh Hiremath --- configs/am335x_guardian_defconfig | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index 4620c2b6aa..6056b78991 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SPL_GPIO_SUPPORT=y +# CONFIG_SPL_GPIO_SUPPORT is not set CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x4 @@ -53,8 +53,7 @@ CONFIG_CMD_MTD=y CONFIG_CMD_NAND=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_BOOTP_DNS2=y -# CONFIG_CMD_LED is not set +CONFIG_CMD_BMP=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(SPL),256k(SPL.backup1),256k(SPL.backup2),256k(SPL.backup3),1m(u-boot),1m(u-boot.backup1),1m(u-boot-2),1m(u-boot-2.backup1),256k(u-boot-env),256k(u-boot-env.backup1),256k(splash-screen),-(UBI)" @@ -97,6 +96,9 @@ CONFIG_PHY=y CONFIG_NOP_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_SINGLE=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_OMAP3_SPI=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y @@ -109,6 +111,11 @@ CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 CONFIG_USB_ETHER=y +CONFIG_DM_VIDEO=y +CONFIG_DM_PANEL_HX8238D=y +CONFIG_VIDEO_BPP16=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_AM335X_LCD=y CONFIG_SPL_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_SPL_OF_LIBFDT=y -- 2.20.1
[PATCH v2 16/18] am335x, guardian: Enable panel driver Himax HX8238D
From: Gireesh Hiremath
- Enable lcd controller
- Display splash screen
Signed-off-by: Gireesh Hiremath
---
On 06/01/21 9:01 pm, gireesh.hirem...@in.bosch.com wrote:
> diff --git a/board/bosch/guardian/board.c
> b/board/bosch/guardian/board.c index 8b3c82cafd..f3e616d21c 100644
> --- a/board/bosch/guardian/board.c
> +++ b/board/bosch/guardian/board.c
> @@ -79,6 +79,18 @@ void am33xx_spl_board_init(void)
> int mpu_vdd;
> int usb_cur_lim;
>
> + struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
> +
> + /*enable lcd controller related clocks*/
> + u32 *const clk_domains[] = { 0 };
> +
> + u32 *const clk_modules_xre1specific[] = {
> + >lcdclkctrl,
> + >lcdcclkstctrl,
> + 0
> + };
> + do_enable_clocks(clk_domains, clk_modules_xre1specific, 1);
I am worried this is going to effect other platforms. Recently CLK
support is introduced for am33 platforms. Can you use that and get
clocks info from DT.
Thanks and regards,
Lokesh
Hi Lokesh
I removed lcdc clock enabling code from board file and used recently
added CLK & LCD driver support from am33 platforms.
Thanks and regards,
Gireesh Hiremath
arch/arm/dts/am335x-guardian-u-boot.dtsi | 11 +++
arch/arm/dts/am335x-guardian.dts | 8 ++-
arch/arm/mach-omap2/am33xx/Kconfig | 2 +
board/bosch/guardian/board.c | 87 +++-
board/bosch/guardian/mux.c | 3 +-
include/configs/am335x_guardian.h| 11 +++
6 files changed, 119 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/am335x-guardian-u-boot.dtsi
b/arch/arm/dts/am335x-guardian-u-boot.dtsi
index 986f58e664..a1a7913de8 100644
--- a/arch/arm/dts/am335x-guardian-u-boot.dtsi
+++ b/arch/arm/dts/am335x-guardian-u-boot.dtsi
@@ -42,6 +42,17 @@
u-boot,dm-pre-reloc;
};
+ {
+ lcd0: display@0 {
+ compatible = "himax,hx8238d";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ reg = <0>;
+ label = "lcd";
+ spi-max-frequency = <10>;
+ };
+};
+
{
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/am335x-guardian.dts b/arch/arm/dts/am335x-guardian.dts
index 207246b4e0..69bee45848 100644
--- a/arch/arm/dts/am335x-guardian.dts
+++ b/arch/arm/dts/am335x-guardian.dts
@@ -87,7 +87,7 @@
ac-bias = <255>;
ac-bias-intrpt= <0>;
dma-burst-sz = <16>;
- bpp = <24>;
+ bpp = <16>;
bus-width = <16>;
fdd = <0x80>;
sync-edge = <0>;
@@ -247,6 +247,12 @@
{
blue-and-red-wiring = "crossed";
status = "okay";
+
+ port {
+ lcdc_0: endpoint@0 {
+ remote-endpoint = <0>;
+ };
+ };
};
{
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig
b/arch/arm/mach-omap2/am33xx/Kconfig
index 9a98e8a0a9..204975092a 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -94,6 +94,8 @@ config TARGET_AM335X_GUARDIAN
select DM_SERIAL
select DM_GPIO
select DM_USB
+ select DM_VIDEO
+ select DM_PANEL_HX8238D
config TARGET_AM335X_SL50
bool "Support am335x_sl50"
diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c
index 6e6221ca60..03740c08b9 100644
--- a/board/bosch/guardian/board.c
+++ b/board/bosch/guardian/board.c
@@ -25,12 +25,16 @@
#include
#include
#include
-#include
#include
#include
#include
#include
#include
+#include
+#include
+#include
+#include
+#include
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -249,13 +253,94 @@ void lcdbacklight_en(void)
brightness != 0 ? 0x0A : 0x02, 0xFF);
}
+#if IS_ENABLED(CONFIG_AM335X_LCD)
+static void splash_screen(void)
+{
+ struct udevice *video_dev;
+ struct udevice *console_dev;
+ struct video_priv *vid_priv;
+ struct mtd_info *mtd;
+ size_t len;
+ int ret;
+
+ struct mtd_device *mtd_dev;
+ struct part_info *part;
+ u8 pnum;
+
+ ret = uclass_get_device(UCLASS_VIDEO, 0, _dev);
+ if (ret != 0) {
+ debug("video device not found\n");
+ goto exit;
+ }
+
+ vid_priv = dev_get_uclass_priv(video_dev);
+ mtdparts_init();
+
+ if (find_dev_and_part(SPLASH_SCREEN_NAND_PART, _dev, , ))
{
+ debug("Could not find nand partition\n");
+ goto splash_screen_text;
+ }
+
+ mtd = get_nand_dev_by_index(mtd_dev->id->num);
+ if (!mtd) {
+ debug("MTD partition is not valid\n");
+ goto splash_screen_text;
+ }
+
+ len = SPLASH_SCREEN_BMP_FILE_SIZE;
+ ret =
[PATCH v2 10/18] am335x, guardian: configs: set boot delay
From: Gireesh Hiremath - set boot delay to zero, to increase boot speed Signed-off-by: Gireesh Hiremath --- configs/am335x_guardian_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index 2ae7507eff..e47c6aad74 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -17,6 +17,7 @@ CONFIG_ENV_OFFSET_REDUND=0x54 CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="am335x-guardian" CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=0 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_DELAY_STR="d" -- 2.20.1
[PATCH v2 12/18] am335x, guardian: update swi logic
From: Gireesh Hiremath
read boot mode gpio and set the swi status
Signed-off-by: Gireesh Hiremath
---
board/bosch/guardian/board.c | 15 +--
include/configs/am335x_guardian.h | 2 +-
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c
index 12d047b74b..8704806047 100644
--- a/board/bosch/guardian/board.c
+++ b/board/bosch/guardian/board.c
@@ -205,8 +205,19 @@ static void set_bootmode_env(void)
goto err;
}
- value = dm_gpio_get_value(_mode_desc);
- value ? env_set("swi_status", "0") : env_set("swi_status", "1");
+ dm_gpio_set_dir_flags(_mode_desc, GPIOD_IS_IN);
+ udelay(10);
+
+ ret = dm_gpio_get_value(_mode_desc);
+ if (ret == 0) {
+ env_set("swi_status", "1");
+ } else if (ret == 1) {
+ env_set("swi_status", "0");
+ } else {
+ printf("swi status gpio error\n");
+ goto err;
+ }
+
return;
err:
diff --git a/include/configs/am335x_guardian.h
b/include/configs/am335x_guardian.h
index fa6e02d09b..b966df08c6 100644
--- a/include/configs/am335x_guardian.h
+++ b/include/configs/am335x_guardian.h
@@ -68,13 +68,13 @@
"setenv rootflags \"bulk_read,chk_data_crc\"; " \
"setenv ethact usb_ether; " \
"if test \"${swi_status}\" -eq 1; then " \
- "setenv extrabootargs \"swi_attached\"; " \
"if dhcp; then " \
"sleep 1; " \
"if tftp \"${tftp_load_addr}\" \"bootscript.scr\"; then " \
"source \"${tftp_load_addr}\"; " \
"fi; " \
"fi; " \
+ "setenv extrabootargs $extrabootargs \"swi_attached\"; " \
"fi;" \
"run bootcmd_ubifs0;\0" \
"altbootcmd=" \
--
2.20.1
[PATCH v2 13/18] am335x, guardian: Enable backlight
From: Gireesh Hiremath
Enable backlight, set brightness value and dimming frequency
Signed-off-by: Gireesh Hiremath
---
board/bosch/guardian/board.c | 26 ++
include/configs/am335x_guardian.h | 1 +
2 files changed, 27 insertions(+)
diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c
index 8704806047..6e6221ca60 100644
--- a/board/bosch/guardian/board.c
+++ b/board/bosch/guardian/board.c
@@ -224,12 +224,38 @@ err:
env_set("swi_status", "err");
}
+void lcdbacklight_en(void)
+{
+ unsigned long brightness = env_get_ulong("backlight_brightness", 10,
50);
+
+ if (brightness > 99 || brightness == 0)
+ brightness = 99;
+
+ /*
+* Brightness range:
+* WLEDCTRL2 DUTY[6:0]
+*
+* 000 b = 1%
+* 000 0001b = 2%
+* ...
+* 110 0010b = 99%
+* 110 0011b = 100%
+*
+*/
+
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL2,
+ brightness, 0xFF);
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL1,
+ brightness != 0 ? 0x0A : 0x02, 0xFF);
+}
+
int board_late_init(void)
{
#ifdef CONFIG_LED_GPIO
led_default_state();
#endif
set_bootmode_env();
+ lcdbacklight_en();
return 0;
}
#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/include/configs/am335x_guardian.h
b/include/configs/am335x_guardian.h
index b966df08c6..08a9ac950c 100644
--- a/include/configs/am335x_guardian.h
+++ b/include/configs/am335x_guardian.h
@@ -63,6 +63,7 @@
BOOTENV \
GUARDIAN_DEFAULT_PROD_ENV \
"autoload=no\0" \
+ "backlight_brightness=50\0" \
"bootubivol=rootfs\0" \
"distro_bootcmd=" \
"setenv rootflags \"bulk_read,chk_data_crc\"; " \
--
2.20.1
[PATCH v2 07/18] am335x, guardian: Update pinmux configuration
From: Moses Christopher
pinmux update for guardian board
- control ASP Board Power: GPIO, on/off ASP Board Power
- control Coincell Voltage Measurement: GPIO, enable/disable
ADC measurements
- powerOff Device GPIO-PowerOff, cut the PMIC supply
Signed-off-by: Moses Christopher
---
On 06/01/21 9:01 pm, gireesh.hirem...@in.bosch.com wrote:
> From: Moses Christopher
>
> pinmux update for guardian board
Please specify what this pinmux update is about.
Thanks and regards,
Lokesh
Hi Lokesh
Pin update details added.
Thanks and regards,
Gireesh Hiremath
arch/arm/dts/am335x-guardian.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/am335x-guardian.dts b/arch/arm/dts/am335x-guardian.dts
index 7e70a96d25..207246b4e0 100644
--- a/arch/arm/dts/am335x-guardian.dts
+++ b/arch/arm/dts/am335x-guardian.dts
@@ -401,12 +401,12 @@
guardian_interface_pins: pinmux_guardian_interface_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7)
- AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLUP | MUX_MODE7)
AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE7)
- AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLUP | MUX_MODE7)
+ AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE7)
AM33XX_IOPAD(0x90c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x91c, PIN_INPUT | MUX_MODE7)
--
2.20.1
[PATCH v2 11/18] am335x, guardian: configs: cmd : disable spl command
From: Gireesh Hiremath - disable support for spl command Signed-off-by: Gireesh Hiremath --- configs/am335x_guardian_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index e47c6aad74..4620c2b6aa 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -40,7 +40,7 @@ CONFIG_SPL_NET_VCI_STRING="Guardian U-Boot SPL" CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_ETHER=y -CONFIG_CMD_SPL=y +# CONFIG_CMD_SPL is not set CONFIG_CMD_SPL_NAND_OFS=0x0 CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set -- 2.20.1
[PATCH v2 05/18] am335x, guardian: configs: cmd: add memtest configs
From: Gireesh Hiremath - Add mtest, meminfo commands Signed-off-by: Gireesh Hiremath --- configs/am335x_guardian_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index a96cdf734c..2ae7507eff 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -43,6 +43,8 @@ CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x0 CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y -- 2.20.1
[PATCH v2 09/18] am335x, guardian: code cleanup and boot optimization
From: Gireesh Hiremath
- remove redundant headers and boot modes from board file
Signed-off-by: Gireesh Hiremath
---
board/bosch/guardian/board.c | 21 -
1 file changed, 21 deletions(-)
diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c
index 9429454a74..12d047b74b 100644
--- a/board/bosch/guardian/board.c
+++ b/board/bosch/guardian/board.c
@@ -9,19 +9,14 @@
*/
#include
-#include
#include
-#include
#include
#include
#include
-#include
#include
-#include
#include
#include
#include
-#include
#include
#include
#include
@@ -193,27 +188,11 @@ int board_init(void)
#ifdef CONFIG_BOARD_LATE_INIT
static void set_bootmode_env(void)
{
- char *boot_device_name = NULL;
char *boot_mode_gpio = "gpio@44e07000_14";
int ret;
- int value;
struct gpio_desc boot_mode_desc;
- switch (gd->arch.omap_boot_device) {
- case BOOT_DEVICE_NAND:
- boot_device_name = "nand";
- break;
- case BOOT_DEVICE_USBETH:
- boot_device_name = "usbeth";
- break;
- default:
- break;
- }
-
- if (boot_device_name)
- env_set("boot_device", boot_device_name);
-
ret = dm_gpio_lookup_name(boot_mode_gpio, _mode_desc);
if (ret) {
printf("%s is not found\n", boot_mode_gpio);
--
2.20.1
[PATCH v2 08/18] am335x, guardian: set environment variable autoload to no
From: Gireesh Hiremath
autoload: if set to "no" then rarpb, bootp or dhcp commands will
just perform a configuration lookup from the BOOTP / DHCP server,
but not try to load any image using TFTP
Signed-off-by: Gireesh Hiremath
---
include/configs/am335x_guardian.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/am335x_guardian.h
b/include/configs/am335x_guardian.h
index acf4d4ab65..fa6e02d09b 100644
--- a/include/configs/am335x_guardian.h
+++ b/include/configs/am335x_guardian.h
@@ -62,9 +62,9 @@
MEM_LAYOUT_ENV_SETTINGS \
BOOTENV \
GUARDIAN_DEFAULT_PROD_ENV \
+ "autoload=no\0" \
"bootubivol=rootfs\0" \
"distro_bootcmd=" \
- "setenv autoload no; " \
"setenv rootflags \"bulk_read,chk_data_crc\"; " \
"setenv ethact usb_ether; " \
"if test \"${swi_status}\" -eq 1; then " \
--
2.20.1
[PATCH v2 03/18] am335x, guardian: configs: add ubi fastmap support
From: Gireesh Hiremath - Trigger fastmap automatically Signed-off-by: Gireesh Hiremath --- configs/am335x_guardian_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index 791bbba26e..a96cdf734c 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -87,6 +87,7 @@ CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x10 CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x20 CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 CONFIG_PHYLIB=y CONFIG_DM_ETH=y CONFIG_PHY=y -- 2.20.1
[PATCH v2 06/18] am335x, guardian: add memtest address range
From: Gireesh Hiremath - Add default mem start address as 0x8000 - Add defauly mem end address as 0x8100 - Implies default test runs for first 16MiB of DRAM Signed-off-by: Gireesh Hiremath --- include/configs/am335x_guardian.h | 4 1 file changed, 4 insertions(+) diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h index fe36e34c7d..acf4d4ab65 100644 --- a/include/configs/am335x_guardian.h +++ b/include/configs/am335x_guardian.h @@ -22,6 +22,10 @@ #define V_OSCK 2400 /* Clock output from T2 */ #define V_SCLK (V_OSCK) +/* mem test config for first 16MiB */ +#define CONFIG_SYS_MEMTEST_START 0x8000 +#define CONFIG_SYS_MEMTEST_END 0x8100 + #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #ifndef CONFIG_SPL_BUILD -- 2.20.1
[PATCH v2 01/18] am335x, guardian: configs: Enable clock driver
From: Gireesh Hiremath Enable TI clock driver support for guardian board Signed-off-by: Gireesh Hiremath --- configs/am335x_guardian_defconfig | 7 +++ 1 file changed, 7 insertions(+) diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index d412311cec..791bbba26e 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -69,6 +69,13 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_SPL_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_CLK=y +CONFIG_CLK_CCF=y +CONFIG_CLK_TI_AM3_DPLL=y +CONFIG_CLK_TI_CTRL=y +CONFIG_CLK_TI_DIVIDER=y +CONFIG_CLK_TI_GATE=y +CONFIG_CLK_TI_MUX=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y -- 2.20.1
[PATCH v2 02/18] am335x, guardian: mem: Add board dependent mem values
From: Moses Christopher - Add mem-guardian.h derived from am33xx/mem.h * Add GPMC config values optimized for Bosch Guardian Board * NAND Chip used by Bosch Guardian Board is Micron MT29F4G08ABBFA Signed-off-by: Moses Christopher --- On 06/01/21 9:01 pm, gireesh.hirem...@in.bosch.com wrote: > From: Moses Christopher > > - Add mem-guardian.h derived from am33xx/mem.h > > * Add GPMC config values optimized for Bosch Guardian Board > * NAND Chip used by Bosch Guardian Board is Micron MT29F4G08ABBFA > > Signed-off-by: Moses Christopher > Just wondering, Isn't NAND framework moved to Driver model and Device-tree model? In that case, these values should be obtained from DT. Thanks and regards, Lokesh Hi Lokesh NAND framework doesn't seems moved to driver model so we obtained values in mem-guardian.h Thanks and regards, Gireesh Hiremath .../include/asm/arch-am33xx/mem-guardian.h| 63 +++ arch/arm/mach-omap2/am33xx/board.c| 4 ++ arch/arm/mach-omap2/mem-common.c | 4 ++ board/bosch/guardian/board.c | 2 +- 4 files changed, 72 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-am33xx/mem-guardian.h diff --git a/arch/arm/include/asm/arch-am33xx/mem-guardian.h b/arch/arm/include/asm/arch-am33xx/mem-guardian.h new file mode 100644 index 00..e864a0fd36 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mem-guardian.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, + * + * (C) Copyright 2020 + * Robert Bosch Power Tools GmbH + * + * Author + * Moses Christopher + * + * Copied from: + * arch/arm/include/asm/arch-am33xx/mem.h + * + * Initial Code from: + * Mansoor Ahamed + * Richard Woodruff + */ + +#ifndef _MEM_GUARDIAN_H_ +#define _MEM_GUARDIAN_H_ + +/* + * GPMC settings - + * Definitions is as per the following format + * #define _GPMC_CONFIG + * Where: + * PART is the part name e.g. M_NAND - Micron Nand Flash + * x is GPMC config registers from 1 to 7 (there will be 7 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. + * + * The following values are optimized for improving the NAND Read speed + * They are applicable and tested for Bosch Guardian Board. + * Read Speeds rose from 1.5MiBs to over 7.6MiBs + * + * Currently valid part Names are (PART): + * M_NAND - Micron NAND + */ +#define GPMC_SIZE_256M 0x0 +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#define M_NAND_GPMC_CONFIG10x0800 +#define M_NAND_GPMC_CONFIG20x00030300 +#define M_NAND_GPMC_CONFIG30x00030300 +#define M_NAND_GPMC_CONFIG40x02000201 +#define M_NAND_GPMC_CONFIG50x00030303 +#define M_NAND_GPMC_CONFIG60x00C0 +#define M_NAND_GPMC_CONFIG70x0008 + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#define DBG_MPDB 6 + +#endif /* endif _MEM_GUARDIAN_H_ */ diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 62178f1e70..4bf0535e3c 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -23,7 +23,11 @@ #include #include #include +#if IS_ENABLED(CONFIG_TARGET_AM335X_GUARDIAN) +#include +#else #include +#endif #include #include #include diff --git a/arch/arm/mach-omap2/mem-common.c b/arch/arm/mach-omap2/mem-common.c index 50d5f3e9eb..2dcf0cf9c3 100644 --- a/arch/arm/mach-omap2/mem-common.c +++ b/arch/arm/mach-omap2/mem-common.c @@ -15,7 +15,11 @@ #include #include #include +#if IS_ENABLED(CONFIG_TARGET_AM335X_GUARDIAN) +#include +#else #include +#endif #include #include #include diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c index 113838f8b7..9429454a74 100644 --- a/board/bosch/guardian/board.c +++ b/board/bosch/guardian/board.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include #include -- 2.20.1
[PATCH v2 04/18] am335x, guardian: set tftp_load_addr in environment
From: Moses Christopher Set tftp_load_addr to 0x8200 in MEM_LAYOUT_ENV_SETTINGS Signed-off-by: Moses Christopher --- include/configs/am335x_guardian.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h index c34c07a493..fe36e34c7d 100644 --- a/include/configs/am335x_guardian.h +++ b/include/configs/am335x_guardian.h @@ -29,6 +29,7 @@ #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x8000\0" \ "pxefile_addr_r=0x8010\0" \ + "tftp_load_addr=0x8200\0" \ "kernel_addr_r=0x8200\0" \ "fdt_addr_r=0x8800\0" \ "ramdisk_addr_r=0x8808\0" \ -- 2.20.1
[PATCH v2 00/18] am335x, guardian: update board specific changes
From: Gireesh Hiremath add support for updated TI clock driver, backlight, splash screen, swi logic, add ubi fastmap support, update pinmux, code clean up address the v1 review comments like: split board changes and defconfig changes into separate patches, adding clock support Gireesh Hiremath (15): am335x, guardian: configs: Enable clock driver for guardian am335x, guardian: configs: add ubi fastmap support am335x, guardian: configs: cmd: add memtest configs am335x, guardian: add memtest address range am335x, guardian: set environment variable autoload to no am335x, guardian: code cleanup and boot optimization am335x, guardian: configs: set boot delay am335x, guardian: configs: cmd : disable spl command am335x, guardian: update swi logic am335x, guardian: Enable backlight am335x, guardian: configs: Enable display config drivers: video: hx8238 fix build bug am335x, guardian: Enable panel driver Himax HX8238D am335x, guardian: software update available status is stored in AM3352 RTC scracth register am335x, guardian: configs: Enable bootcount nvmem support Moses Christopher (3): am335x, guardian: mem: Add board dependent mem values am335x, guardian: set tftp_load_addr in environment am335x, guardian: Update pinmux configuration arch/arm/dts/am335x-guardian-u-boot.dtsi | 11 ++ arch/arm/dts/am335x-guardian.dts | 14 +- .../include/asm/arch-am33xx/mem-guardian.h| 63 arch/arm/mach-omap2/am33xx/Kconfig| 2 + arch/arm/mach-omap2/am33xx/board.c| 4 + arch/arm/mach-omap2/mem-common.c | 4 + board/bosch/guardian/board.c | 151 +++--- board/bosch/guardian/mux.c| 3 +- configs/am335x_guardian_defconfig | 27 +++- drivers/bootcount/Kconfig | 27 +++- drivers/bootcount/Makefile| 1 + drivers/bootcount/bootcount_nvmem.c | 57 +++ drivers/video/Makefile| 2 +- drivers/video/hx8238d.c | 4 +- include/configs/am335x_guardian.h | 21 ++- 15 files changed, 349 insertions(+), 42 deletions(-) create mode 100644 arch/arm/include/asm/arch-am33xx/mem-guardian.h create mode 100644 drivers/bootcount/bootcount_nvmem.c -- 2.20.1
Re: [PATCH] efi_loader: simplify tcg2_create_digest()
On 22.04.21 13:32, Ilias Apalodimas wrote:
> Bumping the digest list count, for all supported algorithms, can be
> calculated outside of the individual switch statements. So let's do that
> for every loop iteration instead and simplify the code a bit.
>
> Signed-off-by: Ilias Apalodimas
Reviewed-by: Heinrich Schuchardt
> ---
> lib/efi_loader/efi_tcg2.c | 5 +
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c
> index d5eca68769b0..94e8f22bbb69 100644
> --- a/lib/efi_loader/efi_tcg2.c
> +++ b/lib/efi_loader/efi_tcg2.c
> @@ -535,30 +535,27 @@ static efi_status_t tcg2_create_digest(const u8 *input,
> u32 length,
> sha1_starts();
> sha1_update(, input, length);
> sha1_finish(, final);
> - digest_list->count++;
> break;
> case TPM2_ALG_SHA256:
> sha256_starts(_256);
> sha256_update(_256, input, length);
> sha256_finish(_256, final);
> - digest_list->count++;
> break;
> case TPM2_ALG_SHA384:
> sha384_starts(_512);
> sha384_update(_512, input, length);
> sha384_finish(_512, final);
> - digest_list->count++;
> break;
> case TPM2_ALG_SHA512:
> sha512_starts(_512);
> sha512_update(_512, input, length);
> sha512_finish(_512, final);
> - digest_list->count++;
> break;
> default:
> EFI_PRINT("Unsupported algorithm %x\n", hash_alg);
> return EFI_INVALID_PARAMETER;
> }
> + digest_list->count++;
> digest_list->digests[i].hash_alg = hash_alg;
> memcpy(_list->digests[i].digest, final,
> (u32)alg_to_len(hash_alg));
> }
>
[PATCH] efi_loader: simplify tcg2_create_digest()
Bumping the digest list count, for all supported algorithms, can be
calculated outside of the individual switch statements. So let's do that
for every loop iteration instead and simplify the code a bit.
Signed-off-by: Ilias Apalodimas
---
lib/efi_loader/efi_tcg2.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c
index d5eca68769b0..94e8f22bbb69 100644
--- a/lib/efi_loader/efi_tcg2.c
+++ b/lib/efi_loader/efi_tcg2.c
@@ -535,30 +535,27 @@ static efi_status_t tcg2_create_digest(const u8 *input,
u32 length,
sha1_starts();
sha1_update(, input, length);
sha1_finish(, final);
- digest_list->count++;
break;
case TPM2_ALG_SHA256:
sha256_starts(_256);
sha256_update(_256, input, length);
sha256_finish(_256, final);
- digest_list->count++;
break;
case TPM2_ALG_SHA384:
sha384_starts(_512);
sha384_update(_512, input, length);
sha384_finish(_512, final);
- digest_list->count++;
break;
case TPM2_ALG_SHA512:
sha512_starts(_512);
sha512_update(_512, input, length);
sha512_finish(_512, final);
- digest_list->count++;
break;
default:
EFI_PRINT("Unsupported algorithm %x\n", hash_alg);
return EFI_INVALID_PARAMETER;
}
+ digest_list->count++;
digest_list->digests[i].hash_alg = hash_alg;
memcpy(_list->digests[i].digest, final,
(u32)alg_to_len(hash_alg));
}
--
2.31.0
Re: [PATCH] Revert "usb: kbd: destroy device after console is stopped"
On Thu, Apr 22, 2021 at 12:11:44PM +0100, Peter Robinson wrote: > On Thu, Apr 22, 2021 at 11:52 AM Andy Shevchenko > wrote: > > > > On Thu, Apr 22, 2021 at 10:19:10AM +0100, Peter Robinson wrote: > > > > Thanks for the report. > > > > > Reverts commit eb5fd9e46c1, it causes ARMv7 devices to stop booting > > > Linux when a USB keyboard is attached. The kernels starts but there's > > > no output. Reverting it makes things work again. > > > > It's not good. When we revert, we introduce another (I consider more > > serious) > > bug. > > Sure, looking at the fixes tags I figured as much, but it also causes > regressions itself. I figured sending a revert would at least start > the discussion off. > > > > Signed-off-by: Peter Robinson > > > Cc: Nicolas Saenz Julienne > > > Cc: Andy Shevchenko > > > --- > > > > > > This has caused us issues on a number of ARMv7 deviices. I'm not sure > > > why specifically ARMv7 because it happens on a RPi3 running Fedora > > > armhfp, but doesn't happen on aarch64. Issue seen on RPis, Cubietruck, > > > and others. > > > > Can we conduct a bit of investigation here? > > Is it using ATAGs or command line? How Linux kernel gets its parameters? > > I believe command line, I've been testing booting using UEFI. TBH I'm > unsure why I see the problem on ARMv7 and not using aarchc64 on the > same device. And what is the U-Boot environment in both cases? (Can you share it somewhere?) -- With Best Regards, Andy Shevchenko
Re: [PATCH] Revert "usb: kbd: destroy device after console is stopped"
On Thu, Apr 22, 2021 at 12:11:44PM +0100, Peter Robinson wrote: > On Thu, Apr 22, 2021 at 11:52 AM Andy Shevchenko > wrote: > > On Thu, Apr 22, 2021 at 10:19:10AM +0100, Peter Robinson wrote: ... > > > This has caused us issues on a number of ARMv7 deviices. I'm not sure > > > why specifically ARMv7 because it happens on a RPi3 running Fedora > > > armhfp, but doesn't happen on aarch64. Issue seen on RPis, Cubietruck, > > > and others. > > > > Can we conduct a bit of investigation here? > > Is it using ATAGs or command line? How Linux kernel gets its parameters? > > I believe command line, I've been testing booting using UEFI. TBH I'm > unsure why I see the problem on ARMv7 and not using aarchc64 on the > same device. What is the command line in both cases? (I'm not so familiar with ARM.aarch64 boards, but does it mean that the hardware is absolutely the same, just the CPU mode is different?) -- With Best Regards, Andy Shevchenko
Re: [PATCH] Revert "usb: kbd: destroy device after console is stopped"
On Thu, Apr 22, 2021 at 11:52 AM Andy Shevchenko wrote: > > On Thu, Apr 22, 2021 at 10:19:10AM +0100, Peter Robinson wrote: > > Thanks for the report. > > > Reverts commit eb5fd9e46c1, it causes ARMv7 devices to stop booting > > Linux when a USB keyboard is attached. The kernels starts but there's > > no output. Reverting it makes things work again. > > It's not good. When we revert, we introduce another (I consider more serious) > bug. Sure, looking at the fixes tags I figured as much, but it also causes regressions itself. I figured sending a revert would at least start the discussion off. > > Signed-off-by: Peter Robinson > > Cc: Nicolas Saenz Julienne > > Cc: Andy Shevchenko > > --- > > > > This has caused us issues on a number of ARMv7 deviices. I'm not sure > > why specifically ARMv7 because it happens on a RPi3 running Fedora > > armhfp, but doesn't happen on aarch64. Issue seen on RPis, Cubietruck, > > and others. > > Can we conduct a bit of investigation here? > Is it using ATAGs or command line? How Linux kernel gets its parameters? I believe command line, I've been testing booting using UEFI. TBH I'm unsure why I see the problem on ARMv7 and not using aarchc64 on the same device.
Re: [PATCH] Revert "usb: kbd: destroy device after console is stopped"
On Thu, Apr 22, 2021 at 10:19:10AM +0100, Peter Robinson wrote: Thanks for the report. > Reverts commit eb5fd9e46c1, it causes ARMv7 devices to stop booting > Linux when a USB keyboard is attached. The kernels starts but there's > no output. Reverting it makes things work again. It's not good. When we revert, we introduce another (I consider more serious) bug. > Signed-off-by: Peter Robinson > Cc: Nicolas Saenz Julienne > Cc: Andy Shevchenko > --- > > This has caused us issues on a number of ARMv7 deviices. I'm not sure > why specifically ARMv7 because it happens on a RPi3 running Fedora > armhfp, but doesn't happen on aarch64. Issue seen on RPis, Cubietruck, > and others. Can we conduct a bit of investigation here? Is it using ATAGs or command line? How Linux kernel gets its parameters? -- With Best Regards, Andy Shevchenko
Re: [PATCH V2 24/24] ARM: imx8m: verdin-imx8mm: Enable USB Host support
Hi Marek, I have the same issue on my iMX8MM based board. Are you continue working on the patch for iMX8MM or should I dig into this problem? I'm asking this just for not duplicating efforts. So if you are not working on this then I'll see if I can properly retrieve the necessary patches to make this work. I think something is missing from previous patch set https://lists.denx.de/pipermail/u-boot/2020-September/426757.html Yours, Paul Tim Harvey 於 2021/4/20 上午8:33 寫道: > On Sun, Apr 11, 2021 at 9:35 AM Marek Vasut wrote: >> Enable USB host support on MX8MM Verdin. >> >> Signed-off-by: Marek Vasut >> Cc: Marcel Ziswiler >> Cc: Max Krummenacher >> Cc: Oleksandr Suvorov >> --- >> V2: No change >> --- >> configs/verdin-imx8mm_defconfig | 8 +++- >> include/configs/verdin-imx8mm.h | 5 + >> 2 files changed, 12 insertions(+), 1 deletion(-) >> >> diff --git a/configs/verdin-imx8mm_defconfig >> b/configs/verdin-imx8mm_defconfig >> index ea0b5978f1..c8c3420b6a 100644 >> --- a/configs/verdin-imx8mm_defconfig >> +++ b/configs/verdin-imx8mm_defconfig >> @@ -37,7 +37,6 @@ CONFIG_SPL_BOARD_INIT=y >> CONFIG_SPL_SEPARATE_BSS=y >> CONFIG_SPL_I2C_SUPPORT=y >> CONFIG_SPL_POWER_SUPPORT=y >> -CONFIG_SPL_USB_HOST_SUPPORT=y >> CONFIG_SPL_WATCHDOG_SUPPORT=y >> CONFIG_SYS_PROMPT="Verdin iMX8MM # " >> # CONFIG_BOOTM_NETBSD is not set >> @@ -50,6 +49,7 @@ CONFIG_CMD_FUSE=y >> CONFIG_CMD_GPIO=y >> CONFIG_CMD_I2C=y >> CONFIG_CMD_MMC=y >> +CONFIG_CMD_USB=y >> CONFIG_CMD_CACHE=y >> CONFIG_CMD_UUID=y >> CONFIG_CMD_REGULATOR=y >> @@ -89,6 +89,8 @@ CONFIG_MII=y >> CONFIG_PINCTRL=y >> CONFIG_SPL_PINCTRL=y >> CONFIG_PINCTRL_IMX8M=y >> +CONFIG_POWER_DOMAIN=y >> +CONFIG_IMX8M_POWER_DOMAIN=y >> CONFIG_DM_PMIC=y >> CONFIG_SPL_DM_PMIC_PCA9450=y >> CONFIG_DM_PMIC_PFUZE100=y >> @@ -101,5 +103,9 @@ CONFIG_SPL_SYSRESET=y >> CONFIG_SYSRESET_PSCI=y >> CONFIG_SYSRESET_WATCHDOG=y >> CONFIG_DM_THERMAL=y >> +CONFIG_USB=y >> +CONFIG_DM_USB=y >> +# CONFIG_SPL_DM_USB is not set >> +CONFIG_USB_EHCI_HCD=y >> CONFIG_IMX_WATCHDOG=y >> CONFIG_OF_LIBFDT_OVERLAY=y >> diff --git a/include/configs/verdin-imx8mm.h >> b/include/configs/verdin-imx8mm.h >> index 4751bf5a5a..e2a817891c 100644 >> --- a/include/configs/verdin-imx8mm.h >> +++ b/include/configs/verdin-imx8mm.h >> @@ -117,5 +117,10 @@ >> #define FEC_QUIRK_ENET_MAC >> #define IMX_FEC_BASE 0x30BE >> >> +/* USB Configs */ >> +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET >> +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) >> +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 >> + >> #endif /*_VERDIN_IMX8MM_H */ >> >> -- >> 2.30.2 >> > Marek, > > Thanks for your work on USB support for IMX8M! > > I'm attempting to add USB support to the venice board following this > example but I think there are still some things missing from the dt to > make this work. I find that mx6_parse_dt_adds failes; Looks like it is > required to have an alias that points to the phy but then it fails > because the phy doesn't have a reg. Also, it would see the > CONFIG_MXC_USB_PORTSC is no longer needed as that is now the default. > > Best regards, > > Tim OpenPGP_signature Description: OpenPGP digital signature
Re: [PATCH V2 1/2] mmc: add OpenPiton mmc support
Dear Jaehoon,
Many thanks again for reviewing our code. I’ll reformat and refactor the patch
as you have kindly suggested. We really appreciate your enthusiasm in this
matter.
Best Regards,
Tianrui
From: Jaehoon Chung
Sent: Thursday, April 22, 2021 2:55 PM
To: Tianrui Wei; u-boot@lists.denx.de
Cc: ycli...@andestech.com; r...@andestech.com; peng@nxp.com;
jbalk...@ucsb.edu
Subject: Re: [PATCH V2 1/2] mmc: add OpenPiton mmc support
Dear Tianrui,
On 4/22/21 3:19 PM, Tianrui Wei wrote:
> This patch adds mmc support for OpenPiton.
>
> Signed-off-by: Tianrui Wei
> Signed-off-by: Jonathan Balkind
>
> ---
>
> drivers/mmc/Kconfig | 6 +
> drivers/mmc/Makefile| 1 +
> drivers/mmc/piton_mmc.c | 177 +
> 3 files changed, 184 insertions(+)
> create mode 100644 drivers/mmc/piton_mmc.c
>
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index 14d79139..41822c39 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -707,6 +707,12 @@ config MMC_SUNXI_HAS_MODE_SWITCH
> bool
> depends on MMC_SUNXI
>
> +config MMC_PITON
> + bool "MMC support for openpiton SoC"
> + depends on DM_MMC && BLK
> + help
> +This driver enables sd card support in U-Boot port for openpiton
> +
> config GENERIC_ATMEL_MCI
> bool "Atmel Multimedia Card Interface support"
> depends on DM_MMC && BLK && ARCH_AT91
> diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
> index 1c849cba..698dfe05 100644
> --- a/drivers/mmc/Makefile
> +++ b/drivers/mmc/Makefile
> @@ -71,6 +71,7 @@ obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o
> obj-$(CONFIG_MMC_SDHCI_ZYNQ) += zynq_sdhci.o
>
> obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
> +obj-$(CONFIG_MMC_PITON) += piton_mmc.o
> obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o
> obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o
> obj-$(CONFIG_MMC_BCM2835)+= bcm2835_sdhost.o
> diff --git a/drivers/mmc/piton_mmc.c b/drivers/mmc/piton_mmc.c
> new file mode 100644
> index ..f2ceb87f
> --- /dev/null
> +++ b/drivers/mmc/piton_mmc.c
> @@ -0,0 +1,177 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2009 SAMSUNG Electronics
> + * Minkyu Kang
> + * Jaehoon Chung
> + * Portions Copyright 2011-2019 NVIDIA Corporation
> + * Portions Copyright 2021 Tianrui Wei
> + * Tianrui Wei
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +struct piton_mmc_plat {
> + struct mmc_config cfg;
> + struct mmc mmc;
> +};
> +
> +struct piton_mmc_priv {
> + u64 piton_mmc_base_addr; /* peripheral id */
> +};
> +
> +/*
> + * see mmc_read_blocks to see how it is used.
> + * start block is hidden at cmd->arg
> + * also, initialize the block size at init
> + */
> +static int piton_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
> +
> struct mmc_data *data)
> +{
> + // check first if this is a pure command
Remove all "//" comment.
If you want to add some comment, add comment with "/* *"
e.g)
/* Check first if this is a pure command */
> + if (data == NULL) {
> + return 0;
> + }
> +
> + // byte count counts all the bytes required for this command
Not need. Remove, plz.
> + u64 byte_cnt = data->blocks * data->blocksize;
> + // get which block in mmc card to start from
Ditto
> + u64 start_block = cmd->cmdarg;
> + // buff points to the address we store the data stored at mmc card
Ditto.
> + unsigned *buff = (unsigned int *) data->dest;
> +
> + struct piton_mmc_priv *priv = dev_get_priv(dev);
> + // start address denotes the absolute address where the transmission
> start
Ditto.
> + u64 start_addr = priv->piton_mmc_base_addr + (start_block);
> +
> + /* if there is a read */
> + if (data->flags & MMC_DATA_READ) {
> + for (u64 i = 0; i < byte_cnt; i += 4) {
> + *(buff) = readl((void *)(start_addr + i));
> + buff++;
> + }
> + } else {
> + /* else there is a write
> + * we don't handle write, so error right away
> + */
> + return -ENODEV;
> + }
> +
> + return 0;
> +}
> +
> +static int piton_mmc_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct piton_mmc_priv *priv = dev_get_priv(dev);
> + struct piton_mmc_plat *plat = dev_get_platdata(dev);
> + struct mmc_config *cfg;
> + struct mmc *mmc;
> + /* fill in device description */
> + struct blk_desc *bdesc;
> +
> + priv->piton_mmc_base_addr = dev_read_addr(dev);
> + cfg = >cfg;
> + cfg->name = "PITON MMC";
> + cfg->host_caps = MMC_MODE_8BIT;
Re: [PATCH] Makefile: fix generation of defaultenv.h from empty initial file
Hi Rasmus,
Thanks for the patch, I've tested it.
On Thu, Apr 22, 2021 at 10:44 AM Rasmus Villemoes
wrote:
>
> When CONFIG_USE_DEFAULT_ENV_FILE=y and the file
> CONFIG_DEFAULT_ENV_FILE is empty (or at least doesn't contain any
> non-comment, non-empty lines), we end up feeding nothing into xxd,
> which in turn then outputs nothing. Then blindly appending ", 0x00"
> means that we end up trying to compile (roughly)
>
> const char defaultenv[] = { , 0x00 }
>
> which is of course broken.
>
> To fix that, change the frobbing of the text file so that we always
> end up printing an extra empty line (which gets turned into that extra
> nul byte we need) - that corresponds better to the binary format
> consisting of a series of key=val nul terminated strings, terminated
> by an empty string.
>
> Reported-by: Oleksandr Suvorov
> Signed-off-by: Rasmus Villemoes
Reviewed-by: Oleksandr Suvorov
> ---
> Makefile | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/Makefile b/Makefile
> index 3fc9777b0b..b7af2b936d 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -1854,11 +1854,10 @@ define filechk_timestamp.h
> endef
>
> define filechk_defaultenv.h
> - (grep -v '^#' | \
> -grep -v '^$$' | \
> + ( { grep -v '^#' | grep -v '^$$' || true ; echo '' ; } | \
> tr '\n' '\0' | \
> sed -e 's/\\\x0\s*//g' | \
> -xxd -i ; echo ", 0x00" ; )
> +xxd -i ; )
> endef
>
> define filechk_dt.h
> --
> 2.29.2
>
--
Best regards
Oleksandr Suvorov
Toradex AG
Ebenaustrasse 10 | 6048 Horw | Switzerland | T: +41 41 500 48 00
[PATCH] Revert "usb: kbd: destroy device after console is stopped"
Reverts commit eb5fd9e46c1, it causes ARMv7 devices to stop booting
Linux when a USB keyboard is attached. The kernels starts but there's
no output. Reverting it makes things work again.
Signed-off-by: Peter Robinson
Cc: Nicolas Saenz Julienne
Cc: Andy Shevchenko
---
This has caused us issues on a number of ARMv7 deviices. I'm not sure
why specifically ARMv7 because it happens on a RPi3 running Fedora
armhfp, but doesn't happen on aarch64. Issue seen on RPis, Cubietruck,
and others.
common/usb_kbd.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index afad260d3d..515f37136f 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -622,12 +622,12 @@ int usb_kbd_deregister(int force)
if (dev) {
usb_kbd_dev = (struct usb_device *)dev->priv;
data = usb_kbd_dev->privptr;
+ if (stdio_deregister_dev(dev, force) != 0)
+ return 1;
#if CONFIG_IS_ENABLED(CONSOLE_MUX)
- if (iomux_replace_device(stdin, DEVNAME, force ? "nulldev" :
""))
+ if (iomux_doenv(stdin, env_get("stdin")) != 0)
return 1;
#endif
- if (stdio_deregister_dev(dev, force) != 0)
- return 1;
#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
destroy_int_queue(usb_kbd_dev, data->intq);
#endif
@@ -665,16 +665,16 @@ static int usb_kbd_remove(struct udevice *dev)
goto err;
}
data = udev->privptr;
+ if (stdio_deregister_dev(sdev, true)) {
+ ret = -EPERM;
+ goto err;
+ }
#if CONFIG_IS_ENABLED(CONSOLE_MUX)
- if (iomux_replace_device(stdin, DEVNAME, "nulldev")) {
+ if (iomux_doenv(stdin, env_get("stdin"))) {
ret = -ENOLINK;
goto err;
}
#endif
- if (stdio_deregister_dev(sdev, true)) {
- ret = -EPERM;
- goto err;
- }
#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
destroy_int_queue(udev, data->intq);
#endif
--
2.31.1
[RFC PATCH v7 2/2] riscv: cpu: fu740: clear feature disable CSR
Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual
https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf
Signed-off-by: Green Wan
Reviewed-by: Sean Anderson
Reviewed-by: Bin Meng
Reviewed-by: Rick Chen
---
arch/riscv/cpu/fu740/spl.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/riscv/cpu/fu740/spl.c b/arch/riscv/cpu/fu740/spl.c
index ea0b2283a2..55e30346ff 100644
--- a/arch/riscv/cpu/fu740/spl.c
+++ b/arch/riscv/cpu/fu740/spl.c
@@ -6,6 +6,9 @@
#include
#include
+#include
+
+#define CSR_U74_FEATURE_DISABLE0x7c1
int spl_soc_init(void)
{
@@ -21,3 +24,15 @@ int spl_soc_init(void)
return 0;
}
+
+void harts_early_init(void)
+{
+ /*
+* Feature Disable CSR
+*
+* Clear feature disable CSR to '0' to turn on all features for
+* each core. This operation must be in M-mode.
+*/
+ if (CONFIG_IS_ENABLED(RISCV_MMODE))
+ csr_write(CSR_U74_FEATURE_DISABLE, 0);
+}
--
2.31.0
[RFC PATCH v7 1/2] riscv: cpu: Add callback to init each core
Add a callback harts_early_init() to start.S to allow different riscv
hart perform setup code for each hart as early as possible. Since all
the harts enter the callback, they must be able to run the same
setup.
Signed-off-by: Green Wan
Reviewed-by: Rick Chen
---
arch/riscv/cpu/cpu.c | 11 +++
arch/riscv/cpu/start.S | 6 ++
2 files changed, 17 insertions(+)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 85592f5bee..43c086ca19 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -140,3 +140,14 @@ int arch_early_init_r(void)
{
return riscv_cpu_probe();
}
+
+/**
+ * harts_early_init() - A callback function called by start.S to configure
+ * feature settings of each hart.
+ *
+ * In a multi-core system, memory access shall be careful here, it shall
+ * take care race conditions.
+ */
+__weak void harts_early_init(void)
+{
+}
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 8589509e01..bdd5517bca 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -117,6 +117,12 @@ call_board_init_f_0:
mv sp, a0
#endif
+ /*
+* Configure proprietary settings and customized CRSs of harts
+*/
+call_harts_early_init:
+ jal harts_early_init
+
#ifndef CONFIG_XIP
/*
* Pick hart to initialize global data and run U-Boot. The other harts
--
2.31.0
[RFC PATCH v7 0/2] riscv: cpu: Add callback to init each core
Add a callback interface, harts_early_init() to perform proprietary or customized CRSs configuration for each hart. harts_early_init() is placed after stack of harts are initialized and before main boot hart is picked up. Several conditions should be aware of or avoided are listed: - cannot access gd At the moment, gd hasn't initialized yet. - all operations in harts_early_init() should only affect core itself For example, the operations for board level should be moved to mach_xxx() or board_init_xxx() functions instead. - Common resource need protection if multicore Since all harts might enter harts_early_init() in parallel, common resource need a mechanism to handle race condition. - A reference implementation is added in ./arch/riscv/cpu/cpu.c The implementation is declared with '__weak' and can be overridden. Changelogs: v7 - remove M-mode check in [v6 1/2] - remove 'arch' from title of patch - add Reviewed-by v6 - revised the description in both of commit message and comment [1/2] - moved the implementation of harts_early_init() in [2/2] from board/sifive/unmatched/spl.c to arch/riscv/cpu/fu740/spl.c. and revised commit message v5 - rename riscv_hart_early_init to harts_early_init - rephrase dummy for harts_early_init() to callback but keep current comments not specific for customizing CSRs only. - Fix nit in [2/2] and add reviewed-by v4 - Revising the comments for riscv_hart_early_init() in [1/2] - Remove unnecessary braces and add reviewed-by in [2/2] Green Wan (2): riscv: cpu: Add callback to init each core riscv: cpu: fu740: clear feature disable CSR arch/riscv/cpu/cpu.c | 11 +++ arch/riscv/cpu/fu740/spl.c | 15 +++ arch/riscv/cpu/start.S | 6 ++ 3 files changed, 32 insertions(+) -- 2.31.0
[PATCH v7 8/8] drivers: net: macb: add fu740 support
From: David Abdurachmanov
Add fu740 support to macb ethernet driver
There is a PLL HW quirk in FU740. The VSC8541XMV-02 specification
requires 125 +/-0.0125 Mhz. But the most close value can be output
by PLL is 125.125 MHz and out of VSC8541XMV-02 spec.
Signed-off-by: David Abdurachmanov
Signed-off-by: Green Wan
Reviewed-by: Ramon Fried
Reviewed-by: Bin Meng
---
drivers/net/macb.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 57ea45e2dc..bf70525c54 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -591,8 +591,17 @@ static int macb_sifive_clk_init(struct udevice *dev, ulong
rate)
* 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic
* and output clock on GMII output signal GTX_CLK
* 1 = MII mode. Use MII input signal TX_CLK in TX logic
+*
+* FU740 have a PLL HW quirk. The 125.125 Mhz is actually out of
+* VSC8541XMV-02 specification. The tolerance level is +/-100ppm.
+* Which means the range should be in between 125MHz +/-0.0125.
+* But the most close value can be output by PLL is 125.125 MHz.
*/
- writel(rate != 12500, gemgxl_regs);
+ if (device_is_compatible(dev, "sifive,fu540-c000-gem"))
+ writel(rate != 12500, gemgxl_regs);
+ else if (device_is_compatible(dev, "sifive,fu740-c000-gem"))
+ writel(rate != 125125000, gemgxl_regs);
+
return 0;
}
@@ -1507,6 +1516,8 @@ static const struct udevice_id macb_eth_ids[] = {
{ .compatible = "cdns,zynq-gem" },
{ .compatible = "sifive,fu540-c000-gem",
.data = (ulong)_config },
+ { .compatible = "sifive,fu740-c000-gem",
+ .data = (ulong)_config },
{ .compatible = "microchip,mpfs-mss-gem",
.data = (ulong)_config },
{ }
--
2.31.0
[PATCH v7 7/8] board: sifive: add HiFive Unmatched board support
Add defconfig and board support for HiFive Unmatched. Signed-off-by: Green Wan Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- arch/riscv/Kconfig | 4 + board/sifive/unleashed/Kconfig | 1 + board/sifive/unmatched/Kconfig | 50 +++ board/sifive/unmatched/MAINTAINERS | 9 + board/sifive/unmatched/Makefile| 9 + board/sifive/unmatched/spl.c | 85 + board/sifive/unmatched/unmatched.c | 24 ++ common/spl/Kconfig | 4 +- configs/sifive_unleashed_defconfig | 1 + configs/sifive_unmatched_defconfig | 54 +++ doc/board/sifive/index.rst | 1 + doc/board/sifive/unmatched.rst | 536 + drivers/reset/Kconfig | 2 +- include/configs/sifive-unmatched.h | 85 + 14 files changed, 862 insertions(+), 3 deletions(-) create mode 100644 board/sifive/unmatched/Kconfig create mode 100644 board/sifive/unmatched/MAINTAINERS create mode 100644 board/sifive/unmatched/Makefile create mode 100644 board/sifive/unmatched/spl.c create mode 100644 board/sifive/unmatched/unmatched.c create mode 100644 configs/sifive_unmatched_defconfig create mode 100644 doc/board/sifive/unmatched.rst create mode 100644 include/configs/sifive-unmatched.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 4177253e44..d12a3be72c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -20,6 +20,9 @@ config TARGET_QEMU_VIRT config TARGET_SIFIVE_UNLEASHED bool "Support SiFive Unleashed Board" +config TARGET_SIFIVE_UNMATCHED + bool "Support SiFive Unmatched Board" + config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" @@ -56,6 +59,7 @@ source "board/AndesTech/ax25-ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/unleashed/Kconfig" +source "board/sifive/unmatched/Kconfig" source "board/sipeed/maix/Kconfig" # platform-specific options below diff --git a/board/sifive/unleashed/Kconfig b/board/sifive/unleashed/Kconfig index dbffd59c98..833cbd370d 100644 --- a/board/sifive/unleashed/Kconfig +++ b/board/sifive/unleashed/Kconfig @@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SIFIVE_FU540 select ENV_IS_IN_SPI_FLASH + select RESET_SIFIVE imply CMD_DHCP imply CMD_EXT2 imply CMD_EXT4 diff --git a/board/sifive/unmatched/Kconfig b/board/sifive/unmatched/Kconfig new file mode 100644 index 00..9e2748ce1e --- /dev/null +++ b/board/sifive/unmatched/Kconfig @@ -0,0 +1,50 @@ +if TARGET_SIFIVE_UNMATCHED + +config SYS_BOARD + default "unmatched" + +config SYS_VENDOR + default "sifive" + +config SYS_CPU + default "fu740" + +config SYS_CONFIG_NAME + default "sifive-unmatched" + +config SYS_TEXT_BASE + default 0x8020 if SPL + default 0x8000 if !RISCV_SMODE + default 0x8020 if RISCV_SMODE + +config SPL_TEXT_BASE + default 0x0800 + +config SPL_OPENSBI_LOAD_ADDR + default 0x8000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SIFIVE_FU740 + select SUPPORT_SPL + select RESET_SIFIVE + imply CMD_DHCP + imply CMD_EXT2 + imply CMD_EXT4 + imply CMD_FAT + imply CMD_FS_GENERIC + imply CMD_GPT + imply PARTITION_TYPE_GUID + imply CMD_NET + imply CMD_PING + imply CMD_SF + imply DOS_PARTITION + imply EFI_PARTITION + imply IP_DYN + imply ISO_PARTITION + imply PHY_LIB + imply PHY_MSCC + imply SYSRESET + imply SYSRESET_GPIO + +endif diff --git a/board/sifive/unmatched/MAINTAINERS b/board/sifive/unmatched/MAINTAINERS new file mode 100644 index 00..94c9510bfa --- /dev/null +++ b/board/sifive/unmatched/MAINTAINERS @@ -0,0 +1,9 @@ +SiFive HiFive Unmatched FU740 BOARD +M: Paul Walmsley +M: Pragnesh Patel +M: Green Wan +S: Maintained +F: board/sifive/unmatched/ +F: doc/board/sifive/hifive-unmatched-fu740.rst +F: include/configs/sifive-unmatched.h +F: configs/sifive_unmatched_defconfig diff --git a/board/sifive/unmatched/Makefile b/board/sifive/unmatched/Makefile new file mode 100644 index 00..6308c80d64 --- /dev/null +++ b/board/sifive/unmatched/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2020-2021 SiFive, Inc + +obj-y += unmatched.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c new file mode 100644 index 00..5e1333b09a --- /dev/null +++ b/board/sifive/unmatched/spl.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020-2021 SiFive, Inc + * + * Authors: + * Pragnesh Patel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12)
[PATCH v7 2/8] drivers: clk: add fu740 support
Add fu740 support. One abstract layer is added for supporting multiple chips such as fu540 and fu740. Signed-off-by: Green Wan --- drivers/clk/sifive/Kconfig | 8 +- drivers/clk/sifive/Makefile | 4 +- drivers/clk/sifive/fu540-prci.c | 769 +-- drivers/clk/sifive/fu540-prci.h | 22 + drivers/clk/sifive/fu740-prci.c | 158 +++ drivers/clk/sifive/fu740-prci.h | 22 + drivers/clk/sifive/sifive-prci.c | 733 + drivers/clk/sifive/sifive-prci.h | 323 + 8 files changed, 1286 insertions(+), 753 deletions(-) create mode 100644 drivers/clk/sifive/fu540-prci.h create mode 100644 drivers/clk/sifive/fu740-prci.c create mode 100644 drivers/clk/sifive/fu740-prci.h create mode 100644 drivers/clk/sifive/sifive-prci.c create mode 100644 drivers/clk/sifive/sifive-prci.h diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig index c4d0a1f9b1..20fc004b59 100644 --- a/drivers/clk/sifive/Kconfig +++ b/drivers/clk/sifive/Kconfig @@ -6,11 +6,11 @@ config CLK_SIFIVE help SoC drivers for SiFive Linux-capable SoCs. -config CLK_SIFIVE_FU540_PRCI - bool "PRCI driver for SiFive FU540 SoCs" +config CLK_SIFIVE_PRCI + bool "PRCI driver for SiFive SoCs" depends on CLK_SIFIVE select CLK_ANALOGBITS_WRPLL_CLN28HPC help Supports the Power Reset Clock interface (PRCI) IP block found in - FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC, - enable this driver. + FU540/FU740 SoCs. If this kernel is meant to run on a SiFive FU540/ + FU740 SoCs, enable this driver. diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile index b224279afb..51348b1ddc 100644 --- a/drivers/clk/sifive/Makefile +++ b/drivers/clk/sifive/Makefile @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI)+= fu540-prci.o +obj-y += sifive-prci.o + +obj-$(CONFIG_CLK_SIFIVE_PRCI) += fu540-prci.o fu740-prci.o diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index b3882d0b77..ceb2c6fab0 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -5,6 +5,8 @@ * Copyright (C) 2018 SiFive, Inc. * Wesley Terpstra * Paul Walmsley + * Zong Li + * Pragnesh Patel * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -15,632 +17,48 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * The FU540 PRCI implements clock and reset control for the SiFive - * FU540-C000 chip. This driver assumes that it has sole control - * over all PRCI resources. - * - * This driver is based on the PRCI driver written by Wesley Terpstra. - * - * Refer, commit 999529edf517ed75b56659d456d221b2ee56bb60 of: - * https://github.com/riscv/riscv-linux - * * References: * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset" */ -#include -#include -#include -#include -#include -#include -#include -#include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects: - * hfclk and rtcclk - */ -#define EXPECTED_CLK_PARENT_COUNT 2 - -/* - * Register offsets and bitmasks - */ - -/* COREPLLCFG0 */ -#define PRCI_COREPLLCFG0_OFFSET0x4 -#define PRCI_COREPLLCFG0_DIVR_SHIFT0 -#define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT) -#define PRCI_COREPLLCFG0_DIVF_SHIFT6 -#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT) -#define PRCI_COREPLLCFG0_DIVQ_SHIFT15 -#define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT) -#define PRCI_COREPLLCFG0_RANGE_SHIFT 18 -#define PRCI_COREPLLCFG0_RANGE_MASK(0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT) -#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24 -#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT) -#define PRCI_COREPLLCFG0_FSE_SHIFT 25 -#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT) -#define PRCI_COREPLLCFG0_LOCK_SHIFT31 -#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT) - -/* COREPLLCFG1 */ -#define PRCI_COREPLLCFG1_OFFSET0x8 -#define PRCI_COREPLLCFG1_CKE_SHIFT 31 -#define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT) - -/* DDRPLLCFG0 */ -#define PRCI_DDRPLLCFG0_OFFSET 0xc -#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0 -#define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT) -#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6 -#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT) -#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15 -#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 <<
[PATCH v7 6/8] riscv: dts: add SiFive Unmatched board support
Add dts files for SiFive Unmatched board.
Signed-off-by: Green Wan
Reviewed-by: Rick Chen
---
arch/riscv/dts/Makefile |1 +
.../dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489 +
.../dts/hifive-unmatched-a00-u-boot.dtsi | 40 +
arch/riscv/dts/hifive-unmatched-a00.dts | 259 +++
4 files changed, 1789 insertions(+)
create mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
create mode 100644 arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
create mode 100644 arch/riscv/dts/hifive-unmatched-a00.dts
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 8138d89d84..ed32f56c9e 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -2,6 +2,7 @@
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
+dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
diff --git a/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
new file mode 100644
index 00..fc3dfd1959
--- /dev/null
+++ b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
@@ -0,0 +1,1489 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) Copyright 2020-2021 SiFive, Inc
+ */
+
+ {
+ sifive,ddr-params = <
+ 0x0a00 /* DENALI_CTL_00_DATA */
+ 0x /* DENALI_CTL_01_DATA */
+ 0x /* DENALI_CTL_02_DATA */
+ 0x /* DENALI_CTL_03_DATA */
+ 0x /* DENALI_CTL_04_DATA */
+ 0x /* DENALI_CTL_05_DATA */
+ 0x000a /* DENALI_CTL_06_DATA */
+ 0x0002d362 /* DENALI_CTL_07_DATA */
+ 0x00071073 /* DENALI_CTL_08_DATA */
+ 0x0a1c0255 /* DENALI_CTL_09_DATA */
+ 0x1c1c0400 /* DENALI_CTL_10_DATA */
+ 0x0404c90b /* DENALI_CTL_11_DATA */
+ 0x2b050405 /* DENALI_CTL_12_DATA */
+ 0x0d0c081e /* DENALI_CTL_13_DATA */
+ 0x08090914 /* DENALI_CTL_14_DATA */
+ 0x00fde718 /* DENALI_CTL_15_DATA */
+ 0x00180a05 /* DENALI_CTL_16_DATA */
+ 0x008b130d /* DENALI_CTL_17_DATA */
+ 0x01000118 /* DENALI_CTL_18_DATA */
+ 0x0d032001 /* DENALI_CTL_19_DATA */
+ 0x /* DENALI_CTL_20_DATA */
+ 0x0101 /* DENALI_CTL_21_DATA */
+ 0x /* DENALI_CTL_22_DATA */
+ 0x0a00 /* DENALI_CTL_23_DATA */
+ 0x /* DENALI_CTL_24_DATA */
+ 0x01450100 /* DENALI_CTL_25_DATA */
+ 0x1c36 /* DENALI_CTL_26_DATA */
+ 0x0005 /* DENALI_CTL_27_DATA */
+ 0x00170006 /* DENALI_CTL_28_DATA */
+ 0x014e0400 /* DENALI_CTL_29_DATA */
+ 0x0301 /* DENALI_CTL_30_DATA */
+ 0x000a0e00 /* DENALI_CTL_31_DATA */
+ 0x04030200 /* DENALI_CTL_32_DATA */
+ 0x031f /* DENALI_CTL_33_DATA */
+ 0x00070004 /* DENALI_CTL_34_DATA */
+ 0x /* DENALI_CTL_35_DATA */
+ 0x /* DENALI_CTL_36_DATA */
+ 0x /* DENALI_CTL_37_DATA */
+ 0x /* DENALI_CTL_38_DATA */
+ 0x /* DENALI_CTL_39_DATA */
+ 0x /* DENALI_CTL_40_DATA */
+ 0x /* DENALI_CTL_41_DATA */
+ 0x /* DENALI_CTL_42_DATA */
+ 0x /* DENALI_CTL_43_DATA */
+ 0x /* DENALI_CTL_44_DATA */
+ 0x /* DENALI_CTL_45_DATA */
+ 0x /* DENALI_CTL_46_DATA */
+ 0x /* DENALI_CTL_47_DATA */
+ 0x /* DENALI_CTL_48_DATA */
+ 0x /* DENALI_CTL_49_DATA */
+ 0x /* DENALI_CTL_50_DATA */
+ 0x /* DENALI_CTL_51_DATA */
+ 0x /* DENALI_CTL_52_DATA */
+ 0x /* DENALI_CTL_53_DATA */
+ 0x /* DENALI_CTL_54_DATA */
+ 0x /* DENALI_CTL_55_DATA */
+ 0x /* DENALI_CTL_56_DATA */
+ 0x /* DENALI_CTL_57_DATA */
+ 0x /* DENALI_CTL_58_DATA */
+ 0x /* DENALI_CTL_59_DATA */
+ 0x0424 /* DENALI_CTL_60_DATA */
+ 0x0201 /* DENALI_CTL_61_DATA
[PATCH v7 5/8] riscv: dts: add fu740 support
Add dts support for fu740. The HiFive Unmatched support is based on
fu740 cpu and drivers in following patch set.
Signed-off-by: Green Wan
[greentime.hu: set fu740 speed to 1.2GHz]
Signed-off-by: Greentime Hu
Reviewed-by: Bin Meng
Reviewed-by: Rick Chen
---
arch/riscv/dts/fu740-c000-u-boot.dtsi | 105 ++
arch/riscv/dts/fu740-c000.dtsi| 329 ++
include/dt-bindings/clock/sifive-fu740-prci.h | 25 ++
include/dt-bindings/reset/sifive-fu740-prci.h | 19 +
4 files changed, 478 insertions(+)
create mode 100644 arch/riscv/dts/fu740-c000-u-boot.dtsi
create mode 100644 arch/riscv/dts/fu740-c000.dtsi
create mode 100644 include/dt-bindings/clock/sifive-fu740-prci.h
create mode 100644 include/dt-bindings/reset/sifive-fu740-prci.h
diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi
b/arch/riscv/dts/fu740-c000-u-boot.dtsi
new file mode 100644
index 00..a5d0688b06
--- /dev/null
+++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) Copyright 2020-2021 SiFive, Inc
+ */
+
+#include
+
+/ {
+ cpus {
+ assigned-clocks = < PRCI_CLK_COREPLL>;
+ assigned-clock-rates = <12>;
+ u-boot,dm-spl;
+ cpu0: cpu@0 {
+ clocks = < PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ status = "okay";
+ cpu0_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu1: cpu@1 {
+ clocks = < PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ cpu1_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu2: cpu@2 {
+ clocks = < PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ cpu2_intc: interrupt-controller {
+u-boot,dm-spl;
+ };
+ };
+ cpu3: cpu@3 {
+ clocks = < PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ cpu3_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu4: cpu@4 {
+ clocks = < PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ cpu4_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ };
+
+ soc {
+ u-boot,dm-spl;
+ clint: clint@200 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <_intc 3 _intc 7
+ _intc 3 _intc 7
+ _intc 3 _intc 7
+ _intc 3 _intc 7
+ _intc 3 _intc 7>;
+ reg = <0x0 0x200 0x0 0x1>;
+ u-boot,dm-spl;
+ };
+ prci: clock-controller@1000 {
+ #reset-cells = <1>;
+ resets = < PRCI_RST_DDR_CTRL_N>,
+< PRCI_RST_DDR_AXI_N>,
+< PRCI_RST_DDR_AHB_N>,
+< PRCI_RST_DDR_PHY_N>,
+< PRCI_RST_GEMGXL_N>,
+< PRCI_RST_CLTX_N>;
+ reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb",
+ "ddr_phy", "gemgxl_reset", "cltx_reset";
+ };
+ dmc: dmc@100b {
+ compatible = "sifive,fu740-c000-ddr";
+ reg = <0x0 0x100b 0x0 0x0800
+ 0x0 0x100b2000 0x0 0x2000
+ 0x0 0x100b8000 0x0 0x1000>;
+ clocks = < PRCI_CLK_DDRPLL>;
+ clock-frequency = <93324>;
+ u-boot,dm-spl;
+ };
+ };
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ assigned-clocks = < PRCI_CLK_GEMGXLPLL>;
+ assigned-clock-rates = <125125000>;
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi
new file mode 100644
index 00..9e876a4fe3
--- /dev/null
+++ b/arch/riscv/dts/fu740-c000.dtsi
@@ -0,0 +1,329 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 SiFive, Inc */
+
+/dts-v1/;
+
+#include
+#include
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,fu740-c000", "sifive,fu740";
[PATCH v7 4/8] drivers: pci: add pcie support for fu740
Add pcie driver for SiFive fu740, the driver depends on
fu740 gpio, clk and reset driver to do init. Force running at Gen1
for better capatible enumeration.
Several devices are tested:
a) M.2 NVMe SSD
b) USB-to-PCI adapter
c) Ethernet adapter (E1000 compatible)
Signed-off-by: Green Wan
---
drivers/pci/Kconfig | 10 +
drivers/pci/Makefile | 1 +
drivers/pci/pcie_dw_sifive.c | 508 +++
3 files changed, 519 insertions(+)
create mode 100644 drivers/pci/pcie_dw_sifive.c
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index cdcdd8f456..b11dd5c02d 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -97,6 +97,16 @@ config PCIE_DW_MVEBU
Armada-8K SoCs. The PCIe controller on Armada-8K is based on
DesignWare hardware.
+config PCIE_DW_SIFIVE
+ bool "Enable SiFive FU740 PCIe"
+ depends on CLK_SIFIVE_PRCI
+ depends on RESET_SIFIVE
+ depends on SIFIVE_GPIO
+ select PCIE_DW_COMMON
+ help
+ Say Y here if you want to enable PCIe controller support on
+ FU740.
+
config PCIE_FSL
bool "FSL PowerPC PCIe support"
depends on DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 96d61821fe..7351f8027d 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -53,3 +53,4 @@ obj-$(CONFIG_PCIE_DW_ROCKCHIP) += pcie_dw_rockchip.o
obj-$(CONFIG_PCIE_DW_MESON) += pcie_dw_meson.o
obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
+obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
diff --git a/drivers/pci/pcie_dw_sifive.c b/drivers/pci/pcie_dw_sifive.c
new file mode 100644
index 00..599eb0ece2
--- /dev/null
+++ b/drivers/pci/pcie_dw_sifive.c
@@ -0,0 +1,508 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SiFive FU740 DesignWare PCIe Controller
+ *
+ * Copyright (C) 2020-2021 SiFive, Inc.
+ *
+ * Based in early part on the i.MX6 PCIe host controller shim which is:
+ *
+ * Copyright (C) 2013 Kosagi
+ * http://www.kosagi.com
+ *
+ * Based on driver from author: Alan Mikhak
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pcie_dw_common.h"
+
+struct pcie_sifive {
+ /* Must be first member of the struct */
+ struct pcie_dw dw;
+
+ /* private control regs */
+ void __iomem *priv_base;
+
+ /* reset, power, clock resources */
+ int sys_int_pin;
+ struct gpio_desc pwren_gpio;
+ struct gpio_desc reset_gpio;
+ struct clk aux_ck;
+ struct reset_ctl reset;
+};
+
+enum pcie_sifive_devtype {
+ SV_PCIE_UNKNOWN_TYPE = 0,
+ SV_PCIE_ENDPOINT_TYPE = 1,
+ SV_PCIE_HOST_TYPE = 3
+};
+
+#define ASSERTION_DELAY100
+#define PCIE_PERST_ASSERT 0x0
+#define PCIE_PERST_DEASSERT0x1
+#define PCIE_PHY_RESET 0x1
+#define PCIE_PHY_RESET_DEASSERT0x0
+#define GPIO_LOW 0x0
+#define GPIO_HIGH 0x1
+#define PCIE_PHY_SEL 0x1
+
+#define sv_info(sv, fmt, arg...) printf(fmt, ## arg)
+#define sv_warn(sv, fmt, arg...) printf(fmt, ## arg)
+#define sv_debug(sv, fmt, arg...) debug(fmt, ## arg)
+#define sv_err(sv, fmt, arg...)printf(fmt, ## arg)
+
+/* Doorbell Interface */
+#define DBI_OFFSET 0x0
+#define DBI_SIZE 0x1000
+
+#define PL_OFFSET 0x700
+
+#define PHY_DEBUG_R0 (PL_OFFSET + 0x28)
+
+#define PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
+#define PHY_DEBUG_R1_LINK_UP (0x1 << 4)
+#define PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
+
+#define PCIE_MISC_CONTROL_10x8bc
+#define DBI_RO_WR_EN BIT(0)
+
+/* pcie reset */
+#define PCIEX8MGMT_PERST_N 0x0
+
+/* LTSSM */
+#define PCIEX8MGMT_APP_LTSSM_ENABLE0x10
+#define LTSSM_ENABLE_BIT BIT(0)
+
+/* phy reset */
+#define PCIEX8MGMT_APP_HOLD_PHY_RST0x18
+
+/* device type */
+#define PCIEX8MGMT_DEVICE_TYPE 0x708
+#define DEVICE_TYPE_EP 0x0
+#define DEVICE_TYPE_RC 0x4
+
+/* phy control registers*/
+#define PCIEX8MGMT_PHY0_CR_PARA_ADDR 0x860
+#define PCIEX8MGMT_PHY0_CR_PARA_RD_EN 0x870
+#define PCIEX8MGMT_PHY0_CR_PARA_RD_DATA0x878
+#define PCIEX8MGMT_PHY0_CR_PARA_SEL0x880
+#define PCIEX8MGMT_PHY0_CR_PARA_WR_DATA0x888
+#define PCIEX8MGMT_PHY0_CR_PARA_WR_EN 0x890
+#define PCIEX8MGMT_PHY0_CR_PARA_ACK0x898
+#define PCIEX8MGMT_PHY1_CR_PARA_ADDR 0x8a0
+#define PCIEX8MGMT_PHY1_CR_PARA_RD_EN 0x8b0
+#define PCIEX8MGMT_PHY1_CR_PARA_RD_DATA0x8b8
+#define PCIEX8MGMT_PHY1_CR_PARA_SEL0x8c0
+#define PCIEX8MGMT_PHY1_CR_PARA_WR_DATA0x8c8
+#define PCIEX8MGMT_PHY1_CR_PARA_WR_EN 0x8d0
+#define PCIEX8MGMT_PHY1_CR_PARA_ACK0x8d8
+
+#define PCIEX8MGMT_LANE_NUM
[PATCH v7 3/8] drivers: ram: sifive: rename fu540_ddr and add fu740 support
Rename fu540_ddr.c to sifive_ddr.c and add fu740 support
Signed-off-by: Green Wan
Reviewed-by: Bin Meng
---
drivers/ram/sifive/Kconfig| 8 +-
drivers/ram/sifive/Makefile | 2 +-
.../ram/sifive/{fu540_ddr.c => sifive_ddr.c} | 89 ++-
3 files changed, 50 insertions(+), 49 deletions(-)
rename drivers/ram/sifive/{fu540_ddr.c => sifive_ddr.c} (81%)
diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig
index 08de692e02..0aaac02656 100644
--- a/drivers/ram/sifive/Kconfig
+++ b/drivers/ram/sifive/Kconfig
@@ -5,9 +5,9 @@ config RAM_SIFIVE
help
This enables support for ram drivers of SiFive SoCs.
-config SIFIVE_FU540_DDR
- bool "SiFive FU540 DDR driver"
+config SIFIVE_DDR
+ bool "SiFive DDR driver"
depends on RAM_SIFIVE
- default y if TARGET_SIFIVE_UNLEASHED
+ default y if TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED
help
- This enables DDR support for the platforms based on SiFive FU540 SoC.
+ This enables DDR support for the platforms based on SiFive SoC.
diff --git a/drivers/ram/sifive/Makefile b/drivers/ram/sifive/Makefile
index d66efec264..4ef89f85bb 100644
--- a/drivers/ram/sifive/Makefile
+++ b/drivers/ram/sifive/Makefile
@@ -3,4 +3,4 @@
# Copyright (c) 2020 SiFive, Inc
#
-obj-$(CONFIG_SIFIVE_FU540_DDR) += fu540_ddr.o
+obj-$(CONFIG_SIFIVE_DDR) += sifive_ddr.o
diff --git a/drivers/ram/sifive/fu540_ddr.c b/drivers/ram/sifive/sifive_ddr.c
similarity index 81%
rename from drivers/ram/sifive/fu540_ddr.c
rename to drivers/ram/sifive/sifive_ddr.c
index c0653bb897..ba18466033 100644
--- a/drivers/ram/sifive/fu540_ddr.c
+++ b/drivers/ram/sifive/sifive_ddr.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
- * (C) Copyright 2020 SiFive, Inc.
+ * (C) Copyright 2020-2021 SiFive, Inc.
*
* Authors:
* Pragnesh Patel
@@ -65,16 +65,16 @@
DECLARE_GLOBAL_DATA_PTR;
-struct fu540_ddrctl {
+struct sifive_ddrctl {
volatile u32 denali_ctl[265];
};
-struct fu540_ddrphy {
+struct sifive_ddrphy {
volatile u32 denali_phy[1215];
};
/**
- * struct fu540_ddr_info
+ * struct sifive_ddr_info
*
* @dev : pointer for the device
* @info: UCLASS RAM information
@@ -83,23 +83,23 @@ struct fu540_ddrphy {
* @ctrl: DDR control base address
* @physical_filter_ctrl: DDR physical filter control base address
*/
-struct fu540_ddr_info {
+struct sifive_ddr_info {
struct udevice *dev;
struct ram_info info;
- struct fu540_ddrctl *ctl;
- struct fu540_ddrphy *phy;
+ struct sifive_ddrctl *ctl;
+ struct sifive_ddrphy *phy;
struct clk ddr_clk;
u32 *physical_filter_ctrl;
};
#if defined(CONFIG_SPL_BUILD)
-struct fu540_ddr_params {
- struct fu540_ddrctl pctl_regs;
- struct fu540_ddrphy phy_regs;
+struct sifive_ddr_params {
+ struct sifive_ddrctl pctl_regs;
+ struct sifive_ddrphy phy_regs;
};
struct sifive_dmc_plat {
- struct fu540_ddr_params ddr_params;
+ struct sifive_ddr_params ddr_params;
};
/*
@@ -118,7 +118,7 @@ static void sdram_copy_to_reg(volatile u32 *dest,
}
}
-static void fu540_ddr_setup_range_protection(volatile u32 *ctl, u64 end_addr)
+static void sifive_ddr_setup_range_protection(volatile u32 *ctl, u64 end_addr)
{
u32 end_addr_16kblocks = ((end_addr >> 14) & 0x7F) - 1;
@@ -135,8 +135,8 @@ static void fu540_ddr_setup_range_protection(volatile u32
*ctl, u64 end_addr)
0x1 << PORT_ADDR_PROTECTION_EN_OFFSET);
}
-static void fu540_ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl,
- u64 ddr_end)
+static void sifive_ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl,
+u64 ddr_end)
{
volatile u64 *filterreg = (volatile u64 *)physical_filter_ctrl;
@@ -149,7 +149,7 @@ static void fu540_ddr_start(volatile u32 *ctl, u32
*physical_filter_ctrl,
filterreg[0] = 0x0f00UL | (ddr_end >> 2);
}
-static void fu540_ddr_check_errata(u32 regbase, u32 updownreg)
+static void sifive_ddr_check_errata(u32 regbase, u32 updownreg)
{
u64 fails = 0;
u32 dq= 0;
@@ -202,7 +202,7 @@ static void fu540_ddr_check_errata(u32 regbase, u32
updownreg)
}
}
-static u64 fu540_ddr_phy_fixup(volatile u32 *ddrphyreg)
+static u64 sifive_ddr_phy_fixup(volatile u32 *ddrphyreg)
{
u32 slicebase = 0;
@@ -213,7 +213,7 @@ static u64 fu540_ddr_phy_fixup(volatile u32 *ddrphyreg)
for (u32 reg = 0; reg < 4; reg++) {
u32 updownreg = readl(regbase + reg + ddrphyreg);
- fu540_ddr_check_errata(regbase, updownreg);
+ sifive_ddr_check_errata(regbase, updownreg);
}
slicebase += 128;
[PATCH v7 1/8] riscv: cpu: fu740: Add support for cpu fu740
Add SiFive fu740 cpu to support RISC-V arch
Signed-off-by: Green Wan
Reviewed-by: Bin Meng
---
arch/riscv/Kconfig| 1 +
arch/riscv/cpu/fu740/Kconfig | 37 +++
arch/riscv/cpu/fu740/Makefile | 12 +
arch/riscv/cpu/fu740/cache.c | 55 +++
arch/riscv/cpu/fu740/cpu.c| 22 +
arch/riscv/cpu/fu740/dram.c | 38
arch/riscv/cpu/fu740/spl.c| 23 ++
arch/riscv/include/asm/arch-fu740/cache.h | 14 ++
arch/riscv/include/asm/arch-fu740/clk.h | 14 ++
arch/riscv/include/asm/arch-fu740/gpio.h | 38
arch/riscv/include/asm/arch-fu740/reset.h | 13 ++
arch/riscv/include/asm/arch-fu740/spl.h | 14 ++
arch/riscv/lib/sifive_clint.c | 1 -
13 files changed, 281 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/cpu/fu740/Kconfig
create mode 100644 arch/riscv/cpu/fu740/Makefile
create mode 100644 arch/riscv/cpu/fu740/cache.c
create mode 100644 arch/riscv/cpu/fu740/cpu.c
create mode 100644 arch/riscv/cpu/fu740/dram.c
create mode 100644 arch/riscv/cpu/fu740/spl.c
create mode 100644 arch/riscv/include/asm/arch-fu740/cache.h
create mode 100644 arch/riscv/include/asm/arch-fu740/clk.h
create mode 100644 arch/riscv/include/asm/arch-fu740/gpio.h
create mode 100644 arch/riscv/include/asm/arch-fu740/reset.h
create mode 100644 arch/riscv/include/asm/arch-fu740/spl.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 3f221dccdb..4177253e44 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -61,6 +61,7 @@ source "board/sipeed/maix/Kconfig"
# platform-specific options below
source "arch/riscv/cpu/ax25/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
+source "arch/riscv/cpu/fu740/Kconfig"
source "arch/riscv/cpu/generic/Kconfig"
# architecture-specific options below
diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
new file mode 100644
index 00..24788beab1
--- /dev/null
+++ b/arch/riscv/cpu/fu740/Kconfig
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020-2021 SiFive, Inc
+# Pragnesh Patel
+
+config SIFIVE_FU740
+ bool
+ select ARCH_EARLY_INIT_R
+ select RAM
+ select SPL_RAM if SPL
+ imply CPU
+ imply CPU_RISCV
+ imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+ imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
+ imply CMD_CPU
+ imply SPL_CPU
+ imply SPL_OPENSBI
+ imply SPL_LOAD_FIT
+ imply SMP
+ imply CLK_SIFIVE
+ imply CLK_SIFIVE_PRCI
+ imply SIFIVE_SERIAL
+ imply MACB
+ imply MII
+ imply SPI
+ imply SPI_SIFIVE
+ imply MMC
+ imply MMC_SPI
+ imply MMC_BROKEN_CD
+ imply CMD_MMC
+ imply DM_GPIO
+ imply SIFIVE_GPIO
+ imply CMD_GPIO
+ imply MISC
+ imply SIFIVE_OTP
+ imply DM_PWM
+ imply PWM_SIFIVE
diff --git a/arch/riscv/cpu/fu740/Makefile b/arch/riscv/cpu/fu740/Makefile
new file mode 100644
index 00..5ef8ac18a7
--- /dev/null
+++ b/arch/riscv/cpu/fu740/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020-2021 SiFive, Inc
+# Pragnesh Patel
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y += spl.o
+else
+obj-y += dram.o
+obj-y += cpu.o
+obj-y += cache.o
+endif
diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c
new file mode 100644
index 00..680955c9e3
--- /dev/null
+++ b/arch/riscv/cpu/fu740/cache.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc
+ *
+ * Authors:
+ * Pragnesh Patel
+ */
+
+#include
+#include
+#include
+#include
+
+/* Register offsets */
+#define L2_CACHE_CONFIG0x000
+#define L2_CACHE_ENABLE0x008
+
+#define MASK_NUM_WAYS GENMASK(15, 8)
+#define NUM_WAYS_SHIFT 8
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int cache_enable_ways(void)
+{
+ const void *blob = gd->fdt_blob;
+ int node;
+ fdt_addr_t base;
+ u32 config;
+ u32 ways;
+
+ volatile u32 *enable;
+
+ node = fdt_node_offset_by_compatible(blob, -1,
+"sifive,fu740-c000-ccache");
+
+ if (node < 0)
+ return node;
+
+ base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
+ NULL, false);
+ if (base == FDT_ADDR_T_NONE)
+ return FDT_ADDR_T_NONE;
+
+ config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
+ ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
+
+ enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
+
+ /* memory barrier */
+ mb();
+ (*enable) = ways - 1;
+ /* memory barrier */
+ mb();
+ return 0;
+}
diff --git a/arch/riscv/cpu/fu740/cpu.c b/arch/riscv/cpu/fu740/cpu.c
new file mode 100644
index
[PATCH v7 0/8] Add FU740 chip and HiFive Unmatched board support
This patch set is to add SiFive fu740 chip and HiFive Unmatched board support. Patches are split into several parts: - [PATCH v7 1/8] support for fu740 cpu - [PATCH v7 2/8] support for fu740 clk driver - [PATCH v7 3/8] rename and support for fu740 ram driver - [PATCH v7 4/8] add pcie driver - [PATCH v7 5/8] dts for SiFive fu740 - [PATCH v7 6/8] dts for SiFive Unmatched board - [PATCH v7 7/8] add Unmatched board support - [PATCH v7 8/8] add fu740 support to macb driver Description - For fu740 cpu support, reuse most of fu540 cpu. - For prci driver, add one abstract layer to separate fu540 and fu740. Move orignal fu540 code to separate files. - For pcie driver, it depends on gpio, prci, clk and reset drivers to do init works. Also based on pcie_dw_common.c - Align with Linux DT file. Tests and patch checks - Able to boot both unmatched and unleashed boards. - PCIe tests . M.2 NVMe SSD . e1000 compatibale ethernet adapter (ping) . pci-to-usb adapter(usb mass storage) - checkpatch is performed. To keep code derived from other boards the same, ignore some warnings/errors in [PATCH 7/8]. Changlogs - V7 . Rebase to latest master branch . Moved dts for fu740 patch [v6 1/7] to [v7 5/8] and seperate dts of Unmatched board from [v6 6/7] into [v7 6/8] . Applied PCIe refactoring patch to base on the common code in pcie_dw_common.c - V6 . Remove redundant DT string for 1.2GHz CPU clock and squash to [1/7] - V5 . Fix unleashed build error in patch [6/8] . Append one more set for 1.2GHz CPU speed . Add "#include " back to sifive_ddr.c . Add Reviewed-by to [4/8] and [7/8] - V4 . fixed incorrect file name in ./board/sifive/unmatched/Makefile . fixed link in doc/board/sifive/index.rst, passed 'make htmldocs' - V3 . Rebase to unleashed rename v2 patch . Rename doc/board/sifive/unmatched.rst board/sifive/unmatched/unmatched.c . Fix tail whitespace . Add 'git mv' info to ram driver and merge patch back to one . Add comment to macb driver for PLL hardware quirk . Add reviewed-by to patch [6/7] . Add 'gpio-poweroff' node for upcoming opensbi integration - V2 . Rebase to unleashed rename patch . remove unnessaary fu540 changes . split ram driver patch into 2 to keep 'git mv' info . use a shorter name for unmatched support . Remove redundant temperature-sensor in DT . Remove unnecessary USB EHCI & OHCI from defconfig . Revised fu740 doc . Fixed year of copyright . Add reviewed-by received in v1 patch David Abdurachmanov (1): drivers: net: macb: add fu740 support Green Wan (7): riscv: cpu: fu740: Add support for cpu fu740 drivers: clk: add fu740 support drivers: ram: sifive: rename fu540_ddr and add fu740 support drivers: pci: add pcie support for fu740 riscv: dts: add fu740 support riscv: dts: add SiFive Unmatched board support board: sifive: add HiFive Unmatched board support arch/riscv/Kconfig|5 + arch/riscv/cpu/fu740/Kconfig | 37 + arch/riscv/cpu/fu740/Makefile | 12 + arch/riscv/cpu/fu740/cache.c | 55 + arch/riscv/cpu/fu740/cpu.c| 22 + arch/riscv/cpu/fu740/dram.c | 38 + arch/riscv/cpu/fu740/spl.c| 23 + arch/riscv/dts/Makefile |1 + arch/riscv/dts/fu740-c000-u-boot.dtsi | 105 ++ arch/riscv/dts/fu740-c000.dtsi| 329 .../dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489 + .../dts/hifive-unmatched-a00-u-boot.dtsi | 40 + arch/riscv/dts/hifive-unmatched-a00.dts | 259 +++ arch/riscv/include/asm/arch-fu740/cache.h | 14 + arch/riscv/include/asm/arch-fu740/clk.h | 14 + arch/riscv/include/asm/arch-fu740/gpio.h | 38 + arch/riscv/include/asm/arch-fu740/reset.h | 13 + arch/riscv/include/asm/arch-fu740/spl.h | 14 + arch/riscv/lib/sifive_clint.c |1 - board/sifive/unleashed/Kconfig|1 + board/sifive/unmatched/Kconfig| 50 + board/sifive/unmatched/MAINTAINERS|9 + board/sifive/unmatched/Makefile |9 + board/sifive/unmatched/spl.c | 85 + board/sifive/unmatched/unmatched.c| 24 + common/spl/Kconfig|4 +- configs/sifive_unleashed_defconfig|1 + configs/sifive_unmatched_defconfig| 54 + doc/board/sifive/index.rst|1 + doc/board/sifive/unmatched.rst| 536 ++ drivers/clk/sifive/Kconfig|8 +- drivers/clk/sifive/Makefile |4 +- drivers/clk/sifive/fu540-prci.c | 769 + drivers/clk/sifive/fu540-prci.h | 22 +
Re: [PATCH 2/2] efi_loader: add PE/COFF image measurement
On 22.04.21 10:09, Ilias Apalodimas wrote:
+ if (!(active & alg_to_mask(hash_alg)))
+ continue;
+ switch (hash_alg) {
+ case TPM2_ALG_SHA1:
>>>
>>> SHA1 is known to be unsafe. Why would we support it?
>>
>> Basically I agree with removing SHA1 support.
>> This efi_tcg2.c implementation aims to support TCG v2, so there is no
>> reason to keep SHA1.
>> Anyway, SHA1 is supported in tcg2_create_digest() for the measurement
>> other than PE/COFF image. Do we also remove SHA1 from
>> tcg2_create_digest()?
>>
>
> The hardware dictates what kind of SHAxxx you are supposed to add in the
> EventLog and the PCRs. Why would we remove the functionality? If someone
> considers SHA1 unsafe, he can just disable it from his hardware and remove it
> from the active algorithms.
>
>
> Cheers
> /Ilias
The TCG EFI ProtocolSpecification explicitely enumerates the four
hashing algorithms of Masahisa's patch, see chapter 6.4.3, "Related
Definitions".
So let's support them.
Best regards
Heinrich
>
>> For other comments, I will modify the code and send v2 patch.
>>
>> Thanks,
>> Masahisa
>>
>>
>> On Wed, 21 Apr 2021 at 19:57, Heinrich Schuchardt wrote:
>>>
>>> On 4/15/21 3:30 PM, Masahisa Kojima wrote:
"TCG PC Client Platform Firmware Profile Specification"
requires to measure every attempt to load and execute
a OS Loader(a UEFI application) into PCR[4].
This commit adds the PE/COFF image measurement, extends PCR,
and appends measurement into Event Log.
Signed-off-by: Masahisa Kojima
---
include/efi_loader.h | 4 +
include/efi_tcg2.h| 10 ++
include/tpm-v2.h | 1 +
lib/efi_loader/efi_image_loader.c | 7 ++
lib/efi_loader/efi_tcg2.c | 187 --
5 files changed, 199 insertions(+), 10 deletions(-)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index de1a496a97..b02bc93c8e 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -426,6 +426,10 @@ efi_status_t efi_disk_register(void);
efi_status_t efi_rng_register(void);
/* Called by efi_init_obj_list() to install EFI_TCG2_PROTOCOL */
efi_status_t efi_tcg2_register(void);
+/* measure the pe-coff image, extend PCR and add Event Log */
+efi_status_t tcg2_measure_pe_image(void *efi, u64 efi_size,
+struct efi_loaded_image_obj *handle,
+struct efi_loaded_image
*loaded_image_info);
/* Create handles and protocols for the partitions of a block device */
int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc
*desc,
const char *if_typename, int diskid,
diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h
index 40e241ce31..f8d46c5fd2 100644
--- a/include/efi_tcg2.h
+++ b/include/efi_tcg2.h
@@ -9,6 +9,8 @@
#if !defined _EFI_TCG2_PROTOCOL_H_
#define _EFI_TCG2_PROTOCOL_H_
+#include
>>>
>>> This include is already included in efi_api.h.
>>>
+#include
#include
#define EFI_TCG2_PROTOCOL_GUID \
@@ -53,6 +55,14 @@ struct efi_tcg2_event {
u8 event[];
} __packed;
+struct uefi_image_load_event {
+ efi_physical_addr_t image_location_in_memory;
+ u64 image_length_in_memory;
+ u64 image_link_time_address;
+ u64 length_of_device_path;
+ struct efi_device_path device_path[];
>>>
>>> A device path is not an array of struct efi_device_path. But the first
>>> element is of this type. So ok.
>>>
+} __packed;
>>>
>>> Why should this be __packed? You don't use arrays of this structure and
>>> it is naturally packed.
>>>
+
struct efi_tcg2_boot_service_capability {
u8 size;
struct efi_tcg2_version structure_version;
diff --git a/include/tpm-v2.h b/include/tpm-v2.h
index df67a196cf..ab9c04dc0a 100644
--- a/include/tpm-v2.h
+++ b/include/tpm-v2.h
@@ -61,6 +61,7 @@ struct udevice;
#define EV_S_CRTM_VERSION ((u32)0x0008)
#define EV_CPU_MICROCODE((u32)0x0009)
#define EV_TABLE_OF_DEVICES ((u32)0x000B)
>>>
>>> Please, add a comment here that the following values are defined in the
>>> "TCG EFI Platform Specification".
>>>
+#define EV_EFI_BOOT_SERVICES_APPLICATION ((u32)0x8003)
>>>
>>> Please, add all EV_EFI_* constants.
>>>
/* TPMS_TAGGED_PROPERTY Structure */
struct tpms_tagged_property {
diff --git a/lib/efi_loader/efi_image_loader.c
b/lib/efi_loader/efi_image_loader.c
index 2c35cb5651..b032ec5dd8 100644
--- a/lib/efi_loader/efi_image_loader.c
+++ b/lib/efi_loader/efi_image_loader.c
@@ -829,6 +829,13 @@ efi_status_t efi_load_pe(struct
Re: [PATCH 2/2] efi_loader: add PE/COFF image measurement
> > > + if (!(active & alg_to_mask(hash_alg)))
> > > + continue;
> > > + switch (hash_alg) {
> > > + case TPM2_ALG_SHA1:
> >
> > SHA1 is known to be unsafe. Why would we support it?
>
> Basically I agree with removing SHA1 support.
> This efi_tcg2.c implementation aims to support TCG v2, so there is no
> reason to keep SHA1.
> Anyway, SHA1 is supported in tcg2_create_digest() for the measurement
> other than PE/COFF image. Do we also remove SHA1 from
> tcg2_create_digest()?
>
The hardware dictates what kind of SHAxxx you are supposed to add in the
EventLog and the PCRs. Why would we remove the functionality? If someone
considers SHA1 unsafe, he can just disable it from his hardware and remove it
from the active algorithms.
Cheers
/Ilias
> For other comments, I will modify the code and send v2 patch.
>
> Thanks,
> Masahisa
>
>
> On Wed, 21 Apr 2021 at 19:57, Heinrich Schuchardt wrote:
> >
> > On 4/15/21 3:30 PM, Masahisa Kojima wrote:
> > > "TCG PC Client Platform Firmware Profile Specification"
> > > requires to measure every attempt to load and execute
> > > a OS Loader(a UEFI application) into PCR[4].
> > > This commit adds the PE/COFF image measurement, extends PCR,
> > > and appends measurement into Event Log.
> > >
> > > Signed-off-by: Masahisa Kojima
> > > ---
> > > include/efi_loader.h | 4 +
> > > include/efi_tcg2.h| 10 ++
> > > include/tpm-v2.h | 1 +
> > > lib/efi_loader/efi_image_loader.c | 7 ++
> > > lib/efi_loader/efi_tcg2.c | 187 --
> > > 5 files changed, 199 insertions(+), 10 deletions(-)
> > >
> > > diff --git a/include/efi_loader.h b/include/efi_loader.h
> > > index de1a496a97..b02bc93c8e 100644
> > > --- a/include/efi_loader.h
> > > +++ b/include/efi_loader.h
> > > @@ -426,6 +426,10 @@ efi_status_t efi_disk_register(void);
> > > efi_status_t efi_rng_register(void);
> > > /* Called by efi_init_obj_list() to install EFI_TCG2_PROTOCOL */
> > > efi_status_t efi_tcg2_register(void);
> > > +/* measure the pe-coff image, extend PCR and add Event Log */
> > > +efi_status_t tcg2_measure_pe_image(void *efi, u64 efi_size,
> > > +struct efi_loaded_image_obj *handle,
> > > +struct efi_loaded_image
> > > *loaded_image_info);
> > > /* Create handles and protocols for the partitions of a block device */
> > > int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc
> > > *desc,
> > > const char *if_typename, int diskid,
> > > diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h
> > > index 40e241ce31..f8d46c5fd2 100644
> > > --- a/include/efi_tcg2.h
> > > +++ b/include/efi_tcg2.h
> > > @@ -9,6 +9,8 @@
> > > #if !defined _EFI_TCG2_PROTOCOL_H_
> > > #define _EFI_TCG2_PROTOCOL_H_
> > >
> > > +#include
> >
> > This include is already included in efi_api.h.
> >
> > > +#include
> > > #include
> > >
> > > #define EFI_TCG2_PROTOCOL_GUID \
> > > @@ -53,6 +55,14 @@ struct efi_tcg2_event {
> > > u8 event[];
> > > } __packed;
> > >
> > > +struct uefi_image_load_event {
> > > + efi_physical_addr_t image_location_in_memory;
> > > + u64 image_length_in_memory;
> > > + u64 image_link_time_address;
> > > + u64 length_of_device_path;
> > > + struct efi_device_path device_path[];
> >
> > A device path is not an array of struct efi_device_path. But the first
> > element is of this type. So ok.
> >
> > > +} __packed;
> >
> > Why should this be __packed? You don't use arrays of this structure and
> > it is naturally packed.
> >
> > > +
> > > struct efi_tcg2_boot_service_capability {
> > > u8 size;
> > > struct efi_tcg2_version structure_version;
> > > diff --git a/include/tpm-v2.h b/include/tpm-v2.h
> > > index df67a196cf..ab9c04dc0a 100644
> > > --- a/include/tpm-v2.h
> > > +++ b/include/tpm-v2.h
> > > @@ -61,6 +61,7 @@ struct udevice;
> > > #define EV_S_CRTM_VERSION ((u32)0x0008)
> > > #define EV_CPU_MICROCODE((u32)0x0009)
> > > #define EV_TABLE_OF_DEVICES ((u32)0x000B)
> >
> > Please, add a comment here that the following values are defined in the
> > "TCG EFI Platform Specification".
> >
> > > +#define EV_EFI_BOOT_SERVICES_APPLICATION ((u32)0x8003)
> >
> > Please, add all EV_EFI_* constants.
> >
> > >
> > > /* TPMS_TAGGED_PROPERTY Structure */
> > > struct tpms_tagged_property {
> > > diff --git a/lib/efi_loader/efi_image_loader.c
> > > b/lib/efi_loader/efi_image_loader.c
> > > index 2c35cb5651..b032ec5dd8 100644
> > > --- a/lib/efi_loader/efi_image_loader.c
> > > +++ b/lib/efi_loader/efi_image_loader.c
> > > @@ -829,6 +829,13 @@ efi_status_t efi_load_pe(struct efi_loaded_image_obj
> > > *handle,
> > > goto err;
> > > }
> > >
> > > +#if CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL)
> > > + /* Measure an PE/COFF image */
> > > + if
[PATCH] Makefile: fix generation of defaultenv.h from empty initial file
When CONFIG_USE_DEFAULT_ENV_FILE=y and the file
CONFIG_DEFAULT_ENV_FILE is empty (or at least doesn't contain any
non-comment, non-empty lines), we end up feeding nothing into xxd,
which in turn then outputs nothing. Then blindly appending ", 0x00"
means that we end up trying to compile (roughly)
const char defaultenv[] = { , 0x00 }
which is of course broken.
To fix that, change the frobbing of the text file so that we always
end up printing an extra empty line (which gets turned into that extra
nul byte we need) - that corresponds better to the binary format
consisting of a series of key=val nul terminated strings, terminated
by an empty string.
Reported-by: Oleksandr Suvorov
Signed-off-by: Rasmus Villemoes
---
Makefile | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/Makefile b/Makefile
index 3fc9777b0b..b7af2b936d 100644
--- a/Makefile
+++ b/Makefile
@@ -1854,11 +1854,10 @@ define filechk_timestamp.h
endef
define filechk_defaultenv.h
- (grep -v '^#' | \
-grep -v '^$$' | \
+ ( { grep -v '^#' | grep -v '^$$' || true ; echo '' ; } | \
tr '\n' '\0' | \
sed -e 's/\\\x0\s*//g' | \
-xxd -i ; echo ", 0x00" ; )
+xxd -i ; )
endef
define filechk_dt.h
--
2.29.2
Re: [PATCH V2 1/2] mmc: add OpenPiton mmc support
Dear Tianrui,
On 4/22/21 3:19 PM, Tianrui Wei wrote:
> This patch adds mmc support for OpenPiton.
>
> Signed-off-by: Tianrui Wei
> Signed-off-by: Jonathan Balkind
>
> ---
>
> drivers/mmc/Kconfig | 6 +
> drivers/mmc/Makefile| 1 +
> drivers/mmc/piton_mmc.c | 177 +
> 3 files changed, 184 insertions(+)
> create mode 100644 drivers/mmc/piton_mmc.c
>
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index 14d79139..41822c39 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -707,6 +707,12 @@ config MMC_SUNXI_HAS_MODE_SWITCH
> bool
> depends on MMC_SUNXI
>
> +config MMC_PITON
> + bool "MMC support for openpiton SoC"
> + depends on DM_MMC && BLK
> + help
> +This driver enables sd card support in U-Boot port for openpiton
> +
> config GENERIC_ATMEL_MCI
> bool "Atmel Multimedia Card Interface support"
> depends on DM_MMC && BLK && ARCH_AT91
> diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
> index 1c849cba..698dfe05 100644
> --- a/drivers/mmc/Makefile
> +++ b/drivers/mmc/Makefile
> @@ -71,6 +71,7 @@ obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o
> obj-$(CONFIG_MMC_SDHCI_ZYNQ) += zynq_sdhci.o
>
> obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
> +obj-$(CONFIG_MMC_PITON) += piton_mmc.o
> obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o
> obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o
> obj-$(CONFIG_MMC_BCM2835)+= bcm2835_sdhost.o
> diff --git a/drivers/mmc/piton_mmc.c b/drivers/mmc/piton_mmc.c
> new file mode 100644
> index ..f2ceb87f
> --- /dev/null
> +++ b/drivers/mmc/piton_mmc.c
> @@ -0,0 +1,177 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2009 SAMSUNG Electronics
> + * Minkyu Kang
> + * Jaehoon Chung
> + * Portions Copyright 2011-2019 NVIDIA Corporation
> + * Portions Copyright 2021 Tianrui Wei
> + * Tianrui Wei
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +struct piton_mmc_plat {
> + struct mmc_config cfg;
> + struct mmc mmc;
> +};
> +
> +struct piton_mmc_priv {
> + u64 piton_mmc_base_addr; /* peripheral id */
> +};
> +
> +/*
> + * see mmc_read_blocks to see how it is used.
> + * start block is hidden at cmd->arg
> + * also, initialize the block size at init
> + */
> +static int piton_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
> +
> struct mmc_data *data)
> +{
> + // check first if this is a pure command
Remove all "//" comment.
If you want to add some comment, add comment with "/* *"
e.g)
/* Check first if this is a pure command */
> + if (data == NULL) {
> + return 0;
> + }
> +
> + // byte count counts all the bytes required for this command
Not need. Remove, plz.
> + u64 byte_cnt = data->blocks * data->blocksize;
> + // get which block in mmc card to start from
Ditto
> + u64 start_block = cmd->cmdarg;
> + // buff points to the address we store the data stored at mmc card
Ditto.
> + unsigned *buff = (unsigned int *) data->dest;
> +
> + struct piton_mmc_priv *priv = dev_get_priv(dev);
> + // start address denotes the absolute address where the transmission
> start
Ditto.
> + u64 start_addr = priv->piton_mmc_base_addr + (start_block);
> +
> + /* if there is a read */
> + if (data->flags & MMC_DATA_READ) {
> + for (u64 i = 0; i < byte_cnt; i += 4) {
> + *(buff) = readl((void *)(start_addr + i));
> + buff++;
> + }
> + } else {
> + /* else there is a write
> + * we don't handle write, so error right away
> + */
> + return -ENODEV;
> + }
> +
> + return 0;
> +}
> +
> +static int piton_mmc_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct piton_mmc_priv *priv = dev_get_priv(dev);
> + struct piton_mmc_plat *plat = dev_get_platdata(dev);
> + struct mmc_config *cfg;
> + struct mmc *mmc;
> + /* fill in device description */
> + struct blk_desc *bdesc;
> +
> + priv->piton_mmc_base_addr = dev_read_addr(dev);
> + cfg = >cfg;
> + cfg->name = "PITON MMC";
> + cfg->host_caps = MMC_MODE_8BIT;
If you can use mmc_of_parse() with dt, it can be removed.
> + cfg->f_max = 10;
> + cfg->f_min = 40;
> + cfg->voltages = MMC_VDD_21_22;
> +
> + mmc = >mmc;
> + mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
> + mmc->capacity_user = 0x1;
> + mmc->capacity_user *= mmc->read_bl_len;
> + mmc->capacity_boot = 0;
> + mmc->capacity_rpmb = 0;
> + for (int i = 0; i < 4; i++)
> + mmc->capacity_gp[i] = 0;
> +
Re: [PATCH v2] Makefile: fix generating environment file
On Wed, Apr 21, 2021 at 11:56 PM Rasmus Villemoes
wrote:
>
> On 21/04/2021 17.21, Oleksandr Suvorov wrote:
> > Hi Rasmus,
> >
> > On Wed, Apr 21, 2021 at 12:34 AM Rasmus Villemoes
> > wrote:
> >>
> >> On 20/04/2021 23.10, Oleksandr Suvorov wrote:
> >>> Hi Rasmus,
> >>>
> >>> Thanks for your feedback!
> >>> Yes, I noted that there were no possible situations with the trailing
> >>> code != 0x00, but simply removing the additional trailing 0x00
> >>> gives us an empty array default_environment[] for the empty defaultenv
> >>> file.
> >>> I need to test whether this case is handled in u-boot properly and
> >>> then prepare the next patch version :P
> >>
> >> No, I'm not suggesting removing the trailing nul byte, it very much has
> >> to be there - the binary format of the environment is a sequence of
> >> nul-terminated C strings of the key=value form, concatenated
> >> back-to-back, terminated by an empty string.
> >
> > (/me saying: never answer at night, never answer at night, never
> > answer at night :-D)
> >
> >>
> >> What I'm suggesting is to take the input file
> >>
> >> ===
> >> foo=bar
> >>
> >> # Set our IP address
> >> ip=1.2.3.4
> >> ===
> >>
> >> do the comment- and empty-line stripping (the two first greps), and then
> >> after that add an extra empty line
> >>
> >> ===
> >> foo=bar
> >> ip=1.2.3.4
> >>
> >> ===
> >>
> >> and then feed that to the 'replace \n by nul bytes' | 'delete
> >> backslash+nul+whitespace' | xxd pipe. That way there's always that
> >> trailing nul on the input to xxd, i.e. in the example above, we would
> >> feed foo=bar\0ip-1.2.3.4\0\0 into xxd, while with an initially empty
> >> file xxd would just receive that single nul byte.
> >>
> >> It's just that I think terminating the sequence of key=value lines by an
> >> empty line more exactly matches the binary format.
> >
> > Sure, now I see. Your solution is more straight and clear.
> > Unfortunately, it doesn't work :)
>
> Yeah, I didn't really expect it to. Ah, it's because "set -e" is in
> effect, so in
>
> ( { grep -v '^#' | grep -v '^$$' ; echo '' ; } | \
>
> the return value of the grep -v '^#' | grep -v '^$$' pipeline is that
> of the second grep, and when there's no input lines that match (such as,
> with an empty input file), that's an EXIT_FAILURE. So the whole subshell
> exits at that point, and nothing gets written to defaultenv_autogenerated.h.
>
> Doing
>
> define filechk_defaultenv.h
> ( { grep -v '^#' | grep -v '^$$' || true ; echo '' ; } | \
> tr '\n' '\0' | \
> sed -e 's/\\\x0\s*//g' | \
> xxd -i ; )
> endef
>
> seems to work.
So will you post your own patch?
> Rasmus
--
Best regards
Oleksandr Suvorov
Toradex AG
Ebenaustrasse 10 | 6048 Horw | Switzerland | T: +41 41 500 48 00
Re: [PATCH V2 0/2] Add OpenPiton board support
This patch add board support for OpenPiton.
Signed-off-by: Tianrui Wei
Signed-off-by: Jonathan Balkind
---
arch/riscv/Kconfig | 4 +
arch/riscv/dts/Makefile | 1 +
arch/riscv/dts/openpiton-riscv64.dts| 159 +
board/openpiton/riscv/Kconfig | 42 ++
board/openpiton/riscv/MAINTAINERS | 6 +
board/openpiton/riscv/Makefile | 5 +
board/openpiton/riscv/openpiton-riscv.c | 41 ++
configs/openpiton_riscv64_defconfig | 132
doc/board/index.rst | 1 +
doc/board/openpiton/index.rst | 9 +
doc/board/openpiton/riscv64.rst | 885
include/configs/openpiton-riscv.h | 58 ++
12 files changed, 1343 insertions(+)
create mode 100644 arch/riscv/dts/openpiton-riscv64.dts
create mode 100644 board/openpiton/riscv/Kconfig
create mode 100644 board/openpiton/riscv/MAINTAINERS
create mode 100644 board/openpiton/riscv/Makefile
create mode 100644 board/openpiton/riscv/openpiton-riscv.c
create mode 100644 configs/openpiton_riscv64_defconfig
create mode 100644 doc/board/openpiton/index.rst
create mode 100644 doc/board/openpiton/riscv64.rst
create mode 100644 include/configs/openpiton-riscv.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 30b05408..50782dee 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -23,6 +23,9 @@ config TARGET_SIFIVE_FU540
config TARGET_SIPEED_MAIX
bool "Support Sipeed Maix Board"
+config TARGET_OPENPITON_RISCV
+bool "Support riscv cores on openpiton SoC"
+
endchoice
config SYS_ICACHE_OFF
@@ -55,6 +58,7 @@ config SPL_SYS_DCACHE_OFF
source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
+source "board/openpiton/riscv/Kconfig"
source "board/sifive/fu540/Kconfig"
source "board/sipeed/maix/Kconfig"
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 3a6f96c6..b511cd74 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
+dtb-$(CONFIG_TARGET_OPENPITON_RISCV) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
diff --git a/arch/riscv/dts/openpiton-riscv64.dts
b/arch/riscv/dts/openpiton-riscv64.dts
new file mode 100644
index ..ce732b92
--- /dev/null
+++ b/arch/riscv/dts/openpiton-riscv64.dts
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2021 Tianrui Wei */
+
+/*
+ * This dts is for a dual core instance of OpenPiton+Ariane built
+ * to run on a Digilent Genesys 2 FPGA at 66.67MHz. These files
+ * are automatically generated by the OpenPiton build system and
+ * this configuration may not be what you need if your configuration
+ * is different from the below.
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ compatible = "openpiton,ariane";
+
+ chosen {
+ stdout-path = "uart0:115200";
+ };
+
+ aliases {
+ console =
+ serial0 =
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+ timebase-frequency = <520835>;
+
+ CPU0: cpu@0 {
+ clock-frequency = <7000>;
+ u-boot,dm-pre-reloc;
+ device_type = "cpu";
+ reg = <0>;
+ status = "okay";
+ compatible = "eth, ariane", "riscv";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ tlb-split;
+ // HLIC - hart local interrupt controller
+ CPU0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
+
+ CPU1: cpu@1 {
+ clock-frequency = <7000>;
+ u-boot,dm-pre-reloc;
+ device_type = "cpu";
+ reg = <1>;
+ status = "okay";
+ compatible = "eth, ariane", "riscv";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ tlb-split;
+ // HLIC - hart local interrupt controller
+ CPU1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+
[PATCH V2 1/2] mmc: add OpenPiton mmc support
This patch adds mmc support for OpenPiton.
Signed-off-by: Tianrui Wei
Signed-off-by: Jonathan Balkind
---
drivers/mmc/Kconfig | 6 +
drivers/mmc/Makefile| 1 +
drivers/mmc/piton_mmc.c | 177 +
3 files changed, 184 insertions(+)
create mode 100644 drivers/mmc/piton_mmc.c
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 14d79139..41822c39 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -707,6 +707,12 @@ config MMC_SUNXI_HAS_MODE_SWITCH
bool
depends on MMC_SUNXI
+config MMC_PITON
+ bool "MMC support for openpiton SoC"
+ depends on DM_MMC && BLK
+ help
+This driver enables sd card support in U-Boot port for openpiton
+
config GENERIC_ATMEL_MCI
bool "Atmel Multimedia Card Interface support"
depends on DM_MMC && BLK && ARCH_AT91
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 1c849cba..698dfe05 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -71,6 +71,7 @@ obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o
obj-$(CONFIG_MMC_SDHCI_ZYNQ) += zynq_sdhci.o
obj-$(CONFIG_MMC_SUNXI)+= sunxi_mmc.o
+obj-$(CONFIG_MMC_PITON)+= piton_mmc.o
obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o
obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o
obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o
diff --git a/drivers/mmc/piton_mmc.c b/drivers/mmc/piton_mmc.c
new file mode 100644
index ..f2ceb87f
--- /dev/null
+++ b/drivers/mmc/piton_mmc.c
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang
+ * Jaehoon Chung
+ * Portions Copyright 2011-2019 NVIDIA Corporation
+ * Portions Copyright 2021 Tianrui Wei
+ * Tianrui Wei
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct piton_mmc_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+struct piton_mmc_priv {
+ u64 piton_mmc_base_addr; /* peripheral id */
+};
+
+/*
+ * see mmc_read_blocks to see how it is used.
+ * start block is hidden at cmd->arg
+ * also, initialize the block size at init
+ */
+static int piton_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+
struct mmc_data *data)
+{
+ // check first if this is a pure command
+ if (data == NULL) {
+ return 0;
+ }
+
+ // byte count counts all the bytes required for this command
+ u64 byte_cnt = data->blocks * data->blocksize;
+ // get which block in mmc card to start from
+ u64 start_block = cmd->cmdarg;
+ // buff points to the address we store the data stored at mmc card
+ unsigned *buff = (unsigned int *) data->dest;
+
+ struct piton_mmc_priv *priv = dev_get_priv(dev);
+ // start address denotes the absolute address where the transmission
start
+ u64 start_addr = priv->piton_mmc_base_addr + (start_block);
+
+ /* if there is a read */
+ if (data->flags & MMC_DATA_READ) {
+ for (u64 i = 0; i < byte_cnt; i += 4) {
+ *(buff) = readl((void *)(start_addr + i));
+ buff++;
+ }
+ } else {
+ /* else there is a write
+* we don't handle write, so error right away
+*/
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int piton_mmc_ofdata_to_platdata(struct udevice *dev)
+{
+ struct piton_mmc_priv *priv = dev_get_priv(dev);
+ struct piton_mmc_plat *plat = dev_get_platdata(dev);
+ struct mmc_config *cfg;
+ struct mmc *mmc;
+ /* fill in device description */
+ struct blk_desc *bdesc;
+
+ priv->piton_mmc_base_addr = dev_read_addr(dev);
+ cfg = >cfg;
+ cfg->name = "PITON MMC";
+ cfg->host_caps = MMC_MODE_8BIT;
+ cfg->f_max = 10;
+ cfg->f_min = 40;
+ cfg->voltages = MMC_VDD_21_22;
+
+ mmc = >mmc;
+ mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
+ mmc->capacity_user = 0x1;
+ mmc->capacity_user *= mmc->read_bl_len;
+ mmc->capacity_boot = 0;
+ mmc->capacity_rpmb = 0;
+ for (int i = 0; i < 4; i++)
+ mmc->capacity_gp[i] = 0;
+ mmc->capacity = 0x20ULL;
+ mmc->has_init = 1;
+
+ bdesc = mmc_get_blk_desc(mmc);
+ bdesc->lun = 0;
+ bdesc->hwpart = 0;
+ bdesc->type = 0;
+ bdesc->blksz = mmc->read_bl_len;
+ bdesc->log2blksz = LOG2(bdesc->blksz);
+ bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
+
+ return 0;
+}
+
+/*
+ * currently, this is ignored. we only use fixed speed
+ */
+static int piton_mmc_set_ios(struct udevice *dev) { return 0; }
+
[PATCH V2 0/2] Add OpenPiton board support
This patch set is to add OpenPiton board support. Patches are split into several parts: - [PATCH 1/2] add OpenPiton support to mmc driver - [PATCH 2/2] add support for OpenPiton board Description - for mmc driver, it's settings are automatically configured at hardware level. We only need to expose the memory mapped interface through U-Boot driver model - For OpenPiton, as we need to embed the device tree blob into the bitstream, there is currently no itb support Tests checks - Able to boot Debian Linux from SD card on Digilent Genesys 2 - Checkpatch is performed, with some warnings ignored Changelogs - V2 . fix styles and typos in [1/2] and [2/2] . add board documentation in [2/2] arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/openpiton-riscv64.dts| 159 + board/openpiton/riscv/Kconfig | 42 ++ board/openpiton/riscv/MAINTAINERS | 6 + board/openpiton/riscv/Makefile | 5 + board/openpiton/riscv/openpiton-riscv.c | 41 ++ configs/openpiton_riscv64_defconfig | 132 doc/board/index.rst | 1 + doc/board/openpiton/index.rst | 9 + doc/board/openpiton/riscv64.rst | 885 drivers/mmc/Kconfig | 6 + drivers/mmc/Makefile| 1 + drivers/mmc/piton_mmc.c | 177 + include/configs/openpiton-riscv.h | 58 ++ 15 files changed, 1527 insertions(+) create mode 100644 arch/riscv/dts/openpiton-riscv64.dts create mode 100644 board/openpiton/riscv/Kconfig create mode 100644 board/openpiton/riscv/MAINTAINERS create mode 100644 board/openpiton/riscv/Makefile create mode 100644 board/openpiton/riscv/openpiton-riscv.c create mode 100644 configs/openpiton_riscv64_defconfig create mode 100644 doc/board/openpiton/index.rst create mode 100644 doc/board/openpiton/riscv64.rst create mode 100644 drivers/mmc/piton_mmc.c create mode 100644 include/configs/openpiton-riscv.h -- 2.17.1
