[PATCH] mtd: spi-nor-ids: Add support for flashes tested by xilinx
Add support for various flashes from below manufacturers which are tested
by xilinx for years.
EON:
en25q128b
GIGA:
gd25lx256e
ISSI:
is25lp008
is25lp016
is25lp01g
is25wp008
is25wp016
is25wp01g
is25wx256
MACRONIX:
mx25u51245f
mx66u1g45g
mx66l2g45g
MICRON:
mt35xl512aba
mt35xu01g
SPANSION:
s70fs01gs_256k
SST:
sst26wf016b
WINBOND:
w25q16dw
w25q16jv
w25q512jv
w25q32bv
w25h02jv
Signed-off-by: Ashok Reddy Soma
---
drivers/mtd/spi/spi-nor-ids.c | 37 +++
1 file changed, 37 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 7050ddc397..5d8bf05ff8 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -82,6 +82,7 @@ const struct flash_info spi_nor_ids[] = {
/* EON -- en25xxx */
{ INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) },
{ INFO("en25q64",0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
+ { INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) },
{ INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) },
{ INFO("en25s64",0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
#endif
@@ -127,11 +128,17 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ {
+ INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
+SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
+ },
#endif
#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
/* ISSI */
{ INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("is25lp008", 0x9d6014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) },
+ { INFO("is25lp016", 0x9d6015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) },
{ INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) },
{ INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) },
{ INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256,
@@ -140,6 +147,10 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ) },
{ INFO("is25lp512", 0x9d601a, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("is25wp008", 0x9d7014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) },
+ { INFO("is25wp016", 0x9d7015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) },
{ INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128,
@@ -151,6 +162,10 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_4B_OPCODES) },
{ INFO("is25wp512", 0x9d701a, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256,
+ SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
SPI_NOR_4B_OPCODES) },
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
/* Macronix */
@@ -176,8 +191,11 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) },
{ INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx25u51245f", 0xc2953a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx66u1g45g", 0xc2253b, 0, 64 * 1024, 2048, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ |
SPI_NOR_4B_OPCODES | SECT_4K) },
{ INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
@@ -208,8 +226,10 @@ const struct flash_info spi_nor_ids[] = {
{
Re: [PATCH v6 1/6] efi_loader: menu-driven addition of UEFI boot option
On Mon, May 16, 2022 at 08:00:37PM +0900, Masahisa Kojima wrote:
> This commit supports the menu-driven UEFI boot option addition.
> User can select the block device volume having
> efi_simple_file_system_protocol and select the file corresponding
> to the Boot variable. Then user enter the label of the BOOT
> variable in utf8.
>
> Signed-off-by: Masahisa Kojima
> ---
> Changes in v6:
> - fix typos
> - modify volume name to match U-Boot syntax
> - compile in CONFIG_EFI_LOADER=n and CONFIG_CMD_BOOTEFI_BOOTMGR=n
Is this correct?
> - simplify u16_strncmp() usage
> - support "a\b.efi" file path, use link list to handle filepath
> - modify length check condition
> - UEFI related menu items only appears with CONFIG_AUTOBOOT_MENU_SHOW=y
Why?
I think that the feature is useful even without AUTOBOOT.
As you know, efidebug is seen as a debugging tool and is not expected
to be enabled in production systems.
So the feature you're adding is the only available UI for boot manager.
What I recommend is
- to create a boot manager maintenance as a standalone U-Boot command,
- to add an bootmenu entry for invoking the command
> Changes in v5:
> - remove forward declarations
> - add const qualifier for menu items
> - fix the possible unaligned access for directory info access
> - split into three commit 1)add boot option 2) delete boot option 3)change
> boot order
> This commit is 1)add boot option.
> - fix file name buffer allocation size, it should be
> EFI_BOOTMENU_FILE_PATH_MAX * sizeof(u16)
> - fix wrong size checking for file selection
>
> Chanes in v4:
> - UEFI boot option maintenance menu is integrated into bootmenu
> - display the simplified volume name(e.g. usb0:1, nvme1:2) for the
> volume selection
> - instead of extending lib/efi_loader/efi_bootmgr.c, newly create
> lib/efi_loader/efi_bootmenu_maintenance.c and implement boot
> variable maintenance into it.
>
> Changes in RFC v3:
> not included in v3 series
>
> Changes in RFC v2:
> - enable utf8 user input for boot option name
> - create lib/efi_loader/efi_console.c::efi_console_get_u16_string() for
> utf8 user input handling
> - use u16_strlcat instead of u16_strcat
> - remove the EFI_CALLs, and newly create or expose the following
> xxx_int() functions.
> efi_locate_handle_buffer_int(), efi_open_volume_int(),
> efi_file_open_int(), efi_file_close_int(), efi_file_read_int() and
> efi_file_setpos_int().
> Note that EFI_CALLs still exist for EFI_DEVICE_PATH_TO_TEXT_PROTOCOL
> and EFI_SIMPLE_TEXT_INPUT/OUTPUT_PROTOCOL
> - use efi_search_protocol() instead of calling locate_protocol() to get
> the device_path_to_text_protocol interface.
> - remove unnecessary puts(ANSI_CLEAR_LINE), this patch is still depends on
> puts(ANSI_CLEAR_CONSOLE)
> - skip SetVariable() if the bootorder is not changed
>
> cmd/bootmenu.c| 73 +-
> include/efi_loader.h | 37 +
> lib/efi_loader/Makefile | 3 +
> lib/efi_loader/efi_bootmenu_maintenance.c | 906 ++
I would say that this file should be moved under /cmd as the code does not
implement any UEFI specification semantics, but simply provides helper
functions for bootmenu command.
Or I recommend that the boot manager be implemented as a standalone command
(as I insisted serveral times before) and the related maintenance feature
be invoked as follows:
=> efibootmanager -i (i for interactive)
> lib/efi_loader/efi_boottime.c | 52 +-
> lib/efi_loader/efi_console.c | 81 ++
> lib/efi_loader/efi_disk.c | 11 +
> lib/efi_loader/efi_file.c | 75 +-
> 8 files changed, 1184 insertions(+), 54 deletions(-)
> create mode 100644 lib/efi_loader/efi_bootmenu_maintenance.c
>
> diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c
> index 8859eebea5..4b846332b0 100644
> --- a/cmd/bootmenu.c
> +++ b/cmd/bootmenu.c
> @@ -19,6 +19,12 @@
>
> /* maximum bootmenu entries */
> #define MAX_COUNT99
> +#if defined(CONFIG_CMD_BOOTEFI_BOOTMGR) && defined(CONFIG_AUTOBOOT_MENU_SHOW)
> +#define STATIC_ENTRY 2
> +#else
> +#define STATIC_ENTRY 1
> +#endif
> +#define MAX_DYNAMIC_ENTRY (MAX_COUNT - STATIC_ENTRY)
>
> /* maximal size of bootmenu env
> * 9 = strlen("bootmenu_")
> @@ -38,10 +44,11 @@ enum boot_type {
> BOOTMENU_TYPE_NONE = 0,
> BOOTMENU_TYPE_BOOTMENU,
> BOOTMENU_TYPE_UEFI_BOOT_OPTION,
> + BOOTMENU_TYPE_UEFI_MAINTENANCE,
> };
>
> struct bootmenu_entry {
> - unsigned short int num; /* unique number 0 .. MAX_COUNT */
> + unsigned short int num; /* unique number 0 .. (MAX_COUNT - 1) */
> char key[3];/* key identifier of number */
> u16 *title; /* title of entry */
> char *command; /* hush command of entry */
> @@ -55,7 +62,7 @@ static char *bootmenu_getoption(unsigned short int n)
> {
> char name[MAX_ENV_SIZE];
>
>
Re: [PATCH] doc: environment: Fix typo
On Wed, May 25, 2022 at 9:09 AM Chris Packham wrote: > > "valu" should be "value". > > Signed-off-by: Chris Packham > --- > > doc/usage/environment.rst | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Bin Meng
[PATCH] doc: environment: Fix typo
"valu" should be "value". Signed-off-by: Chris Packham --- doc/usage/environment.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst index dc6170394460..28a8952b7528 100644 --- a/doc/usage/environment.rst +++ b/doc/usage/environment.rst @@ -347,7 +347,7 @@ bootpretryperiod Unsigned value, in milliseconds. If not set, the period will be either the default (28000), or a value based on CONFIG_NET_RETRY_COUNT, if defined. This value has -precedence over the valu based on CONFIG_NET_RETRY_COUNT. +precedence over the value based on CONFIG_NET_RETRY_COUNT. memmatches Number of matches found by the last 'ms' command, in hex -- 2.36.1
Pull request: u-boot-sunxi/master fixes for v2022.07
Hi Tom, please pull the master branch from u-boot-sunxi, containing fixes and updates for 2022.07. The bulk of it is (finally!) some DT sync from the kernel. We refrained from syncing one incompatible change, as this would spoil booting Linux kernels before v5.13 with U-Boot's DT (via UEFI, for instance). I test booted Linux v5.18 and v5.4 with that new DT on some boards, and the headless peripherals (MMC, USB, Ethernet) seemed to work. The rest are fixes: - silencing missing clock warnings due to the new pinctrl driver - fixing "UART0 on PortF", allowing UART access through the SD card pins - add an F1C100s clock driver, to enable MMC support (SPI comes later) - some cleanups for CONS_INDEX_n in Kconfig Tested on BananaPi-M1, Pine64-LTS, Pine-H64, X96-Mate (H616) and OrangePi-Zero. Thanks, Andre === The following changes since commit 6f00b97d7e5760d92566317dde6c4b9224790827: Merge https://source.denx.de/u-boot/custodians/u-boot-usb (2022-05-20 22:07:56 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-sunxi.git master for you to fetch changes up to 7495051219b64ec0e8fac8930586dc10666530da: serial: Remove obsolete CONS_INDEX_n Kconfig options (2022-05-24 01:46:06 +0100) Andre Przywara (5): sunxi: F1C100s: update DT files from Linux Revert "sunxi: f1c100s: Drop SYSRESET to enable reset functionality" clk: sunxi: add PIO bus gate clocks clk: sunxi: add and use dummy gate clocks sunxi: board: Fix UART PortF pinmux setup George Hilliard (1): clk: sunxi: implement clock driver for suniv f1c100s Samuel Holland (17): dt-bindings: sunxi: Update clock/reset binding headers ARM: dts: sunxi: Remove unused devicetree headers ARM: dts: sun7i: Sync from Linux v5.18-rc1 ARM: dts: sun4i: Sync from Linux v5.18-rc1 ARM: dts: sunxi: A13/A31/A23/A33: Sync from Linux v5.18-rc1 ARM: dts: sun9i: Sync from Linux v5.18-rc1 ARM: dts: sun8i: A83T: Sync from Linux v5.18-rc1 ARM: dts: sunxi: H2+/H3/H5: Sync from Linux v5.18-rc1 ARM: dts: sun8i: V3/V3s/S3: Sync from Linux v5.18-rc1 ARM: dts: sun8i: R40/T3: Sync from Linux v5.18-rc1 ARM: dts: sun50i: A64: Sync from Linux v5.18-rc1 ARM: dts: sun50i: H6: Sync from Linux v5.18-rc1 sunxi: Skip MMC0 init when its pinmux conflicts with UART0 mmc: sunxi: Remove unnecessary pinmux option dependency clk: sunxi: h6_r: Correct the driver name sunxi: Remove obsolete Kconfig selections serial: Remove obsolete CONS_INDEX_n Kconfig options arch/arm/dts/Makefile | 22 +- arch/arm/dts/axp22x.dtsi | 11 +- arch/arm/dts/axp803.dtsi | 10 +- arch/arm/dts/axp81x.dtsi | 15 +- arch/arm/dts/sun4i-a10-inet97fv2.dts | 22 +- arch/arm/dts/sun50i-a64-cpu-opp.dtsi | 2 +- arch/arm/dts/sun50i-a64-orangepi-win.dts | 2 +- arch/arm/dts/sun50i-a64-pinebook.dts | 1 + arch/arm/dts/sun50i-a64-pinephone.dtsi | 27 ++ arch/arm/dts/sun50i-a64-pinetab.dts| 29 +- arch/arm/dts/sun50i-a64-teres-i.dts| 4 +- arch/arm/dts/sun50i-a64.dtsi | 93 -- arch/arm/dts/sun50i-h5-cpu-opp.dtsi| 2 +- arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts | 9 +- arch/arm/dts/sun50i-h5.dtsi| 6 +- arch/arm/dts/sun50i-h6-beelink-gs1.dts | 38 +-- arch/arm/dts/sun50i-h6-cpu-opp.dtsi| 2 +- arch/arm/dts/sun50i-h6-orangepi-3.dts | 14 +- arch/arm/dts/sun50i-h6-orangepi.dtsi | 22 +- arch/arm/dts/sun50i-h6-pine-h64-model-b.dts| 51 arch/arm/dts/sun50i-h6-tanix-tx6-mini.dts | 15 + arch/arm/dts/sun50i-h6-tanix-tx6.dts | 115 +-- arch/arm/dts/sun50i-h6-tanix.dtsi | 189 arch/arm/dts/sun50i-h6.dtsi| 26 +- arch/arm/dts/sun5i-a10s-auxtek-t003.dts| 16 +- arch/arm/dts/sun5i-a10s-auxtek-t004.dts| 35 +-- arch/arm/dts/sun5i-a10s-mk802.dts | 31 +- arch/arm/dts/sun5i-a10s-olinuxino-micro.dts| 68 + arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts | 22 +- arch/arm/dts/sun5i-a10s-wobo-i5.dts| 34 +-- arch/arm/dts/sun5i-a10s.dtsi | 30 +- arch/arm/dts/sun5i-a13-ampe-a76.dts| 2 +- arch/arm/dts/sun5i-a13-empire-electronix-d709.dts | 41 +-- arch/arm/dts/sun5i-a13-hsg-h702.dts| 37 +-- arch/arm/dts/sun5i-a13-inet-86vs.dts | 2 +- ...i-q8-common.dtsi => sun5i-a13-licheepi-one.dts} | 146 + arch/arm/dts/sun5i-a13-olinuxino-micro.dts | 50 +--- arch/arm/dts/sun5i-a13-olinuxino.dts
Re: [u-boot PATCH 3/3] k3-am642-evm-u-boot: Use binman to generate u-boot.img and tispl.bin
On 5/9/22 2:29 AM, Roger Quadros wrote:
Introduce k3-am642-evm-binman.dtsi to provide binman configuration.
R5 build is still not converted to use binman so restrict binman.dtsi
to A53 builds only.
This patch also take care of building Secure (HS) images using
binman instead of tools/k3_fit_atf.sh if CONFIG_BINMAN is set.
Signed-off-by: Roger Quadros
---
arch/arm/dts/k3-am642-evm-binman.dtsi | 230 ++
arch/arm/dts/k3-am642-evm-u-boot.dtsi | 3 +
arch/arm/mach-k3/Kconfig | 1 +
arch/arm/mach-k3/config.mk| 7 +
4 files changed, 241 insertions(+)
create mode 100644 arch/arm/dts/k3-am642-evm-binman.dtsi
diff --git a/arch/arm/dts/k3-am642-evm-binman.dtsi
b/arch/arm/dts/k3-am642-evm-binman.dtsi
new file mode 100644
index 00..9e85ef41b0
--- /dev/null
+++ b/arch/arm/dts/k3-am642-evm-binman.dtsi
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+#ifdef CONFIG_TARGET_AM642_A53_EVM
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+#define TISPL "tispl.bin_HS"
+#define UBOOT_IMG "u-boot.img_HS"
+#else
+#define TISPL "tispl.bin"
+#define UBOOT_IMG "u-boot.img"
+#endif
+
+#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
+#define SPL_AM642_EVM_DTB "spl/dts/k3-am642-evm.dtb"
+#define SPL_AM642_SK_DTB "spl/dts/k3-am642-sk.dtb"
+
+#define UBOOT_NODTB "u-boot-nodtb.bin"
+#define AM642_EVM_DTB "arch/arm/dts/k3-am642-evm.dtb"
+#define AM642_SK_DTB "arch/arm/dts/k3-am642-sk.dtb"
+
+ {
+ ti-spl {
+ filename = TISPL;
+ pad-byte = <0xff>;
+
+ fit {
+ description = "Configuration to load ATF and SPL";
+ #address-cells = <1>;
+
+ images {
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ os = "arm-trusted-firmware";
+ load = ;
+ entry = ;
+ atf-bl31 {
+ filename = "bl31.bin";
+ };
On HS, bl31.bin and the below TEE and DM images must also be signed
before being packaged into tispl.bin.
Can we add signing here?
Andrew
+ };
+
+ tee {
+ description = "OPTEE";
+ type = "tee";
+ arch = "arm64";
+ compression = "none";
+ os = "tee";
+ load = <0x9e80>;
+ entry = <0x9e80>;
+ tee-os {
+ filename = "tee-pager_v2.bin";
+ };
+ };
+
+ dm {
+ description = "DM binary";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "DM";
+ load = <0x8900>;
+ entry = <0x8900>;
+ blob-ext {
+ filename = "/dev/null";
+ };
+ };
+
+ spl {
+ description = "SPL (64-bit)";
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <0x8008>;
+ entry = <0x8008>;
+#ifdef CONFIG_TI_SECURE_DEVICE
+ ti-secure {
+#else
+ blob {
+#endif
+ filename = SPL_NODTB;
+ };
+ };
+
+ fdt-1 {
+ description = "k3-am642-evm";
+ type = "flat_dt";
+ arch = "arm";
+
Re: [PATCH] bootmenu: fix bootmenu title handling
On Tuesday 24 May 2022 09:43:56 Pali Rohár wrote:
> On Tuesday 24 May 2022 12:45:30 Masahisa Kojima wrote:
> > The commit a3d0aa87acbe ("bootmenu: update bootmenu_entry structure")
> > changes the bootmenu title type from char to u16(UTF16 string)
> > to support EFI based system. If EFI_LOADER is not enabled,
> > printf("%ls") is not supported, so bootmenu does not appear
> > correctly.
> >
> > This commit switches the menu title type from "char" to "u16"
> > only when the EFI_LOADER is enabled.
> >
> > Fixes: a3d0aa87acbe ("bootmenu: update bootmenu_entry structure")
> > Signed-off-by: Masahisa Kojima
> > ---
> > cmd/bootmenu.c | 48
> > 1 file changed, 32 insertions(+), 16 deletions(-)
> >
> > diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c
> > index 8859eebea5..e422e0b348 100644
> > --- a/cmd/bootmenu.c
> > +++ b/cmd/bootmenu.c
> > @@ -20,6 +20,20 @@
> > /* maximum bootmenu entries */
> > #define MAX_COUNT 99
> >
> > +#if (CONFIG_IS_ENABLED(EFI_LOADER))
> > +#define TITLE_CHAR u16
> > +#define titlefmt "ls"
> > +#define TITLE_STRDUP u16_strdup
> > +#define TITLE_STRNCPY(d, s, l) utf8_utf16_strncpy(, s, l)
> > +#define TITLE_STR(x) u##x
> > +#else
> > +#define TITLE_CHAR char
> > +#define titlefmt "s"
> > +#define TITLE_STRDUP strdup
> > +#define TITLE_STRNCPY(d, s, l) strncpy(d, s, l)
> > +#define TITLE_STR(x) x
> > +#endif
>
> This reminds me win98 days with tchar macros when NT systems used UCS-2
> and DOS systems OEM codepage... Do we really have to use these 20 years
> old patterns in new code?
>
> Still, I do not see reason why EFI bloatware code has to be in common
> U-boot code and not in separated parts?
Anyway, now I have tested this patch, menu entries are now printed on
serial console correctly, but still I'm not able to terminate bootmenu
by CTRL+C like before that commit. So bootmenu is still broken on nokia
n900.
> > +
> > /* maximal size of bootmenu env
> > * 9 = strlen("bootmenu_")
> > * 2 = strlen(MAX_COUNT)
> > @@ -43,7 +57,7 @@ enum boot_type {
> > struct bootmenu_entry {
> > unsigned short int num; /* unique number 0 .. MAX_COUNT */
> > char key[3];/* key identifier of number */
> > - u16 *title; /* title of entry */
> > + TITLE_CHAR *title; /* title of entry */
> > char *command; /* hush command of entry */
> > enum boot_type type;/* boot type of entry */
> > u16 bootorder; /* order for each boot type */
> > @@ -76,7 +90,7 @@ static void bootmenu_print_entry(void *data)
> > if (reverse)
> > puts(ANSI_COLOR_REVERSE);
> >
> > - printf("%ls", entry->title);
> > + printf("%" titlefmt "", entry->title);
> >
> > if (reverse)
> > puts(ANSI_COLOR_RESET);
> > @@ -170,7 +184,7 @@ static int prepare_bootmenu_entry(struct bootmenu_data
> > *menu,
> > struct bootmenu_entry *iter = *current;
> >
> > while ((option = bootmenu_getoption(i))) {
> > - u16 *buf;
> > + TITLE_CHAR *buf;
> >
> > sep = strchr(option, '=');
> > if (!sep) {
> > @@ -183,13 +197,13 @@ static int prepare_bootmenu_entry(struct
> > bootmenu_data *menu,
> > return -ENOMEM;
> >
> > len = sep-option;
> > - buf = calloc(1, (len + 1) * sizeof(u16));
> > + buf = calloc(1, (len + 1) * sizeof(TITLE_CHAR));
> > entry->title = buf;
> > if (!entry->title) {
> > free(entry);
> > return -ENOMEM;
> > }
> > - utf8_utf16_strncpy(, option, len);
> > + TITLE_STRNCPY(buf, option, len);
> >
> > len = strlen(sep + 1);
> > entry->command = malloc(len + 1);
> > @@ -227,6 +241,7 @@ static int prepare_bootmenu_entry(struct bootmenu_data
> > *menu,
> > return 1;
> > }
> >
> > +#if (CONFIG_IS_ENABLED(CMD_BOOTEFI_BOOTMGR))
> > /**
> > * prepare_uefi_bootorder_entry() - generate the uefi bootmenu entries
> > *
> > @@ -315,6 +330,7 @@ static int prepare_uefi_bootorder_entry(struct
> > bootmenu_data *menu,
> >
> > return 1;
> > }
> > +#endif
> >
> > static struct bootmenu_data *bootmenu_create(int delay)
> > {
> > @@ -341,13 +357,13 @@ static struct bootmenu_data *bootmenu_create(int
> > delay)
> > if (ret < 0)
> > goto cleanup;
> >
> > - if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR)) {
> > - if (i < MAX_COUNT - 1) {
> > - ret = prepare_uefi_bootorder_entry(menu, , );
> > - if (ret < 0 && ret != -ENOENT)
> > - goto cleanup;
> > - }
> > +#if (CONFIG_IS_ENABLED(CMD_BOOTEFI_BOOTMGR))
> > + if (i < MAX_COUNT - 1) {
> > + ret = prepare_uefi_bootorder_entry(menu, , );
> > + if (ret < 0 && ret != -ENOENT)
> > + goto cleanup;
> >
Re: [PATCH] net: Add missing PCI dependency for CONFIG_E1000
On 5/24/22 1:16 PM, Pali Rohár wrote: > On Tuesday 24 May 2022 13:12:02 Sean Anderson wrote: >> Hi Pali, >> >> On 5/23/22 4:41 AM, Pali Rohár wrote: >> > Signed-off-by: Pali Rohár >> > --- >> > drivers/net/Kconfig | 1 + >> > 1 file changed, 1 insertion(+) >> > >> > diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig >> > index 7fe0e00649cf..84d859c21eb8 100644 >> > --- a/drivers/net/Kconfig >> > +++ b/drivers/net/Kconfig >> > @@ -231,6 +231,7 @@ config DWC_ETH_QOS_TEGRA186 >> > >> > config E1000 >> >bool "Intel PRO/1000 Gigabit Ethernet support" >> > + depends on PCI >> >help >> > This driver supports Intel(R) PRO/1000 gigabit ethernet family of >> > adapters. For more information on how to identify your adapter, go >> > >> >> This appears to be a duplicate of [1]. >> >> [1] >> https://lore.kernel.org/u-boot/20220426183533.3224252-1-sean.ander...@seco.com/ >> >> --Sean > > Interesting... this is my second duplicate patch this week. > > Any idea why above patch was not accepted yet? Looks like Ramon has not done a pull request since mid April [1]. Though based on the past pattern, it seems like he just makes one PR each release. Perhaps Tom can pick this up? [1] https://lore.kernel.org/u-boot/cagi-ruk9pev+j8ocjxtejxnky-lm+3sgysckuyjerhldzxa...@mail.gmail.com/ --Sean
Re: [PATCH] net: Add missing PCI dependency for CONFIG_E1000
On Tuesday 24 May 2022 13:12:02 Sean Anderson wrote: > Hi Pali, > > On 5/23/22 4:41 AM, Pali Rohár wrote: > > Signed-off-by: Pali Rohár > > --- > > drivers/net/Kconfig | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig > > index 7fe0e00649cf..84d859c21eb8 100644 > > --- a/drivers/net/Kconfig > > +++ b/drivers/net/Kconfig > > @@ -231,6 +231,7 @@ config DWC_ETH_QOS_TEGRA186 > > > > config E1000 > > bool "Intel PRO/1000 Gigabit Ethernet support" > > + depends on PCI > > help > > This driver supports Intel(R) PRO/1000 gigabit ethernet family of > > adapters. For more information on how to identify your adapter, go > > > > This appears to be a duplicate of [1]. > > [1] > https://lore.kernel.org/u-boot/20220426183533.3224252-1-sean.ander...@seco.com/ > > --Sean Interesting... this is my second duplicate patch this week. Any idea why above patch was not accepted yet? I'm just testing U-Boot builds and I hit the same issue in dependency graph.
Re: [PATCH] net: Add missing PCI dependency for CONFIG_E1000
Hi Pali, On 5/23/22 4:41 AM, Pali Rohár wrote: > Signed-off-by: Pali Rohár > --- > drivers/net/Kconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig > index 7fe0e00649cf..84d859c21eb8 100644 > --- a/drivers/net/Kconfig > +++ b/drivers/net/Kconfig > @@ -231,6 +231,7 @@ config DWC_ETH_QOS_TEGRA186 > > config E1000 > bool "Intel PRO/1000 Gigabit Ethernet support" > + depends on PCI > help > This driver supports Intel(R) PRO/1000 gigabit ethernet family of > adapters. For more information on how to identify your adapter, go > This appears to be a duplicate of [1]. [1] https://lore.kernel.org/u-boot/20220426183533.3224252-1-sean.ander...@seco.com/ --Sean
Re: [PATCH 2/2] clk: sunxi: add and use dummy gate clocks
On Fri, 6 May 2022 01:33:01 +0100
Andre Przywara wrote:
> Some devices enumerate various clocks in their DT, and many drivers
> just blanketly try to enable all of them. This creates problems
> since we only model a few gate clocks, and the clock driver outputs
> a warning when a clock is not described:
> =
> sunxi_set_gate: (CLK#3) unhandled
> =
>
> Some clocks don't have an enable bit, or are already enabled in a
> different way, so we might want to just ignore them.
>
> Add a CCU_CLK_F_DUMMY_GATE flag that indicates that case, and define
> a GATE_DUMMY macro that can be used in the clock description array.
> Define a few clocks, used by some pinctrl devices, that way to suppress
> the runtime warnings.
>
> Signed-off-by: Andre Przywara
Applied to sunxi/master.
Thanks,
Andre
> ---
> drivers/clk/sunxi/clk_h6.c| 2 ++
> drivers/clk/sunxi/clk_h616.c | 2 ++
> drivers/clk/sunxi/clk_h6_r.c | 2 ++
> drivers/clk/sunxi/clk_sunxi.c | 3 +++
> include/clk/sunxi.h | 5 +
> 5 files changed, 14 insertions(+)
>
> diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
> index f4e26cbcd45..b3202342932 100644
> --- a/drivers/clk/sunxi/clk_h6.c
> +++ b/drivers/clk/sunxi/clk_h6.c
> @@ -16,6 +16,8 @@
> static struct ccu_clk_gate h6_gates[] = {
> [CLK_PLL_PERIPH0] = GATE(0x020, BIT(31)),
>
> + [CLK_APB1] = GATE_DUMMY,
> +
> [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
> [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
> [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c
> index 65ab44643da..80099727def 100644
> --- a/drivers/clk/sunxi/clk_h616.c
> +++ b/drivers/clk/sunxi/clk_h616.c
> @@ -15,6 +15,8 @@
> static struct ccu_clk_gate h616_gates[] = {
> [CLK_PLL_PERIPH0] = GATE(0x020, BIT(31) | BIT(27)),
>
> + [CLK_APB1] = GATE_DUMMY,
> +
> [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
> [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
> [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_h6_r.c b/drivers/clk/sunxi/clk_h6_r.c
> index 2e0bbaa903b..c592886a258 100644
> --- a/drivers/clk/sunxi/clk_h6_r.c
> +++ b/drivers/clk/sunxi/clk_h6_r.c
> @@ -11,6 +11,8 @@
> #include
>
> static struct ccu_clk_gate h6_r_gates[] = {
> + [CLK_R_APB1]= GATE_DUMMY,
> +
> [CLK_R_APB1_TIMER] = GATE(0x11c, BIT(0)),
> [CLK_R_APB1_TWD]= GATE(0x12c, BIT(0)),
> [CLK_R_APB1_PWM]= GATE(0x13c, BIT(0)),
> diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c
> index 9673b58a492..9a21367a5d0 100644
> --- a/drivers/clk/sunxi/clk_sunxi.c
> +++ b/drivers/clk/sunxi/clk_sunxi.c
> @@ -27,6 +27,9 @@ static int sunxi_set_gate(struct clk *clk, bool on)
> const struct ccu_clk_gate *gate = priv_to_gate(priv, clk->id);
> u32 reg;
>
> + if ((gate->flags & CCU_CLK_F_DUMMY_GATE))
> + return 0;
> +
> if (!(gate->flags & CCU_CLK_F_IS_VALID)) {
> printf("%s: (CLK#%ld) unhandled\n", __func__, clk->id);
> return 0;
> diff --git a/include/clk/sunxi.h b/include/clk/sunxi.h
> index a2239b990b8..c4a9dee5ebf 100644
> --- a/include/clk/sunxi.h
> +++ b/include/clk/sunxi.h
> @@ -18,6 +18,7 @@
> enum ccu_flags {
> CCU_CLK_F_IS_VALID = BIT(0),
> CCU_RST_F_IS_VALID = BIT(1),
> + CCU_CLK_F_DUMMY_GATE= BIT(2),
> };
>
> /**
> @@ -38,6 +39,10 @@ struct ccu_clk_gate {
> .flags = CCU_CLK_F_IS_VALID,\
> }
>
> +#define GATE_DUMMY { \
> + .flags = CCU_CLK_F_DUMMY_GATE, \
> +}
> +
> /**
> * struct ccu_reset - ccu reset
> * @off: reset offset
Re: [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1
On Wed, 27 Apr 2022 15:31:19 -0500 Samuel Holland wrote: > This series brings all of our devicetrees up to date with Linux. > > Older SoCs (before A83T) have not been synchronized in over 3 years. > And I don't have any of this hardware to test. But there are not major > changes to those devicetrees either. > > The big motivation for including older SoCs in this update is converting > the USB PHY driver to get its VBUS detection GPIO/regulator from the > devicetree instead of from a pin name in Kconfig. Many older boards had > those properties added or fixed since the last devicetree sync. This PHY > driver change is necessary to complete the DM_GPIO migration. > > A couple of breaking changes were made to several SoCs' devicetrees in > Linux relating to the "r_intc" interrupt controller. New kernels support > old devicetrees, but not the other way around. So to be most compatible > and avoid regressions, those changes are skipped here. Applied the whole series to sunxi/master, including the Mele M5 fix. Thanks! Andre > > > Samuel Holland (12): > dt-bindings: sunxi: Update clock/reset binding headers > ARM: dts: sunxi: Remove unused devicetree headers > ARM: dts: sun4i: Sync from Linux v5.18-rc1 > ARM: dts: sun7i: Sync from Linux v5.18-rc1 > ARM: dts: sunxi: A13/A31/A23/A33: Sync from Linux v5.18-rc1 > ARM: dts: sun9i: Sync from Linux v5.18-rc1 > ARM: dts: sun8i: A83T: Sync from Linux v5.18-rc1 > ARM: dts: sunxi: H2+/H3/H5: Sync from Linux v5.18-rc1 > ARM: dts: sun8i: V3/V3s/S3: Sync from Linux v5.18-rc1 > ARM: dts: sun8i: R40/T3: Sync from Linux v5.18-rc1 > ARM: dts: sun50i: A64: Sync from Linux v5.18-rc1 > ARM: dts: sun50i: H6: Sync from Linux v5.18-rc1 > > arch/arm/dts/Makefile | 25 +- > arch/arm/dts/axp209.dtsi | 6 +- > arch/arm/dts/axp22x.dtsi | 11 +- > arch/arm/dts/axp803.dtsi | 10 +- > arch/arm/dts/axp81x.dtsi | 15 +- > arch/arm/dts/sun4i-a10-a1000.dts | 31 +- > arch/arm/dts/sun4i-a10-ba10-tvbox.dts | 2 +- > arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts| 20 +- > arch/arm/dts/sun4i-a10-cubieboard.dts | 16 +- > arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts | 21 +- > arch/arm/dts/sun4i-a10-hackberry.dts | 2 +- > arch/arm/dts/sun4i-a10-hyundai-a7hd.dts | 20 +- > arch/arm/dts/sun4i-a10-inet1.dts | 21 +- > arch/arm/dts/sun4i-a10-inet97fv2.dts | 22 +- > arch/arm/dts/sun4i-a10-inet9f-rev03.dts | 74 ++-- > .../dts/sun4i-a10-itead-iteaduino-plus.dts| 2 +- > arch/arm/dts/sun4i-a10-jesurun-q5.dts | 4 +- > arch/arm/dts/sun4i-a10-marsboard.dts | 22 +- > arch/arm/dts/sun4i-a10-olinuxino-lime.dts | 33 +- > arch/arm/dts/sun4i-a10-pcduino.dts| 20 +- > arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts | 21 +- > arch/arm/dts/sun4i-a10-topwise-a721.dts | 242 + > arch/arm/dts/sun4i-a10.dtsi | 135 ++- > arch/arm/dts/sun50i-a64-cpu-opp.dtsi | 2 +- > arch/arm/dts/sun50i-a64-orangepi-win.dts | 2 +- > arch/arm/dts/sun50i-a64-pinebook.dts | 1 + > arch/arm/dts/sun50i-a64-pinephone.dtsi| 27 ++ > arch/arm/dts/sun50i-a64-pinetab.dts | 29 +- > arch/arm/dts/sun50i-a64-teres-i.dts | 4 +- > arch/arm/dts/sun50i-a64.dtsi | 93 +++-- > arch/arm/dts/sun50i-h5-cpu-opp.dtsi | 2 +- > arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts | 9 +- > arch/arm/dts/sun50i-h5.dtsi | 6 +- > arch/arm/dts/sun50i-h6-beelink-gs1.dts| 38 +- > arch/arm/dts/sun50i-h6-cpu-opp.dtsi | 2 +- > arch/arm/dts/sun50i-h6-orangepi-3.dts | 14 +- > arch/arm/dts/sun50i-h6-orangepi.dtsi | 22 +- > arch/arm/dts/sun50i-h6-pine-h64-model-b.dts | 51 +++ > arch/arm/dts/sun50i-h6-tanix-tx6-mini.dts | 15 + > arch/arm/dts/sun50i-h6-tanix-tx6.dts | 115 +- > arch/arm/dts/sun50i-h6-tanix.dtsi | 189 ++ > arch/arm/dts/sun50i-h6.dtsi | 26 +- > arch/arm/dts/sun5i-a10s-auxtek-t003.dts | 16 +- > arch/arm/dts/sun5i-a10s-auxtek-t004.dts | 35 +- > arch/arm/dts/sun5i-a10s-mk802.dts | 31 +- > arch/arm/dts/sun5i-a10s-olinuxino-micro.dts | 68 +--- > arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts | 22 +- > arch/arm/dts/sun5i-a10s-wobo-i5.dts | 34 +- > arch/arm/dts/sun5i-a10s.dtsi | 30 +- > arch/arm/dts/sun5i-a13-ampe-a76.dts | 2 +- > .../dts/sun5i-a13-empire-electronix-d709.dts | 41 +-- > arch/arm/dts/sun5i-a13-hsg-h702.dts | 37 +- > arch/arm/dts/sun5i-a13-inet-86vs.dts | 2 +- > ...common.dtsi => sun5i-a13-licheepi-one.dts} | 146 +--- > arch/arm/dts/sun5i-a13-olinuxino-micro.dts| 50 +-- > arch/arm/dts/sun5i-a13-olinuxino.dts
Re: [PATCH] sunxi: board: Fix UART PortF pinmux setup
On Fri, 6 May 2022 01:37:03 +0100 Andre Przywara wrote: > When CONFIG_UART0_PORT_F is defined, we try to configure two PortF pins > (usually used for the SD card) as UART0. Some SoCs use the mux value of > 3 for this, while others use 4. > > The combination of Kconfig symbols we currently use was not quite right: > we mis-configure the A31, A64, H6 and H616. > > Going through the list in the pinctrl driver, there are only a few older > SoCs that use a value of 4, so revert the #ifdef clause, and name those > explicitly, instead of the other way around. > > Signed-off-by: Andre Przywara Applied to sunxi/master. Thanks, Andre > --- > arch/arm/mach-sunxi/board.c | 13 +++-- > 1 file changed, 7 insertions(+), 6 deletions(-) > > diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c > index 173e946465d..8f7c894286d 100644 > --- a/arch/arm/mach-sunxi/board.c > +++ b/arch/arm/mach-sunxi/board.c > @@ -87,15 +87,16 @@ static int gpio_init(void) > sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); > sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); > #endif > -#if (defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)) || \ > -defined(CONFIG_MACH_SUNIV) > - sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); > - sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); > -#else > +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || \ > +defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I_R40) || \ > +defined(CONFIG_MACH_SUN9I) > sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0); > sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0); > +#else > + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); > + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); > #endif > - sunxi_gpio_set_pull(SUNXI_GPF(4), 1); > + sunxi_gpio_set_pull(SUNXI_GPF(4), SUNXI_GPIO_PULL_UP); > #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV) > sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0); > sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0);
Re: [PATCH] clk: sunxi: h6_r: Correct the driver name
On Sat, 23 Apr 2022 16:07:16 -0500
Samuel Holland wrote:
> H6 is from the sun50i family, not sun6i.
>
> Signed-off-by: Samuel Holland
Applied to sunxi/master.
Thanks!
Andre
> ---
>
> drivers/clk/sunxi/clk_h6_r.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/sunxi/clk_h6_r.c b/drivers/clk/sunxi/clk_h6_r.c
> index b9e527e16a..2e0bbaa903 100644
> --- a/drivers/clk/sunxi/clk_h6_r.c
> +++ b/drivers/clk/sunxi/clk_h6_r.c
> @@ -50,8 +50,8 @@ static const struct udevice_id h6_r_clk_ids[] = {
> { }
> };
>
> -U_BOOT_DRIVER(clk_sun6i_h6_r) = {
> - .name = "sun6i_h6_r_ccu",
> +U_BOOT_DRIVER(clk_sun50i_h6_r) = {
> + .name = "sun50i_h6_r_ccu",
> .id = UCLASS_CLK,
> .of_match = h6_r_clk_ids,
> .priv_auto = sizeof(struct ccu_priv),
Re: [PATCH 1/2] sunxi: Skip MMC0 init when its pinmux conflicts with UART0
On Sun, 10 Apr 2022 00:13:33 -0500
Samuel Holland wrote:
> Currently, selecting UART0_PORT_F entirely disables MMC support on sunxi
> platforms. But this is a bigger hammer then needed. Muxing UART0 to the
> pins on port F only causes a conflict with MMC0, so minimize the impact
> by specifically skipping MMC0 init. We can continue to use MMC1/2 if
> those are enabled.
>
> Let's also remove the preprocessor check while refacting this function.
>
> Signed-off-by: Samuel Holland
Applied to sunxi/master.
Thanks,
Andre
> ---
>
> board/sunxi/board.c | 22 ++
> 1 file changed, 10 insertions(+), 12 deletions(-)
>
> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> index 89324159d5..7822001d99 100644
> --- a/board/sunxi/board.c
> +++ b/board/sunxi/board.c
> @@ -516,19 +516,17 @@ static void mmc_pinmux_setup(int sdc)
>
> int board_mmc_init(struct bd_info *bis)
> {
> - __maybe_unused struct mmc *mmc0, *mmc1;
> -
> - mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
> - mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
> - if (!mmc0)
> - return -1;
> + if (!IS_ENABLED(CONFIG_UART0_PORT_F)) {
> + mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
> + if (!sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT))
> + return -1;
> + }
>
> -#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
> - mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
> - mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
> - if (!mmc1)
> - return -1;
> -#endif
> + if (CONFIG_MMC_SUNXI_SLOT_EXTRA != -1) {
> + mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
> + if (!sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA))
> + return -1;
> + }
>
> return 0;
> }
Re: [PATCH 1/7] clk: sunxi: implement clock driver for suniv f1c100s
On Tue, 3 May 2022 22:20:34 +0100
Andre Przywara wrote:
> From: George Hilliard
>
> The f1c100s has a clock tree similar to those of other sunxi parts.
> Add support for it.
>
> Signed-off-by: George Hilliard
> Signed-off-by: Yifan Gu
> Acked-by: Sean Anderson
> [Andre: add PIO and I2C]
> Signed-off-by: Andre Przywara
Applied to sunxi/master.
Thanks,
Andre
> ---
> drivers/clk/sunxi/Kconfig | 7
> drivers/clk/sunxi/Makefile | 1 +
> drivers/clk/sunxi/clk_f1c100s.c | 74 +
> 3 files changed, 82 insertions(+)
> create mode 100644 drivers/clk/sunxi/clk_f1c100s.c
>
> diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
> index f19908113e1..bf11fad6eef 100644
> --- a/drivers/clk/sunxi/Kconfig
> +++ b/drivers/clk/sunxi/Kconfig
> @@ -10,6 +10,13 @@ config CLK_SUNXI
>
> if CLK_SUNXI
>
> +config CLK_SUNIV_F1C100S
> + bool "Clock driver for Allwinner F1C100s"
> + default MACH_SUNIV
> + help
> + This enables common clock driver support for platforms based
> + on Allwinner F1C100s SoC.
> +
> config CLK_SUN4I_A10
> bool "Clock driver for Allwinner A10/A20"
> default MACH_SUN4I || MACH_SUN7I
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index 48a48a2f000..895da02ebea 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -8,6 +8,7 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
>
> obj-$(CONFIG_CLK_SUNXI) += clk_sun6i_rtc.o
>
> +obj-$(CONFIG_CLK_SUNIV_F1C100S) += clk_f1c100s.o
> obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
> obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
> obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
> diff --git a/drivers/clk/sunxi/clk_f1c100s.c b/drivers/clk/sunxi/clk_f1c100s.c
> new file mode 100644
> index 000..72cf8a6e5c0
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk_f1c100s.c
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: (GPL-2.0+)
> +/*
> + * Copyright (C) 2019 George Hilliard .
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +static struct ccu_clk_gate f1c100s_gates[] = {
> + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
> + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
> + [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
> + [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
> + [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
> +
> + [CLK_BUS_I2C0] = GATE(0x068, BIT(16)),
> + [CLK_BUS_I2C1] = GATE(0x068, BIT(17)),
> + [CLK_BUS_I2C2] = GATE(0x068, BIT(18)),
> + [CLK_BUS_PIO] = GATE(0x068, BIT(19)),
> +
> + [CLK_BUS_UART0] = GATE(0x06c, BIT(20)),
> + [CLK_BUS_UART1] = GATE(0x06c, BIT(21)),
> + [CLK_BUS_UART2] = GATE(0x06c, BIT(22)),
> +
> + [CLK_USB_PHY0] = GATE(0x0cc, BIT(1)),
> +};
> +
> +static struct ccu_reset f1c100s_resets[] = {
> + [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
> +
> + [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
> + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
> + [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
> + [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
> + [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
> +
> + [RST_BUS_I2C0] = RESET(0x2d0, BIT(16)),
> + [RST_BUS_I2C1] = RESET(0x2d0, BIT(17)),
> + [RST_BUS_I2C2] = RESET(0x2d0, BIT(18)),
> + [RST_BUS_UART0] = RESET(0x2d0, BIT(20)),
> + [RST_BUS_UART1] = RESET(0x2d0, BIT(21)),
> + [RST_BUS_UART2] = RESET(0x2d0, BIT(22)),
> +};
> +
> +static const struct ccu_desc f1c100s_ccu_desc = {
> + .gates = f1c100s_gates,
> + .resets = f1c100s_resets,
> +};
> +
> +static int f1c100s_clk_bind(struct udevice *dev)
> +{
> + return sunxi_reset_bind(dev, ARRAY_SIZE(f1c100s_resets));
> +}
> +
> +static const struct udevice_id f1c100s_clk_ids[] = {
> + { .compatible = "allwinner,suniv-f1c100s-ccu",
> + .data = (ulong)_ccu_desc },
> + { }
> +};
> +
> +U_BOOT_DRIVER(clk_suniv_f1c100s) = {
> + .name = "suniv_f1c100s_ccu",
> + .id = UCLASS_CLK,
> + .of_match = f1c100s_clk_ids,
> + .priv_auto = sizeof(struct ccu_priv),
> + .ops= _clk_ops,
> + .probe = sunxi_clk_probe,
> + .bind = f1c100s_clk_bind,
> +};
Re: [PATCH 2/2] mmc: sunxi: Remove unnecessary pinmux option dependency
On Sun, 10 Apr 2022 00:13:34 -0500 Samuel Holland wrote: > Now that the pinmux conflict is handled in the board code (by skipping > setup for the one conflicting MMC controller), the driver does not need > to be entirely disabled based on the UART pinmux. > > Signed-off-by: Samuel Holland Applied to sunxi/master. Thanks, Andre > --- > > drivers/mmc/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig > index f04cc44e19..5e2921ce41 100644 > --- a/drivers/mmc/Kconfig > +++ b/drivers/mmc/Kconfig > @@ -727,7 +727,7 @@ config ZYNQ_HISPD_BROKEN > > config MMC_SUNXI > bool "Allwinner sunxi SD/MMC Host Controller support" > - depends on ARCH_SUNXI && !UART0_PORT_F > + depends on ARCH_SUNXI > default y > help > This selects support for the SD/MMC Host Controller on
Re: [PATCH 5/7] sunxi: F1C100s: update DT files from Linux
On Tue, 3 May 2022 22:20:38 +0100
Andre Przywara wrote:
> The initial U-Boot F1C100s port was based on the mainline kernel DT
> files, which were quite basic and were missing the essential MMC and
> SPI peripherals. While we could work around this in the SPL by
> hardcoding the required information, this left U-Boot proper without SD
> card or SPI flash support, so actual loading would require FEL boot.
>
> Now the missing DT bits have been submitted and accepted in the kernel
> tree, so lets sync back those files into U-Boot to enable MMC and
> SPI, plus benefit from some fixes.
>
> This is a verbatim copy of the .dts and .dtsi file from
> linux-sunxi/dt-for-5.19[1], which have been part of linux-next for a
> while as well.
Applied to sunxi/master.
Thanks,
Andre
>
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git/log/?h=sunxi/dt-for-5.19
>
> Link:
> https://lore.kernel.org/linux-arm-kernel/20220317162349.739636-1-andre.przyw...@arm.com/
> Signed-off-by: Andre Przywara
> ---
> arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 31 ++
> arch/arm/dts/suniv-f1c100s.dtsi | 104 +--
> 2 files changed, 125 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
> b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
> index a1154e6c7cb..04e59b8381c 100644
> --- a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
> +++ b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
> @@ -11,12 +11,43 @@
> compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";
>
> aliases {
> + mmc0 =
> serial0 =
> + spi0 =
> };
>
> chosen {
> stdout-path = "serial0:115200n8";
> };
> +
> + reg_vcc3v3: vcc3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v3";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + };
> +};
> +
> + {
> + broken-cd;
> + bus-width = <4>;
> + disable-wp;
> + status = "okay";
> + vmmc-supply = <_vcc3v3>;
> +};
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pc_pins>;
> + status = "okay";
> +
> + flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "winbond,w25q128", "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <4000>;
> + };
> };
>
> {
> diff --git a/arch/arm/dts/suniv-f1c100s.dtsi b/arch/arm/dts/suniv-f1c100s.dtsi
> index 6100d3b75f6..0edc1724407 100644
> --- a/arch/arm/dts/suniv-f1c100s.dtsi
> +++ b/arch/arm/dts/suniv-f1c100s.dtsi
> @@ -4,6 +4,9 @@
> * Copyright 2018 Mesih Kilinc
> */
>
> +#include
> +#include
> +
> / {
> #address-cells = <1>;
> #size-cells = <1>;
> @@ -26,9 +29,13 @@
> };
>
> cpus {
> - cpu {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> compatible = "arm,arm926ej-s";
> device_type = "cpu";
> + reg = <0x0>;
> };
> };
>
> @@ -62,6 +69,70 @@
> };
> };
>
> + spi0: spi@1c05000 {
> + compatible = "allwinner,suniv-f1c100s-spi",
> + "allwinner,sun8i-h3-spi";
> + reg = <0x01c05000 0x1000>;
> + interrupts = <10>;
> + clocks = < CLK_BUS_SPI0>, < CLK_BUS_SPI0>;
> + clock-names = "ahb", "mod";
> + resets = < RST_BUS_SPI0>;
> + status = "disabled";
> + num-cs = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + spi1: spi@1c06000 {
> + compatible = "allwinner,suniv-f1c100s-spi",
> + "allwinner,sun8i-h3-spi";
> + reg = <0x01c06000 0x1000>;
> + interrupts = <11>;
> + clocks = < CLK_BUS_SPI1>, < CLK_BUS_SPI1>;
> + clock-names = "ahb", "mod";
> + resets = < RST_BUS_SPI1>;
> + status = "disabled";
> + num-cs = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc0: mmc@1c0f000 {
> + compatible = "allwinner,suniv-f1c100s-mmc",
> + "allwinner,sun7i-a20-mmc";
> + reg = <0x01c0f000 0x1000>;
> + clocks = < CLK_BUS_MMC0>,
> + < CLK_MMC0>,
> + < CLK_MMC0_OUTPUT>,
> + < CLK_MMC0_SAMPLE>;
> + clock-names =
Re: [PATCH 6/7] Revert "sunxi: f1c100s: Drop SYSRESET to enable reset functionality"
On Tue, 3 May 2022 22:20:39 +0100 Andre Przywara wrote: > The original Allwinner F1C100 .dtsi imported from the Linux kernel tree > used the wrong compatible string for the watchdog timer, so the Allwinner > DM reset driver was not working properly. We worked around this by > disabling the SYSRESET driver, so the hardcoded SPL reset driver took > over. > Now the issue was fixed in the DTs in mainline Linux, and we synced the > fixed .dtsi file into U-Boot, so drop the hack and use the normal U-Boot > proper reset infrastructure. > > This reverts commit cfcf1952c11e6ffcbbf88eb63c49edca2acf1d5e. > > Signed-off-by: Andre Przywara Applied to sunxi/master. Thanks, Andre > --- > configs/licheepi_nano_defconfig | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig > index 67b7b85c491..9fd1dcc9958 100644 > --- a/configs/licheepi_nano_defconfig > +++ b/configs/licheepi_nano_defconfig > @@ -10,4 +10,3 @@ CONFIG_DRAM_CLK=156 > CONFIG_DRAM_ZQ=0 > # CONFIG_VIDEO_SUNXI is not set > CONFIG_SPL_SPI_SUNXI=y > -# CONFIG_SYSRESET is not set
Re: [PATCH 1/2] sunxi: Remove obsolete Kconfig selections
On Mon, 9 May 2022 00:10:54 -0500 Samuel Holland wrote: > ARCH_SUNXI selects DM_SERIAL, so the condition can never be satisfied. > > Signed-off-by: Samuel Holland Applied to sunxi/master. Thanks! Andre > --- > > arch/arm/mach-sunxi/Kconfig | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig > index 1f43b25324..ee606c5bbc 100644 > --- a/arch/arm/mach-sunxi/Kconfig > +++ b/arch/arm/mach-sunxi/Kconfig > @@ -207,7 +207,6 @@ config MACH_SUN5I > select PHY_SUN4I_USB > select SUNXI_GEN_SUN4I > select SUPPORT_SPL > - imply CONS_INDEX_2 if !DM_SERIAL > imply SPL_SYS_I2C_LEGACY > imply SYS_I2C_LEGACY > > @@ -255,7 +254,6 @@ config MACH_SUN8I_A23 > select SUPPORT_SPL > select SYS_I2C_SUN8I_RSB > select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT > - imply CONS_INDEX_5 if !DM_SERIAL > > config MACH_SUN8I_A33 > bool "sun8i (Allwinner A33)" > @@ -270,7 +268,6 @@ config MACH_SUN8I_A33 > select SUPPORT_SPL > select SYS_I2C_SUN8I_RSB > select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT > - imply CONS_INDEX_5 if !DM_SERIAL > > config MACH_SUN8I_A83T > bool "sun8i (Allwinner A83T)"
Re: [PATCH 1/2] clk: sunxi: add PIO bus gate clocks
On Fri, 6 May 2022 01:33:00 +0100
Andre Przywara wrote:
> The introduction of the DM pinctrl driver made its probe function enable
> all clocks enumerated in the DT. This includes the "CLK_BUS_PIO" (and
> variations) gate clock, but also CLK_PLL_PERIPH0. So far we didn't
> describe those clocks in our clock driver.
> As we enable them already in the SPL, the devices happen to work, but
> the clock driver still complains about not finding those clocks:
> =
> sunxi_set_gate: (CLK#58) unhandled
> =
>
> Add the one-liners that are needed to announce the gate bit for those
> clocks, to silence that message on the console.
>
> Signed-off-by: Andre Przywara
Applied to sunxi/master.
Thanks,
Andre
> ---
> drivers/clk/sunxi/clk_a10.c | 2 ++
> drivers/clk/sunxi/clk_a10s.c | 2 ++
> drivers/clk/sunxi/clk_a23.c | 2 ++
> drivers/clk/sunxi/clk_a31.c | 2 ++
> drivers/clk/sunxi/clk_a64.c | 4
> drivers/clk/sunxi/clk_a80.c | 2 ++
> drivers/clk/sunxi/clk_a83t.c | 2 ++
> drivers/clk/sunxi/clk_h3.c | 4
> drivers/clk/sunxi/clk_h6.c | 2 ++
> drivers/clk/sunxi/clk_h616.c | 2 ++
> drivers/clk/sunxi/clk_r40.c | 2 ++
> drivers/clk/sunxi/clk_v3s.c | 2 ++
> 12 files changed, 28 insertions(+)
>
> diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
> index 90b929d3d32..db92848aafd 100644
> --- a/drivers/clk/sunxi/clk_a10.c
> +++ b/drivers/clk/sunxi/clk_a10.c
> @@ -31,6 +31,8 @@ static struct ccu_clk_gate a10_gates[] = {
>
> [CLK_AHB_GMAC] = GATE(0x064, BIT(17)),
>
> + [CLK_APB0_PIO] = GATE(0x068, BIT(5)),
> +
> [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
> [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
> [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
> index addf4f4d5cd..0c6564ef3b6 100644
> --- a/drivers/clk/sunxi/clk_a10s.c
> +++ b/drivers/clk/sunxi/clk_a10s.c
> @@ -25,6 +25,8 @@ static struct ccu_clk_gate a10s_gates[] = {
> [CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
> [CLK_AHB_SPI2] = GATE(0x060, BIT(22)),
>
> + [CLK_APB0_PIO] = GATE(0x068, BIT(5)),
> +
> [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
> [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
> [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
> index c45d2c35298..0280fb51e2d 100644
> --- a/drivers/clk/sunxi/clk_a23.c
> +++ b/drivers/clk/sunxi/clk_a23.c
> @@ -23,6 +23,8 @@ static struct ccu_clk_gate a23_gates[] = {
> [CLK_BUS_EHCI] = GATE(0x060, BIT(26)),
> [CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
>
> + [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
> +
> [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
> [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
> [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
> index 251fc3b705e..26d25f32408 100644
> --- a/drivers/clk/sunxi/clk_a31.c
> +++ b/drivers/clk/sunxi/clk_a31.c
> @@ -30,6 +30,8 @@ static struct ccu_clk_gate a31_gates[] = {
> [CLK_AHB1_OHCI1]= GATE(0x060, BIT(30)),
> [CLK_AHB1_OHCI2]= GATE(0x060, BIT(31)),
>
> + [CLK_APB1_PIO] = GATE(0x068, BIT(5)),
> +
> [CLK_APB2_I2C0] = GATE(0x06c, BIT(0)),
> [CLK_APB2_I2C1] = GATE(0x06c, BIT(1)),
> [CLK_APB2_I2C2] = GATE(0x06c, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
> index 1004a795033..cbb9168edb9 100644
> --- a/drivers/clk/sunxi/clk_a64.c
> +++ b/drivers/clk/sunxi/clk_a64.c
> @@ -14,6 +14,8 @@
> #include
>
> static const struct ccu_clk_gate a64_gates[] = {
> + [CLK_PLL_PERIPH0] = GATE(0x028, BIT(31)),
> +
> [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
> [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
> [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
> @@ -26,6 +28,8 @@ static const struct ccu_clk_gate a64_gates[] = {
> [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
> [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
>
> + [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
> +
> [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
> [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
> [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c
> index 8a0834d83a3..1ee1f99a8f4 100644
> --- a/drivers/clk/sunxi/clk_a80.c
> +++ b/drivers/clk/sunxi/clk_a80.c
> @@ -25,6 +25,8 @@ static const struct ccu_clk_gate a80_gates[] = {
> [CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
> [CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
>
> + [CLK_BUS_PIO] = GATE(0x590, BIT(5)),
> +
> [CLK_BUS_I2C0] = GATE(0x594, BIT(0)),
> [CLK_BUS_I2C1] = GATE(0x594, BIT(1)),
>
Re: [PATCH 2/2] serial: Remove obsolete CONS_INDEX_n Kconfig options
On Mon, 9 May 2022 00:10:55 -0500 Samuel Holland wrote: > These were only ever implied by sunxi platforms, and that usage has > been removed. Current practice is to specify CONFIG_CONS_INDEX in each > board's defconfig. > > Signed-off-by: Samuel Holland Applied to sunxi/master. Thanks! Andre > --- > > drivers/serial/Kconfig | 26 -- > 1 file changed, 26 deletions(-) > > diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig > index 1e595d0600..71a0591697 100644 > --- a/drivers/serial/Kconfig > +++ b/drivers/serial/Kconfig > @@ -74,36 +74,10 @@ config TPL_SERIAL_PRESENT > This option enables the full UART in TPL, so if is it disabled, > the full UART driver will be omitted, thus saving space. > > -# Logic to allow us to use the imply keyword to set what the default port > -# should be. The default is otherwise 1. > -config CONS_INDEX_0 > - bool > - > -config CONS_INDEX_2 > - bool > - > -config CONS_INDEX_3 > - bool > - > -config CONS_INDEX_4 > - bool > - > -config CONS_INDEX_5 > - bool > - > -config CONS_INDEX_6 > - bool > - > config CONS_INDEX > int "UART used for console" > depends on SPECIFY_CONSOLE_INDEX > range 0 6 > - default 0 if CONS_INDEX_0 > - default 2 if CONS_INDEX_2 > - default 3 if CONS_INDEX_3 > - default 4 if CONS_INDEX_4 > - default 5 if CONS_INDEX_5 > - default 6 if CONS_INDEX_6 > default 1 > help > Set this to match the UART number of the serial console.
Re: [PULL] u-boot-socfpga/master
On Mon, May 23, 2022 at 11:50:15PM +0200, Marek Vasut wrote: > The following changes since commit c0a1409d21e7b342566dccb9cc1d38209aabc5ff: > > configs: Resync with savedefconfig (2022-05-23 13:56:21 -0400) > > are available in the Git repository at: > > git://git.denx.de/u-boot-socfpga.git master > > for you to fetch changes up to 1b05136a6ca8387175ca7bf1aa66a9c40a153cc2: > > arm: socfpga: Add the terasic de10-standard board (2022-05-23 21:28:07 > +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: TPM tree pull request
On Tue, May 24, 2022 at 03:57:53PM +0300, Ilias Apalodimas wrote: > Please pull the latest TPM changes. Eddie added support for i2c devices. > You can find the CI for that tree at > https://source.denx.de/u-boot/custodians/u-boot-tpm/-/commits/tpm-24052022 > > The following changes since commit 6f00b97d7e5760d92566317dde6c4b9224790827: > > Merge https://source.denx.de/u-boot/custodians/u-boot-usb (2022-05-20 > 22:07:56 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-tpm/ tags/tpm-24052022 > > for you to fetch changes up to 9f971dac9369d0b27e8a3199bf03793d7185f56b: > > tpm: add support for TPMv2.x I2C chips (2022-05-23 16:33:58 +0300) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5] board: purism: add the Purism Librem5 phone
On 2022-05-24 08:10, Tom Rini wrote:
On Tue, May 24, 2022 at 07:15:01AM -0700, Angus Ainslie wrote:
Hi Stefano,
On 2022-05-23 02:36, Stefano Babic wrote:
> On 06.05.22 14:44, Angus Ainslie wrote:
> > Initial commit of Librem5 u-boot and SPL
> >
> > Signed-off-by: Angus Ainslie
> > Co-developed-by: Sebastian Krzyszkowiak
> >
> > Signed-off-by: Sebastian Krzyszkowiak
> > ---
>
> Hi Angus,
>
> with "configs: get rid of build warnings due to SPL_USB_DWC3_GENERIC"
> most issues are solved, but a TI board is still broken.
>
I'll resend the patch that includes a fix for the aarch64 board.
> A second issue is for the blob signed_dp_imx8m.bin, it should be done
> like for signed_hdmi.bin to avoid CI breakages.
>
> Here the result of pipeline:
>
> https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/437965
>
I see that the imx8mq_evk does not fail CI build but I'm not seeing
how the
missing signed_hdmi.bin file is handled. Any hints ?
You need to use binman to handle it, does
arch/arm/dts/imx8mq-u-boot.dtsi provide some clues?
Currently the librem5-r4-u-boot.dtsi ( text below ) includes
imx8mq-u-boot.dtsi and I tried deleting the signed-hdmi and including a
signed-dp in it's place. Now instead of an error about a missing
"signed_hdmi_imx8m.bin" I get an error about a missing
"signed_dp_imx8m.bin" so I know I'm having an effect but not enough of
one.
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#include "imx8mq-u-boot.dtsi"
_uart1 {
u-boot,dm-spl;
};
{ /* console */
u-boot,dm-spl;
};
{
/delete-node/ signed-hdmi;
signed-dp {
filename = "signed_dp_imx8m.bin";
signed-dp-imx8m {
filename = "signed_dp_imx8m.bin";
type = "blob-ext";
};
};
};
Re: [PATCH v5] board: purism: add the Purism Librem5 phone
On Tue, May 24, 2022 at 07:15:01AM -0700, Angus Ainslie wrote: > Hi Stefano, > > On 2022-05-23 02:36, Stefano Babic wrote: > > On 06.05.22 14:44, Angus Ainslie wrote: > > > Initial commit of Librem5 u-boot and SPL > > > > > > Signed-off-by: Angus Ainslie > > > Co-developed-by: Sebastian Krzyszkowiak > > > > > > Signed-off-by: Sebastian Krzyszkowiak > > > --- > > > > Hi Angus, > > > > with "configs: get rid of build warnings due to SPL_USB_DWC3_GENERIC" > > most issues are solved, but a TI board is still broken. > > > > I'll resend the patch that includes a fix for the aarch64 board. > > > A second issue is for the blob signed_dp_imx8m.bin, it should be done > > like for signed_hdmi.bin to avoid CI breakages. > > > > Here the result of pipeline: > > > > https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/437965 > > > > I see that the imx8mq_evk does not fail CI build but I'm not seeing how the > missing signed_hdmi.bin file is handled. Any hints ? You need to use binman to handle it, does arch/arm/dts/imx8mq-u-boot.dtsi provide some clues? -- Tom signature.asc Description: PGP signature
Re: [PATCH v5] board: purism: add the Purism Librem5 phone
Hi Stefano, On 2022-05-23 02:36, Stefano Babic wrote: On 06.05.22 14:44, Angus Ainslie wrote: Initial commit of Librem5 u-boot and SPL Signed-off-by: Angus Ainslie Co-developed-by: Sebastian Krzyszkowiak Signed-off-by: Sebastian Krzyszkowiak --- Hi Angus, with "configs: get rid of build warnings due to SPL_USB_DWC3_GENERIC" most issues are solved, but a TI board is still broken. I'll resend the patch that includes a fix for the aarch64 board. A second issue is for the blob signed_dp_imx8m.bin, it should be done like for signed_hdmi.bin to avoid CI breakages. Here the result of pipeline: https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/437965 I see that the imx8mq_evk does not fail CI build but I'm not seeing how the missing signed_hdmi.bin file is handled. Any hints ? Thanks Angus Best regards, Stefano
TPM tree pull request
Please pull the latest TPM changes. Eddie added support for i2c devices. You can find the CI for that tree at https://source.denx.de/u-boot/custodians/u-boot-tpm/-/commits/tpm-24052022 The following changes since commit 6f00b97d7e5760d92566317dde6c4b9224790827: Merge https://source.denx.de/u-boot/custodians/u-boot-usb (2022-05-20 22:07:56 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-tpm/ tags/tpm-24052022 for you to fetch changes up to 9f971dac9369d0b27e8a3199bf03793d7185f56b: tpm: add support for TPMv2.x I2C chips (2022-05-23 16:33:58 +0300) Add support for i2c devices Eddie James (2): tpm: core: Set timeouts before requesting locality tpm: add support for TPMv2.x I2C chips drivers/tpm/Kconfig | 9 +++ drivers/tpm/Makefile| 1 + drivers/tpm/tpm2_tis_core.c | 7 +- drivers/tpm/tpm2_tis_i2c.c | 171 4 files changed, 185 insertions(+), 3 deletions(-) create mode 100644 drivers/tpm/tpm2_tis_i2c.c
Re: [PATCH] phy: dp83867: add dp83867_{read,write}_mmd helpers
On Tue, May 24, 2022 at 01:31:41PM +0200, Rasmus Villemoes wrote:
> On 19/05/2022 16.38, Vladimir Oltean wrote:
> > Hi Rasmus,
> >
> > On Tue, May 17, 2022 at 04:27:06PM +0200, Rasmus Villemoes wrote:
> >> Since the phy_{read,write}_mmd functions are static inlines using
> >> other static inline functions, they cause code using them to explode.
> >>
> >> Defining local wrappers cuts the size of the generated code by 50%:
> >>
> >> $ size drivers/net/phy/dp83867.o.{before,after}
> >>textdata bss dec hex filename
> >>4873 112 049851379 drivers/net/phy/dp83867.o.before
> >>2413 112 02525 9dd drivers/net/phy/dp83867.o.after
> >>
> >> Of course, most of that improvement could also be had by making the
> >> phy_*_mmd functions out-of-line, and they probably should be, but this
>
> >> still has the advantage of avoiding passing the DP83867_DEVADDR
> >> argument at all call sites, which allows lines to be unwrapped (and
> >> probably also gives a little .text reduction by itself).
> >>
> >> Signed-off-by: Rasmus Villemoes
> >> ---
> >
> > Have you considered making phy_read_mmd() and phy_write_mmd() non-inline?
> > There are few users, but it looks like they would all benefit from this.
>
> Yes, I wrote precisely that in the commit message. But the problem with
> that is finding some TU to put them in which is guaranteed to be built
> and included by all current users. This localized change gives just
> about the same benefit in .text, plus the line unwrapping. And nothing
> prevents somebody later from figuring out a proper place to put
> out-of-line versions of these phy_*_mmd functions.
I don't see why the translation unit you mention cannot be
drivers/net/phy/phy.c.
For phy_read_mmd() and phy_write_mmd() this is even pretty easy to see,
as all the callers are either PHY drivers or cmd/mdio.c which itself
depends on CONFIG_PHYLIB.
The phy_read() and phy_write() calls themselves can also be probably be
uninlined as a further exercise, but I didn't request that.
But yeah, ok, whatever.
[PATCH] test: fix parsing the mksquashfs version number
Testing with mksquasshfs 4.5.1 results in an error
ValueError: could not convert string to float: '4.5.1'
Version 4.10 would be considered to be lower than 4.4.
Fixes: 04c9813e951f ("test/py: rewrite common tools for SquashFS tests")
Signed-off-by: Heinrich Schuchardt
---
test/py/tests/test_fs/test_squashfs/sqfs_common.py | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/test/py/tests/test_fs/test_squashfs/sqfs_common.py
b/test/py/tests/test_fs/test_squashfs/sqfs_common.py
index 8b84c2cdca..d1621dcce3 100644
--- a/test/py/tests/test_fs/test_squashfs/sqfs_common.py
+++ b/test/py/tests/test_fs/test_squashfs/sqfs_common.py
@@ -146,15 +146,14 @@ def get_mksquashfs_version():
out = subprocess.run(['mksquashfs -version'], shell=True, check=True,
capture_output=True, text=True)
# 'out' is: mksquashfs version X (/mm/dd) ...
-return float(out.stdout.split()[2].split('-')[0])
+return out.stdout.split()[2].split('.')[0:2]
def check_mksquashfs_version():
""" Checks if mksquashfs meets the required version. """
-required_version = 4.4
-if get_mksquashfs_version() < required_version:
-print('Error: mksquashfs is too old.')
-print('Required version: {}'.format(required_version))
+version = get_mksquashfs_version();
+if int(version[0]) < 4 or int(version[0]) == 4 and int(version[1]) < 4 :
+print('Error: mksquashfs is too old, required version: 4.4')
raise AssertionError
def make_all_images(build_dir):
--
2.36.1
Re: [PATCH] phy: dp83867: add dp83867_{read,write}_mmd helpers
On 19/05/2022 16.38, Vladimir Oltean wrote:
> Hi Rasmus,
>
> On Tue, May 17, 2022 at 04:27:06PM +0200, Rasmus Villemoes wrote:
>> Since the phy_{read,write}_mmd functions are static inlines using
>> other static inline functions, they cause code using them to explode.
>>
>> Defining local wrappers cuts the size of the generated code by 50%:
>>
>> $ size drivers/net/phy/dp83867.o.{before,after}
>>textdata bss dec hex filename
>>4873 112 049851379 drivers/net/phy/dp83867.o.before
>>2413 112 02525 9dd drivers/net/phy/dp83867.o.after
>>
>> Of course, most of that improvement could also be had by making the
>> phy_*_mmd functions out-of-line, and they probably should be, but this
>> still has the advantage of avoiding passing the DP83867_DEVADDR
>> argument at all call sites, which allows lines to be unwrapped (and
>> probably also gives a little .text reduction by itself).
>>
>> Signed-off-by: Rasmus Villemoes
>> ---
>
> Have you considered making phy_read_mmd() and phy_write_mmd() non-inline?
> There are few users, but it looks like they would all benefit from this.
Yes, I wrote precisely that in the commit message. But the problem with
that is finding some TU to put them in which is guaranteed to be built
and included by all current users. This localized change gives just
about the same benefit in .text, plus the line unwrapping. And nothing
prevents somebody later from figuring out a proper place to put
out-of-line versions of these phy_*_mmd functions.
Rasmus
[PATCH] powerpc: dts: p2020: Define PMC node
Copy definition of PMC node from upstream Linux kernel P2020 dts files.
Signed-off-by: Pali Rohár
---
arch/powerpc/dts/p2020-post.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index d281bed5afd5..0d0cd2273cd4 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -104,6 +104,11 @@
reg = <0xe 0x1000>;
fsl,has-rstcr;
};
+
+ pmc: power@e0070 {
+ compatible = "fsl,mpc8548-pmc";
+ reg = <0xe0070 0x20>;
+ };
};
/* PCIe controller base address 0x8000 */
--
2.20.1
Re: [PATCH v6 3/6] efi_loader: menu-driven update of UEFI bootorder variable
On 5/16/22 13:00, Masahisa Kojima wrote:
This commit adds the menu-driven update of UEFI bootorder
variable.
Signed-off-by: Masahisa Kojima
---
(no update since v5)
Changes in v5:
- split into the separate patch
lib/efi_loader/efi_bootmenu_maintenance.c | 102 ++
1 file changed, 102 insertions(+)
diff --git a/lib/efi_loader/efi_bootmenu_maintenance.c
b/lib/efi_loader/efi_bootmenu_maintenance.c
index 96306cd2cc..be67fca95f 100644
--- a/lib/efi_loader/efi_bootmenu_maintenance.c
+++ b/lib/efi_loader/efi_bootmenu_maintenance.c
@@ -746,6 +746,56 @@ static efi_status_t
efi_bootmenu_boot_add_enter_name(struct efi_bootmenu_boot_op
return ret;
}
+static efi_status_t allow_decimal(struct efi_input_key *key)
+{
+ if (u'0' <= key->unicode_char && key->unicode_char <= u'9')
+ return EFI_SUCCESS;
+
+ return EFI_INVALID_PARAMETER;
+}
+
+static efi_status_t efi_bootmenu_change_boot_order(int selected, int max, int
*new)
+{
+ efi_status_t ret;
+ u16 new_order[EFI_BOOT_ORDER_MAX_SIZE_IN_DECIMAL] = {0};
After selecting an item why can we simply use the up and down key to
move the selected item?
+
+ printf(ANSI_CURSOR_POSITION, 2, 1);
+ puts(" *** U-Boot EFI Boot Manager Menu ***");
+ printf(ANSI_CURSOR_POSITION, 4, 1);
+ printf(" current boot order : %d", selected);
+
+ printf(ANSI_CURSOR_POSITION, 6, 1);
+ printf(" new boot order(0 - %4d): ", max);
+
+ printf(ANSI_CURSOR_POSITION, 8, 1);
+ puts(" ENTER to complete, ESC/CTRL+C to quit");
+
+ printf(ANSI_CURSOR_POSITION, 6, 29);
+ puts(ANSI_CURSOR_SHOW);
+
+ for (;;) {
+ memset(new_order, 0, sizeof(new_order));
+ ret = efi_console_get_u16_string(cin, cout, new_order, 6,
allow_decimal, 6, 29);
+ if (ret == EFI_SUCCESS) {
+ int i;
+ int val = 0;
+
+ for (i = 0;
+i < u16_strnlen(new_order,
EFI_BOOT_ORDER_MAX_SIZE_IN_DECIMAL - 1);
+i++)
+ val = (val * 10) + (new_order[i] - u'0');
+
+ if (val > max)
+ continue;
+
+ *new = val;
+ return EFI_SUCCESS;
+ } else {
+ return ret;
+ }
+ }
+}
+
static efi_status_t efi_bootmenu_select_file_handler(struct
efi_bootmenu_boot_option *bo)
{
efi_status_t ret;
@@ -996,6 +1046,57 @@ static efi_status_t
efi_bootmenu_process_delete_boot_option(void *data, bool *ex
return ret;
}
+static efi_status_t efi_bootmenu_process_change_boot_order(void *data, bool
*exit)
+{
+ int selected;
+ int new_order;
+ efi_status_t ret;
+ efi_uintn_t num, size;
+ u16 *bootorder = NULL;
+ u16 *new_bootorder = NULL;
+
+ bootorder = efi_get_var(u"BootOrder", _global_variable_guid, );
+ if (!bootorder)
+ return EFI_NOT_FOUND;
+
+ num = size / sizeof(u16);
+ ret = efi_bootmenu_show_boot_selection(bootorder, num, );
+ if (ret != EFI_SUCCESS)
+ goto out;
+
+ ret = efi_bootmenu_change_boot_order(selected, num - 1, _order);
+ if (ret != EFI_SUCCESS)
+ goto out;
+
+ new_bootorder = calloc(1, size);
+ if (!new_bootorder)
+ goto out;
+
+ memcpy(new_bootorder, bootorder, size);
+ if (selected > new_order) {
+ new_bootorder[new_order] = bootorder[selected];
+ memcpy(_bootorder[new_order + 1], [new_order],
+ (selected - new_order) * sizeof(u16));
+ } else if (selected < new_order) {
+ new_bootorder[new_order] = bootorder[selected];
+ memcpy(_bootorder[selected], [selected + 1],
+ (new_order - selected) * sizeof(u16));
After updating an item we should be in the
efi_bootmenu_show_boot_selection() screen again.
Best regards
Heinrich
+ } else {
+ /* nothing to change */
+ goto out;
+ }
+ ret = efi_set_variable_int(u"BootOrder", _global_variable_guid,
+ EFI_VARIABLE_NON_VOLATILE |
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS,
+ size, new_bootorder, false);
+out:
+ free(new_bootorder);
+ free(bootorder);
+
+ return ret;
+}
+
static efi_status_t efi_bootmenu_init(void)
{
efi_status_t ret;
@@ -1025,6 +1126,7 @@ static efi_status_t efi_bootmenu_init(void)
static const struct efi_bootmenu_item maintenance_menu_items[] = {
{u"Add Boot Option", efi_bootmenu_process_add_boot_option},
{u"Delete Boot Option", efi_bootmenu_process_delete_boot_option},
+ {u"Change
RE: [PATCH] fpga: intel_sdm_mb: Add checking for INTEL_SIP_SMC_STATUS_BUSY (1)
> -Original Message-
> From: Maniyam, Dinesh
> Sent: Monday, 9 May, 2022 3:43 PM
> To: u-boot@lists.denx.de
> Cc: Michal Simek ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Gan, Yau Wai ; Kho, Sin Hui
> ; Lokanathan, Raaj ;
> Maniyam, Dinesh ; Ley Foon Tan
>
> Subject: [PATCH] fpga: intel_sdm_mb: Add checking for
> INTEL_SIP_SMC_STATUS_BUSY (1)
>
> From: Dinesh Maniyam
>
> Status busy means transfer is accepted but SDM does not have more freed
> buffer. It is not an error. Continue process the data if receive OK and BUSY
> status.
Can you help to improve the commit message? That is not possible wr_ret would
return with two results(OK and BUSY) in status at the same time. Please change
to "OK or Busy status".
Please extend the years of copyright to "2018-2022"
>
> Signed-off-by: Ley Foon Tan
> Signed-off-by: Dinesh Maniyam
> ---
> drivers/fpga/intel_sdm_mb.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c
> index f5fd9a14c2..5e0b2777e0 100644
> --- a/drivers/fpga/intel_sdm_mb.c
> +++ b/drivers/fpga/intel_sdm_mb.c
> @@ -70,7 +70,8 @@ static int send_bitstream(const void *rbf_data, size_t
> rbf_size)
> debug("wr_ret = %d, rbf_data = %p, buf_size
> = %08lx\n",
> wr_ret, rbf_data, buf_size);
>
> - if (wr_ret)
> + if (wr_ret != INTEL_SIP_SMC_STATUS_OK &&
> + wr_ret != INTEL_SIP_SMC_STATUS_BUSY)
Alignment issue after "(" above, please run the checkpatch.pl
> continue;
>
> rbf_size -= buf_size;
> --
> 2.26.2
Re: [PATCH] net: Add missing PCI dependency for CONFIG_E1000
On Mon, May 23, 2022 at 11:42 AM Pali Rohár wrote: > > Signed-off-by: Pali Rohár > --- > drivers/net/Kconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig > index 7fe0e00649cf..84d859c21eb8 100644 > --- a/drivers/net/Kconfig > +++ b/drivers/net/Kconfig > @@ -231,6 +231,7 @@ config DWC_ETH_QOS_TEGRA186 > > config E1000 > bool "Intel PRO/1000 Gigabit Ethernet support" > + depends on PCI > help > This driver supports Intel(R) PRO/1000 gigabit ethernet family of > adapters. For more information on how to identify your adapter, go > -- > 2.20.1 > Reviewed-by: Ramon Fried
RE: [PATCH] arm: dts: socfpga: stratix10: Update MMC smplsel value
> -Original Message-
> From: Gan, Yau Wai
> Sent: Tuesday, 24 May, 2022 3:02 PM
> To: u-boot@lists.denx.de
> Cc: Gan, Yau Wai ; Chee, Tien Fong
>
> Subject: [PATCH] arm: dts: socfpga: stratix10: Update MMC smplsel value
>
> From: Yau Wai Gan
>
> This new MMC sample select value is obtained from running tests on
> multiple Stratix 10 boards and proven working.
>
> Signed-off-by: Yau Wai Gan
> ---
> arch/arm/dts/socfpga_stratix10_socdk.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts
> b/arch/arm/dts/socfpga_stratix10_socdk.dts
> index 6622720f77..8e6a405917 100755
> --- a/arch/arm/dts/socfpga_stratix10_socdk.dts
> +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
> @@ -93,7 +93,7 @@
> broken-cd;
> bus-width = <4>;
> drvsel = <3>;
> - smplsel = <0>;
> + smplsel = <2>;
> };
>
> {
> --
> 2.13.0
Reviewed-by: Tien Fong Chee
Regards
Tien Fong
[PATCH v2] SPL: Do not allow enabling SPL symbols for non-SPL builds
It does not make sense to enable SPL options when not building SPL binary. So disallow selecting SPL options for non-SPL builds. Signed-off-by: Pali Rohár --- Changes in v2: * Move SPL compression options under one big if SPL ... endif --- arch/arm/Kconfig| 6 +- arch/arm/cpu/armv8/Kconfig | 2 ++ common/Kconfig | 5 + common/spl/Kconfig | 4 ++-- drivers/firmware/Kconfig| 1 + drivers/gpio/Kconfig| 1 + drivers/misc/Kconfig| 1 + drivers/mmc/Kconfig | 5 + drivers/mtd/spi/Kconfig | 1 + drivers/power/Kconfig | 1 + drivers/power/acpi_pmc/Kconfig | 1 + drivers/power/regulator/Kconfig | 1 + fs/cbfs/Kconfig | 1 + lib/Kconfig | 20 +--- 14 files changed, 40 insertions(+), 10 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9898c7d68e1b..0492cc53678e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -991,7 +991,7 @@ config ARCH_MX6 imply SYS_THUMB_BUILD imply SPL_SEPARATE_BSS -if ARCH_MX6 +if ARCH_MX6 && SPL config SPL_LDSCRIPT default "arch/arm/mach-omap2/u-boot-spl.lds" endif @@ -2349,7 +2349,11 @@ source "arch/arm/Kconfig.debug" endmenu +if SPL + config SPL_LDSCRIPT default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64 + +endif diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 09f3f50fa22f..0476446bc5ba 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -76,6 +76,7 @@ config ARMV8_SEC_FIRMWARE_SUPPORT config SPL_ARMV8_SEC_FIRMWARE_SUPPORT bool "Enable ARMv8 secure monitor firmware framework support for SPL" + depends on SPL select SPL_FIT select SPL_OF_LIBFDT help @@ -83,6 +84,7 @@ config SPL_ARMV8_SEC_FIRMWARE_SUPPORT config SPL_RECOVER_DATA_SECTION bool "save/restore SPL data section" + depends on SPL help Say Y here to save SPL data section for cold boot, and restore at warm boot in SPL phase. diff --git a/common/Kconfig b/common/Kconfig index a96842a5c11d..8e59dcef4b8b 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -81,10 +81,14 @@ config LOGLEVEL 8 - debug content 9 - debug hardware I/O +if SPL + config SPL_LOGLEVEL int default LOGLEVEL +endif + config TPL_LOGLEVEL int default LOGLEVEL @@ -241,6 +245,7 @@ config SYS_STDIO_DEREGISTER config SPL_SYS_STDIO_DEREGISTER bool "Allow deregistering stdio devices in SPL" + depends on SPL help Generally there is no need to deregister stdio devices since they are never deactivated. But if a stdio device is used which can be diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 50ff113cab21..6f40e11c8f3b 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -19,6 +19,8 @@ config SPL help If you want to build SPL as well as the normal image, say Y. +if SPL + config SPL_FRAMEWORK bool "Support SPL based upon the common SPL framework" depends on SPL @@ -150,8 +152,6 @@ config HANDOFF in boot. It is available in gd->handoff. The state state is set up in SPL (or TPL if that is being used). -if SPL - config SPL_HANDOFF bool "Pass hand-off information from SPL to U-Boot proper" depends on HANDOFF && SPL_BLOBLIST diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index ef958b3a7a4e..55069e395ff2 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -3,6 +3,7 @@ config FIRMWARE config SPL_FIRMWARE bool "Enable Firmware driver support in SPL" + depends on SPL depends on FIRMWARE config SPL_ARM_PSCI_FW diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 149a62ffe611..3ba97515b718 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -490,6 +490,7 @@ config DM_PCA953X config SPL_DM_PCA953X bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports in SPL" + depends on SPL depends on DM_GPIO help Say yes here to provide access to several register-oriented diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 85ae7f62e911..209cd4272ac0 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -504,6 +504,7 @@ config FS_LOADER config SPL_FS_LOADER bool "Enable loader driver for file system" + depends on SPL help This is file system generic loader which can be used to load the file image from the storage into target such as memory. diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index f04cc44e1973..a3f0cd00ed74 100644 ---
[PATCH] TPL: Do not allow enabling TPL symbols for non-TPL builds
It does not make sense to enable TPL options when not building TPL binary. So disallow selecting TPL options for non-TPL builds. Signed-off-by: Pali Rohár --- common/Kconfig | 4 drivers/power/acpi_pmc/Kconfig | 1 + lib/Kconfig| 3 ++- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/common/Kconfig b/common/Kconfig index 8e59dcef4b8b..ba59edd14673 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -89,10 +89,14 @@ config SPL_LOGLEVEL endif +if TPL + config TPL_LOGLEVEL int default LOGLEVEL +endif + config VPL_LOGLEVEL int "loglevel for VPL" default LOGLEVEL diff --git a/drivers/power/acpi_pmc/Kconfig b/drivers/power/acpi_pmc/Kconfig index 8b712abc41e9..629acb071427 100644 --- a/drivers/power/acpi_pmc/Kconfig +++ b/drivers/power/acpi_pmc/Kconfig @@ -18,6 +18,7 @@ config SPL_ACPI_PMC config TPL_ACPI_PMC bool "Power Manager (x86 PMC) support in TPL" + depends on TPL default y if ACPI_PMC help Enable support for an x86-style power-management controller which diff --git a/lib/Kconfig b/lib/Kconfig index 299381ac80d5..ef1c57a075f6 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -249,6 +249,7 @@ config SPL_TINY_MEMSET config TPL_TINY_MEMSET bool "Use a very small memset() in TPL" + depends on TPL help The faster memset() is the arch-specific one (if available) enabled by CONFIG_USE_ARCH_MEMSET. If that is not enabled, we can still get @@ -779,7 +780,7 @@ config TPL_OF_LIBFDT config TPL_OF_LIBFDT_ASSUME_MASK hex "Mask of conditions to assume for libfdt" - depends on TPL_OF_LIBFDT || FIT + depends on TPL_OF_LIBFDT || (TPL && FIT) default 0xff help Use this to change the assumptions made by libfdt in TPL about the -- 2.20.1
[PATCH] arch: mvebu: Disable by default unused peripherals in SPL
SPL on mvebu loads proper U-Boot from custom Marvell kwbimage format and therefore support for other binary formats is not required to be present in SPL. Boot source of proper U-Boot is defined by compile time options and therefore it is not required to enable all possible and unused peripherals in SPL by default. This change decrease size of SPL binaries. Signed-off-by: Pali Rohár --- common/spl/Kconfig | 2 ++ disk/Kconfig| 2 ++ drivers/mmc/Kconfig | 1 + drivers/usb/Kconfig | 1 + 4 files changed, 6 insertions(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 50ff113cab21..0c8df271aa59 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -218,6 +218,7 @@ config SPL_BOOTCOUNT_LIMIT config SPL_RAW_IMAGE_SUPPORT bool "Support SPL loading and booting of RAW images" + default n if ARCH_MVEBU default n if (ARCH_MX6 && (SPL_MMC || SPL_SATA)) default y depends on !TI_SECURE_DEVICE @@ -228,6 +229,7 @@ config SPL_RAW_IMAGE_SUPPORT config SPL_LEGACY_IMAGE_FORMAT bool "Support SPL loading and booting of Legacy images" + default n if ARCH_MVEBU default y if !SPL_LOAD_FIT depends on !TI_SECURE_DEVICE help diff --git a/disk/Kconfig b/disk/Kconfig index 359af3b27e6d..81d8867ed7fc 100644 --- a/disk/Kconfig +++ b/disk/Kconfig @@ -60,6 +60,7 @@ config DOS_PARTITION config SPL_DOS_PARTITION bool "Enable MS Dos partition table for SPL" depends on SPL + default n if ARCH_MVEBU default n if ARCH_SUNXI default y if DOS_PARTITION select SPL_PARTITIONS @@ -130,6 +131,7 @@ config EFI_PARTITION_ENTRIES_OFF config SPL_EFI_PARTITION bool "Enable EFI GPT partition table for SPL" depends on SPL + default n if ARCH_MVEBU default n if ARCH_SUNXI default y if EFI_PARTITION select SPL_PARTITIONS diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index f04cc44e1973..847c0ef0acc7 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -45,6 +45,7 @@ config DM_MMC config SPL_DM_MMC bool "Enable MMC controllers using Driver Model in SPL" depends on SPL_DM && DM_MMC + default n if ARCH_MVEBU && !MVEBU_SPL_BOOT_DEVICE_MMC default y help This enables the MultiMediaCard (MMC) uclass which supports MMC and diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index ab1d061bd0d5..075e9682c435 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -50,6 +50,7 @@ config DM_USB config SPL_DM_USB bool "Enable driver model for USB host most in SPL" depends on SPL_DM && DM_USB + default n if ARCH_MVEBU default y config DM_USB_GADGET -- 2.20.1
[PATCH v1] rng: nuvoton: Add NPCM7xx rng driver
Add Nuvoton BMC NPCM750 rng driver.
Signed-off-by: Jim Liu
---
drivers/rng/Kconfig| 7 ++
drivers/rng/Makefile | 1 +
drivers/rng/npcm_rng.c | 156 +
3 files changed, 164 insertions(+)
create mode 100644 drivers/rng/npcm_rng.c
diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index c10f7d345b..c0c49c3484 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -31,6 +31,13 @@ config RNG_MSM
This driver provides support for the Random Number
Generator hardware found on Qualcomm SoCs.
+config RNG_NPCM
+ bool "Nuvoton NPCM SoCs Random Number Generator support"
+ depends on DM_RNG
+ help
+ Enable random number generator on NPCM SoCs.
+ This unit can provide 750 to 1000 random bits per second
+
config RNG_OPTEE
bool "OP-TEE based Random Number Generator support"
depends on DM_RNG && OPTEE
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 435b3b965a..0ae0ed4171 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_DM_RNG) += rng-uclass.o
obj-$(CONFIG_RNG_MESON) += meson-rng.o
obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o
obj-$(CONFIG_RNG_MSM) += msm_rng.o
+obj-$(CONFIG_RNG_NPCM) += npcm_rng.o
obj-$(CONFIG_RNG_OPTEE) += optee_rng.o
obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o
diff --git a/drivers/rng/npcm_rng.c b/drivers/rng/npcm_rng.c
new file mode 100644
index 00..70c1c032b6
--- /dev/null
+++ b/drivers/rng/npcm_rng.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define RNGCS_RNGE BIT(0)
+#define RNGCS_DVALIDBIT(1)
+#define RNGCS_CLKP(range) ((0x0f & (range)) << 2)
+#define RNGMODE_M1ROSEL_VAL (0x02) /* Ring Oscillator Select for Method I
*/
+
+enum {
+ RNG_CLKP_80_100_MHZ = 0x00, /*default */
+ RNG_CLKP_60_80_MHZ = 0x01,
+ RNG_CLKP_50_60_MHZ = 0x02,
+ RNG_CLKP_40_50_MHZ = 0x03,
+ RNG_CLKP_30_40_MHZ = 0x04,
+ RNG_CLKP_25_30_MHZ = 0x05,
+ RNG_CLKP_20_25_MHZ = 0x06,
+ RNG_CLKP_5_20_MHZ = 0x07,
+ RNG_CLKP_2_15_MHZ = 0x08,
+ RNG_CLKP_9_12_MHZ = 0x09,
+ RNG_CLKP_7_9_MHZ= 0x0A,
+ RNG_CLKP_6_7_MHZ= 0x0B,
+ RNG_CLKP_5_6_MHZ= 0x0C,
+ RNG_CLKP_4_5_MHZ= 0x0D,
+ RNG_CLKP_3_4_MHZ= 0x0E,
+ RNG_NUM_OF_CLKP
+};
+
+struct npcm_rng_regs {
+ unsigned int rngcs;
+ unsigned int rngd;
+ unsigned int rngmode;
+};
+
+struct npcm_rng_priv {
+ struct npcm_rng_regs *regs;
+};
+
+static struct npcm_rng_priv *rng_priv;
+
+void npcm_rng_init(void)
+{
+ struct npcm_rng_regs *regs = rng_priv->regs;
+ int init;
+
+ /* check if rng enabled */
+ init = readb(>rngcs);
+ if ((init & RNGCS_RNGE) == 0) {
+ /* init rng */
+ writeb(RNGCS_CLKP(RNG_CLKP_20_25_MHZ) | RNGCS_RNGE,
>rngcs);
+ writeb(RNGMODE_M1ROSEL_VAL, >rngmode);
+ }
+}
+
+void npcm_rng_disable(void)
+{
+ struct npcm_rng_regs *regs = rng_priv->regs;
+
+ /* disable rng */
+ writeb(0, >rngcs);
+ writeb(0, >rngmode);
+}
+
+void srand(unsigned int seed)
+{
+ /* no need to seed for now */
+}
+
+int npcm_rng_read(struct udevice *dev, void *data, size_t max)
+{
+ struct npcm_rng_regs *regs = rng_priv->regs;
+ int i;
+ int ret_val = 0;
+ char *buf = data;
+
+ npcm_rng_init();
+
+ printf("NPCM HW RNG\n");
+ /* Wait for RNG done (max bytes) */
+ for (i = 0; i < max; i++) {
+/* wait until DVALID is set */
+ while ((readb(>rngcs) & RNGCS_DVALID) == 0)
+ ;
+ buf[i] = ((unsigned int)readb(>rngd) & 0x00FF);
+ }
+
+ return ret_val;
+}
+
+unsigned int rand_r(unsigned int *seedp)
+{
+ struct npcm_rng_regs *regs = rng_priv->regs;
+ int i;
+ unsigned int ret_val = 0;
+
+ npcm_rng_init();
+
+ /* Wait for RNG done (4 bytes) */
+ for (i = 0; i < 4 ; i++) {
+ /* wait until DVALID is set */
+ while ((readb(>rngcs) & RNGCS_DVALID) == 0)
+ ;
+ ret_val |= (((unsigned int)readb(>rngd) & 0x00FF) <<
(i * 8));
+ }
+
+ return ret_val;
+}
+
+unsigned int rand(void)
+{
+ return rand_r(NULL);
+}
+
+static int npcm_rng_bind(struct udevice *dev)
+{
+ rng_priv = calloc(1, sizeof(struct npcm_rng_priv));
+ if (!rng_priv)
+ return -ENOMEM;
+
+ rng_priv->regs = dev_remap_addr_index(dev, 0);
+ if (!rng_priv->regs) {
+ printf("Cannot find rng reg address, binding failed\n");
+ return -EINVAL;
+ }
+
+ printf("RNG: NPCM RNG module bind OK\n");
[PATCH v2] mmc: nuvoton: Add NPCM7xx mmc driver
Add Nuvoton BMC NPCM750 mmc control driver.
Signed-off-by: Jim Liu
---
Changes for v2:
- modify kconfig description
- use mmc_of_parse
- modify U_BOOT_DRIVER and Copyright time
---
drivers/mmc/Kconfig | 12 ++
drivers/mmc/Makefile | 1 +
drivers/mmc/npcm_sdhci.c | 86
3 files changed, 99 insertions(+)
create mode 100644 drivers/mmc/npcm_sdhci.c
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index f04cc44e19..f6a1eb2ac5 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -607,6 +607,18 @@ config MMC_SDHCI_MV
If unsure, say N.
+config MMC_SDHCI_NPCM
+ bool "SDHCI support on Nuvoton NPCM device"
+ depends on MMC_SDHCI
+ depends on DM_MMC
+ help
+ This selects the Secure Digital Host Controller Interface (SDHCI)
+ on Nuvoton NPCM device.
+
+ If you have a controller with this interface, say Y here.
+
+ If unsure, say N.
+
config MMC_SDHCI_PIC32
bool "Microchip PIC32 on-chip SDHCI support"
depends on DM_MMC && MACH_PIC32
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 9627509302..280da24567 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -67,6 +67,7 @@ obj-$(CONFIG_MMC_SDHCI_IPROC) += iproc_sdhci.o
obj-$(CONFIG_MMC_SDHCI_KONA) += kona_sdhci.o
obj-$(CONFIG_MMC_SDHCI_MSM)+= msm_sdhci.o
obj-$(CONFIG_MMC_SDHCI_MV) += mv_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_NPCM)+= npcm_sdhci.o
obj-$(CONFIG_MMC_SDHCI_PIC32) += pic32_sdhci.o
obj-$(CONFIG_MMC_SDHCI_ROCKCHIP) += rockchip_sdhci.o
obj-$(CONFIG_MMC_SDHCI_S5P)+= s5p_sdhci.o
diff --git a/drivers/mmc/npcm_sdhci.c b/drivers/mmc/npcm_sdhci.c
new file mode 100644
index 00..7eb17cce0b
--- /dev/null
+++ b/drivers/mmc/npcm_sdhci.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define NPCM_SDHC_MIN_FREQ 40
+
+struct npcm_sdhci_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+static int npcm_sdhci_probe(struct udevice *dev)
+{
+ struct npcm_sdhci_plat *plat = dev_get_plat(dev);
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ struct udevice *vqmmc_supply;
+ int vqmmc_uv, ret;
+ struct clk clk;
+
+ host->name = dev->name;
+ host->ioaddr = dev_read_addr_ptr(dev);
+ host->max_clk = dev_read_u32_default(dev, "clock-frequency", 0);
+
+ ret = clk_get_by_index(dev, 0, );
+ if (!ret && host->max_clk) {
+ ret = clk_set_rate(, host->max_clk);
+ if (ret < 0)
+ return ret;
+ }
+
+ if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
+ device_get_supply_regulator(dev, "vqmmc-supply", _supply);
+ vqmmc_uv = dev_read_u32_default(dev, "vqmmc-microvolt", 0);
+ /* Set IO voltage */
+ if (vqmmc_supply && vqmmc_uv)
+ regulator_set_value(vqmmc_supply, vqmmc_uv);
+ }
+
+ host->index = dev_read_u32_default(dev, "index", 0);
+ ret = mmc_of_parse(dev, >cfg);
+ if (ret)
+ return ret;
+
+ host->mmc = >mmc;
+ host->mmc->priv = host;
+ host->mmc->dev = dev;
+ upriv->mmc = host->mmc;
+
+ ret = sdhci_setup_cfg(>cfg, host, 0, NPCM_SDHC_MIN_FREQ);
+ if (ret)
+ return ret;
+
+ return sdhci_probe(dev);
+}
+
+static int npcm_sdhci_bind(struct udevice *dev)
+{
+ struct npcm_sdhci_plat *plat = dev_get_plat(dev);
+
+ return sdhci_bind(dev, >mmc, >cfg);
+}
+
+static const struct udevice_id npcm_mmc_ids[] = {
+ { .compatible = "nuvoton,npcm750-sdhci" },
+ { .compatible = "nuvoton,npcm845-sdhci" },
+ { }
+};
+
+U_BOOT_DRIVER(npcm_sdhci_drv) = {
+ .name = "npcm_sdhci",
+ .id = UCLASS_MMC,
+ .of_match = npcm_mmc_ids,
+ .ops= _ops,
+ .bind = npcm_sdhci_bind,
+ .probe = npcm_sdhci_probe,
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct npcm_sdhci_plat),
+};
--
2.17.1
Re: [PATCH] bootmenu: fix bootmenu title handling
On Tuesday 24 May 2022 12:45:30 Masahisa Kojima wrote:
> The commit a3d0aa87acbe ("bootmenu: update bootmenu_entry structure")
> changes the bootmenu title type from char to u16(UTF16 string)
> to support EFI based system. If EFI_LOADER is not enabled,
> printf("%ls") is not supported, so bootmenu does not appear
> correctly.
>
> This commit switches the menu title type from "char" to "u16"
> only when the EFI_LOADER is enabled.
>
> Fixes: a3d0aa87acbe ("bootmenu: update bootmenu_entry structure")
> Signed-off-by: Masahisa Kojima
> ---
> cmd/bootmenu.c | 48
> 1 file changed, 32 insertions(+), 16 deletions(-)
>
> diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c
> index 8859eebea5..e422e0b348 100644
> --- a/cmd/bootmenu.c
> +++ b/cmd/bootmenu.c
> @@ -20,6 +20,20 @@
> /* maximum bootmenu entries */
> #define MAX_COUNT99
>
> +#if (CONFIG_IS_ENABLED(EFI_LOADER))
> +#define TITLE_CHAR u16
> +#define titlefmt "ls"
> +#define TITLE_STRDUP u16_strdup
> +#define TITLE_STRNCPY(d, s, l) utf8_utf16_strncpy(, s, l)
> +#define TITLE_STR(x) u##x
> +#else
> +#define TITLE_CHAR char
> +#define titlefmt "s"
> +#define TITLE_STRDUP strdup
> +#define TITLE_STRNCPY(d, s, l) strncpy(d, s, l)
> +#define TITLE_STR(x) x
> +#endif
This reminds me win98 days with tchar macros when NT systems used UCS-2
and DOS systems OEM codepage... Do we really have to use these 20 years
old patterns in new code?
Still, I do not see reason why EFI bloatware code has to be in common
U-boot code and not in separated parts?
> +
> /* maximal size of bootmenu env
> * 9 = strlen("bootmenu_")
> * 2 = strlen(MAX_COUNT)
> @@ -43,7 +57,7 @@ enum boot_type {
> struct bootmenu_entry {
> unsigned short int num; /* unique number 0 .. MAX_COUNT */
> char key[3];/* key identifier of number */
> - u16 *title; /* title of entry */
> + TITLE_CHAR *title; /* title of entry */
> char *command; /* hush command of entry */
> enum boot_type type;/* boot type of entry */
> u16 bootorder; /* order for each boot type */
> @@ -76,7 +90,7 @@ static void bootmenu_print_entry(void *data)
> if (reverse)
> puts(ANSI_COLOR_REVERSE);
>
> - printf("%ls", entry->title);
> + printf("%" titlefmt "", entry->title);
>
> if (reverse)
> puts(ANSI_COLOR_RESET);
> @@ -170,7 +184,7 @@ static int prepare_bootmenu_entry(struct bootmenu_data
> *menu,
> struct bootmenu_entry *iter = *current;
>
> while ((option = bootmenu_getoption(i))) {
> - u16 *buf;
> + TITLE_CHAR *buf;
>
> sep = strchr(option, '=');
> if (!sep) {
> @@ -183,13 +197,13 @@ static int prepare_bootmenu_entry(struct bootmenu_data
> *menu,
> return -ENOMEM;
>
> len = sep-option;
> - buf = calloc(1, (len + 1) * sizeof(u16));
> + buf = calloc(1, (len + 1) * sizeof(TITLE_CHAR));
> entry->title = buf;
> if (!entry->title) {
> free(entry);
> return -ENOMEM;
> }
> - utf8_utf16_strncpy(, option, len);
> + TITLE_STRNCPY(buf, option, len);
>
> len = strlen(sep + 1);
> entry->command = malloc(len + 1);
> @@ -227,6 +241,7 @@ static int prepare_bootmenu_entry(struct bootmenu_data
> *menu,
> return 1;
> }
>
> +#if (CONFIG_IS_ENABLED(CMD_BOOTEFI_BOOTMGR))
> /**
> * prepare_uefi_bootorder_entry() - generate the uefi bootmenu entries
> *
> @@ -315,6 +330,7 @@ static int prepare_uefi_bootorder_entry(struct
> bootmenu_data *menu,
>
> return 1;
> }
> +#endif
>
> static struct bootmenu_data *bootmenu_create(int delay)
> {
> @@ -341,13 +357,13 @@ static struct bootmenu_data *bootmenu_create(int delay)
> if (ret < 0)
> goto cleanup;
>
> - if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR)) {
> - if (i < MAX_COUNT - 1) {
> - ret = prepare_uefi_bootorder_entry(menu, , );
> - if (ret < 0 && ret != -ENOENT)
> - goto cleanup;
> - }
> +#if (CONFIG_IS_ENABLED(CMD_BOOTEFI_BOOTMGR))
> + if (i < MAX_COUNT - 1) {
> + ret = prepare_uefi_bootorder_entry(menu, , );
> + if (ret < 0 && ret != -ENOENT)
> + goto cleanup;
> }
> +#endif
>
> /* Add U-Boot console entry at the end */
> if (i <= MAX_COUNT - 1) {
> @@ -357,9 +373,9 @@ static struct bootmenu_data *bootmenu_create(int delay)
>
> /* Add Quit entry if entering U-Boot console is disabled */
> if (IS_ENABLED(CONFIG_CMD_BOOTMENU_ENTER_UBOOT_CONSOLE))
> - entry->title = u16_strdup(u"U-Boot console");
> +
Re: U-Boot v2022.07-rc2 regression: Bootmenu is completely broken
On Tuesday 24 May 2022 09:26:08 Masahisa Kojima wrote:
> On Tue, 24 May 2022 at 04:41, Pali Rohár wrote:
> >
> > On Monday 23 May 2022 15:29:04 Tom Rini wrote:
> > > On Mon, May 23, 2022 at 09:27:37PM +0200, Pali Rohár wrote:
> > > > Hello!
> > > >
> > > > U-Boot Bootmenu in git master branch is completely broken and does not
> > > > work. You can test it e.g. in qemu version of nokia n900 (see rx51.rst).
> > > >
> > > > Bootmenu just prints garbage on both serial console and VGA video
> > > > output and no option works.
> > > >
> > > > *** U-Boot Boot Menu ***
> > > >
> > > > A
> > > > I
> > > > E
> > > > U
> > > > U
> > > >
> > > >
> > > > Press UP/DOWN to move, ENTER to select, ESC/CTRL+C to quit
> > > >
> > > > I bisected this issue and problem is in:
> > > >
> > > > a3d0aa87acbec4b983f54c24a6e7fd8e9e7b9728 is the first bad commit
> > > > commit a3d0aa87acbec4b983f54c24a6e7fd8e9e7b9728
> > > > Author: Masahisa Kojima
> > > > Date: Thu Apr 28 17:09:41 2022 +0900
> > > >
> > > > bootmenu: update bootmenu_entry structure
>
> This patch modified the menu title from char* to
> u16*(UTF16 string) to support the EFI system.
> But if the system does not support EFI, printf("%ls") does not
> work correctly.
Now I see it from commit description.
But WHY on the earth?? It double size of all strings which is the issue
for space limited devices. Nobody sane is using legacy encoding UTF-16
in these days and even Windows people are moving to UTF-8. So
introduction of UTF-16 in **common** U-Boot code is step backward. And
if EFI is the reason, it should have been put into EFI code, not into
common U-Boot code. I really dislike this EFI bloatware... I have
checked and this commit increased size of u-boot binaries also on
non-EFI platforms, which is really bad. Sigh. For example on Nokia N900
we really do not have free space for this EFI nonsense.
> # I think currently only the first character is displayed.
>
> I will send a fix.
> Sorry for bothering you.
>
> Thanks,
> Masahisa Kojima
>
> > > >
> > > > This is a preparation for succeeding addition of uefi boot
> > > > and distro boot menu entries into bootmenu.
> > > > The bootmenu_entry title is updated to u16 string because
> > > > uefi use u16 string. This commit also factors out the function
> > > > to prepare the entries generated by "bootmenu_x" U-Boot
> > > > environment
> > > > variable.
> > > >
> > > > Signed-off-by: Masahisa Kojima
> > > > Reviewed-by: Heinrich Schuchardt
> > > >
> > > >
> > > > :04 04 37c91714b049be307521831c0470b3b6c8af2407
> > > > b3e865073a46108cccbf4dc0b401789ef0b05a2e M cmd
> > > >
> > > > Before that commit Bootmenu works fine and on serial console prints:
> > > >
> > > > *** U-Boot Boot Menu ***
> > > >
> > > > Attached kernel
> > > > Internal eMMC
> > > > External SD card
> > > > U-Boot boot order
> > > > U-Boot console
> > > >
> > > >
> > > > Press UP/DOWN to move, ENTER to select, ESC/CTRL+C to quit
> > > >
> > > >
> > > > Could you please look at it and fix it?
> > >
> > > To be clear, the bootmenu stuff is or is not supposed to be tested with
> > > the current rx51 test script?
> >
> > rx51 test script sets bootmenu timeout to 1s and just let bootmenu
> > timeout. Timeout cause that default boot action is taken. Script does
> > not interact with stdin / bootmenu.
> >
> > So... not selecting anything in bootmenu is working and hence rx51 test
> > script did not complained.
Re: [PATCH 0/5] Add support for versal specific cadence ospi driver
Hi Jagan, On 5/12/22 12:05, Ashok Reddy Soma wrote: This patch series does the following: * Move macros from cadence driver to cadence header file * Add new versal specific cadence ospi driver * Reset qspi flash in when driver probed * Enable/Disable apb linear mode based on dma usage * Fix cadence qspi flash speed programming T Karthik Reddy (5): spi: cadence-qspi: move cadence qspi macros to header file arm64: versal: Add versal specific cadence ospi driver spi: cadence-qspi: reset qspi flash for versal platform spi: cadence_qspi: Enable apb linear mode for apb read & write operations spi: cadence-qspi: Fix programming ospi flash speed MAINTAINERS | 1 + arch/arm/mach-versal/include/mach/hardware.h | 15 ++ configs/xilinx_versal_virt_defconfig | 2 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/cadence_ospi_versal.c| 237 +++ drivers/spi/cadence_qspi.c | 40 +++- drivers/spi/cadence_qspi.h | 189 +++ drivers/spi/cadence_qspi_apb.c | 163 + include/zynqmp_firmware.h| 9 + 10 files changed, 510 insertions(+), 155 deletions(-) create mode 100644 drivers/spi/cadence_ospi_versal.c Are you going to review this? If not I will queue it via my tree. Thanks, Michal
[PATCH V5 9/9] imx: imx8mm-icore: migrate to use BINMAN
From: Peng Fan Use BINMAN instead of imx specific packing method. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/Kconfig | 1 + arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg | 10 +- configs/imx8mm-icore-mx8mm-ctouch2_defconfig| 2 +- configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 2 +- 4 files changed, 4 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 61397bf88d1..ba26975544c 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -68,6 +68,7 @@ config TARGET_IMX8MM_EVK config TARGET_IMX8MM_ICORE_MX8MM bool "Engicam i.Core MX8M Mini SOM" + select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 diff --git a/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg b/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg index e06d53ef417..5dcb8ae72f0 100644 --- a/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg +++ b/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg @@ -3,13 +3,5 @@ * Copyright 2019 NXP */ - -FIT BOOT_FROM sd -LOADER spl/u-boot-spl-ddr.bin 0x7E1000 -SECOND_LOADER u-boot.itb 0x4020 0x6 - -DDR_FW lpddr4_pmu_train_1d_imem.bin -DDR_FW lpddr4_pmu_train_1d_dmem.bin -DDR_FW lpddr4_pmu_train_2d_imem.bin -DDR_FW lpddr4_pmu_train_2d_dmem.bin +LOADER u-boot-spl-ddr.bin 0x7E1000 diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig index d95a74a7237..dcb12e5d026 100644 --- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig +++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig @@ -20,7 +20,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-ctouch2.dtb" CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig index 43c697a39d8..22acf7317b4 100644 --- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig +++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig @@ -20,7 +20,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-edimm2.2.dtb" CONFIG_SPL_BOARD_INIT=y -- 2.36.0
[PATCH V5 8/9] binman_sym: guard with CONFIG_SPL_BINMAN_SYMBOLS
From: Peng Fan There is case that CONFIG_BINMAN is defined, but CONFIG_SPL_BINMAN_SYMBOLS is not defined. In that case, there will be build failure. So use CONFIG_SPL_BINMAN_SYMBOLS to guard the macros, and define CONFIG_SPL_BINMAN_SYMBOLS in binman syms test. Tested-by: Tim Harvey #imx8m[m,n,p]-venice Signed-off-by: Peng Fan --- include/binman_sym.h| 2 +- tools/binman/test/u_boot_binman_syms.c | 1 + tools/binman/test/u_boot_binman_syms_size.c | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/include/binman_sym.h b/include/binman_sym.h index 72e6765fe52..548d8f5654c 100644 --- a/include/binman_sym.h +++ b/include/binman_sym.h @@ -13,7 +13,7 @@ #define BINMAN_SYM_MISSING (-1UL) -#ifdef CONFIG_BINMAN +#ifdef CONFIG_SPL_BINMAN_SYMBOLS /** * binman_symname() - Internal function to get a binman symbol name diff --git a/tools/binman/test/u_boot_binman_syms.c b/tools/binman/test/u_boot_binman_syms.c index 37fc339ce84..f4a4d1f6846 100644 --- a/tools/binman/test/u_boot_binman_syms.c +++ b/tools/binman/test/u_boot_binman_syms.c @@ -6,6 +6,7 @@ */ #define CONFIG_BINMAN +#define CONFIG_SPL_BINMAN_SYMBOLS #include binman_sym_declare(unsigned long, u_boot_spl_any, offset); diff --git a/tools/binman/test/u_boot_binman_syms_size.c b/tools/binman/test/u_boot_binman_syms_size.c index 7224bc1863c..3a01d8ca4be 100644 --- a/tools/binman/test/u_boot_binman_syms_size.c +++ b/tools/binman/test/u_boot_binman_syms_size.c @@ -6,6 +6,7 @@ */ #define CONFIG_BINMAN +#define CONFIG_SPL_BINMAN_SYMBOLS #include binman_sym_declare(char, u_boot_spl, pos); -- 2.36.0
[PATCH V5 7/9] arm: dts: imx8m: shrink ddr firmware size to actual file size
From: Peng Fan
After we switch to use BINMAN_SYMBOLS, there is no need to pad
the file size to 0x8000 and 0x4000. After we use BINMAN_SYMBOLS,
the u-boot-spl-ddr.bin shrink about 36KB with i.MX8MP-EVK.
Tested-by: Tim Harvey #imx8m[m,n,p]-venice
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mm-u-boot.dtsi | 8
arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi| 8
arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 4 ++--
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 8
arch/arm/dts/imx8mn-evk-u-boot.dtsi | 8
arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 8
arch/arm/dts/imx8mn-venice-u-boot.dtsi| 8
arch/arm/dts/imx8mp-u-boot.dtsi | 8
arch/arm/dts/imx8mq-cm-u-boot.dtsi| 8
arch/arm/dts/imx8mq-u-boot.dtsi | 8
10 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index 769b7963db1..7600bd3d30a 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -42,25 +42,25 @@
imem-1d {
filename = "lpddr4_pmu_train_1d_imem.bin";
- size = <0x8000>;
+ align-end = <4>;
type = "blob-ext";
};
dmem-1d {
filename = "lpddr4_pmu_train_1d_dmem.bin";
- size = <0x4000>;
+ align-end = <4>;
type = "blob-ext";
};
imem-2d {
filename = "lpddr4_pmu_train_2d_imem.bin";
- size = <0x8000>;
+ align-end = <4>;
type = "blob-ext";
};
dmem-2d {
filename = "lpddr4_pmu_train_2d_dmem.bin";
- size = <0x4000>;
+ align-end = <4>;
type = "blob-ext";
};
};
diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
index 024d57712b8..090a17c93a7 100644
--- a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
@@ -150,26 +150,26 @@
imem-1d {
filename = "lpddr4_pmu_train_1d_imem.bin";
- size = <0x8000>;
type = "blob-ext";
+ align-end = <4>;
};
dmem-1d {
filename = "lpddr4_pmu_train_1d_dmem.bin";
- size = <0x4000>;
type = "blob-ext";
+ align-end = <4>;
};
imem-2d {
filename = "lpddr4_pmu_train_2d_imem.bin";
- size = <0x8000>;
type = "blob-ext";
+ align-end = <4>;
};
dmem-2d {
filename = "lpddr4_pmu_train_2d_dmem.bin";
- size = <0x4000>;
type = "blob-ext";
+ align-end = <4>;
};
};
diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
index 8f95f0efe65..6a79e2743f8 100644
--- a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
+++ b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
@@ -114,13 +114,13 @@
imem-1d {
filename = "ddr3_imem_1d.bin";
- size = <0x8000>;
+ align-end = <4>;
type = "blob-ext";
};
dmem-1d {
filename = "ddr3_dmem_1d.bin";
- size = <0x4000>;
+ align-end = <4>;
type = "blob-ext";
};
};
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index ef1f60bff8d..7660ab8d58b 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -158,26 +158,26 @@
imem-1d {
filename = "ddr4_imem_1d_201810.bin";
- size = <0x8000>;
type = "blob-ext";
+ align-end = <4>;
};
dmem-1d {
filename = "ddr4_dmem_1d_201810.bin";
- size = <0x4000>;
type = "blob-ext";
+ align-end = <4>;
};
imem-2d {
filename = "ddr4_imem_2d_201810.bin";
- size = <0x8000>;
[PATCH V5 6/9] ddr: imx8m: helper: load ddr firmware according to binman symbols
From: Peng Fan
By reading binman symbols, we no need hard coded IMEM_LEN/DMEM_LEN after
we update the binman dtsi to drop 0x8000/0x4000 length for the firmware.
And that could save binary size for many KBs.
Tested-by: Tim Harvey #imx8m[m,n,p]-venice
Signed-off-by: Peng Fan
---
drivers/ddr/imx/imx8m/helper.c | 51 --
1 file changed, 43 insertions(+), 8 deletions(-)
diff --git a/drivers/ddr/imx/imx8m/helper.c b/drivers/ddr/imx/imx8m/helper.c
index f23904bf712..5d7f6110639 100644
--- a/drivers/ddr/imx/imx8m/helper.c
+++ b/drivers/ddr/imx/imx8m/helper.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -25,15 +26,30 @@ DECLARE_GLOBAL_DATA_PTR;
#define DMEM_OFFSET_ADDR 0x00054000
#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
+binman_sym_declare(ulong, imem_1d, image_pos);
+binman_sym_declare(ulong, imem_1d, size);
+
+binman_sym_declare(ulong, dmem_1d, image_pos);
+binman_sym_declare(ulong, dmem_1d, size);
+
+#if !IS_ENABLED(CONFIG_IMX8M_DDR3L)
+binman_sym_declare(ulong, imem_2d, image_pos);
+binman_sym_declare(ulong, imem_2d, size);
+
+binman_sym_declare(ulong, dmem_2d, image_pos);
+binman_sym_declare(ulong, dmem_2d, size);
+#endif
+
/* We need PHY iMEM PHY is 32KB padded */
void ddr_load_train_firmware(enum fw_type type)
{
u32 tmp32, i;
u32 error = 0;
unsigned long pr_to32, pr_from32;
- unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
- unsigned long imem_start = (unsigned long)&_end + fw_offset;
- unsigned long dmem_start;
+ uint32_t fw_offset = type ? IMEM_2D_OFFSET : 0;
+ uint32_t imem_start = (unsigned long)&_end + fw_offset;
+ uint32_t dmem_start;
+ uint32_t imem_len = IMEM_LEN, dmem_len = DMEM_LEN;
#ifdef CONFIG_SPL_OF_CONTROL
if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) {
@@ -43,11 +59,30 @@ void ddr_load_train_firmware(enum fw_type type)
}
#endif
- dmem_start = imem_start + IMEM_LEN;
+ dmem_start = imem_start + imem_len;
+
+ if (CONFIG_IS_ENABLED(BINMAN_SYMBOLS)) {
+ switch (type) {
+ case FW_1D_IMAGE:
+ imem_start = binman_sym(ulong, imem_1d, image_pos);
+ imem_len = binman_sym(ulong, imem_1d, size);
+ dmem_start = binman_sym(ulong, dmem_1d, image_pos);
+ dmem_len = binman_sym(ulong, dmem_1d, size);
+ break;
+ case FW_2D_IMAGE:
+#if !IS_ENABLED(CONFIG_IMX8M_DDR3L)
+ imem_start = binman_sym(ulong, imem_2d, image_pos);
+ imem_len = binman_sym(ulong, imem_2d, size);
+ dmem_start = binman_sym(ulong, dmem_2d, image_pos);
+ dmem_len = binman_sym(ulong, dmem_2d, size);
+#endif
+ break;
+ }
+ }
pr_from32 = imem_start;
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
- for (i = 0x0; i < IMEM_LEN; ) {
+ for (i = 0x0; i < imem_len; ) {
tmp32 = readl(pr_from32);
writew(tmp32 & 0x, pr_to32);
pr_to32 += 4;
@@ -59,7 +94,7 @@ void ddr_load_train_firmware(enum fw_type type)
pr_from32 = dmem_start;
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
- for (i = 0x0; i < DMEM_LEN; ) {
+ for (i = 0x0; i < dmem_len; ) {
tmp32 = readl(pr_from32);
writew(tmp32 & 0x, pr_to32);
pr_to32 += 4;
@@ -72,7 +107,7 @@ void ddr_load_train_firmware(enum fw_type type)
debug("check ddr_pmu_train_imem code\n");
pr_from32 = imem_start;
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
- for (i = 0x0; i < IMEM_LEN; ) {
+ for (i = 0x0; i < imem_len; ) {
tmp32 = (readw(pr_to32) & 0x);
pr_to32 += 4;
tmp32 += ((readw(pr_to32) & 0x) << 16);
@@ -93,7 +128,7 @@ void ddr_load_train_firmware(enum fw_type type)
debug("check ddr4_pmu_train_dmem code\n");
pr_from32 = dmem_start;
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
- for (i = 0x0; i < DMEM_LEN;) {
+ for (i = 0x0; i < dmem_len;) {
tmp32 = (readw(pr_to32) & 0x);
pr_to32 += 4;
tmp32 += ((readw(pr_to32) & 0x) << 16);
--
2.36.0
[PATCH V5 5/9] arm: dts: imx8m: add no-u-boot-any property
From: Peng Fan
Preparing to support BINMAN_SYMBOLS, i.MX8M no need u-boot-any in spl
stage, so add no-u-boot-any property to avoid binman report error.
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mm-u-boot.dtsi | 1 +
arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi| 1 +
arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 1 +
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 1 +
arch/arm/dts/imx8mn-evk-u-boot.dtsi | 1 +
arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 1 +
arch/arm/dts/imx8mn-venice-u-boot.dtsi| 1 +
arch/arm/dts/imx8mp-u-boot.dtsi | 1 +
arch/arm/dts/imx8mq-cm-u-boot.dtsi| 1 +
arch/arm/dts/imx8mq-u-boot.dtsi | 1 +
10 files changed, 10 insertions(+)
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index dc036894d82..769b7963db1 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -33,6 +33,7 @@
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
+ no-u-boot-any;
u-boot-spl {
align-end = <4>;
diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
index 3c29f71ec6c..024d57712b8 100644
--- a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
@@ -142,6 +142,7 @@
pad-byte = <0xff>;
align-size = <4>;
align = <4>;
+ no-u-boot-any;
u-boot-spl {
align-end = <4>;
diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
index 904f1d795a3..8f95f0efe65 100644
--- a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
+++ b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
@@ -105,6 +105,7 @@
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
+ no-u-boot-any;
u-boot-spl {
align-end = <4>;
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 3f6b67e22df..ef1f60bff8d 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -150,6 +150,7 @@
pad-byte = <0xff>;
align-size = <4>;
align = <4>;
+ no-u-boot-any;
u-boot-spl {
align-end = <4>;
diff --git a/arch/arm/dts/imx8mn-evk-u-boot.dtsi
b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
index b73ce32221f..bd035f2e780 100644
--- a/arch/arm/dts/imx8mn-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
@@ -31,6 +31,7 @@
pad-byte = <0xff>;
align-size = <4>;
align = <4>;
+ no-u-boot-any;
u-boot-spl {
align-end = <4>;
diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
index c5fa37a3b8a..484b55d4668 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -124,6 +124,7 @@
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
+ no-u-boot-any;
u-boot-spl {
align-end = <4>;
diff --git a/arch/arm/dts/imx8mn-venice-u-boot.dtsi
b/arch/arm/dts/imx8mn-venice-u-boot.dtsi
index 1e8b0e2aeed..62ca7cae0ec 100644
--- a/arch/arm/dts/imx8mn-venice-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-venice-u-boot.dtsi
@@ -120,6 +120,7 @@
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
+ no-u-boot-any;
u-boot-spl {
align-end = <4>;
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi
index aaf70d92dfb..2c66e30708f 100644
--- a/arch/arm/dts/imx8mp-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-u-boot.dtsi
@@ -56,6 +56,7 @@
pad-byte = <0xff>;
align-size = <4>;
align = <4>;
+ no-u-boot-any;
u-boot-spl {
align-end = <4>;
diff --git a/arch/arm/dts/imx8mq-cm-u-boot.dtsi
b/arch/arm/dts/imx8mq-cm-u-boot.dtsi
index 79a71c2a414..afa0d07296d 100644
--- a/arch/arm/dts/imx8mq-cm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-cm-u-boot.dtsi
@@ -23,6 +23,7 @@
pad-byte = <0xff>;
align-size = <4>;
align = <4>;
+ no-u-boot-any;
u-boot-spl {
align-end = <4>;
diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi
index 31c96f919c0..90014710ea5 100644
---
[PATCH V5 4/9] binman: introduce no-u-boot-any property
From: Peng Fan
By default when BINMAN_SYMBOLS is enabled, common/spl/spl.c has a code
piece `binman_sym_declare(ulong, u_boot_any, image_pos);` which requires
u-boot* node in device tree binman node section. But some
platforms(i.MX8M) not need it. To avoid build break with BINMAN_SYMBOLS,
introduce a no-u-boot-any property.
Signed-off-by: Peng Fan
---
tools/binman/binman.rst | 6 ++
tools/binman/etype/section.py | 5 +
2 files changed, 11 insertions(+)
diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst
index 935839c433e..9dab83b45c8 100644
--- a/tools/binman/binman.rst
+++ b/tools/binman/binman.rst
@@ -502,6 +502,12 @@ no-expanded:
`no-expanded` property disables this just for a single entry. Put the
`no-expanded` boolean property in the node to select this behaviour.
+no-u-boot-any:
+By default when BINMAN_SYMBOLS are enabled,
+`binman_sym_declare(ulong, u_boot_any, image_pos);` requires a u-boot node
+in binman section. Some platforms not need it with the help of this flag
+set.
+
The attributes supported for images and sections are described below. Several
are similar to those for entries.
diff --git a/tools/binman/etype/section.py b/tools/binman/etype/section.py
index e3f362b442b..a09c539a12b 100644
--- a/tools/binman/etype/section.py
+++ b/tools/binman/etype/section.py
@@ -164,6 +164,7 @@ class Entry_section(Entry):
self._skip_at_start = None
self._end_4gb = False
self._ignore_missing = False
+self._no_uboot_any = False
def ReadNode(self):
"""Read properties from the section node"""
@@ -172,6 +173,7 @@ class Entry_section(Entry):
self._sort = fdt_util.GetBool(self._node, 'sort-by-offset')
self._end_4gb = fdt_util.GetBool(self._node, 'end-at-4gb')
self._skip_at_start = fdt_util.GetInt(self._node, 'skip-at-start')
+self._no_uboot_any = fdt_util.GetBool(self._node, 'no-u-boot-any')
if self._end_4gb:
if not self.size:
self.Raise("Section size must be provided when using
end-at-4gb")
@@ -565,9 +567,12 @@ class Entry_section(Entry):
rest = name[len(root):]
if rest in ['', '-img', '-nodtb']:
entry = entries[name]
+
if not entry:
err = ("%s: Entry '%s' not found in list (%s)" %
(msg, entry_name, ','.join(entries.keys(
+if entry_name == 'u-boot-any' and self._no_uboot_any:
+return None
if optional:
print('Warning: %s' % err, file=sys.stderr)
return None
--
2.36.0
[PATCH V5 3/9] tools: binman: section: replace @ with -
From: Peng Fan
In arch/arm/dts/imx8mp-u-boot.dtsi, there are blob-ext@1, blob-ext@2 and
etc which is for packing ddr phy firmware. However we could not declare
symbol name such as 'binman_sym_declare(ulong, blob_ext@1, image_pos)',
because '@' is not allowed, so we choose to declare the symbol
'binman_sym_declare(ulong, blob_ext_1, image_pos);' with '@' replaced with
'_'. It does not impact if there is no '@' in section name.
Tested-by: Tim Harvey #imx8m[m,n,p]-venice
Reviewed-by: Tom Rini
Signed-off-by: Peng Fan
---
tools/binman/etype/section.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/binman/etype/section.py b/tools/binman/etype/section.py
index bd67238b919..e3f362b442b 100644
--- a/tools/binman/etype/section.py
+++ b/tools/binman/etype/section.py
@@ -875,7 +875,7 @@ class Entry_section(Entry):
entries[entry.GetPath()] = entry
for entry in to_add.values():
self._CollectEntries(entries, entries_by_name, entry)
-entries_by_name[add_entry.name] = add_entry
+entries_by_name[add_entry.name.replace('@', '-')] = add_entry
def MissingArgs(self, entry, missing):
"""Report a missing argument, if enabled
--
2.36.0
[PATCH V5 2/9] armv8: u-boot-spl.lds: mark __image_copy_start as symbol
From: Peng Fan
In arch/arm/lib/sections.c there is below code:
char __image_copy_start[0] __section(".__image_copy_start");
But actually 'objdump -t spl/u-boot-spl' not able to find out
symbol '__image_copy_start' for binman update image-pos/size.
So update link file
Reviewed-by: Tom Rini
Tested-by: Tim Harvey #imx8m[m,n,p]-venice
Signed-off-by: Peng Fan
---
arch/arm/cpu/armv8/u-boot-spl.lds | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds
b/arch/arm/cpu/armv8/u-boot-spl.lds
index 730eb93dbc3..9b1e7d46287 100644
--- a/arch/arm/cpu/armv8/u-boot-spl.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -23,7 +23,7 @@ SECTIONS
{
.text : {
. = ALIGN(8);
- *(.__image_copy_start)
+ __image_copy_start = .;
CPUDIR/start.o (.text*)
*(.text*)
} >.sram
--
2.36.0
[PATCH V5 1/9] arm: dts: imx8m: update binman ddr firmware node name
From: Peng Fan
We are migrating to use BINMAN SYMBOLS, the current name is not
a valid binman type, so update to unify them.
Also add `type = "blob-ext";` for generating a valid binman symbol
Tested-by: Tim Harvey #imx8m[m,n,p]-venice
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mm-u-boot.dtsi | 8
arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi| 12
arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 4 ++--
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 12
arch/arm/dts/imx8mn-evk-u-boot.dtsi | 12
arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 8
arch/arm/dts/imx8mn-venice-u-boot.dtsi| 8
arch/arm/dts/imx8mp-u-boot.dtsi | 12
arch/arm/dts/imx8mq-cm-u-boot.dtsi| 12
arch/arm/dts/imx8mq-u-boot.dtsi | 8
10 files changed, 58 insertions(+), 38 deletions(-)
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index 9f66cdb65a9..dc036894d82 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -39,25 +39,25 @@
filename = "u-boot-spl.bin";
};
- 1d-imem {
+ imem-1d {
filename = "lpddr4_pmu_train_1d_imem.bin";
size = <0x8000>;
type = "blob-ext";
};
- 1d-dmem {
+ dmem-1d {
filename = "lpddr4_pmu_train_1d_dmem.bin";
size = <0x4000>;
type = "blob-ext";
};
- 2d-imem {
+ imem-2d {
filename = "lpddr4_pmu_train_2d_imem.bin";
size = <0x8000>;
type = "blob-ext";
};
- 2d-dmem {
+ dmem-2d {
filename = "lpddr4_pmu_train_2d_dmem.bin";
size = <0x4000>;
type = "blob-ext";
diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
index eb1dd8debba..3c29f71ec6c 100644
--- a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
@@ -147,24 +147,28 @@
align-end = <4>;
};
- blob_1: blob-ext@1 {
+ imem-1d {
filename = "lpddr4_pmu_train_1d_imem.bin";
size = <0x8000>;
+ type = "blob-ext";
};
- blob_2: blob-ext@2 {
+ dmem-1d {
filename = "lpddr4_pmu_train_1d_dmem.bin";
size = <0x4000>;
+ type = "blob-ext";
};
- blob_3: blob-ext@3 {
+ imem-2d {
filename = "lpddr4_pmu_train_2d_imem.bin";
size = <0x8000>;
+ type = "blob-ext";
};
- blob_4: blob-ext@4 {
+ dmem-2d {
filename = "lpddr4_pmu_train_2d_dmem.bin";
size = <0x4000>;
+ type = "blob-ext";
};
};
diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
index 46a9d7fd78b..904f1d795a3 100644
--- a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
+++ b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
@@ -111,13 +111,13 @@
filename = "u-boot-spl.bin";
};
- 1d-imem {
+ imem-1d {
filename = "ddr3_imem_1d.bin";
size = <0x8000>;
type = "blob-ext";
};
- 1d_dmem {
+ dmem-1d {
filename = "ddr3_dmem_1d.bin";
size = <0x4000>;
type = "blob-ext";
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 4d0ecb07d4f..3f6b67e22df 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -155,24 +155,28 @@
align-end = <4>;
};
- blob_1: blob-ext@1 {
+ imem-1d {
filename = "ddr4_imem_1d_201810.bin";
size = <0x8000>;
+ type = "blob-ext";
};
- blob_2: blob-ext@2 {
+ dmem-1d {
filename = "ddr4_dmem_1d_201810.bin";
size = <0x4000>;
+ type = "blob-ext";
};
- blob_3: blob-ext@3
[PATCH V5 0/9] arm64: binman: use binman symbols for imx
From: Peng Fan V5: Introduce no-u-boot-any property to drop the X86 guard patch 1 Add blob-ext type for ddr firmware node Include a missing dts change V4: Fix three boards build failure V3: Add R-b/T-b Fix build warning V2: resolve some CI failure include patch 7 binman symbol is a good feature, but only used on X86 for now. This patchset is to use it for i.MX8M platform. The current imx8m ddr phy firmware consumes lots of space, because we pad them to the largest 32KB and 16KB for IMEM and DMEM. With this patchset we use binman symbols to get firmware location and size, we could save near 36KB with i.MX8MP-EVK. Please help check and test Peng Fan (9): arm: dts: imx8m: update binman ddr firmware node name armv8: u-boot-spl.lds: mark __image_copy_start as symbol tools: binman: section: replace @ with - binman: introduce no-u-boot-any property arm: dts: imx8m: add no-u-boot-any property ddr: imx8m: helper: load ddr firmware according to binman symbols arm: dts: imx8m: shrink ddr firmware size to actual file size binman_sym: guard with CONFIG_SPL_BINMAN_SYMBOLS imx: imx8mm-icore: migrate to use BINMAN arch/arm/cpu/armv8/u-boot-spl.lds | 2 +- arch/arm/dts/imx8mm-u-boot.dtsi | 17 --- arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi| 21 +--- .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 9 ++-- arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 21 +--- arch/arm/dts/imx8mn-evk-u-boot.dtsi | 21 +--- .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 17 --- arch/arm/dts/imx8mn-venice-u-boot.dtsi| 17 --- arch/arm/dts/imx8mp-u-boot.dtsi | 21 +--- arch/arm/dts/imx8mq-cm-u-boot.dtsi| 21 +--- arch/arm/dts/imx8mq-u-boot.dtsi | 17 --- arch/arm/mach-imx/imx8m/Kconfig | 1 + .../mach-imx/imx8m/imximage-8mm-lpddr4.cfg| 10 +--- configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 2 +- configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 2 +- drivers/ddr/imx/imx8m/helper.c| 51 --- include/binman_sym.h | 2 +- tools/binman/binman.rst | 6 +++ tools/binman/etype/section.py | 7 ++- tools/binman/test/u_boot_binman_syms.c| 1 + tools/binman/test/u_boot_binman_syms_size.c | 1 + 21 files changed, 169 insertions(+), 98 deletions(-) -- 2.36.0
[PATCH] arm: dts: socfpga: stratix10: Update MMC smplsel value
From: Yau Wai Gan
This new MMC sample select value is obtained from running
tests on multiple Stratix 10 boards and proven working.
Signed-off-by: Yau Wai Gan
---
arch/arm/dts/socfpga_stratix10_socdk.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts
b/arch/arm/dts/socfpga_stratix10_socdk.dts
index 6622720f77..8e6a405917 100755
--- a/arch/arm/dts/socfpga_stratix10_socdk.dts
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -93,7 +93,7 @@
broken-cd;
bus-width = <4>;
drvsel = <3>;
- smplsel = <0>;
+ smplsel = <2>;
};
{
--
2.13.0
Re: [PATCH] xilinx: zynqmp: Wire tee for Multi DTB use cases
st 18. 5. 2022 v 13:41 odesílatel Michal Simek napsal:
>
> Fix TEE wiring when MULTI_DTB is selected.
>
> Signed-off-by: Michal Simek
> ---
>
> arch/arm/mach-zynqmp/mkimage_fit_atf.sh | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
> b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
> index 72a8a3eb7714..40ed23b0ba6a 100755
> --- a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
> +++ b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh
> @@ -140,6 +140,15 @@ cat << __CONF_SECTION1_EOF
> };
> __CONF_SECTION1_EOF
> else
> +if [ -f $BL32 ]; then
> +cat << __CONF_SECTION1_EOF
> + config_1 {
> + description = "Multi DTB with TF-A and TEE";
> + firmware = "atf";
> + loadables = "uboot", "tee", "fdt_1";
> + };
> +__CONF_SECTION1_EOF
> +else
> cat << __CONF_SECTION1_EOF
> config_1 {
> description = "Multi DTB with TF-A";
> @@ -148,6 +157,7 @@ cat << __CONF_SECTION1_EOF
> };
> __CONF_SECTION1_EOF
> fi
> +fi
>
> cat << __ITS_EOF
> };
> --
> 2.36.0
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
[v4 06/12] arm: dts: aspeed: Update SPI flash node settings
For both AST2500 and AST2600, there are three
SPI controllers, FMC(Firmware Memory Controller),
SPI1 and SPI2. The clock source is HCLK. Following
is the basic information for ASPEED SPI controller.
AST2500:
- FMC:
CS number: 3
controller reg: 0x1e62 - 0x1e62
decoded address: 0x2000 - 0x2fff
- SPI1:
CS number: 2
controller reg: 0x1e63 - 0x1e630fff
decoded address: 0x3000 - 0x37ff
- SPI2:
CS number: 2
controller reg: 0x1e631000 - 0x1e631fff
decoded address: 0x3800 - 0x3fff
AST2600:
- FMC:
CS number: 3
controller reg: 0x1e62 - 0x1e62
decoded address: 0x2000 - 0x2fff
- SPI1:
CS number: 2
controller reg: 0x1e63 - 0x1e630fff
decoded address: 0x3000 - 0x3fff
- SPI2:
CS number: 3
controller reg: 0x1e631000 - 0x1e631fff
decoded address: 0x5000 - 0x5fff
Signed-off-by: Chin-Ting Kuo
---
arch/arm/dts/ast2500-evb.dts | 33 +
arch/arm/dts/ast2500.dtsi| 23 ---
arch/arm/dts/ast2600-evb.dts | 8
arch/arm/dts/ast2600.dtsi| 34 +++---
4 files changed, 68 insertions(+), 30 deletions(-)
diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index 4796ed445f..c6b7675902 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -73,3 +73,36 @@
pinctrl-names = "default";
pinctrl-0 = <_sd2_default>;
};
+
+ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <_fwspics1_default>;
+
+ flash@0 {
+ status = "okay";
+ spi-max-frequency = <5000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ };
+
+ flash@1 {
+ status = "okay";
+ spi-max-frequency = <5000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ };
+};
+
+ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <_spi1cs1_default>;
+
+ flash@0 {
+ status = "okay";
+ spi-max-frequency = <5000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ };
+};
diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi
index ee66ef6704..d78a53aeb7 100644
--- a/arch/arm/dts/ast2500.dtsi
+++ b/arch/arm/dts/ast2500.dtsi
@@ -57,23 +57,26 @@
ranges;
fmc: flash-controller@1e62 {
- reg = < 0x1e62 0xc4
- 0x2000 0x1000 >;
+ reg = <0x1e62 0xc4>, <0x2000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-fmc";
+ clocks = < ASPEED_CLK_AHB>;
+ num-cs = <3>;
status = "disabled";
- interrupts = <19>;
+
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
+
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
+
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
@@ -82,17 +85,20 @@
};
spi1: flash-controller@1e63 {
- reg = < 0x1e63 0xc4
- 0x3000 0x0800 >;
+ reg = <0x1e63 0xc4>, <0x3000 0x0800>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
+ clocks = < ASPEED_CLK_AHB>;
+ num-cs = <2>;
status = "disabled";
+
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
+
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
@@ -101,17 +107,20 @@
};
spi2: flash-controller@1e631000 {
- reg = < 0x1e631000 0xc4
- 0x3800 0x0800 >;
+ reg = <0x1e631000 0xc4>, <0x3800 0x0800>;
#address-cells = <1>;
#size-cells = <0>;
[v4 09/12] spi: aspeed: SPI dirmap read support
>From the HW point of view, the performance of
command read mode is greater than user mode slightly.
Thus, dirmap read framework is introduced to achieve
this goal.
In dirmap_create, a specific decoded address area with
flash size is assigned to each CS. CPU can thus access
the SPI flash as normal memory in dirmap_read function.
Signed-off-by: Chin-Ting Kuo
---
drivers/spi/spi-aspeed.c | 93
1 file changed, 93 insertions(+)
diff --git a/drivers/spi/spi-aspeed.c b/drivers/spi/spi-aspeed.c
index 9574aff793..e5e348eb7b 100644
--- a/drivers/spi/spi-aspeed.c
+++ b/drivers/spi/spi-aspeed.c
@@ -85,6 +85,8 @@ struct aspeed_spi_info {
static int aspeed_spi_trim_decoded_size(struct udevice *bus,
u32 decoded_sz_arr[]);
+static int aspeed_spi_decoded_range_config(struct udevice *bus,
+ u32 decoded_sz_arr[]);
static u32 aspeed_spi_get_io_mode(u32 bus_width)
{
@@ -509,6 +511,95 @@ static int aspeed_spi_exec_op_user_mode(struct spi_slave
*slave,
return 0;
}
+static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
+{
+ int ret = 0;
+ struct udevice *dev = desc->slave->dev;
+ struct udevice *bus = dev->parent;
+ struct aspeed_spi_plat *plat = dev_get_plat(bus);
+ struct aspeed_spi_priv *priv = dev_get_priv(bus);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+ const struct aspeed_spi_info *info = priv->info;
+ struct spi_mem_op op_tmpl = desc->info.op_tmpl;
+ u32 i;
+ u32 cs = slave_plat->cs;
+ u32 decoded_sz_arr[ASPEED_SPI_MAX_CS];
+ u32 reg_val;
+
+ if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) {
+ for (i = 0; i < priv->num_cs; i++) {
+ reg_val = readl(plat->ctrl_base +
+ REG_CE0_DECODED_ADDR_REG + i * 4);
+ decoded_sz_arr[i] =
+ info->segment_end(bus, reg_val) -
+ info->segment_start(bus, reg_val);
+ }
+
+ decoded_sz_arr[cs] = desc->info.length;
+
+ if (info->adjust_decoded_sz)
+ info->adjust_decoded_sz(bus, decoded_sz_arr);
+
+ for (i = 0; i < priv->num_cs; i++) {
+ dev_dbg(dev, "cs: %d, sz: 0x%x\n", i,
+ decoded_sz_arr[i]);
+ }
+
+ ret = aspeed_spi_decoded_range_config(bus, decoded_sz_arr);
+ if (ret)
+ return ret;
+
+ reg_val = readl(plat->ctrl_base + REG_CE0_CTRL_REG + cs * 4) &
+ (~info->cmd_io_ctrl_mask);
+ reg_val |= aspeed_spi_get_io_mode(op_tmpl.data.buswidth) |
+ op_tmpl.cmd.opcode << 16 |
+ ((op_tmpl.dummy.nbytes) & 0x3) << 6 |
+ ((op_tmpl.dummy.nbytes) & 0x4) << 14 |
+ CTRL_IO_MODE_CMD_READ;
+
+ writel(reg_val,
+ plat->ctrl_base + REG_CE0_CTRL_REG + cs * 4);
+ priv->flashes[cs].ce_ctrl_read = reg_val;
+
+ dev_dbg(dev, "read bus width: %d [0x%08x]\n",
+ op_tmpl.data.buswidth, priv->flashes[cs].ce_ctrl_read);
+ } else {
+ /*
+* dirmap_write is not supported currently due to a HW
+* limitation for command write mode: The written data
+* length should be multiple of 4-byte.
+*/
+ return -EOPNOTSUPP;
+ }
+
+ return ret;
+}
+
+static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
+ u64 offs, size_t len, void *buf)
+{
+ struct udevice *dev = desc->slave->dev;
+ struct aspeed_spi_priv *priv = dev_get_priv(dev->parent);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+ u32 cs = slave_plat->cs;
+ int ret;
+
+ dev_dbg(dev, "read op:0x%x, addr:0x%llx, len:0x%x\n",
+ desc->info.op_tmpl.cmd.opcode, offs, len);
+
+ if (priv->flashes[cs].ahb_win_sz < offs + len ||
+ (offs + len) % 4 != 0) {
+ ret = aspeed_spi_exec_op_user_mode(desc->slave,
+ >info.op_tmpl);
+ if (ret != 0)
+ return 0;
+ } else {
+ memcpy_fromio(buf, priv->flashes[cs].ahb_base + offs, len);
+ }
+
+ return len;
+}
+
static struct aspeed_spi_flash *aspeed_spi_get_flash(struct udevice *dev)
{
struct udevice *bus = dev->parent;
@@ -792,6 +883,8 @@ static int aspeed_spi_probe(struct udevice *bus)
static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
.supports_op = aspeed_spi_supports_op,
.exec_op =
[v4 07/12] spi-mem: Add dirmap API from Linux
This adds the dirmap API originally introduced in Linux commit aa167f3
("spi: spi-mem: Add a new API to support direct mapping"). This also
includes several follow-up patches and fixes.
Changes from Linux include:
* Added Kconfig option
* Changed struct device to struct udevice
* Changed struct spi_mem to struct spi_slave
This patch is obtained from the following patch
https://patchwork.ozlabs.org/project/uboot/patch/20210205043924.149504-3-sean...@gmail.com/
Signed-off-by: Chin-Ting Kuo
Signed-off-by: Sean Anderson
Acked-by: Pratyush Yadav
---
v2: Remove "#if CONFIG_SPI_DIRMAP" compile wrapper.
v3: Fix a grammatical error in spi-mem.h.
drivers/spi/Kconfig | 10 ++
drivers/spi/spi-mem.c | 268 ++
include/spi-mem.h | 79 +
3 files changed, 357 insertions(+)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a616294910..297253714a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -40,6 +40,16 @@ config SPI_MEM
This extension is meant to simplify interaction with SPI memories
by providing an high-level interface to send memory-like commands.
+config SPI_DIRMAP
+ bool "SPI direct mapping"
+ depends on SPI_MEM
+ help
+ Enable the SPI direct mapping API. Most modern SPI controllers can
+ directly map a SPI memory (or a portion of the SPI memory) in the CPU
+ address space. Most of the time this brings significant performance
+ improvements as it automates the whole process of sending SPI memory
+ operations every time a new region is accessed.
+
if DM_SPI
config ALTERA_SPI
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 9c1ede1b61..8e8995fc53 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -21,6 +21,8 @@
#include
#include
#include
+#include
+#include
#endif
#ifndef __UBOOT__
@@ -491,6 +493,272 @@ int spi_mem_adjust_op_size(struct spi_slave *slave,
struct spi_mem_op *op)
}
EXPORT_SYMBOL_GPL(spi_mem_adjust_op_size);
+static ssize_t spi_mem_no_dirmap_read(struct spi_mem_dirmap_desc *desc,
+ u64 offs, size_t len, void *buf)
+{
+ struct spi_mem_op op = desc->info.op_tmpl;
+ int ret;
+
+ op.addr.val = desc->info.offset + offs;
+ op.data.buf.in = buf;
+ op.data.nbytes = len;
+ ret = spi_mem_adjust_op_size(desc->slave, );
+ if (ret)
+ return ret;
+
+ ret = spi_mem_exec_op(desc->slave, );
+ if (ret)
+ return ret;
+
+ return op.data.nbytes;
+}
+
+static ssize_t spi_mem_no_dirmap_write(struct spi_mem_dirmap_desc *desc,
+ u64 offs, size_t len, const void *buf)
+{
+ struct spi_mem_op op = desc->info.op_tmpl;
+ int ret;
+
+ op.addr.val = desc->info.offset + offs;
+ op.data.buf.out = buf;
+ op.data.nbytes = len;
+ ret = spi_mem_adjust_op_size(desc->slave, );
+ if (ret)
+ return ret;
+
+ ret = spi_mem_exec_op(desc->slave, );
+ if (ret)
+ return ret;
+
+ return op.data.nbytes;
+}
+
+/**
+ * spi_mem_dirmap_create() - Create a direct mapping descriptor
+ * @mem: SPI mem device this direct mapping should be created for
+ * @info: direct mapping information
+ *
+ * This function is creating a direct mapping descriptor which can then be used
+ * to access the memory using spi_mem_dirmap_read() or spi_mem_dirmap_write().
+ * If the SPI controller driver does not support direct mapping, this function
+ * falls back to an implementation using spi_mem_exec_op(), so that the caller
+ * doesn't have to bother implementing a fallback on his own.
+ *
+ * Return: a valid pointer in case of success, and ERR_PTR() otherwise.
+ */
+struct spi_mem_dirmap_desc *
+spi_mem_dirmap_create(struct spi_slave *slave,
+ const struct spi_mem_dirmap_info *info)
+{
+ struct udevice *bus = slave->dev->parent;
+ struct dm_spi_ops *ops = spi_get_ops(bus);
+ struct spi_mem_dirmap_desc *desc;
+ int ret = -EOPNOTSUPP;
+
+ /* Make sure the number of address cycles is between 1 and 8 bytes. */
+ if (!info->op_tmpl.addr.nbytes || info->op_tmpl.addr.nbytes > 8)
+ return ERR_PTR(-EINVAL);
+
+ /* data.dir should either be SPI_MEM_DATA_IN or SPI_MEM_DATA_OUT. */
+ if (info->op_tmpl.data.dir == SPI_MEM_NO_DATA)
+ return ERR_PTR(-EINVAL);
+
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return ERR_PTR(-ENOMEM);
+
+ desc->slave = slave;
+ desc->info = *info;
+ if (ops->mem_ops && ops->mem_ops->dirmap_create)
+ ret = ops->mem_ops->dirmap_create(desc);
+
+ if (ret) {
+ desc->nodirmap = true;
+ if (!spi_mem_supports_op(desc->slave, >info.op_tmpl))
+ ret = -EOPNOTSUPP;
+ else
+
[v4 08/12] mtd: spi-nor: Use spi-mem dirmap API
This adds support for the dirmap API to the spi-nor subsystem, as
introduced in Linux commit df5c210 ("mtd: spi-nor: use spi-mem
dirmap API").
This patch is synchronize from the following patch
https://patchwork.ozlabs.org/project/uboot/patch/20210205043924.149504-4-sean...@gmail.com/
Signed-off-by: Chin-Ting Kuo
Signed-off-by: Sean Anderson
Acked-by: Pratyush Yadav
---
v2: Use "if (CONFIG_IS_ENABLED(SPI_DIRMAP))" to wrap
spi_dirmap related functions.
drivers/mtd/spi/sf_probe.c | 76 ++
drivers/mtd/spi/spi-nor-core.c | 55 +---
include/linux/mtd/spi-nor.h| 18
3 files changed, 133 insertions(+), 16 deletions(-)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index f461082e03..e192f97efd 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -10,13 +10,69 @@
#include
#include
#include
+#include
#include
#include
#include
#include
+#include
#include "sf_internal.h"
+static int spi_nor_create_read_dirmap(struct spi_nor *nor)
+{
+ struct spi_mem_dirmap_info info = {
+ .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
+ SPI_MEM_OP_ADDR(nor->addr_width, 0, 0),
+ SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
+ SPI_MEM_OP_DATA_IN(0, NULL, 0)),
+ .offset = 0,
+ .length = nor->mtd.size,
+ };
+ struct spi_mem_op *op = _tmpl;
+
+ /* get transfer protocols. */
+ spi_nor_setup_op(nor, op, nor->read_proto);
+ op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
+
+ /* convert the dummy cycles to the number of bytes */
+ op->dummy.nbytes = (nor->read_dummy * op->dummy.buswidth) / 8;
+ if (spi_nor_protocol_is_dtr(nor->read_proto))
+ op->dummy.nbytes *= 2;
+
+ nor->dirmap.rdesc = spi_mem_dirmap_create(nor->spi, );
+ if (IS_ERR(nor->dirmap.rdesc))
+ return PTR_ERR(nor->dirmap.rdesc);
+
+ return 0;
+}
+
+static int spi_nor_create_write_dirmap(struct spi_nor *nor)
+{
+ struct spi_mem_dirmap_info info = {
+ .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
+ SPI_MEM_OP_ADDR(nor->addr_width, 0, 0),
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_OUT(0, NULL, 0)),
+ .offset = 0,
+ .length = nor->mtd.size,
+ };
+ struct spi_mem_op *op = _tmpl;
+
+ /* get transfer protocols. */
+ spi_nor_setup_op(nor, op, nor->write_proto);
+ op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
+
+ if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
+ op->addr.nbytes = 0;
+
+ nor->dirmap.wdesc = spi_mem_dirmap_create(nor->spi, );
+ if (IS_ERR(nor->dirmap.wdesc))
+ return PTR_ERR(nor->dirmap.wdesc);
+
+ return 0;
+}
+
/**
* spi_flash_probe_slave() - Probe for a SPI flash device on a bus
*
@@ -45,6 +101,16 @@ static int spi_flash_probe_slave(struct spi_flash *flash)
if (ret)
goto err_read_id;
+ if (CONFIG_IS_ENABLED(SPI_DIRMAP)) {
+ ret = spi_nor_create_read_dirmap(flash);
+ if (ret)
+ return ret;
+
+ ret = spi_nor_create_write_dirmap(flash);
+ if (ret)
+ return ret;
+ }
+
if (CONFIG_IS_ENABLED(SPI_FLASH_MTD))
ret = spi_flash_mtd_register(flash);
@@ -83,6 +149,11 @@ struct spi_flash *spi_flash_probe(unsigned int busnum,
unsigned int cs,
void spi_flash_free(struct spi_flash *flash)
{
+ if (CONFIG_IS_ENABLED(SPI_DIRMAP)) {
+ spi_mem_dirmap_destroy(flash->dirmap.wdesc);
+ spi_mem_dirmap_destroy(flash->dirmap.rdesc);
+ }
+
if (CONFIG_IS_ENABLED(SPI_FLASH_MTD))
spi_flash_mtd_unregister(flash);
@@ -153,6 +224,11 @@ static int spi_flash_std_remove(struct udevice *dev)
struct spi_flash *flash = dev_get_uclass_priv(dev);
int ret;
+ if (CONFIG_IS_ENABLED(SPI_DIRMAP)) {
+ spi_mem_dirmap_destroy(flash->dirmap.wdesc);
+ spi_mem_dirmap_destroy(flash->dirmap.rdesc);
+ }
+
ret = spi_nor_remove(flash);
if (ret)
return ret;
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 3b7c817c02..0c6262b7fd 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -239,9 +239,9 @@ static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor,
* need to be initialized.
* @proto: the protocol from which the properties need to be set.
*/
-static void spi_nor_setup_op(const struct spi_nor
