Re: [PATCH 10/14] clk: scmi: support SCMI multi-channel
On 5/13/22 2:26 AM, Etienne Carriere wrote:
Update SCMI clock driver to get its assigned SCMI channel during
initialization. This change allows SCMI clock protocol to use a
dedicated channel when defined in the DT. The reference is saved
in SCMI clock driver private data.
Cc: Lukasz Majewski
Cc: Sean Anderson
Signed-off-by: Etienne Carriere
---
drivers/clk/clk_scmi.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c
index 0d0bb72eaf7..5cf7bd73df5 100644
--- a/drivers/clk/clk_scmi.c
+++ b/drivers/clk/clk_scmi.c
@@ -15,6 +15,7 @@
static int scmi_clk_get_num_clock(struct udevice *dev, size_t *num_clocks)
{
+ struct scmi_channel **scmi_channel_ref = dev_get_priv(dev);
struct scmi_clk_protocol_attr_out out;
struct scmi_msg msg = {
.protocol_id = SCMI_PROTOCOL_ID_CLOCK,
@@ -24,7 +25,7 @@ static int scmi_clk_get_num_clock(struct udevice *dev, size_t
*num_clocks)
};
int ret;
- ret = devm_scmi_process_msg(dev, NULL, );
+ ret = devm_scmi_process_msg(dev, *scmi_channel_ref, );
if (ret)
return ret;
@@ -35,6 +36,7 @@ static int scmi_clk_get_num_clock(struct udevice *dev, size_t *num_clocks)
static int scmi_clk_get_attibute(struct udevice *dev, int clkid, char **name)
{
+ struct scmi_channel **scmi_channel_ref = dev_get_priv(dev);
struct scmi_clk_attribute_in in = {
.clock_id = clkid,
};
@@ -49,7 +51,7 @@ static int scmi_clk_get_attibute(struct udevice *dev, int
clkid, char **name)
};
int ret;
- ret = devm_scmi_process_msg(dev, NULL, );
+ ret = devm_scmi_process_msg(dev, *scmi_channel_ref, );
if (ret)
return ret;
@@ -60,6 +62,7 @@ static int scmi_clk_get_attibute(struct udevice *dev, int clkid, char **name)
static int scmi_clk_gate(struct clk *clk, int enable)
{
+ struct scmi_channel **scmi_channel_ref = dev_get_priv(clk->dev);
struct scmi_clk_state_in in = {
.clock_id = clk->id,
.attributes = enable,
@@ -70,7 +73,7 @@ static int scmi_clk_gate(struct clk *clk, int enable)
in, out);
int ret;
- ret = devm_scmi_process_msg(clk->dev, NULL, );
+ ret = devm_scmi_process_msg(clk->dev, *scmi_channel_ref, );
if (ret)
return ret;
@@ -89,6 +92,7 @@ static int scmi_clk_disable(struct clk *clk)
static ulong scmi_clk_get_rate(struct clk *clk)
{
+ struct scmi_channel **scmi_channel_ref = dev_get_priv(clk->dev);
struct scmi_clk_rate_get_in in = {
.clock_id = clk->id,
};
@@ -98,7 +102,7 @@ static ulong scmi_clk_get_rate(struct clk *clk)
in, out);
int ret;
- ret = devm_scmi_process_msg(clk->dev, NULL, );
+ ret = devm_scmi_process_msg(clk->dev, *scmi_channel_ref, );
if (ret < 0)
return ret;
@@ -111,6 +115,7 @@ static ulong scmi_clk_get_rate(struct clk *clk)
static ulong scmi_clk_set_rate(struct clk *clk, ulong rate)
{
+ struct scmi_channel **scmi_channel_ref = dev_get_priv(clk->dev);
struct scmi_clk_rate_set_in in = {
.clock_id = clk->id,
.flags = SCMI_CLK_RATE_ROUND_CLOSEST,
@@ -123,7 +128,7 @@ static ulong scmi_clk_set_rate(struct clk *clk, ulong rate)
in, out);
int ret;
- ret = devm_scmi_process_msg(clk->dev, NULL, );
+ ret = devm_scmi_process_msg(clk->dev, *scmi_channel_ref, );
if (ret < 0)
return ret;
@@ -136,10 +141,15 @@ static ulong scmi_clk_set_rate(struct clk *clk, ulong rate)
static int scmi_clk_probe(struct udevice *dev)
{
+ struct scmi_channel **scmi_channel_ref = dev_get_priv(dev);
struct clk *clk;
size_t num_clocks, i;
int ret;
+ ret = devm_scmi_of_get_channel(dev, scmi_channel_ref);
+ if (ret)
+ return ret;
+
if (!CONFIG_IS_ENABLED(CLK_CCF))
return 0;
@@ -186,5 +196,6 @@ U_BOOT_DRIVER(scmi_clock) = {
.name = "scmi_clk",
.id = UCLASS_CLK,
.ops = _clk_ops,
- .probe = _clk_probe,
+ .probe = scmi_clk_probe,
+ .priv_auto = sizeof(struct scmi_channel *),
Please create a priv struct to hold this. E.g.
/**
* struct scmi_clk_priv - Private data for SCMI clocks
* @channel: ...
*/
struct scmi_clk_priv {
struct scmi_channel *channel;
};
This will allow for easier refactoring if it is necessary to add additional
per-device data in the future.
--Sean
Re: [PATCH v6] pinctrl: nuvoton: Add NPCM8xx pinctrl driver
On 5/3/22 1:33 AM, Stanley Chu wrote: Add Nuvoton BMC NPCM845 Pinmux and Pinconf support. Signed-off-by: Stanley Chu --- v6: - sync pin name with Linux driver - add support for gpi35/gpi36/gpio183~189 v5: - lower-case hex consistently - use uint type for pin list in the group_config struct v4: - correct the pin flags, add slew rate control suuport for rgmii pins v3: - separate group names and function names in different tables to allow for adding additional functions v2: - drop the WDnRCRB/CORSTCB register access, it is not for GPIO modules reset control --- drivers/pinctrl/Kconfig |1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/nuvoton/Kconfig | 12 + drivers/pinctrl/nuvoton/Makefile |1 + drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 1225 + 5 files changed, 1240 insertions(+) create mode 100644 drivers/pinctrl/nuvoton/Kconfig create mode 100644 drivers/pinctrl/nuvoton/Makefile create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 13033198f9..e14e885c3e 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -339,6 +339,7 @@ source "drivers/pinctrl/mscc/Kconfig" source "drivers/pinctrl/mtmips/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/nexell/Kconfig" +source "drivers/pinctrl/nuvoton/Kconfig" source "drivers/pinctrl/nxp/Kconfig" source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/rockchip/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 9b4978253b..aa31f31c16 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_ATH79) += ath79/ obj-$(CONFIG_PINCTRL_INTEL) += intel/ obj-$(CONFIG_ARCH_MTMIPS) += mtmips/ +obj-$(CONFIG_ARCH_NPCM) += nuvoton/ obj-$(CONFIG_ARCH_RMOBILE) += renesas/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig new file mode 100644 index 00..519539d6ae --- /dev/null +++ b/drivers/pinctrl/nuvoton/Kconfig @@ -0,0 +1,12 @@ +config PINCTRL_NPCM8XX + bool "Pinctrl driver for Nuvoton NPCM8XX" + depends on DM && PINCTRL_GENERIC && ARCH_NPCM8XX + help + Support pin muxing and pin configuration on + Nuvoton NPCM8XX SoC. + + The NPCM8XX contains 256 GPIO pins. Most of them are + multiplexed with other system functions. These pins can + be configured as either GPIO pin or alternate function. + It also supports basic configurations such as pull up/down, + drive-strength, and slew rate control for some of the pins. diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile new file mode 100644 index 00..a6dfdf3672 --- /dev/null +++ b/drivers/pinctrl/nuvoton/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_PINCTRL_NPCM8XX) += pinctrl-npcm8xx.o diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c new file mode 100644 index 00..cc49310506 --- /dev/null +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -0,0 +1,1225 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Nuvoton Technology Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* GCR register offsets */ +#define WD0RCR 0x38 +#define WD1RCR 0x3c +#define WD2RCR 0x40 +#define SWRSTC10x44 +#define SWRSTC20x48 +#define SWRSTC30x4c +#define SWRSTC40x50 +#define CORSTC 0x5c +#define FLOCKR10x74 +#define INTCR4 0xc0 +#define I2CSEGSEL 0xe0 +#define MFSEL1 0x260 +#define MFSEL2 0x264 +#define MFSEL3 0x268 +#define MFSEL4 0x26c +#define MFSEL5 0x270 +#define MFSEL6 0x274 +#define MFSEL7 0x278 + +/* GPIO register offsets */ +#define GPIO_POL 0x08 /* Polarity */ +#define GPIO_DOUT 0x0c /* Data OUT */ +#define GPIO_OTYP 0x14 /* Output Type */ +#define GPIO_PU0x1c /* Pull-up */ +#define GPIO_PD0x20 /* Pull-down */ +#define GPIO_DBNC 0x24 /* Debounce */ +#define GPIO_EVEN 0x40 /* Event Enable */ +#define GPIO_EVST 0x4c /* Event Status */ +#define GPIO_IEM 0x58 /* Input Enable */ +#define GPIO_OSRC 0x5c /* Output Slew-Rate Control */ +#define GPIO_ODSC 0x60 /* Output Drive Strength Control */ +#define GPIO_OES 0x70 /* Output Enable Set */ +#define GPIO_OEC 0x74 /* Output Enable Clear */ + +#define NPCM8XX_GPIO_PER_BANK 32 +#define GPIOX_OFFSET 16 + +/* The lists contain alternate GPIO pins of the function */ +/* Serial Interfaces */ +static
Re: imx8mm eLCDIF clock
On 4/22/22 2:39 AM, Tommaso Merciai wrote: On Thu, Apr 21, 2022 at 08:09:59PM -0400, Sean Anderson wrote: On 4/21/22 2:48 AM, Tommaso Merciai wrote: Hi, I'm working on drivers/clk/imx/clk-imx8mm.c to port and bring up eLCDIF clocks. After port all necessary clocks needed by eLCDIF I found that IMX8MM_VIDEO_PLL1 clock is not enabled and need the following code to enable it at the end of the clk-imx8mm probe: struct clk *clkp; clk_get_by_id(IMX8MM_VIDEO_PLL1, ); clk_set_rate(clkp, 59400UL); clk_enable(clkp); What do you think about this solution? There is a more standard way to do this? PLL1 should be a parent of one of the clocks required by the eLCDIF. That clock should call clk_enable() on PLL1 when it is enabled itself. If you want to set a specific rate, you can do that with assigned-clock-rates in either the clock's DT node, or the eLCDIF's DT node. Hi Sean, Thanks for your suggestion, I need only to enable it, I have already assign the right rate from dts. The doubt at this point is: it's right call clk_enable from clk-imx8mm.c? I think yes because it handle by "fsl,imx8mm-ccm" driver, maybe protected by CONFIG_DM_VIDEO could be a good solution. Let me know. I don't think so. Generally whatever uses the clock (e.g. your video driver) will call clk_enable, and CCF should propegate that enable up the clock tree. --Sean
[PATCH] doc: sandbox: Add additional valgrind documentation
This document some additional options which can be used with valgrind, as well as directions for future work. It also fixes up inline literals to actually be inline literals (and not italics). The content of this documentation is primarily adapted from [1]. [1] https://lore.kernel.org/u-boot/57cb4b49-fa30-1194-9ac3-faa53e803...@gmail.com/ Signed-off-by: Sean Anderson --- doc/arch/sandbox.rst | 65 +--- 1 file changed, 61 insertions(+), 4 deletions(-) diff --git a/doc/arch/sandbox.rst b/doc/arch/sandbox.rst index e1119492b4..cd5090be71 100644 --- a/doc/arch/sandbox.rst +++ b/doc/arch/sandbox.rst @@ -479,19 +479,76 @@ It is possible to run U-Boot under valgrind to check memory allocations:: valgrind ./u-boot -For more detailed results, enable `CONFIG_VALGRIND`. There are many false -positives due to `malloc` itself. Suppress these with:: +For more detailed results, enable ``CONFIG_VALGRIND``. There are many false +positives due to ``malloc`` itself. Suppress these with:: valgrind --suppressions=scripts/u-boot.supp ./u-boot If you are running sandbox SPL or TPL, then valgrind will not by default notice when U-Boot jumps from TPL to SPL, or from SPL to U-Boot proper. To -fix this, use `--trace-children=yes`. To show who alloc'd some troublesome -memory, use `--track-origins=yes`. To uncover possible errors, try running all +fix this, use ``--trace-children=yes``. To show who alloc'd some troublesome +memory, use ``--track-origins=yes``. To uncover possible errors, try running all unit tests with:: valgrind --track-origins=yes --suppressions=scripts/u-boot.supp ./u-boot -Tc 'ut all' +Additional options +^^ + +The following options are useful in addition to the above examples: + +* ``--error-limit=no`` will enable printing more than 1000 errors in a + single session. +* ``--vgdb=yes --vgdb-error=0`` will let you use gdb to attach like:: + +gdb -ex "target remote | vgdb" u-boot + + This is very helpful for inspecting the program state when there is + an error. +* Passing ``-t cooked`` to U-Boot will keep the console in a sane state if you + terminate it early (instead of having to run tset). + +Future work +^^^ + +The biggest limitation to the current approach is that +supressions don't "un-taint" uninitialized memory accesses. Currently, I +have dlmalloc's reads its bookkeeping information marked as a "red +zone." This means that all reads to it are marked as illegal by +valgrind. This is fine for regular code, but dlmalloc really does need +to access this area, so we suppress its violations. However, if dlmalloc +then passes a result calculated from a "tainted" access, that result is +still tainted. So the first accessor will raise a warning. This means +that every construct like + +.. code-block:: + +foo = malloc(sizeof(*foo)); +if (!foo) +return -ENOMEM; + +will raise a warning when we check the result of malloc. Whoops. + +There are three ways (as I see it) to address this: + +* Don't mark dlmalloc bookkeeping information as a red zone. This is the + simplest solution, but reduces the power of valgrind immensely, since + we can no longer determine that (e.g.) access past the end of an array + is undefined. +* Implement red zones properly. This would involve growing every + allocation by a fixed amount (16 bytes or so) and then using that + extra space for a real red zone that neither regular code nor dlmalloc + needs to access. Unfortunately, this would probably some fairly + intensive surgery to dlmalloc to add/remove the offset appropriately. +* Mark bookkeeping information as valid before we use it in dlmalloc, + and then mark it invalid before returning. This would be the most + correct, but it would be very tricky to implement since there are so + many code paths to mark. I think it would be the most effort out of + the three options here. + +Until one of the above options are implemented, it will remain difficult +to sift through the massive amount of spurious warnings. + Testing --- -- 2.35.1
[PULL] u-boot-riscv/master
Hi Tom, The following changes since commit 7e0edcadb09d55d5319fdc862041fd1b874476f5: Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-05-24 23:29:00 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to c544b281cd3e549a4fcbf4ba9a05a5d72c9557dd: riscv: qemu: Set kernel_comp_addr_r for compressed kernel (2022-05-26 18:42:34 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/12131 Bin Meng (3): riscv: sifive: unmatched: Adjust for big ramdisk image riscv: sifive: unleashed: Set kernel_comp_addr_r for compressed kernel riscv: qemu: Set kernel_comp_addr_r for compressed kernel Heinrich Schuchardt (1): cmd/sbi: add implementation ID 6 - Coffer Leo Yu-Chi Liang (1): riscv: Clean up asm/io.h Michal Simek (1): riscv: remove CONFIG_ARCH_MAP_SYSMEM from io.h Rick Chen (2): riscv: ae350: Fix OF_BOARD boot failure riscv: ae350: Fix OF_BOARD boot failure arch/riscv/include/asm/io.h | 138 --- board/AndesTech/ax25-ae350/Kconfig | 1 + cmd/riscv/sbi.c | 1 + configs/ae350_rv32_spl_defconfig | 1 + configs/ae350_rv32_spl_xip_defconfig | 1 + configs/ae350_rv64_spl_defconfig | 1 + configs/ae350_rv64_spl_xip_defconfig | 1 + doc/board/sifive/unleashed.rst | 2 - include/configs/qemu-riscv.h | 10 ++- include/configs/sifive-unleashed.h | 10 ++- include/configs/sifive-unmatched.h | 10 +-- 11 files changed, 23 insertions(+), 153 deletions(-) Best regards, Leo
Re: [PATCH 2/2] mmc: fsl_esdhc_imx: Implement wait_dat0 mmc ops
On 5/26/22 23:37, Loic Poulain wrote:
> Implement wait_dat0 mmc ops callbac, allowing to reduce SPL boot time.
>
> Before (using grabserial):
> [0.01 0.01] U-Boot SPL 2021.04-
> [0.028257 0.028257] DDRINFO: start DRAM init
> [0.028500 0.000243] DDRINFO: DRAM rate 3000MTS
> [0.304627 0.276127] DDRINFO:ddrphy calibration done
> [0.305647 0.001020] DDRINFO: ddrmix config done
> [0.352584 0.046937] SEC0: RNG instantiated
> [0.374299 0.021715] Normal Boot
> [0.374675 0.000376] Trying to boot from MMC2
> [1.250580 0.875905] NOTICE: BL31: v2.4(release):lf-5.10.72-2.2.0-0-g5782363f9
> [1.251985 0.001405] NOTICE: BL31: Built : 08:02:40, Apr 12 2022
> [1.522560 0.270575]
> [1.522734 0.000174]
> [1.522788 0.54] U-Boot 2021.04-
>
> After:
> [0.01 0.01] U-Boot SPL 2021.04-
> [0.001614 0.001614] DDRINFO: start DRAM init
> [0.002377 0.000763] DDRINFO: DRAM rate 3000MTS
> [0.278494 0.276117] DDRINFO:ddrphy calibration done
> [0.279266 0.000772] DDRINFO: ddrmix config done
> [0.338432 0.059166] SEC0: RNG instantiated
> [0.339051 0.000619] Normal Boot
> [0.339431 0.000380] Trying to boot from MMC2
> [0.412587 0.073156] NOTICE: BL31: v2.4(release):lf-5.15.5-1.0.0-0-g05f788b
> [0.414191 0.001604] NOTICE: BL31: Built : 10:35:26, Apr 6 2022
> [0.700685 0.286494]
> [0.700793 0.000108]
> [0.700845 0.52] U-Boot 2021.04-
>
> Signed-off-by: Loic Poulain
Reviewed-by: Jaehoon Chung
Best Regards,
Jaehoon Chung
> ---
> drivers/mmc/fsl_esdhc_imx.c | 50
> ++---
> 1 file changed, 33 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
> index 02208a5..ec52f93 100644
> --- a/drivers/mmc/fsl_esdhc_imx.c
> +++ b/drivers/mmc/fsl_esdhc_imx.c
> @@ -1060,6 +1060,30 @@ static int esdhc_getcd_common(struct fsl_esdhc_priv
> *priv)
> return timeout > 0;
> }
>
> +static int esdhc_wait_dat0_common(struct fsl_esdhc_priv *priv, int state,
> + int timeout_us)
> +{
> + struct fsl_esdhc *regs = priv->esdhc_regs;
> + int ret, err;
> + u32 tmp;
> +
> + /* make sure the card clock keep on */
> + esdhc_setbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
> +
> + ret = readx_poll_timeout(esdhc_read32, >prsstat, tmp,
> + !!(tmp & PRSSTAT_DAT0) == !!state,
> + timeout_us);
> +
> + /* change to default setting, let host control the card clock */
> + esdhc_clrbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
> +
> + err = readx_poll_timeout(esdhc_read32, >prsstat, tmp, tmp &
> PRSSTAT_SDOFF, 100);
> + if (err)
> + pr_warn("card clock not gate off as expect.\n");
> +
> + return ret;
> +}
> +
> static int esdhc_reset(struct fsl_esdhc *regs)
> {
> ulong start;
> @@ -1109,11 +1133,19 @@ static int esdhc_set_ios(struct mmc *mmc)
> return esdhc_set_ios_common(priv, mmc);
> }
>
> +static int esdhc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
> +{
> + struct fsl_esdhc_priv *priv = mmc->priv;
> +
> + return esdhc_wait_dat0_common(priv, state, timeout_us);
> +}
> +
> static const struct mmc_ops esdhc_ops = {
> .getcd = esdhc_getcd,
> .init = esdhc_init,
> .send_cmd = esdhc_send_cmd,
> .set_ios= esdhc_set_ios,
> + .wait_dat0 = esdhc_wait_dat0,
> };
> #endif
>
> @@ -1576,25 +1608,9 @@ static int __maybe_unused
> fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
> static int fsl_esdhc_wait_dat0(struct udevice *dev, int state,
> int timeout_us)
> {
> - int ret, err;
> - u32 tmp;
> struct fsl_esdhc_priv *priv = dev_get_priv(dev);
> - struct fsl_esdhc *regs = priv->esdhc_regs;
>
> - /* make sure the card clock keep on */
> - esdhc_setbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
> -
> - ret = readx_poll_timeout(esdhc_read32, >prsstat, tmp,
> - !!(tmp & PRSSTAT_DAT0) == !!state,
> - timeout_us);
> -
> - /* change to default setting, let host control the card clock */
> - esdhc_clrbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
> - err = readx_poll_timeout(esdhc_read32, >prsstat, tmp, tmp &
> PRSSTAT_SDOFF, 100);
> - if (err)
> - dev_warn(dev, "card clock not gate off as expect.\n");
> -
> - return ret;
> + return esdhc_wait_dat0_common(priv, state, timeout_us);
> }
>
> static const struct dm_mmc_ops fsl_esdhc_ops = {
Re: [PATCH 1/2] mmc: Add support for wait_dat0 callback
On 5/26/22 23:37, Loic Poulain wrote:
> There is no wait_dat0 mmc ops, causing operations waiting for data
> line state change (e.g mmc_switch_voltage) to fallback to a 250ms
> active delay. mmc_ops still used when DM_MMC is not enabled, which
> is often the case for SPL. The result can be unexpectly long SPL
> boot time.
>
> This change adds support for wait_dat0() mmc operation.
>
> Signed-off-by: Loic Poulain
Reviewed-by: Jaehoon Chung
Best Regards,
Jaehoon Chung
> ---
> drivers/mmc/mmc.c | 3 +++
> include/mmc.h | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
> index f6ccd83..109f340 100644
> --- a/drivers/mmc/mmc.c
> +++ b/drivers/mmc/mmc.c
> @@ -34,6 +34,9 @@ static int mmc_set_signal_voltage(struct mmc *mmc, uint
> signal_voltage);
>
> static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
> {
> + if (mmc->cfg->ops->wait_dat0)
> + return mmc->cfg->ops->wait_dat0(mmc, state, timeout_us);
> +
> return -ENOSYS;
> }
>
> diff --git a/include/mmc.h b/include/mmc.h
> index 6bdcce8..b7e94e8 100644
> --- a/include/mmc.h
> +++ b/include/mmc.h
> @@ -561,6 +561,7 @@ struct mmc_ops {
> int (*getwp)(struct mmc *mmc);
> int (*host_power_cycle)(struct mmc *mmc);
> int (*get_b_max)(struct mmc *mmc, void *dst, lbaint_t blkcnt);
> + int (*wait_dat0)(struct mmc *mmc, int state, int timeout_us);
> };
>
> static inline int mmc_hs400_prepare_ddr(struct mmc *mmc)
[PATCH v1 9/9] MAINTAINERS: Introduce HPE GXP Architecture
From: Nick Hawkins Create a section in MAINTAINERS for the GXP HPE architecture Signed-off-by: Nick Hawkins --- MAINTAINERS | 12 1 file changed, 12 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 56be0bfad0..4417092f2d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -257,6 +257,18 @@ F: arch/arm/cpu/armv8/hisilicon F: arch/arm/include/asm/arch-hi6220/ F: arch/arm/include/asm/arch-hi3660/ +ARM HPE GXP ARCHITECTURE +M: Jean-Marie Verdun +M: Nick Hawkins +S: Maintained +F: arch/arm/dts/hpe-bmc* +F: arch/arm/dts/hpe-gxp* +F: arch/arm/mach-hpe/ +F: board/hpe/ +F: doc/device-tree-bindings/arm/hpe,gxp.yaml +F: doc/device-tree-bindings/timer/hpe,gxp-timer.yaml +F: drivers/timer/gxp-timer.c + ARM IPQ40XX M: Robert Marko M: Luka Kovacic -- 2.17.1
[PATCH v1 6/9] ARM: dts: Add device tree files for hpe gxp soc
From: Nick Hawkins
The HPE SoC is new to linux. A basic device tree layout with minimum
required for linux to boot including a timer and watchdog support has
been created.
The dts file is empty at this point but will be updated in subsequent
updates as board specific features are enabled.
Signed-off-by: Nick Hawkins
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/hpe-bmc-dl360gen10.dts | 26
arch/arm/dts/hpe-gxp.dtsi | 95 +
3 files changed, 123 insertions(+)
create mode 100644 arch/arm/dts/hpe-bmc-dl360gen10.dts
create mode 100644 arch/arm/dts/hpe-gxp.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 83630af4f6..6223998eb7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1213,6 +1213,8 @@ dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
+dtb-$(CONFIG_TARGET_GXP) += hpe-bmc-dl360gen10.dts
+
dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb \
imx8mm-cl-iot-gate-ied.dtbo \
imx8mm-cl-iot-gate-ied-adc0.dtbo \
diff --git a/arch/arm/dts/hpe-bmc-dl360gen10.dts
b/arch/arm/dts/hpe-bmc-dl360gen10.dts
new file mode 100644
index 00..3a7382ce40
--- /dev/null
+++ b/arch/arm/dts/hpe-bmc-dl360gen10.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for HPE DL360Gen10
+ */
+
+/include/ "hpe-gxp.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "hpe,gxp-dl360gen10", "hpe,gxp";
+ model = "Hewlett Packard Enterprise ProLiant dl360 Gen10";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x4000 0x2000>;
+ };
+};
diff --git a/arch/arm/dts/hpe-gxp.dtsi b/arch/arm/dts/hpe-gxp.dtsi
new file mode 100644
index 00..fbf817ee04
--- /dev/null
+++ b/arch/arm/dts/hpe-gxp.dtsi
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for HPE GXP
+ */
+
+/dts-v1/;
+/ {
+ model = "Hewlett Packard Enterprise GXP BMC";
+ compatible = "hpe,gxp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ device_type = "cpu";
+ next-level-cache = <>;
+ };
+ };
+
+ clocks {
+ pll: clock-0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <16>;
+ };
+
+ iopclk: clock-1 {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ clocks = <>;
+ };
+ };
+
+ axi {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ dma-ranges;
+
+ L2: cache-controller@b004 {
+ compatible = "arm,pl310-cache";
+ reg = <0xb004 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ ahb@c000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc000 0x3000>;
+ dma-ranges;
+
+ vic0: interrupt-controller@eff {
+ compatible = "arm,pl192-vic";
+ reg = <0xeff 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ vic1: interrupt-controller@80f0 {
+ compatible = "arm,pl192-vic";
+ reg = <0x80f0 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ uartc: serial@f0 {
+ compatible = "ns16550a";
+ reg = <0xf0 0x8>;
+ interrupts = <19>;
+ interrupt-parent = <>;
+ clock-frequency = <1846153>;
+ reg-shift = <0>;
+ };
+
+
[PATCH v1 8/9] configs: gxp: add gxp_defconfig
From: Nick Hawkins This is the initial very basic config that enables the U-Boot console on the hpe gxp soc. Signed-off-by: Nick Hawkins --- configs/gxp_defconfig | 48 +++ 1 file changed, 48 insertions(+) create mode 100644 configs/gxp_defconfig diff --git a/configs/gxp_defconfig b/configs/gxp_defconfig new file mode 100644 index 00..2d45fd694b --- /dev/null +++ b/configs/gxp_defconfig @@ -0,0 +1,48 @@ +CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y +CONFIG_ARCH_GXP=y +CONFIG_SYS_MALLOC_LEN=0x400 +CONFIG_GXP_VROM_64MB=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x1 +CONFIG_ENV_OFFSET=0x6 +CONFIG_ENV_SECT_SIZE=0x1 +CONFIG_DEFAULT_DEVICE_TREE="hpe-bmc-dl360gen10" +CONFIG_ENV_OFFSET_REDUND=0x7 +CONFIG_SYS_LOAD_ADDR=0x4010 +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_BOOTDELAY=5 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlyprintk console=ttyS2,115200 user_debug=31" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="gxp# " +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +CONFIG_CMD_MISC=y +CONFIG_CMD_USB=y +CONFIG_CMD_FAT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_NETCONSOLE=y +CONFIG_MISC=y +CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0 +# CONFIG_MMC is not set +# CONFIG_POWER is not set +CONFIG_RAM=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_TIMER=y +CONFIG_GXP_TIMER=y +CONFIG_LMB = y -- 2.17.1
[PATCH v1 7/9] configs: gxp: add core support
From: Nick Hawkins Add the include file for the gxp soc. Signed-off-by: Nick Hawkins --- include/configs/gxp.h | 96 +++ 1 file changed, 96 insertions(+) create mode 100644 include/configs/gxp.h diff --git a/include/configs/gxp.h b/include/configs/gxp.h new file mode 100644 index 00..601d6e405d --- /dev/null +++ b/include/configs/gxp.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * GXP board + * + * (C) Copyright 2022 Hewlett Packard Enterprise Development LP. + * Author: Nick Hawkins + * Author: Jean-Marie Verdun + */ + +#ifndef _GXP_H_ +#define _GXP_H_ + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_MALLOC_LEN 0x400 +#define CONFIG_SYS_INIT_SP_ADDR 0x200 + +#ifdef CONFIG_TARGET_GXP +#ifdef CONFIG_GXP_ECC +#define CONFIG_SYS_SDRAM_SIZE 0x0f80 +#else +#define CONFIG_SYS_SDRAM_SIZE 0x1f00 +#endif + +#ifdef CONFIG_GXP_VROM_64MB +#undef CONFIG_SYS_SDRAM_SIZE +#ifdef CONFIG_GXP_ECC + #define CONFIG_SYS_SDRAM_SIZE 0x0c00 +#else + #define CONFIG_SYS_SDRAM_SIZE 0x1800 +#endif +#endif + +#ifdef CONFIG_GXP_VROM_32MB +#undef CONFIG_SYS_SDRAM_SIZE +#ifdef CONFIG_GXP_ECC + #define CONFIG_SYS_SDRAM_SIZE 0x0e00 +#else + #define CONFIG_SYS_SDRAM_SIZE 0x1c00 +#endif +#endif +#endif + +#ifdef CONFIG_TARGET_GXP2 +#define CONFIG_SYS_SDRAM_SIZE 0x1b20 + +#ifdef CONFIG_GXP_VROM_64MB +#undef CONFIG_SYS_SDRAM_SIZE +#define CONFIG_SYS_SDRAM_SIZE 0x1400 +#endif + +#ifdef CONFIG_GXP_VROM_32MB +#undef CONFIG_SYS_SDRAM_SIZE +#define CONFIG_SYS_SDRAM_SIZE 0x1800 +#endif +#endif + +#define CONFIG_SYS_SDRAM_BASE 0x4000 +#define CONFIG_SYS_LOAD_ADDR0x4010 +#define CONFIG_BOOTCOMMAND "run spiboot" +//#define CONFIG_SYS_BOOTM_LEN0xC0 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "recover_file=openbmc-hpe-recovery-image.mtd\0" \ + "recover_cmd=usb start; " \ + "mw.b 0xD10D 0x40; " \ + "if fatload usb 0 0x5000 $recover_file 0x4C 0x8; then " \ + "setenv bootargs console=ttyS0,115200 recovery; " \ + "setenv force_recovery; " \ + "saveenv; " \ + "bootm 0x5000; " \ + "else " \ + "while itest 0 < 1; do " \ + "mw.b 0xd105 0xc0; " \ + "sleep .1; " \ + "mw.b 0xd105 0x00; " \ + "sleep .1; " \ + "done; " \ + "fi; " \ + "reset;\0" \ + "spiboot=if itest.b *0xD1B2 == 6; then " \ + "run recover_cmd;" \ + "fi;" \ + "if printenv force_recovery; then " \ + "run recover_cmd; " \ + "else " \ + "bootm 0xfc08; " \ + "run recover_cmd; " \ + "fi;\0" + +/*--*/ +/* Network Configuration */ +/*--*/ +#define CONFIG_PHY_ADDR 0 + +#endif -- 2.17.1
[PATCH v1 4/9] dt-bindings: arm: hpe: add GXP Support
From: Nick Hawkins Add support for HPE GXP. The GXP is based on the cortex a9 processor and supports arm7. Signed-off-by: Nick Hawkins --- doc/device-tree-bindings/arm/hpe,gxp.yaml | 27 +++ 1 file changed, 27 insertions(+) create mode 100644 doc/device-tree-bindings/arm/hpe,gxp.yaml diff --git a/doc/device-tree-bindings/arm/hpe,gxp.yaml b/doc/device-tree-bindings/arm/hpe,gxp.yaml new file mode 100644 index 00..224bbcb93f --- /dev/null +++ b/doc/device-tree-bindings/arm/hpe,gxp.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hpe,gxp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HPE BMC GXP platforms + +maintainers: + - Nick Hawkins + - Jean-Marie Verdun + +properties: + compatible: +oneOf: + - description: GXP Based Boards +items: + - enum: + - hpe,gxp-dl360gen10 + - const: hpe,gxp + +required: + - compatible + +additionalProperties: true + +... -- 2.17.1
[PATCH v1 5/9] dt-bindings: timer: Add hpe gxp timer
From: Nick Hawkins
Add support for the HPE GXP Timer. There are multiple
timers on the SoC but only one is enabled at this time.
Signed-off-by: Nick Hawkins
---
.../timer/hpe,gxp-timer.yaml | 47 +++
1 file changed, 47 insertions(+)
create mode 100644 doc/device-tree-bindings/timer/hpe,gxp-timer.yaml
diff --git a/doc/device-tree-bindings/timer/hpe,gxp-timer.yaml
b/doc/device-tree-bindings/timer/hpe,gxp-timer.yaml
new file mode 100644
index 00..d33d90f44d
--- /dev/null
+++ b/doc/device-tree-bindings/timer/hpe,gxp-timer.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/hpe,gxp-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HPE GXP Timer
+
+maintainers:
+ - Nick Hawkins
+ - Jean-Marie Verdun
+
+properties:
+ compatible:
+const: hpe,gxp-timer
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+maxItems: 1
+
+ clock-names:
+const: iop
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+timer@c000 {
+compatible = "hpe,gxp-timer";
+reg = <0x80 0x16>;
+interrupts = <0>;
+interrupt-parent = <>;
+clocks = <>;
+clock-names = "iop";
+};
--
2.17.1
[PATCH v1 3/9] board: hpe: gxp: add HPE GXP soc support
From: Nick Hawkins
Add basic support for the HPE GXP SoC. Reset the EHCI controller at
boot.
Signed-off-by: Nick Hawkins
---
board/hpe/gxp/Kconfig | 47 +++
board/hpe/gxp/Makefile| 1 +
board/hpe/gxp/gxp_board.c | 33 +++
3 files changed, 81 insertions(+)
create mode 100644 board/hpe/gxp/Kconfig
create mode 100644 board/hpe/gxp/Makefile
create mode 100644 board/hpe/gxp/gxp_board.c
diff --git a/board/hpe/gxp/Kconfig b/board/hpe/gxp/Kconfig
new file mode 100644
index 00..5fea1a6a0d
--- /dev/null
+++ b/board/hpe/gxp/Kconfig
@@ -0,0 +1,47 @@
+choice
+ prompt "SoC select"
+
+config TARGET_GXP
+ bool "GXP"
+ select DM
+ select SOC_GXP
+ imply CMD_DM
+
+config TARGET_GXP2
+ bool "GXP2"
+ select DM
+ select SOC_GXP
+ select GXP_ECC
+ imply CMD_DM
+
+endchoice
+
+choice
+ prompt "GXP VROM size"
+ default GXP_VROM_64MB
+ optional
+
+config GXP_VROM_64MB
+ bool "64MB"
+
+config GXP_VROM_32MB
+ bool "32MB"
+endchoice
+
+config GXP_ECC
+ default n
+ bool "Enable memory ECC protected"
+ help
+ Use half of memory to enable ECC protected
+
+config SYS_BOARD
+ default "gxp"
+
+config SYS_VENDOR
+ default "hpe"
+
+config SYS_CONFIG_NAME
+ default "gxp"
+
+config SYS_TEXT_BASE
+ default 0x5000
diff --git a/board/hpe/gxp/Makefile b/board/hpe/gxp/Makefile
new file mode 100644
index 00..775d6bf849
--- /dev/null
+++ b/board/hpe/gxp/Makefile
@@ -0,0 +1 @@
+obj-y += gxp_board.o
diff --git a/board/hpe/gxp/gxp_board.c b/board/hpe/gxp/gxp_board.c
new file mode 100644
index 00..7fc1bf2fd6
--- /dev/null
+++ b/board/hpe/gxp/gxp_board.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * GXP timer driver
+ *
+ * (C) Copyright 2022 Hewlett Packard Enterprise Development LP.
+ * Author: Nick Hawkins
+ * Author: Jean-Marie Verdun
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ECHI_CMD 0xcefe0010
+
+int board_init(void)
+{
+ writel(0x00080002, ECHI_CMD);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
--
2.17.1
[PATCH v1 2/9] timer: gxp: Add HPE GXP timer support
From: Nick Hawkins
Add support for the HPE GXP SOC timer. The GXP supports several different
kinds of timers but for the purpose of this driver there is only support
for the General Timer. The timer has a 1us resolution and is 56 bits.
Signed-off-by: Nick Hawkins
---
drivers/timer/Kconfig | 7 +
drivers/timer/Makefile| 1 +
drivers/timer/gxp-timer.c | 65 +++
3 files changed, 73 insertions(+)
create mode 100644 drivers/timer/gxp-timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 7b8ab56ed3..d592dba285 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -139,6 +139,13 @@ config DESIGNWARE_APB_TIMER
Enables support for the Designware APB Timer driver. This timer is
present on Altera SoCFPGA SoCs.
+config GXP_TIMER
+ bool "HPE GXP Timer"
+ depends on TIMER
+ help
+ Enables support for the GXP Timer driver. This timer is
+ present on HPE GXP SoCs.
+
config MPC83XX_TIMER
bool "MPC83xx timer support"
depends on TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index b2f002d597..cc2b8516b5 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_$(SPL_)ATMEL_PIT_TIMER) += atmel_pit_timer.o
obj-$(CONFIG_$(SPL_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o
obj-$(CONFIG_CADENCE_TTC_TIMER)+= cadence-ttc.o
obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
+obj-$(CONFIG_GXP_TIMER)+= gxp-timer.o
obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
obj-$(CONFIG_NOMADIK_MTU_TIMER)+= nomadik-mtu-timer.o
obj-$(CONFIG_NPCM_TIMER)+= npcm-timer.o
diff --git a/drivers/timer/gxp-timer.c b/drivers/timer/gxp-timer.c
new file mode 100644
index 00..db11eddf74
--- /dev/null
+++ b/drivers/timer/gxp-timer.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * GXP timer driver
+ *
+ * (C) Copyright 2022 Hewlett Packard Enterprise Development LP.
+ * Author: Nick Hawkins
+ * Author: Jean-Marie Verdun
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define USTIMELO 0x18
+#define USTIMEHI 0x1C
+
+struct gxp_timer_priv {
+ void __iomem *base;
+};
+
+static u64 gxp_timer_get_count(struct udevice *dev)
+{
+ struct gxp_timer_priv *priv = dev_get_priv(dev);
+ u64 val;
+
+ val = readl(priv->base + USTIMEHI);
+ val = (val << 32) | readl(priv->base + USTIMELO);
+
+ return val;
+}
+
+static int gxp_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct gxp_timer_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+
+ uc_priv->clock_rate = 100;
+
+ return 0;
+}
+
+static const struct timer_ops gxp_timer_ops = {
+ .get_count = gxp_timer_get_count,
+};
+
+static const struct udevice_id gxp_timer_ids[] = {
+ { .compatible = "hpe,gxp-timer" },
+ {}
+};
+
+U_BOOT_DRIVER(gxp_timer) = {
+ .name = "gxp-timer",
+ .id = UCLASS_TIMER,
+ .of_match = gxp_timer_ids,
+ .priv_auto = sizeof(struct gxp_timer_priv),
+ .probe = gxp_timer_probe,
+ .ops = _timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.17.1
[PATCH v1 1/9] ARM: hpe: gxp: add core support
From: Nick Hawkins
The GXP is the HPE BMC SoC that is used in the majority
of current generation HPE servers. Traditionally the asic will
last multiple generations of server before being replaced.
Info about SoC:
HPE GXP is the name of the HPE Soc. This SoC is used to implement many BMC
features at HPE. It supports ARMv7 architecture based on the Cortex A9
core. It is capable of using an AXI bus to whicha memory controller is
attached. It has multiple SPI interfaces to connect boot flash and BIOS
flash. It uses a 10/100/1000 MAC for network connectivity. It has multiple
i2c engines to drive connectivity with a host infrastructure. There
currently are no public specifications but this process is being worked.
Signed-off-by: Nick Hawkins
---
arch/arm/Kconfig | 8
arch/arm/Makefile | 1 +
arch/arm/mach-hpe/Makefile | 1 +
arch/arm/mach-hpe/gxp/Kconfig | 9 +
arch/arm/mach-hpe/gxp/Makefile | 1 +
arch/arm/mach-hpe/gxp/reset.c | 26 ++
6 files changed, 46 insertions(+)
create mode 100644 arch/arm/mach-hpe/Makefile
create mode 100644 arch/arm/mach-hpe/gxp/Kconfig
create mode 100644 arch/arm/mach-hpe/gxp/Makefile
create mode 100644 arch/arm/mach-hpe/gxp/reset.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9898c7d68e..1f9fc1bb8e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2085,6 +2085,12 @@ config TARGET_XENGUEST_ARM64
select SSCANF
imply OF_HAS_PRIOR_STAGE
+config ARCH_GXP
+ bool "Support HPE GXP SoCs"
+ select DM
+ select OF_CONTROL
+ imply CMD_DM
+
endchoice
config SUPPORT_PASSING_ATAGS
@@ -2193,6 +2199,8 @@ source "arch/arm/mach-davinci/Kconfig"
source "arch/arm/mach-exynos/Kconfig"
+source "arch/arm/mach-hpe/gxp/Kconfig"
+
source "arch/arm/mach-highbank/Kconfig"
source "arch/arm/mach-integrator/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 85c23bcf77..cfaa38594c 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -62,6 +62,7 @@ machine-$(CONFIG_ARCH_BCM283X)+= bcm283x
machine-$(CONFIG_ARCH_BCMSTB) += bcmstb
machine-$(CONFIG_ARCH_DAVINCI) += davinci
machine-$(CONFIG_ARCH_EXYNOS) += exynos
+machine-$(CONFIG_ARCH_GXP) += hpe
machine-$(CONFIG_ARCH_HIGHBANK)+= highbank
machine-$(CONFIG_ARCH_IPQ40XX) += ipq40xx
machine-$(CONFIG_ARCH_K3) += k3
diff --git a/arch/arm/mach-hpe/Makefile b/arch/arm/mach-hpe/Makefile
new file mode 100644
index 00..afe5f7a29e
--- /dev/null
+++ b/arch/arm/mach-hpe/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_SOC_GXP) += gxp/
diff --git a/arch/arm/mach-hpe/gxp/Kconfig b/arch/arm/mach-hpe/gxp/Kconfig
new file mode 100644
index 00..2d43133ab0
--- /dev/null
+++ b/arch/arm/mach-hpe/gxp/Kconfig
@@ -0,0 +1,9 @@
+if ARCH_GXP
+
+config SOC_GXP
+ bool
+ select CPU_V7A
+
+source "board/hpe/gxp/Kconfig"
+
+endif
diff --git a/arch/arm/mach-hpe/gxp/Makefile b/arch/arm/mach-hpe/gxp/Makefile
new file mode 100644
index 00..f3cc6684b8
--- /dev/null
+++ b/arch/arm/mach-hpe/gxp/Makefile
@@ -0,0 +1 @@
+obj-y += reset.o
diff --git a/arch/arm/mach-hpe/gxp/reset.c b/arch/arm/mach-hpe/gxp/reset.c
new file mode 100644
index 00..4d4d5f015f
--- /dev/null
+++ b/arch/arm/mach-hpe/gxp/reset.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * GXP driver
+ *
+ * (C) Copyright 2022 Hewlett Packard Enterprise Development LP.
+ * Author: Nick Hawkins
+ * Author: Jean-Marie Verdun
+ */
+
+#include
+#include
+
+#define GXP_CCR0xc000
+
+/* empty to satisfy current lowlevel_init, can be removed any time */
+void lowlevel_init(void)
+{
+}
+
+void reset_cpu(ulong ignored)
+{
+ writel(1, GXP_CCR);
+
+ while (1)
+ ; /* loop forever till reset */
+}
--
2.17.1
[PATCH v1 0/9] Introduce HPE GXP Architecture
From: Nick Hawkins The GXP is the HPE BMC SoC that is used in the majority of HPE current generation servers. Traditionally the asic will last multiple generations of server before being replaced. Info about SoC: HPE GXP is the name of the HPE SoC. This SoC is used to implement many BMC features at HPE. It supports ARMv7 architecture based on the Cortex A9 core. It is capable of using an AXI bus to which a memory controller is attached. It has multiple SPI interfaces to connect boot flash and BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It has multiple i2c engines to drive connectivity with a host infrastructure. The initial patches enable the timer enabling U-Boot prompt to work. Nick Hawkins (9): ARM: hpe: gxp: add core support timer: gxp: Add HPE GXP timer support board: hpe: gxp: add HPE GXP soc support dt-bindings: arm: hpe: add GXP Support dt-bindings: timer: Add hpe gxp timer ARM: dts: Add device tree files for hpe gxp soc configs: gxp: add core support configs: gxp: add gxp_defconfig MAINTAINERS: Introduce HPE GXP Architecture MAINTAINERS | 12 +++ arch/arm/Kconfig | 8 ++ arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 2 + arch/arm/dts/hpe-bmc-dl360gen10.dts | 26 + arch/arm/dts/hpe-gxp.dtsi | 95 ++ arch/arm/mach-hpe/Makefile| 1 + arch/arm/mach-hpe/gxp/Kconfig | 9 ++ arch/arm/mach-hpe/gxp/Makefile| 1 + arch/arm/mach-hpe/gxp/reset.c | 26 + board/hpe/gxp/Kconfig | 47 + board/hpe/gxp/Makefile| 1 + board/hpe/gxp/gxp_board.c | 33 +++ configs/gxp_defconfig | 48 ++ doc/device-tree-bindings/arm/hpe,gxp.yaml | 27 ++ .../timer/hpe,gxp-timer.yaml | 47 + drivers/timer/Kconfig | 7 ++ drivers/timer/Makefile| 1 + drivers/timer/gxp-timer.c | 65 + include/configs/gxp.h | 96 +++ 20 files changed, 553 insertions(+) create mode 100644 arch/arm/dts/hpe-bmc-dl360gen10.dts create mode 100644 arch/arm/dts/hpe-gxp.dtsi create mode 100644 arch/arm/mach-hpe/Makefile create mode 100644 arch/arm/mach-hpe/gxp/Kconfig create mode 100644 arch/arm/mach-hpe/gxp/Makefile create mode 100644 arch/arm/mach-hpe/gxp/reset.c create mode 100644 board/hpe/gxp/Kconfig create mode 100644 board/hpe/gxp/Makefile create mode 100644 board/hpe/gxp/gxp_board.c create mode 100644 configs/gxp_defconfig create mode 100644 doc/device-tree-bindings/arm/hpe,gxp.yaml create mode 100644 doc/device-tree-bindings/timer/hpe,gxp-timer.yaml create mode 100644 drivers/timer/gxp-timer.c create mode 100644 include/configs/gxp.h -- 2.17.1
[PATCH v1 1/8] timer: gxp: Add HPE GXP timer support
From: Nick Hawkins
Add support for the HPE GXP SOC timer. The GXP supports several different
kinds of timers but for the purpose of this driver there is only support
for the General Timer. The timer has a 1us resolution and is 56 bits.
Signed-off-by: Nick Hawkins
---
drivers/timer/Kconfig | 7 +
drivers/timer/Makefile| 1 +
drivers/timer/gxp-timer.c | 65 +++
3 files changed, 73 insertions(+)
create mode 100644 drivers/timer/gxp-timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 7b8ab56ed3..d592dba285 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -139,6 +139,13 @@ config DESIGNWARE_APB_TIMER
Enables support for the Designware APB Timer driver. This timer is
present on Altera SoCFPGA SoCs.
+config GXP_TIMER
+ bool "HPE GXP Timer"
+ depends on TIMER
+ help
+ Enables support for the GXP Timer driver. This timer is
+ present on HPE GXP SoCs.
+
config MPC83XX_TIMER
bool "MPC83xx timer support"
depends on TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index b2f002d597..cc2b8516b5 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_$(SPL_)ATMEL_PIT_TIMER) += atmel_pit_timer.o
obj-$(CONFIG_$(SPL_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o
obj-$(CONFIG_CADENCE_TTC_TIMER)+= cadence-ttc.o
obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
+obj-$(CONFIG_GXP_TIMER)+= gxp-timer.o
obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
obj-$(CONFIG_NOMADIK_MTU_TIMER)+= nomadik-mtu-timer.o
obj-$(CONFIG_NPCM_TIMER)+= npcm-timer.o
diff --git a/drivers/timer/gxp-timer.c b/drivers/timer/gxp-timer.c
new file mode 100644
index 00..db11eddf74
--- /dev/null
+++ b/drivers/timer/gxp-timer.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * GXP timer driver
+ *
+ * (C) Copyright 2022 Hewlett Packard Enterprise Development LP.
+ * Author: Nick Hawkins
+ * Author: Jean-Marie Verdun
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define USTIMELO 0x18
+#define USTIMEHI 0x1C
+
+struct gxp_timer_priv {
+ void __iomem *base;
+};
+
+static u64 gxp_timer_get_count(struct udevice *dev)
+{
+ struct gxp_timer_priv *priv = dev_get_priv(dev);
+ u64 val;
+
+ val = readl(priv->base + USTIMEHI);
+ val = (val << 32) | readl(priv->base + USTIMELO);
+
+ return val;
+}
+
+static int gxp_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct gxp_timer_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+
+ uc_priv->clock_rate = 100;
+
+ return 0;
+}
+
+static const struct timer_ops gxp_timer_ops = {
+ .get_count = gxp_timer_get_count,
+};
+
+static const struct udevice_id gxp_timer_ids[] = {
+ { .compatible = "hpe,gxp-timer" },
+ {}
+};
+
+U_BOOT_DRIVER(gxp_timer) = {
+ .name = "gxp-timer",
+ .id = UCLASS_TIMER,
+ .of_match = gxp_timer_ids,
+ .priv_auto = sizeof(struct gxp_timer_priv),
+ .probe = gxp_timer_probe,
+ .ops = _timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.17.1
[PATCH v1 0/8] Introduce HPE GXP Architecture
From: Nick Hawkins The GXP is the HPE BMC SoC that is used in the majority of HPE current generation servers. Traditionally the asic will last multiple generations of server before being replaced. Info about SoC: HPE GXP is the name of the HPE SoC. This SoC is used to implement many BMC features at HPE. It supports ARMv7 architecture based on the Cortex A9 core. It is capable of using an AXI bus to which a memory controller is attached. It has multiple SPI interfaces to connect boot flash and BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It has multiple i2c engines to drive connectivity with a host infrastructure. The initial patches enable the timer and enable U-Boot prompt to work. Nick Hawkins (8): timer: gxp: Add HPE GXP timer support board: hpe: gxp: add HPE GXP soc support dt-bindings: arm: hpe: add GXP Support dt-bindings: timer: Add hpe gxp timer ARM: dts: Add device tree files for hpe gxp soc configs: gxp: add core support configs: gxp: add gxp_defconfig MAINTAINERS: Introduce HPE GXP Architecture MAINTAINERS | 12 +++ arch/arm/dts/Makefile | 2 + arch/arm/dts/hpe-bmc-dl360gen10.dts | 26 + arch/arm/dts/hpe-gxp.dtsi | 95 ++ board/hpe/gxp/Kconfig | 47 + board/hpe/gxp/Makefile| 1 + board/hpe/gxp/gxp_board.c | 33 +++ configs/gxp_defconfig | 48 ++ doc/device-tree-bindings/arm/hpe,gxp.yaml | 27 ++ .../timer/hpe,gxp-timer.yaml | 47 + drivers/timer/Kconfig | 7 ++ drivers/timer/Makefile| 1 + drivers/timer/gxp-timer.c | 65 + include/configs/gxp.h | 96 +++ 14 files changed, 507 insertions(+) create mode 100644 arch/arm/dts/hpe-bmc-dl360gen10.dts create mode 100644 arch/arm/dts/hpe-gxp.dtsi create mode 100644 board/hpe/gxp/Kconfig create mode 100644 board/hpe/gxp/Makefile create mode 100644 board/hpe/gxp/gxp_board.c create mode 100644 configs/gxp_defconfig create mode 100644 doc/device-tree-bindings/arm/hpe,gxp.yaml create mode 100644 doc/device-tree-bindings/timer/hpe,gxp-timer.yaml create mode 100644 drivers/timer/gxp-timer.c create mode 100644 include/configs/gxp.h -- 2.17.1
Re: [PATCH v3] net: Check for the minimum IP header total length
Hi Michael, On Thu, May 26, 2022 at 2:24 PM Michael Nazzareno Trimarchi wrote: >> +#define IP_MIN_TOTAL_LENGTH(IP_HDR_SIZE + 1) >> + > Not needed Thanks for reviewing it. Please ignore v3. It is v2 that has the correct logic.
Re: [PATCH v3] net: Check for the minimum IP header total length
Hi
Il gio 26 mag 2022, 18:36 Fabio Estevam ha scritto:
> From: Fabio Estevam
>
> Nicolas Bidron and Nicolas Guigo reported the two bugs below:
>
> "
> --BUG 1--
>
> In compiled versions of U-Boot that define CONFIG_IP_DEFRAG, a value of
> `ip->ip_len` (IP packet header's Total Length) higher than `IP_HDR_SIZE`
> and strictly lower than `IP_HDR_SIZE+8` will lead to a value for `len`
> comprised between `0` and `7`. This will ultimately result in a
> truncated division by `8` resulting value of `0` forcing the hole
> metadata and fragment to point to the same location. The subsequent
> memcopy will overwrite the hole metadata with the fragment data. Through
> a second fragment, this can be exploited to write to an arbitrary offset
> controlled by that overwritten hole metadata value.
>
> This bug is only exploitable locally as it requires crafting two packets
> the first of which would most likely be dropped through routing due to
> its unexpectedly low Total Length. However, this bug can potentially be
> exploited to root linux based embedded devices locally.
>
> ```C
> static struct ip_udp_hdr *__net_defragment(struct ip_udp_hdr *ip, int
> *lenp)
> {
> static uchar pkt_buff[IP_PKTSIZE] __aligned(PKTALIGN);
> static u16 first_hole, total_len;
> struct hole *payload, *thisfrag, *h, *newh;
> struct ip_udp_hdr *localip = (struct ip_udp_hdr *)pkt_buff;
> uchar *indata = (uchar *)ip;
> int offset8, start, len, done = 0;
> u16 ip_off = ntohs(ip->ip_off);
>
> /* payload starts after IP header, this fragment is in there */
> payload = (struct hole *)(pkt_buff + IP_HDR_SIZE);
> offset8 = (ip_off & IP_OFFS);
> thisfrag = payload + offset8;
> start = offset8 * 8;
> len = ntohs(ip->ip_len) - IP_HDR_SIZE;
> ```
>
> The last line of the previous excerpt from `u-boot/net/net.c` shows how
> the attacker can control the value of `len` to be strictly lower than
> `8` by issuing a packet with `ip_len` between `21` and `27`
> (`IP_HDR_SIZE` has a value of `20`).
>
> Also note that `offset8` here is `0` which leads to `thisfrag = payload`.
>
> ```C
> } else if (h >= thisfrag) {
> /* overlaps with initial part of the hole: move this hole */
> newh = thisfrag + (len / 8);
> *newh = *h;
> h = newh;
> if (h->next_hole)
> payload[h->next_hole].prev_hole = (h - payload);
> if (h->prev_hole)
> payload[h->prev_hole].next_hole = (h - payload);
> else
> first_hole = (h - payload);
>
> } else {
> ```
>
> Lower down the same function, execution reaches the above code path.
> Here, `len / 8` evaluates to `0` leading to `newh = thisfrag`. Also note
> that `first_hole` here is `0` since `h` and `payload` point to the same
> location.
>
> ```C
> /* finally copy this fragment and possibly return whole packet */
> memcpy((uchar *)thisfrag, indata + IP_HDR_SIZE, len);
> ```
>
> Finally, in the above excerpt the `memcpy` overwrites the hole metadata
> since `thisfrag` and `h` both point to the same location. The hole
> metadata is effectively overwritten with arbitrary data from the
> fragmented IP packet data. If `len` was crafted to be `6`, `last_byte`,
> `next_hole`, and `prev_hole` of the `first_hole` can be controlled by
> the attacker.
>
> Finally the arbitrary offset write occurs through a second fragment that
> only needs to be crafted to write data in the hole pointed to by the
> previously controlled hole metadata (`next_hole`) from the first packet.
>
> ### Recommendation
>
> Handle cases where `len` is strictly lower than 8 by preventing the
> overwrite of the hole metadata during the memcpy of the fragment. This
> could be achieved by either:
> * Moving the location where the hole metadata is stored when `len` is
> lower than `8`.
> * Or outright rejecting fragmented IP datagram with a Total Length
> (`ip_len`) lower than 28 bytes which is the minimum valid fragmented IP
> datagram size (as defined as the minimum fragment of 8 octets in the IP
> Specification Document:
> [RFC791](https://datatracker.ietf.org/doc/html/rfc791) page 25).
>
> --BUG 2--
>
> In compiled versions of U-Boot that define CONFIG_IP_DEFRAG, a value of
> `ip->ip_len` (IP packet header's Total Length) lower than `IP_HDR_SIZE`
> will lead to a negative value for `len` which will ultimately result in
> a buffer overflow during the subsequent `memcpy` that uses `len` as it's
> `count` parameter.
>
> This bug is only exploitable on local ethernet as it requires crafting
> an invalid packet to include an unexpected `ip_len` value in the IP UDP
> header that's lower than the minimum accepted Total Length of a packet
> (21 as defined in the IP Specification Document:
> [RFC791](https://datatracker.ietf.org/doc/html/rfc791)). Such packet
> would in all likelihood be dropped while being routed to its final
> destination through most routing equipment
Re: [PATCH v2] net: Check for the minimum IP fragmented datagram size
On Thu, May 26, 2022 at 1:10 PM Fabio Estevam wrote: > > On 26/05/2022 11:14, Fabio Estevam wrote: > > > Add a check for ip_len lesser than 28 and stop processing the packet > > in this case. > > > > Such a check covers the two reported bugs. > > Ops, it is (ip->ip_len < 21) the condition that satisfies both cases. > > I will send a v3. Actually, the condition in v2 is the correct one :-) Sorry for the confusion.
[PATCH v3] net: Check for the minimum IP header total length
From: Fabio Estevam
Nicolas Bidron and Nicolas Guigo reported the two bugs below:
"
--BUG 1--
In compiled versions of U-Boot that define CONFIG_IP_DEFRAG, a value of
`ip->ip_len` (IP packet header's Total Length) higher than `IP_HDR_SIZE`
and strictly lower than `IP_HDR_SIZE+8` will lead to a value for `len`
comprised between `0` and `7`. This will ultimately result in a
truncated division by `8` resulting value of `0` forcing the hole
metadata and fragment to point to the same location. The subsequent
memcopy will overwrite the hole metadata with the fragment data. Through
a second fragment, this can be exploited to write to an arbitrary offset
controlled by that overwritten hole metadata value.
This bug is only exploitable locally as it requires crafting two packets
the first of which would most likely be dropped through routing due to
its unexpectedly low Total Length. However, this bug can potentially be
exploited to root linux based embedded devices locally.
```C
static struct ip_udp_hdr *__net_defragment(struct ip_udp_hdr *ip, int *lenp)
{
static uchar pkt_buff[IP_PKTSIZE] __aligned(PKTALIGN);
static u16 first_hole, total_len;
struct hole *payload, *thisfrag, *h, *newh;
struct ip_udp_hdr *localip = (struct ip_udp_hdr *)pkt_buff;
uchar *indata = (uchar *)ip;
int offset8, start, len, done = 0;
u16 ip_off = ntohs(ip->ip_off);
/* payload starts after IP header, this fragment is in there */
payload = (struct hole *)(pkt_buff + IP_HDR_SIZE);
offset8 = (ip_off & IP_OFFS);
thisfrag = payload + offset8;
start = offset8 * 8;
len = ntohs(ip->ip_len) - IP_HDR_SIZE;
```
The last line of the previous excerpt from `u-boot/net/net.c` shows how
the attacker can control the value of `len` to be strictly lower than
`8` by issuing a packet with `ip_len` between `21` and `27`
(`IP_HDR_SIZE` has a value of `20`).
Also note that `offset8` here is `0` which leads to `thisfrag = payload`.
```C
} else if (h >= thisfrag) {
/* overlaps with initial part of the hole: move this hole */
newh = thisfrag + (len / 8);
*newh = *h;
h = newh;
if (h->next_hole)
payload[h->next_hole].prev_hole = (h - payload);
if (h->prev_hole)
payload[h->prev_hole].next_hole = (h - payload);
else
first_hole = (h - payload);
} else {
```
Lower down the same function, execution reaches the above code path.
Here, `len / 8` evaluates to `0` leading to `newh = thisfrag`. Also note
that `first_hole` here is `0` since `h` and `payload` point to the same
location.
```C
/* finally copy this fragment and possibly return whole packet */
memcpy((uchar *)thisfrag, indata + IP_HDR_SIZE, len);
```
Finally, in the above excerpt the `memcpy` overwrites the hole metadata
since `thisfrag` and `h` both point to the same location. The hole
metadata is effectively overwritten with arbitrary data from the
fragmented IP packet data. If `len` was crafted to be `6`, `last_byte`,
`next_hole`, and `prev_hole` of the `first_hole` can be controlled by
the attacker.
Finally the arbitrary offset write occurs through a second fragment that
only needs to be crafted to write data in the hole pointed to by the
previously controlled hole metadata (`next_hole`) from the first packet.
### Recommendation
Handle cases where `len` is strictly lower than 8 by preventing the
overwrite of the hole metadata during the memcpy of the fragment. This
could be achieved by either:
* Moving the location where the hole metadata is stored when `len` is
lower than `8`.
* Or outright rejecting fragmented IP datagram with a Total Length
(`ip_len`) lower than 28 bytes which is the minimum valid fragmented IP
datagram size (as defined as the minimum fragment of 8 octets in the IP
Specification Document:
[RFC791](https://datatracker.ietf.org/doc/html/rfc791) page 25).
--BUG 2--
In compiled versions of U-Boot that define CONFIG_IP_DEFRAG, a value of
`ip->ip_len` (IP packet header's Total Length) lower than `IP_HDR_SIZE`
will lead to a negative value for `len` which will ultimately result in
a buffer overflow during the subsequent `memcpy` that uses `len` as it's
`count` parameter.
This bug is only exploitable on local ethernet as it requires crafting
an invalid packet to include an unexpected `ip_len` value in the IP UDP
header that's lower than the minimum accepted Total Length of a packet
(21 as defined in the IP Specification Document:
[RFC791](https://datatracker.ietf.org/doc/html/rfc791)). Such packet
would in all likelihood be dropped while being routed to its final
destination through most routing equipment and as such requires the
attacker to be in a local position in order to be exploited.
```C
static struct ip_udp_hdr *__net_defragment(struct ip_udp_hdr *ip, int *lenp)
{
static uchar pkt_buff[IP_PKTSIZE] __aligned(PKTALIGN);
static u16 first_hole,
Re: [PATCH v2] net: Check for the minimum IP fragmented datagram size
On 26/05/2022 11:14, Fabio Estevam wrote: Add a check for ip_len lesser than 28 and stop processing the packet in this case. Such a check covers the two reported bugs. Ops, it is (ip->ip_len < 21) the condition that satisfies both cases. I will send a v3.
[PATCH v2 09/11] socfpga: arria10: Improve bitstream loading speed
Apply some optimizations to speed up bitstream loading
(both for full and split periph/core bitstreams):
* Change the size of the first fs read, so that all the subsequent
reads are aligned to a specific value (called MAX_FIRST_LOAD_SIZE).
This value was chosen so that in subsequent reads the fat fs driver
doesn't have to allocate a temporary buffer in get_contents
(assuming 8KiB clusters).
* Change the buffer size to a larger value when reading to ddr
(but not too large, because large transfers cause a stack overflow
in the dwmmc driver).
Signed-off-by: Paweł Anikiel
---
drivers/fpga/socfpga_arria10.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 798e3a3f90..07bfe3060e 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -30,6 +30,14 @@
#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
#define FPGA_TIMEOUT_CNT 0x100
#define DEFAULT_DDR_LOAD_ADDRESS 0x400
+#define DDR_BUFFER_SIZE0x10
+
+/* When reading bitstream from a filesystem, the size of the first read is
+ * changed so that the subsequent reads are aligned to this value. This value
+ * was chosen so that in subsequent reads the fat fs driver doesn't have to
+ * allocate a temporary buffer in get_contents (assuming 8KiB clusters).
+ */
+#define MAX_FIRST_LOAD_SIZE0x2000
DECLARE_GLOBAL_DATA_PTR;
@@ -526,7 +534,8 @@ static void get_rbf_image_info(struct rbf_info *rbf, u16
*buffer)
#ifdef CONFIG_FS_LOADER
static int first_loading_rbf_to_buffer(struct udevice *dev,
struct fpga_loadfs_info *fpga_loadfs,
- u32 *buffer, size_t *buffer_bsize)
+ u32 *buffer, size_t *buffer_bsize,
+ size_t *buffer_bsize_ori)
{
u32 *buffer_p = (u32 *)*buffer;
u32 *loadable = buffer_p;
@@ -674,6 +683,7 @@ static int first_loading_rbf_to_buffer(struct udevice *dev,
}
buffer_size = rbf_size;
+ *buffer_bsize_ori = DDR_BUFFER_SIZE;
}
debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
@@ -686,11 +696,16 @@ static int first_loading_rbf_to_buffer(struct udevice
*dev,
* chunk by chunk transfer is required due to smaller buffer size
* compare to bitstream
*/
+
+ if (buffer_size > MAX_FIRST_LOAD_SIZE)
+ buffer_size = MAX_FIRST_LOAD_SIZE;
+
if (rbf_size <= buffer_size) {
/* Loading whole bitstream into buffer */
buffer_size = rbf_size;
fpga_loadfs->remaining = 0;
} else {
+ buffer_size -= rbf_offset % buffer_size;
fpga_loadfs->remaining -= buffer_size;
}
@@ -806,7 +821,8 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void
*buf, size_t bsize,
* function below.
*/
ret = first_loading_rbf_to_buffer(dev, _loadfs, ,
- _sizebytes);
+ _sizebytes,
+ _sizebytes_ori);
if (ret == 1) {
printf("FPGA: Skipping configuration ...\n");
return 0;
--
2.36.1.124.g0e6072fb45-goog
Re: [PATCH v2 12/12] doc: ti: Add readme for AM62x SK
Hi Vignesh! On May 25, 2022 thus sayeth Vignesh Raghavendra: > Add info of boot flow and build steps for AM62x SK. > > Signed-off-by: Vignesh Raghavendra > --- Reviewed-by: Bryan Brattlof Looks good to me! ~Bryan
[PATCH v2 11/11] socfpga: arria10: Allow dcache_enable before relocation
Before relocating to SDRAM, the ECC is initialized by clearing the
whole SDRAM. In order to speed this up, dcache_enable is used (see
sdram_init_ecc_bits).
Since commit 503eea451903 ("arm: cp15: update DACR value to activate
access control"), this no longer works, because running code in OCRAM
with the XN bit set causes a page fault. Override dram_bank_mmu_setup
to disable XN in the OCRAM and setup DRAM dcache before relocation.
Signed-off-by: Paweł Anikiel
---
arch/arm/mach-socfpga/misc_arria10.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc_arria10.c
b/arch/arm/mach-socfpga/misc_arria10.c
index 0ed2adfd84..7ce888d197 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -246,3 +246,29 @@ int qspi_flash_software_reset(void)
return 0;
}
#endif
+
+void dram_bank_mmu_setup(int bank)
+{
+ struct bd_info *bd = gd->bd;
+ u32 start, size;
+ int i;
+
+ /* If we're still in OCRAM, don't set the XN bit on it */
+ if (!(gd->flags & GD_FLG_RELOC)) {
+ set_section_dcache(
+ CONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,
+ DCACHE_WRITETHROUGH);
+ }
+
+ /*
+* The default implementation of this function allows the DRAM dcache
+* to be enabled only after relocation. However, to speed up ECC
+* initialization, we want to be able to enable DRAM dcache before
+* relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram
+* is set first).
+*/
+ start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
+ size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
+ for (i = start; i < start + size; i++)
+ set_section_dcache(i, DCACHE_DEFAULT_OPTION);
+}
--
2.36.1.124.g0e6072fb45-goog
Re: [PATCH v2 09/12] board: ti: Introduce the basic files to support AM62 SK board
On Wed, May 25, 2022 at 01:38:47PM +0530, Vignesh Raghavendra wrote: > From: Suman Anna > > Add basic support for AM62 SK. This has 2GB DDR. > Note that stack for R5 SPL is in OCRAM @ 0x7000 so that is away from > BSS and does not step on BSS section > > Add only the bare minimum required to support UART and SD. > > Signed-off-by: Suman Anna > Signed-off-by: Aswath Govindraju > Signed-off-by: Nishanth Menon > Signed-off-by: Vignesh Raghavendra Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 04/12] arm: mach-k3: Introduce the basic files to support AM62
On Wed, May 25, 2022 at 01:38:42PM +0530, Vignesh Raghavendra wrote: > From: Suman Anna > > The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC > architecture platform, providing ultra-low-power modes, dual display, > multi-sensor edge compute, security and other BOM-saving integration. > The AM62 SoC targets broad market to enable applications such as > Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building > Automation, Appliances and more. > > Some highlights of this SoC are: > > * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. > Pin-to-pin compatible options for single and quad core are available. > * Cortex-M4F for general-purpose or safety usage. > * Dual display support, providing 24-bit RBG parallel interface and > OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display > resolution. > * Selectable GPUsupport, up to 8GFLOPS, providing better user experience > in 3D graphic display case and Android. > * PRU(Programmable Realtime Unit) support for customized programmable > interfaces/IOs. > * Integrated Giga-bit Ethernet switch supporting up to a total of two > external ports (TSN capable). > * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for > NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, > 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. > * Dedicated Centralized System Controller for Security, Power, and > Resource Management. > * Multiple low power modes support, ex: Deep sleep,Standby, MCU-only, > enabling battery powered system design. > > AM625 is the first device of the family. Add DT bindings for the same. > > More details can be found in the Technical Reference Manual: > https://www.ti.com/lit/pdf/spruiv7 > > Signed-off-by: Suman Anna > Signed-off-by: Gowtham Tammana > Signed-off-by: Aswath Govindraju > Signed-off-by: Nishanth Menon > Signed-off-by: Vignesh Raghavendra Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 03/12] soc: ti: k3-socinfo: Add entry for AM62X SoC family
On Wed, May 25, 2022 at 01:38:41PM +0530, Vignesh Raghavendra wrote: > From: Suman Anna > > Add support for AM62x SoC identification. > > Signed-off-by: Suman Anna > Signed-off-by: Vignesh Raghavendra Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [GIT PULL] xilinx patches for v2022.07-rc4
On Wed, May 25, 2022 at 02:07:52PM +0200, Michal Simek wrote: > Hi Tom, > > please pull these patches to your tree. All of them are fixes I have > collected for v2022.07 version. Gitlab CI doesn't show any issue too. > > Thanks, > Michal > > The following changes since commit c387e62614713d0cc9e3ed022b86c9f320b02853: > > Merge branch '2022-05-11-Kconfig-cleanups-etc' (2022-05-11 13:27:44 -0400) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-microblaze.git > tags/xilinx-for-v2022.07-rc4 > > for you to fetch changes up to 594f692f491f0def6c4b6543e158a7f367b35dcc: > > xilinx: zynqmp: Wire tee for Multi DTB use cases (2022-05-24 08:44:24 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PATCH v2 06/11] misc: atsha204a: Increase wake delay by tWHI
>From the ATSHA204A datasheet (document DS40002025A):
Wake: If SDA is held low for a period greater than tWLO, the device
exits low-power mode and, after a delay of tWHI, is ready to receive
I2C commands.
tWHI value can be found in table 7-2.
Signed-off-by: Paweł Anikiel
---
drivers/misc/atsha204a-i2c.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c
index aa6acf0f9a..81ecb5b617 100644
--- a/drivers/misc/atsha204a-i2c.c
+++ b/drivers/misc/atsha204a-i2c.c
@@ -21,7 +21,8 @@
#include
#include
-#define ATSHA204A_TWLO 60
+#define ATSHA204A_TWLO_US 60
+#define ATSHA204A_TWHI_US 2500
#define ATSHA204A_TRANSACTION_TIMEOUT 10
#define ATSHA204A_TRANSACTION_RETRY5
#define ATSHA204A_EXECTIME 5000
@@ -109,7 +110,7 @@ int atsha204a_wakeup(struct udevice *dev)
continue;
}
- udelay(ATSHA204A_TWLO);
+ udelay(ATSHA204A_TWLO_US + ATSHA204A_TWHI_US);
res = atsha204a_recv_resp(dev, );
if (res) {
--
2.36.1.124.g0e6072fb45-goog
[PATCH v2 05/11] config: Add Chameleonv3 config
Add defconfig and Kconfig files for Google Chameleon V3 board
Signed-off-by: Paweł Anikiel
---
arch/arm/mach-socfpga/Kconfig | 7 +
configs/socfpga_chameleonv3_defconfig | 29 ++
include/configs/socfpga_chameleonv3.h | 44 +++
3 files changed, 80 insertions(+)
create mode 100644 configs/socfpga_chameleonv3_defconfig
create mode 100644 include/configs/socfpga_chameleonv3.h
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 78a7549a41..fe851f575e 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -143,6 +143,10 @@ config TARGET_SOCFPGA_ARRIA5_SOCDK
bool "Altera SOCFPGA SoCDK (Arria V)"
select TARGET_SOCFPGA_ARRIA5
+config TARGET_SOCFPGA_CHAMELEONV3
+ bool "Google Chameleon v3 (Arria 10)"
+ select TARGET_SOCFPGA_ARRIA10
+
config TARGET_SOCFPGA_CYCLONE5_SOCDK
bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -194,6 +198,7 @@ config SYS_BOARD
default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+ default "chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -219,6 +224,7 @@ config SYS_VENDOR
default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+ default "google" if TARGET_SOCFPGA_CHAMELEONV3
default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -234,6 +240,7 @@ config SYS_CONFIG_NAME
default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+ default "socfpga_chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
diff --git a/configs/socfpga_chameleonv3_defconfig
b/configs/socfpga_chameleonv3_defconfig
new file mode 100644
index 00..7870d31b09
--- /dev/null
+++ b/configs/socfpga_chameleonv3_defconfig
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_FPGA=y
+CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_SIZE=0x1
+CONFIG_ENV_OFFSET=0x4400
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_DESIGNWARE_APB_TIMER=y
+CONFIG_MMC_DW=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
+CONFIG_MISC_INIT_R=y
+CONFIG_ATSHA204A=y
diff --git a/include/configs/socfpga_chameleonv3.h
b/include/configs/socfpga_chameleonv3.h
new file mode 100644
index 00..891b762946
--- /dev/null
+++ b/include/configs/socfpga_chameleonv3.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 Google LLC
+ */
+#ifndef __SOCFGPA_CHAMELEONV3_H__
+#define __SOCFGPA_CHAMELEONV3_H__
+
+#include
+
+#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
+
+/*
+ * U-Boot general configurations
+ */
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x4000
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autoload=no\0" \
+ "bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rw
rootwait\0" \
+ "distro_bootcmd=bridge enable; run bootcmd_mmc\0" \
+ "bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm\0" \
+ "bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm\0"
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL 0x
+
+/* SPL memory allocation configuration, this is for FAT implementation */
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000
+
+/* The rest of the configuration is shared */
+#include
+
+#endif /* __SOCFGPA_CHAMELEONV3_H__ */
--
2.36.1.124.g0e6072fb45-goog
[PATCH v2 04/11] board: Add Chameleonv3 board dir
Add board directory for Google Chameleon V3 board
Signed-off-by: Paweł Anikiel
---
board/google/chameleonv3/Makefile | 5 +++
board/google/chameleonv3/board.c | 27 ++
board/google/chameleonv3/fpga.its | 28 ++
board/google/chameleonv3/fpga_early_io.its | 35 ++
board/google/chameleonv3/mercury_aa1.c | 43 ++
board/google/chameleonv3/mercury_aa1.h | 12 ++
6 files changed, 150 insertions(+)
create mode 100644 board/google/chameleonv3/Makefile
create mode 100644 board/google/chameleonv3/board.c
create mode 100644 board/google/chameleonv3/fpga.its
create mode 100644 board/google/chameleonv3/fpga_early_io.its
create mode 100644 board/google/chameleonv3/mercury_aa1.c
create mode 100644 board/google/chameleonv3/mercury_aa1.h
diff --git a/board/google/chameleonv3/Makefile
b/board/google/chameleonv3/Makefile
new file mode 100644
index 00..bb413fde83
--- /dev/null
+++ b/board/google/chameleonv3/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright 2022 Google LLC
+
+obj-y := board.o mercury_aa1.o
diff --git a/board/google/chameleonv3/board.c b/board/google/chameleonv3/board.c
new file mode 100644
index 00..4d3049689d
--- /dev/null
+++ b/board/google/chameleonv3/board.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include
+#include
+#include "mercury_aa1.h"
+
+int misc_init_r(void)
+{
+ u8 mac[ARP_HLEN];
+ int res;
+
+ if (env_get("ethaddr"))
+ return 0;
+
+ res = mercury_aa1_read_mac(mac);
+ if (res) {
+ printf("couldn't read mac address: %s\n", errno_str(res));
+ return 0;
+ }
+
+ if (is_valid_ethaddr(mac))
+ eth_env_set_enetaddr("ethaddr", mac);
+
+ return 0;
+}
diff --git a/board/google/chameleonv3/fpga.its
b/board/google/chameleonv3/fpga.its
new file mode 100644
index 00..85a830002f
--- /dev/null
+++ b/board/google/chameleonv3/fpga.its
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+
+/ {
+ description = "FIT image with FPGA bistream";
+ #address-cells = <1>;
+
+ images {
+ fpga-periph-1 {
+ description = "FPGA full bitstream";
+ data = /incbin/("../../../fpga.rbf");
+ type = "fpga";
+ arch = "arm";
+ compression = "none";
+ };
+ };
+
+ configurations {
+ default = "config-1";
+ config-1 {
+ description = "Boot with FPGA config";
+ fpga = "fpga-periph-1";
+ };
+ };
+};
diff --git a/board/google/chameleonv3/fpga_early_io.its
b/board/google/chameleonv3/fpga_early_io.its
new file mode 100644
index 00..ebc7bcbaae
--- /dev/null
+++ b/board/google/chameleonv3/fpga_early_io.its
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+
+/ {
+ description = "FIT image with FPGA bistream";
+ #address-cells = <1>;
+
+ images {
+ fpga-periph-1 {
+ description = "FPGA peripheral bitstream";
+ data = /incbin/("../../../periph.rbf");
+ type = "fpga";
+ arch = "arm";
+ compression = "none";
+ };
+ fpga-core-1 {
+ description = "FPGA core bitstream";
+ data = /incbin/("../../../core.rbf");
+ type = "fpga";
+ arch = "arm";
+ compression = "none";
+ };
+ };
+
+ configurations {
+ default = "config-1";
+ config-1 {
+ description = "Boot with FPGA config";
+ fpga = "fpga-periph-1", "fpga-core-1";
+ };
+ };
+};
diff --git a/board/google/chameleonv3/mercury_aa1.c
b/board/google/chameleonv3/mercury_aa1.c
new file mode 100644
index 00..ed447ec37c
--- /dev/null
+++ b/board/google/chameleonv3/mercury_aa1.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include
+#include
+#include
+#include
+#include "mercury_aa1.h"
+
+#define MERCURY_AA1_ATSHA204A_OTP_MAC0 4
+#define MERCURY_AA1_ATSHA204A_OTP_MAC1 5
+
+int mercury_aa1_read_mac(u8 *mac)
+{
+ struct udevice *dev;
+ u8 buf[8];
+ int ret;
+
+ ret = uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", );
+ if (ret)
+ return ret;
+
+ ret = atsha204a_wakeup(dev);
+ if (ret)
+ return ret;
+
+ ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+
[PATCH v2 03/11] arm: dts: Add Chameleonv3 devicetrees
Add devicetrees for Google Chameleon V3 board
Signed-off-by: Paweł Anikiel
Signed-off-by: Alexandru M Stan
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/socfpga_arria10_chameleonv3.dts | 90 +++
...fpga_arria10_chameleonv3_270_3-u-boot.dtsi | 8 ++
.../dts/socfpga_arria10_chameleonv3_270_3.dts | 5 ++
...fpga_arria10_chameleonv3_480_2-u-boot.dtsi | 8 ++
.../dts/socfpga_arria10_chameleonv3_480_2.dts | 5 ++
6 files changed, 118 insertions(+)
create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3.dts
create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 83630af4f6..910b6c3acd 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -418,6 +418,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
\
socfpga_agilex_socdk.dtb\
socfpga_arria5_secu1.dtb\
socfpga_arria5_socdk.dtb\
+ socfpga_arria10_chameleonv3_270_3.dtb \
+ socfpga_arria10_chameleonv3_480_2.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_is1.dtb\
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3.dts
b/arch/arm/dts/socfpga_arria10_chameleonv3.dts
new file mode 100644
index 00..988cc44543
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+#include "socfpga_arria10_mercury_aa1.dtsi"
+
+/ {
+ model = "Google Chameleon V3";
+ compatible = "google,chameleon-v3",
+"altr,socfpga-arria10", "altr,socfpga";
+
+ aliases {
+ serial0 =
+ i2c0 =
+ i2c1 =
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+
+ ssm2603: ssm2603@1a {
+ compatible = "adi,ssm2603";
+ reg = <0x1a>;
+ };
+};
+
+ {
+ status = "okay";
+
+ u80: u80@21 {
+ compatible = "nxp,pca9535";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SOM_AUD_MUTE",
+ "DP1_OUT_CEC_EN",
+ "DP2_OUT_CEC_EN",
+ "DP1_SOM_PS8469_CAD",
+ "DPD_SOM_PS8469_CAD",
+ "DP_OUT_PWR_EN",
+ "STM32_RST_L",
+ "STM32_BOOT0",
+
+ "FPGA_PROT",
+ "STM32_FPGA_COMM0",
+ "TP119",
+ "TP120",
+ "TP121",
+ "TP122",
+ "TP123",
+ "TP124";
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+ dr_mode = "host";
+};
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
new file mode 100644
index 00..e789d49657
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3_270_3_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
new file mode 100644
index 00..5f40af6eb9
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3.dts"
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
new file mode 100644
index 00..7bbcc471c5
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3_480_2_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
diff
[PATCH v2 10/11] socfpga: arria10: Wait for fifo empty after writing bitstream
For some reason, on the Mercury+ AA1 module, calling
fpgamgr_wait_early_user_mode immediately after writing the peripheral
bitstream leaves the fpga in a broken state (ddr calibration hangs).
Adding a delay before the first sync word is written seems to fix this.
Inspecting the fpgamgr registers before and after the delay,
imgcfg_FifoEmpty is the only bit that changes. Waiting for this bit
(instead of a hardcoded delay) also fixes the issue.
Signed-off-by: Paweł Anikiel
---
drivers/fpga/socfpga_arria10.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 07bfe3060e..d8089122af 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -80,6 +80,13 @@ static int wait_for_user_mode(void)
1, FPGA_TIMEOUT_MSEC, false);
}
+static int wait_for_fifo_empty(void)
+{
+ return wait_for_bit_le32(_manager_base->imgcfg_stat,
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK,
+ 1, FPGA_TIMEOUT_MSEC, false);
+}
+
int is_fpgamgr_early_user_mode(void)
{
return (readl(_manager_base->imgcfg_stat) &
@@ -874,6 +881,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void
*buf, size_t bsize,
WATCHDOG_RESET();
}
+ wait_for_fifo_empty();
if (fpga_loadfs.rbfinfo.section == periph_section) {
if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
--
2.36.1.124.g0e6072fb45-goog
[PATCH v2 08/11] socfpga: arria10: Replace delays with busy waiting in cm_full_cfg
Using udelay while the clocks aren't fully configured causes the timer
system to save the wrong clock rate. Use sdelay and wait_on_value
instead (the values used in these functions were found experimentally).
Signed-off-by: Paweł Anikiel
---
arch/arm/mach-socfpga/clock_manager.c | 7 ---
arch/arm/mach-socfpga/clock_manager_arria10.c | 12 ++--
arch/arm/mach-socfpga/include/mach/clock_manager.h | 4
3 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager.c
b/arch/arm/mach-socfpga/clock_manager.c
index 9e645a4253..c9bd4859f7 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -39,9 +39,10 @@ void cm_wait_for_lock(u32 mask)
/* function to poll in the fsm busy bit */
int cm_wait_for_fsm(void)
{
- return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() +
-CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 2,
-false);
+ void *reg = (void *)(socfpga_get_clkmgr_addr() + CLKMGR_STAT);
+
+ /* 20s timeout */
+ return wait_on_value(CLKMGR_STAT_BUSY, 0, reg, 1);
}
int set_cpu_clk_info(void)
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
b/arch/arm/mach-socfpga/clock_manager_arria10.c
index 58d5d3fd8a..daa06b9d03 100644
--- a/arch/arm/mach-socfpga/clock_manager_arria10.c
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -551,13 +551,13 @@ static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
- mdelay(1);
+ sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
main_cfg->vco1_numer,
socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
- mdelay(1);
+ sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
@@ -585,13 +585,13 @@ static void cm_pll_ramp_periph(struct mainpll_cfg
*main_cfg,
clk_hz),
socfpga_get_clkmgr_addr() +
CLKMGR_A10_PERPLL_VCO1);
- mdelay(1);
+ sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
per_cfg->vco1_numer,
socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
- mdelay(1);
+ sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
@@ -727,7 +727,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct
perpll_cfg *per_cfg)
socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
/* Wait for at least 5 us */
- udelay(5);
+ sdelay(5000);
/* Now deassert BGPWRDN and PWRDN */
clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
@@ -738,7 +738,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct
perpll_cfg *per_cfg)
CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
/* Wait for at least 7 us */
- udelay(7);
+ sdelay(7000);
/* enable the VCO and disable the external regulator to PLL */
writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0) &
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index a8cb07a1c4..78013f0527 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -20,6 +20,10 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz);
#endif
#endif
+void sdelay(unsigned long loops);
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
+ u32 bound);
+
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#include
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
--
2.36.1.124.g0e6072fb45-goog
[PATCH v2 07/11] sysreset: socfpga: Use parent device for reading base address
This driver is a child of the rstmgr driver, both of which share the
same devicetree node. As a result, passing the child's udevice pointer
to dev_read_addr_ptr results in a failure of reading the #address-cells
property. Use the parent udevice pointer instead.
Signed-off-by: Paweł Anikiel
---
drivers/sysreset/sysreset_socfpga.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/sysreset/sysreset_socfpga.c
b/drivers/sysreset/sysreset_socfpga.c
index e38296ac3f..9b62dd5eab 100644
--- a/drivers/sysreset/sysreset_socfpga.c
+++ b/drivers/sysreset/sysreset_socfpga.c
@@ -40,7 +40,7 @@ static int socfpga_sysreset_probe(struct udevice *dev)
{
struct socfpga_sysreset_data *data = dev_get_priv(dev);
- data->rstmgr_base = dev_read_addr_ptr(dev);
+ data->rstmgr_base = dev_read_addr_ptr(dev_get_parent(dev));
return 0;
}
--
2.36.1.124.g0e6072fb45-goog
[PATCH v2 01/11] arm: dts: Add Mercury+ AA1 devicetrees
Devicetree headers for Mercury+ AA1 module
Signed-off-by: Paweł Anikiel
---
.../socfpga_arria10_mercury_aa1-u-boot.dtsi | 54 ++
arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi | 72 +++
2 files changed, 126 insertions(+)
create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
b/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
new file mode 100644
index 00..365e05100a
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10-u-boot.dtsi"
+
+/ {
+ chosen {
+ firmware-loader = <_loader0>;
+ };
+
+ fs_loader0: fs-loader {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ phandlepart = < 1>;
+ };
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+_mgr {
+ u-boot,dm-pre-reloc;
+ altr,bitstream = "fpga.itb";
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+_sdmmc_clk {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+_sdmmc_clk {
+ u-boot,dm-pre-reloc;
+};
+
+_clk {
+ u-boot,dm-pre-reloc;
+};
+
+_free_clk {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
b/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
new file mode 100644
index 00..fee1fc39bb
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10.dtsi"
+
+/ {
+ aliases {
+ ethernet0 =
+ serial1 =
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x8000>; /* 2GB */
+ };
+};
+
+ {
+ phy-mode = "rgmii";
+ phy-handle = <>;
+
+ max-frame-size = <3800>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ rxd0-skew-ps = <420>; /* 0ps */
+ rxd1-skew-ps = <420>; /* 0ps */
+ rxd2-skew-ps = <420>; /* 0ps */
+ rxd3-skew-ps = <420>; /* 0ps */
+ txen-skew-ps = <0>; /* -420ps */
+ txc-skew-ps = <1860>; /* 960ps */
+ rxdv-skew-ps = <420>; /* 0ps */
+ rxc-skew-ps = <1680>; /* 780ps */
+ };
+ };
+};
+
+ {
+ atsha204a: atsha204a@64 {
+ compatible = "atmel,atsha204a";
+ reg = <0x64>;
+ };
+
+ isl12022: isl12022@6f {
+ compatible = "isil,isl12022";
+ reg = <0x6f>;
+ };
+};
+
+ {
+ cap-sd-highspeed;
+ broken-cd;
+ bus-width = <4>;
+};
+
+ {
+ clock-frequency = <>;
+};
--
2.36.1.124.g0e6072fb45-goog
[PATCH v2 02/11] arm: dts: Add Chameleonv3 handoff headers
Add handoff headers for the Google Chameleonv3 variants: 480-2 and 270-3. Both files were generated using qts-filter-a10.sh. Signed-off-by: Paweł Anikiel --- ...ocfpga_arria10_chameleonv3_270_3_handoff.h | 305 ++ ...ocfpga_arria10_chameleonv3_480_2_handoff.h | 305 ++ 2 files changed, 610 insertions(+) create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h new file mode 100644 index 00..9d8f4a0dd3 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Intel Arria 10 SoCFPGA configuration + */ + +#ifndef __SOCFPGA_ARRIA10_CONFIG_H__ +#define __SOCFPGA_ARRIA10_CONFIG_H__ + +/* Clocks */ +#define CB_INTOSC_LS_CLK_HZ 6000 +#define EMAC0_CLK_HZ 25000 +#define EMAC1_CLK_HZ 25000 +#define EMAC2_CLK_HZ 25000 +#define EOSC1_CLK_HZ +#define F2H_FREE_CLK_HZ 2 +#define H2F_USER0_CLK_HZ 2 +#define H2F_USER1_CLK_HZ 1 +#define L3_MAIN_FREE_CLK_HZ 2 +#define SDMMC_CLK_HZ 2 +#define TPIU_CLK_HZ 1 +#define MAINPLLGRP_CNTR15CLK_CNT 900 +#define MAINPLLGRP_CNTR2CLK_CNT 900 +#define MAINPLLGRP_CNTR3CLK_CNT 900 +#define MAINPLLGRP_CNTR4CLK_CNT 900 +#define MAINPLLGRP_CNTR5CLK_CNT 900 +#define MAINPLLGRP_CNTR6CLK_CNT 7 +#define MAINPLLGRP_CNTR7CLK_CNT 7 +#define MAINPLLGRP_CNTR7CLK_SRC 0 +#define MAINPLLGRP_CNTR8CLK_CNT 15 +#define MAINPLLGRP_CNTR9CLK_CNT 900 +#define MAINPLLGRP_CNTR9CLK_SRC 0 +#define MAINPLLGRP_MPUCLK_CNT 0 +#define MAINPLLGRP_MPUCLK_SRC 0 +#define MAINPLLGRP_NOCCLK_CNT 0 +#define MAINPLLGRP_NOCCLK_SRC 0 +#define MAINPLLGRP_NOCDIV_CSATCLK 0 +#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1 +#define MAINPLLGRP_NOCDIV_CSTRACECLK 0 +#define MAINPLLGRP_NOCDIV_L4MAINCLK 0 +#define MAINPLLGRP_NOCDIV_L4MPCLK 1 +#define MAINPLLGRP_NOCDIV_L4SPCLK 2 +#define MAINPLLGRP_VCO0_PSRC 0 +#define MAINPLLGRP_VCO1_DENOM 32 +#define MAINPLLGRP_VCO1_NUMER 1584 +#define PERPLLGRP_CNTR2CLK_CNT 5 +#define PERPLLGRP_CNTR2CLK_SRC 1 +#define PERPLLGRP_CNTR3CLK_CNT 900 +#define PERPLLGRP_CNTR3CLK_SRC 1 +#define PERPLLGRP_CNTR4CLK_CNT 14 +#define PERPLLGRP_CNTR4CLK_SRC 1 +#define PERPLLGRP_CNTR5CLK_CNT 374 +#define PERPLLGRP_CNTR5CLK_SRC 1 +#define PERPLLGRP_CNTR6CLK_CNT 900 +#define PERPLLGRP_CNTR6CLK_SRC 0 +#define PERPLLGRP_CNTR7CLK_CNT 900 +#define PERPLLGRP_CNTR8CLK_CNT 900 +#define PERPLLGRP_CNTR8CLK_SRC 0 +#define PERPLLGRP_CNTR9CLK_CNT 900 +#define PERPLLGRP_EMACCTL_EMAC0SEL 0 +#define PERPLLGRP_EMACCTL_EMAC1SEL 0 +#define PERPLLGRP_EMACCTL_EMAC2SEL 0 +#define PERPLLGRP_GPIODIV_GPIODBCLK 32000 +#define PERPLLGRP_VCO0_PSRC 0 +#define PERPLLGRP_VCO1_DENOM 32 +#define PERPLLGRP_VCO1_NUMER 1485 +#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16 +#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8 +#define CLKMGR_TESTIOCTRL_PERICLKSEL 8 +#define ALTERAGRP_MPUCLK_MAINCNT 1 +#define ALTERAGRP_MPUCLK_PERICNT 900 +#define ALTERAGRP_NOCCLK_MAINCNT 7 +#define ALTERAGRP_NOCCLK_PERICNT 900 +#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \ + (ALTERAGRP_MPUCLK_MAINCNT)) +#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \ + (ALTERAGRP_NOCCLK_MAINCNT)) + +/* Pin Mux Configuration */ +#define CONFIG_IO_10_INPUT_BUF_EN 1 +#define CONFIG_IO_10_PD_DRV_STRG 10 +#define CONFIG_IO_10_PD_SLW_RT 1 +#define CONFIG_IO_10_PU_DRV_STRG 8 +#define CONFIG_IO_10_PU_SLW_RT 1 +#define CONFIG_IO_10_RTRIM 1 +#define CONFIG_IO_10_WK_PU_EN 0 +#define CONFIG_IO_11_INPUT_BUF_EN 1 +#define CONFIG_IO_11_PD_DRV_STRG 10 +#define CONFIG_IO_11_PD_SLW_RT 1 +#define CONFIG_IO_11_PU_DRV_STRG 8 +#define CONFIG_IO_11_PU_SLW_RT 1 +#define CONFIG_IO_11_RTRIM 1 +#define CONFIG_IO_11_WK_PU_EN 0 +#define CONFIG_IO_12_INPUT_BUF_EN 0 +#define CONFIG_IO_12_PD_DRV_STRG 0 +#define CONFIG_IO_12_PD_SLW_RT 0 +#define CONFIG_IO_12_PU_DRV_STRG 0 +#define CONFIG_IO_12_PU_SLW_RT 0 +#define CONFIG_IO_12_RTRIM 1 +#define CONFIG_IO_12_WK_PU_EN 1 +#define CONFIG_IO_13_INPUT_BUF_EN 0 +#define CONFIG_IO_13_PD_DRV_STRG 0 +#define CONFIG_IO_13_PD_SLW_RT 0 +#define CONFIG_IO_13_PU_DRV_STRG 0 +#define CONFIG_IO_13_PU_SLW_RT 0 +#define CONFIG_IO_13_RTRIM 1 +#define CONFIG_IO_13_WK_PU_EN 1 +#define CONFIG_IO_14_INPUT_BUF_EN 0 +#define CONFIG_IO_14_PD_DRV_STRG 0 +#define CONFIG_IO_14_PD_SLW_RT 0 +#define CONFIG_IO_14_PU_DRV_STRG 0 +#define CONFIG_IO_14_PU_SLW_RT 0 +#define CONFIG_IO_14_RTRIM 1 +#define CONFIG_IO_14_WK_PU_EN 1 +#define CONFIG_IO_15_INPUT_BUF_EN 0 +#define CONFIG_IO_15_PD_DRV_STRG 0 +#define CONFIG_IO_15_PD_SLW_RT 0 +#define CONFIG_IO_15_PU_DRV_STRG 0 +#define CONFIG_IO_15_PU_SLW_RT 0 +#define CONFIG_IO_15_RTRIM 1 +#define CONFIG_IO_15_WK_PU_EN 1 +#define CONFIG_IO_16_INPUT_BUF_EN 0 +#define CONFIG_IO_16_PD_DRV_STRG 10 +#define CONFIG_IO_16_PD_SLW_RT 1 +#define
[PATCH v2 00/11] Add Chameleon v3 support
The Google Chameleon v3 is a board made for testing both video and audio interfaces of external devices. It has a connector compatible with the Mercury+ AA1 module, which itself contains an Arria 10 SoCFPGA. The AA1 module comes in a few different configurations, the Chameleon V3 supports ME-AA1-270-3E4-D11 and ME-AA1-480-2I3-D12E. This patchset adds support for the Chameleon v3 (both versions), as well as some bugfixes and optimizations, mostly in Arria 10 code. V2: Adjust devicetrees so that they work both in u-boot and linux Put u-boot-specific parts of devicetrees into *-u-boot.dtsi files Minor changes in Kconfig, defconfig, and config.h Paweł Anikiel (11): arm: dts: Add Mercury+ AA1 devicetrees arm: dts: Add Chameleonv3 handoff headers arm: dts: Add Chameleonv3 devicetrees board: Add Chameleonv3 board dir config: Add Chameleonv3 config misc: atsha204a: Increase wake delay by tWHI sysreset: socfpga: Use parent device for reading base address socfpga: arria10: Replace delays with busy waiting in cm_full_cfg socfpga: arria10: Improve bitstream loading speed socfpga: arria10: Wait for fifo empty after writing bitstream socfpga: arria10: Allow dcache_enable before relocation arch/arm/dts/Makefile | 2 + arch/arm/dts/socfpga_arria10_chameleonv3.dts | 90 ++ ...fpga_arria10_chameleonv3_270_3-u-boot.dtsi | 8 + .../dts/socfpga_arria10_chameleonv3_270_3.dts | 5 + ...ocfpga_arria10_chameleonv3_270_3_handoff.h | 305 ++ ...fpga_arria10_chameleonv3_480_2-u-boot.dtsi | 8 + .../dts/socfpga_arria10_chameleonv3_480_2.dts | 5 + ...ocfpga_arria10_chameleonv3_480_2_handoff.h | 305 ++ .../socfpga_arria10_mercury_aa1-u-boot.dtsi | 54 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi | 72 + arch/arm/mach-socfpga/Kconfig | 7 + arch/arm/mach-socfpga/clock_manager.c | 7 +- arch/arm/mach-socfpga/clock_manager_arria10.c | 12 +- .../mach-socfpga/include/mach/clock_manager.h | 4 + arch/arm/mach-socfpga/misc_arria10.c | 26 ++ board/google/chameleonv3/Makefile | 5 + board/google/chameleonv3/board.c | 27 ++ board/google/chameleonv3/fpga.its | 28 ++ board/google/chameleonv3/fpga_early_io.its| 35 ++ board/google/chameleonv3/mercury_aa1.c| 43 +++ board/google/chameleonv3/mercury_aa1.h| 12 + configs/socfpga_chameleonv3_defconfig | 29 ++ drivers/fpga/socfpga_arria10.c| 28 +- drivers/misc/atsha204a-i2c.c | 5 +- drivers/sysreset/sysreset_socfpga.c | 2 +- include/configs/socfpga_chameleonv3.h | 44 +++ 26 files changed, 1154 insertions(+), 14 deletions(-) create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3.dts create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi create mode 100644 board/google/chameleonv3/Makefile create mode 100644 board/google/chameleonv3/board.c create mode 100644 board/google/chameleonv3/fpga.its create mode 100644 board/google/chameleonv3/fpga_early_io.its create mode 100644 board/google/chameleonv3/mercury_aa1.c create mode 100644 board/google/chameleonv3/mercury_aa1.h create mode 100644 configs/socfpga_chameleonv3_defconfig create mode 100644 include/configs/socfpga_chameleonv3.h -- 2.36.1.124.g0e6072fb45-goog
[PATCH 1/2] mmc: Add support for wait_dat0 callback
There is no wait_dat0 mmc ops, causing operations waiting for data
line state change (e.g mmc_switch_voltage) to fallback to a 250ms
active delay. mmc_ops still used when DM_MMC is not enabled, which
is often the case for SPL. The result can be unexpectly long SPL
boot time.
This change adds support for wait_dat0() mmc operation.
Signed-off-by: Loic Poulain
---
drivers/mmc/mmc.c | 3 +++
include/mmc.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index f6ccd83..109f340 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -34,6 +34,9 @@ static int mmc_set_signal_voltage(struct mmc *mmc, uint
signal_voltage);
static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
{
+ if (mmc->cfg->ops->wait_dat0)
+ return mmc->cfg->ops->wait_dat0(mmc, state, timeout_us);
+
return -ENOSYS;
}
diff --git a/include/mmc.h b/include/mmc.h
index 6bdcce8..b7e94e8 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -561,6 +561,7 @@ struct mmc_ops {
int (*getwp)(struct mmc *mmc);
int (*host_power_cycle)(struct mmc *mmc);
int (*get_b_max)(struct mmc *mmc, void *dst, lbaint_t blkcnt);
+ int (*wait_dat0)(struct mmc *mmc, int state, int timeout_us);
};
static inline int mmc_hs400_prepare_ddr(struct mmc *mmc)
--
2.7.4
[PATCH 2/2] mmc: fsl_esdhc_imx: Implement wait_dat0 mmc ops
Implement wait_dat0 mmc ops callbac, allowing to reduce SPL boot time.
Before (using grabserial):
[0.01 0.01] U-Boot SPL 2021.04-
[0.028257 0.028257] DDRINFO: start DRAM init
[0.028500 0.000243] DDRINFO: DRAM rate 3000MTS
[0.304627 0.276127] DDRINFO:ddrphy calibration done
[0.305647 0.001020] DDRINFO: ddrmix config done
[0.352584 0.046937] SEC0: RNG instantiated
[0.374299 0.021715] Normal Boot
[0.374675 0.000376] Trying to boot from MMC2
[1.250580 0.875905] NOTICE: BL31: v2.4(release):lf-5.10.72-2.2.0-0-g5782363f9
[1.251985 0.001405] NOTICE: BL31: Built : 08:02:40, Apr 12 2022
[1.522560 0.270575]
[1.522734 0.000174]
[1.522788 0.54] U-Boot 2021.04-
After:
[0.01 0.01] U-Boot SPL 2021.04-
[0.001614 0.001614] DDRINFO: start DRAM init
[0.002377 0.000763] DDRINFO: DRAM rate 3000MTS
[0.278494 0.276117] DDRINFO:ddrphy calibration done
[0.279266 0.000772] DDRINFO: ddrmix config done
[0.338432 0.059166] SEC0: RNG instantiated
[0.339051 0.000619] Normal Boot
[0.339431 0.000380] Trying to boot from MMC2
[0.412587 0.073156] NOTICE: BL31: v2.4(release):lf-5.15.5-1.0.0-0-g05f788b
[0.414191 0.001604] NOTICE: BL31: Built : 10:35:26, Apr 6 2022
[0.700685 0.286494]
[0.700793 0.000108]
[0.700845 0.52] U-Boot 2021.04-
Signed-off-by: Loic Poulain
---
drivers/mmc/fsl_esdhc_imx.c | 50 ++---
1 file changed, 33 insertions(+), 17 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 02208a5..ec52f93 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -1060,6 +1060,30 @@ static int esdhc_getcd_common(struct fsl_esdhc_priv
*priv)
return timeout > 0;
}
+static int esdhc_wait_dat0_common(struct fsl_esdhc_priv *priv, int state,
+ int timeout_us)
+{
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ int ret, err;
+ u32 tmp;
+
+ /* make sure the card clock keep on */
+ esdhc_setbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+
+ ret = readx_poll_timeout(esdhc_read32, >prsstat, tmp,
+ !!(tmp & PRSSTAT_DAT0) == !!state,
+ timeout_us);
+
+ /* change to default setting, let host control the card clock */
+ esdhc_clrbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+
+ err = readx_poll_timeout(esdhc_read32, >prsstat, tmp, tmp &
PRSSTAT_SDOFF, 100);
+ if (err)
+ pr_warn("card clock not gate off as expect.\n");
+
+ return ret;
+}
+
static int esdhc_reset(struct fsl_esdhc *regs)
{
ulong start;
@@ -1109,11 +1133,19 @@ static int esdhc_set_ios(struct mmc *mmc)
return esdhc_set_ios_common(priv, mmc);
}
+static int esdhc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
+{
+ struct fsl_esdhc_priv *priv = mmc->priv;
+
+ return esdhc_wait_dat0_common(priv, state, timeout_us);
+}
+
static const struct mmc_ops esdhc_ops = {
.getcd = esdhc_getcd,
.init = esdhc_init,
.send_cmd = esdhc_send_cmd,
.set_ios= esdhc_set_ios,
+ .wait_dat0 = esdhc_wait_dat0,
};
#endif
@@ -1576,25 +1608,9 @@ static int __maybe_unused
fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
static int fsl_esdhc_wait_dat0(struct udevice *dev, int state,
int timeout_us)
{
- int ret, err;
- u32 tmp;
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
- struct fsl_esdhc *regs = priv->esdhc_regs;
- /* make sure the card clock keep on */
- esdhc_setbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
-
- ret = readx_poll_timeout(esdhc_read32, >prsstat, tmp,
- !!(tmp & PRSSTAT_DAT0) == !!state,
- timeout_us);
-
- /* change to default setting, let host control the card clock */
- esdhc_clrbits32(>vendorspec, VENDORSPEC_FRC_SDCLK_ON);
- err = readx_poll_timeout(esdhc_read32, >prsstat, tmp, tmp &
PRSSTAT_SDOFF, 100);
- if (err)
- dev_warn(dev, "card clock not gate off as expect.\n");
-
- return ret;
+ return esdhc_wait_dat0_common(priv, state, timeout_us);
}
static const struct dm_mmc_ops fsl_esdhc_ops = {
--
2.7.4
Re: [u-boot PATCH 3/3] k3-am642-evm-u-boot: Use binman to generate u-boot.img and tispl.bin
On Thu, May 26, 2022 at 10:28:45AM +0300, Roger Quadros wrote:
> On 25/05/2022 18:14, Andrew Davis wrote:
> > On 5/25/22 3:30 AM, Roger Quadros wrote:
> >> Hi Andrew,
> >>
> >> On 25/05/2022 01:03, Andrew Davis wrote:
> >>> On 5/9/22 2:29 AM, Roger Quadros wrote:
> Introduce k3-am642-evm-binman.dtsi to provide binman configuration.
>
> R5 build is still not converted to use binman so restrict binman.dtsi
> to A53 builds only.
>
> This patch also take care of building Secure (HS) images using
> binman instead of tools/k3_fit_atf.sh if CONFIG_BINMAN is set.
>
> Signed-off-by: Roger Quadros
> ---
> arch/arm/dts/k3-am642-evm-binman.dtsi | 230 ++
> arch/arm/dts/k3-am642-evm-u-boot.dtsi | 3 +
> arch/arm/mach-k3/Kconfig | 1 +
> arch/arm/mach-k3/config.mk | 7 +
> 4 files changed, 241 insertions(+)
> create mode 100644 arch/arm/dts/k3-am642-evm-binman.dtsi
>
> diff --git a/arch/arm/dts/k3-am642-evm-binman.dtsi
> b/arch/arm/dts/k3-am642-evm-binman.dtsi
> new file mode 100644
> index 00..9e85ef41b0
> --- /dev/null
> +++ b/arch/arm/dts/k3-am642-evm-binman.dtsi
> @@ -0,0 +1,230 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2021 Texas Instruments Incorporated -
> https://www.ti.com/
> + */
> +
> +/ {
> + binman: binman {
> + multiple-images;
> + };
> +};
> +
> +#ifdef CONFIG_TARGET_AM642_A53_EVM
> +
> +#ifdef CONFIG_TI_SECURE_DEVICE
> +#define TISPL "tispl.bin_HS"
> +#define UBOOT_IMG "u-boot.img_HS"
> +#else
> +#define TISPL "tispl.bin"
> +#define UBOOT_IMG "u-boot.img"
> +#endif
> +
> +#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
> +#define SPL_AM642_EVM_DTB "spl/dts/k3-am642-evm.dtb"
> +#define SPL_AM642_SK_DTB "spl/dts/k3-am642-sk.dtb"
> +
> +#define UBOOT_NODTB "u-boot-nodtb.bin"
> +#define AM642_EVM_DTB "arch/arm/dts/k3-am642-evm.dtb"
> +#define AM642_SK_DTB "arch/arm/dts/k3-am642-sk.dtb"
> +
> + {
> + ti-spl {
> + filename = TISPL;
> + pad-byte = <0xff>;
> +
> + fit {
> + description = "Configuration to load ATF and SPL";
> + #address-cells = <1>;
> +
> + images {
> +
> + atf {
> + description = "ARM Trusted Firmware";
> + type = "firmware";
> + arch = "arm64";
> + compression = "none";
> + os = "arm-trusted-firmware";
> + load = ;
> + entry = ;
> + atf-bl31 {
> + filename = "bl31.bin";
> + };
> >>>
> >>>
> >>> On HS, bl31.bin and the below TEE and DM images must also be signed
> >>> before being packaged into tispl.bin.
> >>> Can we add signing here?
> >>
> >> I'm wondering how this is working as is on HS boards.
> >>
> >
> >
> > Today we manually sign those two before we feed them to U-Boot build.
> > I'd like to fix that and have them signed along with all the other
> > parts here when packaging them together.
> >
>
> OK. Then this is new feature. Do you mind if I make a separate patch for it?
> But first I need to figure out what to do ;)
>
> >
> >> Another thing to note is that the atf and tee entries take into
> >> consideration
> >> the below environment variables
> >> -a atf-bl31-path=${BL31} \
> >> -a tee-os-path=${TEE} \
> >>
> >> How do we continue to support that while adding the signing bits?
> >>
> >
> >
> > That's my question also, I'm not sure how we would make the type 'ti-secure'
> > while also changing their path names, seems like a limitation currently
> > of using etypes to do the signing, since we can do path renames from
> > command line.
>
> Simon,
>
> Any thoughts on how to get the new ti-secure etype work with atf-bl31 and
> tee-os etypes so that it can take the data output of those entries and create
> a signed binary with filenames from those entries or atf-bl31-path and
> tee-os-path?
>
> Can something like this work?
>
> ti-secure {
> atf-bl31 {
> filename = "bl31.bin";
> };
> }
>
> We could probably get rid of filename property from ti-secure etype and use
> blob for regular files.
>
> ti-secure {
> blob {
> filename = "somefile.ext";
> }
> }
Adding in Alper as well..
>
> cheers,
> -roger
>
> >
> > Andrew
> >
> >
> >> cheers,
> >> -roger
> >>
> >>>
> >>> Andrew
> >>>
> >>>
> + };
> +
> + tee {
> +
[PATCH v2] net: Check for the minimum IP fragmented datagram size
From: Fabio Estevam
Nicolas Bidron and Nicolas Guigo reported the two bugs below:
"
--BUG 1--
In compiled versions of U-Boot that define CONFIG_IP_DEFRAG, a value of
`ip->ip_len` (IP packet header's Total Length) higher than `IP_HDR_SIZE`
and strictly lower than `IP_HDR_SIZE+8` will lead to a value for `len`
comprised between `0` and `7`. This will ultimately result in a
truncated division by `8` resulting value of `0` forcing the hole
metadata and fragment to point to the same location. The subsequent
memcopy will overwrite the hole metadata with the fragment data. Through
a second fragment, this can be exploited to write to an arbitrary offset
controlled by that overwritten hole metadata value.
This bug is only exploitable locally as it requires crafting two packets
the first of which would most likely be dropped through routing due to
its unexpectedly low Total Length. However, this bug can potentially be
exploited to root linux based embedded devices locally.
```C
static struct ip_udp_hdr *__net_defragment(struct ip_udp_hdr *ip, int *lenp)
{
static uchar pkt_buff[IP_PKTSIZE] __aligned(PKTALIGN);
static u16 first_hole, total_len;
struct hole *payload, *thisfrag, *h, *newh;
struct ip_udp_hdr *localip = (struct ip_udp_hdr *)pkt_buff;
uchar *indata = (uchar *)ip;
int offset8, start, len, done = 0;
u16 ip_off = ntohs(ip->ip_off);
/* payload starts after IP header, this fragment is in there */
payload = (struct hole *)(pkt_buff + IP_HDR_SIZE);
offset8 = (ip_off & IP_OFFS);
thisfrag = payload + offset8;
start = offset8 * 8;
len = ntohs(ip->ip_len) - IP_HDR_SIZE;
```
The last line of the previous excerpt from `u-boot/net/net.c` shows how
the attacker can control the value of `len` to be strictly lower than
`8` by issuing a packet with `ip_len` between `21` and `27`
(`IP_HDR_SIZE` has a value of `20`).
Also note that `offset8` here is `0` which leads to `thisfrag = payload`.
```C
} else if (h >= thisfrag) {
/* overlaps with initial part of the hole: move this hole */
newh = thisfrag + (len / 8);
*newh = *h;
h = newh;
if (h->next_hole)
payload[h->next_hole].prev_hole = (h - payload);
if (h->prev_hole)
payload[h->prev_hole].next_hole = (h - payload);
else
first_hole = (h - payload);
} else {
```
Lower down the same function, execution reaches the above code path.
Here, `len / 8` evaluates to `0` leading to `newh = thisfrag`. Also note
that `first_hole` here is `0` since `h` and `payload` point to the same
location.
```C
/* finally copy this fragment and possibly return whole packet */
memcpy((uchar *)thisfrag, indata + IP_HDR_SIZE, len);
```
Finally, in the above excerpt the `memcpy` overwrites the hole metadata
since `thisfrag` and `h` both point to the same location. The hole
metadata is effectively overwritten with arbitrary data from the
fragmented IP packet data. If `len` was crafted to be `6`, `last_byte`,
`next_hole`, and `prev_hole` of the `first_hole` can be controlled by
the attacker.
Finally the arbitrary offset write occurs through a second fragment that
only needs to be crafted to write data in the hole pointed to by the
previously controlled hole metadata (`next_hole`) from the first packet.
### Recommendation
Handle cases where `len` is strictly lower than 8 by preventing the
overwrite of the hole metadata during the memcpy of the fragment. This
could be achieved by either:
* Moving the location where the hole metadata is stored when `len` is
lower than `8`.
* Or outright rejecting fragmented IP datagram with a Total Length
(`ip_len`) lower than 28 bytes which is the minimum valid fragmented IP
datagram size (as defined as the minimum fragment of 8 octets in the IP
Specification Document:
[RFC791](https://datatracker.ietf.org/doc/html/rfc791) page 25).
--BUG 2--
In compiled versions of U-Boot that define CONFIG_IP_DEFRAG, a value of
`ip->ip_len` (IP packet header's Total Length) lower than `IP_HDR_SIZE`
will lead to a negative value for `len` which will ultimately result in
a buffer overflow during the subsequent `memcpy` that uses `len` as it's
`count` parameter.
This bug is only exploitable on local ethernet as it requires crafting
an invalid packet to include an unexpected `ip_len` value in the IP UDP
header that's lower than the minimum accepted Total Length of a packet
(21 as defined in the IP Specification Document:
[RFC791](https://datatracker.ietf.org/doc/html/rfc791)). Such packet
would in all likelihood be dropped while being routed to its final
destination through most routing equipment and as such requires the
attacker to be in a local position in order to be exploited.
```C
static struct ip_udp_hdr *__net_defragment(struct ip_udp_hdr *ip, int *lenp)
{
static uchar pkt_buff[IP_PKTSIZE] __aligned(PKTALIGN);
static u16 first_hole,
Re: Pull request for efi-2022-07-rc4
On Thu, May 26, 2022 at 07:13:01PM +0900, Masahisa Kojima wrote: > Hi Heinrich, Tom, > > On Thu, 26 May 2022 at 18:56, Heinrich Schuchardt wrote: > > > > Dear Tom, > > > > The following changes since commit 7e0edcadb09d55d5319fdc862041fd1b874476f5: > > > >Merge branch 'master' of > > https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-05-24 > > 23:29:00 -0400) > > > > are available in the Git repository at: > > > >https://source.denx.de/u-boot/custodians/u-boot-efi.git > > tags/efi-2022-07-rc4 > > > > for you to fetch changes up to 019ba3a6a644cceba46d92d42a1ed0677885a929: > > > >doc/build/gcc: add more required packages (2022-05-26 10:15:58 +0200) > > > > Gitlab CI showed no problems: > > https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/12127 > > > > > > Pull request for efi-2022-07-rc4 > > > > UEFI: > > > > * fix a problem in loading an image from a short-path > > * fix building the bootmenu command for CONFIG_EFI_LOADER=n > > * correct the bootefi command syntax > > * add firmware management protocol to the documentation > > > > Others: > > > > * bootmenu: fix bootmenu title handling > > > > > > AKASHI Takahiro (2): > >efi_loader: disk: add efi_disk_is_removable() > >efi_loader: bootmgr: fix a problem in loading an image from a > > short-path > > > > Bin Meng (2): > >doc: sandbox: Correct the memory size config option > >doc: sandbox: Add a note of disabling LTO when using gdb > > > > Heinrich Schuchardt (6): > >disk: incorrect message in is_gpt_valid() > >test: restore timeout after bootmenu unit test > >test: fix pylint warnings in test_efi_selftest.py > >test: don't change console timeout in EFI selftest. > >cmd/bootefi: correct command syntax > >doc/build/gcc: add more required packages > > > > Masahisa Kojima (2): > >bootmenu: fix bootmenu title handling > > I have sent the revised version of the patch. > Could you ignore "bootmenu: fix bootmenu title handling" > and apply the revised patch here? > https://patchwork.ozlabs.org/project/uboot/patch/20220526100938.9558-2-masahisa.koj...@linaro.org/ I'll wait for an updated PR, thanks. -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/3] misc: i2c_eeprom: remove 24aa02e48
Am 2022-05-26 16:04, schrieb Eugen Hristev:
This compatible does not exist in the bindings.
All occurences in DT have been replaced by at24c02 which is equivalent.
Fixes: 7264066707 ("misc: i2c_eeprom: Add compatible for 24AA02E48")
Signed-off-by: Eugen Hristev
Reviewed-by: Michael Walle
-michael
Re: [PATCH 1/3] ARM: dts: at91: replace microchip,24aa02e48 with atmel,at24c02
Am 2022-05-26 16:04, schrieb Eugen Hristev:
microchip,24aa025e48 does not exist in the bindings of this driver.
It can be replaced with atmel,at24c02 which is a standard compatible
and the memory is compatible with this one, depending on the page size.
microchip 24aa02e48 has a page size of 8, while 24aa025e48 has a page
size of 16 bytes.
Nice. Thanks for taking care! One minor nit below.
Signed-off-by: Eugen Hristev
Reviewed-by: Michael Walle
---
arch/arm/dts/at91-sama5d2_icp.dts | 6 +++---
arch/arm/dts/at91-sama7g5ek.dts | 4 ++--
arch/arm/dts/sama5d27_som1.dtsi | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/at91-sama5d2_icp.dts
b/arch/arm/dts/at91-sama5d2_icp.dts
index 44522197ff..0b0db1b2be 100644
--- a/arch/arm/dts/at91-sama5d2_icp.dts
+++ b/arch/arm/dts/at91-sama5d2_icp.dts
@@ -68,19 +68,19 @@
status = "okay";
eeprom@50 {
- compatible = "microchip,24aa02e48";
+ compatible = "atmel,24c02"; /* EEPROM
is 2Kbits microchip
24aa025e48, an at24c02 with page size of 16 */
reg = <0x50>;
pagesize = <16>;
};
eeprom@52 {
- compatible = "microchip,24aa02e48";
+ compatible = "atmel,24c02"; /* EEPROM
is 2Kbits microchip
24aa025e48, an at24c02 with page size of 16 */
reg = <0x52>;
pagesize = <16>;
};
eeprom@53 {
- compatible = "microchip,24aa02e48";
+ compatible = "atmel,24c02"; /* EEPROM
is 2Kbits microchip
24aa025e48, an at24c02 with page size of 16 */
reg = <0x53>;
pagesize = <16>;
};
diff --git a/arch/arm/dts/at91-sama7g5ek.dts
b/arch/arm/dts/at91-sama7g5ek.dts
index 086ee45005..eaba0de3f7 100644
--- a/arch/arm/dts/at91-sama7g5ek.dts
+++ b/arch/arm/dts/at91-sama7g5ek.dts
@@ -405,13 +405,13 @@
status = "okay";
eeprom@52 {
- compatible = "microchip,24aa02e48";
+ compatible = "atmel,24c02"; /* EEPROM is 2Kbits
microchip
24aa025e48, an at24c02 with page size of 16 */
reg = <0x52>;
pagesize = <16>;
};
eeprom@53 {
- compatible = "microchip,24aa02e48";
+ compatible = "atmel,24c02"; /* EEPROM is 2Kbits
microchip
24aa025e48, an at24c02 with page size of 16 */
reg = <0x53>;
pagesize = <16>;
};
diff --git a/arch/arm/dts/sama5d27_som1.dtsi
b/arch/arm/dts/sama5d27_som1.dtsi
index ea7540bcfc..db4fefadcd 100644
--- a/arch/arm/dts/sama5d27_som1.dtsi
+++ b/arch/arm/dts/sama5d27_som1.dtsi
@@ -92,7 +92,7 @@
status = "okay";
i2c_eeprom: i2c_eeprom@50 {
Nit: that one should actually be just "eeprom@50".
-michael
- compatible = "microchip,24aa02e48";
+ compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip
24aa02e48 */
reg = <0x50>;
};
};
Re: Raspberry Pi won’t boot from compressed subvolume (BTRFS)
Hi Matthias, thanks for your time and response.
> Just a random guess, but bcn2837-rpi-3-b.dtb does look right, the DTB should
> be
> called bcm2837-rpi-3-b.dtb
Sorry, that was an OCR error (wasn't sure how to screenshot or log to
a file in this context, so pictures -> OCR seemed like my best option,
pictures available here:
https://discourse.nixos.org/t/btrfs-pi-wont-boot-from-compressed-subvolume/18462/2?u=n8henrie).
It is indeed `bc*m*`... in the actual output.
> Then you try to fixup that address which has no valid DTB and fails.
>
> Anyway to me that sounds like a nixOS problem rather then a U-Boot problem.
> I'm
> not even sure which version of U-Boot you are using and if it has any patches
> on
> top of the upstream version.
Sorry, I included the link to the relevant code
(https://github.com/NixOS/nixpkgs/blob/3d4e586313d292c9e764a8e88a1fdccb16ffb2d3/pkgs/misc/uboot/default.nix)
but should have included those details:
```
defaultSrc = fetchurl {
url = "ftp://ftp.denx.de/pub/u-boot/u-boot-${defaultVersion}.tar.bz2;;
hash = "sha256-gbRUMifbIowD+KG/XdvIE7C7j2VVzkYGTvchpvxoBBM=";
defaultVersion = "2022.01";
```
By default it will have two patches:
-
https://github.com/NixOS/nixpkgs/blob/master/pkgs/misc/uboot/0001-configs-rpi-allow-for-bigger-kernels.patch
-
https://github.com/NixOS/nixpkgs/blob/master/pkgs/misc/uboot/0001-rpi-Copy-properties-from-firmware-dtb-to-the-loaded-.patch
The latter looks like it might be relevant.
I was suspicious about it being a u-boot issue because everything
works fine by default, it's only when I enable zstd compression that I
get the above errors. However I'm pretty new to NixOS and obviously
know little about u-boot, so you may well be correct!
Nate
On Wed, May 25, 2022 at 2:58 AM Matthias Brugger wrote:
>
>
>
> On 22/05/2022 17:36, Nathan Henrie wrote:
> > Hello u-boot team,
> >
> > I’ve been experimenting for about a year with a NixOS-based Raspberry Pi
> > image, with the end goal of a zstd-compressed image that uses BTRFS
> > subvolumes, having the root filesystem at @ and boot at @boot (with several
> > other subvolumes). The NixOS Raspberry Pi images use u-boot by default.
> > I’ve started a few discussions in the NixOS community as I learn and
> > iterate:
> > https://discourse.nixos.org/t/raspberry-pi-nixos-on-btrfs-root/14081 and
> > I’ve made my code available at: https://github.com/n8henrie/nixos-btrfs-pi
> > . I’m sure it’s obvious (or will be soon) that I’m a hobbyist, a novice
> > with NixOS, and that I understand very little about u-boot and bootloaders
> > in general, so I hope you can be patient as I humbly ask for someone to
> > point me in the right direction.
> >
> > For reference, the official NixOS code for generating u-boot images is
> > here:
> > https://github.com/NixOS/nixpkgs/blob/3d4e586313d292c9e764a8e88a1fdccb16ffb2d3/pkgs/misc/uboot/default.nix
> >
> > I’ve made a lot of progress, including an image that reliably boots from
> > @boot to the @ root subvolume with the u-boot configuration:
> >
> > CONFIG_CMD_BTRFS=y
> > CONFIG_ZSTD=y
> > CONFIG_BOOTCOMMAND="setenv boot_prefixes / /boot/ /@/ /@boot/; run
> > distro_bootcmd;"
> >
> > with kernel params: "root=LABEL=NIXOS_SD" "rootfstype=btrfs"
> > "rootflags=subvol=@"
> >
> > Unfortunately, after the initial boot and going through the initial OS
> > installation steps, if I have compression enabled, it reboots into a boot
> > loop with the following error messages:
> >
> > Scanning mmc 0:2...
> > Found /@boot/extlinux/extlinux.conf
> > Retrieving file: /@boot/extlinux/extlinux.conf
> > 2938 bytes read in 27 ms (105.5 KiB/s)
> >
> > 1 NixOS Default
> > 2 NixOS Configuration 4 (2022-02-24 21:34 22.05pre356135.7f9b6c2babf)
> > 3 NixOS Configuration 3 (2022-02-25 03:59 22.05pre356435.7/9b6eZbabf)
> > 4: NixOS Configuration 2 (2022-02-24 21:34 22.05pre356435.7/9b6c2babr)
> > 5: NixOS
> > Enter choice: 1: NixOS - Default
> > Retrieving file:
> > /@boot/extlinux/..nixos/zhbharzhzqga617uc37uk0g6q1bx891u-initrd-linux-5.10.101-initrd
> > 20588420 bytes read in 1910 ms (10.3 MiB/s)
> > Retrieving file:
> > /@boot/extlinux/..nixos/6c1m6j0k1gmjrmikOyyizariiry?Zlqr-linux-5.10.101-Image
> > 50629120 bytes read in 6863 ms (7 MiB/s)
> > append:
> > init-mix/store/pikl8ju4077iaix36n8mifzu6l6rcajz-nixos-system-nixpi-22.05p
> > re356435-7/9b6eZbabf/init console=tty1 console=ttyAMAO console=ttyS0,
> > 1115200 root= LABEL=-NIXOS_SD rootfstype=btrfs rootflags=subvol=@
> > loglevel=4
> > Retrieving file:
> > /@boot/extlinux/../nixos/6c16j0k1gmjrmikOyyizari1ry72lqr-linux-5.10.101-dtbs/broadcon/bcn2837-rpi-3-b.dtb
>
> Just a random guess, but bcn2837-rpi-3-b.dtb does look right, the DTB should
> be
> called bcm2837-rpi-3-b.dtb
>
> > 14310 bytes read in 66 ms (210.9 KiB/s)
> > Moving Image from 0x8 to 0x20, end=32f
> > ## Flattened Device Tree blob at 0370
> > Booting using the fdt blob at 0x370
> > Using Device Tree in place at 0370 end 037067e5
> >
[PATCH 04/11] arm: Use CONFIG_SPL_STACK or CONFIG_SYS_INIT_SP_ADDR directly.
In some cases, we define CONFIG_SYS_INIT_SP_ADDR differently for SPL or full U-Boot. This case should be making use of CONFIG_SPL_STACK, as that's what that variable is for. In a few other cases we define CONFIG_SPL_STACK directly to CONFIG_SYS_INIT_SP_ADDR, but do not need to as the code handles this correctly, normally. Signed-off-by: Tom Rini --- include/configs/imxrt1020-evk.h| 5 - include/configs/imxrt1050-evk.h| 5 - include/configs/sam9x60_curiosity.h| 5 + include/configs/sama5d27_som1_ek.h | 5 + include/configs/sama5d27_wlsom1_ek.h | 5 + include/configs/sama5d2_icp.h | 5 + include/configs/sama5d2_xplained.h | 5 + include/configs/sama5d3_xplained.h | 5 + include/configs/sama5d3xek.h | 5 + include/configs/sama5d4_xplained.h | 5 + include/configs/sama5d4ek.h| 5 + include/configs/sama7g5ek.h| 5 + include/configs/smartweb.h | 5 + include/configs/socfpga_soc64_common.h | 10 +++--- include/configs/stm32f746-disco.h | 5 - 15 files changed, 14 insertions(+), 66 deletions(-) diff --git a/include/configs/imxrt1020-evk.h b/include/configs/imxrt1020-evk.h index 79feab389e32..afae6a4e387a 100644 --- a/include/configs/imxrt1020-evk.h +++ b/include/configs/imxrt1020-evk.h @@ -24,12 +24,7 @@ * Configuration of the external SDRAM memory */ -/* For SPL */ -#ifdef CONFIG_SUPPORT_SPL -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SYS_SPL_LEN 0x8000 #define CONFIG_SYS_UBOOT_START 0x800023FD -#endif -/* For SPL ends */ #endif /* __IMXRT1020_EVK_H */ diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h index 5c2f975ba7f0..4b341a349c2f 100644 --- a/include/configs/imxrt1050-evk.h +++ b/include/configs/imxrt1050-evk.h @@ -31,12 +31,7 @@ * Configuration of the external SDRAM memory */ -/* For SPL */ -#ifdef CONFIG_SUPPORT_SPL -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SYS_SPL_LEN 0x8000 #define CONFIG_SYS_UBOOT_START 0x800023FD -#endif -/* For SPL ends */ #endif /* __IMXRT1050_EVK_H */ diff --git a/include/configs/sam9x60_curiosity.h b/include/configs/sam9x60_curiosity.h index 2708711a4ebc..aa3feb4a367d 100644 --- a/include/configs/sam9x60_curiosity.h +++ b/include/configs/sam9x60_curiosity.h @@ -20,12 +20,9 @@ #define CONFIG_SYS_SDRAM_BASE 0x2000 #define CONFIG_SYS_SDRAM_SIZE 0x800 /* 128 MB */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else +#define CONFIG_SPL_STACK 0x218000 #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 + CONFIG_SYS_MALLOC_F_LEN - \ GENERATED_GBL_DATA_SIZE) -#endif #endif diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h index eb29f211ef01..933dcace9d77 100644 --- a/include/configs/sama5d27_som1_ek.h +++ b/include/configs/sama5d27_som1_ek.h @@ -14,14 +14,11 @@ #undef CONFIG_SYS_AT91_MAIN_CLOCK #define CONFIG_SYS_AT91_MAIN_CLOCK 2400 /* from 24 MHz crystal */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR0x218000 -#else #define CONFIG_SYS_INIT_SP_ADDR \ (0x2200 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif /* SPL */ +#define CONFIG_SPL_STACK 0x218000 #define CONFIG_SPL_BSS_START_ADDR 0x2000 #define CONFIG_SYS_SPL_MALLOC_START0x2008 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x8 diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index 54ef48ce3edb..9bf7016acaf0 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -19,14 +19,11 @@ #define CONFIG_SYS_SDRAM_BASE 0x2000 #define CONFIG_SYS_SDRAM_SIZE 0x1000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR0x218000 -#else #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif /* SPL */ +#define CONFIG_SPL_STACK 0x218000 #define CONFIG_SPL_BSS_START_ADDR 0x2000 #define CONFIG_SYS_SPL_MALLOC_START0x2008 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x8 diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h index bd24d5743d45..09cc53ef122e 100644 --- a/include/configs/sama5d2_icp.h +++ b/include/configs/sama5d2_icp.h @@ -18,12 +18,9 @@ #define CONFIG_SYS_SDRAM_BASE 0x2000 #define CONFIG_SYS_SDRAM_SIZE 0x2000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR0x218000 -#else +#define CONFIG_SPL_STACK 0x218000 #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif #ifdef CONFIG_SD_BOOT /* u-boot env in
[PATCH 02/11] arm: pxa: Remove CONFIG_CPU_PXA25X
There are no platforms that set this, remove the code. Signed-off-by: Tom Rini --- arch/arm/cpu/pxa/Makefile |1 - arch/arm/cpu/pxa/cpuinfo.c |6 - arch/arm/cpu/pxa/start.S | 111 +- arch/arm/include/asm/arch-pxa/config.h |2 - arch/arm/include/asm/config.h |1 - drivers/mmc/pxa_mmc_gen.c |7 +- drivers/net/smc9.h | 152 +- drivers/serial/serial_pxa.c|1 - drivers/usb/gadget/Makefile|1 - drivers/usb/gadget/pxa25x_udc.c| 2049 drivers/usb/gadget/pxa25x_udc.h| 149 -- include/dm/platform_data/serial_pxa.h | 15 - include/lcd.h |3 +- 13 files changed, 6 insertions(+), 2492 deletions(-) delete mode 100644 drivers/usb/gadget/pxa25x_udc.c delete mode 100644 drivers/usb/gadget/pxa25x_udc.h diff --git a/arch/arm/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile index 263d9ddb4a01..fab77325c799 100644 --- a/arch/arm/cpu/pxa/Makefile +++ b/arch/arm/cpu/pxa/Makefile @@ -5,7 +5,6 @@ extra-y= start.o -obj-$(CONFIG_CPU_PXA25X) += pxa2xx.o obj-$(CONFIG_CPU_PXA27X) += pxa2xx.o obj-y += cpuinfo.o diff --git a/arch/arm/cpu/pxa/cpuinfo.c b/arch/arm/cpu/pxa/cpuinfo.c index 0d9542f998e4..549b61d6e0f9 100644 --- a/arch/arm/cpu/pxa/cpuinfo.c +++ b/arch/arm/cpu/pxa/cpuinfo.c @@ -11,12 +11,6 @@ #include #include -#ifdef CONFIG_CPU_PXA25X -#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xf800) -#error "Init SP address must be set to 0xf800 for PXA250" -#endif -#endif - #defineCPU_MASK_PXA_PRODID 0x03f0 #defineCPU_MASK_PXA_REVID 0x000f diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 896e05f1fda4..ab7bcb4e5625 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -49,9 +49,6 @@ reset: bl cpu_init_crit #endif -#ifdef CONFIG_CPU_PXA25X - bl lock_cache_for_stack -#endif #ifdef CONFIG_CPU_PXA27X /* * enable clock for SRAM @@ -67,20 +64,7 @@ reset: .globl c_runtime_cpu_setup c_runtime_cpu_setup: - -#ifdef CONFIG_CPU_PXA25X - /* -* Unlock (actually, disable) the cache now that board_init_f -* is done. We could do this earlier but we would need to add -* a new C runtime hook, whereas c_runtime_cpu_setup already -* exists. -* As this routine is just a call to cpu_init_crit, let us -* tail-optimize and do a simple branch here. -*/ - b cpu_init_crit -#else bx lr -#endif /* * @@ -92,7 +76,7 @@ c_runtime_cpu_setup: * * */ -#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) cpu_init_crit: /* * flush v4 I/D caches @@ -111,95 +95,4 @@ cpu_init_crit: mcr p15, 0, r0, c1, c0, 0 mov pc, lr /* back to my caller */ -#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || CONFIG_CPU_PXA25X */ - -/* - * Enable MMU to use DCache as DRAM. - * - * This is useful on PXA25x and PXA26x in early bootstages, where there is no - * other possible memory available to hold stack. - */ -#ifdef CONFIG_CPU_PXA25X -.macro CPWAIT reg - mrc p15, 0, \reg, c2, c0, 0 - mov \reg, \reg - sub pc, pc, #4 -.endm -lock_cache_for_stack: - /* Domain access -- enable for all CPs */ - ldr r0, =0x - mcr p15, 0, r0, c3, c0, 0 - - /* Point TTBR to MMU table */ - ldr r0, =mmutable - mcr p15, 0, r0, c2, c0, 0 - - /* Kick in MMU, ICache, DCache, BTB */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, #0x1b00 - bic r0, #0x0087 - orr r0, #0x1800 - orr r0, #0x0005 - mcr p15, 0, r0, c1, c0, 0 - CPWAIT r0 - - /* Unlock Icache, Dcache */ - mcr p15, 0, r0, c9, c1, 1 - mcr p15, 0, r0, c9, c2, 1 - - /* Flush Icache, Dcache, BTB */ - mcr p15, 0, r0, c7, c7, 0 - - /* Unlock I-TLB, D-TLB */ - mcr p15, 0, r0, c10, c4, 1 - mcr p15, 0, r0, c10, c8, 1 - - /* Flush TLB */ - mcr p15, 0, r0, c8, c7, 0 - - /* Allocate 4096 bytes of Dcache as RAM */ - - /* Drain pending loads and stores */ - mcr p15, 0, r0, c7, c10, 4 - - mov r4, #0x00 - mov r5, #0x00 - mov r2, #0x01 - mcr p15, 0, r0, c9, c2, 0 - CPWAIT r0 - - /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */ - mov r0, #128 - ldr r1, =0xf000 - -alloc: - mcr p15, 0, r1, c7, c2, 5 - /* Drain pending loads and stores */ - mcr p15, 0, r0, c7, c10, 4 - strdr4, [r1], #8 -
[PATCH 10/11] Introduce include/system-constants.h
We have a number of CONFIG symbols today that are of the form: SYM1 = CONST1 + CONST2 or other static math operations (shifts, etc). The issue is that by moving these to Kconfig we no longer have the ability to calculate these values, so they become less flexible and useful. It's also the case that sometimes a platform will just define SYM1 directly or perform a slightly different set of calculations. We introduce this header now to have a place to start to handle these cases. Signed-off-by: Tom Rini --- include/system-constants.h | 6 ++ 1 file changed, 6 insertions(+) create mode 100644 include/system-constants.h diff --git a/include/system-constants.h b/include/system-constants.h new file mode 100644 index ..4fd24f460993 --- /dev/null +++ b/include/system-constants.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __SYSTEM_CONSTANTS_H__ +#define __SYSTEM_CONSTANTS_H__ + +#endif -- 2.25.1
[PATCH 08/11] powerpc: Switch to using CONFIG_SYS_INIT_SP_OFFSET from CONFIG_SYS_GBL_DATA_OFFSET
In the places where PowerPC references CONFIG_SYS_GBL_DATA_OFFSET it
does so as (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET). And
it defines CONFIG_SYS_GBL_DATA_OFFSET in the same manner that other
architectures define CONFIG_SYS_INIT_SP_OFFSET. Other architectures
define CONFIG_SYS_INIT_SP_ADDR as (CONFIG_SYS_INIT_RAM_ADDR +
CONFIG_SYS_INIT_SP_OFFSET) typically. Rename things within PowerPC for
consistency with other architectures.
Signed-off-by: Tom Rini
---
README| 18 --
arch/powerpc/cpu/mpc83xx/cpu_init.c | 2 +-
arch/powerpc/cpu/mpc83xx/spl_minimal.c| 2 +-
arch/powerpc/cpu/mpc83xx/start.S | 4 ++--
arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 2 +-
arch/powerpc/cpu/mpc85xx/start.S | 4 ++--
include/configs/MPC837XERDB.h | 4 ++--
include/configs/MPC8548CDS.h | 4 ++--
include/configs/P1010RDB.h| 5 ++---
include/configs/P2041RDB.h| 5 ++---
include/configs/T102xRDB.h| 5 ++---
include/configs/T104xRDB.h| 5 ++---
include/configs/T208xQDS.h| 5 ++---
include/configs/T208xRDB.h| 5 ++---
include/configs/T4240RDB.h| 5 ++---
include/configs/corenet_ds.h | 4 ++--
include/configs/gazerbeam.h | 4 ++--
include/configs/ids8313.h | 6 ++
include/configs/km/km-mpc83xx.h | 4 ++--
include/configs/kmcent2.h | 5 ++---
include/configs/p1_p2_rdb_pc.h| 5 ++---
include/configs/qemu-ppce500.h| 5 ++---
include/configs/socrates.h| 4 ++--
23 files changed, 41 insertions(+), 71 deletions(-)
diff --git a/README b/README
index d6ff909e9a44..f79a7331b219 100644
--- a/README
+++ b/README
@@ -2130,24 +2130,6 @@ Low Level (hardware related) configuration options:
U-Boot uses the following memory types:
- MPC8xx: IMMR (internal memory of the CPU)
-- CONFIG_SYS_GBL_DATA_OFFSET:
-
- Offset of the initial data structure in the memory
- area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
- CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
- data is located at the end of the available space
- (sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
- GENERATED_GBL_DATA_SIZE), and the initial stack is just
- below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
- CONFIG_SYS_GBL_DATA_OFFSET) downward.
-
- Note:
- On the MPC824X (or other systems that use the data
- cache for initial memory) the address chosen for
- CONFIG_SYS_INIT_RAM_ADDR is basically arbitrary - it must
- point to an otherwise UNUSED address space between
- the top of RAM and the start of the PCI space.
-
- CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)
- CONFIG_SYS_OR_TIMING_SDRAM:
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c
b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index e6dcb8a33507..b2b259b1cbdf 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -138,7 +138,7 @@ void cpu_init_f (volatile immap_t * im)
0;
/* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+ gd = (gd_t *)CONFIG_SYS_INIT_SP_ADDR;
/* global data region was cleared in start.S */
diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c
b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
index 11b1e613fb90..6d4655f1adea 100644
--- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
@@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
void cpu_init_f (volatile immap_t * im)
{
/* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+ gd = (gd_t *)CONFIG_SYS_INIT_SP_ADDR;
/* global data region was cleared in start.S */
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index 7a01b16b75eb..b136456f5fec 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -229,8 +229,8 @@ in_flash:
/* set up the stack pointer in our newly created
* cache-ram; use r3 to keep the new SP for now to
* avoid overiding the SP it uselessly */
- lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
- ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR +
CONFIG_SYS_GBL_DATA_OFFSET)@l
+ lis r3, CONFIG_SYS_INIT_SP_ADDR@h
+ ori r3, r3, CONFIG_SYS_INIT_SP_ADDR@l
/* r4 = end of GD area */
addi r4, r3, GENERATED_GBL_DATA_SIZE
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
[PATCH 09/11] stih410-b2260: Switch to using GENERATED_GBL_DATA_SIZE
We have GENERATED_GBL_DATA_SIZE to tell us how large the generated global data is, so do not use a hard-coded value of 1024 for it. Signed-off-by: Tom Rini --- include/configs/stih410-b2260.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index fba93fd9d32c..69b9232201ba 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -42,10 +42,9 @@ /* Extra Commands */ -#define CONFIG_SYS_GBL_DATA_SIZE 1024/* Global data structures */ #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_TEXT_BASE - \ CONFIG_SYS_MALLOC_LEN - \ -CONFIG_SYS_GBL_DATA_SIZE) +GENERATED_GBL_DATA_SIZE) /* USB Configs */ #define CONFIG_USB_OHCI_NEW -- 2.25.1
[PATCH 06/11] m68k: Stop using CONFIG_SYS_GBL_DATA_OFFSET
This value is only referenced by PowerPC code in a way other than directly as CONFIG_SYS_INIT_SP_ADDR. Switch to CONFIG_SYS_INIT_SP_ADDR directly. Signed-off-by: Tom Rini --- include/configs/M5208EVBE.h | 3 +-- include/configs/M5235EVB.h | 3 +-- include/configs/M5249EVB.h | 3 +-- include/configs/M5253DEMO.h | 3 +-- include/configs/M5272C3.h| 3 +-- include/configs/M5275EVB.h | 3 +-- include/configs/M5282EVB.h | 3 +-- include/configs/M53017EVB.h | 3 +-- include/configs/M5329EVB.h | 3 +-- include/configs/M5373EVB.h | 3 +-- include/configs/amcore.h | 3 +-- include/configs/astro_mcf5373l.h | 3 +-- include/configs/cobra5272.h | 3 +-- include/configs/eb_cpu5282.h | 3 +-- include/configs/stmark2.h| 3 +-- 15 files changed, 15 insertions(+), 30 deletions(-) diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 4ca71ad41ba2..04b39cb3d398 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -65,8 +65,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x8000 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) /* * Start addresses for the final memory configuration diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 68b695c6fbbd..c69de822e754 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -75,8 +75,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x2000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1 /* Size of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_CTRL 0x21 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10) /*--- * Start addresses for the final memory configuration diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index 64eae702160f..97b2ce19437c 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -44,8 +44,7 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x2000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define LDS_BOARD_TEXT \ . = DEFINED(env_offset) ? env_offset : .; \ diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index e81768441ec4..939e0ba18f18 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -79,8 +79,7 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x2000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * Start addresses for the final memory configuration diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index bd4c531751e2..4c13f4dd43fe 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -76,8 +76,7 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x2000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM*/ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /*--- * Start addresses for the final memory configuration diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 99412aabdec9..0520869050d2 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -78,8 +78,7 @@ */ #define CONFIG_SYS_INIT_RAM_ADDR 0x2000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -
[PATCH 07/11] mpc85xx: Switch to setting the initial stack pointer more clearly
Currently, since we know that in the combination of CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET all of the "high" bits are in CONFIG_SYS_INIT_RAM_ADDR and "low" bits are in CONFIG_SYS_GBL_DATA_OFFSET we reference this separately in start.S, but added together everywhere else. For clarity consistency, reference the combined value here instead. Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc85xx/start.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 7a079edb691e..48f06f51c8fd 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1160,8 +1160,8 @@ _start_cont: bne 1b #if CONFIG_VAL(SYS_MALLOC_F_LEN) - lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h - ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l + lis r4,(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h + ori r4,r4,(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l addir3,r3,16/* Pre-relocation malloc area */ stw r3,GD_MALLOC_BASE(r4) -- 2.25.1
[PATCH 01/11] m68k: Remove dead code
There are no mcf5227x platforms, remove the CPU code.
Signed-off-by: Tom Rini
---
arch/m68k/Kconfig | 6 -
arch/m68k/cpu/mcf5227x/Makefile | 9 -
arch/m68k/cpu/mcf5227x/cpu.c| 67
arch/m68k/cpu/mcf5227x/cpu_init.c | 152 -
arch/m68k/cpu/mcf5227x/dspi.c | 43 ---
arch/m68k/cpu/mcf5227x/interrupts.c | 37 ---
arch/m68k/cpu/mcf5227x/speed.c | 127 ---
arch/m68k/cpu/mcf5227x/start.S | 491
8 files changed, 932 deletions(-)
delete mode 100644 arch/m68k/cpu/mcf5227x/Makefile
delete mode 100644 arch/m68k/cpu/mcf5227x/cpu.c
delete mode 100644 arch/m68k/cpu/mcf5227x/cpu_init.c
delete mode 100644 arch/m68k/cpu/mcf5227x/dspi.c
delete mode 100644 arch/m68k/cpu/mcf5227x/interrupts.c
delete mode 100644 arch/m68k/cpu/mcf5227x/speed.c
delete mode 100644 arch/m68k/cpu/mcf5227x/start.S
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 7f6e4310f1f4..e609ae0c9cdb 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -53,12 +53,6 @@ config MCF5441x
select DM_SERIAL
bool
-config MCF5227x
- select OF_CONTROL
- select DM
-select DM_SERIAL
- bool
-
# processor type
config M5208
bool
diff --git a/arch/m68k/cpu/mcf5227x/Makefile b/arch/m68k/cpu/mcf5227x/Makefile
deleted file mode 100644
index 6a38c4838e99..
--- a/arch/m68k/cpu/mcf5227x/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
-
-# ccflags-y += -DET_DEBUG
-
-extra-y= start.o
-obj-y = cpu.o speed.o cpu_init.o interrupts.o dspi.o
diff --git a/arch/m68k/cpu/mcf5227x/cpu.c b/arch/m68k/cpu/mcf5227x/cpu.c
deleted file mode 100644
index a7adf64f0de0..
--- a/arch/m68k/cpu/mcf5227x/cpu.c
+++ /dev/null
@@ -1,67 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
- *
- * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (tsi-chung.l...@freescale.com)
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include
-#include
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- rcm_t *rcm = (rcm_t *) (MMAP_RCM);
- udelay(1000);
- setbits_8(>rcr, RCM_RCR_SOFTRST);
-
- /* we don't return! */
- return 0;
-};
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- ccm_t *ccm = (ccm_t *) MMAP_CCM;
- u16 msk;
- u16 id = 0;
- u8 ver;
-
- puts("CPU: ");
- msk = (in_be16(>cir) >> 6);
- ver = (in_be16(>cir) & 0x003f);
- switch (msk) {
- case 0x6c:
- id = 52277;
- break;
- }
-
- if (id) {
- char buf1[32], buf2[32], buf3[32];
-
- printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
- ver);
- printf(" CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
- strmhz(buf1, gd->cpu_clk),
- strmhz(buf2, gd->bus_clk),
- strmhz(buf3, gd->arch.flb_clk));
- printf(" INP CLK %s MHz VCO CLK %s MHz\n",
- strmhz(buf1, gd->arch.inp_clk),
- strmhz(buf2, gd->arch.vco_clk));
- }
-
- return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/m68k/cpu/mcf5227x/cpu_init.c
b/arch/m68k/cpu/mcf5227x/cpu_init.c
deleted file mode 100644
index 4ab13b4d8eab..
--- a/arch/m68k/cpu/mcf5227x/cpu_init.c
+++ /dev/null
@@ -1,152 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
- *
- * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (tsi-chung.l...@freescale.com)
- */
-
-#include
-#include
-#include
-#include
-
-#include
-#include
-#include
-#include
-
-void cfspi_port_conf(void)
-{
- gpio_t *gpio = (gpio_t *)MMAP_GPIO;
-
- out_8(>par_dspi,
- GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
- GPIO_PAR_DSPI_SCK_SCK);
-}
-
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- * initialize the UPM's
- */
-void cpu_init_f(void)
-{
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
-
-#if !defined(CONFIG_CF_SBF)
- scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
- pll_t *pll = (pll_t *)MMAP_PLL;
-
- /* Workaround, must place before fbcs */
- out_be32(>psr, 0x12);
-
- out_be32(>mpr, 0x);
- out_be32(>pacra, 0);
- out_be32(>pacrb, 0);
- out_be32(>pacrc, 0);
- out_be32(>pacrd, 0);
- out_be32(>pacre, 0);
- out_be32(>pacrf,
[PATCH 05/11] arm: Stop using CONFIG_SYS_GBL_DATA_OFFSET
This value is only referenced by PowerPC code in a way other than directly as CONFIG_SYS_INIT_SP_ADDR. Switch to CONFIG_SYS_INIT_SP_ADDR directly. Signed-off-by: Tom Rini --- include/configs/integrator-common.h | 3 +-- include/configs/vexpress_common.h | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index d578b0246051..927daa71ad18 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -32,10 +32,9 @@ #define PHYS_SDRAM_1_SIZE 0x0800 /* 128 MB */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ +#define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_SDRAM_BASE + \ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET /* * FLASH and environment organization diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index f27280af99ef..86cb56e7a189 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -139,10 +139,9 @@ /* additions for new relocation code */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ +#define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_SDRAM_BASE + \ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDRCONFIG_SYS_GBL_DATA_OFFSET /* Basic environment settings */ #define BOOT_TARGET_DEVICES(func) \ -- 2.25.1
[PATCH 03/11] mvebu: Use CONFIG_SPL_STACK + 4 directly for bootparam location
The definition of CONFIG_SPL_BOOTROM_SAVE is always a fixed
CONFIG_SPL_STACK + 4, while CONFIG_SPL_STACK is not constant. This
change will make it clear where the location is still, once
CONFIG_SPL_STACK moves to Kconfig.
Cc: Stefan Roese
Signed-off-by: Tom Rini
---
arch/arm/mach-mvebu/lowlevel_spl.S | 8
arch/arm/mach-mvebu/spl.c | 2 +-
include/configs/clearfog.h | 1 -
include/configs/controlcenterdc.h | 1 -
include/configs/db-88f6720.h | 1 -
include/configs/db-88f6820-amc.h | 1 -
include/configs/db-88f6820-gp.h| 1 -
include/configs/db-mv784mp-gp.h| 1 -
include/configs/ds414.h| 1 -
include/configs/helios4.h | 1 -
include/configs/maxbcm.h | 1 -
include/configs/theadorable.h | 1 -
include/configs/turris_omnia.h | 1 -
include/configs/x530.h | 1 -
14 files changed, 5 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-mvebu/lowlevel_spl.S
b/arch/arm/mach-mvebu/lowlevel_spl.S
index 501c239e9d38..49891df9ea9e 100644
--- a/arch/arm/mach-mvebu/lowlevel_spl.S
+++ b/arch/arm/mach-mvebu/lowlevel_spl.S
@@ -8,19 +8,19 @@
* contains U-Boot SPL, optionally it can also contain additional arguments.
* The number of these arguments is in r0, pointer to the argument array in r1.
* BootROM expects executable BIN header code to return to address stored in
lr.
- * Other registers (r2 - r12) must be preserved. We save all registers to
- * CONFIG_SPL_BOOTROM_SAVE address. BIN header arguments (passed via r0 and r1)
+ * Other registers (r2 - r12) must be preserved. We save all registers to the
+ * address of CONFIG_SPL_STACK + 4. BIN header arguments (passed via r0 and r1)
* are currently not used by U-Boot SPL binary.
*/
ENTRY(save_boot_params)
stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */
- ldr r12, =CONFIG_SPL_BOOTROM_SAVE
+ ldr r12, =(CONFIG_SPL_STACK + 4)
str sp, [r12]
b save_boot_params_ret
ENDPROC(save_boot_params)
ENTRY(return_to_bootrom)
- ldr r12, =CONFIG_SPL_BOOTROM_SAVE
+ ldr r12, =(CONFIG_SPL_STACK + 4)
ldr sp, [r12]
ldmfd sp!, {r0 - r12, lr} /* @ restore registers from stack */
mov r0, #0x0/* @ return value: 0x0 NO_ERR */
diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
index fa9a1d7ab65e..13c99913c380 100644
--- a/arch/arm/mach-mvebu/spl.c
+++ b/arch/arm/mach-mvebu/spl.c
@@ -283,7 +283,7 @@ u32 spl_boot_device(void)
int board_return_to_bootrom(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
- u32 *regs = *(u32 **)CONFIG_SPL_BOOTROM_SAVE;
+ u32 *regs = *(u32 **)(CONFIG_SPL_STACK + 4);
printf("Returning to BootROM (return address 0x%08x)...\n", regs[13]);
return_to_bootrom();
diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h
index b67a31981b07..6cf44877601f 100644
--- a/include/configs/clearfog.h
+++ b/include/configs/clearfog.h
@@ -48,7 +48,6 @@
#define CONFIG_SPL_BSS_START_ADDR (0x4000 + CONFIG_SPL_SIZE)
#define CONFIG_SPL_STACK (0x4000 + ((192 - 16) << 10))
-#define CONFIG_SPL_BOOTROM_SAVE(CONFIG_SPL_STACK + 4)
#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) ||
defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA)
/* SPL related MMC defines */
diff --git a/include/configs/controlcenterdc.h
b/include/configs/controlcenterdc.h
index 08eb0dbbf954..78b7d4f17f29 100644
--- a/include/configs/controlcenterdc.h
+++ b/include/configs/controlcenterdc.h
@@ -40,7 +40,6 @@
#define CONFIG_SPL_BSS_START_ADDR (0x4000 + CONFIG_SPL_SIZE)
#define CONFIG_SPL_STACK (0x4000 + ((212 - 16) << 10))
-#define CONFIG_SPL_BOOTROM_SAVE(CONFIG_SPL_STACK + 4)
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
/* SPL related MMC defines */
diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h
index 89786044c834..eeaae1fdabcb 100644
--- a/include/configs/db-88f6720.h
+++ b/include/configs/db-88f6720.h
@@ -38,6 +38,5 @@
#define CONFIG_SPL_BSS_START_ADDR (0x4000 + (128 << 10))
#define CONFIG_SPL_STACK (0x4000 + ((192 - 16) << 10))
-#define CONFIG_SPL_BOOTROM_SAVE(CONFIG_SPL_STACK + 4)
#endif /* _CONFIG_DB_88F6720_H */
diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h
index 56fd872272d9..cb2050015e00 100644
--- a/include/configs/db-88f6820-amc.h
+++ b/include/configs/db-88f6820-amc.h
@@ -45,7 +45,6 @@
#define CONFIG_SPL_BSS_START_ADDR (0x4000 + CONFIG_SPL_SIZE)
#define CONFIG_SPL_STACK (0x4000 + ((192 - 16) << 10))
-#define CONFIG_SPL_BOOTROM_SAVE(CONFIG_SPL_STACK + 4)
/*
* mv-common.h should be defined after CMD configs since it used them
diff --git a/include/configs/db-88f6820-gp.h
[PATCH] net: Check for the minimum IP fragmented datagram size
From: Fabio Estevam
Nicolas Bidron and Nicolas Guigo reported the two bugs below:
"
--BUG 1--
In compiled versions of U-Boot that define CONFIG_IP_DEFRAG, a value of
`ip->ip_len` (IP packet header's Total Length) higher than `IP_HDR_SIZE`
and strictly lower than `IP_HDR_SIZE+8` will lead to a value for `len`
comprised between `0` and `7`. This will ultimately result in a
truncated division by `8` resulting value of `0` forcing the hole
metadata and fragment to point to the same location. The subsequent
memcopy will overwrite the hole metadata with the fragment data. Through
a second fragment, this can be exploited to write to an arbitrary offset
controlled by that overwritten hole metadata value.
This bug is only exploitable locally as it requires crafting two packets
the first of which would most likely be dropped through routing due to
its unexpectedly low Total Length. However, this bug can potentially be
exploited to root linux based embedded devices locally.
```C
static struct ip_udp_hdr *__net_defragment(struct ip_udp_hdr *ip, int *lenp)
{
static uchar pkt_buff[IP_PKTSIZE] __aligned(PKTALIGN);
static u16 first_hole, total_len;
struct hole *payload, *thisfrag, *h, *newh;
struct ip_udp_hdr *localip = (struct ip_udp_hdr *)pkt_buff;
uchar *indata = (uchar *)ip;
int offset8, start, len, done = 0;
u16 ip_off = ntohs(ip->ip_off);
/* payload starts after IP header, this fragment is in there */
payload = (struct hole *)(pkt_buff + IP_HDR_SIZE);
offset8 = (ip_off & IP_OFFS);
thisfrag = payload + offset8;
start = offset8 * 8;
len = ntohs(ip->ip_len) - IP_HDR_SIZE;
```
The last line of the previous excerpt from `u-boot/net/net.c` shows how
the attacker can control the value of `len` to be strictly lower than
`8` by issuing a packet with `ip_len` between `21` and `27`
(`IP_HDR_SIZE` has a value of `20`).
Also note that `offset8` here is `0` which leads to `thisfrag = payload`.
```C
} else if (h >= thisfrag) {
/* overlaps with initial part of the hole: move this hole */
newh = thisfrag + (len / 8);
*newh = *h;
h = newh;
if (h->next_hole)
payload[h->next_hole].prev_hole = (h - payload);
if (h->prev_hole)
payload[h->prev_hole].next_hole = (h - payload);
else
first_hole = (h - payload);
} else {
```
Lower down the same function, execution reaches the above code path.
Here, `len / 8` evaluates to `0` leading to `newh = thisfrag`. Also note
that `first_hole` here is `0` since `h` and `payload` point to the same
location.
```C
/* finally copy this fragment and possibly return whole packet */
memcpy((uchar *)thisfrag, indata + IP_HDR_SIZE, len);
```
Finally, in the above excerpt the `memcpy` overwrites the hole metadata
since `thisfrag` and `h` both point to the same location. The hole
metadata is effectively overwritten with arbitrary data from the
fragmented IP packet data. If `len` was crafted to be `6`, `last_byte`,
`next_hole`, and `prev_hole` of the `first_hole` can be controlled by
the attacker.
Finally the arbitrary offset write occurs through a second fragment that
only needs to be crafted to write data in the hole pointed to by the
previously controlled hole metadata (`next_hole`) from the first packet.
### Recommendation
Handle cases where `len` is strictly lower than 8 by preventing the
overwrite of the hole metadata during the memcpy of the fragment. This
could be achieved by either:
* Moving the location where the hole metadata is stored when `len` is
lower than `8`.
* Or outright rejecting fragmented IP datagram with a Total Length
(`ip_len`) lower than 28 bytes which is the minimum valid fragmented IP
datagram size (as defined as the minimum fragment of 8 octets in the IP
Specification Document:
[RFC791](https://datatracker.ietf.org/doc/html/rfc791) page 25).
--BUG 2--
In compiled versions of U-Boot that define CONFIG_IP_DEFRAG, a value of
`ip->ip_len` (IP packet header's Total Length) lower than `IP_HDR_SIZE`
will lead to a negative value for `len` which will ultimately result in
a buffer overflow during the subsequent `memcpy` that uses `len` as it's
`count` parameter.
This bug is only exploitable on local ethernet as it requires crafting
an invalid packet to include an unexpected `ip_len` value in the IP UDP
header that's lower than the minimum accepted Total Length of a packet
(21 as defined in the IP Specification Document:
[RFC791](https://datatracker.ietf.org/doc/html/rfc791)). Such packet
would in all likelihood be dropped while being routed to its final
destination through most routing equipment and as such requires the
attacker to be in a local position in order to be exploited.
```C
static struct ip_udp_hdr *__net_defragment(struct ip_udp_hdr *ip, int *lenp)
{
static uchar pkt_buff[IP_PKTSIZE] __aligned(PKTALIGN);
static u16 first_hole,
[PATCH] powerpc: bootm: Fix sizes in memory adjusting warning
Old size is stored in size variable and new size is in bootm_size variable.
Signed-off-by: Pali Rohár
---
arch/powerpc/lib/bootm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 8d65047aa4d4..2704f6562803 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -137,7 +137,8 @@ void arch_lmb_reserve(struct lmb *lmb)
if (size < bootm_size) {
ulong base = bootmap_base + size;
- printf("WARNING: adjusting available memory to %lx\n", size);
+ printf("WARNING: adjusting available memory from 0x%lx to
0x%llx\n",
+ size, (unsigned long long)bootm_size);
lmb_reserve(lmb, base, bootm_size - size);
}
--
2.20.1
Re: Vulnerability Disclosure in net/
Hi Fabio On Thu, May 26, 2022 at 2:13 PM Fabio Estevam wrote: > > Hi Ramon, > > On Wed, May 25, 2022 at 11:46 PM Ramon Fried wrote: > > > Hi Nicolas, > > Thanks for the research. > > I have read your description thoroughly, very interesting. > > I will implement fixes to the findings. > > Is it enough to add the check below? > > --- a/net/net.c > +++ b/net/net.c > @@ -906,6 +906,9 @@ static struct ip_udp_hdr *__net_defragment(struct > ip_udp_hdr *ip, int *lenp) > uchar *indata = (uchar *)ip; > int offset8, start, len, done = 0; > u16 ip_off = ntohs(ip->ip_off); > + > + if (ip->ip_len < 28) > + return NULL; > If you comment on it up or nobody will remember what is 28 tomorrow Michael > /* payload starts after IP header, this fragment is in there */ > payload = (struct hole *)(pkt_buff + IP_HDR_SIZE); -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 mich...@amarulasolutions.com __ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 i...@amarulasolutions.com www.amarulasolutions.com
Re: Vulnerability Disclosure in net/
Hi Ramon, On Wed, May 25, 2022 at 11:46 PM Ramon Fried wrote: > Hi Nicolas, > Thanks for the research. > I have read your description thoroughly, very interesting. > I will implement fixes to the findings. Is it enough to add the check below? --- a/net/net.c +++ b/net/net.c @@ -906,6 +906,9 @@ static struct ip_udp_hdr *__net_defragment(struct ip_udp_hdr *ip, int *lenp) uchar *indata = (uchar *)ip; int offset8, start, len, done = 0; u16 ip_off = ntohs(ip->ip_off); + + if (ip->ip_len < 28) + return NULL; /* payload starts after IP header, this fragment is in there */ payload = (struct hole *)(pkt_buff + IP_HDR_SIZE);
Re: Vulnerability Disclosure in net/
Hi Ramon,
On 26/05/2022 04:46, Ramon Fried wrote:
On Wed, May 18, 2022 at 7:14 PM Nicolas Bidron
wrote:
Hello,
We found a couple of bugs in net/net.s in the IP defragmentation
function __net_defragment(). Below the writeup for the 2 bugs:
---BUG 1---
# Hole Descriptor Overwrite in U-Boot IP Packet Defragmentation Leads to
Arbitrary Out of Bounds Write Primitive (CVE-TBD)
| | |
| --- | --- |
|Project | U-Boot |
|Project URL | https://github.com/u-boot/u-boot |
|Versions affected | all versions up to commit TBD |
|Systems affected | All systems defining `CONFIG_IP_DEFRAG` |
|CVE identifier | TBD |
|Advisory URL | TBD |
|Risk | Critical 9.6 (CVSS:3.1/AV:A/AC:L/PR:N/UI:N/S:C/C:H/I:H/A:H) |
|Authors | Nicolas Guigo, Nicolas Bidron |
### Summary
U-boot is a popular boot loader for embedded systems with
implementations for a large number of architectures and prominent in
most linux based embedded systems.
### Location
In `u-boot/net/net.c` the `__net_defragment` function line 900 through 1018.
### Impact
The U-Boot implementation of
[RFC815](https://datatracker.ietf.org/doc/html/rfc815) IP DATAGRAM
REASSEMBLY ALGORITHMS is susceptible to a Hole Descriptor overwrite
attack which ultimately leads to an arbitrary write primitve.
### Description
In compiled versions of U-Boot that define CONFIG_IP_DEFRAG, a value of
`ip->ip_len` (IP packet header's Total Length) higher than `IP_HDR_SIZE`
and strictly lower than `IP_HDR_SIZE+8` will lead to a value for `len`
comprised between `0` and `7`. This will ultimately result in a
truncated division by `8` resulting value of `0` forcing the hole
metadata and fragment to point to the same location. The subsequent
memcopy will overwrite the hole metadata with the fragment data. Through
a second fragment, this can be exploited to write to an arbitrary offset
controlled by that overwritten hole metadata value.
This bug is only exploitable locally as it requires crafting two packets
the first of which would most likely be dropped through routing due to
its unexpectedly low Total Length. However, this bug can potentially be
exploited to root linux based embedded devices locally.
```C
static struct ip_udp_hdr *__net_defragment(struct ip_udp_hdr *ip, int *lenp)
{
static uchar pkt_buff[IP_PKTSIZE] __aligned(PKTALIGN);
static u16 first_hole, total_len;
struct hole *payload, *thisfrag, *h, *newh;
struct ip_udp_hdr *localip = (struct ip_udp_hdr *)pkt_buff;
uchar *indata = (uchar *)ip;
int offset8, start, len, done = 0;
u16 ip_off = ntohs(ip->ip_off);
/* payload starts after IP header, this fragment is in there */
payload = (struct hole *)(pkt_buff + IP_HDR_SIZE);
offset8 = (ip_off & IP_OFFS);
thisfrag = payload + offset8;
start = offset8 * 8;
len = ntohs(ip->ip_len) - IP_HDR_SIZE;
```
The last line of the previous excerpt from `u-boot/net/net.c` shows how
the attacker can control the value of `len` to be strictly lower than
`8` by issuing a packet with `ip_len` between `21` and `27`
(`IP_HDR_SIZE` has a value of `20`).
Also note that `offset8` here is `0` which leads to `thisfrag = payload`.
```C
} else if (h >= thisfrag) {
/* overlaps with initial part of the hole: move this hole */
newh = thisfrag + (len / 8);
*newh = *h;
h = newh;
if (h->next_hole)
payload[h->next_hole].prev_hole = (h - payload);
if (h->prev_hole)
payload[h->prev_hole].next_hole = (h - payload);
else
first_hole = (h - payload);
} else {
```
Lower down the same function, execution reaches the above code path.
Here, `len / 8` evaluates to `0` leading to `newh = thisfrag`. Also note
that `first_hole` here is `0` since `h` and `payload` point to the same
location.
```C
/* finally copy this fragment and possibly return whole packet */
memcpy((uchar *)thisfrag, indata + IP_HDR_SIZE, len);
```
Finally, in the above excerpt the `memcpy` overwrites the hole metadata
since `thisfrag` and `h` both point to the same location. The hole
metadata is effectively overwritten with arbitrary data from the
fragmented IP packet data. If `len` was crafted to be `6`, `last_byte`,
`next_hole`, and `prev_hole` of the `first_hole` can be controlled by
the attacker.
Finally the arbitrary offset write occurs through a second fragment that
only needs to be crafted to write data in the hole pointed to by the
previously controlled hole metadata (`next_hole`) from the first packet.
### Recommendation
Handle cases where `len` is strictly lower than 8 by preventing the
overwrite of the hole metadata during the memcpy of the fragment. This
could be achieved by either:
* Moving the location where the hole metadata is stored when `len` is
lower than `8`.
* Or outright rejecting fragmented IP datagram with a Total Length
(`ip_len`) lower than 28 bytes which is the minimum valid fragmented IP
Re: Pull request for efi-2022-07-rc4
Hi Heinrich, Tom, On Thu, 26 May 2022 at 18:56, Heinrich Schuchardt wrote: > > Dear Tom, > > The following changes since commit 7e0edcadb09d55d5319fdc862041fd1b874476f5: > >Merge branch 'master' of > https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-05-24 > 23:29:00 -0400) > > are available in the Git repository at: > >https://source.denx.de/u-boot/custodians/u-boot-efi.git > tags/efi-2022-07-rc4 > > for you to fetch changes up to 019ba3a6a644cceba46d92d42a1ed0677885a929: > >doc/build/gcc: add more required packages (2022-05-26 10:15:58 +0200) > > Gitlab CI showed no problems: > https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/12127 > > > Pull request for efi-2022-07-rc4 > > UEFI: > > * fix a problem in loading an image from a short-path > * fix building the bootmenu command for CONFIG_EFI_LOADER=n > * correct the bootefi command syntax > * add firmware management protocol to the documentation > > Others: > > * bootmenu: fix bootmenu title handling > > > AKASHI Takahiro (2): >efi_loader: disk: add efi_disk_is_removable() >efi_loader: bootmgr: fix a problem in loading an image from a > short-path > > Bin Meng (2): >doc: sandbox: Correct the memory size config option >doc: sandbox: Add a note of disabling LTO when using gdb > > Heinrich Schuchardt (6): >disk: incorrect message in is_gpt_valid() >test: restore timeout after bootmenu unit test >test: fix pylint warnings in test_efi_selftest.py >test: don't change console timeout in EFI selftest. >cmd/bootefi: correct command syntax >doc/build/gcc: add more required packages > > Masahisa Kojima (2): >bootmenu: fix bootmenu title handling I have sent the revised version of the patch. Could you ignore "bootmenu: fix bootmenu title handling" and apply the revised patch here? https://patchwork.ozlabs.org/project/uboot/patch/20220526100938.9558-2-masahisa.koj...@linaro.org/ Thanks, Masahisa Kojima >lib/charset: fix compile warnings > > Vincent Stehlé (2): >efi: fix documentation warnings >doc/efi: add firmware management protocol to the documentation > > cmd/bootefi.c | 21 +--- > cmd/bootmenu.c | 48 +++-- > disk/part_efi.c| 4 +- > doc/api/efi.rst| 6 +++ > doc/arch/sandbox.rst | 5 +- > doc/build/gcc.rst | 8 +-- > doc/usage/cmd/bootefi.rst | 8 +-- > include/charset.h | 2 +- > include/efi_loader.h | 3 ++ > lib/efi_loader/efi_bootmgr.c | 107 > +++-- > lib/efi_loader/efi_disk.c | 27 ++ > lib/efi_loader/efi_firmware.c | 10 ++-- > test/py/tests/test_bootmenu.py | 66 +++ > test/py/tests/test_efi_selftest.py | 91 ++- > 14 files changed, 266 insertions(+), 140 deletions(-)
[PATCH v2 2/2] bootmenu: U-Boot console is enabled as default
The commit 2158b0da220c ("bootmenu: add Kconfig option
not to enter U-Boot console") disables to enter U-Boot
console from bootmenu as default, this change affects the
existing bootmenu users.
This commit reverts the default behavior, the bootmenu can
enter U-Boot console same as before.
CMD_BOOTMENU_ENTER_UBOOT_CONSOLE is renamed
BOOTMENU_DISABLE_UBOOT_CONSOLE and depends on
AUTOBOOT_MENU_SHOW.
Fixes: 2158b0da220c ("bootmenu: add Kconfig option not to enter U-Boot console")
Signed-off-by: Masahisa Kojima
Tested-by: Pali Rohar
---
Changes in v2:
- remove "default n" since it is default option
- use 80 characters in one line
boot/Kconfig | 7 +++
cmd/Kconfig| 10 --
cmd/bootmenu.c | 4 ++--
3 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/boot/Kconfig b/boot/Kconfig
index dff4d23b88..08451c65a5 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -1143,6 +1143,13 @@ config AUTOBOOT_MENU_SHOW
environmnent variable (if enabled) and before handling the boot delay.
See README.bootmenu for more details.
+config BOOTMENU_DISABLE_UBOOT_CONSOLE
+ bool "Disallow bootmenu to enter the U-Boot console"
+ depends on AUTOBOOT_MENU_SHOW
+ help
+ If this option is enabled, user can not enter the U-Boot console from
+ bootmenu. It increases the system security.
+
config BOOT_RETRY
bool "Boot retry feature"
help
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 69c1814d24..09193b61b9 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -357,16 +357,6 @@ config CMD_BOOTMENU
help
Add an ANSI terminal boot menu command.
-config CMD_BOOTMENU_ENTER_UBOOT_CONSOLE
- bool "Allow Bootmenu to enter the U-Boot console"
- depends on CMD_BOOTMENU
- default n
- help
- Add an entry to enter U-Boot console in bootmenu.
- If this option is disabled, user can not enter
- the U-Boot console from bootmenu. It increases
- the system security.
-
config CMD_ADTIMG
bool "adtimg"
help
diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c
index bf88c2127b..1002c6b20a 100644
--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
@@ -362,7 +362,7 @@ static struct bootmenu_data *bootmenu_create(int delay)
goto cleanup;
/* Add Quit entry if entering U-Boot console is disabled */
- if (IS_ENABLED(CONFIG_CMD_BOOTMENU_ENTER_UBOOT_CONSOLE))
+ if (!IS_ENABLED(CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE))
entry->title = strdup("U-Boot console");
else
entry->title = strdup("Quit");
@@ -595,7 +595,7 @@ int menu_show(int bootdelay)
if (ret == BOOTMENU_RET_UPDATED)
continue;
- if (!IS_ENABLED(CONFIG_CMD_BOOTMENU_ENTER_UBOOT_CONSOLE)) {
+ if (IS_ENABLED(CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE)) {
if (ret == BOOTMENU_RET_QUIT) {
/* default boot process */
if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR))
--
2.17.1
[PATCH v2 1/2] bootmenu: use utf-8 for menu title
The commit a3d0aa87acbe ("bootmenu: update bootmenu_entry structure")
changes the bootmenu title type from char to u16(UTF16 string)
to support EFI based system. If EFI_LOADER is not enabled,
printf("%ls") is not supported, so bootmenu does not appear
correctly.
This commit changes the type of menu title from u16(UTF16) to
utf-8 string and EFI strings is conveted into utf-8.
Fixes: a3d0aa87acbe ("bootmenu: update bootmenu_entry structure")
Signed-off-by: Masahisa Kojima
Tested-by: Pali Rohar
---
(no change since v1)
cmd/bootmenu.c | 36 +---
1 file changed, 21 insertions(+), 15 deletions(-)
diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c
index 8859eebea5..bf88c2127b 100644
--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
@@ -43,7 +43,7 @@ enum boot_type {
struct bootmenu_entry {
unsigned short int num; /* unique number 0 .. MAX_COUNT */
char key[3];/* key identifier of number */
- u16 *title; /* title of entry */
+ char *title;/* title of entry */
char *command; /* hush command of entry */
enum boot_type type;/* boot type of entry */
u16 bootorder; /* order for each boot type */
@@ -76,7 +76,7 @@ static void bootmenu_print_entry(void *data)
if (reverse)
puts(ANSI_COLOR_REVERSE);
- printf("%ls", entry->title);
+ printf("%s", entry->title);
if (reverse)
puts(ANSI_COLOR_RESET);
@@ -170,7 +170,7 @@ static int prepare_bootmenu_entry(struct bootmenu_data
*menu,
struct bootmenu_entry *iter = *current;
while ((option = bootmenu_getoption(i))) {
- u16 *buf;
+ char *buf;
sep = strchr(option, '=');
if (!sep) {
@@ -183,13 +183,13 @@ static int prepare_bootmenu_entry(struct bootmenu_data
*menu,
return -ENOMEM;
len = sep-option;
- buf = calloc(1, (len + 1) * sizeof(u16));
+ buf = calloc(1, (len + 1));
entry->title = buf;
if (!entry->title) {
free(entry);
return -ENOMEM;
}
- utf8_utf16_strncpy(, option, len);
+ strncpy(buf, option, len);
len = strlen(sep + 1);
entry->command = malloc(len + 1);
@@ -227,6 +227,7 @@ static int prepare_bootmenu_entry(struct bootmenu_data
*menu,
return 1;
}
+#if (CONFIG_IS_ENABLED(CMD_BOOTEFI_BOOTMGR))
/**
* prepare_uefi_bootorder_entry() - generate the uefi bootmenu entries
*
@@ -279,13 +280,17 @@ static int prepare_uefi_bootorder_entry(struct
bootmenu_data *menu,
}
if (lo.attributes & LOAD_OPTION_ACTIVE) {
- entry->title = u16_strdup(lo.label);
- if (!entry->title) {
+ char *buf;
+
+ buf = calloc(1, utf16_utf8_strlen(lo.label) + 1);
+ if (!buf) {
free(load_option);
free(entry);
free(bootorder);
return -ENOMEM;
}
+ entry->title = buf;
+ utf16_utf8_strncpy(, lo.label,
u16_strlen(lo.label));
entry->command = strdup("bootefi bootmgr");
sprintf(entry->key, "%d", i);
entry->num = i;
@@ -315,6 +320,7 @@ static int prepare_uefi_bootorder_entry(struct
bootmenu_data *menu,
return 1;
}
+#endif
static struct bootmenu_data *bootmenu_create(int delay)
{
@@ -341,13 +347,13 @@ static struct bootmenu_data *bootmenu_create(int delay)
if (ret < 0)
goto cleanup;
- if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR)) {
- if (i < MAX_COUNT - 1) {
+#if (CONFIG_IS_ENABLED(CMD_BOOTEFI_BOOTMGR))
+ if (i < MAX_COUNT - 1) {
ret = prepare_uefi_bootorder_entry(menu, , );
if (ret < 0 && ret != -ENOENT)
goto cleanup;
- }
}
+#endif
/* Add U-Boot console entry at the end */
if (i <= MAX_COUNT - 1) {
@@ -357,9 +363,9 @@ static struct bootmenu_data *bootmenu_create(int delay)
/* Add Quit entry if entering U-Boot console is disabled */
if (IS_ENABLED(CONFIG_CMD_BOOTMENU_ENTER_UBOOT_CONSOLE))
- entry->title = u16_strdup(u"U-Boot console");
+ entry->title = strdup("U-Boot console");
else
- entry->title = u16_strdup(u"Quit");
+ entry->title = strdup("Quit");
if (!entry->title) {
free(entry);
@@
[PATCH v2 0/2] fix issues in bootmenu after adding efi entries
This series fixes the issue in bootmenu after adding efi entries. Masahisa Kojima (2): bootmenu: use utf-8 for menu title bootmenu: U-Boot console is enabled as default boot/Kconfig | 7 +++ cmd/Kconfig| 10 -- cmd/bootmenu.c | 40 +++- 3 files changed, 30 insertions(+), 27 deletions(-) -- 2.17.1
Pull request for efi-2022-07-rc4
Dear Tom, The following changes since commit 7e0edcadb09d55d5319fdc862041fd1b874476f5: Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-05-24 23:29:00 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-efi.git tags/efi-2022-07-rc4 for you to fetch changes up to 019ba3a6a644cceba46d92d42a1ed0677885a929: doc/build/gcc: add more required packages (2022-05-26 10:15:58 +0200) Gitlab CI showed no problems: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/12127 Pull request for efi-2022-07-rc4 UEFI: * fix a problem in loading an image from a short-path * fix building the bootmenu command for CONFIG_EFI_LOADER=n * correct the bootefi command syntax * add firmware management protocol to the documentation Others: * bootmenu: fix bootmenu title handling AKASHI Takahiro (2): efi_loader: disk: add efi_disk_is_removable() efi_loader: bootmgr: fix a problem in loading an image from a short-path Bin Meng (2): doc: sandbox: Correct the memory size config option doc: sandbox: Add a note of disabling LTO when using gdb Heinrich Schuchardt (6): disk: incorrect message in is_gpt_valid() test: restore timeout after bootmenu unit test test: fix pylint warnings in test_efi_selftest.py test: don't change console timeout in EFI selftest. cmd/bootefi: correct command syntax doc/build/gcc: add more required packages Masahisa Kojima (2): bootmenu: fix bootmenu title handling lib/charset: fix compile warnings Vincent Stehlé (2): efi: fix documentation warnings doc/efi: add firmware management protocol to the documentation cmd/bootefi.c | 21 +--- cmd/bootmenu.c | 48 +++-- disk/part_efi.c| 4 +- doc/api/efi.rst| 6 +++ doc/arch/sandbox.rst | 5 +- doc/build/gcc.rst | 8 +-- doc/usage/cmd/bootefi.rst | 8 +-- include/charset.h | 2 +- include/efi_loader.h | 3 ++ lib/efi_loader/efi_bootmgr.c | 107 +++-- lib/efi_loader/efi_disk.c | 27 ++ lib/efi_loader/efi_firmware.c | 10 ++-- test/py/tests/test_bootmenu.py | 66 +++ test/py/tests/test_efi_selftest.py | 91 ++- 14 files changed, 266 insertions(+), 140 deletions(-)
Re: [PATCH 3/3] riscv: qemu: Set kernel_comp_addr_r for compressed kernel
On Tue, May 24, 2022 at 12:31:14PM +0800, Bin Meng wrote: > Set kernel_comp_addr_r and kernel_comp_size for compressed kernel. > Adjust existing addresses for ramdisk, so that kernel_comp_addr_r > comes before the ramdisk image, since the decompressed kernel size > is known to us. This way we can allow big ramdisk image to be loaded. > > Signed-off-by: Bin Meng > --- > > include/configs/qemu-riscv.h | 10 ++ > 1 file changed, 6 insertions(+), 4 deletions(-) > Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 2/3] riscv: sifive: unleashed: Set kernel_comp_addr_r for compressed kernel
On Tue, May 24, 2022 at 12:31:13PM +0800, Bin Meng wrote: > Set kernel_comp_addr_r and kernel_comp_size for compressed kernel. > Adjust existing addresses for ramdisk, so that kernel_comp_addr_r > comes before the ramdisk image, since the decompressed kernel size > is known to us. This way we can allow big ramdisk image to be loaded. > > Update unleashed.rst to remove the manual environment configuration > for compressed kernel boot. > > Signed-off-by: Bin Meng > --- > > doc/board/sifive/unleashed.rst | 2 -- > include/configs/sifive-unleashed.h | 10 ++ > 2 files changed, 6 insertions(+), 6 deletions(-) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 1/3] riscv: sifive: unmatched: Adjust for big ramdisk image
On Tue, May 24, 2022 at 12:31:12PM +0800, Bin Meng wrote: > Move kernel_comp_addr_r to an address that comes before the ramdisk > image, since the decompressed kernel size is known to us. This way > we can allow big ramdisk image to be loaded. > > Signed-off-by: Bin Meng > --- > > include/configs/sifive-unmatched.h | 10 +- > 1 file changed, 5 insertions(+), 5 deletions(-) Reviewed-by: Leo Yu-Chi Liang
[PATCH v3] board: freescale: p1_p2_rdb_pc: Move boot reset macros to p1_p2_bootsrc.h
Code for changing boot source is platform generic and can be used by any P1* and P2* compatible RDB board. Not only by boards which use config header file p1_p2_rdb_pc.h. So move this code from p1_p2_rdb_pc.h to p1_p2_bootsrc.h and cleanup macros for generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS. This allows to use code for resetting board and rebooting to other boot source also by other boards in future. Signed-off-by: Pali Rohár --- Changes in v3: * Fix copyright header Changes in v2: * Fix commit message * Move macros to file p1_p2_bootsrc.h * Rewrite macros even more to be more generic and use them without custom macros in p1_p2_rdb_pc.h --- include/configs/p1_p2_bootsrc.h | 59 + include/configs/p1_p2_rdb_pc.h | 41 +-- 2 files changed, 68 insertions(+), 32 deletions(-) create mode 100644 include/configs/p1_p2_bootsrc.h diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h new file mode 100644 index ..13e4fdb4fdf6 --- /dev/null +++ b/include/configs/p1_p2_bootsrc.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + * Copyright 2022 Pali Rohár + */ + +#include + +#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CONFIG_SYS_I2C_PCA9557_ADDR) +#error "CONFIG_SYS_SPD_BUS_NUM and CONFIG_SYS_I2C_PCA9557_ADDR are required" +#endif + +#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 msk 1 + +#define __VAR_CMD(var, cmd) __stringify(var=cmd\0) +#define __VAR_CMD_RST(var, cmd) __VAR_CMD(var, cmd; reset) + +#ifdef __SW_NOR_BANK_LO +#define MAP_NOR_LO_CMD(var, ...) __VAR_CMD(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_NOR_BANK_LO, __SW_NOR_BANK_MASK)) +#else +#define MAP_NOR_LO_CMD(var, ...) "" +#endif + +#ifdef __SW_NOR_BANK_UP +#define MAP_NOR_UP_CMD(var, ...) __VAR_CMD(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_NOR_BANK_UP, __SW_NOR_BANK_MASK)) +#else +#define MAP_NOR_UP_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_NOR +#define RST_NOR_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK)) +#else +#define RST_NOR_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_SPI +#define RST_SPI_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK)) +#else +#define RST_SPI_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_SD +#define RST_SD_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SD, __SW_BOOT_MASK)) +#else +#define RST_SD_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_NAND +#define RST_NAND_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK)) +#else +#define RST_NAND_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_PCIE +#define RST_PCIE_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK)) +#else +#define RST_PCIE_CMD(var, ...) "" +#endif diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index f6ecf2a7a8b8..0d655818a924 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -542,31 +542,7 @@ #define CONFIG_ROOTPATH"/opt/nfsroot" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ -#ifdef __SW_BOOT_NOR -#define __NOR_RST_CMD \ -norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_SPI -#define __SPI_RST_CMD \ -spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_SD -#define __SD_RST_CMD \ -sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_NAND -#define __NAND_RST_CMD \ -nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_PCIE -#define __PCIE_RST_CMD \ -pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif +#include "p1_p2_bootsrc.h" #defineCONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0"\ @@ -593,13 +569,14 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset "nandfdtaddr=8\0" \ "ramdisk_size=12\0"\ __VSCFW_ADDR \ -"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
Re: [PATCH v2] board: freescale: p1_p2_rdb_pc: Move boot reset macros to p1_p2_bootsrc.h
On Thursday 26 May 2022 06:08:04 Priyanka Jain (OSS) wrote: > >-Original Message- > >From: U-Boot On Behalf Of Pali Rohár > >Sent: Monday, April 25, 2022 8:18 PM > >To: Priyanka Jain ; Qiang Zhao ; > >Shengzhou Liu ; Sinan Akman > >Cc: u-boot@lists.denx.de > >Subject: [PATCH v2] board: freescale: p1_p2_rdb_pc: Move boot reset macros to > >p1_p2_bootsrc.h > > > >Code for changing boot source is platform generic and can be used by any > >P1* and P2* compatible RDB board. Not only by boards which use config header > >file p1_p2_rdb_pc.h. > > > >So move this code from p1_p2_rdb_pc.h to p1_p2_bootsrc.h and cleanup macros > >for generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS. > > > >This allows to use code for resetting board and rebooting to other boot > >source > >also by other boards in future. > > > >Signed-off-by: Pali Rohár > >--- > >Changes in v2: > >* Fix commit message > >* Move macros to file p1_p2_bootsrc.h > >* Rewrite macros even more to be more generic and use them without custom > > macros in p1_p2_rdb_pc.h > >--- > > include/configs/p1_p2_bootsrc.h | 55 + > >include/configs/p1_p2_rdb_pc.h | 41 ++-- > > 2 files changed, 64 insertions(+), 32 deletions(-) create mode 100644 > >include/configs/p1_p2_bootsrc.h > > > >diff --git a/include/configs/p1_p2_bootsrc.h > >b/include/configs/p1_p2_bootsrc.h > >new file mode 100644 index ..a274c57786f5 > >--- /dev/null > >+++ b/include/configs/p1_p2_bootsrc.h > >@@ -0,0 +1,55 @@ > >+// SPDX-License-Identifier: GPL-2.0+ > >+// (C) 2022 Pali Rohár > >+ > Code is copied from one file to another. Please don’t remove original > copyright I rewritten all those macros from scratch during moving and I therefore I have thought about copyright header (I just put default one here). But I can copy+paste copyright header from old file, no problem. > > > Regards > Priyanka
Out of bounds write vulnerability in the sqfs_readdir() function
Hello u-boot list,
I found the sqfs_readdir() function is vulnerable to Out-of-Bound write,
which will cause arbitrary code execution.
```
int sqfs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp)
{
..
/* Set entry name */
strncpy(dent->name, dirs->entry->name, dirs->entry->name_size + 1);
dent->name[dirs->entry->name_size + 1] = '\0';
offset = dirs->entry->name_size + 1 + SQFS_ENTRY_BASE_LENGTH;
dirs->entry_count--;
...
}
struct squashfs_dir_stream {
struct fs_dir_stream fs_dirs;
struct fs_dirent dentp;
size_t size;
int entry_count;
struct squashfs_directory_header *dir_header;
struct squashfs_directory_entry *entry;
..
};
static int sqfs_search_dir(struct squashfs_dir_stream *dirs, char
**token_list,
int token_count, u32 *m_list, int m_count)
{
..
while (!sqfs_readdir(dirsp, )) {
ret = strcmp(dent->name, token_list[j]);
if (!ret)
break;
free(dirs->entry);
dirs->entry = NULL;
}
..
}
```
The sqfs_readdir() function use strncpy to set entry name, while the type
of dirs->entry->name_size is defined as "u16" in the struct
squashfs_directory_entry
and dent->name
is defined as "char[256]" in the struct fs_dirent.
We can overwrite *dirs_header and *entry in the struct squashfs_dir_stream,
so that we can use the sqfs_search_dir() function to free a fake
chunk which causes arbitrary code execution.
You can see the Poc in the attachment.
host bind 0 test4.sqfs
ls host 0 /dirs
test4.sqfs
Description: Binary data
[PATCH 1/1] doc/build/gcc: add more required packages
The following Python packages are used by U-Boot, too: * python3-asteval * python3-subunit * python3-testtools Signed-off-by: Heinrich Schuchardt --- doc/build/gcc.rst | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/doc/build/gcc.rst b/doc/build/gcc.rst index 470a7aa349..682051abeb 100644 --- a/doc/build/gcc.rst +++ b/doc/build/gcc.rst @@ -27,10 +27,10 @@ Depending on the build targets further packages maybe needed device-tree-compiler dfu-util efitools flex gdisk graphviz imagemagick \ liblz4-tool libgnutls28-dev libguestfs-tools libncurses-dev \ libpython3-dev libsdl2-dev libssl-dev lz4 lzma lzma-alone openssl \ - pkg-config python3 python3-coverage python3-pkg-resources \ - python3-pycryptodome python3-pyelftools python3-pytest \ - python3-sphinxcontrib.apidoc python3-sphinx-rtd-theme python3-virtualenv \ - swig + pkg-config python3 python3-asteval python3-coverage \ + python3-pkg-resources python3-pycryptodome python3-pyelftools \ + python3-pytest python3-sphinxcontrib.apidoc python3-sphinx-rtd-theme \ + python3-subunit python3-testtools python3-virtualenv swig SUSE based ~~ -- 2.36.1
Re: [PATCH] doc: sandbox: Add a note of disabling LTO when using gdb
On 5/17/22 18:21, Bin Meng wrote: Image created by LTO is not friendly to debugger, let's document this. Signed-off-by: Bin Meng --- doc/arch/sandbox.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/arch/sandbox.rst b/doc/arch/sandbox.rst index 246ab5b380..19167d22fb 100644 --- a/doc/arch/sandbox.rst +++ b/doc/arch/sandbox.rst @@ -477,6 +477,8 @@ board_init_f() and board_init_r(). This approach can be used on normal boards as well as sandbox. +When debugging with gdb, it's better to disable Link Timer Optimizations +(CONFIG_LTO = n). CC_OPTIMIZE_FOR_DEBUG should be mentioned here too. I will add this when merging. Should CC_OPTIMIZE_FOR_DEBUG disable LTO? The usefulness of LTO=n, CC_OPTIMIZE_FOR_DEBUG=y for debugging is not sandbox specific but applies to QEMU and JTAG debugging too. I think the section "Debugging the init sequence" should not live on a page that is sandbox specific. Instead we should add a new page on debugging U-Boot. Reviewed-by: Heinrich Schuchardt SDL_CONFIG --
Re: [PATCH v6 3/6] efi_loader: menu-driven update of UEFI bootorder variable
On Tue, 24 May 2022 at 19:42, Heinrich Schuchardt wrote:
>
> On 5/16/22 13:00, Masahisa Kojima wrote:
> > This commit adds the menu-driven update of UEFI bootorder
> > variable.
> >
> > Signed-off-by: Masahisa Kojima
> > ---
> > (no update since v5)
> >
> > Changes in v5:
> > - split into the separate patch
> >
> > lib/efi_loader/efi_bootmenu_maintenance.c | 102 ++
> > 1 file changed, 102 insertions(+)
> >
> > diff --git a/lib/efi_loader/efi_bootmenu_maintenance.c
> > b/lib/efi_loader/efi_bootmenu_maintenance.c
> > index 96306cd2cc..be67fca95f 100644
> > --- a/lib/efi_loader/efi_bootmenu_maintenance.c
> > +++ b/lib/efi_loader/efi_bootmenu_maintenance.c
> > @@ -746,6 +746,56 @@ static efi_status_t
> > efi_bootmenu_boot_add_enter_name(struct efi_bootmenu_boot_op
> > return ret;
> > }
> >
> > +static efi_status_t allow_decimal(struct efi_input_key *key)
> > +{
> > + if (u'0' <= key->unicode_char && key->unicode_char <= u'9')
> > + return EFI_SUCCESS;
> > +
> > + return EFI_INVALID_PARAMETER;
> > +}
> > +
> > +static efi_status_t efi_bootmenu_change_boot_order(int selected, int max,
> > int *new)
> > +{
> > + efi_status_t ret;
> > + u16 new_order[EFI_BOOT_ORDER_MAX_SIZE_IN_DECIMAL] = {0};
>
> After selecting an item why can we simply use the up and down key to
> move the selected item?
OK, I will use the up and down key, as Takahiro also
requested this before.
>
> > +
> > + printf(ANSI_CURSOR_POSITION, 2, 1);
> > + puts(" *** U-Boot EFI Boot Manager Menu ***");
> > + printf(ANSI_CURSOR_POSITION, 4, 1);
> > + printf(" current boot order : %d", selected);
> > +
> > + printf(ANSI_CURSOR_POSITION, 6, 1);
> > + printf(" new boot order(0 - %4d): ", max);
> > +
> > + printf(ANSI_CURSOR_POSITION, 8, 1);
> > + puts(" ENTER to complete, ESC/CTRL+C to quit");
> > +
> > + printf(ANSI_CURSOR_POSITION, 6, 29);
> > + puts(ANSI_CURSOR_SHOW);
> > +
> > + for (;;) {
> > + memset(new_order, 0, sizeof(new_order));
> > + ret = efi_console_get_u16_string(cin, cout, new_order, 6,
> > allow_decimal, 6, 29);
> > + if (ret == EFI_SUCCESS) {
> > + int i;
> > + int val = 0;
> > +
> > + for (i = 0;
> > + i < u16_strnlen(new_order,
> > EFI_BOOT_ORDER_MAX_SIZE_IN_DECIMAL - 1);
> > + i++)
> > + val = (val * 10) + (new_order[i] - u'0');
> > +
> > + if (val > max)
> > + continue;
> > +
> > + *new = val;
> > + return EFI_SUCCESS;
> > + } else {
> > + return ret;
> > + }
> > + }
> > +}
> > +
> > static efi_status_t efi_bootmenu_select_file_handler(struct
> > efi_bootmenu_boot_option *bo)
> > {
> > efi_status_t ret;
> > @@ -996,6 +1046,57 @@ static efi_status_t
> > efi_bootmenu_process_delete_boot_option(void *data, bool *ex
> > return ret;
> > }
> >
> > +static efi_status_t efi_bootmenu_process_change_boot_order(void *data,
> > bool *exit)
> > +{
> > + int selected;
> > + int new_order;
> > + efi_status_t ret;
> > + efi_uintn_t num, size;
> > + u16 *bootorder = NULL;
> > + u16 *new_bootorder = NULL;
> > +
> > + bootorder = efi_get_var(u"BootOrder", _global_variable_guid,
> > );
> > + if (!bootorder)
> > + return EFI_NOT_FOUND;
> > +
> > + num = size / sizeof(u16);
> > + ret = efi_bootmenu_show_boot_selection(bootorder, num, );
> > + if (ret != EFI_SUCCESS)
> > + goto out;
> > +
> > + ret = efi_bootmenu_change_boot_order(selected, num - 1, _order);
> > + if (ret != EFI_SUCCESS)
> > + goto out;
> > +
> > + new_bootorder = calloc(1, size);
> > + if (!new_bootorder)
> > + goto out;
> > +
> > + memcpy(new_bootorder, bootorder, size);
> > + if (selected > new_order) {
> > + new_bootorder[new_order] = bootorder[selected];
> > + memcpy(_bootorder[new_order + 1], [new_order],
> > +(selected - new_order) * sizeof(u16));
> > + } else if (selected < new_order) {
> > + new_bootorder[new_order] = bootorder[selected];
> > + memcpy(_bootorder[selected], [selected + 1],
> > +(new_order - selected) * sizeof(u16));
>
> After updating an item we should be in the
> efi_bootmenu_show_boot_selection() screen again.
OK.
Thanks,
Masahisa Kojima
>
> Best regards
>
> Heinrich
>
> > + } else {
> > + /* nothing to change */
> > + goto out;
> > + }
> > + ret = efi_set_variable_int(u"BootOrder", _global_variable_guid,
> > +EFI_VARIABLE_NON_VOLATILE |
> > +EFI_VARIABLE_BOOTSERVICE_ACCESS |
> > +
Re: [PATCH v6 1/6] efi_loader: menu-driven addition of UEFI boot option
On 5/25/22 03:38, Takahiro Akashi wrote:
On Mon, May 16, 2022 at 08:00:37PM +0900, Masahisa Kojima wrote:
This commit supports the menu-driven UEFI boot option addition.
User can select the block device volume having
efi_simple_file_system_protocol and select the file corresponding
to the Boot variable. Then user enter the label of the BOOT
variable in utf8.
Signed-off-by: Masahisa Kojima
---
Changes in v6:
- fix typos
- modify volume name to match U-Boot syntax
- compile in CONFIG_EFI_LOADER=n and CONFIG_CMD_BOOTEFI_BOOTMGR=n
Is this correct?
- simplify u16_strncmp() usage
- support "a\b.efi" file path, use link list to handle filepath
- modify length check condition
- UEFI related menu items only appears with CONFIG_AUTOBOOT_MENU_SHOW=y
Why?
I think that the feature is useful even without AUTOBOOT.
As you know, efidebug is seen as a debugging tool and is not expected
to be enabled in production systems.
So the feature you're adding is the only available UI for boot manager.
What I recommend is
- to create a boot manager maintenance as a standalone U-Boot command,
- to add an bootmenu entry for invoking the command
Changes in v5:
- remove forward declarations
- add const qualifier for menu items
- fix the possible unaligned access for directory info access
- split into three commit 1)add boot option 2) delete boot option 3)change boot
order
This commit is 1)add boot option.
- fix file name buffer allocation size, it should be EFI_BOOTMENU_FILE_PATH_MAX
* sizeof(u16)
- fix wrong size checking for file selection
Chanes in v4:
- UEFI boot option maintenance menu is integrated into bootmenu
- display the simplified volume name(e.g. usb0:1, nvme1:2) for the
volume selection
- instead of extending lib/efi_loader/efi_bootmgr.c, newly create
lib/efi_loader/efi_bootmenu_maintenance.c and implement boot
variable maintenance into it.
Changes in RFC v3:
not included in v3 series
Changes in RFC v2:
- enable utf8 user input for boot option name
- create lib/efi_loader/efi_console.c::efi_console_get_u16_string() for
utf8 user input handling
- use u16_strlcat instead of u16_strcat
- remove the EFI_CALLs, and newly create or expose the following
xxx_int() functions.
efi_locate_handle_buffer_int(), efi_open_volume_int(),
efi_file_open_int(), efi_file_close_int(), efi_file_read_int() and
efi_file_setpos_int().
Note that EFI_CALLs still exist for EFI_DEVICE_PATH_TO_TEXT_PROTOCOL
and EFI_SIMPLE_TEXT_INPUT/OUTPUT_PROTOCOL
- use efi_search_protocol() instead of calling locate_protocol() to get
the device_path_to_text_protocol interface.
- remove unnecessary puts(ANSI_CLEAR_LINE), this patch is still depends on
puts(ANSI_CLEAR_CONSOLE)
- skip SetVariable() if the bootorder is not changed
cmd/bootmenu.c| 73 +-
include/efi_loader.h | 37 +
lib/efi_loader/Makefile | 3 +
lib/efi_loader/efi_bootmenu_maintenance.c | 906 ++
I would say that this file should be moved under /cmd as the code does not
implement any UEFI specification semantics, but simply provides helper
functions for bootmenu command.
Or I recommend that the boot manager be implemented as a standalone command
(as I insisted serveral times before) and the related maintenance feature
be invoked as follows:
=> efibootmanager -i (i for interactive)
lib/efi_loader/efi_boottime.c | 52 +-
lib/efi_loader/efi_console.c | 81 ++
lib/efi_loader/efi_disk.c | 11 +
lib/efi_loader/efi_file.c | 75 +-
8 files changed, 1184 insertions(+), 54 deletions(-)
create mode 100644 lib/efi_loader/efi_bootmenu_maintenance.c
diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c
index 8859eebea5..4b846332b0 100644
--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
@@ -19,6 +19,12 @@
/* maximum bootmenu entries */
#define MAX_COUNT 99
+#if defined(CONFIG_CMD_BOOTEFI_BOOTMGR) && defined(CONFIG_AUTOBOOT_MENU_SHOW)
+#define STATIC_ENTRY 2
+#else
+#define STATIC_ENTRY 1
+#endif
+#define MAX_DYNAMIC_ENTRY (MAX_COUNT - STATIC_ENTRY)
/* maximal size of bootmenu env
* 9 = strlen("bootmenu_")
@@ -38,10 +44,11 @@ enum boot_type {
BOOTMENU_TYPE_NONE = 0,
BOOTMENU_TYPE_BOOTMENU,
BOOTMENU_TYPE_UEFI_BOOT_OPTION,
+ BOOTMENU_TYPE_UEFI_MAINTENANCE,
};
struct bootmenu_entry {
- unsigned short int num; /* unique number 0 .. MAX_COUNT */
+ unsigned short int num; /* unique number 0 .. (MAX_COUNT - 1) */
char key[3];/* key identifier of number */
u16 *title; /* title of entry */
char *command; /* hush command of entry */
@@ -55,7 +62,7 @@ static char *bootmenu_getoption(unsigned short int n)
{
char name[MAX_ENV_SIZE];
- if (n > MAX_COUNT)
+ if (n > MAX_DYNAMIC_ENTRY)
return NULL;
Re: [u-boot PATCH 3/3] k3-am642-evm-u-boot: Use binman to generate u-boot.img and tispl.bin
On 25/05/2022 18:14, Andrew Davis wrote:
> On 5/25/22 3:30 AM, Roger Quadros wrote:
>> Hi Andrew,
>>
>> On 25/05/2022 01:03, Andrew Davis wrote:
>>> On 5/9/22 2:29 AM, Roger Quadros wrote:
Introduce k3-am642-evm-binman.dtsi to provide binman configuration.
R5 build is still not converted to use binman so restrict binman.dtsi
to A53 builds only.
This patch also take care of building Secure (HS) images using
binman instead of tools/k3_fit_atf.sh if CONFIG_BINMAN is set.
Signed-off-by: Roger Quadros
---
arch/arm/dts/k3-am642-evm-binman.dtsi | 230 ++
arch/arm/dts/k3-am642-evm-u-boot.dtsi | 3 +
arch/arm/mach-k3/Kconfig | 1 +
arch/arm/mach-k3/config.mk | 7 +
4 files changed, 241 insertions(+)
create mode 100644 arch/arm/dts/k3-am642-evm-binman.dtsi
diff --git a/arch/arm/dts/k3-am642-evm-binman.dtsi
b/arch/arm/dts/k3-am642-evm-binman.dtsi
new file mode 100644
index 00..9e85ef41b0
--- /dev/null
+++ b/arch/arm/dts/k3-am642-evm-binman.dtsi
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+#ifdef CONFIG_TARGET_AM642_A53_EVM
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+#define TISPL "tispl.bin_HS"
+#define UBOOT_IMG "u-boot.img_HS"
+#else
+#define TISPL "tispl.bin"
+#define UBOOT_IMG "u-boot.img"
+#endif
+
+#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
+#define SPL_AM642_EVM_DTB "spl/dts/k3-am642-evm.dtb"
+#define SPL_AM642_SK_DTB "spl/dts/k3-am642-sk.dtb"
+
+#define UBOOT_NODTB "u-boot-nodtb.bin"
+#define AM642_EVM_DTB "arch/arm/dts/k3-am642-evm.dtb"
+#define AM642_SK_DTB "arch/arm/dts/k3-am642-sk.dtb"
+
+ {
+ ti-spl {
+ filename = TISPL;
+ pad-byte = <0xff>;
+
+ fit {
+ description = "Configuration to load ATF and SPL";
+ #address-cells = <1>;
+
+ images {
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ os = "arm-trusted-firmware";
+ load = ;
+ entry = ;
+ atf-bl31 {
+ filename = "bl31.bin";
+ };
>>>
>>>
>>> On HS, bl31.bin and the below TEE and DM images must also be signed
>>> before being packaged into tispl.bin.
>>> Can we add signing here?
>>
>> I'm wondering how this is working as is on HS boards.
>>
>
>
> Today we manually sign those two before we feed them to U-Boot build.
> I'd like to fix that and have them signed along with all the other
> parts here when packaging them together.
>
OK. Then this is new feature. Do you mind if I make a separate patch for it?
But first I need to figure out what to do ;)
>
>> Another thing to note is that the atf and tee entries take into consideration
>> the below environment variables
>> -a atf-bl31-path=${BL31} \
>> -a tee-os-path=${TEE} \
>>
>> How do we continue to support that while adding the signing bits?
>>
>
>
> That's my question also, I'm not sure how we would make the type 'ti-secure'
> while also changing their path names, seems like a limitation currently
> of using etypes to do the signing, since we can do path renames from
> command line.
Simon,
Any thoughts on how to get the new ti-secure etype work with atf-bl31 and
tee-os etypes so that it can take the data output of those entries and create
a signed binary with filenames from those entries or atf-bl31-path and
tee-os-path?
Can something like this work?
ti-secure {
atf-bl31 {
filename = "bl31.bin";
};
}
We could probably get rid of filename property from ti-secure etype and use
blob for regular files.
ti-secure {
blob {
filename = "somefile.ext";
}
}
cheers,
-roger
>
> Andrew
>
>
>> cheers,
>> -roger
>>
>>>
>>> Andrew
>>>
>>>
+ };
+
+ tee {
+ description = "OPTEE";
+ type = "tee";
+ arch = "arm64";
+ compression = "none";
+ os = "tee";
+ load = <0x9e80>;
+ entry = <0x9e80>;
+ tee-os {
+ filename = "tee-pager_v2.bin";
Re: [PATCH] mach-rockchip: make_fit_atf.py: support OP-TEE tee.bin v1 format
On 2022/5/11 23:35, Jerome Forissier wrote:
This commit adds support for the OP-TEE 'tee.bin' v1 format for Rockchip
platforms.
Since OP-TEE 3.8.0, tee.bin contains meta-data in a proprietary format
in addition to the ELF data. They are essential information for proper
initialization of the TEE core, such as the size of the memory region
covered by the TEE or a compact representation of runtime relocation
data when ASLR is enabled.
With OP-TEE 3.8.0 onwards, 'tee.elf' MUST NOT be used and 'tee.bin'
MUST be used instead. Ignoring this recommendation can lead to crashes
as described in [3].
Link: [1]
https://github.com/OP-TEE/optee_os/commit/5dd1570ac5b0f6563b1a9c074533a19107b8222d
Link: [2]
https://github.com/OP-TEE/optee_os/blob/3.17.0/scripts/gen_tee_bin.py#L275-L302
Link: [3] https://github.com/OP-TEE/optee_os/issues/4542
Signed-off-by: Jerome Forissier
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/mach-rockchip/make_fit_atf.py | 43 +-
1 file changed, 35 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-rockchip/make_fit_atf.py
b/arch/arm/mach-rockchip/make_fit_atf.py
index f3224d2555..fcea652388 100755
--- a/arch/arm/mach-rockchip/make_fit_atf.py
+++ b/arch/arm/mach-rockchip/make_fit_atf.py
@@ -137,7 +137,7 @@ def generate_atf_fit_dts_bl31(fit_file, bl31_file_name,
tee_file_name, dtbs_file
num_segments = len(segments)
if tee_file_name:
-tee_segments = unpack_elf(tee_file_name)
+tee_segments = unpack_tee_file(tee_file_name)
for index, entry, paddr, data in tee_segments:
append_tee_node(fit_file, num_segments + index + 1, paddr, entry)
num_segments = num_segments + len(tee_segments)
@@ -169,7 +169,7 @@ def generate_atf_binary(bl31_file_name):
def generate_tee_binary(tee_file_name):
if tee_file_name:
-for index, entry, paddr, data in unpack_elf(tee_file_name):
+for index, entry, paddr, data in unpack_tee_file(tee_file_name):
file_name = 'tee_0x%08x.bin' % paddr
with open(file_name, "wb") as atf:
atf.write(data)
@@ -194,6 +194,31 @@ def unpack_elf(filename):
segments.append((index, e_entry, p_paddr, p_data))
return segments
+def unpack_tee_file(filename):
+if filename.endswith('.elf'):
+return unpack_elf(filename)
+with open(filename, 'rb') as file:
+bin = file.read()
+segments = []
+if bin[0:5] == b'OPTE\x01':
+# OP-TEE v1 format (tee.bin)
+init_sz, start_hi, start_lo, _, paged_sz = struct.unpack_from('<5I',
+ bin,
+ 0x8)
+if paged_sz != 0:
+raise ValueError("OP-TEE paged mode not supported")
+e_entry = (start_hi << 32) + start_lo
+p_addr = e_entry
+p_data = bin[0x1c:]
+if len(p_data) != init_sz:
+raise ValueError("Invalid file '%s': size mismatch "
+ "(expected %d, have %d)" % (filename, init_sz,
+ len(p_data)))
+segments.append((0, e_entry, p_addr, p_data))
+else:
+raise ValueError("Unknown format for TEE file '%s'" % filename)
+return segments
+
def main():
uboot_elf = "./u-boot"
fit_its = sys.stdout
@@ -210,11 +235,13 @@ def main():
logging.warning(' Please read Building section in
doc/README.rockchip')
if "TEE" in os.environ:
-tee_elf = os.getenv("TEE")
+tee_file = os.getenv("TEE")
+elif os.path.isfile("./tee.bin"):
+tee_file = "./tee.bin"
elif os.path.isfile("./tee.elf"):
-tee_elf = "./tee.elf"
+tee_file = "./tee.elf"
else:
-tee_elf = ""
+tee_file = ""
opts, args = getopt.getopt(sys.argv[1:], "o:u:b:t:h")
for opt, val in opts:
@@ -225,16 +252,16 @@ def main():
elif opt == "-b":
bl31_elf = val
elif opt == "-t":
-tee_elf = val
+tee_file = val
elif opt == "-h":
print(__doc__)
sys.exit(2)
dtbs = args
-generate_atf_fit_dts(fit_its, bl31_elf, tee_elf, uboot_elf, dtbs)
+generate_atf_fit_dts(fit_its, bl31_elf, tee_file, uboot_elf, dtbs)
generate_atf_binary(bl31_elf)
-generate_tee_binary(tee_elf)
+generate_tee_binary(tee_file)
if __name__ == "__main__":
main()
Re: [PATCH] rockchip: rk3328: nanopi-r2s: Use the sdcard for the env
On 2022/5/4 02:41, Emmanuel Vadot wrote: The NanoPi-R2S doesn't have eMMC so use the sdcard as the device to save the environment variables Signed-off-by: Emmanuel Vadot Reviewed-by: Kever Yang Thanks, - Kever --- configs/nanopi-r2s-rk3328_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 453e54295d..0665368c4d 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -44,6 +44,7 @@ CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TPL_DM=y
Re: [PATCH v1] arm: dts: rockchip: rk3288: move dma-controller nodes
On 2022/5/2 19:22, Johan Jonker wrote:
In order to better compare the Linux rk3288.dtsi version
with the u-boot version move the dma-controller nodes
to the DT root.
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3288.dtsi | 76 ++--
1 file changed, 35 insertions(+), 41 deletions(-)
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 469df94e..53ee760b 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -86,47 +86,6 @@
};
};
- amba {
- compatible = "arm,amba-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- dmac_peri: dma-controller@ff25 {
- compatible = "arm,pl330", "arm,primecell";
- broken-no-flushp;
- reg = <0xff25 0x4000>;
- interrupts = ,
-;
- #dma-cells = <1>;
- clocks = < ACLK_DMAC2>;
- clock-names = "apb_pclk";
- };
-
- dmac_bus_ns: dma-controller@ff60 {
- compatible = "arm,pl330", "arm,primecell";
- broken-no-flushp;
- reg = <0xff60 0x4000>;
- interrupts = ,
-;
- #dma-cells = <1>;
- clocks = < ACLK_DMAC1>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
-
- dmac_bus_s: dma-controller@ffb2 {
- compatible = "arm,pl330", "arm,primecell";
- broken-no-flushp;
- reg = <0xffb2 0x4000>;
- interrupts = ,
-;
- #dma-cells = <1>;
- clocks = < ACLK_DMAC1>;
- clock-names = "apb_pclk";
- };
- };
-
xin24m: oscillator {
compatible = "fixed-clock";
clock-frequency = <2400>;
@@ -367,6 +326,18 @@
pinctrl-0 = <_xfer>;
status = "disabled";
};
+
+ dmac_peri: dma-controller@ff25 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0xff25 0x4000>;
+ interrupts = ,
+;
+ #dma-cells = <1>;
+ broken-no-flushp;
+ clocks = < ACLK_DMAC2>;
+ clock-names = "apb_pclk";
+ };
+
thermal: thermal-zones {
#include "rk3288-thermal.dtsi"
};
@@ -458,6 +429,18 @@
status = "disabled";
};
+ dmac_bus_ns: dma-controller@ff60 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0xff60 0x4000>;
+ interrupts = ,
+;
+ #dma-cells = <1>;
+ broken-no-flushp;
+ clocks = < ACLK_DMAC1>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
i2c0: i2c@ff65 {
compatible = "rockchip,rk3288-i2c";
reg = <0xff65 0x1000>;
@@ -870,6 +853,17 @@
status = "disabled";
};
+ dmac_bus_s: dma-controller@ffb2 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0xffb2 0x4000>;
+ interrupts = ,
+;
+ #dma-cells = <1>;
+ broken-no-flushp;
+ clocks = < ACLK_DMAC1>;
+ clock-names = "apb_pclk";
+ };
+
efuse: efuse@ffb4 {
compatible = "rockchip,rk3288-efuse";
reg = <0xffb4 0x1>;
Re: [PATCH v1] arm: dts: rockchip: rk3288: sort mipi hdmi lvds and dp nodes
On 2022/5/2 18:19, Johan Jonker wrote:
In order to better compare the Linux rk3288.dtsi version
with the u-boot version sort the mipi,hdmi,lvds and dp nodes.
Changed:
Rename mipi_dsi label.
Rename dp nodename.
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3288-evb.dtsi | 2 +-
arch/arm/dts/rk3288.dtsi | 110 +--
2 files changed, 56 insertions(+), 56 deletions(-)
diff --git a/arch/arm/dts/rk3288-evb.dtsi b/arch/arm/dts/rk3288-evb.dtsi
index 04902c0b..72da8847 100644
--- a/arch/arm/dts/rk3288-evb.dtsi
+++ b/arch/arm/dts/rk3288-evb.dtsi
@@ -448,7 +448,7 @@
status = "okay";
};
-_dsi0 {
+_dsi {
status = "disabled";
rockchip,panel = <>;
display-timings {
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 0bfa4c39..469df94e 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -709,54 +709,29 @@
status = "disabled";
};
- edp: edp@ff97 {
- compatible = "rockchip,rk3288-edp";
- reg = <0xff97 0x4000>;
- interrupts = ;
- clocks = < SCLK_EDP>, < SCLK_EDP_24M>, <
PCLK_EDP_CTRL>;
- rockchip,grf = <>;
- clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
- resets = < 111>;
- reset-names = "edp";
- power-domains = < RK3288_PD_VIO>;
- status = "disabled";
- ports {
- edp_in: port {
- #address-cells = <1>;
- #size-cells = <0>;
- edp_in_vopb: endpoint@0 {
- reg = <0>;
- remote-endpoint = <_out_edp>;
- };
- edp_in_vopl: endpoint@1 {
- reg = <1>;
- remote-endpoint = <_out_edp>;
- };
- };
- };
- };
-
- hdmi: hdmi@ff98 {
- compatible = "rockchip,rk3288-dw-hdmi";
- reg = <0xff98 0x2>;
- reg-io-width = <4>;
- ddc-i2c-bus = <>;
+ mipi_dsi: mipi@ff96 {
+ compatible = "rockchip,rk3288_mipi_dsi";
+ reg = <0xff96 0x4000>;
+ clocks = < PCLK_MIPI_DSI0>;
+ clock-names = "pclk_mipi";
+ /*pinctrl-names = "default";
+ pinctrl-0 = <_ctl>;*/
rockchip,grf = <>;
- interrupts = ;
- clocks = < PCLK_HDMI_CTRL>, < SCLK_HDMI_HDCP>;
- clock-names = "iahb", "isfr";
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
ports {
- hdmi_in: port {
+ reg = <1>;
+ mipi_in: port {
#address-cells = <1>;
#size-cells = <0>;
- hdmi_in_vopb: endpoint@0 {
+ mipi_in_vopb: endpoint@0 {
reg = <0>;
- remote-endpoint = <_out_hdmi>;
+ remote-endpoint = <_out_mipi>;
};
- hdmi_in_vopl: endpoint@1 {
+ mipi_in_vopl: endpoint@1 {
reg = <1>;
- remote-endpoint = <_out_hdmi>;
+ remote-endpoint = <_out_mipi>;
};
};
};
@@ -790,29 +765,54 @@
};
};
- mipi_dsi0: mipi@ff96 {
- compatible = "rockchip,rk3288_mipi_dsi";
- reg = <0xff96 0x4000>;
- clocks = < PCLK_MIPI_DSI0>;
- clock-names = "pclk_mipi";
- /*pinctrl-names = "default";
- pinctrl-0 = <_ctl>;*/
+ edp: dp@ff97 {
+ compatible = "rockchip,rk3288-edp";
+ reg = <0xff97 0x4000>;
+ interrupts = ;
+ clocks = < SCLK_EDP>, < SCLK_EDP_24M>, <
PCLK_EDP_CTRL>;
rockchip,grf = <>;
- #address-cells = <1>;
- #size-cells = <0>;
+ clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
+ resets = < 111>;
+ reset-names = "edp";
+ power-domains = < RK3288_PD_VIO>;
status = "disabled";
ports {
- reg = <1>;
- mipi_in: port {
+ edp_in: port {
Re: [PATCH v1] arm: dts: rockchip: rk3288: rename mmc nodenames
On 2022/5/2 17:42, Johan Jonker wrote:
The boot_devices constants for rk3288 were changed to match the
binding, but the dtsi file was not synced.
Fix by renaming the rk3288 mmc node names.
Also correct the clock name for "ciu-drive".
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3288.dtsi | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 5e40e741..0bfa4c39 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -150,48 +150,48 @@
ports = <_out>, <_out>;
};
- sdmmc: dwmmc@ff0c {
+ sdmmc: mmc@ff0c {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <15000>;
clocks = < HCLK_SDMMC>, < SCLK_SDMMC>,
< SCLK_SDMMC_DRV>, < SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = ;
reg = <0xff0c 0x4000>;
status = "disabled";
};
- sdio0: dwmmc@ff0d {
+ sdio0: mmc@ff0d {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <15000>;
clocks = < HCLK_SDIO0>, < SCLK_SDIO0>,
< SCLK_SDIO0_DRV>, < SCLK_SDIO0_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = ;
reg = <0xff0d 0x4000>;
status = "disabled";
};
- sdio1: dwmmc@ff0e {
+ sdio1: mmc@ff0e {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <15000>;
clocks = < HCLK_SDIO1>, < SCLK_SDIO1>,
< SCLK_SDIO1_DRV>, < SCLK_SDIO1_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = ;
reg = <0xff0e 0x4000>;
status = "disabled";
};
- emmc: dwmmc@ff0f {
+ emmc: mmc@ff0f {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <15000>;
clocks = < HCLK_EMMC>, < SCLK_EMMC>,
< SCLK_EMMC_DRV>, < SCLK_EMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = ;
reg = <0xff0f 0x4000>;
Re: [PATCH v1] arm: dts: rockchip: rk3288: bulk convert gpios to their constant counterparts
On 2022/5/2 16:58, Johan Jonker wrote:
Bulk convert rk3288 DT gpios to their constant counterparts.
Partial Linux sync for the rk3288.dtsi file.
ARM: dts: rockchip: bulk convert gpios to their constant counterparts
https://lore.kernel.org/all/20190402121852.14442-1-he...@sntech.de/
sed -i -f script.sed rk3288.dtsi
/rockchip,pins *=/bcheck
b # to end of script
:append-next-line
N
:check
/^[^;]*$/bappend-next-line
s/
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3288.dtsi | 274 +++
1 file changed, 137 insertions(+), 137 deletions(-)
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index c4abfa37..5e40e741 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -1072,411 +1072,411 @@
sleep {
global_pwroff: global-pwroff {
- rockchip,pins = <0 0 RK_FUNC_1 _pull_none>;
+ rockchip,pins = <0 RK_PA0 1 _pull_none>;
};
ddrio_pwroff: ddrio-pwroff {
- rockchip,pins = <0 1 RK_FUNC_1 _pull_none>;
+ rockchip,pins = <0 RK_PA1 1 _pull_none>;
};
ddr0_retention: ddr0-retention {
- rockchip,pins = <0 2 RK_FUNC_1 _pull_up>;
+ rockchip,pins = <0 RK_PA2 1 _pull_up>;
};
ddr1_retention: ddr1-retention {
- rockchip,pins = <0 3 RK_FUNC_1 _pull_up>;
+ rockchip,pins = <0 RK_PA3 1 _pull_up>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
- rockchip,pins = <0 15 RK_FUNC_1
_pull_none>,
- <0 16 RK_FUNC_1
_pull_none>;
+ rockchip,pins = <0 RK_PB7 1 _pull_none>,
+ <0 RK_PC0 1 _pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
- rockchip,pins = <8 4 RK_FUNC_1 _pull_none>,
- <8 5 RK_FUNC_1 _pull_none>;
+ rockchip,pins = <8 RK_PA4 1 _pull_none>,
+ <8 RK_PA5 1 _pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
- rockchip,pins = <6 9 RK_FUNC_1 _pull_none>,
- <6 10 RK_FUNC_1
_pull_none>;
+ rockchip,pins = <6 RK_PB1 1 _pull_none>,
+ <6 RK_PB2 1 _pull_none>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
- rockchip,pins = <2 16 RK_FUNC_1
_pull_none>,
- <2 17 RK_FUNC_1
_pull_none>;
+ rockchip,pins = <2 RK_PC0 1 _pull_none>,
+ <2 RK_PC1 1 _pull_none>;
};
};
i2c4 {
i2c4_xfer: i2c4-xfer {
- rockchip,pins = <7 17 RK_FUNC_1
_pull_none>,
- <7 18 RK_FUNC_1
_pull_none>;
+ rockchip,pins = <7 RK_PC1 1 _pull_none>,
+ <7 RK_PC2 1 _pull_none>;
};
};
i2c5 {
i2c5_xfer: i2c5-xfer {
- rockchip,pins = <7 19 RK_FUNC_1
_pull_none>,
- <7 20 RK_FUNC_1
_pull_none>;
+ rockchip,pins = <7 RK_PC3 1 _pull_none>,
+ <7 RK_PC4 1 _pull_none>;
};
};
i2s0 {
i2s0_bus: i2s0-bus {
- rockchip,pins = <6 0 RK_FUNC_1 _pull_none>,
- <6 1 RK_FUNC_1 _pull_none>,
- <6 2 RK_FUNC_1 _pull_none>,
- <6 3 RK_FUNC_1 _pull_none>,
- <6 4 RK_FUNC_1 _pull_none>,
- <6 8 RK_FUNC_1 _pull_none>;
+ rockchip,pins = <6 RK_PA0 1 _pull_none>,
+ <6 RK_PA1 1 _pull_none>,
+ <6 RK_PA2 1 _pull_none>,
+ <6 RK_PA3 1 _pull_none>,
+
Re: [PATCH v1 4/4] arm: dts: rockchip: remove usb-phy fallback string for rk3188
On 2022/4/30 05:40, Johan Jonker wrote:
With the conversion of rockchip-usb-phy.yaml a long time used fallback
string for rk3066a/rk3188 was added. The linux driver doesn't do much with
the GRF phy address range, however the u-boot driver rockchip_usb2_phy.c
does. The bits in GRF_UOC0_CON2 for rk3066a/rk3188 and rk3288 for example
don't match. Remove the usb-phy fallback string for rk3188
to prevent possible strange side effects.
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3188.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi
index 6764776c..9a80f83a 100644
--- a/arch/arm/dts/rk3188.dtsi
+++ b/arch/arm/dts/rk3188.dtsi
@@ -642,8 +642,7 @@
compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd";
usbphy: usbphy {
- compatible = "rockchip,rk3188-usb-phy",
-"rockchip,rk3288-usb-phy";
+ compatible = "rockchip,rk3188-usb-phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
Re: [PATCH v1 3/4] rockchip: board: change condition board_usb_init() in function
On 2022/4/30 05:40, Johan Jonker wrote: Change define condition in board_usb_init() function to allow rk3066/rk3188 to use the USB PHY driver. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang Thanks, - Kever --- arch/arm/mach-rockchip/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 5304eb05..cbe00d64 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -90,7 +90,7 @@ int board_usb_init(int index, enum usb_init_type init) } otg_data.regs_otg = ofnode_get_addr(node); -#ifdef CONFIG_ROCKCHIP_RK3288 +#ifdef CONFIG_ROCKCHIP_USB2_PHY int ret; u32 phandle, offset; ofnode phy_node;
Re: [PATCH v1 2/4] rockchip: usb: phy: add rk3066/rk3188 support
On 2022/4/30 05:40, Johan Jonker wrote:
Add rk3066a/rk3188 support to rockchip_usb2_phy.c
They don't have completely identical usb phy registers,
so separate comapatible strings and data.
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/usb/phy/rockchip_usb2_phy.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/usb/phy/rockchip_usb2_phy.c
b/drivers/usb/phy/rockchip_usb2_phy.c
index 93caa821..c46ad86d 100644
--- a/drivers/usb/phy/rockchip_usb2_phy.c
+++ b/drivers/usb/phy/rockchip_usb2_phy.c
@@ -42,6 +42,12 @@ struct rockchip_usb2_phy_dt_id {
const void *data;
};
+static const struct rockchip_usb2_phy_cfg rk3066a_pdata = {
+ .port_reset = {0x00, 12, 12, 0, 1},
+ .soft_con = {0x08, 2, 2, 0, 1},
+ .suspend= {0x08, 8, 3, (0x01 << 3), (0x2A << 3)},
+};
+
static const struct rockchip_usb2_phy_cfg rk3288_pdata = {
.port_reset = {0x00, 12, 12, 0, 1},
.soft_con = {0x08, 2, 2, 0, 1},
@@ -49,6 +55,8 @@ static const struct rockchip_usb2_phy_cfg rk3288_pdata = {
};
static struct rockchip_usb2_phy_dt_id rockchip_usb2_phy_dt_ids[] = {
+ { .compatible = "rockchip,rk3066a-usb-phy", .data = _pdata },
+ { .compatible = "rockchip,rk3188-usb-phy", .data = _pdata },
{ .compatible = "rockchip,rk3288-usb-phy", .data = _pdata },
{}
};
Re: [PATCH v1 1/4] rockchip: usb: gadget: add rk3066 product id
On 2022/4/30 05:40, Johan Jonker wrote: From: Paweł Jarosz Product id of rk3066 usb otg is 0x300a. Signed-off-by: Paweł Jarosz Signed-off-by: Johan Jonker Reviewed-by: Kever Yang Thanks, - Kever --- drivers/usb/gadget/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index d81a9c5a..8c6cf474 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -61,6 +61,7 @@ config USB_GADGET_PRODUCT_NUM hex "Product ID of the USB device" default 0x1010 if ARCH_SUNXI default 0x310a if ROCKCHIP_RK3036 + default 0x300a if ROCKCHIP_RK3066 default 0x310c if ROCKCHIP_RK3128 default 0x320a if ROCKCHIP_RK3229 || ROCKCHIP_RK3288 default 0x330a if ROCKCHIP_RK3328
Re: [PATCH 1/2] power: pmic: rk8xx: Support sysreset shutdown method
Hi Chris,
On 2022/5/24 03:30, Chris Morgan wrote:
From: Chris Morgan
Add support for sysreset shutdown for this PMIC. The values were pulled
from the various datasheets, but for now it has only been tested on
the rk817 (for an Odroid Go Advance).
Signed-off-by: Chris Morgan
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/power/pmic/rk8xx.c | 50 +-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c
index 5f442fea68..1ffbecc02a 100644
--- a/drivers/power/pmic/rk8xx.c
+++ b/drivers/power/pmic/rk8xx.c
@@ -6,10 +6,50 @@
#include
#include
+#include
#include
#include
#include
#include
+#include
+
+static int rk8xx_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct rk8xx_priv *priv = dev_get_priv(dev->parent);
+
+ if (type != SYSRESET_POWER_OFF)
+ return -EPROTONOSUPPORT;
+
+ switch (priv->variant) {
+ case RK805_ID:
+ case RK808_ID:
+ case RK816_ID:
+ case RK818_ID:
+ pmic_clrsetbits(dev->parent, REG_DEVCTRL, 0, BIT(0));
+ break;
+ case RK809_ID:
+ case RK817_ID:
+ pmic_clrsetbits(dev->parent, RK817_REG_SYS_CFG3, 0,
+ BIT(0));
+ break;
+ default:
+ printf("Unknown PMIC RK%x: Cannot shutdown\n",
+ priv->variant);
+ return -EPROTONOSUPPORT;
+ };
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops rk8xx_sysreset_ops = {
+ .request= rk8xx_sysreset_request,
+};
+
+U_BOOT_DRIVER(rk8xx_sysreset) = {
+ .name = "rk8xx_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops= _sysreset_ops,
+};
static struct reg_data rk817_init_reg[] = {
/* enable the under-voltage protection,
@@ -61,7 +101,7 @@ static int rk8xx_read(struct udevice *dev, uint reg, uint8_t
*buff, int len)
static int rk8xx_bind(struct udevice *dev)
{
ofnode regulators_node;
- int children;
+ int children, ret;
regulators_node = dev_read_subnode(dev, "regulators");
if (!ofnode_valid(regulators_node)) {
@@ -72,6 +112,14 @@ static int rk8xx_bind(struct udevice *dev)
debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+ if (CONFIG_IS_ENABLED(SYSRESET)) {
+ ret = device_bind_driver_to_node(dev, "rk8xx_sysreset",
+"rk8xx_sysreset",
+dev_ofnode(dev), NULL);
+ if (ret)
+ return ret;
+ }
+
children = pmic_bind_children(dev, regulators_node, pmic_children_info);
if (!children)
debug("%s: %s - no child found\n", __func__, dev->name);
Re: [PATCH 2/2] bootmenu: U-Boot console is enabled as default
On Thu, 26 May 2022 at 15:23, Michal Simek wrote:
>
>
>
> On 5/25/22 10:18, Masahisa Kojima wrote:
> > [CAUTION: External Email]
> >
> > The commit 2158b0da220c ("bootmenu: add Kconfig option
> > not to enter U-Boot console") disables to enter U-Boot
> > console from bootmenu as default, this change affects the
> > existing bootmenu users.
> >
> > This commit reverts the default behavior, the bootmenu can
> > enter U-Boot console same as before.
> > CMD_BOOTMENU_ENTER_UBOOT_CONSOLE is renamed
> > BOOTMENU_DISABLE_UBOOT_CONSOLE and depends on
> > AUTOBOOT_MENU_SHOW.
> >
> > Fixes: 2158b0da220c ("bootmenu: add Kconfig option not to enter U-Boot
> > console")
> > Signed-off-by: Masahisa Kojima
> > ---
> > boot/Kconfig | 9 +
> > cmd/Kconfig| 10 --
> > cmd/bootmenu.c | 4 ++--
> > 3 files changed, 11 insertions(+), 12 deletions(-)
> >
> > diff --git a/boot/Kconfig b/boot/Kconfig
> > index dff4d23b88..2eae3d5c6b 100644
> > --- a/boot/Kconfig
> > +++ b/boot/Kconfig
> > @@ -1143,6 +1143,15 @@ config AUTOBOOT_MENU_SHOW
> >environmnent variable (if enabled) and before handling the boot
> > delay.
> >See README.bootmenu for more details.
> >
> > +config BOOTMENU_DISABLE_UBOOT_CONSOLE
> > + bool "Disallow bootmenu to enter the U-Boot console"
> > + depends on AUTOBOOT_MENU_SHOW
> > + default n
>
> Remove this line. It is default option anyway.
OK.
>
>
> > + help
> > + If this option is enabled, user can not enter
> > + the U-Boot console from bootmenu. It increases
> > + the system security.
>
> you have 80 chars limit that's why please use it.
OK, I will use 80 chars for one line.
Thanks,
Masahisa Kojima
>
> > +
> > config BOOT_RETRY
> > bool "Boot retry feature"
> > help
> > diff --git a/cmd/Kconfig b/cmd/Kconfig
> > index 69c1814d24..09193b61b9 100644
> > --- a/cmd/Kconfig
> > +++ b/cmd/Kconfig
> > @@ -357,16 +357,6 @@ config CMD_BOOTMENU
> > help
> >Add an ANSI terminal boot menu command.
> >
> > -config CMD_BOOTMENU_ENTER_UBOOT_CONSOLE
> > - bool "Allow Bootmenu to enter the U-Boot console"
> > - depends on CMD_BOOTMENU
> > - default n
> > - help
> > - Add an entry to enter U-Boot console in bootmenu.
> > - If this option is disabled, user can not enter
> > - the U-Boot console from bootmenu. It increases
> > - the system security.
> > -
> > config CMD_ADTIMG
> > bool "adtimg"
> > help
> > diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c
> > index bf88c2127b..1002c6b20a 100644
> > --- a/cmd/bootmenu.c
> > +++ b/cmd/bootmenu.c
> > @@ -362,7 +362,7 @@ static struct bootmenu_data *bootmenu_create(int delay)
> > goto cleanup;
> >
> > /* Add Quit entry if entering U-Boot console is disabled */
> > - if (IS_ENABLED(CONFIG_CMD_BOOTMENU_ENTER_UBOOT_CONSOLE))
> > + if (!IS_ENABLED(CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE))
> > entry->title = strdup("U-Boot console");
> > else
> > entry->title = strdup("Quit");
> > @@ -595,7 +595,7 @@ int menu_show(int bootdelay)
> > if (ret == BOOTMENU_RET_UPDATED)
> > continue;
> >
> > - if (!IS_ENABLED(CONFIG_CMD_BOOTMENU_ENTER_UBOOT_CONSOLE)) {
> > + if (IS_ENABLED(CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE)) {
> > if (ret == BOOTMENU_RET_QUIT) {
> > /* default boot process */
> > if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR))
> > --
> > 2.17.1
> >
>
> M
Re: [PATCH 2/2] bootmenu: U-Boot console is enabled as default
On 5/25/22 10:18, Masahisa Kojima wrote:
[CAUTION: External Email]
The commit 2158b0da220c ("bootmenu: add Kconfig option
not to enter U-Boot console") disables to enter U-Boot
console from bootmenu as default, this change affects the
existing bootmenu users.
This commit reverts the default behavior, the bootmenu can
enter U-Boot console same as before.
CMD_BOOTMENU_ENTER_UBOOT_CONSOLE is renamed
BOOTMENU_DISABLE_UBOOT_CONSOLE and depends on
AUTOBOOT_MENU_SHOW.
Fixes: 2158b0da220c ("bootmenu: add Kconfig option not to enter U-Boot console")
Signed-off-by: Masahisa Kojima
---
boot/Kconfig | 9 +
cmd/Kconfig| 10 --
cmd/bootmenu.c | 4 ++--
3 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/boot/Kconfig b/boot/Kconfig
index dff4d23b88..2eae3d5c6b 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -1143,6 +1143,15 @@ config AUTOBOOT_MENU_SHOW
environmnent variable (if enabled) and before handling the boot
delay.
See README.bootmenu for more details.
+config BOOTMENU_DISABLE_UBOOT_CONSOLE
+ bool "Disallow bootmenu to enter the U-Boot console"
+ depends on AUTOBOOT_MENU_SHOW
+ default n
Remove this line. It is default option anyway.
+ help
+ If this option is enabled, user can not enter
+ the U-Boot console from bootmenu. It increases
+ the system security.
you have 80 chars limit that's why please use it.
+
config BOOT_RETRY
bool "Boot retry feature"
help
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 69c1814d24..09193b61b9 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -357,16 +357,6 @@ config CMD_BOOTMENU
help
Add an ANSI terminal boot menu command.
-config CMD_BOOTMENU_ENTER_UBOOT_CONSOLE
- bool "Allow Bootmenu to enter the U-Boot console"
- depends on CMD_BOOTMENU
- default n
- help
- Add an entry to enter U-Boot console in bootmenu.
- If this option is disabled, user can not enter
- the U-Boot console from bootmenu. It increases
- the system security.
-
config CMD_ADTIMG
bool "adtimg"
help
diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c
index bf88c2127b..1002c6b20a 100644
--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
@@ -362,7 +362,7 @@ static struct bootmenu_data *bootmenu_create(int delay)
goto cleanup;
/* Add Quit entry if entering U-Boot console is disabled */
- if (IS_ENABLED(CONFIG_CMD_BOOTMENU_ENTER_UBOOT_CONSOLE))
+ if (!IS_ENABLED(CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE))
entry->title = strdup("U-Boot console");
else
entry->title = strdup("Quit");
@@ -595,7 +595,7 @@ int menu_show(int bootdelay)
if (ret == BOOTMENU_RET_UPDATED)
continue;
- if (!IS_ENABLED(CONFIG_CMD_BOOTMENU_ENTER_UBOOT_CONSOLE)) {
+ if (IS_ENABLED(CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE)) {
if (ret == BOOTMENU_RET_QUIT) {
/* default boot process */
if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR))
--
2.17.1
M
RE: [PATCH v2] board: freescale: p1_p2_rdb_pc: Move boot reset macros to p1_p2_bootsrc.h
>-Original Message- >From: U-Boot On Behalf Of Pali Rohár >Sent: Monday, April 25, 2022 8:18 PM >To: Priyanka Jain ; Qiang Zhao ; >Shengzhou Liu ; Sinan Akman >Cc: u-boot@lists.denx.de >Subject: [PATCH v2] board: freescale: p1_p2_rdb_pc: Move boot reset macros to >p1_p2_bootsrc.h > >Code for changing boot source is platform generic and can be used by any >P1* and P2* compatible RDB board. Not only by boards which use config header >file p1_p2_rdb_pc.h. > >So move this code from p1_p2_rdb_pc.h to p1_p2_bootsrc.h and cleanup macros >for generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS. > >This allows to use code for resetting board and rebooting to other boot source >also by other boards in future. > >Signed-off-by: Pali Rohár >--- >Changes in v2: >* Fix commit message >* Move macros to file p1_p2_bootsrc.h >* Rewrite macros even more to be more generic and use them without custom > macros in p1_p2_rdb_pc.h >--- > include/configs/p1_p2_bootsrc.h | 55 + >include/configs/p1_p2_rdb_pc.h | 41 ++-- > 2 files changed, 64 insertions(+), 32 deletions(-) create mode 100644 >include/configs/p1_p2_bootsrc.h > >diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h >new file mode 100644 index ..a274c57786f5 >--- /dev/null >+++ b/include/configs/p1_p2_bootsrc.h >@@ -0,0 +1,55 @@ >+// SPDX-License-Identifier: GPL-2.0+ >+// (C) 2022 Pali Rohár >+ Code is copied from one file to another. Please don’t remove original copyright Regards Priyanka
