Re: [PATCH] SPI NOR: zynq_virt: enabling Gigadevice part # in zynq virt config file
On 12/11/22 03:21, Victor Lim wrote: CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email. Enabling Gigadevice part # in this config file The same issues as before. Fix subject, fix commit message Signed-off-by: Victor Lim Doesn't match. --- configs/xilinx_zynq_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 611c5e993c..6506cc7ecc 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -131,3 +131,4 @@ CONFIG_SPL_GZIP=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_SPI_FLASH_GIGADEVICE=y Incorrect location. M
Re: [PATCH] patch: SPI: NOR: zynqmp_virt: enabling Gigadevice part #
On 12/11/22 03:07, Victor Lim wrote: CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email. Enabling Gigadevice part # in this config file Signed-off-by: Victor Lim Email here doesn't match with email you used for sending. Please fix this. --- configs/xilinx_zynqmp_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index e63b19b911..f1e58426aa 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -218,3 +218,4 @@ CONFIG_EFI_SET_TIME=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_SPI_FLASH_GIGADEVICE=y Please place it to proper location not just append to the end. Thanks, Michal
Re: [PATCH] patch v2: SPI NOR: zynqmp: zynq: gd55lx02g
Title should be [PATCH V2] SPI NOR: zynqmp: zynq: gd55lx02g The commit need not contain patch version information. You can use the command: git format-patch -M -C -o mypatch --cover-letter --subject-prefix=" PATCH V2" -1 while generating the patch. On 11/12/22 21:25, Victor Lim wrote: adding gd55lx02g to the file Also, adding the flash vendor name, datasheet link would help. For example see https://lore.kernel.org/u-boot/be07aed81a6122f41d45a9f5a4390f1c194577e2.1624944246.git.takahiro.kuw...@infineon.com/ Please use that as a template. Signed-off-by: Victor Lim [...] -- Thanks and Regards, Dhruva Gole
Re: [PATCH 1/4] riscv: spl: Introduce SPL_OPENSBI_OS_BOOT
> On 12/7/22 01:23, Rick Chen wrote:
> > In RISC-V, it only provide normal mode booting currently.
> > To speed up the booting process, here provide SPL_OPENSBI_OS_BOOT
> > to achieve this feature which will be call Fast-Boot mode. By
>
> Can you name this something different. We already have something called
> fastboot in-tree (the Android-derived protocol) and there's a Microsoft
> technology called fastboot (some kind of hibernation). "OS Boot" isn't
> very specific either, since we (almost always) boot an OS. Maybe "Eagle
> mode" by analogy to Falcon mode, which lets SPL directly boot an OS.
I think fast boot is a behavior which shall be interpreted widely but
not proprietary.
Or maybe I can rename it as RISC-V Fast Boot to distinguish them.
>
> (Is this substantially different from falcon mode anyway?)
Please see the explanations to Tom.
>
> > enabling SPL_OPENSBI_OS_BOOT, it will generate linux.itb instead
> > of default u-boot.itb after compiling. It initializes memory with
> > the U-Boot SPL at the first stage, just like what a regular booting
> > process (i.e. Normal Boot) does in the beginning. Instead of jumping
> > to the U-Boot proper from OpenSBI before booting Linux Kernel, the
> > Fast Boot process jumps directly to Linux Kernel to gain shorter
> > booting time.
> >
> > Signed-off-by: Rick Chen
> > ---
> > common/spl/Kconfig | 14 ++
> > common/spl/spl_fit.c | 3 ++-
> > common/spl/spl_opensbi.c | 25 -
> > 3 files changed, 28 insertions(+), 14 deletions(-)
> >
> > diff --git a/common/spl/Kconfig b/common/spl/Kconfig
> > index 05181bdba3..8805aba1b7 100644
> > --- a/common/spl/Kconfig
> > +++ b/common/spl/Kconfig
> > @@ -1509,6 +1509,20 @@ config SPL_OPENSBI_SCRATCH_OPTIONS
> > Options passed to fw_dynamic, for example
> > SBI_SCRATCH_NO_BOOT_PRINTS or
> > SBI_SCRATCH_DEBUG_PRINTS.
> >
> > +config SPL_OPENSBI_OS_BOOT
>
> Please use the same name for the config as for the description.
>
> > + bool "openSBI Fast Boot"
> > + depends on SPL_OPENSBI
> > + help
> > + Enable this openSBI can jump to Linux Kernel directly.
>
> Can you put some of the explanation from the commit message here?
OK, I will move some messages here from commit messages.
>
> > +
> > +config SPL_OPENSBI_FIT_NAME
> > + string "SPL openSBI fit image name"
> > + depends on SPL_OPENSBI
> > + default "linux.itb" if SPL_OPENSBI_OS_BOOT
> > + default "u-boot.itb"
> > + help
> > + This will help to generate different fit name accordingly.
>
> Why not SPL_FS_LOAD_PAYLOAD_NAME?
>
> It looks like the code changes below do not use these configs. Can you
> move them to the next patch so it is clearer that they are for binman?
I have saw this config, but it does't support SPL_RAM but only for filesystem
That is why I don't leverage it.
I can prepare a patch as below if no other concerns:
config SPL_FS_LOAD_PAYLOAD_NAME
string "File to load for U-Boot from the filesystem"
depends on SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS || SPL_RAM
default "tispl.bin" if SYS_K3_SPL_ATF
default "u-boot.itb" if SPL_LOAD_FIT
default "linux.itb" if SPL_OPENSBI_OS_BOOT
default "u-boot.img"
help
Filename to read to load U-Boot when reading from filesystem.
Thanks,
Rick
>
> --Sean
>
> > config SPL_TARGET
> > string "Addtional build targets for 'make'"
> > default "spl/u-boot-spl.srec" if RCAR_GEN2
> > diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
> > index c1ed31e367..c5b1dfb3ba 100644
> > --- a/common/spl/spl_fit.c
> > +++ b/common/spl/spl_fit.c
> > @@ -363,7 +363,8 @@ static bool os_takes_devicetree(uint8_t os)
> > case IH_OS_U_BOOT:
> > return true;
> > case IH_OS_LINUX:
> > - return IS_ENABLED(CONFIG_SPL_OS_BOOT);
> > + return IS_ENABLED(CONFIG_SPL_OS_BOOT) ||
> > + IS_ENABLED(CONFIG_SPL_OPENSBI_OS_BOOT);
> > default:
> > return false;
> > }
> > diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
> > index b0f40076c3..83869c6b18 100644
> > --- a/common/spl/spl_opensbi.c
> > +++ b/common/spl/spl_opensbi.c
> > @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
> >
> > struct fw_dynamic_info opensbi_info;
> >
> > -static int spl_opensbi_find_uboot_node(void *blob, int *uboot_node)
> > +static int spl_opensbi_find_os_node(void *blob, int *os_node)
> > {
> > int fit_images_node, node;
> > const char *fit_os;
> > @@ -34,10 +34,9 @@ static int spl_opensbi_find_uboot_node(void *blob, int
> > *uboot_node)
> > if (!fit_os)
> > continue;
> >
> > - if (genimg_get_os_id(fit_os) == IH_OS_U_BOOT) {
> > - *uboot_node = node;
> > - return 0;
> > - }
> > + *os_node = node;
> > +
> > + return 0;
> > }
> >
> > return -ENODEV;
> > @@ -45,8 +44,8 @@ static int
Re: [PATCH] serial: Do not write additional \r before \n for dm_serial drivers
On 12/11/22 00:27, Pali Rohár wrote:
serial-uclass.c code already puts \r before \n for all dm_serial drivers.
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/serial/serial_lpuart.c | 3 ---
drivers/serial/serial_mpc8xx.c | 3 ---
2 files changed, 6 deletions(-)
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index ff576da516d4..07941c29ed74 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -349,9 +349,6 @@ static void _lpuart32_serial_putc(struct lpuart_serial_plat
*plat,
struct lpuart_fsl_reg32 *base = plat->reg;
u32 stat;
- if (c == '\n')
- serial_putc('\r');
-
while (true) {
lpuart_read32(plat->flags, >stat, );
diff --git a/drivers/serial/serial_mpc8xx.c b/drivers/serial/serial_mpc8xx.c
index aeae6ae6cd25..808a40f503ea 100644
--- a/drivers/serial/serial_mpc8xx.c
+++ b/drivers/serial/serial_mpc8xx.c
@@ -176,9 +176,6 @@ static int serial_mpc8xx_putc(struct udevice *dev, const
char c)
cpm8xx_t__iomem *cpmp = &(im->im_cpm);
struct serialbuffer __iomem *rtx;
- if (c == '\n')
- serial_mpc8xx_putc(dev, '\r');
-
rtx = (struct serialbuffer __iomem *)>cp_dpmem[CPM_SERIAL_BASE];
/* Wait for last character to go. */
Viele Grüße,
Stefan Roese
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH 1/4] riscv: spl: Introduce SPL_OPENSBI_OS_BOOT
Hi Tom > On Fri, Dec 09, 2022 at 08:48:37AM -0500, Sean Anderson wrote: > > On 12/7/22 01:23, Rick Chen wrote: > > > In RISC-V, it only provide normal mode booting currently. > > > To speed up the booting process, here provide SPL_OPENSBI_OS_BOOT > > > to achieve this feature which will be call Fast-Boot mode. By > > > > Can you name this something different. We already have something called > > fastboot in-tree (the Android-derived protocol) and there's a Microsoft > > technology called fastboot (some kind of hibernation). "OS Boot" isn't > > very specific either, since we (almost always) boot an OS. Maybe "Eagle > > mode" by analogy to Falcon mode, which lets SPL directly boot an OS. > > > > (Is this substantially different from falcon mode anyway?) > > I was kind of wondering if this is different, really, from Falcon Mode. > Falcon Mode didn't initially have to factor in other-firmware as that's > not a hard requirement on arm32 like it is on arm64 or risc-v. But my > first read of this was that it seems like the RISC-V specific side of > doing Falcon Mode and dealing with the prior stage needs correctly. > Yes. It is a little bit different from the Falcon mode (SPL_OS_BOOT=y). When I try to enable SPL_OS_BOOT, it will encounter that SYS_SPL_ARGS_ADDR and jump_to_image_linux() shall be defined but they are un-necessary for RISC-V. Because the flow of OpenSBI and SPL_OS_BOOT are totally different code flow in board_init_r() of common/spl/spl.c. That is why I added a new symbol called SPL_OPENSBI_OS_BOOT for this RISC-V fast boot implementation. Thanks, Rick > -- > Tom
[PATCH v1 17/17] configs: starfive: add starfive_visionfive2_defconfig
This is the initial basic config for StarFive VisionFive v2 board. It
includes consol, Norflash, sdio, ddr etc.
Signed-off-by: Yanhong Wang
---
configs/starfive_visionfive2_defconfig | 72 ++
1 file changed, 72 insertions(+)
create mode 100644 configs/starfive_visionfive2_defconfig
diff --git a/configs/starfive_visionfive2_defconfig
b/configs/starfive_visionfive2_defconfig
new file mode 100644
index 00..54ae6b2a43
--- /dev/null
+++ b/configs/starfive_visionfive2_defconfig
@@ -0,0 +1,72 @@
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x80
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="starfive_visionfive2"
+CONFIG_SPL_TEXT_BASE=0x800
+CONFIG_SYS_PROMPT="StarFive #"
+CONFIG_SPL_MMC=y
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x8200
+CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
+CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
+CONFIG_ARCH_RV64I=y
+CONFIG_CMODEL_MEDANY=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8000
+CONFIG_FIT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
+CONFIG_DEFAULT_FDT_FILE="starfive/starfive_visionfive2.dtb"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_BSS_START_ADDR=0x804
+CONFIG_SPL_BSS_MAX_SIZE=0x1
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0x818
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x8000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x40
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
+CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_JH7110=y
+# CONFIG_I2C is not set
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_SF_DEFAULT_SPEED=1
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_STARFIVE=y
+# CONFIG_RAM_SIFIVE is not set
+CONFIG_DM_RESET=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_TIMER_EARLY=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--
2.17.1
[PATCH v1 14/17] riscv: dts: jh7110: Add initial StarFive JH7110 device tree
Add initial device tree for the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang
---
arch/riscv/dts/jh7110.dtsi | 497 +
1 file changed, 497 insertions(+)
create mode 100644 arch/riscv/dts/jh7110.dtsi
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
new file mode 100644
index 00..49d34b85af
--- /dev/null
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -0,0 +1,497 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing
+ */
+
+/dts-v1/;
+
+#include
+#include
+
+/ {
+ compatible = "starfive,jh7110";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ S76_0: cpu@0 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <0>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <8192>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <16384>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <>;
+ riscv,isa = "rv64imacu";
+ tlb-split;
+ status = "disabled";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_1: cpu@1 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <1>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <>;
+ riscv,isa = "rv64imafdcbsu";
+ tlb-split;
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_2: cpu@2 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <2>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <>;
+ riscv,isa = "rv64imafdcbsu";
+ tlb-split;
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_3: cpu@3 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <3>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <>;
+ riscv,isa = "rv64imafdcbsu";
+ tlb-split;
+
+ cpu3_intc:
[PATCH v1 16/17] riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree
Add initial device tree for StarFive VisionFive v2 board.
Signed-off-by: Yanhong Wang
---
arch/riscv/dts/Makefile | 2 +-
.../dts/starfive_visionfive2-u-boot.dtsi | 66 +
arch/riscv/dts/starfive_visionfive2.dts | 234 ++
3 files changed, 301 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/dts/starfive_visionfive2-u-boot.dtsi
create mode 100644 arch/riscv/dts/starfive_visionfive2.dts
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 5c15a0f303..0351cc0c38 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -7,7 +7,7 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += starfive_visionfive2.dtb
include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y)
diff --git a/arch/riscv/dts/starfive_visionfive2-u-boot.dtsi
b/arch/riscv/dts/starfive_visionfive2-u-boot.dtsi
new file mode 100644
index 00..60f93d5830
--- /dev/null
+++ b/arch/riscv/dts/starfive_visionfive2-u-boot.dtsi
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include "binman.dtsi"
+#include "jh7110-u-boot.dtsi"
+/ {
+ chosen {
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ spi0 =
+ u-boot,dm-spl;
+ };
+
+ config {
+ u-boot,dm-spl;
+ u-boot,spl-payload-offset = <0x10>;
+ };
+
+ memory@4000 {
+ u-boot,dm-spl;
+ };
+};
+
+_syscon {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+
+ nor-flash@0 {
+ u-boot,dm-spl;
+ };
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
diff --git a/arch/riscv/dts/starfive_visionfive2.dts
b/arch/riscv/dts/starfive_visionfive2.dts
new file mode 100644
index 00..52b31546da
--- /dev/null
+++ b/arch/riscv/dts/starfive_visionfive2.dts
@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "jh7110.dtsi"
+#include
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "StarFive VisionFive V2";
+ compatible = "starfive,jh7110";
+
+ aliases {
+ spi0 =
+ mmc0 =
+ mmc1 =
+ };
+
+ chosen {
+ stdout-path = "/soc/serial@1000:115200";
+ };
+
+ cpus {
+ timebase-frequency = <400>;
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x0 0x4000 0x1 0x0>;
+ };
+
+ soc {
+ sys_syscon: sys_syscon@1303 {
+ compatible = "syscon";
+ reg = <0x0 0x1303 0x0 0x1000>;
+ };
+ };
+};
+
+_0 {
+ status = "okay";
+};
+
+ {
+ clock-frequency = <2400>;
+};
+
+_rtc {
+ clock-frequency = <32768>;
+};
+
+_rmii_refin {
+ clock-frequency = <5000>;
+};
+
+_rgmii_rxin {
+ clock-frequency = <12500>;
+};
+
+_rmii_refin {
+ clock-frequency = <5000>;
+};
+
+_rgmii_rxin {
+ clock-frequency = <12500>;
+};
+
+_bclk_ext {
+ clock-frequency = <12288000>;
+};
+
+_lrck_ext {
+ clock-frequency = <192000>;
+};
+
+_bclk_ext {
+ clock-frequency = <12288000>;
+};
+
+_lrck_ext {
+ clock-frequency = <192000>;
+};
+
+_ext {
+ clock-frequency = <49152000>;
+};
+
+_ext {
+ clock-frequency = <12288000>;
+};
+
+ {
+ status = "okay";
+ uart0_pins: uart0-0 {
+ tx-pins {
+ pinmux = ;
+ bias-disable;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ rx-pins {
+ pinmux = ;
+ bias-pull-up;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+
+ mmc0_pins: mmc0-pins {
+mmc0-pins-rest {
+ pinmux = ;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ sdcard1_pins:
[PATCH v1 15/17] riscv: dts: jh7110: Add initial u-boot device tree
Add initial u-boot device tree for the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang
---
arch/riscv/dts/jh7110-u-boot.dtsi | 86 +++
1 file changed, 86 insertions(+)
create mode 100644 arch/riscv/dts/jh7110-u-boot.dtsi
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi
b/arch/riscv/dts/jh7110-u-boot.dtsi
new file mode 100644
index 00..243237e83a
--- /dev/null
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include
+
+/ {
+ cpus: cpus {
+ u-boot,dm-spl;
+
+ cpu0: cpu@0 {
+ u-boot,dm-spl;
+ status = "okay";
+ cpu0_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+
+ cpu1: cpu@1 {
+ u-boot,dm-spl;
+ cpu1_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+
+ cpu2: cpu@2 {
+ u-boot,dm-spl;
+ cpu2_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+
+ cpu3: cpu@3 {
+ u-boot,dm-spl;
+ cpu3_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+
+ cpu4: cpu@4 {
+ u-boot,dm-spl;
+ cpu4_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ };
+
+ soc {
+ u-boot,dm-spl;
+
+ clint: clint@200 {
+ u-boot,dm-spl;
+ };
+
+ dmc: dmc@1570 {
+ u-boot,dm-spl;
+ compatible = "starfive,jh7110-dmc";
+ reg = <0x0 0x1570 0x0 0x1>,
+ <0x0 0x1300 0x0 0x1>;
+ resets = < JH7110_SYSRST_DDR_AXI>,
+ < JH7110_SYSRST_DDR_OSC>,
+ < JH7110_SYSRST_DDR_APB>;
+ reset-names = "axi", "osc", "apb";
+ clocks = < JH7110_SYSCLK_PLL1_OUT>;
+ clock-names = "pll1";
+ clock-frequency = <2133>;
+ };
+ };
+};
+
+_rmii_refin {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
--
2.17.1
[PATCH v1 13/17] board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig
Add board support for StarFive VisionFive v2. Signed-off-by: Yanhong Wang --- arch/riscv/Kconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ebc4bef220..e341c364f1 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -24,6 +24,9 @@ config TARGET_SIFIVE_UNMATCHED bool "Support SiFive Unmatched Board" select SYS_CACHE_SHIFT_6 +config TARGET_STARFIVE_VISIONFIVE2 + bool "Support StarFive VisionFive2 Board" + config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" select SYS_CACHE_SHIFT_6 @@ -65,12 +68,14 @@ source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" +source "board/starfive/visionfive2/Kconfig" # platform-specific options below source "arch/riscv/cpu/ax25/Kconfig" source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/generic/Kconfig" +source "arch/riscv/cpu/jh7110/Kconfig" # architecture-specific options below -- 2.17.1
[PATCH v1 08/17] pinctrl: starfive: Add StarFive JH7110 driver
From: Kuan Lim Lee
Add pinctrl driver for StarFive JH7110 SoC.
Signed-off-by: Kuan Lim Lee
Signed-off-by: Emil Renner Berthing
Signed-off-by: Jianlong Huang
Signed-off-by: Yanhong Wang
---
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/starfive/Kconfig | 16 +
drivers/pinctrl/starfive/Makefile | 6 +
drivers/pinctrl/starfive/pinctrl-jh7110-aon.c | 113 +
drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 399
drivers/pinctrl/starfive/pinctrl-starfive.c | 428 ++
drivers/pinctrl/starfive/pinctrl-starfive.h | 55 +++
8 files changed, 1019 insertions(+)
create mode 100644 drivers/pinctrl/starfive/Kconfig
create mode 100644 drivers/pinctrl/starfive/Makefile
create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-aon.c
create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.c
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.h
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index b6ef2acced..75b3ff47a2 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -359,5 +359,6 @@ source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/rockchip/Kconfig"
source "drivers/pinctrl/sunxi/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
+source "drivers/pinctrl/starfive/Kconfig"
endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 3b167d099f..852adee4b4 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -32,3 +32,4 @@ obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o
obj-$(CONFIG_$(SPL_)PINCTRL_STMFX) += pinctrl-stmfx.o
obj-y += broadcom/
obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o
+obj-$(CONFIG_PINCTRL_STARFIVE) += starfive/
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
new file mode 100644
index 00..ece05b25d3
--- /dev/null
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config PINCTRL_STARFIVE
+ bool "Pinctrl driver for StarFive SoC"
+ depends on PINCTRL_FULL
+ help
+ Say yes here to support pin control on the StarFive RISC-V SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
+
+config PINCTRL_STARFIVE_JH7110
+ bool "Pinctrl and GPIO driver for StarFive JH7110 SoC"
+ depends on PINCTRL_STARFIVE
+ help
+ This selects the pinctrl driver for JH7110 starfive.
diff --git a/drivers/pinctrl/starfive/Makefile
b/drivers/pinctrl/starfive/Makefile
new file mode 100644
index 00..e4caa4cbb7
--- /dev/null
+++ b/drivers/pinctrl/starfive/Makefile
@@ -0,0 +1,6 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Core
+obj-$(CONFIG_PINCTRL_STARFIVE) += pinctrl-starfive.o
+# SoC Drivers
+obj-$(CONFIG_PINCTRL_STARFIVE_JH7110) += pinctrl-jh7110-sys.o
pinctrl-jh7110-aon.o
diff --git a/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c
b/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c
new file mode 100644
index 00..54ffe32481
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-jh7110-aon.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl / GPIO driver for StarFive JH7110 SoC
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Lee Kuan Lim
+ * Author: Jianlong Huang
+ */
+
+#include
+#include
+#include
+
+#include
+#include "pinctrl-starfive.h"
+
+#define JH7110_AON_NGPIO 4
+#define JH7110_AON_GC_BASE 64
+
+/* registers */
+#define JH7110_AON_DOEN0x0
+#define JH7110_AON_DOUT0x4
+#define JH7110_AON_GPI 0x8
+#define JH7110_AON_GPIOIN 0x2c
+
+#define JH7110_AON_GPIOEN 0xc
+#define JH7110_AON_GPIOIS 0x10
+#define JH7110_AON_GPIOIC 0x14
+#define JH7110_AON_GPIOIBE 0x18
+#define JH7110_AON_GPIOIEV 0x1c
+#define JH7110_AON_GPIOIE 0x20
+#define JH7110_AON_GPIORIS 0x28
+#define JH7110_AON_GPIOMIS 0x28
+
+#define AON_GPO_PDA_0_5_CFG0x30
+
+static int jh7110_aon_set_one_pin_mux(struct udevice *dev, unsigned int pin,
+ unsigned int din, u32 dout,
+ u32 doen, u32 func)
+{
+ struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+
+ if (pin < priv->info->ngpios && func == 0)
+ starfive_set_gpiomux(dev, pin, din, dout, doen);
+
+ return 0;
+}
+
+static int jh7110_aon_get_padcfg_base(struct udevice *dev,
+ unsigned int pin)
+{
+ if (pin < PAD_GMAC0_MDC)
+ return
[PATCH v1 12/17] board: starfive: Add Kconfig for StarFive VisionFive v2 Board
Add Kconfig to select the basic functions for StarFive VisionFive v2 Board. Signed-off-by: Yanhong Wang --- board/starfive/visionfive2/Kconfig | 53 ++ 1 file changed, 53 insertions(+) create mode 100644 board/starfive/visionfive2/Kconfig diff --git a/board/starfive/visionfive2/Kconfig b/board/starfive/visionfive2/Kconfig new file mode 100644 index 00..2186a93964 --- /dev/null +++ b/board/starfive/visionfive2/Kconfig @@ -0,0 +1,53 @@ +if TARGET_STARFIVE_VISIONFIVE2 + +config SYS_CPU + default "jh7110" + +config SYS_BOARD + default "visionfive2" + +config SYS_VENDOR + default "starfive" + +config SYS_CONFIG_NAME + default "starfive-visionfive2" + +config TEXT_BASE + default 0x4020 if SPL + default 0x4000 if !RISCV_SMODE + default 0x4020 if RISCV_SMODE + +config SPL_TEXT_BASE + default 0x0800 + +config SPL_OPENSBI_LOAD_ADDR + default 0x8000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select STARFIVE_JH7110 + select SUPPORT_SPL + select BINMAN + imply CMD_CPU + imply CMD_DHCP + imply CMD_EXT2 + imply CMD_EXT4 + imply CMD_FAT + imply CMD_FS_GENERIC + imply CMD_GPIO + imply CMD_GPT + imply CMD_MMC + imply CMD_NET + imply CMD_PING + imply CMD_SF + imply DM_GPIO + imply DOS_PARTITION + imply EFI_PARTITION + imply MII + imply IP_DYN + imply ISO_PARTITION + imply PARTITION_TYPE_GUID + imply PHY_LIB + imply PHY_MSCC + +endif -- 2.17.1
[PATCH v1 09/17] ram: starfive: add ddr driver
Add driver for StarFive JH7110 to support ddr initialization in SPL.
Signed-off-by: Yanhong Wang
---
drivers/ram/Kconfig |1 +
drivers/ram/Makefile|4 +-
drivers/ram/starfive/Kconfig|5 +
drivers/ram/starfive/Makefile | 11 +
drivers/ram/starfive/ddrcsr_boot.c | 340 +
drivers/ram/starfive/ddrphy_start.c | 280
drivers/ram/starfive/ddrphy_train.c | 384 ++
drivers/ram/starfive/ddrphy_utils.c | 1956 +++
drivers/ram/starfive/starfive_ddr.c | 162 +++
drivers/ram/starfive/starfive_ddr.h | 66 +
10 files changed, 3208 insertions(+), 1 deletion(-)
create mode 100644 drivers/ram/starfive/Kconfig
create mode 100644 drivers/ram/starfive/Makefile
create mode 100644 drivers/ram/starfive/ddrcsr_boot.c
create mode 100644 drivers/ram/starfive/ddrphy_start.c
create mode 100644 drivers/ram/starfive/ddrphy_train.c
create mode 100644 drivers/ram/starfive/ddrphy_utils.c
create mode 100644 drivers/ram/starfive/starfive_ddr.c
create mode 100644 drivers/ram/starfive/starfive_ddr.h
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 86857c0627..91882d9328 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -101,3 +101,4 @@ source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/sifive/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
source "drivers/ram/octeon/Kconfig"
+source "drivers/ram/starfive/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 5a39611349..f709893fa2 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -20,5 +20,7 @@ obj-$(CONFIG_K3_DDRSS) += k3-ddrss/
obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
obj-$(CONFIG_RAM_SIFIVE) += sifive/
-
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/
+endif
obj-$(CONFIG_ARCH_OCTEON) += octeon/
diff --git a/drivers/ram/starfive/Kconfig b/drivers/ram/starfive/Kconfig
new file mode 100644
index 00..80c790066f
--- /dev/null
+++ b/drivers/ram/starfive/Kconfig
@@ -0,0 +1,5 @@
+config SPL_STARFIVE_DDR
+ bool "StarFive DDR driver in SPL"
+ depends on SPL_RAM && STARFIVE_JH7110
+ help
+ This enables DDR support for the platforms based on StarFive JH7110
SoC.
diff --git a/drivers/ram/starfive/Makefile b/drivers/ram/starfive/Makefile
new file mode 100644
index 00..1df42c377b
--- /dev/null
+++ b/drivers/ram/starfive/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2022 StarFive, Inc
+#
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_start.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_train.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive_ddr.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_utils.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrcsr_boot.o
+endif
\ No newline at end of file
diff --git a/drivers/ram/starfive/ddrcsr_boot.c
b/drivers/ram/starfive/ddrcsr_boot.c
new file mode 100644
index 00..e17cb251d1
--- /dev/null
+++ b/drivers/ram/starfive/ddrcsr_boot.c
@@ -0,0 +1,340 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "starfive_ddr.h"
+
+#define REGOFFSET(offset) ((offset) / 4)
+
+static const struct ddr_reg_cfg ddr_csr_cfg[] = {
+ {0x0, 0x0,0x0001, REGSETALL},
+ {0xf00, 0x0,0x40001030, (OFFSET_SEL | F_SET | REG4G |
REG8G)},
+ {0xf00, 0x0,0x40001030, (OFFSET_SEL | F_SET | REG2G)},
+ {0xf04, 0x0,0x0001, (OFFSET_SEL | F_SET | REG4G |
REG8G)},
+ {0xf04, 0x0,0x0081, (OFFSET_SEL | F_SET | REG2G)},
+ {0xf10, 0x0,0x0040, (OFFSET_SEL | REGSETALL)},
+ {0xf14, 0x0,0x043f, (OFFSET_SEL | REGSETALL)},
+ {0xf18, 0x0,0x, (OFFSET_SEL | REGSETALL)},
+ {0xf30, 0x0,0x1f41, (OFFSET_SEL | REGSETALL)},
+ {0xf34, 0x0,0x1f41, (OFFSET_SEL | F_SET | REG4G |
REG8G)},
+ {0x110, 0x0,0xc001, (OFFSET_SEL | REGSETALL)},
+ {0x114, 0x0,0x, (OFFSET_SEL | REGSETALL)},
+ {0x10c, 0x0,0x0505, REGSETALL},
+ {0x11c, 0x0,0x, REGSETALL},
+ {0x500, 0x0,0x0201, REGSETALL},
+ {0x514, 0x0,0x0100, REGSETALL},
+ {0x6a8, 0x0,0x0004, REGSETALL},
+ {0xea8, 0x0,0x0004, REGSETALL},
+ {0x504, 0x0,0x4000, REGSETALL}
+};
+
+static const struct ddr_reg_cfg ddr_csr_cfg1[] = {
+ {0x310, 0x0,0x0002, REGSETALL},
+ {0x310, 0x0,0x00020001, REGSETALL},
+ {0x600, 0x0,0x002e0176, REGSETALL},
+ {0x604, 0x0,0x002e0176,
[PATCH v1 10/17] board: starfive: add StarFive VisionFive v2 board support
Add board support for StarFive VisionFive v2.
Signed-off-by: Yanhong Wang
---
board/starfive/visionfive2/MAINTAINERS| 7 ++
board/starfive/visionfive2/Makefile | 7 ++
board/starfive/visionfive2/spl.c | 119 ++
.../visionfive2/starfive_visionfive2.c| 39 ++
include/configs/starfive-visionfive2.h| 18 +++
5 files changed, 190 insertions(+)
create mode 100644 board/starfive/visionfive2/MAINTAINERS
create mode 100644 board/starfive/visionfive2/Makefile
create mode 100644 board/starfive/visionfive2/spl.c
create mode 100644 board/starfive/visionfive2/starfive_visionfive2.c
create mode 100644 include/configs/starfive-visionfive2.h
diff --git a/board/starfive/visionfive2/MAINTAINERS
b/board/starfive/visionfive2/MAINTAINERS
new file mode 100644
index 00..c5369086d8
--- /dev/null
+++ b/board/starfive/visionfive2/MAINTAINERS
@@ -0,0 +1,7 @@
+STARFIVE JH7110 VISIONFIVE2 BOARD
+M: startfive
+S: Maintained
+F: arch/riscv/include/asm/arch-jh7110/
+F: board/starfive/visionfive2/
+F: include/configs/starfive-visionfive2.h
+F: configs/starfive_visionfive2_defconfig
diff --git a/board/starfive/visionfive2/Makefile
b/board/starfive/visionfive2/Makefile
new file mode 100644
index 00..66c854df39
--- /dev/null
+++ b/board/starfive/visionfive2/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 StarFive Technology Co., Ltd.
+#
+
+obj-y := starfive_visionfive2.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
new file mode 100644
index 00..473689eb71
--- /dev/null
+++ b/board/starfive/visionfive2/spl.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define JH7110_CLK_CPU_ROOT_OFFSET 0x0U
+#define JH7110_CLK_CPU_ROOT_SHIFT 24
+#define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24)
+#define JH7110_CLK_BUS_ROOT_OFFSET 0x14U
+#define JH7110_CLK_BUS_ROOT_SHIFT 24
+#define JH7110_CLK_BUS_ROOT_MASK GENMASK(29, 24)
+#define JH7110_CLK_PERH_ROOT_OFFSET0x10U
+#define JH7110_CLK_PERH_ROOT_SHIFT 24
+#define JH7110_CLK_PERH_ROOT_MASK GENMASK(29, 24)
+#define JH7110_CLK_NOC_BUS_STG_AXI_OFFSET 0x180U
+#define JH7110_CLK_NOC_BUS_STG_AXI_SHIFT 31
+#define JH7110_CLK_NOC_BUS_STG_AXI_MASKBIT(31)
+#define JH7110_CLK_AON_APB_FUNC_OFFSET 0x4U
+#define JH7110_CLK_AON_APB_FUNC_SHIFT 24
+#define JH7110_CLK_AON_APB_FUNC_MASK GENMASK(29, 24)
+#define JH7110_CLK_QSPI_REF_OFFSET 0x168U
+#define JH7110_CLK_QSPI_REF_SHIFT 24
+#define JH7110_CLK_QSPI_REF_MASK GENMASK(29, 24)
+
+#define SET_DIV(type, val) \
+ clrsetbits_le32(JH7110_SYS_CRG + JH7110_CLK_##type##_OFFSET, \
+ JH7110_CLK_##type##_MASK, \
+ ((val) << JH7110_CLK_##type##_SHIFT) & JH7110_CLK_##type##_MASK)
+
+int spl_board_init_f(void)
+{
+ int ret;
+
+ ret = spl_soc_init();
+ if (ret) {
+ debug("JH7110 SPL init failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+u32 spl_boot_device(void)
+{
+ u32 mode;
+
+ mode = in_le32(JH7110_BOOT_MODE_SELECT_REG)
+ & JH7110_BOOT_MODE_SELECT_MASK;
+ switch (mode) {
+ case 0:
+ return BOOT_DEVICE_SPI;
+
+ case 1:
+ return BOOT_DEVICE_MMC2;
+
+ case 2:
+ return BOOT_DEVICE_MMC1;
+
+ case 3:
+ return BOOT_DEVICE_UART;
+
+ default:
+ debug("Unsupported boot device 0x%x.\n", mode);
+ return BOOT_DEVICE_NONE;
+ }
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ ret = spl_early_init();
+ if (ret)
+ panic("spl_early_init() failed: %d\n", ret);
+
+ riscv_cpu_setup(NULL, NULL);
+ preloader_console_init();
+
+ /* select clk_pll0 by default */
+ SET_DIV(CPU_ROOT, 1);
+
+ /* select clk_pll2 by default */
+ SET_DIV(BUS_ROOT, 1);
+
+ /* select clk_pll2 by default */
+ SET_DIV(PERH_ROOT, 1);
+
+ SET_DIV(NOC_BUS_STG_AXI, 1);
+
+ clrsetbits_le32(JH7110_AON_CRG + JH7110_CLK_AON_APB_FUNC_OFFSET,
+ JH7110_CLK_AON_APB_FUNC_MASK,
+ BIT(JH7110_CLK_AON_APB_FUNC_SHIFT));
+
+ /* select clk_pll0 by default */
+ SET_DIV(QSPI_REF, 1);
+
+ ret = spl_board_init_f();
+ if (ret) {
+ debug("spl_board_init_f init failed: %d\n", ret);
+ return;
+ }
+}
+
+#if CONFIG_IS_ENABLED(SPL_LOAD_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ /*
[PATCH v1 11/17] riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC
Add Kconfig to select the basic functions for StarFive JH7110 SoC. Signed-off-by: Yanhong Wang --- arch/riscv/cpu/jh7110/Kconfig | 28 1 file changed, 28 insertions(+) create mode 100644 arch/riscv/cpu/jh7110/Kconfig diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig new file mode 100644 index 00..3f145415eb --- /dev/null +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022 StarFive Technology Co., Ltd. + +config STARFIVE_JH7110 + bool + select ARCH_EARLY_INIT_R + select CLK_JH7110 + select CPU + select CPU_RISCV + select RAM + select RESET_JH7110 + select SUPPORT_SPL + select SPL_RAM if SPL + select SPL_STARFIVE_DDR + select PINCTRL_STARFIVE_JH7110 + imply MMC + imply MMC_BROKEN_CD + imply MMC_SPI + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply SIFIVE_CACHE + imply SIFIVE_CCACHE + imply SMP + imply SPI + imply SPL_CPU + imply SPL_LOAD_FIT + imply SPL_OPENSBI + imply SPL_SIFIVE_CLINT -- 2.17.1
[PATCH v1 07/17] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions
From: Jianlong Huang Add pinctrl definitions for StarFive JH7110 SoC. Signed-off-by: Kuan Lim Lee Signed-off-by: Emil Renner Berthing Signed-off-by: Jianlong Huang Signed-off-by: Yanhong Wang --- .../pinctrl/pinctrl-starfive-jh7110.h | 427 ++ 1 file changed, 427 insertions(+) create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h diff --git a/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h new file mode 100644 index 00..fb02345caa --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h @@ -0,0 +1,427 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2022 Emil Renner Berthing + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__ +#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__ + +/* + * mux bits: + * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 | + * | din| dout | doen | function | gpio nr | + * + * dout: output signal + * doen: output enable signal + * din: optional input signal, 0xff = none + * function: + * gpio nr: gpio number, 0 - 63 + */ +#define GPIOMUX(n, dout, doen, din) ( \ + (((din) & 0xff) << 24) | \ + (((dout) & 0xff) << 16) | \ + (((doen) & 0x3f) << 10) | \ + ((n) & 0x3f)) + +#define PINMUX(n, func) ((1 << 10) | (((func) & 0x3) << 8) | ((n) & 0xff)) + +/* sys_iomux pin */ +#definePAD_GPIO00 +#definePAD_GPIO11 +#definePAD_GPIO22 +#definePAD_GPIO33 +#definePAD_GPIO44 +#definePAD_GPIO55 +#definePAD_GPIO66 +#definePAD_GPIO77 +#definePAD_GPIO88 +#definePAD_GPIO99 +#definePAD_GPIO10 10 +#definePAD_GPIO11 11 +#definePAD_GPIO12 12 +#definePAD_GPIO13 13 +#definePAD_GPIO14 14 +#definePAD_GPIO15 15 +#definePAD_GPIO16 16 +#definePAD_GPIO17 17 +#definePAD_GPIO18 18 +#definePAD_GPIO19 19 +#definePAD_GPIO20 20 +#definePAD_GPIO21 21 +#definePAD_GPIO22 22 +#definePAD_GPIO23 23 +#definePAD_GPIO24 24 +#definePAD_GPIO25 25 +#definePAD_GPIO26 26 +#definePAD_GPIO27 27 +#definePAD_GPIO28 28 +#definePAD_GPIO29 29 +#definePAD_GPIO30 30 +#definePAD_GPIO31 31 +#definePAD_GPIO32 32 +#definePAD_GPIO33 33 +#definePAD_GPIO34 34 +#definePAD_GPIO35 35 +#definePAD_GPIO36 36 +#definePAD_GPIO37 37 +#definePAD_GPIO38 38 +#definePAD_GPIO39 39 +#definePAD_GPIO40 40 +#definePAD_GPIO41 41 +#definePAD_GPIO42 42 +#definePAD_GPIO43 43 +#definePAD_GPIO44 44 +#definePAD_GPIO45 45 +#definePAD_GPIO46 46 +#definePAD_GPIO47 47 +#definePAD_GPIO48 48 +#definePAD_GPIO49 49 +#definePAD_GPIO50 50 +#definePAD_GPIO51 51 +#definePAD_GPIO52 52 +#definePAD_GPIO53 53 +#definePAD_GPIO54 54 +#definePAD_GPIO55 55 +#definePAD_GPIO56 56 +#definePAD_GPIO57 57 +#definePAD_GPIO58 58 +#definePAD_GPIO59 59 +#definePAD_GPIO60 60 +#definePAD_GPIO61 61 +#definePAD_GPIO62 62 +#definePAD_GPIO63 63 +#definePAD_SD0_CLK 64 +#definePAD_SD0_CMD 65 +#definePAD_SD0_DATA0 66 +#definePAD_SD0_DATA1 67 +#definePAD_SD0_DATA2 68 +#definePAD_SD0_DATA3 69 +#definePAD_SD0_DATA4 70 +#definePAD_SD0_DATA5 71 +#definePAD_SD0_DATA6 72 +#definePAD_SD0_DATA7 73 +#definePAD_SD0_STRB74 +#definePAD_GMAC1_MDC 75 +#definePAD_GMAC1_MDIO 76 +#definePAD_GMAC1_RXD0 77 +#definePAD_GMAC1_RXD1 78 +#definePAD_GMAC1_RXD2 79 +#definePAD_GMAC1_RXD3 80 +#definePAD_GMAC1_RXDV 81 +#definePAD_GMAC1_RXC 82 +#definePAD_GMAC1_TXD0 83 +#definePAD_GMAC1_TXD1 84 +#definePAD_GMAC1_TXD2 85 +#definePAD_GMAC1_TXD3 86 +#definePAD_GMAC1_TXEN 87 +#definePAD_GMAC1_TXC 88 +#definePAD_QSPI_SCLK 89 +#definePAD_QSPI_CS090 +#definePAD_QSPI_DATA0 91 +#definePAD_QSPI_DATA1 92 +#definePAD_QSPI_DATA2 93 +#definePAD_QSPI_DATA3 94 + +/* aon_iomux pin */ +#definePAD_TESTEN 0 +#definePAD_RGPIO0 1 +#definePAD_RGPIO1 2 +#definePAD_RGPIO2
[PATCH v1 06/17] clk: starfive: Add StarFive JH7110 clock driver
Add a DM clock driver for StarFive JH7110 SoC. Signed-off-by: Yanhong Wang --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/starfive/Kconfig | 15 + drivers/clk/starfive/Makefile | 4 + drivers/clk/starfive/clk-jh7110-pll.c | 362 ++ drivers/clk/starfive/clk-jh7110.c | 651 ++ drivers/clk/starfive/clk.h| 42 ++ 7 files changed, 1076 insertions(+) create mode 100644 drivers/clk/starfive/Kconfig create mode 100644 drivers/clk/starfive/Makefile create mode 100644 drivers/clk/starfive/clk-jh7110-pll.c create mode 100644 drivers/clk/starfive/clk-jh7110.c create mode 100644 drivers/clk/starfive/clk.h diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 09aa97ee8c..4d60c84aad 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -235,6 +235,7 @@ source "drivers/clk/owl/Kconfig" source "drivers/clk/renesas/Kconfig" source "drivers/clk/sunxi/Kconfig" source "drivers/clk/sifive/Kconfig" +source "drivers/clk/starfive/Kconfig" source "drivers/clk/stm32/Kconfig" source "drivers/clk/tegra/Kconfig" source "drivers/clk/ti/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index c274cda77c..66f5860356 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o obj-y += analogbits/ obj-y += imx/ +obj-$(CONFIG_CLK_JH7110) += starfive/ obj-y += tegra/ obj-y += ti/ obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/ diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig new file mode 100644 index 00..e4bf2a5c5e --- /dev/null +++ b/drivers/clk/starfive/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0+ + +config SPL_CLK_JH7110 + bool "SPL clock support for JH7110" + depends on STARFIVE_JH7110 && SPL + select SPL_CLK + select SPL_CLK_CCF + help + This enables SPL DM support for clock driver in JH7110. + +config CLK_JH7110 + bool "StarFive JH7110 clock support" + depends on CLK && CLK_CCF && STARFIVE_JH7110 + help + This enables support clock driver for StarFive JH7110 SoC platform. diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile new file mode 100644 index 00..ec0d157094 --- /dev/null +++ b/drivers/clk/starfive/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += clk-jh7110.o +obj-y += clk-jh7110-pll.o diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c new file mode 100644 index 00..8be9500b62 --- /dev/null +++ b/drivers/clk/starfive/clk-jh7110-pll.c @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * + * Author: Yanhong Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define UBOOT_DM_CLK_JH7110_PLLX "jh7110_clk_pllx" + +#define PLL0_DACPD_MASKBIT(24) +#define PLL0_DSMPD_MASKBIT(25) +#define PLL0_FBDIV_MASKGENMASK(11, 0) +#define PLL0_FRAC_MASK GENMASK(23, 0) +#define PLL0_PD_MASK BIT(27) +#define PLL0_POSTDIV1_MASK GENMASK(29, 28) +#define PLL0_PREDIV_MASK GENMASK(5, 0) +#define PLL1_DACPD_MASKBIT(15) +#define PLL1_DSMPD_MASKBIT(16) +#define PLL1_FBDIV_MASKGENMASK(28, 17) +#define PLL1_FRAC_MASK GENMASK(23, 0) +#define PLL1_PD_MASK BIT(27) +#define PLL1_POSTDIV1_MASK GENMASK(29, 28) +#define PLL1_PREDIV_MASK GENMASK(5, 0) +#define PLL2_DACPD_MASKBIT(15) +#define PLL2_DSMPD_MASKBIT(16) +#define PLL2_FBDIV_MASKGENMASK(28, 17) +#define PLL2_FRAC_MASK GENMASK(23, 0) +#define PLL2_PD_MASK BIT(27) +#define PLL2_POSTDIV1_MASK GENMASK(29, 28) +#define PLL2_PREDIV_MASK GENMASK(5, 0) + +#define PLL0_DACPD_OFFSET 0x18 +#define PLL0_DSMPD_OFFSET 0x18 +#define PLL0_FBDIV_OFFSET 0x1C +#define PLL0_FRAC_OFFSET 0x20 +#define PLL0_PD_OFFSET 0x20 +#define PLL0_POSTDIV1_OFFSET 0x20 +#define PLL0_PREDIV_OFFSET 0x24 +#define PLL1_DACPD_OFFSET 0x24 +#define PLL1_DSMPD_OFFSET 0x24 +#define PLL1_FBDIV_OFFSET 0x24 +#define PLL1_FRAC_OFFSET 0x28 +#define PLL1_PD_OFFSET 0x28 +#define PLL1_POSTDIV1_OFFSET 0x28 +#define PLL1_PREDIV_OFFSET 0x2c +#define PLL2_DACPD_OFFSET 0x2c +#define PLL2_DSMPD_OFFSET 0x2c +#define PLL2_FBDIV_OFFSET 0x2c +#define PLL2_FRAC_OFFSET 0x30 +#define PLL2_PD_OFFSET 0x30 +#define PLL2_POSTDIV1_OFFSET 0x30 +#define PLL2_PREDIV_OFFSET 0x34 + +#define PLL_PD_OFF 1 +#define PLL_PD_ON 0 + +#define CLK_DDR_BUS_MASK GENMASK(29, 24) +#define CLK_DDR_BUS_OFFSET 0xAC +#define CLK_DDR_BUS_OSC_DIV2 0 +#define
[PATCH v1 05/17] dt-bindings: clock: Add StarFive JH7110 clock definitions
Add all clock outputs for the StarFive JH7110 clock generator. Signed-off-by: Yanhong Wang --- include/dt-bindings/clock/starfive-jh7110.h | 271 1 file changed, 271 insertions(+) create mode 100644 include/dt-bindings/clock/starfive-jh7110.h diff --git a/include/dt-bindings/clock/starfive-jh7110.h b/include/dt-bindings/clock/starfive-jh7110.h new file mode 100644 index 00..7f939e0ce4 --- /dev/null +++ b/include/dt-bindings/clock/starfive-jh7110.h @@ -0,0 +1,271 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * + * Author: Yanhong Wang + */ + +#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CLOCK_H__ +#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CLOCK_H__ + +#define JH7110_SYSCLK_CPU_ROOT 0 +#define JH7110_SYSCLK_CPU_CORE 1 +#define JH7110_SYSCLK_CPU_BUS 2 +#define JH7110_SYSCLK_GPU_ROOT 3 +#define JH7110_SYSCLK_PERH_ROOT4 +#define JH7110_SYSCLK_BUS_ROOT 5 +#define JH7110_SYSCLK_NOCSTG_BUS 6 +#define JH7110_SYSCLK_AXI_CFG0 7 +#define JH7110_SYSCLK_STG_AXIAHB 8 +#define JH7110_SYSCLK_AHB0 9 +#define JH7110_SYSCLK_AHB1 10 +#define JH7110_SYSCLK_APB_BUS_FUNC 11 +#define JH7110_SYSCLK_APB0 12 +#define JH7110_SYSCLK_PLL0_DIV213 +#define JH7110_SYSCLK_PLL1_DIV214 +#define JH7110_SYSCLK_PLL2_DIV215 +#define JH7110_SYSCLK_AUDIO_ROOT 16 +#define JH7110_SYSCLK_MCLK_INNER 17 +#define JH7110_SYSCLK_MCLK 18 +#define JH7110_SYSCLK_MCLK_OUT 19 +#define JH7110_SYSCLK_ISP_2X 20 +#define JH7110_SYSCLK_ISP_AXI 21 +#define JH7110_SYSCLK_GCLK022 +#define JH7110_SYSCLK_GCLK123 +#define JH7110_SYSCLK_GCLK224 +#define JH7110_SYSCLK_CORE 25 +#define JH7110_SYSCLK_CORE126 +#define JH7110_SYSCLK_CORE227 +#define JH7110_SYSCLK_CORE328 +#define JH7110_SYSCLK_CORE429 +#define JH7110_SYSCLK_DEBUG30 +#define JH7110_SYSCLK_RTC_TOGGLE 31 +#define JH7110_SYSCLK_TRACE0 32 +#define JH7110_SYSCLK_TRACE1 33 +#define JH7110_SYSCLK_TRACE2 34 +#define JH7110_SYSCLK_TRACE3 35 +#define JH7110_SYSCLK_TRACE4 36 +#define JH7110_SYSCLK_TRACE_COM37 +#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 +#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 +#define JH7110_SYSCLK_OSC_DIV2 40 +#define JH7110_SYSCLK_PLL1_DIV441 +#define JH7110_SYSCLK_PLL1_DIV842 +#define JH7110_SYSCLK_DDR_BUS 43 +#define JH7110_SYSCLK_DDR_AXI 44 +#define JH7110_SYSCLK_GPU_CORE 45 +#define JH7110_SYSCLK_GPU_CORE_CLK 46 +#define JH7110_SYSCLK_GPU_SYS_CLK 47 +#define JH7110_SYSCLK_GPU_APB 48 +#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 +#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 +#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X 51 +#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI 52 +#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 +#define JH7110_SYSCLK_HIFI4_CORE 54 +#define JH7110_SYSCLK_HIFI4_AXI55 +#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN56 +#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB 57 +#define JH7110_SYSCLK_VOUT_SRC 58 +#define JH7110_SYSCLK_VOUT_AXI 59 +#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 +#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB61 +#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI62 +#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK63 +#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF 64 +#define JH7110_SYSCLK_JPEGC_AXI65 +#define JH7110_SYSCLK_CODAJ12_AXI 66 +#define JH7110_SYSCLK_CODAJ12_CORE 67 +#define JH7110_SYSCLK_CODAJ12_APB 68 +#define JH7110_SYSCLK_VDEC_AXI 69 +#define JH7110_SYSCLK_WAVE511_AXI 70 +#define JH7110_SYSCLK_WAVE511_BPU 71 +#define JH7110_SYSCLK_WAVE511_VCE 72 +#define JH7110_SYSCLK_WAVE511_APB 73 +#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG 74 +#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN75 +#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 +#define JH7110_SYSCLK_VENC_AXI 77 +#define JH7110_SYSCLK_WAVE420L_AXI 78 +#define JH7110_SYSCLK_WAVE420L_BPU 79 +#define JH7110_SYSCLK_WAVE420L_VCE 80 +#define JH7110_SYSCLK_WAVE420L_APB 81 +#define
[PATCH v1 04/17] reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC
Add a DM reset driver for StarFive JH7110 SoC.
Note that the register base address of reset controller is the
same with the clock controller. Therefore, there is no device
tree node alone for reset driver.It binds device node in
the clock driver
Signed-off-by: Yanhong Wang
---
drivers/reset/Kconfig| 16
drivers/reset/Makefile | 1 +
drivers/reset/reset-jh7110.c | 158 +++
3 files changed, 175 insertions(+)
create mode 100644 drivers/reset/reset-jh7110.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 4cb0ba0850..1ca701bb92 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -172,6 +172,22 @@ config RESET_SIFIVE
different hw blocks like DDR, gemgxl. With this driver we leverage
U-Boot's reset framework to reset these hardware blocks.
+config RESET_JH7110
+ bool "Reset driver for StarFive JH7110 SoC"
+ depends on DM_RESET && STARFIVE_JH7110
+ default y
+ help
+ Support for reset controller on StarFive
+ JH7110 SoCs.
+
+config SPL_RESET_JH7110
+ bool "SPL Reset driver for StarFive JH7110 SoC"
+ depends on SPL && STARFIVE_JH7110
+ default y
+ help
+ Support for reset controller on StarFive
+ JH7110 SoCs in SPL.
+
config RESET_SYSCON
bool "Enable generic syscon reset driver support"
depends on DM_RESET
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 0620b62809..05967b030a 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -31,3 +31,4 @@ obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o
obj-$(CONFIG_RESET_DRA7) += reset-dra7.o
+obj-$(CONFIG_$(SPL_TPL_)RESET_JH7110) += reset-jh7110.o
diff --git a/drivers/reset/reset-jh7110.c b/drivers/reset/reset-jh7110.c
new file mode 100644
index 00..6887b794d6
--- /dev/null
+++ b/drivers/reset/reset-jh7110.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct jh7110_reset_priv {
+ void __iomem *reg;
+ u32 assert;
+ u32 status;
+ u32 resets;
+};
+
+struct reset_info {
+ const char *compat;
+ const u32 nr_resets;
+ const u32 assert_offset;
+ const u32 status_offset;
+};
+
+static const struct reset_info jh7110_rst_info[] = {
+ {
+ .compat = "starfive,jh7110-syscrg",
+ .nr_resets = JH7110_SYSRST_END,
+ .assert_offset = 0x2F8,
+ .status_offset = 0x308,
+ },
+ {
+ .compat = "starfive,jh7110-aoncrg",
+ .nr_resets = JH7110_AONRST_END,
+ .assert_offset = 0x38,
+ .status_offset = 0x3C,
+ },
+ {
+ .compat = "starfive,jh7110-stgcrg",
+ .nr_resets = JH7110_STGRST_END,
+ .assert_offset = 0x74,
+ .status_offset = 0x78,
+ }
+};
+
+static const struct reset_info *jh7110_reset_get_cfg(const char *compat)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(jh7110_rst_info); i++)
+ if (!strcmp(compat, jh7110_rst_info[i].compat))
+ return _rst_info[i];
+
+ return NULL;
+}
+
+static int jh7110_reset_trigger(struct jh7110_reset_priv *priv,
+ unsigned long id, bool assert)
+{
+ ulong group;
+ u32 mask, value, done = 0;
+ ulong addr;
+
+ group = id / 32;
+ mask = BIT(id % 32);
+
+ if (!assert)
+ done ^= mask;
+
+ addr = (ulong)priv->reg + priv->assert + group * sizeof(u32);
+ value = readl((ulong *)addr);
+
+ if (assert)
+ value |= mask;
+ else
+ value &= ~mask;
+
+ writel(value, (ulong *)addr);
+ addr = (ulong)priv->reg + priv->status + group * sizeof(u32);
+
+ return readl_poll_timeout((ulong *)addr, value,
+ (value & mask) == done, 1000);
+}
+
+static int jh7110_reset_assert(struct reset_ctl *rst)
+{
+ struct jh7110_reset_priv *priv = dev_get_priv(rst->dev);
+
+ jh7110_reset_trigger(priv, rst->id, true);
+
+ return 0;
+}
+
+static int jh7110_reset_deassert(struct reset_ctl *rst)
+{
+ struct jh7110_reset_priv *priv = dev_get_priv(rst->dev);
+
+ jh7110_reset_trigger(priv, rst->id, false);
+
+ return 0;
+}
+
+static int jh7110_reset_free(struct reset_ctl *rst)
+{
+ return 0;
+}
+
+static int jh7110_reset_request(struct reset_ctl *rst)
+{
+ struct jh7110_reset_priv *priv = dev_get_priv(rst->dev);
+
+ if (rst->id >= priv->resets)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int jh7110_reset_probe(struct
[PATCH v1 03/17] dt-bindings: reset: Add StarFive JH7110 reset definitions
Add resets for the StarFive JH7110 system(SYS),system-top-group(STG) and always-on(AON) reset controller. Signed-off-by: Yanhong Wang --- include/dt-bindings/reset/starfive-jh7110.h | 183 1 file changed, 183 insertions(+) create mode 100644 include/dt-bindings/reset/starfive-jh7110.h diff --git a/include/dt-bindings/reset/starfive-jh7110.h b/include/dt-bindings/reset/starfive-jh7110.h new file mode 100644 index 00..117b305892 --- /dev/null +++ b/include/dt-bindings/reset/starfive-jh7110.h @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * + * Author: Yanhong Wang + */ + +#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ +#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ + +/* SYSCRG resets */ +#define JH7110_SYSRST_JTAG2APB 0 +#define JH7110_SYSRST_SYSCON 1 +#define JH7110_SYSRST_IOMUX2 +#define JH7110_SYSRST_BUS 3 +#define JH7110_SYSRST_DEBUG4 +#define JH7110_SYSRST_CORE05 +#define JH7110_SYSRST_CORE16 +#define JH7110_SYSRST_CORE27 +#define JH7110_SYSRST_CORE38 +#define JH7110_SYSRST_CORE49 +#define JH7110_SYSRST_CORE0_ST 10 +#define JH7110_SYSRST_CORE1_ST 11 +#define JH7110_SYSRST_CORE2_ST 12 +#define JH7110_SYSRST_CORE3_ST 13 +#define JH7110_SYSRST_CORE4_ST 14 +#define JH7110_SYSRST_TRACE0 15 +#define JH7110_SYSRST_TRACE1 16 +#define JH7110_SYSRST_TRACE2 17 +#define JH7110_SYSRST_TRACE3 18 +#define JH7110_SYSRST_TRACE4 19 +#define JH7110_SYSRST_TRACE_COM20 +#define JH7110_SYSRST_GPU_APB 21 +#define JH7110_SYSRST_GPU_DOMA 22 +#define JH7110_SYSRST_NOC_BUS_APB_BUS 23 +#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24 +#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25 +#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26 +#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27 +#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28 +#define JH7110_SYSRST_NOC_BUS_DDRC 29 +#define JH7110_SYSRST_NOC_BUS_STG_AXI 30 +#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31 + +#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32 +#define JH7110_SYSRST_AXI_CFG1_DEC_AHB 33 +#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN34 +#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN35 +#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV36 +#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4 37 +#define JH7110_SYSRST_DDR_AXI 38 +#define JH7110_SYSRST_DDR_OSC 39 +#define JH7110_SYSRST_DDR_APB 40 +#define JH7110_SYSRST_DOM_ISP_TOP_N41 +#define JH7110_SYSRST_DOM_ISP_TOP_AXI 42 +#define JH7110_SYSRST_DOM_VOUT_TOP_SRC 43 +#define JH7110_SYSRST_CODAJ12_AXI 44 +#define JH7110_SYSRST_CODAJ12_CORE 45 +#define JH7110_SYSRST_CODAJ12_APB 46 +#define JH7110_SYSRST_WAVE511_AXI 47 +#define JH7110_SYSRST_WAVE511_BPU 48 +#define JH7110_SYSRST_WAVE511_VCE 49 +#define JH7110_SYSRST_WAVE511_APB 50 +#define JH7110_SYSRST_VDEC_JPG_ARB_JPG 51 +#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN52 +#define JH7110_SYSRST_AXIMEM0_AXI 53 +#define JH7110_SYSRST_WAVE420L_AXI 54 +#define JH7110_SYSRST_WAVE420L_BPU 55 +#define JH7110_SYSRST_WAVE420L_VCE 56 +#define JH7110_SYSRST_WAVE420L_APB 57 +#define JH7110_SYSRST_AXIMEM1_AXI 58 +#define JH7110_SYSRST_AXIMEM2_AXI 59 +#define JH7110_SYSRST_INTMEM 60 +#define JH7110_SYSRST_QSPI_AHB 61 +#define JH7110_SYSRST_QSPI_APB 62 +#define JH7110_SYSRST_QSPI_REF 63 + +#define JH7110_SYSRST_SDIO0_AHB64 +#define JH7110_SYSRST_SDIO1_AHB65 +#define JH7110_SYSRST_GMAC1_AXI66 +#define JH7110_SYSRST_GMAC1_AHB67 +#define JH7110_SYSRST_MAILBOX 68 +#define JH7110_SYSRST_SPI0_APB 69 +#define JH7110_SYSRST_SPI1_APB 70 +#define JH7110_SYSRST_SPI2_APB 71 +#define JH7110_SYSRST_SPI3_APB 72 +#define JH7110_SYSRST_SPI4_APB 73 +#define JH7110_SYSRST_SPI5_APB 74 +#define JH7110_SYSRST_SPI6_APB 75 +#define JH7110_SYSRST_I2C0_APB 76 +#define JH7110_SYSRST_I2C1_APB 77 +#define JH7110_SYSRST_I2C2_APB 78 +#define JH7110_SYSRST_I2C3_APB 79 +#define JH7110_SYSRST_I2C4_APB 80 +#define JH7110_SYSRST_I2C5_APB 81 +#define
[PATCH v1 00/17] Basic StarFive JH7110 RISC-V SoC support
This series of patches base on the latest branch/master, and add support for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order for this to be achieved, the respective DT nodes have been added, and the required defconfigs have been added to the boards' defconfig. What is more, the basic required DM drivers have been added, such as reset, clock, pinctrl, uart, ram etc. Note that the register base address of reset controller is same with the clock controller. Therefore, there is no device tree node alone for reset driver. It binds device node in the clock driver. The u-boot-spl and u-boot has been tested on the VisionFive V2 boards which equip with JH7110 SoC and works normally. For more information and support, you can visit RVspace wiki[1]. [1] https://wiki.rvspace.org/ Jianlong Huang (1): dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions Kuan Lim Lee (1): pinctrl: starfive: Add StarFive JH7110 driver Yanhong Wang (15): riscv: cpu: jh7110: Add support for jh7110 SoC cache: starfive: Add StarFive JH7110 support dt-bindings: reset: Add StarFive JH7110 reset definitions reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC dt-bindings: clock: Add StarFive JH7110 clock definitions clk: starfive: Add StarFive JH7110 clock driver ram: starfive: add ddr driver board: starfive: add StarFive VisionFive v2 board support riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC board: starfive: Add Kconfig for StarFive VisionFive v2 Board board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig riscv: dts: jh7110: Add initial StarFive JH7110 device tree riscv: dts: jh7110: Add initial u-boot device tree riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree configs: starfive: add starfive_visionfive2_defconfig arch/riscv/Kconfig|5 + arch/riscv/cpu/jh7110/Kconfig | 28 + arch/riscv/cpu/jh7110/Makefile| 10 + arch/riscv/cpu/jh7110/cpu.c | 23 + arch/riscv/cpu/jh7110/dram.c | 38 + arch/riscv/cpu/jh7110/spl.c | 56 + arch/riscv/dts/Makefile |2 +- arch/riscv/dts/jh7110-u-boot.dtsi | 86 + arch/riscv/dts/jh7110.dtsi| 497 + .../dts/starfive_visionfive2-u-boot.dtsi | 66 + arch/riscv/dts/starfive_visionfive2.dts | 234 ++ .../include/asm/arch-jh7110/jh7110-regs.h | 20 + arch/riscv/include/asm/arch-jh7110/spl.h | 13 + board/starfive/visionfive2/Kconfig| 53 + board/starfive/visionfive2/MAINTAINERS|7 + board/starfive/visionfive2/Makefile |7 + board/starfive/visionfive2/spl.c | 119 + .../visionfive2/starfive_visionfive2.c| 39 + configs/starfive_visionfive2_defconfig| 72 + drivers/cache/cache-sifive-ccache.c |1 + drivers/clk/Kconfig |1 + drivers/clk/Makefile |1 + drivers/clk/starfive/Kconfig | 15 + drivers/clk/starfive/Makefile |4 + drivers/clk/starfive/clk-jh7110-pll.c | 362 +++ drivers/clk/starfive/clk-jh7110.c | 651 ++ drivers/clk/starfive/clk.h| 42 + drivers/pinctrl/Kconfig |1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/starfive/Kconfig | 16 + drivers/pinctrl/starfive/Makefile |6 + drivers/pinctrl/starfive/pinctrl-jh7110-aon.c | 113 + drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 399 drivers/pinctrl/starfive/pinctrl-starfive.c | 428 drivers/pinctrl/starfive/pinctrl-starfive.h | 55 + drivers/ram/Kconfig |1 + drivers/ram/Makefile |4 +- drivers/ram/starfive/Kconfig |5 + drivers/ram/starfive/Makefile | 11 + drivers/ram/starfive/ddrcsr_boot.c| 340 +++ drivers/ram/starfive/ddrphy_start.c | 280 +++ drivers/ram/starfive/ddrphy_train.c | 384 drivers/ram/starfive/ddrphy_utils.c | 1956 + drivers/ram/starfive/starfive_ddr.c | 162 ++ drivers/ram/starfive/starfive_ddr.h | 66 + drivers/reset/Kconfig | 16 + drivers/reset/Makefile|1 + drivers/reset/reset-jh7110.c | 158 ++ include/configs/starfive-visionfive2.h| 18 + include/dt-bindings/clock/starfive-jh7110.h | 271 +++ .../pinctrl/pinctrl-starfive-jh7110.h | 427 include/dt-bindings/reset/starfive-jh7110.h | 183 ++ 52 files changed, 7752 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/cpu/jh7110/Kconfig create mode 100644 arch/riscv/cpu/jh7110/Makefile create mode 100644 arch/riscv/cpu/jh7110/cpu.c
[PATCH v1 01/17] riscv: cpu: jh7110: Add support for jh7110 SoC
Add StarFive JH7110 SoC to support RISC-V arch.
Signed-off-by: Yanhong Wang
---
arch/riscv/cpu/jh7110/Makefile| 10
arch/riscv/cpu/jh7110/cpu.c | 23
arch/riscv/cpu/jh7110/dram.c | 38 +
arch/riscv/cpu/jh7110/spl.c | 56 +++
.../include/asm/arch-jh7110/jh7110-regs.h | 20 +++
arch/riscv/include/asm/arch-jh7110/spl.h | 13 +
6 files changed, 160 insertions(+)
create mode 100644 arch/riscv/cpu/jh7110/Makefile
create mode 100644 arch/riscv/cpu/jh7110/cpu.c
create mode 100644 arch/riscv/cpu/jh7110/dram.c
create mode 100644 arch/riscv/cpu/jh7110/spl.c
create mode 100644 arch/riscv/include/asm/arch-jh7110/jh7110-regs.h
create mode 100644 arch/riscv/include/asm/arch-jh7110/spl.h
diff --git a/arch/riscv/cpu/jh7110/Makefile b/arch/riscv/cpu/jh7110/Makefile
new file mode 100644
index 00..951c95631e
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 StarFive Technology Co., Ltd.
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y += spl.o
+else
+obj-y += cpu.o
+obj-y += dram.o
+endif
diff --git a/arch/riscv/cpu/jh7110/cpu.c b/arch/riscv/cpu/jh7110/cpu.c
new file mode 100644
index 00..5da71908c0
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/cpu.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+ cache_flush();
+
+ return 0;
+}
diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c
new file mode 100644
index 00..4ce91aee9d
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/dram.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+{
+ /*
+* Ensure that we run from first 4GB so that all
+* addresses used by U-Boot are 32bit addresses.
+*
+* This in-turn ensures that 32bit DMA capable
+* devices work fine because DMA mapping APIs will
+* provide 32bit DMA addresses only.
+*/
+ if (IS_ENABLED(CONFIG_64BIT) && gd->ram_top > SZ_4G)
+ return SZ_4G;
+
+ return gd->ram_top;
+}
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
new file mode 100644
index 00..a0aacacf7b
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ *
+ */
+
+#include
+#include
+#include
+
+#define CSR_U74_FEATURE_DISABLE0x7c1
+
+int spl_soc_init(void)
+{
+ int ret;
+ struct udevice *dev;
+
+ /* DDR init */
+ ret = uclass_get_device(UCLASS_RAM, 0, );
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return ret;
+ }
+
+ /* flash init */
+ ret = uclass_get_device(UCLASS_SPI_FLASH, 0, );
+ if (ret) {
+ debug("SPI init failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+void harts_early_init(void)
+{
+ /*
+* Feature Disable CSR
+*
+* Clear feature disable CSR to '0' to turn on all features for
+* each core. This operation must be in M-mode.
+*/
+ if (CONFIG_IS_ENABLED(RISCV_MMODE))
+ csr_write(CSR_U74_FEATURE_DISABLE, 0);
+
+ /* clear L2 LIM memory
+* set __bss_end to 0x81F region to zero
+*/
+ asm volatile("la t1, __bss_end\n\t"
+ "li t2, 0x81F\n\t"
+ "spl_clear_l2im:\n\t"
+ "sd zero, 0(t1)\n\t"
+ "addi t1, t1, 8\n\t"
+ "blt t1, t2, spl_clear_l2im\n\t");
+}
diff --git a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h
b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h
new file mode 100644
index 00..a204fbcadf
--- /dev/null
+++ b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang
+ *
+ */
+
+#ifndef __STARFIVE_JH7110_REGS_H
+#define __STARFIVE_JH7110_REGS_H
+
+#define JH7110_SYS_SYSCON 0x1303
+#define JH7110_SYS_IOMUX 0x1304
+#define JH7110_AON_SYSCON
[PATCH v1 02/17] cache: starfive: Add StarFive JH7110 support
This adds support for the StarFive JH7110 SoC which also
feature this SiFive cache controller.
Signed-off-by: Yanhong Wang
---
drivers/cache/cache-sifive-ccache.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cache/cache-sifive-ccache.c
b/drivers/cache/cache-sifive-ccache.c
index c8766f6242..c1bef0b4d3 100644
--- a/drivers/cache/cache-sifive-ccache.c
+++ b/drivers/cache/cache-sifive-ccache.c
@@ -62,6 +62,7 @@ static int sifive_ccache_probe(struct udevice *dev)
static const struct udevice_id sifive_ccache_ids[] = {
{ .compatible = "sifive,fu540-c000-ccache" },
{ .compatible = "sifive,fu740-c000-ccache" },
+ { .compatible = "starfive,jh7110-ccache" },
{}
};
--
2.17.1
Re: [PATCH 0/8] sunxi: Update H616 DRAM driver
On Sun, 11 Dec 2022 17:32:05 +0100 Jernej Skrabec wrote: Hi Jernej, many thanks for putting this together! I will have a more elaborate look at each patch later. > Current H616 DRAM driver is completely customized to Orange Pi Zero2 > board, which is currently the only H616 board supported by U-Boot. Not anymore, I merged the X96 Mate support lately, after the DT got merged into the Linux tree. Those are the values for the box I came up with: CONFIG_DRAM_SUN50I_H616_DX_ODT=0x03030303 CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e CONFIG_DRAM_SUN50I_H616_CA_DRI=0x1c12 CONFIG_DRAM_SUN50I_H616_TPR0=0xcc05 CONFIG_DRAM_SUN50I_H616_TPR10=0x2f0007 CONFIG_DRAM_SUN50I_H616_TPR11=0x CONFIG_DRAM_SUN50I_H616_TPR12=0xfedf7557 based on this boot0 found in some firmware update image: 00045400 be 02 00 ea 65 47 4f 4e 2e 42 54 30 cc ba f3 80 |eGON.BT0| 00045410 00 c0 00 00 30 00 00 00 00 00 00 00 00 00 02 00 |0...| 00045420 00 00 02 00 00 00 00 00 00 00 00 00 34 2e 30 00 |4.0.| 00045430 00 00 00 00 03 00 00 00 88 02 00 00 03 00 00 00 || 00045440 03 03 03 03 0e 0e 0e 0e 12 1c 00 00 01 00 00 00 || 00045450 fb 30 00 00 00 00 00 00 40 08 00 00 04 00 00 00 |.0..@...| 00045460 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 || 00045470 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 || 00045480 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 || 00045490 05 0c 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 || 000454a0 80 80 80 33 07 00 2f 00 dd dd ff ff 57 75 df fe |...3../.Wu..| 000454b0 40 00 00 00 00 00 00 00 00 00 00 00 08 00 02 01 |@...| I would be grateful if you could verify this. I built it, and it reported the 4GB correctly, also managed to boot into Linux just fine. No extensive testing, nor didn't I compare register dumps or disassembly (yet). Cheers, Andre P.S. Any plans on upstreaming support for your T95 H616 TV box? That would probably help the case here. > Needless to say, this is not ideal for adding new boards. With changes > in this series, all DDR3 boards are supported and all that is needed is > just vendor DRAM values extracted from Android image. New DRAM types > should also be easier to support, since a lot of constants used before > are not really DRAM type dependent. > > Changes were verified by decompiling driver and generated values were > compared to previous, hard coded ones. This was done without dram_para > structures, so compiler was able to heavily optimize code and produce > constants. > > Please take a look. > > Best regards, > Jernej > > Jernej Skrabec (8): > sunxi: Fix write to H616 DRAM CR register > sunxi: cosmetic: Fix H616 DRAM driver code style > sunxi: parameterize H616 DRAM ODT values > sunxi: Convert H616 DRAM options to single setting > sunxi: Always configure ODT on H616 DRAM > sunxi: Make bit delay function in H616 DRAM code void > sunxi: Parameterize bit delay code in H616 DRAM driver > sunxi: Parameterize H616 DRAM code some more > > .../include/asm/arch-sunxi/dram_sun50i_h616.h | 18 + > arch/arm/mach-sunxi/Kconfig | 67 +-- > arch/arm/mach-sunxi/dram_sun50i_h616.c| 445 +++--- > configs/orangepi_zero2_defconfig | 8 +- > 4 files changed, 348 insertions(+), 190 deletions(-) >
[PATCH v1 15/16] apalis-imx8: update update_uboot confirmation message
From: Marcel Ziswiler
Update update_uboot confirmation message.
Signed-off-by: Marcel Ziswiler
---
include/configs/apalis-imx8.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h
index 85c305f8f00..c54c4d0465a 100644
--- a/include/configs/apalis-imx8.h
+++ b/include/configs/apalis-imx8.h
@@ -40,7 +40,7 @@
"initrd_high=0x\0" \
"setup=setenv setupargs console=tty1 console=${console},${baudrate} " \
"consoleblank=0 earlycon\0" \
- "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \
+ "update_uboot=askenv confirm Did you load flash.bin resp.
u-boot-dtb.imx (y/N)?; " \
"if test \"$confirm\" = \"y\"; then " \
"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \
--
2.35.1
[PATCH v1 16/16] apalis-imx8: update env memory layout
From: Marcel Ziswiler
Update the distro config env memory layout for the Apalis iMX8 aka
QuadMax:
- kernel_comp_addr_r=0xf000 temporary area for uncompressing (ie FIT
images or Image.gz booted using booti)
- kernel_comp_size=0x0800
- loadaddr=0x9540 avoiding any reserved areas located before that
- fdt_addr_r = loadaddr + 128MB - allows for 128MB kernel
- scriptaddr = fdt_addr_r + 512KB - allows for 512KB fdt
- ramdisk_addr_r = scriptaddr + 512KB - allows for 512KB script
Basic idea of memory layout taken from commit fd5c7173ade4
("imx8m{m,n}_venice: update env memory layout"). However, moved past
any reserved areas to avoid any kind of conflicts.
Note that for our regular BSP Layers and Reference Images for Yocto
Project an updated distro boot script is required (see
meta-toradex-bsp-common/recipes-bsp/u-boot/u-boot-distro-boot).
Signed-off-by: Marcel Ziswiler
---
configs/apalis-imx8_defconfig | 2 +-
include/configs/apalis-imx8.h | 10 ++
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig
index 019846e1af2..8acf645167e 100644
--- a/configs/apalis-imx8_defconfig
+++ b/configs/apalis-imx8_defconfig
@@ -10,7 +10,7 @@ CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis"
CONFIG_TARGET_APALIS_IMX8=y
CONFIG_SYS_PROMPT="Apalis iMX8 # "
-CONFIG_SYS_LOAD_ADDR=0x8028
+CONFIG_SYS_LOAD_ADDR=0x9540
CONFIG_SYS_MEMTEST_START=0x8800
CONFIG_SYS_MEMTEST_END=0x8900
CONFIG_DISTRO_DEFAULTS=y
diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h
index c54c4d0465a..c4f2cd604d5 100644
--- a/include/configs/apalis-imx8.h
+++ b/include/configs/apalis-imx8.h
@@ -15,10 +15,12 @@
#define CONFIG_SERVERIP192.168.10.1
#define MEM_LAYOUT_ENV_SETTINGS \
- "fdt_addr_r=0x8400\0" \
- "kernel_addr_r=0x8200\0" \
- "ramdisk_addr_r=0x9440\0" \
- "scriptaddr=0x8700\0"
+ "fdt_addr_r=0x9d40\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "kernel_comp_addr_r=0xf000\0" \
+ "kernel_comp_size=0x0800\0" \
+ "ramdisk_addr_r=0x9d50\0" \
+ "scriptaddr=0x9d48\0"
/* Enable Distro Boot */
#define BOOT_TARGET_DEVICES(func) \
--
2.35.1
[PATCH v1 13/16] apalis-imx8: introduce setup setting setupargs
From: Marcel Ziswiler
Introduce setup setting setupargs and move earlycon there.
Signed-off-by: Marcel Ziswiler
---
include/configs/apalis-imx8.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h
index 92e81d8854a..92b71e7a7c5 100644
--- a/include/configs/apalis-imx8.h
+++ b/include/configs/apalis-imx8.h
@@ -34,7 +34,7 @@
MEM_LAYOUT_ENV_SETTINGS \
"boot_file=Image\0" \
"boot_script_dhcp=boot.scr\0" \
- "console=ttyLP1 earlycon\0" \
+ "console=ttyLP1\0" \
"fdt_addr=0x8300\0" \
"fdt_board=eval\0" \
"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
@@ -45,6 +45,8 @@
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"panel=NULL\0" \
+ "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \
+ "consoleblank=0 earlycon\0" \
"update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \
"if test \"$confirm\" = \"y\"; then " \
"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
--
2.35.1
[PATCH v1 10/16] apalis-imx8: update spdx license identifier string
From: Marcel Ziswiler Update SPDX license identifier string. While at it also update copyright period. Signed-off-by: Marcel Ziswiler --- arch/arm/dts/fsl-imx8qm-apalis.dts | 4 ++-- board/toradex/apalis-imx8/Makefile | 4 ++-- board/toradex/apalis-imx8/apalis-imx8-imximage.cfg | 4 ++-- board/toradex/apalis-imx8/apalis-imx8.c| 4 ++-- include/configs/apalis-imx8.h | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/dts/fsl-imx8qm-apalis.dts b/arch/arm/dts/fsl-imx8qm-apalis.dts index 0d8d3b3e8e8..7daa4483d72 100644 --- a/arch/arm/dts/fsl-imx8qm-apalis.dts +++ b/arch/arm/dts/fsl-imx8qm-apalis.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2017-2019 Toradex + * Copyright 2017-2022 Toradex */ /dts-v1/; diff --git a/board/toradex/apalis-imx8/Makefile b/board/toradex/apalis-imx8/Makefile index a8c3eb7240b..fe19cfdf695 100644 --- a/board/toradex/apalis-imx8/Makefile +++ b/board/toradex/apalis-imx8/Makefile @@ -1,6 +1,6 @@ -# SPDX-License-Identifier: GPL-2.0+ +# SPDX-License-Identifier: GPL-2.0-or-later # -# Copyright 2019 Toradex +# Copyright 2019-2022 Toradex # obj-y += apalis-imx8.o diff --git a/board/toradex/apalis-imx8/apalis-imx8-imximage.cfg b/board/toradex/apalis-imx8/apalis-imx8-imximage.cfg index 16183f96679..fc4aa74990c 100644 --- a/board/toradex/apalis-imx8/apalis-imx8-imximage.cfg +++ b/board/toradex/apalis-imx8/apalis-imx8-imximage.cfg @@ -1,6 +1,6 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * Copyright 2019 Toradex + * Copyright 2019-2022 Toradex * * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure * and create imx8image boot image diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index 84d700107af..1eaf9951d55 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0-or-later /* - * Copyright 2019 Toradex + * Copyright 2019-2022 Toradex */ #include diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index d08d211f495..30cfae870cf 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -1,6 +1,6 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * Copyright 2019-2021 Toradex + * Copyright 2019-2022 Toradex */ #ifndef __APALIS_IMX8_H -- 2.35.1
[PATCH v1 12/16] apalis-imx8: remove obsolete net usb start
From: Marcel Ziswiler Remove obsolete net USB start. While at it also add a comment about enabling distro-boot. Signed-off-by: Marcel Ziswiler --- include/configs/apalis-imx8.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index 66e8727b60f..92e81d8854a 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -20,14 +20,13 @@ "ramdisk_addr_r=0x9440\0" \ "scriptaddr=0x8700\0" +/* Enable Distro Boot */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ func(MMC, mmc, 0) \ func(DHCP, dhcp, na) #include -#undef BOOTENV_RUN_NET_USB_START -#define BOOTENV_RUN_NET_USB_START "" /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ -- 2.35.1
[PATCH v1 14/16] apalis-imx8: drop obsolete environment variables
From: Marcel Ziswiler
Drop obsolete environment variables fdt_addr, finduuid, mmcargs, mmcdev,
mmcpart and panel.
Signed-off-by: Marcel Ziswiler
---
include/configs/apalis-imx8.h | 7 ---
1 file changed, 7 deletions(-)
diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h
index 92b71e7a7c5..85c305f8f00 100644
--- a/include/configs/apalis-imx8.h
+++ b/include/configs/apalis-imx8.h
@@ -35,16 +35,9 @@
"boot_file=Image\0" \
"boot_script_dhcp=boot.scr\0" \
"console=ttyLP1\0" \
- "fdt_addr=0x8300\0" \
"fdt_board=eval\0" \
- "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
"initrd_addr=0x8380\0" \
"initrd_high=0x\0" \
- "mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=PARTUUID=${uuid} rootwait " \
- "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=1\0" \
- "panel=NULL\0" \
"setup=setenv setupargs console=tty1 console=${console},${baudrate} " \
"consoleblank=0 earlycon\0" \
"update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \
--
2.35.1
[PATCH v1 08/16] apalis/colibri-imx8/8x: remove global variable script
From: Oleksandr Suvorov
The distroboot script system scans boot_scripts variable and
try to find and use to boot each script name mentioned there.
Setting global variable "script" breaks this general mechanism
of searching and running a distro boot script.
Remove global variables "script" to fix working the general
distro boot script mechanism.
Signed-off-by: Oleksandr Suvorov
Signed-off-by: Marcel Ziswiler
---
include/configs/apalis-imx8.h | 1 -
include/configs/colibri-imx8x.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h
index 6275751273c..d08d211f495 100644
--- a/include/configs/apalis-imx8.h
+++ b/include/configs/apalis-imx8.h
@@ -50,7 +50,6 @@
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"panel=NULL\0" \
- "script=boot.scr\0" \
"update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \
"if test \"$confirm\" = \"y\"; then " \
"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h
index d641fbf47e7..734034e9944 100644
--- a/include/configs/colibri-imx8x.h
+++ b/include/configs/colibri-imx8x.h
@@ -81,7 +81,6 @@
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"panel=NULL\0" \
- "script=boot.scr\0" \
"update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \
"if test \"$confirm\" = \"y\"; then " \
"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
--
2.35.1
[PATCH v1 11/16] apalis-imx8: remove obsolete sdhc related config defines
From: Marcel Ziswiler
Remove obsolete SDHC related config defines. Nowadays, all SDHC related
hardware configuration comes from the device tree.
Signed-off-by: Marcel Ziswiler
---
include/configs/apalis-imx8.h | 9 -
1 file changed, 9 deletions(-)
diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h
index 30cfae870cf..66e8727b60f 100644
--- a/include/configs/apalis-imx8.h
+++ b/include/configs/apalis-imx8.h
@@ -9,10 +9,6 @@
#include
#include
-#define CFG_SYS_FSL_ESDHC_ADDR 0
-#define USDHC1_BASE_ADDR 0x5b01
-#define USDHC2_BASE_ADDR 0x5b02
-
/* Networking */
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
@@ -56,11 +52,6 @@
"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \
"${blkcnt}; fi\0"
-/* Link Definitions */
-
-/* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */
-#define CFG_SYS_FSL_USDHC_NUM 3
-
#define CONFIG_SYS_SDRAM_BASE 0x8000
#define PHYS_SDRAM_1 0x8000
#define PHYS_SDRAM_2 0x88000
--
2.35.1
[PATCH v1 09/16] apalis-imx8: enable environment bootcount limit
From: Marcel Ziswiler Enable optional environment bootcount limit functionality. Signed-off-by: Marcel Ziswiler --- configs/apalis-imx8_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index eabdb12478c..019846e1af2 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -53,6 +53,8 @@ CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_TFTP_TSIZE=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y CONFIG_CLK_IMX8=y CONFIG_CPU=y CONFIG_MXC_GPIO=y -- 2.35.1
[PATCH v1 07/16] apalis/colibri-imx8/8x: add overlay support for i.mx 8/8x-based soms
From: Oleksandr Suvorov There is no "apply" command enabled for "fdt". Enable "apply" command to allow overlays to be applied. Signed-off-by: Oleksandr Suvorov Signed-off-by: Marcel Ziswiler --- configs/apalis-imx8_defconfig | 1 + configs/colibri-imx8x_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index aee43d07816..eabdb12478c 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -80,4 +80,5 @@ CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y CONFIG_IMX_SCU_THERMAL=y +CONFIG_OF_LIBFDT_OVERLAY=y # CONFIG_EFI_LOADER is not set diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig index 6896236045b..70b9927406d 100644 --- a/configs/colibri-imx8x_defconfig +++ b/configs/colibri-imx8x_defconfig @@ -74,4 +74,5 @@ CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y CONFIG_IMX_SCU_THERMAL=y +CONFIG_OF_LIBFDT_OVERLAY=y # CONFIG_EFI_LOADER is not set -- 2.35.1
[PATCH v1 06/16] apalis-imx8: set bootdelay
From: Marcel Ziswiler
Set the boot delay to one second.
Signed-off-by: Marcel Ziswiler
---
configs/apalis-imx8_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig
index 92a0c67b32e..aee43d07816 100644
--- a/configs/apalis-imx8_defconfig
+++ b/configs/apalis-imx8_defconfig
@@ -20,6 +20,7 @@ CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=1
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile
${soc}-apalis${variant}-${fdt_board}.dtb"
CONFIG_LOG=y
--
2.35.1
[PATCH v1 05/16] apalis-imx8: provide proper config_sys_prompt
From: Igor Opaniuk This provides correct system prompt for U-Boot console. Signed-off-by: Igor Opaniuk Signed-off-by: Marcel Ziswiler --- configs/apalis-imx8_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index c14cb996a3e..92a0c67b32e 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0xDE00 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis" CONFIG_TARGET_APALIS_IMX8=y +CONFIG_SYS_PROMPT="Apalis iMX8 # " CONFIG_SYS_LOAD_ADDR=0x8028 CONFIG_SYS_MEMTEST_START=0x8800 CONFIG_SYS_MEMTEST_END=0x8900 -- 2.35.1
[PATCH v1 03/16] apalis-imx8: turn off lcd backlight before os handover
From: Marcel Ziswiler
U-Boot typically tears down the display controller before handing
control over to Linux. On LCD displays disabling pixel clock leads to a
fading out effect with vertical/horizontal lines. Make sure to disable
back light GPIO Apalis BKL1 before booting Linux.
Signed-off-by: Marcel Ziswiler
---
board/toradex/apalis-imx8/apalis-imx8.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/board/toradex/apalis-imx8/apalis-imx8.c
b/board/toradex/apalis-imx8/apalis-imx8.c
index d4be999e24d..d8c68765d16 100644
--- a/board/toradex/apalis-imx8/apalis-imx8.c
+++ b/board/toradex/apalis-imx8/apalis-imx8.c
@@ -182,9 +182,18 @@ int board_early_init_f(void)
}
#if CONFIG_IS_ENABLED(DM_GPIO)
+
+#define BKL1_GPIO IMX_GPIO_NR(1, 10)
+
+static iomux_cfg_t board_gpios[] = {
+ SC_P_LVDS1_GPIO00 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
static void board_gpio_init(void)
{
- /* TODO */
+ imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios));
+
+ gpio_request(BKL1_GPIO, "BKL1_GPIO");
}
#else
static inline void board_gpio_init(void) {}
@@ -202,6 +211,14 @@ int board_phy_config(struct phy_device *phydev)
}
#endif
+/*
+ * Backlight off before OS handover
+ */
+void board_preboot_os(void)
+{
+ gpio_direction_output(BKL1_GPIO, 0);
+}
+
int checkboard(void)
{
puts("Model: Toradex Apalis iMX8\n");
--
2.35.1
[PATCH v1 04/16] apalis-imx8: display build info
From: Marcel Ziswiler
Display build info with information about the version of SCFW, SECO and
TF-A (ATF).
Signed-off-by: Marcel Ziswiler
---
board/toradex/apalis-imx8/apalis-imx8.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/toradex/apalis-imx8/apalis-imx8.c
b/board/toradex/apalis-imx8/apalis-imx8.c
index d8c68765d16..84d700107af 100644
--- a/board/toradex/apalis-imx8/apalis-imx8.c
+++ b/board/toradex/apalis-imx8/apalis-imx8.c
@@ -332,6 +332,8 @@ int board_late_init(void)
env_set("board_rev", "v1.0");
#endif
+ build_info();
+
select_dt_from_module_version();
return 0;
--
2.35.1
[PATCH v1 00/16] apalis-imx8: boot issue fix and support refresh
From: Marcel Ziswiler This series fixes a boot issue and refreshes Apalis iMX8 support as follows: - fix booting caused by missing DM_EVENT - implement PCB version and SoC variant handling - turn off LCD backlight before OS handover - display build info - provide proper prompt - set bootdelay - add overlays support - remove global environment variable script - enable environment bootcount limit - update SPDX license identifier string - remove obsolete SDHC related config defines - remove obsolete net usb start - introduce setup setting setupargs - drop obsolete environment variables - update update_uboot confirmation message - update env memory layout Igor Opaniuk (1): apalis-imx8: provide proper config_sys_prompt Marcel Ziswiler (13): apalis-imx8: fix booting caused by missing dm_event apalis-imx8: implement pcb version and soc variant handling apalis-imx8: turn off lcd backlight before os handover apalis-imx8: display build info apalis-imx8: set bootdelay apalis-imx8: enable environment bootcount limit apalis-imx8: update spdx license identifier string apalis-imx8: remove obsolete sdhc related config defines apalis-imx8: remove obsolete net usb start apalis-imx8: introduce setup setting setupargs apalis-imx8: drop obsolete environment variables apalis-imx8: update update_uboot confirmation message apalis-imx8: update env memory layout Oleksandr Suvorov (2): apalis/colibri-imx8/8x: add overlay support for i.mx 8/8x-based soms apalis/colibri-imx8/8x: remove global variable script arch/arm/dts/fsl-imx8qm-apalis.dts| 4 +- board/toradex/apalis-imx8/Makefile| 4 +- .../apalis-imx8/apalis-imx8-imximage.cfg | 4 +- board/toradex/apalis-imx8/apalis-imx8.c | 129 +- configs/apalis-imx8_defconfig | 10 +- configs/colibri-imx8x_defconfig | 1 + include/configs/apalis-imx8.h | 45 ++ include/configs/colibri-imx8x.h | 1 - 8 files changed, 156 insertions(+), 42 deletions(-) -- 2.35.1
[PATCH v1 02/16] apalis-imx8: implement pcb version and soc variant handling
From: Marcel Ziswiler
Implement PCB version and SoC variant handling which automatically loads
the correct device tree for the Linux kernel.
Signed-off-by: Marcel Ziswiler
---
board/toradex/apalis-imx8/apalis-imx8.c | 104 +++-
configs/apalis-imx8_defconfig | 2 +
include/configs/apalis-imx8.h | 3 +-
3 files changed, 106 insertions(+), 3 deletions(-)
diff --git a/board/toradex/apalis-imx8/apalis-imx8.c
b/board/toradex/apalis-imx8/apalis-imx8.c
index 408198843fd..d4be999e24d 100644
--- a/board/toradex/apalis-imx8/apalis-imx8.c
+++ b/board/toradex/apalis-imx8/apalis-imx8.c
@@ -15,10 +15,12 @@
#include
#include
#include
+#include
#include
#include
-#include
#include
+#include
+#include
#include "../common/tdx-cfg-block.h"
@@ -29,11 +31,41 @@ DECLARE_GLOBAL_DATA_PTR;
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+#define PCB_VERS_DETECT((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT)
| \
+(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define PCB_VERS_DEFAULT ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT)
| \
+(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+(SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT) |
\
+(SC_PAD_28FDSOI_DSE_DV_HIGH <<
PADRING_DSE_SHIFT))
+
#define TDX_USER_FUSE_BLOCK1_A 276
#define TDX_USER_FUSE_BLOCK1_B 277
#define TDX_USER_FUSE_BLOCK2_A 278
#define TDX_USER_FUSE_BLOCK2_B 279
+enum pcb_rev_t {
+ PCB_VERSION_1_0,
+ PCB_VERSION_1_1
+};
+
+static iomux_cfg_t pcb_vers_detect[] = {
+ SC_P_MIPI_DSI0_GPIO0_00 | MUX_MODE_ALT(3) |
MUX_PAD_CTRL(PCB_VERS_DETECT),
+ SC_P_MIPI_DSI0_GPIO0_01 | MUX_MODE_ALT(3) |
MUX_PAD_CTRL(PCB_VERS_DETECT),
+};
+
+static iomux_cfg_t pcb_vers_default[] = {
+ SC_P_MIPI_DSI0_GPIO0_00 | MUX_MODE_ALT(3) |
MUX_PAD_CTRL(PCB_VERS_DEFAULT),
+ SC_P_MIPI_DSI0_GPIO0_01 | MUX_MODE_ALT(3) |
MUX_PAD_CTRL(PCB_VERS_DEFAULT),
+};
+
static iomux_cfg_t uart1_pads[] = {
SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
@@ -180,6 +212,74 @@ int checkboard(void)
return 0;
}
+static enum pcb_rev_t get_pcb_revision(void)
+{
+ unsigned int pcb_vers = 0;
+
+ imx8_iomux_setup_multiple_pads(pcb_vers_detect,
+ ARRAY_SIZE(pcb_vers_detect));
+
+ gpio_request(IMX_GPIO_NR(1, 18),
+"PCB version detection on PAD SC_P_MIPI_DSI0_GPIO0_00");
+ gpio_request(IMX_GPIO_NR(1, 19),
+"PCB version detection on PAD SC_P_MIPI_DSI0_GPIO0_01");
+ gpio_direction_input(IMX_GPIO_NR(1, 18));
+ gpio_direction_input(IMX_GPIO_NR(1, 19));
+
+ udelay(1000);
+
+ pcb_vers = gpio_get_value(IMX_GPIO_NR(1, 18));
+ pcb_vers |= gpio_get_value(IMX_GPIO_NR(1, 19)) << 1;
+
+ /* Set muxing back to default values for saving energy */
+ imx8_iomux_setup_multiple_pads(pcb_vers_default,
+ ARRAY_SIZE(pcb_vers_default));
+
+ switch (pcb_vers) {
+ case 0b11:
+ return PCB_VERSION_1_0;
+ case 0b10:
+ return PCB_VERSION_1_1;
+ default:
+ printf("Unknown PCB version=0x%x, default to V1.1\n", pcb_vers);
+ return PCB_VERSION_1_1;
+ }
+}
+
+static void select_dt_from_module_version(void)
+{
+ env_set("soc", "imx8qm");
+ env_set("variant", "-v1.1");
+
+ switch (tdx_hw_tag.prodid) {
+ /* Select Apalis iMX8QM device trees */
+ case APALIS_IMX8QM_IT:
+ case APALIS_IMX8QM_WIFI_BT_IT:
+ if (get_pcb_revision() == PCB_VERSION_1_0)
+ env_set("variant", "");
+ break;
+ /* Select Apalis iMX8QP device trees */
+ case APALIS_IMX8QP_WIFI_BT:
+ case APALIS_IMX8QP:
+ env_set("soc", "imx8qp");
+ break;
+ default:
+ printf("Unknown Apalis iMX8 module\n");
+ return;
+ }
+}
+
+static int do_select_dt_from_module_version(struct cmd_tbl *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ select_dt_from_module_version();
+ return 0;
+}
+
+U_BOOT_CMD(select_dt_from_module_version, CONFIG_SYS_MAXARGS, 1,
[PATCH v1 01/16] apalis-imx8: fix booting caused by missing dm_event
From: Marcel Ziswiler
Without the DM_EVENT absolutely no output whatsoever and the system does
not boot at all.
Fixes: c5ef2025579e ("dm: fix DM_EVENT dependencies")
Signed-off-by: Marcel Ziswiler
---
configs/apalis-imx8_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig
index 6226d50c8ac..b2f8416e326 100644
--- a/configs/apalis-imx8_defconfig
+++ b/configs/apalis-imx8_defconfig
@@ -22,6 +22,7 @@ CONFIG_OF_SYSTEM_SETUP=y
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_EVENT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_CBSIZE=2048
--
2.35.1
Re: [PATCH] sunxi: Fix serial console for A10s-OLinuXino-MICRO
On Sun, 11 Dec 2022 23:00:54 +0100
Mark Kettenis wrote:
Hi,
> On this board CONFIG_CONS_INDEX needs to be 1 unlike other sun5i
> boards. Since this is the default, remove to bogus setting.
Indeed, UART1 is not even configured in the DT, and Olimex' user manual
mentions explicitly that UART0 should be used for debug.
> Fixes: 7095f8641863 ("sunxi: Convert CONS_INDEX to Kconfig")
> Signed-off-by: Mark Kettenis
Reviewed-by: Andre Przywara
Thanks,
Andre
> ---
> configs/A10s-OLinuXino-M_defconfig | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/configs/A10s-OLinuXino-M_defconfig
> b/configs/A10s-OLinuXino-M_defconfig
> index 2ac68039b0..37ebeb9c85 100644
> --- a/configs/A10s-OLinuXino-M_defconfig
> +++ b/configs/A10s-OLinuXino-M_defconfig
> @@ -17,6 +17,5 @@ CONFIG_SYS_I2C_SPEED=40
> CONFIG_MII=y
> CONFIG_SUN4I_EMAC=y
> CONFIG_AXP152_POWER=y
> -CONFIG_CONS_INDEX=2
> CONFIG_USB_EHCI_HCD=y
> CONFIG_USB_OHCI_HCD=y
[PATCH] sunxi: Fix serial console for A10s-OLinuXino-MICRO
On this board CONFIG_CONS_INDEX needs to be 1 unlike other sun5i
boards. Since this is the default, remove to bogus setting.
Fixes: 7095f8641863 ("sunxi: Convert CONS_INDEX to Kconfig")
Signed-off-by: Mark Kettenis
---
configs/A10s-OLinuXino-M_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/A10s-OLinuXino-M_defconfig
b/configs/A10s-OLinuXino-M_defconfig
index 2ac68039b0..37ebeb9c85 100644
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -17,6 +17,5 @@ CONFIG_SYS_I2C_SPEED=40
CONFIG_MII=y
CONFIG_SUN4I_EMAC=y
CONFIG_AXP152_POWER=y
-CONFIG_CONS_INDEX=2
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
--
2.38.1
Re: Pull request for u-boot-nand-20221211
On Sun, Dec 11, 2022 at 02:41:42PM +0100, Dario Binacchi wrote: > Hi Tom, > > The following changes since commit 8f170408774b30aa4ee91b3cc90ba09b564d4651: > > Merge tag 'u-boot-stm32-20221207' of > https://source.denx.de/u-boot/custodians/u-boot-stm (2022-12-08 > 11:25:08 -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/u-boot.git u-boot-nand-20221211 Note that you I think told request-pull something slightly wrong as it should say https://source.denx.de/u-boot/custodians/u-boot-nand-flash.git here, for future reference. > for you to fetch changes up to fda2253d121f05921e419edffe615c607917792a: > > spl: spl_legacy: fix invalid offset in SPL_COPY_PAYLOAD_ONLY > (2022-12-10 14:35:55 +0100) > > Gitlab CI showed no issues: > https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/14397 > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 0/5] Complete the migration of MTDPARTS_DEFAULT / MTDIDS_DEFAULT
On 7/12/22 21:26, Patrick Delaunay wrote:
> Addition for previous commit a331017c237c ("Complete migration of
> MTDPARTS_DEFAULT / MTDIDS_DEFAULT, include in environment")
>
> Remove the remaining defines MTDPARTS_DEFAULT and MTDIDS_DEFAULT
> in the configuration files (include/configs/*.h).
>
> After this serie, the only remaining references of these 2 defines are
> located in cmd/mtdparts.c and only for local purpose when
> CONFIG_MTDIDS_DEFAULT or CONFIG_MTDPART_DEFAULT are not defined.
>
> Patrick.
>
>
> Patrick Delaunay (5):
>configs: am333x_guardian: move MTDIDS_DEFAULT in defconfif
>configs: x530: move MTDPART/MTDIDS_DEFAULT in defconfig
>configs: SBx81LIFXCAT: move MTDPART_DEFAULT in defconfig
>configs: SBx81LIFKW: move MTDPART_DEFAULT in defconfig
>configs: remove support of MTDIDS_DEFAULT/MTDPARTS_DEFAULT
For x530, SBx81LIFXCAT and SBx81LIFKW
Reviewed-by: Chris Packham
> cmd/mtdparts.c| 5 +
> configs/SBx81LIFKW_defconfig | 1 +
> configs/SBx81LIFXCAT_defconfig| 1 +
> configs/am335x_guardian_defconfig | 1 +
> configs/x530_defconfig| 2 ++
> drivers/mtd/mtd_uboot.c | 4
> include/configs/SBx81LIFKW.h | 1 -
> include/configs/SBx81LIFXCAT.h| 1 -
> include/configs/am335x_guardian.h | 1 -
> include/configs/x530.h| 2 --
> 10 files changed, 6 insertions(+), 13 deletions(-)
>
Re: [PATCH 2/2] configs: increase CONFIG_SYS_BOOTM_LEN to support kernel > 32MB
On Sun, Dec 11, 2022 at 11:46:54PM +0800, Jit Loon Lim wrote: > From: Kah Jing Lee > > Increase CONFIG_SYS_BOOTM_LEN to support kernel image from 5.15.lts > that is > 32MB > > Signed-off-by: Kah Jing Lee > Signed-off-by: Jit Loon Lim > --- > include/configs/socfpga_soc64_common.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/configs/socfpga_soc64_common.h > b/include/configs/socfpga_soc64_common.h > index 7fe9dced88..5167a2903e 100644 > --- a/include/configs/socfpga_soc64_common.h > +++ b/include/configs/socfpga_soc64_common.h > @@ -22,6 +22,7 @@ > */ > > /* Extend size of kernel image for uncompression */ > +#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) This option is controlled via Kconfig. -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/2] configs: add env. variable to support compressed kernel in qspiboot
On Sun, Dec 11, 2022 at 11:46:53PM +0800, Jit Loon Lim wrote: > From: Kah Jing Lee > > Fix qspiboot issue which uncompressed kernel(5.16) overflows to rootfs > Add 2 env. variables to support compressed kernel in legacy qspiboot: > setenv kernel_comp_addr_r 0x900 > setenv kernel_comp_size 0x0100 > > Signed-off-by: Kah Jing Lee > Signed-off-by: Jit Loon Lim > --- > include/configs/socfpga_soc64_common.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/configs/socfpga_soc64_common.h > b/include/configs/socfpga_soc64_common.h > index f7f3bc1f13..7fe9dced88 100644 > --- a/include/configs/socfpga_soc64_common.h > +++ b/include/configs/socfpga_soc64_common.h > @@ -133,6 +133,8 @@ > #else > > #define CONFIG_EXTRA_ENV_SETTINGS \ > + "kernel_comp_addr_r=0x900\0" \ > + "kernel_comp_size=0x0100\0" \ > "qspibootimageaddr=0x020E\0" \ > "qspifdtaddr=0x020D\0" \ > "bootimagesize=0x01F0\0" \ I would really like to see these kind of changes start being introduced in the text based environment files instead at this point, thanks. -- Tom signature.asc Description: PGP signature
[PATCH] ARM: imx: Factor common code out of Data Modul i.MX8M Mini eDM SBC
Pull common.c into common subdirectory of the board file,
since this code can be reused by other Data Modul SBCs.
Drop the include of lpddr4_timing.h, which is unneeded.
Signed-off-by: Marek Vasut
---
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
---
board/data_modul/common/common.c | 194 ++
board/data_modul/common/common.h | 18 ++
board/data_modul/imx8mm_edm_sbc/Makefile | 2 +-
board/data_modul/imx8mm_edm_sbc/common.c | 37
.../imx8mm_data_modul_edm_sbc.c | 66 +-
.../data_modul/imx8mm_edm_sbc/lpddr4_timing.h | 2 -
board/data_modul/imx8mm_edm_sbc/spl.c | 81 +---
7 files changed, 220 insertions(+), 180 deletions(-)
create mode 100644 board/data_modul/common/common.c
create mode 100644 board/data_modul/common/common.h
delete mode 100644 board/data_modul/imx8mm_edm_sbc/common.c
diff --git a/board/data_modul/common/common.c b/board/data_modul/common/common.c
new file mode 100644
index 000..bf9a11472d1
--- /dev/null
+++ b/board/data_modul/common/common.c
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Marek Vasut
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+u8 dmo_get_memcfg(void)
+{
+ struct gpio_desc gpio[4];
+ u8 memcfg = 0;
+ ofnode node;
+ int i, ret;
+
+ node = ofnode_path("/config");
+ if (!ofnode_valid(node)) {
+ printf("%s: no /config node?\n", __func__);
+ return BIT(2) | BIT(0);
+ }
+
+ ret = gpio_request_list_by_name_nodev(node,
+ "dmo,ram-coding-gpios",
+ gpio, ARRAY_SIZE(gpio),
+ GPIOD_IS_IN);
+ for (i = 0; i < ret; i++)
+ memcfg |= !!dm_gpio_get_value(&(gpio[i])) << i;
+
+ gpio_free_list_nodev(gpio, ret);
+
+ return memcfg;
+}
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+ u8 memcfg = dmo_get_memcfg();
+
+ *size = (4ULL >> ((memcfg >> 1) & 0x3)) * SZ_1G;
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+static void data_modul_imx_edm_sbc_early_init_f(const iomux_v3_cfg_t wdog_pad)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_pad(wdog_pad | MUX_PAD_CTRL(WDOG_PAD_CTRL));
+
+ set_wdog_reset(wdog);
+}
+
+__weak int data_modul_imx_edm_sbc_board_power_init(void)
+{
+ return 0;
+}
+
+static void spl_dram_init(struct dram_timing_info *dram_timing_info[8])
+{
+ u8 memcfg = dmo_get_memcfg();
+ int i;
+
+ printf("DDR: %d GiB x%d [0x%x]\n",
+ /* 0..4 GiB, 1..2 GiB, 0..1 GiB */
+ 4 >> ((memcfg >> 1) & 0x3),
+ /* 0..x32, 1..x16 */
+ 32 >> (memcfg & BIT(0)),
+ memcfg);
+
+ if (!dram_timing_info[memcfg]) {
+ printf("Unsupported DRAM strapping, trying lowest supported.
MEMCFG=0x%x\n",
+ memcfg);
+ for (i = 7; i >= 0; i--)
+ if (dram_timing_info[i])/* Configuration found
*/
+ break;
+ }
+
+ ddr_init(dram_timing_info[memcfg]);
+}
+
+void dmo_board_init_f(const iomux_v3_cfg_t wdog_pad,
+ struct dram_timing_info *dram_timing_info[8])
+{
+ struct udevice *dev;
+ int ret;
+
+ icache_enable();
+
+ arch_cpu_init();
+
+ init_uart_clk(2);
+
+ data_modul_imx_edm_sbc_early_init_f(wdog_pad);
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
+ preloader_console_init();
+
+ ret = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@3038",
+ );
+ if (ret < 0) {
+ printf("Failed to find clock node. Check device tree\n");
+ hang();
+ }
+
+ enable_tzc380();
+
+ data_modul_imx_edm_sbc_board_power_init();
+
+ /* DDR initialization */
+ spl_dram_init(dram_timing_info);
+
+ board_init_r(NULL, 0);
+}
+#else
+void dmo_setup_boot_device(void)
+{
+ int boot_device = get_boot_device();
+ char *devnum;
+
+ devnum = env_get("devnum");
+ if (devnum) /* devnum is already set */
+ return;
+
+ if (boot_device == MMC3_BOOT) /* eMMC */
+ env_set_ulong("devnum", 0);
+ else
+
[PATCH] ARM: imx: Drop board side icache enable on Data Modul i.MX8M Mini eDM SBC
The icache is enabled in common architecture code since commit:
2fa763baa1c ("ARM: imx: Enable instruction cache early on on i.MX8M")
Drop the board side duplicate code.
Signed-off-by: Marek Vasut
---
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
---
board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c
b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c
index dc0883002c8..82856f7a08c 100644
--- a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c
+++ b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c
@@ -19,12 +19,6 @@
DECLARE_GLOBAL_DATA_PTR;
-int mach_cpu_init(void)
-{
- icache_enable();
- return 0;
-}
-
int board_phys_sdram_size(phys_size_t *size)
{
u8 memcfg = dmo_get_memcfg();
--
2.35.1
[PATCH] ARM: imx: Enable LTO for Data Modul i.MX8M Mini eDM SBC
Enable LTO to reduce the size of SPL. Signed-off-by: Marek Vasut --- Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic --- configs/imx8mm_data_modul_edm_sbc_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index 3ccd26817ba..d9821885c3a 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -24,6 +24,7 @@ CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_ENV_OFFSET_REDUND=0xFFFC CONFIG_IMX_BOOTAUX=y CONFIG_SYS_LOAD_ADDR=0x6000 +CONFIG_LTO=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y -- 2.35.1
Re: [PATCH 8/8] sunxi: Parameterize H616 DRAM code some more
Dne nedelja, 11. december 2022 ob 17:32:13 CET je Jernej Skrabec napisal(a):
> Part of the code, previously known as "unknown feature" also doesn't
> have constant values. They are derived from TPR0 parameter in vendor
> DRAM code. Introduce that parameter here too, to ease adding new boards.
>
> Signed-off-by: Jernej Skrabec
> ---
> .../include/asm/arch-sunxi/dram_sun50i_h616.h | 1 +
> arch/arm/mach-sunxi/Kconfig | 6
> arch/arm/mach-sunxi/dram_sun50i_h616.c| 35 +++
> 3 files changed, 35 insertions(+), 7 deletions(-)
> diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
> b/arch/arm/mach-sunxi/dram_sun50i_h616.c index df06cea42464..6d8f8d371bfe
> 100644
> --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
> +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
> @@ -808,15 +808,35 @@ static bool mctl_phy_init(struct dram_para *para)
> writel(phy_init[i], [i]);
>
> if (para->tpr10 & TPR10_UNKNOWN_FEAT0) {
> + if (para->tpr0 & BIT(30))
> + val = (para->tpr0 >> 7) & 0x3e;
> + else
> + val = (para->tpr10 >> 3) & 0x1e;
> +
> ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x780);
> for (i = 0; i < 32; i++)
> - writel(0x16, [i]);
> - writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x78c);
> - writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7a4);
> - writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7b8);
> - writel(0x8, SUNXI_DRAM_PHY0_BASE + 0x7d4);
> - writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7dc);
> - writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7e0);
> + writel(val, [i]);
> +
> + val = (para->tpr10 << 1) & 0x1e;
> + writel(val, SUNXI_DRAM_PHY0_BASE + 0x7dc);
> + writel(val, SUNXI_DRAM_PHY0_BASE + 0x7e0);
> +
> + /* following configuration is DDR3 specific */
> + val = (para->tpr10 >> 7) & 0x1e;
> + writel(val, SUNXI_DRAM_PHY0_BASE + 0x7d4);
> + /*
> + * TODO: Offsets 0x79c, 0x794 and 0x7e4 may need
> + * to be set here. However, this doesn't seem to
> + * be needed by any board seen in the wild for now.
> + * It's not implemented because it would unnecessarily
> + * introduce PARA2 and TPR2 options.
> + */
I just noticed that PARA2 check actually checks rank. I think it's important
to implement it (register 0x79c) and uses only TPR10 value, which is already
present.
Best regards,
Jernej
> + if (para->tpr0 & BIT(31)) {
> + val = (para->tpr0 << 1) & 0x3e;
> + writel(val, SUNXI_DRAM_PHY0_BASE + 0x78c);
> + writel(val, SUNXI_DRAM_PHY0_BASE + 0x7a4);
> + writel(val, SUNXI_DRAM_PHY0_BASE + 0x7b8);
> + }
> }
>
> writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x3dc);
[PATCH 7/8] sunxi: Parameterize bit delay code in H616 DRAM driver
These values are highly board specific and thus make sense to add
parameter for them. To ease adding support for new boards, let's make
them same as in vendor DRAM settings.
Signed-off-by: Jernej Skrabec
---
.../include/asm/arch-sunxi/dram_sun50i_h616.h | 4 +
arch/arm/mach-sunxi/Kconfig | 18 ++
arch/arm/mach-sunxi/dram_sun50i_h616.c| 189 +-
3 files changed, 162 insertions(+), 49 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
index b5140c79b70e..c7890c83391f 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
@@ -145,6 +145,7 @@ check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240);
#define TPR10_READ_CALIBRATION BIT(21)
#define TPR10_READ_TRAININGBIT(22)
#define TPR10_WRITE_TRAINING BIT(23)
+#define TPR10_UNKNOWN_FEAT3BIT(30)
struct dram_para {
u32 clk;
@@ -156,7 +157,10 @@ struct dram_para {
u32 dx_odt;
u32 dx_dri;
u32 ca_dri;
+ u32 odt_en;
u32 tpr10;
+ u32 tpr11;
+ u32 tpr12;
};
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 778304b77e26..b050f0a56971 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -67,11 +67,29 @@ config DRAM_SUN50I_H616_CA_DRI
help
CA DRI value from vendor DRAM settings.
+config DRAM_SUN50I_H616_ODT_EN
+ hex "H616 DRAM ODT EN parameter"
+ default 0x1
+ help
+ ODT EN value from vendor DRAM settings.
+
config DRAM_SUN50I_H616_TPR10
hex "H616 DRAM TPR10 parameter"
help
TPR10 value from vendor DRAM settings. It tells which features
should be configured, like write leveling, read calibration, etc.
+
+config DRAM_SUN50I_H616_TPR11
+ hex "H616 DRAM TPR11 parameter"
+ default 0x0
+ help
+ TPR11 value from vendor DRAM settings.
+
+config DRAM_SUN50I_H616_TPR12
+ hex "H616 DRAM TPR12 parameter"
+ default 0x0
+ help
+ TPR12 value from vendor DRAM settings.
endif
config SUN6I_PRCM
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 3b2ba168498c..df06cea42464 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -574,7 +574,7 @@ static bool mctl_phy_write_training(struct dram_para *para)
static void mctl_phy_bit_delay_compensation(struct dram_para *para)
{
- u32 *ptr;
+ u32 *ptr, val;
int i;
if (para->tpr10 & TPR10_UNKNOWN_FEAT2) {
@@ -582,49 +582,93 @@ static void mctl_phy_bit_delay_compensation(struct
dram_para *para)
setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 8);
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
+ if (para->tpr10 & TPR10_UNKNOWN_FEAT3)
+ val = para->tpr11 & 0x3f;
+ else
+ val = (para->tpr11 & 0xf) << 1;
+
ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x484);
for (i = 0; i < 9; i++) {
- writel_relaxed(0x16, ptr);
- writel_relaxed(0x16, ptr + 0x30);
+ writel_relaxed(val, ptr);
+ writel_relaxed(val, ptr + 0x30);
ptr += 2;
}
- writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4d0);
- writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x590);
- writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4cc);
- writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x58c);
+
+ if (para->tpr10 & TPR10_UNKNOWN_FEAT3)
+ val = (para->odt_en >> 15) & 0x1e;
+ else
+ val = (para->tpr11 >> 15) & 0x1e;
+
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x4d0);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x590);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x4cc);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x58c);
+
+ if (para->tpr10 & TPR10_UNKNOWN_FEAT3)
+ val = (para->tpr11 >> 8) & 0x3f;
+ else
+ val = (para->tpr11 >> 3) & 0x1e;
ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x4d8);
for (i = 0; i < 9; i++) {
- writel_relaxed(0x1a, ptr);
- writel_relaxed(0x1a, ptr + 0x30);
+ writel_relaxed(val, ptr);
+ writel_relaxed(val, ptr + 0x30);
ptr += 2;
}
- writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x524);
- writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x5e4);
- writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x520);
-
[PATCH 8/8] sunxi: Parameterize H616 DRAM code some more
Part of the code, previously known as "unknown feature" also doesn't
have constant values. They are derived from TPR0 parameter in vendor
DRAM code. Introduce that parameter here too, to ease adding new boards.
Signed-off-by: Jernej Skrabec
---
.../include/asm/arch-sunxi/dram_sun50i_h616.h | 1 +
arch/arm/mach-sunxi/Kconfig | 6
arch/arm/mach-sunxi/dram_sun50i_h616.c| 35 +++
3 files changed, 35 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
index c7890c83391f..ff736bd88d10 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
@@ -158,6 +158,7 @@ struct dram_para {
u32 dx_dri;
u32 ca_dri;
u32 odt_en;
+ u32 tpr0;
u32 tpr10;
u32 tpr11;
u32 tpr12;
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index b050f0a56971..7858a7045f7e 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -73,6 +73,12 @@ config DRAM_SUN50I_H616_ODT_EN
help
ODT EN value from vendor DRAM settings.
+config DRAM_SUN50I_H616_TPR0
+ hex "H616 DRAM TPR0 parameter"
+ default 0x0
+ help
+ TPR0 value from vendor DRAM settings.
+
config DRAM_SUN50I_H616_TPR10
hex "H616 DRAM TPR10 parameter"
help
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index df06cea42464..6d8f8d371bfe 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -808,15 +808,35 @@ static bool mctl_phy_init(struct dram_para *para)
writel(phy_init[i], [i]);
if (para->tpr10 & TPR10_UNKNOWN_FEAT0) {
+ if (para->tpr0 & BIT(30))
+ val = (para->tpr0 >> 7) & 0x3e;
+ else
+ val = (para->tpr10 >> 3) & 0x1e;
+
ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x780);
for (i = 0; i < 32; i++)
- writel(0x16, [i]);
- writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x78c);
- writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7a4);
- writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7b8);
- writel(0x8, SUNXI_DRAM_PHY0_BASE + 0x7d4);
- writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7dc);
- writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7e0);
+ writel(val, [i]);
+
+ val = (para->tpr10 << 1) & 0x1e;
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x7dc);
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x7e0);
+
+ /* following configuration is DDR3 specific */
+ val = (para->tpr10 >> 7) & 0x1e;
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x7d4);
+ /*
+* TODO: Offsets 0x79c, 0x794 and 0x7e4 may need
+* to be set here. However, this doesn't seem to
+* be needed by any board seen in the wild for now.
+* It's not implemented because it would unnecessarily
+* introduce PARA2 and TPR2 options.
+*/
+ if (para->tpr0 & BIT(31)) {
+ val = (para->tpr0 << 1) & 0x3e;
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x78c);
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x7a4);
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x7b8);
+ }
}
writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x3dc);
@@ -1110,6 +1130,7 @@ unsigned long sunxi_dram_init(void)
.dx_dri = CONFIG_DRAM_SUN50I_H616_DX_DRI,
.ca_dri = CONFIG_DRAM_SUN50I_H616_CA_DRI,
.odt_en = CONFIG_DRAM_SUN50I_H616_ODT_EN,
+ .tpr0 = CONFIG_DRAM_SUN50I_H616_TPR0,
.tpr10 = CONFIG_DRAM_SUN50I_H616_TPR10,
.tpr11 = CONFIG_DRAM_SUN50I_H616_TPR11,
.tpr12 = CONFIG_DRAM_SUN50I_H616_TPR12,
--
2.38.1
[PATCH 6/8] sunxi: Make bit delay function in H616 DRAM code void
Mentioned function result is always true and result isn't checked
anyway. Let's make it void.
Signed-off-by: Jernej Skrabec
---
arch/arm/mach-sunxi/dram_sun50i_h616.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index bf5b4ddfb5c2..3b2ba168498c 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -572,7 +572,7 @@ static bool mctl_phy_write_training(struct dram_para *para)
return result;
}
-static bool mctl_phy_bit_delay_compensation(struct dram_para *para)
+static void mctl_phy_bit_delay_compensation(struct dram_para *para)
{
u32 *ptr;
int i;
@@ -683,8 +683,6 @@ static bool mctl_phy_bit_delay_compensation(struct
dram_para *para)
setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, 0x80);
}
-
- return true;
}
static bool mctl_phy_init(struct dram_para *para)
--
2.38.1
[PATCH 5/8] sunxi: Always configure ODT on H616 DRAM
Vendor H616 DRAM code always configure part which we call ODT configuration. Let's reflect that here too. Signed-off-by: Jernej Skrabec --- arch/arm/mach-sunxi/Kconfig| 2 +- arch/arm/mach-sunxi/dram_sun50i_h616.c | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index abcbd0fb9061..778304b77e26 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -488,12 +488,12 @@ config DRAM_ZQ config DRAM_ODT_EN bool "sunxi dram odt enable" + depends on !MACH_SUN50I_H616 default y if MACH_SUN8I_A23 default y if MACH_SUNXI_H3_H5 default y if MACH_SUN8I_R40 default y if MACH_SUN50I default y if MACH_SUN50I_H6 - default y if MACH_SUN50I_H616 ---help--- Select this to enable dram odt (on die termination). diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 14a01a3c4e54..bf5b4ddfb5c2 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -736,8 +736,7 @@ static bool mctl_phy_init(struct dram_para *para) writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x3dc); writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x45c); - if (IS_ENABLED(CONFIG_DRAM_ODT_EN)) - mctl_phy_configure_odt(para); + mctl_phy_configure_odt(para); clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 7, 0xa); -- 2.38.1
[PATCH 3/8] sunxi: parameterize H616 DRAM ODT values
While ODT values for same memory type are similar, they are not
necessary the same. Let's parameterize them and make parameter same as
in vendor DRAM settings. That way it will be easy to introduce new board
support.
Signed-off-by: Jernej Skrabec
---
.../include/asm/arch-sunxi/dram_sun50i_h616.h | 3 +
arch/arm/mach-sunxi/Kconfig | 15 +
arch/arm/mach-sunxi/dram_sun50i_h616.c| 59 ---
configs/orangepi_zero2_defconfig | 3 +
4 files changed, 58 insertions(+), 22 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
index 134679d55205..c9e1f84bfcdd 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
@@ -144,6 +144,9 @@ struct dram_para {
u8 rows;
u8 ranks;
u8 bus_full_width;
+ u32 dx_odt;
+ u32 dx_dri;
+ u32 ca_dri;
};
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index dbe6005daab1..cad53f19912c 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -83,6 +83,21 @@ config DRAM_SUN50I_H616_UNKNOWN_FEATURE
---help---
Select this when DRAM on your H616 board needs this unknown
feature.
+
+config DRAM_SUN50I_H616_DX_ODT
+ hex "H616 DRAM DX ODT parameter"
+ help
+ DX ODT value from vendor DRAM settings.
+
+config DRAM_SUN50I_H616_DX_DRI
+ hex "H616 DRAM DX DRI parameter"
+ help
+ DX DRI value from vendor DRAM settings.
+
+config DRAM_SUN50I_H616_CA_DRI
+ hex "H616 DRAM CA DRI parameter"
+ help
+ CA DRI value from vendor DRAM settings.
endif
config SUN6I_PRCM
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 49983bf7a1b8..06a07dfbf9cc 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -234,37 +234,49 @@ static const u8 phy_init[] = {
0x09, 0x05, 0x18
};
-static void mctl_phy_configure_odt(void)
+static void mctl_phy_configure_odt(struct dram_para *para)
{
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x388);
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x38c);
+ unsigned int val;
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x3c8);
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x3cc);
+ val = para->dx_dri & 0x1f;
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x388);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x38c);
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x408);
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x40c);
+ val = (para->dx_dri >> 8) & 0x1f;
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c8);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3cc);
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x448);
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x44c);
+ val = (para->dx_dri >> 16) & 0x1f;
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x408);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x40c);
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x340);
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x344);
+ val = (para->dx_dri >> 24) & 0x1f;
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x448);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x44c);
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x348);
- writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x34c);
+ val = para->ca_dri & 0x1f;
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x340);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x344);
- writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x380);
- writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x384);
+ val = (para->ca_dri >> 8) & 0x1f;
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x348);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x34c);
- writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x3c0);
- writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x3c4);
+ val = para->dx_odt & 0x1f;
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x380);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x384);
- writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x400);
- writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x404);
+ val = (para->dx_odt >> 8) & 0x1f;
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c0);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c4);
- writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x440);
- writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x444);
+ val = (para->dx_odt >> 16) & 0x1f;
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x400);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x404);
+
+ val = (para->dx_odt >> 24) & 0x1f;
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x440);
+ writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x444);
[PATCH 4/8] sunxi: Convert H616 DRAM options to single setting
Vendor DRAM settings use TPR10 parameter to enable various features.
There are many mores features that just those that are currently
mentioned. Since new will be added later and most are not known, let's
reuse value from vendor DRAM driver as-is. This will also help adding
support for new boards.
Signed-off-by: Jernej Skrabec
---
.../include/asm/arch-sunxi/dram_sun50i_h616.h | 10 +
arch/arm/mach-sunxi/Kconfig | 38 +---
arch/arm/mach-sunxi/dram_sun50i_h616.c| 197 +-
configs/orangepi_zero2_defconfig | 5 +-
4 files changed, 117 insertions(+), 133 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
index c9e1f84bfcdd..b5140c79b70e 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
@@ -137,6 +137,15 @@ check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240);
#define MSTR_ACTIVE_RANKS(x) (((x == 2) ? 3 : 1) << 24)
#define MSTR_BURST_LENGTH(x) (((x) >> 1) << 16)
+/* TODO: figure out what unknown features do */
+#define TPR10_UNKNOWN_FEAT0BIT(16)
+#define TPR10_UNKNOWN_FEAT1BIT(17)
+#define TPR10_UNKNOWN_FEAT2BIT(18)
+#define TPR10_WRITE_LEVELING BIT(20)
+#define TPR10_READ_CALIBRATION BIT(21)
+#define TPR10_READ_TRAININGBIT(22)
+#define TPR10_WRITE_TRAINING BIT(23)
+
struct dram_para {
u32 clk;
enum sunxi_dram_type type;
@@ -147,6 +156,7 @@ struct dram_para {
u32 dx_odt;
u32 dx_dri;
u32 ca_dri;
+ u32 tpr10;
};
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index cad53f19912c..abcbd0fb9061 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -52,38 +52,6 @@ config DRAM_SUN50I_H616
like H616.
if DRAM_SUN50I_H616
-config DRAM_SUN50I_H616_WRITE_LEVELING
- bool "H616 DRAM write leveling"
- ---help---
- Select this when DRAM on your H616 board needs write leveling.
-
-config DRAM_SUN50I_H616_READ_CALIBRATION
- bool "H616 DRAM read calibration"
- ---help---
- Select this when DRAM on your H616 board needs read calibration.
-
-config DRAM_SUN50I_H616_READ_TRAINING
- bool "H616 DRAM read training"
- ---help---
- Select this when DRAM on your H616 board needs read training.
-
-config DRAM_SUN50I_H616_WRITE_TRAINING
- bool "H616 DRAM write training"
- ---help---
- Select this when DRAM on your H616 board needs write training.
-
-config DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION
- bool "H616 DRAM bit delay compensation"
- ---help---
- Select this when DRAM on your H616 board needs bit delay
- compensation.
-
-config DRAM_SUN50I_H616_UNKNOWN_FEATURE
- bool "H616 DRAM unknown feature"
- ---help---
- Select this when DRAM on your H616 board needs this unknown
- feature.
-
config DRAM_SUN50I_H616_DX_ODT
hex "H616 DRAM DX ODT parameter"
help
@@ -98,6 +66,12 @@ config DRAM_SUN50I_H616_CA_DRI
hex "H616 DRAM CA DRI parameter"
help
CA DRI value from vendor DRAM settings.
+
+config DRAM_SUN50I_H616_TPR10
+ hex "H616 DRAM TPR10 parameter"
+ help
+ TPR10 value from vendor DRAM settings. It tells which features
+ should be configured, like write leveling, read calibration, etc.
endif
config SUN6I_PRCM
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 06a07dfbf9cc..14a01a3c4e54 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -577,109 +577,112 @@ static bool mctl_phy_bit_delay_compensation(struct
dram_para *para)
u32 *ptr;
int i;
- clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1);
- setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 8);
- clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
+ if (para->tpr10 & TPR10_UNKNOWN_FEAT2) {
+ clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1);
+ setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 8);
+ clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
- ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x484);
- for (i = 0; i < 9; i++) {
- writel_relaxed(0x16, ptr);
- writel_relaxed(0x16, ptr + 0x30);
- ptr += 2;
- }
- writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4d0);
- writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x590);
- writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4cc);
- writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x58c);
+ ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x484);
+ for (i = 0; i < 9; i++) {
+ writel_relaxed(0x16, ptr);
+ writel_relaxed(0x16, ptr + 0x30);
+ ptr += 2;
+ }
+ writel_relaxed(0x1c,
[PATCH 2/8] sunxi: cosmetic: Fix H616 DRAM driver code style
Fix code style for pointer declaration. This is just cosmetic change to
avoid checkpatch errors in later commits.
Signed-off-by: Jernej Skrabec
---
arch/arm/mach-sunxi/dram_sun50i_h616.c | 74 +-
1 file changed, 37 insertions(+), 37 deletions(-)
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 039e76224367..49983bf7a1b8 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -285,7 +285,7 @@ static bool mctl_phy_write_leveling(struct dram_para *para)
else
val = 3;
- mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x188), val, val);
+ mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x188), val, val);
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4);
@@ -314,7 +314,7 @@ static bool mctl_phy_write_leveling(struct dram_para *para)
else
val = 3;
- mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x188),
val, val);
+ mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x188),
val, val);
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4);
}
@@ -398,26 +398,26 @@ static bool mctl_phy_read_training(struct dram_para *para)
setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 6);
setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 1);
- mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x840), 0xc, 0xc);
+ mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x840), 0xc, 0xc);
if (readl(SUNXI_DRAM_PHY0_BASE + 0x840) & 3)
result = false;
if (para->bus_full_width) {
- mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0xa40),
0xc, 0xc);
+ mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa40),
0xc, 0xc);
if (readl(SUNXI_DRAM_PHY0_BASE + 0xa40) & 3)
result = false;
}
- ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x898);
- ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x850);
+ ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x898);
+ ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x850);
for (i = 0; i < 9; i++) {
val1 = readl([i]);
val2 = readl([i]);
if (val1 - val2 <= 6)
result = false;
}
- ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x8bc);
- ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x874);
+ ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x8bc);
+ ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x874);
for (i = 0; i < 9; i++) {
val1 = readl([i]);
val2 = readl([i]);
@@ -426,8 +426,8 @@ static bool mctl_phy_read_training(struct dram_para *para)
}
if (para->bus_full_width) {
- ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xa98);
- ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xa50);
+ ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa98);
+ ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa50);
for (i = 0; i < 9; i++) {
val1 = readl([i]);
val2 = readl([i]);
@@ -435,8 +435,8 @@ static bool mctl_phy_read_training(struct dram_para *para)
result = false;
}
- ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xabc);
- ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xa74);
+ ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xabc);
+ ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa74);
for (i = 0; i < 9; i++) {
val1 = readl([i]);
val2 = readl([i]);
@@ -454,12 +454,12 @@ static bool mctl_phy_read_training(struct dram_para *para)
setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 6);
setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 1);
- mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x840),
0xc, 0xc);
+ mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x840),
0xc, 0xc);
if (readl(SUNXI_DRAM_PHY0_BASE + 0x840) & 3)
result = false;
if (para->bus_full_width) {
- mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE +
0xa40), 0xc, 0xc);
+ mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE +
0xa40), 0xc, 0xc);
if (readl(SUNXI_DRAM_PHY0_BASE + 0xa40) & 3)
result = false;
}
@@ -488,26 +488,26 @@ static bool mctl_phy_write_training(struct dram_para
*para)
setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x20);
- mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x8e0), 3, 3);
+ mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x8e0), 3, 3);
if (readl(SUNXI_DRAM_PHY0_BASE + 0x8e0) & 0xc)
[PATCH 1/8] sunxi: Fix write to H616 DRAM CR register
Vendor DRAM code actually writes to whole CR register and not just sets bit 31 in mctl_ctrl_init(). Just to be safe, do that here too. Signed-off-by: Jernej Skrabec --- arch/arm/mach-sunxi/dram_sun50i_h616.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 454c845a0010..039e76224367 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -873,7 +873,7 @@ static bool mctl_ctrl_init(struct dram_para *para) writel(0x06000400, _ctl->unk_0x3240); writel(0x06000400, _ctl->unk_0x4240); - setbits_le32(_com->cr, BIT(31)); + writel(BIT(31), _com->cr); mctl_set_addrmap(para); -- 2.38.1
[PATCH 0/8] sunxi: Update H616 DRAM driver
Current H616 DRAM driver is completely customized to Orange Pi Zero2 board, which is currently the only H616 board supported by U-Boot. Needless to say, this is not ideal for adding new boards. With changes in this series, all DDR3 boards are supported and all that is needed is just vendor DRAM values extracted from Android image. New DRAM types should also be easier to support, since a lot of constants used before are not really DRAM type dependent. Changes were verified by decompiling driver and generated values were compared to previous, hard coded ones. This was done without dram_para structures, so compiler was able to heavily optimize code and produce constants. Please take a look. Best regards, Jernej Jernej Skrabec (8): sunxi: Fix write to H616 DRAM CR register sunxi: cosmetic: Fix H616 DRAM driver code style sunxi: parameterize H616 DRAM ODT values sunxi: Convert H616 DRAM options to single setting sunxi: Always configure ODT on H616 DRAM sunxi: Make bit delay function in H616 DRAM code void sunxi: Parameterize bit delay code in H616 DRAM driver sunxi: Parameterize H616 DRAM code some more .../include/asm/arch-sunxi/dram_sun50i_h616.h | 18 + arch/arm/mach-sunxi/Kconfig | 67 +-- arch/arm/mach-sunxi/dram_sun50i_h616.c| 445 +++--- configs/orangepi_zero2_defconfig | 8 +- 4 files changed, 348 insertions(+), 190 deletions(-) -- 2.38.1
[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd55lx02g
adding gd55lx02g to the file
Signed-off-by: Victor Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 726781f15b..a729575979 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -194,6 +194,8 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
{INFO("gd55lx01g", 0xc8681B, 0, 64 * 1024, 2048,SECT_4K |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lx02g", 0xc8681C, 0, 64 * 1024, 4096,SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
#endif
#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
/* ISSI */
--
2.25.1
[PATCH] mtd: spi: Add ISSI QSPI to lightweight SPI flash stack for spl
From: "Lokanathan, Raaj"
Add support for reading data/images from this ISSI QSPI flash.
Signed-off-by: Lokanathan, Raaj
Signed-off-by: Jit Loon Lim
---
drivers/mtd/spi/spi-nor-tiny.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c
index 68152ce3b4..6a5da38cb1 100644
--- a/drivers/mtd/spi/spi-nor-tiny.c
+++ b/drivers/mtd/spi/spi-nor-tiny.c
@@ -219,6 +219,7 @@ static inline int set_4byte(struct spi_nor *nor, const
struct flash_info *info,
case SNOR_MFR_MICRON:
/* Some Micron need WREN command; all will accept it */
need_wren = true;
+ case SNOR_MFR_ISSI:
case SNOR_MFR_MACRONIX:
case SNOR_MFR_WINBOND:
if (need_wren)
@@ -432,7 +433,7 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to,
size_t len,
return -ENOTSUPP;
}
-#ifdef CONFIG_SPI_FLASH_MACRONIX
+#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
/**
* macronix_quad_enable() - set QE bit in Status Register.
* @nor: pointer to a 'struct spi_nor'
@@ -661,8 +662,9 @@ static int spi_nor_setup(struct spi_nor *nor, const struct
flash_info *info,
/* Enable Quad I/O if needed. */
if (spi_nor_get_protocol_width(nor->read_proto) == 4) {
switch (JEDEC_MFR(info)) {
-#ifdef CONFIG_SPI_FLASH_MACRONIX
+#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
case SNOR_MFR_MACRONIX:
+ case SNOR_MFR_ISSI:
err = macronix_quad_enable(nor);
break;
#endif
--
2.26.2
[PATCH] arm: socfpga: Expand the help text for the bridge command.
From: "Lokanathan, Raaj" The existing bridge command is incomplete and it has spelling error. This newly added help text indicates the bit positions and the values of the mask. ie: bit 0 = h2f/s2f, bit 1 = lwhps2fpga, and bit 2 = f2h/f2s These bridges available only in Stratix 10: bit3: f2sdram0 bit4: f2sdram1 bit5: f2sdram2 Signed-off-by: Lokanathan, Raaj Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/misc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 9c19157de7..0112cfd101 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -209,8 +209,9 @@ static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc, U_BOOT_CMD(bridge, 3, 1, do_bridge, "SoCFPGA HPS FPGA bridge control", - "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" - "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges \n" + "bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges\n" + "Bit 3, Bit 4 and Bit 5 bridges only available in Stratix 10\n" "" ); -- 2.26.2
[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd55lx01g
adding gd55lx01g to the file
Signed-off-by: Victor Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 370d1f7698..726781f15b 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -192,6 +192,8 @@ const struct flash_info spi_nor_ids[] = {
},
{INFO("gd25lx512", 0xc8681A, 0, 64 * 1024, 1024,SECT_4K |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lx01g", 0xc8681B, 0, 64 * 1024, 2048,SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
#endif
#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
/* ISSI */
--
2.25.1
[PATCH 2/2] configs: increase CONFIG_SYS_BOOTM_LEN to support kernel > 32MB
From: Kah Jing Lee Increase CONFIG_SYS_BOOTM_LEN to support kernel image from 5.15.lts that is > 32MB Signed-off-by: Kah Jing Lee Signed-off-by: Jit Loon Lim --- include/configs/socfpga_soc64_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 7fe9dced88..5167a2903e 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -22,6 +22,7 @@ */ /* Extend size of kernel image for uncompression */ +#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) /* * U-Boot run time memory configurations -- 2.26.2
[PATCH 1/2] configs: add env. variable to support compressed kernel in qspiboot
From: Kah Jing Lee Fix qspiboot issue which uncompressed kernel(5.16) overflows to rootfs Add 2 env. variables to support compressed kernel in legacy qspiboot: setenv kernel_comp_addr_r 0x900 setenv kernel_comp_size 0x0100 Signed-off-by: Kah Jing Lee Signed-off-by: Jit Loon Lim --- include/configs/socfpga_soc64_common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index f7f3bc1f13..7fe9dced88 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -133,6 +133,8 @@ #else #define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_comp_addr_r=0x900\0" \ + "kernel_comp_size=0x0100\0" \ "qspibootimageaddr=0x020E\0" \ "qspifdtaddr=0x020D\0" \ "bootimagesize=0x01F0\0" \ -- 2.26.2
[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lx512
adding gd25lx512 to the file
Signed-off-by: Victor Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 8bead629f4..370d1f7698 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -190,6 +190,8 @@ const struct flash_info spi_nor_ids[] = {
INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
},
+ {INFO("gd25lx512", 0xc8681A, 0, 64 * 1024, 1024,SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
#endif
#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
/* ISSI */
--
2.25.1
[PATCH] Add CONFIG_SYS_NAND_SELF_INIT to Kconfig for NAND DENALI driver
From: "Lokanathan, Raaj" Add the CONFIG_SYS_NAND_SELF_INIT to the Kconfig to follow the changes from mainline. Signed-off-by: Lokanathan, Raaj Signed-off-by: Jit Loon Lim --- drivers/mtd/nand/raw/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index ce67d1abde..1e889afd01 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -148,6 +148,7 @@ config NAND_DENALI config NAND_DENALI_DT bool "Support Denali NAND controller as a DT device" select NAND_DENALI + select SPL_SYS_NAND_SELF_INIT depends on OF_CONTROL && DM_MTD help Enable the driver for NAND flash on platforms using a Denali NAND -- 2.26.2
[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd55lt02g
adding gd55lt02g to the file
Signed-off-by: Victor Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index a90b1a2e3c..8bead629f4 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -184,6 +184,8 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
{INFO("gd55lt01g", 0xc8661B, 0, 64 * 1024, 2048,SECT_4K |
SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lt02g", 0xc8661C, 0, 64 * 1024, 4096,SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
{
INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
--
2.25.1
[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd55lt01g
adding gd55lt01g to the file
Signed-off-by: Victor Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 0419dca074..a90b1a2e3c 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -182,6 +182,8 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
{INFO("gd25lt512", 0xc8661A, 0, 64 * 1024, 1024,SECT_4K |
SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lt01g", 0xc8661B, 0, 64 * 1024, 2048,SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
{
INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
--
2.25.1
[PATCH] spl: fit: nand: fix fit loading on bad blocks
From: Tien Fong Chee
The offset at which the image to be loaded from NAND is located
is retrieved from the itb header. The presence of bad blocks in
the area of the NAND where the itb image is located could
invalidate the offset which must therefore be adjusted taking
into account the state of the sectors concerned.
Signed-off-by: Tien Fong Chee
Signed-off-by: Jit Loon Lim
---
common/spl/spl_nand.c | 3 +-
drivers/mtd/nand/raw/denali.c | 91 ++-
2 files changed, 92 insertions(+), 2 deletions(-)
diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index 7b7579a2df..d94148ec71 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -45,10 +45,11 @@ static ulong spl_nand_fit_read(struct spl_load_info *load,
ulong offs,
int err;
ulong sector;
- sector = *(int *)load->priv;
offs *= load->bl_len;
size *= load->bl_len;
+ sector = *(int *)load->priv;
offs = sector + nand_spl_adjust_offset(sector, offs - sector);
+
err = nand_spl_load_image(offs, size, dst);
if (err)
return 0;
diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c
index c827f80281..290c12ac96 100644
--- a/drivers/mtd/nand/raw/denali.c
+++ b/drivers/mtd/nand/raw/denali.c
@@ -2,7 +2,7 @@
/*
* Copyright (C) 2014 Panasonic Corporation
* Copyright (C) 2013-2014, Altera Corporation
- * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
+ * Copyright (C) 2009-2022, Intel Corporation and its suppliers.
*/
#include
@@ -1374,3 +1374,92 @@ free_buf:
return ret;
}
+
+#ifdef CONFIG_SPL_BUILD
+struct mtd_info *nand_get_mtd(void)
+{
+ struct mtd_info *mtd;
+
+ mtd = get_nand_dev_by_index(nand_curr_device);
+ if (!mtd)
+ hang();
+
+ return mtd;
+}
+
+int nand_spl_load_image(u32 offset, u32 len, void *dst)
+{
+ size_t count = len, actual = 0, page_align_overhead = 0;
+ u32 page_align_offset = 0;
+ u8 *page_buffer;
+ int err = 0;
+ struct mtd_info *mtd;
+ if (!len || !dst)
+ return -EINVAL;
+
+ mtd = get_nand_dev_by_index(nand_curr_device);
+ if (!mtd)
+ hang();
+ mtd = nand_get_mtd();
+
+ if ((offset & (mtd->writesize - 1)) != 0) {
+ page_buffer = malloc_cache_aligned(mtd->writesize);
+ if (!page_buffer) {
+ debug("Error: allocating buffer\n");
+ return -ENOMEM;
+ }
+ page_align_overhead = offset % mtd->writesize;
+ page_align_offset = (offset / mtd->writesize) * mtd->writesize;
+ count = mtd->writesize;
+ err = nand_read_skip_bad(mtd, page_align_offset, ,
+, mtd->size, page_buffer);
+ if (err)
+ return err;
+ count -= page_align_overhead;
+ count = min((size_t)len, count);
+ memcpy(dst, page_buffer + page_align_overhead, count);
+ free(page_buffer);
+ len -= count;
+ if (!len)
+ return err;
+ offset += count;
+ dst += count;
+ count = len;
+ }
+ return nand_read_skip_bad(mtd, offset, , , mtd->size, dst);
+}
+
+/*
+ * This function is to adjust the load offset to skip bad blocks.
+ * The Denali NAND load image does skip bad blocks during read,
+ * hence this function is returning the offset as it is.
+ * The offset at which the image to be loaded from NAND is located is
+ * retrieved from the itb header. The presence of bad blocks in the area
+ * of the NAND where the itb image is located could invalidate the offset
+ * which must therefore be adjusted taking into account the state of the
+ * sectors concerned
+ */
+u32 nand_spl_adjust_offset(u32 sector, u32 offs)
+{
+ u32 sector_align_offset, sector_align_end_offset;
+ struct mtd_info *mtd;
+
+ mtd = nand_get_mtd();
+
+ sector_align_offset = sector & (~(mtd->erasesize - 1));
+
+ sector_align_end_offset = (sector + offs) & (~(mtd->erasesize - 1));
+
+ while (sector_align_offset <= sector_align_end_offset) {
+ if (nand_block_isbad(mtd, sector_align_offset)) {
+ offs += mtd->erasesize;
+ sector_align_end_offset += mtd->erasesize;
+ }
+ sector_align_offset += mtd->erasesize;
+ }
+
+ return offs;
+}
+
+void nand_deselect(void) {}
+#endif
--
2.26.2
[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lt512
adding gd25lt512 to the file
Signed-off-by: Victor Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 7dd1b63faa..0419dca074 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -180,6 +180,8 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
SPI_NOR_4B_OPCODES)},
{INFO("gd25lt256", 0xc86619, 0, 64 * 1024, 512, SECT_4K |
SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25lt512", 0xc8661A, 0, 64 * 1024, 1024,SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
{
INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
--
2.25.1
[PATCH] mtd: spi-nor-ids: add Macronix flash entry
From: Tien Fong Chee
Add Macronix mx25u51245g flash entry, so this can be used on
SoCFPGA devices.
Signed-off-by: Tien Fong Chee
Signed-off-by: Jit Loon Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 4fe8b0d92c..f5cf3d0156 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -182,7 +182,7 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K) },
{ INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) },
{ INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
- SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
{ INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ) },
{ INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K |
SPI_NOR_4B_OPCODES) },
--
2.26.2
[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lt256
adding gd25lt256 to the file
Signed-off-by: Victor Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 6634e9ceb1..7dd1b63faa 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -178,6 +178,8 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
SPI_NOR_4B_OPCODES)},
{INFO("gd25lf511", 0xc8631A, 0, 64 * 1024, 1024,SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
SPI_NOR_4B_OPCODES)},
+ {INFO("gd25lt256", 0xc86619, 0, 64 * 1024, 512, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
{
INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
--
2.25.1
[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lf511
adding gd25lf511 to the file
Signed-off-by: Victor Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 4aeaccd6d1..6634e9ceb1 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -176,6 +176,8 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
{INFO("gd25lf255", 0xc86319, 0, 64 * 1024, 512, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
SPI_NOR_4B_OPCODES)},
+ {INFO("gd25lf511", 0xc8631A, 0, 64 * 1024, 1024,SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
SPI_NOR_4B_OPCODES)},
{
INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
--
2.25.1
[PATCH] include: configs: socfpga: Add environment variables for distro boot
From: Yau Wai Gan
Added environment variables needed to support distro boot.
Signed-off-by: Yau Wai Gan
Signed-off-by: Jit Loon Lim
---
include/configs/socfpga_soc64_common.h | 81 +-
1 file changed, 80 insertions(+), 1 deletion(-)
diff --git a/include/configs/socfpga_soc64_common.h
b/include/configs/socfpga_soc64_common.h
index 5b1d243153..f7f3bc1f13 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -54,6 +54,84 @@
#define CONFIG_BOOTFILE "Image"
#endif
+#if IS_ENABLED(CONFIG_DISTRO_DEFAULTS)
+#if IS_ENABLED(CONFIG_CMD_MMC)
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#if IS_ENABLED(CONFIG_CMD_SF)
+#define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na)
+#else
+#define BOOT_TARGET_DEVICES_QSPI(func)
+#endif
+
+#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
+ "bootcmd_qspi=sf probe && " \
+ "sf read ${scriptaddr} ${qspiscriptaddr} ${scriptsize} && " \
+ "echo QSPI: Trying to boot script at ${scriptaddr} && " \
+ "source ${scriptaddr}; " \
+ "echo QSPI: SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
+ "qspi "
+
+#if IS_ENABLED(CONFIG_CMD_NAND)
+# define BOOT_TARGET_DEVICES_NAND(func)func(NAND, nand, na)
+#else
+# define BOOT_TARGET_DEVICES_NAND(func)
+#endif
+
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+ "bootcmd_nand=ubi part root && " \
+ "ubi readvol ${scriptaddr} script && " \
+ "echo NAND: Trying to boot script at ${scriptaddr} && " \
+ "source ${scriptaddr}; " \
+ "echo NAND: SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+ "nand "
+
+#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_DEVICES_MMC(func) \
+ BOOT_TARGET_DEVICES_QSPI(func) \
+ BOOT_TARGET_DEVICES_NAND(func)
+
+#include
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_addr_r=0x200\0" \
+ "fdt_addr_r=0x600\0" \
+ "qspiscriptaddr=0x0211\0" \
+ "scriptsize=0x0001\0" \
+ "qspibootimageaddr=0x0212\0" \
+ "bootimagesize=0x0320\0" \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "bootfile=" CONFIG_BOOTFILE "\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+ "linux_qspi_enable=if sf probe; then " \
+ "echo Enabling QSPI at Linux DTB...;" \
+ "fdt addr ${fdt_addr}; fdt resize;" \
+ "fdt set /soc/spi@ff8d2000 status okay;" \
+ "if fdt set /soc/clocks/qspi-clk clock-frequency" \
+ " ${qspi_clock}; then" \
+ " else fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \
+ " ${qspi_clock}; fi; fi\0" \
+ "scriptaddr=0x05FF\0" \
+ "scriptfile=boot.scr\0" \
+ "nandroot=ubi0:rootfs\0" \
+ "socfpga_legacy_reset_compat=1\0" \
+ "rsu_status=rsu dtb; rsu display_dcmf_version; "\
+ "rsu display_dcmf_status; rsu display_max_retry\0" \
+ "smc_fid_rd=0xC207\0" \
+ "smc_fid_wr=0xC208\0" \
+ "smc_fid_upd=0xC209\0 " \
+ BOOTENV
+
+#else
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"qspibootimageaddr=0x020E\0" \
"qspifdtaddr=0x020D\0" \
@@ -106,7 +184,8 @@
"rsu display_dcmf_status; rsu display_max_retry\0" \
"smc_fid_rd=0xC207\0" \
"smc_fid_wr=0xC208\0" \
- "smc_fid_upd=0xC209\0 " \
+ "smc_fid_upd=0xC209\0 "
+#endif /*#if IS_ENABLED(CONFIG_DISTRO_DEFAULTS)*/
/*
* External memory configurations
--
2.26.2
[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lf255
adding gd25lf255 to the file
Signed-off-by: Victor Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index d3dba87c22..4aeaccd6d1 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -174,6 +174,8 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
{INFO("gd25lf128", 0xc86318, 0, 64 * 1024, 256, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
+ {INFO("gd25lf255", 0xc86319, 0, 64 * 1024, 512, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
SPI_NOR_4B_OPCODES)},
{
INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
--
2.25.1
[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lf128
adding gd25lf128 to the file
Signed-off-by: Victor Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 86e97dcb4e..d3dba87c22 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -172,6 +172,8 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
{INFO("gd25lf64", 0xc86317, 0, 64 * 1024, 128, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
+ {INFO("gd25lf128", 0xc86318, 0, 64 * 1024, 256, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
{
INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
--
2.25.1
[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lf64
adding gd25lf64 to the file
Signed-off-by: Victor Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 758aca20fd..86e97dcb4e 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -170,6 +170,8 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
{INFO("gd25lf32", 0xc86316, 0, 64 * 1024, 64, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
+ {INFO("gd25lf64", 0xc86317, 0, 64 * 1024, 128, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
{
INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
--
2.25.1
[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lf32
adding gd25lf32 to the file
Signed-off-by: Victor Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index dbf8b8e298..758aca20fd 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -168,6 +168,8 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
{INFO("gd25lf16", 0xc86315, 0, 64 * 1024, 32, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+ {INFO("gd25lf32", 0xc86316, 0, 64 * 1024, 64, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
{
INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
--
2.25.1
[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lf16
adding gd25lf16 to the file
Signed-off-by: Victor Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 158b0057a5..dbf8b8e298 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -166,6 +166,8 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
{INFO("gd25lf80", 0xc86314, 0, 64 * 1024, 16, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+ {INFO("gd25lf16", 0xc86315, 0, 64 * 1024, 32, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
{
INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
--
2.25.1
[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lf80
adding gd25lf80 to the file
Signed-off-by: Victor Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 5d8a08bfe2..158b0057a5 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -164,6 +164,8 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
{INFO("gd55lb02g", 0xc8671C, 0, 64 * 1024, 4096,SECT_4K |
SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25lf80", 0xc86314, 0, 64 * 1024, 16, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
{
INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
--
2.25.1
[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd55lb02g
adding gd55lb02g to the file
Signed-off-by: Victor Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index b9381042ac..5d8a08bfe2 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -162,6 +162,8 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
{INFO("gd55lb01g", 0xc8671B, 0, 64 * 1024, 2048,SECT_4K |
SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lb02g", 0xc8671C, 0, 64 * 1024, 4096,SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
{
INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
--
2.25.1
[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd55lb01g
adding gd55lb01g to the file
Signed-off-by: Victor Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 213a404604..b9381042ac 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -160,6 +160,8 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
{INFO("gd25lb512", 0xc8671A, 0, 64 * 1024, 1024,SECT_4K |
SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lb01g", 0xc8671B, 0, 64 * 1024, 2048,SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
{
INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
--
2.25.1
[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lb512
adding gd25lb512 to the file
Signed-off-by: Victor Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 00c46f75be..213a404604 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -158,6 +158,8 @@ const struct flash_info spi_nor_ids[] = {
},
{INFO("gd25lb256", 0xc86719, 0, 64 * 1024, 512, SECT_4K |
SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25lb512", 0xc8671A, 0, 64 * 1024, 1024,SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
{
INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
--
2.25.1
[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lb256
adding gd25lb256 to the file
Signed-off-by: Victor Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 133550dd3b..00c46f75be 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -156,6 +156,8 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ {INFO("gd25lb256", 0xc86719, 0, 64 * 1024, 512, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
{
INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
--
2.25.1
[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd55x02g
adding gd55x02g to the file
Signed-off-by: Victor Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index f6ca16ac62..133550dd3b 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -144,6 +144,8 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
{INFO("gd55x01g", 0xc8481B, 0, 64 * 1024, 2048, SECT_4K |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
{
INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ |
--
2.25.1
[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd55x01g
adding gd55x01g to the file
Signed-off-by: Victor Lim
---
drivers/mtd/spi/spi-nor-ids.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 741b40fbde..f6ca16ac62 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -142,6 +142,8 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
{INFO("gd25x512", 0xc8481A, 0, 64 * 1024, 1024, SECT_4K |
SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55x01g", 0xc8481B, 0, 64 * 1024, 2048, SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
{
INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ |
--
2.25.1
[PATCH] mkimage: fit: Support signed configurations in 'auto' FITs
Hi, The patch follows, as per discussion in email thread "Patch proposal - mkimage: fit: Support signed conf 'auto' FITs". Let me know if you prefer something to be changed, or patch to be split in several commits. I have updated the man page with description of the new feature and examples. Also fixed some wrong or misleading information. === mkimage: fit: Support signed configurations in 'auto' FITs Extend support for signing in auto-generated (-f auto) FIT. Previously, it was possible to get signed 'images' subnodes in the FIT using options -g and -o together with -f auto. This patch allows signing 'configurations' subnodes instead of 'images' ones (which are hashed), using option -f auto-conf instead of -f auto. Adding also -K and -r options, will add public key to file with required = "conf" property. Summary: -f auto => FIT with crc32 images -f auto -g ... -o ... => FIT with signed images -f auto-conf -g ... -o ... => FIT with sha1 images and signed confs Example: FIT with kernel, two device tree files, and signed configurations; public key (needed to verify signatures) is added to u-boot.dtb with required = "conf" property. mkimage -f auto-conf -A arm -O linux -T kernel -C none -a 43e0 \ -e 0 -d vmlinuz -b /path/to/first.dtb -b /path/to/second.dtb \ -k /folder/with/key-files -g keyname -o sha256,rsa4096 \ -K u-boot.dtb -r kernel.itb Example: Add public key with required = "conf" property to u-boot.dtb without needing to sign anything. This will also create a useless FIT named unused.itb. mkimage -f auto-conf -d /dev/null -k /folder/with/key-files \ -g keyname -o sha256,rsa4096 -K u-boot.dtb -r unused.itb Signed-off-by: Massimo Pegorer --- doc/mkimage.1 | 119 -- tools/fit_image.c | 75 +++-- tools/imagetool.h | 10 +++- tools/mkimage.c | 23 +++-- 4 files changed, 160 insertions(+), 67 deletions(-) diff --git a/doc/mkimage.1 b/doc/mkimage.1 index 353ea8b2f7..d8727ec73c 100644 --- a/doc/mkimage.1 +++ b/doc/mkimage.1 @@ -22,7 +22,8 @@ mkimage \- generate images for U-Boot .SY mkimage .RI [ option\~ .\|.\|.\&] .BI \-f\~ image-tree-source-file\c -.RB | auto +.RB | auto\c +.RB | auto-conf .I image-file-name .YS . @@ -296,9 +297,9 @@ FIT. See for details on using external data. . .TP -\fB\-f \fIimage-tree-source-file\fR | \fBauto +\fB\-f \fIimage-tree-source-file\fR | \fBauto\fR | \fBauto-conf .TQ -\fB\-\-fit \fIimage-tree-source-file\fR | \fBauto +\fB\-\-fit \fIimage-tree-source-file\fR | \fBauto\fR | \fBauto-conf Image tree source file that describes the structure and contents of the FIT image. .IP @@ -317,7 +318,25 @@ and options may be used to specify the image to include in the FIT and its attributes. No .I image-tree-source-file -is required. +is required. The +.BR \-g , +.BR \-o , +and +.B \-k +or +.B \-G +options may be used to get \(oqimages\(cq signed subnodes in the generated +auto FIT. Instead, to get \(oqconfigurations\(cq signed subnodes and +\(oqimages\(cq hashed subnodes, pass +.BR "\-f auto-conf". +In this case +.BR \-g , +.BR \-o , +and +.B \-k +or +.B \-G +are mandatory options. . .TP .B \-F @@ -348,16 +367,16 @@ for use with signing, and a certificate necessary when embedding it into another device tree using .BR \-K . .I name -defaults to the value of the signature node's \(oqkey-name-hint\(cq property, -but may be overridden using -.BR \-g . +is the value of the signature node's \(oqkey-name-hint\(cq property. . .TP .BI \-G " key-file" .TQ .BI \-\-key\-file " key-file" Specifies the private key file to use when signing. This option may be used -instead of \-k. +instead of \-k. Useful when the private key file basename does not match +\(oqkey-name-hint\(cq value. But note that it may lead to unexpected results +when used together with -K and/or -k options. . .TP .BI \-K " key-destination" @@ -373,49 +392,50 @@ CONFIG_OF_CONTROL in U-Boot. .BI \-g " key-name-hint" .TQ .BI \-\-key\-name\-hint " key-name-hint" -Overrides the signature node's \(oqkey-name-hint\(cq property. This is -especially useful when signing an image with -.BR "\-f auto" . -This is the -.I name -part of the key. The directory part is set by -.BR \-k . -This option also indicates that the images included in the FIT should be signed. -If this option is specified, then +Specifies the value of signature node \(oqkey-name-hint\(cq property for +an automatically generated FIT image. It makes sense only when used with +.B "\-f auto" +or +.BR "\-f auto-conf". +This option also indicates that the images or configurations included in +the FIT should be signed. If this option is specified, then .B \-o must be specified as well. . .TP -.BI \-o " crypto" , checksum +.BI \-o " checksum" , crypto .TQ -.BI \-\-algo " crypto" , checksum -Specifies the algorithm to be used for signing a FIT image. The default is -taken from the signature node's
[PATCH 3/4] arm: dts: Update NAND MTD partition for Agilex and Stratix 10
From: Sin Hui Kho
Change NAND flash MTD partition in device tree after implementation of
UBI and UBIFS. "u-boot" partition remain for raw u-boot image, but "root"
partition is use for UBI image containing all other components.
Signed-off-by: Sin Hui Kho
Signed-off-by: Jit Loon Lim
---
arch/arm/dts/socfpga_agilex_socdk_nand.dts| 55 ++
arch/arm/dts/socfpga_stratix10_socdk_nand.dts | 167 ++
2 files changed, 222 insertions(+)
create mode 100755 arch/arm/dts/socfpga_agilex_socdk_nand.dts
create mode 100755 arch/arm/dts/socfpga_stratix10_socdk_nand.dts
diff --git a/arch/arm/dts/socfpga_agilex_socdk_nand.dts
b/arch/arm/dts/socfpga_agilex_socdk_nand.dts
new file mode 100755
index 00..3237e34c99
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex_socdk_nand.dts
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation
+ */
+#include "socfpga_agilex_socdk.dts"
+#include "socfpga_agilex_socdk-u-boot.dtsi"
+ {
+ status = "disabled";
+};
+ {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <>;
+ max-frame-size = <3800>;
+ mdio2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy2: ethernet-phy@2 {
+ reg = <4>;
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ rxd0-skew-ps = <420>; /* 0ps */
+ rxd1-skew-ps = <420>; /* 0ps */
+ rxd2-skew-ps = <420>; /* 0ps */
+ rxd3-skew-ps = <420>; /* 0ps */
+ txen-skew-ps = <0>; /* -420ps */
+ txc-skew-ps = <1860>; /* 960ps */
+ rxdv-skew-ps = <420>; /* 0ps */
+ rxc-skew-ps = <1680>; /* 780ps */
+ };
+ };
+};
+ {
+ status = "disabled";
+};
+ {
+ flash@0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "u-boot";
+ reg = <0 0x20>;
+ };
+ partition@20 {
+ label = "root";
+ reg = <0x20 0x3fe0>;
+ };
+ };
+ };
+};
\ No newline at end of file
diff --git a/arch/arm/dts/socfpga_stratix10_socdk_nand.dts
b/arch/arm/dts/socfpga_stratix10_socdk_nand.dts
new file mode 100755
index 00..9a23c36b92
--- /dev/null
+++ b/arch/arm/dts/socfpga_stratix10_socdk_nand.dts
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright Altera Corporation (C) 2015. All rights reserved.
+ */
+#include "socfpga_stratix10.dtsi"
+/ {
+ model = "SoCFPGA Stratix 10 SoCDK";
+ aliases {
+ serial0 =
+ ethernet0 =
+ ethernet1 =
+ ethernet2 =
+ };
+ leds {
+ compatible = "gpio-leds";
+ hps0 {
+ label = "hps_led0";
+ gpios = < 20 GPIO_ACTIVE_HIGH>;
+ };
+ hps1 {
+ label = "hps_led1";
+ gpios = < 19 GPIO_ACTIVE_HIGH>;
+ };
+ hps2 {
+ label = "hps_led2";
+ gpios = < 21 GPIO_ACTIVE_HIGH>;
+ };
+ };
+ memory {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0 0 0>;
+ };
+ ref_033v: 033-v-ref {
+ compatible = "regulator-fixed";
+ regulator-name = "0.33V";
+ regulator-min-microvolt = <33>;
+ regulator-max-microvolt = <33>;
+ };
+ soc {
+ clocks {
+ osc1 {
+ clock-frequency = <2500>;
+ };
+ };
+ eccmgr {
+ sdmmca-ecc@ff8c8c00 {
+ compatible = "altr,socfpga-s10-sdmmc-ecc",
+"altr,socfpga-sdmmc-ecc";
+ reg = <0xff8c8c00 0x100>;
+ altr,ecc-parent = <>;
+ interrupts = <14 4>,
+<15 4>;
+ };
+ };
+ };
+};
+ {
+ status = "okay";
+};
+ {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <>;
+
[PATCH 1/4] configs: defconfig: Enable UBI and UBIFS for Agilex and Stratix10
From: Sin Hui Kho Enabling configs required for UBI and UBIFS commands. Set environment in a UBI volume. So, remove CONFIG_ENV_IS_IN_NAND as the environment is now in UBI volume. Signed-off-by: Sin Hui Kho Signed-off-by: Jit Loon Lim --- configs/socfpga_agilex_nand_atf_defconfig| 11 +-- configs/socfpga_agilex_nand_defconfig| 11 +-- configs/socfpga_stratix10_nand_atf_defconfig | 11 +-- configs/socfpga_stratix10_nand_defconfig | 11 +-- 4 files changed, 36 insertions(+), 8 deletions(-) diff --git a/configs/socfpga_agilex_nand_atf_defconfig b/configs/socfpga_agilex_nand_atf_defconfig index bfc893fd39..16509d868b 100644 --- a/configs/socfpga_agilex_nand_atf_defconfig +++ b/configs/socfpga_agilex_nand_atf_defconfig @@ -53,7 +53,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_MTDIDS_DEFAULT="nand0=ffb9.nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb9.nand.0:2m(u-boot),256k(env),256k(dtb),32m(kernel),32m(misc),-(rootfs)" -CONFIG_ENV_IS_IN_NAND=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y @@ -90,4 +89,12 @@ CONFIG_USB_STORAGE=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_UBI=y +CONFIG_CMD_UBIFS=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_ENV_IS_IN_UBI=y +CONFIG_ENV_UBI_PART="root" +CONFIG_ENV_UBI_VOLUME="env" \ No newline at end of file diff --git a/configs/socfpga_agilex_nand_defconfig b/configs/socfpga_agilex_nand_defconfig index 3f95aac147..7ba5016c2e 100644 --- a/configs/socfpga_agilex_nand_defconfig +++ b/configs/socfpga_agilex_nand_defconfig @@ -46,7 +46,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_MTDIDS_DEFAULT="nand0=ffb9.nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb9.nand.0:2m(u-boot),256k(env),256k(dtb),32m(kernel),32m(misc),-(rootfs)" -CONFIG_ENV_IS_IN_NAND=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y @@ -83,4 +82,12 @@ CONFIG_USB_STORAGE=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_UBI=y +CONFIG_CMD_UBIFS=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_ENV_IS_IN_UBI=y +CONFIG_ENV_UBI_PART="root" +CONFIG_ENV_UBI_VOLUME="env" \ No newline at end of file diff --git a/configs/socfpga_stratix10_nand_atf_defconfig b/configs/socfpga_stratix10_nand_atf_defconfig index a9abd85e68..4a4b426b99 100644 --- a/configs/socfpga_stratix10_nand_atf_defconfig +++ b/configs/socfpga_stratix10_nand_atf_defconfig @@ -53,7 +53,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_MTDIDS_DEFAULT="nand0=ffb9.nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb9.nand.0:2m(u-boot),256k(env),256k(dtb),32m(kernel),32m(misc),-(rootfs)" -CONFIG_ENV_IS_IN_NAND=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y @@ -91,4 +90,12 @@ CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_UBI=y +CONFIG_CMD_UBIFS=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_ENV_IS_IN_UBI=y +CONFIG_ENV_UBI_PART="root" +CONFIG_ENV_UBI_VOLUME="env" \ No newline at end of file diff --git a/configs/socfpga_stratix10_nand_defconfig b/configs/socfpga_stratix10_nand_defconfig index 48c20e5b11..a148eac83f 100644 --- a/configs/socfpga_stratix10_nand_defconfig +++ b/configs/socfpga_stratix10_nand_defconfig @@ -46,7 +46,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_MTDIDS_DEFAULT="nand0=ffb9.nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb9.nand.0:2m(u-boot),256k(env),256k(dtb),32m(kernel),32m(misc),-(rootfs)" -CONFIG_ENV_IS_IN_NAND=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y @@ -84,4 +83,12 @@ CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_UBI=y +CONFIG_CMD_UBIFS=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_ENV_IS_IN_UBI=y +CONFIG_ENV_UBI_PART="root" +CONFIG_ENV_UBI_VOLUME="env" \ No newline at end of file -- 2.26.2
[PATCH 4/4] arm: socfpga: soc64: Load and boot for NAND flash with UBI and UBIFS in enviroment
From: Sin Hui Kho
Load kernel and device tree from UBI volume. Set root file system type
for NAND boot as UBIFS located at UBI volume on MTD partition 1 or
namely "root".
Signed-off-by: Sin Hui Kho
Signed-off-by: Jit Loon Lim
---
include/configs/socfpga_soc64_common.h | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/include/configs/socfpga_soc64_common.h
b/include/configs/socfpga_soc64_common.h
index 5939f13231..5b1d243153 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -92,10 +92,15 @@
"scriptfile=u-boot.scr\0" \
"fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
"then source ${scriptaddr}:script; fi\0" \
+ "nandroot=ubi0:rootfs\0" \
+ "nandload=ubi part root; ubi readvol ${loadaddr} kernel; ubi readvol
${fdt_addr} dtb\0" \
+ "nandboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${nandroot} rw rootwait rootfstype=ubifs
ubi.mtd=1; " \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
"nandfitboot=setenv bootargs " CONFIG_BOOTARGS \
- " root=${nandroot} rw rootwait rootfstype=jffs2; " \
+ " root=${nandroot} rw rootwait rootfstype=ubifs
ubi.mtd=1; " \
"bootm ${loadaddr}\0" \
- "nandfitload=nand read ${loadaddr} kernel\0" \
+ "nandfitload=ubi part root; ubi readvol ${loadaddr} kernel\0" \
"socfpga_legacy_reset_compat=1\0" \
"rsu_status=rsu dtb; rsu display_dcmf_version; "\
"rsu display_dcmf_status; rsu display_max_retry\0" \
--
2.26.2
[PATCH 2/4] configs: defconfig: Update default NAND MTD partition for Agilex and Stratix 10
From: Sin Hui Kho Change default MTD partition scheme for NAND flash after implementation of UBI and UBIFS. "u-boot" partition remain for raw u-boot image, but "root" partition is use for UBI image containing all other components. Signed-off-by: Sin Hui Kho Signed-off-by: Jit Loon Lim --- configs/socfpga_agilex_nand_atf_defconfig| 2 +- configs/socfpga_agilex_nand_defconfig| 2 +- configs/socfpga_stratix10_nand_atf_defconfig | 2 +- configs/socfpga_stratix10_nand_defconfig | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/configs/socfpga_agilex_nand_atf_defconfig b/configs/socfpga_agilex_nand_atf_defconfig index 16509d868b..eeaaacff7a 100644 --- a/configs/socfpga_agilex_nand_atf_defconfig +++ b/configs/socfpga_agilex_nand_atf_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_MTDIDS_DEFAULT="nand0=ffb9.nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb9.nand.0:2m(u-boot),256k(env),256k(dtb),32m(kernel),32m(misc),-(rootfs)" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb9.nand.0:2m(u-boot),-(root)" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y diff --git a/configs/socfpga_agilex_nand_defconfig b/configs/socfpga_agilex_nand_defconfig index 7ba5016c2e..50c17bd8af 100644 --- a/configs/socfpga_agilex_nand_defconfig +++ b/configs/socfpga_agilex_nand_defconfig @@ -45,7 +45,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_MTDIDS_DEFAULT="nand0=ffb9.nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb9.nand.0:2m(u-boot),256k(env),256k(dtb),32m(kernel),32m(misc),-(rootfs)" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb9.nand.0:2m(u-boot),-(root)" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y diff --git a/configs/socfpga_stratix10_nand_atf_defconfig b/configs/socfpga_stratix10_nand_atf_defconfig index 4a4b426b99..443f057219 100644 --- a/configs/socfpga_stratix10_nand_atf_defconfig +++ b/configs/socfpga_stratix10_nand_atf_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_MTDIDS_DEFAULT="nand0=ffb9.nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb9.nand.0:2m(u-boot),256k(env),256k(dtb),32m(kernel),32m(misc),-(rootfs)" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb9.nand.0:2m(u-boot),-(root)" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y diff --git a/configs/socfpga_stratix10_nand_defconfig b/configs/socfpga_stratix10_nand_defconfig index a148eac83f..db2dd17dff 100644 --- a/configs/socfpga_stratix10_nand_defconfig +++ b/configs/socfpga_stratix10_nand_defconfig @@ -45,7 +45,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_MTDIDS_DEFAULT="nand0=ffb9.nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb9.nand.0:2m(u-boot),256k(env),256k(dtb),32m(kernel),32m(misc),-(rootfs)" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb9.nand.0:2m(u-boot),-(root)" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y -- 2.26.2
[PATCH] arm: socfpga: Export Board ID as U-boot Environment Variable
From: Yau Wai Gan
Board ID is exported as environment variable for use to boot Linux FIT
configuration.
Signed-off-by: Yau Wai Gan
Signed-off-by: Jit Loon Lim
---
arch/arm/mach-socfpga/misc_soc64.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc_soc64.c
b/arch/arm/mach-socfpga/misc_soc64.c
index 49b241b7b8..d092268fea 100644
--- a/arch/arm/mach-socfpga/misc_soc64.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -20,6 +20,8 @@
DECLARE_GLOBAL_DATA_PTR;
+u8 socfpga_get_board_id(void);
+
/*
* FPGA programming support for SoC FPGA Stratix 10
*/
@@ -57,10 +59,15 @@ int print_cpuinfo(void)
int arch_misc_init(void)
{
char qspi_string[13];
+ char id[3];
sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
env_set("qspi_clock", qspi_string);
+ /* Export board_id as environment variable */
+ sprintf(id, "%u", socfpga_get_board_id());
+ env_set("board_id", id);
+
return 0;
}
#endif
--
2.26.2
[PATCH u-boot] powerpc/mpc85xx: Improve disabling of SPE instructions
Specifying -mspe=no also disables usage of SPE instructions. It is documented in "[PATCH,rs6000] make -mno-spe work as expected" email: http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html So replace -mspe=yes by -mspe=no, so make it clear that u-boot has to be compiled without SPE instructions. Linux kernel contains following Makefile code to achieve it: # No SPE instruction when building kernel # (We use all available options to help semi-broken compilers) KBUILD_CFLAGS += $(call cc-option,-mno-spe) KBUILD_CFLAGS += $(call cc-option,-mspe=no) Do same for U-Boot. Signed-off-by: Pali Rohár --- arch/powerpc/cpu/mpc85xx/config.mk | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/config.mk b/arch/powerpc/cpu/mpc85xx/config.mk index b6b5d2053aea..482bb90cb120 100644 --- a/arch/powerpc/cpu/mpc85xx/config.mk +++ b/arch/powerpc/cpu/mpc85xx/config.mk @@ -6,11 +6,12 @@ PLATFORM_CPPFLAGS += -msoft-float -mno-string PLATFORM_RELFLAGS += -msingle-pic-base -fno-jump-tables -# -mspe=yes is needed to have -mno-spe accepted by a buggy GCC; +# No SPE instruction when building u-boot +# (We use all available options to help semi-broken compilers) # see "[PATCH,rs6000] make -mno-spe work as expected" on # http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html -PLATFORM_CPPFLAGS += $(call cc-option,-mspe=yes) \ - $(call cc-option,-mno-spe) +PLATFORM_CPPFLAGS += $(call cc-option,-mno-spe) \ +$(call cc-option,-mspe=no) ifdef CONFIG_E6500 PLATFORM_CPPFLAGS += -mcpu=e6500 -- 2.20.1
[PATCH] arm: socfpga: Enable U-boot FIT Config Name Match with Board ID
From: Yau Wai Gan
U-boot FIT configuration shall be selected based on the Board ID that is set.
Signed-off-by: Yau Wai Gan
Signed-off-by: Jit Loon Lim
---
arch/arm/mach-socfpga/board.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 11abf864f5..a9086d9fbe 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -131,13 +131,16 @@ u8 socfpga_get_board_id(void)
}
-#ifdef CONFIG_SPL_BUILD
-__weak int board_fit_config_name_match(const char *name)
+#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
+int board_fit_config_name_match(const char *name)
{
- /* Just empty function now - can't decide what to choose */
- debug("%s: %s\n", __func__, name);
+ char board_name[10];
- return 0;
+ sprintf(board_name, "board_%u", socfpga_get_board_id());
+
+ debug("Board name: %s\n", board_name);
+
+ return strcmp(name, board_name);
}
#endif
--
2.26.2
[PATCH u-boot] powerpc/mpc85xx: Pass correct cpu compiler flags
When gcc's default cpu (selected by --with-cpu= during gcc's configure
phase) does not match target u-boot board cpu then u-boot binary does not
have to be compiled correctly. Lot of distributions sets gcc's default cpu
to generic powerpc variant which works fine.
U-Boot already pass -Wa,-me500 flag to gcc which instructs GNU AS to accept
e500 specific instructions when processing assembler source files (.S).
This affects also assembly files generated by gcc from C source files. And
because gcc for generic powerpc cpu puts '.machine ppc' at the beginning of
the generated assembly file, it basically overwrites -me500 flag by which
was GNU AS invoked (from U-boot build system).
It started to be an issue since binutils 2.38 which does not keep enabled
extra functional units selected by previous cpu. Hence issuing directive
'.machine ppc' (generated by gcc for generic powerpc) after '.machine e500'
(specifying at command line) disables usage of e500 specific instructions.
And compiling arch/powerpc/cpu/mpc85xx/tlb.c code throws following
assembler errors:
{standard input}: Assembler messages:
{standard input}:127: Error: unrecognized opcode: `tlbre'
{standard input}:418: Error: unrecognized opcode: `tlbre'
{standard input}:821: Error: unrecognized opcode: `msync'
{standard input}:821: Error: unrecognized opcode: `tlbwe'
{standard input}:884: Error: unrecognized opcode: `tlbsx'
This issue was already hit by Debian people and is reported in bug tracker:
https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1003490
Calling gcc with -mcpu=8540 flag fixes this issue because -mcpu=8540 tells
gcc to compile code for e500 core/cpu (overwriting gcc's default cpu) and
does not put '.machine ppc' directive into assembly anymore.
Also if gcc is invoked with -mpcu=8540 then it pass -me500 flag to GNU AS.
So it is needed to specify -Wa,-me500 flag because it is implicitly added.
Fix this issue properly by specifying correct -mcpu compiler flag for all
supported powerpc cores in U-Boot mpc85xx platform, which are: e500v1,
e500v2, e500mc, e5500 and e6500. For specifying e500v1 and e500v2 cores,
gcc has unintuitive -mcpu=8540 flag name, for other cores -mcpu matches
core name.
Older gcc versions (up to gcc 8) had also -mcpu=8548 flag for specifying
e500v2 cores but the only difference between -mcpu=8540 and -mcpu=8548 was
HW support of double precision floating point. So it is fine to use
-mcpu=8540 for both e500v1 and e500v2 cores as u-boot does not use floating
point arithmetic.
Note that U-Boot's CONFIG_E500 option is set also for other cpus, not only
for e500v1 and e500v2. So do not check for CONFIG_E500 and rather set e500
as last fallback value when no other mpc85xx cpu matches.
Signed-off-by: Pali Rohár
---
arch/powerpc/cpu/mpc85xx/config.mk | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc85xx/config.mk
b/arch/powerpc/cpu/mpc85xx/config.mk
index 7a1d81cf2d76..b6b5d2053aea 100644
--- a/arch/powerpc/cpu/mpc85xx/config.mk
+++ b/arch/powerpc/cpu/mpc85xx/config.mk
@@ -3,7 +3,7 @@
# (C) Copyright 2002,2003 Motorola Inc.
# Xianghua Xiao, x.x...@motorola.com
-PLATFORM_CPPFLAGS += -Wa,-me500 -msoft-float -mno-string
+PLATFORM_CPPFLAGS += -msoft-float -mno-string
PLATFORM_RELFLAGS += -msingle-pic-base -fno-jump-tables
# -mspe=yes is needed to have -mno-spe accepted by a buggy GCC;
@@ -11,3 +11,13 @@ PLATFORM_RELFLAGS += -msingle-pic-base -fno-jump-tables
# http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html
PLATFORM_CPPFLAGS += $(call cc-option,-mspe=yes) \
$(call cc-option,-mno-spe)
+
+ifdef CONFIG_E6500
+PLATFORM_CPPFLAGS += -mcpu=e6500
+else ifdef CONFIG_E5500
+PLATFORM_CPPFLAGS += -mcpu=e5500
+else ifdef CONFIG_E500MC
+PLATFORM_CPPFLAGS += -mcpu=e500mc
+else
+PLATFORM_CPPFLAGS += -mcpu=8540
+endif
--
2.20.1
[PATCH] arm: socfpga: Add function to get Board ID
From: Yau Wai Gan
Board ID is defined in JTAG User Code register. This function retrieves the
Board ID and perform validation on it.
Signed-off-by: Yau Wai Gan
Signed-off-by: Jit Loon Lim
---
arch/arm/mach-socfpga/board.c | 39 +++
.../mach-socfpga/include/mach/mailbox_s10.h | 1 +
2 files changed, 40 insertions(+)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 914a44970d..11abf864f5 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -7,9 +7,11 @@
#include
#include
+#include
#include
#include
#include
+#include
#include
#include
#include
@@ -23,6 +25,8 @@
DECLARE_GLOBAL_DATA_PTR;
+#define DEFAULT_JTAG_USERCODE 0x
+
void s_init(void) {
#ifndef CONFIG_ARM64
/*
@@ -92,6 +96,41 @@ int g_dnl_board_usb_cable_connected(void)
}
#endif
+u8 socfpga_get_board_id(void)
+{
+ u8 board_id = 0;
+ u32 jtag_usercode;
+ int err;
+
+#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)
+ err = smc_get_usercode(_usercode);
+#else
+ u32 resp_len = 1;
+
+ err = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_GET_USERCODE, MBOX_CMD_DIRECT,
0,
+ NULL, 0, _len, _usercode);
+#endif
+
+ if (err) {
+ puts("Fail to read JTAG Usercode. Default Board ID to 0\n");
+ return board_id;
+ }
+
+ debug("Valid JTAG Usercode: %u\n", jtag_usercode);
+
+ if (jtag_usercode == DEFAULT_JTAG_USERCODE) {
+ debug("JTAG Usercode is not set. Default Board ID to 0\n");
+ } else if (jtag_usercode >= 0 && jtag_usercode <= 255) {
+ board_id = jtag_usercode;
+ debug("Valid JTAG Usercode. Set Board ID to %u\n", board_id);
+ } else {
+ puts("Board ID is not in range 0 to 255\n");
+ }
+
+ return board_id;
+}
+
+
#ifdef CONFIG_SPL_BUILD
__weak int board_fit_config_name_match(const char *name)
{
diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
index fbaf11597e..2cc7c89044 100644
--- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -119,6 +119,7 @@ enum ALT_SDM_MBOX_RESP_CODE {
#define MBOX_RECONFIG_DATA 8
#define MBOX_RECONFIG_STATUS 9
#define MBOX_VAB_SRC_CERT 11
+#define MBOX_GET_USERCODE 19
#define MBOX_QSPI_OPEN 50
#define MBOX_QSPI_CLOSE51
#define MBOX_QSPI_DIRECT 59
--
2.26.2
Re: [u-boot][PATCH 00/14] rawnand: omap_gpmc: driver model support
Hi Roger,
On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros wrote:
>
> Hi Michael,
>
> On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
> > Hi Roger
> >
> > On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros wrote:
> >>
> >> Hi,
> >>
> >> On 11/10/2022 14:49, Roger Quadros wrote:
> >>> Hi,
> >>>
> >>> This series adds driver model support for rawnand: omap_gpmc
> >>> and omap_elm drivers.
> >>>
> >>> This will enable the driver to be used on K2/K3 platforms as well.
> >>
> >> Any comments on patches 5 and later? Thanks
> >>
> >
> > We will try to close this week.
>
> Could you please give your comments on the last few patches. Thanks!
>
> cheers,
> -roger
>
> >
> > Michael
> >
> >>
> >> cheers,
> >> -roger
> >>
> >>>
> >>> cheers,
> >>> -roger
> >>>
> >>> Roger Quadros (14):
> >>> mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
> >>> mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
> >>> mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
> >>> mtd: rawnand: omap_gpmc: Optimize NAND reads
> >>> mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction
> >>> mtd: rawnand: nand_base: Allow base driver to be used in SPL without
> >>> nand_bbt
> >>> mtd: rawnand: nand_spl_loaders: Fix cast type build warning
> >>> mtd: rawnand: omap_gpmc: Reduce .bss usage
> >>> dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation
> >>> mtd: rawnand: omap_gpmc: support u-boot driver model
> >>> mtd: rawnand: omap_gpmc: Add SPL NAND support
> >>> mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC
> >>> dt-bindings: mtd: Add ti,elm DT binding documentation
> >>> mtd: rawnand: omap_elm: u-boot driver model support
> >>>
> >>> doc/device-tree-bindings/mtd/ti,elm.yaml | 72 +++
> >>> .../mtd/ti,gpmc-nand.yaml | 129 +
> >>> drivers/mtd/nand/raw/Kconfig | 11 +-
> >>> drivers/mtd/nand/raw/Makefile | 2 +-
> >>> drivers/mtd/nand/raw/nand_base.c | 18 +-
> >>> drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +-
> >>> drivers/mtd/nand/raw/omap_elm.c | 33 +-
> >>> .../mtd => drivers/mtd/nand/raw}/omap_elm.h | 6 +
> >>> drivers/mtd/nand/raw/omap_gpmc.c | 500 +-
> >>> 9 files changed, 637 insertions(+), 136 deletions(-)
> >>> create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml
> >>> create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
> >>> rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
> >>>
> >
> >
> >
I tried to merge your whole series but after the second fix and the
third time the CI/CD pipeline failed
I thought it's better you fix the problems. So, I only accepted some
of the first few patches in the series:
01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads
07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning
08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage
For the others, please fix them to run the tests successfully.
Thanks and regards,
Dario
--
Dario Binacchi
Embedded Linux Developer
dario.binac...@amarulasolutions.com
__
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
i...@amarulasolutions.com
www.amarulasolutions.com
