RE: [PATCH 1/2] Revert "mmc: s5p_sdhci: unset the SDHCI_QUIRK_BROKEN_R1B"
Hi Henrik,
> -Original Message-
> From: Henrik Grimler
> Sent: Saturday, March 11, 2023 7:32 PM
> To: Jaehoon Chung
> Cc: jo...@diskos.nl; peng@nxp.com; andy...@sony.com; s...@chromium.org;
> u-boot@lists.denx.de;
> ~postmarketos/upstream...@lists.sr.ht
> Subject: Re: [PATCH 1/2] Revert "mmc: s5p_sdhci: unset the
> SDHCI_QUIRK_BROKEN_R1B"
>
> Hi Jaehoon,
>
> On Fri, Feb 10, 2023 at 09:00:33AM +0900, Jaehoon Chung wrote:
> > Hi,
> >
> > > -Original Message-
> > > From: U-Boot On Behalf Of Henrik Grimler
> > > Sent: Thursday, February 9, 2023 4:04 AM
> > > To: jo...@diskos.nl; jh80.ch...@gmail.com; andy...@sony.com;
> > > s...@chromium.org;
> > > m.szyprow...@samsung.com; u-boot@lists.denx.de;
> > > ~postmarketos/upstream...@lists.sr.ht
> > > Cc: Henrik Grimler
> > > Subject: [PATCH 1/2] Revert "mmc: s5p_sdhci: unset the
> > > SDHCI_QUIRK_BROKEN_R1B"
> > >
> > > This reverts commit a034ec06ff1d558bbe11d5ee05edbb4de3ee2215.
> > >
> > > Commit 4a3ea75de4c5 ("Revert "mmc: sdhci: set to INT_DATA_END when
> > > there are data"") reverted the alternative fix that was added for
> > > Exynos 4 devices, causing an error when trying to boot from an sdcard:
> > >
> > > <...>
> > > Loading Environment from MMC... sdhci_send_command: Timeout for
> > > status update!
> > > mmc fail to send stop cmd
> > > <...>
> >
> > Thanks for sharing issue.
> >
> > I will check this on Exynos Board. Frankly, I hope not to re-add QUIRK.
> > Because it was verified that it was working fine without
> > SDHCI_QUIKR_BROKEN_RIB.
>
> Just wondering if you have had an opportunity to test this on any of
> your devices? You can find v2 here, though this patch had no changes:
> https://protect2.fireeye.com/v1/url?k=f02940b0-91a25586-f028cbff-74fe485fffe0-
> 524f6754708289dd=1=39932d75-a824-41c5-a3b2-
> d9b467bd34a8=https%3A%2F%2Flists.denx.de%2Fpipermail%2Fu-boot%2F2023-February%2F508928.html
I have found what you faced.
U-Boot 2023.04-rc3-00265-gbcf343146ff3-dirty (Mar 13 2023 - 14:35:43 +0900)
CPU: Exynos4412 @ 1 GHz
Model: Odroid based on Exynos4412
Type: u3
DRAM: 2 GiB
Core: 101 devices, 12 uclasses, devicetree: separate
LDO20@VDDQ_EMMC_1.8V: set 180 uV; enabling
LDO22@VDDQ_EMMC_2.8V: set 280 uV; enabling
LDO21@TFLASH_2.8V: set 280 uV; enabling
MMC: SAMSUNG SDHCI: 2, EXYNOS DWMMC: 0
Loading Environment from MMC... sdhci_send_command: Timeout for status update!
mmc fail to send stop cmd
sdhci_send_command: Timeout for status update!
mmc fail to send stop cmd
** fs_devread read error - block
sdhci_send_command: Timeout for status update!
mmc fail to send stop cmd
*** Warning - !read failed, using default environment
I'm checking yours on my u3 board. I will reply today. Sorry for too late.
Best Regards,
Jaehoon Chung
>
> > Best Regards,
> > Jaehoon Chung
>
> Best regards,
> Henrik Grimler
>
> > >
> > > Re-add the quirk to allow booting from sdcards again.
> > >
> > > Signed-off-by: Henrik Grimler
> > > ---
> > > drivers/mmc/s5p_sdhci.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c
> > > index dee84263c3fd..3b74feae68c7 100644
> > > --- a/drivers/mmc/s5p_sdhci.c
> > > +++ b/drivers/mmc/s5p_sdhci.c
> > > @@ -90,7 +90,7 @@ static int s5p_sdhci_core_init(struct sdhci_host *host)
> > > host->name = S5P_NAME;
> > >
> > > host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
> > > - SDHCI_QUIRK_32BIT_DMA_ADDR |
> > > + SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
> > > SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8;
> > > host->max_clk = 5200;
> > > host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
> > > --
> > > 2.30.2
> >
> >
RE: [GIT PULL] Please pull u-boot-mmc master
Hi, > -Original Message- > From: Tom Rini > Sent: Saturday, March 11, 2023 3:09 AM > To: Marek Vasut > Cc: Jaehoon Chung ; U-Boot Mailing List > ; Loic Poulain > ; Stefan Roese ; Jae hoon Chung > > Subject: Re: [GIT PULL] Please pull u-boot-mmc master > > On Fri, Mar 10, 2023 at 05:28:40PM +0100, Marek Vasut wrote: > > On 3/10/23 16:44, Tom Rini wrote: > > > On Fri, Mar 10, 2023 at 01:22:15PM +0900, Jaehoon Chung wrote: > > > > Dear Tom, > > > > > > > > > > > > Please pull u-boot-mmc master into u-boot master branch. > > > > If there is any problem, let me know, plz. > > > > > > At this point in the cycle I have to ask, are these all fixes of > > > specific issues? If not, I'd rather take this to -next. Thanks! > > > > The stuff from me can easily go into next. > > And on that note, I have bad news. This commit: > Author: Marek Vasut > Date: Thu Jan 5 15:28:31 2023 +0100 > > spl: mmc: Pass eMMC HW partition 7 through > > leads to my pine64_plus board hanging in SPL with: > U-Boot SPL 2023.04-rc3-00084-g85f29eb025cb (Mar 10 2023 - 13:05:36 -0500) > DRAM: 1024 MiB > Trying to boot from MMC1 > > When trying to boot from SD card. If you don't have something there that > you can get to fail, let me know and I'll get you access to my lab. I will check again this. Thanks! Best Regards, Jaehoon Chung > > -- > Tom
Re: [RFC PATCH 2/2] kconfig: U-Boot additions
On Sun, Mar 12, 2023 at 3:35 AM Simon Glass wrote: > > Bring in some U-Boot additions > > This seems to build OK, but 'make menuconfig' does not build the > scripts/kconfig/mconf utility. > > Signed-off-by: Simon Glass > --- > > scripts/kconfig/Makefile | 10 ++ > 1 file changed, 10 insertions(+) > Tested building qemu-x86 and qemu-riscv_spl, and boot on QEMU Tested-by: Bin Meng
Re: [RFC PATCH 1/2] kconfig: Bring in from Linux v6.2
On Sun, Mar 12, 2023 at 8:05 AM Simon Glass wrote:
>
> Bring in this code wholesale, replacing the old U-Boot code.
>
> Signed-off-by: Simon Glass
> ---
>
> scripts/kconfig/.gitignore| 20 +-
> scripts/kconfig/Makefile | 211 ++--
> scripts/kconfig/conf.c| 499 +---
> scripts/kconfig/confdata.c| 1074
> scripts/kconfig/expr.c| 30 +-
> scripts/kconfig/expr.h| 17 +-
> scripts/kconfig/gconf-cfg.sh | 15 +-
> scripts/kconfig/gconf.c | 47 +-
> scripts/kconfig/images.c | 34 +-
> scripts/kconfig/images.h | 33 +
> scripts/kconfig/internal.h|9 +
> scripts/kconfig/kconf_id.c| 52 -
> scripts/kconfig/{zconf.l => lexer.l} | 247 ++--
> scripts/kconfig/list.h|2 +-
> scripts/kconfig/lkc.h | 91 +-
> scripts/kconfig/lkc_proto.h | 22 +-
> scripts/kconfig/lxdialog/.gitignore |4 -
> scripts/kconfig/lxdialog/BIG.FAT.WARNING |2 +-
> scripts/kconfig/lxdialog/inputbox.c |3 +-
> scripts/kconfig/lxdialog/util.c |4 +-
> scripts/kconfig/mconf-cfg.sh | 36 +-
> scripts/kconfig/mconf.c | 42 +-
> scripts/kconfig/menu.c| 263 ++--
> scripts/kconfig/merge_config.sh | 75 +-
> scripts/kconfig/nconf-cfg.sh | 32 +-
> scripts/kconfig/nconf.c | 89 +-
> scripts/kconfig/nconf.gui.c | 292 ++---
> scripts/kconfig/nconf.h | 56 +-
> scripts/kconfig/{zconf.y => parser.y} | 336 ++---
> scripts/kconfig/preprocess.c | 12 +-
> scripts/kconfig/qconf-cfg.sh | 29 +-
> scripts/kconfig/qconf.cc | 1106 +
> scripts/kconfig/qconf.h | 163 +--
> scripts/kconfig/streamline_config.pl | 98 +-
> scripts/kconfig/symbol.c | 106 +-
> scripts/kconfig/tests/auto_submenu/Kconfig|2 +
> .../kconfig/tests/auto_submenu/__init__.py|1 +
> scripts/kconfig/tests/choice/Kconfig |4 +-
> scripts/kconfig/tests/choice/__init__.py |1 +
> .../tests/choice_value_with_m_dep/Kconfig |4 +-
> .../tests/choice_value_with_m_dep/__init__.py |1 +
> scripts/kconfig/tests/conftest.py |4 +
> .../tests/err_recursive_dep/expected_stderr | 14 +-
> .../kconfig/tests/err_recursive_inc/Kconfig |1 +
> .../tests/err_recursive_inc/Kconfig.inc1 |1 +
> .../tests/err_recursive_inc/Kconfig.inc2 |1 +
> .../tests/err_recursive_inc/Kconfig.inc3 |1 +
> .../tests/err_recursive_inc/__init__.py |1 +
> .../tests/err_recursive_inc/expected_stderr |6 +-
> scripts/kconfig/tests/inter_choice/Kconfig|4 +-
> .../kconfig/tests/inter_choice/__init__.py|1 +
> .../kconfig/tests/new_choice_with_dep/Kconfig |2 +
> .../tests/new_choice_with_dep/__init__.py |1 +
> .../tests/no_write_if_dep_unmet/Kconfig |2 +
> .../tests/no_write_if_dep_unmet/__init__.py |1 +
> .../tests/preprocess/builtin_func/Kconfig | 27 +
> .../tests/preprocess/builtin_func/__init__.py |9 +
> .../preprocess/builtin_func/expected_stderr |5 +
> .../preprocess/builtin_func/expected_stdout |1 +
> .../preprocess/circular_expansion/Kconfig |5 +
> .../preprocess/circular_expansion/__init__.py | 11 +
> .../circular_expansion/expected_stderr|1 +
> .../kconfig/tests/preprocess/escape/Kconfig | 44 +
> .../tests/preprocess/escape/__init__.py |8 +
> .../tests/preprocess/escape/expected_stderr | 10 +
> .../kconfig/tests/preprocess/variable/Kconfig | 53 +
> .../tests/preprocess/variable/__init__.py |8 +
> .../tests/preprocess/variable/expected_stderr |9 +
> .../kconfig/tests/rand_nested_choice/Kconfig | 33 -
> .../tests/rand_nested_choice/__init__.py | 16 -
> .../tests/rand_nested_choice/expected_stdout0 |2 -
> .../tests/rand_nested_choice/expected_stdout1 |4 -
> .../tests/rand_nested_choice/expected_stdout2 |5 -
> scripts/kconfig/util.c|5 +-
> 74 files changed, 2786 insertions(+), 2674 deletions(-)
> create mode 100644 scripts/kconfig/images.h
> create mode 100644 scripts/kconfig/internal.h
> delete mode 100644 scripts/kconfig/kconf_id.c
> rename scripts/kconfig/{zconf.l => lexer.l} (67%)
> delete mode 100644 scripts/kconfig/lxdialog/.gitignore
> mode change 100644 => 100755 scripts/kconfig/nconf-cfg.sh
> rename scripts/kconfig/{zconf.y => parser.y} (70%)
> create mode 100644
[PATCH] arm: kirkwood: Enable Debug UART for Zyxel NSA310S
It's useful to enable Debug UART for future DM Serial regression tests for Kirkwood boards. Also, see background discussion in this thread: https://lists.denx.de/pipermail/u-boot/2023-March/512010.html Signed-off-by: Tony Dinh --- configs/nsa310s_defconfig | 4 1 file changed, 4 insertions(+) diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index 76839e62dd..b936ae1b25 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -15,8 +15,11 @@ CONFIG_ENV_SIZE=0x2 CONFIG_ENV_OFFSET=0xE CONFIG_DEFAULT_DEVICE_TREE="kirkwood-nsa310s" CONFIG_SYS_PROMPT="NSA310s> " +CONFIG_DEBUG_UART_BASE=0xf1012000 +CONFIG_DEBUG_UART_CLOCK=16667 CONFIG_IDENT_STRING="\nZyXEL NSA310S/320S 1/2-Bay Power Media Server" CONFIG_SYS_LOAD_ADDR=0x80 +CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y @@ -50,6 +53,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_PHY_MARVELL=y CONFIG_MVGBE=y CONFIG_MII=y +CONFIG_DEBUG_UART_SHIFT=2 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_UBIFS_SILENCE_MSG=y -- 2.30.2
[PATCH 11/13] dm: Emit the arch_cpu_init_dm() even only before relocation
The original function was only called once, before relocation. The new
one is called again after relocation. This was not the intend of the
original call. Fix this by renaming and updating the calling logic.
With this, chromebook_link64 makes it through SPL.
Fixes: 7fe32b3442f ("event: Convert arch_cpu_init_dm() to")
Signed-off-by: Simon Glass
---
arch/arm/mach-imx/imx8/cpu.c| 2 +-
arch/arm/mach-imx/imx8m/soc.c | 2 +-
arch/arm/mach-imx/imx8ulp/soc.c | 2 +-
arch/arm/mach-imx/imx9/soc.c| 2 +-
arch/arm/mach-omap2/am33xx/board.c | 2 +-
arch/arm/mach-omap2/hwinit-common.c | 2 +-
arch/mips/mach-pic32/cpu.c | 2 +-
arch/nios2/cpu/cpu.c| 2 +-
arch/riscv/cpu/cpu.c| 2 +-
arch/x86/cpu/baytrail/cpu.c | 2 +-
arch/x86/cpu/broadwell/cpu.c| 2 +-
arch/x86/cpu/ivybridge/cpu.c| 2 +-
arch/x86/cpu/quark/quark.c | 2 +-
arch/x86/lib/fsp2/fsp_init.c| 2 +-
doc/develop/event.rst | 6 +++---
drivers/core/root.c | 4 ++--
drivers/cpu/microblaze_cpu.c| 2 +-
include/event.h | 2 +-
18 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index be1f4edded10..99772f68c32b 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -89,7 +89,7 @@ static int imx8_init_mu(void *ctx, struct event *event)
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT, imx8_init_mu);
+EVENT_SPY(EVT_DM_POST_INIT_F, imx8_init_mu);
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index df865e997d38..903620ad6a83 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -549,7 +549,7 @@ static int imx8m_check_clock(void *ctx, struct event *event)
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT, imx8m_check_clock);
+EVENT_SPY(EVT_DM_POST_INIT_F, imx8m_check_clock);
static void imx8m_setup_snvs(void)
{
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 5d95fb89a61c..70142cbb0f4b 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -685,7 +685,7 @@ static int imx8ulp_check_mu(void *ctx, struct event *event)
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT, imx8ulp_check_mu);
+EVENT_SPY(EVT_DM_POST_INIT_F, imx8ulp_check_mu);
#if defined(CONFIG_SPL_BUILD)
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index a16e22ea6bbf..252663a9eec2 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -262,7 +262,7 @@ int imx9_probe_mu(void *ctx, struct event *event)
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT, imx9_probe_mu);
+EVENT_SPY(EVT_DM_POST_INIT_F, imx9_probe_mu);
int timer_init(void)
{
diff --git a/arch/arm/mach-omap2/am33xx/board.c
b/arch/arm/mach-omap2/am33xx/board.c
index a52d04d85c8a..ecc0a592e993 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -535,4 +535,4 @@ static int am33xx_dm_post_init(void *ctx, struct event
*event)
#endif
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT, am33xx_dm_post_init);
+EVENT_SPY(EVT_DM_POST_INIT_F, am33xx_dm_post_init);
diff --git a/arch/arm/mach-omap2/hwinit-common.c
b/arch/arm/mach-omap2/hwinit-common.c
index c4a8eabc3ebe..771533394bcd 100644
--- a/arch/arm/mach-omap2/hwinit-common.c
+++ b/arch/arm/mach-omap2/hwinit-common.c
@@ -246,7 +246,7 @@ static int omap2_system_init(void *ctx, struct event *event)
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT, omap2_system_init);
+EVENT_SPY(EVT_DM_POST_INIT_F, omap2_system_init);
/*
* Routine: wait_for_command_complete
diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c
index de449e3c6a20..ec3c2505313c 100644
--- a/arch/mips/mach-pic32/cpu.c
+++ b/arch/mips/mach-pic32/cpu.c
@@ -102,7 +102,7 @@ static int pic32_flash_prefetch(void *ctx, struct event
*event)
prefetch_init();
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT, pic32_flash_prefetch);
+EVENT_SPY(EVT_DM_POST_INIT_F, pic32_flash_prefetch);
/* Un-gate DDR2 modules (gated by default) */
static void ddr2_pmd_ungate(void)
diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c
index 85544503a5ee..da167f4b29e9 100644
--- a/arch/nios2/cpu/cpu.c
+++ b/arch/nios2/cpu/cpu.c
@@ -80,7 +80,7 @@ static int nios_cpu_setup(void *ctx, struct event *event)
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT, nios_cpu_setup);
+EVENT_SPY(EVT_DM_POST_INIT_F, nios_cpu_setup);
static int altera_nios2_get_desc(const struct udevice *dev, char *buf,
int size)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index e1ed4ec01d04..ecfb1fb08c4b 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -145,7 +145,7 @@ int
[PATCH 12/13] x86: Allow listing MTRRs in SPL
Move MTRR-listing code into a common file so it can be used from SPL.
Update the 'mtrr' command to call it.
Use this in SPL just before adjusting the MTRRs, so we can see the state
set up by the board. Only show it when debug is enabled.
Signed-off-by: Simon Glass
---
arch/x86/cpu/mtrr.c | 61 +
arch/x86/include/asm/mtrr.h | 20
arch/x86/lib/spl.c | 7 +
cmd/x86/mtrr.c | 60 +++-
4 files changed, 92 insertions(+), 56 deletions(-)
diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c
index e69dfb552b16..1d3beee33555 100644
--- a/arch/x86/cpu/mtrr.c
+++ b/arch/x86/cpu/mtrr.c
@@ -30,6 +30,16 @@
DECLARE_GLOBAL_DATA_PTR;
+const char *const mtrr_type_name[MTRR_TYPE_COUNT] = {
+ "Uncacheable",
+ "Combine",
+ "2",
+ "3",
+ "Through",
+ "Protect",
+ "Back",
+};
+
/* Prepare to adjust MTRRs */
void mtrr_open(struct mtrr_state *state, bool do_caches)
{
@@ -320,3 +330,54 @@ int mtrr_set(int cpu_select, int reg, u64 base, u64 mask)
return mtrr_start_op(cpu_select, );
}
+
+static void read_mtrrs_(void *arg)
+{
+ struct mtrr_info *info = arg;
+
+ mtrr_read_all(info);
+}
+
+int mtrr_list(int reg_count, int cpu_select)
+{
+ struct mtrr_info info;
+ int ret;
+ int i;
+
+ printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||",
+ "Mask ||", "Size ||");
+ memset(, '\0', sizeof(info));
+ ret = mp_run_on_cpus(cpu_select, read_mtrrs_, );
+ if (ret)
+ return log_msg_ret("run", ret);
+ for (i = 0; i < reg_count; i++) {
+ const char *type = "Invalid";
+ uint64_t base, mask, size;
+ bool valid;
+
+ base = info.mtrr[i].base;
+ mask = info.mtrr[i].mask;
+ size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1);
+ size |= (1 << 12) - 1;
+ size += 1;
+ valid = mask & MTRR_PHYS_MASK_VALID;
+ type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK];
+ printf("%d %-5s %-12s %016llx %016llx %016llx\n", i,
+ valid ? "Y" : "N", type, base & ~MTRR_BASE_TYPE_MASK,
+ mask & ~MTRR_PHYS_MASK_VALID, size);
+ }
+
+ return 0;
+}
+
+int mtrr_get_type_by_name(const char *typename)
+{
+ int i;
+
+ for (i = 0; i < MTRR_TYPE_COUNT; i++) {
+ if (*typename == *mtrr_type_name[i])
+ return i;
+ }
+
+ return -EINVAL;
+};
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
index ca2edc7878f7..2e995f540616 100644
--- a/arch/x86/include/asm/mtrr.h
+++ b/arch/x86/include/asm/mtrr.h
@@ -190,6 +190,26 @@ int mtrr_set(int cpu_select, int reg, u64 base, u64 mask);
*/
int mtrr_get_var_count(void);
+/**
+ * mtrr_list() - List the MTRRs
+ *
+ * Shows a list of all the MTRRs including their values
+ *
+ * @reg_count: Number of registers to show. You can use mtrr_get_var_count()
for
+ * this
+ * @cpu_select: CPU to use. Use MP_SELECT_BSP for the boot CPU
+ * Returns: 0 if OK, -ve if the CPU was not found
+ */
+int mtrr_list(int reg_count, int cpu_select);
+
+/**
+ * mtrr_get_type_by_name() - Get the type of an MTRR given its type name
+ *
+ * @typename: Name to check
+ * Returns: MTRR type (MTRR_TYPE_...) or -EINVAL if invalid
+ */
+int mtrr_get_type_by_name(const char *typename);
+
#endif
#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index eb0af219ae29..0f2319ccc212 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -139,6 +140,12 @@ static int x86_spl_init(void)
arch_setup_gd(gd->new_gd);
gd->start_addr_sp = (ulong)ptr;
+ if (_LOG_DEBUG) {
+ ret = mtrr_list(mtrr_get_var_count(), MP_SELECT_BSP);
+ if (ret)
+ printf("mtrr_list failed\n");
+ }
+
/* Cache the SPI flash. Otherwise copying the code to RAM takes ages */
ret = mtrr_add_request(MTRR_TYPE_WRBACK,
(1ULL << 32) - CONFIG_XIP_ROM_SIZE,
diff --git a/cmd/x86/mtrr.c b/cmd/x86/mtrr.c
index b213a942fde4..c1880c7806e6 100644
--- a/cmd/x86/mtrr.c
+++ b/cmd/x86/mtrr.c
@@ -10,71 +10,19 @@
#include
#include
-static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = {
- "Uncacheable",
- "Combine",
- "2",
- "3",
- "Through",
- "Protect",
- "Back",
-};
-
-static void read_mtrrs(void *arg)
-{
- struct mtrr_info *info = arg;
-
- mtrr_read_all(info);
-}
-
-static int do_mtrr_list(int reg_count, int cpu_select)
-{
- struct mtrr_info info;
- int ret;
- int i;
-
- printf("Reg Valid Write-type
[PATCH 13/13] x86: Add on to existing MTRRs in SPL
We don't actually set up all of these registers in SPL, so using
mtrr_commit() with erase some. Use mtrr_set_next_var() instead.
Signed-off-by: Simon Glass
---
arch/x86/lib/spl.c | 10 +-
configs/chromebook_link64_defconfig | 2 ++
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index 0f2319ccc212..88d7e1424174 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -147,14 +147,14 @@ static int x86_spl_init(void)
}
/* Cache the SPI flash. Otherwise copying the code to RAM takes ages */
- ret = mtrr_add_request(MTRR_TYPE_WRBACK,
+ mtrr_set_next_var(MTRR_TYPE_WRBACK,
(1ULL << 32) - CONFIG_XIP_ROM_SIZE,
CONFIG_XIP_ROM_SIZE);
- if (ret) {
- debug("%s: SPI cache setup failed (err=%d)\n", __func__, ret);
- return ret;
+ if (_LOG_DEBUG) {
+ ret = mtrr_list(mtrr_get_var_count(), MP_SELECT_BSP);
+ if (ret)
+ printf("mtrr_list failed\n");
}
- mtrr_commit(true);
# else
ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, );
if (ret)
diff --git a/configs/chromebook_link64_defconfig
b/configs/chromebook_link64_defconfig
index 8c75d654290b..192cbbecbe0e 100644
--- a/configs/chromebook_link64_defconfig
+++ b/configs/chromebook_link64_defconfig
@@ -69,6 +69,7 @@ CONFIG_TFTP_TSIZE=y
CONFIG_USE_ROOTPATH=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
# CONFIG_ACPIGEN is not set
CONFIG_LBA48=y
CONFIG_SYS_64BIT_LBA=y
@@ -88,6 +89,7 @@ CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_VIDEO_IVYBRIDGE_IGD=y
CONFIG_CONSOLE_SCROLL_LINES=5
+# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
# CONFIG_GZIP is not set
--
2.40.0.rc1.284.g88254d51c5-goog
[PATCH 10/13] sf: Rename spi-nor-tiny functions
The 'tiny' SPI nor functions have the same name as their big brothers,
which can be confusing. Use different names so it is clear which
version is in the image.
Signed-off-by: Simon Glass
---
drivers/mtd/spi/spi-nor-tiny.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c
index 68152ce3b4b9..7aa24e129f96 100644
--- a/drivers/mtd/spi/spi-nor-tiny.c
+++ b/drivers/mtd/spi/spi-nor-tiny.c
@@ -361,7 +361,7 @@ static int spi_nor_wait_till_ready(struct spi_nor *nor)
* Erase an address range on the nor chip. The address range may extend
* one or more erase sectors. Return an error is there is a problem erasing.
*/
-static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
+static int spi_nor_erase_tiny(struct mtd_info *mtd, struct erase_info *instr)
{
return -ENOTSUPP;
}
@@ -390,8 +390,8 @@ static const struct flash_info *spi_nor_read_id(struct
spi_nor *nor)
return ERR_PTR(-EMEDIUMTYPE);
}
-static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
- size_t *retlen, u_char *buf)
+static int spi_nor_read_tiny(struct mtd_info *mtd, loff_t from, size_t len,
+size_t *retlen, u_char *buf)
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
int ret;
@@ -426,8 +426,8 @@ read_err:
* FLASH_PAGESIZE chunks. The address range may be any size provided
* it is within the physical boundaries.
*/
-static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
-size_t *retlen, const u_char *buf)
+static int spi_nor_write_tiny(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, const u_char *buf)
{
return -ENOTSUPP;
}
@@ -741,9 +741,9 @@ int spi_nor_scan(struct spi_nor *nor)
mtd->writesize = 1;
mtd->flags = MTD_CAP_NORFLASH;
mtd->size = info->sector_size * info->n_sectors;
- mtd->_erase = spi_nor_erase;
- mtd->_read = spi_nor_read;
- mtd->_write = spi_nor_write;
+ mtd->_erase = spi_nor_erase_tiny;
+ mtd->_read = spi_nor_read_tiny;
+ mtd->_write = spi_nor_write_tiny;
nor->size = mtd->size;
--
2.40.0.rc1.284.g88254d51c5-goog
[PATCH 09/13] sf: Guard against zero erasesize
With tiny SPI flash the erasesize is 0 which can cause a divide-by-zero
error. Check for this and returns a proper error instead.
Signed-off-by: Simon Glass
---
drivers/mtd/spi/sf_probe.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index e192f97efdc4..de6516f1065b 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -189,7 +189,8 @@ static int spi_flash_std_erase(struct udevice *dev, u32
offset, size_t len)
struct mtd_info *mtd = >mtd;
struct erase_info instr;
- if (offset % mtd->erasesize || len % mtd->erasesize) {
+ if (!mtd->erasesize ||
+ (offset % mtd->erasesize || len % mtd->erasesize)) {
debug("SF: Erase offset/length not multiple of erase size\n");
return -EINVAL;
}
--
2.40.0.rc1.284.g88254d51c5-goog
[PATCH 04/13] x86: ivybridge: Ensure LPC is available for GPIO base
The bd82x6x_get_gpio_base() does not work if the LPC is not set up.
Probe it early to avoid this problem.
In chromebook_link64 this propblem shows up as an inability to read
the GPIO straps for the memory type.
Signed-off-by: Simon Glass
---
arch/x86/cpu/ivybridge/bd82x6x.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 89312a863499..417290f559e9 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -31,7 +31,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define RCBA_AUDIO_CONFIG_HDA BIT(31)
#define RCBA_AUDIO_CONFIG_MASK 0xfe
-#ifndef CONFIG_HAVE_FSP
static int pch_revision_id = -1;
static int pch_type = -1;
@@ -162,15 +161,19 @@ void pch_iobp_update(struct udevice *dev, u32 address,
u32 andvalue,
static int bd82x6x_probe(struct udevice *dev)
{
- if (!(gd->flags & GD_FLG_RELOC))
- return 0;
+ /* make sure the LPC is inited since it provides the gpio base */
+ uclass_first_device(UCLASS_LPC, );
+
+ if (!IS_ENABLED(CONFIG_HAVE_FSP)) {
+ if (!(gd->flags & GD_FLG_RELOC))
+ return 0;
- /* Cause the SATA device to do its init */
- uclass_first_device(UCLASS_AHCI, );
+ /* Cause the SATA device to do its init */
+ uclass_first_device(UCLASS_AHCI, );
+ }
return 0;
}
-#endif /* CONFIG_HAVE_FSP */
static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
{
@@ -269,8 +272,6 @@ U_BOOT_DRIVER(bd82x6x_drv) = {
.name = "bd82x6x",
.id = UCLASS_PCH,
.of_match = bd82x6x_ids,
-#ifndef CONFIG_HAVE_FSP
.probe = bd82x6x_probe,
-#endif
.ops= _pch_ops,
};
--
2.40.0.rc1.284.g88254d51c5-goog
[PATCH 08/13] x86: spl: Show debugging for BSS
Show the area of memory cleared for BSS, when debugging is enabled.
Signed-off-by: Simon Glass
---
arch/x86/lib/spl.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index bdf57ef7b5bd..eb0af219ae29 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -117,7 +117,9 @@ static int x86_spl_init(void)
}
#ifndef CONFIG_SYS_COREBOOT
- memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
+ debug("BSS clear from %lx to %lx len %lx\n", (ulong)&__bss_start,
+ (ulong)&__bss_end, (ulong)&__bss_end - (ulong)&__bss_start);
+ memset(&__bss_start, '\0', (ulong)&__bss_end - (ulong)&__bss_start);
# ifndef CONFIG_TPL
/* TODO(s...@chromium.org): Consider calling cpu_init_r() here */
--
2.40.0.rc1.284.g88254d51c5-goog
[PATCH 07/13] x86: mrc: Correct SPL debug message
SPL printf() does not normally support %#x so just use %x instead. Hex is
expected in U-Boot anyway.
Signed-off-by: Simon Glass
---
arch/x86/lib/mrccache.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
index 38632e513fce..2f6f6880003e 100644
--- a/arch/x86/lib/mrccache.c
+++ b/arch/x86/lib/mrccache.c
@@ -303,7 +303,7 @@ static int mrccache_save_type(enum mrc_type_t type)
mrc = >arch.mrc[type];
if (!mrc->len)
return 0;
- log_debug("Saving %#x bytes of MRC output data type %d to SPI flash\n",
+ log_debug("Saving %x bytes of MRC output data type %d to SPI flash\n",
mrc->len, type);
ret = mrccache_get_region(type, , );
if (ret)
--
2.40.0.rc1.284.g88254d51c5-goog
[PATCH 06/13] x86: Tidy up availability of string functions
For now, just enable the fast-but-large string functions in 32-boot U-Boot proper only. Avoid using them in SPL. We cannot use then in 64-bit builds since we only have 32-bit assembly. Signed-off-by: Simon Glass --- arch/x86/include/asm/string.h | 6 +- arch/x86/lib/Makefile | 4 +++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/string.h b/arch/x86/include/asm/string.h index c15b264a5c08..5c49b0f009b7 100644 --- a/arch/x86/include/asm/string.h +++ b/arch/x86/include/asm/string.h @@ -14,7 +14,11 @@ extern char *strrchr(const char *s, int c); #undef __HAVE_ARCH_STRCHR extern char *strchr(const char *s, int c); -#ifdef CONFIG_X86_64 +/* + * Our assembly routines do not work on in 64-bit mode and we don't do a lot of + * copying in SPL, so code size is more important there. + */ +#if defined(CONFIG_SPL_BUILD) || !IS_ENABLED(CONFIG_X86_32BIT_INIT) #undef __HAVE_ARCH_MEMCPY extern void *memcpy(void *, const void *, __kernel_size_t); diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index a6f22441474b..b0612ae6dd5f 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -10,7 +10,9 @@ obj-y += bios.o obj-y += bios_asm.o obj-y += bios_interrupts.o endif -obj-y += string.o +endif +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_X86_32BIT_INIT) += string.o endif ifndef CONFIG_SPL_BUILD obj-$(CONFIG_CMD_BOOTM) += bootm.o -- 2.40.0.rc1.284.g88254d51c5-goog
[PATCH 05/13] x86: Support debug UART in 64-bit mode
The debug UART is already set up in SPL, so there is no need to do
anything here. We must provide the (empty) function though.
Signed-off-by: Simon Glass
---
arch/x86/cpu/x86_64/cpu.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
index 6a387612916c..d1c3873dd6a7 100644
--- a/arch/x86/cpu/x86_64/cpu.c
+++ b/arch/x86/cpu/x86_64/cpu.c
@@ -50,3 +50,10 @@ int x86_cpu_init_f(void)
{
return 0;
}
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+ /* this was already done in SPL */
+}
+#endif
--
2.40.0.rc1.284.g88254d51c5-goog
[PATCH 03/13] x86: samus: Drop EFI_LOADER
This adds a lot of code so that it cannot be build with the binary blobs. It is not used on this board. Drop it. Signed-off-by: Simon Glass --- configs/chromebook_samus_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index b933a2352e3f..0d20891d2bcc 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -84,3 +84,4 @@ CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y CONFIG_TPM=y # CONFIG_GZIP is not set +# CONFIG_EFI_LOADER is not set -- 2.40.0.rc1.284.g88254d51c5-goog
[PATCH 02/13] buildman: Fix CROSS_COMPILE output for sandbox
The previous attempt at fixing this broke the normal usage of the -A flag. At present, 'buildman -A sandbox' adds the path containing the toolchain. We can assume that this is in the path and we don't want to set CROSS_COMPILE=/bin/ Change this to align with what MakeEnvironment() does, but only for sandbox boards. Signed-off-by: Simon Glass --- tools/buildman/toolchain.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py index 688f2e268726..241e8e69307f 100644 --- a/tools/buildman/toolchain.py +++ b/tools/buildman/toolchain.py @@ -156,9 +156,10 @@ class Toolchain: Returns: Value of that environment variable or arguments """ -wrapper = self.GetWrapper() if which == VAR_CROSS_COMPILE: -return wrapper + os.path.join(self.path, self.cross) +wrapper = self.GetWrapper() +base = '' if self.arch == 'sandbox' else self.path +return wrapper + os.path.join(base, self.cross) elif which == VAR_PATH: return self.path elif which == VAR_ARCH: -- 2.40.0.rc1.284.g88254d51c5-goog
[PATCH 01/13] Revert "buildman: Correct CROSS_COMPILE output for sandbox"
This reverts commit bd0a548ad4a155fec29473d4cc8e135832926973. Signed-off-by: Simon Glass --- tools/buildman/toolchain.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py index 8f9130bdcdf6..688f2e268726 100644 --- a/tools/buildman/toolchain.py +++ b/tools/buildman/toolchain.py @@ -156,8 +156,9 @@ class Toolchain: Returns: Value of that environment variable or arguments """ +wrapper = self.GetWrapper() if which == VAR_CROSS_COMPILE: -return self.GetWrapper() + self.cross +return wrapper + os.path.join(self.path, self.cross) elif which == VAR_PATH: return self.path elif which == VAR_ARCH: -- 2.40.0.rc1.284.g88254d51c5-goog
Re: [PATCH v7 11/23] core: remap: fix regmap_init_mem_plat() reg size handeling
Hi Johan, On Sun, 12 Mar 2023 at 06:21, Johan Jonker wrote: > > > > On 3/11/23 02:37, Simon Glass wrote: > > Hi Johan, > > > > On Fri, 10 Mar 2023 at 08:42, Johan Jonker wrote: > >> > >> The fdt_addr_t and phys_addr_t size have been decoupled. > >> A 32bit CPU can expect 64-bit data from the device tree parser, > > > > > Sorry if you already responded and I missed it. > > > > I don't understand this line. It looks like sizeof(fdt_addr_t) is > > still 4 on 32-bit machines. So what does this actually mean? > > The original response on WHY we need it for partitions: > https://lore.kernel.org/u-boot/7256f237-4b7b-f7d7-834f-f7c3fb898...@gmail.com/T/#m81afcb203e2309c05ca97d36c63ef758cf3cef89 > > Below an explanation of the consequences. > Does this text below help? Yes, I think I was reading it more generally, but here you are just talking about partitions. Regards, Simon
Re: [PATCH v8 08/24] rockchip: timer: dw-apb-timer: use regs variable with uintptr_t size
On Sun, 12 Mar 2023 at 18:29, Johan Jonker wrote: > > The fdt_addr_t and phys_addr_t size have been decoupled. > A 32bit CPU can expect 64-bit data from the device tree parser, > so use a regs variable with uintptr_t size in the > dw-apb-timer.c file. > > Signed-off-by: Johan Jonker > --- > > Changed V8: > use uintptr_t instead of phys_addr_t > > Changed V6: > remove cast > change title > --- > drivers/timer/dw-apb-timer.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Simon Glass
Re: [PATCH v8 09/24] rockchip: pwm: rk_pwm: use base variable with uintptr_t size
On Sun, 12 Mar 2023 at 18:30, Johan Jonker wrote: > > The fdt_addr_t and phys_addr_t size have been decoupled. > A 32bit CPU can expect 64-bit data from the device tree parser, > so use a base variable with uintptr_t size in the > rk_pwm.c file. > > Signed-off-by: Johan Jonker > --- > > Changed V8: > use uintptr_t instead of phys_addr_t > > Changed V6: > new patch > --- > drivers/pwm/rk_pwm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Simon Glass
Re: [PATCH v8 10/24] rockchip: spi: rk_spi: use base variable with uintptr_t size
On Sun, 12 Mar 2023 at 18:30, Johan Jonker wrote: > > The fdt_addr_t and phys_addr_t size have been decoupled. > A 32bit CPU can expect 64-bit data from the device tree parser, > so use a base variable with uintptr_t size in the > rk_spi.c file. > > Signed-off-by: Johan Jonker > --- > > Changed V8: > new patch > --- > drivers/spi/rk_spi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Simon Glass
Re: [PATCH v8 12/24] core: remap: fix regmap_init_mem_plat() reg size handeling
On Sun, 12 Mar 2023 at 18:30, Johan Jonker wrote: > > The fdt_addr_t and phys_addr_t size have been decoupled. > A 32bit CPU can expect 64-bit data from the device tree parser, > so convert regmap_init_mem_plat() input to handel both. The > syscon class driver also makes use of the regmap_init_mem_plat() > function, but has no way of knowing the format of the > device-specific platform data. In case of odd reg structures other > then that the syscon class driver assumes the regmap must be > filled in the individual syscon driver before pre-probe. > Also fix the ARRAY_SIZE divider in the syscon class driver. > > Signed-off-by: Johan Jonker > --- > > Changed V8: > fix comment > > Changed V7: > changed title > add reg size input > rework function calls > --- > drivers/core/regmap.c | 23 +++ > drivers/core/syscon-uclass.c| 23 ++- > drivers/ram/rockchip/sdram_rk3066.c | 2 +- > drivers/ram/rockchip/sdram_rk3188.c | 2 +- > drivers/ram/rockchip/sdram_rk322x.c | 2 +- > drivers/ram/rockchip/sdram_rk3288.c | 2 +- > drivers/ram/rockchip/sdram_rk3328.c | 2 +- > drivers/ram/rockchip/sdram_rk3399.c | 2 +- > include/regmap.h| 5 +++-- > include/syscon.h| 13 - > 10 files changed, 46 insertions(+), 30 deletions(-) Reviewed-by: Simon Glass
Re: [PATCH v8 13/24] rockchip: rk3288: syscon_rk3288: store syscon platdata in regmap
On Sun, 12 Mar 2023 at 18:31, Johan Jonker wrote: > > The Rockchip SoC rk3288 has 2 types of device trees floating around. > A 64bit reg size when synced from Linux and a 32bit for U-boot. > A pre-probe function in the syscon class driver assumes only 32bit. > For other odd reg structures the regmap must be defined in the individual > syscon driver. Store rk3288 platdata in a regmap before pre-probe > during bind. > > Signed-off-by: Johan Jonker > --- > > Note: > Proof of concept not tested with rk3288 hardware, > but with rk3066. > > Changed V7: > new patch > --- > arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 121 ++ > 1 file changed, 121 insertions(+) > I tested this on chromebook_jerry which uses SPL_OF_PLATDATA Reviewed-by: Simon Glass Tested-by: Simon Glass Can we sync up with Linux on the DT? Regards, Simon
Re: [PATCH v8 17/24] drivers: use dev_read_addr_index_ptr when cast to pointer
On Sun, 12 Mar 2023 at 18:31, Johan Jonker wrote: > > The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU > can expect 64-bit data from the device tree parser, so use > dev_read_addr_index_ptr instead of the dev_read_addr_index function > in the various files in the drivers directory that cast to a pointer. > As we are there also streamline the error response to -EINVAL on return. > > Signed-off-by: Johan Jonker > Reviewed-by: Michael Trimarchi > --- > > Changed V6: > use -EINVAL on return > drop cast > --- > drivers/mtd/nand/raw/cortina_nand.c | 4 ++-- > drivers/net/dm9000x.c | 2 +- > drivers/net/dwmac_meson8b.c | 4 ++-- > drivers/pci/pcie_dw_meson.c | 8 > drivers/pci/pcie_dw_rockchip.c | 8 > drivers/watchdog/sbsa_gwdt.c| 12 ++-- > 6 files changed, 19 insertions(+), 19 deletions(-) Reviewed-by: Simon Glass
Please pull u-boot-dm/next
Hi Tom,
This is for the -next branch
https://source.denx.de/u-boot/custodians/u-boot-dm/-/pipelines/15568
The following changes since commit bcf343146ff365a88481b9a80920ed146c6dee5b:
Merge tag 'dm-next-9mar23' of
https://source.denx.de/u-boot/custodians/u-boot-dm into next
(2023-03-09 11:22:50 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-dm.git tags/dm-next-12mar23
for you to fetch changes up to 7bb28330f7b4d20bcf844ec306dcfbb41296cfa8:
buildman: Fix CROSS_COMPILE output for sandbox (2023-03-12 11:37:34 -0600)
More tests and fixes for fdt command
binman signing feature
fix buildman -A bug introduced recently
Ivan Mikhaylov (3):
binman: add documentation for binman sign option
binman: add sign option for binman
binman: add tests for sign option
Marek Vasut (10):
test: Wrap assert macros in ({ ... }) and fix missing semicolons
test: cmd: fdt: Drop new unneeded curly brackets
console: Use only 0x00 as line separator for console recording
cmd: fdt: Drop the 0x prefix
test: cmd: fdt: Test fdt print and list
test: cmd: fdt: Test fdt header
test: cmd: fdt: Test fdt memory
test: cmd: fdt: Test fdt rsvmem
test: cmd: fdt: Test fdt chosen
test: cmd: fdt: Test fdt apply
Roman Kopytin (1):
tools: add fdt_add_pubkey
Simon Glass (2):
Revert "buildman: Correct CROSS_COMPILE output for sandbox"
buildman: Fix CROSS_COMPILE output for sandbox
cmd/fdt.c | 2 +-
common/console.c | 2 +-
common/main.c | 1 +
include/test/ut.h | 152 -
test/cmd/fdt.c | 562
-
test/cmd/pwm.c | 4 +-
test/dm/acpigen.c | 2 +-
test/dm/misc.c | 4 +-
test/dm/phy.c | 8 +-
test/dm/scmi.c | 4 +-
test/lib/kconfig.c | 10 +-
test/lib/kconfig_spl.c | 6 +-
test/unicode_ut.c | 6 +-
tools/.gitignore | 1 +
tools/Makefile | 3 +
tools/binman/binman.rst| 47 +
tools/binman/cmdline.py| 13 ++
tools/binman/control.py| 30 ++-
tools/binman/entry.py | 3 +
tools/binman/etype/fit.py | 16 ++
tools/binman/ftest.py | 93
tools/binman/test/280_fit_sign.dts | 63 ++
tools/binman/test/281_sign_non_fit.dts | 65 ++
tools/buildman/toolchain.py| 4 +-
tools/fdt_add_pubkey.c | 138
25 files changed, 1155 insertions(+), 84 deletions(-)
create mode 100644 tools/binman/test/280_fit_sign.dts
create mode 100644 tools/binman/test/281_sign_non_fit.dts
create mode 100644 tools/fdt_add_pubkey.c
Regards,
Simon
RE: [PATCH] i2c: correct I2C deblock logic
> -Original Message-
> From: Bough Chen
> Sent: 2023年2月10日 17:27
> To: h...@denx.de; al.koc...@gmail.com; ma...@denx.de
> Cc: u-boot@lists.denx.de; dl-uboot-imx ;
> xypron.g...@gmx.de; Bough Chen
> Subject: [PATCH] i2c: correct I2C deblock logic
>
> From: Haibo Chen
>
> Current code use dm_gpio_get_value() to get SDA and SCL value, and the value
> depends on the flag GPIOD_ACTIVE_LOW. When toggle SCL to wait slave
> release SDA, the SDA are config as GPIOD_IS_IN, and whether contain the
> GPIOD_ACTIVE_LOW depends on the DTS setting. Usually, for I2C GPIO, we use
> GPIOD_ACTIVE_LOW flag in DTS, so if the SDA is in low level, then
> dm_gpio_get_value() will return 1, current code logic will stop the SCL toggle
> wrongly, cause the I2C deblock not work as expect.
>
> This patch force set the GPIOD_ACTIVE_LOW for both GPIOD_IS_IN and
> GPIOD_IS_OUT, and make the return value of i2c_gpio_get_pin() eaqual to the
> physical voltage logic level.
>
Hi,
Any comments for this patch, just a reminder in case you miss it.
Best Regards
Haibo Chen
> Fixes: aa54192d4a87 ("dm: i2c: implement gpio-based I2C deblock")
> Signed-off-by: Haibo Chen
> ---
> drivers/i2c/i2c-uclass.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index
> 8d9a89ed89..4dc707c659 100644
> --- a/drivers/i2c/i2c-uclass.c
> +++ b/drivers/i2c/i2c-uclass.c
> @@ -505,7 +505,8 @@ uint i2c_get_chip_addr_offset_mask(struct udevice
> *dev) static void i2c_gpio_set_pin(struct gpio_desc *pin, int bit) {
> if (bit)
> - dm_gpio_set_dir_flags(pin, GPIOD_IS_IN);
> + dm_gpio_set_dir_flags(pin, GPIOD_IS_IN |
> +GPIOD_ACTIVE_LOW);
> else
> dm_gpio_set_dir_flags(pin, GPIOD_IS_OUT |
> GPIOD_ACTIVE_LOW |
> @@ -514,7 +515,7 @@ static void i2c_gpio_set_pin(struct gpio_desc *pin, int
> bit)
>
> static int i2c_gpio_get_pin(struct gpio_desc *pin) {
> - return dm_gpio_get_value(pin);
> + return !dm_gpio_get_value(pin);
> }
>
> int i2c_deblock_gpio_loop(struct gpio_desc *sda_pin,
> --
> 2.34.1
[PATCH v8 24/24] include: fdtdec: decouple fdt_addr_t and phys_addr_t size
The DT specification supports CPUs with both 32-bit and 64-bit addressing capabilities. In U-boot the fdt_addr_t and phys_addr_t size are coupled by a typedef. The MTD NAND drivers for 32-bit CPU's can describe partitions with a 64-bit reg property. These partitions synced from Linux end up with the wrong offset and sizes when only the lower 32-bit is passed. Decouple the fdt_addr_t and phys_addr_t size as they don't necessary match. Signed-off-by: Johan Jonker Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- Note: Due to the large number of references to fdt_addr_t this patch serie fixes only some bugs, but not all. Apply only when all remaining errors and warnings due to this patch are fixed. Help with testing/debug appreciated. --- Kconfig | 8 include/fdtdec.h | 13 + 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/Kconfig b/Kconfig index a75cce7e..7697dade 100644 --- a/Kconfig +++ b/Kconfig @@ -422,11 +422,19 @@ endif # EXPERT config PHYS_64BIT bool "64bit physical address support" + select FDT_64BIT help Say Y here to support 64bit physical memory address. This can be used not only for 64bit SoCs, but also for large physical address extension on 32bit SoCs. +config FDT_64BIT + bool "64bit fdt address support" + help + Say Y here to support 64bit fdt addresses. + This can be used not only for 64bit SoCs, but also + for large address extensions on 32bit SoCs. + config HAS_ROM bool select BINMAN diff --git a/include/fdtdec.h b/include/fdtdec.h index aa61a0fc..6b768ed5 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -18,15 +18,18 @@ #include /* - * A typedef for a physical address. Note that fdt data is always big + * Support for 64bit fdt addresses. + * This can be used not only for 64bit SoCs, but also + * for large address extensions on 32bit SoCs. + * Note that fdt data is always big * endian even on a litle endian machine. */ -typedef phys_addr_t fdt_addr_t; -typedef phys_size_t fdt_size_t; #define FDT_SIZE_T_NONE (-1U) -#ifdef CONFIG_PHYS_64BIT +#ifdef CONFIG_FDT_64BIT +typedef u64 fdt_addr_t; +typedef u64 fdt_size_t; #define FDT_ADDR_T_NONE ((ulong)(-1)) #define fdt_addr_to_cpu(reg) be64_to_cpu(reg) @@ -35,6 +38,8 @@ typedef phys_size_t fdt_size_t; #define cpu_to_fdt_size(reg) cpu_to_be64(reg) typedef fdt64_t fdt_val_t; #else +typedef u32 fdt_addr_t; +typedef u32 fdt_size_t; #define FDT_ADDR_T_NONE (-1U) #define fdt_addr_to_cpu(reg) be32_to_cpu(reg) -- 2.20.1
[PATCH v8 23/24] arm: stm32mp: spl: fix function with fdt_addr_t input
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so fix ofnode_get_addr_size function with fdt_addr_t input to
be able to handle both sizes for stm32mp SoC in spl.c file.
Signed-off-by: Johan Jonker
Reviewed-by: Simon Glass
---
Changed V7:
remove cast
---
arch/arm/mach-stm32mp/spl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c
index 19d9fe04..6c79259b 100644
--- a/arch/arm/mach-stm32mp/spl.c
+++ b/arch/arm/mach-stm32mp/spl.c
@@ -112,7 +112,7 @@ uint32_t stm32mp_get_dram_size(void)
static int optee_get_reserved_memory(uint32_t *start, uint32_t *size)
{
- phys_size_t fdt_mem_size;
+ fdt_addr_t fdt_mem_size;
fdt_addr_t fdt_start;
ofnode node;
--
2.20.1
[PATCH v8 22/24] drivers: fix debug string with fdt_addr_t input
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so fix some
debug strings with fdt_addr_t to be able to handle both sizes.
Signed-off-by: Johan Jonker
Reviewed-by: Simon Glass
---
Changed V5:
new patch
---
arch/arm/mach-mvebu/cpu.c | 2 +-
drivers/clk/ti/clk-ctrl.c | 9 +
drivers/phy/phy-stm32-usbphyc.c | 4 ++--
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 329d1369..f58689e1 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -631,7 +631,7 @@ int board_xhci_enable(fdt_addr_t base)
{
const struct mbus_dram_target_info *dram;
- printf("MVEBU XHCI INIT controller @ 0x%lx\n", base);
+ printf("MVEBU XHCI INIT controller @ 0x%llx\n", (fdt64_t)base);
dram = mvebu_mbus_dram_info();
xhci_mvebu_mbus_config((void __iomem *)base, dram);
diff --git a/drivers/clk/ti/clk-ctrl.c b/drivers/clk/ti/clk-ctrl.c
index 6cc02d2e..8926e57e 100644
--- a/drivers/clk/ti/clk-ctrl.c
+++ b/drivers/clk/ti/clk-ctrl.c
@@ -44,7 +44,7 @@ static int clk_ti_ctrl_disable(struct clk *clk)
offs = priv->offs[0].start + clk->id;
err = clk_ti_ctrl_check_offs(clk, offs);
if (err) {
- dev_err(clk->dev, "invalid offset: 0x%lx\n", offs);
+ dev_err(clk->dev, "invalid offset: 0x%llx\n", (fdt64_t)offs);
return err;
}
@@ -64,7 +64,7 @@ static int clk_ti_ctrl_enable(struct clk *clk)
offs = priv->offs[0].start + clk->id;
err = clk_ti_ctrl_check_offs(clk, offs);
if (err) {
- dev_err(clk->dev, "invalid offset: 0x%lx\n", offs);
+ dev_err(clk->dev, "invalid offset: 0x%llx\n", (fdt64_t)offs);
return err;
}
@@ -125,8 +125,9 @@ static int clk_ti_ctrl_of_to_plat(struct udevice *dev)
}
priv->offs[i].end = priv->offs[i].start + fdt_size;
- dev_dbg(dev, "start=0x%08lx, end=0x%08lx\n",
- priv->offs[i].start, priv->offs[i].end);
+ dev_dbg(dev, "start=0x%016llx, end=0x%016llx\n",
+ (fdt64_t)priv->offs[i].start,
+ (fdt64_t)priv->offs[i].end);
}
return 0;
diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c
index dcf2194e..15bd60ca 100644
--- a/drivers/phy/phy-stm32-usbphyc.c
+++ b/drivers/phy/phy-stm32-usbphyc.c
@@ -583,8 +583,8 @@ static int stm32_usbphyc_probe(struct udevice *dev)
phy_id = ofnode_read_u32_default(node, "reg", FDT_ADDR_T_NONE);
if (phy_id >= MAX_PHYS) {
- dev_err(dev, "invalid reg value %lx for %s\n",
- phy_id, ofnode_get_name(node));
+ dev_err(dev, "invalid reg value %llx for %s\n",
+ (fdt64_t)phy_id, ofnode_get_name(node));
return -ENOENT;
}
--
2.20.1
[PATCH v8 21/24] drivers: use devfdt_get_addr_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_ptr instead of the devfdt_get_addr function in
the various files in the drivers directory that cast to a pointer.
Signed-off-by: Johan Jonker
Reviewed-by: Simon Glass
---
Changed V6:
drop cast
skip livetree.rst
Changed V5:
new patch
---
drivers/clk/at91/sama7g5.c | 2 +-
drivers/clk/at91/sckc.c| 2 +-
drivers/spi/mtk_snor.c | 2 +-
drivers/spi/mtk_spim.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index d1ec3c82..7a5a2906 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -1114,7 +1114,7 @@ static const struct pmc_clk_setup {
static int sama7g5_clk_probe(struct udevice *dev)
{
- void __iomem *base = (void *)devfdt_get_addr(dev);
+ void __iomem *base = devfdt_get_addr_ptr(dev);
unsigned int *clkmuxallocs[SAMA7G5_MAX_MUX_ALLOCS];
unsigned int *muxallocs[SAMA7G5_MAX_MUX_ALLOCS];
const char *p[10];
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index 34ce611a..43136ab2 100644
--- a/drivers/clk/at91/sckc.c
+++ b/drivers/clk/at91/sckc.c
@@ -123,7 +123,7 @@ U_BOOT_DRIVER(at91_sam9x60_td_slck) = {
static int at91_sam9x60_sckc_probe(struct udevice *dev)
{
struct sam9x60_sckc *sckc = dev_get_priv(dev);
- void __iomem *base = (void *)devfdt_get_addr(dev);
+ void __iomem *base = devfdt_get_addr_ptr(dev);
const char *slow_rc_osc, *slow_osc;
const char *parents[2];
struct clk *clk, c;
diff --git a/drivers/spi/mtk_snor.c b/drivers/spi/mtk_snor.c
index 04f588a7..4b7d4a6e 100644
--- a/drivers/spi/mtk_snor.c
+++ b/drivers/spi/mtk_snor.c
@@ -470,7 +470,7 @@ static int mtk_snor_probe(struct udevice *bus)
int ret;
u32 reg;
- priv->base = (void __iomem *)devfdt_get_addr(bus);
+ priv->base = devfdt_get_addr_ptr(bus);
if (!priv->base)
return -EINVAL;
diff --git a/drivers/spi/mtk_spim.c b/drivers/spi/mtk_spim.c
index a7c0fc59..ebb8ee8e 100644
--- a/drivers/spi/mtk_spim.c
+++ b/drivers/spi/mtk_spim.c
@@ -641,7 +641,7 @@ static int mtk_spim_probe(struct udevice *dev)
struct mtk_spim_priv *priv = dev_get_priv(dev);
int ret;
- priv->base = (void __iomem *)devfdt_get_addr(dev);
+ priv->base = devfdt_get_addr_ptr(dev);
if (!priv->base)
return -EINVAL;
--
2.20.1
[PATCH v8 20/24] drivers: use devfdt_get_addr_index_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function
in the various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.
Signed-off-by: Johan Jonker
Reviewed-by: Simon Glass
---
Changed V6:
use -EINVAL on return
drop cast
---
drivers/clk/clk-hsdk-cgu.c| 4 ++--
drivers/ddr/altera/sdram_gen5.c | 4 ++--
drivers/mmc/xenon_sdhci.c | 2 +-
drivers/net/mvpp2.c | 24
drivers/pci/pcie_dw_mvebu.c | 4 ++--
drivers/pci/pcie_imx.c| 4 ++--
drivers/pci/pcie_layerscape_ep.c | 8
drivers/phy/marvell/comphy_core.c | 12 ++--
drivers/spi/cadence_qspi.c| 2 +-
drivers/usb/musb-new/ti-musb.c| 2 +-
10 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index 26b0aa9a..e28543ef 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -753,11 +753,11 @@ static int hsdk_cgu_clk_probe(struct udevice *dev)
else
hsdk_clk->map = hsdk_4xd_clk_map;
- hsdk_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index(dev, 0);
+ hsdk_clk->cgu_regs = devfdt_get_addr_index_ptr(dev, 0);
if (!hsdk_clk->cgu_regs)
return -EINVAL;
- hsdk_clk->creg_regs = (void __iomem *)devfdt_get_addr_index(dev, 1);
+ hsdk_clk->creg_regs = devfdt_get_addr_index_ptr(dev, 1);
if (!hsdk_clk->creg_regs)
return -EINVAL;
diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c
index 8d3ce495..34d2a278 100644
--- a/drivers/ddr/altera/sdram_gen5.c
+++ b/drivers/ddr/altera/sdram_gen5.c
@@ -567,9 +567,9 @@ static int altera_gen5_sdram_of_to_plat(struct udevice *dev)
{
struct altera_gen5_sdram_plat *plat = dev_get_plat(dev);
- plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0);
+ plat->sdr = devfdt_get_addr_index_ptr(dev, 0);
if (!plat->sdr)
- return -ENODEV;
+ return -EINVAL;
return 0;
}
diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c
index 2f880509..16ac84a2 100644
--- a/drivers/mmc/xenon_sdhci.c
+++ b/drivers/mmc/xenon_sdhci.c
@@ -537,7 +537,7 @@ static int xenon_sdhci_of_to_plat(struct udevice *dev)
host->ioaddr = dev_read_addr_ptr(dev);
if (device_is_compatible(dev, "marvell,armada-3700-sdhci"))
- priv->pad_ctrl_reg = (void *)devfdt_get_addr_index(dev, 1);
+ priv->pad_ctrl_reg = devfdt_get_addr_index_ptr(dev, 1);
name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type",
NULL);
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 1bad50d3..a4be8497 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -5349,18 +5349,18 @@ static int mvpp2_base_probe(struct udevice *dev)
}
/* Save base addresses for later use */
- priv->base = (void *)devfdt_get_addr_index(dev, 0);
- if (IS_ERR(priv->base))
- return PTR_ERR(priv->base);
+ priv->base = devfdt_get_addr_index_ptr(dev, 0);
+ if (!priv->base)
+ return -EINVAL;
if (priv->hw_version == MVPP21) {
- priv->lms_base = (void *)devfdt_get_addr_index(dev, 1);
- if (IS_ERR(priv->lms_base))
- return PTR_ERR(priv->lms_base);
+ priv->lms_base = devfdt_get_addr_index_ptr(dev, 1);
+ if (!priv->lms_base)
+ return -EINVAL;
} else {
- priv->iface_base = (void *)devfdt_get_addr_index(dev, 1);
- if (IS_ERR(priv->iface_base))
- return PTR_ERR(priv->iface_base);
+ priv->iface_base = devfdt_get_addr_index_ptr(dev, 1);
+ if (!priv->iface_base)
+ return -EINVAL;
/* Store common base addresses for all ports */
priv->mpcs_base = priv->iface_base + MVPP22_MPCS;
@@ -5399,10 +5399,10 @@ static int mvpp2_probe(struct udevice *dev)
if (priv->hw_version == MVPP21) {
int priv_common_regs_num = 2;
- port->base = (void __iomem *)devfdt_get_addr_index(
+ port->base = devfdt_get_addr_index_ptr(
dev->parent, priv_common_regs_num + port->id);
- if (IS_ERR(port->base))
- return PTR_ERR(port->base);
+ if (!port->base)
+ return -EINVAL;
} else {
port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"gop-port-id", -1);
diff --git a/drivers/pci/pcie_dw_mvebu.c
[PATCH v8 19/24] drivers: use devfdt_get_addr_size_index_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_size_index_ptr instead of the devfdt_get_addr_size_index function in the various files in the drivers directory that cast to a pointer. Signed-off-by: Johan Jonker Reviewed-by: Michael Trimarchi Reviewed-by: Simon Glass --- drivers/pci/pcie_dw_mvebu.c | 6 +++--- drivers/spi/cadence_qspi.c | 3 +-- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index a0b82c78..3b2ada54 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -569,9 +569,9 @@ static int pcie_dw_mvebu_of_to_plat(struct udevice *dev) return -EINVAL; /* Get the config space base address and size */ - pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1, ->cfg_size); - if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE) + pcie->cfg_base = devfdt_get_addr_size_index_ptr(dev, 1, + >cfg_size); + if (!pcie->cfg_base) return -EINVAL; return 0; diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index c7f10c50..6a52676a 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -384,8 +384,7 @@ static int cadence_spi_of_to_plat(struct udevice *bus) ofnode subnode; plat->regbase = (void *)devfdt_get_addr_index(bus, 0); - plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1, - >ahbsize); + plat->ahbbase = devfdt_get_addr_size_index_ptr(bus, 1, >ahbsize); plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs"); plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128); plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4); -- 2.20.1
[PATCH v8 18/24] drivers: use dev_read_addr_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_ptr instead of the dev_read_addr function in the
various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.
Signed-off-by: Johan Jonker
Reviewed-by: Simon Glass
---
Changed V6:
use -EINVAL on return
drop cast
Changed V5:
rebase
fix typo
fix more files
---
arch/arm/mach-mvebu/system-controller.c| 4 ++--
doc/develop/driver-model/livetree.rst | 2 +-
drivers/ata/dwc_ahsata.c | 2 +-
drivers/cache/cache-l2x0.c | 2 +-
drivers/cache/cache-v5l2.c | 2 +-
drivers/gpio/mscc_sgpio.c | 2 +-
drivers/gpio/tegra_gpio.c | 4 ++--
drivers/gpio/xilinx_gpio.c | 2 +-
drivers/i2c/i2c-cdns.c | 4 ++--
drivers/i2c/tegra_i2c.c| 4 ++--
drivers/mmc/am654_sdhci.c | 2 +-
drivers/mmc/davinci_mmc.c | 2 +-
drivers/mmc/piton_mmc.c| 2 +-
drivers/mmc/tegra_mmc.c| 2 +-
drivers/mmc/zynq_sdhci.c | 6 +++---
drivers/mtd/nand/raw/arasan_nfc.c | 2 +-
drivers/mtd/nand/raw/cortina_nand.c| 2 +-
drivers/mtd/nand/raw/mxic_nand.c | 2 +-
drivers/mtd/nand/raw/tegra_nand.c | 2 +-
drivers/mtd/nand/raw/zynq_nand.c | 2 +-
drivers/net/mvmdio.c | 2 +-
drivers/net/qe/dm_qe_uec_phy.c | 2 +-
drivers/pci/pci-aardvark.c | 4 ++--
drivers/phy/allwinner/phy-sun50i-usb3.c| 6 +++---
drivers/phy/qcom/phy-qcom-usb-hs-28nm.c| 4 ++--
drivers/phy/qcom/phy-qcom-usb-ss.c | 4 ++--
drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 4 ++--
drivers/phy/rockchip/phy-rockchip-typec.c | 6 +++---
drivers/pwm/tegra_pwm.c| 2 +-
drivers/serial/serial_zynq.c | 6 +++---
drivers/spi/mpc8xxx_spi.c | 2 +-
drivers/spi/mscc_bb_spi.c | 2 +-
drivers/spi/sh_qspi.c | 2 +-
drivers/spi/spi-mxic.c | 2 +-
drivers/spi/xilinx_spi.c | 2 +-
drivers/ufs/ufs.c | 2 +-
drivers/usb/host/ehci-tegra.c | 2 +-
drivers/video/dw_mipi_dsi.c| 4 ++--
drivers/video/rockchip/rk_vop.c| 2 +-
drivers/video/stm32/stm32_dsi.c| 4 ++--
drivers/video/stm32/stm32_ltdc.c | 4 ++--
drivers/video/tegra124/display.c | 2 +-
drivers/video/tegra124/sor.c | 6 +++---
drivers/video/ti/tilcdc.c | 4 ++--
drivers/watchdog/cdns_wdt.c| 6 +++---
drivers/watchdog/sp805_wdt.c | 6 +++---
drivers/watchdog/xilinx_tb_wdt.c | 6 +++---
47 files changed, 75 insertions(+), 75 deletions(-)
diff --git a/arch/arm/mach-mvebu/system-controller.c
b/arch/arm/mach-mvebu/system-controller.c
index e90aff0c..7cdde11c 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -71,8 +71,8 @@ static int mvebu_reset_of_to_plat(struct udevice *dev)
{
struct mvebu_reset_data *data = dev_get_priv(dev);
- data->base = (void *)dev_read_addr(dev);
- if ((fdt_addr_t)data->base == FDT_ADDR_T_NONE)
+ data->base = dev_read_addr_ptr(dev);
+ if (!data->base)
return -EINVAL;
return 0;
diff --git a/doc/develop/driver-model/livetree.rst
b/doc/develop/driver-model/livetree.rst
index 579eef5c..20055d55 100644
--- a/doc/develop/driver-model/livetree.rst
+++ b/doc/develop/driver-model/livetree.rst
@@ -103,7 +103,7 @@ The new code is:
struct udevice *bus;
-i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
+i2c_bus->regs = dev_read_addr_ptr(dev);
plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", 50);
The dev_read\_...() interface is more convenient and works with both the
diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c
index 167b5a39..6a4d861b 100644
--- a/drivers/ata/dwc_ahsata.c
+++ b/drivers/ata/dwc_ahsata.c
@@ -912,7 +912,7 @@ int dwc_ahsata_probe(struct udevice *dev)
#endif
uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
- uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev);
+ uc_priv->mmio_base = dev_read_addr_ptr(dev);
/* initialize adapter */
ret = ahci_host_init(uc_priv);
diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c
index a1556fbf..560f4c94 100644
---
[PATCH v8 17/24] drivers: use dev_read_addr_index_ptr when cast to pointer
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_index_ptr instead of the dev_read_addr_index function
in the various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.
Signed-off-by: Johan Jonker
Reviewed-by: Michael Trimarchi
---
Changed V6:
use -EINVAL on return
drop cast
---
drivers/mtd/nand/raw/cortina_nand.c | 4 ++--
drivers/net/dm9000x.c | 2 +-
drivers/net/dwmac_meson8b.c | 4 ++--
drivers/pci/pcie_dw_meson.c | 8
drivers/pci/pcie_dw_rockchip.c | 8
drivers/watchdog/sbsa_gwdt.c| 12 ++--
6 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/mtd/nand/raw/cortina_nand.c
b/drivers/mtd/nand/raw/cortina_nand.c
index 88798f23..8de35731 100644
--- a/drivers/mtd/nand/raw/cortina_nand.c
+++ b/drivers/mtd/nand/raw/cortina_nand.c
@@ -1175,8 +1175,8 @@ static int fdt_decode_nand(struct udevice *dev, struct
nand_drv *info)
int ecc_strength;
info->reg = (struct nand_ctlr *)dev_read_addr(dev);
- info->dma_glb = (struct dma_global *)dev_read_addr_index(dev, 1);
- info->dma_nand = (struct dma_ssp *)dev_read_addr_index(dev, 2);
+ info->dma_glb = dev_read_addr_index_ptr(dev, 1);
+ info->dma_nand = dev_read_addr_index_ptr(dev, 2);
info->config.enabled = dev_read_enabled(dev);
ecc_strength = dev_read_u32_default(dev, "nand-ecc-strength", 16);
info->flash_base =
diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c
index b46bdeb2..bec8d67d 100644
--- a/drivers/net/dm9000x.c
+++ b/drivers/net/dm9000x.c
@@ -651,7 +651,7 @@ static int dm9000_of_to_plat(struct udevice *dev)
pdata->iobase = dev_read_addr_index(dev, 0);
db->base_io = (void __iomem *)pdata->iobase;
- db->base_data = (void __iomem *)dev_read_addr_index(dev, 1);
+ db->base_data = dev_read_addr_index_ptr(dev, 1);
return 0;
}
diff --git a/drivers/net/dwmac_meson8b.c b/drivers/net/dwmac_meson8b.c
index ddbaa87d..871171e1 100644
--- a/drivers/net/dwmac_meson8b.c
+++ b/drivers/net/dwmac_meson8b.c
@@ -41,8 +41,8 @@ static int dwmac_meson8b_of_to_plat(struct udevice *dev)
{
struct dwmac_meson8b_plat *pdata = dev_get_plat(dev);
- pdata->regs = (void *)dev_read_addr_index(dev, 1);
- if ((fdt_addr_t)pdata->regs == FDT_ADDR_T_NONE)
+ pdata->regs = dev_read_addr_index_ptr(dev, 1);
+ if (!pdata->regs)
return -EINVAL;
pdata->dwmac_setup = (void *)dev_get_driver_data(dev);
diff --git a/drivers/pci/pcie_dw_meson.c b/drivers/pci/pcie_dw_meson.c
index 07da9fa5..f9537979 100644
--- a/drivers/pci/pcie_dw_meson.c
+++ b/drivers/pci/pcie_dw_meson.c
@@ -337,15 +337,15 @@ static int meson_pcie_parse_dt(struct udevice *dev)
struct meson_pcie *priv = dev_get_priv(dev);
int ret;
- priv->dw.dbi_base = (void *)dev_read_addr_index(dev, 0);
+ priv->dw.dbi_base = dev_read_addr_index_ptr(dev, 0);
if (!priv->dw.dbi_base)
- return -ENODEV;
+ return -EINVAL;
dev_dbg(dev, "ELBI address is 0x%p\n", priv->dw.dbi_base);
- priv->meson_cfg_base = (void *)dev_read_addr_index(dev, 1);
+ priv->meson_cfg_base = dev_read_addr_index_ptr(dev, 1);
if (!priv->meson_cfg_base)
- return -ENODEV;
+ return -EINVAL;
dev_dbg(dev, "CFG address is 0x%p\n", priv->meson_cfg_base);
diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 9322e735..624ca1cb 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -353,15 +353,15 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
struct rk_pcie *priv = dev_get_priv(dev);
int ret;
- priv->dw.dbi_base = (void *)dev_read_addr_index(dev, 0);
+ priv->dw.dbi_base = dev_read_addr_index_ptr(dev, 0);
if (!priv->dw.dbi_base)
- return -ENODEV;
+ return -EINVAL;
dev_dbg(dev, "DBI address is 0x%p\n", priv->dw.dbi_base);
- priv->apb_base = (void *)dev_read_addr_index(dev, 1);
+ priv->apb_base = dev_read_addr_index_ptr(dev, 1);
if (!priv->apb_base)
- return -ENODEV;
+ return -EINVAL;
dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base);
diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c
index f43cd3fd..96d04665 100644
--- a/drivers/watchdog/sbsa_gwdt.c
+++ b/drivers/watchdog/sbsa_gwdt.c
@@ -98,13 +98,13 @@ static int sbsa_gwdt_of_to_plat(struct udevice *dev)
{
struct sbsa_gwdt_priv *priv = dev_get_priv(dev);
- priv->reg_control = (void __iomem *)dev_read_addr_index(dev, 0);
- if (IS_ERR(priv->reg_control))
- return PTR_ERR(priv->reg_control);
+ priv->reg_control =
[PATCH v8 16/24] spi: spi-aspeed-smc: use devfdt_get_addr_index_ptr
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use devfdt_get_addr_index_ptr and devfdt_get_addr_size_index_ptr
function in the spi-aspeed-smc.c file. Also fix dev_dbg to be able
to handle both sizes. As we are there also streamline the error
response to -EINVAL on return.
Signed-off-by: Johan Jonker
Reviewed-by: Michael Trimarchi
---
Changed V6:
use -EINVAL on return
---
drivers/spi/spi-aspeed-smc.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index 4b6ea9f8..39620310 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -1125,17 +1125,16 @@ static int apseed_spi_of_to_plat(struct udevice *bus)
int ret;
struct clk hclk;
- priv->regs = (void __iomem *)devfdt_get_addr_index(bus, 0);
- if ((u32)priv->regs == FDT_ADDR_T_NONE) {
+ priv->regs = devfdt_get_addr_index_ptr(bus, 0);
+ if (!priv->regs) {
dev_err(bus, "wrong ctrl base\n");
- return -ENODEV;
+ return -EINVAL;
}
- plat->ahb_base =
- (void __iomem *)devfdt_get_addr_size_index(bus, 1,
>ahb_sz);
- if ((u32)plat->ahb_base == FDT_ADDR_T_NONE) {
+ plat->ahb_base = devfdt_get_addr_size_index_ptr(bus, 1, >ahb_sz);
+ if (!plat->ahb_base) {
dev_err(bus, "wrong AHB base\n");
- return -ENODEV;
+ return -EINVAL;
}
plat->max_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS);
@@ -1151,8 +1150,8 @@ static int apseed_spi_of_to_plat(struct udevice *bus)
plat->hclk_rate = clk_get_rate();
clk_free();
- dev_dbg(bus, "ctrl_base = 0x%x, ahb_base = 0x%p, size = 0x%lx\n",
- (u32)priv->regs, plat->ahb_base, plat->ahb_sz);
+ dev_dbg(bus, "ctrl_base = 0x%x, ahb_base = 0x%p, size = 0x%llx\n",
+ (u32)priv->regs, plat->ahb_base, (fdt64_t)plat->ahb_sz);
dev_dbg(bus, "hclk = %dMHz, max_cs = %d\n",
plat->hclk_rate / 100, plat->max_cs);
--
2.20.1
[PATCH v8 15/24] core: read: add dev_read_addr_index_ptr function
Add dev_read_addr_index_ptr function with the
same functionality as dev_read_addr_index,
but instead a return pointer is given.
Use map_sysmem() function as cast for the return.
Make same fix for dev_read_addr_ptr() function.
Signed-off-by: Johan Jonker
Reviewed-by: Simon Glass
---
Changed V6:
use map_sysmem()
Changed V5:
new patch
---
drivers/core/read.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/core/read.c b/drivers/core/read.c
index e0543bba..0289a2ed 100644
--- a/drivers/core/read.c
+++ b/drivers/core/read.c
@@ -131,6 +131,16 @@ fdt_addr_t dev_read_addr_index(const struct udevice *dev,
int index)
return devfdt_get_addr_index(dev, index);
}
+void *dev_read_addr_index_ptr(const struct udevice *dev, int index)
+{
+ fdt_addr_t addr = dev_read_addr_index(dev, index);
+
+ if (addr == FDT_ADDR_T_NONE)
+ return NULL;
+
+ return map_sysmem(addr, 0);
+}
+
fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, int index,
fdt_size_t *size)
{
@@ -190,7 +200,10 @@ void *dev_read_addr_ptr(const struct udevice *dev)
{
fdt_addr_t addr = dev_read_addr(dev);
- return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr;
+ if (addr == FDT_ADDR_T_NONE)
+ return NULL;
+
+ return map_sysmem(addr, 0);
}
void *dev_remap_addr(const struct udevice *dev)
--
2.20.1
[PATCH v8 14/24] core: fdtaddr: add devfdt_get_addr_size_index_ptr function
Add devfdt_get_addr_size_index_ptr function with the same
functionality as devfdt_get_addr_size_index, but instead
a return pointer is given.
Use map_sysmem() function as cast for the return.
Make same fix for devfdt_get_addr_index_ptr() function.
Suggested-by: Michael Nazzareno Trimarchi
Signed-off-by: Johan Jonker
Reviewed-by: Michael Trimarchi
Reviewed-by: Simon Glass
---
Changed V7:
use map_sysmem()
Changed V5:
fix spelling
use tabs
---
drivers/core/fdtaddr.c | 17 -
include/dm/fdtaddr.h | 17 -
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c
index 91bcd1a2..546db675 100644
--- a/drivers/core/fdtaddr.c
+++ b/drivers/core/fdtaddr.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -97,7 +98,10 @@ void *devfdt_get_addr_index_ptr(const struct udevice *dev,
int index)
{
fdt_addr_t addr = devfdt_get_addr_index(dev, index);
- return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr;
+ if (addr == FDT_ADDR_T_NONE)
+ return NULL;
+
+ return map_sysmem(addr, 0);
}
fdt_addr_t devfdt_get_addr_size_index(const struct udevice *dev, int index,
@@ -122,6 +126,17 @@ fdt_addr_t devfdt_get_addr_size_index(const struct udevice
*dev, int index,
#endif
}
+void *devfdt_get_addr_size_index_ptr(const struct udevice *dev, int index,
+fdt_size_t *size)
+{
+ fdt_addr_t addr = devfdt_get_addr_size_index(dev, index, size);
+
+ if (addr == FDT_ADDR_T_NONE)
+ return NULL;
+
+ return map_sysmem(addr, 0);
+}
+
fdt_addr_t devfdt_get_addr_name(const struct udevice *dev, const char *name)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)
diff --git a/include/dm/fdtaddr.h b/include/dm/fdtaddr.h
index c9d2b27b..dcdc1913 100644
--- a/include/dm/fdtaddr.h
+++ b/include/dm/fdtaddr.h
@@ -111,7 +111,7 @@ void *devfdt_get_addr_index_ptr(const struct udevice *dev,
int index);
* @dev: Pointer to a device
* @index: the 'reg' property can hold a list of pairs
*and @index is used to select which one is required
- * @size: Pointer to size varible - this function returns the size
+ * @size: Pointer to size variable - this function returns the size
*specified in the 'reg' property here
*
* Return: addr
@@ -119,6 +119,21 @@ void *devfdt_get_addr_index_ptr(const struct udevice *dev,
int index);
fdt_addr_t devfdt_get_addr_size_index(const struct udevice *dev, int index,
fdt_size_t *size);
+/**
+ * devfdt_get_addr_size_index_ptr() - Return indexed pointer to the address of
the
+ *reg property of a device
+ *
+ * @dev: Pointer to a device
+ * @index: the 'reg' property can hold a list of pairs
+ *and @index is used to select which one is required
+ * @size: Pointer to size variable - this function returns the size
+ *specified in the 'reg' property here
+ *
+ * Return: Pointer to addr, or NULL if there is no such property
+ */
+void *devfdt_get_addr_size_index_ptr(const struct udevice *dev, int index,
+fdt_size_t *size);
+
/**
* devfdt_get_addr_name() - Get the reg property of a device, indexed by name
*
--
2.20.1
[PATCH v8 13/24] rockchip: rk3288: syscon_rk3288: store syscon platdata in regmap
The Rockchip SoC rk3288 has 2 types of device trees floating around.
A 64bit reg size when synced from Linux and a 32bit for U-boot.
A pre-probe function in the syscon class driver assumes only 32bit.
For other odd reg structures the regmap must be defined in the individual
syscon driver. Store rk3288 platdata in a regmap before pre-probe
during bind.
Signed-off-by: Johan Jonker
---
Note:
Proof of concept not tested with rk3288 hardware,
but with rk3066.
Changed V7:
new patch
---
arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 121 ++
1 file changed, 121 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
index 9c1ae880..8b2c2f32 100644
--- a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
@@ -6,7 +6,10 @@
#include
#include
+#include
#include
+#include
+#include
#include
#include
@@ -25,6 +28,103 @@ U_BOOT_DRIVER(syscon_rk3288) = {
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
+#if IS_ENABLED(CONFIG_FDT_64BIT)
+struct rockchip_rk3288_noc_plat {
+ struct dtd_rockchip_rk3288_noc dtplat;
+};
+
+struct rockchip_rk3288_grf_plat {
+ struct dtd_rockchip_rk3288_grf dtplat;
+};
+
+struct rockchip_rk3288_sgrf_plat {
+ struct dtd_rockchip_rk3288_sgrf dtplat;
+};
+
+struct rockchip_rk3288_pmu_plat {
+ struct dtd_rockchip_rk3288_pmu dtplat;
+};
+
+static int rk3288_noc_bind_of_plat(struct udevice *dev)
+{
+ struct rockchip_rk3288_noc_plat *plat = dev_get_plat(dev);
+ struct syscon_uc_info *priv = dev_get_uclass_priv(dev);
+ int size = dev->uclass->uc_drv->per_device_auto;
+
+ if (size && !priv) {
+ priv = calloc(1, size);
+ if (!priv)
+ return -ENOMEM;
+ dev_set_uclass_priv(dev, priv);
+ }
+
+ dev->driver_data = dev->driver->of_match->data;
+ debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
+
+ return regmap_init_mem_plat(dev, plat->dtplat.reg,
sizeof(plat->dtplat.reg[0]),
+ ARRAY_SIZE(plat->dtplat.reg) / 2,
>regmap);
+}
+
+static int rk3288_grf_bind_of_plat(struct udevice *dev)
+{
+ struct rockchip_rk3288_grf_plat *plat = dev_get_plat(dev);
+ struct syscon_uc_info *priv = dev_get_uclass_priv(dev);
+ int size = dev->uclass->uc_drv->per_device_auto;
+
+ if (size && !priv) {
+ priv = calloc(1, size);
+ if (!priv)
+ return -ENOMEM;
+ dev_set_uclass_priv(dev, priv);
+ }
+
+ dev->driver_data = dev->driver->of_match->data;
+ debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
+
+ return regmap_init_mem_plat(dev, plat->dtplat.reg,
sizeof(plat->dtplat.reg[0]),
+ ARRAY_SIZE(plat->dtplat.reg) / 2,
>regmap);
+}
+
+static int rk3288_sgrf_bind_of_plat(struct udevice *dev)
+{
+ struct rockchip_rk3288_sgrf_plat *plat = dev_get_plat(dev);
+ struct syscon_uc_info *priv = dev_get_uclass_priv(dev);
+ int size = dev->uclass->uc_drv->per_device_auto;
+
+ if (size && !priv) {
+ priv = calloc(1, size);
+ if (!priv)
+ return -ENOMEM;
+ dev_set_uclass_priv(dev, priv);
+ }
+
+ dev->driver_data = dev->driver->of_match->data;
+ debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
+
+ return regmap_init_mem_plat(dev, plat->dtplat.reg,
sizeof(plat->dtplat.reg[0]),
+ ARRAY_SIZE(plat->dtplat.reg) / 2,
>regmap);
+}
+
+static int rk3288_pmu_bind_of_plat(struct udevice *dev)
+{
+ struct rockchip_rk3288_pmu_plat *plat = dev_get_plat(dev);
+ struct syscon_uc_info *priv = dev_get_uclass_priv(dev);
+ int size = dev->uclass->uc_drv->per_device_auto;
+
+ if (size && !priv) {
+ priv = calloc(1, size);
+ if (!priv)
+ return -ENOMEM;
+ dev_set_uclass_priv(dev, priv);
+ }
+
+ dev->driver_data = dev->driver->of_match->data;
+ debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
+
+ return regmap_init_mem_plat(dev, plat->dtplat.reg,
sizeof(plat->dtplat.reg[0]),
+ ARRAY_SIZE(plat->dtplat.reg) / 2,
>regmap);
+}
+#else
static int rk3288_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
@@ -32,32 +132,53 @@ static int rk3288_syscon_bind_of_plat(struct udevice *dev)
return 0;
}
+#endif
U_BOOT_DRIVER(rockchip_rk3288_noc) = {
.name = "rockchip_rk3288_noc",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids,
+#if IS_ENABLED(CONFIG_FDT_64BIT)
+ .bind = rk3288_noc_bind_of_plat,
+ .plat_auto = sizeof(struct rockchip_rk3288_noc_plat),
+#else
.bind =
[PATCH v8 12/24] core: remap: fix regmap_init_mem_plat() reg size handeling
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so convert regmap_init_mem_plat() input to handel both. The
syscon class driver also makes use of the regmap_init_mem_plat()
function, but has no way of knowing the format of the
device-specific platform data. In case of odd reg structures other
then that the syscon class driver assumes the regmap must be
filled in the individual syscon driver before pre-probe.
Also fix the ARRAY_SIZE divider in the syscon class driver.
Signed-off-by: Johan Jonker
---
Changed V8:
fix comment
Changed V7:
changed title
add reg size input
rework function calls
---
drivers/core/regmap.c | 23 +++
drivers/core/syscon-uclass.c| 23 ++-
drivers/ram/rockchip/sdram_rk3066.c | 2 +-
drivers/ram/rockchip/sdram_rk3188.c | 2 +-
drivers/ram/rockchip/sdram_rk322x.c | 2 +-
drivers/ram/rockchip/sdram_rk3288.c | 2 +-
drivers/ram/rockchip/sdram_rk3328.c | 2 +-
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
include/regmap.h| 5 +++--
include/syscon.h| 13 -
10 files changed, 46 insertions(+), 30 deletions(-)
diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index e33bb9d7..dd323280 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c
@@ -79,7 +79,7 @@ static struct regmap *regmap_alloc(int count)
}
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-int regmap_init_mem_plat(struct udevice *dev, fdt_val_t *reg, int count,
+int regmap_init_mem_plat(struct udevice *dev, void *reg, int size, int count,
struct regmap **mapp)
{
struct regmap_range *range;
@@ -89,9 +89,24 @@ int regmap_init_mem_plat(struct udevice *dev, fdt_val_t
*reg, int count,
if (!map)
return -ENOMEM;
- for (range = map->ranges; count > 0; reg += 2, range++, count--) {
- range->start = *reg;
- range->size = reg[1];
+ if (size == sizeof(fdt32_t)) {
+ fdt32_t *ptr = (fdt32_t *)reg;
+
+ for (range = map->ranges; count > 0;
+ptr += 2, range++, count--) {
+ range->start = *ptr;
+ range->size = ptr[1];
+ }
+ } else if (size == sizeof(fdt64_t)) {
+ fdt64_t *ptr = (fdt64_t *)reg;
+
+ for (range = map->ranges; count > 0;
+ptr += 2, range++, count--) {
+ range->start = *ptr;
+ range->size = ptr[1];
+ }
+ } else {
+ return -EINVAL;
}
*mapp = map;
diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c
index 25fdb66e..a47b8bd3 100644
--- a/drivers/core/syscon-uclass.c
+++ b/drivers/core/syscon-uclass.c
@@ -49,17 +49,30 @@ static int syscon_pre_probe(struct udevice *dev)
if (device_get_uclass_id(dev->parent) == UCLASS_PCI)
return 0;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
/*
* With OF_PLATDATA we really have no way of knowing the format of
* the device-specific platform data. So we assume that it starts with
-* a 'reg' member, and this holds a single address and size. Drivers
-* using OF_PLATDATA will need to ensure that this is true.
+* a 'reg' member that holds a single address and size. Drivers
+* using OF_PLATDATA will need to ensure that this is true. In case of
+* odd reg structures other then the syscon_base_plat structure
+* below the regmap must be defined in the individual syscon driver.
*/
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct syscon_base_plat {
+ phys_addr_t reg[2];
+ };
+
struct syscon_base_plat *plat = dev_get_plat(dev);
- return regmap_init_mem_plat(dev, plat->reg, ARRAY_SIZE(plat->reg),
- >regmap);
+ /*
+* Return if the regmap is already defined in the individual
+* syscon driver.
+*/
+ if (priv->regmap)
+ return 0;
+
+ return regmap_init_mem_plat(dev, plat->reg, sizeof(plat->reg[0]),
+ ARRAY_SIZE(plat->reg) / 2, >regmap);
#else
return regmap_init_mem(dev_ofnode(dev), >regmap);
#endif
diff --git a/drivers/ram/rockchip/sdram_rk3066.c
b/drivers/ram/rockchip/sdram_rk3066.c
index a2425f22..39c0be56 100644
--- a/drivers/ram/rockchip/sdram_rk3066.c
+++ b/drivers/ram/rockchip/sdram_rk3066.c
@@ -801,7 +801,7 @@ static int rk3066_dmc_conv_of_plat(struct udevice *dev)
memcpy(>base, of_plat->rockchip_sdram_params, sizeof(plat->base));
/* RK3066 supports dual-channel, set default channel num to 2. */
plat->num_channels = 1;
- ret = regmap_init_mem_plat(dev, of_plat->reg,
+ ret = regmap_init_mem_plat(dev, of_plat->reg, sizeof(of_plat->reg[0]),
[PATCH v8 11/24] include: dm: ofnode: fix headers
When fdt_addr_t and phys_addr_t are split it turns out that the header don't match the functions, so fix the headers. Signed-off-by: Johan Jonker Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- include/dm/ofnode.h | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 3f6b0843..cd966f6a 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -678,8 +678,8 @@ int ofnode_read_size(ofnode node, const char *propname); * @size: Pointer to size of the address * Return: address, or FDT_ADDR_T_NONE if not present or invalid */ -phys_addr_t ofnode_get_addr_size_index(ofnode node, int index, - fdt_size_t *size); +fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index, + fdt_size_t *size); /** * ofnode_get_addr_size_index_notrans() - get an address/size from a node @@ -695,8 +695,8 @@ phys_addr_t ofnode_get_addr_size_index(ofnode node, int index, * @size: Pointer to size of the address * Return: address, or FDT_ADDR_T_NONE if not present or invalid */ -phys_addr_t ofnode_get_addr_size_index_notrans(ofnode node, int index, - fdt_size_t *size); +fdt_addr_t ofnode_get_addr_size_index_notrans(ofnode node, int index, + fdt_size_t *size); /** * ofnode_get_addr_index() - get an address from a node @@ -707,7 +707,7 @@ phys_addr_t ofnode_get_addr_size_index_notrans(ofnode node, int index, * @index: Index of address to read (0 for first) * Return: address, or FDT_ADDR_T_NONE if not present or invalid */ -phys_addr_t ofnode_get_addr_index(ofnode node, int index); +fdt_addr_t ofnode_get_addr_index(ofnode node, int index); /** * ofnode_get_addr() - get an address from a node @@ -717,7 +717,7 @@ phys_addr_t ofnode_get_addr_index(ofnode node, int index); * @node: node to read from * Return: address, or FDT_ADDR_T_NONE if not present or invalid */ -phys_addr_t ofnode_get_addr(ofnode node); +fdt_addr_t ofnode_get_addr(ofnode node); /** * ofnode_get_size() - get size from a node @@ -1067,8 +1067,8 @@ const void *ofprop_get_property(const struct ofprop *prop, * @sizep: place to put size value (on success) * Return: address value, or FDT_ADDR_T_NONE on error */ -phys_addr_t ofnode_get_addr_size(ofnode node, const char *propname, -phys_size_t *sizep); +fdt_addr_t ofnode_get_addr_size(ofnode node, const char *propname, + fdt_size_t *sizep); /** * ofnode_read_u8_array_ptr() - find an 8-bit array -- 2.20.1
[PATCH v8 10/24] rockchip: spi: rk_spi: use base variable with uintptr_t size
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use a base variable with uintptr_t size in the
rk_spi.c file.
Signed-off-by: Johan Jonker
---
Changed V8:
new patch
---
drivers/spi/rk_spi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 66b20fce..7de94335 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -45,7 +45,7 @@ struct rockchip_spi_plat {
struct dtd_rockchip_rk3288_spi of_plat;
#endif
s32 frequency; /* Default clock frequency, -1 for none */
- fdt_addr_t base;
+ uintptr_t base;
uint deactivate_delay_us; /* Delay to wait after deactivate */
uint activate_delay_us; /* Delay to wait after activate */
};
--
2.20.1
[PATCH v8 09/24] rockchip: pwm: rk_pwm: use base variable with uintptr_t size
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use a base variable with uintptr_t size in the
rk_pwm.c file.
Signed-off-by: Johan Jonker
---
Changed V8:
use uintptr_t instead of phys_addr_t
Changed V6:
new patch
---
drivers/pwm/rk_pwm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c
index 071eb04f..1858d597 100644
--- a/drivers/pwm/rk_pwm.c
+++ b/drivers/pwm/rk_pwm.c
@@ -30,7 +30,7 @@ struct rockchip_pwm_data {
};
struct rk_pwm_priv {
- fdt_addr_t base;
+ uintptr_t base;
ulong freq;
u32 conf_polarity;
const struct rockchip_pwm_data *data;
--
2.20.1
[PATCH v8 08/24] rockchip: timer: dw-apb-timer: use regs variable with uintptr_t size
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use a regs variable with uintptr_t size in the
dw-apb-timer.c file.
Signed-off-by: Johan Jonker
---
Changed V8:
use uintptr_t instead of phys_addr_t
Changed V6:
remove cast
change title
---
drivers/timer/dw-apb-timer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c
index 10f0a9f6..b171232c 100644
--- a/drivers/timer/dw-apb-timer.c
+++ b/drivers/timer/dw-apb-timer.c
@@ -23,7 +23,7 @@
#define DW_APB_CTRL0x8
struct dw_apb_timer_priv {
- fdt_addr_t regs;
+ uintptr_t regs;
struct reset_ctl_bulk resets;
};
--
2.20.1
[PATCH v8 07/24] rockchip: adc: rockchip-saradc: use dev_read_addr_ptr
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expext 64-bit data from the device tree parser,
so use dev_read_addr_ptr in the rockchip-saradc.c file.
As we are there also streamline the error response to -EINVAL on return.
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
---
Changed V6:
use -EINVAL on return
drop cast
---
drivers/adc/rockchip-saradc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c
index 760f8fe6..809486eb 100644
--- a/drivers/adc/rockchip-saradc.c
+++ b/drivers/adc/rockchip-saradc.c
@@ -145,10 +145,10 @@ int rockchip_saradc_of_to_plat(struct udevice *dev)
struct rockchip_saradc_data *data;
data = (struct rockchip_saradc_data *)dev_get_driver_data(dev);
- priv->regs = (struct rockchip_saradc_regs *)dev_read_addr(dev);
- if (priv->regs == (struct rockchip_saradc_regs *)FDT_ADDR_T_NONE) {
+ priv->regs = dev_read_addr_ptr(dev);
+ if (!priv->regs) {
pr_err("Dev: %s - can't get address!", dev->name);
- return -ENODATA;
+ return -EINVAL;
}
priv->data = data;
--
2.20.1
[PATCH v8 06/24] mtd: nand: add support for the Sandisk SDTNQGAMA chip
Sandisk SDTNQGAMA is a 8GB size, 3.3V 8 bit chip with 16KB page size,
1KB write size and 40 bit ecc support
Signed-off-by: Paweł Jarosz
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
Acked-by: Michael Trimarchi
---
drivers/mtd/nand/raw/nand_ids.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c
index d0cfacc6..22ea5e2f 100644
--- a/drivers/mtd/nand/raw/nand_ids.c
+++ b/drivers/mtd/nand/raw/nand_ids.c
@@ -48,6 +48,9 @@ struct nand_flash_dev nand_flash_ids[] = {
{"TC58NVG6D2 64G 3.3V 8-bit",
{ .id = {0x98, 0xde, 0x94, 0x82, 0x76, 0x56, 0x04, 0x20} },
SZ_8K, SZ_8K, SZ_2M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
+ {"SDTNQGAMA 64G 3.3V 8-bit",
+ { .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x57} },
+ SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) },
{"SDTNRGAMA 64G 3.3V 8-bit",
{ .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} },
SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) },
--
2.20.1
[PATCH v8 05/24] mtd: nand: raw: rockchip_nfc: fix oobfree offset and description
The MTD framework reserves 1 or 2 bytes for the bad block marker depending on the bus size. The rockchip_nfc driver currently only supports a 8 bit bus, but reserves standard 2 bytes for the BBM. The first free OOB byte is therefore OOB2 at offset 2. Page address(PA) bytes are moved to the last 4 positions before ECC. Update the description for U-boot. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- drivers/mtd/nand/raw/rockchip_nfc.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c b/drivers/mtd/nand/raw/rockchip_nfc.c index 25e04974..5fcf6a6b 100644 --- a/drivers/mtd/nand/raw/rockchip_nfc.c +++ b/drivers/mtd/nand/raw/rockchip_nfc.c @@ -487,10 +487,10 @@ static int rk_nfc_write_page_raw(struct mtd_info *mtd, * *BBM OOB1 OOB2 OOB3 |..| PA0 PA1 PA2 PA3 * -* The rk_nfc_ooblayout_free() function already has reserved -* these 4 bytes with: +* The oobfree structure already has reserved these 4 bytes +* together with 2 bytes for BBM by reducing it's length: * -* oob_region->offset = NFC_SYS_DATA_SIZE + 2; +* oobfree[0].length = rknand->metadata_size - NFC_SYS_DATA_SIZE - 2; */ if (!i) memcpy(rk_nfc_oob_ptr(chip, i), @@ -867,7 +867,7 @@ static int rk_nfc_ecc_init(struct rk_nfc *nfc, struct nand_chip *chip) ecc->layout->eccpos[i] = rknand->metadata_size + i; ecc->layout->oobfree[0].length = rknand->metadata_size - NFC_SYS_DATA_SIZE - 2; - ecc->layout->oobfree[0].offset = NFC_SYS_DATA_SIZE + 2; + ecc->layout->oobfree[0].offset = 2; return 0; } -- 2.20.1
[PATCH v8 04/24] mtd: nand: raw: rockchip_nfc: add flash_node to chip structure
Add flash_node to the rockchip_nfc driver chip structure in order to find the partitions in the add_mtd_partitions_of() function. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang Reviewed-by: Michael Trimarchi --- drivers/mtd/nand/raw/rockchip_nfc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c b/drivers/mtd/nand/raw/rockchip_nfc.c index 90cd86a2..25e04974 100644 --- a/drivers/mtd/nand/raw/rockchip_nfc.c +++ b/drivers/mtd/nand/raw/rockchip_nfc.c @@ -934,6 +934,7 @@ static int rk_nfc_nand_chip_init(ofnode node, struct rk_nfc *nfc, int devnum) nand_set_controller_data(chip, nfc); + chip->flash_node = node; chip->chip_delay = NFC_RB_DELAY_US; chip->select_chip = rk_nfc_select_chip; chip->cmd_ctrl = rk_nfc_cmd; -- 2.20.1
[PATCH v8 03/24] mtd: nand: raw: rockchip_nfc: add layout structure
The MTD framework in U-boot is not identical for drivers ported
from Linux. The rockchip_nfc driver was ported with OOB ops functions
while the framework expects a layout structure per chip.
Fix by adding a structure with OOB data and remove unused functions.
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
Reviewed-by: Michael Trimarchi
---
drivers/mtd/nand/raw/rockchip_nfc.c | 61 ++---
1 file changed, 20 insertions(+), 41 deletions(-)
diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c
b/drivers/mtd/nand/raw/rockchip_nfc.c
index 021e7ef7..90cd86a2 100644
--- a/drivers/mtd/nand/raw/rockchip_nfc.c
+++ b/drivers/mtd/nand/raw/rockchip_nfc.c
@@ -814,47 +814,9 @@ static void rk_nfc_disable_clks(struct rk_nfc *nfc)
clk_disable_unprepare(nfc->ahb_clk);
}
-static int rk_nfc_ooblayout_free(struct mtd_info *mtd, int section,
-struct mtd_oob_region *oob_region)
-{
- struct nand_chip *chip = mtd_to_nand(mtd);
- struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
-
- if (section)
- return -ERANGE;
-
- /*
-* The beginning of the OOB area stores the reserved data for the NFC,
-* the size of the reserved data is NFC_SYS_DATA_SIZE bytes.
-*/
- oob_region->length = rknand->metadata_size - NFC_SYS_DATA_SIZE - 2;
- oob_region->offset = NFC_SYS_DATA_SIZE + 2;
-
- return 0;
-}
-
-static int rk_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
- struct mtd_oob_region *oob_region)
-{
- struct nand_chip *chip = mtd_to_nand(mtd);
- struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
-
- if (section)
- return -ERANGE;
-
- oob_region->length = mtd->oobsize - rknand->metadata_size;
- oob_region->offset = rknand->metadata_size;
-
- return 0;
-}
-
-static const struct mtd_ooblayout_ops rk_nfc_ooblayout_ops = {
- .rfree = rk_nfc_ooblayout_free,
- .ecc = rk_nfc_ooblayout_ecc,
-};
-
static int rk_nfc_ecc_init(struct rk_nfc *nfc, struct nand_chip *chip)
{
+ struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
const u8 *strengths = nfc->cfg->ecc_strengths;
struct mtd_info *mtd = nand_to_mtd(chip);
struct nand_ecc_ctrl *ecc = >ecc;
@@ -892,6 +854,21 @@ static int rk_nfc_ecc_init(struct rk_nfc *nfc, struct
nand_chip *chip)
ecc->steps = mtd->writesize / ecc->size;
ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * chip->ecc.size), 8);
+ if (ecc->bytes * ecc->steps > mtd->oobsize - rknand->metadata_size)
+ return -EINVAL;
+
+ ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
+ if (!ecc->layout)
+ return -ENOMEM;
+
+ ecc->layout->eccbytes = ecc->bytes * ecc->steps;
+
+ for (i = 0; i < ecc->layout->eccbytes; i++)
+ ecc->layout->eccpos[i] = rknand->metadata_size + i;
+
+ ecc->layout->oobfree[0].length = rknand->metadata_size -
NFC_SYS_DATA_SIZE - 2;
+ ecc->layout->oobfree[0].offset = NFC_SYS_DATA_SIZE + 2;
+
return 0;
}
@@ -969,7 +946,6 @@ static int rk_nfc_nand_chip_init(ofnode node, struct rk_nfc
*nfc, int devnum)
chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
- mtd_set_ooblayout(mtd, _nfc_ooblayout_ops);
rk_nfc_hw_init(nfc);
ret = nand_scan_ident(mtd, nsels, NULL);
if (ret)
@@ -998,13 +974,16 @@ static int rk_nfc_nand_chip_init(ofnode node, struct
rk_nfc *nfc, int devnum)
if (!nfc->page_buf) {
nfc->page_buf = kzalloc(NFC_MAX_PAGE_SIZE, GFP_KERNEL);
- if (!nfc->page_buf)
+ if (!nfc->page_buf) {
+ kfree(ecc->layout);
return -ENOMEM;
+ }
}
if (!nfc->oob_buf) {
nfc->oob_buf = kzalloc(NFC_MAX_OOB_SIZE, GFP_KERNEL);
if (!nfc->oob_buf) {
+ kfree(ecc->layout);
kfree(nfc->page_buf);
nfc->page_buf = NULL;
return -ENOMEM;
--
2.20.1
[PATCH v8 02/24] mtd: nand: raw: rockchip_nfc: remove the compatible string "rockchip,rk3308-nfc"
The compatible string for rk3308 has as fallback string
"rockchip,rv1108-nfc". As there is no logic in probe priority between
the SoC orientated string and the fall back, so remove the compatible
string "rockchip,rk3308-nfc" from the driver.
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
Reviewed-by: Michael Trimarchi
---
drivers/mtd/nand/raw/rockchip_nfc.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c
b/drivers/mtd/nand/raw/rockchip_nfc.c
index 9f424a25..021e7ef7 100644
--- a/drivers/mtd/nand/raw/rockchip_nfc.c
+++ b/drivers/mtd/nand/raw/rockchip_nfc.c
@@ -1165,10 +1165,6 @@ static const struct udevice_id rk_nfc_id_table[] = {
.compatible = "rockchip,rv1108-nfc",
.data = (unsigned long)_v8_cfg
},
- {
- .compatible = "rockchip,rk3308-nfc",
- .data = (unsigned long)_v8_cfg
- },
{ /* sentinel */ }
};
--
2.20.1
[PATCH v8 01/24] mtd: nand: raw: rockchip_nfc: use dev_read_addr_ptr
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expext 64-bit data from the device tree parser,
so use dev_read_addr_ptr in the rockchip_nfc.c file.
Signed-off-by: Johan Jonker
Reviewed-by: Michael Trimarchi
---
Changed V6:
use -EINVAL on return
---
drivers/mtd/nand/raw/rockchip_nfc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c
b/drivers/mtd/nand/raw/rockchip_nfc.c
index d016d255..9f424a25 100644
--- a/drivers/mtd/nand/raw/rockchip_nfc.c
+++ b/drivers/mtd/nand/raw/rockchip_nfc.c
@@ -1180,9 +1180,9 @@ static int rk_nfc_probe(struct udevice *dev)
nfc->cfg = (void *)dev_get_driver_data(dev);
nfc->dev = dev;
- nfc->regs = (void *)dev_read_addr(dev);
- if (IS_ERR(nfc->regs)) {
- ret = PTR_ERR(nfc->regs);
+ nfc->regs = dev_read_addr_ptr(dev);
+ if (!nfc->regs) {
+ ret = -EINVAL;
goto release_nfc;
}
--
2.20.1
Re: [PATCH 2/2] buildman: Fix CROSS_COMPILE output for sandbox
The previous attempt at fixing this broke the normal usage of the -A flag. At present, 'buildman -A sandbox' adds the path containing the toolchain. We can assume that this is in the path and we don't want to set CROSS_COMPILE=/bin/ Change this to align with what MakeEnvironment() does, but only for sandbox boards. Signed-off-by: Simon Glass --- tools/buildman/toolchain.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) Applied to u-boot-dm/next, thanks!
Re: [PATCH 1/2] Revert "buildman: Correct CROSS_COMPILE output for sandbox"
This reverts commit bd0a548ad4a155fec29473d4cc8e135832926973. Signed-off-by: Simon Glass --- tools/buildman/toolchain.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) Applied to u-boot-dm/next, thanks!
[PATCH v8 00/24] Fixes for Rockchip NFC driver part 1
This serie contains fixes for the Rockchip NFC driver, which was ported to U-boot and merged with little review and testing it seems. Part 1 aims at passing the probe function without errors. Extended with tree wide function cleanup needed for 64bit DT parsing. Fixed are: 64bit FDT parsing compatible string removal add missing layout structure add missing flash_node pointer add missing chip ID Changed V8: change comments use uintptr_t size instead of phys_addr_t add another fdt_addr_t fix Changed V7: add proof of concept for syscon node with variable reg size handling use another map_sysmem() function as cast remove cast Changed V6: use -EINVAL on return drop cast use map_sysmem() function as cast add and rename patch Changed V5: sort patch order add more fixes with pointer functions add debug text fixes test with binman for ARM only due to limited resources Changed V4: fix cast and divider in syscon-uclass.c Changed V3: use dev_read_addr_ptr fix oobfree Johan Jonker (23): mtd: nand: raw: rockchip_nfc: use dev_read_addr_ptr mtd: nand: raw: rockchip_nfc: remove the compatible string "rockchip,rk3308-nfc" mtd: nand: raw: rockchip_nfc: add layout structure mtd: nand: raw: rockchip_nfc: add flash_node to chip structure mtd: nand: raw: rockchip_nfc: fix oobfree offset and description rockchip: adc: rockchip-saradc: use dev_read_addr_ptr rockchip: timer: dw-apb-timer: use regs variable with uintptr_t size rockchip: pwm: rk_pwm: use base variable with uintptr_t size rockchip: spi: rk_spi: use base variable with uintptr_t size include: dm: ofnode: fix headers core: remap: fix regmap_init_mem_plat() reg size handeling rockchip: rk3288: syscon_rk3288: store syscon platdata in regmap core: fdtaddr: add devfdt_get_addr_size_index_ptr function core: read: add dev_read_addr_index_ptr function spi: spi-aspeed-smc: use devfdt_get_addr_index_ptr drivers: use dev_read_addr_index_ptr when cast to pointer drivers: use dev_read_addr_ptr when cast to pointer drivers: use devfdt_get_addr_size_index_ptr when cast to pointer drivers: use devfdt_get_addr_index_ptr when cast to pointer drivers: use devfdt_get_addr_ptr when cast to pointer drivers: fix debug string with fdt_addr_t input arm: stm32mp: spl: fix function with fdt_addr_t input include: fdtdec: decouple fdt_addr_t and phys_addr_t size Paweł Jarosz (1): mtd: nand: add support for the Sandisk SDTNQGAMA chip Kconfig | 8 ++ arch/arm/mach-mvebu/cpu.c | 2 +- arch/arm/mach-mvebu/system-controller.c | 4 +- arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 121 ++ arch/arm/mach-stm32mp/spl.c | 2 +- doc/develop/driver-model/livetree.rst | 2 +- drivers/adc/rockchip-saradc.c | 6 +- drivers/ata/dwc_ahsata.c | 2 +- drivers/cache/cache-l2x0.c| 2 +- drivers/cache/cache-v5l2.c| 2 +- drivers/clk/at91/sama7g5.c| 2 +- drivers/clk/at91/sckc.c | 2 +- drivers/clk/clk-hsdk-cgu.c| 4 +- drivers/clk/ti/clk-ctrl.c | 9 +- drivers/core/fdtaddr.c| 17 ++- drivers/core/read.c | 15 ++- drivers/core/regmap.c | 23 +++- drivers/core/syscon-uclass.c | 23 +++- drivers/ddr/altera/sdram_gen5.c | 4 +- drivers/gpio/mscc_sgpio.c | 2 +- drivers/gpio/tegra_gpio.c | 4 +- drivers/gpio/xilinx_gpio.c| 2 +- drivers/i2c/i2c-cdns.c| 4 +- drivers/i2c/tegra_i2c.c | 4 +- drivers/mmc/am654_sdhci.c | 2 +- drivers/mmc/davinci_mmc.c | 2 +- drivers/mmc/piton_mmc.c | 2 +- drivers/mmc/tegra_mmc.c | 2 +- drivers/mmc/xenon_sdhci.c | 2 +- drivers/mmc/zynq_sdhci.c | 6 +- drivers/mtd/nand/raw/arasan_nfc.c | 2 +- drivers/mtd/nand/raw/cortina_nand.c | 6 +- drivers/mtd/nand/raw/mxic_nand.c | 2 +- drivers/mtd/nand/raw/nand_ids.c | 3 + drivers/mtd/nand/raw/rockchip_nfc.c | 78 --- drivers/mtd/nand/raw/tegra_nand.c | 2 +- drivers/mtd/nand/raw/zynq_nand.c | 2 +- drivers/net/dm9000x.c | 2 +- drivers/net/dwmac_meson8b.c | 4 +- drivers/net/mvmdio.c | 2 +- drivers/net/mvpp2.c | 24 ++-- drivers/net/qe/dm_qe_uec_phy.c| 2 +- drivers/pci/pci-aardvark.c| 4 +- drivers/pci/pcie_dw_meson.c | 8 +-
Re: [PATCH RFC u-boot-mvebu] arm: kirkwood: Move internal registers in arch_very_early_init() function
Hi Pali,
On Sun, Mar 12, 2023 at 2:38 PM Pali Rohár wrote:
>
> On Sunday 12 March 2023 14:30:29 Tony Dinh wrote:
> > Hi Pali,
> >
> > On Sat, Mar 11, 2023 at 4:29 PM Pali Rohár wrote:
> > >
> > > On Saturday 11 March 2023 15:47:29 Tony Dinh wrote:
> > > > Hi Pali,
> > > >
> > > > On Sat, Mar 11, 2023 at 2:57 AM Pali Rohár wrote:
> > > > >
> > > > > Same change as was done for mvebu in commit 5bb2c550b11e ("arm:
> > > > > mvebu: Move
> > > > > internal registers in arch_very_early_init() function") but for
> > > > > kirkwood.
> > > > >
> > > > > Signed-off-by: Pali Rohár
> > > > > ---
> > > > > Hello! Please test this RFC patch on more Kirkwood boards if there is
> > > > > any issue with it.
> > > >
> > > > I've run a regression test with this patch (Debug UART is not
> > > > enabled). And everything was OK. No change in behavior.
> > >
> > > Ok! Thanks for testing.
> > >
> > > > However, when I turned on Debug UART on the nsa310s (88F6702) board,
> > > > and ran with kwboot, it froze right away upon starting. Unrelated to
> > > > this patch, I believe DEBUG_UART has been broken for Kirkwood lately,
> > > > perhaps sometime late December to present, but I did not have time to
> > > > track it down. Here is the last thread that I had Debug UART working
> > > > on the Pogo V4 (88F6192):
> > > > https://lists.denx.de/pipermail/u-boot/2022-December/502605.html
> > > >
> > > > For reference, here is my local patch to configure the NSA310S, in
> > > > addition to this patch.
> > >
> > > I do not know what could broke it, but I see there two things which you
> > > could change in your configuration.
> > >
> > > 1. Try to set UART shift register to 2. Not sure what is default but in
> > >kirkwood.dtsi file it is 2.
> > >
> > >CONFIG_DEBUG_UART_SHIFT=2
> > >
> > > 2. Recheck UART clock. In kw88f6281.h is defined that TCLK is either
> > >16667 or 2. And it is configured by strapping pins. TCLK
> > >cannot be 25000 on 6281 for sure. I do not know to which clock
> > >is connected UART base clock, but my guess is that it is TCLK.
> >
> > Thanks for the suggestion. Indeed, the combination of
> > CONFIG_DEBUG_UART_CLOCK=16667 and CONFIG_DEBUG_UART_SHIFT=2 works
> > as it should (88F6702/88F6192 TCLK=16667).
> >
> > Without setting CONFIG_DEBUG_UART_SHIFT in defconfig, it is default to 0.
> >
> > CONFIG_DEBUG_UART_SHIFT=2 is the key here, because U-Boot does not
> > hang with CONFIG_DEBUG_UART_CLOCK=25000. The board runs OK, but
> > the Debug UART announcement output is gibberish.
>
> Perfect! So ideally send a patch with adding those options into
> nsa310s_defconfig. I guess that CONFIG_DEBUG_UART_ANNOUNCE is not
> needed.
Sure, I will do that. In the meantime, I ran some more tests and here
are some interesting results (thanks to Debug UART working now).
1. I've confirmed that, at the moment, we need your patch to see
DEBUG_UART early output for Kirkwood. Without it, with DEBUG_UART
configured correctly, I don't see any output on this board. It will
run fine but behaving like there is no Debug UART enabled.
2. There is no need for the u-boot,dm-pre-reloc tag on Kirkwood
boards. The serial-uclass function serial_check_stdout() binds it
anyway ff the console is not marked to be bound before relocation:
https://github.com/u-boot/u-boot/blob/master/drivers/serial/serial-uclass.c#L67
3. The previous problem we saw with the Pogo V4 (Kirwood 6192) DM
serial might be related to all this. Hopefully with your patch I can
track it down further.
Thanks,
Tony
>
> > So I guess back on the Dec 19th build, perhaps I was just lucky that
> > some internal values were used for Kirkwood, but not CONFIG_xxx.
> >
> > Thanks,
> > Tony
> >
> > > > diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig
> > > > index 76839e62dd..4bef35d576 100644
> > > > --- a/configs/nsa310s_defconfig
> > > > +++ b/configs/nsa310s_defconfig
> > > > @@ -15,8 +15,11 @@ CONFIG_ENV_SIZE=0x2
> > > > CONFIG_ENV_OFFSET=0xE
> > > > CONFIG_DEFAULT_DEVICE_TREE="kirkwood-nsa310s"
> > > > CONFIG_SYS_PROMPT="NSA310s> "
> > > > +CONFIG_DEBUG_UART_BASE=0xf1012000
> > > > +CONFIG_DEBUG_UART_CLOCK=25000
> > > > CONFIG_IDENT_STRING="\nZyXEL NSA310S/320S 1/2-Bay Power Media Server"
> > > > CONFIG_SYS_LOAD_ADDR=0x80
> > > > +CONFIG_DEBUG_UART=y
> > > > CONFIG_DISTRO_DEFAULTS=y
> > > > CONFIG_BOOTDELAY=3
> > > > CONFIG_USE_PREBOOT=y
> > > > @@ -50,6 +53,7 @@ CONFIG_MTD_RAW_NAND=y
> > > > CONFIG_PHY_MARVELL=y
> > > > CONFIG_MVGBE=y
> > > > CONFIG_MII=y
> > > > +CONFIG_DEBUG_UART_ANNOUNCE=y
> > > > CONFIG_USB=y
> > > > CONFIG_USB_EHCI_HCD=y
> > > > CONFIG_UBIFS_SILENCE_MSG=y
> > > >
> > > > diff --git a/arch/arm/dts/kirkwood-nsa310s.dts
> > > > b/arch/arm/dts/kirkwood-nsa310s.dts
> > > > index 09ee76c2a2..2df45aa6da 100644
> > > > --- a/arch/arm/dts/kirkwood-nsa310s.dts
> > > > +++ b/arch/arm/dts/kirkwood-nsa310s.dts
> > > > @@ -22,6 +22,10 @@
> > > > reg =
RE: [GIT PULL] Please pull u-boot-mmc master
Dear Tom, > -Original Message- > From: Tom Rini > Sent: Saturday, March 11, 2023 12:44 AM > To: Jaehoon Chung > Cc: U-Boot Mailing List ; Loic Poulain > ; Marek Vasut > ; Stefan Roese ; Jae hoon Chung > > Subject: Re: [GIT PULL] Please pull u-boot-mmc master > > On Fri, Mar 10, 2023 at 01:22:15PM +0900, Jaehoon Chung wrote: > > Dear Tom, > > > > > > Please pull u-boot-mmc master into u-boot master branch. > > If there is any problem, let me know, plz. > > At this point in the cycle I have to ask, are these all fixes of > specific issues? If not, I'd rather take this to -next. Thanks! Okay. I will request PR as -next again. Discard this PR. Best Regards, Jaehoon Chung > > -- > Tom
Re: [RFC PATCH 00/16] arm: Add Rockchip RK3588 support
Hi Eugen, On 2023-03-08 09:57, Eugen Hristev wrote: > On 1/29/23 11:04, Jonas Karlman wrote: >> On 2023-01-27 14:21, Jagan Teki wrote: >>> On Fri, 27 Jan 2023 at 05:13, Jonas Karlman wrote: On 2023-01-26 23:16, Jonas Karlman wrote: > Hi Jagan, > On 2023-01-26 20:17, Jagan Teki wrote: >> On Fri, 27 Jan 2023 at 00:33, Jonas Karlman wrote: >>> >>> On 2023-01-26 19:26, Jagan Teki wrote: Hi Simon, On Thu, 26 Jan 2023 at 23:34, Simon Glass wrote: > > Hi Jagan, > > On Thu, 26 Jan 2023 at 10:42, Jagan Teki wrote: >> >> On Thu, 26 Jan 2023 at 22:28, Jonas Karlman wrote: >>> >>> Hi Jagan, >>> On 2023-01-26 17:51, Jagan Teki wrote: Hi Jonas, On Thu, 26 Jan 2023 at 04:17, Jonas Karlman wrote: > > Hi Jagan, > > On 2023-01-25 23:27, Jagan Teki wrote: >> This series support Rockchip RK3588. All the device tree files >> are >> synced from linux-next with the proper SHA1 mentioned in the >> commit >> messages. >> >> Unfortunately, the BL31 from rkbin is not compatible with U-Boot >> so >> it is failing to load ATF entry from SPL and hang. >> >> Verified below BL31 versions, >>bl31-v1.15 >>bl31-v1.21 >>bl31-v1.22 >>bl31-v1.23 >>bl31-v1.24 >>bl31-v1.25 >>bl31-v1.26 >> >>> >>> < snip > >>> > > As you can see in the logs above there is timeout waiting for data. > > I managed to find the issue and have a workaround that gets me longer > in the boot process, there still seem to be other issue with the rk3588 > startup. > > > U-Boot SPL 2023.01 (Jan 26 2023 - 22:03:00 +) > Trying to boot from MMC1 > ## Checking hash(es) for config config-1 ... OK > ## Checking hash(es) for Image atf-1 ... sha256+ OK > ## Checking hash(es) for Image u-boot ... sha256+ OK > ## Checking hash(es) for Image fdt-1 ... sha256+ OK > ## Checking hash(es) for Image atf-2 ... sha256+ OK > ## Checking hash(es) for Image atf-3 ... sha256+ OK > INFO:Preloader serial: 2 > NOTICE: BL31: v2.3():v2.3-468-ge529a2760:derrick.huang > NOTICE: BL31: Built : 09:59:49, Nov 21 2022 > INFO:spec: 0x1 > INFO:ext 32k is not valid > INFO:ddr: stride-en 4CH > INFO:GICv3 without legacy support detected. > INFO:ARM GICv3 driver initialized in EL3 > INFO:valid_cpu_msk=0xff bcore0_rst = 0x0, bcore1_rst = 0x0 > INFO:system boots from cpu-hwid-0 > INFO:idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001 > INFO:dfs DDR fsp_params[0].freq_mhz= 2112MHz > INFO:dfs DDR fsp_params[1].freq_mhz= 528MHz > INFO:dfs DDR fsp_params[2].freq_mhz= 1068MHz > INFO:dfs DDR fsp_params[3].freq_mhz= 1560MHz > INFO:BL31: Initialising Exception Handling Framework > INFO:BL31: Initializing runtime services > WARNING: No OPTEE provided by BL2 boot loader, Booting device without > OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK > ERROR: Error initializing runtime service opteed_fast > INFO:BL31: Preparing for EL3 exit to normal world > INFO:Entry point address = 0xa0 > INFO:SPSR = 0x3c9 > "Synchronous Abort" handler, esr 0x9600 > elr: 00a23650 lr : 00a24d9c > x0 : 00b7fbe8 x1 : 350003402a0003f3 > x2 : x3 : 00b80ff0 > x4 : 00b80ff0 x5 : 00b80e88 > x6 : 0054 x7 : 0044 > x8 : 000a x9 : > x10: 0034 x11: 0002 > x12: 1988 x13: 00b7fadc > x14: 00a7e808 x15: 00a7e808 > x16: x17: > x18: 00b7fe50 x19: 00b7fbe8 > x20: 3c14dc00 x21: 3c14dc00 > x22: 00a7e808 x23: > x24: x25: > x26: x27: > x28: x29: 00b7fb80 > > Code: f90013f5 f941 b4000201 f9400021 (f9403435) > Resetting CPU ... > > > This was running on top of u-boot-dm/master > 060a65e899859dcbf42049a18be20ce7118e7c0e > with some rk3568 patches and this series, see [1]. > > The last 3 commits contains workaround to issue with sdmmc clock. > dwmmc driver set sclk to (uint)-2, my workaround just adds a > fallback to default 400khz clock. > > Next issue is the sync abort, looks it happens when u-boot > tries to set clock
Re: [PATCH RFC u-boot-mvebu] arm: kirkwood: Move internal registers in arch_very_early_init() function
On Sunday 12 March 2023 14:30:29 Tony Dinh wrote:
> Hi Pali,
>
> On Sat, Mar 11, 2023 at 4:29 PM Pali Rohár wrote:
> >
> > On Saturday 11 March 2023 15:47:29 Tony Dinh wrote:
> > > Hi Pali,
> > >
> > > On Sat, Mar 11, 2023 at 2:57 AM Pali Rohár wrote:
> > > >
> > > > Same change as was done for mvebu in commit 5bb2c550b11e ("arm: mvebu:
> > > > Move
> > > > internal registers in arch_very_early_init() function") but for
> > > > kirkwood.
> > > >
> > > > Signed-off-by: Pali Rohár
> > > > ---
> > > > Hello! Please test this RFC patch on more Kirkwood boards if there is
> > > > any issue with it.
> > >
> > > I've run a regression test with this patch (Debug UART is not
> > > enabled). And everything was OK. No change in behavior.
> >
> > Ok! Thanks for testing.
> >
> > > However, when I turned on Debug UART on the nsa310s (88F6702) board,
> > > and ran with kwboot, it froze right away upon starting. Unrelated to
> > > this patch, I believe DEBUG_UART has been broken for Kirkwood lately,
> > > perhaps sometime late December to present, but I did not have time to
> > > track it down. Here is the last thread that I had Debug UART working
> > > on the Pogo V4 (88F6192):
> > > https://lists.denx.de/pipermail/u-boot/2022-December/502605.html
> > >
> > > For reference, here is my local patch to configure the NSA310S, in
> > > addition to this patch.
> >
> > I do not know what could broke it, but I see there two things which you
> > could change in your configuration.
> >
> > 1. Try to set UART shift register to 2. Not sure what is default but in
> >kirkwood.dtsi file it is 2.
> >
> >CONFIG_DEBUG_UART_SHIFT=2
> >
> > 2. Recheck UART clock. In kw88f6281.h is defined that TCLK is either
> >16667 or 2. And it is configured by strapping pins. TCLK
> >cannot be 25000 on 6281 for sure. I do not know to which clock
> >is connected UART base clock, but my guess is that it is TCLK.
>
> Thanks for the suggestion. Indeed, the combination of
> CONFIG_DEBUG_UART_CLOCK=16667 and CONFIG_DEBUG_UART_SHIFT=2 works
> as it should (88F6702/88F6192 TCLK=16667).
>
> Without setting CONFIG_DEBUG_UART_SHIFT in defconfig, it is default to 0.
>
> CONFIG_DEBUG_UART_SHIFT=2 is the key here, because U-Boot does not
> hang with CONFIG_DEBUG_UART_CLOCK=25000. The board runs OK, but
> the Debug UART announcement output is gibberish.
Perfect! So ideally send a patch with adding those options into
nsa310s_defconfig. I guess that CONFIG_DEBUG_UART_ANNOUNCE is not
needed.
> So I guess back on the Dec 19th build, perhaps I was just lucky that
> some internal values were used for Kirkwood, but not CONFIG_xxx.
>
> Thanks,
> Tony
>
> > > diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig
> > > index 76839e62dd..4bef35d576 100644
> > > --- a/configs/nsa310s_defconfig
> > > +++ b/configs/nsa310s_defconfig
> > > @@ -15,8 +15,11 @@ CONFIG_ENV_SIZE=0x2
> > > CONFIG_ENV_OFFSET=0xE
> > > CONFIG_DEFAULT_DEVICE_TREE="kirkwood-nsa310s"
> > > CONFIG_SYS_PROMPT="NSA310s> "
> > > +CONFIG_DEBUG_UART_BASE=0xf1012000
> > > +CONFIG_DEBUG_UART_CLOCK=25000
> > > CONFIG_IDENT_STRING="\nZyXEL NSA310S/320S 1/2-Bay Power Media Server"
> > > CONFIG_SYS_LOAD_ADDR=0x80
> > > +CONFIG_DEBUG_UART=y
> > > CONFIG_DISTRO_DEFAULTS=y
> > > CONFIG_BOOTDELAY=3
> > > CONFIG_USE_PREBOOT=y
> > > @@ -50,6 +53,7 @@ CONFIG_MTD_RAW_NAND=y
> > > CONFIG_PHY_MARVELL=y
> > > CONFIG_MVGBE=y
> > > CONFIG_MII=y
> > > +CONFIG_DEBUG_UART_ANNOUNCE=y
> > > CONFIG_USB=y
> > > CONFIG_USB_EHCI_HCD=y
> > > CONFIG_UBIFS_SILENCE_MSG=y
> > >
> > > diff --git a/arch/arm/dts/kirkwood-nsa310s.dts
> > > b/arch/arm/dts/kirkwood-nsa310s.dts
> > > index 09ee76c2a2..2df45aa6da 100644
> > > --- a/arch/arm/dts/kirkwood-nsa310s.dts
> > > +++ b/arch/arm/dts/kirkwood-nsa310s.dts
> > > @@ -22,6 +22,10 @@
> > > reg = <0x 0x1000>;
> > > };
> > >
> > > + aliases {
> > > + serial0 =
> > > + };
> > > +
> > > chosen {
> > > bootargs = "console=ttyS0,115200";
> > > stdout-path =
> > > @@ -317,3 +321,8 @@
> > > {
> > > status = "okay";
> > > };
> > > +
> > > + {
> > > +status = "okay";
> > > +u-boot,dm-pre-reloc;
> > > +};
> > >
> > > If anybody is available to test this patch with Debug UART enabled, it
> > > would be great. I'll wait a few days and if there is no suggestion, I
> > > would do a bisect from Dec 19th.
> > >
> > > Thanks,
> > > Tony
> > >
> > > > ---
> > > > arch/arm/mach-kirkwood/Kconfig| 2 ++
> > > > arch/arm/mach-kirkwood/Makefile | 1 +
> > > > arch/arm/mach-kirkwood/cpu.c | 3 ---
> > > > arch/arm/mach-kirkwood/lowlevel.S | 12
> > > > 4 files changed, 15 insertions(+), 3 deletions(-)
> > > > create mode 100644 arch/arm/mach-kirkwood/lowlevel.S
> > > >
> > > > diff --git a/arch/arm/mach-kirkwood/Kconfig
> > > > b/arch/arm/mach-kirkwood/Kconfig
> > > >
Re: [PATCH RFC u-boot-mvebu] arm: kirkwood: Move internal registers in arch_very_early_init() function
Hi Pali,
On Sat, Mar 11, 2023 at 4:29 PM Pali Rohár wrote:
>
> On Saturday 11 March 2023 15:47:29 Tony Dinh wrote:
> > Hi Pali,
> >
> > On Sat, Mar 11, 2023 at 2:57 AM Pali Rohár wrote:
> > >
> > > Same change as was done for mvebu in commit 5bb2c550b11e ("arm: mvebu:
> > > Move
> > > internal registers in arch_very_early_init() function") but for kirkwood.
> > >
> > > Signed-off-by: Pali Rohár
> > > ---
> > > Hello! Please test this RFC patch on more Kirkwood boards if there is
> > > any issue with it.
> >
> > I've run a regression test with this patch (Debug UART is not
> > enabled). And everything was OK. No change in behavior.
>
> Ok! Thanks for testing.
>
> > However, when I turned on Debug UART on the nsa310s (88F6702) board,
> > and ran with kwboot, it froze right away upon starting. Unrelated to
> > this patch, I believe DEBUG_UART has been broken for Kirkwood lately,
> > perhaps sometime late December to present, but I did not have time to
> > track it down. Here is the last thread that I had Debug UART working
> > on the Pogo V4 (88F6192):
> > https://lists.denx.de/pipermail/u-boot/2022-December/502605.html
> >
> > For reference, here is my local patch to configure the NSA310S, in
> > addition to this patch.
>
> I do not know what could broke it, but I see there two things which you
> could change in your configuration.
>
> 1. Try to set UART shift register to 2. Not sure what is default but in
>kirkwood.dtsi file it is 2.
>
>CONFIG_DEBUG_UART_SHIFT=2
>
> 2. Recheck UART clock. In kw88f6281.h is defined that TCLK is either
>16667 or 2. And it is configured by strapping pins. TCLK
>cannot be 25000 on 6281 for sure. I do not know to which clock
>is connected UART base clock, but my guess is that it is TCLK.
Thanks for the suggestion. Indeed, the combination of
CONFIG_DEBUG_UART_CLOCK=16667 and CONFIG_DEBUG_UART_SHIFT=2 works
as it should (88F6702/88F6192 TCLK=16667).
Without setting CONFIG_DEBUG_UART_SHIFT in defconfig, it is default to 0.
CONFIG_DEBUG_UART_SHIFT=2 is the key here, because U-Boot does not
hang with CONFIG_DEBUG_UART_CLOCK=25000. The board runs OK, but
the Debug UART announcement output is gibberish.
So I guess back on the Dec 19th build, perhaps I was just lucky that
some internal values were used for Kirkwood, but not CONFIG_xxx.
Thanks,
Tony
> > diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig
> > index 76839e62dd..4bef35d576 100644
> > --- a/configs/nsa310s_defconfig
> > +++ b/configs/nsa310s_defconfig
> > @@ -15,8 +15,11 @@ CONFIG_ENV_SIZE=0x2
> > CONFIG_ENV_OFFSET=0xE
> > CONFIG_DEFAULT_DEVICE_TREE="kirkwood-nsa310s"
> > CONFIG_SYS_PROMPT="NSA310s> "
> > +CONFIG_DEBUG_UART_BASE=0xf1012000
> > +CONFIG_DEBUG_UART_CLOCK=25000
> > CONFIG_IDENT_STRING="\nZyXEL NSA310S/320S 1/2-Bay Power Media Server"
> > CONFIG_SYS_LOAD_ADDR=0x80
> > +CONFIG_DEBUG_UART=y
> > CONFIG_DISTRO_DEFAULTS=y
> > CONFIG_BOOTDELAY=3
> > CONFIG_USE_PREBOOT=y
> > @@ -50,6 +53,7 @@ CONFIG_MTD_RAW_NAND=y
> > CONFIG_PHY_MARVELL=y
> > CONFIG_MVGBE=y
> > CONFIG_MII=y
> > +CONFIG_DEBUG_UART_ANNOUNCE=y
> > CONFIG_USB=y
> > CONFIG_USB_EHCI_HCD=y
> > CONFIG_UBIFS_SILENCE_MSG=y
> >
> > diff --git a/arch/arm/dts/kirkwood-nsa310s.dts
> > b/arch/arm/dts/kirkwood-nsa310s.dts
> > index 09ee76c2a2..2df45aa6da 100644
> > --- a/arch/arm/dts/kirkwood-nsa310s.dts
> > +++ b/arch/arm/dts/kirkwood-nsa310s.dts
> > @@ -22,6 +22,10 @@
> > reg = <0x 0x1000>;
> > };
> >
> > + aliases {
> > + serial0 =
> > + };
> > +
> > chosen {
> > bootargs = "console=ttyS0,115200";
> > stdout-path =
> > @@ -317,3 +321,8 @@
> > {
> > status = "okay";
> > };
> > +
> > + {
> > +status = "okay";
> > +u-boot,dm-pre-reloc;
> > +};
> >
> > If anybody is available to test this patch with Debug UART enabled, it
> > would be great. I'll wait a few days and if there is no suggestion, I
> > would do a bisect from Dec 19th.
> >
> > Thanks,
> > Tony
> >
> > > ---
> > > arch/arm/mach-kirkwood/Kconfig| 2 ++
> > > arch/arm/mach-kirkwood/Makefile | 1 +
> > > arch/arm/mach-kirkwood/cpu.c | 3 ---
> > > arch/arm/mach-kirkwood/lowlevel.S | 12
> > > 4 files changed, 15 insertions(+), 3 deletions(-)
> > > create mode 100644 arch/arm/mach-kirkwood/lowlevel.S
> > >
> > > diff --git a/arch/arm/mach-kirkwood/Kconfig
> > > b/arch/arm/mach-kirkwood/Kconfig
> > > index c8a193dd4cdf..ba39e9ae416e 100644
> > > --- a/arch/arm/mach-kirkwood/Kconfig
> > > +++ b/arch/arm/mach-kirkwood/Kconfig
> > > @@ -5,9 +5,11 @@ config FEROCEON_88FR131
> > >
> > > config KW88F6192
> > > bool
> > > + select ARCH_VERY_EARLY_INIT
> > >
> > > config KW88F6281
> > > bool
> > > + select ARCH_VERY_EARLY_INIT
> > >
> > > config SHEEVA_88SV131
> > > bool
> > > diff --git a/arch/arm/mach-kirkwood/Makefile
Re: [PATCH v2 1/5] binman: add documentation for binman sign option
Add the documentation about binman sign option and providing an example. Signed-off-by: Ivan Mikhaylov --- tools/binman/binman.rst | 18 ++ 1 file changed, 18 insertions(+) Applied to u-boot-dm/next, thanks! Applied to u-boot-dm/next, thanks!
Re: [PATCH v2 2/5] binman: add sign option for binman
Hi Ivan, On Tue, 7 Mar 2023 at 14:13, Ivan Mikhaylov wrote: > > Introduce proof of concept for binman's new option which provides sign > and replace FIT containers in binary images. > > Usage as example: > > from: > mkimage -G privateky -r -o sha256,rsa4096 -F fit > binman replace -i flash.bin -f fit.fit fit > > to: > binman sign -i flash.bin -k privatekey -a sha256,rsa4096 -f fit.fit fit > > and to this one if it's need to be extracted, signed with key and put it > back in image: > binman sign -i flash.bin -k privatekey -a sha256,rsa4096 fit > > Signed-off-by: Ivan Mikhaylov > --- > tools/binman/cmdline.py | 13 + > tools/binman/control.py | 29 - > tools/binman/etype/fit.py | 18 ++ > tools/binman/etype/section.py | 3 +++ > 4 files changed, 62 insertions(+), 1 deletion(-) This needs a few tweaks to get the test coverage up to 100% and use the mark_build_done() feature added a few days ago. I have taken the liberty of updating it and will apply it soon, since this has been outstanding for a while. Regards, Simon Applied to u-boot-dm/next, thanks! Applied to u-boot-dm/next, thanks!
Re: [PATCH v2 3/5] binman: add tests for sign option
Hi Ivan, On Fri, 10 Mar 2023 at 17:47, Simon Glass wrote: > > Add the test which provides sequence of actions: > 1. create the image from binman dts > 2. create public and private keys > 3. add public key into dtb with fdt_add_pubkey > 4. 1. sign FIT container with new sign option with extracting from > image > 2. sign exact FIT container with replacing of it in image > 5. check with fit_check_sign > > Signed-off-by: Ivan Mikhaylov > --- > tools/binman/ftest.py | 61 + > tools/binman/test/277_fit_sign.dts | 63 ++ > 2 files changed, 124 insertions(+) > create mode 100644 tools/binman/test/277_fit_sign.dts > > Applied to u-boot-dm/next, thanks! As mentioned on the other email I had a bit of trouble getting this over the line Here is what I did: Renumber test file from 277 to 280 Move UpdateSignatures() to Entry base class Don't allow missing mkimage as it doesn't make sense Propagate --toolpath for CI Call mark_build_done() to avoid regenerating FIT Regards, Simon Applied to u-boot-dm/next, thanks!
Re: [PATCH v7 11/23] core: remap: fix regmap_init_mem_plat() reg size handeling
On 3/11/23 02:37, Simon Glass wrote:
> Hi Johan,
>
> On Fri, 10 Mar 2023 at 08:42, Johan Jonker wrote:
>>
>> The fdt_addr_t and phys_addr_t size have been decoupled.
>> A 32bit CPU can expect 64-bit data from the device tree parser,
>
> Sorry if you already responded and I missed it.
>
> I don't understand this line. It looks like sizeof(fdt_addr_t) is
> still 4 on 32-bit machines. So what does this actually mean?
The original response on WHY we need it for partitions:
https://lore.kernel.org/u-boot/7256f237-4b7b-f7d7-834f-f7c3fb898...@gmail.com/T/#m81afcb203e2309c05ca97d36c63ef758cf3cef89
Below an explanation of the consequences.
Does this text below help?
Johan
===
Current (coupled):
phys_addr_t fdt_addr_t
1: 32bit 32bit (problem: not enough bits to describe NAND
partitions)
2: 64bit 64bit
New (decoupled)
phys_addr_t fdt_addr_t
1: 32bit 32bit (problem: not enough bits to describe NAND
partitions)
2: 64bit 64bit
3: 32bit 64bit (Current U-boot DT with rk3288 32bit reg size DT)
4: 32bit 64bit (Synced rk3288 Linux 64bit reg size DT)
===
For situation 3 and 4:
In sandbox a 64bit addr is cast back to phys_addr_t and then to pointer of a
memory area.
On real hardware a 64bit addr is cast to uintptr_t and then to a pointer.
In this serie we fix the functions that have a wrong cast on the same line and
are easy to find:
- data->base = (void *)dev_read_addr(dev);
+ data->base = dev_read_addr_ptr(dev);
This makes it pass the test.
Not fixed are drivers that cast later on:
addr_base = dev_read_addr(dev);
if (addr_base == FDT_ADDR_T_NONE)
return -EINVAL;
priv->regs = (void __iomem *)addr_base;
These drivers must be fixed by there MAINTAINERS if they like to enable
decoupling.
This passes the test as long as they don't use it.
===
>From io.h:
/* For sandbox, we want addresses to point into our RAM buffer */
static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
{
return map_physmem(paddr, len, MAP_WRBACK);
}
===
>From compiler.h:
/* Type for `void *' pointers. */
typedef unsigned long int uintptr_t;
>From mapmem.h
/* Define a null map_sysmem() if the architecture doesn't use it */
# ifdef CONFIG_ARCH_MAP_SYSMEM
#include
# else
static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
{
return (void *)(uintptr_t)paddr;
}
===
U-boot 32bit size:
noc: syscon@ffac {
compatible = "rockchip,rk3288-noc", "syscon";
reg = <0xffac 0x2000>;
u-boot,dm-pre-reloc;
};
struct dtd_rockchip_rk3288_noc {
fdt32_t reg[2];
};
static struct dtd_rockchip_rk3288_noc dtv_syscon_at_ffac = {
.reg= {0xffac, 0x2000},
};
===
Linux 64bit reg size:
noc: syscon@ffac {
compatible = "rockchip,rk3288-noc", "syscon";
reg = <0x0 0xffac 0x0 0x2000>;
u-boot,dm-pre-reloc;
};
struct dtd_rockchip_rk3288_noc {
fdt64_t reg[2];
};
static struct dtd_rockchip_rk3288_noc dtv_syscon_at_ffac = {
.reg= {0xffac, 0x2000},
};
===
Program output on why we must specify the pointer reg size or else things mess
up.
/*
gcc c_size_test.c -o c_size_test
./c_size_test
sizeof char 1 8
sizeof short 2 16
sizeof int 4 32
sizeof long 8 64
016llx
x bbaa9988
llx ffeeddccbbaa9988
x ffeeddcc
x bbaa9988
x 77665544
x 33221100
x2 bbaa9988
x2 ffeeddcc
x2 33221100
x2 77665544
llx ffeeddccbbaa9988
llx 7766554433221100
llx2 bbaa9988ffeeddcc
llx2 3322110077665544
*/
#include
int main(void) {
printf("sizeof char %d %d\n", sizeof(char), sizeof(char)*8);
printf("sizeof short %d %d\n", sizeof(short), sizeof(short)*8);
printf("sizeof int %d %d\n", sizeof(int), sizeof(int)*8);
printf("sizeof long %d %d\n", sizeof(long), sizeof(long)*8);
unsigned long long val = -1;
printf("016llx %016llx\n", (unsigned long long)val);
unsigned long long val2[] = {0xffeeddccbbaa9988, 0x7766554433221100};
unsigned int val3[] = {0xffeeddcc, 0xbbaa9988, 0x77665544, 0x33221100};
printf("x %x\n", (unsigned int)val2[0]);
printf("llx %llx\n", (unsigned long long)val2[0]);
unsigned int *ptr = (unsigned int *)val3;
int count;
for (count = 2; count > 0;
ptr += 2, count--) {
printf("x %x\n", *ptr);
printf("x %x\n", ptr[1]);
}
ptr = (unsigned int *)val2;
for (count = 2; count > 0;
ptr += 2, count--) {
printf("x2 %x\n", *ptr);
printf("x2 %x\n", ptr[1]);
}
unsigned long long *ptr2 = (unsigned long long *)val2;
for (count = 1; count > 0;
ptr += 2, count--) {
Re: [RESEND PATCH] kconfig: Proposed language extension for multiple builds
On Sun, Mar 12, 2023 at 1:55 AM Tom Rini wrote: > > On Fri, Mar 10, 2023 at 09:39:15PM -0800, Randy Dunlap wrote: > > Hi-- > > > > On 3/10/23 18:37, Simon Glass wrote: > > > (I am sending this again to get more feedback) > > > > > > In the case of Linux, only one build is produced so there is only a > > > single configuration. For other projects, such as U-Boot and Zephyr, the > > > same code is used to produce multiple builds, each with related (but > > > different) options enabled. > > > > > > This can be handled with the existing kconfig language, but it is quite > > > verbose, somewhat tedious and very error-prone, since there is a lot of > > > duplication. The result is hard to maintain. > > > > > > Describe an extension to the Kconfig language to support easier handling > > > of this use case. > > > > > > Signed-off-by: Simon Glass > > > > IMO Masahiro has already answered this multiple times and I agree with his > > answers. > > > > For others, the full previous thread is at > > > > https://lore.kernel.org/all/20230219145453.1.Idaaf79c3e768b85750d5a7eb732052576c5e07e5@changeid/ > > Well, I think what was unclear, or maybe we just wanted to confirm the > answer was "none at all", was this. As good community neighbors, we see > a generic issue in the Kconfig language, a tool used frequently outside > of just the Linux kernel, and would like to contribute back. Ideally > without having first gone off, designed and implemented something, and > then been told it's all wrong and to rewrite it first. So what level of > interest is there in this? Sorry, no interest. If you want to get a clear answer, NACK. > > As I pointed out in that thread, I believe barebox has examples where > some keyword like we're proposing here would help them (and yes, there's > only a dozen or so symbols so it's also manageable without anything > special), Barebox keeps PBL in very limited, ad-hoc implementation. PBL has no more than 10 user-configurable options. Sascha Hauer designed it this way. Linux kernel also has a small loader (a.k.a decompressor) in arch/*/boot/decompress/. For example, CONFIG_KERNEL_GZIP is a CONFIG option for the decompressor instead of the main kernel. In this sense, you could apply your theory, "Linux kernel is also multi build-phases, so Kconfig should have this extension to move CONFIG_KERNEL_GZIP to another build phase". No, no. The main kernel and the decompressor are well separated and the latter is small and simple. Barebox is the same - the main Barebox and PBL are well separated and PBL is really small and simple. The problems you are suffering from do not exist in Barebox. > and Simon believes Zephyr will be in a similar situation soon > enough (which doesn't use the kernel's implementation of the language). Zephyr does not share any Kconfig code with Linux. They use Python implementation, a.k.a. Kconfiglib. It is up to the Zephyr community, but this requires extra effort. > Frankly, I keep going back to "tristate" is just the original example of > what we're talking about here (CONFIG_FOO=n, CONFIG_FOO_MODULE=y), not > that I'm suggesting we would remove the tristate word. > So we would really like to make sure as many people and projects are > aware, as possible. This is on the boundary. We can make the tristate optional if it does not make the code too ugly. But, if you do not add CONFIG_MODULES in your Kconfig file, users will not see 'm' in the first place. I know some help messages still mention 'm', but is this the problem you want to solve? > And as Simon asked in the thread, what about code refactoring that makes > further maintenance easier? Clearly, such patches would need to be > against the current appropriate tree. If such patches clean up the code, they will be appreciated. -- Best Regards Masahiro Yamada
Re: [RFC/PATCH] lib/Kconfig: Enable OF_LIBFDT_OVERLAY by default when FIT is enabled
Hi Tom, On Fri, Mar 10, 2023 at 01:12:24PM -0500, Tom Rini wrote: > On Sun, Jan 29, 2023 at 06:30:22PM +0200, Laurent Pinchart wrote: > > > FIT image support is commonly used to bundle a kernel image, a device > > tree, and device tree overlays. Applying overlays requires the > > OF_LIBFDT_OVERLAY config option to be set, which lots of boards fail to > > select, most likely because developers never noticed. This leads to an > > error when trying to apply overlays: > > > > "config with overlays but CONFIG_OF_LIBFDT_OVERLAY not set" > > > > TI ARM boards select the option by default. Extend this to all systems > > that select the FIT option. This only affects the default, overlay > > support can still be disabled manually in the configuration. > > > > Signed-off-by: Laurent Pinchart > > Reviewed-by: Marek Vasut > > Reviewed-by: Simon Glass > > --- > > I'm posting this as an RFC to get feedback. If the idea is generally > > appreciated, I'll update the defconfig files accordingly. > > Alright, so, I put this through a world build, and most platforms grow > by 4-5kB. Thank you for testing this, despite the patch falling off my radar. > I think that means what I'd really like to see as a starting > point is more SoCs doing an "imply OF_LIBFDT_OVERLAY if OF_LIBFDT && FIT" > or adding to the default y list below, or similar. If that brings us to > the point where a good number of ARM boards with FIT are enabling it, we > can default y if ARM, for example. But right now it's more like several > hundred boards growing in size, which is uncomfortable, given the size > it's growing by. I'm fine with that. I've submitted the original patch because I had to update a vendor-supplied U-Boot binary to get overlay support, which ended up being a bit rabbit hole for various reasons. I thought it would be nice to save users from this kind of trouble. I can send patches to enable the option for SoC I care about, but generally speaking, who should decide which SoC(s) should imply OF_LIBFDT_OVERLAY ? -- Regards, Laurent Pinchart
